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Sample records for high-k gate dielectrics

  1. Study of high-k gate dielectrics by means of positron annihilation

    International Nuclear Information System (INIS)

    Uedono, A.; Naito, T.; Otsuka, T.; Ito, K.; Shiraishi, K.; Yamabe, K.; Miyazaki, S.; Watanabe, H.; Umezawa, N.; Hamid, A.; Chikyow, T.; Ohdaira, T.; Suzuki, R.; Ishibashi, S.; Inumiya, S.; Kamiyama, S.; Akasaka, Y.; Nara, Y.; Yamada, K.

    2007-01-01

    High-dielectric constant (high-k) gate materials, such as HfSiO x and HfAlO x , fabricated by atomic-layer-deposition techniques were characterized using monoenergetic positron beams. Measurements of the Doppler broadening spectra of annihilation radiation and the lifetime spectra of positrons indicated that positrons annihilated from the trapped state by open volumes that exist intrinsically in amorphous structures of the films. The size distributions of the open volumes and the local atomic configurations around such volumes can be discussed using positron annihilation parameters, and they were found to correlate with the electrical properties of the films. We confirmed that the positron annihilation is useful technique to characterize the matrix structure of amorphous high-k materials, and can be used to determine process parameters for the fabrication of high-k gate dielectrics. (copyright 2007 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  2. Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

    Science.gov (United States)

    Jayanti, Srikant

    Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG

  3. Investigation of high- k yttrium copper titanate thin films as alternative gate dielectrics

    International Nuclear Information System (INIS)

    Monteduro, Anna Grazia; Ameer, Zoobia; Rizzato, Silvia; Martino, Maurizio; Caricato, Anna Paola; Maruccio, Giuseppe; Tasco, Vittorianna; Lekshmi, Indira Chaitanya; Hazarika, Abhijit; Choudhury, Debraj; Sarma, D D

    2016-01-01

    Nearly amorphous high- k yttrium copper titanate thin films deposited by laser ablation were investigated in both metal–oxide–semiconductor (MOS) and metal–insulator–metal (MIM) junctions in order to assess the potentialities of this material as a gate oxide. The trend of dielectric parameters with film deposition shows a wide tunability for the dielectric constant and AC conductivity, with a remarkably high dielectric constant value of up to 95 for the thick films and conductivity as low as 6  ×  10 −10 S cm −1 for the thin films deposited at high oxygen pressure. The AC conductivity analysis points out a decrease in the conductivity, indicating the formation of a blocking interface layer, probably due to partial oxidation of the thin films during cool-down in an oxygen atmosphere. Topography and surface potential characterizations highlight differences in the thin film microstructure as a function of the deposition conditions; these differences seem to affect their electrical properties. (paper)

  4. Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High-k Gate Dielectric Materials

    Directory of Open Access Journals (Sweden)

    Yu-Hsien Lin

    2015-01-01

    Full Text Available We investigated amorphous indium gallium zinc oxide (a-IGZO thin film transistors (TFTs using different high-k gate dielectric materials such as silicon nitride (Si3N4 and aluminum oxide (Al2O3 at low temperature process (<300°C and compared them with low temperature silicon dioxide (SiO2. The IGZO device with high-k gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, postannealing treatment is an essential process for completing the process. The chemical reaction of the high-k/IGZO interface due to heat formation in high-k/IGZO materials results in reliability issue. We also used the voltage stress for testing the reliability for the device with different high-k gate dielectric materials and explained the interface effect by charge band diagram.

  5. Pentacene based thin film transistors with high-k dielectric Nd2O3 as a gate insulator

    International Nuclear Information System (INIS)

    Sarma, R.; Saikia, D.

    2010-01-01

    We have investigated the pentacene based Organic Thin Film Transistors (OTFTs) with high-k dielectric Nd 2 O 3 . Use of high dielectric constant (high-k) gate insulator Nd 2 O 3 reduces the threshold voltage and sub threshold swing of the OTFTs. The calculated threshold voltage -2.2V and sub-threshold swing 1V/decade, current ON-OFF ratio is 1.7 X 10 4 and mobility is 0.13cm 2 /V.s. Pentacene film is deposited on Nd 2 O 3 surface using two step deposition method. Deposited pentacene film is found poly crystalline in nature. (author)

  6. Al2O3 nanocrystals embedded in amorphous Lu2O3 high-k gate dielectric for floating gate memory application

    International Nuclear Information System (INIS)

    Yuan, C L; Chan, M Y; Lee, P S; Darmawan, P; Setiawan, Y

    2007-01-01

    The integration of nanoparticles has high potential in technological applications and opens up possibilities of the development of new devices. Compared to the conventional floating gate memory, a structure containing nanocrystals embedded in dielectrics shows high potential to produce a memory with high endurance, low operating voltage, fast write-erase speeds and better immunity to soft errors [S. Tiwari, F. Rana, H. Hanafi et al. 1996 Appl.Phys. Lett. 68, 1377]. A significant improvement on data retention [J. J. Lee, X. Wang et al. 2003 Proceedings of the VLSI Technol. Symposium, p33] can be observed when discrete nanodots are used instead of continuous floating gate as charge storage nodes because local defect related leakage can be reduced efficiently. Furthermore, using a high-k dielectric in place of the conventional SiO2 based dielectric, nanodots flash memory is able to achieve significantly improved programming efficiency and data retention [A. Thean and J. -P. Leburton, 2002 IEEE Potentials 21, 35; D. W. Kim, T. Kim and S. K. Banerjee, 2003 IEEE Trans. Electron Devices 50, 1823]. We have recently successfully developed a method to produce nanodots embedded in high-k gate dielectrics [C. L. Yuan, P. Darmawan, Y. Setiawan and P. S. Lee, 2006 Electrochemical and Solid-State Letters 9, F53; C. L. Yuan, P. Darmawan, Y. Setiawan and P. S. Lee, 2006 Europhys. Lett. 74, 177]. In this paper, we fabricated the memory structure of Al 2 O 3 nanocrystals embedded in amorphous Lu 2 O 3 high k dielectric using pulsed laser ablation. The mean size and density of the Al 2 O 3 nanocrystals are estimated to be about 5 nm and 7x1011 cm -2 , respectively. Good electrical performances in terms of large memory window and good data retention were observed. Our preparation method is simple, fast and economical

  7. A threshold-voltage model for small-scaled GaAs nMOSFET with stacked high-k gate dielectric

    Science.gov (United States)

    Chaowen, Liu; Jingping, Xu; Lu, Liu; Hanhan, Lu; Yuan, Huang

    2016-02-01

    A threshold-voltage model for a stacked high-k gate dielectric GaAs MOSFET is established by solving a two-dimensional Poisson's equation in channel and considering the short-channel, DIBL and quantum effects. The simulated results are in good agreement with the Silvaco TCAD data, confirming the correctness and validity of the model. Using the model, impacts of structural and physical parameters of the stack high-k gate dielectric on the threshold-voltage shift and the temperature characteristics of the threshold voltage are investigated. The results show that the stacked gate dielectric structure can effectively suppress the fringing-field and DIBL effects and improve the threshold and temperature characteristics, and on the other hand, the influence of temperature on the threshold voltage is overestimated if the quantum effect is ignored. Project supported by the National Natural Science Foundation of China (No. 61176100).

  8. A threshold-voltage model for small-scaled GaAs nMOSFET with stacked high-k gate dielectric

    International Nuclear Information System (INIS)

    Liu Chaowen; Xu Jingping; Liu Lu; Lu Hanhan; Huang Yuan

    2016-01-01

    A threshold-voltage model for a stacked high-k gate dielectric GaAs MOSFET is established by solving a two-dimensional Poisson's equation in channel and considering the short-channel, DIBL and quantum effects. The simulated results are in good agreement with the Silvaco TCAD data, confirming the correctness and validity of the model. Using the model, impacts of structural and physical parameters of the stack high-k gate dielectric on the threshold-voltage shift and the temperature characteristics of the threshold voltage are investigated. The results show that the stacked gate dielectric structure can effectively suppress the fringing-field and DIBL effects and improve the threshold and temperature characteristics, and on the other hand, the influence of temperature on the threshold voltage is overestimated if the quantum effect is ignored. (paper)

  9. Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High-k Gate Dielectric Materials

    International Nuclear Information System (INIS)

    Lin, Y. H.; Chou, J. C.

    2015-01-01

    We investigated amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFT_s) using different high-Κ gate dielectric materials such as silicon nitride (Si_3N_4) and aluminum oxide (Al_2O_3) at low temperature process (<300 degree) and compared them with low temperature silicon dioxide (SiO_2). The IGZO device with high-Κ gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, post annealing treatment is an essential process for completing the process. The chemical reaction of the high-κ/IGZO interface due to heat formation in high-Κ/IGZO materials results in reliability issue. We also used the voltage stress for testing the reliability for the device with different high-Κ gate dielectric materials and explained the interface effect by charge band diagram.

  10. First-principles simulations of the leakage current in metal-oxide-semiconductor structures caused by oxygen vacancies in HfO2 high-K gate dielectric

    International Nuclear Information System (INIS)

    Mao, L.F.; Wang, Z.O.

    2008-01-01

    HfO 2 high-K gate dielectric has been used as a new gate dielectric in metal-oxide-semiconductor structures. First-principles simulations are used to study the effects of oxygen vacancies on the tunneling current through the oxide. A level which is nearly 1.25 eV from the bottom of the conduction band is introduced into the bandgap due to the oxygen vacancies. The tunneling current calculations show that the tunneling currents through the gate oxide with different defect density possess the typical characteristic of stress-induced leakage current. Further analysis shows that the location of oxygen vacancies will have a marked effect on the tunneling current. The largest increase in the tunneling current caused by oxygen vacancies comes about at the middle oxide field when defects are located at the middle of the oxide. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  11. Growth Related Carrier Mobility Enhancement of Pentacene Thin-Film Transistors with High-k Oxide Gate Dielectric

    International Nuclear Information System (INIS)

    Ai-Fang, Yu; Qiong, Qi; Peng, Jiang; Chao, Jiang

    2009-01-01

    Carrier mobility enhancement from 0.09 to 0.59 cm 2 /Vs is achieved for pentacene-based thin-film transistors (TFTs) by modifying the HfO 2 gate dielectric with a polystyrene (PS) thin film. The improvement of the transistor's performance is found to be strongly related to the initial film morphologies of pentacene on the dielectrics. In contrast to the three-dimensional island-like growth mode on the HfO 2 surface, the Stranski-Krastanov growth mode on the smooth and nonpolar PS/HfO 2 surface is believed to be the origin of the excellent carrier mobility of the TFTs. A large well-connected first monolayer with fewer boundaries is formed via the Stranski–Krastanov growth mode, which facilitates a charge transport parallel to the substrate and promotes higher carrier mobility. (cross-disciplinary physics and related areas of science and technology)

  12. Vacancy-fluorine complexes and their impact on the properties of metal-oxide transistors with high-k gate dielectrics studied using monoenergetic positron beams

    Science.gov (United States)

    Uedono, A.; Inumiya, S.; Matsuki, T.; Aoyama, T.; Nara, Y.; Ishibashi, S.; Ohdaira, T.; Suzuki, R.; Miyazaki, S.; Yamada, K.

    2007-09-01

    Vacancy-fluorine complexes in metal-oxide semiconductors (MOS) with high-k gate dielectrics were studied using a positron annihilation technique. F+ ions were implanted into Si substrates before the deposition of gate dielectrics (HfSiON). The shift of threshold voltage (Vth) in MOS capacitors and an increase in Fermi level position below the HfSiON/Si interface were observed after F+ implantation. Doppler broadening spectra of the annihilation radiation and positron lifetimes were measured before and after HfSiON fabrication processes. From a comparison between Doppler broadening spectra and those obtained by first-principles calculation, the major defect species in Si substrates after annealing treatment (1050 °C, 5 s) was identified as vacancy-fluorine complexes (V3F2). The origin of the Vth shift in the MOS capacitors was attributed to V3F2 located in channel regions.

  13. Low-temperature fabrication of sputtered high-k HfO2 gate dielectric for flexible a-IGZO thin film transistors

    Science.gov (United States)

    Yao, Rihui; Zheng, Zeke; Xiong, Mei; Zhang, Xiaochen; Li, Xiaoqing; Ning, Honglong; Fang, Zhiqiang; Xie, Weiguang; Lu, Xubing; Peng, Junbiao

    2018-03-01

    In this work, low temperature fabrication of a sputtered high-k HfO2 gate dielectric for flexible a-IGZO thin film transistors (TFTs) on polyimide substrates was investigated. The effects of Ar-pressure during the sputtering process and then especially the post-annealing treatments at low temperature (≤200 °C) for HfO2 on reducing the density of defects in the bulk and on the surface were systematically studied. X-ray reflectivity, UV-vis and X-ray photoelectron spectroscopy, and micro-wave photoconductivity decay measurements were carried out and indicated that the high quality of optimized HfO2 film and its high dielectric properties contributed to the low concentration of structural defects and shallow localized defects such as oxygen vacancies. As a result, the well-structured HfO2 gate dielectric exhibited a high density of 9.7 g/cm3, a high dielectric constant of 28.5, a wide optical bandgap of 4.75 eV, and relatively low leakage current. The corresponding flexible a-IGZO TFT on polyimide exhibited an optimal device performance with a saturation mobility of 10.3 cm2 V-1 s-1, an Ion/Ioff ratio of 4.3 × 107, a SS value of 0.28 V dec-1, and a threshold voltage (Vth) of 1.1 V, as well as favorable stability under NBS/PBS gate bias and bending stress.

  14. Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process

    International Nuclear Information System (INIS)

    Wang Yan-Rong; Yang Hong; Xu Hao; Wang Xiao-Lei; Luo Wei-Chun; Qi Lu-Wei; Zhang Shu-Xiang; Wang Wen-Wu; Yan Jiang; Zhu Hui-Long; Zhao Chao; Chen Da-Peng; Ye Tian-Chun

    2015-01-01

    A multi-deposition multi-annealing technique (MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device’s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown (TDDB) characteristics of positive channel metal oxide semiconductor (PMOS) under different MDMA process conditions, including the deposition/annealing (D and A) cycles, the D and A time, and the total annealing time. The results show that the increases of the number of D and A cycles (from 1 to 2) and D and A time (from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail (TTF) at 63.2% increases by about several times. However, too many D and A cycles (such as 4 cycles) make the equivalent oxide thickness (EOT) increase by about 1 Å and the TTF of PMOS worsen. Moreover, different D and A times and numbers of D and A cycles induce different breakdown mechanisms. (paper)

  15. High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure.

    Science.gov (United States)

    Chen, Szu-Hung; Liao, Wen-Shiang; Yang, Hsin-Chia; Wang, Shea-Jue; Liaw, Yue-Gie; Wang, Hao; Gu, Haoshuang; Wang, Mu-Chun

    2012-08-01

    A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal-semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

  16. The influence of carbon doping on the performance of Gd2O3 as high-k gate dielectric

    International Nuclear Information System (INIS)

    Shekhter, P.; Yehezkel, S.; Shriki, A.; Eizenberg, M.; Chaudhuri, A. R.; Osten, H. J.; Laha, A.

    2014-01-01

    One of the approaches for overcoming the issue of leakage current in modern metal-oxide-semiconductor devices is utilizing the high dielectric constants of lanthanide based oxides. We investigated the effect of carbon doping directly into Gd 2 O 3 layers on the performance of such devices. It was found that the amount of carbon introduced into the dielectric is above the solubility limit; carbon atoms enrich the oxide-semiconductor interface and cause a significant shift in the flat band voltage of the stack. Although the carbon atoms slightly degrade this interface, this method has a potential for tuning the flat band voltage of such structures

  17. In situ atomic layer nitridation on the top and down regions of the amorphous and crystalline high-K gate dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Tsai, Meng-Chen [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China); Lee, Min-Hung [Institute of Electro-Optical Science and Technology, National Taiwan Normal University, Taipei 11677, Taiwan (China); Kuo, Chin-Lung; Lin, Hsin-Chih [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China); Chen, Miin-Jang, E-mail: mjchen@ntu.edu.tw [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China)

    2016-11-30

    Highlights: • The structural and electrical characteristics of the ZrO{sub 2} high-K dielectrics, treated with the in situ atomic layer doping of nitrogen into the top and down regions (top and down nitridation, TN and DN, respectively), were investigated. • The amorphous DN sample has a lower leakage current density (J{sub g}) than the amorphous TN sample, attributed to the formation of SiO{sub x}N{sub y} in the interfacial layer (IL). • The crystalline TN sample exhibited a lower CET and a similar J{sub g} as compared with the crystalline DN sample, which can be ascribed to the suppression of IL regrowth. • The crystalline ZrO{sub 2} with in situ atomic layer doping of nitrogen into the top region exhibited superior scaling limit, electrical characteristics, and reliability. - Abstract: Amorphous and crystalline ZrO{sub 2} gate dielectrics treated with in situ atomic layer nitridation on the top and down regions (top and down nitridation, abbreviated as TN and DN) were investigated. In a comparison between the as-deposited amorphous DN and TN samples, the DN sample has a lower leakage current density (J{sub g}) of ∼7 × 10{sup −4} A/cm{sup 2} with a similar capacitance equivalent thickness (CET) of ∼1.53 nm, attributed to the formation of SiO{sub x}N{sub y} in the interfacial layer (IL). The post-metallization annealing (PMA) leads to the transformation of ZrO{sub 2} from the amorphous to the crystalline tetragonal/cubic phase, resulting in an increment of the dielectric constant. The PMA-treated TN sample exhibits a lower CET of 1.22 nm along with a similar J{sub g} of ∼1.4 × 10{sup −5} A/cm{sup 2} as compared with the PMA-treated DN sample, which can be ascribed to the suppression of IL regrowth. The result reveals that the nitrogen engineering in the top and down regions has a significant impact on the electrical characteristics of amorphous and crystalline ZrO{sub 2} gate dielectrics, and the nitrogen incorporation at the top of crystalline

  18. High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

    Science.gov (United States)

    Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

    2018-04-18

    A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

  19. The electrical performance and gate bias stability of an amorphous InGaZnO thin-film transistor with HfO2 high-k dielectrics

    Science.gov (United States)

    Wang, Ruo Zheng; Wu, Sheng Li; Li, Xin Yu; Zhang, Jin Tao

    2017-07-01

    In this study, we set out to fabricate an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with SiNx/HfO2/SiNx (SHS) sandwiched dielectrics. The J-V and C-V of this SHS film were extracted by the Au/p-Si/SHS/Ti structure. At room temperature the a-IGZO with SHS dielectrics showed the following electrical properties: a threshold voltage of 2.9 V, a subthreshold slope of 0.35 V/decade, an on/off current ratio of 3.5 × 107, and a mobility of 12.8 cm2 V-1 s-1. Finally, we tested the influence of gate bias stress on the TFT, and the result showed that the threshold voltage shifted to a positive voltage when applying a positive gate voltage to the TFT.

  20. Optimum source/drain overlap design for 16 nm high-k/metal gate MOSFETs

    International Nuclear Information System (INIS)

    Jang, Junyong; Lim, Towoo; Kim, Youngmin

    2009-01-01

    We explore a source/drain (S/D) design for a 16 nm MOSFET utilizing a replacement process for a high-k gate dielectric and metal gate electrode integration. Using TCAD simulation, a trade-off study between series resistance and overlap capacitance is carried out for a high-k dielectric surrounding gate structure, which results from the replacement process. An optimum S/D overlap to gate for the high-k surrounding gate structure is found to be different from the conventional gate structure, i.e. 0∼1 nm underlap is preferred for the surround high-k gate structure while 1∼2 nm overlap for the conventional gate one

  1. Thermal response of Ru electrodes in contact with SiO2 and Hf-based high-k gate dielectrics

    International Nuclear Information System (INIS)

    Wen, H.-C.; Lysaght, P.; Alshareef, H.N.; Huffman, C.; Harris, H.R.; Choi, K.; Senzaki, Y.; Luan, H.; Majhi, P.; Lee, B.H.; Campin, M. J.; Foran, B.; Lian, G.D.; Kwong, D.-L.

    2005-01-01

    A systematic experimental evaluation of the thermal stability of Ru metal gate electrodes in direct contact with SiO 2 and Hf-based dielectric layers was performed and correlated with electrical device measurements. The distinctly different interfacial reactions in the Ru/SiO 2 , Ru/HfO 2 , and Ru/HfSiO x film systems were observed through cross-sectional high-resolution transmission electron microscopy, high angle annular dark field scanning transmission electron microscopy with electron-energy-loss spectra, and energy dispersive x-ray spectra analysis. Ru interacted with SiO 2 , but remained stable on HfO 2 at 1000 deg. C. The onset of Ru/SiO 2 interfacial interactions is identified via silicon substrate pitting possibly from Ru diffusion into the dielectric in samples exposed to a 900 deg. C/10-s anneal. The dependence of capacitor device degradation with decreasing SiO 2 thickness suggests Ru diffuses through SiO 2 , followed by an abrupt, rapid, nonuniform interaction of ruthenium silicide as Ru contacts the Si substrate. Local interdiffusion detected on Ru/HfSiO x samples may be due to phase separation of HfSiO x into HfO 2 grains within a SiO 2 matrix, suggesting that SiO 2 provides a diffusion pathway for Ru. Detailed evidence consistent with a dual reaction mechanism for the Ru/SiO 2 system at 1000 deg. C is presented

  2. Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

    Directory of Open Access Journals (Sweden)

    H. Hussin

    2014-01-01

    Full Text Available We present a simulation study on negative bias temperature instability (NBTI induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2 and hafnium oxide (HfO2 layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2 are increased but is reduced by 11% when the SiO2 interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2 interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated.

  3. Materials Fundamentals of Gate Dielectrics

    CERN Document Server

    Demkov, Alexander A

    2006-01-01

    This book presents materials fundamentals of novel gate dielectrics that are being introduced into semiconductor manufacturing to ensure the continuous scalling of the CMOS devices. This is a very fast evolving field of research so we choose to focus on the basic understanding of the structure, thermodunamics, and electronic properties of these materials that determine their performance in device applications. Most of these materials are transition metal oxides. Ironically, the d-orbitals responsible for the high dielectric constant cause sever integration difficulties thus intrinsically limiting high-k dielectrics. Though new in the electronics industry many of these materials are wel known in the field of ceramics, and we describe this unique connection. The complexity of the structure-property relations in TM oxides makes the use of the state of the art first-principles calculations necessary. Several chapters give a detailed description of the modern theory of polarization, and heterojunction band discont...

  4. Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high- k metal gate NMOSFET with kMC TDDB simulations

    International Nuclear Information System (INIS)

    Xu Hao; Yang Hong; Luo Wei-Chun; Xu Ye-Feng; Wang Yan-Rong; Tang Bo; Wang Wen-Wu; Qi Lu-Wei; Li Jun-Feng; Yan Jiang; Zhu Hui-Long; Zhao Chao; Chen Da-Peng; Ye Tian-Chun

    2016-01-01

    The thickness effect of the TiN capping layer on the time dependent dielectric breakdown (TDDB) characteristic of ultra-thin EOT high- k metal gate NMOSFET is investigated in this paper. Based on experimental results, it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer. From the charge pumping measurement and secondary ion mass spectroscopy (SIMS) analysis, it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density. In addition, the influences of interface and bulk trap density ratio N it / N ot are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo (kMC) method. The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses. (paper)

  5. Channel mobility degradation and charge trapping in high-k/metal gate NMOSFETs

    International Nuclear Information System (INIS)

    Mathew, Shajan; Bera, L.K.; Balasubramanian, N.; Joo, M.S.; Cho, B.J.

    2004-01-01

    NMOSFETs with Metalo-Organic Chemical Vapor Deposited (MOCVD) HfAlO gate dielectric and TiN metal gate have been fabricated. Channel electron mobility was measured using the split-CV method and compared with SiO 2 devices. All high-k devices showed lower mobility compared with SiO 2 reference devices. High-k MOSFETs exhibited significant charge trapping and threshold instability. Threshold voltage recovery with time was studied on devices with oxide/nitride interfacial layer between high-k film and silicon substrate

  6. Fabrication of Nonvolatile Memory Effects in High-k Dielectric Thin Films Using Electron Irradiation

    International Nuclear Information System (INIS)

    Park, Chanrock; Cho, Daehee; Kim, Jeongeun; Hwang, Jinha

    2010-01-01

    Electron Irradiation can be applied towards nano-floating gate memories which are recognized as one of the next-generation nonvolatile memory semiconductors. NFGMs can overcome the preexisting limitations encountered in Dynamic Random Access Memories and Flash memories with the excellent advantages, i. e. high-density information storage, high response speed, high compactness, etc. The traditional nano-floating gate memories are fabricated through multi-layered nano structures of the dissimilar materials where the charge-trapping portions are sandwiched into the high-k dielectrics. However, this work reports the unique nonvolatile responses in single-layered high-k dielectric thin films if irradiated with highly accelerated electron beams. The implications of the electron irradiation will be discussed towards high-performance nano-floating gate memories

  7. On the Evaluation of Gate Dielectrics for 4H-SiC Based Power MOSFETs

    Directory of Open Access Journals (Sweden)

    Muhammad Nawaz

    2015-01-01

    Full Text Available This work deals with the assessment of gate dielectric for 4H-SiC MOSFETs using technology based two-dimensional numerical computer simulations. Results are studied for variety of gate dielectric candidates with varying thicknesses using well-known Fowler-Nordheim tunneling model. Compared to conventional SiO2 as a gate dielectric for 4H-SiC MOSFETs, high-k gate dielectric such as HfO2 reduces significantly the amount of electric field in the gate dielectric with equal gate dielectric thickness and hence the overall gate current density. High-k gate dielectric further reduces the shift in the threshold voltage with varying dielectric thicknesses, thus leading to better process margin and stable device operating behavior. For fixed dielectric thickness, a total shift in the threshold voltage of about 2.5 V has been observed with increasing dielectric constant from SiO2 (k=3.9 to HfO2 (k=25. This further results in higher transconductance of the device with the increase of the dielectric constant from SiO2 to HfO2. Furthermore, 4H-SiC MOSFETs are found to be more sensitive to the shift in the threshold voltage with conventional SiO2 as gate dielectric than high-k dielectric with the presence of interface state charge density that is typically observed at the interface of dielectric and 4H-SiC MOS surface.

  8. High-k dielectrics as bioelectronic interface for field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Borstlap, D

    2007-03-15

    Ion-sensitive field-effect transistors (ISFETs) are employed as bioelectronic sensors for the cell-transistor coupling and for the detection of DNA sequences. For these applications, thermally grown SiO{sub 2} films are used as standard gate dielectric. In the first part of this dissertation, the suitability of high-k dielectrics was studied to increase the gate capacitance and hence the signal-to-noise ratio of bioelectronic ISFETs: Upon culturing primary rat neurons on the corresponding high-k dielectrics, Al{sub 2}O{sub 3}, yttria stabilised zirkonia (YSZ), DyScO{sub 3}, CeO{sub 2}, LaAlO{sub 3}, GdScO{sub 3} and LaScO{sub 3} proved to be biocompatible substrates. Comprehensive electrical and electrochemical current-voltage measurements and capacitance-voltage measurements were performed for the determination of the dielectric properties of the high-k dielectrics. In the second part of the dissertation, standard SiO{sub 2} ISFETs with lower input capacitance and high-k dielectric Al{sub 2}O{sub 3}, YSZ und DyScO{sub 3} ISFETs were comprehensively characterised and compared with each other regarding their signal-to-noise ratio, their ion sensitivity and their drift behaviour. The ion sensitivity measurements showed that the YSZ ISFETs were considerably more sensitive to K{sup +} and Na{sup +} ions than the SiO{sub 2}, Al{sub 2}O{sub 3} und DyScO{sub 3} ISFETs. In the final third part of the dissertation, bioelectronic experiments were performed with the high-k ISFETs. The shape of the signals, which were measured from HL-1 cells with YSZ ISFETs, differed considerably from the corresponding measurements with SiO{sub 2} and DyScO{sub 3} ISFETs: After the onset of the K{sup +} current, the action potentials measured with YSZ ISFETs showed a strong drift in the direction opposite to the K{sup +} current signal. First coupling experiments between HEK 293 cells, which were transfected with a K{sup +} ion channel, and YSZ ISFETs affirmed the assumption from the HL-1

  9. Nano-CMOS gate dielectric engineering

    CERN Document Server

    Wong, Hei

    2011-01-01

    According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

  10. New theory of effective work functions at metal/high-k dielectric interfaces : application to metal/high-k HfO2 and la2O 3 dielectric interfaces

    OpenAIRE

    Shiraishi, Kenji; Nakayama, Takashi; Akasaka, Yasushi; Miyazaki, Seiichi; Nakaoka, Takashi; Ohmori, Kenji; Ahmet, Parhat; Torii, Kazuyoshi; Watanabe, Heiji; Chikyow, Toyohiro; Nara, Yasuo; Iwai, Hiroshi; Yamada, Keisaku

    2006-01-01

    We have constructed a universal theory of the work functions at metal/high-k HfO2 and La2O3 dielectric interfaces by introducing a new concept of generalized charge neutrality levels. Our theory systematically reproduces the experimentally observed work functions of various gate metals on Hf-based high-k dielectrics, including the hitherto unpredictable behaviors of the work functions of p-metals. Our new concept provides effective guiding principles to achieving near-bandedge work functions ...

  11. Integration issues of high-k and metal gate into conventional CMOS technology

    International Nuclear Information System (INIS)

    Song, S.C.; Zhang, Z.; Huffman, C.; Bae, S.H.; Sim, J.H.; Kirsch, P.; Majhi, P.; Moumen, N.; Lee, B.H.

    2006-01-01

    Issues surrounding the integration of Hf-based high-k dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate stack process as well as optimization of other CMOS process steps enables robust CMOSFETs with a wide process latitude. HfO 2 of a 2 nm physical thickness shows complete suppression of transient charge trapping resulting from a significant reduction in film volume as well as kinetically suppressed crystallization. Metal thickness is also critical when optimizing physical stress effects and minimizing dopant diffusion. A high temperature anneal after source and drain implantation in a conventional CMOSFET process reduces the interface state density and improves electron mobility

  12. Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology

    International Nuclear Information System (INIS)

    Weng, W.T.; Lin, H.C.; Huang, T.Y.; Lee, Y.J.; Lin, H.C.

    2009-01-01

    This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO 2 /poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

  13. Electronic States of High-k Oxides in Gate Stack Structures

    Science.gov (United States)

    Zhu, Chiyu

    In this dissertation, in-situ X-ray and ultraviolet photoemission spectroscopy have been employed to study the interface chemistry and electronic structure of potential high-k gate stack materials. In these gate stack materials, HfO2 and La2O3 are selected as high-k dielectrics, VO2 and ZnO serve as potential channel layer materials. The gate stack structures have been prepared using a reactive electron beam system and a plasma enhanced atomic layer deposition system. Three interrelated issues represent the central themes of the research: 1) the interface band alignment, 2) candidate high-k materials, and 3) band bending, internal electric fields, and charge transfer. 1) The most highlighted issue is the band alignment of specific high-k structures. Band alignment relationships were deduced by analysis of XPS and UPS spectra for three different structures: a) HfO2/VO2/SiO2/Si, b) HfO 2-La2O3/ZnO/SiO2/Si, and c) HfO 2/VO2/ HfO2/SiO2/Si. The valence band offset of HfO2/VO2, ZnO/SiO2 and HfO 2/SiO2 are determined to be 3.4 +/- 0.1, 1.5 +/- 0.1, and 0.7 +/- 0.1 eV. The valence band offset between HfO2-La2O3 and ZnO was almost negligible. Two band alignment models, the electron affinity model and the charge neutrality level model, are discussed. The results show the charge neutrality model is preferred to describe these structures. 2) High-k candidate materials were studied through comparison of pure Hf oxide, pure La oxide, and alloyed Hf-La oxide films. An issue with the application of pure HfO2 is crystallization which may increase the leakage current in gate stack structures. An issue with the application of pure La2O3 is the presence of carbon contamination in the film. Our study shows that the alloyed Hf-La oxide films exhibit an amorphous structure along with reduced carbon contamination. 3) Band bending and internal electric fields in the gate stack structure were observed by XPS and UPS and indicate the charge transfer during the growth and process. The oxygen

  14. Modeling of leakage currents in high-k dielectrics

    International Nuclear Information System (INIS)

    Jegert, Gunther Christian

    2012-01-01

    Leakage currents are one of the major bottlenecks impeding the downscaling efforts of the semiconductor industry. Two core devices of integrated circuits, the transistor and, especially, the DRAM storage capacitor, suffer from the increasing loss currents. In this perspective a fundamental understanding of the physical origin of these leakage currents is highly desirable. However, the complexity of the involved transport phenomena so far has prevented the development of microscopic models. Instead, the analysis of transport through the ultra-thin layers of high-permittivity (high-k) dielectrics, which are employed as insulating layers, was carried out at an empirical level using simple compact models. Unfortunately, these offer only limited insight into the physics involved on the microscale. In this context the present work was initialized in order to establish a framework of microscopic physical models that allow a fundamental description of the transport processes relevant in high-k thin films. A simulation tool that makes use of kinetic Monte Carlo techniques was developed for this purpose embedding the above models in an environment that allows qualitative and quantitative analyses of the electronic transport in such films. Existing continuum approaches, which tend to conceal the important physics behind phenomenological fitting parameters, were replaced by three-dimensional transport simulations at the level of single charge carriers. Spatially localized phenomena, such as percolation of charge carriers across pointlike defects, being subject to structural relaxation processes, or electrode roughness effects, could be investigated in this simulation scheme. Stepwise a self-consistent, closed transport model for the TiN/ZrO 2 material system, which is of outmost importance for the semiconductor industry, was developed. Based on this model viable strategies for the optimization of TiN/ZrO 2 /TiN capacitor structures were suggested and problem areas that may

  15. Modeling of leakage currents in high-k dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Jegert, Gunther Christian

    2012-03-15

    Leakage currents are one of the major bottlenecks impeding the downscaling efforts of the semiconductor industry. Two core devices of integrated circuits, the transistor and, especially, the DRAM storage capacitor, suffer from the increasing loss currents. In this perspective a fundamental understanding of the physical origin of these leakage currents is highly desirable. However, the complexity of the involved transport phenomena so far has prevented the development of microscopic models. Instead, the analysis of transport through the ultra-thin layers of high-permittivity (high-k) dielectrics, which are employed as insulating layers, was carried out at an empirical level using simple compact models. Unfortunately, these offer only limited insight into the physics involved on the microscale. In this context the present work was initialized in order to establish a framework of microscopic physical models that allow a fundamental description of the transport processes relevant in high-k thin films. A simulation tool that makes use of kinetic Monte Carlo techniques was developed for this purpose embedding the above models in an environment that allows qualitative and quantitative analyses of the electronic transport in such films. Existing continuum approaches, which tend to conceal the important physics behind phenomenological fitting parameters, were replaced by three-dimensional transport simulations at the level of single charge carriers. Spatially localized phenomena, such as percolation of charge carriers across pointlike defects, being subject to structural relaxation processes, or electrode roughness effects, could be investigated in this simulation scheme. Stepwise a self-consistent, closed transport model for the TiN/ZrO{sub 2} material system, which is of outmost importance for the semiconductor industry, was developed. Based on this model viable strategies for the optimization of TiN/ZrO{sub 2}/TiN capacitor structures were suggested and problem areas

  16. Microstructure and chemical analysis of Hf-based high-k dielectric layers in metal-insulator-metal capacitors

    Energy Technology Data Exchange (ETDEWEB)

    Thangadurai, P. [Department of Materials Engineering, Technion - Israel Institute of Technology, Haifa 32000 (Israel); Mikhelashvili, V.; Eisenstein, G. [Department of Electrical Engineering, Technion - Israel Institute of Technology, Haifa 32000 (Israel); Kaplan, W.D., E-mail: kaplan@tx.technion.ac.i [Department of Materials Engineering, Technion - Israel Institute of Technology, Haifa 32000 (Israel)

    2010-05-31

    The microstructure and chemistry of the high-k gate dielectric significantly influences the performance of metal-insulator-metal (MIM) and metal-oxide-semiconductor devices. In particular, the local structure, chemistry, and inter-layer mixing are important phenomena to be understood. In the present study, high resolution and analytical transmission electron microscopy are combined to study the local structure, morphology, and chemistry in MIM capacitors containing a Hf-based high-k dielectric. The gate dielectric, bottom and gate electrodes were deposited on p-type Si(100) wafers by electron beam evaporation. Four chemically distinguishable sub-layers were identified within the dielectric stack. One is an unintentionally formed 4.0 nm thick interfacial layer of Ta{sub 2}O{sub 5} at the interface between the Ta electrode and the dielectric. The other three layers are based on HfN{sub x}O{sub y} and HfTiO{sub y}, and intermixing between the nearby sub-layers including deposited SiO{sub 2}. Hf-rich clusters were found in the HfN{sub x}O{sub y} layer adjacent to the Ta{sub 2}O{sub 5} layer.

  17. Investigation of 6T SRAM memory circuit using high-k dielectrics based nano scale junctionless transistor

    Science.gov (United States)

    Charles Pravin, J.; Nirmal, D.; Prajoon, P.; Mohan Kumar, N.; Ajayan, J.

    2017-04-01

    In this paper the Dual Metal Surround Gate Junctionless Transistor (DMSGJLT) has been implemented with various high-k dielectric. The leakage current in the device is analysed in detail by obtaining the band structure for different high-k dielectric material. It is noticed that with increasing dielectric constant the device provides more resistance for the direct tunnelling of electron in off state. The gate oxide capacitance also shows 0.1 μF improvement with Hafnium Oxide (HfO2) than Silicon Oxide (SiO2). This paved the way for a better memory application when high-k dielectric is used. The Six Transistor (6T) Static Random Access Memory (SRAM) circuit implemented shows 41.4% improvement in read noise margin for HfO2 than SiO2. It also shows 37.49% improvement in write noise margin and 30.16% improvement in hold noise margin for HfO2 than SiO2.

  18. Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

    Science.gov (United States)

    Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

    2013-06-01

    In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

  19. Evolutionary search for new high-k dielectric materials: methodology and applications to hafnia-based oxides.

    Science.gov (United States)

    Zeng, Qingfeng; Oganov, Artem R; Lyakhov, Andriy O; Xie, Congwei; Zhang, Xiaodong; Zhang, Jin; Zhu, Qiang; Wei, Bingqing; Grigorenko, Ilya; Zhang, Litong; Cheng, Laifei

    2014-02-01

    High-k dielectric materials are important as gate oxides in microelectronics and as potential dielectrics for capacitors. In order to enable computational discovery of novel high-k dielectric materials, we propose a fitness model (energy storage density) that includes the dielectric constant, bandgap, and intrinsic breakdown field. This model, used as a fitness function in conjunction with first-principles calculations and the global optimization evolutionary algorithm USPEX, efficiently leads to practically important results. We found a number of high-fitness structures of SiO2 and HfO2, some of which correspond to known phases and some of which are new. The results allow us to propose characteristics (genes) common to high-fitness structures--these are the coordination polyhedra and their degree of distortion. Our variable-composition searches in the HfO2-SiO2 system uncovered several high-fitness states. This hybrid algorithm opens up a new avenue for discovering novel high-k dielectrics with both fixed and variable compositions, and will speed up the process of materials discovery.

  20. Design and Optimization of 22 nm Gate Length High-k/Metal gate NMOS Transistor

    International Nuclear Information System (INIS)

    Afifah Maheran A H; Menon P S; Shaari, S; Elgomati, H A; Salehuddin, F; Ahmad, I

    2013-01-01

    In this paper, we invented the optimization experiment design of a 22 nm gate length NMOS device which uses a combination of high-k material and metal as the gate which was numerically developed using an industrial-based simulator. The high-k material is Titanium dioxide (TiO 2 ), while the metal gate is Tungsten Silicide (WSi x ). The design is optimized using the L9 Taguchi method to get the optimum parameter design. There are four process parameters and two noise parameters which were varied for analyzing the effect on the threshold voltage (V th ). The objective of this experiment is to minimize the variance of V th where Taguchi's nominal-the-best signal-to-noise ratio (S/N Ratio) was used. The best settings of the process parameters were determined using Analysis of Mean (ANOM) and analysis of variance (ANOVA) to reduce the variability of V th . The results show that the V th values have least variance and the mean value can be adjusted to 0.306V ±0.027 for the NMOS device which is in line with projections by the ITRS specifications.

  1. 4f-5d hybridization in a high k dielectric

    International Nuclear Information System (INIS)

    Losovyj, Ya.B.; Tang, Jinke; Wang, Wendong; Hong Yuanjia; Palshin, Vadim; Tittsworth, Roland

    2006-01-01

    While intra-atomic f-d hybridization is expected, experimental confirmation of f-d hybridization in the photoemission final state leading to 4f band structure has been limited to 5f systems and compound systems with very shallow 4f levels. We demonstrate that core 4f states can contribute to the valence band structure in a wide band gap dielectric, in this case HfO 2 in the photoemission final state. In spite of the complications of sample charging, we find evidence of symmetry in the shallow 4f levels and wave vector dependent band dispersion, the latter consistent with the crystal structure of HfO 2

  2. Atomic layer deposition of crystalline SrHfO3 directly on Ge (001) for high-k dielectric applications

    International Nuclear Information System (INIS)

    McDaniel, Martin D.; Ngo, Thong Q.; Ekerdt, John G.; Hu, Chengqing; Jiang, Aiting; Yu, Edward T.; Lu, Sirong; Smith, David J.; Posadas, Agham; Demkov, Alexander A.

    2015-01-01

    The current work explores the crystalline perovskite oxide, strontium hafnate, as a potential high-k gate dielectric for Ge-based transistors. SrHfO 3 (SHO) is grown directly on Ge by atomic layer deposition and becomes crystalline with epitaxial registry after post-deposition vacuum annealing at ∼700 °C for 5 min. The 2 × 1 reconstructed, clean Ge (001) surface is a necessary template to achieve crystalline films upon annealing. The SHO films exhibit excellent crystallinity, as shown by x-ray diffraction and transmission electron microscopy. The SHO films have favorable electronic properties for consideration as a high-k gate dielectric on Ge, with satisfactory band offsets (>2 eV), low leakage current (<10 −5 A/cm 2 at an applied field of 1 MV/cm) at an equivalent oxide thickness of 1 nm, and a reasonable dielectric constant (k ∼ 18). The interface trap density (D it ) is estimated to be as low as ∼2 × 10 12  cm −2  eV −1 under the current growth and anneal conditions. Some interfacial reaction is observed between SHO and Ge at temperatures above ∼650 °C, which may contribute to increased D it value. This study confirms the potential for crystalline oxides grown directly on Ge by atomic layer deposition for advanced electronic applications

  3. Combining a multi deposition multi annealing technique with a scavenging (Ti) to improve the high-k/metal gate stack performance for a gate-last process

    International Nuclear Information System (INIS)

    Zhang ShuXiang; Yang Hong; Tang Bo; Tang Zhaoyun; Xu Yefeng; Xu Jing; Yan Jiang

    2014-01-01

    ALD HfO 2 films fabricated by a novel multi deposition multi annealing (MDMA) technique are investigated, we have included samples both with and without a Ti scavenging layer. As compared to the reference gate stack treated by conventional one-time deposition and annealing (D and A), devices receiving MDMA show a significant reduction in leakage current. Meanwhile, EOT growth is effectively controlled by the Ti scavenging layer. This improvement strongly correlates with the cycle number of D and A (while keeping the total annealing time and total dielectrics thickness the same). Transmission electron microscope and energy-dispersive X-ray spectroscopy analysis suggests that oxygen incorporation into both the high-k film and the interfacial layer is likely to be responsible for the improvement of the device. This novel MDMA is promising for the development of gate stack technology in a gate last integration scheme. (semiconductor technology)

  4. Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor

    Science.gov (United States)

    Madan, Jaya; Gupta, R. S.; Chaujar, Rishu

    2015-09-01

    In this work, an analytical drain current model for gate dielectric engineered (hetero dielectric)-dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed. Parabolic approximation has been used to solve the two-dimensional (2D) Poisson equation with appropriate boundary conditions and continuity equations to evaluate analytical expressions for surface potential, electric field, tunneling barrier width and drain current. Further, the analog performance of the device is studied for three high-k dielectrics (Si3N4, HfO2, and ZrO2), and it has been investigated that the problem of lower ION, can be overcome by using the hetero-gate architecture. Moreover, the impact of scaling the gate oxide thickness and bias variations has also been studied. The HD-DMG-GAA-TFET shows an enhanced ION of the order of 10-4 A. The effectiveness of the proposed model is validated by comparing it with ATLAS device simulations.

  5. Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs

    Science.gov (United States)

    Dentoni Litta, E.; Hellström, P.-E.; Östling, M.

    2015-06-01

    High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.

  6. Intermodulation Linearity in High-k/Metal Gate 28 nm RF CMOS Transistors

    Directory of Open Access Journals (Sweden)

    Zhen Li

    2015-09-01

    Full Text Available This paper presents experimental characterization, simulation, and Volterra series based analysis of intermodulation linearity on a high-k/metal gate 28 nm RF CMOS technology. A figure-of-merit is proposed to account for both VGS and VDS nonlinearity, and extracted from frequency dependence of measured IIP3. Implications to biasing current and voltage optimization for linearity are discussed.

  7. Study of strained-Si p-channel MOSFETs with HfO2 gate dielectric

    Science.gov (United States)

    Pradhan, Diana; Das, Sanghamitra; Dash, Tara Prasanna

    2016-10-01

    In this work, the transconductance of strained-Si p-MOSFETs with high-K dielectric (HfO2) as gate oxide, has been presented through simulation using the TCAD tool Silvaco-ATLAS. The results have been compared with a SiO2/strained-Si p-MOSFET device. Peak transconductance enhancement factors of 2.97 and 2.73 has been obtained for strained-Si p-MOSFETs in comparison to bulk Si channel p-MOSFETs with SiO2 and high-K dielectric respectively. This behavior is in good agreement with the reported experimental results. The transconductance of the strained-Si device at low temperatures has also been simulated. As expected, the mobility and hence the transconductance increases at lower temperatures due to reduced phonon scattering. However, the enhancements with high-K gate dielectric is less as compared to that with SiO2.

  8. Towards low-voltage organic thin film transistors (OTFTs with solution-processed high-k dielectric and interface engineering

    Directory of Open Access Journals (Sweden)

    Yaorong Su

    2015-11-01

    Full Text Available Although impressive progress has been made in improving the performance of organic thin film transistors (OTFTs, the high operation voltage resulting from the low gate capacitance density of traditional SiO2 remains a severe limitation that hinders OTFTs'development in practical applications. In this regard, developing new materials with high-k characteristics at low cost is of great scientific and technological importance in the area of both academia and industry. Here, we introduce a simple solution-based technique to fabricate high-k metal oxide dielectric system (ATO at low-temperature, which can be used effectively to realize low-voltage operation of OTFTs. On the other hand, it is well known that the properties of the dielectric/semiconductor and electrode/semiconductor interfaces are crucial in controlling the electrical properties of OTFTs. By optimizing the above two interfaces with octadecylphosphonic acid (ODPA self-assembled monolayer (SAM and properly modified low-cost Cu, obviously improved device performance is attained in our low-voltage OTFTs. Further more, organic electronic devices on flexible substrates have attracted much attention due to their low-cost, rollability, large-area processability, and so on. Basing on the above results, outstanding electrical performance is achieved in flexible devices. Our studies demonstrate an effective way to realize low-voltage, high-performance OTFTs at low-cost.

  9. High performance solution processed zirconium oxide gate dielectric appropriate for low temperature device application

    Energy Technology Data Exchange (ETDEWEB)

    Hasan, Musarrat; Nguyen, Manh-Cuong; Kim, Hyojin; You, Seung-Won; Jeon, Yoon-Seok; Tong, Duc-Tai; Lee, Dong-Hwi; Jeong, Jae Kyeong; Choi, Rino, E-mail: rino.choi@inha.ac.kr

    2015-08-31

    This paper reports a solution processed electrical device with zirconium oxide gate dielectric that was fabricated at a low enough temperature appropriate for flexible electronics. Both inorganic dielectric and channel materials were synthesized in the same organic solvent. The dielectric constant achieved was 13 at 250 °C with a reasonably low leakage current. The bottom gate transistor devices showed the highest mobility of 75 cm{sup 2}/V s. The device is operated at low voltage with high-k dielectric with excellent transconductance and low threshold voltage. Overall, the results highlight the potential of low temperature solution based deposition in fabricating more complicated circuits for a range of applications. - Highlights: • We develop a low temperature inorganic dielectric deposition process. • We fabricate oxide semiconductor channel devices using all-solution processes. • Same solvent is used for dielectric and oxide semiconductor deposition.

  10. Improved integration of ultra-thin high-k dielectrics in few-layer MoS2 FET by remote forming gas plasma pretreatment

    Science.gov (United States)

    Wang, Xiao; Zhang, Tian-Bao; Yang, Wen; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

    2017-01-01

    The effective and high-quality integration of high-k dielectrics on two-dimensional (2D) crystals is essential to the device structure engineering and performance improvement of field-effect transistor (FET) based on the 2D semiconductors. We report a 2D MoS2 transistor with ultra-thin Al2O3 top-gate dielectric (6.1 nm) and extremely low leakage current. Remote forming gas plasma pretreatment was carried out prior to the atomic layer deposition, providing nucleation sites with the physically adsorbed ions on the MoS2 surface. The top gate MoS2 FET exhibited excellent electrical performance, including high on/off current ratio over 109, subthreshold swing of 85 mV/decade and field-effect mobility of 45.03 cm2/V s. Top gate leakage current less than 0.08 pA/μm2 at 4 MV/cm has been obtained, which is the smallest compared with the reported top-gated MoS2 transistors. Such an optimized integration of high-k dielectric in 2D semiconductor FET with enhanced performance is very attractive, and it paves the way towards the realization of more advanced 2D nanoelectronic devices and integrated circuits.

  11. Extraction and dielectric properties of curcuminoid films grown on Si substrate for high-k dielectric applications

    International Nuclear Information System (INIS)

    Dakhel, A.A.; Jasim, Khalil E.; Cassidy, S.; Henari, F.Z.

    2013-01-01

    Highlights: • The unknown insulating properties of curcuminoid extract are systematically studied. • Optical study gives a bandgap of 3.15 eV and a refractive index of 1.92 at 505 nm. • Turmeric is a high-k environmental friendly material for use in microelectronics. • Curcuminoid extract can be used as insulator of MIS devices with ε ′ ∞ ≈54.2. -- Abstract: Curcuminoids were extracted from turmeric powder and evaporated in vacuum to prepare thin films on p-Si and glass substrates for dielectric and optical investigations. The optical absorption spectrum of the prepared amorphous film was not identical to that of the molecular one, which was identified by a strong wide absorption band in between ∼220 and 540 nm. The onset energy of the optical absorption of the film was calculated by using Hamberg et al. method. The dielectric properties of this material were systematically studied for future eco friendly applications in metal–insulator–semiconductor MIS field of applications. The complex dielectric properties were studied in the frequency range of 1–1000 kHz and was analysed in-terms of dielectric impedance Z * (ω) and modulus M * (ω). Generally, the curcuminoid complex can be considered as a high-k material and can be used in the environmental friendly production of microelectronic devices

  12. Extraction and dielectric properties of curcuminoid films grown on Si substrate for high-k dielectric applications

    Energy Technology Data Exchange (ETDEWEB)

    Dakhel, A.A.; Jasim, Khalil E. [Department of Physics, College of Science, University of Bahrain, P.O. Box 32038 (Bahrain); Cassidy, S. [Department of Basic Medical Sciences, Royal College of Surgeons in Ireland, Medical University of Bahrain, P.O. Box 15503 (Bahrain); Henari, F.Z., E-mail: fzhenari@rcsi-mub.com [Department of Basic Medical Sciences, Royal College of Surgeons in Ireland, Medical University of Bahrain, P.O. Box 15503 (Bahrain)

    2013-09-20

    Highlights: • The unknown insulating properties of curcuminoid extract are systematically studied. • Optical study gives a bandgap of 3.15 eV and a refractive index of 1.92 at 505 nm. • Turmeric is a high-k environmental friendly material for use in microelectronics. • Curcuminoid extract can be used as insulator of MIS devices with ε{sup ′}{sub ∞}≈54.2. -- Abstract: Curcuminoids were extracted from turmeric powder and evaporated in vacuum to prepare thin films on p-Si and glass substrates for dielectric and optical investigations. The optical absorption spectrum of the prepared amorphous film was not identical to that of the molecular one, which was identified by a strong wide absorption band in between ∼220 and 540 nm. The onset energy of the optical absorption of the film was calculated by using Hamberg et al. method. The dielectric properties of this material were systematically studied for future eco friendly applications in metal–insulator–semiconductor MIS field of applications. The complex dielectric properties were studied in the frequency range of 1–1000 kHz and was analysed in-terms of dielectric impedance Z{sup *}(ω) and modulus M{sup *}(ω). Generally, the curcuminoid complex can be considered as a high-k material and can be used in the environmental friendly production of microelectronic devices.

  13. Polaron-electron assisted giant dielectric dispersion in SrZrO{sub 3} high-k dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Borkar, Hitesh; Barvat, Arun; Pal, Prabir; Kumar, Ashok, E-mail: ashok553@nplindia.org [CSIR-National Physical Laboratory, Dr. K. S. Krishnan Marg, New Delhi 110012 (India); Academy of Scientific and Innovative Research (AcSIR), CSIR-National Physical Laboratory (CSIR-NPL) Campus, Dr. K S Krishnan Marg, New Delhi 110012 (India); Shukla, A. K. [CSIR-National Physical Laboratory, Dr. K. S. Krishnan Marg, New Delhi 110012 (India); Pulikkotil, J. J. [CSIR-National Physical Laboratory, Dr. K. S. Krishnan Marg, New Delhi 110012 (India); Academy of Scientific and Innovative Research (AcSIR), CSIR-National Physical Laboratory (CSIR-NPL) Campus, Dr. K S Krishnan Marg, New Delhi 110012 (India); Computation and Networking Facility, CSIR-National Physical Laboratory, New Delhi 110012 (India)

    2016-06-07

    The SrZrO{sub 3} is a well known high-k dielectric constant (∼22) and high optical bandgap (∼5.8 eV) material and one of the potential candidates for future generation nanoelectronic logic elements (8 nm node technology) beyond silicon. Its dielectric behavior is fairly robust and frequency independent till 470 K; however, it suffers a strong small-polaron based electronic phase transition (T{sub e}) linking 650 to 750 K. The impedance spectroscopy measurements revealed the presence of conducting grains and grain boundaries at elevated temperature which provide energetic mobile charge carriers with activation energy in the range of 0.7 to 1.2 eV supporting the oxygen ions and proton conduction. X-ray photoemission spectroscopy measurements suggest the presence of weak non-stoichiometric O{sup 2−} anions and hydroxyl species bound to different sites at the surface and bulk. These thermally activated charge carriers at elevated temperature significantly contribute to the polaronic based dielectric anomaly and conductivity. Our dielectric anomaly supports pseudo phase transition due to high degree of change in ZrO{sub 6} octahedral angle in the temperature range of 650–750 K, where electron density and phonon vibration affect the dielectric and conductivity properties.

  14. From surface to volume plasmons in hyperbolic metamaterials: General existence conditions for bulk high-k waves in metal-dielectric and graphene-dielectric multilayers

    DEFF Research Database (Denmark)

    Zhukovsky, Sergei; Andryieuski, Andrei; Sipe, John E.

    2014-01-01

    -dielectric and recently introduced graphene-dielectric stacks. We confirm that short-range surface plasmons in thin metal layers can give rise to hyperbolic metamaterial properties and demonstrate that long-range surface plasmons cannot. We also show that graphene-dielectric multilayers tend to support high- k waves...

  15. Yttrium scandate thin film as alternative high-permittivity dielectric for germanium gate stack formation

    Energy Technology Data Exchange (ETDEWEB)

    Lu, Cimang, E-mail: cimang@adam.t.u-tokyo.ac.jp; Lee, Choong Hyun; Nishimura, Tomonori; Toriumi, Akira [Department of Materials Engineering, The University of Tokyo, 7-3-1 Hongo, Tokyo 113-8656 (Japan); JST, CREST, 7-3-1 Hongo, Tokyo 113-8656 (Japan)

    2015-08-17

    We investigated yttrium scandate (YScO{sub 3}) as an alternative high-permittivity (k) dielectric thin film for Ge gate stack formation. Significant enhancement of k-value is reported in YScO{sub 3} comparing to both of its binary compounds, Y{sub 2}O{sub 3} and Sc{sub 2}O{sub 3}, without any cost of interface properties. It suggests a feasible approach to a design of promising high-k dielectrics for Ge gate stack, namely, the formation of high-k ternary oxide out of two medium-k binary oxides. Aggressive scaling of equivalent oxide thickness (EOT) with promising interface properties is presented by using YScO{sub 3} as high-k dielectric and yttrium-doped GeO{sub 2} (Y-GeO{sub 2}) as interfacial layer, for a demonstration of high-k gate stack on Ge. In addition, we demonstrate Ge n-MOSFET performance showing the peak electron mobility over 1000 cm{sup 2}/V s in sub-nm EOT region by YScO{sub 3}/Y-GeO{sub 2}/Ge gate stack.

  16. Poly(methyl methacrylate) as a self-assembled gate dielectric for graphene field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Sanne, A.; Movva, H. C. P.; Kang, S.; McClellan, C.; Corbet, C. M.; Banerjee, S. K. [Microelectronics Research Center, University of Texas, Austin, Texas 78758 (United States)

    2014-02-24

    We investigate poly(methyl methacrylate) (PMMA) as a low thermal budget organic gate dielectric for graphene field effect-transistors (GFETs) based on a simple process flow. We show that high temperature baking steps above the glass transition temperature (∼130 °C) can leave a self-assembled, thin PMMA film on graphene, where we get a gate dielectric almost for “free” without additional atomic layer deposition type steps. Electrical characterization of GFETs with PMMA as a gate dielectric yields a dielectric constant of k = 3.0. GFETs with thinner PMMA dielectrics have a lower dielectric constant due to decreased polarization arising from neutralization of dipoles and charged carriers as baking temperatures increase. The leakage through PMMA gate dielectric increases with decreasing dielectric thickness and increasing electric field. Unlike conventional high-k gate dielectrics, such low-k organic gate dielectrics are potentially attractive for devices such as the proposed Bilayer pseudoSpin Field-Effect Transistor or flexible high speed graphene electronics.

  17. Gate-first integration of tunable work function metal gates of different thicknesses into high-k metal gates CMOS FinFETs for multi- VTh engineering

    KAUST Repository

    Hussain, Muhammad Mustafa

    2010-03-01

    Gate-first integration of tunable work function metal gates of different thicknesses (320 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ∼ 40 mV/V), nearly symmetric VTh, low T inv(∼ 1.4 nm), and high Ion(∼780μAμm) for N/PMOS without any intentional strain enhancement. © 2006 IEEE.

  18. Gate-first integration of tunable work function metal gates of different thicknesses into high-k metal gates CMOS FinFETs for multi- VTh engineering

    KAUST Repository

    Hussain, Muhammad Mustafa; Smith, Casey Eben; Harris, Harlan Rusty; Young, Chadwin; Tseng, Hsinghuang; Jammy, Rajarao

    2010-01-01

    Gate-first integration of tunable work function metal gates of different thicknesses (320 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ∼ 40 mV/V), nearly symmetric VTh, low T inv(∼ 1.4 nm), and high Ion(∼780μAμm) for N/PMOS without any intentional strain enhancement. © 2006 IEEE.

  19. Flexible semi-transparent silicon (100) fabric with high-k/metal gate devices

    KAUST Repository

    Rojas, Jhonathan Prieto

    2013-01-07

    Can we build a flexible and transparent truly high performance computer? High-k/metal gate stack based metal-oxide-semiconductor capacitor devices are monolithically fabricated on industry\\'s most widely used low-cost bulk single-crystalline silicon (100) wafers and then released as continuous, mechanically flexible, optically semi-transparent and high thermal budget compatible silicon fabric with devices. This is the first ever demonstration with this set of materials which allows full degree of freedom to fabricate nanoelectronics devices using state-of-the-art CMOS compatible processes and then to utilize them in an unprecedented way for wide deployment over nearly any kind of shape and architecture surfaces. Electrical characterization shows uncompromising performance of post release devices. Mechanical characterization shows extra-ordinary flexibility (minimum bending radius of 1 cm) making this generic process attractive to extend the horizon of flexible electronics for truly high performance computers. Schematic and photograph of flexible high-k/metal gate MOSCAPs showing high flexibility and C-V plot showing uncompromised performance. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  20. Analyzing the effect of gate dielectric on the leakage currents

    Directory of Open Access Journals (Sweden)

    Sakshi

    2016-01-01

    Full Text Available An analytical threshold voltage model for MOSFETs has been developed using different gate dielectric oxides by using MATLAB software. This paper explains the dependency of threshold voltage on the dielectric material. The variation in the subthreshold currents with the change in the threshold voltage sue to the change of dielectric material has also been studied.

  1. Backside versus frontside advanced chemical analysis of high-k/metal gate stacks

    Energy Technology Data Exchange (ETDEWEB)

    Martinez, E., E-mail: eugenie.martinez@cea.fr [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Saidi, B. [STMicroelectronics, 850 rue Jean Monnet, 38926 Rousset Cedex, Crolles (France); Veillerot, M. [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Caubet, P. [STMicroelectronics, 850 rue Jean Monnet, 38926 Rousset Cedex, Crolles (France); Fabbri, J-M. [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Piallat, F. [STMicroelectronics, 850 rue Jean Monnet, 38926 Rousset Cedex, Crolles (France); Gassilloud, R. [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Schamm-Chardon, S. [CEMES-CNRS et Université de Toulouse, 29 rue Jeanne Marvig, 31055 Toulouse (France)

    2015-08-15

    Highlights: • The backside approach is a promising solution for advanced chemical characterization of future MOSFETs. • Frontside ToF-SIMS and Auger depth profiles are affected by cumulative mixing effects and thus not relevant for analyzing ultra-thin layers. • Higher in-depth resolution is possible in the backside approach for Auger and ToF-SIMS depth profiling. • Backside depth profiling allows revealing ultra-thin layers and elemental in-depth redistribution inside high-k/metal gate stacks. • Backside XPS allows preserving the full metal gate, thus enabling the analysis of real technological samples. - Abstract: Downscaling of transistors beyond the 14 nm technological node requires the implementation of new architectures and materials. Advanced characterization methods are needed to gain information about the chemical composition of buried layers and interfaces. An effective approach based on backside analysis is presented here. X-ray photoelectron spectroscopy, Auger depth profiling and time-of-flight secondary ions mass spectrometry are combined to investigate inter-diffusion phenomena. To highlight improvements related to the backside method, backside and frontside analyses are compared. Critical information regarding nitrogen, oxygen and aluminium redistribution inside the gate stacks is obtained only in the backside configuration.

  2. Full Polymer Dielectric Elastomeric Actuators (DEA Functionalised with Carbon Nanotubes and High-K Ceramics

    Directory of Open Access Journals (Sweden)

    Tilo Köckritz

    2016-09-01

    Full Text Available Dielectric elastomer actuators (DEA are special devices which have a simple working and construction principle and outstanding actuation properties. The DEAs consist of a combination of different materials for the dielectric and electrode layers. The combination of these layers causes incompatibilities in their interconnections. Dramatic differences in the mechanical properties and bad adhesion of the layers are the principal causes for the reduction of the actuation displacement and strong reduction of lifetime. Common DEAs achieve actuation displacements of 2% and a durability of some million cycles. The following investigations represent a new approach to solving the problems of common systems. The investigated DEA consists of only one basic raw polymer, which was modified according to the required demands of each layer. The basic raw polymer was modified with single-walled carbon nanotubes or high-k ceramics, for example, lead magnesium niobate-lead titanate. The development of the full polymer DEA comprised the development of materials and technologies to realise a reproducible layer composition. It was proven that the full polymer actuator worked according to the theoretical rules. The investigated system achieved actuation displacements above 20% regarding thickness, outstanding interconnections at each layer without any failures, and durability above 3 million cycles without any indication of an impending malfunction.

  3. Pentacene-Based Thin Film Transistor with Inkjet-Printed Nanocomposite High-K Dielectrics

    Directory of Open Access Journals (Sweden)

    Chao-Te Liu

    2012-01-01

    Full Text Available The nanocomposite gate insulating film of a pentacene-based thin film transistor was deposited by inkjet printing. In this study, utilizing the pearl miller to crumble the agglomerations and the dispersant to well stabilize the dispersion of nano-TiO2 particles in the polymer matrix of the ink increases the dose concentration for pico-jetting, which could be as the gate dielectric film made by inkjet printing without the photography process. Finally, we realized top contact pentacene-TFTs and successfully accomplished the purpose of directly patternability and increase the performance of the device based on the nanocomposite by inkjet printing. These devices exhibited p-channel TFT characteristics with a high field-effect mobility (a saturation mobility of ̃0.58 cm2 V−1 s−1, a large current ratio (>103 and a low operation voltage (<6 V. Furthermore, we accorded the deposited mechanisms which caused the interface difference between of inkjet printing and spin coating. And we used XRD, SEM, Raman spectroscopy to help us analyze the transfer characteristics of pentacene films and the performance of OTFTs.

  4. Evaluation of the effects of thermal annealing temperature and high-k dielectrics on amorphous InGaZnO thin films by using pseudo-MOS transistors

    International Nuclear Information System (INIS)

    Lee, Se-Won; Cho, Won-Ju

    2012-01-01

    The effects of annealing temperatures and high-k gate dielectric materials on the amorphous In-Ga-Zn-O thin-film transistors (a-IGZO TFTs) were investigated using pseudo-metal-oxide semiconductor transistors (Ψ-MOSFETs), a method without conventional source/drain (S/D) layer deposition. Annealing of the a-IGZO film was carried out at 150 - 900 .deg. C in a N 2 ambient for 30 min. As the annealing temperature was increased, the electrical characteristics of Ψ-MOSFETs on a-IGZO were drastically improved. However, when the annealing temperature exceeded 700 .deg. C, a deterioration of the MOS parameters was observed, including a shift of the threshold voltage (V th ) in a negative direction, an increase in the subthreshold slope (SS) and hysteresis, a decrease in the field effect mobility (μ FE ), an increase in the trap density (N t ), and a decrease in the on/off ratio. Meanwhile, the high-k gate dielectrics enhanced the performance of a-IGZO Ψ-MOSFETs. The ZrO 2 gate dielectrics particularly exhibited excellent characteristics in terms of SS (128 mV/dec), μ FE (10.2 cm -2 /V·s), N t (1.1 x 10 12 cm -2 ), and on/off ratio (5.3 x 10 6 ). Accordingly, the Ψ-MOSFET structure is a useful method for rapid evaluation of the effects of the process and the material on a-IGZO TFTs without a conventional S/D layer deposition.

  5. Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks

    International Nuclear Information System (INIS)

    Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Liu, Xi-Wen; Chang, Ting-Chang; Chen, Ching-En; Ho, Szu-Han; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Lu, Ching-Sen

    2014-01-01

    This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO 2 interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks.

  6. A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

    Science.gov (United States)

    Wallace, Robert M.

    2001-03-01

    Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

  7. Atomic layer deposition of crystalline SrHfO{sub 3} directly on Ge (001) for high-k dielectric applications

    Energy Technology Data Exchange (ETDEWEB)

    McDaniel, Martin D.; Ngo, Thong Q.; Ekerdt, John G., E-mail: ekerdt@utexas.edu [Department of Chemical Engineering, The University of Texas at Austin, Austin, Texas 78712 (United States); Hu, Chengqing; Jiang, Aiting; Yu, Edward T. [Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States); Lu, Sirong; Smith, David J. [Department of Physics, Arizona State University, Tempe, Arizona 85287 (United States); Posadas, Agham; Demkov, Alexander A. [Department of Physics, The University of Texas at Austin, Austin, Texas 78712 (United States)

    2015-02-07

    The current work explores the crystalline perovskite oxide, strontium hafnate, as a potential high-k gate dielectric for Ge-based transistors. SrHfO{sub 3} (SHO) is grown directly on Ge by atomic layer deposition and becomes crystalline with epitaxial registry after post-deposition vacuum annealing at ∼700 °C for 5 min. The 2 × 1 reconstructed, clean Ge (001) surface is a necessary template to achieve crystalline films upon annealing. The SHO films exhibit excellent crystallinity, as shown by x-ray diffraction and transmission electron microscopy. The SHO films have favorable electronic properties for consideration as a high-k gate dielectric on Ge, with satisfactory band offsets (>2 eV), low leakage current (<10{sup −5} A/cm{sup 2} at an applied field of 1 MV/cm) at an equivalent oxide thickness of 1 nm, and a reasonable dielectric constant (k ∼ 18). The interface trap density (D{sub it}) is estimated to be as low as ∼2 × 10{sup 12 }cm{sup −2 }eV{sup −1} under the current growth and anneal conditions. Some interfacial reaction is observed between SHO and Ge at temperatures above ∼650 °C, which may contribute to increased D{sub it} value. This study confirms the potential for crystalline oxides grown directly on Ge by atomic layer deposition for advanced electronic applications.

  8. Surface and interfacial chemistry of high-k dielectric and interconnect materials on silicon

    Science.gov (United States)

    Kirsch, Paul Daniel

    Surfaces and interfaces play a critical role in the manufacture and function of silicon based integrated circuits. It is therefore reasonable to study the chemistries at these surfaces and interfaces to improve existing processes and to develop new ones. Model barium strontium titanate high-k dielectric systems have been deposited on ultrathin silicon oxynitride in ultrahigh vacuum. The resulting nanostructures are characterized with secondary ion mass spectroscopy (SIMS) and X-ray photoelectron spectroscopy (XPS). An interfacial reaction between Ba and Sr atoms and SiOxNy was found to create silicates, BaSixOy or SrSi xOy. Inclusion of N in the interfacial oxide decreased silicate formation in both Ba and Sr systems. Furthermore, inclusion of N in the interfacial oxide decreased the penetration of Ba and Sr containing species, such as silicides and silicates. Sputter deposited HfO2 was studied on nitrided and unnitrided Si(100) surfaces. XPS and SIMS were used to verify the presence of interfacial HfSixOy and estimate its relative amount on both nitrided and unnitrided samples. More HfSixOy formed without the SiNx interfacial layer. These interfacial chemistry results are then used to explain the electrical measurements obtained from metal oxide semiconductor (MOS) capacitors. MOS capacitors with interfacial SiNx exhibit reduced leakage current and increased capacitance. Lastly, surface science techniques were used to develop a processing technique for reducing thin films of copper (II) and copper (I) oxide to copper. Deuterium atoms (D*) and methyl radicals (CH3*) were shown to reduce Cu 2+ and/or Cu1+ to Cu0 within 30 min at a surface temperature of 400 K under a flux of 1 x 1015 atoms/cm2s. Temperature programmed desorption experiments suggest that oxygen leaves the surface as D2O and CO2 for the D* and CH3* treated surfaces, respectively.

  9. CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

    Science.gov (United States)

    Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

    2018-04-01

    Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

  10. Integration of atomic layer deposited high-k dielectrics on GaSb via hydrogen plasma exposure

    Directory of Open Access Journals (Sweden)

    Laura B. Ruppalt

    2014-12-01

    Full Text Available In this letter we report the efficacy of a hydrogen plasma pretreatment for integrating atomic layer deposited (ALD high-k dielectric stacks with device-quality p-type GaSb(001 epitaxial layers. Molecular beam eptiaxy-grown GaSb surfaces were subjected to a 30 minute H2/Ar plasma treatment and subsequently removed to air. High-k HfO2 and Al2O3/HfO2 bilayer insulating films were then deposited via ALD and samples were processed into standard metal-oxide-semiconductor (MOS capacitors. The quality of the semiconductor/dielectric interface was probed by current-voltage and variable-frequency admittance measurements. Measurement results indicate that the H2-plamsa pretreatment leads to a low density of interface states nearly independent of the deposited dielectric material, suggesting that pre-deposition H2-plasma exposure, coupled with ALD of high-k dielectrics, may provide an effective means for achieving high-quality GaSb MOS structures for advanced Sb-based digital and analog electronics.

  11. Energy-loss return gate via liquid dielectric polarization.

    Science.gov (United States)

    Kim, Taehun; Yong, Hyungseok; Kim, Banseok; Kim, Dongseob; Choi, Dukhyun; Park, Yong Tae; Lee, Sangmin

    2018-04-12

    There has been much research on renewable energy-harvesting techniques. However, owing to increasing energy demands, significant energy-related issues remain to be solved. Efforts aimed at reducing the amount of energy loss in electric/electronic systems are essential for reducing energy consumption and protecting the environment. Here, we design an energy-loss return gate system that reduces energy loss from electric/electronic systems by utilizing the polarization of liquid dielectrics. The use of a liquid dielectric material in the energy-loss return gate generates electrostatic potential energy while reducing the dielectric loss of the electric/electronic system. Hence, an energy-loss return gate can make breakthrough impacts possible by amplifying energy-harvesting efficiency, lowering the power consumption of electronics, and storing the returned energy. Our study indicates the potential for enhancing energy-harvesting technologies for electric/electronics systems, while increasing the widespread development of these systems.

  12. Understanding the Structure of High-K Gate Oxides - Oral Presentation

    Energy Technology Data Exchange (ETDEWEB)

    Miranda, Andre [SLAC National Accelerator Lab., Menlo Park, CA (United States)

    2015-08-25

    Hafnium Oxide (HfO2) amorphous thin films are being used as gate oxides in transistors because of their high dielectric constant (κ) over Silicon Dioxide. The present study looks to find the atomic structure of HfO2 thin films which hasn’t been done with the technique of this study. In this study, two HfO2 samples were studied. One sample was made with thermal atomic layer deposition (ALD) on top of a Chromium and Gold layer on a silicon wafer. The second sample was made with plasma ALD on top of a Chromium and Gold layer on a Silicon wafer. Both films were deposited at a thickness of 50nm. To obtain atomic structure information, Grazing Incidence X-ray diffraction (GIXRD) was carried out on the HfO2 samples. Because of this, absorption, footprint, polarization, and dead time corrections were applied to the scattering intensity data collected. The scattering curves displayed a difference in structure between the ALD processes. The plasma ALD sample showed the broad peak characteristic of an amorphous structure whereas the thermal ALD sample showed an amorphous structure with characteristics of crystalline materials. This appears to suggest that the thermal process results in a mostly amorphous material with crystallites within. Further, the scattering intensity data was used to calculate a pair distribution function (PDF) to show more atomic structure. The PDF showed atom distances in the plasma ALD sample had structure up to 10 Å, while the thermal ALD sample showed the same structure below 10 Å. This structure that shows up below 10 Å matches the bond distances of HfO2 published in literature. The PDF for the thermal ALD sample also showed peaks up to 20 Å, suggesting repeating atomic spacing outside the HfO2 molecule in the sample. This appears to suggest that there is some crystalline structure within the thermal ALD sample.

  13. SEMICONDUCTOR DEVICES: Structural and electrical characteristics of lanthanum oxide gate dielectric film on GaAs pHEMT technology

    Science.gov (United States)

    Chia-Song, Wu; Hsing-Chung, Liu

    2009-11-01

    This paper investigates the feasibility of using a lanthanum oxide thin film (La2O3) with a high dielectric constant as a gate dielectric on GaAs pHEMTs to reduce gate leakage current and improve the gate to drain breakdown voltage relative to the conventional GaAs pHEMT. An E/D mode pHEMT in a single chip was realized by selecting the appropriate La2O3 thickness. The thin La2O3 film was characterized: its chemical composition and crystalline structure were determined by X-ray photoelectron spectroscopy and X-ray diffraction, respectively. La2O3 exhibited good thermal stability after post-deposition annealing at 200, 400 and 600 °C because of its high binding-energy (835.6 eV). Experimental results clearly demonstrated that the La2O3 thin film was thermally stable. The DC and RF characteristics of Pt/La2O3/Ti/Au gate and conventional Pt/Ti/Au gate pHEMTs were examined. The measurements indicated that the transistor with the Pt/La2O3/Ti/Au gate had a higher breakdown voltage and lower gate leakage current. Accordingly, the La2O3 thin film is a potential high-k material for use as a gate dielectric to improve electrical performance and the thermal effect in high-power applications.

  14. Plasma nitridation optimization for sub-15 A gate dielectrics

    NARCIS (Netherlands)

    Cubaynes, F.N; Schmitz, Jurriaan; van der Marel, C.; Snijders, J.H.M.; Veloso, A.; Rothschild, A.; Olsen, C.; Date, L.

    The work investigates the impact of plasma nitridation process parameters upon the physical properties and upon the electrical performance of sub-15 A plasma nitrided gate dielectrics. The nitrogen distribution and chemical bonding of ultra-thin plasma nitrided films have been investigated using

  15. Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for Advanced CMOS Devices

    Directory of Open Access Journals (Sweden)

    Masamichi Suzuki

    2012-03-01

    Full Text Available A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3 high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process.

  16. 2-D modeling and analysis of short-channel behavior of a front high- K gate stack triple-material gate SB SON MOSFET

    Science.gov (United States)

    Banerjee, Pritha; Kumari, Tripty; Sarkar, Subir Kumar

    2018-02-01

    This paper presents the 2-D analytical modeling of a front high- K gate stack triple-material gate Schottky Barrier Silicon-On-Nothing MOSFET. Using the two-dimensional Poisson's equation and considering the popular parabolic potential approximation, expression for surface potential as well as the electric field has been considered. In addition, the response of the proposed device towards aggressive downscaling, that is, its extent of immunity towards the different short-channel effects, has also been considered in this work. The analytical results obtained have been validated using the simulated results obtained using ATLAS, a two-dimensional device simulator from SILVACO.

  17. Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

    Science.gov (United States)

    Choi, Woo Young; Lee, Hyun Kook

    2016-01-01

    The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

  18. Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

    International Nuclear Information System (INIS)

    Ghosh, Bahniman; Mondal, Partha; Akram, M. W.; Bal, Punyasloka; Salimath, Akshay Kumar

    2014-01-01

    We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel. These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n–p–n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability. (semiconductor devices)

  19. GaN-Based High-k Praseodymium Oxide Gate MISFETs with P2S5/(NH42SX + UV Interface Treatment Technology

    Directory of Open Access Journals (Sweden)

    Chao-Wei Lin

    2012-01-01

    Full Text Available This study examines the praseodymium-oxide- (Pr2O3- passivated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs with high dielectric constant in which the AlGaN Schottky layers are treated with P2S5/(NH42SX + ultraviolet (UV illumination. An electron-beam evaporated Pr2O3 insulator is used instead of traditional plasma-assisted chemical vapor deposition (PECVD, in order to prevent plasma-induced damage to the AlGaN. In this work, the HEMTs are pretreated with P2S5/(NH42SX solution and UV illumination before the gate insulator (Pr2O3 is deposited. Since stable sulfur that is bound to the Ga species can be obtained easily and surface oxygen atoms are reduced by the P2S5/(NH42SX pretreatment, the lowest leakage current is observed in MIS-HEMT. Additionally, a low flicker noise and a low surface roughness (0.38 nm are also obtained using this novel process, which demonstrates its ability to reduce the surface states. Low gate leakage current Pr2O3 and high-k AlGaN/GaN MIS-HEMTs, with P2S5/(NH42SX + UV illumination treatment, are suited to low-noise applications, because of the electron-beam-evaporated insulator and the new chemical pretreatment.

  20. Impact and Origin of Interface States in MOS Capacitor with Monolayer MoS2 and HfO2 High-k Dielectric.

    Science.gov (United States)

    Xia, Pengkun; Feng, Xuewei; Ng, Rui Jie; Wang, Shijie; Chi, Dongzhi; Li, Cequn; He, Zhubing; Liu, Xinke; Ang, Kah-Wee

    2017-01-13

    Two-dimensional layered semiconductors such as molybdenum disulfide (MoS 2 ) at the quantum limit are promising material for nanoelectronics and optoelectronics applications. Understanding the interface properties between the atomically thin MoS 2 channel and gate dielectric is fundamentally important for enhancing the carrier transport properties. Here, we investigate the frequency dispersion mechanism in a metal-oxide-semiconductor capacitor (MOSCAP) with a monolayer MoS 2 and an ultra-thin HfO 2 high-k gate dielectric. We show that the existence of sulfur vacancies at the MoS 2 -HfO 2 interface is responsible for the generation of interface states with a density (D it ) reaching ~7.03 × 10 11  cm -2  eV -1 . This is evidenced by a deficit S:Mo ratio of ~1.96 using X-ray photoelectron spectroscopy (XPS) analysis, which deviates from its ideal stoichiometric value. First-principles calculations within the density-functional theory framework further confirms the presence of trap states due to sulfur deficiency, which exist within the MoS 2 bandgap. This corroborates to a voltage-dependent frequency dispersion of ~11.5% at weak accumulation which decreases monotonically to ~9.0% at strong accumulation as the Fermi level moves away from the mid-gap trap states. Further reduction in D it could be achieved by thermally diffusing S atoms to the MoS 2 -HfO 2 interface to annihilate the vacancies. This work provides an insight into the interface properties for enabling the development of MoS 2 devices with carrier transport enhancement.

  1. Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics

    KAUST Repository

    Alshareef, Husam N.

    2010-11-19

    Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.

  2. Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics

    KAUST Repository

    Alshareef, Husam N.; Caraveo-Frescas, J. A.; Cha, D. K.

    2010-01-01

    Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.

  3. SEMICONDUCTOR TECHNOLOGY: Wet etching characteristics of a HfSiON high-k dielectric in HF-based solutions

    Science.gov (United States)

    Yongliang, Li; Qiuxia, Xu

    2010-03-01

    The wet etching properties of a HfSiON high-k dielectric in HF-based solutions are investigated. HF-based solutions are the most promising wet chemistries for the removal of HfSiON, and etch selectivity of HF-based solutions can be improved by the addition of an acid and/or an alcohol to the HF solution. Due to densification during annealing, the etch rate of HfSiON annealed at 900 °C for 30 s is significantly reduced compared with as-deposited HfSiON in HF-based solutions. After the HfSiON film has been completely removed by HF-based solutions, it is not possible to etch the interfacial layer and the etched surface does not have a hydrophobic nature, since N diffuses to the interface layer or Si substrate formation of Si-N bonds that dissolves very slowly in HF-based solutions. Existing Si-N bonds at the interface between the new high-k dielectric deposit and the Si substrate may degrade the carrier mobility due to Coulomb scattering. In addition, we show that N2 plasma treatment before wet etching is not very effective in increasing the wet etch rate for a thin HfSiON film in our case.

  4. Wet etching characteristics of a HfSiON high-k dielectric in HF-based solutions

    International Nuclear Information System (INIS)

    Li Yongliang; Xu Qiuxia

    2010-01-01

    The wet etching properties of a HfSiON high-k dielectric in HF-based solutions are investigated. HF-based solutions are the most promising wet chemistries for the removal of HfSiON, and etch selectivity of HF-based solutions can be improved by the addition of an acid and/or an alcohol to the HF solution. Due to densification during annealing, the etch rate of HfSiON annealed at 900 0 C for 30 s is significantly reduced compared with as-deposited HfSiON in HF-based solutions. After the HfSiON film has been completely removed by HF-based solutions, it is not possible to etch the interfacial layer and the etched surface does not have a hydrophobic nature, since N diffuses to the interface layer or Si substrate formation of Si-N bonds that dissolves very slowly in HF-based solutions. Existing Si-N bonds at the interface between the new high-k dielectric deposit and the Si substrate may degrade the carrier mobility due to Coulomb scattering. In addition, we show that N 2 plasma treatment before wet etching is not very effective in increasing the wet etch rate for a thin HfSiON film in our case. (semiconductor technology)

  5. Ternary rare-earth based alternative gate-dielectrics for future integration in MOSFETs

    Energy Technology Data Exchange (ETDEWEB)

    Schubert, Juergen; Lopes, Joao Marcelo; Durgun Oezben, Eylem; Luptak, Roman; Lenk, Steffi; Zander, Willi; Roeckerath, Martin [IBN 1-IT, Forschungszentrum Juelich, 52425 Juelich (Germany)

    2009-07-01

    The dielectric SiO{sub 2} has been the key to the tremendous improvements in Si-based metal-oxide-semiconductor (MOS) device performance over the past four decades. It has, however, reached its limit in terms of scaling since it exhibits a leakage current density higher than 1 A/cm{sup 2} and does not retain its intrinsic physical properties at thicknesses below 1.5 nm. In order to overcome these problems and keep Moore's law ongoing, the use of higher dielectric constant (k) gate oxides has been suggested. These high-k materials must satisfy numerous requirements such as the high k, low leakage currents, suitable band gap und offsets to silicon. Rare-earth based dielectrics are promising materials which fulfill these needs. We will review the properties of REScO{sub 3} (RE = La, Dy, Gd, Sm, Tb) and LaLuO{sub 3} thin films, grown with pulsed laser deposition, e-gun evaporation or molecular beam deposition, integrated in capacitors and transistors. A k > 20 for the REScO{sub 3} (RE = Dy, Gd) and around 30 for (RE = La, Sm, Tb) and LaLuO{sub 3} are obtained. Transistors prepared on SOI and sSOI show mobility values up to 380 cm{sup 2}/Vs on sSOI, which are comparable to such prepared with HfO{sub 2}.

  6. High-performance pentacene OTFT by incorporating Ti in LaON gate dielectric

    Science.gov (United States)

    Ma, Y. X.; Han, C. Y.; Tang, W. M.; Lai, P. T.

    2017-07-01

    Pentacene organic thin-film transistors (OTFT) using high-k LaTiON gate dielectric with different Ti contents are investigated. The LaxTi(1-x)ON films (with x = 1, 0.87, 0.76, and 0.67) are deposited by reactive sputtering followed by an annealing in N2 at 200 °C. The OTFT with La0.87Ti0.13ON can achieve a high carrier mobility of 2.6 cm2/V.s, a small threshold voltage of -1.5 V, a small sub-threshold swing of 0.07 V/dec, and a small hysteresis of 0.17 V. AFM and X-ray photoelectron spectroscopy reveal that Ti can suppress the hygroscopicity of La oxide to achieve a smoother dielectric surface, which can result in larger pentacene grains and thus higher carrier mobility. All the devices show a clockwise hysteresis because both the LaOH formation and Ti incorporation can generate acceptor-like traps in the gate dielectric.

  7. Atomic layer deposited high-k dielectric on graphene by functionalization through atmospheric plasma treatment

    Science.gov (United States)

    Shin, Jeong Woo; Kang, Myung Hoon; Oh, Seongkook; Yang, Byung Chan; Seong, Kwonil; Ahn, Hyo-Sok; Lee, Tae Hoon; An, Jihwan

    2018-05-01

    Atomic layer-deposited (ALD) dielectric films on graphene usually show noncontinuous and rough morphology owing to the inert surface of graphene. Here, we demonstrate the deposition of thin and uniform ALD ZrO2 films with no seed layer on chemical vapor-deposited graphene functionalized by atmospheric oxygen plasma treatment. Transmission electron microscopy showed that the ALD ZrO2 films were highly crystalline, despite a low ALD temperature of 150 °C. The ALD ZrO2 film served as an effective passivation layer for graphene, which was shown by negative shifts in the Dirac voltage and the enhanced air stability of graphene field-effect transistors after ALD of ZrO2. The ALD ZrO2 film on the functionalized graphene may find use in flexible graphene electronics and biosensors owing to its low process temperature and its capacity to improve device performance and stability.

  8. Nitride passivation of the interface between high-k dielectrics and SiGe

    Energy Technology Data Exchange (ETDEWEB)

    Sardashti, Kasra [Department of Chemistry and Biochemistry, University of California, San Diego, La Jolla, California 92093-0358 (United States); Materials Science and Engineering Program, University of California, San Diego, La Jolla, California 92093-0411 (United States); Hu, Kai-Ting [Department of Chemistry and Biochemistry, University of California, San Diego, La Jolla, California 92093-0358 (United States); Department of Mechanical and Aerospace Engineering, University of California, San Diego, La Jolla, California 92093-0411 (United States); Tang, Kechao; McIntyre, Paul [Department of Materials Science and Engineering, Stanford University, Stanford, California 94305 (United States); Madisetti, Shailesh; Oktyabrsky, Serge [Colleges of Nanoscale Science and Engineering, SUNY Polytechnic Institute, Albany, New York 12222 (United States); Siddiqui, Shariq; Sahu, Bhagawan [TD Research, GLOBALFOUNDRIES US, Inc., Albany, New York 12203 (United States); Yoshida, Naomi; Kachian, Jessica; Dong, Lin [Applied Materials, Inc., Santa Clara, California 95054 (United States); Fruhberger, Bernd [California Institute for Telecommunications and Information Technology, University of California San Diego, La Jolla, California 92093-0436 (United States); Kummel, Andrew C., E-mail: akummel@ucsd.edu [Department of Chemistry and Biochemistry, University of California, San Diego, La Jolla, California 92093-0358 (United States)

    2016-01-04

    In-situ direct ammonia (NH{sub 3}) plasma nitridation has been used to passivate the Al{sub 2}O{sub 3}/SiGe interfaces with Si nitride and oxynitride. X-ray photoelectron spectroscopy of the buried Al{sub 2}O{sub 3}/SiGe interface shows that NH{sub 3} plasma pre-treatment should be performed at high temperatures (300 °C) to fully prevent Ge nitride and oxynitride formation at the interface and Ge out-diffusion into the oxide. C-V and I-V spectroscopy results show a lower density of interface traps and smaller gate leakage for samples with plasma nitridation at 300 °C.

  9. Chemical vapor deposited monolayer MoS2 top-gate MOSFET with atomic-layer-deposited ZrO2 as gate dielectric

    Science.gov (United States)

    Hu, Yaoqiao; Jiang, Huaxing; Lau, Kei May; Li, Qiang

    2018-04-01

    For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec-1, and a field-effect electron mobility of 12.1 cm2 V-1 s-1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm-1 at V DS = 5 V. The gate leakage current is below 10-2 A cm-2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm-1 is obtained. Gate hysteresis and frequency-dependent capacitance-voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ˜3 × 1012 cm-2 eV-1.

  10. Electrical properties of nano-resistors made from the Zr-doped HfO2 high-k dielectric film

    Science.gov (United States)

    Zhang, Shumao; Kuo, Yue

    2018-03-01

    Electrical properties of nano-sized resistors made from the breakdown of the metal-oxide-semiconductor capacitor composed of the amorphous high-k gate dielectric have been investigated under different stress voltages and temperatures. The effective resistance of nano-resistors in the device was estimated from the I-V curve in the high voltage range. It decreased with the increase of the number of resistors. The resistance showed complicated temperature dependence, i.e. it neither behaves like a conductor nor a semiconductor. In the low voltage operation range, the charge transfer was controlled by the Schottky barrier at the nano-resistor/Si interface. The barrier height decreased with the increase of stress voltage, which was probably caused by the change of the nano-resistor composition. Separately, it was observed that the barrier height was dependent on the temperature, which was probably due to the dynamic nano-resistor formation process and the inhomogeneous barrier height distribution. The unique electrical characteristics of this new type of nano-resistors are important for many electronic and optoelectronic applications.

  11. Silicate formation at the interface of Pr-oxide as a high-K dielectric and Si(001) surfaces

    International Nuclear Information System (INIS)

    Schmeisser, D.; Zheng, F.; Perez-Dieste, V.; Himpsel, F.J.; LoNigro, R.; Toro, R.G.; Malandrino, G.; Fragala, I.L.

    2006-01-01

    The composition and chemical bonding of the first atoms across the interface between Si(001) and the dielectric determine the quality of dielectric gate stacks. An analysis of that hidden interface is a challenge as it requires both, high sensitivity and elemental and chemical state information. We used X-ray absorption spectroscopy in total electron yield and total fluorescence yield at the Si2p and the O1s edges to address that issue. We report on results of Pr 2 O 3 /Si(001) as prepared by both, epitaxial growth and metal organic chemical vapor deposition (MOCVD), and compare to the SiO 2 /Si(001) system as a reference. We find evidence for the silicate formation at the interface as derived from the characteristic features at the Si2p and the O1s edges. The results are in line with model experiments in which films of increasing film thickness are deposited in situ on bare Si(001) surfaces

  12. Carbon nanotube transistors with graphene oxide films as gate dielectrics

    Institute of Scientific and Technical Information of China (English)

    2010-01-01

    Carbon nanomaterials,including the one-dimensional(1-D) carbon nanotube(CNT) and two-dimensional(2-D) graphene,are heralded as ideal candidates for next generation nanoelectronics.An essential component for the development of advanced nanoelectronics devices is processing-compatible oxide.Here,in analogy to the widespread use of silicon dioxide(SiO2) in silicon microelectronic industry,we report the proof-of-principle use of graphite oxide(GO) as a gate dielectrics for CNT field-effect transistor(FET) via a fast and simple solution-based processing in the ambient condition.The exceptional transistor characteristics,including low operation voltage(2 V),high carrier mobility(950 cm2/V-1 s-1),and the negligible gate hysteresis,suggest a potential route to the future all-carbon nanoelectronics.

  13. Comparative studies of AlGaN/GaN MOS-HEMTs with stacked gate dielectrics by the mixed thin film growth method

    International Nuclear Information System (INIS)

    Chou, Bo-Yi; Hsu, Wei-Chou; Liu, Han-Yin; Ho, Chiu-Sheng; Lee, Ching-Sung

    2013-01-01

    This paper reports Al 0.27 Ga 0.73 N/GaN metal–oxide–semiconductor high electron mobility transistors (MOS-HEMTs) with stacked Al 2 O 3 /HfO 2 gate dielectrics by using hydrogen peroxideoxidation/sputtering techniques. The Al 2 O 3 employed as a gate dielectric and surface passivation layer effectively suppresses the gate leakage current, improves RF drain current collapse and exhibits good thermal stability. Moreover, by stacking the good insulating high-k HfO 2 dielectric further suppresses the gate leakage, enhances the dielectric breakdown field and power-added efficiency, and decreases the equivalent oxide thickness. The present MOS-HEMT design has demonstrated superior improvements of 10.1% (16.4%) in the maximum drain–source current (I DS,max ), 11.4% (22.5%) in the gate voltage swing and 12.5%/14.4% (21.9%/22.3%) in the two-terminal gate–drain breakdown/turn-on voltages (BV GD /V ON ), and the present design also demonstrates the lowest gate leakage current and best thermal stability characteristics as compared to two reference MOS-HEMTs with a single Al 2 O 3 /(HfO 2 ) dielectric layer of the same physical thickness. (invited paper)

  14. Low-Temperature Solution-Processed Gate Dielectrics for High-Performance Organic Thin Film Transistors

    Directory of Open Access Journals (Sweden)

    Jaekyun Kim

    2015-10-01

    Full Text Available A low-temperature solution-processed high-k gate dielectric layer for use in a high-performance solution-processed semiconducting polymer organic thin-film transistor (OTFT was demonstrated. Photochemical activation of sol-gel-derived AlOx films under 150 °C permitted the formation of a dense film with low leakage and relatively high dielectric-permittivity characteristics, which are almost comparable to the results yielded by the conventionally used vacuum deposition and high temperature annealing method. Octadecylphosphonic acid (ODPA self-assembled monolayer (SAM treatment of the AlOx was employed in order to realize high-performance (>0.4 cm2/Vs saturation mobility and low-operation-voltage (<5 V diketopyrrolopyrrole (DPP-based OTFTs on an ultra-thin polyimide film (3-μm thick. Thus, low-temperature photochemically-annealed solution-processed AlOx film with SAM layer is an attractive candidate as a dielectric-layer for use in high-performance organic TFTs operated at low voltages.

  15. Broadening of Distribution of Trap States in PbS Quantum Dot Field-Effect Transistors with High-k Dielectrics.

    Science.gov (United States)

    Nugraha, Mohamad I; Häusermann, Roger; Watanabe, Shun; Matsui, Hiroyuki; Sytnyk, Mykhailo; Heiss, Wolfgang; Takeya, Jun; Loi, Maria A

    2017-02-08

    We perform a quantitative analysis of the trap density of states (trap DOS) in PbS quantum dot field-effect transistors (QD-FETs), which utilize several polymer gate insulators with a wide range of dielectric constants. With increasing gate dielectric constant, we observe increasing trap DOS close to the lowest unoccupied molecular orbital (LUMO) of the QDs. In addition, this increase is also consistently followed by broadening of the trap DOS. We rationalize that the increase and broadening of the spectral trap distribution originate from dipolar disorder as well as polaronic interactions, which are appearing at strong dielectric polarization. Interestingly, the increased polaron-induced traps do not show any negative effect on the charge carrier mobility in our QD devices at the highest applied gate voltage, giving the possibility to fabricate efficient low-voltage QD devices without suppressing carrier transport.

  16. Transfer-Free Fabrication of Graphene Scaffolds on High-k Dielectrics from Metal-Organic Oligomers.

    Science.gov (United States)

    Pang, Qingqing; Wang, Deyan; Wang, Xiuyan; Feng, Shaoguang; Clark, Michael B; Li, Qiaowei

    2016-09-28

    In situ fabrication of graphene scaffold-ZrO2 nanofilms is achieved by thermal annealing of Zr-based metal-organic oligomers on SiO2 substrates. The structural similarities of the aromatic moieties in the ligand (phenyl-, naphthyl-, anthryl-, and pyrenyl-) compared to graphene play a major role in the ordering of the graphene scaffolds obtained. The depth profiling analysis reveals ultrathin carbon-pure or carbon-rich surfaces of the graphene scaffold-ZrO2 nanofilms. The graphene scaffolds with ∼96.0% transmittance in the visible region and 4.8 nm in thickness can be grown with this non-chemical vapor deposition method. Furthermore, the heterogeneous graphene scaffold-ZrO2 nanofilms show a low sheet resistance of 17.0 kΩ per square, corresponding to electrical conductivity of 3197 S m(-1). The strategy provides a facile method to fabricate graphene scaffolds directly on high-k dielectrics without transferring process, paving the way for its application in fabricating electronic devices.

  17. Conduction band-edge d-states in high-k dielectrics due to Jahn-Teller term splittings

    International Nuclear Information System (INIS)

    Lucovsky, G.; Fulton, C.C.; Zhang, Y.; Luning, J.; Edge, L.; Whitten, J.L.; Nemanich, R.J.; Schlom, D.G.; Afanase'v, V.V.

    2005-01-01

    X-ray absorption spectroscopy (XAS) is used to study conduction band edge electronic structure of high-k transition metal (TM) and trivalent lanthanide series rare earth (RE) oxide dielectrics. Empty TM/RE d-states are studied by intra-atomic transitions originating in core level spin-orbit split p-states, and conduction band states are studied in inter-atomic transitions which originate in the oxygen atom 1s core level state. In non-crystalline Zr and Hf silicate alloys, the local bonding symmetry, or crystal field splits these d-states into doubly and triply degenerate features. In nano-crystalline oxides, there are additional d-state splittings due to contributions of more distant neighbors that completely remove d-state degeneracies via the Jahn-Teller effect mechanism. This gives rise to highly localized band edge states that are electronically active in photoconductivity, internal photoemission, and act as bulk traps in metal oxide semiconductor (MOS) devices

  18. Comprehensive study and design of scaled metal/high-k/Ge gate stacks with ultrathin aluminum oxide interlayers

    Energy Technology Data Exchange (ETDEWEB)

    Asahara, Ryohei; Hideshima, Iori; Oka, Hiroshi; Minoura, Yuya; Hosoi, Takuji, E-mail: hosoi@mls.eng.osaka-u.ac.jp; Shimura, Takayoshi; Watanabe, Heiji [Graduate School of Engineering, Osaka University, 2-1 Yamadaoka, Suita, Osaka 565-0871 (Japan); Ogawa, Shingo [Graduate School of Engineering, Osaka University, 2-1 Yamadaoka, Suita, Osaka 565-0871 (Japan); Toray Research Center Inc., 3-3-7 Sonoyama, Otsu, Shiga 520-8567 (Japan); Yoshigoe, Akitaka; Teraoka, Yuden [Japan Atomic Energy Agency, 1-1-1 Kouto, Sayo-cho, Sayo-gun, Hyogo 679-5148 (Japan)

    2015-06-08

    Advanced metal/high-k/Ge gate stacks with a sub-nm equivalent oxide thickness (EOT) and improved interface properties were demonstrated by controlling interface reactions using ultrathin aluminum oxide (AlO{sub x}) interlayers. A step-by-step in situ procedure by deposition of AlO{sub x} and hafnium oxide (HfO{sub x}) layers on Ge and subsequent plasma oxidation was conducted to fabricate Pt/HfO{sub 2}/AlO{sub x}/GeO{sub x}/Ge stacked structures. Comprehensive study by means of physical and electrical characterizations revealed distinct impacts of AlO{sub x} interlayers, plasma oxidation, and metal electrodes serving as capping layers on EOT scaling, improved interface quality, and thermal stability of the stacks. Aggressive EOT scaling down to 0.56 nm and very low interface state density of 2.4 × 10{sup 11 }cm{sup −2}eV{sup −1} with a sub-nm EOT and sufficient thermal stability were achieved by systematic process optimization.

  19. A Review of Nanoscale Channel and Gate Engineered FINFETs for VLSI Mixed Signal Applications Using Zirconium-di-Oxide Dielectrics

    Directory of Open Access Journals (Sweden)

    D.Nirmal

    2014-07-01

    Full Text Available In the past, most of the research and development efforts in the area of CMOS and IC’s are oriented towards reducing the power and increasing the gain of the circuits. While focusing the attention on low power and high gain in the device, the materials of the device also been taken into consideration. In the present technology, Computationally intensive devices with low power dissipation and high gain are becoming a critical application domain. Several factors have contributed to this paradigm shift. The primary driving factor being the increase in scale of integration, the chip has to accommodate smaller and faster transistors than their predecessors. During the last decade semiconductor technology has been led by conventional scaling. Scaling, has been aimed towards higher speed, lower power and higher density of the semiconductor devices. However, as scaling approached its physical limits, it has become more difficult and challenging for fabrication industry. Therefore, tremendous research has been carried out to investigate the alternatives, and this led to the introduction of new Nano materials and concepts to overcome the difficulties in the device fabrications. In order to reduce the leakage current and parasitic capacitance in devices, gate oxide high-k dielectric materials are explored. Among the different high-k materials available the nano size Zirconium dioxide material is suggested as an alternate gate oxide material for devices due to its thermal stability and small grain size of material. To meet the requirements of ITRS roadmap 2012, the Multi gate devices are considered to be one of the most promising technologies for the future microelectronics industry due to its excellent immunity to short channel effects and high value of On current. The double gate or multi gate devices provide a better scalability option due to its excellent immunity to short-channel effects. Here the different high-k materials are replaced in different

  20. Effects of Annealing Time on the Performance of OTFT on Glass with ZrO2 as Gate Dielectric

    Directory of Open Access Journals (Sweden)

    W. M. Tang

    2012-01-01

    Full Text Available Copper phthalocyanine-based organic thin-film transistors (OTFTs with zirconium oxide (ZrO2 as gate dielectric have been fabricated on glass substrates. The gate dielectric is annealed in N2 at different durations (5, 15, 40, and 60 min to investigate the effects of annealing time on the electrical properties of the OTFTs. Experimental results show that the longer the annealing time for the OTFT, the better the performance. Among the devices studied, OTFTs with gate dielectric annealed at 350°C in N2 for 60 min exhibit the best device performance. They have a small threshold voltage of −0.58 V, a low subthreshold slope of 0.8 V/decade, and a low off-state current of 0.73 nA. These characteristics demonstrate that the fabricated device is suitable for low-voltage and low-power operations. When compared with the TFT samples annealed for 5 min, the ones annealed for 60 min have 20% higher mobility and nearly two times smaller the subthreshold slope and off-state current. The extended annealing can effectively reduce the defects in the high-k film and produces a better insulator/organic interface. This results in lower amount of carrier scattering and larger CuPc grains for carrier transport.

  1. Simulation of dual-gate SOI MOSFET with different dielectric layers

    Science.gov (United States)

    Yadav, Jyoti; Chaudhary, R.; Mukhiya, R.; Sharma, R.; Khanna, V. K.

    2016-04-01

    The paper presents the process design and simulation of silicon-on-insulator (SOI)-based dual-gate metal oxide field-effect transistor (DG-MOSFET) stacked with different dielectric layers on the top of gate oxide. A detailed 2D process simulation of SOI-MOSFETs and its electrical characterization has been done using SILVACO® TCAD tool. A variation in transconductance was observed with different dielectric layers, AlN-gate MOSFET having the highest tranconductance value as compared to other three dielectric layers (SiO2, Si3N4 and Al2O3).

  2. Direct deposition of aluminum oxide gate dielectric on graphene channel using nitrogen plasma treatment

    International Nuclear Information System (INIS)

    Lim, Taekyung; Kim, Dongchool; Ju, Sanghyun

    2013-01-01

    Deposition of high-quality dielectric on a graphene channel is an essential technology to overcome structural constraints for the development of nano-electronic devices. In this study, we investigated a method for directly depositing aluminum oxide (Al 2 O 3 ) on a graphene channel through nitrogen plasma treatment. The deposited Al 2 O 3 thin film on graphene demonstrated excellent dielectric properties with negligible charge trapping and de-trapping in the gate insulator. A top-gate-structural graphene transistor was fabricated using Al 2 O 3 as the gate dielectric with nitrogen plasma treatment on graphene channel region, and exhibited p-type transistor characteristics

  3. Controlling Chain Conformations of High-k Fluoropolymer Dielectrics to Enhance Charge Mobilities in Rubrene Single-Crystal Field-Effect Transistors.

    Science.gov (United States)

    Adhikari, Jwala M; Gadinski, Matthew R; Li, Qi; Sun, Kaige G; Reyes-Martinez, Marcos A; Iagodkine, Elissei; Briseno, Alejandro L; Jackson, Thomas N; Wang, Qing; Gomez, Enrique D

    2016-12-01

    A novel photopatternable high-k fluoropolymer, poly(vinylidene fluoride-bromotrifluoroethylene) P(VDF-BTFE), with a dielectric constant (k) between 8 and 11 is demonstrated in thin-film transistors. Crosslinking P(VDF-BTFE) reduces energetic disorder at the dielectric-semiconductor interface by controlling the chain conformations of P(VDF-BTFE), thereby leading to approximately a threefold enhancement in the charge mobility of rubrene single-crystal field-effect transistors. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  4. Sol–gel deposited ceria thin films as gate dielectric for CMOS ...

    Indian Academy of Sciences (India)

    Sol–gel deposited ceria thin films as gate dielectric for CMOS technology. ANIL G KHAIRNAR ... The semiconductor roadmap following Moore's law is responsible for ..... The financial support from University Grants Commi- ssion (UGC), New ...

  5. Self-aligned top-gate InGaZnO thin film transistors using SiO{sub 2}/Al{sub 2}O{sub 3} stack gate dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Rongsheng; Zhou, Wei; Zhang, Meng; Wong, Man; Kwok, Hoi Sing

    2013-12-02

    Self-aligned top-gate amorphous indium–gallium–zinc oxide (a-IGZO) thin film transistors (TFTs) utilizing SiO{sub 2}/Al{sub 2}O{sub 3} stack thin films as gate dielectric are developed in this paper. Due to high quality of the high-k Al{sub 2}O{sub 3} and good interface between active layer and gate dielectric, the resulting a-IGZO TFT exhibits good electrical performance including field-effect mobility of 9 cm{sup 2}/Vs, threshold voltage of 2.2 V, subthreshold swing of 0.2 V/decade, and on/off current ratio of 1 × 10{sup 7}. With scaling down of the channel length, good characteristics are also obtained with a small shift of the threshold voltage and no degradation of subthreshold swing. - Highlights: • Self-aligned top-gate indium–gallium–zinc oxide thin-film transistor is proposed. • SiO{sub 2}/Al{sub 2}O{sub 3} stack gate dielectric is proposed. • The source/drain areas are hydrogen-doped by CHF{sub 3} plasma. • The devices show good electrical performance and scaling down behavior.

  6. High-κ gate dielectrics: Current status and materials properties considerations

    Science.gov (United States)

    Wilk, G. D.; Wallace, R. M.; Anthony, J. M.

    2001-05-01

    Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward successful integration into the expected processing conditions for future CMOS technologies, especially due to their tendency to form at interfaces with Si (e.g. silicates). These pseudobinary systems also thereby enable the use of other high-κ materials by serving as an interfacial high-κ layer. While work is ongoing, much research is still required, as it is clear that any material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

  7. Hysteresis behaviour of low-voltage organic field-effect transistors employing high dielectric constant polymer gate dielectrics

    International Nuclear Information System (INIS)

    Kim, Se Hyun; Yun, Won Min; Kwon, Oh-Kwan; Hong, Kipyo; Yang, Chanwoo; Park, Chan Eon; Choi, Woon-Seop

    2010-01-01

    Here, we report on the fabrication of low-voltage-operating pentacene-based organic field-effect transistors (OFETs) that utilize crosslinked cyanoethylated poly(vinyl alcohol) (CR-V) gate dielectrics. The crosslinked CR-V-based OFET could be operated successfully at low voltages (below 4 V), but abnormal behaviour during device operation, such as uncertainty in the field-effect mobility (μ) and hysteresis, was induced by the slow polarization of moieties embedded in the gate dielectric (e.g. polar functionalities, ionic impurities, water and solvent molecules). In an effort to improve the stability of OFET operation, we measured the dependence of μ and hysteresis on dielectric thickness, CR-V crosslinking conditions and sweep rate of the gate bias. The influence of the CR-V surface properties on μ, hysteresis, and the structural and morphological features of the pentacene layer grown on the gate dielectric was characterized and compared with the properties of pentacene grown on a polystyrene surface.

  8. Performance of organic field effect transistors with high-k gate oxide after application of consecutive bias stress

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Sunwoo; Choi, Changhwan; Lee, Kilbock [Department of Materials Science and Engineering, Hanyang University, Seoul, 133-791 (Korea, Republic of); Cho, Joong Hwee [Department of Embedded Systems Engineering,University of Incheon, Incheon 406-722 (Korea, Republic of); Ko, Ki-Young [Korea Institute of Patent Information, Seoul, 146-8 (Korea, Republic of); Ahn, Jinho, E-mail: jhahn@hanyang.ac.kr [Department of Materials Science and Engineering, Hanyang University, Seoul, 133-791 (Korea, Republic of)

    2012-10-30

    We report the effect of consecutive electrical stress on the performance of organic field effect transistors (OFETs). Sputtered aluminum oxide (Al{sub 2}O{sub 3}) and hafnium oxide (HfO{sub 2}) were used as gate oxide layers. After the electrical stress, the threshold voltage, which strongly depends on bulk defects, was remarkably shifted to the negative direction, while the other performance characteristics of OFETs such as on-current, transconductance and mobility, which are sensitive to interface defects, were slightly decreased. This result implies that the defects in the bulk layer are significantly affected compared to the defects in the interface layer. Thus, it is important to control the defects in the pentacene bulk layer in order to maintain the good reliabilities of pentacene devices. Those defects in HfO{sub 2} gate oxide devices were larger compared to those in Al{sub 2}O{sub 3} gate oxide devices.

  9. High-k 3D-barium titanate foam/phenolphthalein poly(ether sulfone)/cyanate ester composites with frequency-stable dielectric properties and extremely low dielectric loss under reduced concentration of ceramics

    Science.gov (United States)

    Zheng, Longhui; Yuan, Li; Guan, Qingbao; Liang, Guozheng; Gu, Aijuan

    2018-01-01

    Higher dielectric constant, lower dielectric loss and better frequency stability have been the developing trends for high dielectric constant (high-k) materials. Herein, new composites have been developed through building unique structure by using hyperbranched polysiloxane modified 3D-barium titanate foam (BTF) (BTF@HSi) as the functional fillers and phenolphthalein poly(ether sulfone) (cPES)/cyanate ester (CE) blend as the resin matrix. For BTF@HSi/cPES/CE composite with 34.1 vol% BTF, its dielectric constant at 100 Hz is as high as 162 and dielectric loss is only 0.007; moreover, the dielectric properties of BTF@HSi/cPES/CE composites exhibit excellent frequency stability. To reveal the mechanism behind these attractive performances of BTF@HSi/cPES/CE composites, three kinds of composites (BTF/CE, BTF/cPES/CE, BTF@HSi/CE) were prepared, their structure and integrated performances were intensively investigated and compared with those of BTF@HSi/cPES/CE composites. Results show that the surface modification of BTF is good for preparing composites with improved thermal stability; while introducing flexible cPES to CE is beneficial to fabricate composites with good quality through effectively blocking cracks caused by the stress concentration, and then endowing the composites with good dielectric properties at reduced concentration of ceramics.

  10. Graphene/Pentacene Barristor with Ion-Gel Gate Dielectric: Flexible Ambipolar Transistor with High Mobility and On/Off Ratio.

    Science.gov (United States)

    Oh, Gwangtaek; Kim, Jin-Soo; Jeon, Ji Hoon; Won, EunA; Son, Jong Wan; Lee, Duk Hyun; Kim, Cheol Kyeom; Jang, Jingon; Lee, Takhee; Park, Bae Ho

    2015-07-28

    High-quality channel layer is required for next-generation flexible electronic devices. Graphene is a good candidate due to its high carrier mobility and unique ambipolar transport characteristics but typically shows a low on/off ratio caused by gapless band structure. Popularly investigated organic semiconductors, such as pentacene, suffer from poor carrier mobility. Here, we propose a graphene/pentacene channel layer with high-k ion-gel gate dielectric. The graphene/pentacene device shows both high on/off ratio and carrier mobility as well as excellent mechanical flexibility. Most importantly, it reveals ambipolar behaviors and related negative differential resistance, which are controlled by external bias. Therefore, our graphene/pentacene barristor with ion-gel gate dielectric can offer various flexible device applications with high performances.

  11. Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

    Science.gov (United States)

    Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J

    2016-06-09

    Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

  12. Optical properties and thermal stability of LaYbO3 ternary oxide for high-k dielectric application

    Science.gov (United States)

    Su, Wei-tao; Yang, Li; Li, Bin

    2011-01-01

    A new ternary rare oxide dielectric LaYbO3 film had been prepared on silicon wafers and quartz substrates by reactive sputtering method using a La-Yb metal target. A range of analysis techniques was performed to determine the optical band gap, thermal stability, and electrical property of the deposited samples. It was found the band gap of LaYbO3 film was about 5.8 eV. And the crystallization temperature for rapid thermal annealing (20 s) was between 900 and 950 °C. X-ray photoelectron spectroscopy results indicate the formation of the SiO2 and silicate in the interface between silicon wafer and LaYbO3 film. The dielectric constant is about 23 from the calculation of capacitance-voltage curve, which is comparable higher than previously reported La2O3 or Yb2O3 film.

  13. Low operating voltage InGaZnO thin-film transistors based on Al2O3 high-k dielectrics fabricated using pulsed laser deposition

    International Nuclear Information System (INIS)

    Geng, G. Z.; Liu, G. X.; Zhang, Q.; Shan, F. K.; Lee, W. J.; Shin, B. C.; Cho, C. R.

    2014-01-01

    Low-voltage-driven amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) with an Al 2 O 3 dielectric were fabricated on a Si substrate by using pulsed laser deposition. Both Al 2 O 3 and IGZO thin films are amorphous, and the thin films have very smooth surfaces. The Al 2 O 3 gate dielectric exhibits a very low leakage current density of 1.3 x 10 -8 A/cm 2 at 5 V and a high capacitance density of 60.9 nF/cm 2 . The IGZO TFT with a structure of Ni/IGZO/Al 2 O 3 /Si exhibits high performance with a low threshold voltage of 1.18 V, a high field effect mobility of 20.25 cm 2 V -1 s -1 , an ultra small subthreshold swing of 87 mV/decade, and a high on/off current ratio of 3 x 10 7 .

  14. High-k dielectric composites of poly(2-cyanoethyl vinyl ether) and barium titanate for flexible electronics

    Czech Academy of Sciences Publication Activity Database

    Piana, Francesco; Pfleger, Jiří; Jambor, R.; Řičica, T.; Macák, J. M.

    2017-01-01

    Roč. 134, č. 37 (2017), s. 1-10, č. článku 45236. ISSN 0021-8995 R&D Projects: GA TA ČR(CZ) TE01020022; GA MŠk(CZ) LO1507 Institutional support: RVO:61389013 Keywords : composites * dielectric properties * nanocrystals Subject RIV: CG - Electrochemistry OBOR OECD: Electrochemistry (dry cells, batteries, fuel cells, corrosion metals, electrolysis) Impact factor: 1.860, year: 2016

  15. Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance

    Science.gov (United States)

    Anand, Sunny; Sarin, R. K.

    2017-02-01

    In this paper, charge-plasma-based tunnel FET is proposed by employing dual material gate with hetero gate dielectric technique and it is named hetero-dielectric dual material gate doping-less TFET (HD_DMG_DLTFET). It is compared with conventional doping-less TFET (DLTFET) and dual material gate doping-less TFET (DMG_DLTFET) on the basis of analog and RF performance. The HD_DMG_DLTFET provides better ON state current ({I}\\text{ON}=94 μ \\text{A}/μ \\text{m}), {I}\\text{ON}/{I}\\text{OFF}(≈ 1.36× {10}13), \\text{point} (≈ 3\\text{mV}/\\text{dec}) and average subthreshold slope (\\text{AV}-\\text{SS}=40.40 \\text{mV}/\\text{dec}). The proposed device offers low total gate capacitance (C gg) along with higher drive current. However, with a better transconductance (g m) and cut-off frequency (f T), the HD_DMG_DLTFET can be a good candidate for RF circuitry. The early voltage (V EA) and output conductance (g d) are also moderate for the proposed device with comparison to other devices and therefore can be a candidate for analog devices. From all these simulation results and their study, it is observed that HD_DMG_DLTFET has improved analog/RF performance compared to DLTFET and DMG_DLTFET.

  16. Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

    OpenAIRE

    Roeckerath, M.; Lopes, J. M. J.; Durgun Özben, E.; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D.G.

    2010-01-01

    Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of < 1 nA/cm(2). Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated ...

  17. Top-gate dielectric induced doping and scattering of charge carriers in epitaxial graphene

    Science.gov (United States)

    Puls, Conor P.; Staley, Neal E.; Moon, Jeong-Sun; Robinson, Joshua A.; Campbell, Paul M.; Tedesco, Joseph L.; Myers-Ward, Rachael L.; Eddy, Charles R.; Gaskill, D. Kurt; Liu, Ying

    2011-07-01

    We show that an e-gun deposited dielectric impose severe limits on epitaxial graphene-based device performance based on Raman spectroscopy and low-temperature transport measurements. Specifically, we show from studies of epitaxial graphene Hall bars covered by SiO2 that the measured carrier density is strongly inhomogenous and predominantly induced by charged impurities at the grapheme/dielectric interface that limit mobility via Coulomb interactions. Our work emphasizes that material integration of epitaxial graphene and a gate dielectric is the next major road block towards the realization of graphene-based electronics.

  18. Enhanced ZnO Thin-Film Transistor Performance Using Bilayer Gate Dielectrics

    KAUST Repository

    Alshammari, Fwzah Hamud; Nayak, Pradipta K.; Wang, Zhenwei; Alshareef, Husam N.

    2016-01-01

    We report ZnO TFTs using Al2O3/Ta2O5 bilayer gate dielectrics grown by atomic layer deposition. The saturation mobility of single layer Ta2O5 dielectric TFT was 0.1 cm2 V-1 s-1, but increased to 13.3 cm2 V-1 s-1 using Al2O3/Ta2O5 bilayer dielectric with significantly lower leakage current and hysteresis. We show that point defects present in ZnO film, particularly VZn, are the main reason for the poor TFT performance with single layer dielectric, although interfacial roughness scattering effects cannot be ruled out. Our approach combines the high dielectric constant of Ta2O5 and the excellent Al2O3/ZnO interface quality, resulting in improved device performance. © 2016 American Chemical Society.

  19. Enhanced ZnO Thin-Film Transistor Performance Using Bilayer Gate Dielectrics

    KAUST Repository

    Alshammari, Fwzah Hamud

    2016-08-24

    We report ZnO TFTs using Al2O3/Ta2O5 bilayer gate dielectrics grown by atomic layer deposition. The saturation mobility of single layer Ta2O5 dielectric TFT was 0.1 cm2 V-1 s-1, but increased to 13.3 cm2 V-1 s-1 using Al2O3/Ta2O5 bilayer dielectric with significantly lower leakage current and hysteresis. We show that point defects present in ZnO film, particularly VZn, are the main reason for the poor TFT performance with single layer dielectric, although interfacial roughness scattering effects cannot be ruled out. Our approach combines the high dielectric constant of Ta2O5 and the excellent Al2O3/ZnO interface quality, resulting in improved device performance. © 2016 American Chemical Society.

  20. Effect of nanocomposite gate-dielectric properties on pentacene microstructure and field-effect transistor characteristics.

    Science.gov (United States)

    Lee, Wen-Hsi; Wang, Chun-Chieh

    2010-02-01

    In this study, the effect of surface energy and roughness of the nanocomposite gate dielectric on pentacene morphology and electrical properties of pentacene OTFT are reported. Nanoparticles TiO2 were added in the polyimide matrix to form a nanocomposite which has a significantly different surface characteristic from polyimide, leading to a discrepancy in the structural properties of pentacene growth. A growth mode of pentacene deposited on the nanocomposite is proposed to explain successfully the effect of surface properties of nanocomposite gate dielectric such as surface energy and roughness on the pentacene morphology and electrical properties of OTFT. To obtain the lower surface energy and smoother surface of nanocomposite gate dielectric that is responsible for the desired crystalline, microstructure of pentacene and electrical properties of device, a bottom contact OTFT-pentacene deposited on the double-layer nanocomposite gate dielectric consisting of top smoothing layer of the neat polyimide and bottom layer of (PI+ nano-TiO2 particles) nanocomposite has been successfully demonstrated to exhibit very promising performance including high current on to off ratio of about 6 x 10(5), threshold voltage of -10 V and moderately high filed mobility of 0.15 cm2V(-1)s(-1).

  1. Gate dielectric strength dependent performance of CNT MOSFET and CNT TFET: A tight binding study

    Directory of Open Access Journals (Sweden)

    Md. Shamim Sarker

    Full Text Available This paper presents a comparative study between CNT MOSFET and CNT TFET taking into account of different dielectric strength of gate oxide materials. Here we have studied the transfer characteristics, on/off current (ION/IOFF ratio and subthreshold slope of the device using Non Equilibrium Greens Function (NEGF formalism in tight binding frameworks. The results are obtained by solving the NEGF and Poisson’s equation self-consistently in NanoTCADViDES environment and found that the ON state performance of CNT MOSFET and CNT TFET have significant dependency on the dielectric strength of the gate oxide materials. The figure of merits of the devices also demonstrates that the CNT TFET is promising for high-speed and low-power logic applications. Keywords: CNT TFET, Subthreshold slop, Barrier width, Conduction band (C.B and Valance band (V.B, Oxide dielectric strength, Tight binding approach

  2. Change in carrier type in high-k gate carbon nanotube field-effect transistors by interface fixed charges

    International Nuclear Information System (INIS)

    Moriyama, N; Ohno, Y; Kitamura, T; Kishimoto, S; Mizutani, T

    2010-01-01

    We study the phenomenon of change in carrier type in carbon nanotube field-effect transistors (CNFETs) caused by the atomic layer deposition (ALD) of a HfO 2 gate insulator. When a HfO 2 layer is deposited on a CNFET, the type of carrier changes from p-type to n-type. The so-obtained n-type device has good performance and stability in air. The conductivity of such a device with a channel length of 0.7 μm is 11% of the quantum conductance 4e 2 /h. The contact resistance for electron current is estimated to be 14 kΩ. The n-type conduction of this CNFET is maintained for more than 100 days. The change in carrier type is attributed to positive fixed charges introduced at the interface between the HfO 2 and SiO 2 layers. We also propose a novel technique to control the type of conduction by utilizing interface fixed charges; this technique is compatible with Si CMOS process technology.

  3. Influence of ultra-thin TiN thickness (1.4 nm and 2.4 nm) on positive bias temperature instability (PBTI) of high-k/metal gate nMOSFETs with gate-last process

    International Nuclear Information System (INIS)

    Qi Lu-Wei; Yang Hong; Ren Shang-Qing; Xu Ye-Feng; Luo Wei-Chun; Xu Hao; Wang Yan-Rong; Tang Bo; Wang Wen-Wu; Yan Jiang; Zhu Hui-Long; Zhao Chao; Chen Da-Peng; Ye Tian-Chun

    2015-01-01

    The positive bias temperature instability (PBTI) degradations of high-k/metal gate (HK/MG) nMOSFETs with thin TiN capping layers (1.4 nm and 2.4 nm) are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI (90 °C, 125 °C, 160 °C) are studied and activation energy (E a ) values (0.13 eV and 0.15 eV) are extracted. Although the equivalent oxide thickness (EOT) values of two TiN thickness values are almost similar (0.85 nm and 0.87 nm), the 2.4-nm TiN one (thicker TiN capping layer) shows better PBTI reliability (13.41% at 0.9 V, 90 °C, 1000 s). This is due to the better interfacial layer/high-k (IL/HK) interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer. (paper)

  4. Comparison of precursors for pulsed metal-organic chemical vapor deposition of HfO2 high-K dielectric thin films

    International Nuclear Information System (INIS)

    Teren, Andrew R.; Thomas, Reji; He, Jiaqing; Ehrhart, Peter

    2005-01-01

    Hafnium oxide films were deposited on Si(100) substrates using pulsed metal-organic chemical vapor deposition (CVD) and evaluated for high-K dielectric applications. Three types of precursors were tested: two oxygenated ones, Hf butoxide-dmae and Hf butoxide-mmp, and an oxygen-free one, Hf diethyl-amide. Depositions were carried out in the temperature range of 350-650 deg. C, yielding different microstructures ranging from amorphous to crystalline, monoclinic, films. The films were compared on the basis of growth rate, phase development, density, interface characteristics, and electrical properties. Some specific features of the pulsed injection technique are considered. For low deposition temperatures the growth rate for the amide precursor was significantly higher than for the mixed butoxide precursors. A thickness-dependent amorphous to crystalline phase transition temperature was found for all precursors. There is an increase of the film density along with the deposition temperature from values as low as 5 g/cm 3 at 350 deg. C to values close to the bulk value of 9.7 g/cm 3 at 550 deg. C. Crystallization is observed in the same temperature range for films of typically 10-20 nm thickness. However, annealing studies show that this density increase is not simply related to the crystallization of the films. Similar electrical properties could be observed for all precursors and the dielectric constant of the films reaches values similar to the best values reported for bulk crystalline HfO 2

  5. Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

    KAUST Repository

    Rojas, Jhonathan Prieto

    2013-02-12

    In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry\\'s most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

  6. Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

    KAUST Repository

    Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa; Sevilla, Galo T.

    2013-01-01

    In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry's most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

  7. Interface Engineering for Atomic Layer Deposited Alumina Gate Dielectric on SiGe Substrates.

    OpenAIRE

    Zhang, L; Guo, Y; Hassan, VV; Tang, K; Foad, MA; Woicik, JC; Pianetta, P; Robertson, John; McIntyre, PC

    2016-01-01

    Optimization of the interface between high-k dielectrics and SiGe substrates is a challenging topic due to the complexity arising from the coexistence of Si and Ge interfacial oxides. Defective high-k/SiGe interfaces limit future applications of SiGe as a channel material for electronic devices. In this paper, we identify the surface layer structure of as-received SiGe and Al2O3/SiGe structures based on soft and hard X-ray photoelectron spectroscopy. As-received SiGe substrates have native Si...

  8. Temperature Effects on a-IGZO Thin Film Transistors Using HfO2 Gate Dielectric Material

    OpenAIRE

    Lin, Yu-Hsien; Chou, Jay-Chi

    2014-01-01

    This study investigated the temperature effect on amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) using hafnium oxide (HfO2) gate dielectric material. HfO2 is an attractive candidate as a high-κ dielectric material for gate oxide because it has great potential to exhibit superior electrical properties with a high drive current. In the process of integrating the gate dielectric and IGZO thin film, postannealing treatment is an essential process for completing the chem...

  9. Pulsed laser deposition of oxide gate dielectrics for pentacene organic field-effect transistors

    International Nuclear Information System (INIS)

    Yaginuma, S.; Yamaguchi, J.; Itaka, K.; Koinuma, H.

    2005-01-01

    We have fabricated Al 2 O 3 , LaAlO 3 (LAO), CaHfO 3 (CHO) and CaZrO 3 (CZO) thin films for the dielectric layers of field-effect transistors (FETs) by pulsed laser deposition (PLD). The films exhibited very smooth surfaces with root-mean-squares (rms) roughnesses of ∼1.3 A as evaluated by using atomic force microscopy (AFM). The breakdown electric fields of Al 2 O 3 , LAO, CHO and CZO films were 7, 6, 10 and 2 MV/cm, respectively. The magnitude of the leak current in each film was low enough to operate FET. We performed a comparative study of pentacene FET fabricated using these oxide dielectrics as gate insulators. High field-effect mobility of 1.4 cm 2 /V s and on/off current ratio of 10 7 were obtained in the pentacene FET using LAO gate insulating film. Use of the LAO films as gate dielectrics has been found to suppress the hysteresis of pentacene FET operations. The LAO films are relevant to the dielectric layer of organic FETs

  10. Device performance of in situ steam generated gate dielectric nitrided by remote plasma nitridation

    International Nuclear Information System (INIS)

    Al-Shareef, H. N.; Karamcheti, A.; Luo, T. Y.; Bersuker, G.; Brown, G. A.; Murto, R. W.; Jackson, M. D.; Huff, H. R.; Kraus, P.; Lopes, D.

    2001-01-01

    In situ steam generated (ISSG) oxides have recently attracted interest for use as gate dielectrics because of their demonstrated reliability improvement over oxides formed by dry oxidation. [G. Minor, G. Xing, H. S. Joo, E. Sanchez, Y. Yokota, C. Chen, D. Lopes, and A. Balakrishna, Electrochem. Soc. Symp. Proc. 99-10, 3 (1999); T. Y. Luo, H. N. Al-Shareef, G. A. Brown, M. Laughery, V. Watt, A. Karamcheti, M. D. Jackson, and H. R. Huff, Proc. SPIE 4181, 220 (2000).] We show in this letter that nitridation of ISSG oxide using a remote plasma decreases the gate leakage current of ISSG oxide by an order of magnitude without significantly degrading transistor performance. In particular, it is shown that the peak normalized transconductance of n-channel devices with an ISSG oxide gate dielectric decreases by only 4% and the normalized drive current by only 3% after remote plasma nitridation (RPN). In addition, it is shown that the reliability of the ISSG oxide exhibits only a small degradation after RPN. These observations suggest that the ISSG/RPN process holds promise for gate dielectric applications. [copyright] 2001 American Institute of Physics

  11. Phosphorus oxide gate dielectric for black phosphorus field effect transistors

    Science.gov (United States)

    Dickerson, W.; Tayari, V.; Fakih, I.; Korinek, A.; Caporali, M.; Serrano-Ruiz, M.; Peruzzini, M.; Heun, S.; Botton, G. A.; Szkopek, T.

    2018-04-01

    The environmental stability of the layered semiconductor black phosphorus (bP) remains a challenge. Passivation of the bP surface with phosphorus oxide, POx, grown by a reactive ion etch with oxygen plasma is known to improve photoluminescence efficiency of exfoliated bP flakes. We apply phosphorus oxide passivation in the fabrication of bP field effect transistors using a gate stack consisting of a POx layer grown by reactive ion etching followed by atomic layer deposition of Al2O3. We observe room temperature top-gate mobilities of 115 cm2 V-1 s-1 in ambient conditions, which we attribute to the low defect density of the bP/POx interface.

  12. Polycrystalline diamond RF MOSFET with MoO3 gate dielectric

    Directory of Open Access Journals (Sweden)

    Zeyang Ren

    2017-12-01

    Full Text Available We report the radio frequency characteristics of the diamond metal-oxide-semiconductor field effect transistor with MoO3 gate dielectric for the first time. The device with 2-μm gate length was fabricated on high quality polycrystalline diamond. The maximum drain current of 150 mA/mm at VGS = -5 V and the maximum transconductance of 27 mS/mm were achieved. The extrinsic cutoff frequency of 1.2 GHz and the maximum oscillation frequency of 1.9 GHz have been measured. The moderate frequency characteristics are attributed to the moderate transconductance limited by the series resistance along the channel. We expect that the frequency characteristics of the device can be improved by increasing the magnitude of gm, or fundamentally decreasing the gate-controlled channel resistance and series resistance along the channel, and down-scaling the gate length.

  13. SiC Power MOSFET with Improved Gate Dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Sbrockey, Nick M. [Structured Materials Industries, Inc., Piscataway, NJ (United States); Tompa, Gary S. [Structured Materials Industries, Inc., Piscataway, NJ (United States); Spencer, Michael G. [Structured Materials Industries, Inc., Piscataway, NJ (United States); Chandrashekhar, Chandra M.V. S. [Structured Materials Industries, Inc., Piscataway, NJ (United States)

    2010-08-23

    In this STTR program, Structured Materials Industries (SMI), and Cornell University are developing novel gate oxide technology, as a critical enabler for silicon carbide (SiC) devices. SiC is a wide bandgap semiconductor material, with many unique properties. SiC devices are ideally suited for high-power, highvoltage, high-frequency, high-temperature and radiation resistant applications. The DOE has expressed interest in developing SiC devices for use in extreme environments, in high energy physics applications and in power generation. The development of transistors based on the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structure will be critical to these applications.

  14. Interface Engineering and Gate Dielectric Engineering for High Performance Ge MOSFETs

    Directory of Open Access Journals (Sweden)

    Jiabao Sun

    2015-01-01

    Full Text Available In recent years, germanium has attracted intensive interests for its promising applications in the microelectronics industry. However, to achieve high performance Ge channel devices, several critical issues still have to be addressed. Amongst them, a high quality gate stack, that is, a low defect interface layer and a dielectric layer, is of crucial importance. In this work, we first review the existing methods of interface engineering and gate dielectric engineering and then in more detail we discuss and compare three promising approaches (i.e., plasma postoxidation, high pressure oxidation, and ozone postoxidation. It has been confirmed that these approaches all can significantly improve the overall performance of the metal-oxide-semiconductor field effect transistor (MOSFET device.

  15. Influence of Gate Dielectrics, Electrodes and Channel Width on OFET Characteristics

    International Nuclear Information System (INIS)

    Liyana, V P; Stephania, A M; Shiju, K; Predeep, P

    2015-01-01

    Organic Field Effect Transistors (OFET) possess wide applications in large area electronics owing to their attractive features like easy fabrication process, light weight, flexibility, cost effectiveness etc. But instability, high operational voltages and low carrier mobility act as inhibitors to commercialization of OFETs and various approaches were tried on a regular basis so as to make it viable. In this work, Poly 3-hexylthiophene-2,5diyl (P3HT) based OFETs with bottom-contact top-gate configuration using Poly vinyl alcohol (PVA) and Poly (methyl methacrylate) (PMMA) as gate dielectrics, aluminium and copper as source-drain electrodes are investigated. An effort is made to compare the effect of these dielectric materials and electrodes on the performance of OFET. Also, an attempt has been made to optimize the channel width of the device. These devices are characterised with mobility (μ), threshold voltage (V T ), on-off ratio (I on /I off ) and their comparative analysis is reported. (paper)

  16. Influence of Gate Dielectrics, Electrodes and Channel Width on OFET Characteristics

    Science.gov (United States)

    Liyana, V. P.; Stephania, A. M.; Shiju, K.; Predeep, P.

    2015-06-01

    Organic Field Effect Transistors (OFET) possess wide applications in large area electronics owing to their attractive features like easy fabrication process, light weight, flexibility, cost effectiveness etc. But instability, high operational voltages and low carrier mobility act as inhibitors to commercialization of OFETs and various approaches were tried on a regular basis so as to make it viable. In this work, Poly 3-hexylthiophene-2,5diyl (P3HT) based OFETs with bottom-contact top-gate configuration using Poly vinyl alcohol (PVA) and Poly (methyl methacrylate) (PMMA) as gate dielectrics, aluminium and copper as source-drain electrodes are investigated. An effort is made to compare the effect of these dielectric materials and electrodes on the performance of OFET. Also, an attempt has been made to optimize the channel width of the device. These devices are characterised with mobility (μ), threshold voltage (VT), on-off ratio (Ion/Ioff) and their comparative analysis is reported.

  17. Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

    Science.gov (United States)

    Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

    2010-01-01

    Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

  18. Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

    International Nuclear Information System (INIS)

    Besleaga, C.; Stan, G.E.; Pintilie, I.; Barquinha, P.; Fortunato, E.; Martins, R.

    2016-01-01

    Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

  19. Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

    Energy Technology Data Exchange (ETDEWEB)

    Besleaga, C.; Stan, G.E.; Pintilie, I. [National Institute of Materials Physics, 405A Atomistilor, 077125 Magurele-Ilfov (Romania); Barquinha, P.; Fortunato, E. [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal); Martins, R., E-mail: rm@uninova.pt [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal)

    2016-08-30

    Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

  20. Effects of Y incorporation in TaON gate dielectric on electrical performance of GaAs metal-oxide-semiconductor capacitor

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Li Ning; Choi, Hoi Wai; Lai, Pui To [Department of Electrical and Electronic Engineering, The University of Hong Kong (China); Xu, Jing Ping [School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan (China)

    2016-09-15

    In this study, GaAs metal-oxide-semiconductor (MOS) capacitors using Y-incorporated TaON as gate dielectric have been investigated. Experimental results show that the sample with a Y/(Y + Ta) atomic ratio of 27.6% exhibits the best device characteristics: high k value (22.9), low interfacestate density (9.0 x 10{sup 11} cm{sup -2} eV{sup -1}), small flatband voltage (1.05 V), small frequency dispersion and low gate leakage current (1.3 x 10{sup -5}A/cm{sup 2} at V{sub fb} + 1 V). These merits should be attributed to the complementary properties of Y{sub 2}O{sub 3} and Ta{sub 2}O{sub 5}:Y can effectively passivate the large amount of oxygen vacancies in Ta{sub 2}O{sub 5}, while the positively-charged oxygen vacancies in Ta{sub 2}O{sub 5} are capable of neutralizing the effects of the negative oxide charges in Y{sub 2}O{sub 3}. This work demonstrates that an appropriate doping of Y content in TaON gate dielectric can effectively improve the electrical performance for GaAs MOS devices. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  1. The memory effect of a pentacene field-effect transistor with a polarizable gate dielectric

    Science.gov (United States)

    Unni, K. N. N.; de Bettignies, Remi; Dabos-Seignon, Sylvie; Nunzi, Jean-Michel

    2004-06-01

    The nonvolatile transistor memory element is an interesting topic in organic electronics. In this case a memory cell consists of only one device where the stored information is written as a gate insulator polarization by a gate voltage pulse and read by the channel conductance control with channel voltage pulse without destruction of the stored information. Therefore such transistor could be the base of non-volatile non-destructively readable computer memory of extremely high density. Also devices with polarizable gate dielectrics can function more effectively in certain circuits. The effective threshold voltage Vt can be brought very close to zero, for applications where the available gate voltage is limited. Resonant and adaptive circuits can be tuned insitu by polarizing the gates. Poly(vinylidene fluoride), PVDF and its copolymer with trifluoroethylene P(VDF-TrFE) are among the best known and most widely used ferroelectric polymers. In this manuscript, we report new results of an organic FET, fabricated with pentacene as the active material and P(VDF-TrFE) as the gate insulator. Application of a writing voltage of -50 V for short duration results in significant change in the threshold voltage and remarkable increase in the drain current. The memory effect is retained over a period of 20 hours.

  2. Label Free Detection of Biomolecules Using Charge-Plasma-Based Gate Underlap Dielectric Modulated Junctionless TFET

    Science.gov (United States)

    Wadhwa, Girish; Raj, Balwinder

    2018-05-01

    Nanoscale devices are emerging as a platform for detecting biomolecules. Various issues were observed during the fabrication process such as random dopant fluctuation and thermal budget. To reduce these issues charge-plasma-based concept is introduced. This paper proposes the implementation of charge-plasma-based gate underlap dielectric modulated junctionless tunnel field effect transistor (DM-JLTFET) for the revelation of biomolecule immobilized in the open cavity gate channel region. In this p+ source and n+ drain regions are introduced by employing different work function over the intrinsic silicon. Also dual material gate architecture is implemented to reduce short channel effect without abandoning any other device characteristic. The sensitivity of biosensor is studied for both the neutral and charge-neutral biomolecules. The effect of device parameters such as channel thickness, cavity length and cavity thickness on drain current have been analyzed through simulations. This paper investigates the performance of charge-plasma-based gate underlap DM-JLTFET for biomolecule sensing applications while varying dielectric constant, charge density at different biasing conditions.

  3. Effect of atomic-arrangement matching on La{sub 2}O{sub 3}/Ge heterostructures for epitaxial high-k-gate-stacks

    Energy Technology Data Exchange (ETDEWEB)

    Kanashima, T., E-mail: kanashima@ee.es.osaka-u.ac.jp; Zenitaka, M.; Kajihara, Y.; Yamada, S.; Hamaya, K. [Graduate School of Engineering Science, Osaka University, Machkaneyama 1-3, Toyonaka, Osaka 560-8531 (Japan); Nohira, H. [Tokyo City University, 1-28-1 Tamazutumi, Setagaya-ku, Tokyo 158-8557 (Japan)

    2015-12-14

    We demonstrate a high-quality La{sub 2}O{sub 3} layer on germanium (Ge) as an epitaxial high-k-gate-insulator, where there is an atomic-arrangement matching condition between La{sub 2}O{sub 3}(001) and Ge(111). Structural analyses reveal that (001)-oriented La{sub 2}O{sub 3} layers were grown epitaxially only when we used Ge(111) despite low growth temperatures less than 300 °C. The permittivity (k) of the La{sub 2}O{sub 3} layer is roughly estimated to be ∼19 from capacitance-voltage (C-V) analyses in Au/La{sub 2}O{sub 3}/Ge structures after post-metallization-annealing treatments, although the C-V curve indicates the presence of carrier traps near the interface. By using X-ray photoelectron spectroscopy analyses, we find that only Ge–O–La bonds are formed at the interface, and the thickness of the equivalent interfacial Ge oxide layer is much smaller than that of GeO{sub 2} monolayer. We discuss a model of the interfacial structure between La{sub 2}O{sub 3} and Ge(111) and comment on the C-V characteristics.

  4. Bio Organic-Semiconductor Field-Effect Transistor (BioFET) Based on Deoxyribonucleic Acid (DNA) Gate Dielectric

    Science.gov (United States)

    2010-03-31

    floating gate devices and metal-insulator-oxide-semiconductor (MIOS) devices. First attempts to use polarizable gate insulators in combination with...bulk of the semiconductor (ii) Due to the polarizable gate dielectric (iii) dipole polarization and (iv)electret effect due to mobile ions in the...characterization was carried out under an argon environment inside the glove box. An Agilent model E5273A with a two source-measurement unit instrument was

  5. GaN MOSHEMT employing HfO2 as a gate dielectric with partially etched barrier

    Science.gov (United States)

    Han, Kefeng; Zhu, Lin

    2017-09-01

    In order to suppress the gate leakage current of a GaN high electron mobility transistor (GaN HEMT), a GaN metal-oxide-semiconductor high electron mobility transistor (MOSHEMT) is proposed, in which a metal-oxide-semiconductor gate with high-dielectric-constant HfO2 as an insulating dielectric is employed to replace the traditional GaN HEMT Schottky gate. A 0.5 μm gate length GaN MOSHEMT was fabricated based on the proposed structure, the {{{Al}}}0.28{{{Ga}}}0.72{{N}} barrier layer is partially etched to produce a higher transconductance without deteriorating the transport characteristics of the two-dimensional electron gas in the channel, the gate dielectric is HfO2 deposited by atomic layer deposition. Current-voltage characteristics and radio frequency characteristics are obtained after device preparation, the maximum current density of the device is 900 mA mm-1, the source-drain breakdown voltage is 75 V, gate current is significantly suppressed and the forward gate voltage swing range is about ten times higher than traditional GaN HEMTs, the GaN MOSHEMT also demonstrates radio frequency characteristics comparable to traditional GaN HEMTs with the same gate length.

  6. Temperature Effects on a-IGZO Thin Film Transistors Using HfO2 Gate Dielectric Material

    Directory of Open Access Journals (Sweden)

    Yu-Hsien Lin

    2014-01-01

    Full Text Available This study investigated the temperature effect on amorphous indium gallium zinc oxide (a-IGZO thin film transistors (TFTs using hafnium oxide (HfO2 gate dielectric material. HfO2 is an attractive candidate as a high-κ dielectric material for gate oxide because it has great potential to exhibit superior electrical properties with a high drive current. In the process of integrating the gate dielectric and IGZO thin film, postannealing treatment is an essential process for completing the chemical reaction of the IGZO thin film and enhancing the gate oxide quality to adjust the electrical characteristics of the TFTs. However, the hafnium atom diffused the IGZO thin film, causing interface roughness because of the stability of the HfO2 dielectric thin film during high-temperature annealing. In this study, the annealing temperature was optimized at 200°C for a HfO2 gate dielectric TFT exhibiting high mobility, a high ION/IOFF ratio, low IOFF current, and excellent subthreshold swing (SS.

  7. Semi-transparent a-IGZO thin-film transistors with polymeric gate dielectric.

    Science.gov (United States)

    Hyung, Gun Woo; Wang, Jian-Xun; Li, Zhao-Hui; Koo, Ja-Ryong; Kwon, Sang Jik; Cho, Eou-Sik; Kim, Young Kwan

    2013-06-01

    We report the fabrication of semi-transparent a-IGZO-based thin-film transistors (TFTs) with crosslinked poly-4-vinylphenol (PVP) gate dielectric layers on PET substrate and thermally-evaporated Al/Ag/Al source and drain (S&D) electrodes, which showed a transmittance of 64% at a 500-nm wavelength and sheet resistance of 16.8 omega/square. The semi-transparent a-IGZO TFTs with a PVP layer exhibited decent saturation mobilities (maximum approximately 5.8 cm2Ns) and on/off current ratios of approximately 10(6).

  8. Electrical Properties of Ultrathin Hf-Ti-O Higher k Gate Dielectric Films and Their Application in ETSOI MOSFET.

    Science.gov (United States)

    Xiong, Yuhua; Chen, Xiaoqiang; Wei, Feng; Du, Jun; Zhao, Hongbin; Tang, Zhaoyun; Tang, Bo; Wang, Wenwu; Yan, Jiang

    2016-12-01

    Ultrathin Hf-Ti-O higher k gate dielectric films (~2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) ~9.4%, low equivalent gate oxide thickness (EOT) of ~0.69 nm and acceptable gate leakage current density of 0.61 A/cm 2 @ (V fb  - 1)V could be obtained. The conduction mechanism through the gate dielectric is dominated by the F-N tunneling in the gate voltage range of -0.5 to -2 V. Under the same physical thickness and process flow, lower EOT and higher I on /I off ratio could be obtained while using Hf-Ti-O as gate dielectric compared with HfO 2 . With Hf-Ti-O as gate dielectric, two ETSOI PMOSFETs with gate width/gate length (W/L) of 0.5 μm/25 nm and 3 μm/40 nm show good performances such as high I on , I on /I off ratio in the magnitude of 10 5 , and peak transconductance, as well as suitable threshold voltage (-0.3~-0.2 V). Particularly, ETSOI PMOSFETs show superior short-channel control capacity with DIBL <82 mV/V and subthreshold swing <70 mV/decade.

  9. High-Mobility 6,13-Bis(triisopropylsilylethynyl) Pentacene Transistors Using Solution-Processed Polysilsesquioxane Gate Dielectric Layers.

    Science.gov (United States)

    Matsuda, Yu; Nakahara, Yoshio; Michiura, Daisuke; Uno, Kazuyuki; Tanaka, Ichiro

    2016-04-01

    Polysilsesquioxane (PSQ) is a low-temperature curable polymer that is compatible with low-cost plastic substrates. We cured PSQ gate dielectric layers by irradiation with ultraviolet light at ~60 °C, and used them for 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) thin film transistors (TFTs). The fabricated TFTs have shown the maximum and average hole mobility of 1.3 and 0.78 ± 0.3 cm2V-1s-1, which are comparable to those of the previously reported transistors using single-crystalline TIPS-pentacene micro-ribbons for their active layers and thermally oxidized SiO2 for their gate dielectric layers. Itis therefore demonstrated that PSQ is a promising polymer gate dielectric material for low-cost organic TFTs.

  10. Properties of zirconium silicate and zirconium-silicon oxynitride high-k dielectric alloys for advanced microelectronic applications: Chemical and electrical characterizations

    Science.gov (United States)

    Ju, Byongsun

    2005-11-01

    As the microelectronic devices are aggressively scaled down to the 1999 International Technology Roadmap, the advanced complementary metal oxide semiconductor (CMOS) is required to increase packing density of ultra-large scale integrated circuits (ULSI). High-k alternative dielectrics can provide the required levels of EOT for device scaling at larger physical thickness, thereby providing a materials pathway for reducing the tunneling current. Zr silicates and its end members (SiO2 and ZrO2) and Zr-Si oxynitride films, (ZrO2)x(Si3N 4)y(SiO2)z, have been deposited using a remote plasma-enhanced chemical vapor deposition (RPECVD) system. After deposition of Zr silicate, the films were exposed to He/N2 plasma to incorporate nitrogen atoms into the surface of films. The amount of incorporated nitrogen atoms was measured by on-line Auger electron spectrometry (AES) as a function of silicate composition and showed its local minimum around the 30% silicate. The effect of nitrogen atoms on capacitance-voltage (C-V) and leakage-voltage (J-V) were also investigated by fabricating metal-oxide-semiconductor (MOS) capacitors. Results suggested that incorporating nitrogen into silicate decreased the leakage current in SiO2-rich silicate, whereas the leakage increased in the middle range of silicate. Zr-Si oxynitride was a pseudo-ternary alloy and no phase separation was detected by x-ray photoelectron spectroscopy (XPS) analysis up to 1100°C annealing. The leakage current of Zr-Si oxynitride films showed two different temperature dependent activation energies, 0.02 eV for low temperature and 0.3 eV for high temperature. Poole-Frenkel emission was the dominant leakage mechanism. Zr silicate alloys with no Si3N4 phase were chemically separated into the SiO2 and ZrO2 phase as annealed above 900°C. While chemical phase separation in Zr silicate films with Si 3N4 phase (Zr-Si oxynitride) were suppressed as increasing the amount of Si3N4 phase due to the narrow bonding network m Si3

  11. Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate

    International Nuclear Information System (INIS)

    Liu, Hsi-Wen; Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Chang, Ting-Chang; Chen, Ching-En; Tseng, Tseung-Yuen; Lin, Chien-Yu; Cheng, Osbert; Huang, Cheng-Tung; Ye, Yi-Han

    2016-01-01

    This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

  12. Direct evaluation of electrical dipole moment and oxygen density ratio at high-k dielectrics/SiO2 interface by X-ray photoelectron spectroscopy analysis

    Science.gov (United States)

    Fujimura, Nobuyuki; Ohta, Akio; Ikeda, Mitsuhisa; Makihara, Katsunori; Miyazaki, Seiichi

    2018-04-01

    The electrical dipole moment at an ultrathin high-k (HfO2, Al2O3, TiO2, Y2O3, and SrO)/SiO2 interface and its correlation with the oxygen density ratio at the interface have been directly evaluated by X-ray photoelectron spectroscopy (XPS) under monochromatized Al Kα radiation. The electrical dipole moment at the high-k/SiO2 interface has been measured from the change in the cut-off energy of secondary photoelectrons. Moreover, the oxygen density ratio at the interface between high-k and SiO2 has been estimated from cation core-line signals, such as Hf 4f, Al 2p, Y 3d, Ti 2p, Sr 3d, and Si 2p. We have experimentally clarified the relationship between the measured electrical dipole moment and the oxygen density ratio at the high-k/SiO2 interface.

  13. Effect of incorporation of nitrogen atoms in Al2O3 gate dielectric of wide-bandgap-semiconductor MOSFET on gate leakage current and negative fixed charge

    Science.gov (United States)

    Kojima, Eiji; Chokawa, Kenta; Shirakawa, Hiroki; Araidai, Masaaki; Hosoi, Takuji; Watanabe, Heiji; Shiraishi, Kenji

    2018-06-01

    We performed first-principle calculations to investigate the effect of incorporation of N atoms into Al2O3 gate dielectrics. Our calculations show that the defect levels generated by VO in Al2O3 are the origin of the stress-induced gate leakage current and that VOVAl complexes in Al2O3 cause negative fixed charge. We revealed that the incorporation of N atoms into Al2O3 eliminates the VO defect levels, reducing the stress-induced gate leakage current. Moreover, this suppresses the formation of negatively charged VOVAl complexes. Therefore, AlON can reduce both stress-induced gate leakage current and negative fixed charge in wide-bandgap-semiconductor MOSFETs.

  14. Effect of gate dielectrics on the performance of p-type Cu2O TFTs processed at room temperature

    KAUST Repository

    Al-Jawhari, Hala A.; Caraveo-Frescas, Jesus Alfonso

    2013-01-01

    /off ratio of around 44, threshold voltage equaling -0.62 V and a sub threshold swing of 1.64 V/dec. These values were obtained at a low operating voltage of -2V. The advantages of using STO as a gate dielectric relative to ATO are discussed. © (2014) Trans

  15. Investigation of Ultraviolet Light Curable Polysilsesquioxane Gate Dielectric Layers for Pentacene Thin Film Transistors.

    Science.gov (United States)

    Shibao, Hideto; Nakahara, Yoshio; Uno, Kazuyuki; Tanaka, Ichiro

    2016-04-01

    Polysilsesquioxane (PSQ) comprising 3-methacryloxypropyl groups was investigated as an ultraviolet (UV)-light curable gate dielectric-material for pentacene thin film transistors (TFTs). The surface of UV-light cured PSQ films was smoother than that of thermally cured ones, and the pentacene layers deposited on the UV-Iight cured PSQ films consisted of larger grains. However, carrier mobility of the TFTs using the UV-light cured PSQ films was lower than that of the TFTs using the thermally cured ones. It was shown that the cross-linker molecules, which were only added to the UV-light cured PSQ films, worked as a major mobility-limiting factor for the TFTs.

  16. Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging?

    Directory of Open Access Journals (Sweden)

    Takashi Ando

    2012-03-01

    Full Text Available Current status and challenges of aggressive equivalent-oxide-thickness (EOT scaling of high-κ gate dielectrics via higher-κ ( > 20 materials and interfacial layer (IL scavenging techniques are reviewed. La-based higher-κ materials show aggressive EOT scaling (0.5–0.8 nm, but with effective workfunction (EWF values suitable only for n-type field-effect-transistor (FET. Further exploration for p-type FET-compatible higher-κ materials is needed. Meanwhile, IL scavenging is a promising approach to extend Hf-based high-κ dielectrics to future nodes. Remote IL scavenging techniques enable EOT scaling below 0.5 nm. Mobility-EOT trends in the literature suggest that short-channel performance improvement is attainable with aggressive EOT scaling via IL scavenging or La-silicate formation. However, extreme IL scaling (e.g., zero-IL is accompanied by loss of EWF control and with severe penalty in reliability. Therefore, highly precise IL thickness control in an ultra-thin IL regime ( < 0.5 nm will be the key technology to satisfy both performance and reliability requirements for future CMOS devices.

  17. Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance

    Science.gov (United States)

    Yadav, Dharmendra Singh; Verma, Abhishek; Sharma, Dheeraj; Tirkey, Sukeshni; Raad, Bhagwan Ram

    2017-11-01

    Tunnel-field-effect-transistor (TFET) has emerged as one of the most prominent devices to replace conventional MOSFET due to its ability to provide sub-threshold slope below 60 mV/decade (SS ≤ 60 mV/decade) and low leakage current. Despite this, TFETs suffer from ambipolar behavior, lower ON-state current, and poor RF performance. To address these issues, we have introduced drain and gate work function engineering with hetero gate dielectric for the first time in charge plasma based doping-less TFET (DL TFET). In this, the usage of dual work functionality over the drain region significantly reduces the ambipolar behavior of the device by varying the energy barrier at drain/channel interface. Whereas, the presence of dual work function at the gate terminal increases the ON-state current (ION). The combined effect of dual work function at the gate and drain electrode results in the increment of ON-state current (ION) and decrement of ambipolar conduction (Iambi) respectively. Furthermore, the incorporation of hetero gate dielectric along with dual work functionality at the drain and gate electrode provides an overall improvement in the performance of the device in terms of reduction in ambipolarity, threshold voltage and sub-threshold slope along with improved ON-state current and high frequency figures of merit.

  18. Medium band gap polymer based solution-processed high-κ composite gate dielectrics for ambipolar OFET

    Science.gov (United States)

    Canımkurbey, Betül; Unay, Hande; Çakırlar, Çiğdem; Büyükköse, Serkan; Çırpan, Ali; Berber, Savas; Altürk Parlak, Elif

    2018-03-01

    The authors present a novel ambipolar organic filed-effect transistors (OFETs) composed of a hybrid dielectric thin film of Ta2O5:PMMA nanocomposite material, and solution processed poly(selenophene, benzotriazole and dialkoxy substituted [1,2-b:4, 5-b‧] dithiophene (P-SBTBDT)-based organic semiconducting material as the active layer of the device. We find that the Ta2O5:PMMA insulator shows n-type conduction character, and its combination with the p-type P-SBTBDT organic semiconductor leads to an ambipolar OFET device. Top-gated OFETs were fabricated on glass substrate consisting of interdigitated ITO electrodes. P-SBTBDT-based material was spin coated on the interdigitated ITO electrodes. Subsequently, a solution processed Ta2O5:PMMA nanocomposite material was spin coated, thereby creating the gate dielectric layer. Finally, as a gate metal, an aluminum layer was deposited by thermal evaporation. The fabricated OFETs exhibited an ambipolar performance with good air-stability, high field-induced current and relatively high electron and hole mobilities although Ta2O5:PMMA nanocomposite films have slightly higher leakage current compared to the pure Ta2O5 films. Dielectric properties of the devices with different ratios of Ta2O5:PMMA were also investigated. The dielectric constant varied between 3.6 and 5.3 at 100 Hz, depending on the Ta2O5:PMMA ratio.

  19. A novel approach for the improvement of electrostatic behaviour of physically doped TFET using plasma formation and shortening of gate electrode with hetero-gate dielectric

    Science.gov (United States)

    Soni, Deepak; Sharma, Dheeraj; Aslam, Mohd.; Yadav, Shivendra

    2018-04-01

    This article presents a new device configuration to enhance current drivability and suppress negative conduction (ambipolar conduction) with improved RF characteristics of physically doped TFET. Here, we used a new approach to get excellent electrical characteristics of hetero-dielectric short gate source electrode TFET (HD-SG SE-TFET) by depositing a metal electrode of 5.93 eV work function over the heavily doped source (P+) region. Deposition of metal electrode induces the plasma (thin layer) of holes under the Si/HfO2 interface due to work function difference of metal and semiconductor. Plasma layer of holes is advantageous to increase abruptness as well as decrease the tunneling barrier at source/channel junction for attaining higher tunneling rate of charge carriers (i.e., electrons), which turns into 86.66 times higher ON-state current compared with the conventional physically doped TFET (C-TFET). Along with metal electrode deposition, gate electrode is under-lapped for inducing asymmetrical concentration of charge carriers in the channel region, which is helpful for widening the tunneling barrier width at the drain/channel interface. Consequently, HD-SG SE-TFET shows suppression of ambipolar behavior with reduction in gate-to-drain capacitance which is beneficial for improvement in RF performance. Furthermore, the effectiveness of hetero-gate dielectric concept has been used for improving the RF performance. Furthermore, reliability of C-TFET and proposed structures has been confirmed in term of linearity.

  20. Low operating voltage n-channel organic field effect transistors using lithium fluoride/PMMA bilayer gate dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Kumar, S.; Dhar, A., E-mail: adhar@phy.iitkgp.ernet.in

    2015-10-15

    Highlights: • Alternative to chemically crosslinking of PMMA to achieve low leakage in provided. • Effect of LiF in reducing gate leakage through the OFET device is studied. • Effect of gate leakage on transistor performance has been investigated. • Low voltage operable and low temperature processed n-channel OFETs were fabricated. - Abstract: We report low temperature processed, low voltage operable n-channel organic field effect transistors (OFETs) using N,N′-Dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C{sub 8}) organic semiconductor and poly(methylmethacrylate) (PMMA)/lithium fluoride (LiF) bilayer gate dielectric. We have studied the role of LiF buffer dielectric in effectively reducing the gate leakage through the device and thus obtaining superior performance in contrast to the single layer PMMA dielectric devices. The bilayer OFET devices had a low threshold voltage (V{sub t}) of the order of 5.3 V. The typical values of saturation electron mobility (μ{sub s}), on/off ratio and inverse sub-threshold slope (S) for the range of devices made were estimated to be 2.8 × 10{sup −3} cm{sup 2}/V s, 385, and 3.8 V/decade respectively. Our work thus provides a potential substitution for much complicated process of chemically crosslinking PMMA to achieve low leakage, high capacitance, and thus low operating voltage OFETs.

  1. Effect of gate dielectrics on the performance of p-type Cu2O TFTs processed at room temperature

    KAUST Repository

    Al-Jawhari, Hala A.

    2013-12-01

    Single-phase Cu2O films with p-type semiconducting properties were successfully deposited by reactive DC magnetron sputtering at room temperature followed by post annealing process at 200°C. Subsequently, such films were used to fabricate bottom gate p-channel Cu2O thin film transistors (TFTs). The effect of using high-κ SrTiO3 (STO) as a gate dielectric on the Cu2O TFT performance was investigated. The results were then compared to our baseline process which uses a 220 nm aluminum titanium oxide (ATO) dielectric deposited on a glass substrate coated with a 200 nm indium tin oxide (ITO) gate electrode. We found that with a 150 nm thick STO, the Cu2O TFTs exhibited a p-type behavior with a field-effect mobility of 0.54 cm2.V-1.s-1, an on/off ratio of around 44, threshold voltage equaling -0.62 V and a sub threshold swing of 1.64 V/dec. These values were obtained at a low operating voltage of -2V. The advantages of using STO as a gate dielectric relative to ATO are discussed. © (2014) Trans Tech Publications, Switzerland.

  2. High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric.

    Science.gov (United States)

    Fujii, Mami N; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

    2015-12-18

    The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices.

  3. High carrier mobility of CoPc wires based field-effect transistors using bi-layer gate dielectric

    Directory of Open Access Journals (Sweden)

    Murali Gedda

    2013-11-01

    Full Text Available Polyvinyl alcohol (PVA and anodized Al2O3 layers were used as bi-layer gate for the fabrication of cobalt phthalocyanine (CoPc wire base field-effect transistors (OFETs. CoPc wires were grown on SiO2 surfaces by organic vapor phase deposition method. These devices exhibit a field-effect carrier mobility (μEF value of 1.11 cm2/Vs. The high carrier mobility for CoPc molecules is attributed to the better capacitive coupling between the channel of CoPc wires and the gate through organic-inorganic dielectric layer. Our measurements also demonstrated the way to determine the thicknesses of the dielectric layers for a better process condition of OFETs.

  4. HfO2 as gate dielectric on Ge: Interfaces and deposition techniques

    International Nuclear Information System (INIS)

    Caymax, M.; Van Elshocht, S.; Houssa, M.; Delabie, A.; Conard, T.; Meuris, M.; Heyns, M.M.; Dimoulas, A.; Spiga, S.; Fanciulli, M.; Seo, J.W.; Goncharova, L.V.

    2006-01-01

    To fabricate MOS gate stacks on Ge, one can choose from a multitude of metal oxides as dielectric material which can be deposited by many chemical or physical vapor deposition techniques. As a few typical examples, we will discuss here the results from atomic layer deposition (ALD), metal organic CVD (MOCVD) and molecular beam deposition (MBD) using HfO 2 /Ge as materials model system. It appears that a completely interface layer free HfO 2 /Ge combination can be made in MBD, but this results in very bad capacitors. The same bad result we find if HfGe y (Hf germanides) are formed like in the case of MOCVD on HF-dipped Ge. A GeO x interfacial layer appears to be indispensable (if no other passivating materials are applied), but the composition of this interfacial layer (as determined by XPS, TOFSIMS and MEIS) is determining for the C/V quality. On the other hand, the presence of Ge in the HfO 2 layer is not the most important factor that can be responsible for poor C/V, although it can still induce bumps in C/V curves, especially in the form of germanates (Hf-O-Ge). We find that most of these interfacial GeO x layers are in fact sub-oxides, and that this could be (part of) the explanation for the high interfacial state densities. In conclusion, we find that the Ge surface preparation is determining for the gate stack quality, but it needs to be adapted to the specific deposition technique

  5. Electrical characterization of ALD HfO2 high-k dielectrics on ( 2 ¯ 01) β-Ga2O3

    Science.gov (United States)

    Shahin, David I.; Tadjer, Marko J.; Wheeler, Virginia D.; Koehler, Andrew D.; Anderson, Travis J.; Eddy, Charles R.; Christou, Aris

    2018-01-01

    The electrical quality of HfO2 dielectrics grown by thermal atomic layer deposition at 175 °C on n-type ( 2 ¯ 01) β-Ga2O3 has been studied through capacitance- and current-voltage measurements on metal-oxide-semiconductor capacitors. These capacitors exhibited excellent electrical characteristics, including dual-sweep capacitance-voltage curves with low hysteresis and stretch-out and a frequency-stable dielectric constant of k˜14 when measured between 10 kHz and 1 MHz. The C-V curves exhibited a uniform and repeatable +1.05 V shift relative to the ideal case when swept from 3.5 to -5 V, yielding positively measured flatband (+2.15 V) and threshold (+1.05 V) voltages that may be useful for normally off n-channel Ga2O3 devices. Using the Terman method, an average interface trap density of 1.3 × 1011 cm-2.eV-1 was obtained between 0.2 and 0.6 eV below the conduction band edge. The forward bias current-voltage characteristic was successfully fitted to the Fowler-Nordheim tunneling model at a field strength of 5 MV/cm, allowing an extraction of a 1.3 eV conduction band offset between HfO2 and Ga2O3, which matches the value previously determined from x-ray photoelectron spectroscopy. However, a temperature dependence in the leakage current was observed. These results suggest that HfO2 is an appealing dielectric for Ga2O3 device applications.

  6. Ambipolar transport in CVD grown MoSe2 monolayer using an ionic liquid gel gate dielectric

    Directory of Open Access Journals (Sweden)

    Deliris N. Ortiz

    2018-03-01

    Full Text Available CVD grown MoSe2 monolayers were electrically characterized at room temperature in a field effect transistor (FET configuration using an ionic liquid (IL as the gate dielectric. During the growth, instead of using MoO3 powder, ammonium heptamolybdate was used for better Mo control of the source and sodium cholate added for lager MoSe2 growth areas. In addition, a high specific capacitance (∼7 μF/cm2 IL was used as the gate dielectric to significantly reduce the operating voltage. The device exhibited ambipolar charge transport at low voltages with enhanced parameters during n- and p-FET operation. IL gating thins the Schottky barrier at the metal/semiconductor interface permitting efficient charge injection into the channel and reduces the effects of contact resistance on device performance. The large specific capacitance of the IL was also responsible for a much higher induced charge density compared to the standard SiO2 dielectric. The device was successfully tested as an inverter with a gain of ∼2. Using a common metal for contacts simplifies fabrication of this ambipolar device, and the possibility of radiative recombination of holes and electrons could further extend its use in low power optoelectronic applications.

  7. Electrical and materials properties of ZrO2 gate dielectrics grown by atomic layer chemical vapor deposition

    Science.gov (United States)

    Perkins, Charles M.; Triplett, Baylor B.; McIntyre, Paul C.; Saraswat, Krishna C.; Haukka, Suvi; Tuominen, Marko

    2001-04-01

    Structural and electrical properties of gate stack structures containing ZrO2 dielectrics were investigated. The ZrO2 films were deposited by atomic layer chemical vapor deposition (ALCVD) after different substrate preparations. The structure, composition, and interfacial characteristics of these gate stacks were examined using cross-sectional transmission electron microscopy and x-ray photoelectron spectroscopy. The ZrO2 films were polycrystalline with either a cubic or tetragonal crystal structure. An amorphous interfacial layer with a moderate dielectric constant formed between the ZrO2 layer and the substrate during ALCVD growth on chemical oxide-terminated silicon. Gate stacks with a measured equivalent oxide thickness (EOT) of 1.3 nm showed leakage values of 10-5 A/cm2 at a bias of -1 V from flatband, which is significantly less than that seen with SiO2 dielectrics of similar EOT. A hysteresis of 8-10 mV was seen for ±2 V sweeps while a midgap interface state density (Dit) of ˜3×1011 states/cm eV was determined from comparisons of measured and ideal capacitance curves.

  8. Design of Higher-k and More Stable Rare Earth Oxides as Gate Dielectrics for Advanced CMOS Devices

    Directory of Open Access Journals (Sweden)

    Yi Zhao

    2012-08-01

    Full Text Available High permittivity (k gate dielectric films are widely studied to substitute SiO2 as gate oxides to suppress the unacceptable gate leakage current when the traditional SiO2 gate oxide becomes ultrathin. For high-k gate oxides, several material properties are dominantly important. The first one, undoubtedly, is permittivity. It has been well studied by many groups in terms of how to obtain a higher permittivity for popular high-k oxides, like HfO2 and La2O3. The second one is crystallization behavior. Although it’s still under the debate whether an amorphous film is definitely better than ploy-crystallized oxide film as a gate oxide upon considering the crystal boundaries induced leakage current, the crystallization behavior should be well understood for a high-k gate oxide because it could also, to some degree, determine the permittivity of the high-k oxide. Finally, some high-k gate oxides, especially rare earth oxides (like La2O3, are not stable in air and very hygroscopic, forming hydroxide. This topic has been well investigated in over the years and significant progresses have been achieved. In this paper, I will intensively review the most recent progresses of the experimental and theoretical studies for preparing higher-k and more stable, in terms of hygroscopic tolerance and crystallization behavior, Hf- and La-based ternary high-k gate oxides.

  9. Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

    Energy Technology Data Exchange (ETDEWEB)

    Tari, Alireza, E-mail: atari@uwaterloo.ca; Lee, Czang-Ho; Wong, William S. [Department of Electrical and Computer Engineering, University of Waterloo, 200 University Avenue West, Waterloo, Ontario N2L 3G1 (Canada)

    2015-07-13

    Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer into the IGZO and resulted in higher resistivity films.

  10. Palladium Gate All Around - Hetero Dielectric -Tunnel FET based highly sensitive Hydrogen Gas Sensor

    Science.gov (United States)

    Madan, Jaya; Chaujar, Rishu

    2016-12-01

    The paper presents a novel highly sensitive Hetero-Dielectric-Gate All Around Tunneling FET (HD-GAA-TFET) based Hydrogen Gas Sensor, incorporating the advantages of band to band tunneling (BTBT) mechanism. Here, the Palladium supported silicon dioxide is used as a sensing media and sensing relies on the interaction of hydrogen with Palladium-SiO2-Si. The high surface to volume ratio in the case of cylindrical GAA structure enhances the fortuities for surface reactions between H2 gas and Pd, and thus improves the sensitivity and stability of the sensor. Behaviour of the sensor in presence of hydrogen and at elevated temperatures is discussed. The conduction path of the sensor which is dependent on sensors radius has also been varied for the optimized sensitivity and static performance analysis of the sensor where the proposed design exhibits a superior performance in terms of threshold voltage, subthreshold swing, and band to band tunneling rate. Stability of the sensor with respect to temperature affectability has also been studied, and it is found that the device is reasonably stable and highly sensitive over the bearable temperature range. The successful utilization of HD-GAA-TFET in gas sensors may open a new door for the development of novel nanostructure gas sensing devices.

  11. Modeling of Dual Gate Material Hetero-dielectric Strained PNPN TFET for Improved ON Current

    Science.gov (United States)

    Kumari, Tripty; Saha, Priyanka; Dash, Dinesh Kumar; Sarkar, Subir Kumar

    2018-01-01

    The tunnel field effect transistor (TFET) is considered to be a promising alternative device for future low-power VLSI circuits due to its steep subthreshold slope, low leakage current and its efficient performance at low supply voltage. However, the main challenging issue associated with realizing TFET for wide scale applications is its low ON current. To overcome this, a dual gate material with the concept of dielectric engineering has been incorporated into conventional TFET structure to tune the tunneling width at source-channel interface allowing significant flow of carriers. In addition to this, N+ pocket is implanted at source-channel junction of the proposed structure and the effect of strain is added for exploring the performance of the model in nanoscale regime. All these added features upgrade the device characteristics leading to higher ON current, low leakage and low threshold voltage. The present work derives the surface potential, electric field expression and drain current by solving 2D Poisson's equation at different boundary conditions. A comparative analysis of proposed model with conventional TFET has been done to establish the superiority of the proposed structure. All analytical results have been compared with the results obtained in SILVACO ATLAS device simulator to establish the accuracy of the derived analytical model.

  12. Dry etching of MgCaO gate dielectric and passivation layers on GaN

    International Nuclear Information System (INIS)

    Hlad, M.; Voss, L.; Gila, B.P.; Abernathy, C.R.; Pearton, S.J.; Ren, F.

    2006-01-01

    MgCaO films grown by rf plasma-assisted molecular beam epitaxy and capped with Sc 2 O 3 are promising candidates as surface passivation layers and gate dielectrics on GaN-based high electron mobility transistors (HEMTs) and metal-oxide semiconductor HEMTs (MOS-HEMTs), respectively. Two different plasma chemistries were examined for etching these thin films on GaN. Inductively coupled plasmas of CH 4 /H 2 /Ar produced etch rates only in the range 20-70 A/min, comparable to the Ar sputter rates under the same conditions. Similarly slow MgCaO etch rates (∼100 A/min) were obtained with Cl 2 /Ar discharges under the same conditions, but GaN showed rates almost an order of magnitude higher. The MgCaO removal rates are limited by the low volatilities of the respective etch products. The CH 4 /H 2 /Ar plasma chemistry produced a selectivity of around 2 for etching the MgCaO with respect to GaN

  13. Electrical and materials properties of AlN/ HfO{sub 2} high-k stack with a metal gate

    Energy Technology Data Exchange (ETDEWEB)

    Reid, Kimberly G. [Tokyo Electron U.S., 14338 FM 1826, Austin, TX 78737 (United States)], E-mail: kim@ireid.com; Dip, Anthony [Tokyo Electron U.S., 2400 Grove Blvd., Austin, TX 78747 (United States)], E-mail: anthony.dip@us.tel.com; Sasaki, Sadao [Tokyo Electron U.S. (United States)], E-mail: Sadao.sasaki@us.tel.com; Triyoso, Dina [Freescale Semiconductor Inc., 3501 Ed Bluestein Blvd, Austin, TX 78721 (United States)], E-mail: Dina.Triyoso@freescale.com; Samavedam, Sri [Freescale Semiconductor Inc., 3501 Ed Bluestein Blvd, Austin, TX 78721 (United States)], E-mail: Sri.Samavedam@freescale.com; Gilmer, David [SEMATECH 2706 Montopolis Drive, Austin, TX 78741 (United States)], E-mail: David.Gilmer@sematech.org; Gondran, Carolyn F.H. [Process Characterization Laboratory, ATDF/SEMATECH, 2706 Montopolis Drive, Austin, Texas 78741 (United States)], E-mail: Carolyn.Gondran@atdf.com

    2009-02-27

    In this study, aluminum nitride (AlN) was grown by molecular layer deposition on HfO{sub 2} that had been deposited on 200 mm Si (100) substrates. The AlN was grown on HfO{sub 2} using sequential exposures of trimethyl-aluminum and ammonia (NH{sub 3}) in a batch vertical furnace. Excellent thickness uniformity on test wafers from the top of the furnace to the bottom of the furnace (across the furnace load) was obtained. The equivalent oxide thickness was 16.5-18.8 A for the AlN/HfO{sub 2} stack on patterned device wafers with a molybdenum oxynitride metal gate with leakage current densities from low 10{sup -5} to mid 10{sup -6} A/cm{sup 2} at threshold voltage minus one volt. There was no change in the work function with the AlN cap on HfO{sub 2} with the MoN metal gate, even with a 1000 deg. C anneal.

  14. AlGaN/GaN MISHEMTs with AlN gate dielectric grown by thermal ALD technique.

    Science.gov (United States)

    Liu, Xiao-Yong; Zhao, Sheng-Xun; Zhang, Lin-Qing; Huang, Hong-Fan; Shi, Jin-Shan; Zhang, Chun-Min; Lu, Hong-Liang; Wang, Peng-Fei; Zhang, David Wei

    2015-01-01

    Recently, AlN plasma-enhanced atomic layer deposition (ALD) passivation technique had been proposed and investigated for suppressing the dynamic on-resistance degradation behavior of high-electron-mobility transistors (HEMTs). In this paper, a novel gate dielectric and passivation technique for GaN-on-Si AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMTs) is presented. This technique features the AlN thin film grown by thermal ALD at 400°C without plasma enhancement. A 10.6-nm AlN thin film was grown upon the surface of the HEMT serving as the gate dielectric under the gate electrode and as the passivation layer in the access region at the same time. The MISHEMTs with thermal ALD AlN exhibit enhanced on/off ratio, reduced channel sheet resistance, reduction of gate leakage by three orders of magnitude at a bias of 4 V, reduced threshold voltage hysteresis of 60 mV, and suppressed current collapse degradation.

  15. AlN and Al oxy-nitride gate dielectrics for reliable gate stacks on Ge and InGaAs channels

    Energy Technology Data Exchange (ETDEWEB)

    Guo, Y.; Li, H.; Robertson, J. [Engineering Department, Cambridge University, Cambridge CB2 1PZ (United Kingdom)

    2016-05-28

    AlN and Al oxy-nitride dielectric layers are proposed instead of Al{sub 2}O{sub 3} as a component of the gate dielectric stacks on higher mobility channels in metal oxide field effect transistors to improve their positive bias stress instability reliability. It is calculated that the gap states of nitrogen vacancies in AlN lie further away in energy from the semiconductor band gap than those of oxygen vacancies in Al{sub 2}O{sub 3}, and thus AlN might be less susceptible to charge trapping and have a better reliability performance. The unfavourable defect energy level distribution in amorphous Al{sub 2}O{sub 3} is attributed to its larger coordination disorder compared to the more symmetrically bonded AlN. Al oxy-nitride is also predicted to have less tendency for charge trapping.

  16. Interfacial Cation-Defect Charge Dipoles in Stacked TiO2/Al2O3 Gate Dielectrics.

    Science.gov (United States)

    Zhang, Liangliang; Janotti, Anderson; Meng, Andrew C; Tang, Kechao; Van de Walle, Chris G; McIntyre, Paul C

    2018-02-14

    Layered atomic-layer-deposited and forming-gas-annealed TiO 2 /Al 2 O 3 dielectric stacks, with the Al 2 O 3 layer interposed between the TiO 2 and a p-type germanium substrate, are found to exhibit a significant interface charge dipole that causes a ∼-0.2 V shift of the flat-band voltage and suppresses the leakage current density for gate injection of electrons. These effects can be eliminated by the formation of a trilayer dielectric stack, consistent with the cancellation of one TiO 2 /Al 2 O 3 interface dipole by the addition of another dipole of opposite sign. Density functional theory calculations indicate that the observed interface-dependent properties of TiO 2 /Al 2 O 3 dielectric stacks are consistent in sign and magnitude with the predicted behavior of Al Ti and Ti Al point-defect dipoles produced by local intermixing of the Al 2 O 3 /TiO 2 layers across the interface. Evidence for such intermixing is found in both electrical and physical characterization of the gate stacks.

  17. Influence of gate dielectric on the ambipolar characteristics of solution-processed organic field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Ribierre, J C; Ghosh, S; Takaishi, K; Muto, T; Aoyama, T, E-mail: jcribierre@ewha.ac.kr, E-mail: taoyama@riken.jp [Advanced Science Institute, RIKEN, 2-1 Hirosawa, Wako, Saitama 351-0198 (Japan)

    2011-05-25

    Solution-processed ambipolar organic field-effect transistors based on dicyanomethylene-substituted quinoidal quaterthiophene derivative [QQT(CN)4] are fabricated using various gate dielectric materials including cross-linked polyimide and poly-4-vinylphenol. Devices with spin-coated polymeric gate dielectric layers show a reduced hysteresis in their transfer characteristics. Among the insulating polymers examined in this study, a new fluorinated polymer with a low dielectric constant of 2.8 significantly improves both hole and electron field-effect mobilities of QQT(CN)4 thin films to values as high as 0.04 and 0.002 cm{sup 2} V{sup -1} s{sup -1}. These values are close to the best mobilities obtained in QQT(CN)4 devices fabricated on SiO{sub 2} treated with octadecyltrichlorosilane. The influence of the metal used for source/drain metal electrodes on the device performance is also investigated. Whereas best device performances are achieved with gold electrodes, more balanced electron and hole field-effect mobilities could be obtained using chromium.

  18. Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

    Science.gov (United States)

    Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

    2018-01-01

    Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

  19. Low operating voltage InGaZnO thin-film transistors based on Al{sub 2}O{sub 3} high-k dielectrics fabricated using pulsed laser deposition

    Energy Technology Data Exchange (ETDEWEB)

    Geng, G. Z.; Liu, G. X.; Zhang, Q.; Shan, F. K. [Qingdao University, Qingdao (China); DongEui University, Busan (Korea, Republic of); Lee, W. J.; Shin, B. C. [DongEui University, Busan (Korea, Republic of); Cho, C. R. [Pusan National University, Busan (Korea, Republic of)

    2014-05-15

    Low-voltage-driven amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) with an Al{sub 2}O{sub 3} dielectric were fabricated on a Si substrate by using pulsed laser deposition. Both Al{sub 2}O{sub 3} and IGZO thin films are amorphous, and the thin films have very smooth surfaces. The Al{sub 2}O{sub 3} gate dielectric exhibits a very low leakage current density of 1.3 x 10{sup -8} A/cm{sup 2} at 5 V and a high capacitance density of 60.9 nF/cm{sup 2}. The IGZO TFT with a structure of Ni/IGZO/Al{sub 2}O{sub 3}/Si exhibits high performance with a low threshold voltage of 1.18 V, a high field effect mobility of 20.25 cm{sup 2}V{sup -1}s{sup -1}, an ultra small subthreshold swing of 87 mV/decade, and a high on/off current ratio of 3 x 10{sup 7}.

  20. Physical and electrical properties of bilayer CeO{sub 2}/TiO{sub 2} gate dielectric stack

    Energy Technology Data Exchange (ETDEWEB)

    Chong, M.M.V. [School of Materials Science and Engineering, Nanyang Technological University of Singapore, Block N 4.1Nanyang Avenue, Singapore 639798 (Singapore); GlobalFoundries Singapore Private Limited, 60 Woodlands Industrial Park D Street 2, Singapore 738406 (Singapore); Lee, P.S. [School of Materials Science and Engineering, Nanyang Technological University of Singapore, Block N 4.1Nanyang Avenue, Singapore 639798 (Singapore); Tok, A.I.Y., E-mail: MIYTOK@ntu.edu.sg [School of Materials Science and Engineering, Nanyang Technological University of Singapore, Block N 4.1Nanyang Avenue, Singapore 639798 (Singapore)

    2016-08-15

    Highlights: • A bilayer gate dielectric stack of CeO{sub 2}/TiO{sub 2} to study the dependency of film growth with varying annealing temperatures is proposed. • The study demonstrates CeO{sub 2}/TiO{sub 2} bilayer stack with comparable κ-value as that of HfO{sub 2} but with reduced leakage current density of 4 orders of magnitude. • Schottky emission is the dominant leakage conduction mechanism of annealed CeO{sub 2}/TiO{sub 2} stack due to thermionic effect of interface properties. - Abstract: This study demonstrates a bilayer gate oxide structure of cerium oxide deposited via pulsed laser deposition and titanium oxide using conventional atomic layer deposition. Samples were deposited on p-type Si (100) substrate and exhibit interesting physical and electrical properties such that 600 °C annealed CeO{sub 2}/TiO{sub 2} samples having κ-value of 18 whereas pure CeO{sub 2} deposited samples have dielectric constant of 17.1 with leakage current density of 8.94 × 10{sup −6} A/cm{sup 2} at 1 V applied voltage. The result shows promising usage of the synthesized rare earth oxides as gate dielectric where ideal κ-value and significant reduction of the leakage current by 5 orders of magnitude is achieved. Leakage current conduction mechanism for as-deposited sample is found to be dominated by Poole–Frenkel (PF) emission; the trap level is found to be at 1.29 eV whereas annealed samples (600 °C and 800 °C) exhibited Schottky emission with trap levels at 1.45 eV and 0.81 eV, respectively.

  1. A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

    Science.gov (United States)

    Ishii, Yuichiro; Tanaka, Miki; Yabuuchi, Makoto; Sawada, Yohei; Tanaka, Shinji; Nii, Koji; Lu, Tien Yu; Huang, Chun Hsien; Sian Chen, Shou; Tse Kuo, Yu; Lung, Ching Cheng; Cheng, Osbert

    2018-04-01

    We propose a highly symmetrical 10 transistor (10T) 2-read/write (2RW) dual-port (DP) static random access memory (SRAM) bitcell in 28 nm high-k/metal-gate (HKMG) planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves the robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (I read) and read static noise margin (SNM) are respectively boosted by +20% and +15 mV by introducing the proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) N-channel MOSs (NMOSs). The minimum operating voltage (V min) of the proposed 256 kbit 10T DP SRAM is 0.53 V in the TT process, 25 °C under the worst access condition with read/write disturbances, and improved by 90 mV (15%) compared with the conventional one.

  2. Electrical characteristics of GdTiO{sub 3} gate dielectric for amorphous InGaZnO thin-film transistors

    Energy Technology Data Exchange (ETDEWEB)

    Her, Jim-Long [Division of Natural Science, Center for General Education, Chang Gung University, Taoyuan 333, Taiwan (China); Pan, Tung-Ming, E-mail: tmpan@mail.cgu.edu.tw [Department of Electronics Engineering, Chang Gung University, Taoyuan 333, Taiwan (China); Liu, Jiang-Hung; Wang, Hong-Jun; Chen, Ching-Hung [Department of Electronics Engineering, Chang Gung University, Taoyuan 333, Taiwan (China); Koyama, Keiichi [Graduate School of Science and Engineering, Kagoshima University, Kagoshima 890-0065 (Japan)

    2014-10-31

    In this article, we studied the structural properties and electrical characteristics of GdTiO{sub 3} gate dielectric for amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) applications. The a-IGZO TFT device featuring the GdTiO{sub 3} gate dielectric exhibited better electrical characteristics, including a small threshold voltage of 0.14 V, a large field-effect mobility of 32.3 cm{sup 2}/V-s, a high I{sub on}/I{sub off} current ratio of 4.2 × 10{sup 8}, and a low subthreshold swing of 213 mV/decade. Furthermore, the electrical instability of GdTiO{sub 3} a-IGZO TFTs was investigated under both positive gate-bias stress (PGBS) and negative gate-bias stress (NGBS) conditions. The electron charge trapping in the gate dielectric dominates the PGBS degradation, while the oxygen vacancies control the NGBS degradation. - Highlights: • Indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) • Structural and electrical properties of the GdTiO{sub 3} film were studied. • a-IGZO TFT featuring GdTi{sub x}O{sub y} dielectric exhibited better electrical characteristics. • TFT instability investigated under positive and negative gate-bias stress conditions.

  3. Study of surface-modified PVP gate dielectric in organic thin film transistors with the nano-particle silver ink source/drain electrode.

    Science.gov (United States)

    Yun, Ho-Jin; Ham, Yong-Hyun; Shin, Hong-Sik; Jeong, Kwang-Seok; Park, Jeong-Gyu; Choi, Deuk-Sung; Lee, Ga-Won

    2011-07-01

    We have fabricated the flexible pentacene based organic thin film transistors (OTFTs) with formulated poly[4-vinylphenol] (PVP) gate dielectrics treated by CF4/O2 plasma on poly[ethersulfones] (PES) substrate. The solution of gate dielectrics is made by adding methylated poly[melamine-co-formaldehyde] (MMF) to PVP. The PVP gate dielectric layer was cross linked at 90 degrees under UV ozone exposure. Source/drain electrodes are formed by micro contact printing (MCP) method using nano particle silver ink for the purposes of low cost and high throughput. The optimized OTFT shows the device performance with field effect mobility of the 0.88 cm2/V s, subthreshold slope of 2.2 V/decade, and on/off current ratios of 1.8 x 10(-6) at -40 V gate bias. We found that hydrophobic PVP gate dielectric surface can influence on the initial film morphologies of pentacene making dense, which is more important for high performance OTFTs than large grain size. Moreover, hydrophobic gate dielelctric surface reduces voids and -OH groups that interrupt the carrier transport in OTFTs.

  4. Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

    KAUST Repository

    Salas-Villasenor, A. L.; Mejia, I.; Hovarth, J.; Alshareef, Husam N.; Cha, D. K.; Ramirez-Bon, R.; Gnade, B. E.; Quevedo-Lopez, M. A.

    2010-01-01

    Cadmium sulfide thin film transistors were demonstrated as the n-type device for use in flexible electronics. CdS thin films were deposited by chemical bath deposition (70° C) on either 100 nm HfO2 or SiO2 as the gate dielectrics. Common gate transistors with channel lengths of 40-100 μm were fabricated with source and drain aluminum top contacts defined using a shadow mask process. No thermal annealing was performed throughout the device process. X-ray diffraction results clearly show the hexagonal crystalline phase of CdS. The electrical performance of HfO 2 /CdS -based thin film transistors shows a field effect mobility and threshold voltage of 25 cm2 V-1 s-1 and 2 V, respectively. Improvement in carrier mobility is associated with better nucleation and growth of CdS films deposited on HfO2. © 2010 The Electrochemical Society.

  5. Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

    KAUST Repository

    Salas-Villasenor, A. L.

    2010-06-29

    Cadmium sulfide thin film transistors were demonstrated as the n-type device for use in flexible electronics. CdS thin films were deposited by chemical bath deposition (70° C) on either 100 nm HfO2 or SiO2 as the gate dielectrics. Common gate transistors with channel lengths of 40-100 μm were fabricated with source and drain aluminum top contacts defined using a shadow mask process. No thermal annealing was performed throughout the device process. X-ray diffraction results clearly show the hexagonal crystalline phase of CdS. The electrical performance of HfO 2 /CdS -based thin film transistors shows a field effect mobility and threshold voltage of 25 cm2 V-1 s-1 and 2 V, respectively. Improvement in carrier mobility is associated with better nucleation and growth of CdS films deposited on HfO2. © 2010 The Electrochemical Society.

  6. A complementary organic inverter of porphyrazine thin films: low-voltage operation using ionic liquid gate dielectrics.

    Science.gov (United States)

    Fujimoto, Takuya; Miyoshi, Yasuhito; Matsushita, Michio M; Awaga, Kunio

    2011-05-28

    We studied a complementary organic inverter consisting of a p-type semiconductor, metal-free phthalocyanine (H(2)Pc), and an n-type semiconductor, tetrakis(thiadiazole)porphyrazine (H(2)TTDPz), operated through the ionic-liquid gate dielectrics of N,N-diethyl-N-methyl(2-methoxyethyl)ammonium bis(trifluoromethylsulfonyl)imide (DEME-TFSI). This organic inverter exhibits high performance with a very low operation voltage below 1.0 V and a dynamic response up to 20 Hz. © The Royal Society of Chemistry 2011

  7. SiO2/AlON stacked gate dielectrics for AlGaN/GaN MOS heterojunction field-effect transistors

    Science.gov (United States)

    Watanabe, Kenta; Terashima, Daiki; Nozaki, Mikito; Yamada, Takahiro; Nakazawa, Satoshi; Ishida, Masahiro; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

    2018-06-01

    Stacked gate dielectrics consisting of wide bandgap SiO2 insulators and thin aluminum oxynitride (AlON) interlayers were systematically investigated in order to improve the performance and reliability of AlGaN/GaN metal–oxide–semiconductor (MOS) devices. A significantly reduced gate leakage current compared with that in a single AlON layer was achieved with these structures, while maintaining the superior thermal stability and electrical properties of the oxynitride/AlGaN interface. Consequently, distinct advantages in terms of the reliability of the gate dielectrics, such as an improved immunity against electron injection and an increased dielectric breakdown field, were demonstrated for AlGaN/GaN MOS capacitors with optimized stacked structures having a 3.3-nm-thick AlON interlayer.

  8. Total Ionizing Dose Effects of Si Vertical Diffused MOSFET with SiO2 and Si3N4/SiO2 Gate Dielectrics

    Directory of Open Access Journals (Sweden)

    Jiongjiong Mo

    2017-01-01

    Full Text Available The total ionizing dose irradiation effects are investigated in Si vertical diffused MOSFETs (VDMOSs with different gate dielectrics including single SiO2 layer and double Si3N4/SiO2 layer. Radiation-induced holes trapping is greater for single SiO2 layer than for double Si3N4/SiO2 layer. Dielectric oxidation temperature dependent TID effects are also studied. Holes trapping induced negative threshold voltage shift is smaller for SiO2 at lower oxidation temperature. Gate bias during irradiation leads to different VTH shift for different gate dielectrics. Single SiO2 layer shows the worst negative VTH at VG=0 V, while double Si3N4/SiO2 shows negative VTH shift at VG=-5 V, positive VTH shift at VG=10 V, and negligible VTH shift at VG=0 V.

  9. High mobility and low operating voltage ZnGaO and ZnGaLiO transistors with spin-coated Al2O3 as gate dielectric

    International Nuclear Information System (INIS)

    Xia, D X; Xu, J B

    2010-01-01

    Spin-coated alumina serving as a gate dielectric in thin film transistors shows interesting dielectric properties for low-voltage applications, despite a moderate capacitance. With Ga singly doped and Ga, Li co-doped ZnO as the active channel layers, typical mobilities of 4.7 cm 2 V -1 s -1 and 2.1 cm 2 V -1 s -1 are achieved, respectively. At a given gate bias, the operation current is much smaller than the previously reported values in low-voltage thin film transistors, primarily relying on the giant-capacitive dielectric. The reported devices combine advantages of high mobility, low power consumption, low cost and ease of fabrication. In addition to the transparent nature of both the dielectric and semiconducting active channels, the superior electrical properties of the devices may provide a new avenue for future transparent electronics. (fast track communication)

  10. Experimental and theoretical investigation of the effect of SiO2 content in gate dielectrics on work function shift induced by nanoscale capping layers

    KAUST Repository

    Caraveo-Frescas, J. A.; Wang, H.; Schwingenschlö gl, Udo; Alshareef, Husam N.

    2012-01-01

    The impact of SiO2 content in ultrathin gate dielectrics on the magnitude of the effective work function (EWF) shift induced by nanoscale capping layers has been investigated experimentally and theoretically. The magnitude of the effective work function shift for four different capping layers (AlN, Al2O3, La2O3, and Gd2O3) is measured as a function of SiO2 content in the gate dielectric. A nearly linear increase of this shift with SiO2 content is observed for all capping layers. The origin of this dependence is explained using density functional theory simulations.

  11. Experimental and theoretical investigation of the effect of SiO2 content in gate dielectrics on work function shift induced by nanoscale capping layers

    KAUST Repository

    Caraveo-Frescas, J. A.

    2012-09-10

    The impact of SiO2 content in ultrathin gate dielectrics on the magnitude of the effective work function (EWF) shift induced by nanoscale capping layers has been investigated experimentally and theoretically. The magnitude of the effective work function shift for four different capping layers (AlN, Al2O3, La2O3, and Gd2O3) is measured as a function of SiO2 content in the gate dielectric. A nearly linear increase of this shift with SiO2 content is observed for all capping layers. The origin of this dependence is explained using density functional theory simulations.

  12. A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

    Science.gov (United States)

    Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

    2018-06-15

    Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

  13. Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

    KAUST Repository

    Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Young, Chadwin D.; Bersuker, Gennadi; Hussain, Muhammad Mustafa

    2015-01-01

    We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard

  14. A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Dumitru, L. M.; Manoli, K.; Magliulo, M.; Torsi, L., E-mail: luisa.torsi@uniba.it [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Ligonzo, T. [Department of Physics, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Palazzo, G. [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Center of Colloid and Surface Science—CSGI—Bari Unit, Via Orabona 4, Bari I-70126 (Italy)

    2015-01-01

    A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

  15. Organic thin film transistors with polymer brush gate dielectrics synthesized by atom transfer radical polymerization

    DEFF Research Database (Denmark)

    Pinto, J.C.; Whiting, G.L.; Khodabakhsh, S.

    2008-01-01

    , synthesized by atom transfer radical polymerization (ATRP), were used to fabricate low voltage OFETs with both evaporated pentacene and solution deposited poly(3-hexylthiophene). The semiconductor-dielectric interfaces in these systems were studied with a variety of methods including scanning force microscopy...

  16. Low voltage operation of IGZO thin film transistors enabled by ultrathin Al2O3 gate dielectric

    Science.gov (United States)

    Ma, Pengfei; Du, Lulu; Wang, Yiming; Jiang, Ran; Xin, Qian; Li, Yuxiang; Song, Aimin

    2018-01-01

    An ultrathin, 5 nm, Al2O3 film grown by atomic-layer deposition was used as a gate dielectric for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The Al2O3 layer showed a low surface roughness of 0.15 nm, a low leakage current, and a high breakdown voltage of 6 V. In particular, a very high gate capacitance of 720 nF/cm2 was achieved, making it possible for the a-IGZO TFTs to not only operate at a low voltage of 1 V but also exhibit desirable properties including a low threshold voltage of 0.3 V, a small subthreshold swing of 100 mV/decade, and a high on/off current ratio of 1.2 × 107. Furthermore, even under an ultralow operation voltage of 0.6 V, well-behaved transistor characteristics were still observed with an on/off ratio as high as 3 × 106. The electron transport through the Al2O3 layer has also been analyzed, indicating the Fowler-Nordheim tunneling mechanism.

  17. Oligo- and polymeric FET devices: Thiophene-based active materials and their interaction with different gate dielectrics

    International Nuclear Information System (INIS)

    Porzio, W.; Destri, S.; Pasini, M.; Bolognesi, A.; Angiulli, A.; Di Gianvincenzo, P.; Natali, D.; Sampietro, M.; Caironi, M.; Fumagalli, L.; Ferrari, S.; Peron, E.; Perissinotti, F.

    2006-01-01

    Derivatives of both oligo- and polythiophene-based FET were recently considered for low cost electronic applications. In the device optimization, factors like redox reversibility of the molecule/polymer, electronic level compatibility with source/drain electrodes, packing closeness, and orientation versus the electrodes, can determine the overall performance. In addition, a gate insulator with a high dielectric constant, a low leakage current, and capability to promote ordering in the semiconductor is required to increase device performances and to lower the FET operating voltage. In this view, Al 2 O 3 appears a good candidate, although its widespread adoption is limited by the disorder that such oxide induces on the semiconductor with detrimental consequences on semiconductor electrical properties. In this contribution, an overview of recent results obtained on thiophene-derivative-based FET devices, fabricated by different growth techniques, and using both thermally grown SiO 2 and Al 2 O 3 from atomic layer deposition gate insulators will be reported and discussed with particular reference to organic solid state aggregation, morphology, and organic-inorganic interface

  18. Energy-band alignment of (HfO2)x(Al2O3)1-x gate dielectrics deposited by atomic layer deposition on β-Ga2O3 (-201)

    Science.gov (United States)

    Yuan, Lei; Zhang, Hongpeng; Jia, Renxu; Guo, Lixin; Zhang, Yimen; Zhang, Yuming

    2018-03-01

    Energy band alignments between series band of Al-rich high-k materials (HfO2)x(Al2O3)1-x and β-Ga2O3 are investigated using X-Ray Photoelectron Spectroscopy (XPS). The results exhibit sufficient conduction band offsets (1.42-1.53 eV) in (HfO2)x(Al2O3)1-x/β-Ga2O3. In addition, it is also obtained that the value of Eg, △Ec, and △Ev for (HfO2)x(Al2O3)1-x/β-Ga2O3 change linearly with x, which can be expressed by 6.98-1.27x, 1.65-0.56x, and 0.48-0.70x, respectively. The higher dielectric constant and higher effective breakdown electric field of (HfO2)x(Al2O3)1-x compared with Al2O3, coupled with sufficient barrier height and lower gate leakage makes it a potential dielectric for high voltage β-Ga2O3 power MOSFET, and also provokes interest in further investigation of HfAlO/β-Ga2O3 interface properties.

  19. Effect of annealing temperature on structural and electrical properties of high-κ YbTixOy gate dielectrics for InGaZnO thin film transistors

    International Nuclear Information System (INIS)

    Pan, Tung-Ming; Chen, Fa-Hsyang; Hung, Meng-Ning

    2015-01-01

    This paper describes the effect of annealing temperature on the structural properties and electrical characteristics of high–κ YbTi x O y gate dielectrics for indium–gallium–zinc–oxide (IGZO) thin-film transistors (TFTs). X-ray diffraction, x-ray photoelectron spectroscopy and atomic force microscopy were used to study the structural, chemical and morphological features, respectively, of these dielectric films annealed at 200, 300 and 400 °C. The YbTi x O y IGZO TFT that had been annealed at 400 °C exhibited better electrical characteristics, such as a small threshold voltage of 0.53 V, a large field-effect mobility of 19.1 cm 2 V −1 s −1 , a high I on /I off ratio of 2.8 × 10 7 , and a low subthreshold swing of 176 mV dec. −1 , relative to those of the systems that had been subjected to other annealing conditions. This result suggests that YbTi x O y dielectric possesses a higher dielectric constant as well as lower oxygen vacancies (or defects) in the film. In addition, the instability of YbTi x O y IGZO TFT was studied under positive gate-bias stress and negative gate-bias stress conditions. (paper)

  20. Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO2 Gate Dielectrics by CF4 Plasma Treatment

    Science.gov (United States)

    Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

    2018-01-01

    In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO2 gate insulator and CF4 plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO2 gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm2/V∙s (without treatment) to 54.6 cm2/V∙s (with CF4 plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO2 gate dielectric has also been improved by the CF4 plasma treatment. By applying the CF4 plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device’s immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF4 plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO2 gate dielectric, but also enhances the device’s reliability. PMID:29772767

  1. Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO2 Gate Dielectrics by CF4 Plasma Treatment

    Directory of Open Access Journals (Sweden)

    Ching-Lin Fan

    2018-05-01

    Full Text Available In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs with a HfO2 gate insulator and CF4 plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO2 gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm2/V∙s (without treatment to 54.6 cm2/V∙s (with CF4 plasma treatment, which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO2 gate dielectric has also been improved by the CF4 plasma treatment. By applying the CF4 plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device’s immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF4 plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO2 gate dielectric, but also enhances the device’s reliability.

  2. Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO₂ Gate Dielectrics by CF₄ Plasma Treatment.

    Science.gov (United States)

    Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

    2018-05-17

    In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO₂ gate insulator and CF₄ plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO₂ gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm²/V∙s (without treatment) to 54.6 cm²/V∙s (with CF₄ plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO₂ gate dielectric has also been improved by the CF₄ plasma treatment. By applying the CF₄ plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device's immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF₄ plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO₂ gate dielectric, but also enhances the device's reliability.

  3. Tungsten trioxide as high-{kappa} gate dielectric for highly transparent and temperature-stable zinc-oxide-based thin-film transistors

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Michael; Wenckstern, Holger von; Grundmann, Marius [Universitaet Leipzig, Fakultaet fuer Physik und Geowissenschaften, Institut fuer Experimentelle Physik II, Linnestr. 5, 04103 Leipzig (Germany)

    2012-07-01

    We demonstrate metal-insulator-semiconductor field-effect transistors with high-{kappa}, room-temperature deposited, highly transparent tungsten trioxide (WO{sub 3}) as gate dielectric. The channel material consists of a zinc oxide (ZnO) thin-film. The transmittance and resistivity of WO{sub 3} films was tuned in order to obtain a highly transparent and insulating WO{sub 3} dielectric. The devices were processed by standard photolithography using lift-off technique. On top of the WO{sub 3} dielectric a highly transparent and conductive oxide consisting of ZnO: Al 3% wt. was deposited. The gate structure of the devices exhibits an average transmittance in the visible spectral range of 86%. The on/off-current ratio is larger than 10{sup 8} with off- and gate leakage-currents below 3 x 10{sup -8} A/cm{sup 2}. Due to the high relative permittivity of {epsilon}{sub r} {approx} 70, a gate voltage sweep of only 2 V is necessary to turn the transistor on and off with a minimum subthreshold swing of 80 mV/decade. The channel mobility of the transistors equals the Hall-effect mobility with a value of 5 cm{sup 2}/Vs. It is furthermore shown, that the devices are stable up to operating temperatures of at least 150 C.

  4. Proton Conducting Graphene Oxide/Chitosan Composite Electrolytes as Gate Dielectrics for New-Concept Devices.

    Science.gov (United States)

    Feng, Ping; Du, Peifu; Wan, Changjin; Shi, Yi; Wan, Qing

    2016-09-30

    New-concept devices featuring the characteristics of ultralow operation voltages and low fabrication cost have received increasing attention recently because they can supplement traditional Si-based electronics. Also, organic/inorganic composite systems can offer an attractive strategy to combine the merits of organic and inorganic materials into promising electronic devices. In this report, solution-processed graphene oxide/chitosan composite film was found to be an excellent proton conducting electrolyte with a high specific capacitance of ~3.2 μF/cm 2 at 1.0 Hz, and it was used to fabricate multi-gate electric double layer transistors. Dual-gate AND logic operation and two-terminal diode operation were realized in a single device. A two-terminal synaptic device was proposed, and some important synaptic behaviors were emulated, which is interesting for neuromorphic systems.

  5. OTFT with pentacene-gate dielectric interface modified by silicon nanoparticles

    International Nuclear Information System (INIS)

    Jakabovic, J.; Kovac, J.; Srnanek, R.; Guldan, S.; Donoval, D.; Weis, M.; Sokolsky, M.; Cirak, J.; Broch, K.; Schreiber, F.

    2011-01-01

    We have for the first time investigated the structural and electrical properties of pentacene OTFT deposited on the semiconductor-gate insulator interface covered with SiNPs monolayer prepared by the LB method and compared these to a reference sample (without SiNPs). The micro-Raman, AFM and XRD measurements confirmed that the pentacene layer deposited on the semiconductor-gate insulator interface covered with a SiNPs monolayer on both hydrophobic and hydrophilic surfaces changes the structure. The Raman measurements show that the average value of α is between 0.8 and 1.0. The different structural quality of pentacene leads to better OTFTs electrical characteristics mainly saturation current of OTFTs with SiNPs increasing (∼ 2.5 x) with storing time (85 days) in comparison to OTFTs without SiNPs, which decrease similarly after 85 days.

  6. Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

    KAUST Repository

    Ghoneim, Mohamed T.

    2015-06-01

    We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard bulk mono-crystalline silicon substrate. A lifetime projection is extracted using statistical analysis of the ramping voltage (Vramp) breakdown and time dependent dielectric breakdown data. The obtained flexible MOSCAPs operational voltages satisfying the 10 years lifetime benchmark are compared to those of the control MOSCAPs, which are not peeled off from the silicon wafer. © 2014 IEEE.

  7. Pentacene thin-film transistors and inverters with plasma-enhanced atomic-layer-deposited Al2O3 gate dielectric

    International Nuclear Information System (INIS)

    Koo, Jae Bon; Lim, Jung Wook; Kim, Seong Hyun; Yun, Sun Jin; Ku, Chan Hoe; Lim, Sang Chul; Lee, Jung Hun

    2007-01-01

    The performances of pentacene thin-film transistor with plasma-enhanced atomic-layer-deposited (PEALD) 150 nm thick Al 2 O 3 dielectric are reported. Saturation mobility of 0.38 cm 2 /V s, threshold voltage of 1 V, subthreshold swing of 0.6 V/decade, and on/off current ratio of about 10 8 have been obtained. Both depletion and enhancement mode inverter have been realized with the change of treatment method of hexamethyldisilazane on PEALD Al 2 O 3 gate dielectric. Full swing depletion mode inverter has been demonstrated at input voltages ranging from 5 V to - 5 V at supply voltage of - 5 V

  8. Highly stretchable carbon nanotube transistors enabled by buckled ion gel gate dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Meng-Yin; Chang, Tzu-Hsuan; Ma, Zhenqiang [Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States); Zhao, Juan [School of Optoelectronic Information, University of Electronic Science and Technology of China, Chengdu 610054 (China); Department of Materials Science and Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States); Xu, Feng; Jacobberger, Robert M.; Arnold, Michael S., E-mail: michael.arnold@wisc.edu [Department of Materials Science and Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States)

    2015-08-03

    Deformable field-effect transistors (FETs) are expected to facilitate new technologies like stretchable displays, conformal devices, and electronic skins. We previously demonstrated stretchable FETs based on buckled thin films of polyfluorene-wrapped semiconducting single-walled carbon nanotubes as the channel, buckled metal films as electrodes, and unbuckled flexible ion gel films as the dielectric. The FETs were stretchable up to 50% without appreciable degradation in performance before failure of the ion gel film. Here, we show that by buckling the ion gel, the integrity and performance of the nanotube FETs are extended to nearly 90% elongation, limited by the stretchability of the elastomer substrate. The FETs maintain an on/off ratio of >10{sup 4} and a field-effect mobility of 5 cm{sup 2} V{sup −1} s{sup −1} under elongation and demonstrate invariant performance over 1000 stretching cycles.

  9. Highly stretchable carbon nanotube transistors enabled by buckled ion gel gate dielectrics

    International Nuclear Information System (INIS)

    Wu, Meng-Yin; Chang, Tzu-Hsuan; Ma, Zhenqiang; Zhao, Juan; Xu, Feng; Jacobberger, Robert M.; Arnold, Michael S.

    2015-01-01

    Deformable field-effect transistors (FETs) are expected to facilitate new technologies like stretchable displays, conformal devices, and electronic skins. We previously demonstrated stretchable FETs based on buckled thin films of polyfluorene-wrapped semiconducting single-walled carbon nanotubes as the channel, buckled metal films as electrodes, and unbuckled flexible ion gel films as the dielectric. The FETs were stretchable up to 50% without appreciable degradation in performance before failure of the ion gel film. Here, we show that by buckling the ion gel, the integrity and performance of the nanotube FETs are extended to nearly 90% elongation, limited by the stretchability of the elastomer substrate. The FETs maintain an on/off ratio of >10 4 and a field-effect mobility of 5 cm 2 V −1 s −1 under elongation and demonstrate invariant performance over 1000 stretching cycles

  10. Band Offsets and Interfacial Properties of HfAlO Gate Dielectric Grown on InP by Atomic Layer Deposition.

    Science.gov (United States)

    Yang, Lifeng; Wang, Tao; Zou, Ying; Lu, Hong-Liang

    2017-12-01

    X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy have been used to determine interfacial properties of HfO 2 and HfAlO gate dielectrics grown on InP by atomic layer deposition. An undesirable interfacial InP x O y layer is easily formed at the HfO 2 /InP interface, which can severely degrade the electrical performance. However, an abrupt interface can be achieved when the growth of the HfAlO dielectric on InP starts with an ultrathin Al 2 O 3 layer. The valence and conduction band offsets for HfAlO/InP heterojunctions have been determined to be 1.87 ± 0.1 and 2.83 ± 0.1 eV, respectively. These advantages make HfAlO a potential dielectric for InP MOSFETs.

  11. Synchrotron radiation x-ray photoelectron spectroscopy study on the interface chemistry of high-k PrxAl2-xO3 (x=0-2) dielectrics on TiN for dynamic random access memory applications

    Science.gov (United States)

    Schroeder, T.; Lupina, G.; Sohal, R.; Lippert, G.; Wenger, Ch.; Seifarth, O.; Tallarida, M.; Schmeisser, D.

    2007-07-01

    Engineered dielectrics combined with compatible metal electrodes are important materials science approaches to scale three-dimensional trench dynamic random access memory (DRAM) cells. Highly insulating dielectrics with high dielectric constants were engineered in this study on TiN metal electrodes by partly substituting Al in the wide band gap insulator Al2O3 by Pr cations. High quality PrAlO3 metal-insulator-metal capacitors were processed with a dielectric constant of 19, three times higher than in the case of Al2O3 reference cells. As a parasitic low dielectric constant interface layer between PrAlO3 and TiN limits the total performance gain, a systematic nondestructive synchrotron x-ray photoelectron spectroscopy study on the interface chemistry of PrxAl2-xO3 (x =0-2) dielectrics on TiN layers was applied to unveil its chemical origin. The interface layer results from the decreasing chemical reactivity of PrxAl2-xO3 dielectrics with increasing Pr content x to reduce native Ti oxide compounds present on unprotected TiN films. Accordingly, PrAlO3 based DRAM capacitors require strict control of the surface chemistry of the TiN electrode, a parameter furthermore of importance to engineer the band offsets of PrxAl2-xO3/TiN heterojunctions.

  12. Interface engineering and reliability characteristics of hafnium dioxide with poly silicon gate and dual metal (ruthenium-tantalum alloy, ruthenium) gate electrode for beyond 65 nm technology

    Science.gov (United States)

    Kim, Young-Hee

    Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is

  13. Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

    Energy Technology Data Exchange (ETDEWEB)

    Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A., E-mail: steven.vitale@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

    2015-07-28

    Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

  14. Effects of the gate dielectric on the subthreshold transport of carbon nanotube network transistors grown by using plasma-enhanced chemical vapor deposition

    International Nuclear Information System (INIS)

    Jeong, Seung Geun; Park, Wan Jun

    2010-01-01

    In this study, we investigated the subthreshold slope of random network carbon nanotube transistors with different geometries and passivations. Single-wall carbon nanotubes with lengths of 1-2 m were grown by using plasma-enhanced chemical vapor deposition to form the transistor channels. A critical channel length, where the subthreshold slope was saturated, of 7 μm was obtained. This was due to the percolational behavior of the nanotube random networks. With the dielectric passivation, the subthreshold slope was dramatically reduced from 9 V/decade to 0.9 V/decade by reducing interfacial trap sites, which then reduced the interface capacitance between the nanotube network and the gate dielectric.

  15. An EELS sub-nanometer investigation of the dielectric gate stack for the realization of InGaAs based MOSFET devices

    International Nuclear Information System (INIS)

    Longo, P; Paterson, G W; Craven, A J; Holland, M C; Thayne, I G

    2010-01-01

    In this paper, a subnanometer investigation of the Ga 2 O 3 /GdGaO dielectric gate stack deposited onto InGaAs is presented. Results regarding the influence of the growth conditions on the interface region from a chemical and morphological point of view are presented. The chemical information reported in this paper has been obtained using electron energy loss spectroscopy (EELS) that was carried out in a scanning transmission electron microscope ((S)TEM) showing both spatial and depth resolution.

  16. Emerging Applications for High K Materials in VLSI Technology

    Science.gov (United States)

    Clark, Robert D.

    2014-01-01

    The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. PMID:28788599

  17. Emerging Applications for High K Materials in VLSI Technology

    Directory of Open Access Journals (Sweden)

    Robert D. Clark

    2014-04-01

    Full Text Available The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI manufacturing for leading edge Dynamic Random Access Memory (DRAM and Complementary Metal Oxide Semiconductor (CMOS applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.

  18. Bias Stability Enhancement in Thin-Film Transistor with a Solution-Processed ZrO2 Dielectric as Gate Insulator

    Directory of Open Access Journals (Sweden)

    Shangxiong Zhou

    2018-05-01

    Full Text Available In this paper, a high-k metal-oxide film (ZrO2 was successfully prepared by a solution-phase method, and whose physical properties were measured by X-ray diffraction (XRD, X-ray reflectivity (XRR and atomic force microscopy (AFM. Furthermore, indium–gallium–zinc oxide thin-film transistors (IGZO-TFTs with high-k ZrO2 dielectric layers were demonstrated, and the electrical performance and bias stability were investigated in detail. By spin-coating 0.3 M precursor six times, a dense ZrO2 film, with smoother surface and fewer defects, was fabricated. The TFT devices with optimal ZrO2 dielectric exhibit a saturation mobility up to 12.7 cm2 V−1 s−1, and an on/off ratio as high as 7.6 × 105. The offset of the threshold voltage was less than 0.6 V under positive and negative bias stress for 3600 s.

  19. Cell characteristics of FePt nano-dot memories with a high-k Al2O3 blocking oxide

    International Nuclear Information System (INIS)

    Lee, Gae Hun; Lee, Jung Min; Yang, Hyung Jun; Song, Yun Heub; Bea, Ji Cheol; Tanaka, Testsu

    2012-01-01

    The cell characteristics of an alloy FePt nano-dot (ND) charge trapping memory with a high-k dielectric as a blocking oxide was investigated. Adoption of a high-k Al 2 O 3 material as a blocking oxide for the metal nano-dot memory provided a superior scaling of the operation voltage compared to silicon oxide under a similar gate leakage level. For the 40-nm-thick high-k (Al 2 O 3 ) blocking oxide, we confirmed an operation voltage reduction of ∼7 V under the same memory window on for silicon dioxide. Also, this device showed a large memory window of 7.8 V and a low leakage current under 10 -10 A in an area of Φ 0.25 mm. From these results, the use of a dielectric (Al 2 O 3 ) as a blocking oxide for a metal nano-dot device is essential, and a metal nano-dot memory with a high-k dielectric will be one of the candidates for a high-density non-volatile memory device.

  20. Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11 000 cm2/V·s

    KAUST Repository

    Smith, Casey

    2013-07-23

    Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11 000 cm 2/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low t ox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance. © 2013 American Chemical Society.

  1. Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11 000 cm2/V·s

    KAUST Repository

    Smith, Casey; Qaisi, Ramy M.; Liu, Zhihong; Yu, Qingkai; Hussain, Muhammad Mustafa

    2013-01-01

    Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11 000 cm 2/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low t ox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance. © 2013 American Chemical Society.

  2. Comparative study on nitridation and oxidation plasma interface treatment for AlGaN/GaN MIS-HEMTs with AlN gate dielectric

    Science.gov (United States)

    Zhu, Jie-Jie; Ma, Xiao-Hua; Hou, Bin; Chen, Li-Xiang; Zhu, Qing; Hao, Yue

    2017-02-01

    This paper demonstrated the comparative study on interface engineering of AlN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) by using plasma interface pre-treatment in various ambient gases. The 15 nm AlN gate dielectric grown by plasma-enhanced atomic layer deposition significantly suppressed the gate leakage current by about two orders of magnitude and increased the peak field-effect mobility by more than 50%. NH3/N2 nitridation plasma treatment (NPT) was used to remove the 3 nm poor-quality interfacial oxide layer and N2O/N2 oxidation plasma treatment (OPT) to improve the quality of interfacial layer, both resulting in improved dielectric/barrier interface quality, positive threshold voltage (V th) shift larger than 0.9 V, and negligible dispersion. In comparison, however, NPT led to further decrease in interface charges by 3.38 × 1012 cm-2 and an extra positive V th shift of 1.3 V. Analysis with fat field-effect transistors showed that NPT resulted in better sub-threshold characteristics and transconductance linearity for MIS-HEMTs compared with OPT. The comparative study suggested that direct removing the poor interfacial oxide layer by nitridation plasma was superior to improving the quality of interfacial layer by oxidation plasma for the interface engineering of GaN-based MIS-HEMTs.

  3. Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene–graphene composite layers for flexible thin film transistors with a polymer gate dielectric

    International Nuclear Information System (INIS)

    Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

    2014-01-01

    Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene–graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene–graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm 2  V −1  s −1 and a threshold voltage of −0.7 V at V gs = −40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm 2  V −1  s −1 and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies. (paper)

  4. Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene-graphene composite layers for flexible thin film transistors with a polymer gate dielectric.

    Science.gov (United States)

    Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

    2014-02-28

    Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene-graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene-graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm(2) V(-1) s(-1) and a threshold voltage of -0.7 V at V(gs) = -40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm(2) V(-1) s(-1) and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies.

  5. Dielectric Modulated FET (DMFET)

    Indian Academy of Sciences (India)

    First page Back Continue Last page Graphics. Working Principle: Change in Dielectric constant due to immobilization of biomolecules in the nanogap cavity leads to change in effective gate capacitance and thus gate bias for FET. Working Principle: Change in Dielectric constant due to immobilization of biomolecules in the ...

  6. Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors.

    Science.gov (United States)

    Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

    2016-12-01

    In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade(-1) and 3.62 × 10(11) eV(-1) cm(-2), respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

  7. Investigation of capacitance characteristics in metal/high-k

    Indian Academy of Sciences (India)

    Keywords. C − V characteristic; high-k dielectric; interface state density; MIS structure; nanotechnology; TCAD simulation. Abstract. Capacitance vs. voltage ( C − V ) curves at AC high frequency of a metal–insulator–semiconductor (MIS) capacitorare investigated in this paper. Bi-dimensional simulations with Silvaco TCAD ...

  8. Sodium beta-alumina thin films as gate dielectrics for AlGaN/GaN metal—insulator—semiconductor high-electron-mobility transistors

    International Nuclear Information System (INIS)

    Tian Ben-Lang; Chen Chao; Li Yan-Rong; Zhang Wan-Li; Liu Xing-Zhao

    2012-01-01

    Sodium beta-alumina (SBA) is deposited on AlGaN/GaN by using a co-deposition process with sodium and Al 2 O 3 as the precursors. The X-ray diffraction (XRD) spectrum reveals that the deposited thin film is amorphous. The binding energy and composition of the deposited thin film, obtained from the X-ray photoelectron spectroscopy (XPS) measurement, are consistent with those of SBA. The dielectric constant of the SBA thin film is about 50. Each of the capacitance—voltage characteristics obtained at five different frequencies shows a high-quality interface between SBA and AlGaN. The interface trap density of metal—insulator—semiconductor high-electron-mobility transistor (MISHEMT) is measured to be (3.5∼9.5)×10 10 cm −2 ·eV −1 by the conductance method. The fixed charge density of SBA dielectric is on the order of 2.7×10 12 cm −2 . Compared with the AlGaN/GaN metal—semiconductor heterostructure high-electron-mobility transistor (MESHEMT), the AlGaN/GaN MISHEMT usually has a threshold voltage that shifts negatively. However, the threshold voltage of the AlGaN/GaN MISHEMT using SBA as the gate dielectric shifts positively from −5.5 V to −3.5 V. From XPS results, the surface valence-band maximum (VBM-EF) of AlGaN is found to decrease from 2.56 eV to 2.25 eV after the SBA thin film deposition. The possible reasons why the threshold voltage of AlGaN/GaN MISHEMT with the SBA gate dielectric shifts positively are the influence of SBA on surface valence-band maximum (VBM-EF), the reduction of interface traps and the effects of sodium ions, and/or the fixed charges in SBA on the two-dimensional electron gas (2DEG). (condensed matter: structural, mechanical, and thermal properties)

  9. Use of water vapor for suppressing the growth of unstable low-{kappa} interlayer in HfTiO gate-dielectric Ge metal-oxide-semiconductor capacitors with sub-nanometer capacitance equivalent thickness

    Energy Technology Data Exchange (ETDEWEB)

    Xu, J.P. [Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan, 430074 (China); Zou, X. [School of Electromachine and Architecture Engineering, Jianghan University, Wuhan, 430056 (China); Lai, P.T. [Department of Electrical and Electronic Engineering, University of Hong Kong, Pokfulam Road (Hong Kong)], E-mail: laip@eee.hku.hk; Li, C.X.; Chan, C.L. [Department of Electrical and Electronic Engineering, University of Hong Kong, Pokfulam Road (Hong Kong)

    2009-03-02

    Annealing of high-permittivity HfTiO gate dielectric on Ge substrate in different gases (N{sub 2}, NH{sub 3}, NO and N{sub 2}O) with or without water vapor is investigated. Analysis by transmission electron microscopy indicates that the four wet anneals can greatly suppress the growth of a GeO{sub x} interlayer at the dielectric/Ge interface, and thus decrease interface states, oxide charges and gate leakage current. Moreover, compared with the wet N{sub 2} anneal, the wet NH{sub 3}, NO and N{sub 2}O anneals decrease the equivalent permittivity of the gate dielectric due to the growth of a GeO{sub x}N{sub y} interlayer. Among the eight anneals, the wet N{sub 2} anneal produces the best dielectric performance with an equivalent relative permittivity of 35, capacitance equivalent thickness of 0.81 nm, interface-state density of 6.4 x 10{sup 11} eV{sup -1} cm{sup -2} and gate leakage current of 2.7 x 10{sup -4} A/cm{sup 2} at V{sub g} = 1 V.

  10. Use of water vapor for suppressing the growth of unstable low-κ interlayer in HfTiO gate-dielectric Ge metal-oxide-semiconductor capacitors with sub-nanometer capacitance equivalent thickness

    International Nuclear Information System (INIS)

    Xu, J.P.; Zou, X.; Lai, P.T.; Li, C.X.; Chan, C.L.

    2009-01-01

    Annealing of high-permittivity HfTiO gate dielectric on Ge substrate in different gases (N 2 , NH 3 , NO and N 2 O) with or without water vapor is investigated. Analysis by transmission electron microscopy indicates that the four wet anneals can greatly suppress the growth of a GeO x interlayer at the dielectric/Ge interface, and thus decrease interface states, oxide charges and gate leakage current. Moreover, compared with the wet N 2 anneal, the wet NH 3 , NO and N 2 O anneals decrease the equivalent permittivity of the gate dielectric due to the growth of a GeO x N y interlayer. Among the eight anneals, the wet N 2 anneal produces the best dielectric performance with an equivalent relative permittivity of 35, capacitance equivalent thickness of 0.81 nm, interface-state density of 6.4 x 10 11 eV -1 cm -2 and gate leakage current of 2.7 x 10 -4 A/cm 2 at V g = 1 V

  11. Effect of the post-deposition annealing on electrical characteristics of MIS structures with HfO{sub 2}/SiO{sub 2} gate dielectric stacks

    Energy Technology Data Exchange (ETDEWEB)

    Taube, Andrzej [Institute of Electron Technology, Al. Lotnikow 32/46, 02-668 Warsaw (Poland); Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland); Mroczynski, Robert, E-mail: rmroczyn@elka.pw.edu.pl [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland); Korwin-Mikke, Katarzyna [Institute of Electron Technology, Al. Lotnikow 32/46, 02-668 Warsaw (Poland); Gieraltowska, Sylwia [Institute of Physics, Polish Academy of Sciences, Al. Lotnikow 32/46, 02-668 Warsaw (Poland); Szmidt, Jan [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland); Piotrowska, Anna [Institute of Electron Technology, Al. Lotnikow 32/46, 02-668 Warsaw (Poland)

    2012-09-01

    In this work, we report on effects of post-deposition annealing on electrical characteristics of metal-insulator-semiconductor (MIS) structures with HfO{sub 2}/SiO{sub 2} double gate dielectric stacks. Obtained results have shown the deterioration of electro-physical properties of MIS structures, e.g. higher interface traps density in the middle of silicon forbidden band (D{sub itmb}), as well as non-uniform distribution and decrease of breakdown voltage (U{sub br}) values, after annealing above 400 Degree-Sign C. Two potential hypothesis of such behavior were proposed: the formation of interfacial layer between hafnia and silicon dioxide and the increase of crystallinity of HfO{sub 2} due to the high temperature treatment. Furthermore, the analysis of conduction mechanisms in investigated stacks revealed Poole-Frenkel (P-F) tunneling at broad range of electric field intensity.

  12. Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

    Science.gov (United States)

    Park, Hyeonwoo; Teramoto, Akinobu; Kuroda, Rihito; Suwa, Tomoyuki; Sugawa, Shigetoshi

    2018-04-01

    Localized stress-induced leakage current (SILC) has become a major problem in the reliability of flash memories. To reduce it, clarifying the SILC mechanism is important, and statistical measurement and analysis have to be carried out. In this study, we applied an array test circuit that can measure the SILC distribution of more than 80,000 nMOSFETs with various gate areas at a high speed (within 80 s) and a high accuracy (on the 10-17 A current order). The results clarified that the distributions of localized SILC in different gate areas follow a universal distribution assuming the same SILC defect density distribution per unit area, and the current of localized SILC defects does not scale down with the gate area. Moreover, the distribution of SILC defect density and its dependence on the oxide field for measurement (E OX-Measure) were experimentally determined for fabricated devices.

  13. Influence of O2 flow rate on HfO2 gate dielectrics for back-gated graphene transistors

    International Nuclear Information System (INIS)

    Ganapathi, Kolla Lakshmi; Bhat, Navakanta; Mohan, Sangeneni

    2014-01-01

    HfO 2  thin films deposited on Si substrate using electron beam evaporation, are evaluated for back-gated graphene transistors. The amount of O 2  flow rate, during evaporation is optimized for 35 nm thick HfO 2  films, to achieve the best optical, chemical and electrical properties. It has been observed that with increasing oxygen flow rate, thickness of the films increased and refractive index decreased due to increase in porosity resulting from the scattering of the evaporant. The films deposited at low O 2  flow rates (1 and 3 SCCM) show better optical and compositional properties. The effects of post-deposition annealing and post-metallization annealing in forming gas ambience (FGA) on the optical and electrical properties of the films have been analyzed. The film deposited at 3 SCCM O 2  flow rate shows the best properties as measured on MOS capacitors. To evaluate the performance of device properties, back-gated bilayer graphene transistors on HfO 2  films deposited at two O 2  flow rates of 3 and 20 SCCM have been fabricated and characterized. The transistor with HfO 2  film deposited at 3 SCCM O 2  flow rate shows better electrical properties consistent with the observations on MOS capacitor structures. This suggests that an optimum oxygen pressure is necessary to get good quality films for high performance devices. (paper)

  14. Structural and electrical characteristics of high-κ ErTixOy gate dielectrics on InGaZnO thin-film transistors

    International Nuclear Information System (INIS)

    Chen, Fa-Hsyang; Her, Jim-Long; Shao, Yu-Hsuan; Li, Wei-Chen; Matsuda, Yasuhiro H.; Pan, Tung-Ming

    2013-01-01

    In this paper, we investigated the structural properties and electrical characteristics of high-κ ErTi x O y gate dielectrics on indium-gallium-zinc oxide thin-film transistors (IGZO TFTs). We used X-ray diffraction, X-ray photoelectron spectroscopy, and atomic force microscopy to investigate the structural and morphological features of these dielectric films after they had been subjected to annealing at various temperatures. The high-κ ErTi x O y IGZO TFT device annealed at 400 °C exhibited better electrical characteristics in terms of a large field-effect mobility (8.24 cm 2 /V-s), low threshold voltage (0.36 V), small subthreshold swing (130 mV/dec), and high I on/off ratio(3.73 × 10 6 ). These results are attributed to the reduction of the trap states and oxygen vacancies between the ErTi x O y film and IGZO active layer interface during high-temperature annealing in oxygen ambient. The reliability of voltage stress also can be improved by the oxygen annealing at 400 °C. - Highlights: • ErTi x O y InGaZnO thin-film transistors (TFT). • Structural and electrical properties of the TFT were investigated. • TFT device annealed at 400 °C exhibited better electrical characteristics. • Reliability of TFT device can be improved by annealing at 400 °C

  15. Low-voltage organic thin film transistors (OTFTs) using crosslinked polyvinyl alcohol (PVA)/neodymium oxide (Nd2O3) bilayer gate dielectrics

    Science.gov (United States)

    Khound, Sagarika; Sarma, Ranjit

    2018-01-01

    We have reported here on the design, processing and dielectric properties of pentacene-based organic thin film transitors (OTFTs) with a bilayer gate dilectrics of crosslinked PVA/Nd2O3 which enables low-voltage organic thin film operations. The dielectric characteristics of PVA/Nd2O3 bilayer films are studied by capacitance-voltage ( C- V) and current-voltage ( I- V) curves in the metal-insulator-metal (MIM) structure. We have analysed the output electrical responses and transfer characteristics of the OTFT devices to determine their performance of OTFT parameters. The mobility of 0.94 cm2/Vs, the threshold voltage of - 2.8 V, the current on-off ratio of 6.2 × 105, the subthreshold slope of 0.61 V/decade are evaluated. Low leakage current of the device is observed from current density-electric field ( J- E) curve. The structure and the morphology of the device are studied using X-ray diffraction (XRD) and atomic force microscope (AFM), respectively. The study demonstrates an effective way to realize low-voltage, high-performance OTFTs at low cost.

  16. Accurate characterization and understanding of interface trap density trends between atomic layer deposited dielectrics and AlGaN/GaN with bonding constraint theory

    Energy Technology Data Exchange (ETDEWEB)

    Ramanan, Narayanan; Lee, Bongmook; Misra, Veena, E-mail: vmisra@ncsu.edu [Department of Electrical and Computer Engineering, North Carolina State University, 2410 Campus Shore Drive, Raleigh, North Carolina 27695 (United States)

    2015-06-15

    Many dielectrics have been proposed for the gate stack or passivation of AlGaN/GaN based metal oxide semiconductor heterojunction field effect transistors, to reduce gate leakage and current collapse, both for power and RF applications. Atomic Layer Deposition (ALD) is preferred for dielectric deposition as it provides uniform, conformal, and high quality films with precise monolayer control of film thickness. Identification of the optimum ALD dielectric for the gate stack or passivation requires a critical investigation of traps created at the dielectric/AlGaN interface. In this work, a pulsed-IV traps characterization method has been used for accurate characterization of interface traps with a variety of ALD dielectrics. High-k dielectrics (HfO{sub 2}, HfAlO, and Al{sub 2}O{sub 3}) are found to host a high density of interface traps with AlGaN. In contrast, ALD SiO{sub 2} shows the lowest interface trap density (<2 × 10{sup 12 }cm{sup −2}) after annealing above 600 °C in N{sub 2} for 60 s. The trend in observed trap densities is subsequently explained with bonding constraint theory, which predicts a high density of interface traps due to a higher coordination state and bond strain in high-k dielectrics.

  17. A comparative study of amorphous InGaZnO thin-film transistors with HfOxNy and HfO2 gate dielectrics

    International Nuclear Information System (INIS)

    Zou, Xiao; Tong, Xingsheng; Fang, Guojia; Yuan, Longyan; Zhao, Xingzhong

    2010-01-01

    High-κ HfO x N y and HfO 2 films are applied to amorphous InGaZnO (a-IGZO) devices as gate dielectric using radio-frequency reactive sputtering. The electrical characteristics and reliability of a-IGZO metal–insulator–semiconductor (MIS) capacitors and thin-film transistors (TFTs) are then investigated. Experimental results indicate that the nitrogen incorporation into HfO 2 can effectively improve the interface quality and enhance the reliability of the devices. Electrical properties with an interface-state density of 5.2 × 10 11 eV −1 cm −2 , capacitance equivalent thickness of 1.65 nm, gate leakage current density of 3.4 × 10 −5 A cm −2 at V fb +1 V, equivalent permittivity of 23.6 and hysteresis voltage of 110 mV are obtained for an Al/HfO x N y /a-IGZO MIS capacitor. Superior performance of HfO x N y /a-IGZO TFTs has also been achieved with a low threshold voltage of 0.33 V, a high saturation mobility of 12.1 cm 2 V −1 s −1 and a large on–off current ratio up to 7 × 10 7 (W/L = 500/20 µm) at 3 V

  18. Fabrication and electrical properties of metal-oxide semiconductor capacitors based on polycrystalline p-Cu{sub x}O and HfO{sub 2}/SiO{sub 2} high-{kappa} stack gate dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Zou Xiao [Department of Electronic Science and Technology, School of Physical Science and Technology, Wuhan University, Wuhan, 430074 (China); Department of Electromachine Engineering, Jianghan University, Wuhan, 430056 (China); Fang Guojia, E-mail: gjfang@whu.edu.c [Department of Electronic Science and Technology, School of Physical Science and Technology, Wuhan University, Wuhan, 430074 (China); Yuan Longyan; Liu Nishuang; Long Hao; Zhao Xingzhong [Department of Electronic Science and Technology, School of Physical Science and Technology, Wuhan University, Wuhan, 430074 (China)

    2010-05-31

    Polycrystalline p-type Cu{sub x}O films were deposited after the growth of HfO{sub 2} dielectric on Si substrate by pulsed laser deposition, and Cu{sub x}O metal-oxide-semiconductor (MOS) capacitors with HfO{sub 2}/SiO{sub 2} stack gate dielectric were primarily fabricated and investigated. X-ray diffraction and X-ray photoelectron spectroscopy were applied to analyze crystalline structure and Cu{sup +}/Cu{sup 2+} ratios of Cu{sub x}O films respectively. SiO{sub 2} interlayer formed between the high-{kappa} dielectric and substrate was estimated by the transmission electron microscope. Results of electrical characteristic measurement indicate that the permittivity of HfO{sub 2} is about 22, and the gate leakage current density of MOS capacitor with 11.3 nm HfO{sub 2}/SiO{sub 2} stack dielectrics is {approx} 10{sup -4} A/cm{sup 2}. Results also show that the annealing in N{sub 2} can improve the quality of Cu{sub x}O/HfO{sub 2} interface and thus reduce the gate leakage density.

  19. Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors.

    Science.gov (United States)

    Chen, Fa-Hsyang; Her, Jim-Long; Shao, Yu-Hsuan; Matsuda, Yasuhiro H; Pan, Tung-Ming

    2013-01-08

    In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric.

  20. Radiation-induced interface state generation in MOS devices with reoxidised nitrided SiO2 gate dielectrics

    International Nuclear Information System (INIS)

    Lo, G.Q.; Shih, D.K.; Ting, W.; Kwong, D.L.

    1989-01-01

    In this letter, the radiation-induced interface state generation ΔD it in MOS devices with reoxidised nitrided gate oxides has been studied. The reoxidised nitrided oxides were fabricated by rapid thermal reoxidation (RTO) of rapidly thermal nitrided (RTN) SiO 2 . The devices were irradiated by exposure to X-rays at doses of 0.5-5.0 Mrad (Si). It is found that the RTO process improves the radiation hardness of RTN oxides in terms of interface state generation. The enhanced interface ''hardness'' of reoxidised nitrided oxides is attributed to the strainless interfacial oxide regrowth or reduction of hydrogen concentration during RTO of RTN oxides. (author)

  1. Poole Frenkel current and Schottky emission in SiN gate dielectric in AlGaN/GaN metal insulator semiconductor heterostructure field effect transistors

    Science.gov (United States)

    Hanna, Mina J.; Zhao, Han; Lee, Jack C.

    2012-10-01

    We analyze the anomalous I-V behavior in SiN prepared by plasma enhanced chemical vapor deposition for use as a gate insulator in AlGaN/GaN metal insulator semiconductor heterostructure filed effect transistors (HFETs). We observe leakage current across the dielectric with opposite polarity with respect to the applied electric field once the voltage sweep reaches a level below a determined threshold. This is observed as the absolute minimum of the leakage current does not occur at minimum voltage level (0 V) but occurs earlier in the sweep interval. Curve-fitting analysis suggests that the charge-transport mechanism in this region is Poole-Frenkel current, followed by Schottky emission due to band bending. Despite the current anomaly, the sample devices have shown a notable reduction of leakage current of over 2 to 6 order of magnitudes compared to the standard Schottky HFET. We show that higher pressures and higher silane concentrations produce better films manifesting less trapping. This conforms to our results that we reported in earlier publications. We found that higher chamber pressure achieves higher sheet carrier concentration that was found to be strongly dependent on the trapped space charge at the SiN/GaN interface. This would suggest that a lower chamber pressure induces more trap states into the SiN/GaN interface.

  2. Synthesis and electrical characterization of low-temperature thermal-cured epoxy resin/functionalized silica hybrid-thin films for application as gate dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Na, Moonkyong, E-mail: nmk@keri.re.kr [HVDC Research Division, Korea Electrotechnology Research Institute, Changwon, 642-120 (Korea, Republic of); System on Chip Chemical Process Research Center, Department of Chemical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, 790-784 (Korea, Republic of); Kang, Young Taec [Creative and Fundamental Research Division, Korea Electrotechnology Research Institute, Changwon, 642-120 (Korea, Republic of); Department of Polymer Science and Engineering, Pusan National University, Busan, 609-735 (Korea, Republic of); Kim, Sang Cheol [HVDC Research Division, Korea Electrotechnology Research Institute, Changwon, 642-120 (Korea, Republic of); Kim, Eun Dong [Creative and Fundamental Research Division, Korea Electrotechnology Research Institute, Changwon, 642-120 (Korea, Republic of)

    2013-07-31

    Thermal-cured hybrid materials were synthesized from homogenous hybrid sols of epoxy resins and organoalkoxysilane-functionalized silica. The chemical structures of raw materials and obtained hybrid materials were characterized using Fourier transform infrared spectroscopy. The thermal resistance of the hybrids was enhanced by hybridization. The interaction between epoxy matrix and the silica particles, which caused hydrogen bonding and van der Waals force was strengthened by organoalkoxysilane. The degradation temperature of the hybrids was improved by approximately 30 °C over that of the parent epoxy material. The hybrid materials were formed into uniformly coated thin films of about 50 nm-thick using a spin coater. An optimum mixing ratio was used to form smooth-surfaced hybrid films. The electrical property of the hybrid film was characterized, and the leakage current was found to be well below 10{sup −6} A cm{sup −2}. - Highlights: • Preparation of thermal-curable hybrid materials using epoxy resin and silica. • The thermal stability was enhanced through hybridization. • The insulation property of hybrid film was investigated as gate dielectrics.

  3. Stability and band offsets between c-plane ZnO semiconductor and LaAlO3 gate dielectric

    Science.gov (United States)

    Wang, Jianli; Chen, Xinfeng; Wu, Shuyin; Tang, Gang; Zhang, Junting; Stampfl, C.

    2018-03-01

    Wurtzite-perovskite heterostructures composed of a high dielectric constant oxide and a wide bandgap semiconductor envision promising applications in field-effect transistors. In the present paper, the structural and electronic properties of LaAlO3/ZnO heterojunctions are investigated by first-principles calculations. We study the initial adsorption of La, Al, and oxygen atoms on ZnO (0001) and (000 1 ¯ ) surfaces and find that La atoms may occupy interstitial sites during the growth of stoichiometric ZnO (0001). The band gap of the stoichiometric ZnO (0001) surface is smaller than that of the stoichiometric ZnO (000 1 ¯ ) surface. The surface formation energy indicates that La or Al atoms may substitute Zn atoms at the nonstoichiometric ZnO (0001) surface. The atomic charges, electronic density of states, and band offsets are analyzed for the optimized LaAlO3/ZnO heterojunctions. There is a band gap for the LaAlO3/ZnO (000 1 ¯ ) heterostructures, and the largest variation in charge occurs at the surface or interface. Our results suggest that the Al-terminated LaAlO3/ZnO (000 1 ¯ ) interfaces are suitable for the design of metal oxide semiconductor devices because the valence and conduction band offsets are both larger than 1 eV and the interface does not produce any in-gap states.

  4. Logic circuits composed of flexible carbon nanotube thin-film transistor and ultra-thin polymer gate dielectric

    Science.gov (United States)

    Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu

    2016-05-01

    Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V-1 sec-1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.

  5. Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

    Science.gov (United States)

    Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

    2009-08-01

    This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

  6. Analytical Modeling of Triple-Metal Hetero-Dielectric DG SON TFET

    Science.gov (United States)

    Mahajan, Aman; Dash, Dinesh Kumar; Banerjee, Pritha; Sarkar, Subir Kumar

    2018-02-01

    In this paper, a 2-D analytical model of triple-metal hetero-dielectric DG TFET is presented by combining the concepts of triple material gate engineering and hetero-dielectric engineering. Three metals with different work functions are used as both front- and back gate electrodes to modulate the barrier at source/channel and channel/drain interface. In addition to this, front gate dielectric consists of high-K HfO2 at source end and low-K SiO2 at drain side, whereas back gate dielectric is replaced by air to further improve the ON current of the device. Surface potential and electric field of the proposed device are formulated solving 2-D Poisson's equation and Young's approximation. Based on this electric field expression, tunneling current is obtained by using Kane's model. Several device parameters are varied to examine the behavior of the proposed device. The analytical model is validated with TCAD simulation results for proving the accuracy of our proposed model.

  7. Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

    Science.gov (United States)

    Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

    2018-06-01

    The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

  8. ALD TiO x as a top-gate dielectric and passivation layer for InGaZnO115 ISFETs

    Science.gov (United States)

    Pavlidis, S.; Bayraktaroglu, B.; Leedy, K.; Henderson, W.; Vogel, E.; Brand, O.

    2017-11-01

    The suitability of atomic layer deposited (ALD) titanium oxide (TiO x ) as a top gate dielectric and passivation layer for indium gallium zinc oxide (InGaZnO115) ion sensitive field effect transistors (ISFETs) is investigated. TiO x is an attractive barrier material, but reports of its use for InGaZnO thin film transistor (TFT) passivation have been conflicting thus far. In this work, it is found that the passivated TFT’s behavior depends on the TiO x deposition temperature, affecting critical device characteristics such as threshold voltage, field-effect mobility and sub-threshold swing. An O2 annealing step is required to recover TFT performance post passivation. It is also observed that the positive bias stress response of the passivated TFTs improves compared the original bare device. Secondary ion mass spectroscopy excludes the effects of hydrogen doping and inter-diffusion as sources of the temperature-dependent performance change, therefore indicating that oxygen gettering induced by TiO x passivation is the likely source of oxygen vacancies and, consequently, carriers in the InGaZnO film. It is also shown that potentiometric sensing using ALD TiO x exhibits a near Nernstian response to pH change, as well as minimizes V TH drift in TiO x passivated InGaZnO TFTs immersed in an acidic liquid. These results add to the understanding of InGaZnO passivation effects and underscore the potential for low-temperature fabricated InGaZnO ISFETs to be used as high-performance mobile chemical sensors.

  9. Electrical characteristics of AlO{sub x}N{sub y} prepared by oxidation of sub-10-nm-thick AlN films for MOS gate dielectric applications

    Energy Technology Data Exchange (ETDEWEB)

    Jeon, Sang Hun; Jang, Hyeon Woo; Kim, Hyun Soo; Noh, Do Young; Hwang, Hyun Sang [Kwangju Institute of Science and Technology, Kwangju (Korea, Republic of)

    2000-12-01

    In this research, the feasibility of ultrathin AlO{sub x}N{sub y} prepared by oxidation of sub 100-A-thick AlN thin films for metal-oxide-semiconductor (MOS) gate dielectric applications was investigated. Oxidation of 51-A-and 98-A-thick as-deposited AlN at 800 .deg. C was used to form 72-A-and 130-A-thick AlO{sub x}N{sub y}, respectively. Based on the capacitance-voltage (C-V) measurements of the MOS capacitor, the dielectric constants of 72 A-thick and 130 A-thick Al-oxynitride were 5.15 and 7, respectively. The leakage current of Al-oxynitride at low field was almost the same as that of thermal SiO{sub 2}. based on the CV data, the interface state density of Al-oxynitride was relatively higher than that of SiO{sub 2}. Although process optimization is still necessary, the Al-oxynitride exhibits some possibility for future MOS gate dielectric applications.

  10. Electrical characteristics of AlO sub x N sub y prepared by oxidation of sub-10-nm-thick AlN films for MOS gate dielectric applications

    CERN Document Server

    Jeon, S H; Kim, H S; Noh, D Y; Hwang, H S

    2000-01-01

    In this research, the feasibility of ultrathin AlO sub x N sub y prepared by oxidation of sub 100-A-thick AlN thin films for metal-oxide-semiconductor (MOS) gate dielectric applications was investigated. Oxidation of 51-A-and 98-A-thick as-deposited AlN at 800 .deg. C was used to form 72-A-and 130-A-thick AlO sub x N sub y , respectively. Based on the capacitance-voltage (C-V) measurements of the MOS capacitor, the dielectric constants of 72 A-thick and 130 A-thick Al-oxynitride were 5.15 and 7, respectively. The leakage current of Al-oxynitride at low field was almost the same as that of thermal SiO sub 2. based on the CV data, the interface state density of Al-oxynitride was relatively higher than that of SiO sub 2. Although process optimization is still necessary, the Al-oxynitride exhibits some possibility for future MOS gate dielectric applications.

  11. Low dielectric constant-based organic field-effect transistors and metal-insulator-semiconductor capacitors

    Science.gov (United States)

    Ukah, Ndubuisi Benjamin

    This thesis describes a study of PFB and pentacene-based organic field-effect transistors (OFET) and metal-insulator-semiconductor (MIS) capacitors with low dielectric constant (k) poly(methyl methacrylate) (PMMA), poly(4-vinyl phenol) (PVP) and cross-linked PVP (c-PVP) gate dielectrics. A physical method -- matrix assisted pulsed laser evaporation (MAPLE) -- of fabricating all-polymer field-effect transistors and MIS capacitors that circumvents inherent polymer dissolution and solvent-selectivity problems, is demonstrated. Pentacene-based OFETs incorporating PMMA and PVP gate dielectrics usually have high operating voltages related to the thickness of the dielectric layer. Reduced PMMA layer thickness (≤ 70 nm) was obtained by dissolving the PMMA in propylene carbonate (PC). The resulting pentacene-based transistors exhibited very low operating voltage (below -3 V), minimal hysteresis in their transfer characteristics, and decent electrical performance. Also low voltage (within -2 V) operation using thin (≤ 80 nm) low-k and hydrophilic PVP and c-PVP dielectric layers obtained via dissolution in high dipole moment and high-k solvents -- PC and dimethyl sulfoxide (DMSO), is demonstrated to be a robust means of achieving improved electrical characteristics and high operational stability in OFETs incorporating PVP and c-PVP dielectrics.

  12. Temperature-dependent field-effect carrier mobility in organic thin-film transistors with a gate SiO2 dielectric modified by H2O2 treatment

    Science.gov (United States)

    Lin, Yow-Jon; Hung, Cheng-Chun

    2018-02-01

    The effect of the modification of a gate SiO2 dielectric using an H2O2 solution on the temperature-dependent behavior of carrier transport for pentacene-based organic thin-film transistors (OTFTs) is studied. H2O2 treatment leads to the formation of Si(-OH) x (i.e., the formation of a hydroxylated layer) on the SiO2 surface that serves to reduce the SiO2 capacitance and weaken the pentacene-SiO2 interaction, thus increasing the field-effect carrier mobility ( µ) in OTFTs. The temperature-dependent behavior of carrier transport is dominated by the multiple trapping model. Note that H2O2 treatment leads to a reduction in the activation energy. The increased value of µ is also attributed to the weakening of the interactions of the charge carriers with the SiO2 dielectric that serves to reduce the activation energy.

  13. The Performance Improvement of N2 Plasma Treatment on ZrO2 Gate Dielectric Thin-Film Transistors with Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition IGZO Channel.

    Science.gov (United States)

    Wu, Chien-Hung; Huang, Bo-Wen; Chang, Kow-Ming; Wang, Shui-Jinn; Lin, Jian-Hong; Hsu, Jui-Mei

    2016-06-01

    The aim of this paper is to illustrate the N2 plasma treatment for high-κ ZrO2 gate dielectric stack (30 nm) with indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs). Experimental results reveal that a suitable incorporation of nitrogen atoms could enhance the device performance by eliminating the oxygen vacancies and provide an amorphous surface with better surface roughness. With N2 plasma treated ZrO2 gate, IGZO channel is fabricated by atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) technique. The best performance of the AP-PECVD IGZO TFTs are obtained with 20 W-90 sec N2 plasma treatment with field-effect mobility (μ(FET)) of 22.5 cm2/V-s, subthreshold swing (SS) of 155 mV/dec, and on/off current ratio (I(on)/I(off)) of 1.49 x 10(7).

  14. Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation

    Science.gov (United States)

    Seema; Chauhan, Sudakar Singh

    2018-05-01

    In this paper, we demonstrate the double gate vertical tunnel field-effect transistor using homo/hetero dielectric buried oxide (HDB) to obtain the optimized device characteristics. In this concern, the existence of double gate, HDB and electrode work-function engineering enhances DC performance and Analog/RF performance. The use of electrostatic doping helps to achieve higher on-current owing to occurrence of higher tunneling generation rate of charge carriers at the source/epitaxial interface. Further, lightly doped drain region and high- k dielectric below channel and drain region are responsible to suppress the ambipolar current. Simulated results clarifies that proposed device have achieved the tremendous performance in terms of driving current capability, steeper subthreshold slope (SS), drain induced barrier lowering (DIBL), hot carrier effects (HCEs) and high frequency parameters for better device reliability.

  15. Effect of Dielectric Interface on the Performance of MoS2 Transistors.

    Science.gov (United States)

    Li, Xuefei; Xiong, Xiong; Li, Tiaoyang; Li, Sichao; Zhang, Zhenfeng; Wu, Yanqing

    2017-12-27

    Because of their wide bandgap and ultrathin body properties, two-dimensional materials are currently being pursued for next-generation electronic and optoelectronic applications. Although there have been increasing numbers of studies on improving the performance of MoS 2 field-effect transistors (FETs) using various methods, the dielectric interface, which plays a decisive role in determining the mobility, interface traps, and thermal transport of MoS 2 FETs, has not been well explored and understood. In this article, we present a comprehensive experimental study on the effect of high-k dielectrics on the performance of few-layer MoS 2 FETs from 300 to 4.3 K. Results show that Al 2 O 3 /HfO 2 could boost the mobility and drain current. Meanwhile, MoS 2 transistors with Al 2 O 3 /HfO 2 demonstrate a 2× reduction in oxide trap density compared to that of the devices with the conventional SiO 2 substrate. Also, we observe a negative differential resistance effect on the device with 1 μm-channel length when using conventional SiO 2 as the gate dielectric due to self-heating, and this is effectively eliminated by using the Al 2 O 3 /HfO 2 gate dielectric. This dielectric engineering provides a highly viable route to realizing high-performance transition metal dichalcogenide-based FETs.

  16. Fabrication of amorphous InGaZnO thin-film transistor with solution processed SrZrO3 gate insulator

    Science.gov (United States)

    Takahashi, Takanori; Oikawa, Kento; Hoga, Takeshi; Uraoka, Yukiharu; Uchiyama, Kiyoshi

    2017-10-01

    In this paper, we describe a method of fabrication of thin film transistors (TFTs) with high dielectric constant (high-k) gate insulator by a solution deposition. We chose a solution processed SrZrO3 as a gate insulator material, which possesses a high dielectric constant of 21 with smooth surface. The IGZO-TFT with solution processed SrZrO3 showed good switching property and enough saturation features, i.e. field effect mobility of 1.7cm2/Vs, threshold voltage of 4.8V, sub-threshold swing of 147mV/decade, and on/off ratio of 2.3×107. Comparing to the TFTs with conventional SiO2 gate insulator, the sub-threshold swing was improved by smooth surface and high field effect due to the high dielectric constant of SrZrO3. These results clearly showed that use of solution processed high-k SrZrO3 gate insulator could improve sub-threshold swing. In addition, the residual carbon originated from organic precursors makes TFT performances degraded.

  17. Insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor devices with Al2O3 or AlTiO gate dielectrics

    Science.gov (United States)

    Le, Son Phuong; Nguyen, Duong Dai; Suzuki, Toshi-kazu

    2018-01-01

    We have investigated insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor (MIS) devices with Al2O3 or AlTiO (an alloy of Al2O3 and TiO2) gate dielectrics obtained by atomic layer deposition on AlGaN. Analyzing insulator-thickness dependences of threshold voltages for the MIS devices, we evaluated positive interface fixed charges, whose density at the AlTiO/AlGaN interface is significantly lower than that at the Al2O3/AlGaN interface. This and a higher dielectric constant of AlTiO lead to rather shallower threshold voltages for the AlTiO gate dielectric than for Al2O3. The lower interface fixed charge density also leads to the fact that the two-dimensional electron concentration is a decreasing function of the insulator thickness for AlTiO, whereas being an increasing function for Al2O3. Moreover, we discuss the relationship between the interface fixed charges and interface states. From the conductance method, it is shown that the interface state densities are very similar at the Al2O3/AlGaN and AlTiO/AlGaN interfaces. Therefore, we consider that the lower AlTiO/AlGaN interface fixed charge density is not owing to electrons trapped at deep interface states compensating the positive fixed charges and can be attributed to a lower density of oxygen-related interface donors.

  18. Observation of band bending of metal/high-k Si capacitor with high energy x-ray photoemission spectroscopy and its application to interface dipole measurement

    Science.gov (United States)

    Kakushima, K.; Okamoto, K.; Tachi, K.; Song, J.; Sato, S.; Kawanago, T.; Tsutsui, K.; Sugii, N.; Ahmet, P.; Hattori, T.; Iwai, H.

    2008-11-01

    Band bendings of Si substrates have been observed using hard x-ray photoemission spectroscopy. With a capability of collecting photoelectrons generated as deep as 40 nm, the binding energy shift in a core level caused by the potential profile at the surface of the substrate results in a spectrum broadening. The broadening is found to be significant when heavily doped substrates are used owing to its steep potential profile. The surface potential of the substrate can be obtained by deconvolution of the spectrum. This method has been applied to observe the band bending profile of metal-oxide-semiconductor capacitors with high-k gate dielectrics. By comparing the band bending profiles of heavily-doped n+- and p+-Si substrates, the interface dipoles presented at interfaces can be estimated. In the case of W gated La2O3/La-silicate capacitor, an interface dipole to shift the potential of -0.45 V has been estimated at La-silicate/Si interface, which effectively reduces the apparent work function of W. On the other hand, an interface dipole of 0.03-0.07 V has been found to exist at Hf-silicate/SiO2 interface for W gated HfO2/Hf-silicate/SiO2 capacitor.

  19. Physical and electrical characteristics of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with rare earth Er2O3 as a gate dielectric

    International Nuclear Information System (INIS)

    Lin, Ray-Ming; Chu, Fu-Chuan; Das, Atanu; Liao, Sheng-Yu; Chou, Shu-Tsun; Chang, Liann-Be

    2013-01-01

    In this study, the rare earth erbium oxide (Er 2 O 3 ) was deposited using an electron beam onto an AlGaN/GaN heterostructure to fabricate metal-oxide-semiconductor high-electron-mobility transistors (MOS–HEMTs) that exhibited device performance superior to that of a conventional HEMT. Under similar bias conditions, the gate leakage currents of these MOS–HEMT devices were four orders of magnitude lower than those of conventional Schottky gate HEMTs. The measured sub-threshold swing (SS) and the effective trap state density (N t ) of the MOS–HEMT were 125 mV/decade and 4.3 × 10 12 cm −2 , respectively. The dielectric constant of the Er 2 O 3 layer in this study was 14, as determined through capacitance–voltage measurements. In addition, the gate–source reverse breakdown voltage increased from –166 V for the conventional HEMT to –196 V for the Er 2 O 3 MOS–HEMT. - Highlights: ► GaN/AlGaN/Er 2 O 3 metal-oxide semiconductor high electron mobility transistor ► Physical and electrical characteristics are presented. ► Electron beam evaporated Er 2 O 3 with excellent surface roughness ► Device exhibits reduced gate leakage current and improved I ON /I OFF ratio

  20. Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure.

    Directory of Open Access Journals (Sweden)

    Z N Khan

    Full Text Available Metal Oxide Semiconductor (MOS capacitors (MOSCAP have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer, time-temperature cycle and sequence are key parameters influencing the device's output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application.

  1. Band Alignment and Optical Properties of (ZrO20.66(HfO20.34 Gate Dielectrics Thin Films on p-Si (100

    Directory of Open Access Journals (Sweden)

    Dahlang Tahir

    2011-11-01

    Full Text Available (ZrO20.66(HfO20.34 dielectric films on p-Si (100 were grown by atomic layer deposition method, for which the conduction band offsets, valence band offsets and band gaps were obtained by using X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy. The band gap, valence and conduction band offset values for (ZrO20.66(HfO20.34 dielectric thin film, grown on Si substrate were about 5.34, 2.35 and 1.87 eV respectively. This band alignment was similar to that of ZrO2. In addition, The dielectric function ε (k, ω, index of refraction n and the extinction coefficient k for the (ZrO20.66(HfO20.34 thin films were obtained from a quantitative analysis of REELS data by comparison to detailed dielectric response model calculations using the QUEELS-ε (k,ω-REELS software package. These optical properties are similar with ZrO2 dielectric thin films.

  2. SEMICONDUCTOR TECHNOLOGY: TaN wet etch for application in dual-metal-gate integration technology

    Science.gov (United States)

    Yongliang, Li; Qiuxia, Xu

    2009-12-01

    Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and Jg-Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.

  3. Effects of N{sub 2} and NH{sub 3} remote plasma nitridation on the structural and electrical characteristics of the HfO{sub 2} gate dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Park, K.-S., E-mail: kunsik@etri.re.kr [RFID/USN Research Department, Electronics and Telecommunications Research Institute, Daejeon 305-700 (Korea, Republic of); Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Daejeon 305-701 (Korea, Republic of); Baek, K.-H.; Kim, D.P.; Woo, J.-C.; Do, L.-M. [RFID/USN Research Department, Electronics and Telecommunications Research Institute, Daejeon 305-700 (Korea, Republic of); No, K.-S. [Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Daejeon 305-701 (Korea, Republic of)

    2010-12-01

    The remote plasma nitridation (RPN) of an HfO{sub 2} film using N{sub 2} and NH{sub 3} has been investigated comparatively. X-ray photoelectron spectroscopy and Auger electron spectroscopy analyses after post-deposition annealing (PDA) at 700 deg. C show that a large amount of nitrogen is present in the bulk film as well as in the interfacial layer for the HfO{sub 2} film nitrided with NH{sub 3}-RPN. It is also shown that the interfacial layer formed during RPN and PDA is a nitrogen-rich Hf-silicate. The C-V characteristics of an HfO{sub x}N{sub y} gate dielectric nitrided with NH{sub 3}-RPN have a smaller equivalent oxide thickness than that nitrided with N{sub 2}-RPN in spite of its thicker interfacial layer.

  4. Improved linearity and reliability in GaN metal-oxide-semiconductor high-electron-mobility transistors using nanolaminate La2O3/SiO2 gate dielectric

    Science.gov (United States)

    Hsu, Ching-Hsiang; Shih, Wang-Cheng; Lin, Yueh-Chin; Hsu, Heng-Tung; Hsu, Hisang-Hua; Huang, Yu-Xiang; Lin, Tai-Wei; Wu, Chia-Hsun; Wu, Wen-Hao; Maa, Jer-Shen; Iwai, Hiroshi; Kakushima, Kuniyuki; Chang, Edward Yi

    2016-04-01

    Improved device performance to enable high-linearity power applications has been discussed in this study. We have compared the La2O3/SiO2 AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with other La2O3-based (La2O3/HfO2, La2O3/CeO2 and single La2O3) MOS-HEMTs. It was found that forming lanthanum silicate films can not only improve the dielectric quality but also can improve the device characteristics. The improved gate insulation, reliability, and linearity of the 8 nm La2O3/SiO2 MOS-HEMT were demonstrated.

  5. Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics on Flexible Substrates

    Science.gov (United States)

    Tetzner, Kornelius; Bose, Indranil R.; Bock, Karlheinz

    2014-01-01

    In this work, the insulating properties of poly(4-vinylphenol) (PVP) and SU-8 (MicroChem, Westborough, MA, USA) dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP) using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor. PMID:28788243

  6. Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics onFlexible Substrates

    Directory of Open Access Journals (Sweden)

    Kornelius Tetzner

    2014-10-01

    Full Text Available In this work, the insulating properties of poly(4-vinylphenol (PVP and SU-8 (MicroChem, Westborough, MA, USA dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor.

  7. Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics onFlexible Substrates.

    Science.gov (United States)

    Tetzner, Kornelius; Bose, Indranil R; Bock, Karlheinz

    2014-10-29

    In this work, the insulating properties of poly(4-vinylphenol) (PVP) and SU-8 (MicroChem, Westborough, MA, USA) dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP) using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor.

  8. Suppression of subthreshold characteristics variation for junctionless multigate transistors using high-k spacers

    International Nuclear Information System (INIS)

    Lou, Haijun; Zhang, Baili; Li, Dan; Lin, Xinnan; He, Jin; Chan, Mansun

    2015-01-01

    In this work, the high-k spacer is proposed to suppress the subthreshold characteristics variation of junctionless multigate transistor (JMT) with non-ideal sidewall angle for the first time. It is demonstrated that the variation of subthreshold characteristics induced by the changing sidewall angle is efficiently suppressed by high-k spacers due to the enhanced corner effect through the fringe capacitance, and the electrostatic integrity of JMTs is also improved at sub-22 nm gate length. Two key parameters of high-k spacer, the thickness and length, have been optimized in terms of the suppression of subthreshold characteristics variation. Then their optimal values are proposed. The benefit of high-k spacer makes JMTs more scalable. (paper)

  9. Bimodal gate-dielectric deposition for improved performance of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

    International Nuclear Information System (INIS)

    Pang Liang; Kim, Kyekyoon

    2012-01-01

    A bimodal deposition scheme combining radiofrequency magnetron sputtering and plasma enhanced chemical vapour deposition (PECVD) is proposed as a means for improving the performance of GaN-based metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs). High-density sputtered-SiO 2 is utilized to reduce the gate leakage current and enhance the breakdown voltage while low-density PECVD-SiO 2 is employed to buffer the sputtering damage and further increase the drain current by engineering the stress-induced-polarization. Thus-fabricated MOSHEMT exhibited a low leakage current of 4.21 × 10 -9 A mm -1 and high breakdown voltage of 634 V for a gate-drain distance of 6 µm, demonstrating the promise of bimodal-SiO 2 deposition scheme for the development of GaN-based MOSHEMTs for high-power application. (paper)

  10. Theoretical and Experimental Studies of New Polymer-Metal High-Dielectric Constant Nanocomposites

    Science.gov (United States)

    Ginzburg, Valeriy; Elwell, Michael; Myers, Kyle; Cieslinski, Robert; Malowinski, Sarah; Bernius, Mark

    2006-03-01

    High-dielectric-constant (high-K) gate materials are important for the needs of electronics industry. Most polymers have dielectric constant in the range 2 materials with K > 10 it is necessary to combine polymers with ceramic or metal nanoparticles. Several formulations based on functionalized Au-nanoparticles (R ˜ 5 -— 10 nm) and PMMA matrix polymer are prepared. Nanocomposite films are subsequently cast from solution. We study the morphology of those nanocomposites using theoretical (Self-Consistent Mean-Field Theory [SCMFT]) and experimental (Transmission Electron Microscopy [TEM]) techniques. Good qualitative agreement between theory and experiment is found. The study validates the utility of SCMFT as screening tool for the preparation of stable (or at least metastable) polymer/nanoparticle mixtures.

  11. Atomic layer deposition grown composite dielectric oxides and ZnO for transparent electronic applications

    International Nuclear Information System (INIS)

    Gieraltowska, S.; Wachnicki, L.; Witkowski, B.S.; Godlewski, M.; Guziewicz, E.

    2012-01-01

    In this paper, we report on transparent transistor obtained using laminar structure of two high-k dielectric oxides (hafnium dioxide, HfO 2 and aluminum oxide, Al 2 O 3 ) and zinc oxide (ZnO) layer grown at low temperature (60 °C–100 °C) using Atomic Layer Deposition (ALD) technology. Our research was focused on the optimization of technological parameters for composite layers Al 2 O 3 /HfO 2 /Al 2 O 3 for thin film transistor structures with ZnO as a channel and a gate layer. We elaborate on the ALD growth of these oxides, finding that the 100 nm thick layers of HfO 2 and Al 2 O 3 exhibit fine surface flatness and required amorphous microstructure. Growth parameters are optimized for the monolayer growth mode and maximum smoothness required for gating.

  12. Enhanced dielectric properties of ZrO2 thin films prepared in nitrogen ambient by pulsed laser deposition

    International Nuclear Information System (INIS)

    Zhu, J; Li, T L; Pan, B; Zhou, L; Liu, Z G

    2003-01-01

    ZrO 2 thin films were fabricated in O 2 ambient and in N 2 ambient by pulsed laser deposition (PLD), respectively. X-ray diffraction revealed that films prepared at 400 deg. C remained amorphous. The dielectric properties of amorphous ZrO 2 films were investigated by measuring the capacitance-frequency characteristics of Pt/ZrO 2 /Pt capacitor structures. The dielectric constant of the films deposited in N 2 ambient was larger than that of the films deposited in O 2 ambient. The dielectric loss was lower for films prepared in N 2 ambient. Atom force microscopy investigation indicated that films deposited in N 2 ambient had smoother surface than films deposited in O 2 ambient. Capacitance-voltage and current-voltage characteristics were studied. The equivalent oxide thickness (EOT) of films with 6.6 nm physical thickness deposited in N 2 ambient is lower than that of films deposited in O 2 ambient. An EOT of 1.38 nm for the film deposited in N 2 ambient was obtained, while the leakage current density was 94.6 mA cm -2 . Therefore, ZrO 2 thins deposited in N 2 ambient have enhanced dielectric properties due to the incorporation of nitrogen which leads to the formation of Zr-doped nitride interfacial layer, and is suggested to be a potential material for alternative high-k (high dielectric constant) gate dielectric applications

  13. Dielectric material options for integrated capacitors

    NARCIS (Netherlands)

    Ruhl, G.; Lehnert, W.; Lukosius, M.; Wenger, C.; Baristiran Kaynak, C.; Blomberg, T.; Haukka, S.; Baumann, P.K.; Besling, W.F.A.; Roest, A.L.; Riou, B.; Lhostis, S.; Halimaou, A.; Roozeboom, F.; Langereis, E.; Kessels, W.M.M.; Zauner, A.; Rushworth, S.A.

    2014-01-01

    Future MIM capacitor generations will require significantly increased specific capacitances by utilization of high-k dielectric materials. In order to achieve high capacitance per chip area, these dielectrics have to be deposited in three-dimensional capacitor structures by ALD or AVD (atomic vapor

  14. Remote interfacial dipole scattering and electron mobility degradation in Ge field-effect transistors with GeO x /Al2O3 gate dielectrics

    Science.gov (United States)

    Wang, Xiaolei; Xiang, Jinjuan; Wang, Shengkai; Wang, Wenwu; Zhao, Chao; Ye, Tianchun; Xiong, Yuhua; Zhang, Jing

    2016-06-01

    Remote Coulomb scattering (RCS) on electron mobility degradation is investigated experimentally in Ge-based metal-oxide-semiconductor field-effect-transistors (MOSFETs) with GeO x /Al2O3 gate stacks. It is found that the mobility increases with greater GeO x thickness (7.8-20.8 Å). The physical origin of this mobility dependence on GeO x thickness is explored. The following factors are excluded: Coulomb scattering due to interfacial traps at GeO x /Ge, phonon scattering, and surface roughness scattering. Therefore, the RCS from charges in gate stacks is studied. The charge distributions in GeO x /Al2O3 gate stacks are evaluated experimentally. The bulk charges in Al2O3 and GeO x are found to be negligible. The density of the interfacial charge is  +3.2  ×  1012 cm-2 at the GeO x /Ge interface and  -2.3  ×  1012 cm-2 at the Al2O3/GeO x interface. The electric dipole at the Al2O3/GeO x interface is found to be  +0.15 V, which corresponds to an areal charge density of 1.9  ×  1013 cm-2. The origin of this mobility dependence on GeO x thickness is attributed to the RCS due to the electric dipole at the Al2O3/GeO x interface. This remote dipole scattering is found to play a significant role in mobility degradation. The discovery of this new scattering mechanism indicates that the engineering of the Al2O3/GeO x interface is key for mobility enhancement and device performance improvement. These results are helpful for understanding and engineering Ge mobility enhancement.

  15. Remote interfacial dipole scattering and electron mobility degradation in Ge field-effect transistors with GeOx/Al2O3 gate dielectrics

    International Nuclear Information System (INIS)

    Wang, Xiaolei; Xiang, Jinjuan; Wang, Shengkai; Wang, Wenwu; Zhao, Chao; Ye, Tianchun; Xiong, Yuhua; Zhang, Jing

    2016-01-01

    Remote Coulomb scattering (RCS) on electron mobility degradation is investigated experimentally in Ge-based metal–oxide–semiconductor field-effect-transistors (MOSFETs) with GeO x /Al 2 O 3 gate stacks. It is found that the mobility increases with greater GeO x thickness (7.8–20.8 Å). The physical origin of this mobility dependence on GeO x thickness is explored. The following factors are excluded: Coulomb scattering due to interfacial traps at GeO x /Ge, phonon scattering, and surface roughness scattering. Therefore, the RCS from charges in gate stacks is studied. The charge distributions in GeO x /Al 2 O 3 gate stacks are evaluated experimentally. The bulk charges in Al 2 O 3 and GeO x are found to be negligible. The density of the interfacial charge is  +3.2  ×  10 12 cm −2 at the GeO x /Ge interface and  −2.3  ×  10 12 cm −2 at the Al 2 O 3 /GeO x interface. The electric dipole at the Al 2 O 3 /GeO x interface is found to be  +0.15 V, which corresponds to an areal charge density of 1.9  ×  10 13 cm −2 . The origin of this mobility dependence on GeO x thickness is attributed to the RCS due to the electric dipole at the Al 2 O 3 /GeO x interface. This remote dipole scattering is found to play a significant role in mobility degradation. The discovery of this new scattering mechanism indicates that the engineering of the Al 2 O 3 /GeO x interface is key for mobility enhancement and device performance improvement. These results are helpful for understanding and engineering Ge mobility enhancement. (paper)

  16. Molecular-beam-deposited yttrium-oxide dielectrics in aluminum-gated metal - oxide - semiconductor field-effect transistors: Effective electron mobility

    International Nuclear Information System (INIS)

    Ragnarsson, L.-A degree.; Guha, S.; Copel, M.; Cartier, E.; Bojarczuk, N. A.; Karasinski, J.

    2001-01-01

    We report on high effective mobilities in yttrium-oxide-based n-channel metal - oxide - semiconductor field-effect transistors (MOSFETs) with aluminum gates. The yttrium oxide was grown in ultrahigh vacuum using a reactive atomic-beam-deposition system. Medium-energy ion-scattering studies indicate an oxide with an approximate composition of Y 2 O 3 on top of a thin layer of interfacial SiO 2 . The thickness of this interfacial oxide as well as the effective mobility are found to be dependent on the postgrowth anneal conditions. Optimum conditions result in mobilities approaching that of SiO 2 -based MOSFETs at higher fields with peak mobilities at approximately 210 cm 2 /Vs. [copyright] 2001 American Institute of Physics

  17. Implementation of atomic layer deposition-based AlON gate dielectrics in AlGaN/GaN MOS structure and its physical and electrical properties

    Science.gov (United States)

    Nozaki, Mikito; Watanabe, Kenta; Yamada, Takahiro; Shih, Hong-An; Nakazawa, Satoshi; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

    2018-06-01

    Alumina incorporating nitrogen (aluminum oxynitride; AlON) for immunity against charge injection was grown on a AlGaN/GaN substrate through the repeated atomic layer deposition (ALD) of AlN layers and in situ oxidation in ozone (O3) ambient under optimized conditions. The nitrogen distribution was uniform in the depth direction, the composition was controllable over a wide range (0.5–32%), and the thickness could be precisely controlled. Physical analysis based on synchrotron radiation X-ray photoelectron spectroscopy (SR-XPS) revealed that harmful intermixing at the insulator/AlGaN interface causing Ga out-diffusion in the gate stack was effectively suppressed by this method. AlON/AlGaN/GaN MOS capacitors were fabricated, and they had excellent electrical properties and immunity against electrical stressing as a result of the improved interface stability.

  18. Structural Evaluation of 5,5′-Bis(naphth-2-yl)-2,2′-bithiophene in Organic Field-Effect Transistors with n-Octadecyltrichlorosilane Coated SiO2 Gate Dielectric

    DEFF Research Database (Denmark)

    Lauritzen, Andreas E.; Torkkeli, Mika; Bikondoa, Oier

    2018-01-01

    We report on the structure and morphology of 5,5′-bis(naphth-2-yl)-2,2′-bithiophene (NaT2) films in bottom-contact organic field-effect transistors (OFETs) with octadecyltrichlorosilane (OTS) coated SiO2 gate dielectric, characterized by atomic force microscopy (AFM), grazing-incidence X......-ray diffraction (GIXRD), and electrical transport measurements. Three types of devices were investigated with the NaT2 thin-film deposited either on (1) pristine SiO2 (corresponding to higher surface energy, 47 mJ/m2) or on OTS deposited on SiO2 under (2) anhydrous or (3) humid conditions (corresponding to lower...... surface energies, 20–25 mJ/m2). NaT2 films grown on pristine SiO2 form nearly featureless three-dimensional islands. NaT2 films grown on OTS/SiO2 deposited under anhydrous conditions form staggered pyramid islands where the interlayer spacing corresponds to the size of the NaT2 unit cell. At the same time...

  19. High-k shallow traps observed by charge pumping with varying discharging times

    International Nuclear Information System (INIS)

    Ho, Szu-Han; Chen, Ching-En; Tseng, Tseung-Yuen; Chang, Ting-Chang; Lu, Ying-Hsin; Lo, Wen-Hung; Tsai, Jyun-Yu; Liu, Kuan-Ju; Wang, Bin-Wei; Cao, Xi-Xin; Chen, Hua-Mao; Cheng, Osbert; Huang, Cheng-Tung; Chen, Tsai-Fu

    2013-01-01

    In this paper, we investigate the influence of falling time and base level time on high-k bulk shallow traps measured by charge pumping technique in n-channel metal-oxide-semiconductor field-effect transistors with HfO 2 /metal gate stacks. N T -V high level characteristic curves with different duty ratios indicate that the electron detrapping time dominates the value of N T for extra contribution of I cp traps. N T is the number of traps, and I cp is charge pumping current. By fitting discharge formula at different temperatures, the results show that extra contribution of I cp traps at high voltage are in fact high-k bulk shallow traps. This is also verified through a comparison of different interlayer thicknesses and different Ti x N 1−x metal gate concentrations. Next, N T -V high level characteristic curves with different falling times (t falling time ) and base level times (t base level ) show that extra contribution of I cp traps decrease with an increase in t falling time . By fitting discharge formula for different t falling time , the results show that electrons trapped in high-k bulk shallow traps first discharge to the channel and then to source and drain during t falling time . This current cannot be measured by the charge pumping technique. Subsequent measurements of N T by charge pumping technique at t base level reveal a remainder of electrons trapped in high-k bulk shallow traps

  20. Effects of thermal annealing on the electrical characteristics of In-Ga-Zn-O thin-film transistors with Al2O3 gate dielectric

    International Nuclear Information System (INIS)

    Zhang, Wen-Peng; Chen, Sun; Qian, Shi-Bing; Ding, Shi-Jin

    2015-01-01

    We studied how the performance of In–Ga–Zn–O (IGZO) thin film transistors (TFTs) with Al 2 O 3 gate insulator was affected by post-fabrication annealing temperature and annealing time. At a fixed annealing time of 2 min, the IGZO TFT exhibited the best transfer and output characteristics in the case of 300 °C in N 2 atmosphere, which is attributed to the achievement of appropriate carrier concentration and Hall mobility in the IGZO film. Further, it was found that both of the carrier concentration and Hall mobility in the IGZO film increased with the increment of annealing temperature. For the annealing temperature of 300 °C, the performance of the IGZO TFT was further improved by extending annealing time to 5 min, i.e., the field effect mobility, sub-threshold swing and on/off current ratio were 11.6 cm 2 /(V · s), 0.42 V dec −1 and 10 6 , respectively. The underlying mechanism was discussed. (paper)

  1. Surface properties of SiO2 with and without H2O2 treatment as gate dielectrics for pentacene thin-film transistor applications

    Science.gov (United States)

    Hung, Cheng-Chun; Lin, Yow-Jon

    2018-01-01

    The effect of H2O2 treatment on the surface properties of SiO2 is studied. H2O2 treatment leads to the formation of Si(sbnd OH)x at the SiO2 surface that serves to reduce the number of trap states, inducing the shift of the Fermi level toward the conduction band minimum. H2O2 treatment also leads to a noticeable reduction in the value of the SiO2 capacitance per unit area. The effect of SiO2 layers with H2O2 treatment on the behavior of carrier transports for the pentacene/SiO2-based organic thin-film transistor (OTFT) is also studied. Experimental identification confirms that the shift of the threshold voltage towards negative gate-source voltages is due to the reduced number of trap states in SiO2 near the pentacene/SiO2 interface. The existence of a hydrogenated layer between pentacene and SiO2 leads to a change in the pentacene-SiO2 interaction, increasing the value of the carrier mobility.

  2. Photon-gated spin transistor

    OpenAIRE

    Li, Fan; Song, Cheng; Cui, Bin; Peng, Jingjing; Gu, Youdi; Wang, Guangyue; Pan, Feng

    2017-01-01

    Spin-polarized field-effect transistor (spin-FET), where a dielectric layer is generally employed for the electrical gating as the traditional FET, stands out as a seminal spintronic device under the miniaturization trend of electronics. It would be fundamentally transformative if optical gating was used for spin-FET. We report a new type of spin-polarized field-effect transistor (spin-FET) with optical gating, which is fabricated by partial exposure of the (La,Sr)MnO3 channel to light-emitti...

  3. High-K Strategy Scale: A Measure of the High-K Independent Criterion of Fitness

    Directory of Open Access Journals (Sweden)

    Cezar Giosan

    2006-01-01

    Full Text Available The present study aimed at testing whether factors documented in the literature as being indicators of a high-K reproductive strategy have effects on fitness in extant humans. A 26-item High-K Strategy Scale comprising these factors was developed and tested on 250 respondents. Items tapping into health and attractiveness, upward mobility, social capital and risks consideration, were included in the scale. As expected, the scale showed a significant correlation with perceived offspring quality and a weak, but significant association with actual number of children. The scale had a high reliability coefficient (Cronbach's Alpha = .92. Expected correlations were found between the scale and number of medical diagnoses, education, perceived social support, and number of previous marriages, strengthening the scale's construct validity. Implications of the results are discussed.

  4. Center for dielectric studies

    Science.gov (United States)

    Cross, L. E.; Newnham, R. E.; Biggers, J. V.

    1984-05-01

    This report focuses upon the parts of the Center program which have drawn most extensively upon Navy funds. In the basic study of polarization processes in high K dielectrics, major progress has been made in understanding the mechanisms in relaxor ferroelectric in the perovskite structure families. A new effort is also being mounted to obtain more precise evaluation of the internal stress effects in fine grained barium titanate. Related to reliability, studies of the effects of induced macro-defects are described, and preparation for the evaluation of space charge by internal potential distribution measurements discussed. To develop new processing methods for very thin dielectric layers, a new type of single barrier layer multilayer is discussed, and work on the thermal evaporation of oriented crystalline antimony sulphur iodide describe.

  5. Dielectric strength of SiO2 in a CMOS transistor structure

    International Nuclear Information System (INIS)

    Soden, J.M.

    1979-01-01

    The distribution of experimental dielectric strengths of SiO 2 gate dielectric in a CMOS transistor structure is shown to be composed of a primary, statistically-normal distribution of high dielectric strength and a secondary distribution spread through the lower dielectric strength region. The dielectric strength was not significantly affected by high level (1 x 10 6 RADS (Si)) gamma radiation or high temperature (200 0 C) stress. The primary distribution breakdowns occurred at topographical edges, mainly at the gate/field oxide interface, and the secondary distribution breakdowns occurred at random locations in the central region of the gate

  6. Ferroelectric dielectrics integrated on silicon

    CERN Document Server

    Defay, Emmanuel

    2013-01-01

    This book describes up-to-date technology applied to high-K materials for More Than Moore applications, i.e. microsystems applied to microelectronics core technologies.After detailing the basic thermodynamic theory applied to high-K dielectrics thin films including extrinsic effects, this book emphasizes the specificity of thin films. Deposition and patterning technologies are then presented. A whole chapter is dedicated to the major role played in the field by X-Ray Diffraction characterization, and other characterization techniques are also described such as Radio frequency characterizat

  7. High-k shallow traps observed by charge pumping with varying discharging times

    Energy Technology Data Exchange (ETDEWEB)

    Ho, Szu-Han; Chen, Ching-En; Tseng, Tseung-Yuen [Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang@mail.phys.nsysu.edu.tw [Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Tainan, Taiwan (China); Lu, Ying-Hsin; Lo, Wen-Hung; Tsai, Jyun-Yu; Liu, Kuan-Ju [Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Wang, Bin-Wei; Cao, Xi-Xin [Department of Embedded System Engineering, Peking University, Beijing, P.R.China (China); Chen, Hua-Mao [Department of Photonics and Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan (China); Cheng, Osbert; Huang, Cheng-Tung; Chen, Tsai-Fu [Device Department, United Microelectronics Corporation, Tainan Science Park, Taiwan (China)

    2013-11-07

    In this paper, we investigate the influence of falling time and base level time on high-k bulk shallow traps measured by charge pumping technique in n-channel metal-oxide-semiconductor field-effect transistors with HfO{sub 2}/metal gate stacks. N{sub T}-V{sub high} {sub level} characteristic curves with different duty ratios indicate that the electron detrapping time dominates the value of N{sub T} for extra contribution of I{sub cp} traps. N{sub T} is the number of traps, and I{sub cp} is charge pumping current. By fitting discharge formula at different temperatures, the results show that extra contribution of I{sub cp} traps at high voltage are in fact high-k bulk shallow traps. This is also verified through a comparison of different interlayer thicknesses and different Ti{sub x}N{sub 1−x} metal gate concentrations. Next, N{sub T}-V{sub high} {sub level} characteristic curves with different falling times (t{sub falling} {sub time}) and base level times (t{sub base} {sub level}) show that extra contribution of I{sub cp} traps decrease with an increase in t{sub falling} {sub time}. By fitting discharge formula for different t{sub falling} {sub time}, the results show that electrons trapped in high-k bulk shallow traps first discharge to the channel and then to source and drain during t{sub falling} {sub time}. This current cannot be measured by the charge pumping technique. Subsequent measurements of N{sub T} by charge pumping technique at t{sub base} {sub level} reveal a remainder of electrons trapped in high-k bulk shallow traps.

  8. Mechanisms for plasma etching of HfO{sub 2} gate stacks with Si selectivity and photoresist trimming

    Energy Technology Data Exchange (ETDEWEB)

    Shoeb, Juline; Kushner, Mark J. [Department of Electrical and Computer Engineering, Iowa State University, Ames, Iowa 50011 (United States); Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109-2122 (United States)

    2009-11-15

    To minimize leakage currents resulting from the thinning of the insulator in the gate stack of field effect transistors, high-dielectric constant (high-k) metal oxides, and HfO{sub 2} in particular, are being implemented as a replacement for SiO{sub 2}. To speed the rate of processing, it is desirable to etch the gate stack (e.g., metal gate, antireflection layers, and dielectric) in a single process while having selectivity to the underlying Si. Plasma etching using Ar/BCl{sub 3}/Cl{sub 2} mixtures effectively etches HfO{sub 2} while having good selectivity to Si. In this article, results from integrated reactor and feature scale modeling of gate-stack etching in Ar/BCl{sub 3}/Cl{sub 2} plasmas, preceded by photoresist trimming in Ar/O{sub 2} plasmas, are discussed. It was found that BCl{sub n} species react with HfO{sub 2}, which under ion impact, form volatile etch products such as B{sub m}OCl{sub n} and HfCl{sub n}. Selectivity to Si is achieved by creating Si-B bonding as a precursor to the deposition of a BCl{sub n} polymer which slows the etch rate relative to HfO{sub 2}. The low ion energies required to achieve this selectivity then challenge one to obtain highly anisotropic profiles in the metal gate portion of the stack. Validation was performed with data from literature. The effect of bias voltage and key reactant probabilities on etch rate, selectivity, and profile are discussed.

  9. Linear gate

    International Nuclear Information System (INIS)

    Suwono.

    1978-01-01

    A linear gate providing a variable gate duration from 0,40μsec to 4μsec was developed. The electronic circuity consists of a linear circuit and an enable circuit. The input signal can be either unipolar or bipolar. If the input signal is bipolar, the negative portion will be filtered. The operation of the linear gate is controlled by the application of a positive enable pulse. (author)

  10. Temperature behavior of electrical properties of high-k lead-magnesium-niobium titanate thin-films

    Energy Technology Data Exchange (ETDEWEB)

    Chen Wenbin, E-mail: cwb0201@163.com [Electromechanical Engineering College, Guilin University of Electronic Technology (China); McCarthy, Kevin G. [Department of Electrical and Electronic Engineering, University College Cork (Ireland); Copuroglu, Mehmet; O' Brien, Shane; Winfield, Richard; Mathewson, Alan [Tyndall National Institute, University College Cork (Ireland)

    2012-05-01

    This paper reports on the temperature dependence of the electrical properties of high-k lead-magnesium-niobium titanate thin films processed with different compositions (with and without nanoparticles) and with different annealing temperatures (450 Degree-Sign C and 750 Degree-Sign C). These characterization results support the ongoing investigation of the material's electrical properties which are necessary before the dielectric can be used in silicon-based IC applications.

  11. Sintering behaviour and microwave dielectric properties of a new ...

    Indian Academy of Sciences (India)

    Additionally, optimized microwave dielectric properties can be achieved for the speci- mens using ... compounds and/or their solid solutions have been investi- gated and applied in ... electron microscope (SEM, S-4800, Hitachi, Japan). The.

  12. Comparative analysis of the effects of tantalum doping and annealing on atomic layer deposited (Ta2O5)x(Al2O3)1−x as potential gate dielectrics for GaN/AlxGa1−xN/GaN high electron mobility transistors

    International Nuclear Information System (INIS)

    Partida-Manzanera, T.; Roberts, J. W.; Sedghi, N.; Potter, R. J.; Bhat, T. N.; Zhang, Z.; Tan, H. R.; Dolmanan, S. B.; Tripathy, S.

    2016-01-01

    This paper describes a method to optimally combine wide band gap Al 2 O 3 with high dielectric constant (high-κ) Ta 2 O 5 for gate dielectric applications. (Ta 2 O 5 ) x (Al 2 O 3 ) 1−x thin films deposited by thermal atomic layer deposition (ALD) on GaN-capped Al x Ga 1−x N/GaN high electron mobility transistor (HEMT) structures have been studied as a function of the Ta 2 O 5 molar fraction. X-ray photoelectron spectroscopy shows that the bandgap of the oxide films linearly decreases from 6.5 eV for pure Al 2 O 3 to 4.6 eV for pure Ta 2 O 5 . The dielectric constant calculated from capacitance-voltage measurements also increases linearly from 7.8 for Al 2 O 3 up to 25.6 for Ta 2 O 5 . The effect of post-deposition annealing in N 2 at 600 °C on the interfacial properties of undoped Al 2 O 3 and Ta-doped (Ta 2 O 5 ) 0.12 (Al 2 O 3 ) 0.88 films grown on GaN-HEMTs has been investigated. These conditions are analogous to the conditions used for source/drain contact formation in gate-first HEMT technology. A reduction of the Ga-O to Ga-N bond ratios at the oxide/HEMT interfaces is observed after annealing, which is attributed to a reduction of interstitial oxygen-related defects. As a result, the conduction band offsets (CBOs) of the Al 2 O 3 /GaN-HEMT and (Ta 2 O 5 ) 0.16 (Al 2 O 3 ) 0.84 /GaN-HEMT samples increased by ∼1.1 eV to 2.8 eV and 2.6 eV, respectively, which is advantageous for n-type HEMTs. The results demonstrate that ALD of Ta-doped Al 2 O 3 can be used to control the properties of the gate dielectric, allowing the κ-value to be increased, while still maintaining a sufficient CBO to the GaN-HEMT structure for low leakage currents

  13. A simulation-based proposed high-k heterostructure AlGaAs/Si junctionless n-type tunnel FET

    International Nuclear Information System (INIS)

    Rahi Shiromani Balmukund; Asthana Pranav; Ghosh Bahniman

    2014-01-01

    We propose a heterostructure junctionless tunnel field effect transistor (HJL-TFET) using AlGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain side. The whole AlGaAs/Si region is heavily doped n-type. The proposed HJL-TFET uses two isolated gates (named gate, gate1) with two different work functions (gate = 4.2 eV, gate1 = 5.2 eV respectively). The 2-D nature of HJL-TFET current flow is studied. The proposed structure is simulated in Silvaco with different gate dielectric materials. This structure exhibits a high on current in the range of 1.4 × 10 −6 A/μm, the off current remains as low as 9.1 × 10 −14 A/μm. So I ON /I OFF ratio of ≃ 10 8 is achieved. Point subthreshold swing has also been reduced to a value of ≃ 41 mV/decade for TiO 2 gate material. (semiconductor devices)

  14. Structural and optical properties of germanium nanostructures on Si(100 and embedded in high-k oxides

    Directory of Open Access Journals (Sweden)

    Ray Samit

    2011-01-01

    Full Text Available Abstract The structural and optical properties of Ge quantum dots (QDs grown on Si(001 for mid-infrared photodetector and Ge nanocrystals embedded in oxide matrices for floating gate memory devices are presented. The infrared photoluminescence (PL signal from Ge islands has been studied at a low temperature. The temperature- and bias-dependent photocurrent spectra of a capped Si/SiGe/Si(001 QDs infrared photodetector device are presented. The properties of Ge nanocrystals of different size and density embedded in high-k matrices grown using radio frequency magnetron sputtering have been studied. Transmission electron micrographs have revealed the formation of isolated spherical Ge nanocrystals in high-k oxide matrix of sizes ranging from 4 to 18 nm. Embedded nanocrystals in high band gap oxides have been found to act as discrete trapping sites for exchanging charge carriers with the conduction channel by direct tunneling that is desired for applications in floating gate memory devices.

  15. Flexible semi-transparent silicon (100) fabric with high-k/metal gate devices

    KAUST Repository

    Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

    2013-01-01

    (100) wafers and then released as continuous, mechanically flexible, optically semi-transparent and high thermal budget compatible silicon fabric with devices. This is the first ever demonstration with this set of materials which allows full degree

  16. Development of III-V p-MOSFETs with high-kappa gate stack for future CMOS applications

    Science.gov (United States)

    Nagaiah, Padmaja

    As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, non-silicon materials and new device architectures are gradually being introduced to improve Si integrated circuit performance and continue transistor scaling. Recently, the replacement of SiO2 with a high-k material (HfO2) as gate dielectric has essentially removed one of the biggest advantages of Si as channel material. As a result, alternate high mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. III-V materials in particular have become of great interest as channel materials, owing to their superior electron transport properties. However, there are several critical challenges that need to be addressed before III-V based CMOS can replace Si CMOS technology. Some of these challenges include development of a high quality, thermally stable gate dielectric/III-V interface, and improvement in III-V p-channel hole mobility to complement the n-channel mobility, low source/drain resistance and integration onto Si substrate. In this thesis, we would be addressing the first two issues i.e. the development high performance III-V p-channels and obtaining high quality III-V/high-k interface. We start with using the device architecture of the already established InGaAs n-channels as a baseline to understand the effect of remote scattering from the high-k oxide and oxide/semiconductor interface on channel transport properties such as electron mobility and channel electron concentration. Temperature dependent Hall electron mobility measurements were performed to separate various scattering induced mobility limiting factors. Dependence of channel mobility on proximity of the channel to the oxide interface, oxide thickness, annealing conditions are discussed. The results from this work will be used in the design of the p-channel MOSFETs. Following this, InxGa1-xAs (x>0.53) is chosen as channel material for developing p

  17. Investigation of capacitance characteristics in metal/high-k ...

    Indian Academy of Sciences (India)

    MS received 4 May 2016; accepted 10 January 2017; published online 21 August 2017. Abstract. Capacitance vs. ... with high-k materials is the prime technological challenge. [2]. ... reliability of MOS devices are strongly dependent on the for-.

  18. Interfacial microstructure of NiSi x/HfO2/SiO x/Si gate stacks

    International Nuclear Information System (INIS)

    Gribelyuk, M.A.; Cabral, C.; Gusev, E.P.; Narayanan, V.

    2007-01-01

    Integration of NiSi x based fully silicided metal gates with HfO 2 high-k gate dielectrics offers promise for further scaling of complementary metal-oxide- semiconductor devices. A combination of high resolution transmission electron microscopy and small probe electron energy loss spectroscopy (EELS) and energy dispersive X-ray analysis has been applied to study interfacial reactions in the undoped gate stack. NiSi was found to be polycrystalline with the grain size decreasing from top to bottom of NiSi x film. Ni content varies near the NiSi/HfO x interface whereby both Ni-rich and monosilicide phases were observed. Spatially non-uniform distribution of oxygen along NiSi x /HfO 2 interface was observed by dark field Scanning Transmission Electron Microscopy and EELS. Interfacial roughness of NiSi x /HfO x was found higher than that of poly-Si/HfO 2 , likely due to compositional non-uniformity of NiSi x . No intermixing between Hf, Ni and Si beyond interfacial roughness was observed

  19. Towards the accurate electronic structure descriptions of typical high-constant dielectrics

    Science.gov (United States)

    Jiang, Ting-Ting; Sun, Qing-Qing; Li, Ye; Guo, Jiao-Jiao; Zhou, Peng; Ding, Shi-Jin; Zhang, David Wei

    2011-05-01

    High-constant dielectrics have gained considerable attention due to their wide applications in advanced devices, such as gate oxides in metal-oxide-semiconductor devices and insulators in high-density metal-insulator-metal capacitors. However, the theoretical investigations of these materials cannot fulfil the requirement of experimental development, especially the requirement for the accurate description of band structures. We performed first-principles calculations based on the hybrid density functionals theory to investigate several typical high-k dielectrics such as Al2O3, HfO2, ZrSiO4, HfSiO4, La2O3 and ZrO2. The band structures of these materials are well described within the framework of hybrid density functionals theory. The band gaps of Al2O3, HfO2, ZrSiO4, HfSiO4, La2O3 and ZrO2are calculated to be 8.0 eV, 5.6 eV, 6.2 eV, 7.1 eV, 5.3 eV and 5.0 eV, respectively, which are very close to the experimental values and far more accurate than those obtained by the traditional generalized gradient approximation method.

  20. Effect of titanium oxide-polystyrene nanocomposite dielectrics on morphology and thin film transistor performance for organic and polymeric semiconductors

    Energy Technology Data Exchange (ETDEWEB)

    Della Pelle, Andrea M. [LGS Innovations, 15 Vreeland Rd., Florham Park, NJ 07932 (United States); Department of Chemistry, University of Massachusetts Amherst, 710 N. Pleasant St. Amherst, MA 01003 (United States); Maliakal, Ashok, E-mail: maliakal@lgsinnovations.com [LGS Innovations, 15 Vreeland Rd., Florham Park, NJ 07932 (United States); Sidorenko, Alexander [Department of Chemistry and Biochemistry, University of the Sciences, 600 South 43rd St., Philadelphia, PA 191034 (United States); Thayumanavan, S. [Department of Chemistry, University of Massachusetts Amherst, 710 N. Pleasant St. Amherst, MA 01003 (United States)

    2012-07-31

    Previous studies have shown that organic thin film transistors with pentacene deposited on gate dielectrics composed of a blend of high K titanium oxide-polystyrene core-shell nanocomposite (TiO{sub 2}-PS) with polystyrene (PS) perform with an order of magnitude increase in saturation mobility for TiO{sub 2}-PS (K = 8) as compared to PS devices (K = 2.5). The current study finds that this performance enhancement can be translated to alternative small single crystal organics such as {alpha}-sexithiophene ({alpha}-6T) (enhancement factor for field effect mobility ranging from 30-100 Multiplication-Sign higher on TiO{sub 2}-PS/PS blended dielectrics as compared to homogenous PS dielectrics). Interestingly however, in the case of semicrystalline polymers such as (poly-3-hexylthiophene) P3HT, this dramatic enhancement is not observed, possibly due to the difference in processing conditions used to fabricate these devices (film transfer as opposed to thermal evaporation). The morphology for {alpha}-sexithiophene ({alpha}-6T) grown by thermal evaporation on TiO{sub 2}-PS/PS blended dielectrics parallels that observed in pentacene devices. Smaller grain size is observed for films grown on dielectrics with higher TiO{sub 2}-PS content. In the case of poly(3-hexylthiophene) (P3HT) devices, constructed via film transfer, morphological differences exist for the P3HT on different substrates, as discerned by atomic force microscopy studies. However, these devices only exhibit a modest (2 Multiplication-Sign ) increase in mobility with increasing TiO{sub 2}-PS content in the films. After annealing of the transferred P3HT thin film transistor (TFT) devices, no appreciable enhancement in mobility is observed across the different blended dielectrics. Overall the results support the hypothesis that nucleation rate is responsible for changes in film morphology and device performance in thermally evaporated small molecule crystalline organic semiconductor TFTs. The increased nucleation

  1. Effect of titanium oxide–polystyrene nanocomposite dielectrics on morphology and thin film transistor performance for organic and polymeric semiconductors

    International Nuclear Information System (INIS)

    Della Pelle, Andrea M.; Maliakal, Ashok; Sidorenko, Alexander; Thayumanavan, S.

    2012-01-01

    Previous studies have shown that organic thin film transistors with pentacene deposited on gate dielectrics composed of a blend of high K titanium oxide–polystyrene core–shell nanocomposite (TiO 2 –PS) with polystyrene (PS) perform with an order of magnitude increase in saturation mobility for TiO 2 –PS (K = 8) as compared to PS devices (K = 2.5). The current study finds that this performance enhancement can be translated to alternative small single crystal organics such as α-sexithiophene (α-6T) (enhancement factor for field effect mobility ranging from 30-100× higher on TiO 2 –PS/PS blended dielectrics as compared to homogenous PS dielectrics). Interestingly however, in the case of semicrystalline polymers such as (poly-3-hexylthiophene) P3HT, this dramatic enhancement is not observed, possibly due to the difference in processing conditions used to fabricate these devices (film transfer as opposed to thermal evaporation). The morphology for α-sexithiophene (α-6T) grown by thermal evaporation on TiO 2 –PS/PS blended dielectrics parallels that observed in pentacene devices. Smaller grain size is observed for films grown on dielectrics with higher TiO 2 –PS content. In the case of poly(3-hexylthiophene) (P3HT) devices, constructed via film transfer, morphological differences exist for the P3HT on different substrates, as discerned by atomic force microscopy studies. However, these devices only exhibit a modest (2×) increase in mobility with increasing TiO 2 –PS content in the films. After annealing of the transferred P3HT thin film transistor (TFT) devices, no appreciable enhancement in mobility is observed across the different blended dielectrics. Overall the results support the hypothesis that nucleation rate is responsible for changes in film morphology and device performance in thermally evaporated small molecule crystalline organic semiconductor TFTs. The increased nucleation rate produces organic polycrystalline films with small grain

  2. Ballistic transport of graphene pnp junctions with embedded local gates

    International Nuclear Information System (INIS)

    Nam, Seung-Geol; Ki, Dong-Keun; Kim, Youngwook; Kim, Jun Sung; Lee, Hu-Jong; Park, Jong Wan

    2011-01-01

    We fabricated graphene pnp devices, by embedding pre-defined local gates in an oxidized surface layer of a silicon substrate. With neither deposition of dielectric material on the graphene nor electron-beam irradiation, we obtained high-quality graphene pnp devices without degradation of the carrier mobility even in the local-gate region. The corresponding increased mean free path leads to the observation of ballistic and phase-coherent transport across a local gate 130 nm wide, which is about an order of magnitude wider than reported previously. Furthermore, in our scheme, we demonstrated independent control of the carrier density in the local-gate region, with a conductance map very much distinct from those of top-gated devices. This was caused by the electric field arising from the global back gate being strongly screened by the embedded local gate. Our scheme allows the realization of ideal multipolar graphene junctions with ballistic carrier transport.

  3. Comparative analysis of the effects of tantalum doping and annealing on atomic layer deposited (Ta{sub 2}O{sub 5}){sub x}(Al{sub 2}O{sub 3}){sub 1−x} as potential gate dielectrics for GaN/Al{sub x}Ga{sub 1−x}N/GaN high electron mobility transistors

    Energy Technology Data Exchange (ETDEWEB)

    Partida-Manzanera, T., E-mail: sgtparti@liv.ac.uk [Centre for Materials and Structures, School of Engineering, University of Liverpool, Liverpool, L69 3GH (United Kingdom); Institute of Materials Research and Engineering, A*STAR (Agency for Science, Technology and Research), Innovis, 2 Fusionopolis way, Singapore 138634 (Singapore); Roberts, J. W.; Sedghi, N.; Potter, R. J. [Centre for Materials and Structures, School of Engineering, University of Liverpool, Liverpool, L69 3GH (United Kingdom); Bhat, T. N.; Zhang, Z.; Tan, H. R.; Dolmanan, S. B.; Tripathy, S. [Institute of Materials Research and Engineering, A*STAR (Agency for Science, Technology and Research), Innovis, 2 Fusionopolis way, Singapore 138634 (Singapore)

    2016-01-14

    This paper describes a method to optimally combine wide band gap Al{sub 2}O{sub 3} with high dielectric constant (high-κ) Ta{sub 2}O{sub 5} for gate dielectric applications. (Ta{sub 2}O{sub 5}){sub x}(Al{sub 2}O{sub 3}){sub 1−x} thin films deposited by thermal atomic layer deposition (ALD) on GaN-capped Al{sub x}Ga{sub 1−x}N/GaN high electron mobility transistor (HEMT) structures have been studied as a function of the Ta{sub 2}O{sub 5} molar fraction. X-ray photoelectron spectroscopy shows that the bandgap of the oxide films linearly decreases from 6.5 eV for pure Al{sub 2}O{sub 3} to 4.6 eV for pure Ta{sub 2}O{sub 5}. The dielectric constant calculated from capacitance-voltage measurements also increases linearly from 7.8 for Al{sub 2}O{sub 3} up to 25.6 for Ta{sub 2}O{sub 5}. The effect of post-deposition annealing in N{sub 2} at 600 °C on the interfacial properties of undoped Al{sub 2}O{sub 3} and Ta-doped (Ta{sub 2}O{sub 5}){sub 0.12}(Al{sub 2}O{sub 3}){sub 0.88} films grown on GaN-HEMTs has been investigated. These conditions are analogous to the conditions used for source/drain contact formation in gate-first HEMT technology. A reduction of the Ga-O to Ga-N bond ratios at the oxide/HEMT interfaces is observed after annealing, which is attributed to a reduction of interstitial oxygen-related defects. As a result, the conduction band offsets (CBOs) of the Al{sub 2}O{sub 3}/GaN-HEMT and (Ta{sub 2}O{sub 5}){sub 0.16}(Al{sub 2}O{sub 3}){sub 0.84}/GaN-HEMT samples increased by ∼1.1 eV to 2.8 eV and 2.6 eV, respectively, which is advantageous for n-type HEMTs. The results demonstrate that ALD of Ta-doped Al{sub 2}O{sub 3} can be used to control the properties of the gate dielectric, allowing the κ-value to be increased, while still maintaining a sufficient CBO to the GaN-HEMT structure for low leakage currents.

  4. High permittivity materials for oxide gate stack in Ge-based metal oxide semiconductor capacitors

    Energy Technology Data Exchange (ETDEWEB)

    Molle, Alessandro, E-mail: alessandro.molle@mdm.infm.i [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Baldovino, Silvia [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano Bicocca, Milano (Italy); Spiga, Sabina [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Fanciulli, Marco [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano Bicocca, Milano (Italy)

    2010-01-01

    In the effort to ultimately shrink the size of logic devices towards a post-Si era, the integration of Ge as alternative channel material for high-speed p-MOSFET devices and the concomitant coupling with high permittivity dielectrics (high-k) as gate oxides is currently a key-challenge in microelectronics. However, the Ge option still suffers from a number of unresolved drawbacks and open issues mainly related to the thermodynamic and electrical compatibility of Ge substrates with high-k gate stack. Strictly speaking, two main concerns can be emphasized. On one side is the dilemma on which chemical/physical passivation is more suitable to minimize the unavoidable presence of electrically active defects at the oxide/semiconductor interface. On the other side, overcoming the SiO{sub 2} gate stack opens the route to a number of potentially outperforming high-k oxides. Two deposition approaches were here separately adopted to investigate the high-k oxide growth on Ge substrates, the molecular beam deposition (MBD) of Gd{sub 2}O{sub 3} and the atomic layer deposition (ALD) of HfO{sub 2}. In the MBD framework epitaxial and amorphous Gd{sub 2}O{sub 3} films were grown onto GeO{sub 2}-passivated Ge substrates. In this case, Ge passivation was achieved by exploiting the Ge{sup 4+} bonding state in GeO{sub 2} ultra-thin interface layers intentionally deposited in between Ge and the high-k oxide by means of atomic oxygen exposure to Ge. The composition of the interface layer has been characterized as a function of the oxidation temperature and evidence of Ge dangling bonds at the GeO{sub 2}/Ge interface has been reported. Finally, the electrical response of MOS capacitors incorporating Gd{sub 2}O{sub 3} and GeO{sub 2}-passivated Ge substrates has been checked by capacitance-voltage measurements. On the other hand, the structural and electrical properties of HfO{sub 2} films grown by ALD on Ge by using different oxygen precursors, i.e. H{sub 2}O, Hf(O{sup t}Bu){sub 2}(mmp

  5. Computation of Dielectric Response in Molecular Solids for High Capacitance Organic Dielectrics.

    Science.gov (United States)

    Heitzer, Henry M; Marks, Tobin J; Ratner, Mark A

    2016-09-20

    The dielectric response of a material is central to numerous processes spanning the fields of chemistry, materials science, biology, and physics. Despite this broad importance across these disciplines, describing the dielectric environment of a molecular system at the level of first-principles theory and computation remains a great challenge and is of importance to understand the behavior of existing systems as well as to guide the design and synthetic realization of new ones. Furthermore, with recent advances in molecular electronics, nanotechnology, and molecular biology, it has become necessary to predict the dielectric properties of molecular systems that are often difficult or impossible to measure experimentally. In these scenarios, it is would be highly desirable to be able to determine dielectric response through efficient, accurate, and chemically informative calculations. A good example of where theoretical modeling of dielectric response would be valuable is in the development of high-capacitance organic gate dielectrics for unconventional electronics such as those that could be fabricated by high-throughput printing techniques. Gate dielectrics are fundamental components of all transistor-based logic circuitry, and the combination high dielectric constant and nanoscopic thickness (i.e., high capacitance) is essential to achieving high switching speeds and low power consumption. Molecule-based dielectrics offer the promise of cheap, flexible, and mass producible electronics when used in conjunction with unconventional organic or inorganic semiconducting materials to fabricate organic field effect transistors (OFETs). The molecular dielectrics developed to date typically have limited dielectric response, which results in low capacitances, translating into poor performance of the resulting OFETs. Furthermore, the development of better performing dielectric materials has been hindered by the current highly empirical and labor-intensive pace of synthetic

  6. Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process

    International Nuclear Information System (INIS)

    Wang Yanrong; Yang Hong; Xu Hao; Luo Weichun; Qi Luwei; Zhang Shuxiang; Wang Wenwu; Zhu Huilong; Zhao Chao; Chen Dapeng; Ye Tianchun; Yan Jiang

    2017-01-01

    In the process of high- k films fabrication, a novel multi deposition multi annealing (MDMA) technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing (PDA) times. The equivalent oxide thickness (EOT) decreases when the annealing time(s) change from 1 to 2. Furthermore, the characteristics of SILC (stress-induced leakage current) for an ultra-thin SiO 2 /HfO 2 gate dielectric stack are studied systematically. The increase of the PDA time(s) from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes. (paper)

  7. Water-gel for gating graphene transistors.

    Science.gov (United States)

    Kim, Beom Joon; Um, Soong Ho; Song, Woo Chul; Kim, Yong Ho; Kang, Moon Sung; Cho, Jeong Ho

    2014-05-14

    Water, the primary electrolyte in biology, attracts significant interest as an electrolyte-type dielectric material for transistors compatible with biological systems. Unfortunately, the fluidic nature and low ionic conductivity of water prevents its practical usage in such applications. Here, we describe the development of a solid state, megahertz-operating, water-based gate dielectric system for operating graphene transistors. The new electrolyte systems were prepared by dissolving metal-substituted DNA polyelectrolytes into water. The addition of these biocompatible polyelectrolytes induced hydrogelation to provide solid-state integrity to the system. They also enhanced the ionic conductivities of the electrolytes, which in turn led to the quick formation of an electric double layer at the graphene/electrolyte interface that is beneficial for modulating currents in graphene transistors at high frequencies. At the optimized conditions, the Na-DNA water-gel-gated flexible transistors and inverters were operated at frequencies above 1 MHz and 100 kHz, respectively.

  8. Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

    Science.gov (United States)

    Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

    2015-12-01

    A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

  9. Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

    Science.gov (United States)

    Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

    2015-12-17

    A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

  10. Tunnel field-effect transistor with two gated intrinsic regions

    Directory of Open Access Journals (Sweden)

    Y. Zhang

    2014-07-01

    Full Text Available In this paper, we propose and validate (using simulations a novel design of silicon tunnel field-effect transistor (TFET, based on a reverse-biased p+-p-n-n+ structure. 2D device simulation results show that our devices have significant improvements of switching performance compared with more conventional devices based on p-i-n structure. With independent gate voltages applied to two gated intrinsic regions, band-to-band tunneling (BTBT could take place at the p-n junction, and no abrupt degenerate doping profile is required. We developed single-side-gate (SSG structure and double-side-gate (DSG structure. SSG devices with HfO2 gate dielectric have a point subthreshold swing of 9.58 mV/decade, while DSG devices with polysilicon gate electrode material and HfO2 gate dielectric have a point subthreshold swing of 16.39 mV/decade. These DSG devices have ON-current of 0.255 μA/μm, while that is lower for SSG devices. Having two nano-scale independent gates will be quite challenging to realize with good uniformity across the wafer and the improved behavior of our TFET makes it a promising steep-slope switch candidate for further investigations.

  11. Mechanical Design of the NSTX High-k Scattering Diagnostic

    International Nuclear Information System (INIS)

    Feder, R.; Mazzucato, E.; Munsat, T.; Park, H.; Smith, D.R.; Ellis, R.; Labik, G.; Priniski, C.

    2005-01-01

    The NSTX High-k Scattering Diagnostic measures small-scale density fluctuations by the heterodyne detection of waves scattered from a millimeter wave probe beam at 280 GHz and λ = 1.07 mm. To enable this measurement, major alterations were made to the NSTX vacuum vessel and Neutral Beam armor. Close collaboration between the PPPL physics and engineering staff resulted in a flexible system with steerable launch and detection optics that can position the scattering volume either near the magnetic axis (ρ ∼ .1) or near the edge (ρ ∼ .8). 150 feet of carefully aligned corrugated waveguide was installed for injection of the probe beam and collection of the scattered signal in to the detection electronics

  12. Identical high- K three-quasiparticle rotational bands

    Energy Technology Data Exchange (ETDEWEB)

    Kaur, Harjeet; Singh, Pardeep [Guru Nanak Dev University, Department of Physics, Amritsar (India)

    2016-12-15

    A comprehensive study of high-K three-quasiparticle rotational bands in odd-A nuclei indicates the similarity in γ-ray energies and dynamic moment of inertia I{sup (2)}. The extent of the identicality between the rotational bands is evaluated by using the energy factor method. For nuclei pairs exhibiting identical bands, the average relative change in the dynamic moment of inertia I{sup (2)} is also determined. The identical behaviour shown by these bands is attributed to the interplay of nuclear structure parameters: deformation and the pairing correlations. Also, experimental trend of the I(ℎ) vs. ℎω (MeV) plot for these nuclei pairs is shown to be in agreement with Tilted-Axis Cranking (TAC) model calculations. (orig.)

  13. Mechanical Design of the NSTX High-k Scattering Diagnostic

    Energy Technology Data Exchange (ETDEWEB)

    Feder, R.; Mazzucato, E.; Munsat, T.; Park, H,; Smith, D. R.; Ellis, R.; Labik, G.; Priniski, C.

    2005-09-26

    The NSTX High-k Scattering Diagnostic measures small-scale density fluctuations by the heterodyne detection of waves scattered from a millimeter wave probe beam at 280 GHz and {lambda}=1.07 mm. To enable this measurement, major alterations were made to the NSTX vacuum vessel and Neutral Beam armor. Close collaboration between the PPPL physics and engineering staff resulted in a flexible system with steerable launch and detection optics that can position the scattering volume either near the magnetic axis ({rho} {approx} .1) or near the edge ({rho} {approx} .8). 150 feet of carefully aligned corrugated waveguide was installed for injection of the probe beam and collection of the scattered signal in to the detection electronics.

  14. Nanostructure characterization of high k materials by spectroscopic ellipsometry

    International Nuclear Information System (INIS)

    Pereira, L.; Aguas, H.; Fortunato, E.; Martins, R.

    2006-01-01

    In this work, the optical and structural properties of high k materials such as tantalum oxide and titanium oxide were studied by spectroscopic ellipsometry, where a Tauc-Lorentz dispersion model based in one (amorphous films) or two oscillators (microcrystalline films) was used. The samples were deposited at room temperature by radio frequency magnetron sputtering and then annealed at temperatures from 100 to 500 deg. C. Concerning the tantalum oxide films, the increase of the annealing temperature, up to 500 deg. C does not change the amorphous nature of the films, increasing, however, their density. The same does not happen with the titanium oxide films that are microcrystalline, even when deposited at room temperature. Data concerning the use of a four-layer model based on one and two Tauc-Lorentz dispersions is also discussed, emphasizing its use for the detection of an amorphous incubation layer, normally present on microcrystalline films grown by sputtering

  15. Atomic layer deposition of dielectrics for carbon-based electronics

    Energy Technology Data Exchange (ETDEWEB)

    Kim, J., E-mail: jiyoung.kim@utdallas.edu; Jandhyala, S.

    2013-11-01

    Carbon based nanomaterials like nanotubes and graphene have emerged as future generation electronic materials for device applications because of their interesting properties such as high-mobility and ability to carry high-current densities compared to conventional semiconductor materials like silicon. Therefore, there is a need to develop techniques to integrate robust gate dielectrics with high-quality interfaces for these materials in order to attain maximum performance. To date, a variety of methods including physical vapor deposition, atomic layer deposition (ALD), physical assembly among others have been employed in order to integrate dielectrics for carbon nanotube and graphene based field-effect transistors. Owing to the difficulty in wetting pristine surfaces of nanotubes and graphene, most of the ALD methods require a seeding technique involving non-covalent functionalization of their surfaces in order to nucleate dielectric growth while maintaining their intrinsic properties. A comprehensive review regarding the various dielectric integration schemes for emerging devices and their limitations with respect to ALD based methods along with a future outlook is provided. - Highlights: • We introduce various dielectric integration schemes for carbon-based devices. • Physical vapor deposition methods tend to degrade device performance. • Atomic layer deposition on pristine surfaces of graphene and nanotube is difficult. • We review different seeding techniques for atomic layer deposition of dielectrics. • Compare the performance of graphene top-gate devices with different dielectrics.

  16. Breakdown of coupling dielectrics for Si microstrip detectors

    International Nuclear Information System (INIS)

    Candelori, A.; Paccagnella, A.; Padova Univ.; Saglimbeni, G.

    1999-01-01

    Double-layer coupling dielectrics for AC-coupled Si microstrip detectors have been electrically characterized in order to determine their performance in a radiation-harsh environment, with a focus on the dielectric breakdown. Two different dielectric technologies have been investigated: SiO 2 /TEOS and SiO 2 /Si 3 N 4 . Dielectrics have been tested by using a negative gate voltage ramp of 0.2 MV/(cm·s). The metal/insulator/Si I-V characteristics show different behaviours depending on the technology. The extrapolated values of the breakdown field for unirradiated devices are significantly higher for SiO 2 /Si 3 N 4 dielectrics, but the data dispersion is lower for SiO 2 /TEOS devices. No significant variation of the breakdown field has been measured after a 10 Mrad (Si) γ irradiation for SiO 2 /Si 3 N 4 dielectrics. Finally, the SiO 2 /Si 3 N 4 DC conduction is enhanced if a positive gate voltage ramp is applied with respect to the negative one, due to the asymmetric conduction of the double-layer dielectric

  17. Atomic layer deposition of dielectrics for carbon-based electronics

    International Nuclear Information System (INIS)

    Kim, J.; Jandhyala, S.

    2013-01-01

    Carbon based nanomaterials like nanotubes and graphene have emerged as future generation electronic materials for device applications because of their interesting properties such as high-mobility and ability to carry high-current densities compared to conventional semiconductor materials like silicon. Therefore, there is a need to develop techniques to integrate robust gate dielectrics with high-quality interfaces for these materials in order to attain maximum performance. To date, a variety of methods including physical vapor deposition, atomic layer deposition (ALD), physical assembly among others have been employed in order to integrate dielectrics for carbon nanotube and graphene based field-effect transistors. Owing to the difficulty in wetting pristine surfaces of nanotubes and graphene, most of the ALD methods require a seeding technique involving non-covalent functionalization of their surfaces in order to nucleate dielectric growth while maintaining their intrinsic properties. A comprehensive review regarding the various dielectric integration schemes for emerging devices and their limitations with respect to ALD based methods along with a future outlook is provided. - Highlights: • We introduce various dielectric integration schemes for carbon-based devices. • Physical vapor deposition methods tend to degrade device performance. • Atomic layer deposition on pristine surfaces of graphene and nanotube is difficult. • We review different seeding techniques for atomic layer deposition of dielectrics. • Compare the performance of graphene top-gate devices with different dielectrics

  18. Super dielectric capacitor using scaffold dielectric

    OpenAIRE

    Phillips, Jonathan

    2018-01-01

    Patent A capacitor having first and second electrodes and a scaffold dielectric. The scaffold dielectric comprises an insulating material with a plurality of longitudinal channels extending across the dielectric and filled with a liquid comprising cations and anions. The plurality of longitudinal channels are substantially parallel and the liquid within the longitudinal channels generally has an ionic strength of at least 0.1. Capacitance results from the migrations of...

  19. C-V analysis at variable frequency of MOS structures with different gates, containing Hf-Doped Ta2O5

    International Nuclear Information System (INIS)

    Stojanovska-Georgievska, L.; Novkovski, N.; Atanassova, E.

    2012-01-01

    The quality of the interface between the insulating layer and the Si substrate in contemporary submicron MOS technology is a critical issue for device functioning. It is characterized through the electrically active defect centers, known as interface states. Their response to the frequency is discussed here, by analyzing capacitance-voltage and conductance-voltage curves. The C-V method is preferred in many cases, since it offers easy measurement, and it is applied to extract information about interface traps and fixed oxide charge, at different frequencies. This technique, related with frequency dependent G-V measurements, can be very useful in characterizing charge trapped in the dielectric and at the interface with Si. By extracting the value of frequency dependent flat band voltage, we have obtained the fixed oxide charges at flat band condition. A comparison between the results obtained by two different methods is made. The samples that are studied are metal-insulator-semiconductor (MIS) structures that include high-k dielectric as insulating layer (Hf doped Ta 2 O 5 ), with thickness of 8 nm, with different metal used as gate electrode. Here the influence of the top electrode on the generation and behavior of the traps in the oxide layer is discussed. The results show that the value of metal work function of the gate material is an issue that should be considered very carefully, especially in the case of high work function metal gates, when generation of extra positive charge than in the case of other metals is observed. (Author)

  20. Decorating TiO2 Nanowires with BaTiO3 Nanoparticles: A New Approach Leading to Substantially Enhanced Energy Storage Capability of High-k Polymer Nanocomposites.

    Science.gov (United States)

    Kang, Da; Wang, Guanyao; Huang, Yanhui; Jiang, Pingkai; Huang, Xingyi

    2018-01-31

    The urgent demand of high energy density and high power density devices has triggered significant interest in high dielectric constant (high-k) flexible nanocomposites comprising dielectric polymer and high-k inorganic nanofiller. However, the large electrical mismatch between polymer and nanofiller usually leads to earlier electric failure of the nanocomposites, resulting in an undesirable decrease of electrical energy storage capability. A few studies show that the introduction of moderate-k shell onto a high-k nanofiller surface can decrease the dielectric constant mismatch, and thus, the corresponding nanocomposites can withstand high electric field. Unfortunately, the low apparent dielectric enhancement of the nanocomposites and high electrical conductivity mismatch between matrix and nanofiller still result in low energy density and low efficiency. In this study, it is demonstrated that encapsulating moderate-k nanofiller with high-k but low electrical conductivity shell is effective to significantly enhance the energy storage capability of dielectric polymer nanocomposites. Specifically, using BaTiO 3 nanoparticles encapsulated TiO 2 (BaTiO 3 @TiO 2 ) core-shell nanowires as filler, the corresponding poly(vinylidene fluoride-co-hexafluoropylene) nanocomposites exhibit superior energy storage capability in comparison with the nanocomposites filled by either BaTiO 3 or TiO 2 nanowires. The nanocomposite film with 5 wt % BaTiO 3 @TiO 2 nanowires possesses an ultrahigh discharged energy density of 9.95 J cm -3 at 500 MV m -1 , much higher than that of commercial biaxial-oriented polypropylene (BOPP) (3.56 J cm -3 at 600 MV m -1 ). This new strategy and corresponding results presented here provide new insights into the design of dielectric polymer nanocomposites with high electrical energy storage capability.

  1. Cleaning Challenges of High-κ/Metal Gate Structures

    KAUST Repository

    Hussain, Muhammad Mustafa; Shamiryan, Denis G.; Paraschiv, Vasile; Sano, Kenichi; Reinhardt, Karen A.

    2010-01-01

    High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.

  2. Cleaning Challenges of High-κ/Metal Gate Structures

    KAUST Repository

    Hussain, Muhammad Mustafa

    2010-12-20

    High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.

  3. Inertial polarization of dielectrics

    OpenAIRE

    Zavodovsky, A. G.

    2011-01-01

    It was proved that accelerated motion of a linear dielectric causes its polarization. Accelerated translational motion of a dielectric's plate leads to the positive charge of the surface facing the direction of motion. Metal plates of a capacitor were used to register polarized charges on a dielectric's surface. Potential difference between the capacitor plates is proportional to acceleration, when acceleration is constant potential difference grows with the increase of a dielectric's area, o...

  4. Radiation sensors based on the generation of mobile protons in organic dielectrics.

    Science.gov (United States)

    Kapetanakis, Eleftherios; Douvas, Antonios M; Argitis, Panagiotis; Normand, Pascal

    2013-06-26

    A sensing scheme based on mobile protons generated by radiation, including ionizing radiation (IonR), in organic gate dielectrics is investigated for the development of metal-insulator-semiconductor (MIS)-type dosimeters. Application of an electric field to the gate dielectric moves the protons and thereby alters the flat band voltage (VFB) of the MIS device. The shift in the VFB is proportional to the IonR-generated protons and, therefore, to the IonR total dose. Triphenylsulfonium nonaflate (TPSNF) photoacid generator (PAG)-containing poly(methyl methacrylate) (PMMA) polymeric films was selected as radiation-sensitive gate dielectrics. The effects of UV (249 nm) and gamma (Co-60) irradiations on the high-frequency capacitance versus the gate voltage (C-VG) curves of the MIS devices were investigated for different total dose values. Systematic improvements in sensitivity can be accomplished by increasing the concentration of the TPSNF molecules embedded in the polymeric matrix.

  5. Optimal Super Dielectric Material

    Science.gov (United States)

    2015-09-01

    plate capacitor will reduce the net field to an unprecedented extent. This family of materials can form materials with dielectric values orders of... Capacitor -Increase Area (A)............8 b. Multi-layer Ceramic Capacitor -Decrease Thickness (d) .......10 c. Super Dielectric Material-Increase...circuit modeling, from [44], and B) SDM capacitor charge and discharge ...................................................22 Figure 15. Dielectric

  6. New gate opening hours

    CERN Multimedia

    GS Department

    2009-01-01

    Please note the new opening hours of the gates as well as the intersites tunnel from the 19 May 2009: GATE A 7h - 19h GATE B 24h/24 GATE C 7h - 9h\t17h - 19h GATE D 8h - 12h\t13h - 16h GATE E 7h - 9h\t17h - 19h Prévessin 24h/24 The intersites tunnel will be opened from 7h30 to 18h non stop. GS-SEM Group Infrastructure and General Services Department

  7. Dielectrics in electric fields

    CERN Document Server

    Raju, Gorur G

    2003-01-01

    Discover nontraditional applications of dielectric studies in this exceptionally crafted field reference or text for seniors and graduate students in power engineering tracks. This text contains more than 800 display equations and discusses polarization phenomena in dielectrics, the complex dielectric constant in an alternating electric field, dielectric relaxation and interfacial polarization, the measurement of absorption and desorption currents in time domains, and high field conduction phenomena. Dielectrics in Electric Fields is an interdisciplinary reference and text for professionals and students in electrical and electronics, chemical, biochemical, and environmental engineering; physical, surface, and colloid chemistry; materials science; and chemical physics.

  8. Reduction of ambipolar characteristics of vertical channel tunneling field-effect transistor by using dielectric sidewall

    International Nuclear Information System (INIS)

    Park, Chun Woong; Cho, Il Hwan; Choi, Woo Young; Lee, Jong-Ho

    2013-01-01

    Ambipolar characteristics of tunneling FETs have been improved by introducing a novel structure which contains dielectric sidewall in the gate region. In the ambipolar operation mode, gate field effect on intrinsic-drain junction region can be reduced with dielectric sidewall. As a result, ambipolar state tunneling probability is decreased at the intrinsic-drain junction. Since the sidewall region is located near the drain region, tunneling probability of source-intrinsic region is not affected by dielectric sidewall. This asymmetric characteristics means only ambipolar current of tunneling FETs can be prohibited by dielectric sidewall. Reduction of ambipolar characteristic of proposed structure has been evaluated with dimension and location of dielectric sidewall. Quantitative analysis of ambipolar characteristics is also investigated with tunneling. (paper)

  9. Lattices of dielectric resonators

    CERN Document Server

    Trubin, Alexander

    2016-01-01

    This book provides the analytical theory of complex systems composed of a large number of high-Q dielectric resonators. Spherical and cylindrical dielectric resonators with inferior and also whispering gallery oscillations allocated in various lattices are considered. A new approach to S-matrix parameter calculations based on perturbation theory of Maxwell equations, developed for a number of high-Q dielectric bodies, is introduced. All physical relationships are obtained in analytical form and are suitable for further computations. Essential attention is given to a new unified formalism of the description of scattering processes. The general scattering task for coupled eigen oscillations of the whole system of dielectric resonators is described. The equations for the  expansion coefficients are explained in an applicable way. The temporal Green functions for the dielectric resonator are presented. The scattering process of short pulses in dielectric filter structures, dielectric antennas  and lattices of d...

  10. Volatile and Nonvolatile Characteristics of Asymmetric Dual-Gate Thyristor RAM with Vertical Structure.

    Science.gov (United States)

    Kim, Hyun-Min; Kwon, Dae Woong; Kim, Sihyun; Lee, Kitae; Lee, Junil; Park, Euyhwan; Lee, Ryoongbin; Kim, Hyungjin; Kim, Sangwan; Park, Byung-Gook

    2018-09-01

    In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (107) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.

  11. Low-voltage bendable pentacene thin-film transistor with stainless steel substrate and polystyrene-coated hafnium silicate dielectric.

    Science.gov (United States)

    Yun, Dong-Jin; Lee, Seunghyup; Yong, Kijung; Rhee, Shi-Woo

    2012-04-01

    The hafnium silicate and aluminum oxide high-k dielectrics were deposited on stainless steel substrate using atomic layer deposition process and octadecyltrichlorosilane (OTS) and polystyrene (PS) were treated improve crystallinity of pentacene grown on them. Besides, the effects of the pentacene deposition condition on the morphologies, crystallinities and electrical properties of pentacene were characterized. Therefore, the surface treatment condition on dielectric and pentacene deposition conditions were optimized. The pentacene grown on polystyrene coated high-k dielectric at low deposition rate and temperature (0.2-0.3 Å/s and R.T.) showed the largest grain size (0.8-1.0 μm) and highest crystallinity among pentacenes deposited various deposition conditions, and the pentacene TFT with polystyrene coated high-k dielectric showed excellent device-performance. To decrease threshold voltage of pentacene TFT, the polystyrene-thickness on high-k dielectric was controlled using different concentration of polystyrene solution. As the polystyrene-thickness on hafnium silicate decreases, the dielectric constant of polystyrene/hafnium silicate increases, while the crystallinity of pentacene grown on polystyrene/hafnium silicate did not change. Using low-thickness polystyrene coated hafnium silicate dielectric, the high-performance and low voltage operating (pentacene thin film transistor (μ: ~2 cm(2)/(V s), on/off ratio, >1 × 10(4)) and complementary inverter (DC gains, ~20) could be fabricated.

  12. Existence conditions for bulk large-wavevector waves in metal-dielectric and graphene-dielectric multilayer hyperbolic metamaterials

    DEFF Research Database (Denmark)

    Zhukovsky, Sergei; Andryieuski, Andrei; Lavrinenko, Andrei

    2014-01-01

    We theoretically investigate general existence conditions for broadband bulk large-wavevector (high-k) propagating waves (such as volume plasmon polaritons in hyperbolic metamaterials) in arbitrary subwavelength periodic multilayers structures. Treating the elementary excitation in the unit cell...... of the structure as a generalized resonance pole of reflection coefficient and using Bloch's theorem, we derive analytical expressions for the band of large-wavevector propagating solutions. We apply our formalism to determine the high-k band existence in two important cases: the well-known metal-dielectric...

  13. Top-gate hybrid complementary inverters using pentacene and amorphous InGaZnO thin-film transistors with high operational stability

    Directory of Open Access Journals (Sweden)

    J. B. Kim

    2012-03-01

    Full Text Available We report on the operational stability of low-voltage hybrid organic-inorganic complementary inverters with a top-gate bottom source-drain geometry. The inverters are comprised of p-channel pentacene and n-channel amorphous InGaZnO thin-film transistors (TFTs with bi-layer gate dielectrics formed from an amorphous layer of a fluoropolymer (CYTOP and a high-k layer of Al2O3. The p- and n- channel TFTs show saturation mobility values of 0.1 ± 0.01 and 5.0 ± 0.5 cm2/Vs, respectively. The individual transistors show high electrical stability with less than 6% drain-to-source current variations after 1 h direct current (DC bias stress. Complementary inverters yield hysteresis-free voltage transfer characteristics for forward and reverse input biases with static DC gain values larger than 45 V/V at 8 V before and after being subjected to different conditions of electrical stress. Small and reversible variations of the switching threshold voltage of the inverters during these stress tests are compatible with the observed stability of the individual TFTs.

  14. Characterization of dielectric materials

    Energy Technology Data Exchange (ETDEWEB)

    King, Danny J.; Babinec, Susan; Hagans, Patrick L.; Maxey, Lonnie C.; Payzant, Edward A.; Daniel, Claus; Sabau, Adrian S.; Dinwiddie, Ralph B.; Armstrong, Beth L.; Howe, Jane Y.; Wood, III, David L.; Nembhard, Nicole S.

    2017-06-27

    A system and a method for characterizing a dielectric material are provided. The system and method generally include applying an excitation signal to electrodes on opposing sides of the dielectric material to evaluate a property of the dielectric material. The method can further include measuring the capacitive impedance across the dielectric material, and determining a variation in the capacitive impedance with respect to either or both of a time domain and a frequency domain. The measured property can include pore size and surface imperfections. The method can still further include modifying a processing parameter as the dielectric material is formed in response to the detected variations in the capacitive impedance, which can correspond to a non-uniformity in the dielectric material.

  15. Stable Low-Voltage Operation Top-Gate Organic Field-Effect Transistors on Cellulose Nanocrystal Substrates

    Science.gov (United States)

    Cheng-Yin Wang; Canek Fuentes-Hernandez; Jen-Chieh Liu; Amir Dindar; Sangmoo Choi; Jeffrey P. Youngblood; Robert J. Moon; Bernard Kippelen

    2015-01-01

    We report on the performance and the characterization of top-gate organic field-effect transistors (OFETs), comprising a bilayer gate dielectric of CYTOP/ Al2O3 and a solution-processed semiconductor layer made of a blend of TIPS-pentacene:PTAA, fabricated on recyclable cellulose nanocrystal−glycerol (CNC/glycerol...

  16. Inductive dielectric analyzer

    International Nuclear Information System (INIS)

    Agranovich, Daniel; Popov, Ivan; Ben Ishai, Paul; Feldman, Yuri; Polygalov, Eugene

    2017-01-01

    One of the approaches to bypass the problem of electrode polarization in dielectric measurements is the free electrode method. The advantage of this technique is that, the probing electric field in the material is not supplied by contact electrodes, but rather by electromagnetic induction. We have designed an inductive dielectric analyzer based on a sensor comprising two concentric toroidal coils. In this work, we present an analytic derivation of the relationship between the impedance measured by the sensor and the complex dielectric permittivity of the sample. The obtained relationship was successfully employed to measure the dielectric permittivity and conductivity of various alcohols and aqueous salt solutions. (paper)

  17. Method of making dielectric capacitors with increased dielectric breakdown strength

    Science.gov (United States)

    Ma, Beihai; Balachandran, Uthamalingam; Liu, Shanshan

    2017-05-09

    The invention is directed to a process for making a dielectric ceramic film capacitor and the ceramic dielectric laminated capacitor formed therefrom, the dielectric ceramic film capacitors having increased dielectric breakdown strength. The invention increases breakdown strength by embedding a conductive oxide layer between electrode layers within the dielectric layer of the capacitors. The conductive oxide layer redistributes and dissipates charge, thus mitigating charge concentration and micro fractures formed within the dielectric by electric fields.

  18. Scanning gate microscopy on graphene: charge inhomogeneity and extrinsic doping

    International Nuclear Information System (INIS)

    Jalilian, Romaneh; Tian Jifa; Chen, Yong P; Jauregui, Luis A; Lopez, Gabriel; Roecker, Caleb; Jovanovic, Igor; Yazdanpanah, Mehdi M; Cohn, Robert W

    2011-01-01

    We have performed scanning gate microscopy (SGM) on graphene field effect transistors (GFET) using a biased metallic nanowire coated with a dielectric layer as a contact mode tip and local top gate. Electrical transport through graphene at various back gate voltages is monitored as a function of tip voltage and tip position. Near the Dirac point, the response of graphene resistance to the tip voltage shows significant variation with tip position, and SGM imaging displays mesoscopic domains of electron-doped and hole-doped regions. Our measurements reveal substantial spatial fluctuation in the carrier density in graphene due to extrinsic local doping from sources such as metal contacts, graphene edges, structural defects and resist residues. Our scanning gate measurements also demonstrate graphene's excellent capability to sense the local electric field and charges.

  19. C-V characterization of Schottky- and MIS-gate SiGe/Si HEMT structures

    International Nuclear Information System (INIS)

    Onojima, Norio; Kasamatsu, Akihumi; Hirose, Nobumitsu; Mimura, Takashi; Matsui, Toshiaki

    2008-01-01

    Electrical properties of Schottky- and metal-insulator-semiconductor (MIS)-gate SiGe/Si high electron mobility transistors (HEMTs) were investigated with capacitance-voltage (C-V) measurements. The MIS-gate HEMT structure was fabricated using a SiN gate insulator formed by catalytic chemical vapor deposition (Cat-CVD). The Cat-CVD SiN thin film (5 nm) was found to be an effective gate insulator with good gate controllability and dielectric properties. We previously investigated device characteristics of sub-100-nm-gate-length Schottky- and MIS-gate HEMTs, and reported that the MIS-gate device had larger maximum drain current density and transconductance (g m ) than the Schottky-gate device. The radio frequency (RF) measurement of the MIS-gate device, however, showed a relatively lower current gain cutoff frequency f T compared with that of the Schottky-gate device. In this study, C-V characterization of the MIS-gate HEMT structure demonstrated that two electron transport channels existed, one at the SiGe/Si buried channel and the other at the SiN/Si surface channel

  20. C-V characterization of Schottky- and MIS-gate SiGe/Si HEMT structures

    Energy Technology Data Exchange (ETDEWEB)

    Onojima, Norio [National Institute of Information and Communications Technology (NICT), Koganei, Tokyo 184-8795 (Japan)], E-mail: nonojima@nict.go.jp; Kasamatsu, Akihumi; Hirose, Nobumitsu [National Institute of Information and Communications Technology (NICT), Koganei, Tokyo 184-8795 (Japan); Mimura, Takashi [National Institute of Information and Communications Technology (NICT), Koganei, Tokyo 184-8795 (Japan); Fujitsu Laboratories Ltd., Atsugi, Kanagawa 243-0197 (Japan); Matsui, Toshiaki [National Institute of Information and Communications Technology (NICT), Koganei, Tokyo 184-8795 (Japan)

    2008-07-30

    Electrical properties of Schottky- and metal-insulator-semiconductor (MIS)-gate SiGe/Si high electron mobility transistors (HEMTs) were investigated with capacitance-voltage (C-V) measurements. The MIS-gate HEMT structure was fabricated using a SiN gate insulator formed by catalytic chemical vapor deposition (Cat-CVD). The Cat-CVD SiN thin film (5 nm) was found to be an effective gate insulator with good gate controllability and dielectric properties. We previously investigated device characteristics of sub-100-nm-gate-length Schottky- and MIS-gate HEMTs, and reported that the MIS-gate device had larger maximum drain current density and transconductance (g{sub m}) than the Schottky-gate device. The radio frequency (RF) measurement of the MIS-gate device, however, showed a relatively lower current gain cutoff frequency f{sub T} compared with that of the Schottky-gate device. In this study, C-V characterization of the MIS-gate HEMT structure demonstrated that two electron transport channels existed, one at the SiGe/Si buried channel and the other at the SiN/Si surface channel.

  1. Contemporary dielectric materials

    CERN Document Server

    Saravanan, R

    2016-01-01

    This book deals with experimental results of the physical characterization of several important, dielectric materials of great current interest. The experimental tools used for the analysis of these materials include X-ray diffraction, dielectric measurements, magnetic measurements using a vibrating sample magnetometer, optical measurements using a UV-Visible spectrometer etc.

  2. Thermal dielectric function

    International Nuclear Information System (INIS)

    Moneta, M.

    1999-01-01

    Thermal dielectric functions ε(k,ω) for homogeneous electron gas were determined and discussed. The ground state of the gas is described by the Fermi-Dirac momentum distribution. The low and high temperature limits of ε(k,ω) were related to the Lindhard dielectric function and to ε(k, omega) derived for Boltzmann and for classical momentum distributions, respectively. (author)

  3. Light in complex dielectrics

    NARCIS (Netherlands)

    Schuurmans, F.J.P.

    1999-01-01

    In this thesis the properties of light in complex dielectrics are described, with the two general topics of "modification of spontaneous emission" and "Anderson localization of light". The first part focuses on the spontaneous emission rate of an excited atom in a dielectric host with variable

  4. Study of the tunnelling initiated leakage current through the carbon nanotube embedded gate oxide in metal oxide semiconductor structures

    International Nuclear Information System (INIS)

    Chakraborty, Gargi; Sarkar, C K; Lu, X B; Dai, J Y

    2008-01-01

    The tunnelling currents through the gate dielectric partly embedded with semiconducting single-wall carbon nanotubes in a silicon metal-oxide-semiconductor (MOS) structure have been investigated. The application of the gate voltage to such an MOS device results in the band bending at the interface of the partly embedded oxide dielectric and the surface of the silicon, initiating tunnelling through the gate oxide responsible for the gate leakage current whenever the thickness of the oxide is scaled. A model for silicon MOS structures, where carbon nanotubes are confined in a narrow layer embedded in the gate dielectric, is proposed to investigate the direct and the Fowler-Nordheim (FN) tunnelling currents of such systems. The idea of embedding such elements in the gate oxide is to assess the possibility for charge storage for memory device applications. Comparing the FN tunnelling onset voltage between the pure gate oxide and the gate oxide embedded with carbon nanotubes, it is found that the onset voltage decreases with the introduction of the nanotubes. The direct tunnelling current has also been studied at very low gate bias, for the thin oxide MOS structure which plays an important role in scaling down the MOS transistors. The FN tunnelling current has also been studied with varying nanotube diameter

  5. Quantum gate decomposition algorithms.

    Energy Technology Data Exchange (ETDEWEB)

    Slepoy, Alexander

    2006-07-01

    Quantum computing algorithms can be conveniently expressed in a format of a quantum logical circuits. Such circuits consist of sequential coupled operations, termed ''quantum gates'', or quantum analogs of bits called qubits. We review a recently proposed method [1] for constructing general ''quantum gates'' operating on an qubits, as composed of a sequence of generic elementary ''gates''.

  6. Materials science, integration, and performance characterization of high-dielectric constant thin film based devices

    Science.gov (United States)

    Fan, Wei

    To overcome the oxidation and diffusion problems encountered during Copper integration with oxide thin film-based devices, TiAl/Cu/Ta heterostructure has been first developed in this study. Investigation on the oxidation and diffusion resistance of the laminate structure showed high electrical conductance and excellent thermal stability in oxygen environment. Two amorphous oxide layers that were formed on both sides of the TiAl barrier after heating in oxygen have been revealed as the structure that effectively prevents oxygen penetration and protects the integrity of underlying Cu layer. Polycrystalline (BaxSr1-x)TiO3 (BST) thin films were subsequently deposited on the Cu-based bottom electrode by RF magnetron sputtering to investigate the interaction between the oxide and Cu layers. The thickness of the interfacial layer and interface roughness play critical roles in the optimization of the electrical performance of the BST capacitors using Cu-based electrode. It was determined that BST deposition at moderate temperature followed by rapid thermal annealing in pure oxygen yields BST/Cu capacitors with good electrical properties for application to high frequency devices. The knowledge obtained on the study of barrier properties of TiAl inspired a continuous research on the materials science issues related to the application of the hybrid TiAlOx, as high-k gate dielectric in MOSFET devices. Novel fabrication process such as deposition of ultra-thin TiAl alloy layer followed by oxidation with atomic oxygen has been established in this study. Stoichiometric amorphous TiAlOx layers, exhibiting only Ti4+ and Al3+ states, were produced with a large variation of oxidation temperature (700°C to room temperature). The interfacial SiOx formation between TiAlOx and Si was substantially inhibited by the use of the low temperature oxidation process. Electrical characterization revealed a large permittivity of 30 and an improved band structure for the produced TiAlOx layers

  7. Metallorganic chemical vapor deposition and atomic layer deposition approaches for the growth of hafnium-based thin films from dialkylamide precursors for advanced CMOS gate stack applications

    Science.gov (United States)

    Consiglio, Steven P.

    To continue the rapid progress of the semiconductor industry as described by Moore's Law, the feasibility of new material systems for front end of the line (FEOL) process technologies needs to be investigated, since the currently employed polysilicon/SiO2-based transistor system is reaching its fundamental scaling limits. Revolutionary breakthroughs in complementary-metal-oxide-semiconductor (CMOS) technology were recently announced by Intel Corporation and International Business Machines Corporation (IBM), with both organizations revealing significant progress in the implementation of hafnium-based high-k dielectrics along with metal gates. This announcement was heralded by Gordon Moore as "...the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s." Accordingly, the study described herein focuses on the growth of Hf-based dielectrics and Hf-based metal gates using chemical vapor-based deposition methods, specifically metallorganic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). A family of Hf source complexes that has received much attention recently due to their desirable properties for implementation in wafer scale manufacturing is the Hf dialkylamide precursors. These precursors are room temperature liquids and possess sufficient volatility and desirable decomposition characteristics for both MOCVD and ALD processing. Another benefit of using these sources is the existence of chemically compatible Si dialkylamide sources as co-precursors for use in Hf silicate growth. The first part of this study investigates properties of MOCVD-deposited HfO2 and HfSixOy using dimethylamido Hf and Si precursor sources using a customized MOCVD reactor. The second part of this study involves a study of wet and dry surface pre-treatments for ALD growth of HfO2 using tetrakis(ethylmethylamido)hafnium in a wafer scale manufacturing environment. The third part of this study is an investigation of

  8. Thin film transistors for flexible electronics: Contacts, dielectrics and semiconductors

    KAUST Repository

    Quevedo-López, Manuel Angel Quevedo

    2011-06-01

    The development of low temperature, thin film transistor processes that have enabled flexible displays also present opportunities for flexible electronics and flexible integrated systems. Of particular interest are possible applications in flexible sensor systems for unattended ground sensors, smart medical bandages, electronic ID tags for geo-location, conformal antennas, radiation detectors, etc. In this paper, we review the impact of gate dielectrics, contacts and semiconductor materials on thin film transistors for flexible electronics applications. We present our recent results to fully integrate hybrid complementary metal oxide semiconductors comprising inorganic and organic-based materials. In particular, we demonstrate novel gate dielectric stacks and semiconducting materials. The impact of source and drain contacts on device performance is also discussed. Copyright © 2011 American Scientific Publishers.

  9. Thin film transistors for flexible electronics: Contacts, dielectrics and semiconductors

    KAUST Repository

    Quevedo-Ló pez, Manuel Angel Quevedo; Wondmagegn, Wudyalew T.; Alshareef, Husam N.; Ramí rez-Bon, Rafael; Gnade, Bruce E.

    2011-01-01

    The development of low temperature, thin film transistor processes that have enabled flexible displays also present opportunities for flexible electronics and flexible integrated systems. Of particular interest are possible applications in flexible sensor systems for unattended ground sensors, smart medical bandages, electronic ID tags for geo-location, conformal antennas, radiation detectors, etc. In this paper, we review the impact of gate dielectrics, contacts and semiconductor materials on thin film transistors for flexible electronics applications. We present our recent results to fully integrate hybrid complementary metal oxide semiconductors comprising inorganic and organic-based materials. In particular, we demonstrate novel gate dielectric stacks and semiconducting materials. The impact of source and drain contacts on device performance is also discussed. Copyright © 2011 American Scientific Publishers.

  10. Low pull-in voltage electrostatic MEMS switch using liquid dielectric

    KAUST Repository

    Zidan, Mohammed A.

    2014-08-01

    In this paper, we present an electrostatic MEMS switch with liquids as dielectric to reduce the actuation voltage. The concept is verified by simulating a lateral dual gate switch, where the required pull-in voltage is reduced by more than 8 times after using water as a dielectric, to become as low as 5.36V. The proposed switch is simulated using COMSOL multiphysics using various liquid volumes to study their effect on the switching performance. Finally, we propose the usage of the lateral switch as a single switch XOR logic gate.

  11. Improved linearity in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with nonlinear polarization dielectric

    International Nuclear Information System (INIS)

    Gao, Tao; Xu, Ruimin; Kong, Yuechan; Zhou, Jianjun; Kong, Cen; Dong, Xun; Chen, Tangsheng

    2015-01-01

    We demonstrate highly improved linearity in a nonlinear ferroelectric of Pb(Zr 0.52 Ti 0.48 )-gated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). Distinct double-hump feature in the transconductance-gate voltage (g m -V g ) curve is observed, yielding remarkable enhancement in gate voltage swing as compared to MIS-HEMT with conventional linear gate dielectric. By incorporating the ferroelectric polarization into a self-consistent calculation, it is disclosed that in addition to the common hump corresponding to the onset of electron accumulation, the second hump at high current level is originated from the nonlinear polar nature of ferroelectric, which enhances the gate capacitance by increasing equivalent dielectric constant nonlinearly. This work paves a way for design of high linearity GaN MIS-HEMT by exploiting the nonlinear properties of dielectric

  12. Improved linearity in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with nonlinear polarization dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Gao, Tao [Fundamental Science on EHF Laboratory, University of Electronic Science and Technology of China (UESTC), Chengdu 611731 (China); Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Devices Institute, Nanjing 210016 (China); Xu, Ruimin [Fundamental Science on EHF Laboratory, University of Electronic Science and Technology of China (UESTC), Chengdu 611731 (China); Kong, Yuechan, E-mail: kycfly@163.com; Zhou, Jianjun; Kong, Cen; Dong, Xun; Chen, Tangsheng [Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Devices Institute, Nanjing 210016 (China)

    2015-06-15

    We demonstrate highly improved linearity in a nonlinear ferroelectric of Pb(Zr{sub 0.52}Ti{sub 0.48})-gated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). Distinct double-hump feature in the transconductance-gate voltage (g{sub m}-V{sub g}) curve is observed, yielding remarkable enhancement in gate voltage swing as compared to MIS-HEMT with conventional linear gate dielectric. By incorporating the ferroelectric polarization into a self-consistent calculation, it is disclosed that in addition to the common hump corresponding to the onset of electron accumulation, the second hump at high current level is originated from the nonlinear polar nature of ferroelectric, which enhances the gate capacitance by increasing equivalent dielectric constant nonlinearly. This work paves a way for design of high linearity GaN MIS-HEMT by exploiting the nonlinear properties of dielectric.

  13. Improved Dielectric Films For Capacitors

    Science.gov (United States)

    Yen, Shiao-Ping S.; Lewis, Carol R.; Cygan, Peter J.; Jow, T. Richard

    1994-01-01

    Dielectric films made from blends of some commercially available high-dielectric-constant cyanoresins with each other and with cellulose triacetate (CTA) have both high dielectric constants and high breakdown strengths. Dielectric constants as high as 16.2. Films used to produce high-energy-density capacitors.

  14. The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

    Science.gov (United States)

    Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Wang, Qianqiong

    2018-03-01

    The DRAM based on the dual-gate tunneling FET (DGTFET) has the advantages of capacitor-less structure and high retention time. In this paper, the optimization of spacer engineering for DGTFET DRAM is systematically investigated by Silvaco-Atlas tool to further improve its performance, including the reduction of reading "0" current and extension of retention time. The simulation results show that spacers at the source and drain sides should apply the low-k and high-k dielectrics, respectively, which can enhance the reading "1" current and reduce reading "0" current. Applying this optimized spacer engineering, the DGTFET DRAM obtains the optimum performance-extremely low reading "0" current (10-14A/μm) and large retention time (10s), which decreases its static power consumption and dynamic refresh rate. And the low reading "0" current also enhances its current ratio (107) of reading "1" to reading "0". Furthermore, the analysis about scalability reveals its inherent shortcoming, which offers the further investigation direction for DGTFET DRAM.

  15. The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor.

    Science.gov (United States)

    Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Wang, Qianqiong

    2018-03-05

    The DRAM based on the dual-gate tunneling FET (DGTFET) has the advantages of capacitor-less structure and high retention time. In this paper, the optimization of spacer engineering for DGTFET DRAM is systematically investigated by Silvaco-Atlas tool to further improve its performance, including the reduction of reading "0" current and extension of retention time. The simulation results show that spacers at the source and drain sides should apply the low-k and high-k dielectrics, respectively, which can enhance the reading "1" current and reduce reading "0" current. Applying this optimized spacer engineering, the DGTFET DRAM obtains the optimum performance-extremely low reading "0" current (10 -14 A/μm) and large retention time (10s), which decreases its static power consumption and dynamic refresh rate. And the low reading "0" current also enhances its current ratio (10 7 ) of reading "1" to reading "0". Furthermore, the analysis about scalability reveals its inherent shortcoming, which offers the further investigation direction for DGTFET DRAM.

  16. Enhancing electrical energy storage capability of dielectric polymer nanocomposites via the room temperature Coulomb blockade effect of ultra-small platinum nanoparticles.

    Science.gov (United States)

    Wang, Liwei; Huang, Xingyi; Zhu, Yingke; Jiang, Pingkai

    2018-02-14

    Introducing a high dielectric constant (high-k) nanofiller into a dielectric polymer is the most common way to achieve flexible nanocomposites for electrostatic energy storage devices. However, the significant decrease of breakdown strength and large increase of dielectric loss has long been known as the bottleneck restricting the enhancement of practical energy storage capability of the nanocomposites. In this study, by introducing ultra-small platinum (energy density of the Pt@PDA@BT nanocomposites is increased by nearly 70% because of the improved energy storage efficiency. This research provides a simple, promising and unique way to enhance energy storage capability of high-k polymer nanocomposites.

  17. Signatures of Mechanosensitive Gating.

    Science.gov (United States)

    Morris, Richard G

    2017-01-10

    The question of how mechanically gated membrane channels open and close is notoriously difficult to address, especially if the protein structure is not available. This perspective highlights the relevance of micropipette-aspirated single-particle tracking-used to obtain a channel's diffusion coefficient, D, as a function of applied membrane tension, σ-as an indirect assay for determining functional behavior in mechanosensitive channels. While ensuring that the protein remains integral to the membrane, such methods can be used to identify not only the gating mechanism of a protein, but also associated physical moduli, such as torsional and dilational rigidity, which correspond to the protein's effective shape change. As an example, three distinct D-versus-σ "signatures" are calculated, corresponding to gating by dilation, gating by tilt, and gating by a combination of both dilation and tilt. Both advantages and disadvantages of the approach are discussed. Copyright © 2017 Biophysical Society. Published by Elsevier Inc. All rights reserved.

  18. Gate-induced carrier delocalization in quantum dot field effect transistors.

    Science.gov (United States)

    Turk, Michael E; Choi, Ji-Hyuk; Oh, Soong Ju; Fafarman, Aaron T; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R; Kikkawa, James M

    2014-10-08

    We study gate-controlled, low-temperature resistance and magnetotransport in indium-doped CdSe quantum dot field effect transistors. We show that using the gate to accumulate electrons in the quantum dot channel increases the "localization product" (localization length times dielectric constant) describing transport at the Fermi level, as expected for Fermi level changes near a mobility edge. Our measurements suggest that the localization length increases to significantly greater than the quantum dot diameter.

  19. Dielectric materials for electrical engineering

    CERN Document Server

    Martinez-Vega, Juan

    2013-01-01

    Part 1 is particularly concerned with physical properties, electrical ageing and modeling with topics such as the physics of charged dielectric materials, conduction mechanisms, dielectric relaxation, space charge, electric ageing and life end models and dielectric experimental characterization. Part 2 concerns some applications specific to dielectric materials: insulating oils for transformers, electrorheological fluids, electrolytic capacitors, ionic membranes, photovoltaic conversion, dielectric thermal control coatings for geostationary satellites, plastics recycling and piezoelectric poly

  20. Cast dielectric composite linear accelerator

    Science.gov (United States)

    Sanders, David M [Livermore, CA; Sampayan, Stephen [Manteca, CA; Slenes, Kirk [Albuquerque, NM; Stoller, H M [Albuquerque, NM

    2009-11-10

    A linear accelerator having cast dielectric composite layers integrally formed with conductor electrodes in a solventless fabrication process, with the cast dielectric composite preferably having a nanoparticle filler in an organic polymer such as a thermosetting resin. By incorporating this cast dielectric composite the dielectric constant of critical insulating layers of the transmission lines of the accelerator are increased while simultaneously maintaining high dielectric strengths for the accelerator.

  1. Light programmable organic transistor memory device based on hybrid dielectric

    Science.gov (United States)

    Ren, Xiaochen; Chan, Paddy K. L.

    2013-09-01

    We have fabricated the transistor memory devices based on SiO2 and polystyrene (PS) hybrid dielectric. The trap states densities with different semiconductors have been investigated and a maximum 160V memory window between programming and erasing is realized. For DNTT based transistor, the trapped electron density is limited by the number of mobile electrons in semiconductor. The charge transport mechanism is verified by light induced Vth shift effect. Furthermore, in order to meet the low operating power requirement of portable electronic devices, we fabricated the organic memory transistor based on AlOx/self-assembly monolayer (SAM)/PS hybrid dielectric, the effective capacitance of hybrid dielectric is 210 nF cm-2 and the transistor can reach saturation state at -3V gate bias. The memory window in transfer I-V curve is around 1V under +/-5V programming and erasing bias.

  2. Work Function Tuning in Sub-20nm Titanium Nitride (TiN) Metal Gate: Mechanism and Engineering

    KAUST Repository

    Hasan, Mehdi

    2011-07-01

    Scaling of transistors (the building blocks of modern information age) provides faster computation at the expense of excessive power dissipation. Thus to address these challenges, high-k/metal gate stack has been introduced in commercially available microprocessors from 2007. Since then titanium nitride (TiN) metal gate’s work function (Wf) tunability with its thickness (thickness increases, work function increases) is a well known phenomenon. Many hypotheses have been made over the years which include but not limited to: trap charge and metal gate nucleation, nitrogen concentration, microstructure agglomeration and global stress, metal oxide formation, and interfacial oxide thickness. However, clear contradictions exist in these assumptions. Also, nearly all these reports skipped a comprehensive approach to explain this complex paradigm. Therefore, in this work we first show a comprehensive physical investigation using transmission electron microcopy/electron energy loss spectroscopy (TEM/EELS), x-ray diffraction (XRD), x-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS) to show replacement of oxygen by nitrogen in the metal/dielectric interface, formation of TiONx, reduction of Ti/N concentration and grain size increment happen with TiN thickness increment and thus may increase the work function. Then, using these finding, we experimentally show 100meV of work function modulation in 10nm TiN Metal-oxide-semiconductor capacitor by using low temperature oxygen annealing. A low thermal budget flow (replicating gate-last) shows similar work function boost up. Also, a work function modulation of 250meV has been possible using oxygen annealing and applying no thermal budget. On the other hand, etch-back of TiN layer can decrease the work function. Thus this study quantifies role of various factors in TiN work function tuning; it also reproduces the thickness varied TiN work function modulation in single thickness TiN thus reducing the

  3. Optics of dielectric microstructures

    DEFF Research Database (Denmark)

    Søndergaard, Thomas

    2002-01-01

    From the work carried out within the ph.d. project two topics have been selected for this thesis, namely emission of radiation by sources in dielectric microstructures, and planar photonic crystal waveguides. The work done within the first topic, emission of radiation by sources in dielectric...... microstructures, will be presented in the part I of this thesis consisting of the chapters 2-5. An introductions is given in chapter 2. In part I three methods are presented for calculating spontaneous and classical emission from sources in dielectric microstructures. The first method presented in chapter 3...... is based on the Fermi Golden Rule, and spontaneous emission from emitters in a passive dielectric microstructure is calculated by summing over the emission into each electromagnetic mode of the radiation field. This method is applied to investigate spontaneous emission in a two-dimensional photonic crystal...

  4. Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

    Science.gov (United States)

    An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

    2016-11-01

    Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

  5. Structured-gate organic field-effect transistors

    International Nuclear Information System (INIS)

    Aljada, Muhsen; Pandey, Ajay K; Velusamy, Marappan; Burn, Paul L; Meredith, Paul; Namdas, Ebinazar B

    2012-01-01

    We report the fabrication and electrical characteristics of structured-gate organic field-effect transistors consisting of a gate electrode patterned with three-dimensional pillars. The pillar gate electrode was over-coated with a gate dielectric (SiO 2 ) and solution processed organic semiconductors producing both unipolar p-type and bipolar behaviour. We show that this new structured-gate architecture delivers higher source-drain currents, higher gate capacitance per unit equivalent linear channel area, and enhanced charge injection (electrons and/or holes) versus the conventional planar structure in all modes of operation. For the bipolar field-effect transistor (FET) the maximum source-drain current enhancements in p- and n-channel mode were >600% and 28%, respectively, leading to p and n charge mobilities with the same order of magnitude. Thus, we have demonstrated that it is possible to use the FET architecture to manipulate and match carrier mobilities of material combinations where one charge carrier is normally dominant. Mobility matching is advantageous for creating organic logic circuit elements such as inverters and amplifiers. Hence, the method represents a facile and generic strategy for improving the performance of standard organic semiconductors as well as new materials and blends. (paper)

  6. Structured-gate organic field-effect transistors

    Science.gov (United States)

    Aljada, Muhsen; Pandey, Ajay K.; Velusamy, Marappan; Burn, Paul L.; Meredith, Paul; Namdas, Ebinazar B.

    2012-06-01

    We report the fabrication and electrical characteristics of structured-gate organic field-effect transistors consisting of a gate electrode patterned with three-dimensional pillars. The pillar gate electrode was over-coated with a gate dielectric (SiO2) and solution processed organic semiconductors producing both unipolar p-type and bipolar behaviour. We show that this new structured-gate architecture delivers higher source-drain currents, higher gate capacitance per unit equivalent linear channel area, and enhanced charge injection (electrons and/or holes) versus the conventional planar structure in all modes of operation. For the bipolar field-effect transistor (FET) the maximum source-drain current enhancements in p- and n-channel mode were >600% and 28%, respectively, leading to p and n charge mobilities with the same order of magnitude. Thus, we have demonstrated that it is possible to use the FET architecture to manipulate and match carrier mobilities of material combinations where one charge carrier is normally dominant. Mobility matching is advantageous for creating organic logic circuit elements such as inverters and amplifiers. Hence, the method represents a facile and generic strategy for improving the performance of standard organic semiconductors as well as new materials and blends.

  7. Effect of dielectric layers on device stability of pentacene-based field-effect transistors.

    Science.gov (United States)

    Di, Chong-an; Yu, Gui; Liu, Yunqi; Guo, Yunlong; Sun, Xiangnan; Zheng, Jian; Wen, Yugeng; Wang, Ying; Wu, Weiping; Zhu, Daoben

    2009-09-07

    We report stable organic field-effect transistors (OFETs) based on pentacene. It was found that device stability strongly depends on the dielectric layer. Pentacene thin-film transistors based on the bare or polystyrene-modified SiO(2) gate dielectrics exhibit excellent electrical stabilities. In contrast, the devices with the octadecyltrichlorosilane (OTS)-treated SiO(2) dielectric layer showed the worst stabilities. The effects of the different dielectrics on the device stabilities were investigated. We found that the surface energy of the gate dielectric plays a crucial role in determining the stability of the pentacene thin film, device performance and degradation of electrical properties. Pentacene aggregation, phase transfer and film morphology are also important factors that influence the device stability of pentacene devices. As a result of the surface energy mismatch between the dielectric layer and organic semiconductor, the electronic performance was degraded. Moreover, when pentacene was deposited on the OTS-treated SiO(2) dielectric layer with very low surface energy, pentacene aggregation occurred and resulted in a dramatic decrease of device performance. These results demonstrated that the stable OFETs could be obtained by using pentacene as a semiconductor layer.

  8. Optical XOR gate

    Science.gov (United States)

    Vawter, G. Allen

    2013-11-12

    An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  9. Direct Effect of Dielectric Surface Energy on Carrier Transport in Organic Field-Effect Transistors.

    Science.gov (United States)

    Zhou, Shujun; Tang, Qingxin; Tian, Hongkun; Zhao, Xiaoli; Tong, Yanhong; Barlow, Stephen; Marder, Seth R; Liu, Yichun

    2018-05-09

    The understanding of the characteristics of gate dielectric that leads to optimized carrier transport remains controversial, and the conventional studies applied organic semiconductor thin films, which introduces the effect of dielectric on the growth of the deposited semiconductor thin films and hence only can explore the indirect effects. Here, we introduce pregrown organic single crystals to eliminate the indirect effect (semiconductor growth) in the conventional studies and to undertake an investigation of the direct effect of dielectric on carrier transport. It is shown that the matching of the polar and dispersive components of surface energy between semiconductor and dielectric is favorable for higher mobility. This new empirical finding may show the direct relationship between dielectric and carrier transport for the optimized mobility of organic field-effect transistors and hence show a promising potential for the development of next-generation high-performance organic electronic devices.

  10. Screening-induced surface polar optical phonon scattering in dual-gated graphene field effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Hu, Bo, E-mail: hubo2011@semi.ac.cn

    2015-03-15

    The effect of surface polar optical phonons (SOs) from the dielectric layers on electron mobility in dual-gated graphene field effect transistors (GFETs) is studied theoretically. By taking into account SO scattering of electron as a main scattering mechanism, the electron mobility is calculated by the iterative solution of Boltzmann transport equation. In treating scattering with the SO modes, the dynamic dielectric screening is included and compared to the static dielectric screening and the dielectric screening in the static limit. It is found that the dynamic dielectric screening effect plays an important role in the range of low net carrier density. More importantly, in-plane acoustic phonon scattering and charged impurity scattering are also included in the total mobility for SiO{sub 2}-supported GFETs with various high-κ top-gate dielectric layers considered. The calculated total mobility results suggest both Al{sub 2}O{sub 3} and AlN are the promising candidate dielectric layers for the enhancement in room temperature mobility of graphene in the future.

  11. Structure and performance of dielectric films based on self-assembled nanocrystals with a high dielectric constant.

    Science.gov (United States)

    Huang, Limin; Liu, Shuangyi; Van Tassell, Barry J; Liu, Xiaohua; Byro, Andrew; Zhang, Henan; Leland, Eli S; Akins, Daniel L; Steingart, Daniel A; Li, Jackie; O'Brien, Stephen

    2013-10-18

    Self-assembled films built from nanoparticles with a high dielectric constant are attractive as a foundation for new dielectric media with increased efficiency and range of operation, due to the ability to exploit nanofabrication techniques and emergent electrical properties originating from the nanoscale. However, because the building block is a discrete one-dimensional unit, it becomes a challenge to capture potential enhancements in dielectric performance in two or three dimensions, frequently due to surface effects or the presence of discontinuities. This is a recurring theme in nanoparticle film technology when applied to the realm of thin film semiconductor and device electronics. We present the use of chemically synthesized (Ba,Sr)TiO3 nanocrystals, and a novel deposition-polymerization technique, as a means to fabricate the dielectric layer. The effective dielectric constant of the film is tunable according to nanoparticle size, and effective film dielectric constants of up to 34 are enabled. Wide area and multilayer dielectrics of up to 8 cm(2) and 190 nF are reported, for which the building block is an 8 nm nanocrystal. We describe models for assessing dielectric performance, and distinct methods for improving the dielectric constant of a nanocrystal thin film. The approach relies on evaporatively driven assembly of perovskite nanocrystals with uniform size distributions in a tunable 7-30 nm size range, coupled with the use of low molecular weight monomer/polymer precursor chemistry that can infiltrate the porous nanocrystal thin film network post assembly. The intercrystal void space (low k dielectric volume fraction) is minimized, while simultaneously promoting intercrystal connectivity and maximizing volume fraction of the high k dielectric component. Furfuryl alcohol, which has good affinity to the surface of (Ba,Sr)TiO3 nanocrystals and miscibility with a range of solvents, is demonstrated to be ideal for the production of nanocomposites. The

  12. High performance top-gated indium–zinc–oxide thin film transistors with in-situ formed HfO{sub 2} gate insulator

    Energy Technology Data Exchange (ETDEWEB)

    Song, Yang, E-mail: yang_song@brown.edu [Department of Physics, Brown University, 182 Hope Street, Providence, RI 02912 (United States); Zaslavsky, A. [Department of Physics, Brown University, 182 Hope Street, Providence, RI 02912 (United States); School of Engineering, Brown University, 184 Hope Street, Providence, RI 02912 (United States); Paine, D.C. [School of Engineering, Brown University, 184 Hope Street, Providence, RI 02912 (United States)

    2016-09-01

    We report on top-gated indium–zinc–oxide (IZO) thin film transistors (TFTs) with an in-situ formed HfO{sub 2} gate dielectric insulator. Building on our previous demonstration of high-performance IZO TFTs with Al{sub 2}O{sub 3}/HfO{sub 2} gate dielectric, we now report on a one-step process, in which Hf is evaporated onto the 20 nm thick IZO channel, forming a partially oxidized HfO{sub x} layer, without any additional insulator in-between. After annealing in air at 300 °C, the in-situ reaction between partially oxidized Hf and IZO forms a high quality HfO{sub 2} gate insulator with a low interface trapped charge density N{sub TC} ~ 2.3 × 10{sup 11} cm{sup −2} and acceptably low gate leakage < 3 × 10{sup −7} A/cm{sup 2} at gate voltage V{sub G} = 1 V. The annealed TFTs with gate length L{sub G} = 50 μm have high mobility ~ 95 cm{sup 2}/V ∙ s (determined via the Y-function technique), high on/off ratio ~ 10{sup 7}, near-zero threshold voltage V{sub T} = − 0.02 V, and a subthreshold swing of 0.062 V/decade, near the theoretical limit. The on-current of our proof-of-concept TFTs is relatively low, but can be improved by reducing L{sub G}, indicating that high-performance top-gated HfO{sub 2}-isolated IZO TFTs can be fabricated using a single-step in-situ dielectric formation approach. - Highlights: • High-performance indium–zinc–oxide (IZO) thin film transistors (TFTs). • Single-step in-situ dielectric formation approach simplifies fabrication process. • During anneal, reaction between HfO{sub x} and IZO channel forms a high quality HfO{sub 2} layer. • Gate insulator HfO{sub 2} shows low interface trapped charge and small gate leakage. • TFTs have high mobility, near-zero threshold voltage, and a low subthreshold swing.

  13. Low pull-in voltage electrostatic MEMS switch using liquid dielectric

    KAUST Repository

    Zidan, Mohammed A.; Kosel, Jü rgen; Salama, Khaled N.

    2014-01-01

    In this paper, we present an electrostatic MEMS switch with liquids as dielectric to reduce the actuation voltage. The concept is verified by simulating a lateral dual gate switch, where the required pull-in voltage is reduced by more than 8 times

  14. Processing and performance of organic insulators as a gate layer in ...

    Indian Academy of Sciences (India)

    Fabrication of organic thin film transistor (OTFT) on flexible substrates is a challenge, because of its low softening temperature, high roughness and flexible nature. Although several organic dielectrics have been used as gate insulator, it is difficult to choose one in absence of a comparative study covering processing of ...

  15. Processing and performance of organic insulators as a gate layer in ...

    Indian Academy of Sciences (India)

    Abstract. Fabrication of organic thin film transistor (OTFT) on flexible substrates is a challenge, because of its low softening temperature, high roughness and flexible nature. Although several organic dielectrics have been used as gate insulator, it is difficult to choose one in absence of a comparative study covering ...

  16. Super Dielectric Materials.

    Science.gov (United States)

    Fromille, Samuel; Phillips, Jonathan

    2014-12-22

    Evidence is provided here that a class of materials with dielectric constants greater than 10⁵ at low frequency (dielectric materials (SDM), can be generated readily from common, inexpensive materials. Specifically it is demonstrated that high surface area alumina powders, loaded to the incipient wetness point with a solution of boric acid dissolved in water, have dielectric constants, near 0 Hz, greater than 4 × 10⁸ in all cases, a remarkable increase over the best dielectric constants previously measured for energy storage capabilities, ca. 1 × 10⁴. It is postulated that any porous, electrically insulating material (e.g., high surface area powders of silica, titania, etc. ), filled with a liquid containing a high concentration of ionic species will potentially be an SDM. Capacitors created with the first generated SDM dielectrics (alumina with boric acid solution), herein called New Paradigm Super (NPS) capacitors display typical electrostatic capacitive behavior, such as increasing capacitance with decreasing thickness, and can be cycled, but are limited to a maximum effective operating voltage of about 0.8 V. A simple theory is presented: Water containing relatively high concentrations of dissolved ions saturates all, or virtually all, the pores (average diameter 500 Å) of the alumina. In an applied field the positive ionic species migrate to the cathode end, and the negative ions to the anode end of each drop. This creates giant dipoles with high charge, hence leading to high dielectric constant behavior. At about 0.8 V, water begins to break down, creating enough ionic species to "short" the individual water droplets. Potentially NPS capacitor stacks can surpass "supercapacitors" in volumetric energy density.

  17. Super Dielectric Materials

    Directory of Open Access Journals (Sweden)

    Samuel Fromille

    2014-12-01

    Full Text Available Evidence is provided here that a class of materials with dielectric constants greater than 105 at low frequency (<10−2 Hz, herein called super dielectric materials (SDM, can be generated readily from common, inexpensive materials. Specifically it is demonstrated that high surface area alumina powders, loaded to the incipient wetness point with a solution of boric acid dissolved in water, have dielectric constants, near 0 Hz, greater than 4 × 108 in all cases, a remarkable increase over the best dielectric constants previously measured for energy storage capabilities, ca. 1 × 104. It is postulated that any porous, electrically insulating material (e.g., high surface area powders of silica, titania, etc., filled with a liquid containing a high concentration of ionic species will potentially be an SDM. Capacitors created with the first generated SDM dielectrics (alumina with boric acid solution, herein called New Paradigm Super (NPS capacitors display typical electrostatic capacitive behavior, such as increasing capacitance with decreasing thickness, and can be cycled, but are limited to a maximum effective operating voltage of about 0.8 V. A simple theory is presented: Water containing relatively high concentrations of dissolved ions saturates all, or virtually all, the pores (average diameter 500 Å of the alumina. In an applied field the positive ionic species migrate to the cathode end, and the negative ions to the anode end of each drop. This creates giant dipoles with high charge, hence leading to high dielectric constant behavior. At about 0.8 V, water begins to break down, creating enough ionic species to “short” the individual water droplets. Potentially NPS capacitor stacks can surpass “supercapacitors” in volumetric energy density.

  18. Thermally switchable dielectrics

    Science.gov (United States)

    Dirk, Shawn M.; Johnson, Ross S.

    2013-04-30

    Precursor polymers to conjugated polymers, such as poly(phenylene vinylene), poly(poly(thiophene vinylene), poly(aniline vinylene), and poly(pyrrole vinylene), can be used as thermally switchable capacitor dielectrics that fail at a specific temperature due to the non-conjugated precursor polymer irreversibly switching from an insulator to the conjugated polymer, which serves as a bleed resistor. The precursor polymer is a good dielectric until it reaches a specific temperature determined by the stability of the leaving groups. Conjugation of the polymer backbone at high temperature effectively disables the capacitor, providing a `built-in` safety mechanism for electronic devices.

  19. On dielectric breakdown statistics

    International Nuclear Information System (INIS)

    Tuncer, Enis; James, D Randy; Sauers, Isidor; Ellis, Alvin R; Pace, Marshall O

    2006-01-01

    In this paper, we investigate the dielectric breakdown data of some insulating materials and focus on the applicability of the two- and three-parameter Weibull distributions. A new distribution function is also proposed. In order to assess the model distribution's trustworthiness, we employ the Monte Carlo technique and, randomly selecting data-subsets from the whole dielectric breakdown data, determine whether the selected probability functions accurately describe the breakdown data. The utility and strength of the proposed expression are illustrated distinctly by the numerical procedure. The proposed expression is shown to be a valuable alternative to the Weibull ones

  20. Chemical sensitivity of Mo gate Mos capacitors

    Energy Technology Data Exchange (ETDEWEB)

    Lombardi, R.M.; Aragon, R. [Laboratorio de Peliculas delgadas, Facultad de Ingenieria, Paseo Colon 850, 1063, Buenos Aires (Argentina)

    2006-07-01

    Mo gate Mos capacitors exhibit a negative shift of their C-V characteristic by up to 240 mV, at 125 C, in response to 1000 ppm hydrogen, in controlled nitrogen atmospheres. The experimental methods for obtaining capacitance and conductance, as a function of polarisation voltage, as well as the relevant equivalent circuits are reviewed. The single-state interface state density, at the semiconductor-dielectric interface, decreases from 2.66 x 10{sup 11} cm{sup -2} e-v{sup -1}, in pure nitrogen, to 2.5 x 10{sup 11} cm{sup -2} e-v{sup -1} in 1000 ppm hydrogen in nitrogen mixtures, at this temperature. (Author)

  1. Multi-quasiparticle high-K isomeric states in deformed nuclei

    Directory of Open Access Journals (Sweden)

    Xu F. R.

    2016-01-01

    Full Text Available In the past years, we have made many theoretical investigations on multi-quasiparticle high-K isomeric states. A deformation-pairing-configuration self-consistent calculation has been developed by calculating a configuration-constrained multi-quasiparticle potential energy surface (PES. The specific single-particle orbits that define the high-K configuration are identified and tracked (adiabatically blocked by calculating the average Nilsson numbers. The deformed Woods-Saxon potential was taken to give single-particle orbits. The configuration-constrained PES takes into account the shape polarization effect. Such calculations give good results on excitation energies, deformations and other structure information about multi-quasiparticle high-K isomeric states. Many different mass regions have been investigated.

  2. High-Sensitivity, Highly Transparent, Gel-Gated MoS2 Phototransistor on Biodegradable Nanopaper

    KAUST Repository

    Zhang, Qing

    2016-06-21

    Transition metal dichalcogenides hold great promise for a variety of novel electrical, optical and mechanical devices and applications. Among them, molybdenum disulphide (MoS2) is gaining increasing attention as the gate dielectric and semiconductive channel for high-perfomance field effect transistors. Here we report on the first MoS2 phototransistor built on flexible, transparent and biodegradable substrate with electrolyte gate dielectric. We have carried out systematic studies on its electrical and optoelectronic properties. The MoS2 phototransistor exhibited excellent photo responsivity of ~1.5 kA/W, about two times higher compared to typical back-gated devices reported in previous studies. The device is highly transparent at the same time with an average optical transmittance of 82%. Successful fabrication of phototransistors on flexible cellulose nanopaper with excellent performance and transparency suggests that it is feasible to achieve an ecofriendly, biodegradable phototransistor with great photoresponsivity, broad spectral range and durable flexibility.

  3. High-Sensitivity, Highly Transparent, Gel-Gated MoS2 Phototransistor on Biodegradable Nanopaper

    KAUST Repository

    Zhang, Qing; Bao, Wenzhong; Gong, Amy; Gong, Tao; Ma, Dakang; Wan, Jiayu; Dai, Jiaqi; Munday, J; He, Jr-Hau; Hu, Liangbing; Zhang, Daihua

    2016-01-01

    Transition metal dichalcogenides hold great promise for a variety of novel electrical, optical and mechanical devices and applications. Among them, molybdenum disulphide (MoS2) is gaining increasing attention as the gate dielectric and semiconductive channel for high-perfomance field effect transistors. Here we report on the first MoS2 phototransistor built on flexible, transparent and biodegradable substrate with electrolyte gate dielectric. We have carried out systematic studies on its electrical and optoelectronic properties. The MoS2 phototransistor exhibited excellent photo responsivity of ~1.5 kA/W, about two times higher compared to typical back-gated devices reported in previous studies. The device is highly transparent at the same time with an average optical transmittance of 82%. Successful fabrication of phototransistors on flexible cellulose nanopaper with excellent performance and transparency suggests that it is feasible to achieve an ecofriendly, biodegradable phototransistor with great photoresponsivity, broad spectral range and durable flexibility.

  4. Gate modulation of proton transport in a nanopore.

    Science.gov (United States)

    Mei, Lanju; Yeh, Li-Hsien; Qian, Shizhi

    2016-03-14

    Proton transport in confined spaces plays a crucial role in many biological processes as well as in modern technological applications, such as fuel cells. To achieve active control of proton conductance, we investigate for the first time the gate modulation of proton transport in a pH-regulated nanopore by a multi-ion model. The model takes into account surface protonation/deprotonation reactions, surface curvature, electroosmotic flow, Stern layer, and electric double layer overlap. The proposed model is validated by good agreement with the existing experimental data on nanopore conductance with and without a gate voltage. The results show that the modulation of proton transport in a nanopore depends on the concentration of the background salt and solution pH. Without background salt, the gated nanopore exhibits an interesting ambipolar conductance behavior when pH is close to the isoelectric point of the dielectric pore material, and the net ionic and proton conductance can be actively regulated with a gate voltage as low as 1 V. The higher the background salt concentration, the lower is the performance of the gate control on the proton transport.

  5. The relevance of electrostatics for scanning-gate microscopy

    International Nuclear Information System (INIS)

    Schnez, S; Guettinger, J; Stampfer, C; Ensslin, K; Ihn, T

    2011-01-01

    Scanning-probe techniques have been developed to extract local information from a given physical system. In particular, conductance maps obtained by means of scanning-gate microscopy (SGM), where a conducting tip of an atomic-force microscope is used as a local and movable gate, seem to present an intuitive picture of the underlying physical processes. Here, we argue that the interpretation of such images is complex and not very intuitive under certain circumstances: scanning a graphene quantum dot (QD) in the Coulomb-blockaded regime, we observe an apparent shift of features in scanning-gate images as a function of gate voltages, which cannot be a real shift of the physical system. Furthermore, we demonstrate the appearance of more than one set of Coulomb rings arising from the graphene QD. We attribute these effects to screening between the metallic tip and the gates. Our results are relevant for SGM on any kind of nanostructure, but are of particular importance for nanostructures that are not covered with a dielectric, e.g. graphene or carbon nanotube structures.

  6. Effects of high-order deformation on high-K isomers in superheavy nuclei

    International Nuclear Information System (INIS)

    Liu, H. L.; Bertulani, C. A.; Xu, F. R.; Walker, P. M.

    2011-01-01

    Using, for the first time, configuration-constrained potential-energy-surface calculations with the inclusion of β 6 deformation, we find remarkable effects of the high-order deformation on the high-K isomers in 254 No, the focus of recent spectroscopy experiments on superheavy nuclei. For shapes with multipolarity six, the isomers are more tightly bound and, microscopically, have enhanced deformed shell gaps at N=152 and Z=100. The inclusion of β 6 deformation significantly improves the description of the very heavy high-K isomers.

  7. Identicity in high-K three quasiparticle rotational bands: a theoretical approach

    International Nuclear Information System (INIS)

    Kaur, Harjeet; Singh, Pardeep; Malik, Sham S

    2015-01-01

    The systematics are studied for the identical band phenomenon in high-K three quasiparticle rotational bands. The identical rotational bands based on the same bandhead spin are analyzed on the basis of similarities in γ-ray energies, dynamic moment of inertia and kinematic moment of inertia in particular, which is a function of deformation degrees of freedom, pairing strengths and Nilsson orbitals in nuclei. It is established that a combined effect of all these parameters decides the identicity of the moment of inertia in high-K three quasiparticle rotational bands as the systematics are backed by the Tilted Axis Cranking model calculations. (paper)

  8. Amplifying genetic logic gates.

    Science.gov (United States)

    Bonnet, Jerome; Yin, Peter; Ortiz, Monica E; Subsoontorn, Pakpoom; Endy, Drew

    2013-05-03

    Organisms must process information encoded via developmental and environmental signals to survive and reproduce. Researchers have also engineered synthetic genetic logic to realize simpler, independent control of biological processes. We developed a three-terminal device architecture, termed the transcriptor, that uses bacteriophage serine integrases to control the flow of RNA polymerase along DNA. Integrase-mediated inversion or deletion of DNA encoding transcription terminators or a promoter modulates transcription rates. We realized permanent amplifying AND, NAND, OR, XOR, NOR, and XNOR gates actuated across common control signal ranges and sequential logic supporting autonomous cell-cell communication of DNA encoding distinct logic-gate states. The single-layer digital logic architecture developed here enables engineering of amplifying logic gates to control transcription rates within and across diverse organisms.

  9. Cardiac gated ventilation

    International Nuclear Information System (INIS)

    Hanson, C.W. III; Hoffman, E.A.

    1995-01-01

    There are several theoretic advantages to synchronizing positive pressure breaths with the cardiac cycle, including the potential for improving distribution of pulmonary and myocardial blood flow and enhancing cardiac output. The authors evaluated the effects of synchronizing respiration to the cardiac cycle using a programmable ventilator and electron beam CT (EBCT) scanning. The hearts of anesthetized dogs were imaged during cardiac gated respiration with a 50 msec scan aperture. Multi slice, short axis, dynamic image data sets spanning the apex to base of the left ventricle were evaluated to determine the volume of the left ventricular chamber at end-diastole and end-systole during apnea, systolic and diastolic cardiac gating. The authors observed an increase in cardiac output of up to 30% with inspiration gated to the systolic phase of the cardiac cycle in a non-failing model of the heart

  10. Laser Direct Writing Process for Making Electrodes and High-k Sol-Gel ZrO2 for Boosting Performances of MoS2 Transistors.

    Science.gov (United States)

    Kwon, Hyuk-Jun; Jang, Jaewon; Grigoropoulos, Costas P

    2016-04-13

    A series of two-dimensional (2D) transition metal dichalcogenides (TMDCs), including molybdenum disulfide (MoS2), can be attractive materials for photonic and electronic applications due to their exceptional properties. Among these unique properties, high mobility of 2D TMDCs enables realization of high-performance nanoelectronics based on a thin film transistor (TFT) platform. In this contribution, we report highly enhanced field effect mobility (μ(eff) = 50.1 cm(2)/(V s), ∼2.5 times) of MoS2 TFTs through the sol-gel processed high-k ZrO2 (∼22.0) insulator, compared to those of typical MoS2/SiO2/Si structures (μ(eff) = 19.4 cm(2)/(V s)) because a high-k dielectric layer can suppress Coulomb electron scattering and reduce interface trap concentration. Additionally, in order to avoid costly conventional mask based photolithography and define the patterns, we employ a simple laser direct writing (LDW) process. This process allows precise and flexible control with reasonable resolution (up to ∼10 nm), depending on the system, and enables fabrication of arbitrarily patterned devices. Taking advantage of continuing developments in laser technology offers a substantial cost decrease, and LDW may emerge as a promising technology.

  11. Comparison of effective relative dielectric permittivities obtained by three independent ways for CeO2-Sm2O3 films prepared by EB-PVD (+IBAD) techniques

    International Nuclear Information System (INIS)

    Kundracik, F.; Neilinger, P.; Hartmanova, M.; Nadazdy, V.; Mansilla, C.

    2011-01-01

    Ceria, as material with relatively high dielectric permittivity, ε r , and ability to form films on the Si substrate, is a candidate for the gate dielectrics in the MOS devices. Doping with suitable e.g. trivalent rare earth oxides and suitable treatment after deposition (preparation) can improve their properties, e.g. ionic conductivity, dielectric permittivity and mechanical hardness. In this work, the dielectric properties of CeO 2 + Sm 2 O 3 films prepared by electron beam physical vapour deposition (EB-PVD) and some of them simultaneously also by the Ar + ionic beam assisted deposition (IBAD) techniques are analysed. (authors)

  12. Accelerated life testing and reliability of high K multilayer ceramic capacitors

    Science.gov (United States)

    Minford, W. J.

    1981-01-01

    The reliability of one lot of high K multilayer ceramic capacitors was evaluated using accelerated life testing. The degradation in insulation resistance was characterized as a function of voltage and temperature. The times to failure at a voltage-temperature stress conformed to a lognormal distribution with a standard deviation approximately 0.5.

  13. Gate valve performance prediction

    International Nuclear Information System (INIS)

    Harrison, D.H.; Damerell, P.S.; Wang, J.K.; Kalsi, M.S.; Wolfe, K.J.

    1994-01-01

    The Electric Power Research Institute is carrying out a program to improve the performance prediction methods for motor-operated valves. As part of this program, an analytical method to predict the stem thrust required to stroke a gate valve has been developed and has been assessed against data from gate valve tests. The method accounts for the loads applied to the disc by fluid flow and for the detailed mechanical interaction of the stem, disc, guides, and seats. To support development of the method, two separate-effects test programs were carried out. One test program determined friction coefficients for contacts between gate valve parts by using material specimens in controlled environments. The other test program investigated the interaction of the stem, disc, guides, and seat using a special fixture with full-sized gate valve parts. The method has been assessed against flow-loop and in-plant test data. These tests include valve sizes from 3 to 18 in. and cover a considerable range of flow, temperature, and differential pressure. Stem thrust predictions for the method bound measured results. In some cases, the bounding predictions are substantially higher than the stem loads required for valve operation, as a result of the bounding nature of the friction coefficients in the method

  14. Stanford, Duke, Rice,... and Gates?

    Science.gov (United States)

    Carey, Kevin

    2009-01-01

    This article presents an open letter to Bill Gates. In his letter, the author suggests that Bill Gates should build a brand-new university, a great 21st-century institution of higher learning. This university will be unlike anything the world has ever seen. He asks Bill Gates not to stop helping existing colleges create the higher-education system…

  15. Thin film silicon on silicon nitride for radiation hardened dielectrically isolated MISFET's

    International Nuclear Information System (INIS)

    Neamen, D.; Shedd, W.; Buchanan, B.

    1975-01-01

    The permanent ionizing radiation effects resulting from charge trapping in a silicon nitride isolation dielectric have been determined for a total ionizing dose up to 10 7 rads (Si). Junction FET's, whose active channel region is directly adjacent to the silicon-silicon nitride interface, were used to measure the effects of the radiation induced charge trapping in the Si 3 N 4 isolation dielectric. The JFET saturation current and channel conductance versus junction gate voltage and substrate voltage were characterized as a function of the total ionizing radiation dose. The experimental results on the Si 3 N 4 are compared to results on similar devices with SiO 2 dielectric isolation. The ramifications of using the silicon nitride for fabricating radiation hardened dielectrically isolated MIS devices are discussed

  16. Double optical gating

    Science.gov (United States)

    Gilbertson, Steve

    The observation and control of dynamics in atomic and molecular targets requires the use of laser pulses with duration less than the characteristic timescale of the process which is to be manipulated. For electron dynamics, this time scale is on the order of attoseconds where 1 attosecond = 10 -18 seconds. In order to generate pulses on this time scale, different gating methods have been proposed. The idea is to extract or "gate" a single pulse from an attosecond pulse train and switch off all the other pulses. While previous methods have had some success, they are very difficult to implement and so far very few labs have access to these unique light sources. The purpose of this work is to introduce a new method, called double optical gating (DOG), and to demonstrate its effectiveness at generating high contrast single isolated attosecond pulses from multi-cycle lasers. First, the method is described in detail and is investigated in the spectral domain. The resulting attosecond pulses produced are then temporally characterized through attosecond streaking. A second method of gating, called generalized double optical gating (GDOG), is also introduced. This method allows attosecond pulse generation directly from a carrier-envelope phase un-stabilized laser system for the first time. Next the methods of DOG and GDOG are implemented in attosecond applications like high flux pulses and extreme broadband spectrum generation. Finally, the attosecond pulses themselves are used in experiments. First, an attosecond/femtosecond cross correlation is used for characterization of spatial and temporal properties of femtosecond pulses. Then, an attosecond pump, femtosecond probe experiment is conducted to observe and control electron dynamics in helium for the first time.

  17. Dielectric nanoresonators for light manipulation

    Science.gov (United States)

    Yang, Zhong-Jian; Jiang, Ruibin; Zhuo, Xiaolu; Xie, Ya-Ming; Wang, Jianfang; Lin, Hai-Qing

    2017-07-01

    Nanostructures made of dielectric materials with high or moderate refractive indexes can support strong electric and magnetic resonances in the optical region. They can therefore function as nanoresonators. In addition to plasmonic metal nanostructures that have been widely investigated, dielectric nanoresonators provide a new type of building blocks for realizing powerful and versatile nanoscale light manipulation. In contrast to plasmonic metal nanostructures, nanoresonators made of appropriate dielectric materials are low-cost, earth-abundant and have very small or even negligible light energy losses. As a result, they will find potential applications in a number of photonic devices, especially those that require low energy losses. In this review, we describe the recent progress on the experimental and theoretical studies of dielectric nanoresonators. We start from the basic theory of the electromagnetic responses of dielectric nanoresonators and their fabrication methods. The optical properties of individual dielectric nanoresonators are then elaborated, followed by the coupling behaviors between dielectric nanoresonators, between dielectric nanoresonators and substrates, and between dielectric nanoresonators and plasmonic metal nanostructures. The applications of dielectric nanoresonators are further described. Finally, the challenges and opportunities in this field are discussed.

  18. Dielectric properties of polyethylene

    International Nuclear Information System (INIS)

    Darwish, S.; Riad, A.S.; El-Shabasy, M.

    2005-01-01

    The temperature dependence of dielectric properties in polyethylene was measured in the frequency range from 10 to 105 Hz. The frequency dependence of the complex impedance in the complex plane could be fitted by semicircles. The system could be represented by an equivalent circuit of a bulk resistance in series with parallel surface resistance-capacitance combination. The relaxation time, has been evaluated from experimental results. Results reveal that the temperature dependence, is a thermally activated process

  19. Dielectric Wakefield Researches

    International Nuclear Information System (INIS)

    Kiselev, V.A.; Linnik, A.F.; Onishchenko, N.I.; Uskov, V.V.; Marshall, T.C.

    2006-01-01

    Excitation of wakefield in cylindrical dielectric waveguide/resonator by a sequence of relativistic electron bunches was investigated using an electron linac 'Almaz-2' (4.5 MeV, 6·10 3 bunches of duration 60 ps and charge 0.32 nC each). Energy spectrum of electrons, radial topography and longitudinal distribution of wakefield, and total energy of excited wakefield were measured by means of magnetic analyzer, high frequency probe, and a sensitive calorimeter

  20. Dielectric lattice gauge theory

    International Nuclear Information System (INIS)

    Mack, G.

    1983-06-01

    Dielectric lattice gauge theory models are introduced. They involve variables PHI(b)epsilong that are attached to the links b = (x+esub(μ),x) of the lattice and take their values in the linear space g which consists of real linear combinations of matrices in the gauge group G. The polar decomposition PHI(b)=U(b)osub(μ)(x) specifies an ordinary lattice gauge field U(b) and a kind of dielectric field epsilonsub(ij)proportionalosub(i)osub(j)sup(*)deltasub(ij). A gauge invariant positive semidefinite kinetic term for the PHI-field is found, and it is shown how to incorporate Wilson fermions in a way which preserves Osterwalder Schrader positivity. Theories with G = SU(2) and without matter fields are studied in some detail. It is proved that confinement holds, in the sense that Wilson loop expectation values show an area law decay, if the Euclidean action has certain qualitative features which imply that PHI = 0 (i.e. dielectric field identical 0) is the unique maximum of the action. (orig.)

  1. Dielectric lattice gauge theory

    International Nuclear Information System (INIS)

    Mack, G.

    1984-01-01

    Dielectric lattice gauge theory models are introduced. They involve variables PHI(b)element ofG that are attached to the links b = (x+esub(μ), x) of the lattice and take their values in the linear space G which consists of real linear combinations of matrices in the gauge group G. The polar decomposition PHI(b)=U(b)sigmasub(μ)(x) specifies an ordinary lattice gauge field U(b) and a kind of dielectric field epsilonsub(ij)proportional sigmasub(i)sigmasub(j)sup(*)deltasub(ij). A gauge invariant positive semidefinite kinetic term for the PHI-field is found, and it is shown how to incorporate Wilson fermions in a way which preserves Osterwalder-Schrader positivity. Theories with G = SU(2) and without matter fields are studied in some detail. It is proved that confinement holds, in the sense that Wilson-loop expectation values show an area law decay, if the euclidean action has certain qualitative features which imply that PHI=0 (i.e. dielectric field identical 0) is the unique maximum of the action. (orig.)

  2. Anomalous degradation behaviors under illuminated gate bias stress in a-Si:H thin film transistor

    International Nuclear Information System (INIS)

    Tsai, Ming-Yen; Chang, Ting-Chang; Chu, Ann-Kuo; Hsieh, Tien-Yu; Lin, Kun-Yao; Wu, Yi-Chun; Huang, Shih-Feng; Chiang, Cheng-Lung; Chen, Po-Lin; Lai, Tzu-Chieh; Lo, Chang-Cheng; Lien, Alan

    2014-01-01

    This study investigates the impact of gate bias stress with and without light illumination in a-Si:H thin film transistors. It has been observed that the I–V curve shifts toward the positive direction after negative and positive gate bias stress due to interface state creation at the gate dielectric. However, this study found that threshold voltages shift negatively and that the transconductance curve maxima are anomalously degraded under illuminated positive gate bias stress. In addition, threshold voltages shift positively under illuminated negative gate bias stress. These degradation behaviors can be ascribed to charge trapping in the passivation layer dominating degradation instability and are verified by a double gate a-Si:H device. - Highlights: • There is abnormal V T shift induced by illuminated gate bias stress in a-Si:H thin film transistors. • Electron–hole pair is generated via trap-assisted photoexcitation. • Abnormal transconductance hump is induced by the leakage current from back channel. • Charge trapping in the passivation layer is likely due to the fact that a constant voltage has been applied to the top gate

  3. A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

    International Nuclear Information System (INIS)

    Luo Xiao-Rong; Hu Gang-Yi; Zhang Zheng-Yuan; Luo Yin-Chun; Fan Ye; Wang Xiao-Wei; Fan Yuan-Hang; Cai Jin-Yong; Wang Pei; Zhou Kun

    2013-01-01

    A low specific on-resistance (R on,sp ) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates, which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R on,sp of 4.151 mΩ·cm 2 (V GS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  4. Threshold-Voltage Shifts in Organic Transistors Due to Self-Assembled Monolayers at the Dielectric: Evidence for Electronic Coupling and Dipolar Effects.

    Science.gov (United States)

    Aghamohammadi, Mahdieh; Rödel, Reinhold; Zschieschang, Ute; Ocal, Carmen; Boschker, Hans; Weitz, R Thomas; Barrena, Esther; Klauk, Hagen

    2015-10-21

    The mechanisms behind the threshold-voltage shift in organic transistors due to functionalizing of the gate dielectric with self-assembled monolayers (SAMs) are still under debate. We address the mechanisms by which SAMs determine the threshold voltage, by analyzing whether the threshold voltage depends on the gate-dielectric capacitance. We have investigated transistors based on five oxide thicknesses and two SAMs with rather diverse chemical properties, using the benchmark organic semiconductor dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene. Unlike several previous studies, we have found that the dependence of the threshold voltage on the gate-dielectric capacitance is completely different for the two SAMs. In transistors with an alkyl SAM, the threshold voltage does not depend on the gate-dielectric capacitance and is determined mainly by the dipolar character of the SAM, whereas in transistors with a fluoroalkyl SAM the threshold voltages exhibit a linear dependence on the inverse of the gate-dielectric capacitance. Kelvin probe force microscopy measurements indicate this behavior is attributed to an electronic coupling between the fluoroalkyl SAM and the organic semiconductor.

  5. High Stability Pentacene Transistors Using Polymeric Dielectric Surface Modifier.

    Science.gov (United States)

    Wang, Xiaohong; Lin, Guangqing; Li, Peng; Lv, Guoqiang; Qiu, Longzhen; Ding, Yunsheng

    2015-08-01

    1,6-bis(trichlorosilyl)hexane (C6Cl), polystyrene (PS), and cross-linked polystyrene (CPS) were investigated as gate dielectric modified layers for high performance organic transistors. The influence of the surface energy, roughness and morphology on the charge transport of the organic thin-film transistors (OTFTs) was investigated. The surface energy and roughness both affect the grain size of the pentacene films which will control the charge carrier mobility of the devices. Pentacene thin-film transistors fabricated on the CPS modified dielectric layers exhibited charge carrier mobility as high as 1.11 cm2 V-1 s-1. The bias stress stability for the CPS devices shows that the drain current only decays 1% after 1530 s and the mobility never decreases until 13530 s.

  6. Dielectric properties of lunar surface

    Science.gov (United States)

    Yushkova, O. V.; Kibardina, I. N.

    2017-03-01

    Measurements of the dielectric characteristics of lunar soil samples are analyzed in the context of dielectric theory. It has been shown that the real component of the dielectric permittivity and the loss tangent of rocks greatly depend on the frequency of the interacting electromagnetic field and the soil temperature. It follows from the analysis that one should take into account diurnal variations in the lunar surface temperature when interpreting the radar-sounding results, especially for the gigahertz radio range.

  7. High-K rotational bands in {sup 174}Hf and {sup 175}Hf

    Energy Technology Data Exchange (ETDEWEB)

    Gjoerup, N L; Sletten, G [The Niels Bohr Institute, Roskilbe (Denmark); Walker, P M [Surrey Univ., Guildford (United Kingdom). Dept. of Physics; Bentley, M A [Daresbury Lab. (United Kingdom); Cullen, D M; Sharpey-Schafer, J F; Fallon, P; Smith, G [Liverpool Univ. (United Kingdom). Oliver Lodge Lab.

    1992-08-01

    High sensitivity experiments with {sup 48}Ca, {sup 18}O and {sup 9}Be induced reactions using the ESSA-30, TESSA-3 and NORDBALL arrays have provided extensive new information on the high spin level structures of {sup 174}Hf and {sup 175}Hf. During the series of experiments, several new bands have been found and most known bands have been extended considerably. Spin and excitation energy ranges for {sup 174}Hf are now {approx} 35 {Dirac_h} and {approx} 13 MeV, respectively, and for {sup 175}Hf ranges are {approx} 30 {Dirac_h} and {approx} 7 MeV. respectively. Several new high-K structures have been found in {sup 174}Hf and the structure of these and the already known high-K bands in both nuclei together with the new Tilted Axis Cranking approach might explain the small K-hindrances observed for K-isomers in this region. (author). 8 refs., 2 figs.

  8. Negative differential transconductance in electrolyte-gated ruthenate

    International Nuclear Information System (INIS)

    Hassan, Muhammad Umair; Dhoot, Anoop Singh; Wimbush, Stuart C.

    2015-01-01

    We report on a study of electric field-induced doping of the highly conductive ruthenate SrRuO 3 using an ionic liquid as the gate dielectric in a field-effect transistor configuration. Two distinct carrier transport regimes are identified for increasing positive gate voltage in thin (10 nm) films grown heteroepitaxially on SrTiO 3 substrates. For V g  = 2 V and lower, the sample shows an increased conductivity of up to 13%, as might be expected for electron doping of a metal. At higher V g  = 2.5 V, we observe a large decrease in electrical conductivity of >20% (at 4.2 K) due to the prevalence of strongly blocked conduction pathways

  9. Negative differential transconductance in electrolyte-gated ruthenate

    Energy Technology Data Exchange (ETDEWEB)

    Hassan, Muhammad Umair [Cavendish Laboratory, University of Cambridge, J J Thomson Avenue, Cambridge CB3 0HE (United Kingdom); Center for Micro and Nano Devices, Department of Physics, COMSATS Institute of Information Technology, Park Road, Shehzad Town 44000, Islamabad (Pakistan); Dhoot, Anoop Singh, E-mail: asd24@cam.ac.uk [Cavendish Laboratory, University of Cambridge, J J Thomson Avenue, Cambridge CB3 0HE (United Kingdom); Wimbush, Stuart C. [Department of Materials Science and Metallurgy, University of Cambridge, 27 Charles Babbage Road, Cambridge CB3 0FS (United Kingdom); The MacDiarmid Institute for Advanced Materials and Nanotechnology, Victoria University of Wellington, P.O. Box 600, Wellington 6140 (New Zealand)

    2015-01-19

    We report on a study of electric field-induced doping of the highly conductive ruthenate SrRuO{sub 3} using an ionic liquid as the gate dielectric in a field-effect transistor configuration. Two distinct carrier transport regimes are identified for increasing positive gate voltage in thin (10 nm) films grown heteroepitaxially on SrTiO{sub 3} substrates. For V{sub g} = 2 V and lower, the sample shows an increased conductivity of up to 13%, as might be expected for electron doping of a metal. At higher V{sub g} = 2.5 V, we observe a large decrease in electrical conductivity of >20% (at 4.2 K) due to the prevalence of strongly blocked conduction pathways.

  10. Accurate characterization of organic thin film transistors in the presence of gate leakage current

    Directory of Open Access Journals (Sweden)

    Vinay K. Singh

    2011-12-01

    Full Text Available The presence of gate leakage through polymer dielectric in organic thin film transistors (OTFT prevents accurate estimation of transistor characteristics especially in subthreshold regime. To mitigate the impact of gate leakage on transfer characteristics and allow accurate estimation of mobility, subthreshold slope and on/off current ratio, a measurement technique involving simultaneous sweep of both gate and drain voltages is proposed. Two dimensional numerical device simulation is used to illustrate the validity of the proposed technique. Experimental results obtained with Pentacene/PMMA OTFT with significant gate leakage show a low on/off current ratio of ∼ 102 and subthreshold is 10 V/decade obtained using conventional measurement technique. The proposed technique reveals that channel on/off current ratio is more than two orders of magnitude higher at ∼104 and subthreshold slope is 4.5 V/decade.

  11. Noise Gating Solar Images

    Science.gov (United States)

    DeForest, Craig; Seaton, Daniel B.; Darnell, John A.

    2017-08-01

    I present and demonstrate a new, general purpose post-processing technique, "3D noise gating", that can reduce image noise by an order of magnitude or more without effective loss of spatial or temporal resolution in typical solar applications.Nearly all scientific images are, ultimately, limited by noise. Noise can be direct Poisson "shot noise" from photon counting effects, or introduced by other means such as detector read noise. Noise is typically represented as a random variable (perhaps with location- or image-dependent characteristics) that is sampled once per pixel or once per resolution element of an image sequence. Noise limits many aspects of image analysis, including photometry, spatiotemporal resolution, feature identification, morphology extraction, and background modeling and separation.Identifying and separating noise from image signal is difficult. The common practice of blurring in space and/or time works because most image "signal" is concentrated in the low Fourier components of an image, while noise is evenly distributed. Blurring in space and/or time attenuates the high spatial and temporal frequencies, reducing noise at the expense of also attenuating image detail. Noise-gating exploits the same property -- "coherence" -- that we use to identify features in images, to separate image features from noise.Processing image sequences through 3-D noise gating results in spectacular (more than 10x) improvements in signal-to-noise ratio, while not blurring bright, resolved features in either space or time. This improves most types of image analysis, including feature identification, time sequence extraction, absolute and relative photometry (including differential emission measure analysis), feature tracking, computer vision, correlation tracking, background modeling, cross-scale analysis, visual display/presentation, and image compression.I will introduce noise gating, describe the method, and show examples from several instruments (including SDO

  12. A quantum Fredkin gate

    Science.gov (United States)

    Patel, Raj B.; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C.; Pryde, Geoff J.

    2016-01-01

    Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently. PMID:27051868

  13. A quantum Fredkin gate.

    Science.gov (United States)

    Patel, Raj B; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C; Pryde, Geoff J

    2016-03-01

    Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently.

  14. Multiple Independent Gate FETs: How Many Gates Do We Need?

    OpenAIRE

    Amarù, Luca; Hills, Gage; Gaillardon, Pierre-Emmanuel; Mitra, Subhasish; De Micheli, Giovanni

    2015-01-01

    Multiple Independent Gate Field Effect Transistors (MIGFETs) are expected to push FET technology further into the semiconductor roadmap. In a MIGFET, supplementary gates either provide (i) enhanced conduction properties or (ii) more intelligent switching functions. In general, each additional gate also introduces a side implementation cost. To enable more efficient digital systems, MIGFETs must leverage their expressive power to realize complex logic circuits with few physical resources. Rese...

  15. Boron nitride as two dimensional dielectric: Reliability and dielectric breakdown

    Energy Technology Data Exchange (ETDEWEB)

    Ji, Yanfeng; Pan, Chengbin; Hui, Fei; Shi, Yuanyuan; Lanza, Mario, E-mail: mlanza@suda.edu.cn [Institute of Functional Nano and Soft Materials, Collaborative Innovation Center of Suzhou Nano Science and Technology, Soochow University, 199 Ren-Ai Road, Suzhou 215123 (China); Zhang, Meiyun; Long, Shibing [Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029 (China); Lian, Xiaojuan; Miao, Feng [National Laboratory of Solid State Microstructures, School of Physics, Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China); Larcher, Luca [DISMI, Università di Modena e Reggio Emilia, 42122 Reggio Emilia (Italy); Wu, Ernest [IBM Research Division, Essex Junction, Vermont 05452 (United States)

    2016-01-04

    Boron Nitride (BN) is a two dimensional insulator with excellent chemical, thermal, mechanical, and optical properties, which make it especially attractive for logic device applications. Nevertheless, its insulating properties and reliability as a dielectric material have never been analyzed in-depth. Here, we present the first thorough characterization of BN as dielectric film using nanoscale and device level experiments complementing with theoretical study. Our results reveal that BN is extremely stable against voltage stress, and it does not show the reliability problems related to conventional dielectrics like HfO{sub 2}, such as charge trapping and detrapping, stress induced leakage current, and untimely dielectric breakdown. Moreover, we observe a unique layer-by-layer dielectric breakdown, both at the nanoscale and device level. These findings may be of interest for many materials scientists and could open a new pathway towards two dimensional logic device applications.

  16. Dielectric Properties Of Nanoferrites

    International Nuclear Information System (INIS)

    Jankov, Stevan B.; Cvejic, Zeljka N.; Rakic, Srdjan; Srdic, Vladimir

    2007-01-01

    Dielectric properties: permittivity, loss factor, tan delta and ionic conductivity of nanostructured ferrites have been measured. Samples used were nickel, zinc and yttrium doped ferrites mixed in various ratios. The synthesis has been performed using precipitation method and obtained powders were pressed in pellets under varying pressure. X-ray diffractography approach for the refinement of structure and microstructural analysis has been performed. All parameters have been measured in 1 Hz to 100 kHz frequency range and 30 deg. C to 80 deg. C temperature range. Significant improvements in permittivity, loss factor and ionic conductivity comparing to bulk samples have been observed

  17. Dielectric materials and electrostatics

    CERN Document Server

    Gallot-Lavalle, Olivier

    2013-01-01

    An introduction to the physics of electrical insulation, this book presents the physical foundations of this discipline and the resulting applications. It is structured in two parts. The first part presents a mathematical and intuitive approach to dielectrics; various concepts, including polarization, induction, forces and losses are discussed. The second part provides readers with the keys to understanding the physics of solid, liquid and gas insulation. It comprises a phenomenological description of discharges in gas and its resulting applications. Finally, the main electrical properties

  18. Tunable Mobility in Double-Gated MoTe2 Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites.

    Science.gov (United States)

    Ji, Hyunjin; Joo, Min-Kyu; Yi, Hojoon; Choi, Homin; Gul, Hamza Zad; Ghimire, Mohan Kumar; Lim, Seong Chu

    2017-08-30

    There is a general consensus that the carrier mobility in a field-effect transistor (FET) made of semiconducting transition-metal dichalcogenides (s-TMDs) is severely degraded by the trapping/detrapping and Coulomb scattering of carriers by ionic charges in the gate oxides. Using a double-gated (DG) MoTe 2 FET, we modulated and enhanced the carrier mobility by adjusting the top- and bottom-gate biases. The relevant mechanism for mobility tuning in this device was explored using static DC and low-frequency (LF) noise characterizations. In the investigations, LF-noise analysis revealed that for a strong back-gate bias the Coulomb scattering of carriers by ionized traps in the gate dielectrics is strongly screened by accumulation charges. This significantly reduces the electrostatic scattering of channel carriers by the interface trap sites, resulting in increased mobility. The reduction of the number of effective trap sites also depends on the gate bias, implying that owing to the gate bias, the carriers are shifted inside the channel. Thus, the number of active trap sites decreases as the carriers are repelled from the interface by the gate bias. The gate-controlled Coulomb-scattering parameter and the trap-site density provide new handles for improving the carrier mobility in TMDs, in a fundamentally different way from dielectric screening observed in previous studies.

  19. 100-nm gate lithography for double-gate transistors

    Science.gov (United States)

    Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

    2001-09-01

    The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

  20. Adjustable threshold-voltage in all-inkjet-printed organic thin film transistor using double-layer dielectric structures

    International Nuclear Information System (INIS)

    Wu, Wen-Jong; Lee, Chang-Hung; Hsu, Chun-Hao; Yang, Shih-Hsien; Lin, Chih-Ting

    2013-01-01

    An all-inkjet-printed organic thin film transistor (OTFT) with a double-layer dielectric structure is proposed and implemented in this study. By using the double-layer structure with different dielectric materials (i.e., polyvinylphenol with poly(vinylidene fluoride-co-hexafluoropropylene)), the threshold-voltage of OTFT can be adjusted. The threshold-voltage shift can be controlled by changing the composition of dielectric layers. That is, an enhancement-mode OTFT can be converted to a depletion-mode OTFT by selectively printing additional dielectric layers to form a high-k/low-k double-layer structure. The printed OTFT has a carrier mobility of 5.0 × 10 −3 cm 2 /V-s. The threshold-voltages of the OTFTs ranged between − 13 V and 10 V. This study demonstrates an additional design parameter for organic electronics manufactured using inkjet printing technology. - Highlights: • A double-layer dielectric organic thin film transistor, OTFT, is implemented. • The threshold voltage of OTFT can be configured by the double dielectric structure. • The composition of the dielectric determines the threshold voltage shift. • The characteristics of OTFTs can be adjusted by double dielectric structures

  1. Discharge ignition near a dielectric

    NARCIS (Netherlands)

    Sobota, A.; Veldhuizen, van E.M.; Stoffels, W.W.

    2008-01-01

    Electrical breakdown in noble gas near a dielectric is an important issue in lighting industry. In order to investigate the influence of the dielectric on the ignition process, we perform measurements in argon, with pressure varying from 0.1 to 1 bar, using a pin–pin electrode geometry. Here, we

  2. Generalized dielectric permittivity tensor

    International Nuclear Information System (INIS)

    Borzdov, G.N.; Barkovskii, L.M.; Fedorov, F.I.

    1986-01-01

    The authors deal with the question of what is to be done with the formalism of the electrodynamics of dispersive media based on the introduction of dielectric-permittivity tensors for purely harmonic fields when Voigt waves and waves of more general form exist. An attempt is made to broaden and generalize the formalism to take into account dispersion of waves of the given type. In dispersive media, the polarization, magnetization, and conduction current-density vectors of point and time are determined by the values of the electromagnetic field vectors in the vicinity of this point (spatial dispersion) in the preceding instants of time (time dispersion). The dielectric-permittivity tensor and other tensors of electrodynamic parameters of the medium are introduced in terms of a set of evolution operators and not the set of harmonic function. It is noted that a magnetic-permeability tensor and an elastic-modulus tensor may be introduced for an acoustic field in dispersive anisotropic media with coupling equations of general form

  3. Quantum-coherence-assisted tunable on- and off-resonance tunneling through a quantum-dot-molecule dielectric film

    International Nuclear Information System (INIS)

    Shen Jianqi; Zeng Ruixi

    2017-01-01

    Quantum-dot-molecular phase coherence (and the relevant quantum-interference-switchable optical response) can be utilized to control electromagnetic wave propagation via a gate voltage, since quantum-dot molecules can exhibit an effect of quantum coherence (phase coherence) when quantum-dot-molecular discrete multilevel transitions are driven by an electromagnetic wave. Interdot tunneling of carriers (electrons and holes) controlled by the gate voltage can lead to destructive quantum interference in a quantum-dot molecule that is coupled to an incident electromagnetic wave, and gives rise to a quantum coherence effect (e.g., electromagnetically induced transparency, EIT) in a quantum-dot-molecule dielectric film. The tunable on- and off-resonance tunneling effect of an incident electromagnetic wave (probe field) through such a quantum-coherent quantum-dot-molecule dielectric film is investigated. It is found that a high gate voltage can lead to the EIT phenomenon of the quantum-dot-molecular systems. Under the condition of on-resonance light tunneling through the present quantum-dot-molecule dielectric film, the probe field should propagate without loss if the probe frequency detuning is zero. Such an effect caused by both EIT and resonant tunneling, which is sensitive to the gate voltage, can be utilized for designing devices such as photonic switching, transistors, and logic gates. (author)

  4. Dielectric Actuation of Polymers

    Science.gov (United States)

    Niu, Xiaofan

    Dielectric polymers are widely used in a plurality of applications, such as electrical insulation, dielectric capacitors, and electromechanical actuators. Dielectric polymers with large strain deformations under an electric field are named dielectric elastomers (DE), because of their relative low modulus, high elongation at break, and outstanding resilience. Dielectric elastomer actuators (DEA) are superior to traditional transducers as a muscle-like technology: large strains, high energy densities, high coupling efficiency, quiet operation, and light weight. One focus of this dissertation is on the design of DE materials with high performance and easy processing. UV radiation curing of reactive species is studied as a generic synthesis methodology to provide a platform for material scientists to customize their own DE materials. Oligomers/monomers, crosslinkers, and other additives are mixed and cured at appropriate ratios to control the stress-strain response, suppress electromechanical instability of the resulting polymers, and provide stable actuation strains larger than 100% and energy densities higher than 1 J/g. The processing is largely simplified in the new material system by removal of the prestretching step. Multilayer stack actuators with 11% linear strain are demonstrated in a procedure fully compatible with industrial production. A multifunctional DE derivative material, bistable electroactive polymer (BSEP), is invented enabling repeatable rigid-to-rigid deformation without bulky external structures. Bistable actuation allows the polymer actuator to have two distinct states that can support external load without device failure. Plasticizers are used to lower the glass transition temperature to 45 °C. Interpenetrating polymer network structure is established inside the BSEP to suppress electromechanical instability, providing a breakdown field of 194 MV/m and a stable bistable strain as large as 228% with a 97% strain fixity. The application of BSEP

  5. Liquid–Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing

    KAUST Repository

    Zhang, Yu

    2017-10-17

    Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid–liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the “sensing channel” can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

  6. Liquid-Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing.

    Science.gov (United States)

    Zhang, Yu; Li, Jun; Li, Rui; Sbircea, Dan-Tiberiu; Giovannitti, Alexander; Xu, Junling; Xu, Huihua; Zhou, Guodong; Bian, Liming; McCulloch, Iain; Zhao, Ni

    2017-11-08

    Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid-liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the "sensing channel" can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

  7. Expert Oracle GoldenGate

    CERN Document Server

    Prusinski, Ben; Chung, Richard

    2011-01-01

    Expert Oracle GoldenGate is a hands-on guide to creating and managing complex data replication environments using the latest in database replication technology from Oracle. GoldenGate is the future in replication technology from Oracle, and aims to be best-of-breed. GoldenGate supports homogeneous replication between Oracle databases. It supports heterogeneous replication involving other brands such as Microsoft SQL Server and IBM DB2 Universal Server. GoldenGate is high-speed, bidirectional, highly-parallelized, and makes only a light impact on the performance of databases involved in replica

  8. High-K structures in {sup 180}W and {sup 181}W

    Energy Technology Data Exchange (ETDEWEB)

    Yeung, K C; Walker, P M; Singleton, B D.D. [Surrey Univ., Guildford (United Kingdom). Dept. of Physics; Urban, W; Lisle, J C; Copnell, J; Mo, J N [Manchester Univ. (United Kingdom). Schuster Lab.; Joyce, M J [Liverpool Univ. (United Kingdom). Oliver Lodge Lab.; Gjorup, N L; Sletten, G [Risoe National Lab., Roskilde (Denmark)

    1992-08-01

    In each of the prolate-deformed isotopes {sup 180}W and {sup 181}W, a very high-K non-collective state has been found which decays directly into the corresponding collective ground-state rotational band. There is complete breakdown of the K-selection rule, in contrast to the partial breakdown observed recently in {sup 174}Hf and {sup 182}Os. Nevertheless, the non-collective states themselves retain characteristics associated with a prolate axially symmetric shape, implying that K is still a useful quantum number. (author). 17 refs., 2 figs.

  9. The effect of injection of high K+ solution into scala media.

    Science.gov (United States)

    Fukazawa, T; Ohmura, M; Yagi, N

    1987-01-01

    Thirty guinea pig ears were studied to investigate the effect of endolymphatic hydrops on the cochlea. High K+ solution was injected into the scala media, and cochlear microphonics (CM) and endocochlear potential (EP) were observed before, during and after the injection. The CM amplitude decreased rapidly after injection, ending in a depressed plateau value. By contrast, EP remained almost unchanged. By changing the composition of the solution it was suggested that the effect of the injection was mechanical one, rather than biochemical. In three ears, spontaneous recovery of CM was observed during a relatively long interval after the injection. The meaning of these findings for the hearing loss in Meniere's disease is discussed.

  10. Structural-optical study of high-dielectric-constant oxide films

    Energy Technology Data Exchange (ETDEWEB)

    Losurdo, M. [Institute of Inorganic Methodologies and Plasmas, IMIP-CNR, Department of Chemistry and INSTM Universita di bari, Via Orabona 4, 70126 Bari (Italy)]. E-mail: maria.losurdo@ba.imip.cnr.it; Giangregorio, M.M. [Institute of Inorganic Methodologies and Plasmas, IMIP-CNR, Department of Chemistry and INSTM Universita di bari, Via Orabona 4, 70126 Bari (Italy); Luchena, M. [Institute of Inorganic Methodologies and Plasmas, IMIP-CNR, Department of Chemistry and INSTM Universita di bari, Via Orabona 4, 70126 Bari (Italy); Capezzuto, P. [Institute of Inorganic Methodologies and Plasmas, IMIP-CNR, Department of Chemistry and INSTM Universita di bari, Via Orabona 4, 70126 Bari (Italy); Bruno, G. [Institute of Inorganic Methodologies and Plasmas, IMIP-CNR, Department of Chemistry and INSTM Universita di bari, Via Orabona 4, 70126 Bari (Italy); Toro, R.G. [Dipartimento di Scienze Chimiche, Universita di Catania, and INSTM-UdR Catania, Viale A. Doria 6, I-95125 Catania (Italy); Malandrino, G. [Dipartimento di Scienze Chimiche, Universita di Catania, and INSTM-UdR Catania, Viale A. Doria 6, I-95125 Catania (Italy); Fragala, I.L. [Dipartimento di Scienze Chimiche, Universita di Catania, and INSTM-UdR Catania, Viale A. Doria 6, I-95125 Catania (Italy); Nigro, R. Lo [Istituto di Microelettronica e Microsistemi, IMM-CNR, Stradale Primosole 50, I-95121 Catania (Italy)

    2006-10-31

    High-k polycrystalline Pr{sub 2}O{sub 3} and amorphous LaAlO{sub 3} oxide thin films deposited on Si(0 0 1) are studied. The microstructure is investigated using X-ray diffraction and scanning electron microscopy. Optical properties are determined in the 0.75-6.5 eV photon energy range using spectroscopic ellipsometry. The polycrystalline Pr{sub 2}O{sub 3} films have an optical gap of 3.86 eV and a dielectric constant of 16-26, which increases with film thickness. Similarly, very thin amorphous LaAlO{sub 3} films have the optical gap of 5.8 eV, and a dielectric constant below 14 which also increases with film thickness. The lower dielectric constant compared to crystalline material is an intrinsic characteristic of amorphous films.

  11. A novel optical gating method for laser gated imaging

    Science.gov (United States)

    Ginat, Ran; Schneider, Ron; Zohar, Eyal; Nesher, Ofer

    2013-06-01

    For the past 15 years, Elbit Systems is developing time-resolved active laser-gated imaging (LGI) systems for various applications. Traditional LGI systems are based on high sensitive gated sensors, synchronized to pulsed laser sources. Elbit propriety multi-pulse per frame method, which is being implemented in LGI systems, improves significantly the imaging quality. A significant characteristic of the LGI is its ability to penetrate a disturbing media, such as rain, haze and some fog types. Current LGI systems are based on image intensifier (II) sensors, limiting the system in spectral response, image quality, reliability and cost. A novel propriety optical gating module was developed in Elbit, untying the dependency of LGI system on II. The optical gating module is not bounded to the radiance wavelength and positioned between the system optics and the sensor. This optical gating method supports the use of conventional solid state sensors. By selecting the appropriate solid state sensor, the new LGI systems can operate at any desired wavelength. In this paper we present the new gating method characteristics, performance and its advantages over the II gating method. The use of the gated imaging systems is described in a variety of applications, including results from latest field experiments.

  12. The Study of Electrical Properties for Multilayer La2O3/Al2O3 Dielectric Stacks and LaAlO3 Dielectric Film Deposited by ALD.

    Science.gov (United States)

    Feng, Xing-Yao; Liu, Hong-Xia; Wang, Xing; Zhao, Lu; Fei, Chen-Xi; Liu, He-Lei

    2017-12-01

    The capacitance and leakage current properties of multilayer La 2 O 3 /Al 2 O 3 dielectric stacks and LaAlO 3 dielectric film are investigated in this paper. A clear promotion of capacitance properties is observed for multilayer La 2 O 3 /Al 2 O 3 stacks after post-deposition annealing (PDA) at 800 °C compared with PDA at 600 °C, which indicated the recombination of defects and dangling bonds performs better at the high-k/Si substrate interface for a higher annealing temperature. For LaAlO 3 dielectric film, compared with multilayer La 2 O 3 /Al 2 O 3 dielectric stacks, a clear promotion of trapped charges density (N ot ) and a degradation of interface trap density (D it ) can be obtained simultaneously. In addition, a significant improvement about leakage current property is observed for LaAlO 3 dielectric film compared with multilayer La 2 O 3 /Al 2 O 3 stacks at the same annealing condition. We also noticed that a better breakdown behavior for multilayer La 2 O 3 /Al 2 O 3 stack is achieved after annealing at a higher temperature for its less defects.

  13. Chemical gating of epitaxial graphene through ultrathin oxide layers.

    Science.gov (United States)

    Larciprete, Rosanna; Lacovig, Paolo; Orlando, Fabrizio; Dalmiglio, Matteo; Omiciuolo, Luca; Baraldi, Alessandro; Lizzit, Silvano

    2015-08-07

    We achieved a controllable chemical gating of epitaxial graphene grown on metal substrates by exploiting the electrostatic polarization of ultrathin SiO2 layers synthesized below it. Intercalated oxygen diffusing through the SiO2 layer modifies the metal-oxide work function and hole dopes graphene. The graphene/oxide/metal heterostructure behaves as a gated plane capacitor with the in situ grown SiO2 layer acting as a homogeneous dielectric spacer, whose high capacity allows the Fermi level of graphene to be shifted by a few hundreds of meV when the oxygen coverage at the metal substrate is of the order of 0.5 monolayers. The hole doping can be finely tuned by controlling the amount of interfacial oxygen, as well as by adjusting the thickness of the oxide layer. After complete thermal desorption of oxygen the intrinsic doping of SiO2 supported graphene is evaluated in the absence of contaminants and adventitious adsorbates. The demonstration that the charge state of graphene can be changed by chemically modifying the buried oxide/metal interface hints at the possibility of tuning the level and sign of doping by the use of other intercalants capable of diffusing through the ultrathin porous dielectric and reach the interface with the metal.

  14. Effect of dual-dielectric hydrogen-diffusion barrier layers on the performance of low-temperature processed transparent InGaZnO thin-film transistors

    Science.gov (United States)

    Tari, Alireza; Wong, William S.

    2018-02-01

    Dual-dielectric SiOx/SiNx thin-film layers were used as back-channel and gate-dielectric barrier layers for bottom-gate InGaZnO (IGZO) thin-film transistors (TFTs). The concentration profiles of hydrogen, indium, gallium, and zinc oxide were analyzed using secondary-ion mass spectroscopy characterization. By implementing an effective H-diffusion barrier, the hydrogen concentration and the creation of H-induced oxygen deficiency (H-Vo complex) defects during the processing of passivated flexible IGZO TFTs were minimized. A bilayer back-channel passivation layer, consisting of electron-beam deposited SiOx on plasma-enhanced chemical vapor-deposition (PECVD) SiNx films, effectively protected the TFT active region from plasma damage and minimized changes in the chemical composition of the semiconductor layer. A dual-dielectric PECVD SiOx/PECVD SiNx gate-dielectric, using SiOx as a barrier layer, also effectively prevented out-diffusion of hydrogen atoms from the PECVD SiNx-gate dielectric to the IGZO channel layer during the device fabrication.

  15. Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Shun; Gao, Xu, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn; Zhong, Ya-Nan; Zhang, Zhong-Da; Xu, Jian-Long; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn [Institute of Functional Nano and Soft Materials (FUNSOM), Jiangsu Key Laboratory for Carbon-Based Functional Materials and Devices, Soochow University, Suzhou, Jiangsu 215123 (China)

    2016-07-11

    High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio and good memory retention.

  16. Anomalous positive flatband voltage shifts in metal gate stacks containing rare-earth oxide capping layers

    KAUST Repository

    Caraveo-Frescas, J. A.

    2012-03-09

    It is shown that the well-known negative flatband voltage (VFB) shift, induced by rare-earth oxide capping in metal gate stacks, can be completely reversed in the absence of the silicon overlayer. Using TaN metal gates and Gd2O3-doped dielectric, we measure a ∼350 mV negative shift with the Si overlayer present and a ∼110 mV positive shift with the Si overlayer removed. This effect is correlated to a positive change in the average electrostatic potential at the TaN/dielectric interface which originates from an interfacial dipole. The dipole is created by the replacement of interfacial oxygen atoms in the HfO2 lattice with nitrogen atoms from TaN.

  17. High performance organic field-effect transistors with ultra-thin HfO2 gate insulator deposited directly onto the organic semiconductor

    International Nuclear Information System (INIS)

    Ono, S.; Häusermann, R.; Chiba, D.; Shimamura, K.; Ono, T.; Batlogg, B.

    2014-01-01

    We have produced stable organic field-effect transistors (OFETs) with an ultra-thin HfO 2 gate insulator deposited directly on top of rubrene single crystals by atomic layer deposition (ALD). We find that ALD is a gentle deposition process to grow thin films without damaging rubrene single crystals, as results these devices have a negligibly small threshold voltage and are very stable against gate-bias-stress, and the mobility exceeds 1 cm 2 /V s. Moreover, the devices show very little degradation even when kept in air for more than 2 months. These results demonstrate thin HfO 2 layers deposited by ALD to be well suited as high capacitance gate dielectrics in OFETs operating at small gate voltage. In addition, the dielectric layer acts as an effective passivation layer to protect the organic semiconductor

  18. Quasi-particle and collective magnetism: Rotation, pairing and blocking in high-K isomers

    International Nuclear Information System (INIS)

    Stone, N.J.; Stone, J.R.; Walker, P.M.; Bingham, C.R.

    2013-01-01

    For the first time, a wide range of collective magnetic g-factors g R , obtained from a novel analysis of experimental data for multi-quasi-particle configurations in high-K isomers, is shown to exhibit a striking systematic variation with the relative number of proton and neutron quasi-particles, N p −N n . Using the principle of additivity, the quasi-particle contribution to magnetism in high-K isomers of Lu–Re, Z=71–75, has been estimated. Based on these estimates, band-structure branching ratio data are used to explore the behavior of the collective contribution as the number and proton/neutron nature (N p , N n ), of the quasi-particle excitations, change. Basic ideas of pairing, its quenching by quasi-particle excitation and the consequent changes to moment of inertia and collective magnetism are discussed. Existing model calculations do not reproduce the observed g R variation adequately. The paired superfluid system of nucleons in these nuclei, and their excitations, present properties of general physics interest. The new-found systematic behavior of g R in multi-quasi-particle excitations of this unique system, showing variation from close to zero for multi-neutron states to above 0.5 for multi-proton states, opens a fresh window on these effects and raises the important question of just which nucleons contribute to the ‘collective’ properties of these nuclei

  19. Radiological and Nuclear Detection Material Science: Novel Rare-Earth Semiconductors for Solid-State Neutron Detectors and Thin High-k Dielectrics

    Science.gov (United States)

    2017-11-01

    6201 Fort Belvoir, VA 22060-6201 T E C H N IC A L R E P O R T DTRA-TR-15-82 Radiological and Nuclear Detection Material Science : Novel...P.A. Dowben, “Surface Charging at the (100) Surface of Cu doped and undoped Li2B4O7”, Applied Surface Science 257 (2011) 3399-3403 27. S.R...V.T. Adamiv, Ya.V. Burak, P.A. Dowben, “The local structure of Mn doped Li2B4O7(001)”, in preparation for Materials Science and Engineering B 40. C

  20. Solution-Processed Dielectrics Based on Thickness-Sorted Two-Dimensional Hexagonal Boron Nitride Nanosheets

    Energy Technology Data Exchange (ETDEWEB)

    Zhu, Jian; Kang, Joohoon; Kang, Junmo; Jariwala, Deep; Wood, Joshua D.; Seo, Jung-Woo T.; Chen, Kan-Sheng; Marks, Tobin J.; Hersam, Mark C.

    2015-10-14

    Gate dielectrics directly affect the mobility, hysteresis, power consumption, and other critical device metrics in high-performance nanoelectronics. With atomically flat and dangling bond-free surfaces, hexagonal boron nitride (h-BN) has emerged as an ideal dielectric for graphene and related two-dimensional semiconductors. While high-quality, atomically thin h-BN has been realized via micromechanical cleavage and chemical vapor deposition, existing liquid exfoliation methods lack sufficient control over h-BN thickness and large-area film quality, thus limiting its use in solution-processed electronics. Here, we employ isopycnic density gradient ultracentrifugation for the preparation of monodisperse, thickness-sorted h-BN inks, which are subsequently layer-by-layer assembled into ultrathin dielectrics with low leakage currents of 3 × 10–9 A/cm2 at 2 MV/cm and high capacitances of 245 nF/cm2. The resulting solution-processed h-BN dielectric films enable the fabrication of graphene field-effect transistors with negligible hysteresis and high mobilities up to 7100 cm2 V–1 s–1 at room temperature. These h-BN inks can also be used as coatings on conventional dielectrics to minimize the effects of underlying traps, resulting in improvements in overall device performance. Overall, this approach for producing and assembling h-BN dielectric inks holds significant promise for translating the superlative performance of two-dimensional heterostructure devices to large-area, solution-processed nanoelectronics.

  1. Penn State DOE GATE Program

    Energy Technology Data Exchange (ETDEWEB)

    Anstrom, Joel

    2012-08-31

    The Graduate Automotive Technology Education (GATE) Program at The Pennsylvania State University (Penn State) was established in October 1998 pursuant to an award from the U.S. Department of Energy (U.S. DOE). The focus area of the Penn State GATE Program is advanced energy storage systems for electric and hybrid vehicles.

  2. Piezoconductivity of gated suspended graphene

    NARCIS (Netherlands)

    Medvedyeva, M.V.; Blanter, Y.M.

    2011-01-01

    We investigate the conductivity of graphene sheet deformed over a gate. The effect of the deformation on the conductivity is twofold: The lattice distortion can be represented as pseudovector potential in the Dirac equation formalism, whereas the gate causes inhomogeneous density redistribution. We

  3. Laser amplification in excited dielectrics

    DEFF Research Database (Denmark)

    Winkler, Thomas; Haahr-Lillevang, Lasse; Sarpe, Cristian

    2018-01-01

    Wide-bandgap dielectrics such as glasses or water are transparent at visible and infrared wavelengths. This changes when they are exposed to ultrashort and highly intense laser pulses. Different interaction mechanisms lead to the appearance of various transient nonlinear optical phenomena. Using...... these, the optical properties of dielectrics can be controlled from the transparent to the metal-like state. Here we expand this range by a yet unexplored mechanism in excited dielectrics: amplification. In a two-colour pump-probe experiment, we show that a 400nm femtosecond laser pulse is coherently...

  4. Low-frequency noise in multilayer MoS2 field-effect transistors: the effect of high-k passivation.

    Science.gov (United States)

    Na, Junhong; Joo, Min-Kyu; Shin, Minju; Huh, Junghwan; Kim, Jae-Sung; Piao, Mingxing; Jin, Jun-Eon; Jang, Ho-Kyun; Choi, Hyung Jong; Shim, Joon Hyung; Kim, Gyu-Tae

    2014-01-07

    Diagnosing of the interface quality and the interactions between insulators and semiconductors is significant to achieve the high performance of nanodevices. Herein, low-frequency noise (LFN) in mechanically exfoliated multilayer molybdenum disulfide (MoS2) (~11.3 nm-thick) field-effect transistors with back-gate control was characterized with and without an Al2O3 high-k passivation layer. The carrier number fluctuation (CNF) model associated with trapping/detrapping the charge carriers at the interface nicely described the noise behavior in the strong accumulation regime both with and without the Al2O3 passivation layer. The interface trap density at the MoS2-SiO2 interface was extracted from the LFN analysis, and estimated to be Nit ~ 10(10) eV(-1) cm(-2) without and with the passivation layer. This suggested that the accumulation channel induced by the back-gate was not significantly influenced by the passivation layer. The Hooge mobility fluctuation (HMF) model implying the bulk conduction was found to describe the drain current fluctuations in the subthreshold regime, which is rarely observed in other nanodevices, attributed to those extremely thin channel sizes. In the case of the thick-MoS2 (~40 nm-thick) without the passivation, the HMF model was clearly observed all over the operation regime, ensuring the existence of the bulk conduction in multilayer MoS2. With the Al2O3 passivation layer, the change in the noise behavior was explained from the point of formation of the additional top channel in the MoS2 because of the fixed charges in the Al2O3. The interface trap density from the additional CNF model was Nit = 1.8 × 10(12) eV(-1) cm(-2) at the MoS2-Al2O3 interface.

  5. On photonic controlled phase gates

    International Nuclear Information System (INIS)

    Kieling, K; Eisert, J; O'Brien, J L

    2010-01-01

    As primitives for entanglement generation, controlled phase gates have a central role in quantum computing. Especially in ideas realizing instances of quantum computation in linear optical gate arrays, a closer look can be rewarding. In such architectures, all effective nonlinearities are induced by measurements. Hence the probability of success is a crucial parameter of such quantum gates. In this paper, we discuss this question for controlled phase gates that implement an arbitrary phase with one and two control qubits. Within the class of post-selected gates in dual-rail encoding with vacuum ancillas, we identify the optimal success probabilities. We construct networks that allow for implementation using current experimental capabilities in detail. The methods employed here appear specifically useful with the advent of integrated linear optical circuits, providing stable interferometers on monolithic structures.

  6. GATE: Improving the computational efficiency

    International Nuclear Information System (INIS)

    Staelens, S.; De Beenhouwer, J.; Kruecker, D.; Maigne, L.; Rannou, F.; Ferrer, L.; D'Asseler, Y.; Buvat, I.; Lemahieu, I.

    2006-01-01

    GATE is a software dedicated to Monte Carlo simulations in Single Photon Emission Computed Tomography (SPECT) and Positron Emission Tomography (PET). An important disadvantage of those simulations is the fundamental burden of computation time. This manuscript describes three different techniques in order to improve the efficiency of those simulations. Firstly, the implementation of variance reduction techniques (VRTs), more specifically the incorporation of geometrical importance sampling, is discussed. After this, the newly designed cluster version of the GATE software is described. The experiments have shown that GATE simulations scale very well on a cluster of homogeneous computers. Finally, an elaboration on the deployment of GATE on the Enabling Grids for E-Science in Europe (EGEE) grid will conclude the description of efficiency enhancement efforts. The three aforementioned methods improve the efficiency of GATE to a large extent and make realistic patient-specific overnight Monte Carlo simulations achievable

  7. Manipulation of plasmonic resonances in graphene coated dielectric cylinders

    KAUST Repository

    Ge, Lixin

    2016-11-16

    Graphene sheets can support surface plasmon as the Dirac electrons oscillate collectively with electromagnetic waves. Compared with the surface plasmon in conventional metal (e.g., Ag and Au), graphene plasmonic owns many remarkable merits especially in Terahertz and far infrared frequencies, such as deep sub-wavelength, low loss, and high tunability. For graphene coated dielectric nano-scatters, localized surface plasmon (LSP)exist and can be excited under specific conditions. The LSPs are associated with the Mie resonance modes, leading to extraordinary large scattering and absorption cross section. In this work, we study systematically the optical scattering properties for graphene coated dielectric cylinders. It is found that the LSP can be manipulated by geometrical parameters and external electric gating. Generally, the resonance frequencies for different resonance modes are not the same. However, under proper design, we show that different resonance modes (e.g., dipole mode, quadruple mode etc.) can be excited at the same frequency. Thus, the scattering and absorption by graphene coated dielectric cylinders can indeed overcome the single channel limit. Our finding may open up new avenues in applications for the graphene-based THz optoelectronic devices.

  8. Top-gated chemical vapor deposition grown graphene transistors with current saturation.

    Science.gov (United States)

    Bai, Jingwei; Liao, Lei; Zhou, Hailong; Cheng, Rui; Liu, Lixin; Huang, Yu; Duan, Xiangfeng

    2011-06-08

    Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.

  9. Gated equilibrium bloodpool scintigraphy

    International Nuclear Information System (INIS)

    Reinders Folmer, S.C.C.

    1981-01-01

    This thesis deals with the clinical applications of gated equilibrium bloodpool scintigraphy, performed with either a gamma camera or a portable detector system, the nuclear stethoscope. The main goal has been to define the value and limitations of noninvasive measurements of left ventricular ejection fraction as a parameter of cardiac performance in various disease states, both for diagnostic purposes as well as during follow-up after medical or surgical intervention. Secondly, it was attempted to extend the use of the equilibrium bloodpool techniques beyond the calculation of ejection fraction alone by considering the feasibility to determine ventricular volumes and by including the possibility of quantifying valvular regurgitation. In both cases, it has been tried to broaden the perspective of the observations by comparing them with results of other, invasive and non-invasive, procedures, in particular cardiac catheterization, M-mode echocardiography and myocardial perfusion scintigraphy. (Auth.)

  10. Dielectric inspection of erythrocyte morphology

    International Nuclear Information System (INIS)

    Hayashi, Yoshihito; Oshige, Ikuya; Katsumoto, Yoichi; Omori, Shinji; Yasuda, Akio; Asami, Koji

    2008-01-01

    We performed a systematic study of the sensitivity of dielectric spectroscopy to erythrocyte morphology. Namely, rabbit erythrocytes of four different shapes were prepared by precisely controlling the pH of the suspending medium, and their complex permittivities over the frequency range from 0.1 to 110 MHz were measured and analyzed. Their quantitative analysis shows that the characteristic frequency and the broadening parameter of the dielectric relaxation of interfacial polarization are highly specific to the erythrocyte shape, while they are insensitive to the cell volume fraction. Therefore, these two dielectric parameters can be used to differentiate erythrocytes of different shapes, if dielectric spectroscopy is applied to flow-cytometric inspection of single blood cells. In addition, we revealed the applicability and limitations of the analytical theory of interfacial polarization to explain the experimental permittivities of non-spherical erythrocytes

  11. Dielectric inspection of erythrocyte morphology

    Energy Technology Data Exchange (ETDEWEB)

    Hayashi, Yoshihito; Oshige, Ikuya; Katsumoto, Yoichi; Omori, Shinji; Yasuda, Akio [Life Science Laboratory, Materials Laboratories, Sony Corporation, Sony Bioinformatics Center, Tokyo Medical and Dental University, Bunkyo-ku, Tokyo 113-8510 (Japan); Asami, Koji [Laboratory of Molecular Aggregation Analysis, Division of Multidisciplinary Chemistry, Institute for Chemical Research, Kyoto University, Uji, Kyoto 611-0011 (Japan)], E-mail: Yoshihito.Hayashi@jp.sony.com

    2008-05-21

    We performed a systematic study of the sensitivity of dielectric spectroscopy to erythrocyte morphology. Namely, rabbit erythrocytes of four different shapes were prepared by precisely controlling the pH of the suspending medium, and their complex permittivities over the frequency range from 0.1 to 110 MHz were measured and analyzed. Their quantitative analysis shows that the characteristic frequency and the broadening parameter of the dielectric relaxation of interfacial polarization are highly specific to the erythrocyte shape, while they are insensitive to the cell volume fraction. Therefore, these two dielectric parameters can be used to differentiate erythrocytes of different shapes, if dielectric spectroscopy is applied to flow-cytometric inspection of single blood cells. In addition, we revealed the applicability and limitations of the analytical theory of interfacial polarization to explain the experimental permittivities of non-spherical erythrocytes.

  12. Silicone-based Dielectric Elastomers

    DEFF Research Database (Denmark)

    Skov, Anne Ladegaard

    Efficient conversion of energy from one form to another (transduction) is an important topic in our daily day, and it is a necessity in moving away from the fossil based society. Dielectric elastomers hold great promise as soft transducers, since they are compliant and light-weight amongst many...... energy efficient solutions are highly sought. These properties allow for interesting products ranging very broadly, e.g. from eye implants over artificial skins over soft robotics to huge wave energy harvesting plants. All these products utilize the inherent softness and compliance of the dielectric...... elastomer transducers. The subject of this thesis is improvement of properties of silicone-based dielectric elastomers with special focus on design guides towards electrically, mechanically, and electromechanically reliable elastomers. Strategies for improving dielectric elastomer performance are widely...

  13. Pairing and Blocking in High-K Isomers: Variation of the Collective Parameter gR

    Directory of Open Access Journals (Sweden)

    Stone N.J.

    2013-12-01

    Full Text Available Using the principle of additivity, the quasi-particle contribution to magnetism in high-K isomers of Lu - Re has been estimated. Based on these estimates band structure branching ratio data is used to explore the behavior of the collective contribution as the number and neutron/proton nature (Np, Nn, of the quasi-particle excitations, change. A striking systematic variation of the collective g-factor gR with the difference, Np – Nn, is revealed. Basic ideas of pairing, its quenching by quasi-particle excitation and the consequent changes to moment of inertia and collective magnetism are discussed. The new found systematic behaviour of gR opens a fresh window on these effects amenable to detailed theoretical investigation.

  14. Maintaining K+ balance on the low-Na+, high-K+ diet

    Science.gov (United States)

    Cornelius, Ryan J.; Wang, Bangchen; Wang-France, Jun

    2016-01-01

    A low-Na+, high-K+ diet (LNaHK) is considered a healthier alternative to the “Western” high-Na+ diet. Because the mechanism for K+ secretion involves Na+ reabsorptive exchange for secreted K+ in the distal nephron, it is not understood how K+ is eliminated with such low Na+ intake. Animals on a LNaHK diet produce an alkaline load, high urinary flows, and markedly elevated plasma ANG II and aldosterone levels to maintain their K+ balance. Recent studies have revealed a potential mechanism involving the actions of alkalosis, urinary flow, elevated ANG II, and aldosterone on two types of K+ channels, renal outer medullary K+ and large-conductance K+ channels, located in principal and intercalated cells. Here, we review these recent advances. PMID:26739887

  15. Interconnect Between a Waveguide and a Dielectric Waveguide Comprising an Impedance Matched Dielectric Lens

    Science.gov (United States)

    Decrossas, Emmanuel (Inventor); Chattopadhyay, Goutam (Inventor); Chahat, Nacer (Inventor); Tang, Adrian J. (Inventor)

    2016-01-01

    A lens for interconnecting a metallic waveguide with a dielectric waveguide is provided. The lens may be coupled a metallic waveguide and a dielectric waveguide, and minimize a signal loss between the metallic waveguide and the dielectric waveguide.

  16. Elemental maps in human allantochorial placental vessels cells: 1. High K{sup +} and acetylcholine effects

    Energy Technology Data Exchange (ETDEWEB)

    Michelet-Habchi, C. E-mail: michelet@cenbg.in2p3.fr; Barberet, Ph.; Dutta, R.K.; Guiet-Bara, A.; Bara, M.; Moretto, Ph

    2003-09-01

    Regulation of vascular tone in the fetal extracorporeal circulation most likely depends on circulating hormones, local paracrine mechanisms and changes in membrane potential of vascular smooth muscle cells (VSMCs) and of vascular endothelial cells (VECs). The membrane potential is a function of the physiological activities of ionic channels (particularly, K{sup +} and Ca{sup 2+} channels in these cells). These channels regulate the ionic distribution into these cells. Micro-particle induced X-ray emission (PIXE) analysis was applied to determine the ionic composition of VSMC and of VEC in the placental human allantochorial vessels in a physiological survival medium (Hanks' solution) modified by the addition of acetylcholine (ACh: which opens the calcium-sensitive K{sup +} channels, K{sub Ca}) and of high concentration of K{sup +} (which blocks the voltage-sensitive K{sup +} channels, K{sub df}). In VSMC (media layer), the addition of ACh induced no modification of the Na, K, Cl, P, S, Mg and Ca concentrations and high K{sup +} medium increased significantly the Cl and K concentrations, the other ion concentrations remaining constant. In endothelium (VEC), ACh addition implicated a significant increase of Na and K concentration, and high K{sup +} medium, a significant increase in Cl and K concentration. These results indicated the importance of K{sub df}, K{sub Ca} and K{sub ATP} channels in the regulation of K{sup +} intracellular distribution in VSMC and VEC and the possible intervention of a Na-K-2Cl cotransport and corroborated the previous electrophysiological data.

  17. Influence of gate recess on the electronic characteristics of β-Ga2O3 MOSFETs

    Science.gov (United States)

    Lv, Yuanjie; Mo, Jianghui; Song, Xubo; He, Zezhao; Wang, Yuangang; Tan, Xin; Zhou, Xingye; Gu, Guodong; Guo, Hongyu; Feng, Zhihong

    2018-05-01

    Gallium oxide (Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with gate recess depths of 110 nm and 220 nm, respectively. The gate recess was formed by dry plasma etching with Cr metal as the mask. The fabricated devices with a 25-nm HfO2 gate dielectric both showed a low off-state drain current of about 1.8 × 10-10 A/mm. The effects of recess depth on the electronic characteristics of Ga2O3 MOSFETs were investigated. Upon increasing the recess depth from 110 nm to 220 nm, the saturated drain current decreased from 20.7 mA/mm to 2.6 mA/mm, while the threshold voltage moved increased to +3 V. Moreover, the breakdown voltage increased from 122 V to 190 V. This is mainly because the inverted-trapezoidal gate played the role of a gate-field plate, which suppressed the peak electric field close to the gate.

  18. A gate current 1/f noise model for GaN/AlGaN HEMTs

    International Nuclear Information System (INIS)

    Liu Yu'an; Zhuang Yiqi

    2014-01-01

    This work presents a theoretical and experimental study on the gate current 1/f noise in AlGaN/GaN HEMTs. Based on the carrier number fluctuation in the two-dimensional electron gas channel of AlGaN/GaN HEMTs, a gate current 1/f noise model containing a trap-assisted tunneling current and a space charge limited current is built. The simulation results are in good agreement with the experiment. Experiments show that, if V g < V x (critical gate voltage of dielectric relaxation), gate current 1/f noise comes from the superimposition of trap-assisted tunneling RTS (random telegraph noise), while V g > V x , gate current 1/f noise comes from not only the trap-assisted tunneling RTS, but also the space charge limited current RTS. This indicates that the gate current 1/f noise of the GaN-based HEMTs device is sensitive to the interaction of defects and the piezoelectric relaxation. It provides a useful characterization tool for deeper information about the defects and their evolution in AlGaN/GaN HEMTs. (semiconductor devices)

  19. Analysis of OFF-state and ON-state performance in a silicon-on-insulator power MOSFET with a low-k dielectric trench

    International Nuclear Information System (INIS)

    Wang Zhigang; Zhang Bo; Li Zhaoji

    2013-01-01

    A novel silicon-on-insulator (SOI) MOSFET with a variable low-k dielectric trench (LDT MOSFET) is proposed and its performance and characteristics are investigated. The trench in the drift region between drain and source is filled with low-k dielectric to extend the effective drift region. At OFF state, the low-k dielectric trench (LDT) can sustain high voltage and enhance the dielectric field due to the accumulation of ionized charges. At the same time, the vertical dielectric field in the buried oxide can also be enhanced by these ionized charges. Additionally, ON-state analysis of LDT MOSFET demonstrates excellent forward characteristics, such as low gate-to-drain charge density ( 2 ) and a robust safe operating area (0–84 V). (semiconductor devices)

  20. Analytical modeling of split-gate junction-less transistor for a biosensor application

    Directory of Open Access Journals (Sweden)

    Shradhya Singh

    2018-04-01

    Full Text Available This paper represents the analytical modeling of split-gate Dielectric Modulated Junction Less Transistor (JLT for label free electrical detection of bio molecules. Some part of the channel region is opened for providing the binding sites for the bio molecules unlike conventional MOSFET which is enclosed with the gate electrode. Due to this open area, the surface potential of this region affected by the charged and neutral bio molecules immobilized to the open region of channel. Surface potential of the channel region obtained by solving two-Dimensional Poisson's equation by potential profile having parabolic nature through channel region using technique called conformal mapping. By deriving the surface potential model, derivation of threshold model can also be done. For the detection of bio molecule, variation in to the threshold voltage due to binding of bio molecule in the gate underlap region is the sensing metric.

  1. New designs of a complete set of Photonic Crystals logic gates

    Science.gov (United States)

    Hussein, Hussein M. E.; Ali, Tamer A.; Rafat, Nadia H.

    2018-03-01

    In this paper, we introduce new designs of all-optical OR, AND, XOR, NOT, NOR, NAND and XNOR logic gates based on the interference effect. The designs are built using 2D square lattice Photonic Crystal (PhC) structure of dielectric rods embedded in air background. The lattice constant, a, and the rod radius, r, are designed to achieve maximum operating range of frequencies using the gap map. We use the Plane Wave Expansion (PWE) method to obtain the band structure and the gap map of the proposed designs. The operating wavelengths achieve a wide band range that varies between 1266.9 nm and 1996 nm with center wavelength at 1550 nm. The Finite-Difference Time-Domain (FDTD) method is used to study the field behavior inside the PhC gates. The gates satisfy their truth tables with reasonable power contrast ratio between logic '1' and logic '0'.

  2. Thermal stability of BaSrO thin films and the influence of Al intermediate layers to the electrical properties of high-k Si(001)/BaSrO/Au MOS diodes

    Energy Technology Data Exchange (ETDEWEB)

    Islam, Shariful; Mueller-Sajak, Dirk; Pfnuer, Herbert [Leibniz-Universitaet Hannover, Inst. f. Festkoerperphysik (Germany); Cosceev, Alexander; Hofmann, Karl R. [Leibniz-Universitaet Hannover, Bauelemente der Mikro- und Nanoelektronik (Germany)

    2011-07-01

    MOS diodes with crystalline Ba{sub 0.7}Sr{sub 0.3}O gate oxide and Au gate metal on n- and p-Si(001) were produced, which have a dielectric constant of {epsilon}{sub r}{approx}28. The oxides were grown on structured Si(001) in a UHV chamber by MBE in oxygen ambient conditions and capped with 100nm Au for ex-situ electrical measurements. I-V measurements show low leakage currents compared to SiO{sub 2} with the same EOT. From C-V measurements we extracted with the Terman method a density of interface states, D{sub it}, of only {approx}10{sup 10}eV{sup -1}cm{sup -2}. We tested the thermal stability of these oxides and investigated them with X-Ray Photoelectron Spectroscopy (XPS). They are fully stable up to 450 C but convert to other chemical species, most likely silicates, at higher temperatures. But even at 700 C no formation of SiO{sub 2} at the interface to Si was detectable. To improve the adhesion between the Au gate metal and the oxide we evaporated a thin layer of Al at the Au/oxide interface. This causes a thickness dependent shift of the flatband voltage. We present our XPS measurements of the chemical origin of this shift.

  3. Reversible logic gates on Physarum Polycephalum

    International Nuclear Information System (INIS)

    Schumann, Andrew

    2015-01-01

    In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum

  4. Demonstration of a Quantum Nondemolition Sum Gate

    DEFF Research Database (Denmark)

    Yoshikawa, J.; Miwa, Y.; Huck, Alexander

    2008-01-01

    The sum gate is the canonical two-mode gate for universal quantum computation based on continuous quantum variables. It represents the natural analogue to a qubit C-NOT gate. In addition, the continuous-variable gate describes a quantum nondemolition (QND) interaction between the quadrature...

  5. Deep Gate Recurrent Neural Network

    Science.gov (United States)

    2016-11-22

    and Fred Cummins. Learning to forget: Continual prediction with lstm . Neural computation, 12(10):2451–2471, 2000. Alex Graves. Generating sequences...DSGU) and Simple Gated Unit (SGU), which are structures for learning long-term dependencies. Compared to traditional Long Short-Term Memory ( LSTM ) and...Gated Recurrent Unit (GRU), both structures require fewer parameters and less computation time in sequence classification tasks. Unlike GRU and LSTM

  6. Bill Gates vil redde Folkeskolen

    DEFF Research Database (Denmark)

    Fejerskov, Adam Moe

    2014-01-01

    Det amerikanske uddannelsessystem bliver for tiden udsat for hård kritik, ledt an af Microsoft stifteren Bill Gates. Gates har indtil videre brugt 3 mia. kroner på at skabe opbakning til tiltag som præstationslønning af lærere og strømlining af pensum på tværs af alle skoler i landet...

  7. Latest design of gate valves

    Energy Technology Data Exchange (ETDEWEB)

    Kurzhofer, U.; Stolte, J.; Weyand, M.

    1996-12-01

    Babcock Sempell, one of the most important valve manufacturers in Europe, has delivered valves for the nuclear power industry since the beginning of the peaceful application of nuclear power in the 1960s. The latest innovation by Babcock Sempell is a gate valve that meets all recent technical requirements of the nuclear power technology. At the moment in the United States, Germany, Sweden, and many other countries, motor-operated gate and globe valves are judged very critically. Besides the absolute control of the so-called {open_quotes}trip failure,{close_quotes} the integrity of all valve parts submitted to operational forces must be maintained. In case of failure of the limit and torque switches, all valve designs have been tested with respect to the quality of guidance of the gate. The guidances (i.e., guides) shall avoid a tilting of the gate during the closing procedure. The gate valve newly designed by Babcock Sempell fulfills all these characteristic criteria. In addition, the valve has cobalt-free seat hardfacing, the suitability of which has been proven by friction tests as well as full-scale blowdown tests at the GAP of Siemens in Karlstein, West Germany. Babcock Sempell was to deliver more than 30 gate valves of this type for 5 Swedish nuclear power stations by autumn 1995. In the presentation, the author will report on the testing performed, qualifications, and sizing criteria which led to the new technical design.

  8. CMOS gate array characterization procedures

    Science.gov (United States)

    Spratt, James P.

    1993-09-01

    Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.

  9. Electrical actuation of dielectric droplets

    International Nuclear Information System (INIS)

    Kumari, N; Bahadur, V; Garimella, S V

    2008-01-01

    Electrical actuation of liquid droplets at the microscale offers promising applications in the fields of microfluidics and lab-on-a-chip devices. Much prior research has targeted the electrical actuation of electrically conducting liquid droplets; however, the actuation of dielectric droplets has remained relatively unexplored, despite the advantages associated with the use of a dielectric droplet. This paper presents modeling and experimental results on the electrical actuation of dielectric droplets between two flat plates. A first-order analytical model, based on the energy-minimization principle, is developed to estimate the electrical actuation force on a dielectric droplet as it moves between two flat plates. Two versions of this analytical model are benchmarked for their suitability and accuracy against a detailed numerical model. The actuation force prediction is then combined with available semi-analytical expressions for predicting the forces opposing droplet motion to develop a model that predicts transient droplet motion under electrical actuation. Electrical actuation of dielectric droplets is experimentally demonstrated by moving transformer oil droplets between two flat plates under the influence of an actuation voltage. Droplet velocities and their dependence on the plate spacing and the applied voltage are experimentally measured and showed reasonable agreement with predictions from the models developed

  10. Psychometrics and life history strategy: the structure and validity of the High K Strategy Scale.

    Science.gov (United States)

    Copping, Lee T; Campbell, Anne; Muncer, Steven

    2014-03-22

    In this paper, we critically review the conceptualization and implementation of psychological measures of life history strategy associated with Differential K theory. The High K Strategy Scale (HKSS: Giosan, 2006) was distributed to a large British sample (n = 809) with the aim of assessing its factor structure and construct validity in relation to theoretically relevant life history variables: age of puberty, age of first sexual encounter, and number of sexual partners. Exploratory and confirmatory factor analyses indicated that the HKSS in its current form did not show an adequate statistical fit to the data. Modifications to improve fit indicated four correlated factors (personal capital, environmental stability, environmental security, and social capital). Later puberty in women was positively associated with measures of the environment and personal capital. Among men, contrary to Differential K predictions but in line with female mate preferences, earlier sexual debut and more sexual partners were positively associated with more favorable environments and higher personal and social capital. We raise concerns about the use of psychometric indicators of lifestyle and personality as proxies for life history strategy when they have not been validated against objective measures derived from contemporary life history theory and when their status as causes, mediators, or correlates has not been investigated.

  11. High-k Scattering Receiver Mixer Performance for NSTX-U

    Science.gov (United States)

    Barchfeld, Robert; Riemenschneider, Paul; Domier, Calvin; Luhmann, Neville; Ren, Yang; Kaita, Robert

    2016-10-01

    The High-k Scattering system detects primarily electron-scale turbulence k θ spectra for studying electron thermal transport in NSTX-U. A 100 mW, 693 GHz probe beam passes through plasma, and scattered power is detected by a 4-pixel quasi optical, mixer array. Remotely controlled receiving optics allows the scattering volume to be located from core to edge with a k θ span of 7 to 40 cm-1. The receiver array features 4 RF diagonal input horns, where the electric field polarization is aligned along the diagonal of a square cross section horn, at 30 mm channel spacing. The local oscillator is provided by a 14.4 GHz source followed by a x48 multiplier chain, giving an intermediate frequency of 1 GHz. The receiver optics receive 4 discreet scattering angles simultaneously, and then focus the signals as 4 parallel signals to their respective horns. A combination of a steerable probe beam, and translating receiver, allows for upward or downward scattering which together can provide information about 2D turbulence wavenumber spectrum. IF signals are digitized and stored for later computer analysis. The performance of the receiver mixers is discussed, along with optical design features to enhance the tuning and performance of the mixers. Work supported in part by U.S. DOE Grant DE-FG02-99ER54518 and DE-AC02-09CH1146.

  12. An “ohmic-first” self-terminating gate-recess technique for normally-off Al2O3/GaN MOSFET

    Science.gov (United States)

    Wang, Hongyue; Wang, Jinyan; Li, Mengjun; He, Yandong; Wang, Maojun; Yu, Min; Wu, Wengang; Zhou, Yang; Dai, Gang

    2018-04-01

    In this article, an ohmic-first AlGaN/GaN self-terminating gate-recess etching technique was demonstrated where ohmic contact formation is ahead of gate-recess-etching/gate-dielectric-deposition (GRE/GDD) process. The ohmic contact exhibits few degradations after the self-terminating gate-recess process. Besides, when comparing with that using the conventional fabrication process, the fabricated device using the ohmic-first fabrication process shows a better gate dielectric quality in terms of more than 3 orders lower forward gate leakage current, more than twice higher reverse breakdown voltage as well as better stability. Based on this proposed technique, the normally-off Al2O3/GaN MOSFET exhibits a threshold voltage (V th) of ˜1.8 V, a maximum drain current of ˜328 mA/mm, a forward gate leakage current of ˜10-6 A/mm and an off-state breakdown voltage of 218 V at room temperature. Meanwhile, high temperature characteristics of the device was also evaluated and small variations (˜7.6%) of the threshold voltage was confirmed up to 300 °C.

  13. Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

    International Nuclear Information System (INIS)

    Kranti, Abhinav; Hao Ying; Armstrong, G Alastair

    2008-01-01

    In this paper, by investigating the influence of source/drain extension region engineering (also known as gate–source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-κ gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on–off current ratio (I on /I off ). Based on the investigation of on-current (I on ), off-current (I off ), I on /I off , intrinsic delay (τ), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/σ) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I on , I off and τ is also investigated for optimized underlap devices

  14. Vertical dielectric screening of few-layer van der Waals semiconductors.

    Science.gov (United States)

    Koo, Jahyun; Gao, Shiyuan; Lee, Hoonkyung; Yang, Li

    2017-10-05

    Vertical dielectric screening is a fundamental parameter of few-layer van der Waals two-dimensional (2D) semiconductors. However, unlike the widely-accepted wisdom claiming that the vertical dielectric screening is sensitive to the thickness, our first-principles calculation based on the linear response theory (within the weak field limit) reveals that this screening is independent of the thickness and, in fact, it is the same as the corresponding bulk value. This conclusion is verified in a wide range of 2D paraelectric semiconductors, covering narrow-gap ones and wide-gap ones with different crystal symmetries, providing an efficient and reliable way to calculate and predict static dielectric screening of reduced-dimensional materials. Employing this conclusion, we satisfactorily explain the tunable band gap in gated 2D semiconductors. We further propose to engineer the vertical dielectric screening by changing the interlayer distance via vertical pressure or hybrid structures. Our predicted vertical dielectric screening can substantially simplify the understanding of a wide range of measurements and it is crucial for designing 2D functional devices.

  15. Laser amplification in excited dielectrics

    Science.gov (United States)

    Winkler, Thomas; Haahr-Lillevang, Lasse; Sarpe, Cristian; Zielinski, Bastian; Götte, Nadine; Senftleben, Arne; Balling, Peter; Baumert, Thomas

    2018-01-01

    Wide-bandgap dielectrics such as glasses or water are transparent at visible and infrared wavelengths. This changes when they are exposed to ultrashort and highly intense laser pulses. Different interaction mechanisms lead to the appearance of various transient nonlinear optical phenomena. Using these, the optical properties of dielectrics can be controlled from the transparent to the metal-like state. Here we expand this range by a yet unexplored mechanism in excited dielectrics: amplification. In a two-colour pump-probe experiment, we show that a 400 nm femtosecond laser pulse is coherently amplified inside an excited sapphire sample on a scale of a few micrometres. Simulations strongly support the proposed two-photon stimulated emission process, which is temporally and spatially controllable. Consequently, we expect applications in all fields that demand strongly localized amplification.

  16. Dielectric function of semiconductor superlattice

    International Nuclear Information System (INIS)

    Qin Guoyi.

    1990-08-01

    We present a calculation of the dielectric function for semiconductor GaAs/Ga 1-x Al x As superlattice taking account of the extension of the electron envelope function and the difference of both the dielectric constant and width between GaAs and Ga 1-x Al x As layers. In the appropriate limits, our results exactly reduce to the well-known results of the quasi two-dimensional electron gas obtained by Lee and Spector and of the period array of two-dimensional electron layers obtained by Das Sarma and Quinn. By means of the dielectric function of the superlattice, the dispersion relation of the collective excitation and the screening property of semiconductor superlattice are discussed and compared with the results of the quasi two-dimensional system and with the results of the periodic array of the two-dimensional electron layers. (author). 4 refs, 3 figs

  17. Novel technique of source and drain engineering for dual-material double-gate (DMDG) SOI MOSFETS

    Science.gov (United States)

    Yadav, Himanshu; Malviya, Abhishek Kumar; Chauhan, R. K.

    2018-04-01

    The dual-metal dual-gate (DMDG) SOI has been used with Dual Sided Source and Drain Engineered 50nm SOI MOSFET with various high-k gate oxide. It has been scrutinized in this work to enhance its electrical performance. The proposed structure is designed by creating Dual Sided Source and Drain Modification and its characteristics are evaluated on ATLAS device simulator. The consequence of this dual sided assorted doping on source and drain side of the DMDG transistor has better leakage current immunity and heightened ION current with higher ION to IOFF Ratio. Which thereby vesting the proposed device appropriate for low power digital applications.

  18. Capacitive Cells for Dielectric Constant Measurement

    Science.gov (United States)

    Aguilar, Horacio Munguía; Maldonado, Rigoberto Franco

    2015-01-01

    A simple capacitive cell for dielectric constant measurement in liquids is presented. As an illustrative application, the cell is used for measuring the degradation of overheated edible oil through the evaluation of their dielectric constant.

  19. Dielectric behaviour of strontium tartrate single crystals

    Indian Academy of Sciences (India)

    Unknown

    dielectric loss (tan δ) as functions of frequency and temperature. Ion core type ... Since the data on dielectric properties of strontium tartrate trihydrate (STT) do not ... through 'AE' make 15-amp dimmerstat, the rate of heating was maintained ...

  20. The Dielectric Constant of Lubrication Oils

    National Research Council Canada - National Science Library

    Carey, A

    1998-01-01

    The values of the dielectric constant of simple molecules is discussed first, along with the relationship between the dielectric constant and other physical properties such as boiling point, melting...

  1. Semiconductor/dielectric interface engineering and characterization

    Science.gov (United States)

    Lucero, Antonio T.

    without exposing the sample to air. This is the first time that such a system has been reported. A special air-gap C-V probe will allow top gated measurements to be made, allowing semiconductor-dielectric interfaces to be studied during device processing.

  2. Silicone elastomers with high dielectric permittivity and high dielectric breakdown strength based on tunable functionalized copolymers

    DEFF Research Database (Denmark)

    Madsen, Frederikke Bahrt; Yu, Liyun; Daugaard, Anders Egede

    2015-01-01

    system, with respect to functionalization, is achieved. It is investigated how the different functionalization variables affect essential DE properties, including dielectric permittivity, dielectric loss, elastic modulus and dielectric breakdown strength, and the optimal degree of chemical......%) was obtained without compromising other vital DE properties such as elastic modulus, gel fraction, dielectric and viscous loss and electrical breakdown strength....

  3. Geometric phase from dielectric matrix

    International Nuclear Information System (INIS)

    Banerjee, D.

    2005-10-01

    The dielectric property of the anisotropic optical medium is found by considering the polarized photon as two component spinor of spherical harmonics. The Geometric Phase of a polarized photon has been evaluated in two ways: the phase two-form of the dielectric matrix through a twist and the Pancharatnam phase (GP) by changing the angular momentum of the incident polarized photon over a closed triangular path on the extended Poincare sphere. The helicity in connection with the spin angular momentum of the chiral photon plays the key role in developing these phase holonomies. (author)

  4. Charge accumulation in lossy dielectrics: a review

    DEFF Research Database (Denmark)

    Rasmussen, Jørgen Knøster; McAllister, Iain Wilson; Crichton, George C

    1999-01-01

    At present, the phenomenon of charge accumulation in solid dielectrics is under intense experimental study. Using a field theoretical approach, we review the basis for charge accumulation in lossy dielectrics. Thereafter, this macroscopic approach is applied to planar geometries such that the mat......At present, the phenomenon of charge accumulation in solid dielectrics is under intense experimental study. Using a field theoretical approach, we review the basis for charge accumulation in lossy dielectrics. Thereafter, this macroscopic approach is applied to planar geometries...

  5. Cellulose Triacetate Dielectric Films For Capacitors

    Science.gov (United States)

    Yen, Shiao-Ping S.; Jow, T. Richard

    1994-01-01

    Cellulose triacetate investigated for use as dielectric material in high-energy-density capacitors for pulsed-electrical-power systems. Films of cellulose triacetate metalized on one or both sides for use as substrates for electrodes and/or as dielectrics between electrodes in capacitors. Used without metalization as simple dielectric films. Advantages include high breakdown strength and self-healing capability.

  6. Ozone production process in pulsed positive dielectric barrier discharge

    Energy Technology Data Exchange (ETDEWEB)

    Ono, Ryo [High Temperature Plasma Center, University of Tokyo, 5-1-5 Kashiwanoha, Kashiwa, Chiba, 227-8568 (Japan); Oda, Tetsuji [Department of Electrical Engineering, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo, 113-8656 (Japan)

    2007-01-07

    The ozone production process in a pulsed positive dielectric barrier discharge (DBD) is studied by measuring the spatial distribution of ozone density using a two-dimensional laser absorption method. DBD occurs in a 6 mm point-to-plane gap with a 1 mm-thick glass plate placed on the plane electrode. First, the propagation of DBD is observed using a short-gated ICCD camera. It is shown that DBD develops in three phases: primary streamer, secondary streamer and surface discharge phases. Next, the spatial distribution of ozone density is measured. It is shown that ozone is mostly produced in the secondary streamer and surface discharge, while only a small amount of ozone is produced in the primary streamer. The rate coefficient of the ozone production reaction, O + O{sub 2} + M {yields} O{sub 3} + M, is estimated to be 2.5 x 10{sup -34} cm{sup 6} s{sup -1}.

  7. Ozone production process in pulsed positive dielectric barrier discharge

    Science.gov (United States)

    Ono, Ryo; Oda, Tetsuji

    2007-01-01

    The ozone production process in a pulsed positive dielectric barrier discharge (DBD) is studied by measuring the spatial distribution of ozone density using a two-dimensional laser absorption method. DBD occurs in a 6 mm point-to-plane gap with a 1 mm-thick glass plate placed on the plane electrode. First, the propagation of DBD is observed using a short-gated ICCD camera. It is shown that DBD develops in three phases: primary streamer, secondary streamer and surface discharge phases. Next, the spatial distribution of ozone density is measured. It is shown that ozone is mostly produced in the secondary streamer and surface discharge, while only a small amount of ozone is produced in the primary streamer. The rate coefficient of the ozone production reaction, O + O2 + M → O3 + M, is estimated to be 2.5 × 10-34 cm6 s-1.

  8. Ozone production process in pulsed positive dielectric barrier discharge

    International Nuclear Information System (INIS)

    Ono, Ryo; Oda, Tetsuji

    2007-01-01

    The ozone production process in a pulsed positive dielectric barrier discharge (DBD) is studied by measuring the spatial distribution of ozone density using a two-dimensional laser absorption method. DBD occurs in a 6 mm point-to-plane gap with a 1 mm-thick glass plate placed on the plane electrode. First, the propagation of DBD is observed using a short-gated ICCD camera. It is shown that DBD develops in three phases: primary streamer, secondary streamer and surface discharge phases. Next, the spatial distribution of ozone density is measured. It is shown that ozone is mostly produced in the secondary streamer and surface discharge, while only a small amount of ozone is produced in the primary streamer. The rate coefficient of the ozone production reaction, O + O 2 + M → O 3 + M, is estimated to be 2.5 x 10 -34 cm 6 s -1

  9. Tailoring the Dielectric Layer Structure for Enhanced Performance of Organic Field-Effect Transistors: The Use of a Sandwiched Polar Dielectric Layer

    Directory of Open Access Journals (Sweden)

    Shijiao Han

    2016-07-01

    Full Text Available To investigate the origins of hydroxyl groups in a polymeric dielectric and its applications in organic field-effect transistors (OFETs, a polar polymer layer was inserted between two polymethyl methacrylate (PMMA dielectric layers, and its effect on the performance as an organic field-effect transistor (OFET was studied. The OFETs with a sandwiched dielectric layer of poly(vinyl alcohol (PVA or poly(4-vinylphenol (PVP containing hydroxyl groups had shown enhanced characteristics compared to those with only PMMA layers. The field-effect mobility had been raised more than 10 times in n-type devices (three times in the p-type one, and the threshold voltage had been lowered almost eight times in p-type devices (two times in the n-type. The on-off ratio of two kinds of devices had been enhanced by almost two orders of magnitude. This was attributed to the orientation of hydroxyl groups from disordered to perpendicular to the substrate under gate-applied voltage bias, and additional charges would be induced by this polarization at the interface between the semiconductor and dielectrics, contributing to the accumulation of charge transfer.

  10. New opening hours of the gates

    CERN Multimedia

    GS Department

    2009-01-01

    Please note the new opening hours of the gates as well as the intersites tunnel from the 19 May 2009: GATE A 7h - 19h GATE B 24h/24 GATE C 7h - 9h\t17h - 19h GATE D 8h - 12h\t13h - 16h GATE E 7h - 9h\t17h - 19h Prévessin 24h/24 The intersites tunnel will be opened from 7h30 to 18h non stop. GS-SEM Group Infrastructure and General Services Department

  11. Solvothermal synthesis of gallium-indium-zinc-oxide nanoparticles for electrolyte-gated transistors.

    Science.gov (United States)

    Santos, Lídia; Nunes, Daniela; Calmeiro, Tomás; Branquinho, Rita; Salgueiro, Daniela; Barquinha, Pedro; Pereira, Luís; Martins, Rodrigo; Fortunato, Elvira

    2015-01-14

    Solution-processed field-effect transistors are strategic building blocks when considering low-cost sustainable flexible electronics. Nevertheless, some challenges (e.g., processing temperature, reliability, reproducibility in large areas, and cost effectiveness) are requirements that must be surpassed in order to achieve high-performance transistors. The present work reports electrolyte-gated transistors using as channel layer gallium-indium-zinc-oxide nanoparticles produced by solvothermal synthesis combined with a solid-state electrolyte based on aqueous dispersions of vinyl acetate stabilized with cellulose derivatives, acrylic acid ester in styrene and lithium perchlorate. The devices fabricated using this approach display a ION/IOFF up to 1 × 10(6), threshold voltage (VTh) of 0.3-1.9 V, and mobility up to 1 cm(2)/(V s), as a function of gallium-indium-zinc-oxide ink formulation and two different annealing temperatures. These results validates the usage of electrolyte-gated transistors as a viable and promising alternative for nanoparticle based semiconductor devices as the electrolyte improves the interface and promotes a more efficient step coverage of the channel layer, reducing the operating voltage when compared with conventional dielectrics gating. Moreover, it is shown that by controlling the applied gate potential, the operation mechanism of the electrolyte-gated transistors can be modified from electric double layer to electrochemical doping.

  12. Design and optimization analysis of dual material gate on DG-IMOS

    Science.gov (United States)

    Singh, Sarabdeep; Raman, Ashish; Kumar, Naveen

    2017-12-01

    An impact ionization MOSFET (IMOS) is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope (SS) of conventional MOSFET at room temperature. In this work, first, the device performance of the p-type double gate impact ionization MOSFET (DG-IMOS) is optimized by adjusting the device design parameters. The adjusted parameters are ratio of gate and intrinsic length, gate dielectric thickness and gate work function. Secondly, the DMG (dual material gate) DG-IMOS is proposed and investigated. This DMG DG-IMOS is further optimized to obtain the best possible performance parameters. Simulation results reveal that DMG DG-IMOS when compared to DG-IMOS, shows better I ON, I ON/I OFF ratio, and RF parameters. Results show that by properly tuning the lengths of two materials at a ratio of 1.5 in DMG DG-IMOS, optimized performance is achieved including I ON/I OFF ratio of 2.87 × 109 A/μm with I ON as 11.87 × 10-4 A/μm and transconductance of 1.06 × 10-3 S/μm. It is analyzed that length of drain side material should be greater than the length of source side material to attain the higher transconductance in DMG DG-IMOS.

  13. Dielectric waveguide amplifiers and lasers

    NARCIS (Netherlands)

    Pollnau, Markus

    The performance of semiconductor amplifiers and lasers has made them the preferred choice for optical gain on a micro-chip. In the past few years, we have demonstrated that also rare-earth-ion-doped dielectric waveguides show remarkable performance, ranging from a small-signal gain per unit length

  14. Dielectric properties of fly ash

    Indian Academy of Sciences (India)

    Unknown

    India's annual coal production is used in about 72 power- generating plants and ... performance of this material as cracking catalyst was investigated with ... Chemically, the FA was silica to an extent of 55–70%, followed by ... Cu, Pb, Cd, Ag, Mn, Fe, Ti, Na, Mo, S, P, Zn and Cl in different ... two-probe method. The dielectric ...

  15. Dielectric polarization in random media

    International Nuclear Information System (INIS)

    Ramshaw, J.D.

    1984-01-01

    The theory of dielectric polarization in random media is systematically formulated in terms of response kernels. The primary response kernel K(12) governs the mean dielectric response at the point r 1 to the external electric field at the point r 2 in an infinite system. The inverse of K(12) is denoted by L(12);. it is simpler and more fundamental than K(12) itself. Rigorous expressions are obtained for the effective dielectric constant epsilon( in terms of L(12) and K(12). The latter expression involves the Onsger-Kirkwood function (epsilon(-epsilon 0 (2epsilon(+epsilon 0 )/epsilon 0 epsilon( (where epsilon 0 is an arbitrary reference value), and appears to be new to the random medium context. A wide variety of series representations for epsilon( are generated by means of general perturbation expansions for K(12) and L(12). A discussion is given of certain pitfalls in the theory, most of which are related to the fact that the response kernels are long ranged. It is shown how the dielectric behavior of nonpolar molecular fluids may be treated as a special case of the general theory. The present results for epsilon( apply equally well to other effective phenomenological coefficients of the same generic type, such as thermal and electrical conductivity, magnetic susceptibility, and diffusion coefficients

  16. Improved di-electric composition

    Energy Technology Data Exchange (ETDEWEB)

    Sharp, R C

    1915-03-29

    An improved di-electric composition is disclosed composed of pitch or bitumen which is melted, and to which is added, while molten, a quantity of finely ground or pulverized spent shale, the whole being mixed or stirred to make a homogeneous composition, substantially as described.

  17. Respiratory gating in cardiac PET

    DEFF Research Database (Denmark)

    Lassen, Martin Lyngby; Rasmussen, Thomas; Christensen, Thomas E

    2017-01-01

    BACKGROUND: Respiratory motion due to breathing during cardiac positron emission tomography (PET) results in spatial blurring and erroneous tracer quantification. Respiratory gating might represent a solution by dividing the PET coincidence dataset into smaller respiratory phase subsets. The aim...... of our study was to compare the resulting imaging quality by the use of a time-based respiratory gating system in two groups administered either adenosine or dipyridamole as the pharmacological stress agent. METHODS AND RESULTS: Forty-eight patients were randomized to adenosine or dipyridamole cardiac...... stress (82)RB-PET. Respiratory rates and depths were measured by a respiratory gating system in addition to registering actual respiratory rates. Patients undergoing adenosine stress showed a decrease in measured respiratory rate from initial to later scan phase measurements [12.4 (±5.7) vs 5.6 (±4...

  18. Robustness of holonomic quantum gates

    International Nuclear Information System (INIS)

    Solinas, P.; Zanardi, P.; Zanghi, N.

    2005-01-01

    Full text: If the driving field fluctuates during the quantum evolution this produces errors in the applied operator. The holonomic (and geometrical) quantum gates are believed to be robust against some kind of noise. Because of the geometrical dependence of the holonomic operators can be robust against this kind of noise; in fact if the fluctuations are fast enough they cancel out leaving the final operator unchanged. I present the numerical studies of holonomic quantum gates subject to this parametric noise, the fidelity of the noise and ideal evolution is calculated for different noise correlation times. The holonomic quantum gates seem robust not only for fast fluctuating fields but also for slow fluctuating fields. These results can be explained as due to the geometrical feature of the holonomic operator: for fast fluctuating fields the fluctuations are canceled out, for slow fluctuating fields the fluctuations do not perturb the loop in the parameter space. (author)

  19. Investigation of the dielectric properties of shale

    International Nuclear Information System (INIS)

    Martemyanov, Sergey M.

    2011-01-01

    The article is dedicated to investigation of the dielectric properties of oil shale. Investigations for samples prepared from shale mined at the deposit in Jilin Province in China were done. The temperature and frequency dependences of rock characteristics needed to calculate the processes of their thermal processing are investigated. Frequency dependences for the relative dielectric constant and dissipation factor of rock in the frequency range from 0,1 Hz to 1 MHz are investigated. The temperature dependences for rock resistance, dielectric capacitance and dissipation factor in the temperature range from 20 to 600°C are studied. Key words: shale, dielectric properties, relative dielectric constant, dissipation factor, temperature dependence, frequency dependence

  20. Shellac Films as a Natural Dielectric Layer for Enhanced Electron Transport in Polymer Field-Effect Transistors.

    Science.gov (United States)

    Baek, Seung Woon; Ha, Jong-Woon; Yoon, Minho; Hwang, Do-Hoon; Lee, Jiyoul

    2018-06-06

    Shellac, a natural polymer resin obtained from the secretions of lac bugs, was evaluated as a dielectric layer in organic field-effect transistors (OFETs) on the basis of donor (D)-acceptor (A)-type conjugated semiconducting copolymers. The measured dielectric constant and breakdown field of the shellac layer were ∼3.4 and 3.0 MV/cm, respectively, comparable with those of a poly(4-vinylphenol) (PVP) film, a commonly used dielectric material. Bottom-gate/top-contact OFETs were fabricated with shellac or PVP as the dielectric layer and one of three different D-A-type semiconducting copolymers as the active layer: poly(cyclopentadithiophene- alt-benzothiadiazole) with p-type characteristics, poly(naphthalene-bis(dicarboximide)- alt-bithiophene) [P(NDI2OD-T2)] with n-type characteristics, and poly(dithienyl-diketopyrrolopyrrole- alt-thienothiophene) [P(DPP2T-TT)] with ambipolar characteristics. The electrical characteristics of the fabricated OFETs were then measured. For all active layers, OFETs with a shellac film as the dielectric layer exhibited a better mobility than those with PVP. For example, the mobility of the OFET with a shellac dielectric and n-type P(NDI2OD-T2) active layer was approximately 2 orders of magnitude greater than that of the corresponding OFET with a PVP insulating layer. When P(DPP2T-TT) served as the active layer, the OFET with shellac as the dielectric exhibited ambipolar characteristics, whereas the corresponding OFET with the PVP dielectric operated only in hole-accumulation mode. The total density of states was analyzed using technology computer-aided design simulations. The results revealed that compared with the OFETs with PVP as the dielectric, the OFETs with shellac as the dielectric had a lower trap-site density at the polymer semiconductor/dielectric interface and much fewer acceptor-like trap sites acting as electron traps. These results demonstrate that shellac is a suitable dielectric material for D-A-type semiconducting