High performance solution processed zirconium oxide gate dielectric appropriate for low temperature device application

Energy Technology Data Exchange (ETDEWEB)

Hasan, Musarrat; Nguyen, Manh-Cuong; Kim, Hyojin; You, Seung-Won; Jeon, Yoon-Seok; Tong, Duc-Tai; Lee, Dong-Hwi; Jeong, Jae Kyeong; Choi, Rino, E-mail: rino.choi@inha.ac.kr

2015-08-31

This paper reports a solution processed electrical device with zirconium oxide gate dielectric that was fabricated at a low enough temperature appropriate for flexible electronics. Both inorganic dielectric and channel materials were synthesized in the same organic solvent. The dielectric constant achieved was 13 at 250 °C with a reasonably low leakage current. The bottom gate transistor devices showed the highest mobility of 75 cm{sup 2}/V s. The device is operated at low voltage with high-k dielectric with excellent transconductance and low threshold voltage. Overall, the results highlight the potential of low temperature solution based deposition in fabricating more complicated circuits for a range of applications. - Highlights: • We develop a low temperature inorganic dielectric deposition process. • We fabricate oxide semiconductor channel devices using all-solution processes. • Same solvent is used for dielectric and oxide semiconductor deposition.

High-performance pentacene OTFT by incorporating Ti in LaON gate dielectric

Science.gov (United States)

Ma, Y. X.; Han, C. Y.; Tang, W. M.; Lai, P. T.

2017-07-01

Pentacene organic thin-film transistors (OTFT) using high-k LaTiON gate dielectric with different Ti contents are investigated. The LaxTi(1-x)ON films (with x = 1, 0.87, 0.76, and 0.67) are deposited by reactive sputtering followed by an annealing in N2 at 200 °C. The OTFT with La0.87Ti0.13ON can achieve a high carrier mobility of 2.6 cm2/V.s, a small threshold voltage of -1.5 V, a small sub-threshold swing of 0.07 V/dec, and a small hysteresis of 0.17 V. AFM and X-ray photoelectron spectroscopy reveal that Ti can suppress the hygroscopicity of La oxide to achieve a smoother dielectric surface, which can result in larger pentacene grains and thus higher carrier mobility. All the devices show a clockwise hysteresis because both the LaOH formation and Ti incorporation can generate acceptor-like traps in the gate dielectric.

Electrical Properties of Ultrathin Hf-Ti-O Higher k Gate Dielectric Films and Their Application in ETSOI MOSFET.

Science.gov (United States)

Xiong, Yuhua; Chen, Xiaoqiang; Wei, Feng; Du, Jun; Zhao, Hongbin; Tang, Zhaoyun; Tang, Bo; Wang, Wenwu; Yan, Jiang

2016-12-01

Ultrathin Hf-Ti-O higher k gate dielectric films (~2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) ~9.4%, low equivalent gate oxide thickness (EOT) of ~0.69 nm and acceptable gate leakage current density of 0.61 A/cm 2 @ (V fb  - 1)V could be obtained. The conduction mechanism through the gate dielectric is dominated by the F-N tunneling in the gate voltage range of -0.5 to -2 V. Under the same physical thickness and process flow, lower EOT and higher I on /I off ratio could be obtained while using Hf-Ti-O as gate dielectric compared with HfO 2 . With Hf-Ti-O as gate dielectric, two ETSOI PMOSFETs with gate width/gate length (W/L) of 0.5 μm/25 nm and 3 μm/40 nm show good performances such as high I on , I on /I off ratio in the magnitude of 10 5 , and peak transconductance, as well as suitable threshold voltage (-0.3~-0.2 V). Particularly, ETSOI PMOSFETs show superior short-channel control capacity with DIBL <82 mV/V and subthreshold swing <70 mV/decade.

High-κ gate dielectrics: Current status and materials properties considerations

Science.gov (United States)

Wilk, G. D.; Wallace, R. M.; Anthony, J. M.

2001-05-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward successful integration into the expected processing conditions for future CMOS technologies, especially due to their tendency to form at interfaces with Si (e.g. silicates). These pseudobinary systems also thereby enable the use of other high-κ materials by serving as an interfacial high-κ layer. While work is ongoing, much research is still required, as it is clear that any material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology

International Nuclear Information System (INIS)

Weng, W.T.; Lin, H.C.; Huang, T.Y.; Lee, Y.J.; Lin, H.C.

2009-01-01

This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO 2 /poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

Design of Higher-k and More Stable Rare Earth Oxides as Gate Dielectrics for Advanced CMOS Devices

Directory of Open Access Journals (Sweden)

Yi Zhao

2012-08-01

Full Text Available High permittivity (k gate dielectric films are widely studied to substitute SiO₂ as gate oxides to suppress the unacceptable gate leakage current when the traditional SiO₂ gate oxide becomes ultrathin. For high-k gate oxides, several material properties are dominantly important. The first one, undoubtedly, is permittivity. It has been well studied by many groups in terms of how to obtain a higher permittivity for popular high-k oxides, like HfO₂ and La₂O₃. The second one is crystallization behavior. Although it’s still under the debate whether an amorphous film is definitely better than ploy-crystallized oxide film as a gate oxide upon considering the crystal boundaries induced leakage current, the crystallization behavior should be well understood for a high-k gate oxide because it could also, to some degree, determine the permittivity of the high-k oxide. Finally, some high-k gate oxides, especially rare earth oxides (like La₂O₃, are not stable in air and very hygroscopic, forming hydroxide. This topic has been well investigated in over the years and significant progresses have been achieved. In this paper, I will intensively review the most recent progresses of the experimental and theoretical studies for preparing higher-k and more stable, in terms of hygroscopic tolerance and crystallization behavior, Hf- and La-based ternary high-k gate oxides.

Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor

Science.gov (United States)

Madan, Jaya; Gupta, R. S.; Chaujar, Rishu

2015-09-01

In this work, an analytical drain current model for gate dielectric engineered (hetero dielectric)-dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed. Parabolic approximation has been used to solve the two-dimensional (2D) Poisson equation with appropriate boundary conditions and continuity equations to evaluate analytical expressions for surface potential, electric field, tunneling barrier width and drain current. Further, the analog performance of the device is studied for three high-k dielectrics (Si3N4, HfO2, and ZrO2), and it has been investigated that the problem of lower ION, can be overcome by using the hetero-gate architecture. Moreover, the impact of scaling the gate oxide thickness and bias variations has also been studied. The HD-DMG-GAA-TFET shows an enhanced ION of the order of 10-4 A. The effectiveness of the proposed model is validated by comparing it with ATLAS device simulations.

Investigation of 6T SRAM memory circuit using high-k dielectrics based nano scale junctionless transistor

Science.gov (United States)

Charles Pravin, J.; Nirmal, D.; Prajoon, P.; Mohan Kumar, N.; Ajayan, J.

2017-04-01

In this paper the Dual Metal Surround Gate Junctionless Transistor (DMSGJLT) has been implemented with various high-k dielectric. The leakage current in the device is analysed in detail by obtaining the band structure for different high-k dielectric material. It is noticed that with increasing dielectric constant the device provides more resistance for the direct tunnelling of electron in off state. The gate oxide capacitance also shows 0.1 μF improvement with Hafnium Oxide (HfO2) than Silicon Oxide (SiO2). This paved the way for a better memory application when high-k dielectric is used. The Six Transistor (6T) Static Random Access Memory (SRAM) circuit implemented shows 41.4% improvement in read noise margin for HfO2 than SiO2. It also shows 37.49% improvement in write noise margin and 30.16% improvement in hold noise margin for HfO2 than SiO2.

Microstructure and chemical analysis of Hf-based high-k dielectric layers in metal-insulator-metal capacitors

Energy Technology Data Exchange (ETDEWEB)

Thangadurai, P. [Department of Materials Engineering, Technion - Israel Institute of Technology, Haifa 32000 (Israel); Mikhelashvili, V.; Eisenstein, G. [Department of Electrical Engineering, Technion - Israel Institute of Technology, Haifa 32000 (Israel); Kaplan, W.D., E-mail: kaplan@tx.technion.ac.i [Department of Materials Engineering, Technion - Israel Institute of Technology, Haifa 32000 (Israel)

2010-05-31

The microstructure and chemistry of the high-k gate dielectric significantly influences the performance of metal-insulator-metal (MIM) and metal-oxide-semiconductor devices. In particular, the local structure, chemistry, and inter-layer mixing are important phenomena to be understood. In the present study, high resolution and analytical transmission electron microscopy are combined to study the local structure, morphology, and chemistry in MIM capacitors containing a Hf-based high-k dielectric. The gate dielectric, bottom and gate electrodes were deposited on p-type Si(100) wafers by electron beam evaporation. Four chemically distinguishable sub-layers were identified within the dielectric stack. One is an unintentionally formed 4.0 nm thick interfacial layer of Ta{sub 2}O{sub 5} at the interface between the Ta electrode and the dielectric. The other three layers are based on HfN{sub x}O{sub y} and HfTiO{sub y}, and intermixing between the nearby sub-layers including deposited SiO{sub 2}. Hf-rich clusters were found in the HfN{sub x}O{sub y} layer adjacent to the Ta{sub 2}O{sub 5} layer.

Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for Advanced CMOS Devices

Directory of Open Access Journals (Sweden)

Masamichi Suzuki

2012-03-01

Full Text Available A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3 high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process.

First-principles simulations of the leakage current in metal-oxide-semiconductor structures caused by oxygen vacancies in HfO2 high-K gate dielectric

International Nuclear Information System (INIS)

Mao, L.F.; Wang, Z.O.

2008-01-01

HfO 2 high-K gate dielectric has been used as a new gate dielectric in metal-oxide-semiconductor structures. First-principles simulations are used to study the effects of oxygen vacancies on the tunneling current through the oxide. A level which is nearly 1.25 eV from the bottom of the conduction band is introduced into the bandgap due to the oxygen vacancies. The tunneling current calculations show that the tunneling currents through the gate oxide with different defect density possess the typical characteristic of stress-induced leakage current. Further analysis shows that the location of oxygen vacancies will have a marked effect on the tunneling current. The largest increase in the tunneling current caused by oxygen vacancies comes about at the middle oxide field when defects are located at the middle of the oxide. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Materials Fundamentals of Gate Dielectrics

CERN Document Server

Demkov, Alexander A

2006-01-01

This book presents materials fundamentals of novel gate dielectrics that are being introduced into semiconductor manufacturing to ensure the continuous scalling of the CMOS devices. This is a very fast evolving field of research so we choose to focus on the basic understanding of the structure, thermodunamics, and electronic properties of these materials that determine their performance in device applications. Most of these materials are transition metal oxides. Ironically, the d-orbitals responsible for the high dielectric constant cause sever integration difficulties thus intrinsically limiting high-k dielectrics. Though new in the electronics industry many of these materials are wel known in the field of ceramics, and we describe this unique connection. The complexity of the structure-property relations in TM oxides makes the use of the state of the art first-principles calculations necessary. Several chapters give a detailed description of the modern theory of polarization, and heterojunction band discont...

Study of strained-Si p-channel MOSFETs with HfO2 gate dielectric

Science.gov (United States)

Pradhan, Diana; Das, Sanghamitra; Dash, Tara Prasanna

2016-10-01

In this work, the transconductance of strained-Si p-MOSFETs with high-K dielectric (HfO2) as gate oxide, has been presented through simulation using the TCAD tool Silvaco-ATLAS. The results have been compared with a SiO2/strained-Si p-MOSFET device. Peak transconductance enhancement factors of 2.97 and 2.73 has been obtained for strained-Si p-MOSFETs in comparison to bulk Si channel p-MOSFETs with SiO2 and high-K dielectric respectively. This behavior is in good agreement with the reported experimental results. The transconductance of the strained-Si device at low temperatures has also been simulated. As expected, the mobility and hence the transconductance increases at lower temperatures due to reduced phonon scattering. However, the enhancements with high-K gate dielectric is less as compared to that with SiO2.

Vacancy-fluorine complexes and their impact on the properties of metal-oxide transistors with high-k gate dielectrics studied using monoenergetic positron beams

Science.gov (United States)

Uedono, A.; Inumiya, S.; Matsuki, T.; Aoyama, T.; Nara, Y.; Ishibashi, S.; Ohdaira, T.; Suzuki, R.; Miyazaki, S.; Yamada, K.

2007-09-01

Vacancy-fluorine complexes in metal-oxide semiconductors (MOS) with high-k gate dielectrics were studied using a positron annihilation technique. F+ ions were implanted into Si substrates before the deposition of gate dielectrics (HfSiON). The shift of threshold voltage (Vth) in MOS capacitors and an increase in Fermi level position below the HfSiON/Si interface were observed after F+ implantation. Doppler broadening spectra of the annihilation radiation and positron lifetimes were measured before and after HfSiON fabrication processes. From a comparison between Doppler broadening spectra and those obtained by first-principles calculation, the major defect species in Si substrates after annealing treatment (1050 °C, 5 s) was identified as vacancy-fluorine complexes (V3F2). The origin of the Vth shift in the MOS capacitors was attributed to V3F2 located in channel regions.

Low-Temperature Solution-Processed Gate Dielectrics for High-Performance Organic Thin Film Transistors

Directory of Open Access Journals (Sweden)

Jaekyun Kim

2015-10-01

Full Text Available A low-temperature solution-processed high-k gate dielectric layer for use in a high-performance solution-processed semiconducting polymer organic thin-film transistor (OTFT was demonstrated. Photochemical activation of sol-gel-derived AlOx films under 150 °C permitted the formation of a dense film with low leakage and relatively high dielectric-permittivity characteristics, which are almost comparable to the results yielded by the conventionally used vacuum deposition and high temperature annealing method. Octadecylphosphonic acid (ODPA self-assembled monolayer (SAM treatment of the AlOx was employed in order to realize high-performance (>0.4 cm2/Vs saturation mobility and low-operation-voltage (<5 V diketopyrrolopyrrole (DPP-based OTFTs on an ultra-thin polyimide film (3-μm thick. Thus, low-temperature photochemically-annealed solution-processed AlOx film with SAM layer is an attractive candidate as a dielectric-layer for use in high-performance organic TFTs operated at low voltages.

Evolutionary search for new high-k dielectric materials: methodology and applications to hafnia-based oxides.

Science.gov (United States)

Zeng, Qingfeng; Oganov, Artem R; Lyakhov, Andriy O; Xie, Congwei; Zhang, Xiaodong; Zhang, Jin; Zhu, Qiang; Wei, Bingqing; Grigorenko, Ilya; Zhang, Litong; Cheng, Laifei

2014-02-01

High-k dielectric materials are important as gate oxides in microelectronics and as potential dielectrics for capacitors. In order to enable computational discovery of novel high-k dielectric materials, we propose a fitness model (energy storage density) that includes the dielectric constant, bandgap, and intrinsic breakdown field. This model, used as a fitness function in conjunction with first-principles calculations and the global optimization evolutionary algorithm USPEX, efficiently leads to practically important results. We found a number of high-fitness structures of SiO2 and HfO2, some of which correspond to known phases and some of which are new. The results allow us to propose characteristics (genes) common to high-fitness structures--these are the coordination polyhedra and their degree of distortion. Our variable-composition searches in the HfO2-SiO2 system uncovered several high-fitness states. This hybrid algorithm opens up a new avenue for discovering novel high-k dielectrics with both fixed and variable compositions, and will speed up the process of materials discovery.

Graphene/Pentacene Barristor with Ion-Gel Gate Dielectric: Flexible Ambipolar Transistor with High Mobility and On/Off Ratio.

Science.gov (United States)

Oh, Gwangtaek; Kim, Jin-Soo; Jeon, Ji Hoon; Won, EunA; Son, Jong Wan; Lee, Duk Hyun; Kim, Cheol Kyeom; Jang, Jingon; Lee, Takhee; Park, Bae Ho

2015-07-28

High-quality channel layer is required for next-generation flexible electronic devices. Graphene is a good candidate due to its high carrier mobility and unique ambipolar transport characteristics but typically shows a low on/off ratio caused by gapless band structure. Popularly investigated organic semiconductors, such as pentacene, suffer from poor carrier mobility. Here, we propose a graphene/pentacene channel layer with high-k ion-gel gate dielectric. The graphene/pentacene device shows both high on/off ratio and carrier mobility as well as excellent mechanical flexibility. Most importantly, it reveals ambipolar behaviors and related negative differential resistance, which are controlled by external bias. Therefore, our graphene/pentacene barristor with ion-gel gate dielectric can offer various flexible device applications with high performances.

Interface Engineering and Gate Dielectric Engineering for High Performance Ge MOSFETs

Directory of Open Access Journals (Sweden)

Jiabao Sun

2015-01-01

Full Text Available In recent years, germanium has attracted intensive interests for its promising applications in the microelectronics industry. However, to achieve high performance Ge channel devices, several critical issues still have to be addressed. Amongst them, a high quality gate stack, that is, a low defect interface layer and a dielectric layer, is of crucial importance. In this work, we first review the existing methods of interface engineering and gate dielectric engineering and then in more detail we discuss and compare three promising approaches (i.e., plasma postoxidation, high pressure oxidation, and ozone postoxidation. It has been confirmed that these approaches all can significantly improve the overall performance of the metal-oxide-semiconductor field effect transistor (MOSFET device.

Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process

International Nuclear Information System (INIS)

Wang Yan-Rong; Yang Hong; Xu Hao; Wang Xiao-Lei; Luo Wei-Chun; Qi Lu-Wei; Zhang Shu-Xiang; Wang Wen-Wu; Yan Jiang; Zhu Hui-Long; Zhao Chao; Chen Da-Peng; Ye Tian-Chun

2015-01-01

A multi-deposition multi-annealing technique (MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device’s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown (TDDB) characteristics of positive channel metal oxide semiconductor (PMOS) under different MDMA process conditions, including the deposition/annealing (D and A) cycles, the D and A time, and the total annealing time. The results show that the increases of the number of D and A cycles (from 1 to 2) and D and A time (from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail (TTF) at 63.2% increases by about several times. However, too many D and A cycles (such as 4 cycles) make the equivalent oxide thickness (EOT) increase by about 1 Å and the TTF of PMOS worsen. Moreover, different D and A times and numbers of D and A cycles induce different breakdown mechanisms. (paper)

Hysteresis behaviour of low-voltage organic field-effect transistors employing high dielectric constant polymer gate dielectrics

International Nuclear Information System (INIS)

Kim, Se Hyun; Yun, Won Min; Kwon, Oh-Kwan; Hong, Kipyo; Yang, Chanwoo; Park, Chan Eon; Choi, Woon-Seop

2010-01-01

Here, we report on the fabrication of low-voltage-operating pentacene-based organic field-effect transistors (OFETs) that utilize crosslinked cyanoethylated poly(vinyl alcohol) (CR-V) gate dielectrics. The crosslinked CR-V-based OFET could be operated successfully at low voltages (below 4 V), but abnormal behaviour during device operation, such as uncertainty in the field-effect mobility (μ) and hysteresis, was induced by the slow polarization of moieties embedded in the gate dielectric (e.g. polar functionalities, ionic impurities, water and solvent molecules). In an effort to improve the stability of OFET operation, we measured the dependence of μ and hysteresis on dielectric thickness, CR-V crosslinking conditions and sweep rate of the gate bias. The influence of the CR-V surface properties on μ, hysteresis, and the structural and morphological features of the pentacene layer grown on the gate dielectric was characterized and compared with the properties of pentacene grown on a polystyrene surface.

Nano-CMOS gate dielectric engineering

CERN Document Server

Wong, Hei

2011-01-01

According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

Integration issues of high-k and metal gate into conventional CMOS technology

International Nuclear Information System (INIS)

Song, S.C.; Zhang, Z.; Huffman, C.; Bae, S.H.; Sim, J.H.; Kirsch, P.; Majhi, P.; Moumen, N.; Lee, B.H.

2006-01-01

Issues surrounding the integration of Hf-based high-k dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate stack process as well as optimization of other CMOS process steps enables robust CMOSFETs with a wide process latitude. HfO 2 of a 2 nm physical thickness shows complete suppression of transient charge trapping resulting from a significant reduction in film volume as well as kinetically suppressed crystallization. Metal thickness is also critical when optimizing physical stress effects and minimizing dopant diffusion. A high temperature anneal after source and drain implantation in a conventional CMOSFET process reduces the interface state density and improves electron mobility

Improved integration of ultra-thin high-k dielectrics in few-layer MoS2 FET by remote forming gas plasma pretreatment

Science.gov (United States)

Wang, Xiao; Zhang, Tian-Bao; Yang, Wen; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

2017-01-01

The effective and high-quality integration of high-k dielectrics on two-dimensional (2D) crystals is essential to the device structure engineering and performance improvement of field-effect transistor (FET) based on the 2D semiconductors. We report a 2D MoS2 transistor with ultra-thin Al2O3 top-gate dielectric (6.1 nm) and extremely low leakage current. Remote forming gas plasma pretreatment was carried out prior to the atomic layer deposition, providing nucleation sites with the physically adsorbed ions on the MoS2 surface. The top gate MoS2 FET exhibited excellent electrical performance, including high on/off current ratio over 109, subthreshold swing of 85 mV/decade and field-effect mobility of 45.03 cm2/V s. Top gate leakage current less than 0.08 pA/μm2 at 4 MV/cm has been obtained, which is the smallest compared with the reported top-gated MoS2 transistors. Such an optimized integration of high-k dielectric in 2D semiconductor FET with enhanced performance is very attractive, and it paves the way towards the realization of more advanced 2D nanoelectronic devices and integrated circuits.

Tungsten trioxide as high-{kappa} gate dielectric for highly transparent and temperature-stable zinc-oxide-based thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Lorenz, Michael; Wenckstern, Holger von; Grundmann, Marius [Universitaet Leipzig, Fakultaet fuer Physik und Geowissenschaften, Institut fuer Experimentelle Physik II, Linnestr. 5, 04103 Leipzig (Germany)

2012-07-01

We demonstrate metal-insulator-semiconductor field-effect transistors with high-{kappa}, room-temperature deposited, highly transparent tungsten trioxide (WO{sub 3}) as gate dielectric. The channel material consists of a zinc oxide (ZnO) thin-film. The transmittance and resistivity of WO{sub 3} films was tuned in order to obtain a highly transparent and insulating WO{sub 3} dielectric. The devices were processed by standard photolithography using lift-off technique. On top of the WO{sub 3} dielectric a highly transparent and conductive oxide consisting of ZnO: Al 3% wt. was deposited. The gate structure of the devices exhibits an average transmittance in the visible spectral range of 86%. The on/off-current ratio is larger than 10{sup 8} with off- and gate leakage-currents below 3 x 10{sup -8} A/cm{sup 2}. Due to the high relative permittivity of {epsilon}{sub r} {approx} 70, a gate voltage sweep of only 2 V is necessary to turn the transistor on and off with a minimum subthreshold swing of 80 mV/decade. The channel mobility of the transistors equals the Hall-effect mobility with a value of 5 cm{sup 2}/Vs. It is furthermore shown, that the devices are stable up to operating temperatures of at least 150 C.

Electronic States of High-k Oxides in Gate Stack Structures

Science.gov (United States)

Zhu, Chiyu

In this dissertation, in-situ X-ray and ultraviolet photoemission spectroscopy have been employed to study the interface chemistry and electronic structure of potential high-k gate stack materials. In these gate stack materials, HfO2 and La2O3 are selected as high-k dielectrics, VO2 and ZnO serve as potential channel layer materials. The gate stack structures have been prepared using a reactive electron beam system and a plasma enhanced atomic layer deposition system. Three interrelated issues represent the central themes of the research: 1) the interface band alignment, 2) candidate high-k materials, and 3) band bending, internal electric fields, and charge transfer. 1) The most highlighted issue is the band alignment of specific high-k structures. Band alignment relationships were deduced by analysis of XPS and UPS spectra for three different structures: a) HfO2/VO2/SiO2/Si, b) HfO 2-La2O3/ZnO/SiO2/Si, and c) HfO 2/VO2/ HfO2/SiO2/Si. The valence band offset of HfO2/VO2, ZnO/SiO2 and HfO 2/SiO2 are determined to be 3.4 +/- 0.1, 1.5 +/- 0.1, and 0.7 +/- 0.1 eV. The valence band offset between HfO2-La2O3 and ZnO was almost negligible. Two band alignment models, the electron affinity model and the charge neutrality level model, are discussed. The results show the charge neutrality model is preferred to describe these structures. 2) High-k candidate materials were studied through comparison of pure Hf oxide, pure La oxide, and alloyed Hf-La oxide films. An issue with the application of pure HfO2 is crystallization which may increase the leakage current in gate stack structures. An issue with the application of pure La2O3 is the presence of carbon contamination in the film. Our study shows that the alloyed Hf-La oxide films exhibit an amorphous structure along with reduced carbon contamination. 3) Band bending and internal electric fields in the gate stack structure were observed by XPS and UPS and indicate the charge transfer during the growth and process. The oxygen

Self-aligned top-gate InGaZnO thin film transistors using SiO{sub 2}/Al{sub 2}O{sub 3} stack gate dielectric

Energy Technology Data Exchange (ETDEWEB)

Chen, Rongsheng; Zhou, Wei; Zhang, Meng; Wong, Man; Kwok, Hoi Sing

2013-12-02

Self-aligned top-gate amorphous indium–gallium–zinc oxide (a-IGZO) thin film transistors (TFTs) utilizing SiO{sub 2}/Al{sub 2}O{sub 3} stack thin films as gate dielectric are developed in this paper. Due to high quality of the high-k Al{sub 2}O{sub 3} and good interface between active layer and gate dielectric, the resulting a-IGZO TFT exhibits good electrical performance including field-effect mobility of 9 cm{sup 2}/Vs, threshold voltage of 2.2 V, subthreshold swing of 0.2 V/decade, and on/off current ratio of 1 × 10{sup 7}. With scaling down of the channel length, good characteristics are also obtained with a small shift of the threshold voltage and no degradation of subthreshold swing. - Highlights: • Self-aligned top-gate indium–gallium–zinc oxide thin-film transistor is proposed. • SiO{sub 2}/Al{sub 2}O{sub 3} stack gate dielectric is proposed. • The source/drain areas are hydrogen-doped by CHF{sub 3} plasma. • The devices show good electrical performance and scaling down behavior.

Comparative studies of AlGaN/GaN MOS-HEMTs with stacked gate dielectrics by the mixed thin film growth method

International Nuclear Information System (INIS)

Chou, Bo-Yi; Hsu, Wei-Chou; Liu, Han-Yin; Ho, Chiu-Sheng; Lee, Ching-Sung

2013-01-01

This paper reports Al 0.27 Ga 0.73 N/GaN metal–oxide–semiconductor high electron mobility transistors (MOS-HEMTs) with stacked Al 2 O 3 /HfO 2 gate dielectrics by using hydrogen peroxideoxidation/sputtering techniques. The Al 2 O 3 employed as a gate dielectric and surface passivation layer effectively suppresses the gate leakage current, improves RF drain current collapse and exhibits good thermal stability. Moreover, by stacking the good insulating high-k HfO 2 dielectric further suppresses the gate leakage, enhances the dielectric breakdown field and power-added efficiency, and decreases the equivalent oxide thickness. The present MOS-HEMT design has demonstrated superior improvements of 10.1% (16.4%) in the maximum drain–source current (I DS,max ), 11.4% (22.5%) in the gate voltage swing and 12.5%/14.4% (21.9%/22.3%) in the two-terminal gate–drain breakdown/turn-on voltages (BV GD /V ON ), and the present design also demonstrates the lowest gate leakage current and best thermal stability characteristics as compared to two reference MOS-HEMTs with a single Al 2 O 3 /(HfO 2 ) dielectric layer of the same physical thickness. (invited paper)

SEMICONDUCTOR DEVICES: Structural and electrical characteristics of lanthanum oxide gate dielectric film on GaAs pHEMT technology

Science.gov (United States)

Chia-Song, Wu; Hsing-Chung, Liu

2009-11-01

This paper investigates the feasibility of using a lanthanum oxide thin film (La2O3) with a high dielectric constant as a gate dielectric on GaAs pHEMTs to reduce gate leakage current and improve the gate to drain breakdown voltage relative to the conventional GaAs pHEMT. An E/D mode pHEMT in a single chip was realized by selecting the appropriate La2O3 thickness. The thin La2O3 film was characterized: its chemical composition and crystalline structure were determined by X-ray photoelectron spectroscopy and X-ray diffraction, respectively. La2O3 exhibited good thermal stability after post-deposition annealing at 200, 400 and 600 °C because of its high binding-energy (835.6 eV). Experimental results clearly demonstrated that the La2O3 thin film was thermally stable. The DC and RF characteristics of Pt/La2O3/Ti/Au gate and conventional Pt/Ti/Au gate pHEMTs were examined. The measurements indicated that the transistor with the Pt/La2O3/Ti/Au gate had a higher breakdown voltage and lower gate leakage current. Accordingly, the La2O3 thin film is a potential high-k material for use as a gate dielectric to improve electrical performance and the thermal effect in high-power applications.

Temperature Effects on a-IGZO Thin Film Transistors Using HfO2 Gate Dielectric Material

Directory of Open Access Journals (Sweden)

Yu-Hsien Lin

2014-01-01

Full Text Available This study investigated the temperature effect on amorphous indium gallium zinc oxide (a-IGZO thin film transistors (TFTs using hafnium oxide (HfO2 gate dielectric material. HfO2 is an attractive candidate as a high-κ dielectric material for gate oxide because it has great potential to exhibit superior electrical properties with a high drive current. In the process of integrating the gate dielectric and IGZO thin film, postannealing treatment is an essential process for completing the chemical reaction of the IGZO thin film and enhancing the gate oxide quality to adjust the electrical characteristics of the TFTs. However, the hafnium atom diffused the IGZO thin film, causing interface roughness because of the stability of the HfO2 dielectric thin film during high-temperature annealing. In this study, the annealing temperature was optimized at 200°C for a HfO2 gate dielectric TFT exhibiting high mobility, a high ION/IOFF ratio, low IOFF current, and excellent subthreshold swing (SS.

In situ atomic layer nitridation on the top and down regions of the amorphous and crystalline high-K gate dielectrics

Energy Technology Data Exchange (ETDEWEB)

Tsai, Meng-Chen [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China); Lee, Min-Hung [Institute of Electro-Optical Science and Technology, National Taiwan Normal University, Taipei 11677, Taiwan (China); Kuo, Chin-Lung; Lin, Hsin-Chih [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China); Chen, Miin-Jang, E-mail: mjchen@ntu.edu.tw [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China)

2016-11-30

Highlights: • The structural and electrical characteristics of the ZrO{sub 2} high-K dielectrics, treated with the in situ atomic layer doping of nitrogen into the top and down regions (top and down nitridation, TN and DN, respectively), were investigated. • The amorphous DN sample has a lower leakage current density (J{sub g}) than the amorphous TN sample, attributed to the formation of SiO{sub x}N{sub y} in the interfacial layer (IL). • The crystalline TN sample exhibited a lower CET and a similar J{sub g} as compared with the crystalline DN sample, which can be ascribed to the suppression of IL regrowth. • The crystalline ZrO{sub 2} with in situ atomic layer doping of nitrogen into the top region exhibited superior scaling limit, electrical characteristics, and reliability. - Abstract: Amorphous and crystalline ZrO{sub 2} gate dielectrics treated with in situ atomic layer nitridation on the top and down regions (top and down nitridation, abbreviated as TN and DN) were investigated. In a comparison between the as-deposited amorphous DN and TN samples, the DN sample has a lower leakage current density (J{sub g}) of ∼7 × 10{sup −4} A/cm{sup 2} with a similar capacitance equivalent thickness (CET) of ∼1.53 nm, attributed to the formation of SiO{sub x}N{sub y} in the interfacial layer (IL). The post-metallization annealing (PMA) leads to the transformation of ZrO{sub 2} from the amorphous to the crystalline tetragonal/cubic phase, resulting in an increment of the dielectric constant. The PMA-treated TN sample exhibits a lower CET of 1.22 nm along with a similar J{sub g} of ∼1.4 × 10{sup −5} A/cm{sup 2} as compared with the PMA-treated DN sample, which can be ascribed to the suppression of IL regrowth. The result reveals that the nitrogen engineering in the top and down regions has a significant impact on the electrical characteristics of amorphous and crystalline ZrO{sub 2} gate dielectrics, and the nitrogen incorporation at the top of crystalline

Chemical vapor deposited monolayer MoS2 top-gate MOSFET with atomic-layer-deposited ZrO2 as gate dielectric

Science.gov (United States)

Hu, Yaoqiao; Jiang, Huaxing; Lau, Kei May; Li, Qiang

2018-04-01

For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec-1, and a field-effect electron mobility of 12.1 cm2 V-1 s-1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm-1 at V DS = 5 V. The gate leakage current is below 10-2 A cm-2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm-1 is obtained. Gate hysteresis and frequency-dependent capacitance-voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ˜3 × 1012 cm-2 eV-1.

Medium band gap polymer based solution-processed high-κ composite gate dielectrics for ambipolar OFET

Science.gov (United States)

Canımkurbey, Betül; Unay, Hande; Çakırlar, Çiğdem; Büyükköse, Serkan; Çırpan, Ali; Berber, Savas; Altürk Parlak, Elif

2018-03-01

The authors present a novel ambipolar organic filed-effect transistors (OFETs) composed of a hybrid dielectric thin film of Ta2O5:PMMA nanocomposite material, and solution processed poly(selenophene, benzotriazole and dialkoxy substituted [1,2-b:4, 5-b‧] dithiophene (P-SBTBDT)-based organic semiconducting material as the active layer of the device. We find that the Ta2O5:PMMA insulator shows n-type conduction character, and its combination with the p-type P-SBTBDT organic semiconductor leads to an ambipolar OFET device. Top-gated OFETs were fabricated on glass substrate consisting of interdigitated ITO electrodes. P-SBTBDT-based material was spin coated on the interdigitated ITO electrodes. Subsequently, a solution processed Ta2O5:PMMA nanocomposite material was spin coated, thereby creating the gate dielectric layer. Finally, as a gate metal, an aluminum layer was deposited by thermal evaporation. The fabricated OFETs exhibited an ambipolar performance with good air-stability, high field-induced current and relatively high electron and hole mobilities although Ta2O5:PMMA nanocomposite films have slightly higher leakage current compared to the pure Ta2O5 films. Dielectric properties of the devices with different ratios of Ta2O5:PMMA were also investigated. The dielectric constant varied between 3.6 and 5.3 at 100 Hz, depending on the Ta2O5:PMMA ratio.

Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high- k metal gate NMOSFET with kMC TDDB simulations

International Nuclear Information System (INIS)

Xu Hao; Yang Hong; Luo Wei-Chun; Xu Ye-Feng; Wang Yan-Rong; Tang Bo; Wang Wen-Wu; Qi Lu-Wei; Li Jun-Feng; Yan Jiang; Zhu Hui-Long; Zhao Chao; Chen Da-Peng; Ye Tian-Chun

2016-01-01

The thickness effect of the TiN capping layer on the time dependent dielectric breakdown (TDDB) characteristic of ultra-thin EOT high- k metal gate NMOSFET is investigated in this paper. Based on experimental results, it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer. From the charge pumping measurement and secondary ion mass spectroscopy (SIMS) analysis, it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density. In addition, the influences of interface and bulk trap density ratio N it / N ot are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo (kMC) method. The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses. (paper)

Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

International Nuclear Information System (INIS)

Ghosh, Bahniman; Mondal, Partha; Akram, M. W.; Bal, Punyasloka; Salimath, Akshay Kumar

2014-01-01

We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel. These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n–p–n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability. (semiconductor devices)

Growth Related Carrier Mobility Enhancement of Pentacene Thin-Film Transistors with High-k Oxide Gate Dielectric

International Nuclear Information System (INIS)

Ai-Fang, Yu; Qiong, Qi; Peng, Jiang; Chao, Jiang

2009-01-01

Carrier mobility enhancement from 0.09 to 0.59 cm 2 /Vs is achieved for pentacene-based thin-film transistors (TFTs) by modifying the HfO 2 gate dielectric with a polystyrene (PS) thin film. The improvement of the transistor's performance is found to be strongly related to the initial film morphologies of pentacene on the dielectrics. In contrast to the three-dimensional island-like growth mode on the HfO 2 surface, the Stranski-Krastanov growth mode on the smooth and nonpolar PS/HfO 2 surface is believed to be the origin of the excellent carrier mobility of the TFTs. A large well-connected first monolayer with fewer boundaries is formed via the Stranski–Krastanov growth mode, which facilitates a charge transport parallel to the substrate and promotes higher carrier mobility. (cross-disciplinary physics and related areas of science and technology)

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

Science.gov (United States)

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J

2016-06-09

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

Temperature Effects on a-IGZO Thin Film Transistors Using HfO2 Gate Dielectric Material

OpenAIRE

Lin, Yu-Hsien; Chou, Jay-Chi

2014-01-01

This study investigated the temperature effect on amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) using hafnium oxide (HfO2) gate dielectric material. HfO2 is an attractive candidate as a high-κ dielectric material for gate oxide because it has great potential to exhibit superior electrical properties with a high drive current. In the process of integrating the gate dielectric and IGZO thin film, postannealing treatment is an essential process for completing the chem...

A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

Science.gov (United States)

Wallace, Robert M.

2001-03-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

Science.gov (United States)

Choi, Woo Young; Lee, Hyun Kook

2016-01-01

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric.

Science.gov (United States)

Fujii, Mami N; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

2015-12-18

The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices.

High-Mobility 6,13-Bis(triisopropylsilylethynyl) Pentacene Transistors Using Solution-Processed Polysilsesquioxane Gate Dielectric Layers.

Science.gov (United States)

Matsuda, Yu; Nakahara, Yoshio; Michiura, Daisuke; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) is a low-temperature curable polymer that is compatible with low-cost plastic substrates. We cured PSQ gate dielectric layers by irradiation with ultraviolet light at ~60 °C, and used them for 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) thin film transistors (TFTs). The fabricated TFTs have shown the maximum and average hole mobility of 1.3 and 0.78 ± 0.3 cm2V-1s-1, which are comparable to those of the previously reported transistors using single-crystalline TIPS-pentacene micro-ribbons for their active layers and thermally oxidized SiO2 for their gate dielectric layers. Itis therefore demonstrated that PSQ is a promising polymer gate dielectric material for low-cost organic TFTs.

Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks

International Nuclear Information System (INIS)

Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Liu, Xi-Wen; Chang, Ting-Chang; Chen, Ching-En; Ho, Szu-Han; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Lu, Ching-Sen

2014-01-01

This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO 2 interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks.

Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

Science.gov (United States)

Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

2018-01-01

Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

Polaron-electron assisted giant dielectric dispersion in SrZrO{sub 3} high-k dielectric

Energy Technology Data Exchange (ETDEWEB)

Borkar, Hitesh; Barvat, Arun; Pal, Prabir; Kumar, Ashok, E-mail: ashok553@nplindia.org [CSIR-National Physical Laboratory, Dr. K. S. Krishnan Marg, New Delhi 110012 (India); Academy of Scientific and Innovative Research (AcSIR), CSIR-National Physical Laboratory (CSIR-NPL) Campus, Dr. K S Krishnan Marg, New Delhi 110012 (India); Shukla, A. K. [CSIR-National Physical Laboratory, Dr. K. S. Krishnan Marg, New Delhi 110012 (India); Pulikkotil, J. J. [CSIR-National Physical Laboratory, Dr. K. S. Krishnan Marg, New Delhi 110012 (India); Academy of Scientific and Innovative Research (AcSIR), CSIR-National Physical Laboratory (CSIR-NPL) Campus, Dr. K S Krishnan Marg, New Delhi 110012 (India); Computation and Networking Facility, CSIR-National Physical Laboratory, New Delhi 110012 (India)

2016-06-07

The SrZrO{sub 3} is a well known high-k dielectric constant (∼22) and high optical bandgap (∼5.8 eV) material and one of the potential candidates for future generation nanoelectronic logic elements (8 nm node technology) beyond silicon. Its dielectric behavior is fairly robust and frequency independent till 470 K; however, it suffers a strong small-polaron based electronic phase transition (T{sub e}) linking 650 to 750 K. The impedance spectroscopy measurements revealed the presence of conducting grains and grain boundaries at elevated temperature which provide energetic mobile charge carriers with activation energy in the range of 0.7 to 1.2 eV supporting the oxygen ions and proton conduction. X-ray photoemission spectroscopy measurements suggest the presence of weak non-stoichiometric O{sup 2−} anions and hydroxyl species bound to different sites at the surface and bulk. These thermally activated charge carriers at elevated temperature significantly contribute to the polaronic based dielectric anomaly and conductivity. Our dielectric anomaly supports pseudo phase transition due to high degree of change in ZrO{sub 6} octahedral angle in the temperature range of 650–750 K, where electron density and phonon vibration affect the dielectric and conductivity properties.

Atomic layer deposition of crystalline SrHfO3 directly on Ge (001) for high-k dielectric applications

International Nuclear Information System (INIS)

McDaniel, Martin D.; Ngo, Thong Q.; Ekerdt, John G.; Hu, Chengqing; Jiang, Aiting; Yu, Edward T.; Lu, Sirong; Smith, David J.; Posadas, Agham; Demkov, Alexander A.

2015-01-01

The current work explores the crystalline perovskite oxide, strontium hafnate, as a potential high-k gate dielectric for Ge-based transistors. SrHfO 3 (SHO) is grown directly on Ge by atomic layer deposition and becomes crystalline with epitaxial registry after post-deposition vacuum annealing at ∼700 °C for 5 min. The 2 × 1 reconstructed, clean Ge (001) surface is a necessary template to achieve crystalline films upon annealing. The SHO films exhibit excellent crystallinity, as shown by x-ray diffraction and transmission electron microscopy. The SHO films have favorable electronic properties for consideration as a high-k gate dielectric on Ge, with satisfactory band offsets (>2 eV), low leakage current (<10 −5 A/cm 2 at an applied field of 1 MV/cm) at an equivalent oxide thickness of 1 nm, and a reasonable dielectric constant (k ∼ 18). The interface trap density (D it ) is estimated to be as low as ∼2 × 10 12  cm −2  eV −1 under the current growth and anneal conditions. Some interfacial reaction is observed between SHO and Ge at temperatures above ∼650 °C, which may contribute to increased D it value. This study confirms the potential for crystalline oxides grown directly on Ge by atomic layer deposition for advanced electronic applications

Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs

Science.gov (United States)

Dentoni Litta, E.; Hellström, P.-E.; Östling, M.

2015-06-01

High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.

High carrier mobility of CoPc wires based field-effect transistors using bi-layer gate dielectric

Directory of Open Access Journals (Sweden)

Murali Gedda

2013-11-01

Full Text Available Polyvinyl alcohol (PVA and anodized Al2O3 layers were used as bi-layer gate for the fabrication of cobalt phthalocyanine (CoPc wire base field-effect transistors (OFETs. CoPc wires were grown on SiO2 surfaces by organic vapor phase deposition method. These devices exhibit a field-effect carrier mobility (μEF value of 1.11 cm2/Vs. The high carrier mobility for CoPc molecules is attributed to the better capacitive coupling between the channel of CoPc wires and the gate through organic-inorganic dielectric layer. Our measurements also demonstrated the way to determine the thicknesses of the dielectric layers for a better process condition of OFETs.

Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

International Nuclear Information System (INIS)

Besleaga, C.; Stan, G.E.; Pintilie, I.; Barquinha, P.; Fortunato, E.; Martins, R.

2016-01-01

Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

Energy Technology Data Exchange (ETDEWEB)

Besleaga, C.; Stan, G.E.; Pintilie, I. [National Institute of Materials Physics, 405A Atomistilor, 077125 Magurele-Ilfov (Romania); Barquinha, P.; Fortunato, E. [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal); Martins, R., E-mail: rm@uninova.pt [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal)

2016-08-30

Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

Ternary rare-earth based alternative gate-dielectrics for future integration in MOSFETs

Energy Technology Data Exchange (ETDEWEB)

Schubert, Juergen; Lopes, Joao Marcelo; Durgun Oezben, Eylem; Luptak, Roman; Lenk, Steffi; Zander, Willi; Roeckerath, Martin [IBN 1-IT, Forschungszentrum Juelich, 52425 Juelich (Germany)

2009-07-01

The dielectric SiO{sub 2} has been the key to the tremendous improvements in Si-based metal-oxide-semiconductor (MOS) device performance over the past four decades. It has, however, reached its limit in terms of scaling since it exhibits a leakage current density higher than 1 A/cm{sup 2} and does not retain its intrinsic physical properties at thicknesses below 1.5 nm. In order to overcome these problems and keep Moore's law ongoing, the use of higher dielectric constant (k) gate oxides has been suggested. These high-k materials must satisfy numerous requirements such as the high k, low leakage currents, suitable band gap und offsets to silicon. Rare-earth based dielectrics are promising materials which fulfill these needs. We will review the properties of REScO{sub 3} (RE = La, Dy, Gd, Sm, Tb) and LaLuO{sub 3} thin films, grown with pulsed laser deposition, e-gun evaporation or molecular beam deposition, integrated in capacitors and transistors. A k > 20 for the REScO{sub 3} (RE = Dy, Gd) and around 30 for (RE = La, Sm, Tb) and LaLuO{sub 3} are obtained. Transistors prepared on SOI and sSOI show mobility values up to 380 cm{sup 2}/Vs on sSOI, which are comparable to such prepared with HfO{sub 2}.

Atomic layer deposition of crystalline SrHfO{sub 3} directly on Ge (001) for high-k dielectric applications

Energy Technology Data Exchange (ETDEWEB)

McDaniel, Martin D.; Ngo, Thong Q.; Ekerdt, John G., E-mail: ekerdt@utexas.edu [Department of Chemical Engineering, The University of Texas at Austin, Austin, Texas 78712 (United States); Hu, Chengqing; Jiang, Aiting; Yu, Edward T. [Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States); Lu, Sirong; Smith, David J. [Department of Physics, Arizona State University, Tempe, Arizona 85287 (United States); Posadas, Agham; Demkov, Alexander A. [Department of Physics, The University of Texas at Austin, Austin, Texas 78712 (United States)

2015-02-07

The current work explores the crystalline perovskite oxide, strontium hafnate, as a potential high-k gate dielectric for Ge-based transistors. SrHfO{sub 3} (SHO) is grown directly on Ge by atomic layer deposition and becomes crystalline with epitaxial registry after post-deposition vacuum annealing at ∼700 °C for 5 min. The 2 × 1 reconstructed, clean Ge (001) surface is a necessary template to achieve crystalline films upon annealing. The SHO films exhibit excellent crystallinity, as shown by x-ray diffraction and transmission electron microscopy. The SHO films have favorable electronic properties for consideration as a high-k gate dielectric on Ge, with satisfactory band offsets (>2 eV), low leakage current (<10{sup −5} A/cm{sup 2} at an applied field of 1 MV/cm) at an equivalent oxide thickness of 1 nm, and a reasonable dielectric constant (k ∼ 18). The interface trap density (D{sub it}) is estimated to be as low as ∼2 × 10{sup 12 }cm{sup −2 }eV{sup −1} under the current growth and anneal conditions. Some interfacial reaction is observed between SHO and Ge at temperatures above ∼650 °C, which may contribute to increased D{sub it} value. This study confirms the potential for crystalline oxides grown directly on Ge by atomic layer deposition for advanced electronic applications.

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Science.gov (United States)

Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

2018-06-01

The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

Simulation of dual-gate SOI MOSFET with different dielectric layers

Science.gov (United States)

Yadav, Jyoti; Chaudhary, R.; Mukhiya, R.; Sharma, R.; Khanna, V. K.

2016-04-01

The paper presents the process design and simulation of silicon-on-insulator (SOI)-based dual-gate metal oxide field-effect transistor (DG-MOSFET) stacked with different dielectric layers on the top of gate oxide. A detailed 2D process simulation of SOI-MOSFETs and its electrical characterization has been done using SILVACO® TCAD tool. A variation in transconductance was observed with different dielectric layers, AlN-gate MOSFET having the highest tranconductance value as compared to other three dielectric layers (SiO2, Si3N4 and Al2O3).

GaN MOSHEMT employing HfO2 as a gate dielectric with partially etched barrier

Science.gov (United States)

Han, Kefeng; Zhu, Lin

2017-09-01

In order to suppress the gate leakage current of a GaN high electron mobility transistor (GaN HEMT), a GaN metal-oxide-semiconductor high electron mobility transistor (MOSHEMT) is proposed, in which a metal-oxide-semiconductor gate with high-dielectric-constant HfO2 as an insulating dielectric is employed to replace the traditional GaN HEMT Schottky gate. A 0.5 μm gate length GaN MOSHEMT was fabricated based on the proposed structure, the {{{Al}}}0.28{{{Ga}}}0.72{{N}} barrier layer is partially etched to produce a higher transconductance without deteriorating the transport characteristics of the two-dimensional electron gas in the channel, the gate dielectric is HfO2 deposited by atomic layer deposition. Current-voltage characteristics and radio frequency characteristics are obtained after device preparation, the maximum current density of the device is 900 mA mm-1, the source-drain breakdown voltage is 75 V, gate current is significantly suppressed and the forward gate voltage swing range is about ten times higher than traditional GaN HEMTs, the GaN MOSHEMT also demonstrates radio frequency characteristics comparable to traditional GaN HEMTs with the same gate length.

Direct deposition of aluminum oxide gate dielectric on graphene channel using nitrogen plasma treatment

International Nuclear Information System (INIS)

Lim, Taekyung; Kim, Dongchool; Ju, Sanghyun

2013-01-01

Deposition of high-quality dielectric on a graphene channel is an essential technology to overcome structural constraints for the development of nano-electronic devices. In this study, we investigated a method for directly depositing aluminum oxide (Al 2 O 3 ) on a graphene channel through nitrogen plasma treatment. The deposited Al 2 O 3 thin film on graphene demonstrated excellent dielectric properties with negligible charge trapping and de-trapping in the gate insulator. A top-gate-structural graphene transistor was fabricated using Al 2 O 3 as the gate dielectric with nitrogen plasma treatment on graphene channel region, and exhibited p-type transistor characteristics

Energy-loss return gate via liquid dielectric polarization.

Science.gov (United States)

Kim, Taehun; Yong, Hyungseok; Kim, Banseok; Kim, Dongseob; Choi, Dukhyun; Park, Yong Tae; Lee, Sangmin

2018-04-12

There has been much research on renewable energy-harvesting techniques. However, owing to increasing energy demands, significant energy-related issues remain to be solved. Efforts aimed at reducing the amount of energy loss in electric/electronic systems are essential for reducing energy consumption and protecting the environment. Here, we design an energy-loss return gate system that reduces energy loss from electric/electronic systems by utilizing the polarization of liquid dielectrics. The use of a liquid dielectric material in the energy-loss return gate generates electrostatic potential energy while reducing the dielectric loss of the electric/electronic system. Hence, an energy-loss return gate can make breakthrough impacts possible by amplifying energy-harvesting efficiency, lowering the power consumption of electronics, and storing the returned energy. Our study indicates the potential for enhancing energy-harvesting technologies for electric/electronics systems, while increasing the widespread development of these systems.

Combining a multi deposition multi annealing technique with a scavenging (Ti) to improve the high-k/metal gate stack performance for a gate-last process

International Nuclear Information System (INIS)

Zhang ShuXiang; Yang Hong; Tang Bo; Tang Zhaoyun; Xu Yefeng; Xu Jing; Yan Jiang

2014-01-01

ALD HfO 2 films fabricated by a novel multi deposition multi annealing (MDMA) technique are investigated, we have included samples both with and without a Ti scavenging layer. As compared to the reference gate stack treated by conventional one-time deposition and annealing (D and A), devices receiving MDMA show a significant reduction in leakage current. Meanwhile, EOT growth is effectively controlled by the Ti scavenging layer. This improvement strongly correlates with the cycle number of D and A (while keeping the total annealing time and total dielectrics thickness the same). Transmission electron microscope and energy-dispersive X-ray spectroscopy analysis suggests that oxygen incorporation into both the high-k film and the interfacial layer is likely to be responsible for the improvement of the device. This novel MDMA is promising for the development of gate stack technology in a gate last integration scheme. (semiconductor technology)

High-Sensitivity, Highly Transparent, Gel-Gated MoS2 Phototransistor on Biodegradable Nanopaper

KAUST Repository

Zhang, Qing

2016-06-21

Transition metal dichalcogenides hold great promise for a variety of novel electrical, optical and mechanical devices and applications. Among them, molybdenum disulphide (MoS2) is gaining increasing attention as the gate dielectric and semiconductive channel for high-perfomance field effect transistors. Here we report on the first MoS2 phototransistor built on flexible, transparent and biodegradable substrate with electrolyte gate dielectric. We have carried out systematic studies on its electrical and optoelectronic properties. The MoS2 phototransistor exhibited excellent photo responsivity of ~1.5 kA/W, about two times higher compared to typical back-gated devices reported in previous studies. The device is highly transparent at the same time with an average optical transmittance of 82%. Successful fabrication of phototransistors on flexible cellulose nanopaper with excellent performance and transparency suggests that it is feasible to achieve an ecofriendly, biodegradable phototransistor with great photoresponsivity, broad spectral range and durable flexibility.

High-Sensitivity, Highly Transparent, Gel-Gated MoS2 Phototransistor on Biodegradable Nanopaper

KAUST Repository

Zhang, Qing; Bao, Wenzhong; Gong, Amy; Gong, Tao; Ma, Dakang; Wan, Jiayu; Dai, Jiaqi; Munday, J; He, Jr-Hau; Hu, Liangbing; Zhang, Daihua

2016-01-01

Transition metal dichalcogenides hold great promise for a variety of novel electrical, optical and mechanical devices and applications. Among them, molybdenum disulphide (MoS2) is gaining increasing attention as the gate dielectric and semiconductive channel for high-perfomance field effect transistors. Here we report on the first MoS2 phototransistor built on flexible, transparent and biodegradable substrate with electrolyte gate dielectric. We have carried out systematic studies on its electrical and optoelectronic properties. The MoS2 phototransistor exhibited excellent photo responsivity of ~1.5 kA/W, about two times higher compared to typical back-gated devices reported in previous studies. The device is highly transparent at the same time with an average optical transmittance of 82%. Successful fabrication of phototransistors on flexible cellulose nanopaper with excellent performance and transparency suggests that it is feasible to achieve an ecofriendly, biodegradable phototransistor with great photoresponsivity, broad spectral range and durable flexibility.

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

Science.gov (United States)

Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

2013-06-01

In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

Thermal response of Ru electrodes in contact with SiO2 and Hf-based high-k gate dielectrics

International Nuclear Information System (INIS)

Wen, H.-C.; Lysaght, P.; Alshareef, H.N.; Huffman, C.; Harris, H.R.; Choi, K.; Senzaki, Y.; Luan, H.; Majhi, P.; Lee, B.H.; Campin, M. J.; Foran, B.; Lian, G.D.; Kwong, D.-L.

2005-01-01

A systematic experimental evaluation of the thermal stability of Ru metal gate electrodes in direct contact with SiO 2 and Hf-based dielectric layers was performed and correlated with electrical device measurements. The distinctly different interfacial reactions in the Ru/SiO 2 , Ru/HfO 2 , and Ru/HfSiO x film systems were observed through cross-sectional high-resolution transmission electron microscopy, high angle annular dark field scanning transmission electron microscopy with electron-energy-loss spectra, and energy dispersive x-ray spectra analysis. Ru interacted with SiO 2 , but remained stable on HfO 2 at 1000 deg. C. The onset of Ru/SiO 2 interfacial interactions is identified via silicon substrate pitting possibly from Ru diffusion into the dielectric in samples exposed to a 900 deg. C/10-s anneal. The dependence of capacitor device degradation with decreasing SiO 2 thickness suggests Ru diffuses through SiO 2 , followed by an abrupt, rapid, nonuniform interaction of ruthenium silicide as Ru contacts the Si substrate. Local interdiffusion detected on Ru/HfSiO x samples may be due to phase separation of HfSiO x into HfO 2 grains within a SiO 2 matrix, suggesting that SiO 2 provides a diffusion pathway for Ru. Detailed evidence consistent with a dual reaction mechanism for the Ru/SiO 2 system at 1000 deg. C is presented

Evaluation of the effects of thermal annealing temperature and high-k dielectrics on amorphous InGaZnO thin films by using pseudo-MOS transistors

International Nuclear Information System (INIS)

Lee, Se-Won; Cho, Won-Ju

2012-01-01

The effects of annealing temperatures and high-k gate dielectric materials on the amorphous In-Ga-Zn-O thin-film transistors (a-IGZO TFTs) were investigated using pseudo-metal-oxide semiconductor transistors (Ψ-MOSFETs), a method without conventional source/drain (S/D) layer deposition. Annealing of the a-IGZO film was carried out at 150 - 900 .deg. C in a N 2 ambient for 30 min. As the annealing temperature was increased, the electrical characteristics of Ψ-MOSFETs on a-IGZO were drastically improved. However, when the annealing temperature exceeded 700 .deg. C, a deterioration of the MOS parameters was observed, including a shift of the threshold voltage (V th ) in a negative direction, an increase in the subthreshold slope (SS) and hysteresis, a decrease in the field effect mobility (μ FE ), an increase in the trap density (N t ), and a decrease in the on/off ratio. Meanwhile, the high-k gate dielectrics enhanced the performance of a-IGZO Ψ-MOSFETs. The ZrO 2 gate dielectrics particularly exhibited excellent characteristics in terms of SS (128 mV/dec), μ FE (10.2 cm -2 /V·s), N t (1.1 x 10 12 cm -2 ), and on/off ratio (5.3 x 10 6 ). Accordingly, the Ψ-MOSFET structure is a useful method for rapid evaluation of the effects of the process and the material on a-IGZO TFTs without a conventional S/D layer deposition.

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors.

Science.gov (United States)

Chen, Fa-Hsyang; Her, Jim-Long; Shao, Yu-Hsuan; Matsuda, Yasuhiro H; Pan, Tung-Ming

2013-01-08

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric.

Interface engineering and reliability characteristics of hafnium dioxide with poly silicon gate and dual metal (ruthenium-tantalum alloy, ruthenium) gate electrode for beyond 65 nm technology

Science.gov (United States)

Kim, Young-Hee

Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is

Effect of nanocomposite gate-dielectric properties on pentacene microstructure and field-effect transistor characteristics.

Science.gov (United States)

Lee, Wen-Hsi; Wang, Chun-Chieh

2010-02-01

In this study, the effect of surface energy and roughness of the nanocomposite gate dielectric on pentacene morphology and electrical properties of pentacene OTFT are reported. Nanoparticles TiO2 were added in the polyimide matrix to form a nanocomposite which has a significantly different surface characteristic from polyimide, leading to a discrepancy in the structural properties of pentacene growth. A growth mode of pentacene deposited on the nanocomposite is proposed to explain successfully the effect of surface properties of nanocomposite gate dielectric such as surface energy and roughness on the pentacene morphology and electrical properties of OTFT. To obtain the lower surface energy and smoother surface of nanocomposite gate dielectric that is responsible for the desired crystalline, microstructure of pentacene and electrical properties of device, a bottom contact OTFT-pentacene deposited on the double-layer nanocomposite gate dielectric consisting of top smoothing layer of the neat polyimide and bottom layer of (PI+ nano-TiO2 particles) nanocomposite has been successfully demonstrated to exhibit very promising performance including high current on to off ratio of about 6 x 10(5), threshold voltage of -10 V and moderately high filed mobility of 0.15 cm2V(-1)s(-1).

Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11 000 cm2/V·s

KAUST Repository

Smith, Casey; Qaisi, Ramy M.; Liu, Zhihong; Yu, Qingkai; Hussain, Muhammad Mustafa

2013-01-01

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11 000 cm 2/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low t ox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance. © 2013 American Chemical Society.

Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11 000 cm2/V·s

KAUST Repository

Smith, Casey

2013-07-23

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11 000 cm 2/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low t ox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance. © 2013 American Chemical Society.

Analysis of OFF-state and ON-state performance in a silicon-on-insulator power MOSFET with a low-k dielectric trench

International Nuclear Information System (INIS)

Wang Zhigang; Zhang Bo; Li Zhaoji

2013-01-01

A novel silicon-on-insulator (SOI) MOSFET with a variable low-k dielectric trench (LDT MOSFET) is proposed and its performance and characteristics are investigated. The trench in the drift region between drain and source is filled with low-k dielectric to extend the effective drift region. At OFF state, the low-k dielectric trench (LDT) can sustain high voltage and enhance the dielectric field due to the accumulation of ionized charges. At the same time, the vertical dielectric field in the buried oxide can also be enhanced by these ionized charges. Additionally, ON-state analysis of LDT MOSFET demonstrates excellent forward characteristics, such as low gate-to-drain charge density ( 2 ) and a robust safe operating area (0–84 V). (semiconductor devices)

Pulsed laser deposition of oxide gate dielectrics for pentacene organic field-effect transistors

International Nuclear Information System (INIS)

Yaginuma, S.; Yamaguchi, J.; Itaka, K.; Koinuma, H.

2005-01-01

We have fabricated Al 2 O 3 , LaAlO 3 (LAO), CaHfO 3 (CHO) and CaZrO 3 (CZO) thin films for the dielectric layers of field-effect transistors (FETs) by pulsed laser deposition (PLD). The films exhibited very smooth surfaces with root-mean-squares (rms) roughnesses of ∼1.3 A as evaluated by using atomic force microscopy (AFM). The breakdown electric fields of Al 2 O 3 , LAO, CHO and CZO films were 7, 6, 10 and 2 MV/cm, respectively. The magnitude of the leak current in each film was low enough to operate FET. We performed a comparative study of pentacene FET fabricated using these oxide dielectrics as gate insulators. High field-effect mobility of 1.4 cm 2 /V s and on/off current ratio of 10 7 were obtained in the pentacene FET using LAO gate insulating film. Use of the LAO films as gate dielectrics has been found to suppress the hysteresis of pentacene FET operations. The LAO films are relevant to the dielectric layer of organic FETs

The electrical performance and gate bias stability of an amorphous InGaZnO thin-film transistor with HfO2 high-k dielectrics

Science.gov (United States)

Wang, Ruo Zheng; Wu, Sheng Li; Li, Xin Yu; Zhang, Jin Tao

2017-07-01

In this study, we set out to fabricate an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with SiNx/HfO2/SiNx (SHS) sandwiched dielectrics. The J-V and C-V of this SHS film were extracted by the Au/p-Si/SHS/Ti structure. At room temperature the a-IGZO with SHS dielectrics showed the following electrical properties: a threshold voltage of 2.9 V, a subthreshold slope of 0.35 V/decade, an on/off current ratio of 3.5 × 107, and a mobility of 12.8 cm2 V-1 s-1. Finally, we tested the influence of gate bias stress on the TFT, and the result showed that the threshold voltage shifted to a positive voltage when applying a positive gate voltage to the TFT.

Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging?

Directory of Open Access Journals (Sweden)

Takashi Ando

2012-03-01

Full Text Available Current status and challenges of aggressive equivalent-oxide-thickness (EOT scaling of high-κ gate dielectrics via higher-κ ( > 20 materials and interfacial layer (IL scavenging techniques are reviewed. La-based higher-κ materials show aggressive EOT scaling (0.5–0.8 nm, but with effective workfunction (EWF values suitable only for n-type field-effect-transistor (FET. Further exploration for p-type FET-compatible higher-κ materials is needed. Meanwhile, IL scavenging is a promising approach to extend Hf-based high-κ dielectrics to future nodes. Remote IL scavenging techniques enable EOT scaling below 0.5 nm. Mobility-EOT trends in the literature suggest that short-channel performance improvement is attainable with aggressive EOT scaling via IL scavenging or La-silicate formation. However, extreme IL scaling (e.g., zero-IL is accompanied by loss of EWF control and with severe penalty in reliability. Therefore, highly precise IL thickness control in an ultra-thin IL regime ( < 0.5 nm will be the key technology to satisfy both performance and reliability requirements for future CMOS devices.

Towards low-voltage organic thin film transistors (OTFTs with solution-processed high-k dielectric and interface engineering

Directory of Open Access Journals (Sweden)

Yaorong Su

2015-11-01

Full Text Available Although impressive progress has been made in improving the performance of organic thin film transistors (OTFTs, the high operation voltage resulting from the low gate capacitance density of traditional SiO2 remains a severe limitation that hinders OTFTs'development in practical applications. In this regard, developing new materials with high-k characteristics at low cost is of great scientific and technological importance in the area of both academia and industry. Here, we introduce a simple solution-based technique to fabricate high-k metal oxide dielectric system (ATO at low-temperature, which can be used effectively to realize low-voltage operation of OTFTs. On the other hand, it is well known that the properties of the dielectric/semiconductor and electrode/semiconductor interfaces are crucial in controlling the electrical properties of OTFTs. By optimizing the above two interfaces with octadecylphosphonic acid (ODPA self-assembled monolayer (SAM and properly modified low-cost Cu, obviously improved device performance is attained in our low-voltage OTFTs. Further more, organic electronic devices on flexible substrates have attracted much attention due to their low-cost, rollability, large-area processability, and so on. Basing on the above results, outstanding electrical performance is achieved in flexible devices. Our studies demonstrate an effective way to realize low-voltage, high-performance OTFTs at low-cost.

Extraction and dielectric properties of curcuminoid films grown on Si substrate for high-k dielectric applications

Energy Technology Data Exchange (ETDEWEB)

Dakhel, A.A.; Jasim, Khalil E. [Department of Physics, College of Science, University of Bahrain, P.O. Box 32038 (Bahrain); Cassidy, S. [Department of Basic Medical Sciences, Royal College of Surgeons in Ireland, Medical University of Bahrain, P.O. Box 15503 (Bahrain); Henari, F.Z., E-mail: fzhenari@rcsi-mub.com [Department of Basic Medical Sciences, Royal College of Surgeons in Ireland, Medical University of Bahrain, P.O. Box 15503 (Bahrain)

2013-09-20

Highlights: • The unknown insulating properties of curcuminoid extract are systematically studied. • Optical study gives a bandgap of 3.15 eV and a refractive index of 1.92 at 505 nm. • Turmeric is a high-k environmental friendly material for use in microelectronics. • Curcuminoid extract can be used as insulator of MIS devices with ε{sup ′}{sub ∞}≈54.2. -- Abstract: Curcuminoids were extracted from turmeric powder and evaporated in vacuum to prepare thin films on p-Si and glass substrates for dielectric and optical investigations. The optical absorption spectrum of the prepared amorphous film was not identical to that of the molecular one, which was identified by a strong wide absorption band in between ∼220 and 540 nm. The onset energy of the optical absorption of the film was calculated by using Hamberg et al. method. The dielectric properties of this material were systematically studied for future eco friendly applications in metal–insulator–semiconductor MIS field of applications. The complex dielectric properties were studied in the frequency range of 1–1000 kHz and was analysed in-terms of dielectric impedance Z{sup *}(ω) and modulus M{sup *}(ω). Generally, the curcuminoid complex can be considered as a high-k material and can be used in the environmental friendly production of microelectronic devices.

Extraction and dielectric properties of curcuminoid films grown on Si substrate for high-k dielectric applications

International Nuclear Information System (INIS)

Dakhel, A.A.; Jasim, Khalil E.; Cassidy, S.; Henari, F.Z.

2013-01-01

Highlights: • The unknown insulating properties of curcuminoid extract are systematically studied. • Optical study gives a bandgap of 3.15 eV and a refractive index of 1.92 at 505 nm. • Turmeric is a high-k environmental friendly material for use in microelectronics. • Curcuminoid extract can be used as insulator of MIS devices with ε ′ ∞ ≈54.2. -- Abstract: Curcuminoids were extracted from turmeric powder and evaporated in vacuum to prepare thin films on p-Si and glass substrates for dielectric and optical investigations. The optical absorption spectrum of the prepared amorphous film was not identical to that of the molecular one, which was identified by a strong wide absorption band in between ∼220 and 540 nm. The onset energy of the optical absorption of the film was calculated by using Hamberg et al. method. The dielectric properties of this material were systematically studied for future eco friendly applications in metal–insulator–semiconductor MIS field of applications. The complex dielectric properties were studied in the frequency range of 1–1000 kHz and was analysed in-terms of dielectric impedance Z * (ω) and modulus M * (ω). Generally, the curcuminoid complex can be considered as a high-k material and can be used in the environmental friendly production of microelectronic devices

Theoretical and Experimental Studies of New Polymer-Metal High-Dielectric Constant Nanocomposites

Science.gov (United States)

Ginzburg, Valeriy; Elwell, Michael; Myers, Kyle; Cieslinski, Robert; Malowinski, Sarah; Bernius, Mark

2006-03-01

High-dielectric-constant (high-K) gate materials are important for the needs of electronics industry. Most polymers have dielectric constant in the range 2 materials with K > 10 it is necessary to combine polymers with ceramic or metal nanoparticles. Several formulations based on functionalized Au-nanoparticles (R ˜ 5 -— 10 nm) and PMMA matrix polymer are prepared. Nanocomposite films are subsequently cast from solution. We study the morphology of those nanocomposites using theoretical (Self-Consistent Mean-Field Theory [SCMFT]) and experimental (Transmission Electron Microscopy [TEM]) techniques. Good qualitative agreement between theory and experiment is found. The study validates the utility of SCMFT as screening tool for the preparation of stable (or at least metastable) polymer/nanoparticle mixtures.

Analyzing the effect of gate dielectric on the leakage currents

Directory of Open Access Journals (Sweden)

Sakshi

2016-01-01

Full Text Available An analytical threshold voltage model for MOSFETs has been developed using different gate dielectric oxides by using MATLAB software. This paper explains the dependency of threshold voltage on the dielectric material. The variation in the subthreshold currents with the change in the threshold voltage sue to the change of dielectric material has also been studied.

Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

KAUST Repository

Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Young, Chadwin D.; Bersuker, Gennadi; Hussain, Muhammad Mustafa

2015-01-01

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard

Design and Optimization of 22 nm Gate Length High-k/Metal gate NMOS Transistor

International Nuclear Information System (INIS)

Afifah Maheran A H; Menon P S; Shaari, S; Elgomati, H A; Salehuddin, F; Ahmad, I

2013-01-01

In this paper, we invented the optimization experiment design of a 22 nm gate length NMOS device which uses a combination of high-k material and metal as the gate which was numerically developed using an industrial-based simulator. The high-k material is Titanium dioxide (TiO 2 ), while the metal gate is Tungsten Silicide (WSi x ). The design is optimized using the L9 Taguchi method to get the optimum parameter design. There are four process parameters and two noise parameters which were varied for analyzing the effect on the threshold voltage (V th ). The objective of this experiment is to minimize the variance of V th where Taguchi's nominal-the-best signal-to-noise ratio (S/N Ratio) was used. The best settings of the process parameters were determined using Analysis of Mean (ANOM) and analysis of variance (ANOVA) to reduce the variability of V th . The results show that the V th values have least variance and the mean value can be adjusted to 0.306V ±0.027 for the NMOS device which is in line with projections by the ITRS specifications.

Study of surface-modified PVP gate dielectric in organic thin film transistors with the nano-particle silver ink source/drain electrode.

Science.gov (United States)

Yun, Ho-Jin; Ham, Yong-Hyun; Shin, Hong-Sik; Jeong, Kwang-Seok; Park, Jeong-Gyu; Choi, Deuk-Sung; Lee, Ga-Won

2011-07-01

We have fabricated the flexible pentacene based organic thin film transistors (OTFTs) with formulated poly[4-vinylphenol] (PVP) gate dielectrics treated by CF4/O2 plasma on poly[ethersulfones] (PES) substrate. The solution of gate dielectrics is made by adding methylated poly[melamine-co-formaldehyde] (MMF) to PVP. The PVP gate dielectric layer was cross linked at 90 degrees under UV ozone exposure. Source/drain electrodes are formed by micro contact printing (MCP) method using nano particle silver ink for the purposes of low cost and high throughput. The optimized OTFT shows the device performance with field effect mobility of the 0.88 cm2/V s, subthreshold slope of 2.2 V/decade, and on/off current ratios of 1.8 x 10(-6) at -40 V gate bias. We found that hydrophobic PVP gate dielectric surface can influence on the initial film morphologies of pentacene making dense, which is more important for high performance OTFTs than large grain size. Moreover, hydrophobic gate dielelctric surface reduces voids and -OH groups that interrupt the carrier transport in OTFTs.

Effects of Annealing Time on the Performance of OTFT on Glass with ZrO2 as Gate Dielectric

Directory of Open Access Journals (Sweden)

W. M. Tang

2012-01-01

Full Text Available Copper phthalocyanine-based organic thin-film transistors (OTFTs with zirconium oxide (ZrO2 as gate dielectric have been fabricated on glass substrates. The gate dielectric is annealed in N2 at different durations (5, 15, 40, and 60 min to investigate the effects of annealing time on the electrical properties of the OTFTs. Experimental results show that the longer the annealing time for the OTFT, the better the performance. Among the devices studied, OTFTs with gate dielectric annealed at 350°C in N2 for 60 min exhibit the best device performance. They have a small threshold voltage of −0.58 V, a low subthreshold slope of 0.8 V/decade, and a low off-state current of 0.73 nA. These characteristics demonstrate that the fabricated device is suitable for low-voltage and low-power operations. When compared with the TFT samples annealed for 5 min, the ones annealed for 60 min have 20% higher mobility and nearly two times smaller the subthreshold slope and off-state current. The extended annealing can effectively reduce the defects in the high-k film and produces a better insulator/organic interface. This results in lower amount of carrier scattering and larger CuPc grains for carrier transport.

Enhanced ZnO Thin-Film Transistor Performance Using Bilayer Gate Dielectrics

KAUST Repository

Alshammari, Fwzah Hamud; Nayak, Pradipta K.; Wang, Zhenwei; Alshareef, Husam N.

2016-01-01

We report ZnO TFTs using Al2O3/Ta2O5 bilayer gate dielectrics grown by atomic layer deposition. The saturation mobility of single layer Ta2O5 dielectric TFT was 0.1 cm2 V-1 s-1, but increased to 13.3 cm2 V-1 s-1 using Al2O3/Ta2O5 bilayer dielectric with significantly lower leakage current and hysteresis. We show that point defects present in ZnO film, particularly VZn, are the main reason for the poor TFT performance with single layer dielectric, although interfacial roughness scattering effects cannot be ruled out. Our approach combines the high dielectric constant of Ta2O5 and the excellent Al2O3/ZnO interface quality, resulting in improved device performance. © 2016 American Chemical Society.

Enhanced ZnO Thin-Film Transistor Performance Using Bilayer Gate Dielectrics

KAUST Repository

Alshammari, Fwzah Hamud

2016-08-24

We report ZnO TFTs using Al2O3/Ta2O5 bilayer gate dielectrics grown by atomic layer deposition. The saturation mobility of single layer Ta2O5 dielectric TFT was 0.1 cm2 V-1 s-1, but increased to 13.3 cm2 V-1 s-1 using Al2O3/Ta2O5 bilayer dielectric with significantly lower leakage current and hysteresis. We show that point defects present in ZnO film, particularly VZn, are the main reason for the poor TFT performance with single layer dielectric, although interfacial roughness scattering effects cannot be ruled out. Our approach combines the high dielectric constant of Ta2O5 and the excellent Al2O3/ZnO interface quality, resulting in improved device performance. © 2016 American Chemical Society.

Analytical Modeling of Triple-Metal Hetero-Dielectric DG SON TFET

Science.gov (United States)

Mahajan, Aman; Dash, Dinesh Kumar; Banerjee, Pritha; Sarkar, Subir Kumar

2018-02-01

In this paper, a 2-D analytical model of triple-metal hetero-dielectric DG TFET is presented by combining the concepts of triple material gate engineering and hetero-dielectric engineering. Three metals with different work functions are used as both front- and back gate electrodes to modulate the barrier at source/channel and channel/drain interface. In addition to this, front gate dielectric consists of high-K HfO2 at source end and low-K SiO2 at drain side, whereas back gate dielectric is replaced by air to further improve the ON current of the device. Surface potential and electric field of the proposed device are formulated solving 2-D Poisson's equation and Young's approximation. Based on this electric field expression, tunneling current is obtained by using Kane's model. Several device parameters are varied to examine the behavior of the proposed device. The analytical model is validated with TCAD simulation results for proving the accuracy of our proposed model.

Polycrystalline diamond RF MOSFET with MoO3 gate dielectric

Directory of Open Access Journals (Sweden)

Zeyang Ren

2017-12-01

Full Text Available We report the radio frequency characteristics of the diamond metal-oxide-semiconductor field effect transistor with MoO3 gate dielectric for the first time. The device with 2-μm gate length was fabricated on high quality polycrystalline diamond. The maximum drain current of 150 mA/mm at VGS = -5 V and the maximum transconductance of 27 mS/mm were achieved. The extrinsic cutoff frequency of 1.2 GHz and the maximum oscillation frequency of 1.9 GHz have been measured. The moderate frequency characteristics are attributed to the moderate transconductance limited by the series resistance along the channel. We expect that the frequency characteristics of the device can be improved by increasing the magnitude of gm, or fundamentally decreasing the gate-controlled channel resistance and series resistance along the channel, and down-scaling the gate length.

Integration of atomic layer deposited high-k dielectrics on GaSb via hydrogen plasma exposure

Directory of Open Access Journals (Sweden)

Laura B. Ruppalt

2014-12-01

Full Text Available In this letter we report the efficacy of a hydrogen plasma pretreatment for integrating atomic layer deposited (ALD high-k dielectric stacks with device-quality p-type GaSb(001 epitaxial layers. Molecular beam eptiaxy-grown GaSb surfaces were subjected to a 30 minute H2/Ar plasma treatment and subsequently removed to air. High-k HfO2 and Al2O3/HfO2 bilayer insulating films were then deposited via ALD and samples were processed into standard metal-oxide-semiconductor (MOS capacitors. The quality of the semiconductor/dielectric interface was probed by current-voltage and variable-frequency admittance measurements. Measurement results indicate that the H2-plamsa pretreatment leads to a low density of interface states nearly independent of the deposited dielectric material, suggesting that pre-deposition H2-plasma exposure, coupled with ALD of high-k dielectrics, may provide an effective means for achieving high-quality GaSb MOS structures for advanced Sb-based digital and analog electronics.

High mobility and low operating voltage ZnGaO and ZnGaLiO transistors with spin-coated Al2O3 as gate dielectric

International Nuclear Information System (INIS)

Xia, D X; Xu, J B

2010-01-01

Spin-coated alumina serving as a gate dielectric in thin film transistors shows interesting dielectric properties for low-voltage applications, despite a moderate capacitance. With Ga singly doped and Ga, Li co-doped ZnO as the active channel layers, typical mobilities of 4.7 cm 2 V -1 s -1 and 2.1 cm 2 V -1 s -1 are achieved, respectively. At a given gate bias, the operation current is much smaller than the previously reported values in low-voltage thin film transistors, primarily relying on the giant-capacitive dielectric. The reported devices combine advantages of high mobility, low power consumption, low cost and ease of fabrication. In addition to the transparent nature of both the dielectric and semiconducting active channels, the superior electrical properties of the devices may provide a new avenue for future transparent electronics. (fast track communication)

High performance top-gated indium–zinc–oxide thin film transistors with in-situ formed HfO{sub 2} gate insulator

Energy Technology Data Exchange (ETDEWEB)

Song, Yang, E-mail: yang_song@brown.edu [Department of Physics, Brown University, 182 Hope Street, Providence, RI 02912 (United States); Zaslavsky, A. [Department of Physics, Brown University, 182 Hope Street, Providence, RI 02912 (United States); School of Engineering, Brown University, 184 Hope Street, Providence, RI 02912 (United States); Paine, D.C. [School of Engineering, Brown University, 184 Hope Street, Providence, RI 02912 (United States)

2016-09-01

We report on top-gated indium–zinc–oxide (IZO) thin film transistors (TFTs) with an in-situ formed HfO{sub 2} gate dielectric insulator. Building on our previous demonstration of high-performance IZO TFTs with Al{sub 2}O{sub 3}/HfO{sub 2} gate dielectric, we now report on a one-step process, in which Hf is evaporated onto the 20 nm thick IZO channel, forming a partially oxidized HfO{sub x} layer, without any additional insulator in-between. After annealing in air at 300 °C, the in-situ reaction between partially oxidized Hf and IZO forms a high quality HfO{sub 2} gate insulator with a low interface trapped charge density N{sub TC} ~ 2.3 × 10{sup 11} cm{sup −2} and acceptably low gate leakage < 3 × 10{sup −7} A/cm{sup 2} at gate voltage V{sub G} = 1 V. The annealed TFTs with gate length L{sub G} = 50 μm have high mobility ~ 95 cm{sup 2}/V ∙ s (determined via the Y-function technique), high on/off ratio ~ 10{sup 7}, near-zero threshold voltage V{sub T} = − 0.02 V, and a subthreshold swing of 0.062 V/decade, near the theoretical limit. The on-current of our proof-of-concept TFTs is relatively low, but can be improved by reducing L{sub G}, indicating that high-performance top-gated HfO{sub 2}-isolated IZO TFTs can be fabricated using a single-step in-situ dielectric formation approach. - Highlights: • High-performance indium–zinc–oxide (IZO) thin film transistors (TFTs). • Single-step in-situ dielectric formation approach simplifies fabrication process. • During anneal, reaction between HfO{sub x} and IZO channel forms a high quality HfO{sub 2} layer. • Gate insulator HfO{sub 2} shows low interface trapped charge and small gate leakage. • TFTs have high mobility, near-zero threshold voltage, and a low subthreshold swing.

AlGaN/GaN MISHEMTs with AlN gate dielectric grown by thermal ALD technique.

Science.gov (United States)

Liu, Xiao-Yong; Zhao, Sheng-Xun; Zhang, Lin-Qing; Huang, Hong-Fan; Shi, Jin-Shan; Zhang, Chun-Min; Lu, Hong-Liang; Wang, Peng-Fei; Zhang, David Wei

2015-01-01

Recently, AlN plasma-enhanced atomic layer deposition (ALD) passivation technique had been proposed and investigated for suppressing the dynamic on-resistance degradation behavior of high-electron-mobility transistors (HEMTs). In this paper, a novel gate dielectric and passivation technique for GaN-on-Si AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMTs) is presented. This technique features the AlN thin film grown by thermal ALD at 400°C without plasma enhancement. A 10.6-nm AlN thin film was grown upon the surface of the HEMT serving as the gate dielectric under the gate electrode and as the passivation layer in the access region at the same time. The MISHEMTs with thermal ALD AlN exhibit enhanced on/off ratio, reduced channel sheet resistance, reduction of gate leakage by three orders of magnitude at a bias of 4 V, reduced threshold voltage hysteresis of 60 mV, and suppressed current collapse degradation.

Electrical characteristics of GdTiO{sub 3} gate dielectric for amorphous InGaZnO thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Her, Jim-Long [Division of Natural Science, Center for General Education, Chang Gung University, Taoyuan 333, Taiwan (China); Pan, Tung-Ming, E-mail: tmpan@mail.cgu.edu.tw [Department of Electronics Engineering, Chang Gung University, Taoyuan 333, Taiwan (China); Liu, Jiang-Hung; Wang, Hong-Jun; Chen, Ching-Hung [Department of Electronics Engineering, Chang Gung University, Taoyuan 333, Taiwan (China); Koyama, Keiichi [Graduate School of Science and Engineering, Kagoshima University, Kagoshima 890-0065 (Japan)

2014-10-31

In this article, we studied the structural properties and electrical characteristics of GdTiO{sub 3} gate dielectric for amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) applications. The a-IGZO TFT device featuring the GdTiO{sub 3} gate dielectric exhibited better electrical characteristics, including a small threshold voltage of 0.14 V, a large field-effect mobility of 32.3 cm{sup 2}/V-s, a high I{sub on}/I{sub off} current ratio of 4.2 × 10{sup 8}, and a low subthreshold swing of 213 mV/decade. Furthermore, the electrical instability of GdTiO{sub 3} a-IGZO TFTs was investigated under both positive gate-bias stress (PGBS) and negative gate-bias stress (NGBS) conditions. The electron charge trapping in the gate dielectric dominates the PGBS degradation, while the oxygen vacancies control the NGBS degradation. - Highlights: • Indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) • Structural and electrical properties of the GdTiO{sub 3} film were studied. • a-IGZO TFT featuring GdTi{sub x}O{sub y} dielectric exhibited better electrical characteristics. • TFT instability investigated under positive and negative gate-bias stress conditions.

Computation of Dielectric Response in Molecular Solids for High Capacitance Organic Dielectrics.

Science.gov (United States)

Heitzer, Henry M; Marks, Tobin J; Ratner, Mark A

2016-09-20

The dielectric response of a material is central to numerous processes spanning the fields of chemistry, materials science, biology, and physics. Despite this broad importance across these disciplines, describing the dielectric environment of a molecular system at the level of first-principles theory and computation remains a great challenge and is of importance to understand the behavior of existing systems as well as to guide the design and synthetic realization of new ones. Furthermore, with recent advances in molecular electronics, nanotechnology, and molecular biology, it has become necessary to predict the dielectric properties of molecular systems that are often difficult or impossible to measure experimentally. In these scenarios, it is would be highly desirable to be able to determine dielectric response through efficient, accurate, and chemically informative calculations. A good example of where theoretical modeling of dielectric response would be valuable is in the development of high-capacitance organic gate dielectrics for unconventional electronics such as those that could be fabricated by high-throughput printing techniques. Gate dielectrics are fundamental components of all transistor-based logic circuitry, and the combination high dielectric constant and nanoscopic thickness (i.e., high capacitance) is essential to achieving high switching speeds and low power consumption. Molecule-based dielectrics offer the promise of cheap, flexible, and mass producible electronics when used in conjunction with unconventional organic or inorganic semiconducting materials to fabricate organic field effect transistors (OFETs). The molecular dielectrics developed to date typically have limited dielectric response, which results in low capacitances, translating into poor performance of the resulting OFETs. Furthermore, the development of better performing dielectric materials has been hindered by the current highly empirical and labor-intensive pace of synthetic

Influence of Gate Dielectrics, Electrodes and Channel Width on OFET Characteristics

International Nuclear Information System (INIS)

Liyana, V P; Stephania, A M; Shiju, K; Predeep, P

2015-01-01

Organic Field Effect Transistors (OFET) possess wide applications in large area electronics owing to their attractive features like easy fabrication process, light weight, flexibility, cost effectiveness etc. But instability, high operational voltages and low carrier mobility act as inhibitors to commercialization of OFETs and various approaches were tried on a regular basis so as to make it viable. In this work, Poly 3-hexylthiophene-2,5diyl (P3HT) based OFETs with bottom-contact top-gate configuration using Poly vinyl alcohol (PVA) and Poly (methyl methacrylate) (PMMA) as gate dielectrics, aluminium and copper as source-drain electrodes are investigated. An effort is made to compare the effect of these dielectric materials and electrodes on the performance of OFET. Also, an attempt has been made to optimize the channel width of the device. These devices are characterised with mobility (μ), threshold voltage (V T ), on-off ratio (I on /I off ) and their comparative analysis is reported. (paper)

Influence of Gate Dielectrics, Electrodes and Channel Width on OFET Characteristics

Science.gov (United States)

Liyana, V. P.; Stephania, A. M.; Shiju, K.; Predeep, P.

2015-06-01

Organic Field Effect Transistors (OFET) possess wide applications in large area electronics owing to their attractive features like easy fabrication process, light weight, flexibility, cost effectiveness etc. But instability, high operational voltages and low carrier mobility act as inhibitors to commercialization of OFETs and various approaches were tried on a regular basis so as to make it viable. In this work, Poly 3-hexylthiophene-2,5diyl (P3HT) based OFETs with bottom-contact top-gate configuration using Poly vinyl alcohol (PVA) and Poly (methyl methacrylate) (PMMA) as gate dielectrics, aluminium and copper as source-drain electrodes are investigated. An effort is made to compare the effect of these dielectric materials and electrodes on the performance of OFET. Also, an attempt has been made to optimize the channel width of the device. These devices are characterised with mobility (μ), threshold voltage (VT), on-off ratio (Ion/Ioff) and their comparative analysis is reported.

Broadening of Distribution of Trap States in PbS Quantum Dot Field-Effect Transistors with High-k Dielectrics.

Science.gov (United States)

Nugraha, Mohamad I; Häusermann, Roger; Watanabe, Shun; Matsui, Hiroyuki; Sytnyk, Mykhailo; Heiss, Wolfgang; Takeya, Jun; Loi, Maria A

2017-02-08

We perform a quantitative analysis of the trap density of states (trap DOS) in PbS quantum dot field-effect transistors (QD-FETs), which utilize several polymer gate insulators with a wide range of dielectric constants. With increasing gate dielectric constant, we observe increasing trap DOS close to the lowest unoccupied molecular orbital (LUMO) of the QDs. In addition, this increase is also consistently followed by broadening of the trap DOS. We rationalize that the increase and broadening of the spectral trap distribution originate from dipolar disorder as well as polaronic interactions, which are appearing at strong dielectric polarization. Interestingly, the increased polaron-induced traps do not show any negative effect on the charge carrier mobility in our QD devices at the highest applied gate voltage, giving the possibility to fabricate efficient low-voltage QD devices without suppressing carrier transport.

Cleaning Challenges of High-κ/Metal Gate Structures

KAUST Repository

Hussain, Muhammad Mustafa; Shamiryan, Denis G.; Paraschiv, Vasile; Sano, Kenichi; Reinhardt, Karen A.

2010-01-01

High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.

Cleaning Challenges of High-κ/Metal Gate Structures

KAUST Repository

Hussain, Muhammad Mustafa

2010-12-20

High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.

Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics

KAUST Repository

Alshareef, Husam N.

2010-11-19

Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.

Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics

KAUST Repository

Alshareef, Husam N.; Caraveo-Frescas, J. A.; Cha, D. K.

2010-01-01

Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.

From surface to volume plasmons in hyperbolic metamaterials: General existence conditions for bulk high-k waves in metal-dielectric and graphene-dielectric multilayers

DEFF Research Database (Denmark)

Zhukovsky, Sergei; Andryieuski, Andrei; Sipe, John E.

2014-01-01

-dielectric and recently introduced graphene-dielectric stacks. We confirm that short-range surface plasmons in thin metal layers can give rise to hyperbolic metamaterial properties and demonstrate that long-range surface plasmons cannot. We also show that graphene-dielectric multilayers tend to support high- k waves...

Gate-first integration of tunable work function metal gates of different thicknesses into high-k metal gates CMOS FinFETs for multi- VTh engineering

KAUST Repository

Hussain, Muhammad Mustafa; Smith, Casey Eben; Harris, Harlan Rusty; Young, Chadwin; Tseng, Hsinghuang; Jammy, Rajarao

2010-01-01

Gate-first integration of tunable work function metal gates of different thicknesses (320 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ∼ 40 mV/V), nearly symmetric VTh, low T inv(∼ 1.4 nm), and high Ion(∼780μAμm) for N/PMOS without any intentional strain enhancement. © 2006 IEEE.

Gate-first integration of tunable work function metal gates of different thicknesses into high-k metal gates CMOS FinFETs for multi- VTh engineering

KAUST Repository

Hussain, Muhammad Mustafa

2010-03-01

Gate-first integration of tunable work function metal gates of different thicknesses (320 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ∼ 40 mV/V), nearly symmetric VTh, low T inv(∼ 1.4 nm), and high Ion(∼780μAμm) for N/PMOS without any intentional strain enhancement. © 2006 IEEE.

Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

KAUST Repository

Ghoneim, Mohamed T.

2015-06-01

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard bulk mono-crystalline silicon substrate. A lifetime projection is extracted using statistical analysis of the ramping voltage (Vramp) breakdown and time dependent dielectric breakdown data. The obtained flexible MOSCAPs operational voltages satisfying the 10 years lifetime benchmark are compared to those of the control MOSCAPs, which are not peeled off from the silicon wafer. © 2014 IEEE.

Effect of annealing temperature on structural and electrical properties of high-κ YbTixOy gate dielectrics for InGaZnO thin film transistors

International Nuclear Information System (INIS)

Pan, Tung-Ming; Chen, Fa-Hsyang; Hung, Meng-Ning

2015-01-01

This paper describes the effect of annealing temperature on the structural properties and electrical characteristics of high–κ YbTi x O y gate dielectrics for indium–gallium–zinc–oxide (IGZO) thin-film transistors (TFTs). X-ray diffraction, x-ray photoelectron spectroscopy and atomic force microscopy were used to study the structural, chemical and morphological features, respectively, of these dielectric films annealed at 200, 300 and 400 °C. The YbTi x O y IGZO TFT that had been annealed at 400 °C exhibited better electrical characteristics, such as a small threshold voltage of 0.53 V, a large field-effect mobility of 19.1 cm 2 V −1 s −1 , a high I on /I off ratio of 2.8 × 10 7 , and a low subthreshold swing of 176 mV dec. −1 , relative to those of the systems that had been subjected to other annealing conditions. This result suggests that YbTi x O y dielectric possesses a higher dielectric constant as well as lower oxygen vacancies (or defects) in the film. In addition, the instability of YbTi x O y IGZO TFT was studied under positive gate-bias stress and negative gate-bias stress conditions. (paper)

Low dielectric constant-based organic field-effect transistors and metal-insulator-semiconductor capacitors

Science.gov (United States)

Ukah, Ndubuisi Benjamin

This thesis describes a study of PFB and pentacene-based organic field-effect transistors (OFET) and metal-insulator-semiconductor (MIS) capacitors with low dielectric constant (k) poly(methyl methacrylate) (PMMA), poly(4-vinyl phenol) (PVP) and cross-linked PVP (c-PVP) gate dielectrics. A physical method -- matrix assisted pulsed laser evaporation (MAPLE) -- of fabricating all-polymer field-effect transistors and MIS capacitors that circumvents inherent polymer dissolution and solvent-selectivity problems, is demonstrated. Pentacene-based OFETs incorporating PMMA and PVP gate dielectrics usually have high operating voltages related to the thickness of the dielectric layer. Reduced PMMA layer thickness (≤ 70 nm) was obtained by dissolving the PMMA in propylene carbonate (PC). The resulting pentacene-based transistors exhibited very low operating voltage (below -3 V), minimal hysteresis in their transfer characteristics, and decent electrical performance. Also low voltage (within -2 V) operation using thin (≤ 80 nm) low-k and hydrophilic PVP and c-PVP dielectric layers obtained via dissolution in high dipole moment and high-k solvents -- PC and dimethyl sulfoxide (DMSO), is demonstrated to be a robust means of achieving improved electrical characteristics and high operational stability in OFETs incorporating PVP and c-PVP dielectrics.

A Review of Nanoscale Channel and Gate Engineered FINFETs for VLSI Mixed Signal Applications Using Zirconium-di-Oxide Dielectrics

Directory of Open Access Journals (Sweden)

D.Nirmal

2014-07-01

Full Text Available In the past, most of the research and development efforts in the area of CMOS and IC’s are oriented towards reducing the power and increasing the gain of the circuits. While focusing the attention on low power and high gain in the device, the materials of the device also been taken into consideration. In the present technology, Computationally intensive devices with low power dissipation and high gain are becoming a critical application domain. Several factors have contributed to this paradigm shift. The primary driving factor being the increase in scale of integration, the chip has to accommodate smaller and faster transistors than their predecessors. During the last decade semiconductor technology has been led by conventional scaling. Scaling, has been aimed towards higher speed, lower power and higher density of the semiconductor devices. However, as scaling approached its physical limits, it has become more difficult and challenging for fabrication industry. Therefore, tremendous research has been carried out to investigate the alternatives, and this led to the introduction of new Nano materials and concepts to overcome the difficulties in the device fabrications. In order to reduce the leakage current and parasitic capacitance in devices, gate oxide high-k dielectric materials are explored. Among the different high-k materials available the nano size Zirconium dioxide material is suggested as an alternate gate oxide material for devices due to its thermal stability and small grain size of material. To meet the requirements of ITRS roadmap 2012, the Multi gate devices are considered to be one of the most promising technologies for the future microelectronics industry due to its excellent immunity to short channel effects and high value of On current. The double gate or multi gate devices provide a better scalability option due to its excellent immunity to short-channel effects. Here the different high-k materials are replaced in different

Effects of Y incorporation in TaON gate dielectric on electrical performance of GaAs metal-oxide-semiconductor capacitor

Energy Technology Data Exchange (ETDEWEB)

Liu, Li Ning; Choi, Hoi Wai; Lai, Pui To [Department of Electrical and Electronic Engineering, The University of Hong Kong (China); Xu, Jing Ping [School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan (China)

2016-09-15

In this study, GaAs metal-oxide-semiconductor (MOS) capacitors using Y-incorporated TaON as gate dielectric have been investigated. Experimental results show that the sample with a Y/(Y + Ta) atomic ratio of 27.6% exhibits the best device characteristics: high k value (22.9), low interfacestate density (9.0 x 10{sup 11} cm{sup -2} eV{sup -1}), small flatband voltage (1.05 V), small frequency dispersion and low gate leakage current (1.3 x 10{sup -5}A/cm{sup 2} at V{sub fb} + 1 V). These merits should be attributed to the complementary properties of Y{sub 2}O{sub 3} and Ta{sub 2}O{sub 5}:Y can effectively passivate the large amount of oxygen vacancies in Ta{sub 2}O{sub 5}, while the positively-charged oxygen vacancies in Ta{sub 2}O{sub 5} are capable of neutralizing the effects of the negative oxide charges in Y{sub 2}O{sub 3}. This work demonstrates that an appropriate doping of Y content in TaON gate dielectric can effectively improve the electrical performance for GaAs MOS devices. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Gate dielectric strength dependent performance of CNT MOSFET and CNT TFET: A tight binding study

Directory of Open Access Journals (Sweden)

Md. Shamim Sarker

Full Text Available This paper presents a comparative study between CNT MOSFET and CNT TFET taking into account of different dielectric strength of gate oxide materials. Here we have studied the transfer characteristics, on/off current (ION/IOFF ratio and subthreshold slope of the device using Non Equilibrium Greens Function (NEGF formalism in tight binding frameworks. The results are obtained by solving the NEGF and Poisson’s equation self-consistently in NanoTCADViDES environment and found that the ON state performance of CNT MOSFET and CNT TFET have significant dependency on the dielectric strength of the gate oxide materials. The figure of merits of the devices also demonstrates that the CNT TFET is promising for high-speed and low-power logic applications. Keywords: CNT TFET, Subthreshold slop, Barrier width, Conduction band (C.B and Valance band (V.B, Oxide dielectric strength, Tight binding approach

Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance

Science.gov (United States)

Anand, Sunny; Sarin, R. K.

2017-02-01

In this paper, charge-plasma-based tunnel FET is proposed by employing dual material gate with hetero gate dielectric technique and it is named hetero-dielectric dual material gate doping-less TFET (HD_DMG_DLTFET). It is compared with conventional doping-less TFET (DLTFET) and dual material gate doping-less TFET (DMG_DLTFET) on the basis of analog and RF performance. The HD_DMG_DLTFET provides better ON state current ({I}\\text{ON}=94 μ \\text{A}/μ \\text{m}), {I}\\text{ON}/{I}\\text{OFF}(≈ 1.36× {10}13), \\text{point} (≈ 3\\text{mV}/\\text{dec}) and average subthreshold slope (\\text{AV}-\\text{SS}=40.40 \\text{mV}/\\text{dec}). The proposed device offers low total gate capacitance (C gg) along with higher drive current. However, with a better transconductance (g m) and cut-off frequency (f T), the HD_DMG_DLTFET can be a good candidate for RF circuitry. The early voltage (V EA) and output conductance (g d) are also moderate for the proposed device with comparison to other devices and therefore can be a candidate for analog devices. From all these simulation results and their study, it is observed that HD_DMG_DLTFET has improved analog/RF performance compared to DLTFET and DMG_DLTFET.

Plasma nitridation optimization for sub-15 A gate dielectrics

NARCIS (Netherlands)

Cubaynes, F.N; Schmitz, Jurriaan; van der Marel, C.; Snijders, J.H.M.; Veloso, A.; Rothschild, A.; Olsen, C.; Date, L.

The work investigates the impact of plasma nitridation process parameters upon the physical properties and upon the electrical performance of sub-15 A plasma nitrided gate dielectrics. The nitrogen distribution and chemical bonding of ultra-thin plasma nitrided films have been investigated using

Carbon nanotube transistors with graphene oxide films as gate dielectrics

Institute of Scientific and Technical Information of China (English)

无

2010-01-01

Carbon nanomaterials,including the one-dimensional(1-D) carbon nanotube(CNT) and two-dimensional(2-D) graphene,are heralded as ideal candidates for next generation nanoelectronics.An essential component for the development of advanced nanoelectronics devices is processing-compatible oxide.Here,in analogy to the widespread use of silicon dioxide(SiO2) in silicon microelectronic industry,we report the proof-of-principle use of graphite oxide(GO) as a gate dielectrics for CNT field-effect transistor(FET) via a fast and simple solution-based processing in the ambient condition.The exceptional transistor characteristics,including low operation voltage(2 V),high carrier mobility(950 cm2/V-1 s-1),and the negligible gate hysteresis,suggest a potential route to the future all-carbon nanoelectronics.

Influence of gate dielectric on the ambipolar characteristics of solution-processed organic field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Ribierre, J C; Ghosh, S; Takaishi, K; Muto, T; Aoyama, T, E-mail: jcribierre@ewha.ac.kr, E-mail: taoyama@riken.jp [Advanced Science Institute, RIKEN, 2-1 Hirosawa, Wako, Saitama 351-0198 (Japan)

2011-05-25

Solution-processed ambipolar organic field-effect transistors based on dicyanomethylene-substituted quinoidal quaterthiophene derivative [QQT(CN)4] are fabricated using various gate dielectric materials including cross-linked polyimide and poly-4-vinylphenol. Devices with spin-coated polymeric gate dielectric layers show a reduced hysteresis in their transfer characteristics. Among the insulating polymers examined in this study, a new fluorinated polymer with a low dielectric constant of 2.8 significantly improves both hole and electron field-effect mobilities of QQT(CN)4 thin films to values as high as 0.04 and 0.002 cm{sup 2} V{sup -1} s{sup -1}. These values are close to the best mobilities obtained in QQT(CN)4 devices fabricated on SiO{sub 2} treated with octadecyltrichlorosilane. The influence of the metal used for source/drain metal electrodes on the device performance is also investigated. Whereas best device performances are achieved with gold electrodes, more balanced electron and hole field-effect mobilities could be obtained using chromium.

Development of III-V p-MOSFETs with high-kappa gate stack for future CMOS applications

Science.gov (United States)

Nagaiah, Padmaja

As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, non-silicon materials and new device architectures are gradually being introduced to improve Si integrated circuit performance and continue transistor scaling. Recently, the replacement of SiO2 with a high-k material (HfO2) as gate dielectric has essentially removed one of the biggest advantages of Si as channel material. As a result, alternate high mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. III-V materials in particular have become of great interest as channel materials, owing to their superior electron transport properties. However, there are several critical challenges that need to be addressed before III-V based CMOS can replace Si CMOS technology. Some of these challenges include development of a high quality, thermally stable gate dielectric/III-V interface, and improvement in III-V p-channel hole mobility to complement the n-channel mobility, low source/drain resistance and integration onto Si substrate. In this thesis, we would be addressing the first two issues i.e. the development high performance III-V p-channels and obtaining high quality III-V/high-k interface. We start with using the device architecture of the already established InGaAs n-channels as a baseline to understand the effect of remote scattering from the high-k oxide and oxide/semiconductor interface on channel transport properties such as electron mobility and channel electron concentration. Temperature dependent Hall electron mobility measurements were performed to separate various scattering induced mobility limiting factors. Dependence of channel mobility on proximity of the channel to the oxide interface, oxide thickness, annealing conditions are discussed. The results from this work will be used in the design of the p-channel MOSFETs. Following this, InxGa1-xAs (x>0.53) is chosen as channel material for developing p

Effect of gate dielectrics on the performance of p-type Cu2O TFTs processed at room temperature

KAUST Repository

Al-Jawhari, Hala A.

2013-12-01

Single-phase Cu2O films with p-type semiconducting properties were successfully deposited by reactive DC magnetron sputtering at room temperature followed by post annealing process at 200°C. Subsequently, such films were used to fabricate bottom gate p-channel Cu2O thin film transistors (TFTs). The effect of using high-κ SrTiO3 (STO) as a gate dielectric on the Cu2O TFT performance was investigated. The results were then compared to our baseline process which uses a 220 nm aluminum titanium oxide (ATO) dielectric deposited on a glass substrate coated with a 200 nm indium tin oxide (ITO) gate electrode. We found that with a 150 nm thick STO, the Cu2O TFTs exhibited a p-type behavior with a field-effect mobility of 0.54 cm2.V-1.s-1, an on/off ratio of around 44, threshold voltage equaling -0.62 V and a sub threshold swing of 1.64 V/dec. These values were obtained at a low operating voltage of -2V. The advantages of using STO as a gate dielectric relative to ATO are discussed. © (2014) Trans Tech Publications, Switzerland.

Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Tari, Alireza, E-mail: atari@uwaterloo.ca; Lee, Czang-Ho; Wong, William S. [Department of Electrical and Computer Engineering, University of Waterloo, 200 University Avenue West, Waterloo, Ontario N2L 3G1 (Canada)

2015-07-13

Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer into the IGZO and resulted in higher resistivity films.

Low operating voltage n-channel organic field effect transistors using lithium fluoride/PMMA bilayer gate dielectric

Energy Technology Data Exchange (ETDEWEB)

Kumar, S.; Dhar, A., E-mail: adhar@phy.iitkgp.ernet.in

2015-10-15

Highlights: • Alternative to chemically crosslinking of PMMA to achieve low leakage in provided. • Effect of LiF in reducing gate leakage through the OFET device is studied. • Effect of gate leakage on transistor performance has been investigated. • Low voltage operable and low temperature processed n-channel OFETs were fabricated. - Abstract: We report low temperature processed, low voltage operable n-channel organic field effect transistors (OFETs) using N,N′-Dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C{sub 8}) organic semiconductor and poly(methylmethacrylate) (PMMA)/lithium fluoride (LiF) bilayer gate dielectric. We have studied the role of LiF buffer dielectric in effectively reducing the gate leakage through the device and thus obtaining superior performance in contrast to the single layer PMMA dielectric devices. The bilayer OFET devices had a low threshold voltage (V{sub t}) of the order of 5.3 V. The typical values of saturation electron mobility (μ{sub s}), on/off ratio and inverse sub-threshold slope (S) for the range of devices made were estimated to be 2.8 × 10{sup −3} cm{sup 2}/V s, 385, and 3.8 V/decade respectively. Our work thus provides a potential substitution for much complicated process of chemically crosslinking PMMA to achieve low leakage, high capacitance, and thus low operating voltage OFETs.

Flexible semi-transparent silicon (100) fabric with high-k/metal gate devices

KAUST Repository

Rojas, Jhonathan Prieto

2013-01-07

Can we build a flexible and transparent truly high performance computer? High-k/metal gate stack based metal-oxide-semiconductor capacitor devices are monolithically fabricated on industry\\'s most widely used low-cost bulk single-crystalline silicon (100) wafers and then released as continuous, mechanically flexible, optically semi-transparent and high thermal budget compatible silicon fabric with devices. This is the first ever demonstration with this set of materials which allows full degree of freedom to fabricate nanoelectronics devices using state-of-the-art CMOS compatible processes and then to utilize them in an unprecedented way for wide deployment over nearly any kind of shape and architecture surfaces. Electrical characterization shows uncompromising performance of post release devices. Mechanical characterization shows extra-ordinary flexibility (minimum bending radius of 1 cm) making this generic process attractive to extend the horizon of flexible electronics for truly high performance computers. Schematic and photograph of flexible high-k/metal gate MOSCAPs showing high flexibility and C-V plot showing uncompromised performance. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

Science.gov (United States)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Device performance of in situ steam generated gate dielectric nitrided by remote plasma nitridation

International Nuclear Information System (INIS)

Al-Shareef, H. N.; Karamcheti, A.; Luo, T. Y.; Bersuker, G.; Brown, G. A.; Murto, R. W.; Jackson, M. D.; Huff, H. R.; Kraus, P.; Lopes, D.

2001-01-01

In situ steam generated (ISSG) oxides have recently attracted interest for use as gate dielectrics because of their demonstrated reliability improvement over oxides formed by dry oxidation. [G. Minor, G. Xing, H. S. Joo, E. Sanchez, Y. Yokota, C. Chen, D. Lopes, and A. Balakrishna, Electrochem. Soc. Symp. Proc. 99-10, 3 (1999); T. Y. Luo, H. N. Al-Shareef, G. A. Brown, M. Laughery, V. Watt, A. Karamcheti, M. D. Jackson, and H. R. Huff, Proc. SPIE 4181, 220 (2000).] We show in this letter that nitridation of ISSG oxide using a remote plasma decreases the gate leakage current of ISSG oxide by an order of magnitude without significantly degrading transistor performance. In particular, it is shown that the peak normalized transconductance of n-channel devices with an ISSG oxide gate dielectric decreases by only 4% and the normalized drive current by only 3% after remote plasma nitridation (RPN). In addition, it is shown that the reliability of the ISSG oxide exhibits only a small degradation after RPN. These observations suggest that the ISSG/RPN process holds promise for gate dielectric applications. [copyright] 2001 American Institute of Physics

Fabrication of amorphous InGaZnO thin-film transistor with solution processed SrZrO3 gate insulator

Science.gov (United States)

Takahashi, Takanori; Oikawa, Kento; Hoga, Takeshi; Uraoka, Yukiharu; Uchiyama, Kiyoshi

2017-10-01

In this paper, we describe a method of fabrication of thin film transistors (TFTs) with high dielectric constant (high-k) gate insulator by a solution deposition. We chose a solution processed SrZrO3 as a gate insulator material, which possesses a high dielectric constant of 21 with smooth surface. The IGZO-TFT with solution processed SrZrO3 showed good switching property and enough saturation features, i.e. field effect mobility of 1.7cm2/Vs, threshold voltage of 4.8V, sub-threshold swing of 147mV/decade, and on/off ratio of 2.3×107. Comparing to the TFTs with conventional SiO2 gate insulator, the sub-threshold swing was improved by smooth surface and high field effect due to the high dielectric constant of SrZrO3. These results clearly showed that use of solution processed high-k SrZrO3 gate insulator could improve sub-threshold swing. In addition, the residual carbon originated from organic precursors makes TFT performances degraded.

Fabrication and electrical properties of metal-oxide semiconductor capacitors based on polycrystalline p-Cu{sub x}O and HfO{sub 2}/SiO{sub 2} high-{kappa} stack gate dielectrics

Energy Technology Data Exchange (ETDEWEB)

Zou Xiao [Department of Electronic Science and Technology, School of Physical Science and Technology, Wuhan University, Wuhan, 430074 (China); Department of Electromachine Engineering, Jianghan University, Wuhan, 430056 (China); Fang Guojia, E-mail: gjfang@whu.edu.c [Department of Electronic Science and Technology, School of Physical Science and Technology, Wuhan University, Wuhan, 430074 (China); Yuan Longyan; Liu Nishuang; Long Hao; Zhao Xingzhong [Department of Electronic Science and Technology, School of Physical Science and Technology, Wuhan University, Wuhan, 430074 (China)

2010-05-31

Polycrystalline p-type Cu{sub x}O films were deposited after the growth of HfO{sub 2} dielectric on Si substrate by pulsed laser deposition, and Cu{sub x}O metal-oxide-semiconductor (MOS) capacitors with HfO{sub 2}/SiO{sub 2} stack gate dielectric were primarily fabricated and investigated. X-ray diffraction and X-ray photoelectron spectroscopy were applied to analyze crystalline structure and Cu{sup +}/Cu{sup 2+} ratios of Cu{sub x}O films respectively. SiO{sub 2} interlayer formed between the high-{kappa} dielectric and substrate was estimated by the transmission electron microscope. Results of electrical characteristic measurement indicate that the permittivity of HfO{sub 2} is about 22, and the gate leakage current density of MOS capacitor with 11.3 nm HfO{sub 2}/SiO{sub 2} stack dielectrics is {approx} 10{sup -4} A/cm{sup 2}. Results also show that the annealing in N{sub 2} can improve the quality of Cu{sub x}O/HfO{sub 2} interface and thus reduce the gate leakage density.

Sol–gel deposited ceria thin films as gate dielectric for CMOS ...

Indian Academy of Sciences (India)

Sol–gel deposited ceria thin films as gate dielectric for CMOS technology. ANIL G KHAIRNAR ... The semiconductor roadmap following Moore's law is responsible for ..... The financial support from University Grants Commi- ssion (UGC), New ...

Ambipolar transport in CVD grown MoSe2 monolayer using an ionic liquid gel gate dielectric

Directory of Open Access Journals (Sweden)

Deliris N. Ortiz

2018-03-01

Full Text Available CVD grown MoSe2 monolayers were electrically characterized at room temperature in a field effect transistor (FET configuration using an ionic liquid (IL as the gate dielectric. During the growth, instead of using MoO3 powder, ammonium heptamolybdate was used for better Mo control of the source and sodium cholate added for lager MoSe2 growth areas. In addition, a high specific capacitance (∼7 μF/cm2 IL was used as the gate dielectric to significantly reduce the operating voltage. The device exhibited ambipolar charge transport at low voltages with enhanced parameters during n- and p-FET operation. IL gating thins the Schottky barrier at the metal/semiconductor interface permitting efficient charge injection into the channel and reduces the effects of contact resistance on device performance. The large specific capacitance of the IL was also responsible for a much higher induced charge density compared to the standard SiO2 dielectric. The device was successfully tested as an inverter with a gain of ∼2. Using a common metal for contacts simplifies fabrication of this ambipolar device, and the possibility of radiative recombination of holes and electrons could further extend its use in low power optoelectronic applications.

Pentacene-Based Thin Film Transistor with Inkjet-Printed Nanocomposite High-K Dielectrics

Directory of Open Access Journals (Sweden)

Chao-Te Liu

2012-01-01

Full Text Available The nanocomposite gate insulating film of a pentacene-based thin film transistor was deposited by inkjet printing. In this study, utilizing the pearl miller to crumble the agglomerations and the dispersant to well stabilize the dispersion of nano-TiO2 particles in the polymer matrix of the ink increases the dose concentration for pico-jetting, which could be as the gate dielectric film made by inkjet printing without the photography process. Finally, we realized top contact pentacene-TFTs and successfully accomplished the purpose of directly patternability and increase the performance of the device based on the nanocomposite by inkjet printing. These devices exhibited p-channel TFT characteristics with a high field-effect mobility (a saturation mobility of ̃0.58 cm2 V−1 s−1, a large current ratio (>103 and a low operation voltage (<6 V. Furthermore, we accorded the deposited mechanisms which caused the interface difference between of inkjet printing and spin coating. And we used XRD, SEM, Raman spectroscopy to help us analyze the transfer characteristics of pentacene films and the performance of OTFTs.

Electrical properties of nano-resistors made from the Zr-doped HfO2 high-k dielectric film

Science.gov (United States)

Zhang, Shumao; Kuo, Yue

2018-03-01

Electrical properties of nano-sized resistors made from the breakdown of the metal-oxide-semiconductor capacitor composed of the amorphous high-k gate dielectric have been investigated under different stress voltages and temperatures. The effective resistance of nano-resistors in the device was estimated from the I-V curve in the high voltage range. It decreased with the increase of the number of resistors. The resistance showed complicated temperature dependence, i.e. it neither behaves like a conductor nor a semiconductor. In the low voltage operation range, the charge transfer was controlled by the Schottky barrier at the nano-resistor/Si interface. The barrier height decreased with the increase of stress voltage, which was probably caused by the change of the nano-resistor composition. Separately, it was observed that the barrier height was dependent on the temperature, which was probably due to the dynamic nano-resistor formation process and the inhomogeneous barrier height distribution. The unique electrical characteristics of this new type of nano-resistors are important for many electronic and optoelectronic applications.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

Science.gov (United States)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

Science.gov (United States)

Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

Improved linearity in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with nonlinear polarization dielectric

International Nuclear Information System (INIS)

Gao, Tao; Xu, Ruimin; Kong, Yuechan; Zhou, Jianjun; Kong, Cen; Dong, Xun; Chen, Tangsheng

2015-01-01

We demonstrate highly improved linearity in a nonlinear ferroelectric of Pb(Zr 0.52 Ti 0.48 )-gated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). Distinct double-hump feature in the transconductance-gate voltage (g m -V g ) curve is observed, yielding remarkable enhancement in gate voltage swing as compared to MIS-HEMT with conventional linear gate dielectric. By incorporating the ferroelectric polarization into a self-consistent calculation, it is disclosed that in addition to the common hump corresponding to the onset of electron accumulation, the second hump at high current level is originated from the nonlinear polar nature of ferroelectric, which enhances the gate capacitance by increasing equivalent dielectric constant nonlinearly. This work paves a way for design of high linearity GaN MIS-HEMT by exploiting the nonlinear properties of dielectric

Sodium beta-alumina thin films as gate dielectrics for AlGaN/GaN metal—insulator—semiconductor high-electron-mobility transistors

International Nuclear Information System (INIS)

Tian Ben-Lang; Chen Chao; Li Yan-Rong; Zhang Wan-Li; Liu Xing-Zhao

2012-01-01

Sodium beta-alumina (SBA) is deposited on AlGaN/GaN by using a co-deposition process with sodium and Al 2 O 3 as the precursors. The X-ray diffraction (XRD) spectrum reveals that the deposited thin film is amorphous. The binding energy and composition of the deposited thin film, obtained from the X-ray photoelectron spectroscopy (XPS) measurement, are consistent with those of SBA. The dielectric constant of the SBA thin film is about 50. Each of the capacitance—voltage characteristics obtained at five different frequencies shows a high-quality interface between SBA and AlGaN. The interface trap density of metal—insulator—semiconductor high-electron-mobility transistor (MISHEMT) is measured to be (3.5∼9.5)×10 10 cm −2 ·eV −1 by the conductance method. The fixed charge density of SBA dielectric is on the order of 2.7×10 12 cm −2 . Compared with the AlGaN/GaN metal—semiconductor heterostructure high-electron-mobility transistor (MESHEMT), the AlGaN/GaN MISHEMT usually has a threshold voltage that shifts negatively. However, the threshold voltage of the AlGaN/GaN MISHEMT using SBA as the gate dielectric shifts positively from −5.5 V to −3.5 V. From XPS results, the surface valence-band maximum (VBM-EF) of AlGaN is found to decrease from 2.56 eV to 2.25 eV after the SBA thin film deposition. The possible reasons why the threshold voltage of AlGaN/GaN MISHEMT with the SBA gate dielectric shifts positively are the influence of SBA on surface valence-band maximum (VBM-EF), the reduction of interface traps and the effects of sodium ions, and/or the fixed charges in SBA on the two-dimensional electron gas (2DEG). (condensed matter: structural, mechanical, and thermal properties)

Improved linearity in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with nonlinear polarization dielectric

Energy Technology Data Exchange (ETDEWEB)

Gao, Tao [Fundamental Science on EHF Laboratory, University of Electronic Science and Technology of China (UESTC), Chengdu 611731 (China); Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Devices Institute, Nanjing 210016 (China); Xu, Ruimin [Fundamental Science on EHF Laboratory, University of Electronic Science and Technology of China (UESTC), Chengdu 611731 (China); Kong, Yuechan, E-mail: kycfly@163.com; Zhou, Jianjun; Kong, Cen; Dong, Xun; Chen, Tangsheng [Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Devices Institute, Nanjing 210016 (China)

2015-06-15

We demonstrate highly improved linearity in a nonlinear ferroelectric of Pb(Zr{sub 0.52}Ti{sub 0.48})-gated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). Distinct double-hump feature in the transconductance-gate voltage (g{sub m}-V{sub g}) curve is observed, yielding remarkable enhancement in gate voltage swing as compared to MIS-HEMT with conventional linear gate dielectric. By incorporating the ferroelectric polarization into a self-consistent calculation, it is disclosed that in addition to the common hump corresponding to the onset of electron accumulation, the second hump at high current level is originated from the nonlinear polar nature of ferroelectric, which enhances the gate capacitance by increasing equivalent dielectric constant nonlinearly. This work paves a way for design of high linearity GaN MIS-HEMT by exploiting the nonlinear properties of dielectric.

The influence of carbon doping on the performance of Gd2O3 as high-k gate dielectric

International Nuclear Information System (INIS)

Shekhter, P.; Yehezkel, S.; Shriki, A.; Eizenberg, M.; Chaudhuri, A. R.; Osten, H. J.; Laha, A.

2014-01-01

One of the approaches for overcoming the issue of leakage current in modern metal-oxide-semiconductor devices is utilizing the high dielectric constants of lanthanide based oxides. We investigated the effect of carbon doping directly into Gd 2 O 3 layers on the performance of such devices. It was found that the amount of carbon introduced into the dielectric is above the solubility limit; carbon atoms enrich the oxide-semiconductor interface and cause a significant shift in the flat band voltage of the stack. Although the carbon atoms slightly degrade this interface, this method has a potential for tuning the flat band voltage of such structures

Ultralow-k nanoporous organosilicate dielectric films imprinted with dendritic spheres.

Science.gov (United States)

Lee, Byeongdu; Park, Young-Hee; Hwang, Yong-Taek; Oh, Weontae; Yoon, Jinhwan; Ree, Moonhor

2005-02-01

Integrated circuits that have improved functionality and speed in a smaller package and that consume less power are desired by the microelectronics industry as well as by end users, to increase device performance and reduce costs. The fabrication of high-performance integrated circuits requires the availability of materials with low or ultralow dielectric constant (low-k: k noise in interconnect conductors, but also minimize power dissipation by reducing the capacitance between the interconnects. Here we describe the preparation of low- and ultralow-k nanoporous organosilicate dielectrics from blends of polymethylsilsesquioxane (PMSSQ) precursor with globular ethyl acrylate-terminated polypropylenimine dendrimers, which act as porogens. These dendrimers are found to mix well with the PMSSQ precursor and after their sacrificial thermal decompositions result in closed, spherical pores of <2.0 nm radius with a very narrow distribution even at high loading. This pore size and distribution are the smallest and the narrowest respectively ever achieved in porous spin-on dielectrics. The method therefore successfully delivers low- and ultralow-k PMSSQ dielectric films that should prove very useful in advanced integrated circuits.

Impact and Origin of Interface States in MOS Capacitor with Monolayer MoS2 and HfO2 High-k Dielectric.

Science.gov (United States)

Xia, Pengkun; Feng, Xuewei; Ng, Rui Jie; Wang, Shijie; Chi, Dongzhi; Li, Cequn; He, Zhubing; Liu, Xinke; Ang, Kah-Wee

2017-01-13

Two-dimensional layered semiconductors such as molybdenum disulfide (MoS 2 ) at the quantum limit are promising material for nanoelectronics and optoelectronics applications. Understanding the interface properties between the atomically thin MoS 2 channel and gate dielectric is fundamentally important for enhancing the carrier transport properties. Here, we investigate the frequency dispersion mechanism in a metal-oxide-semiconductor capacitor (MOSCAP) with a monolayer MoS 2 and an ultra-thin HfO 2 high-k gate dielectric. We show that the existence of sulfur vacancies at the MoS 2 -HfO 2 interface is responsible for the generation of interface states with a density (D it ) reaching ~7.03 × 10 11  cm -2  eV -1 . This is evidenced by a deficit S:Mo ratio of ~1.96 using X-ray photoelectron spectroscopy (XPS) analysis, which deviates from its ideal stoichiometric value. First-principles calculations within the density-functional theory framework further confirms the presence of trap states due to sulfur deficiency, which exist within the MoS 2 bandgap. This corroborates to a voltage-dependent frequency dispersion of ~11.5% at weak accumulation which decreases monotonically to ~9.0% at strong accumulation as the Fermi level moves away from the mid-gap trap states. Further reduction in D it could be achieved by thermally diffusing S atoms to the MoS 2 -HfO 2 interface to annihilate the vacancies. This work provides an insight into the interface properties for enabling the development of MoS 2 devices with carrier transport enhancement.

Top-gate dielectric induced doping and scattering of charge carriers in epitaxial graphene

Science.gov (United States)

Puls, Conor P.; Staley, Neal E.; Moon, Jeong-Sun; Robinson, Joshua A.; Campbell, Paul M.; Tedesco, Joseph L.; Myers-Ward, Rachael L.; Eddy, Charles R.; Gaskill, D. Kurt; Liu, Ying

2011-07-01

We show that an e-gun deposited dielectric impose severe limits on epitaxial graphene-based device performance based on Raman spectroscopy and low-temperature transport measurements. Specifically, we show from studies of epitaxial graphene Hall bars covered by SiO2 that the measured carrier density is strongly inhomogenous and predominantly induced by charged impurities at the grapheme/dielectric interface that limit mobility via Coulomb interactions. Our work emphasizes that material integration of epitaxial graphene and a gate dielectric is the next major road block towards the realization of graphene-based electronics.

Cell characteristics of FePt nano-dot memories with a high-k Al2O3 blocking oxide

International Nuclear Information System (INIS)

Lee, Gae Hun; Lee, Jung Min; Yang, Hyung Jun; Song, Yun Heub; Bea, Ji Cheol; Tanaka, Testsu

2012-01-01

The cell characteristics of an alloy FePt nano-dot (ND) charge trapping memory with a high-k dielectric as a blocking oxide was investigated. Adoption of a high-k Al 2 O 3 material as a blocking oxide for the metal nano-dot memory provided a superior scaling of the operation voltage compared to silicon oxide under a similar gate leakage level. For the 40-nm-thick high-k (Al 2 O 3 ) blocking oxide, we confirmed an operation voltage reduction of ∼7 V under the same memory window on for silicon dioxide. Also, this device showed a large memory window of 7.8 V and a low leakage current under 10 -10 A in an area of Φ 0.25 mm. From these results, the use of a dielectric (Al 2 O 3 ) as a blocking oxide for a metal nano-dot device is essential, and a metal nano-dot memory with a high-k dielectric will be one of the candidates for a high-density non-volatile memory device.

Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance

Science.gov (United States)

Yadav, Dharmendra Singh; Verma, Abhishek; Sharma, Dheeraj; Tirkey, Sukeshni; Raad, Bhagwan Ram

2017-11-01

Tunnel-field-effect-transistor (TFET) has emerged as one of the most prominent devices to replace conventional MOSFET due to its ability to provide sub-threshold slope below 60 mV/decade (SS ≤ 60 mV/decade) and low leakage current. Despite this, TFETs suffer from ambipolar behavior, lower ON-state current, and poor RF performance. To address these issues, we have introduced drain and gate work function engineering with hetero gate dielectric for the first time in charge plasma based doping-less TFET (DL TFET). In this, the usage of dual work functionality over the drain region significantly reduces the ambipolar behavior of the device by varying the energy barrier at drain/channel interface. Whereas, the presence of dual work function at the gate terminal increases the ON-state current (ION). The combined effect of dual work function at the gate and drain electrode results in the increment of ON-state current (ION) and decrement of ambipolar conduction (Iambi) respectively. Furthermore, the incorporation of hetero gate dielectric along with dual work functionality at the drain and gate electrode provides an overall improvement in the performance of the device in terms of reduction in ambipolarity, threshold voltage and sub-threshold slope along with improved ON-state current and high frequency figures of merit.

Intermodulation Linearity in High-k/Metal Gate 28 nm RF CMOS Transistors

Directory of Open Access Journals (Sweden)

Zhen Li

2015-09-01

Full Text Available This paper presents experimental characterization, simulation, and Volterra series based analysis of intermodulation linearity on a high-k/metal gate 28 nm RF CMOS technology. A figure-of-merit is proposed to account for both VGS and VDS nonlinearity, and extracted from frequency dependence of measured IIP3. Implications to biasing current and voltage optimization for linearity are discussed.

GaN-Based High-k Praseodymium Oxide Gate MISFETs with P2S5/(NH42SX + UV Interface Treatment Technology

Directory of Open Access Journals (Sweden)

Chao-Wei Lin

2012-01-01

Full Text Available This study examines the praseodymium-oxide- (Pr2O3- passivated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs with high dielectric constant in which the AlGaN Schottky layers are treated with P2S5/(NH42SX + ultraviolet (UV illumination. An electron-beam evaporated Pr2O3 insulator is used instead of traditional plasma-assisted chemical vapor deposition (PECVD, in order to prevent plasma-induced damage to the AlGaN. In this work, the HEMTs are pretreated with P2S5/(NH42SX solution and UV illumination before the gate insulator (Pr2O3 is deposited. Since stable sulfur that is bound to the Ga species can be obtained easily and surface oxygen atoms are reduced by the P2S5/(NH42SX pretreatment, the lowest leakage current is observed in MIS-HEMT. Additionally, a low flicker noise and a low surface roughness (0.38 nm are also obtained using this novel process, which demonstrates its ability to reduce the surface states. Low gate leakage current Pr2O3 and high-k AlGaN/GaN MIS-HEMTs, with P2S5/(NH42SX + UV illumination treatment, are suited to low-noise applications, because of the electron-beam-evaporated insulator and the new chemical pretreatment.

Bio Organic-Semiconductor Field-Effect Transistor (BioFET) Based on Deoxyribonucleic Acid (DNA) Gate Dielectric

Science.gov (United States)

2010-03-31

floating gate devices and metal-insulator-oxide-semiconductor (MIOS) devices. First attempts to use polarizable gate insulators in combination with...bulk of the semiconductor (ii) Due to the polarizable gate dielectric (iii) dipole polarization and (iv)electret effect due to mobile ions in the...characterization was carried out under an argon environment inside the glove box. An Agilent model E5273A with a two source-measurement unit instrument was

SiO2/AlON stacked gate dielectrics for AlGaN/GaN MOS heterojunction field-effect transistors

Science.gov (United States)

Watanabe, Kenta; Terashima, Daiki; Nozaki, Mikito; Yamada, Takahiro; Nakazawa, Satoshi; Ishida, Masahiro; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

Stacked gate dielectrics consisting of wide bandgap SiO2 insulators and thin aluminum oxynitride (AlON) interlayers were systematically investigated in order to improve the performance and reliability of AlGaN/GaN metal–oxide–semiconductor (MOS) devices. A significantly reduced gate leakage current compared with that in a single AlON layer was achieved with these structures, while maintaining the superior thermal stability and electrical properties of the oxynitride/AlGaN interface. Consequently, distinct advantages in terms of the reliability of the gate dielectrics, such as an improved immunity against electron injection and an increased dielectric breakdown field, were demonstrated for AlGaN/GaN MOS capacitors with optimized stacked structures having a 3.3-nm-thick AlON interlayer.

Accurate characterization and understanding of interface trap density trends between atomic layer deposited dielectrics and AlGaN/GaN with bonding constraint theory

Energy Technology Data Exchange (ETDEWEB)

Ramanan, Narayanan; Lee, Bongmook; Misra, Veena, E-mail: vmisra@ncsu.edu [Department of Electrical and Computer Engineering, North Carolina State University, 2410 Campus Shore Drive, Raleigh, North Carolina 27695 (United States)

2015-06-15

Many dielectrics have been proposed for the gate stack or passivation of AlGaN/GaN based metal oxide semiconductor heterojunction field effect transistors, to reduce gate leakage and current collapse, both for power and RF applications. Atomic Layer Deposition (ALD) is preferred for dielectric deposition as it provides uniform, conformal, and high quality films with precise monolayer control of film thickness. Identification of the optimum ALD dielectric for the gate stack or passivation requires a critical investigation of traps created at the dielectric/AlGaN interface. In this work, a pulsed-IV traps characterization method has been used for accurate characterization of interface traps with a variety of ALD dielectrics. High-k dielectrics (HfO{sub 2}, HfAlO, and Al{sub 2}O{sub 3}) are found to host a high density of interface traps with AlGaN. In contrast, ALD SiO{sub 2} shows the lowest interface trap density (<2 × 10{sup 12 }cm{sup −2}) after annealing above 600 °C in N{sub 2} for 60 s. The trend in observed trap densities is subsequently explained with bonding constraint theory, which predicts a high density of interface traps due to a higher coordination state and bond strain in high-k dielectrics.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

OpenAIRE

Roeckerath, M.; Lopes, J. M. J.; Durgun Özben, E.; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D.G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of < 1 nA/cm(2). Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated ...

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

Science.gov (United States)

Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

2009-08-01

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

A Non-canonical Voltage-Sensing Mechanism Controls Gating in K2P K(+) Channels.

Science.gov (United States)

Schewe, Marcus; Nematian-Ardestani, Ehsan; Sun, Han; Musinszki, Marianne; Cordeiro, Sönke; Bucci, Giovanna; de Groot, Bert L; Tucker, Stephen J; Rapedius, Markus; Baukrowitz, Thomas

2016-02-25

Two-pore domain (K2P) K(+) channels are major regulators of excitability that endow cells with an outwardly rectifying background "leak" conductance. In some K2P channels, strong voltage-dependent activation has been observed, but the mechanism remains unresolved because they lack a canonical voltage-sensing domain. Here, we show voltage-dependent gating is common to most K2P channels and that this voltage sensitivity originates from the movement of three to four ions into the high electric field of an inactive selectivity filter. Overall, this ion-flux gating mechanism generates a one-way "check valve" within the filter because outward movement of K(+) induces filter opening, whereas inward movement promotes inactivation. Furthermore, many physiological stimuli switch off this flux gating mode to convert K2P channels into a leak conductance. These findings provide insight into the functional plasticity of a K(+)-selective filter and also refine our understanding of K2P channels and the mechanisms by which ion channels can sense voltage. Copyright © 2016 The Authors. Published by Elsevier Inc. All rights reserved.

Dielectric strength of SiO2 in a CMOS transistor structure

International Nuclear Information System (INIS)

Soden, J.M.

1979-01-01

The distribution of experimental dielectric strengths of SiO 2 gate dielectric in a CMOS transistor structure is shown to be composed of a primary, statistically-normal distribution of high dielectric strength and a secondary distribution spread through the lower dielectric strength region. The dielectric strength was not significantly affected by high level (1 x 10 6 RADS (Si)) gamma radiation or high temperature (200 0 C) stress. The primary distribution breakdowns occurred at topographical edges, mainly at the gate/field oxide interface, and the secondary distribution breakdowns occurred at random locations in the central region of the gate

Effect of Dielectric Interface on the Performance of MoS2 Transistors.

Science.gov (United States)

Li, Xuefei; Xiong, Xiong; Li, Tiaoyang; Li, Sichao; Zhang, Zhenfeng; Wu, Yanqing

2017-12-27

Because of their wide bandgap and ultrathin body properties, two-dimensional materials are currently being pursued for next-generation electronic and optoelectronic applications. Although there have been increasing numbers of studies on improving the performance of MoS 2 field-effect transistors (FETs) using various methods, the dielectric interface, which plays a decisive role in determining the mobility, interface traps, and thermal transport of MoS 2 FETs, has not been well explored and understood. In this article, we present a comprehensive experimental study on the effect of high-k dielectrics on the performance of few-layer MoS 2 FETs from 300 to 4.3 K. Results show that Al 2 O 3 /HfO 2 could boost the mobility and drain current. Meanwhile, MoS 2 transistors with Al 2 O 3 /HfO 2 demonstrate a 2× reduction in oxide trap density compared to that of the devices with the conventional SiO 2 substrate. Also, we observe a negative differential resistance effect on the device with 1 μm-channel length when using conventional SiO 2 as the gate dielectric due to self-heating, and this is effectively eliminated by using the Al 2 O 3 /HfO 2 gate dielectric. This dielectric engineering provides a highly viable route to realizing high-performance transition metal dichalcogenide-based FETs.

Label Free Detection of Biomolecules Using Charge-Plasma-Based Gate Underlap Dielectric Modulated Junctionless TFET

Science.gov (United States)

Wadhwa, Girish; Raj, Balwinder

2018-05-01

Nanoscale devices are emerging as a platform for detecting biomolecules. Various issues were observed during the fabrication process such as random dopant fluctuation and thermal budget. To reduce these issues charge-plasma-based concept is introduced. This paper proposes the implementation of charge-plasma-based gate underlap dielectric modulated junctionless tunnel field effect transistor (DM-JLTFET) for the revelation of biomolecule immobilized in the open cavity gate channel region. In this p+ source and n+ drain regions are introduced by employing different work function over the intrinsic silicon. Also dual material gate architecture is implemented to reduce short channel effect without abandoning any other device characteristic. The sensitivity of biosensor is studied for both the neutral and charge-neutral biomolecules. The effect of device parameters such as channel thickness, cavity length and cavity thickness on drain current have been analyzed through simulations. This paper investigates the performance of charge-plasma-based gate underlap DM-JLTFET for biomolecule sensing applications while varying dielectric constant, charge density at different biasing conditions.

The memory effect of a pentacene field-effect transistor with a polarizable gate dielectric

Science.gov (United States)

Unni, K. N. N.; de Bettignies, Remi; Dabos-Seignon, Sylvie; Nunzi, Jean-Michel

2004-06-01

The nonvolatile transistor memory element is an interesting topic in organic electronics. In this case a memory cell consists of only one device where the stored information is written as a gate insulator polarization by a gate voltage pulse and read by the channel conductance control with channel voltage pulse without destruction of the stored information. Therefore such transistor could be the base of non-volatile non-destructively readable computer memory of extremely high density. Also devices with polarizable gate dielectrics can function more effectively in certain circuits. The effective threshold voltage Vt can be brought very close to zero, for applications where the available gate voltage is limited. Resonant and adaptive circuits can be tuned insitu by polarizing the gates. Poly(vinylidene fluoride), PVDF and its copolymer with trifluoroethylene P(VDF-TrFE) are among the best known and most widely used ferroelectric polymers. In this manuscript, we report new results of an organic FET, fabricated with pentacene as the active material and P(VDF-TrFE) as the gate insulator. Application of a writing voltage of -50 V for short duration results in significant change in the threshold voltage and remarkable increase in the drain current. The memory effect is retained over a period of 20 hours.

Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

Directory of Open Access Journals (Sweden)

H. Hussin

2014-01-01

Full Text Available We present a simulation study on negative bias temperature instability (NBTI induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2 and hafnium oxide (HfO2 layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2 are increased but is reduced by 11% when the SiO2 interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2 interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated.

Controlling Chain Conformations of High-k Fluoropolymer Dielectrics to Enhance Charge Mobilities in Rubrene Single-Crystal Field-Effect Transistors.

Science.gov (United States)

Adhikari, Jwala M; Gadinski, Matthew R; Li, Qi; Sun, Kaige G; Reyes-Martinez, Marcos A; Iagodkine, Elissei; Briseno, Alejandro L; Jackson, Thomas N; Wang, Qing; Gomez, Enrique D

2016-12-01

A novel photopatternable high-k fluoropolymer, poly(vinylidene fluoride-bromotrifluoroethylene) P(VDF-BTFE), with a dielectric constant (k) between 8 and 11 is demonstrated in thin-film transistors. Crosslinking P(VDF-BTFE) reduces energetic disorder at the dielectric-semiconductor interface by controlling the chain conformations of P(VDF-BTFE), thereby leading to approximately a threefold enhancement in the charge mobility of rubrene single-crystal field-effect transistors. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Palladium Gate All Around - Hetero Dielectric -Tunnel FET based highly sensitive Hydrogen Gas Sensor

Science.gov (United States)

Madan, Jaya; Chaujar, Rishu

2016-12-01

The paper presents a novel highly sensitive Hetero-Dielectric-Gate All Around Tunneling FET (HD-GAA-TFET) based Hydrogen Gas Sensor, incorporating the advantages of band to band tunneling (BTBT) mechanism. Here, the Palladium supported silicon dioxide is used as a sensing media and sensing relies on the interaction of hydrogen with Palladium-SiO2-Si. The high surface to volume ratio in the case of cylindrical GAA structure enhances the fortuities for surface reactions between H2 gas and Pd, and thus improves the sensitivity and stability of the sensor. Behaviour of the sensor in presence of hydrogen and at elevated temperatures is discussed. The conduction path of the sensor which is dependent on sensors radius has also been varied for the optimized sensitivity and static performance analysis of the sensor where the proposed design exhibits a superior performance in terms of threshold voltage, subthreshold swing, and band to band tunneling rate. Stability of the sensor with respect to temperature affectability has also been studied, and it is found that the device is reasonably stable and highly sensitive over the bearable temperature range. The successful utilization of HD-GAA-TFET in gas sensors may open a new door for the development of novel nanostructure gas sensing devices.

Use of water vapor for suppressing the growth of unstable low-κ interlayer in HfTiO gate-dielectric Ge metal-oxide-semiconductor capacitors with sub-nanometer capacitance equivalent thickness

International Nuclear Information System (INIS)

Xu, J.P.; Zou, X.; Lai, P.T.; Li, C.X.; Chan, C.L.

2009-01-01

Annealing of high-permittivity HfTiO gate dielectric on Ge substrate in different gases (N 2 , NH 3 , NO and N 2 O) with or without water vapor is investigated. Analysis by transmission electron microscopy indicates that the four wet anneals can greatly suppress the growth of a GeO x interlayer at the dielectric/Ge interface, and thus decrease interface states, oxide charges and gate leakage current. Moreover, compared with the wet N 2 anneal, the wet NH 3 , NO and N 2 O anneals decrease the equivalent permittivity of the gate dielectric due to the growth of a GeO x N y interlayer. Among the eight anneals, the wet N 2 anneal produces the best dielectric performance with an equivalent relative permittivity of 35, capacitance equivalent thickness of 0.81 nm, interface-state density of 6.4 x 10 11 eV -1 cm -2 and gate leakage current of 2.7 x 10 -4 A/cm 2 at V g = 1 V

Electrical and materials properties of ZrO2 gate dielectrics grown by atomic layer chemical vapor deposition

Science.gov (United States)

Perkins, Charles M.; Triplett, Baylor B.; McIntyre, Paul C.; Saraswat, Krishna C.; Haukka, Suvi; Tuominen, Marko

2001-04-01

Structural and electrical properties of gate stack structures containing ZrO2 dielectrics were investigated. The ZrO2 films were deposited by atomic layer chemical vapor deposition (ALCVD) after different substrate preparations. The structure, composition, and interfacial characteristics of these gate stacks were examined using cross-sectional transmission electron microscopy and x-ray photoelectron spectroscopy. The ZrO2 films were polycrystalline with either a cubic or tetragonal crystal structure. An amorphous interfacial layer with a moderate dielectric constant formed between the ZrO2 layer and the substrate during ALCVD growth on chemical oxide-terminated silicon. Gate stacks with a measured equivalent oxide thickness (EOT) of 1.3 nm showed leakage values of 10-5 A/cm2 at a bias of -1 V from flatband, which is significantly less than that seen with SiO2 dielectrics of similar EOT. A hysteresis of 8-10 mV was seen for ±2 V sweeps while a midgap interface state density (Dit) of ˜3×1011 states/cm eV was determined from comparisons of measured and ideal capacitance curves.

Silicate formation at the interface of Pr-oxide as a high-K dielectric and Si(001) surfaces

International Nuclear Information System (INIS)

Schmeisser, D.; Zheng, F.; Perez-Dieste, V.; Himpsel, F.J.; LoNigro, R.; Toro, R.G.; Malandrino, G.; Fragala, I.L.

2006-01-01

The composition and chemical bonding of the first atoms across the interface between Si(001) and the dielectric determine the quality of dielectric gate stacks. An analysis of that hidden interface is a challenge as it requires both, high sensitivity and elemental and chemical state information. We used X-ray absorption spectroscopy in total electron yield and total fluorescence yield at the Si2p and the O1s edges to address that issue. We report on results of Pr 2 O 3 /Si(001) as prepared by both, epitaxial growth and metal organic chemical vapor deposition (MOCVD), and compare to the SiO 2 /Si(001) system as a reference. We find evidence for the silicate formation at the interface as derived from the characteristic features at the Si2p and the O1s edges. The results are in line with model experiments in which films of increasing film thickness are deposited in situ on bare Si(001) surfaces

A simple method for reducing inevitable dielectric loss in high-permittivity dielectric elastomers

DEFF Research Database (Denmark)

Madsen, Frederikke Bahrt; Yu, Liyun; Mazurek, Piotr Stanislaw

2016-01-01

elastomer matrix, with high dielectric permittivity and a low Young's modulus, aligned with no loss of mechanical stability, was prepared through the use of commercially available chloropropyl-functional silicone oil mixed into a tough commercial liquid silicone rubber silicone elastomer. The addition...... also decreased the dielectric losses of an elastomer containing dielectric permittivity-enhancing TiO2 fillers. Commercially available chloropropyl-functional silicone oil thus constitutes a facile method for improved silicone DEs, with very low dielectric losses.......Commercial viability of dielectric elastomers (DEs) is currently limited by a few obstacles, including high driving voltages (in the kV range). Driving voltage can be lowered by either decreasing the Young's modulus or increasing the dielectric permittivity of silicone elastomers, or a combination...

Towards the accurate electronic structure descriptions of typical high-constant dielectrics

Science.gov (United States)

Jiang, Ting-Ting; Sun, Qing-Qing; Li, Ye; Guo, Jiao-Jiao; Zhou, Peng; Ding, Shi-Jin; Zhang, David Wei

2011-05-01

High-constant dielectrics have gained considerable attention due to their wide applications in advanced devices, such as gate oxides in metal-oxide-semiconductor devices and insulators in high-density metal-insulator-metal capacitors. However, the theoretical investigations of these materials cannot fulfil the requirement of experimental development, especially the requirement for the accurate description of band structures. We performed first-principles calculations based on the hybrid density functionals theory to investigate several typical high-k dielectrics such as Al2O3, HfO2, ZrSiO4, HfSiO4, La2O3 and ZrO2. The band structures of these materials are well described within the framework of hybrid density functionals theory. The band gaps of Al2O3, HfO2, ZrSiO4, HfSiO4, La2O3 and ZrO2are calculated to be 8.0 eV, 5.6 eV, 6.2 eV, 7.1 eV, 5.3 eV and 5.0 eV, respectively, which are very close to the experimental values and far more accurate than those obtained by the traditional generalized gradient approximation method.

Backside versus frontside advanced chemical analysis of high-k/metal gate stacks

Energy Technology Data Exchange (ETDEWEB)

Martinez, E., E-mail: eugenie.martinez@cea.fr [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Saidi, B. [STMicroelectronics, 850 rue Jean Monnet, 38926 Rousset Cedex, Crolles (France); Veillerot, M. [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Caubet, P. [STMicroelectronics, 850 rue Jean Monnet, 38926 Rousset Cedex, Crolles (France); Fabbri, J-M. [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Piallat, F. [STMicroelectronics, 850 rue Jean Monnet, 38926 Rousset Cedex, Crolles (France); Gassilloud, R. [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Schamm-Chardon, S. [CEMES-CNRS et Université de Toulouse, 29 rue Jeanne Marvig, 31055 Toulouse (France)

2015-08-15

Highlights: • The backside approach is a promising solution for advanced chemical characterization of future MOSFETs. • Frontside ToF-SIMS and Auger depth profiles are affected by cumulative mixing effects and thus not relevant for analyzing ultra-thin layers. • Higher in-depth resolution is possible in the backside approach for Auger and ToF-SIMS depth profiling. • Backside depth profiling allows revealing ultra-thin layers and elemental in-depth redistribution inside high-k/metal gate stacks. • Backside XPS allows preserving the full metal gate, thus enabling the analysis of real technological samples. - Abstract: Downscaling of transistors beyond the 14 nm technological node requires the implementation of new architectures and materials. Advanced characterization methods are needed to gain information about the chemical composition of buried layers and interfaces. An effective approach based on backside analysis is presented here. X-ray photoelectron spectroscopy, Auger depth profiling and time-of-flight secondary ions mass spectrometry are combined to investigate inter-diffusion phenomena. To highlight improvements related to the backside method, backside and frontside analyses are compared. Critical information regarding nitrogen, oxygen and aluminium redistribution inside the gate stacks is obtained only in the backside configuration.

Effects of Voltage-Gated K+ Channel on Cell Proliferation in Multiple Myeloma

Directory of Open Access Journals (Sweden)

Wei Wang

2014-01-01

Full Text Available Objective. To study the effects and underlying mechanisms of voltage-gated K+ channels on the proliferation of multiple myeloma cells. Methods. RPMI-8226 MM cell line was used for the experiments. Voltage-gated K+ currents and the resting potential were recorded by whole-cell patch-clamp technique. RT-PCR detected Kv channel mRNA expression. Cell viability was analyzed with MTT assay. Cell counting system was employed to monitor cell proliferation. DNA contents and cell volume were analyzed by flow cytometry. Results. Currents recorded in RPMI-8226 cells were confirmed to be voltage-gated K+ channels. A high level of Kv1.3 mRNA was detected but no Kv3.1 mRNA was detected in RPMI-8226 cells. Voltage-gated K+ channel blocker 4-aminopyridine (4-AP (2 mM depolarized the resting potential from −42 ± 1.7 mV to −31.8 ± 2.8 mV (P0.05. Conclusions. In RPMI-8226, voltage-gated K+ channels are involved in proliferation and cell cycle progression its influence on the resting potential and cell volume may be responsible for this process; the inhibitory effect of the voltage-gated K+ channel blocker on RPMI-8226 cell proliferation is a phase-specific event.

Plasma polymerized high energy density dielectric films for capacitors

Science.gov (United States)

Yamagishi, F. G.

1983-01-01

High energy density polymeric dielectric films were prepared by plasma polymerization of a variety of gaseous monomers. This technique gives thin, reproducible, pinhole free, conformable, adherent, and insoluble coatings and overcomes the processing problems found in the preparation of thin films with bulk polymers. Thus, devices are prepared completely in a vacuum environment. The plasma polymerized films prepared all showed dielectric strengths of greater than 1000 kV/cm and in some cases values of greater than 4000 kV/cm were observed. The dielectric loss of all films was generally less than 1% at frequencies below 10 kHz, but this value increased at higher frequencies. All films were self healing. The dielectric strength was a function of the polymerization technique, whereas the dielectric constant varied with the structure of the starting material. Because of the thin films used (thickness in the submicron range) surface smoothness of the metal electrodes was found to be critical in obtaining high dielectric strengths. High dielectric strength graft copolymers were also prepared. Plasma polymerized ethane was found to be thermally stable up to 150 C in the presence of air and 250 C in the absence of air. No glass transitions were observed for this material.

Use of water vapor for suppressing the growth of unstable low-{kappa} interlayer in HfTiO gate-dielectric Ge metal-oxide-semiconductor capacitors with sub-nanometer capacitance equivalent thickness

Energy Technology Data Exchange (ETDEWEB)

Xu, J.P. [Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan, 430074 (China); Zou, X. [School of Electromachine and Architecture Engineering, Jianghan University, Wuhan, 430056 (China); Lai, P.T. [Department of Electrical and Electronic Engineering, University of Hong Kong, Pokfulam Road (Hong Kong)], E-mail: laip@eee.hku.hk; Li, C.X.; Chan, C.L. [Department of Electrical and Electronic Engineering, University of Hong Kong, Pokfulam Road (Hong Kong)

2009-03-02

Annealing of high-permittivity HfTiO gate dielectric on Ge substrate in different gases (N{sub 2}, NH{sub 3}, NO and N{sub 2}O) with or without water vapor is investigated. Analysis by transmission electron microscopy indicates that the four wet anneals can greatly suppress the growth of a GeO{sub x} interlayer at the dielectric/Ge interface, and thus decrease interface states, oxide charges and gate leakage current. Moreover, compared with the wet N{sub 2} anneal, the wet NH{sub 3}, NO and N{sub 2}O anneals decrease the equivalent permittivity of the gate dielectric due to the growth of a GeO{sub x}N{sub y} interlayer. Among the eight anneals, the wet N{sub 2} anneal produces the best dielectric performance with an equivalent relative permittivity of 35, capacitance equivalent thickness of 0.81 nm, interface-state density of 6.4 x 10{sup 11} eV{sup -1} cm{sup -2} and gate leakage current of 2.7 x 10{sup -4} A/cm{sup 2} at V{sub g} = 1 V.

Design and testing of 45 kV, 50 kHz pulse power supply for dielectric barrier discharges

Science.gov (United States)

Sharma, Surender Kumar; Shyam, Anurag

2016-10-01

The design, construction, and testing of high frequency, high voltage pulse power supply are reported. The purpose of the power supply is to generate dielectric barrier discharges for industrial applications. The power supply is compact and has the advantage of low cost, over current protection, and convenient control for voltage and frequency selection. The power supply can generate high voltage pulses of up to 45 kV at the repetitive frequency range of 1 kHz-50 kHz with 1.2 kW input power. The output current of the power supply is limited to 500 mA. The pulse rise time and fall time are less than 2 μs and the pulse width is 2 μs. The power supply is short circuit proof and can withstand variable plasma load conditions. The power supply mainly consists of a half bridge series resonant converter to charge an intermediate capacitor, which discharges through a step-up transformer at high frequency to generate high voltage pulses. Semiconductor switches and amorphous cores are used for power modulation at higher frequencies. The power supply is tested with quartz tube dielectric barrier discharge load and worked stably. The design details and the performance of the power supply on no load and dielectric barrier discharge load are presented.

2-D modeling and analysis of short-channel behavior of a front high- K gate stack triple-material gate SB SON MOSFET

Science.gov (United States)

Banerjee, Pritha; Kumari, Tripty; Sarkar, Subir Kumar

2018-02-01

This paper presents the 2-D analytical modeling of a front high- K gate stack triple-material gate Schottky Barrier Silicon-On-Nothing MOSFET. Using the two-dimensional Poisson's equation and considering the popular parabolic potential approximation, expression for surface potential as well as the electric field has been considered. In addition, the response of the proposed device towards aggressive downscaling, that is, its extent of immunity towards the different short-channel effects, has also been considered in this work. The analytical results obtained have been validated using the simulated results obtained using ATLAS, a two-dimensional device simulator from SILVACO.

Water-gel for gating graphene transistors.

Science.gov (United States)

Kim, Beom Joon; Um, Soong Ho; Song, Woo Chul; Kim, Yong Ho; Kang, Moon Sung; Cho, Jeong Ho

2014-05-14

Water, the primary electrolyte in biology, attracts significant interest as an electrolyte-type dielectric material for transistors compatible with biological systems. Unfortunately, the fluidic nature and low ionic conductivity of water prevents its practical usage in such applications. Here, we describe the development of a solid state, megahertz-operating, water-based gate dielectric system for operating graphene transistors. The new electrolyte systems were prepared by dissolving metal-substituted DNA polyelectrolytes into water. The addition of these biocompatible polyelectrolytes induced hydrogelation to provide solid-state integrity to the system. They also enhanced the ionic conductivities of the electrolytes, which in turn led to the quick formation of an electric double layer at the graphene/electrolyte interface that is beneficial for modulating currents in graphene transistors at high frequencies. At the optimized conditions, the Na-DNA water-gel-gated flexible transistors and inverters were operated at frequencies above 1 MHz and 100 kHz, respectively.

Structural and electrical characteristics of high-κ ErTixOy gate dielectrics on InGaZnO thin-film transistors

International Nuclear Information System (INIS)

Chen, Fa-Hsyang; Her, Jim-Long; Shao, Yu-Hsuan; Li, Wei-Chen; Matsuda, Yasuhiro H.; Pan, Tung-Ming

2013-01-01

In this paper, we investigated the structural properties and electrical characteristics of high-κ ErTi x O y gate dielectrics on indium-gallium-zinc oxide thin-film transistors (IGZO TFTs). We used X-ray diffraction, X-ray photoelectron spectroscopy, and atomic force microscopy to investigate the structural and morphological features of these dielectric films after they had been subjected to annealing at various temperatures. The high-κ ErTi x O y IGZO TFT device annealed at 400 °C exhibited better electrical characteristics in terms of a large field-effect mobility (8.24 cm 2 /V-s), low threshold voltage (0.36 V), small subthreshold swing (130 mV/dec), and high I on/off ratio(3.73 × 10 6 ). These results are attributed to the reduction of the trap states and oxygen vacancies between the ErTi x O y film and IGZO active layer interface during high-temperature annealing in oxygen ambient. The reliability of voltage stress also can be improved by the oxygen annealing at 400 °C. - Highlights: • ErTi x O y InGaZnO thin-film transistors (TFT). • Structural and electrical properties of the TFT were investigated. • TFT device annealed at 400 °C exhibited better electrical characteristics. • Reliability of TFT device can be improved by annealing at 400 °C

Mechanistic study of plasma damage to porous low-k: Process development and dielectric recovery

Science.gov (United States)

Shi, Hualiang

Low-k dielectrics with porosity are being introduced to reduce the RC delay of Cu/low-k interconnect. However, during the O2 plasma ashing process, the porous low-k dielectrics tend to degrade due to methyl depletion, moisture uptake, and densification, increasing the dielectric constant and leakage current. This dissertation presents a study of the mechanisms of plasma damage and dielectric recovery. The kinetics of plasma interaction with low-k dielectrics was investigated both experimentally and theoretically. By using a gap structure, the roles of ion, photon, and radical in producing damage on low-k dielectrics were differentiated. Oxidative plasma induced damage was proportional to the oxygen radical density, enhanced by VUV photon, and increased with substrate temperature. Ion bombardment induced surface densification, blocking radical diffusion. Two analytical models were derived to quantify the plasma damage. Based on the radical diffusion, reaction, and recombination inside porous low-k dielectrics, a plasma altered layer model was derived to interpret the chemical effect in the low ion energy region. It predicted that oxidative plasma induced damage can be reduced by decreasing pore radius, substrate temperature, and oxygen radical density and increasing carbon concentration and surface recombination rate inside low-k dielectrics. The model validity was verified by experiments and Monte-Carlo simulations. This model was also extended to the patterned low-k structure. Based on the ion collision cascade process, a sputtering yield model was introduced to interpret the physical effect in the high ion energy region. The model validity was verified by checking the ion angular and energy dependences of sputtering yield using O2/He/Ar plasma, low-k dielectrics with different k values, and a Faraday cage. Low-k dielectrics and plasma process were optimized to reduce plasma damage, including increasing carbon concentration in low-k dielectrics, switching plasma

SEMICONDUCTOR TECHNOLOGY: TaN wet etch for application in dual-metal-gate integration technology

Science.gov (United States)

Yongliang, Li; Qiuxia, Xu

2009-12-01

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and Jg-Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.

High Stability Pentacene Transistors Using Polymeric Dielectric Surface Modifier.

Science.gov (United States)

Wang, Xiaohong; Lin, Guangqing; Li, Peng; Lv, Guoqiang; Qiu, Longzhen; Ding, Yunsheng

2015-08-01

1,6-bis(trichlorosilyl)hexane (C6Cl), polystyrene (PS), and cross-linked polystyrene (CPS) were investigated as gate dielectric modified layers for high performance organic transistors. The influence of the surface energy, roughness and morphology on the charge transport of the organic thin-film transistors (OTFTs) was investigated. The surface energy and roughness both affect the grain size of the pentacene films which will control the charge carrier mobility of the devices. Pentacene thin-film transistors fabricated on the CPS modified dielectric layers exhibited charge carrier mobility as high as 1.11 cm2 V-1 s-1. The bias stress stability for the CPS devices shows that the drain current only decays 1% after 1530 s and the mobility never decreases until 13530 s.

Interfacial Cation-Defect Charge Dipoles in Stacked TiO2/Al2O3 Gate Dielectrics.

Science.gov (United States)

Zhang, Liangliang; Janotti, Anderson; Meng, Andrew C; Tang, Kechao; Van de Walle, Chris G; McIntyre, Paul C

2018-02-14

Layered atomic-layer-deposited and forming-gas-annealed TiO 2 /Al 2 O 3 dielectric stacks, with the Al 2 O 3 layer interposed between the TiO 2 and a p-type germanium substrate, are found to exhibit a significant interface charge dipole that causes a ∼-0.2 V shift of the flat-band voltage and suppresses the leakage current density for gate injection of electrons. These effects can be eliminated by the formation of a trilayer dielectric stack, consistent with the cancellation of one TiO 2 /Al 2 O 3 interface dipole by the addition of another dipole of opposite sign. Density functional theory calculations indicate that the observed interface-dependent properties of TiO 2 /Al 2 O 3 dielectric stacks are consistent in sign and magnitude with the predicted behavior of Al Ti and Ti Al point-defect dipoles produced by local intermixing of the Al 2 O 3 /TiO 2 layers across the interface. Evidence for such intermixing is found in both electrical and physical characterization of the gate stacks.

High-k 3D-barium titanate foam/phenolphthalein poly(ether sulfone)/cyanate ester composites with frequency-stable dielectric properties and extremely low dielectric loss under reduced concentration of ceramics

Science.gov (United States)

Zheng, Longhui; Yuan, Li; Guan, Qingbao; Liang, Guozheng; Gu, Aijuan

2018-01-01

Higher dielectric constant, lower dielectric loss and better frequency stability have been the developing trends for high dielectric constant (high-k) materials. Herein, new composites have been developed through building unique structure by using hyperbranched polysiloxane modified 3D-barium titanate foam (BTF) (BTF@HSi) as the functional fillers and phenolphthalein poly(ether sulfone) (cPES)/cyanate ester (CE) blend as the resin matrix. For BTF@HSi/cPES/CE composite with 34.1 vol% BTF, its dielectric constant at 100 Hz is as high as 162 and dielectric loss is only 0.007; moreover, the dielectric properties of BTF@HSi/cPES/CE composites exhibit excellent frequency stability. To reveal the mechanism behind these attractive performances of BTF@HSi/cPES/CE composites, three kinds of composites (BTF/CE, BTF/cPES/CE, BTF@HSi/CE) were prepared, their structure and integrated performances were intensively investigated and compared with those of BTF@HSi/cPES/CE composites. Results show that the surface modification of BTF is good for preparing composites with improved thermal stability; while introducing flexible cPES to CE is beneficial to fabricate composites with good quality through effectively blocking cracks caused by the stress concentration, and then endowing the composites with good dielectric properties at reduced concentration of ceramics.

A complementary organic inverter of porphyrazine thin films: low-voltage operation using ionic liquid gate dielectrics.

Science.gov (United States)

Fujimoto, Takuya; Miyoshi, Yasuhito; Matsushita, Michio M; Awaga, Kunio

2011-05-28

We studied a complementary organic inverter consisting of a p-type semiconductor, metal-free phthalocyanine (H(2)Pc), and an n-type semiconductor, tetrakis(thiadiazole)porphyrazine (H(2)TTDPz), operated through the ionic-liquid gate dielectrics of N,N-diethyl-N-methyl(2-methoxyethyl)ammonium bis(trifluoromethylsulfonyl)imide (DEME-TFSI). This organic inverter exhibits high performance with a very low operation voltage below 1.0 V and a dynamic response up to 20 Hz. © The Royal Society of Chemistry 2011

Low operating voltage InGaZnO thin-film transistors based on Al2O3 high-k dielectrics fabricated using pulsed laser deposition

International Nuclear Information System (INIS)

Geng, G. Z.; Liu, G. X.; Zhang, Q.; Shan, F. K.; Lee, W. J.; Shin, B. C.; Cho, C. R.

2014-01-01

Low-voltage-driven amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) with an Al 2 O 3 dielectric were fabricated on a Si substrate by using pulsed laser deposition. Both Al 2 O 3 and IGZO thin films are amorphous, and the thin films have very smooth surfaces. The Al 2 O 3 gate dielectric exhibits a very low leakage current density of 1.3 x 10 -8 A/cm 2 at 5 V and a high capacitance density of 60.9 nF/cm 2 . The IGZO TFT with a structure of Ni/IGZO/Al 2 O 3 /Si exhibits high performance with a low threshold voltage of 1.18 V, a high field effect mobility of 20.25 cm 2 V -1 s -1 , an ultra small subthreshold swing of 87 mV/decade, and a high on/off current ratio of 3 x 10 7 .

Wet etching characteristics of a HfSiON high-k dielectric in HF-based solutions

International Nuclear Information System (INIS)

Li Yongliang; Xu Qiuxia

2010-01-01

The wet etching properties of a HfSiON high-k dielectric in HF-based solutions are investigated. HF-based solutions are the most promising wet chemistries for the removal of HfSiON, and etch selectivity of HF-based solutions can be improved by the addition of an acid and/or an alcohol to the HF solution. Due to densification during annealing, the etch rate of HfSiON annealed at 900 0 C for 30 s is significantly reduced compared with as-deposited HfSiON in HF-based solutions. After the HfSiON film has been completely removed by HF-based solutions, it is not possible to etch the interfacial layer and the etched surface does not have a hydrophobic nature, since N diffuses to the interface layer or Si substrate formation of Si-N bonds that dissolves very slowly in HF-based solutions. Existing Si-N bonds at the interface between the new high-k dielectric deposit and the Si substrate may degrade the carrier mobility due to Coulomb scattering. In addition, we show that N 2 plasma treatment before wet etching is not very effective in increasing the wet etch rate for a thin HfSiON film in our case. (semiconductor technology)

Effect of incorporation of nitrogen atoms in Al2O3 gate dielectric of wide-bandgap-semiconductor MOSFET on gate leakage current and negative fixed charge

Science.gov (United States)

Kojima, Eiji; Chokawa, Kenta; Shirakawa, Hiroki; Araidai, Masaaki; Hosoi, Takuji; Watanabe, Heiji; Shiraishi, Kenji

2018-06-01

We performed first-principle calculations to investigate the effect of incorporation of N atoms into Al2O3 gate dielectrics. Our calculations show that the defect levels generated by VO in Al2O3 are the origin of the stress-induced gate leakage current and that VOVAl complexes in Al2O3 cause negative fixed charge. We revealed that the incorporation of N atoms into Al2O3 eliminates the VO defect levels, reducing the stress-induced gate leakage current. Moreover, this suppresses the formation of negatively charged VOVAl complexes. Therefore, AlON can reduce both stress-induced gate leakage current and negative fixed charge in wide-bandgap-semiconductor MOSFETs.

Semi-transparent a-IGZO thin-film transistors with polymeric gate dielectric.

Science.gov (United States)

Hyung, Gun Woo; Wang, Jian-Xun; Li, Zhao-Hui; Koo, Ja-Ryong; Kwon, Sang Jik; Cho, Eou-Sik; Kim, Young Kwan

2013-06-01

We report the fabrication of semi-transparent a-IGZO-based thin-film transistors (TFTs) with crosslinked poly-4-vinylphenol (PVP) gate dielectric layers on PET substrate and thermally-evaporated Al/Ag/Al source and drain (S&D) electrodes, which showed a transmittance of 64% at a 500-nm wavelength and sheet resistance of 16.8 omega/square. The semi-transparent a-IGZO TFTs with a PVP layer exhibited decent saturation mobilities (maximum approximately 5.8 cm2Ns) and on/off current ratios of approximately 10(6).

Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation

Science.gov (United States)

Seema; Chauhan, Sudakar Singh

2018-05-01

In this paper, we demonstrate the double gate vertical tunnel field-effect transistor using homo/hetero dielectric buried oxide (HDB) to obtain the optimized device characteristics. In this concern, the existence of double gate, HDB and electrode work-function engineering enhances DC performance and Analog/RF performance. The use of electrostatic doping helps to achieve higher on-current owing to occurrence of higher tunneling generation rate of charge carriers at the source/epitaxial interface. Further, lightly doped drain region and high- k dielectric below channel and drain region are responsible to suppress the ambipolar current. Simulated results clarifies that proposed device have achieved the tremendous performance in terms of driving current capability, steeper subthreshold slope (SS), drain induced barrier lowering (DIBL), hot carrier effects (HCEs) and high frequency parameters for better device reliability.

Band Offsets and Interfacial Properties of HfAlO Gate Dielectric Grown on InP by Atomic Layer Deposition.

Science.gov (United States)

Yang, Lifeng; Wang, Tao; Zou, Ying; Lu, Hong-Liang

2017-12-01

X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy have been used to determine interfacial properties of HfO 2 and HfAlO gate dielectrics grown on InP by atomic layer deposition. An undesirable interfacial InP x O y layer is easily formed at the HfO 2 /InP interface, which can severely degrade the electrical performance. However, an abrupt interface can be achieved when the growth of the HfAlO dielectric on InP starts with an ultrathin Al 2 O 3 layer. The valence and conduction band offsets for HfAlO/InP heterojunctions have been determined to be 1.87 ± 0.1 and 2.83 ± 0.1 eV, respectively. These advantages make HfAlO a potential dielectric for InP MOSFETs.

Examination of Critical Length Effect in Copper Interconnects With Oxide and Low-k Dielectrics

International Nuclear Information System (INIS)

Thrasher, Stacye; Gall, Martin; Justison, Patrick; Hernandez, Richard; Kawasaki, Hisao; Capasso, Cristiano; Nguyen, Timothy

2004-01-01

As technology moves toward faster microelectronic devices with smaller feature sizes, copper is replacing aluminum-copper alloy and low-k dielectric is replacing oxide as the materials of choice for advanced interconnect integrations. Copper not only brings to the table the advantage of lower resistivity, but also exhibits better electromigration performance when compared to Al(Cu). Low-k dielectric materials are advantageous because they reduce power consumption and improve signal delay. Due to these advantages, the industry trend is moving towards integrating copper and low-k dielectric for high performance interconnects. The purpose of this study is to evaluate the critical length effect in single-inlaid copper interconnects and determine the critical product (jl)c, for a variety of integrations, examining the effect of ILD (oxide vs. low-k), geometry, and stress temperature

Modeling of leakage currents in high-k dielectrics

International Nuclear Information System (INIS)

Jegert, Gunther Christian

2012-01-01

Leakage currents are one of the major bottlenecks impeding the downscaling efforts of the semiconductor industry. Two core devices of integrated circuits, the transistor and, especially, the DRAM storage capacitor, suffer from the increasing loss currents. In this perspective a fundamental understanding of the physical origin of these leakage currents is highly desirable. However, the complexity of the involved transport phenomena so far has prevented the development of microscopic models. Instead, the analysis of transport through the ultra-thin layers of high-permittivity (high-k) dielectrics, which are employed as insulating layers, was carried out at an empirical level using simple compact models. Unfortunately, these offer only limited insight into the physics involved on the microscale. In this context the present work was initialized in order to establish a framework of microscopic physical models that allow a fundamental description of the transport processes relevant in high-k thin films. A simulation tool that makes use of kinetic Monte Carlo techniques was developed for this purpose embedding the above models in an environment that allows qualitative and quantitative analyses of the electronic transport in such films. Existing continuum approaches, which tend to conceal the important physics behind phenomenological fitting parameters, were replaced by three-dimensional transport simulations at the level of single charge carriers. Spatially localized phenomena, such as percolation of charge carriers across pointlike defects, being subject to structural relaxation processes, or electrode roughness effects, could be investigated in this simulation scheme. Stepwise a self-consistent, closed transport model for the TiN/ZrO 2 material system, which is of outmost importance for the semiconductor industry, was developed. Based on this model viable strategies for the optimization of TiN/ZrO 2 /TiN capacitor structures were suggested and problem areas that may

Modeling of leakage currents in high-k dielectrics

Energy Technology Data Exchange (ETDEWEB)

Jegert, Gunther Christian

2012-03-15

Leakage currents are one of the major bottlenecks impeding the downscaling efforts of the semiconductor industry. Two core devices of integrated circuits, the transistor and, especially, the DRAM storage capacitor, suffer from the increasing loss currents. In this perspective a fundamental understanding of the physical origin of these leakage currents is highly desirable. However, the complexity of the involved transport phenomena so far has prevented the development of microscopic models. Instead, the analysis of transport through the ultra-thin layers of high-permittivity (high-k) dielectrics, which are employed as insulating layers, was carried out at an empirical level using simple compact models. Unfortunately, these offer only limited insight into the physics involved on the microscale. In this context the present work was initialized in order to establish a framework of microscopic physical models that allow a fundamental description of the transport processes relevant in high-k thin films. A simulation tool that makes use of kinetic Monte Carlo techniques was developed for this purpose embedding the above models in an environment that allows qualitative and quantitative analyses of the electronic transport in such films. Existing continuum approaches, which tend to conceal the important physics behind phenomenological fitting parameters, were replaced by three-dimensional transport simulations at the level of single charge carriers. Spatially localized phenomena, such as percolation of charge carriers across pointlike defects, being subject to structural relaxation processes, or electrode roughness effects, could be investigated in this simulation scheme. Stepwise a self-consistent, closed transport model for the TiN/ZrO{sub 2} material system, which is of outmost importance for the semiconductor industry, was developed. Based on this model viable strategies for the optimization of TiN/ZrO{sub 2}/TiN capacitor structures were suggested and problem areas

Total Ionizing Dose Effects of Si Vertical Diffused MOSFET with SiO2 and Si3N4/SiO2 Gate Dielectrics

Directory of Open Access Journals (Sweden)

Jiongjiong Mo

2017-01-01

Full Text Available The total ionizing dose irradiation effects are investigated in Si vertical diffused MOSFETs (VDMOSs with different gate dielectrics including single SiO2 layer and double Si3N4/SiO2 layer. Radiation-induced holes trapping is greater for single SiO2 layer than for double Si3N4/SiO2 layer. Dielectric oxidation temperature dependent TID effects are also studied. Holes trapping induced negative threshold voltage shift is smaller for SiO2 at lower oxidation temperature. Gate bias during irradiation leads to different VTH shift for different gate dielectrics. Single SiO2 layer shows the worst negative VTH at VG=0 V, while double Si3N4/SiO2 shows negative VTH shift at VG=-5 V, positive VTH shift at VG=10 V, and negligible VTH shift at VG=0 V.

Dielectric properties of polyhedral oligomeric silsesquioxane (POSS)-based nanocomposites at 77k

International Nuclear Information System (INIS)

Pan, Ming-Jen; Gorzkowski, Edward; McAllister, Kelly

2011-01-01

The goal of this study is to develop dielectric nanocomposites for high energy density applications at liquid nitrogen temperature by utilizing a unique nano-material polyhedral oligomeric silsesquioxanes (POSS). A POSS molecule is consisted of a silica cage core with 8 silicon and 12 oxygen atoms and organic functional groups attached to the corners of the cage. In this study, we utilize POSS for the fabrication of nanocomposites both as a silica nanoparticle filler to enhance the breakdown strength and as a surfactant for effective dispersion of high permittivity ceramic nanoparticles in a polymer matrix. The matrix materials selected for the study are polyvinylidene fluoride (PVDF) and poly(methyl methacrylate) (PMMA). The ceramic nanoparticles are barium strontium titanate (BST 50/50) and strontium titanate. The dielectric properties of the solution-cast nanocomposites films were correlated to the composition and processing conditions. We determined that the addition of POSS did not provide enhanced dielectric performance in PVDF- and PMMA-based materials at either room temperature or 77K. In addition, we found that the dielectric breakdown strength of PMMA is lower at 77K than at room temperature, contradicting literature data.

Mechanical property changes in porous low-k dielectric thin films during processing

Energy Technology Data Exchange (ETDEWEB)

Stan, G., E-mail: gheorghe.stan@nist.gov; Gates, R. S. [Material Measurement Laboratory, National Institute of Standards and Technology, Gaithersburg, Maryland 20899 (United States); Kavuri, P. [Physical Measurement Laboratory, National Institute of Standards and Technology, Gaithersburg, Maryland 20899 (United States); Torres, J.; Michalak, D.; Ege, C.; Bielefeld, J.; King, S. W. [Logic Technology Development, Intel Corporation, Hillsboro, Oregon 97124 (United States)

2014-10-13

The design of future generations of Cu-low-k dielectric interconnects with reduced electronic crosstalk often requires engineering materials with an optimal trade off between their dielectric constant and elastic modulus. This is because the benefits associated with the reduction of the dielectric constant by increasing the porosity of materials, for example, can adversely affect their mechanical integrity during processing. By using load-dependent contact-resonance atomic force microscopy, the changes in the elastic modulus of low-k dielectric materials due to processing were accurately measured. These changes were linked to alterations sustained by the structure of low-k dielectric films during processing. A two-phase model was used for quantitative assessments of the elastic modulus changes undergone by the organosilicate skeleton of the structure of porous and pore-filled dielectrics.

Demonstration of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with silicon-oxy-nitride as the gate insulator

International Nuclear Information System (INIS)

Balachander, K.; Arulkumaran, S.; Egawa, T.; Sano, Y.; Baskar, K.

2005-01-01

AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs) were fabricated with plasma enhanced chemical vapor deposited silicon oxy-nitride (SiON) as an insulating layer. The compositions of SiON thin films were confirmed using X-ray photoelectron spectroscopy. The fabricated MOSHEMTs exhibited a very high saturation current density of 1.1 A/mm coupled with high positive operational gate voltage up to +7 V. The MOSHEMTs also exhibited four orders of low gate leakage current and high forward-on voltage when compared with the conventional HEMTs. The drain current collapse using gate pulse measurements showed only a negligible difference in the saturation current density revealing the drastic improvement in passivation of the surface states due to the high quality of dielectric thin films deposited. Thus, based on the improved direct-current operation, SiON can be considered to be a potential gate oxide comparable with other dielectric insulators

Elastic properties of porous low-k dielectric nano-films

Science.gov (United States)

Zhou, W.; Bailey, S.; Sooryakumar, R.; King, S.; Xu, G.; Mays, E.; Ege, C.; Bielefeld, J.

2011-08-01

Low-k dielectrics have predominantly replaced silicon dioxide as the interlayer dielectric for interconnects in state of the art integrated circuits. In order to further reduce interconnect RC delays, additional reductions in k for these low-k materials are being pursued via the introduction of controlled levels of porosity. The main challenge for such dielectrics is the substantial reduction in elastic properties that accompanies the increased pore volume. We report on Brillouin light scattering measurements used to determine the elastic properties of these films at thicknesses well below 200 nm, which are pertinent to their introduction into present ultralarge scale integrated technology. The observation of longitudinal and transverse standing wave acoustic resonances and their transformation into traveling waves with finite in-plane wave vectors provides for a direct non-destructive measure of the principal elastic constants that characterize the elastic properties of these porous nano-scale films. The mode dispersion further confirms that for porosity levels of up to 25%, the reduction in the dielectric constant does not result in severe degradation in the Young's modulus and Poisson's ratio of the films.

Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure.

Directory of Open Access Journals (Sweden)

Z N Khan

Full Text Available Metal Oxide Semiconductor (MOS capacitors (MOSCAP have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer, time-temperature cycle and sequence are key parameters influencing the device's output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

Science.gov (United States)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-01

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

Science.gov (United States)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-17

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

AlN and Al oxy-nitride gate dielectrics for reliable gate stacks on Ge and InGaAs channels

Energy Technology Data Exchange (ETDEWEB)

Guo, Y.; Li, H.; Robertson, J. [Engineering Department, Cambridge University, Cambridge CB2 1PZ (United Kingdom)

2016-05-28

AlN and Al oxy-nitride dielectric layers are proposed instead of Al{sub 2}O{sub 3} as a component of the gate dielectric stacks on higher mobility channels in metal oxide field effect transistors to improve their positive bias stress instability reliability. It is calculated that the gap states of nitrogen vacancies in AlN lie further away in energy from the semiconductor band gap than those of oxygen vacancies in Al{sub 2}O{sub 3}, and thus AlN might be less susceptible to charge trapping and have a better reliability performance. The unfavourable defect energy level distribution in amorphous Al{sub 2}O{sub 3} is attributed to its larger coordination disorder compared to the more symmetrically bonded AlN. Al oxy-nitride is also predicted to have less tendency for charge trapping.

Interface Engineering for Atomic Layer Deposited Alumina Gate Dielectric on SiGe Substrates.

OpenAIRE

Zhang, L; Guo, Y; Hassan, VV; Tang, K; Foad, MA; Woicik, JC; Pianetta, P; Robertson, John; McIntyre, PC

2016-01-01

Optimization of the interface between high-k dielectrics and SiGe substrates is a challenging topic due to the complexity arising from the coexistence of Si and Ge interfacial oxides. Defective high-k/SiGe interfaces limit future applications of SiGe as a channel material for electronic devices. In this paper, we identify the surface layer structure of as-received SiGe and Al2O3/SiGe structures based on soft and hard X-ray photoelectron spectroscopy. As-received SiGe substrates have native Si...

Dielectric Modulated FET (DMFET)

Indian Academy of Sciences (India)

First page Back Continue Last page Graphics. Working Principle: Change in Dielectric constant due to immobilization of biomolecules in the nanogap cavity leads to change in effective gate capacitance and thus gate bias for FET. Working Principle: Change in Dielectric constant due to immobilization of biomolecules in the ...

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO₂ Gate Dielectrics by CF₄ Plasma Treatment.

Science.gov (United States)

Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

2018-05-17

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO₂ gate insulator and CF₄ plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO₂ gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm²/V∙s (without treatment) to 54.6 cm²/V∙s (with CF₄ plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO₂ gate dielectric has also been improved by the CF₄ plasma treatment. By applying the CF₄ plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device's immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF₄ plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO₂ gate dielectric, but also enhances the device's reliability.

A novel approach for the improvement of electrostatic behaviour of physically doped TFET using plasma formation and shortening of gate electrode with hetero-gate dielectric

Science.gov (United States)

Soni, Deepak; Sharma, Dheeraj; Aslam, Mohd.; Yadav, Shivendra

2018-04-01

This article presents a new device configuration to enhance current drivability and suppress negative conduction (ambipolar conduction) with improved RF characteristics of physically doped TFET. Here, we used a new approach to get excellent electrical characteristics of hetero-dielectric short gate source electrode TFET (HD-SG SE-TFET) by depositing a metal electrode of 5.93 eV work function over the heavily doped source (P+) region. Deposition of metal electrode induces the plasma (thin layer) of holes under the Si/HfO2 interface due to work function difference of metal and semiconductor. Plasma layer of holes is advantageous to increase abruptness as well as decrease the tunneling barrier at source/channel junction for attaining higher tunneling rate of charge carriers (i.e., electrons), which turns into 86.66 times higher ON-state current compared with the conventional physically doped TFET (C-TFET). Along with metal electrode deposition, gate electrode is under-lapped for inducing asymmetrical concentration of charge carriers in the channel region, which is helpful for widening the tunneling barrier width at the drain/channel interface. Consequently, HD-SG SE-TFET shows suppression of ambipolar behavior with reduction in gate-to-drain capacitance which is beneficial for improvement in RF performance. Furthermore, the effectiveness of hetero-gate dielectric concept has been used for improving the RF performance. Furthermore, reliability of C-TFET and proposed structures has been confirmed in term of linearity.

Negative differential transconductance in electrolyte-gated ruthenate

International Nuclear Information System (INIS)

Hassan, Muhammad Umair; Dhoot, Anoop Singh; Wimbush, Stuart C.

2015-01-01

We report on a study of electric field-induced doping of the highly conductive ruthenate SrRuO 3 using an ionic liquid as the gate dielectric in a field-effect transistor configuration. Two distinct carrier transport regimes are identified for increasing positive gate voltage in thin (10 nm) films grown heteroepitaxially on SrTiO 3 substrates. For V g  = 2 V and lower, the sample shows an increased conductivity of up to 13%, as might be expected for electron doping of a metal. At higher V g  = 2.5 V, we observe a large decrease in electrical conductivity of >20% (at 4.2 K) due to the prevalence of strongly blocked conduction pathways

Negative differential transconductance in electrolyte-gated ruthenate

Energy Technology Data Exchange (ETDEWEB)

Hassan, Muhammad Umair [Cavendish Laboratory, University of Cambridge, J J Thomson Avenue, Cambridge CB3 0HE (United Kingdom); Center for Micro and Nano Devices, Department of Physics, COMSATS Institute of Information Technology, Park Road, Shehzad Town 44000, Islamabad (Pakistan); Dhoot, Anoop Singh, E-mail: asd24@cam.ac.uk [Cavendish Laboratory, University of Cambridge, J J Thomson Avenue, Cambridge CB3 0HE (United Kingdom); Wimbush, Stuart C. [Department of Materials Science and Metallurgy, University of Cambridge, 27 Charles Babbage Road, Cambridge CB3 0FS (United Kingdom); The MacDiarmid Institute for Advanced Materials and Nanotechnology, Victoria University of Wellington, P.O. Box 600, Wellington 6140 (New Zealand)

2015-01-19

We report on a study of electric field-induced doping of the highly conductive ruthenate SrRuO{sub 3} using an ionic liquid as the gate dielectric in a field-effect transistor configuration. Two distinct carrier transport regimes are identified for increasing positive gate voltage in thin (10 nm) films grown heteroepitaxially on SrTiO{sub 3} substrates. For V{sub g} = 2 V and lower, the sample shows an increased conductivity of up to 13%, as might be expected for electron doping of a metal. At higher V{sub g} = 2.5 V, we observe a large decrease in electrical conductivity of >20% (at 4.2 K) due to the prevalence of strongly blocked conduction pathways.

Low voltage operation of IGZO thin film transistors enabled by ultrathin Al2O3 gate dielectric

Science.gov (United States)

Ma, Pengfei; Du, Lulu; Wang, Yiming; Jiang, Ran; Xin, Qian; Li, Yuxiang; Song, Aimin

2018-01-01

An ultrathin, 5 nm, Al2O3 film grown by atomic-layer deposition was used as a gate dielectric for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The Al2O3 layer showed a low surface roughness of 0.15 nm, a low leakage current, and a high breakdown voltage of 6 V. In particular, a very high gate capacitance of 720 nF/cm2 was achieved, making it possible for the a-IGZO TFTs to not only operate at a low voltage of 1 V but also exhibit desirable properties including a low threshold voltage of 0.3 V, a small subthreshold swing of 100 mV/decade, and a high on/off current ratio of 1.2 × 107. Furthermore, even under an ultralow operation voltage of 0.6 V, well-behaved transistor characteristics were still observed with an on/off ratio as high as 3 × 106. The electron transport through the Al2O3 layer has also been analyzed, indicating the Fowler-Nordheim tunneling mechanism.

Improved linearity and reliability in GaN metal-oxide-semiconductor high-electron-mobility transistors using nanolaminate La2O3/SiO2 gate dielectric

Science.gov (United States)

Hsu, Ching-Hsiang; Shih, Wang-Cheng; Lin, Yueh-Chin; Hsu, Heng-Tung; Hsu, Hisang-Hua; Huang, Yu-Xiang; Lin, Tai-Wei; Wu, Chia-Hsun; Wu, Wen-Hao; Maa, Jer-Shen; Iwai, Hiroshi; Kakushima, Kuniyuki; Chang, Edward Yi

2016-04-01

Improved device performance to enable high-linearity power applications has been discussed in this study. We have compared the La2O3/SiO2 AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with other La2O3-based (La2O3/HfO2, La2O3/CeO2 and single La2O3) MOS-HEMTs. It was found that forming lanthanum silicate films can not only improve the dielectric quality but also can improve the device characteristics. The improved gate insulation, reliability, and linearity of the 8 nm La2O3/SiO2 MOS-HEMT were demonstrated.

Gated viewing and high-accuracy three-dimensional laser radar

DEFF Research Database (Denmark)

Busck, Jens; Heiselberg, Henning

2004-01-01

, a high PRF of 32 kHz, and a high-speed camera with gate times down to 200 ps and delay steps down to 100 ps. The electronics and the software also allow for gated viewing with automatic gain control versus range, whereby foreground backscatter can be suppressed. We describe our technique for the rapid...

High performance organic field-effect transistors with ultra-thin HfO2 gate insulator deposited directly onto the organic semiconductor

International Nuclear Information System (INIS)

Ono, S.; Häusermann, R.; Chiba, D.; Shimamura, K.; Ono, T.; Batlogg, B.

2014-01-01

We have produced stable organic field-effect transistors (OFETs) with an ultra-thin HfO 2 gate insulator deposited directly on top of rubrene single crystals by atomic layer deposition (ALD). We find that ALD is a gentle deposition process to grow thin films without damaging rubrene single crystals, as results these devices have a negligibly small threshold voltage and are very stable against gate-bias-stress, and the mobility exceeds 1 cm 2 /V s. Moreover, the devices show very little degradation even when kept in air for more than 2 months. These results demonstrate thin HfO 2 layers deposited by ALD to be well suited as high capacitance gate dielectrics in OFETs operating at small gate voltage. In addition, the dielectric layer acts as an effective passivation layer to protect the organic semiconductor

Multibit C_kNOT quantum gates via Rydberg blockade

DEFF Research Database (Denmark)

Isenhower, L.; Saffman, Mark; Mølmer, Klaus

2011-01-01

Long range Rydberg blockade interactions have the potential for efficient implementation of quantum gates between multiple atoms. Here we present and analyze a protocol for implementation of a k-atom controlled NOT (CkNOT) neutral atom gate. This gate can be implemented using sequential or simult......Long range Rydberg blockade interactions have the potential for efficient implementation of quantum gates between multiple atoms. Here we present and analyze a protocol for implementation of a k-atom controlled NOT (CkNOT) neutral atom gate. This gate can be implemented using sequential...... or simultaneous addressing of the control atoms which requires only 2k + 3 or 5 Rydberg π pulses respectively. A detailed error analysis relevant for implementations based on alkali atom Rydberg states is provided which shows that gate errors less than 10% are possible for k = 35....

Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors.

Science.gov (United States)

Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

2016-12-01

In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade(-1) and 3.62 × 10(11) eV(-1) cm(-2), respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

Low operating voltage InGaZnO thin-film transistors based on Al{sub 2}O{sub 3} high-k dielectrics fabricated using pulsed laser deposition

Energy Technology Data Exchange (ETDEWEB)

Geng, G. Z.; Liu, G. X.; Zhang, Q.; Shan, F. K. [Qingdao University, Qingdao (China); DongEui University, Busan (Korea, Republic of); Lee, W. J.; Shin, B. C. [DongEui University, Busan (Korea, Republic of); Cho, C. R. [Pusan National University, Busan (Korea, Republic of)

2014-05-15

Low-voltage-driven amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) with an Al{sub 2}O{sub 3} dielectric were fabricated on a Si substrate by using pulsed laser deposition. Both Al{sub 2}O{sub 3} and IGZO thin films are amorphous, and the thin films have very smooth surfaces. The Al{sub 2}O{sub 3} gate dielectric exhibits a very low leakage current density of 1.3 x 10{sup -8} A/cm{sup 2} at 5 V and a high capacitance density of 60.9 nF/cm{sup 2}. The IGZO TFT with a structure of Ni/IGZO/Al{sub 2}O{sub 3}/Si exhibits high performance with a low threshold voltage of 1.18 V, a high field effect mobility of 20.25 cm{sup 2}V{sup -1}s{sup -1}, an ultra small subthreshold swing of 87 mV/decade, and a high on/off current ratio of 3 x 10{sup 7}.

Inverse agonist-like action of cadmium on G-protein-gated inward-rectifier K+ channels

International Nuclear Information System (INIS)

Inanobe, Atsushi; Matsuura, Takanori; Nakagawa, Atsushi; Kurachi, Yoshihisa

2011-01-01

Highlights: → We examined allosteric control of K + channel gating. → We identified a high-affinity site for Cd 2+ to inhibit Kir3.2 activity. → The 6-coordination geometry supports the binding. → Cd 2+ inhibits Kir3.2 by trapping the conformation in the closed state. -- Abstract: The gate at the pore-forming domain of potassium channels is allosterically controlled by a stimulus-sensing domain. Using Cd 2+ as a probe, we examined the structural elements responsible for gating in an inward-rectifier K + channel (Kir3.2). One of four endogenous cysteines facing the cytoplasm contributes to a high-affinity site for inhibition by internal Cd 2+ . Crystal structure of its cytoplasmic domain in complex with Cd 2+ reveals that octahedral coordination geometry supports the high-affinity binding. This mode of action causes the tethering of the N-terminus to CD loop in the stimulus-sensing domain, suggesting that their conformational changes participate in gating and Cd 2+ inhibits Kir3.2 by trapping the conformation in the closed state like 'inverse agonist'.

Synthesis and Characterization of High-Dielectric-Constant Nanographite-Polyurethane Composite

Science.gov (United States)

Mishra, Praveen; Bhat, Badekai Ramachandra; Bhattacharya, B.; Mehra, R. M.

2018-05-01

In the face of ever-growing demand for capacitors and energy storage devices, development of high-dielectric-constant materials is of paramount importance. Among various dielectric materials available, polymer dielectrics are preferred for their good processability. We report herein synthesis and characterization of nanographite-polyurethane composite with high dielectric constant. Nanographite showed good dispersibility in the polyurethane matrix. The thermosetting nature of polyurethane gives the composite the ability to withstand higher temperature without melting. The resultant composite was studied for its dielectric constant (ɛ) as a function of frequency. The composite exhibited logarithmic variation of ɛ from 3000 at 100 Hz to 225 at 60 kHz. The material also exhibited stable dissipation factor (tan δ) across the applied frequencies, suggesting its ability to resist current leakage.

SEMICONDUCTOR TECHNOLOGY: Wet etching characteristics of a HfSiON high-k dielectric in HF-based solutions

Science.gov (United States)

Yongliang, Li; Qiuxia, Xu

2010-03-01

The wet etching properties of a HfSiON high-k dielectric in HF-based solutions are investigated. HF-based solutions are the most promising wet chemistries for the removal of HfSiON, and etch selectivity of HF-based solutions can be improved by the addition of an acid and/or an alcohol to the HF solution. Due to densification during annealing, the etch rate of HfSiON annealed at 900 °C for 30 s is significantly reduced compared with as-deposited HfSiON in HF-based solutions. After the HfSiON film has been completely removed by HF-based solutions, it is not possible to etch the interfacial layer and the etched surface does not have a hydrophobic nature, since N diffuses to the interface layer or Si substrate formation of Si-N bonds that dissolves very slowly in HF-based solutions. Existing Si-N bonds at the interface between the new high-k dielectric deposit and the Si substrate may degrade the carrier mobility due to Coulomb scattering. In addition, we show that N2 plasma treatment before wet etching is not very effective in increasing the wet etch rate for a thin HfSiON film in our case.

Future directions of positron annihilation spectroscopy in low-k dielectric films

International Nuclear Information System (INIS)

Gidley, D.W.; Vallery, R.S.; Liu, M.; Peng, H.G.

2007-01-01

Positronium Annihilation Lifetime Spectroscopy (PALS) has become recognized in the microelectronics industry as one of only several methods capable of quantitatively characterizing engineered nanopores in next-generation (k < 2.2) interlayer dielectric (ILD) thin films. Successes and shortcomings of PALS to date will be assessed and compared with other methods of porosimetry such as ellipsometric and X-ray porosimetries (EP and XRP). A major theme in future low-k research focuses on the ability to integrate porous ILD's into chip fabrication; the vulnerability of porous dielectrics to etching, ashing, and chemical-mechanical polishing in process integration is delaying the introduction of ultra-low-k films. As device size approaches 45 nm the need to probe very small (sub-nanometer), semi-isolated pores beneath thin diffusion barriers is even more challenging. Depth-profiled PALS with its ability to determine a quantitative pore interconnection length and easily resolve 0.3 nm pores beneath diffusion barriers or in trench-patterned dielectrics should have a bright future in porous ILD research. The ability of PALS (and PAS in general) to deduce evolution and growth of pores with porosity should find broad applicability in the emerging field of high performance materials with strategically engineered nanopores. (copyright 2007 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

High permittivity materials for oxide gate stack in Ge-based metal oxide semiconductor capacitors

Energy Technology Data Exchange (ETDEWEB)

Molle, Alessandro, E-mail: alessandro.molle@mdm.infm.i [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Baldovino, Silvia [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano Bicocca, Milano (Italy); Spiga, Sabina [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Fanciulli, Marco [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano Bicocca, Milano (Italy)

2010-01-01

In the effort to ultimately shrink the size of logic devices towards a post-Si era, the integration of Ge as alternative channel material for high-speed p-MOSFET devices and the concomitant coupling with high permittivity dielectrics (high-k) as gate oxides is currently a key-challenge in microelectronics. However, the Ge option still suffers from a number of unresolved drawbacks and open issues mainly related to the thermodynamic and electrical compatibility of Ge substrates with high-k gate stack. Strictly speaking, two main concerns can be emphasized. On one side is the dilemma on which chemical/physical passivation is more suitable to minimize the unavoidable presence of electrically active defects at the oxide/semiconductor interface. On the other side, overcoming the SiO{sub 2} gate stack opens the route to a number of potentially outperforming high-k oxides. Two deposition approaches were here separately adopted to investigate the high-k oxide growth on Ge substrates, the molecular beam deposition (MBD) of Gd{sub 2}O{sub 3} and the atomic layer deposition (ALD) of HfO{sub 2}. In the MBD framework epitaxial and amorphous Gd{sub 2}O{sub 3} films were grown onto GeO{sub 2}-passivated Ge substrates. In this case, Ge passivation was achieved by exploiting the Ge{sup 4+} bonding state in GeO{sub 2} ultra-thin interface layers intentionally deposited in between Ge and the high-k oxide by means of atomic oxygen exposure to Ge. The composition of the interface layer has been characterized as a function of the oxidation temperature and evidence of Ge dangling bonds at the GeO{sub 2}/Ge interface has been reported. Finally, the electrical response of MOS capacitors incorporating Gd{sub 2}O{sub 3} and GeO{sub 2}-passivated Ge substrates has been checked by capacitance-voltage measurements. On the other hand, the structural and electrical properties of HfO{sub 2} films grown by ALD on Ge by using different oxygen precursors, i.e. H{sub 2}O, Hf(O{sup t}Bu){sub 2}(mmp

Emerging Applications for High K Materials in VLSI Technology

Science.gov (United States)

Clark, Robert D.

2014-01-01

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. PMID:28788599

Emerging Applications for High K Materials in VLSI Technology

Directory of Open Access Journals (Sweden)

Robert D. Clark

2014-04-01

Full Text Available The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI manufacturing for leading edge Dynamic Random Access Memory (DRAM and Complementary Metal Oxide Semiconductor (CMOS applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.

Influence of ultra-thin TiN thickness (1.4 nm and 2.4 nm) on positive bias temperature instability (PBTI) of high-k/metal gate nMOSFETs with gate-last process

International Nuclear Information System (INIS)

Qi Lu-Wei; Yang Hong; Ren Shang-Qing; Xu Ye-Feng; Luo Wei-Chun; Xu Hao; Wang Yan-Rong; Tang Bo; Wang Wen-Wu; Yan Jiang; Zhu Hui-Long; Zhao Chao; Chen Da-Peng; Ye Tian-Chun

2015-01-01

The positive bias temperature instability (PBTI) degradations of high-k/metal gate (HK/MG) nMOSFETs with thin TiN capping layers (1.4 nm and 2.4 nm) are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI (90 °C, 125 °C, 160 °C) are studied and activation energy (E a ) values (0.13 eV and 0.15 eV) are extracted. Although the equivalent oxide thickness (EOT) values of two TiN thickness values are almost similar (0.85 nm and 0.87 nm), the 2.4-nm TiN one (thicker TiN capping layer) shows better PBTI reliability (13.41% at 0.9 V, 90 °C, 1000 s). This is due to the better interfacial layer/high-k (IL/HK) interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer. (paper)

Physical and electrical characteristics of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with rare earth Er2O3 as a gate dielectric

International Nuclear Information System (INIS)

Lin, Ray-Ming; Chu, Fu-Chuan; Das, Atanu; Liao, Sheng-Yu; Chou, Shu-Tsun; Chang, Liann-Be

2013-01-01

In this study, the rare earth erbium oxide (Er 2 O 3 ) was deposited using an electron beam onto an AlGaN/GaN heterostructure to fabricate metal-oxide-semiconductor high-electron-mobility transistors (MOS–HEMTs) that exhibited device performance superior to that of a conventional HEMT. Under similar bias conditions, the gate leakage currents of these MOS–HEMT devices were four orders of magnitude lower than those of conventional Schottky gate HEMTs. The measured sub-threshold swing (SS) and the effective trap state density (N t ) of the MOS–HEMT were 125 mV/decade and 4.3 × 10 12 cm −2 , respectively. The dielectric constant of the Er 2 O 3 layer in this study was 14, as determined through capacitance–voltage measurements. In addition, the gate–source reverse breakdown voltage increased from –166 V for the conventional HEMT to –196 V for the Er 2 O 3 MOS–HEMT. - Highlights: ► GaN/AlGaN/Er 2 O 3 metal-oxide semiconductor high electron mobility transistor ► Physical and electrical characteristics are presented. ► Electron beam evaporated Er 2 O 3 with excellent surface roughness ► Device exhibits reduced gate leakage current and improved I ON /I OFF ratio

Nanocomposites of TiO2/cyanoethylated cellulose with ultra high dielectric constants

International Nuclear Information System (INIS)

Madusanka, Nadeesh; Shivareddy, Sai G; Hiralal, Pritesh; Choi, Youngjin; Amaratunga, Gehan A J; Eddleston, Mark D; Oliver, Rachel A

2016-01-01

A novel dielectric nanocomposite containing a high permittivity polymer, cyanoethylated cellulose (CRS) and TiO 2 nanoparticles was successfully prepared with different weight percentages (10%, 20% and 30%) of TiO 2 . The intermolecular interactions and morphology within the polymer nanocomposites were analysed. TiO 2 /CRS nanofilms on SiO 2 /Si wafers were used to form metal–insulator–metal type capacitors. Capacitances and loss factors in the frequency range of 1 kHz–1 MHz were measured. At 1 kHz CRS-TiO 2 nanocomposites exhibited ultra high dielectric constants of 118, 176 and 207 for nanocomposites with 10%, 20% and 30% weight of TiO 2 respectively, significantly higher than reported values of pure CRS (21), TiO 2 (41) and other dielectric polymer-TiO 2 nanocomposite films. Furthermore, all three CRS-TiO 2 nanocomposites show a loss factor <0.3 at 1 kHz and low leakage current densities (10 −6 –10 −7 A cm −2 ). Leakage was studied using conductive atomic force microscopy and it was observed that the leakage is associated with TiO 2 nanoparticles embedded in the CRS polymer matrix. A new class of ultra high dielectric constant hybrids using nanoscale inorganic dielectrics dispersed in a high permittivity polymer suitable for energy management applications is reported. (paper)

Thermal Experimental Analysis for Dielectric Characterization of High Density Polyethylene Nanocomposites

Directory of Open Access Journals (Sweden)

Ahmed Thabet Mohamed

2016-01-01

Full Text Available The importance of nanoparticles in controlling physical properties of polymeric nanocomposite materials leads us to study effects of these nanoparticles on electric and dielectric properties of polymers in industry In this research, the dielectric behaviour of High-Density Polyethylene (HDPE nanocomposites materials that filled with nanoparticles of clay or fumed silica has been investigated at various frequencies (10 Hz-1 kHz and temperatures (20-60°C. Dielectric spectroscopy has been used to characterize ionic conduction, then, the effects of nanoparticles concentration on the dielectric losses and capacitive charge of the new nanocomposites can be stated. Capacitive charge and loss tangent in high density polyethylene nanocomposites are measured by dielectric spectroscopy. Different dielectric behaviour has been observed depending on type and concentration of nanoparticles under variant thermal conditions.

Microwave dielectric study of polar liquids at 298 K

Science.gov (United States)

Maharolkar, Aruna P.; Murugkar, A.; Khirade, P. W.

2018-05-01

Present paper deals with study of microwave dielectric properties like dielectric constant, viscosity, density and refractive index for the binary mixtures of Dimethylsulphoxide (DMSO) and Methanol over the entire concentration range were measured at 298K. The experimental data further used to determine the excess properties viz. excess static dielectric constant, excess molar volume, excess viscosity& derived properties viz. molar refraction&Bruggman factor. The values of excess properties further fitted with Redlich-Kister (R-K Fit) equation to calculate the binary coefficients and standard deviation. The resulting excess parameters are used to indicate the presence of intermolecular interactions and strength of intermolecular interactions between the molecules in the binary mixtures. Excess parameters indicate structure breaking factor in the mixture predominates in the system.

Structure and performance of dielectric films based on self-assembled nanocrystals with a high dielectric constant.

Science.gov (United States)

Huang, Limin; Liu, Shuangyi; Van Tassell, Barry J; Liu, Xiaohua; Byro, Andrew; Zhang, Henan; Leland, Eli S; Akins, Daniel L; Steingart, Daniel A; Li, Jackie; O'Brien, Stephen

2013-10-18

Self-assembled films built from nanoparticles with a high dielectric constant are attractive as a foundation for new dielectric media with increased efficiency and range of operation, due to the ability to exploit nanofabrication techniques and emergent electrical properties originating from the nanoscale. However, because the building block is a discrete one-dimensional unit, it becomes a challenge to capture potential enhancements in dielectric performance in two or three dimensions, frequently due to surface effects or the presence of discontinuities. This is a recurring theme in nanoparticle film technology when applied to the realm of thin film semiconductor and device electronics. We present the use of chemically synthesized (Ba,Sr)TiO3 nanocrystals, and a novel deposition-polymerization technique, as a means to fabricate the dielectric layer. The effective dielectric constant of the film is tunable according to nanoparticle size, and effective film dielectric constants of up to 34 are enabled. Wide area and multilayer dielectrics of up to 8 cm(2) and 190 nF are reported, for which the building block is an 8 nm nanocrystal. We describe models for assessing dielectric performance, and distinct methods for improving the dielectric constant of a nanocrystal thin film. The approach relies on evaporatively driven assembly of perovskite nanocrystals with uniform size distributions in a tunable 7-30 nm size range, coupled with the use of low molecular weight monomer/polymer precursor chemistry that can infiltrate the porous nanocrystal thin film network post assembly. The intercrystal void space (low k dielectric volume fraction) is minimized, while simultaneously promoting intercrystal connectivity and maximizing volume fraction of the high k dielectric component. Furfuryl alcohol, which has good affinity to the surface of (Ba,Sr)TiO3 nanocrystals and miscibility with a range of solvents, is demonstrated to be ideal for the production of nanocomposites. The

Physical and electrical properties of bilayer CeO{sub 2}/TiO{sub 2} gate dielectric stack

Energy Technology Data Exchange (ETDEWEB)

Chong, M.M.V. [School of Materials Science and Engineering, Nanyang Technological University of Singapore, Block N 4.1Nanyang Avenue, Singapore 639798 (Singapore); GlobalFoundries Singapore Private Limited, 60 Woodlands Industrial Park D Street 2, Singapore 738406 (Singapore); Lee, P.S. [School of Materials Science and Engineering, Nanyang Technological University of Singapore, Block N 4.1Nanyang Avenue, Singapore 639798 (Singapore); Tok, A.I.Y., E-mail: MIYTOK@ntu.edu.sg [School of Materials Science and Engineering, Nanyang Technological University of Singapore, Block N 4.1Nanyang Avenue, Singapore 639798 (Singapore)

2016-08-15

Highlights: • A bilayer gate dielectric stack of CeO{sub 2}/TiO{sub 2} to study the dependency of film growth with varying annealing temperatures is proposed. • The study demonstrates CeO{sub 2}/TiO{sub 2} bilayer stack with comparable κ-value as that of HfO{sub 2} but with reduced leakage current density of 4 orders of magnitude. • Schottky emission is the dominant leakage conduction mechanism of annealed CeO{sub 2}/TiO{sub 2} stack due to thermionic effect of interface properties. - Abstract: This study demonstrates a bilayer gate oxide structure of cerium oxide deposited via pulsed laser deposition and titanium oxide using conventional atomic layer deposition. Samples were deposited on p-type Si (100) substrate and exhibit interesting physical and electrical properties such that 600 °C annealed CeO{sub 2}/TiO{sub 2} samples having κ-value of 18 whereas pure CeO{sub 2} deposited samples have dielectric constant of 17.1 with leakage current density of 8.94 × 10{sup −6} A/cm{sup 2} at 1 V applied voltage. The result shows promising usage of the synthesized rare earth oxides as gate dielectric where ideal κ-value and significant reduction of the leakage current by 5 orders of magnitude is achieved. Leakage current conduction mechanism for as-deposited sample is found to be dominated by Poole–Frenkel (PF) emission; the trap level is found to be at 1.29 eV whereas annealed samples (600 °C and 800 °C) exhibited Schottky emission with trap levels at 1.45 eV and 0.81 eV, respectively.

Transfer-Free Fabrication of Graphene Scaffolds on High-k Dielectrics from Metal-Organic Oligomers.

Science.gov (United States)

Pang, Qingqing; Wang, Deyan; Wang, Xiuyan; Feng, Shaoguang; Clark, Michael B; Li, Qiaowei

2016-09-28

In situ fabrication of graphene scaffold-ZrO2 nanofilms is achieved by thermal annealing of Zr-based metal-organic oligomers on SiO2 substrates. The structural similarities of the aromatic moieties in the ligand (phenyl-, naphthyl-, anthryl-, and pyrenyl-) compared to graphene play a major role in the ordering of the graphene scaffolds obtained. The depth profiling analysis reveals ultrathin carbon-pure or carbon-rich surfaces of the graphene scaffold-ZrO2 nanofilms. The graphene scaffolds with ∼96.0% transmittance in the visible region and 4.8 nm in thickness can be grown with this non-chemical vapor deposition method. Furthermore, the heterogeneous graphene scaffold-ZrO2 nanofilms show a low sheet resistance of 17.0 kΩ per square, corresponding to electrical conductivity of 3197 S m(-1). The strategy provides a facile method to fabricate graphene scaffolds directly on high-k dielectrics without transferring process, paving the way for its application in fabricating electronic devices.

Sterol Regulation of Voltage-Gated K+ Channels.

Science.gov (United States)

Balajthy, Andras; Hajdu, Peter; Panyi, Gyorgy; Varga, Zoltan

2017-01-01

Cholesterol is an essential lipid building block of the cellular plasma membrane. In addition to its structural role, it regulates the fluidity and raft structure of the membrane and influences the course of numerous membrane-linked signaling pathways and the function of transmembrane proteins, including ion channels. This is supported by a vast body of scientific data, which demonstrates the modulation of ion channels with a great variety of ion selectivity, gating, and tissue distribution by changes in membrane cholesterol. Here, we review what is currently known about the modulation of voltage-gated K + (Kv) channels by changes in membrane cholesterol content, considering raft association of the channels, the roles of cholesterol recognition sites, and those of adaptor proteins in cholesterol-Kv channel interactions. We specifically focus on Kv1.3, the dominant K + channel of human T cells. Effects of cholesterol depletion and enrichment and 7-dehydrocholesterol enrichment on Kv1.3 gating are discussed in the context of the immunological synapse and the comparison of the in vitro effects of sterol modifications on Kv1.3 function with ex vivo effects on cells from hypercholesterolemic and Smith-Lemli-Opitz patients. © 2017 Elsevier Inc. All rights reserved.

Energy-band alignment of (HfO2)x(Al2O3)1-x gate dielectrics deposited by atomic layer deposition on β-Ga2O3 (-201)

Science.gov (United States)

Yuan, Lei; Zhang, Hongpeng; Jia, Renxu; Guo, Lixin; Zhang, Yimen; Zhang, Yuming

2018-03-01

Energy band alignments between series band of Al-rich high-k materials (HfO2)x(Al2O3)1-x and β-Ga2O3 are investigated using X-Ray Photoelectron Spectroscopy (XPS). The results exhibit sufficient conduction band offsets (1.42-1.53 eV) in (HfO2)x(Al2O3)1-x/β-Ga2O3. In addition, it is also obtained that the value of Eg, △Ec, and △Ev for (HfO2)x(Al2O3)1-x/β-Ga2O3 change linearly with x, which can be expressed by 6.98-1.27x, 1.65-0.56x, and 0.48-0.70x, respectively. The higher dielectric constant and higher effective breakdown electric field of (HfO2)x(Al2O3)1-x compared with Al2O3, coupled with sufficient barrier height and lower gate leakage makes it a potential dielectric for high voltage β-Ga2O3 power MOSFET, and also provokes interest in further investigation of HfAlO/β-Ga2O3 interface properties.

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO2 Gate Dielectrics by CF4 Plasma Treatment

Science.gov (United States)

Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

2018-01-01

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO2 gate insulator and CF4 plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO2 gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm2/V∙s (without treatment) to 54.6 cm2/V∙s (with CF4 plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO2 gate dielectric has also been improved by the CF4 plasma treatment. By applying the CF4 plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device’s immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF4 plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO2 gate dielectric, but also enhances the device’s reliability. PMID:29772767

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO2 Gate Dielectrics by CF4 Plasma Treatment

Directory of Open Access Journals (Sweden)

Ching-Lin Fan

2018-05-01

Full Text Available In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs with a HfO2 gate insulator and CF4 plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO2 gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm2/V∙s (without treatment to 54.6 cm2/V∙s (with CF4 plasma treatment, which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO2 gate dielectric has also been improved by the CF4 plasma treatment. By applying the CF4 plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device’s immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF4 plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO2 gate dielectric, but also enhances the device’s reliability.

Oligo- and polymeric FET devices: Thiophene-based active materials and their interaction with different gate dielectrics

International Nuclear Information System (INIS)

Porzio, W.; Destri, S.; Pasini, M.; Bolognesi, A.; Angiulli, A.; Di Gianvincenzo, P.; Natali, D.; Sampietro, M.; Caironi, M.; Fumagalli, L.; Ferrari, S.; Peron, E.; Perissinotti, F.

2006-01-01

Derivatives of both oligo- and polythiophene-based FET were recently considered for low cost electronic applications. In the device optimization, factors like redox reversibility of the molecule/polymer, electronic level compatibility with source/drain electrodes, packing closeness, and orientation versus the electrodes, can determine the overall performance. In addition, a gate insulator with a high dielectric constant, a low leakage current, and capability to promote ordering in the semiconductor is required to increase device performances and to lower the FET operating voltage. In this view, Al 2 O 3 appears a good candidate, although its widespread adoption is limited by the disorder that such oxide induces on the semiconductor with detrimental consequences on semiconductor electrical properties. In this contribution, an overview of recent results obtained on thiophene-derivative-based FET devices, fabricated by different growth techniques, and using both thermally grown SiO 2 and Al 2 O 3 from atomic layer deposition gate insulators will be reported and discussed with particular reference to organic solid state aggregation, morphology, and organic-inorganic interface

Effect of gate dielectrics on the performance of p-type Cu2O TFTs processed at room temperature

KAUST Repository

Al-Jawhari, Hala A.; Caraveo-Frescas, Jesus Alfonso

2013-01-01

/off ratio of around 44, threshold voltage equaling -0.62 V and a sub threshold swing of 1.64 V/dec. These values were obtained at a low operating voltage of -2V. The advantages of using STO as a gate dielectric relative to ATO are discussed. © (2014) Trans

Full Polymer Dielectric Elastomeric Actuators (DEA Functionalised with Carbon Nanotubes and High-K Ceramics

Directory of Open Access Journals (Sweden)

Tilo Köckritz

2016-09-01

Full Text Available Dielectric elastomer actuators (DEA are special devices which have a simple working and construction principle and outstanding actuation properties. The DEAs consist of a combination of different materials for the dielectric and electrode layers. The combination of these layers causes incompatibilities in their interconnections. Dramatic differences in the mechanical properties and bad adhesion of the layers are the principal causes for the reduction of the actuation displacement and strong reduction of lifetime. Common DEAs achieve actuation displacements of 2% and a durability of some million cycles. The following investigations represent a new approach to solving the problems of common systems. The investigated DEA consists of only one basic raw polymer, which was modified according to the required demands of each layer. The basic raw polymer was modified with single-walled carbon nanotubes or high-k ceramics, for example, lead magnesium niobate-lead titanate. The development of the full polymer DEA comprised the development of materials and technologies to realise a reproducible layer composition. It was proven that the full polymer actuator worked according to the theoretical rules. The investigated system achieved actuation displacements above 20% regarding thickness, outstanding interconnections at each layer without any failures, and durability above 3 million cycles without any indication of an impending malfunction.

Experimental and theoretical investigation of the effect of SiO2 content in gate dielectrics on work function shift induced by nanoscale capping layers

KAUST Repository

Caraveo-Frescas, J. A.; Wang, H.; Schwingenschlö gl, Udo; Alshareef, Husam N.

2012-01-01

The impact of SiO2 content in ultrathin gate dielectrics on the magnitude of the effective work function (EWF) shift induced by nanoscale capping layers has been investigated experimentally and theoretically. The magnitude of the effective work function shift for four different capping layers (AlN, Al2O3, La2O3, and Gd2O3) is measured as a function of SiO2 content in the gate dielectric. A nearly linear increase of this shift with SiO2 content is observed for all capping layers. The origin of this dependence is explained using density functional theory simulations.

Experimental and theoretical investigation of the effect of SiO2 content in gate dielectrics on work function shift induced by nanoscale capping layers

KAUST Repository

Caraveo-Frescas, J. A.

2012-09-10

The impact of SiO2 content in ultrathin gate dielectrics on the magnitude of the effective work function (EWF) shift induced by nanoscale capping layers has been investigated experimentally and theoretically. The magnitude of the effective work function shift for four different capping layers (AlN, Al2O3, La2O3, and Gd2O3) is measured as a function of SiO2 content in the gate dielectric. A nearly linear increase of this shift with SiO2 content is observed for all capping layers. The origin of this dependence is explained using density functional theory simulations.

Atomic layer deposition of dielectrics for carbon-based electronics

Energy Technology Data Exchange (ETDEWEB)

Kim, J., E-mail: jiyoung.kim@utdallas.edu; Jandhyala, S.

2013-11-01

Carbon based nanomaterials like nanotubes and graphene have emerged as future generation electronic materials for device applications because of their interesting properties such as high-mobility and ability to carry high-current densities compared to conventional semiconductor materials like silicon. Therefore, there is a need to develop techniques to integrate robust gate dielectrics with high-quality interfaces for these materials in order to attain maximum performance. To date, a variety of methods including physical vapor deposition, atomic layer deposition (ALD), physical assembly among others have been employed in order to integrate dielectrics for carbon nanotube and graphene based field-effect transistors. Owing to the difficulty in wetting pristine surfaces of nanotubes and graphene, most of the ALD methods require a seeding technique involving non-covalent functionalization of their surfaces in order to nucleate dielectric growth while maintaining their intrinsic properties. A comprehensive review regarding the various dielectric integration schemes for emerging devices and their limitations with respect to ALD based methods along with a future outlook is provided. - Highlights: • We introduce various dielectric integration schemes for carbon-based devices. • Physical vapor deposition methods tend to degrade device performance. • Atomic layer deposition on pristine surfaces of graphene and nanotube is difficult. • We review different seeding techniques for atomic layer deposition of dielectrics. • Compare the performance of graphene top-gate devices with different dielectrics.

Atomic layer deposition of dielectrics for carbon-based electronics

International Nuclear Information System (INIS)

Kim, J.; Jandhyala, S.

2013-01-01

Carbon based nanomaterials like nanotubes and graphene have emerged as future generation electronic materials for device applications because of their interesting properties such as high-mobility and ability to carry high-current densities compared to conventional semiconductor materials like silicon. Therefore, there is a need to develop techniques to integrate robust gate dielectrics with high-quality interfaces for these materials in order to attain maximum performance. To date, a variety of methods including physical vapor deposition, atomic layer deposition (ALD), physical assembly among others have been employed in order to integrate dielectrics for carbon nanotube and graphene based field-effect transistors. Owing to the difficulty in wetting pristine surfaces of nanotubes and graphene, most of the ALD methods require a seeding technique involving non-covalent functionalization of their surfaces in order to nucleate dielectric growth while maintaining their intrinsic properties. A comprehensive review regarding the various dielectric integration schemes for emerging devices and their limitations with respect to ALD based methods along with a future outlook is provided. - Highlights: • We introduce various dielectric integration schemes for carbon-based devices. • Physical vapor deposition methods tend to degrade device performance. • Atomic layer deposition on pristine surfaces of graphene and nanotube is difficult. • We review different seeding techniques for atomic layer deposition of dielectrics. • Compare the performance of graphene top-gate devices with different dielectrics

High-throughput identification of higher-κ dielectrics from an amorphous N2-doped HfO2–TiO2 library

International Nuclear Information System (INIS)

Chang, K.-S.; Lu, W.-C.; Wu, C.-Y.; Feng, H.-C.

2014-01-01

Highlights: • Amorphous N 2 -doped HfO 2 –TiO 2 libraries were fabricated using sputtering. • Structure and quality of the dielectric and interfacial layers were investigated. • κ (54), J L < 10 −6 A/cm 2 , and equivalent oxide thickness (1 nm) were identified. - Abstract: High-throughput sputtering was used to fabricate high-quality, amorphous, thin HfO 2 –TiO 2 and N 2 -doped HfO 2 –TiO 2 (HfON–TiON) gate dielectric libraries. Electron probe energy dispersive spectroscopy was used to investigate the structures, compositions, and qualities of the dielectric and interfacial layers of these libraries to determine their electrical properties. A κ value of approximately 54, a leakage current density <10 −6 A/cm 2 , and an equivalent oxide thickness of approximately 1 nm were identified in an HfON–TiON library within a composition range of 68–80 at.% Ti. This library exhibits promise for application in highly advanced metal–oxide–semiconductor (higher-κ) gate stacks

Structure and Properties of Epitaxial Dielectrics on gallium nitride

Science.gov (United States)

Wheeler, Virginia Danielle

GaN is recognized as a possible material for metal oxide semiconductor field effect transistors (MOSFETs) used in high temperature, high power and high speed electronic applications. However, high gate leakage and low device breakdown voltages limit their use in these applications. The use of high-kappa dielectrics, which have both a high permittivity (ε) and high band gap energy (Eg), can reduce the leakage current density that adversely affects MOS devices. La2O3 and Sc2O 3 are rare earth oxides with a large Eg (6.18 eV and 6.3 eV respectively) and a relatively high ε (27 and 14.1 respectively), which make them good candidates for enhancing MOSFET performance. Epitaxial growth of oxides is a possible approach to reducing leakage current and Fermi level pinning related to a high density of interface states for dielectrics on compound semiconductors. In this work, La2O3 and Sc2O 3 were characterized structurally and electronically as potential epitaxial gate dielectrics for use in GaN based MOSFETs. GaN surface treatments were examined as a means for additional interface passivation and influencing subsequent oxide formation. Potassium persulfate (K2(SO4)2) and potassium hydroxide (KOH) were explored as a way to achieve improved passivation and desired surface termination for GaN films deposited on sapphire substrates by metal organic chemical vapor deposition (MOCVD). X-ray photoelectron spectroscopy (XPS) showed that KOH left a nitrogen-rich interface, while K2(SO 4)2 left a gallium-rich interface, which provides a way to control surface oxide formation. K2(SO4)2 exhibited a shift in the O1s peak indicating the formation of a gallium-rich GaOx at the surface with decreased carbon contaminants. GaO x acts as a passivating layer prior to dielectric deposition, which resulted in an order of magnitude reduction in leakage current, a reduced hysteresis window, and an overall improvement in device performance. Furthermore, K2(SO4)2 resulted in an additional 0.4 eV of

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

Energy Technology Data Exchange (ETDEWEB)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina [Department of Materials Science and Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen D-91058 (Germany); Institute for Physical Chemistry, Universität Heidelberg, Heidelberg D-69120 (Germany); Miehler, Dominik [Department of Materials Science and Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen D-91058 (Germany); Zaumseil, Jana, E-mail: zaumseil@uni-heidelberg.de [Institute for Physical Chemistry, Universität Heidelberg, Heidelberg D-69120 (Germany)

2015-08-24

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.

Inverse agonist-like action of cadmium on G-protein-gated inward-rectifier K{sup +} channels

Energy Technology Data Exchange (ETDEWEB)

Inanobe, Atsushi, E-mail: inanobe@pharma2.med.osaka-u.ac.jp [Department of Pharmacology, Graduate School of Medicine, Osaka University, Osaka (Japan); Center for Advanced Medical Engineering and Informatics, Osaka University, Osaka (Japan); Matsuura, Takanori [Laboratory of Protein Informatics, Institute for Protein Research, Osaka University, Osaka (Japan); Nakagawa, Atsushi [Laboratory of Supramolecular Crystallography, Institute for Protein Research, Osaka University, Osaka (Japan); Kurachi, Yoshihisa, E-mail: ykurachi@pharma2.med.osaka-u.ac.jp [Department of Pharmacology, Graduate School of Medicine, Osaka University, Osaka (Japan); Center for Advanced Medical Engineering and Informatics, Osaka University, Osaka (Japan)

2011-04-08

Highlights: {yields} We examined allosteric control of K{sup +} channel gating. {yields} We identified a high-affinity site for Cd{sup 2+} to inhibit Kir3.2 activity. {yields} The 6-coordination geometry supports the binding. {yields} Cd{sup 2+} inhibits Kir3.2 by trapping the conformation in the closed state. -- Abstract: The gate at the pore-forming domain of potassium channels is allosterically controlled by a stimulus-sensing domain. Using Cd{sup 2+} as a probe, we examined the structural elements responsible for gating in an inward-rectifier K{sup +} channel (Kir3.2). One of four endogenous cysteines facing the cytoplasm contributes to a high-affinity site for inhibition by internal Cd{sup 2+}. Crystal structure of its cytoplasmic domain in complex with Cd{sup 2+} reveals that octahedral coordination geometry supports the high-affinity binding. This mode of action causes the tethering of the N-terminus to CD loop in the stimulus-sensing domain, suggesting that their conformational changes participate in gating and Cd{sup 2+} inhibits Kir3.2 by trapping the conformation in the closed state like 'inverse agonist'.

Radiation sensors based on the generation of mobile protons in organic dielectrics.

Science.gov (United States)

Kapetanakis, Eleftherios; Douvas, Antonios M; Argitis, Panagiotis; Normand, Pascal

2013-06-26

A sensing scheme based on mobile protons generated by radiation, including ionizing radiation (IonR), in organic gate dielectrics is investigated for the development of metal-insulator-semiconductor (MIS)-type dosimeters. Application of an electric field to the gate dielectric moves the protons and thereby alters the flat band voltage (VFB) of the MIS device. The shift in the VFB is proportional to the IonR-generated protons and, therefore, to the IonR total dose. Triphenylsulfonium nonaflate (TPSNF) photoacid generator (PAG)-containing poly(methyl methacrylate) (PMMA) polymeric films was selected as radiation-sensitive gate dielectrics. The effects of UV (249 nm) and gamma (Co-60) irradiations on the high-frequency capacitance versus the gate voltage (C-VG) curves of the MIS devices were investigated for different total dose values. Systematic improvements in sensitivity can be accomplished by increasing the concentration of the TPSNF molecules embedded in the polymeric matrix.

Top-gate hybrid complementary inverters using pentacene and amorphous InGaZnO thin-film transistors with high operational stability

Directory of Open Access Journals (Sweden)

J. B. Kim

2012-03-01

Full Text Available We report on the operational stability of low-voltage hybrid organic-inorganic complementary inverters with a top-gate bottom source-drain geometry. The inverters are comprised of p-channel pentacene and n-channel amorphous InGaZnO thin-film transistors (TFTs with bi-layer gate dielectrics formed from an amorphous layer of a fluoropolymer (CYTOP and a high-k layer of Al2O3. The p- and n- channel TFTs show saturation mobility values of 0.1 ± 0.01 and 5.0 ± 0.5 cm2/Vs, respectively. The individual transistors show high electrical stability with less than 6% drain-to-source current variations after 1 h direct current (DC bias stress. Complementary inverters yield hysteresis-free voltage transfer characteristics for forward and reverse input biases with static DC gain values larger than 45 V/V at 8 V before and after being subjected to different conditions of electrical stress. Small and reversible variations of the switching threshold voltage of the inverters during these stress tests are compatible with the observed stability of the individual TFTs.

Evidence of Gate Voltage Oscillations during Short Circuit of Commercial 1.7 kV/ 1 kA IGBT Power Modules

DEFF Research Database (Denmark)

Reigosa, Paula Diaz; Wu, Rui; Iannuzzo, Francesco

2015-01-01

This paper analyzes the evidence of critical gate voltage oscillations in 1.7 kV/1 kA Insulated-Gate Bipolar Transistor (IGBT) power modules under short circuit conditions. A 6 kA/1.1 kV Non-Destructive Test (NDT) set up for repeatable short circuit tests has been built with a 40 nH stray inducta...

Understanding the Structure of High-K Gate Oxides - Oral Presentation

Energy Technology Data Exchange (ETDEWEB)

Miranda, Andre [SLAC National Accelerator Lab., Menlo Park, CA (United States)

2015-08-25

Hafnium Oxide (HfO₂) amorphous thin films are being used as gate oxides in transistors because of their high dielectric constant (κ) over Silicon Dioxide. The present study looks to find the atomic structure of HfO₂ thin films which hasn’t been done with the technique of this study. In this study, two HfO₂ samples were studied. One sample was made with thermal atomic layer deposition (ALD) on top of a Chromium and Gold layer on a silicon wafer. The second sample was made with plasma ALD on top of a Chromium and Gold layer on a Silicon wafer. Both films were deposited at a thickness of 50nm. To obtain atomic structure information, Grazing Incidence X-ray diffraction (GIXRD) was carried out on the HfO₂ samples. Because of this, absorption, footprint, polarization, and dead time corrections were applied to the scattering intensity data collected. The scattering curves displayed a difference in structure between the ALD processes. The plasma ALD sample showed the broad peak characteristic of an amorphous structure whereas the thermal ALD sample showed an amorphous structure with characteristics of crystalline materials. This appears to suggest that the thermal process results in a mostly amorphous material with crystallites within. Further, the scattering intensity data was used to calculate a pair distribution function (PDF) to show more atomic structure. The PDF showed atom distances in the plasma ALD sample had structure up to 10 Å, while the thermal ALD sample showed the same structure below 10 Å. This structure that shows up below 10 Å matches the bond distances of HfO₂ published in literature. The PDF for the thermal ALD sample also showed peaks up to 20 Å, suggesting repeating atomic spacing outside the HfO₂ molecule in the sample. This appears to suggest that there is some crystalline structure within the thermal ALD sample.

Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

Science.gov (United States)

An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

2016-11-01

Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

Pentacene thin-film transistors and inverters with plasma-enhanced atomic-layer-deposited Al2O3 gate dielectric

International Nuclear Information System (INIS)

Koo, Jae Bon; Lim, Jung Wook; Kim, Seong Hyun; Yun, Sun Jin; Ku, Chan Hoe; Lim, Sang Chul; Lee, Jung Hun

2007-01-01

The performances of pentacene thin-film transistor with plasma-enhanced atomic-layer-deposited (PEALD) 150 nm thick Al 2 O 3 dielectric are reported. Saturation mobility of 0.38 cm 2 /V s, threshold voltage of 1 V, subthreshold swing of 0.6 V/decade, and on/off current ratio of about 10 8 have been obtained. Both depletion and enhancement mode inverter have been realized with the change of treatment method of hexamethyldisilazane on PEALD Al 2 O 3 gate dielectric. Full swing depletion mode inverter has been demonstrated at input voltages ranging from 5 V to - 5 V at supply voltage of - 5 V

Silicone elastomers with high dielectric permittivity and high dielectric breakdown strength based on dipolar copolymers

DEFF Research Database (Denmark)

Madsen, Frederikke Bahrt; Yu, Liyun; Daugaard, Anders Egede

2014-01-01

Dielectric elastomers (DES) are a promising new transducer technology, but high driving voltages limit their current commercial potential. One method used to lower driving voltage is to increase dielectric permittivity of the elastomer. A novel silicone elastomer system with high dielectric...

Pros and cons of symmetrical dual-k spacer technology in hybrid FinFETs

Science.gov (United States)

Pradhan, K. P.; Andrade, M. G. C.; Sahu, P. K.

2016-12-01

The symmetrical dual-k spacer technology in hybrid FinFETs has been widely explored for better electrostatic control of the fin-based devices in nanoscale region. Since, high-k tangible spacer materials are broadly became a matter of study due to their better immunity to the short channel effects (SCEs) in nano devices. However, the only cause that restricts the circuit designers from using high-k spacer is the unreasonable increasing fringing capacitances. This work quantitatively analyzed the benefits and drawbacks of considering two different dielectric spacer materials symmetrically in either sides of the channel for the hybrid device. From the demonstrated results, the inclusion of high-k spacer predicts an effective reduction in off-state leakage along with an improvement in drive current. However, these devices have paid the cost in terms of a high total gate-to-gate capacitance (Cgg) that consequently results poor cutoff frequency (fT) and delay.

Thermal dielectric function

International Nuclear Information System (INIS)

Moneta, M.

1999-01-01

Thermal dielectric functions ε(k,ω) for homogeneous electron gas were determined and discussed. The ground state of the gas is described by the Fermi-Dirac momentum distribution. The low and high temperature limits of ε(k,ω) were related to the Lindhard dielectric function and to ε(k, omega) derived for Boltzmann and for classical momentum distributions, respectively. (author)

HfO2 as gate dielectric on Ge: Interfaces and deposition techniques

International Nuclear Information System (INIS)

Caymax, M.; Van Elshocht, S.; Houssa, M.; Delabie, A.; Conard, T.; Meuris, M.; Heyns, M.M.; Dimoulas, A.; Spiga, S.; Fanciulli, M.; Seo, J.W.; Goncharova, L.V.

2006-01-01

To fabricate MOS gate stacks on Ge, one can choose from a multitude of metal oxides as dielectric material which can be deposited by many chemical or physical vapor deposition techniques. As a few typical examples, we will discuss here the results from atomic layer deposition (ALD), metal organic CVD (MOCVD) and molecular beam deposition (MBD) using HfO 2 /Ge as materials model system. It appears that a completely interface layer free HfO 2 /Ge combination can be made in MBD, but this results in very bad capacitors. The same bad result we find if HfGe y (Hf germanides) are formed like in the case of MOCVD on HF-dipped Ge. A GeO x interfacial layer appears to be indispensable (if no other passivating materials are applied), but the composition of this interfacial layer (as determined by XPS, TOFSIMS and MEIS) is determining for the C/V quality. On the other hand, the presence of Ge in the HfO 2 layer is not the most important factor that can be responsible for poor C/V, although it can still induce bumps in C/V curves, especially in the form of germanates (Hf-O-Ge). We find that most of these interfacial GeO x layers are in fact sub-oxides, and that this could be (part of) the explanation for the high interfacial state densities. In conclusion, we find that the Ge surface preparation is determining for the gate stack quality, but it needs to be adapted to the specific deposition technique

Bias Stability Enhancement in Thin-Film Transistor with a Solution-Processed ZrO2 Dielectric as Gate Insulator

Directory of Open Access Journals (Sweden)

Shangxiong Zhou

2018-05-01

Full Text Available In this paper, a high-k metal-oxide film (ZrO2 was successfully prepared by a solution-phase method, and whose physical properties were measured by X-ray diffraction (XRD, X-ray reflectivity (XRR and atomic force microscopy (AFM. Furthermore, indium–gallium–zinc oxide thin-film transistors (IGZO-TFTs with high-k ZrO2 dielectric layers were demonstrated, and the electrical performance and bias stability were investigated in detail. By spin-coating 0.3 M precursor six times, a dense ZrO2 film, with smoother surface and fewer defects, was fabricated. The TFT devices with optimal ZrO2 dielectric exhibit a saturation mobility up to 12.7 cm2 V−1 s−1, and an on/off ratio as high as 7.6 × 105. The offset of the threshold voltage was less than 0.6 V under positive and negative bias stress for 3600 s.

High temperature polymer film dielectrics for aerospace power conditioning capacitor applications

Energy Technology Data Exchange (ETDEWEB)

Venkat, Narayanan, E-mail: venkats3@gmail.co [University of Dayton Research Institute (UDRI), Dayton, OH 45469 (United States); Dang, Thuy D. [Air Force Research Laboratory-Nanostructured and Biological Materials Branch (AFRL/RXBN) (United States); Bai Zongwu; McNier, Victor K. [University of Dayton Research Institute (UDRI), Dayton, OH 45469 (United States); DeCerbo, Jennifer N. [Air Force Research Laboratory-Electrical Technology Branch (AFRL/RZPE), Wright-Patterson Air Force Base, OH 45433 (United States); Tsao, B.-H. [University of Dayton Research Institute (UDRI), Dayton, OH 45469 (United States); Stricker, Jeffery T. [Air Force Research Laboratory-Electrical Technology Branch (AFRL/RZPE), Wright-Patterson Air Force Base, OH 45433 (United States)

2010-04-15

Polymer dielectrics are the preferred materials of choice for capacitive energy-storage applications because of their potential for high dielectric breakdown strengths, low dissipation factors and good dielectric stability over a wide range of frequencies and temperatures, despite having inherently lower dielectric constants relative to ceramic dielectrics. They are also amenable to large area processing into films at a relatively lower cost. Air Force currently has a strong need for the development of compact capacitors which are thermally robust for operation in a variety of aerospace power conditioning applications. While such applications typically use polycarbonate (PC) dielectric films in wound capacitors for operation from -55 deg. C to 125 deg. C, future power electronic systems would require the use of polymer dielectrics that can reliably operate up to elevated temperatures in the range of 250-350 deg. C. The focus of this research is the generation and dielectric evaluation of metallized, thin free-standing films derived from high temperature polymer structures such as fluorinated polybenzoxazoles, post-functionalized fluorinated polyimides and fluorenyl polyesters incorporating diamond-like hydrocarbon units. The discussion is centered mainly on variable temperature dielectric measurements of film capacitance and dissipation factor and the effects of thermal cycling, up to a maximum temperature of 350 deg. C, on film dielectric performance. Initial studies clearly point to the dielectric stability of these films for high temperature power conditioning applications, as indicated by their relatively low temperature coefficient of capacitance (TCC) (approx2%) over the entire range of temperatures. Some of the films were also found to exhibit good dielectric breakdown strengths (up to 470 V/mum) and a film dissipation factor of the order of <0.003 (0.3%) at the frequency of interest (10 kHz) for the intended applications. The measured relative dielectric

Mechanisms for plasma etching of HfO{sub 2} gate stacks with Si selectivity and photoresist trimming

Energy Technology Data Exchange (ETDEWEB)

Shoeb, Juline; Kushner, Mark J. [Department of Electrical and Computer Engineering, Iowa State University, Ames, Iowa 50011 (United States); Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109-2122 (United States)

2009-11-15

To minimize leakage currents resulting from the thinning of the insulator in the gate stack of field effect transistors, high-dielectric constant (high-k) metal oxides, and HfO{sub 2} in particular, are being implemented as a replacement for SiO{sub 2}. To speed the rate of processing, it is desirable to etch the gate stack (e.g., metal gate, antireflection layers, and dielectric) in a single process while having selectivity to the underlying Si. Plasma etching using Ar/BCl{sub 3}/Cl{sub 2} mixtures effectively etches HfO{sub 2} while having good selectivity to Si. In this article, results from integrated reactor and feature scale modeling of gate-stack etching in Ar/BCl{sub 3}/Cl{sub 2} plasmas, preceded by photoresist trimming in Ar/O{sub 2} plasmas, are discussed. It was found that BCl{sub n} species react with HfO{sub 2}, which under ion impact, form volatile etch products such as B{sub m}OCl{sub n} and HfCl{sub n}. Selectivity to Si is achieved by creating Si-B bonding as a precursor to the deposition of a BCl{sub n} polymer which slows the etch rate relative to HfO{sub 2}. The low ion energies required to achieve this selectivity then challenge one to obtain highly anisotropic profiles in the metal gate portion of the stack. Validation was performed with data from literature. The effect of bias voltage and key reactant probabilities on etch rate, selectivity, and profile are discussed.

Comparative study of phase structure and dielectric properties for K0.5Bi0.5TiO3-BiAlO3 and LaAlO3-BiAlO3

International Nuclear Information System (INIS)

Hou, Yudong; Zheng, Mupeng; Si, Meiju; Cui, Lei; Zhu, Mankang; Yan, Hui

2013-01-01

In this work, two perovskite-type compounds, K 0.5 Bi 0.5 TiO 3 and LaAlO 3 , have been selected as host material to incorporate with BiAlO 3 using a solid-state reaction route. The phase evolution and dielectric properties for both systems have been investigated in detail. For the K 0.5 Bi 0.5 TiO 3 -BiAlO 3 system, it is interesting to find that when using Bi 2 O 3 , Al 2 O 3 , K 2 CO 3 , and TiO 2 as starting materials, the formed compounds are K 0.5 Bi 0.5 TiO 3 -K 0.5 Bi 4.5 Ti 4 O 15 and Al 2 O 3 only plays a dopant role. There are two distinct dielectric peaks appearing in the patterns of temperature dependence of dielectric constant, corresponding to the phase-transition points of perovskite-type K 0.5 Bi 0.5 TiO 3 and Aurivillius-type K 0.5 Bi 4.5 Ti 4 O 15 , independently. In comparison, using Bi 2 O 3 , Al 2 O 3 , and La 2 O 3 as starting materials, the pure perovskite phase LaAlO 3 -BiAlO 3 can be obtained. Compared to the inherent paraelectric behavior in LaAlO 3 , the diffuse phase-transition phenomena can be observed in the LaAlO 3 -BiAlO 3 binary system, which corresponds well to the Vogel-Fulcher (VF) relationship. Moreover, compared to pure LaAlO 3 , the synthesized LaAlO 3 -BiAlO 3 compound shows enhanced dielectric properties, which are promising in application as gate dielectric materials. (copyright 2013 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

SGK3 Sensitivity of Voltage Gated K+ Channel Kv1.5 (KCNA5

Directory of Open Access Journals (Sweden)

Musaab Ahmed

2016-01-01

Full Text Available Background: The serum & glucocorticoid inducible kinase isoform SGK3 is a powerful regulator of several transporters, ion channels and the Na+/K+ ATPase. Targets of SGK3 include the ubiquitin ligase Nedd4-2, which is in turn a known regulator of the voltage gated K+ channel Kv1.5 (KCNA5. The present study thus explored whether SGK3 modifies the activity of the voltage gated K+ channel KCNA5, which participates in the regulation of diverse functions including atrial cardiac action potential, activity of vascular smooth muscle cells, insulin release and tumour cell proliferation. Methods: cRNA encoding KCNA5 was injected into Xenopus oocytes with and without additional injection of cRNA encoding wild-type SGK3, constitutively active S419DSGK3, inactive K191NSGK3 and/or wild type Nedd4-2. Voltage gated K+ channel activity was quantified utilizing dual electrode voltage clamp. Results: Voltage gated current in KCNA5 expressing Xenopus oocytes was significantly enhanced by wild-type SGK3 and S419DSGK3, but not by K191NSGK3. SGK3 was effective in the presence of ouabain (1 mM and thus did not require Na+/K+ ATPase activity. Coexpression of Nedd4-2 decreased the voltage gated current in KCNA5 expressing Xenopus oocytes, an effect largely reversed by additional coexpression of SGK3. Conclusion: SGK3 is a positive regulator of KCNA5, which is at least partially effective by abrogating the effect of Nedd4-2.

Outward Rectification of Voltage-Gated K+ Channels Evolved at Least Twice in Life History.

Directory of Open Access Journals (Sweden)

Janin Riedelsberger

Full Text Available Voltage-gated potassium (K+ channels are present in all living systems. Despite high structural similarities in the transmembrane domains (TMD, this K+ channel type segregates into at least two main functional categories-hyperpolarization-activated, inward-rectifying (Kin and depolarization-activated, outward-rectifying (Kout channels. Voltage-gated K+ channels sense the membrane voltage via a voltage-sensing domain that is connected to the conduction pathway of the channel. It has been shown that the voltage-sensing mechanism is the same in Kin and Kout channels, but its performance results in opposite pore conformations. It is not known how the different coupling of voltage-sensor and pore is implemented. Here, we studied sequence and structural data of voltage-gated K+ channels from animals and plants with emphasis on the property of opposite rectification. We identified structural hotspots that alone allow already the distinction between Kin and Kout channels. Among them is a loop between TMD S5 and the pore that is very short in animal Kout, longer in plant and animal Kin and the longest in plant Kout channels. In combination with further structural and phylogenetic analyses this finding suggests that outward-rectification evolved twice and independently in the animal and plant kingdom.

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene-graphene composite layers for flexible thin film transistors with a polymer gate dielectric.

Science.gov (United States)

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-02-28

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene-graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene-graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm(2) V(-1) s(-1) and a threshold voltage of -0.7 V at V(gs) = -40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm(2) V(-1) s(-1) and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies.

Dry etching of MgCaO gate dielectric and passivation layers on GaN

International Nuclear Information System (INIS)

Hlad, M.; Voss, L.; Gila, B.P.; Abernathy, C.R.; Pearton, S.J.; Ren, F.

2006-01-01

MgCaO films grown by rf plasma-assisted molecular beam epitaxy and capped with Sc 2 O 3 are promising candidates as surface passivation layers and gate dielectrics on GaN-based high electron mobility transistors (HEMTs) and metal-oxide semiconductor HEMTs (MOS-HEMTs), respectively. Two different plasma chemistries were examined for etching these thin films on GaN. Inductively coupled plasmas of CH 4 /H 2 /Ar produced etch rates only in the range 20-70 A/min, comparable to the Ar sputter rates under the same conditions. Similarly slow MgCaO etch rates (∼100 A/min) were obtained with Cl 2 /Ar discharges under the same conditions, but GaN showed rates almost an order of magnitude higher. The MgCaO removal rates are limited by the low volatilities of the respective etch products. The CH 4 /H 2 /Ar plasma chemistry produced a selectivity of around 2 for etching the MgCaO with respect to GaN

Coronary endothelial function assessment using self-gated cardiac cine MRI and k-t sparse SENSE.

Science.gov (United States)

Yerly, Jérôme; Ginami, Giulia; Nordio, Giovanna; Coristine, Andrew J; Coppo, Simone; Monney, Pierre; Stuber, Matthias

2016-11-01

Electrocardiogram (ECG)-gated cine MRI, paired with isometric handgrip exercise, can be used to accurately, reproducibly, and noninvasively measure coronary endothelial function (CEF). Obtaining a reliable ECG signal at higher field strengths, however, can be challenging due to rapid gradient switching and an increased heart rate under stress. To address these limitations, we present a self-gated cardiac cine MRI framework for CEF measurements that operates without ECG signal. Cross-sectional slices of the right coronary artery (RCA) were acquired using a two-dimensional golden angle radial trajectory. This sampling approach, combined with the k-t sparse SENSE algorithm, allows for the reconstruction of both real-time images for self-gating signal calculations and retrospectively reordered self-gated cine images. CEF measurements were quantitatively compared using both the self-gated and the standard ECG-gated approach. Self-gated cine images with high-quality, temporal, and spatial resolution were reconstructed for 18 healthy volunteers. CEF as measured in self-gated images was in good agreement (R 2  = 0.60) with that measured by its standard ECG-gated counterpart. High spatial and temporal resolution cross-sectional cine images of the RCA can be obtained without ECG signal. The coronary vasomotor response to handgrip exercise compares favorably with that obtained with the standard ECG-gated method. Magn Reson Med 76:1443-1454, 2015. © 2015 International Society for Magnetic Resonance in Medicine. © 2015 International Society for Magnetic Resonance in Medicine.

Electrical characteristics of AlO sub x N sub y prepared by oxidation of sub-10-nm-thick AlN films for MOS gate dielectric applications

CERN Document Server

Jeon, S H; Kim, H S; Noh, D Y; Hwang, H S

2000-01-01

In this research, the feasibility of ultrathin AlO sub x N sub y prepared by oxidation of sub 100-A-thick AlN thin films for metal-oxide-semiconductor (MOS) gate dielectric applications was investigated. Oxidation of 51-A-and 98-A-thick as-deposited AlN at 800 .deg. C was used to form 72-A-and 130-A-thick AlO sub x N sub y , respectively. Based on the capacitance-voltage (C-V) measurements of the MOS capacitor, the dielectric constants of 72 A-thick and 130 A-thick Al-oxynitride were 5.15 and 7, respectively. The leakage current of Al-oxynitride at low field was almost the same as that of thermal SiO sub 2. based on the CV data, the interface state density of Al-oxynitride was relatively higher than that of SiO sub 2. Although process optimization is still necessary, the Al-oxynitride exhibits some possibility for future MOS gate dielectric applications.

Electrical characteristics of AlO{sub x}N{sub y} prepared by oxidation of sub-10-nm-thick AlN films for MOS gate dielectric applications

Energy Technology Data Exchange (ETDEWEB)

Jeon, Sang Hun; Jang, Hyeon Woo; Kim, Hyun Soo; Noh, Do Young; Hwang, Hyun Sang [Kwangju Institute of Science and Technology, Kwangju (Korea, Republic of)

2000-12-01

In this research, the feasibility of ultrathin AlO{sub x}N{sub y} prepared by oxidation of sub 100-A-thick AlN thin films for metal-oxide-semiconductor (MOS) gate dielectric applications was investigated. Oxidation of 51-A-and 98-A-thick as-deposited AlN at 800 .deg. C was used to form 72-A-and 130-A-thick AlO{sub x}N{sub y}, respectively. Based on the capacitance-voltage (C-V) measurements of the MOS capacitor, the dielectric constants of 72 A-thick and 130 A-thick Al-oxynitride were 5.15 and 7, respectively. The leakage current of Al-oxynitride at low field was almost the same as that of thermal SiO{sub 2}. based on the CV data, the interface state density of Al-oxynitride was relatively higher than that of SiO{sub 2}. Although process optimization is still necessary, the Al-oxynitride exhibits some possibility for future MOS gate dielectric applications.

Conduction band-edge d-states in high-k dielectrics due to Jahn-Teller term splittings

International Nuclear Information System (INIS)

Lucovsky, G.; Fulton, C.C.; Zhang, Y.; Luning, J.; Edge, L.; Whitten, J.L.; Nemanich, R.J.; Schlom, D.G.; Afanase'v, V.V.

2005-01-01

X-ray absorption spectroscopy (XAS) is used to study conduction band edge electronic structure of high-k transition metal (TM) and trivalent lanthanide series rare earth (RE) oxide dielectrics. Empty TM/RE d-states are studied by intra-atomic transitions originating in core level spin-orbit split p-states, and conduction band states are studied in inter-atomic transitions which originate in the oxygen atom 1s core level state. In non-crystalline Zr and Hf silicate alloys, the local bonding symmetry, or crystal field splits these d-states into doubly and triply degenerate features. In nano-crystalline oxides, there are additional d-state splittings due to contributions of more distant neighbors that completely remove d-state degeneracies via the Jahn-Teller effect mechanism. This gives rise to highly localized band edge states that are electronically active in photoconductivity, internal photoemission, and act as bulk traps in metal oxide semiconductor (MOS) devices

Perovskite oxynitride LaTiOxNy thin films: Dielectric characterization in low and high frequencies

International Nuclear Information System (INIS)

Lu, Y.; Ziani, A.; Le Paven-Thivet, C.; Benzerga, R.; Le Gendre, L.; Fasquelle, D.; Kassem, H.

2011-01-01

Lanthanum titanium oxynitride (LaTiO x N y ) thin films are studied with respect to their dielectric properties in low and high frequencies. Thin films are deposited by radio frequency magnetron sputtering on different substrates. Effects of nitrogen content and crystalline quality on dielectric properties are investigated. In low-frequency range, textured LaTiO x N y thin films deposited on conductive single crystal Nb–STO show a dielectric constant ε′ ≈ 140 with low losses tanδ = 0.012 at 100 kHz. For the LaTiO x N y polycrystalline films deposited on conductive silicon substrates with platinum (Pt/Ti/SiO 2 /Si), the tunability reached up to 57% for a weak electric field of 50 kV/cm. In high-frequency range, epitaxial LaTiO x N y films deposited on MgO substrate present a high dielectric constant with low losses (ε′ ≈ 170, tanδ = 0.011, 12 GHz).

Investigation of Ultraviolet Light Curable Polysilsesquioxane Gate Dielectric Layers for Pentacene Thin Film Transistors.

Science.gov (United States)

Shibao, Hideto; Nakahara, Yoshio; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) comprising 3-methacryloxypropyl groups was investigated as an ultraviolet (UV)-light curable gate dielectric-material for pentacene thin film transistors (TFTs). The surface of UV-light cured PSQ films was smoother than that of thermally cured ones, and the pentacene layers deposited on the UV-Iight cured PSQ films consisted of larger grains. However, carrier mobility of the TFTs using the UV-light cured PSQ films was lower than that of the TFTs using the thermally cured ones. It was shown that the cross-linker molecules, which were only added to the UV-light cured PSQ films, worked as a major mobility-limiting factor for the TFTs.

Structural-optical study of high-dielectric-constant oxide films

Energy Technology Data Exchange (ETDEWEB)

Losurdo, M. [Institute of Inorganic Methodologies and Plasmas, IMIP-CNR, Department of Chemistry and INSTM Universita di bari, Via Orabona 4, 70126 Bari (Italy)]. E-mail: maria.losurdo@ba.imip.cnr.it; Giangregorio, M.M. [Institute of Inorganic Methodologies and Plasmas, IMIP-CNR, Department of Chemistry and INSTM Universita di bari, Via Orabona 4, 70126 Bari (Italy); Luchena, M. [Institute of Inorganic Methodologies and Plasmas, IMIP-CNR, Department of Chemistry and INSTM Universita di bari, Via Orabona 4, 70126 Bari (Italy); Capezzuto, P. [Institute of Inorganic Methodologies and Plasmas, IMIP-CNR, Department of Chemistry and INSTM Universita di bari, Via Orabona 4, 70126 Bari (Italy); Bruno, G. [Institute of Inorganic Methodologies and Plasmas, IMIP-CNR, Department of Chemistry and INSTM Universita di bari, Via Orabona 4, 70126 Bari (Italy); Toro, R.G. [Dipartimento di Scienze Chimiche, Universita di Catania, and INSTM-UdR Catania, Viale A. Doria 6, I-95125 Catania (Italy); Malandrino, G. [Dipartimento di Scienze Chimiche, Universita di Catania, and INSTM-UdR Catania, Viale A. Doria 6, I-95125 Catania (Italy); Fragala, I.L. [Dipartimento di Scienze Chimiche, Universita di Catania, and INSTM-UdR Catania, Viale A. Doria 6, I-95125 Catania (Italy); Nigro, R. Lo [Istituto di Microelettronica e Microsistemi, IMM-CNR, Stradale Primosole 50, I-95121 Catania (Italy)

2006-10-31

High-k polycrystalline Pr{sub 2}O{sub 3} and amorphous LaAlO{sub 3} oxide thin films deposited on Si(0 0 1) are studied. The microstructure is investigated using X-ray diffraction and scanning electron microscopy. Optical properties are determined in the 0.75-6.5 eV photon energy range using spectroscopic ellipsometry. The polycrystalline Pr{sub 2}O{sub 3} films have an optical gap of 3.86 eV and a dielectric constant of 16-26, which increases with film thickness. Similarly, very thin amorphous LaAlO{sub 3} films have the optical gap of 5.8 eV, and a dielectric constant below 14 which also increases with film thickness. The lower dielectric constant compared to crystalline material is an intrinsic characteristic of amorphous films.

Comparative study on nitridation and oxidation plasma interface treatment for AlGaN/GaN MIS-HEMTs with AlN gate dielectric

Science.gov (United States)

Zhu, Jie-Jie; Ma, Xiao-Hua; Hou, Bin; Chen, Li-Xiang; Zhu, Qing; Hao, Yue

2017-02-01

This paper demonstrated the comparative study on interface engineering of AlN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) by using plasma interface pre-treatment in various ambient gases. The 15 nm AlN gate dielectric grown by plasma-enhanced atomic layer deposition significantly suppressed the gate leakage current by about two orders of magnitude and increased the peak field-effect mobility by more than 50%. NH3/N2 nitridation plasma treatment (NPT) was used to remove the 3 nm poor-quality interfacial oxide layer and N2O/N2 oxidation plasma treatment (OPT) to improve the quality of interfacial layer, both resulting in improved dielectric/barrier interface quality, positive threshold voltage (V th) shift larger than 0.9 V, and negligible dispersion. In comparison, however, NPT led to further decrease in interface charges by 3.38 × 1012 cm-2 and an extra positive V th shift of 1.3 V. Analysis with fat field-effect transistors showed that NPT resulted in better sub-threshold characteristics and transconductance linearity for MIS-HEMTs compared with OPT. The comparative study suggested that direct removing the poor interfacial oxide layer by nitridation plasma was superior to improving the quality of interfacial layer by oxidation plasma for the interface engineering of GaN-based MIS-HEMTs.

Top-gated chemical vapor deposition grown graphene transistors with current saturation.

Science.gov (United States)

Bai, Jingwei; Liao, Lei; Zhou, Hailong; Cheng, Rui; Liu, Lixin; Huang, Yu; Duan, Xiangfeng

2011-06-08

Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.

High temperature dielectric function of silicon, germanium and GaN

Energy Technology Data Exchange (ETDEWEB)

Leyer, Martin; Pristovsek, Markus; Kneissl, Michael [Technische Universitaet Berlin (Germany). Institut fuer Festkoerperphysik

2010-07-01

In the last few years accurate values for the optical properties of silicon, germanium and GaN at high temperatures have become important as a reference for in-situ analysis, e.g. reflectometry. Precise temperature dependent dielectric measurements are necessary for the growth of GaInP/GaInAs/Ge triple-junction solar cells and the hetero epitaxy of GaN on silicon and sapphire. We performed spectroscopic ellipsometry (SE) measurements of the dielectric function of silicon, germanium and GaN between 1.5 eV and 6.5 eV in the temperature range from 300 K to 1300 K. The Samples were deoxidized chemically or by heating. High resolution SE spectra were taken every 50 K while cooling down to room temperature. The temperature dependence of the critical energies is compared to literature. Measurements for germanium showed a shift of the E{sub 2} critical point of {proportional_to}0.1 eV toward lower energies. The reason for this behavior is a non-negligible oxide layer on the samples in the literature.

High-k dielectric composites of poly(2-cyanoethyl vinyl ether) and barium titanate for flexible electronics

Czech Academy of Sciences Publication Activity Database

Piana, Francesco; Pfleger, Jiří; Jambor, R.; Řičica, T.; Macák, J. M.

2017-01-01

Roč. 134, č. 37 (2017), s. 1-10, č. článku 45236. ISSN 0021-8995 R&D Projects: GA TA ČR(CZ) TE01020022; GA MŠk(CZ) LO1507 Institutional support: RVO:61389013 Keywords : composites * dielectric properties * nanocrystals Subject RIV: CG - Electrochemistry OBOR OECD: Electrochemistry (dry cells, batteries, fuel cells, corrosion metals, electrolysis) Impact factor: 1.860, year: 2016

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene–graphene composite layers for flexible thin film transistors with a polymer gate dielectric

International Nuclear Information System (INIS)

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-01-01

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene–graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene–graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm 2  V −1  s −1 and a threshold voltage of −0.7 V at V gs = −40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm 2  V −1  s −1 and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies. (paper)

Effect of ciguatoxin 3C on voltage-gated Na+ and K+ currents in mouse taste cells.

Science.gov (United States)

Ghiaroni, Valeria; Fuwa, Haruhiko; Inoue, Masayuki; Sasaki, Makoto; Miyazaki, Keisuke; Hirama, Masahiro; Yasumoto, Takeshi; Rossini, Gian Paolo; Scalera, Giuseppe; Bigiani, Albertino

2006-09-01

The marine dinoflagellate Gambierdiscus toxicus produces highly lipophilic, polycyclic ether toxins that cause a seafood poisoning called ciguatera. Ciguatoxins (CTXs) and gambierol represent the two major causative agents of ciguatera intoxication, which include taste alterations (dysgeusiae). However, information on the mode of action of ciguatera toxins in taste cells is scarce. Here, we have studied the effect of synthetic CTX3C (a CTX congener) on mouse taste cells. By using the patch-clamp technique to monitor membrane ion currents, we found that CTX3C markedly affected the operation of voltage-gated Na(+) channels but was ineffective on voltage-gated K(+) channels. This result was the exact opposite of what we obtained earlier with gambierol, which inhibits K(+) channels but not Na(+) channels. Thus, CTXs and gambierol affect with high potency the operation of separate classes of voltage-gated ion channels in taste cells. Our data suggest that taste disturbances reported in ciguatera poisoning might be due to the ability of ciguatera toxins to interfere with ion channels in taste buds.

Generation of high-fidelity controlled-NOT logic gates by coupled superconducting qubits

International Nuclear Information System (INIS)

Galiautdinov, Andrei

2007-01-01

Building on the previous results of the Weyl chamber steering method, we demonstrate how to generate high-fidelity controlled-NOT (CNOT) gates by direct application of certain physically relevant Hamiltonians with fixed coupling constants containing Rabi terms. Such Hamiltonians are often used to describe two superconducting qubits driven by local rf pulses. It is found that in order to achieve 100% fidelity in a system with capacitive coupling of strength g, one Rabi term suffices. We give the exact values of the physical parameters needed to implement such CNOT gates. The gate time and all possible Rabi frequencies are found to be t=π/(2g) and Ω 1 /g=√(64n 2 -1),n=1,2,3,.... Generation of a perfect CNOT gate in a system with inductive coupling, characterized by additional constant k, requires the presence of both Rabi terms. The gate time is again t=π/(2g), but now there is an infinite number of solutions, each of which is valid in a certain range of k and is characterized by a pair of integers (n,m), (Ω 1,2 /g)=√(16n 2 -((k-1/2)) 2 )±√(16m 2 -((k+1/2)) 2 ). We distinguish two cases, depending on the sign of the coupling constant: (i) the antiferromagnetic case (k≥0) with n≥m=0,1,2,... and (ii) the ferromagnetic case (k≤0) with n>m=0,1,2,.... We conclude with consideration of fidelity degradation by switching to resonance. Simulation of time evolution based on the fourth-order Magnus expansion reveals characteristics of the gate similar to those found in the exact case, with slightly shorter gate time and shifted values of the Rabi frequencies

Highly Stable, Dual-Gated MoS2 Transistors Encapsulated by Hexagonal Boron Nitride with Gate-Controllable Contact, Resistance, and Threshold Voltage.

Science.gov (United States)

Lee, Gwan-Hyoung; Cui, Xu; Kim, Young Duck; Arefe, Ghidewon; Zhang, Xian; Lee, Chul-Ho; Ye, Fan; Watanabe, Kenji; Taniguchi, Takashi; Kim, Philip; Hone, James

2015-07-28

Emerging two-dimensional (2D) semiconductors such as molybdenum disulfide (MoS2) have been intensively studied because of their novel properties for advanced electronics and optoelectronics. However, 2D materials are by nature sensitive to environmental influences, such as temperature, humidity, adsorbates, and trapped charges in neighboring dielectrics. Therefore, it is crucial to develop device architectures that provide both high performance and long-term stability. Here we report high performance of dual-gated van der Waals (vdW) heterostructure devices in which MoS2 layers are fully encapsulated by hexagonal boron nitride (hBN) and contacts are formed using graphene. The hBN-encapsulation provides excellent protection from environmental factors, resulting in highly stable device performance, even at elevated temperatures. Our measurements also reveal high-quality electrical contacts and reduced hysteresis, leading to high two-terminal carrier mobility (33-151 cm(2) V(-1) s(-1)) and low subthreshold swing (80 mV/dec) at room temperature. Furthermore, adjustment of graphene Fermi level and use of dual gates enable us to separately control contact resistance and threshold voltage. This novel vdW heterostructure device opens up a new way toward fabrication of stable, high-performance devices based on 2D materials.

Screening-induced surface polar optical phonon scattering in dual-gated graphene field effect transistors

Energy Technology Data Exchange (ETDEWEB)

Hu, Bo, E-mail: hubo2011@semi.ac.cn

2015-03-15

The effect of surface polar optical phonons (SOs) from the dielectric layers on electron mobility in dual-gated graphene field effect transistors (GFETs) is studied theoretically. By taking into account SO scattering of electron as a main scattering mechanism, the electron mobility is calculated by the iterative solution of Boltzmann transport equation. In treating scattering with the SO modes, the dynamic dielectric screening is included and compared to the static dielectric screening and the dielectric screening in the static limit. It is found that the dynamic dielectric screening effect plays an important role in the range of low net carrier density. More importantly, in-plane acoustic phonon scattering and charged impurity scattering are also included in the total mobility for SiO{sub 2}-supported GFETs with various high-κ top-gate dielectric layers considered. The calculated total mobility results suggest both Al{sub 2}O{sub 3} and AlN are the promising candidate dielectric layers for the enhancement in room temperature mobility of graphene in the future.

Organic dielectrics in high voltage cables

Energy Technology Data Exchange (ETDEWEB)

Vermeer, J

1962-03-01

It appears that the limit has been reached in the applicability of oil-impregnated paper as the dielectric for ehv cables, as with rising voltages the prevention of conductor losses becomes increasingly difficult, while the dielectric losses of the insulation, increasing as the square of the voltage, contribute to a greater extent to the temperature rise of the conductor. The power transmitting capacity of ehv cables reaches a maximum at 500 to 600 kV for these reasons. Apart from artificial cooling, a substantial improvement can be obtained only with the use of insulating materials with much lower dielectric losses; these can moreover be applied with a smaller wall thickness, but this means higher field strengths. Synthetic polymer materials meet these requirements but can be used successfully only in the form of lapped film tapes impregnated with suitable liquids. The electrical properties of these heterogeneous dielectrics, in particular, their impulse breakdown strengths are studied in detail.

Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

Energy Technology Data Exchange (ETDEWEB)

Wang, Shun; Gao, Xu, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn; Zhong, Ya-Nan; Zhang, Zhong-Da; Xu, Jian-Long; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn [Institute of Functional Nano and Soft Materials (FUNSOM), Jiangsu Key Laboratory for Carbon-Based Functional Materials and Devices, Soochow University, Suzhou, Jiangsu 215123 (China)

2016-07-11

High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio and good memory retention.

Comparative analysis of the effects of tantalum doping and annealing on atomic layer deposited (Ta2O5)x(Al2O3)1−x as potential gate dielectrics for GaN/AlxGa1−xN/GaN high electron mobility transistors

International Nuclear Information System (INIS)

Partida-Manzanera, T.; Roberts, J. W.; Sedghi, N.; Potter, R. J.; Bhat, T. N.; Zhang, Z.; Tan, H. R.; Dolmanan, S. B.; Tripathy, S.

2016-01-01

This paper describes a method to optimally combine wide band gap Al 2 O 3 with high dielectric constant (high-κ) Ta 2 O 5 for gate dielectric applications. (Ta 2 O 5 ) x (Al 2 O 3 ) 1−x thin films deposited by thermal atomic layer deposition (ALD) on GaN-capped Al x Ga 1−x N/GaN high electron mobility transistor (HEMT) structures have been studied as a function of the Ta 2 O 5 molar fraction. X-ray photoelectron spectroscopy shows that the bandgap of the oxide films linearly decreases from 6.5 eV for pure Al 2 O 3 to 4.6 eV for pure Ta 2 O 5 . The dielectric constant calculated from capacitance-voltage measurements also increases linearly from 7.8 for Al 2 O 3 up to 25.6 for Ta 2 O 5 . The effect of post-deposition annealing in N 2 at 600 °C on the interfacial properties of undoped Al 2 O 3 and Ta-doped (Ta 2 O 5 ) 0.12 (Al 2 O 3 ) 0.88 films grown on GaN-HEMTs has been investigated. These conditions are analogous to the conditions used for source/drain contact formation in gate-first HEMT technology. A reduction of the Ga-O to Ga-N bond ratios at the oxide/HEMT interfaces is observed after annealing, which is attributed to a reduction of interstitial oxygen-related defects. As a result, the conduction band offsets (CBOs) of the Al 2 O 3 /GaN-HEMT and (Ta 2 O 5 ) 0.16 (Al 2 O 3 ) 0.84 /GaN-HEMT samples increased by ∼1.1 eV to 2.8 eV and 2.6 eV, respectively, which is advantageous for n-type HEMTs. The results demonstrate that ALD of Ta-doped Al 2 O 3 can be used to control the properties of the gate dielectric, allowing the κ-value to be increased, while still maintaining a sufficient CBO to the GaN-HEMT structure for low leakage currents

GaN-on-silicon high-electron-mobility transistor technology with ultra-low leakage up to 3000 V using local substrate removal and AlN ultra-wide bandgap

Science.gov (United States)

Dogmus, Ezgi; Zegaoui, Malek; Medjdoub, Farid

2018-03-01

We report on extremely low off-state leakage current in AlGaN/GaN-on-silicon metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) up to a high blocking voltage. Remarkably low off-state gate and drain leakage currents below 1 µA/mm up to 3 kV have been achieved owing to the use of a thick in situ SiN gate dielectric under the gate, and a local Si substrate removal technique combined with a cost effective 15-µm-thick AlN dielectric layer followed by a Cu deposition. This result establishes a manufacturable state-of-the-art high-voltage GaN-on-silicon power transistors while maintaining a low specific on-resistance of approximately 10 mΩ·cm2.

Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

Energy Technology Data Exchange (ETDEWEB)

Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A., E-mail: steven.vitale@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

2015-07-28

Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

KAUST Repository

Salas-Villasenor, A. L.; Mejia, I.; Hovarth, J.; Alshareef, Husam N.; Cha, D. K.; Ramirez-Bon, R.; Gnade, B. E.; Quevedo-Lopez, M. A.

2010-01-01

Cadmium sulfide thin film transistors were demonstrated as the n-type device for use in flexible electronics. CdS thin films were deposited by chemical bath deposition (70° C) on either 100 nm HfO2 or SiO2 as the gate dielectrics. Common gate transistors with channel lengths of 40-100 μm were fabricated with source and drain aluminum top contacts defined using a shadow mask process. No thermal annealing was performed throughout the device process. X-ray diffraction results clearly show the hexagonal crystalline phase of CdS. The electrical performance of HfO 2 /CdS -based thin film transistors shows a field effect mobility and threshold voltage of 25 cm2 V-1 s-1 and 2 V, respectively. Improvement in carrier mobility is associated with better nucleation and growth of CdS films deposited on HfO2. © 2010 The Electrochemical Society.

Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

KAUST Repository

Salas-Villasenor, A. L.

2010-06-29

Cadmium sulfide thin film transistors were demonstrated as the n-type device for use in flexible electronics. CdS thin films were deposited by chemical bath deposition (70° C) on either 100 nm HfO2 or SiO2 as the gate dielectrics. Common gate transistors with channel lengths of 40-100 μm were fabricated with source and drain aluminum top contacts defined using a shadow mask process. No thermal annealing was performed throughout the device process. X-ray diffraction results clearly show the hexagonal crystalline phase of CdS. The electrical performance of HfO 2 /CdS -based thin film transistors shows a field effect mobility and threshold voltage of 25 cm2 V-1 s-1 and 2 V, respectively. Improvement in carrier mobility is associated with better nucleation and growth of CdS films deposited on HfO2. © 2010 The Electrochemical Society.

Disclosed dielectric and electromechanical properties of hydrogenated nitrile–butadiene dielectric elastomer

International Nuclear Information System (INIS)

Yang, Dan; Tian, Ming; Dong, Yingchao; Liu, Haoliang; Yu, Yingchun; Zhang, Liqun

2012-01-01

This paper presents a comprehensive study of the effects of acrylonitrile content, crosslink density and plasticization on the dielectric and electromechanical performances of hydrogenated nitrile–butadiene dielectric elastomer. It was found that by increasing the acrylonitrile content of hydrogenated nitrile–butadiene dielectric elastomer, the dielectric constant will be improved accompanied with a sharp decrease of electrical breakdown strength leading to a small actuated strain. At a fixed electric field, a high crosslink density increased the elastic modulus of dielectric elastomer, but it also enhanced the electrical breakdown strength leading to a high actuated strain. Adding a plasticizer into the dielectric elastomer decreased the dielectric constant and electrical breakdown strength slightly, but reduced the elastic modulus sharply, which was beneficial for obtaining a large strain at low electric field from the dielectric elastomer. The largest actuated strain of 22% at an electric field of 30 kV mm −1 without any prestrain was obtained. Moreover, the hydrogenated nitrile–butadiene dielectric actuator showed good history dependence. This proposed material has great potential to be an excellent dielectric elastomer. (paper)

Photon-gated spin transistor

OpenAIRE

Li, Fan; Song, Cheng; Cui, Bin; Peng, Jingjing; Gu, Youdi; Wang, Guangyue; Pan, Feng

2017-01-01

Spin-polarized field-effect transistor (spin-FET), where a dielectric layer is generally employed for the electrical gating as the traditional FET, stands out as a seminal spintronic device under the miniaturization trend of electronics. It would be fundamentally transformative if optical gating was used for spin-FET. We report a new type of spin-polarized field-effect transistor (spin-FET) with optical gating, which is fabricated by partial exposure of the (La,Sr)MnO3 channel to light-emitti...

Molecular Aspects of Structure, Gating, and Physiology of pH-Sensitive Background K2P and Kir K+-Transport Channels

Science.gov (United States)

Sepúlveda, Francisco V.; Pablo Cid, L.; Teulon, Jacques; Niemeyer, María Isabel

2015-01-01

K+ channels fulfill roles spanning from the control of excitability to the regulation of transepithelial transport. Here we review two groups of K+ channels, pH-regulated K2P channels and the transport group of Kir channels. After considering advances in the molecular aspects of their gating based on structural and functional studies, we examine their participation in certain chosen physiological and pathophysiological scenarios. Crystal structures of K2P and Kir channels reveal rather unique features with important consequences for the gating mechanisms. Important tasks of these channels are discussed in kidney physiology and disease, K+ homeostasis in the brain by Kir channel-equipped glia, and central functions in the hearing mechanism in the inner ear and in acid secretion by parietal cells in the stomach. K2P channels fulfill a crucial part in central chemoreception probably by virtue of their pH sensitivity and are central to adrenal secretion of aldosterone. Finally, some unorthodox behaviors of the selectivity filters of K2P channels might explain their normal and pathological functions. Although a great deal has been learned about structure, molecular details of gating, and physiological functions of K2P and Kir K+-transport channels, this has been only scratching at the surface. More molecular and animal studies are clearly needed to deepen our knowledge. PMID:25540142

Breakdown of coupling dielectrics for Si microstrip detectors

International Nuclear Information System (INIS)

Candelori, A.; Paccagnella, A.; Padova Univ.; Saglimbeni, G.

1999-01-01

Double-layer coupling dielectrics for AC-coupled Si microstrip detectors have been electrically characterized in order to determine their performance in a radiation-harsh environment, with a focus on the dielectric breakdown. Two different dielectric technologies have been investigated: SiO 2 /TEOS and SiO 2 /Si 3 N 4 . Dielectrics have been tested by using a negative gate voltage ramp of 0.2 MV/(cm·s). The metal/insulator/Si I-V characteristics show different behaviours depending on the technology. The extrapolated values of the breakdown field for unirradiated devices are significantly higher for SiO 2 /Si 3 N 4 dielectrics, but the data dispersion is lower for SiO 2 /TEOS devices. No significant variation of the breakdown field has been measured after a 10 Mrad (Si) γ irradiation for SiO 2 /Si 3 N 4 dielectrics. Finally, the SiO 2 /Si 3 N 4 DC conduction is enhanced if a positive gate voltage ramp is applied with respect to the negative one, due to the asymmetric conduction of the double-layer dielectric

Observation of band bending of metal/high-k Si capacitor with high energy x-ray photoemission spectroscopy and its application to interface dipole measurement

Science.gov (United States)

Kakushima, K.; Okamoto, K.; Tachi, K.; Song, J.; Sato, S.; Kawanago, T.; Tsutsui, K.; Sugii, N.; Ahmet, P.; Hattori, T.; Iwai, H.

2008-11-01

Band bendings of Si substrates have been observed using hard x-ray photoemission spectroscopy. With a capability of collecting photoelectrons generated as deep as 40 nm, the binding energy shift in a core level caused by the potential profile at the surface of the substrate results in a spectrum broadening. The broadening is found to be significant when heavily doped substrates are used owing to its steep potential profile. The surface potential of the substrate can be obtained by deconvolution of the spectrum. This method has been applied to observe the band bending profile of metal-oxide-semiconductor capacitors with high-k gate dielectrics. By comparing the band bending profiles of heavily-doped n+- and p+-Si substrates, the interface dipoles presented at interfaces can be estimated. In the case of W gated La2O3/La-silicate capacitor, an interface dipole to shift the potential of -0.45 V has been estimated at La-silicate/Si interface, which effectively reduces the apparent work function of W. On the other hand, an interface dipole of 0.03-0.07 V has been found to exist at Hf-silicate/SiO2 interface for W gated HfO2/Hf-silicate/SiO2 capacitor.

Voltage-Gated Potassium Channels: A Structural Examination of Selectivity and Gating

Science.gov (United States)

Kim, Dorothy M.; Nimigean, Crina M.

2016-01-01

Voltage-gated potassium channels play a fundamental role in the generation and propagation of the action potential. The discovery of these channels began with predictions made by early pioneers, and has culminated in their extensive functional and structural characterization by electrophysiological, spectroscopic, and crystallographic studies. With the aid of a variety of crystal structures of these channels, a highly detailed picture emerges of how the voltage-sensing domain reports changes in the membrane electric field and couples this to conformational changes in the activation gate. In addition, high-resolution structural and functional studies of K+ channel pores, such as KcsA and MthK, offer a comprehensive picture on how selectivity is achieved in K+ channels. Here, we illustrate the remarkable features of voltage-gated potassium channels and explain the mechanisms used by these machines with experimental data. PMID:27141052

Interfacial microstructure of NiSi x/HfO2/SiO x/Si gate stacks

International Nuclear Information System (INIS)

Gribelyuk, M.A.; Cabral, C.; Gusev, E.P.; Narayanan, V.

2007-01-01

Integration of NiSi x based fully silicided metal gates with HfO 2 high-k gate dielectrics offers promise for further scaling of complementary metal-oxide- semiconductor devices. A combination of high resolution transmission electron microscopy and small probe electron energy loss spectroscopy (EELS) and energy dispersive X-ray analysis has been applied to study interfacial reactions in the undoped gate stack. NiSi was found to be polycrystalline with the grain size decreasing from top to bottom of NiSi x film. Ni content varies near the NiSi/HfO x interface whereby both Ni-rich and monosilicide phases were observed. Spatially non-uniform distribution of oxygen along NiSi x /HfO 2 interface was observed by dark field Scanning Transmission Electron Microscopy and EELS. Interfacial roughness of NiSi x /HfO x was found higher than that of poly-Si/HfO 2 , likely due to compositional non-uniformity of NiSi x . No intermixing between Hf, Ni and Si beyond interfacial roughness was observed

Correlation between stress-induced leakage current and dielectric degradation in ultra-porous SiOCH low-k materials

Energy Technology Data Exchange (ETDEWEB)

Wu, C., E-mail: Chen.Wu@imec.be; De Wolf, I. [imec, Kapeldreef 75, 3001 Leuven (Belgium); Department of Materials Engineering, KU Leuven, 3000 Leuven (Belgium); Li, Y.; Leśniewska, A.; Varela Pedreira, O.; Marneffe, J.-F. de; Ciofi, I.; Verdonck, P.; Baklanov, M. R.; Bömmels, J.; Tőkei, Zs.; Croes, K. [imec, Kapeldreef 75, 3001 Leuven (Belgium)

2015-10-28

Stress-Induced Leakage Current (SILC) behavior during the dielectric degradation of ultra-porous SiOCH low-k materials was investigated. Under high voltage stress, SILC increases to a critical value before final hard breakdown. This SILC increase rate is mainly driven by the injected charges and is negligibly influenced by temperature and voltage. SILC is found to be transient and shows a t{sup −1} relaxation behavior, where t is the storage time at low voltages. This t{sup −1} transient behavior, described by the tunneling front model, is caused by both electron charging of neutral defects in the dielectric close to the cathode interface and discharging of donor defects close to the anode interface. These defects have a uniform density distribution within the probed depth range, which is confirmed by the observed flat band voltage shift results collected during the low voltage storage. By applying an additional discharging step after the low voltage storage, the trap energies and spatial distributions are derived. In a highly degraded low-k dielectric, the majority of defects have a trap depth between 3.4 eV and 3.6 eV and a density level of 1 × 10{sup 18 }eV{sup −1 }cm{sup −3}. The relation between the defect density N and the total amount of the injected charges Q is measured to be sub-linear, N ∼ Q{sup 0.45±0.07}. The physical nature of these stress-induced defects is suggested to be caused by the degradation of the Si-O based skeleton in the low-k dielectric.

Low-voltage organic thin film transistors (OTFTs) using crosslinked polyvinyl alcohol (PVA)/neodymium oxide (Nd2O3) bilayer gate dielectrics

Science.gov (United States)

Khound, Sagarika; Sarma, Ranjit

2018-01-01

We have reported here on the design, processing and dielectric properties of pentacene-based organic thin film transitors (OTFTs) with a bilayer gate dilectrics of crosslinked PVA/Nd2O3 which enables low-voltage organic thin film operations. The dielectric characteristics of PVA/Nd2O3 bilayer films are studied by capacitance-voltage ( C- V) and current-voltage ( I- V) curves in the metal-insulator-metal (MIM) structure. We have analysed the output electrical responses and transfer characteristics of the OTFT devices to determine their performance of OTFT parameters. The mobility of 0.94 cm2/Vs, the threshold voltage of - 2.8 V, the current on-off ratio of 6.2 × 105, the subthreshold slope of 0.61 V/decade are evaluated. Low leakage current of the device is observed from current density-electric field ( J- E) curve. The structure and the morphology of the device are studied using X-ray diffraction (XRD) and atomic force microscope (AFM), respectively. The study demonstrates an effective way to realize low-voltage, high-performance OTFTs at low cost.

Dielectric properties of (K0.5Na0.5)NbO3-(Bi0.5Li0.5)ZrO3 lead-free ceramics as high-temperature ceramic capacitors

Science.gov (United States)

Yan, Tianxiang; Han, Feifei; Ren, Shaokai; Ma, Xing; Fang, Liang; Liu, Laijun; Kuang, Xiaojun; Elouadi, Brahim

2018-04-01

(1 - x)K0.5Na0.5NbO3- x(Bi0.5Li0.5)ZrO3 (labeled as (1 - x)KNN- xBLZ) lead-free ceramics were fabricated by a solid-state reaction method. A research was conducted on the effects of BLZ content on structure, dielectric properties and relaxation behavior of KNN ceramics. By combining the X-ray diffraction patterns with the temperature dependence of dielectric properties, an orthorhombic-tetragonal phase coexistence was identified for x = 0.03, a tetragonal phase was determined for x = 0.05, and a single rhombohedral structure occurred at x = 0.08. The 0.92KNN-0.08BLZ ceramic exhibits a high and stable permittivity ( 1317, ± 15% variation) from 55 to 445 °C and low dielectric loss (≤ 6%) from 120 to 400 °C, which is hugely attractive for high-temperature capacitors. Activation energies of both high-temperature dielectric relaxation and dc conductivity first increase and then decline with the increase of BLZ, which might be attributed to the lattice distortion and concentration of oxygen vacancies.

Effects of the gate dielectric on the subthreshold transport of carbon nanotube network transistors grown by using plasma-enhanced chemical vapor deposition

International Nuclear Information System (INIS)

Jeong, Seung Geun; Park, Wan Jun

2010-01-01

In this study, we investigated the subthreshold slope of random network carbon nanotube transistors with different geometries and passivations. Single-wall carbon nanotubes with lengths of 1-2 m were grown by using plasma-enhanced chemical vapor deposition to form the transistor channels. A critical channel length, where the subthreshold slope was saturated, of 7 μm was obtained. This was due to the percolational behavior of the nanotube random networks. With the dielectric passivation, the subthreshold slope was dramatically reduced from 9 V/decade to 0.9 V/decade by reducing interfacial trap sites, which then reduced the interface capacitance between the nanotube network and the gate dielectric.

Surface patterned dielectrics by direct writing of anodic oxides using scanning droplet cell microscopy

International Nuclear Information System (INIS)

Siket, Christian M.; Mardare, Andrei Ionut; Kaltenbrunner, Martin; Bauer, Siegfried; Hassel, Achim Walter

2013-01-01

Highlights: • Scanning droplet cell microscopy was applied for local gate oxide writing. • Sharp lines are obtained at the highest writing speed of 1 mm min −1 . • 13.4 kC cm −3 was found as charge per volume for aluminium oxide. • High field constant of 24 nm V −1 and dielectric constant of 12 were determined for Al 2 O 3 by CV and EIS. -- Abstract: Scanning droplet cell microscopy was used for patterning of anodic oxide lines on the surface of Al thin films by direct writing. The structural modifications of the written oxide lines as a function of the writing speed were studied by analyzing the relative error of the line widths. Sharper lines were obtained for writing speeds faster than 1 mm min −1 . An increase in sharpness was observed for higher writing speeds. A theoretical model based on the Faraday law is proposed to explain the constant anodisation current measured during the writing process and yielded a charge per volume of 13.4 kC cm −3 for Al 2 O 3 . From calculated oxide film thicknesses the high field constant was found to be 24 nm V −1 . Electrochemical impedance spectroscopy revealed an increase of the electrical permittivity up to ε = 12 with the decrease of the writing speed of the oxide line. Writing of anodic oxide lines was proven to be an important step in preparing capacitors and gate dielectrics in plastic electronics

Investigation of capacitance characteristics in metal/high-k

Indian Academy of Sciences (India)

Keywords. C − V characteristic; high-k dielectric; interface state density; MIS structure; nanotechnology; TCAD simulation. Abstract. Capacitance vs. voltage ( C − V ) curves at AC high frequency of a metal–insulator–semiconductor (MIS) capacitorare investigated in this paper. Bi-dimensional simulations with Silvaco TCAD ...

Band Alignment and Optical Properties of (ZrO20.66(HfO20.34 Gate Dielectrics Thin Films on p-Si (100

Directory of Open Access Journals (Sweden)

Dahlang Tahir

2011-11-01

Full Text Available (ZrO20.66(HfO20.34 dielectric films on p-Si (100 were grown by atomic layer deposition method, for which the conduction band offsets, valence band offsets and band gaps were obtained by using X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy. The band gap, valence and conduction band offset values for (ZrO20.66(HfO20.34 dielectric thin film, grown on Si substrate were about 5.34, 2.35 and 1.87 eV respectively. This band alignment was similar to that of ZrO2. In addition, The dielectric function ε (k, ω, index of refraction n and the extinction coefficient k for the (ZrO20.66(HfO20.34 thin films were obtained from a quantitative analysis of REELS data by comparison to detailed dielectric response model calculations using the QUEELS-ε (k,ω-REELS software package. These optical properties are similar with ZrO2 dielectric thin films.

10 K gate I(2)L and 1 K component analog compatible bipolar VLSI technology - HIT-2

Science.gov (United States)

Washio, K.; Watanabe, T.; Okabe, T.; Horie, N.

1985-02-01

An advanced analog/digital bipolar VLSI technology that combines on the same chip 2-ns 10 K I(2)L gates with 1 K analog devices is proposed. The new technology, called high-density integration technology-2, is based on a new structure concept that consists of three major techniques: shallow grooved-isolation, I(2)L active layer etching, and I(2)L current gain increase. I(2)L circuits with 80-MHz maximum toggle frequency have developed compatibly with n-p-n transistors having a BV(CE0) of more than 10 V and an f(T) of 5 GHz, and lateral p-n-p transistors having an f(T) of 150 MHz.

High thermal conductivity lossy dielectric using a multi layer configuration

Science.gov (United States)

Tiegs, Terry N.; Kiggans, Jr., James O.

2003-01-01

Systems and methods are described for loss dielectrics. A loss dielectric includes at least one high dielectric loss layer and at least one high thermal conductivity-electrically insulating layer adjacent the at least one high dielectric loss layer. A method of manufacturing a loss dielectric includes providing at least one high dielectric loss layer and providing at least one high thermal conductivity-electrically insulating layer adjacent the at least one high dielectric loss layer. The systems and methods provide advantages because the loss dielectrics are less costly and more environmentally friendly than the available alternatives.

Electrode/Dielectric Strip For High-Energy-Density Capacitor

Science.gov (United States)

Yen, Shiao-Ping S.

1994-01-01

Improved unitary electrode/dielectric strip serves as winding in high-energy-density capacitor in pulsed power supply. Offers combination of qualities essential for high energy density: high permittivity of dielectric layers, thinness, and high resistance to breakdown of dielectric at high electric fields. Capacitors with strip material not impregnated with liquid.

Investigations on MgO-dielectric GaN/AlGaN/GaN MOS-HEMTs by using an ultrasonic spray pyrolysis deposition technique

International Nuclear Information System (INIS)

Lee, Ching-Sung; Liu, Han-Yin; Wu, Ting-Ting; Hsu, Wei-Chou; Sun, Wen-Ching; Wei, Sung-Yen; Yu, Sheng-Min

2016-01-01

This work investigates GaN/Al 0.24 Ga 0.76 N/GaN metal-oxide-semiconductor high electron mobility transistors (MOS-HEMTs) grown on a Si substrate with MgO gate dielectric by using the non-vacuum ultrasonic spray pyrolysis deposition (USPD) technique. The oxide layer thickness is tuned to be 30 nm with the dielectric constant of 8.8. Electron spectroscopy for chemical analysis (ESCA), secondary ion mass spectrometry (SIMS), atomic force microscopy (AFM), transmission electron microscopy (TEM), C–V, low-frequency noise spectra, and pulsed I–V measurements are performed to characterize the interface and oxide quality for the MOS-gate structure. Improved device performances have been successfully achieved for the present MOS-HEMT (Schottky-gate HEMT) design, consisting of a maximum drain-source current density (I DS, max ) of 681 (500) mA/mm at V GS  = 4 (2) V, I DS at V GS  = 0 V (I DSS0 ) of 329 (289) mA/mm, gate-voltage swing (GVS) of 2.2 (1.6) V, two-terminal gate-drain breakdown voltage (BV GD ) of −123 (−104) V, turn-on voltage (V on ) of 1.7 (0.8) V, three-terminal off-state drain-source breakdown voltage (BV DS ) of 119 (96) V, and on/off current ratio (I on /I off ) of 2.5 × 10 8 (1.2 × 10 3 ) at 300 K. Improved high-frequency and power performances are also achieved in the present MOS-HEMT design. (paper)

Enhanced dielectric properties of ZrO2 thin films prepared in nitrogen ambient by pulsed laser deposition

International Nuclear Information System (INIS)

Zhu, J; Li, T L; Pan, B; Zhou, L; Liu, Z G

2003-01-01

ZrO 2 thin films were fabricated in O 2 ambient and in N 2 ambient by pulsed laser deposition (PLD), respectively. X-ray diffraction revealed that films prepared at 400 deg. C remained amorphous. The dielectric properties of amorphous ZrO 2 films were investigated by measuring the capacitance-frequency characteristics of Pt/ZrO 2 /Pt capacitor structures. The dielectric constant of the films deposited in N 2 ambient was larger than that of the films deposited in O 2 ambient. The dielectric loss was lower for films prepared in N 2 ambient. Atom force microscopy investigation indicated that films deposited in N 2 ambient had smoother surface than films deposited in O 2 ambient. Capacitance-voltage and current-voltage characteristics were studied. The equivalent oxide thickness (EOT) of films with 6.6 nm physical thickness deposited in N 2 ambient is lower than that of films deposited in O 2 ambient. An EOT of 1.38 nm for the film deposited in N 2 ambient was obtained, while the leakage current density was 94.6 mA cm -2 . Therefore, ZrO 2 thins deposited in N 2 ambient have enhanced dielectric properties due to the incorporation of nitrogen which leads to the formation of Zr-doped nitride interfacial layer, and is suggested to be a potential material for alternative high-k (high dielectric constant) gate dielectric applications

Atomic layer deposition grown composite dielectric oxides and ZnO for transparent electronic applications

International Nuclear Information System (INIS)

Gieraltowska, S.; Wachnicki, L.; Witkowski, B.S.; Godlewski, M.; Guziewicz, E.

2012-01-01

In this paper, we report on transparent transistor obtained using laminar structure of two high-k dielectric oxides (hafnium dioxide, HfO 2 and aluminum oxide, Al 2 O 3 ) and zinc oxide (ZnO) layer grown at low temperature (60 °C–100 °C) using Atomic Layer Deposition (ALD) technology. Our research was focused on the optimization of technological parameters for composite layers Al 2 O 3 /HfO 2 /Al 2 O 3 for thin film transistor structures with ZnO as a channel and a gate layer. We elaborate on the ALD growth of these oxides, finding that the 100 nm thick layers of HfO 2 and Al 2 O 3 exhibit fine surface flatness and required amorphous microstructure. Growth parameters are optimized for the monolayer growth mode and maximum smoothness required for gating.

Off Axis Growth of Strontium Titanate Films with High Dielectric Constant Tuning and Low Loss

Science.gov (United States)

Kampangkeaw, Satreerat

2002-03-01

Using off-axis pulsed laser deposition, we have grown strontium titanate (STO) films on neodymium gallate (NGO) and lanthanum aluminate (LAO) substrates. We measured the film dielectric constant and loss tangent as a function of temperature in the 10kHz to 1 MHz frequency range. We found that the loss is less than 0.01 We also obtained a figure of merit from the relative variation of the dielectric constant divided by the loss tangent. The obtained figured of merit at 35K and 1MHz is about 1000 comparable to bulk values. The dielectric constant of these films can be changed by a factor of 4-8 in the presence of a DC electric field up to 5V/μm. The films show significant variations of dielectric properties grown on different substrates at different locations respect to the axis of the plume. The STO films on LAO having high dielectric constant and dielectric tuning were grown in region near the center of the plume. On the other hand, STO on NGO shows this effect only on the films grown far from the plume axis.

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

Science.gov (United States)

Ishii, Yuichiro; Tanaka, Miki; Yabuuchi, Makoto; Sawada, Yohei; Tanaka, Shinji; Nii, Koji; Lu, Tien Yu; Huang, Chun Hsien; Sian Chen, Shou; Tse Kuo, Yu; Lung, Ching Cheng; Cheng, Osbert

2018-04-01

We propose a highly symmetrical 10 transistor (10T) 2-read/write (2RW) dual-port (DP) static random access memory (SRAM) bitcell in 28 nm high-k/metal-gate (HKMG) planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves the robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (I read) and read static noise margin (SNM) are respectively boosted by +20% and +15 mV by introducing the proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) N-channel MOSs (NMOSs). The minimum operating voltage (V min) of the proposed 256 kbit 10T DP SRAM is 0.53 V in the TT process, 25 °C under the worst access condition with read/write disturbances, and improved by 90 mV (15%) compared with the conventional one.

SiC Power MOSFET with Improved Gate Dielectric

Energy Technology Data Exchange (ETDEWEB)

Sbrockey, Nick M. [Structured Materials Industries, Inc., Piscataway, NJ (United States); Tompa, Gary S. [Structured Materials Industries, Inc., Piscataway, NJ (United States); Spencer, Michael G. [Structured Materials Industries, Inc., Piscataway, NJ (United States); Chandrashekhar, Chandra M.V. S. [Structured Materials Industries, Inc., Piscataway, NJ (United States)

2010-08-23

In this STTR program, Structured Materials Industries (SMI), and Cornell University are developing novel gate oxide technology, as a critical enabler for silicon carbide (SiC) devices. SiC is a wide bandgap semiconductor material, with many unique properties. SiC devices are ideally suited for high-power, highvoltage, high-frequency, high-temperature and radiation resistant applications. The DOE has expressed interest in developing SiC devices for use in extreme environments, in high energy physics applications and in power generation. The development of transistors based on the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structure will be critical to these applications.

A simulation-based proposed high-k heterostructure AlGaAs/Si junctionless n-type tunnel FET

International Nuclear Information System (INIS)

Rahi Shiromani Balmukund; Asthana Pranav; Ghosh Bahniman

2014-01-01

We propose a heterostructure junctionless tunnel field effect transistor (HJL-TFET) using AlGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain side. The whole AlGaAs/Si region is heavily doped n-type. The proposed HJL-TFET uses two isolated gates (named gate, gate1) with two different work functions (gate = 4.2 eV, gate1 = 5.2 eV respectively). The 2-D nature of HJL-TFET current flow is studied. The proposed structure is simulated in Silvaco with different gate dielectric materials. This structure exhibits a high on current in the range of 1.4 × 10 −6 A/μm, the off current remains as low as 9.1 × 10 −14 A/μm. So I ON /I OFF ratio of ≃ 10 8 is achieved. Point subthreshold swing has also been reduced to a value of ≃ 41 mV/decade for TiO 2 gate material. (semiconductor devices)

Brillouin light scattering studies on the mechanical properties of ultrathin, porous low-K dielectric films

Science.gov (United States)

Zhou, Wei; Sooryakumar, R.; King, Sean

2010-03-01

Low K dielectrics have predominantly replaced silicon dioxide as the interlayer dielectric material for interconnects in state of the art integrated circuits. To further reduce interconnect resistance-capacitance (RC) delays, additional reductions in the K for these low-K materials is being pursued by the introduction of controlled levels of porosity. The main challenge for porous low-K dielectrics is the substantial reduction in mechanical properties that is accompanied by the increased pore volume content needed to reduce K. We report on the application of the nondestructive Brillouin light scattering technique to monitor and characterize the mechanical properties of these porous films at thicknesses well below 200 nm that are pertinent to present applications. Observation of longitudinal and transverse standing wave acoustic resonances and the dispersion that accompany their transformation into traveling waves with finite in-plane wave vectors provides for the principal elastic constants that completely characterize the mechanical properties of these porous films. The mode amplitudes of the standing waves, their variation within the film, and the calculated Brillouin intensities account for most aspects of the spectra. The resulting elastic constants are compared with corresponding values obtained from other experimental techniques.

Dielectric material options for integrated capacitors

NARCIS (Netherlands)

Ruhl, G.; Lehnert, W.; Lukosius, M.; Wenger, C.; Baristiran Kaynak, C.; Blomberg, T.; Haukka, S.; Baumann, P.K.; Besling, W.F.A.; Roest, A.L.; Riou, B.; Lhostis, S.; Halimaou, A.; Roozeboom, F.; Langereis, E.; Kessels, W.M.M.; Zauner, A.; Rushworth, S.A.

2014-01-01

Future MIM capacitor generations will require significantly increased specific capacitances by utilization of high-k dielectric materials. In order to achieve high capacitance per chip area, these dielectrics have to be deposited in three-dimensional capacitor structures by ALD or AVD (atomic vapor

Quantum-coherence-assisted tunable on- and off-resonance tunneling through a quantum-dot-molecule dielectric film

International Nuclear Information System (INIS)

Shen Jianqi; Zeng Ruixi

2017-01-01

Quantum-dot-molecular phase coherence (and the relevant quantum-interference-switchable optical response) can be utilized to control electromagnetic wave propagation via a gate voltage, since quantum-dot molecules can exhibit an effect of quantum coherence (phase coherence) when quantum-dot-molecular discrete multilevel transitions are driven by an electromagnetic wave. Interdot tunneling of carriers (electrons and holes) controlled by the gate voltage can lead to destructive quantum interference in a quantum-dot molecule that is coupled to an incident electromagnetic wave, and gives rise to a quantum coherence effect (e.g., electromagnetically induced transparency, EIT) in a quantum-dot-molecule dielectric film. The tunable on- and off-resonance tunneling effect of an incident electromagnetic wave (probe field) through such a quantum-coherent quantum-dot-molecule dielectric film is investigated. It is found that a high gate voltage can lead to the EIT phenomenon of the quantum-dot-molecular systems. Under the condition of on-resonance light tunneling through the present quantum-dot-molecule dielectric film, the probe field should propagate without loss if the probe frequency detuning is zero. Such an effect caused by both EIT and resonant tunneling, which is sensitive to the gate voltage, can be utilized for designing devices such as photonic switching, transistors, and logic gates. (author)

Dielectric and thermal properties of isotactic polypropylene/hexagonal boron nitride composites for high-frequency applications

International Nuclear Information System (INIS)

Takahashi, Susumu; Imai, Yusuke; Kan, Akinori; Hotta, Yuji; Ogawa, Hirotaka

2014-01-01

Highlights: • The degree of orientation of the hBN could be controlled by the fabrication process. • The dielectric constants of composites ranged between 2.25 and 3.39. • The dielectric loss of composites was on the order of 10 −4 for all compositions. • The thermal conductivity were improved by controlling orientation of hBN. - Abstract: Dielectric composites aimed for high frequency applications were prepared by using anisotropic hexagonal boron nitride (hBN) particles as a fillers and isotactic polypropylene (iPP) as polymer matrix. Dielectric and thermal properties of the composites were studied, focusing on the filler orientation in the plate-shape specimens and filler concentration up to 40 vol%. The degree of orientation of the filler was controlled by the composite fabrication process. Hot-pressing gave relatively random orientation of the filler in the matrix, while injection molding induced a high orientation. Dielectric constant (ε r ) of the composites ranged between 2.25 and 3.39. The estimation of ε r based on the Bruggeman mixing model agreed well with the measured value. Low dielectric losses (tan δ) at microwave frequencies, on the order of 10 −4 , were obtained for all the compositions. Through-thickness thermal conductivity (k) of the hot-pressed samples showed a drastic increase with increasing the filler concentration, reaching up to 2.1 W/m K at 40 vol% of hBN. The filler concentration dependence of k was less significant for the injection molded composites. In-plane thermal expansion was almost independent on the filler orientation, while the coefficient of thermal expansion for the thickness direction of the hot-pressed sample was reduced to approximately half of the injection molded counterpart. These differences in thermal conductivity and thermal expansion are thought to arise from the difference in hBN filler orientation

High performance germanium MOSFETs

International Nuclear Information System (INIS)

Saraswat, Krishna; Chui, Chi On; Krishnamohan, Tejas; Kim, Donghyun; Nayfeh, Ammar; Pethe, Abhijit

2006-01-01

Ge is a very promising material as future channel materials for nanoscale MOSFETs due to its high mobility and thus a higher source injection velocity, which translates into higher drive current and smaller gate delay. However, for Ge to become main-stream, surface passivation and heterogeneous integration of crystalline Ge layers on Si must be achieved. We have demonstrated growth of fully relaxed smooth single crystal Ge layers on Si using a novel multi-step growth and hydrogen anneal process without any graded buffer SiGe layer. Surface passivation of Ge has been achieved with its native oxynitride (GeO x N y ) and high-permittivity (high-k) metal oxides of Al, Zr and Hf. High mobility MOSFETs have been demonstrated in bulk Ge with high-k gate dielectrics and metal gates. However, due to their smaller bandgap and higher dielectric constant, most high mobility materials suffer from large band-to-band tunneling (BTBT) leakage currents and worse short channel effects. We present novel, Si and Ge based heterostructure MOSFETs, which can significantly reduce the BTBT leakage currents while retaining high channel mobility, making them suitable for scaling into the sub-15 nm regime. Through full band Monte-Carlo, Poisson-Schrodinger and detailed BTBT simulations we show a dramatic reduction in BTBT and excellent electrostatic control of the channel, while maintaining very high drive currents in these highly scaled heterostructure DGFETs. Heterostructure MOSFETs with varying strained-Ge or SiGe thickness, Si cap thickness and Ge percentage were fabricated on bulk Si and SOI substrates. The ultra-thin (∼2 nm) strained-Ge channel heterostructure MOSFETs exhibited >4x mobility enhancements over bulk Si devices and >10x BTBT reduction over surface channel strained SiGe devices

High performance germanium MOSFETs

Energy Technology Data Exchange (ETDEWEB)

Saraswat, Krishna [Department of Electrical Engineering, Stanford University, Stanford, CA 94305 (United States)]. E-mail: saraswat@stanford.edu; Chui, Chi On [Department of Electrical Engineering, Stanford University, Stanford, CA 94305 (United States); Krishnamohan, Tejas [Department of Electrical Engineering, Stanford University, Stanford, CA 94305 (United States); Kim, Donghyun [Department of Electrical Engineering, Stanford University, Stanford, CA 94305 (United States); Nayfeh, Ammar [Department of Electrical Engineering, Stanford University, Stanford, CA 94305 (United States); Pethe, Abhijit [Department of Electrical Engineering, Stanford University, Stanford, CA 94305 (United States)

2006-12-15

Ge is a very promising material as future channel materials for nanoscale MOSFETs due to its high mobility and thus a higher source injection velocity, which translates into higher drive current and smaller gate delay. However, for Ge to become main-stream, surface passivation and heterogeneous integration of crystalline Ge layers on Si must be achieved. We have demonstrated growth of fully relaxed smooth single crystal Ge layers on Si using a novel multi-step growth and hydrogen anneal process without any graded buffer SiGe layer. Surface passivation of Ge has been achieved with its native oxynitride (GeO {sub x}N {sub y} ) and high-permittivity (high-k) metal oxides of Al, Zr and Hf. High mobility MOSFETs have been demonstrated in bulk Ge with high-k gate dielectrics and metal gates. However, due to their smaller bandgap and higher dielectric constant, most high mobility materials suffer from large band-to-band tunneling (BTBT) leakage currents and worse short channel effects. We present novel, Si and Ge based heterostructure MOSFETs, which can significantly reduce the BTBT leakage currents while retaining high channel mobility, making them suitable for scaling into the sub-15 nm regime. Through full band Monte-Carlo, Poisson-Schrodinger and detailed BTBT simulations we show a dramatic reduction in BTBT and excellent electrostatic control of the channel, while maintaining very high drive currents in these highly scaled heterostructure DGFETs. Heterostructure MOSFETs with varying strained-Ge or SiGe thickness, Si cap thickness and Ge percentage were fabricated on bulk Si and SOI substrates. The ultra-thin ({approx}2 nm) strained-Ge channel heterostructure MOSFETs exhibited >4x mobility enhancements over bulk Si devices and >10x BTBT reduction over surface channel strained SiGe devices.

Thermal Conductivity and High-Frequency Dielectric Properties of Pressureless Sintered SiC-AlN Multiphase Ceramics

Directory of Open Access Journals (Sweden)

Jialin Gu

2018-06-01

Full Text Available SiC-AlN multiphase ceramics with 10 wt. %Y2O3-BaO-SiO2 additives were fabricated by pressureless sintering in a nitrogen atmosphere. The effects of SiC contents and sintering temperatures on the sinterability, microstructure, thermal conductivity and high-frequency dielectric properties were characterized. In addition to 6H-SiC and AlN, the samples also contained Y3Al5O12 and Y4Al2O9. SiC-AlN ceramics sintered with 50 wt. % SiC at 2173 K exhibited the best thermal diffusivity and thermal conductivity (26.21 mm2·s−1 and 61.02 W·m−1·K−1, respectively. The dielectric constant and dielectric loss of the sample sintered with 50 wt. % SiC and 2123 K were 33–37 and 0.4–0.5 at 12.4–18 GHz. The dielectric constant and dielectric loss of the samples decreased as the frequency of electromagnetic waves increased from 12.4–18 GHz. The dielectric thermal conductivity properties of the SiC-AlN samples are discussed.

Ballistic transport of graphene pnp junctions with embedded local gates

International Nuclear Information System (INIS)

Nam, Seung-Geol; Ki, Dong-Keun; Kim, Youngwook; Kim, Jun Sung; Lee, Hu-Jong; Park, Jong Wan

2011-01-01

We fabricated graphene pnp devices, by embedding pre-defined local gates in an oxidized surface layer of a silicon substrate. With neither deposition of dielectric material on the graphene nor electron-beam irradiation, we obtained high-quality graphene pnp devices without degradation of the carrier mobility even in the local-gate region. The corresponding increased mean free path leads to the observation of ballistic and phase-coherent transport across a local gate 130 nm wide, which is about an order of magnitude wider than reported previously. Furthermore, in our scheme, we demonstrated independent control of the carrier density in the local-gate region, with a conductance map very much distinct from those of top-gated devices. This was caused by the electric field arising from the global back gate being strongly screened by the embedded local gate. Our scheme allows the realization of ideal multipolar graphene junctions with ballistic carrier transport.

Black Phosphorus Based Field Effect Transistors with Simultaneously Achieved Near Ideal Subthreshold Swing and High Hole Mobility at Room Temperature.

Science.gov (United States)

Liu, Xinke; Ang, Kah-Wee; Yu, Wenjie; He, Jiazhu; Feng, Xuewei; Liu, Qiang; Jiang, He; Dan Tang; Wen, Jiao; Lu, Youming; Liu, Wenjun; Cao, Peijiang; Han, Shun; Wu, Jing; Liu, Wenjun; Wang, Xi; Zhu, Deliang; He, Zhubing

2016-04-22

Black phosphorus (BP) has emerged as a promising two-dimensional (2D) material for next generation transistor applications due to its superior carrier transport properties. Among other issues, achieving reduced subthreshold swing and enhanced hole mobility simultaneously remains a challenge which requires careful optimization of the BP/gate oxide interface. Here, we report the realization of high performance BP transistors integrated with HfO2 high-k gate dielectric using a low temperature CMOS process. The fabricated devices were shown to demonstrate a near ideal subthreshold swing (SS) of ~69 mV/dec and a room temperature hole mobility of exceeding >400 cm(2)/Vs. These figure-of-merits are benchmarked to be the best-of-its-kind, which outperform previously reported BP transistors realized on traditional SiO2 gate dielectric. X-ray photoelectron spectroscopy (XPS) analysis further reveals the evidence of a more chemically stable BP when formed on HfO2 high-k as opposed to SiO2, which gives rise to a better interface quality that accounts for the SS and hole mobility improvement. These results unveil the potential of black phosphorus as an emerging channel material for future nanoelectronic device applications.

Evaluation of high temperature capacitor dielectrics

Science.gov (United States)

Hammoud, Ahmad N.; Myers, Ira T.

1992-01-01

Experiments were carried out to evaluate four candidate materials for high temperature capacitor dielectric applications. The materials investigated were polybenzimidazole polymer and three aramid papers: Voltex 450, Nomex 410, and Nomex M 418, an aramid paper containing 50 percent mica. The samples were heat treated for six hours at 60 C and the direct current and 60 Hz alternating current breakdown voltages of both dry and impregnated samples were obtained in a temperature range of 20 to 250 C. The samples were also characterized in terms of their dielectric constant, dielectric loss, and conductivity over this temperature range with an electrical stress of 60 Hz, 50 V/mil present. Additional measurements are underway to determine the volume resistivity, thermal shrinkage, and weight loss of the materials. Preliminary data indicate that the heat treatment of the films slightly improves the dielectric properties with no influence on their breakdown behavior. Impregnation of the samples leads to significant increases in both alternating and direct current breakdown strength. The results are discussed and conclusions made concerning their suitability as high temperature capacitor dielectrics.

The Performance Improvement of N2 Plasma Treatment on ZrO2 Gate Dielectric Thin-Film Transistors with Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition IGZO Channel.

Science.gov (United States)

Wu, Chien-Hung; Huang, Bo-Wen; Chang, Kow-Ming; Wang, Shui-Jinn; Lin, Jian-Hong; Hsu, Jui-Mei

2016-06-01

The aim of this paper is to illustrate the N2 plasma treatment for high-κ ZrO2 gate dielectric stack (30 nm) with indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs). Experimental results reveal that a suitable incorporation of nitrogen atoms could enhance the device performance by eliminating the oxygen vacancies and provide an amorphous surface with better surface roughness. With N2 plasma treated ZrO2 gate, IGZO channel is fabricated by atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) technique. The best performance of the AP-PECVD IGZO TFTs are obtained with 20 W-90 sec N2 plasma treatment with field-effect mobility (μ(FET)) of 22.5 cm2/V-s, subthreshold swing (SS) of 155 mV/dec, and on/off current ratio (I(on)/I(off)) of 1.49 x 10(7).

An EELS sub-nanometer investigation of the dielectric gate stack for the realization of InGaAs based MOSFET devices

International Nuclear Information System (INIS)

Longo, P; Paterson, G W; Craven, A J; Holland, M C; Thayne, I G

2010-01-01

In this paper, a subnanometer investigation of the Ga 2 O 3 /GdGaO dielectric gate stack deposited onto InGaAs is presented. Results regarding the influence of the growth conditions on the interface region from a chemical and morphological point of view are presented. The chemical information reported in this paper has been obtained using electron energy loss spectroscopy (EELS) that was carried out in a scanning transmission electron microscope ((S)TEM) showing both spatial and depth resolution.

Low-voltage organic field-effect transistors based on novel high-κ organometallic lanthanide complex for gate insulating materials

Directory of Open Access Journals (Sweden)

Qi Liu

2014-08-01

Full Text Available A novel high-κ organometallic lanthanide complex, Eu(tta3L (tta=2-thenoyltrifluoroacetonate, L = 4,5-pinene bipyridine, is used as gate insulating material to fabricate low-voltage pentacene field-effect transistors (FETs. The optimized gate insulator exhibits the excellent properties such as low leakage current density, low surface roughness, and high dielectric constant. When operated under a low voltage of −5 V, the pentacene FET devices show the attractive electrical performance, e.g. carrier mobility (μFET of 0.17 cm2 V−1 s−1, threshold voltage (Vth of −0.9 V, on/off current ratio of 5 × 103, and subthreshold slope (SS of 1.0 V dec−1, which is much better than that of devices obtained on conventional 300 nm SiO2 substrate (0.13 cm2 V−1 s−1, −7.3 V and 3.1 V dec−1 for μFET, Vth and SS value when operated at −30 V. These results indicate that this kind of high-κ organometallic lanthanide complex becomes a promising candidate as gate insulator for low-voltage organic FETs.

Surface and interfacial chemistry of high-k dielectric and interconnect materials on silicon

Science.gov (United States)

Kirsch, Paul Daniel

Surfaces and interfaces play a critical role in the manufacture and function of silicon based integrated circuits. It is therefore reasonable to study the chemistries at these surfaces and interfaces to improve existing processes and to develop new ones. Model barium strontium titanate high-k dielectric systems have been deposited on ultrathin silicon oxynitride in ultrahigh vacuum. The resulting nanostructures are characterized with secondary ion mass spectroscopy (SIMS) and X-ray photoelectron spectroscopy (XPS). An interfacial reaction between Ba and Sr atoms and SiOxNy was found to create silicates, BaSixOy or SrSi xOy. Inclusion of N in the interfacial oxide decreased silicate formation in both Ba and Sr systems. Furthermore, inclusion of N in the interfacial oxide decreased the penetration of Ba and Sr containing species, such as silicides and silicates. Sputter deposited HfO2 was studied on nitrided and unnitrided Si(100) surfaces. XPS and SIMS were used to verify the presence of interfacial HfSixOy and estimate its relative amount on both nitrided and unnitrided samples. More HfSixOy formed without the SiNx interfacial layer. These interfacial chemistry results are then used to explain the electrical measurements obtained from metal oxide semiconductor (MOS) capacitors. MOS capacitors with interfacial SiNx exhibit reduced leakage current and increased capacitance. Lastly, surface science techniques were used to develop a processing technique for reducing thin films of copper (II) and copper (I) oxide to copper. Deuterium atoms (D*) and methyl radicals (CH3*) were shown to reduce Cu 2+ and/or Cu1+ to Cu0 within 30 min at a surface temperature of 400 K under a flux of 1 x 1015 atoms/cm2s. Temperature programmed desorption experiments suggest that oxygen leaves the surface as D2O and CO2 for the D* and CH3* treated surfaces, respectively.

Electrical characterization of ALD HfO2 high-k dielectrics on ( 2 ¯ 01) β-Ga2O3

Science.gov (United States)

Shahin, David I.; Tadjer, Marko J.; Wheeler, Virginia D.; Koehler, Andrew D.; Anderson, Travis J.; Eddy, Charles R.; Christou, Aris

2018-01-01

The electrical quality of HfO2 dielectrics grown by thermal atomic layer deposition at 175 °C on n-type ( 2 ¯ 01) β-Ga2O3 has been studied through capacitance- and current-voltage measurements on metal-oxide-semiconductor capacitors. These capacitors exhibited excellent electrical characteristics, including dual-sweep capacitance-voltage curves with low hysteresis and stretch-out and a frequency-stable dielectric constant of k˜14 when measured between 10 kHz and 1 MHz. The C-V curves exhibited a uniform and repeatable +1.05 V shift relative to the ideal case when swept from 3.5 to -5 V, yielding positively measured flatband (+2.15 V) and threshold (+1.05 V) voltages that may be useful for normally off n-channel Ga2O3 devices. Using the Terman method, an average interface trap density of 1.3 × 1011 cm-2.eV-1 was obtained between 0.2 and 0.6 eV below the conduction band edge. The forward bias current-voltage characteristic was successfully fitted to the Fowler-Nordheim tunneling model at a field strength of 5 MV/cm, allowing an extraction of a 1.3 eV conduction band offset between HfO2 and Ga2O3, which matches the value previously determined from x-ray photoelectron spectroscopy. However, a temperature dependence in the leakage current was observed. These results suggest that HfO2 is an appealing dielectric for Ga2O3 device applications.

High-pressure cell for simultaneous dielectric and neutron spectroscopy

Science.gov (United States)

Sanz, Alejandro; Hansen, Henriette Wase; Jakobsen, Bo; Pedersen, Ib H.; Capaccioli, Simone; Adrjanowicz, Karolina; Paluch, Marian; Gonthier, Julien; Frick, Bernhard; Lelièvre-Berna, Eddy; Peters, Judith; Niss, Kristine

2018-02-01

In this article, we report on the design, manufacture, and testing of a high-pressure cell for simultaneous dielectric and neutron spectroscopy. This cell is a unique tool for studying dynamics on different time scales, from kilo- to picoseconds, covering universal features such as the α relaxation and fast vibrations at the same time. The cell, constructed in cylindrical geometry, is made of a high-strength aluminum alloy and operates up to 500 MPa in a temperature range between roughly 2 and 320 K. In order to measure the scattered neutron intensity and the sample capacitance simultaneously, a cylindrical capacitor is positioned within the bore of the high-pressure container. The capacitor consists of two concentric electrodes separated by insulating spacers. The performance of this setup has been successfully verified by collecting simultaneous dielectric and neutron spectroscopy data on dipropylene glycol, using both backscattering and time-of-flight instruments. We have carried out the experiments at different combinations of temperature and pressure in both the supercooled liquid and glassy state.

A comparative study of amorphous InGaZnO thin-film transistors with HfOxNy and HfO2 gate dielectrics

International Nuclear Information System (INIS)

Zou, Xiao; Tong, Xingsheng; Fang, Guojia; Yuan, Longyan; Zhao, Xingzhong

2010-01-01

High-κ HfO x N y and HfO 2 films are applied to amorphous InGaZnO (a-IGZO) devices as gate dielectric using radio-frequency reactive sputtering. The electrical characteristics and reliability of a-IGZO metal–insulator–semiconductor (MIS) capacitors and thin-film transistors (TFTs) are then investigated. Experimental results indicate that the nitrogen incorporation into HfO 2 can effectively improve the interface quality and enhance the reliability of the devices. Electrical properties with an interface-state density of 5.2 × 10 11 eV −1 cm −2 , capacitance equivalent thickness of 1.65 nm, gate leakage current density of 3.4 × 10 −5 A cm −2 at V fb +1 V, equivalent permittivity of 23.6 and hysteresis voltage of 110 mV are obtained for an Al/HfO x N y /a-IGZO MIS capacitor. Superior performance of HfO x N y /a-IGZO TFTs has also been achieved with a low threshold voltage of 0.33 V, a high saturation mobility of 12.1 cm 2 V −1 s −1 and a large on–off current ratio up to 7 × 10 7 (W/L = 500/20 µm) at 3 V

Dielectric and AC-conductivity studies of Dy2O3 doped (K0.5Na0.5NbO3 ceramics

Directory of Open Access Journals (Sweden)

Mahesh Peddigari

2014-08-01

Full Text Available (K0.5Na0.5NbO3 + x wt.% Dy2O3 (x = 0–1.5 ferroelectric ceramics were prepared by conventional solid state reaction method. XRD patterns revealed that orthorhombic symmetry has transformed into psuedocubic symmetry with increasing the substitution of Dy3+ in the Na+ site. Temperature and frequency dependences of relative dielectric permittivity maximum conforms the transformation from normal ferroelectric to relaxor ferroelectric behaviour. Frequency dependence of the relative dielectric permittivity maximum temperature observed for the samples with x ≥ 1.0 and satisfied the Vogel–Fulcher law. The diffuseness exponent γ (1.27–1.95 estimated from the high temperature slopes of the diffused dielectric permittivity data reveals that the degree of relaxor behavior increases with increasing the amount of Dy2O3. The temperature dependence of AC-conductivity σAC (T analysis in the range 310 K < T < 470 K reveals the existence of variable range hopping of charge carriers with average hopping length RH and hopping energy EH are in the range 8.5–27 Å and 48–153 meV, respectively. Voltage dependent dielectric constant measurements confirm the ferroelectric nature of KNN+ x wt% Dy2O3 ceramics.

Characterization, integration and reliability of HfO2 and LaLuO3 high-κ/metal gate stacks for CMOS applications

International Nuclear Information System (INIS)

Nichau, Alexander

2013-01-01

. A lower limit found was EOT=5 Aa for Al doping inside TiN. The doping of TiN on LaLuO 3 is proven by electron energy loss spectroscopy (EELS) studies to modify the interfacial silicate layer to La-rich silicates or even reduce the layer. The oxide quality in Si/HfO 2 /TiN gate stacks is characterized by charge pumping and carrier mobility measurements on 3d MOSFETs a.k.a. FinFETs. The oxide quality in terms of the number of interface (and oxide) traps on top- and sidewall of FinFETs is compared for three different annealing processes. A high temperature anneal of HfO 2 improves significantly the oxide quality and mobility. The gate oxide integrity (GOI) of gate stacks below 1 nm EOT is determined by time-dependent dielectric breakdown (TDDB) measurements on FinFETs with HfO 2 /TiN gate stacks. A successful EOT scaling has always to consider the oxide quality and resulting reliability. Degraded oxide quality leads to mobility degradation and earlier soft-breakdown, i.e. leakage current increase.

High thermal conductivity lossy dielectric using co-densified multilayer configuration

Science.gov (United States)

Tiegs, Terry N.; Kiggans, Jr., James O.

2003-06-17

Systems and methods are described for loss dielectrics. A method of manufacturing a lossy dielectric includes providing at least one high dielectric loss layer and providing at least one high thermal conductivity-electrically insulating layer adjacent the at least one high dielectric loss layer and then densifying together. The systems and methods provide advantages because the lossy dielectrics are less costly and more environmentally friendly than the available alternatives.

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

Science.gov (United States)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

Very fast, high peak-power, planar triode amplifiers for driving optical gates

International Nuclear Information System (INIS)

Howland, M.M.; Davis, S.J.; Gagnon, W.L.

1979-01-01

Recent extensions of the peak power capabilities of planar triodes have made possible the latter's use as very fast pulse amplifiers, to drive optical gates within high-power Nd:glass laser chains. These pulse amplifiers switch voltages in the 20 kV range with rise times of a few nanoseconds, into crystal optical gates that are essentially capacitive loads. This paper describes a simplified procedure for designing these pulse amplifiers. It further outlines the use of bridged-T constant resistance networks to transform load capacitance into pure resistance, independent of frequency

An “ohmic-first” self-terminating gate-recess technique for normally-off Al2O3/GaN MOSFET

Science.gov (United States)

Wang, Hongyue; Wang, Jinyan; Li, Mengjun; He, Yandong; Wang, Maojun; Yu, Min; Wu, Wengang; Zhou, Yang; Dai, Gang

2018-04-01

In this article, an ohmic-first AlGaN/GaN self-terminating gate-recess etching technique was demonstrated where ohmic contact formation is ahead of gate-recess-etching/gate-dielectric-deposition (GRE/GDD) process. The ohmic contact exhibits few degradations after the self-terminating gate-recess process. Besides, when comparing with that using the conventional fabrication process, the fabricated device using the ohmic-first fabrication process shows a better gate dielectric quality in terms of more than 3 orders lower forward gate leakage current, more than twice higher reverse breakdown voltage as well as better stability. Based on this proposed technique, the normally-off Al2O3/GaN MOSFET exhibits a threshold voltage (V th) of ˜1.8 V, a maximum drain current of ˜328 mA/mm, a forward gate leakage current of ˜10-6 A/mm and an off-state breakdown voltage of 218 V at room temperature. Meanwhile, high temperature characteristics of the device was also evaluated and small variations (˜7.6%) of the threshold voltage was confirmed up to 300 °C.

Tunnel field-effect transistor with two gated intrinsic regions

Directory of Open Access Journals (Sweden)

Y. Zhang

2014-07-01

Full Text Available In this paper, we propose and validate (using simulations a novel design of silicon tunnel field-effect transistor (TFET, based on a reverse-biased p+-p-n-n+ structure. 2D device simulation results show that our devices have significant improvements of switching performance compared with more conventional devices based on p-i-n structure. With independent gate voltages applied to two gated intrinsic regions, band-to-band tunneling (BTBT could take place at the p-n junction, and no abrupt degenerate doping profile is required. We developed single-side-gate (SSG structure and double-side-gate (DSG structure. SSG devices with HfO2 gate dielectric have a point subthreshold swing of 9.58 mV/decade, while DSG devices with polysilicon gate electrode material and HfO2 gate dielectric have a point subthreshold swing of 16.39 mV/decade. These DSG devices have ON-current of 0.255 μA/μm, while that is lower for SSG devices. Having two nano-scale independent gates will be quite challenging to realize with good uniformity across the wafer and the improved behavior of our TFET makes it a promising steep-slope switch candidate for further investigations.

Perovskite oxynitride LaTiO{sub x}N{sub y} thin films: Dielectric characterization in low and high frequencies

Energy Technology Data Exchange (ETDEWEB)

Lu, Y.; Ziani, A. [Institut d' Electronique et de Telecommunications de Rennes (IETR) UMR-CNRS 6164, groupe ' Antennes et Hyperfrequences' , University of Rennes 1, UEB, IUT Saint Brieuc, 18 rue Henri Wallon, 22004 Saint Brieuc cedex (France); Le Paven-Thivet, C., E-mail: claire.lepaven@univ-rennes1.fr [Institut d' Electronique et de Telecommunications de Rennes (IETR) UMR-CNRS 6164, groupe ' Antennes et Hyperfrequences' , University of Rennes 1, UEB, IUT Saint Brieuc, 18 rue Henri Wallon, 22004 Saint Brieuc cedex (France); Benzerga, R.; Le Gendre, L. [Institut d' Electronique et de Telecommunications de Rennes (IETR) UMR-CNRS 6164, groupe ' Antennes et Hyperfrequences' , University of Rennes 1, UEB, IUT Saint Brieuc, 18 rue Henri Wallon, 22004 Saint Brieuc cedex (France); Fasquelle, D. [Laboratoire d' Etude des Materiaux et des Composants pour l' Electronique (LEMCEL) UPRES-EA 2601, University of Littoral-Cote d' Opale, 50 rue Ferdinand Buisson, F-62228 Calais cedex (France); Kassem, H. [Laboratoire de l' Integration du Materiau au Systeme(IMS) UMR-CNRS 5218, groupe Materiaux, University of Bordeaux 1, 16 avenue Pey-Berland, 33607 Pessac (France); and others

2011-11-01

Lanthanum titanium oxynitride (LaTiO{sub x}N{sub y}) thin films are studied with respect to their dielectric properties in low and high frequencies. Thin films are deposited by radio frequency magnetron sputtering on different substrates. Effects of nitrogen content and crystalline quality on dielectric properties are investigated. In low-frequency range, textured LaTiO{sub x}N{sub y} thin films deposited on conductive single crystal Nb-STO show a dielectric constant {epsilon} Prime Almost-Equal-To 140 with low losses tan{delta} = 0.012 at 100 kHz. For the LaTiO{sub x}N{sub y} polycrystalline films deposited on conductive silicon substrates with platinum (Pt/Ti/SiO{sub 2}/Si), the tunability reached up to 57% for a weak electric field of 50 kV/cm. In high-frequency range, epitaxial LaTiO{sub x}N{sub y} films deposited on MgO substrate present a high dielectric constant with low losses ({epsilon} Prime Almost-Equal-To 170, tan{delta} = 0.011, 12 GHz).

Indexes to Volume 76

Indian Academy of Sciences (India)

and CO by positron impact: ... 519–531. Dielectric relaxation studies in 5CB nematic liquid crystal at 9 GHz under ... with varying oxide thickness. Sanjeev K Gupta, A ... semiconductor devices with high-K gate dielectric impacts on the inversion.

Self-Healing, High-Permittivity Silicone Dielectric Elastomer

DEFF Research Database (Denmark)

Madsen, Frederikke Bahrt; Yu, Liyun; Skov, Anne Ladegaard

2016-01-01

possesses high dielectric permittivity and consists of an interpenetrating polymer network of silicone elastomer and ionic silicone species that are cross-linked through proton exchange between amines and acids. The ionically cross-linked silicone provides self-healing properties after electrical breakdown...... or cuts made directly to the material due to the reassembly of the ionic bonds that are broken during damage. The dielectric elastomers presented in this paper pave the way to increased lifetimes and the ability of dielectric elastomers to survive millions of cycles in high-voltage conditions....

pH sensor using AlGaN/GaN high electron mobility transistors with Sc2O3 in the gate region

International Nuclear Information System (INIS)

Kang, B. S.; Wang, H. T.; Ren, F.; Gila, B. P.; Abernathy, C. R.; Pearton, S. J.; Johnson, J. W.; Rajagopal, P.; Roberts, J. C.; Piner, E. L.; Linthicum, K. J.

2007-01-01

Ungated AlGaN/GaN high electron mobility transistors (HEMTs) exhibit large changes in current upon exposing the gate region to polar liquids. The polar nature of the electrolyte introduced leds to a change of surface charges, producing a change in surface potential at the semiconductor/liquid interface. The use of Sc 2 O 3 gate dielectric produced superior results to either a native oxide or UV ozone-induced oxide in the gate region. The ungated HEMTs with Sc 2 O 3 in the gate region exhibited a linear change in current between pH 3 and 10 of 37 μA/pH. The HEMT pH sensors show stable operation with a resolution of <0.1 pH over the entire pH range. The results indicate that the HEMTs may have application in monitoring pH solution changes between 7 and 8, the range of interest for testing human blood

Bimodal gate-dielectric deposition for improved performance of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

International Nuclear Information System (INIS)

Pang Liang; Kim, Kyekyoon

2012-01-01

A bimodal deposition scheme combining radiofrequency magnetron sputtering and plasma enhanced chemical vapour deposition (PECVD) is proposed as a means for improving the performance of GaN-based metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs). High-density sputtered-SiO 2 is utilized to reduce the gate leakage current and enhance the breakdown voltage while low-density PECVD-SiO 2 is employed to buffer the sputtering damage and further increase the drain current by engineering the stress-induced-polarization. Thus-fabricated MOSHEMT exhibited a low leakage current of 4.21 × 10 -9 A mm -1 and high breakdown voltage of 634 V for a gate-drain distance of 6 µm, demonstrating the promise of bimodal-SiO 2 deposition scheme for the development of GaN-based MOSHEMTs for high-power application. (paper)

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

Science.gov (United States)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

Processing and performance of organic insulators as a gate layer in ...

Indian Academy of Sciences (India)

Abstract. Fabrication of organic thin film transistor (OTFT) on flexible substrates is a challenge, because of its low softening temperature, high roughness and flexible nature. Although several organic dielectrics have been used as gate insulator, it is difficult to choose one in absence of a comparative study covering ...

A high energy density relaxor antiferroelectric pulsed capacitor dielectric

Energy Technology Data Exchange (ETDEWEB)

Jo, Hwan Ryul; Lynch, Christopher S. [Department of Mechanical and Aerospace Engineering, University of California, Los Angeles (UCLA), Los Angeles, California 90095 (United States)

2016-01-14

Pulsed capacitors require high energy density and low loss, properties that can be realized through selection of composition. Ceramic (Pb{sub 0.88}La{sub 0.08})(Zr{sub 0.91}Ti{sub 0.09})O{sub 3} was found to be an ideal candidate. La{sup 3+} doping and excess PbO were used to produce relaxor antiferroelectric behavior with slim and slanted hysteresis loops to reduce the dielectric hysteresis loss, to increase the dielectric strength, and to increase the discharge energy density. The discharge energy density of this composition was found to be 3.04 J/cm{sup 3} with applied electric field of 170 kV/cm, and the energy efficiency, defined as the ratio of the discharge energy density to the charging energy density, was 0.920. This high efficiency reduces the heat generated under cyclic loading and improves the reliability. The properties were observed to degrade some with temperature increase above 80 °C. Repeated electric field cycles up to 10 000 cycles were applied to the specimen with no observed performance degradation.

Gate driver with high common mode rejection and self turn-on mitigation for a 10 kV SiC MOSFET enabled MV converter

DEFF Research Database (Denmark)

Dalal, Dipen Narendrabhai; Christensen, Nicklas; Jørgensen, Asger Bjørn

2017-01-01

Miller clamp circuit for a 10 kV half bridge SiC MOSFET power module. Designed power supply and the gate driver circuit are verified in a double pulse test setup and a continuous switching operation using the 10 kV half bridge silicon carbide MOSFET power module. An in-depth experimental verification...

Materials science, integration, and performance characterization of high-dielectric constant thin film based devices

Science.gov (United States)

Fan, Wei

To overcome the oxidation and diffusion problems encountered during Copper integration with oxide thin film-based devices, TiAl/Cu/Ta heterostructure has been first developed in this study. Investigation on the oxidation and diffusion resistance of the laminate structure showed high electrical conductance and excellent thermal stability in oxygen environment. Two amorphous oxide layers that were formed on both sides of the TiAl barrier after heating in oxygen have been revealed as the structure that effectively prevents oxygen penetration and protects the integrity of underlying Cu layer. Polycrystalline (BaxSr1-x)TiO3 (BST) thin films were subsequently deposited on the Cu-based bottom electrode by RF magnetron sputtering to investigate the interaction between the oxide and Cu layers. The thickness of the interfacial layer and interface roughness play critical roles in the optimization of the electrical performance of the BST capacitors using Cu-based electrode. It was determined that BST deposition at moderate temperature followed by rapid thermal annealing in pure oxygen yields BST/Cu capacitors with good electrical properties for application to high frequency devices. The knowledge obtained on the study of barrier properties of TiAl inspired a continuous research on the materials science issues related to the application of the hybrid TiAlOx, as high-k gate dielectric in MOSFET devices. Novel fabrication process such as deposition of ultra-thin TiAl alloy layer followed by oxidation with atomic oxygen has been established in this study. Stoichiometric amorphous TiAlOx layers, exhibiting only Ti4+ and Al3+ states, were produced with a large variation of oxidation temperature (700°C to room temperature). The interfacial SiOx formation between TiAlOx and Si was substantially inhibited by the use of the low temperature oxidation process. Electrical characterization revealed a large permittivity of 30 and an improved band structure for the produced TiAlOx layers

Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate

International Nuclear Information System (INIS)

Liu, Hsi-Wen; Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Chang, Ting-Chang; Chen, Ching-En; Tseng, Tseung-Yuen; Lin, Chien-Yu; Cheng, Osbert; Huang, Cheng-Tung; Ye, Yi-Han

2016-01-01

This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

Dual-Gate p-GaN Gate High Electron Mobility Transistors for Steep Subthreshold Slope.

Science.gov (United States)

Bae, Jong-Ho; Lee, Jong-Ho

2016-05-01

A steep subthreshold slope characteristic is achieved through p-GaN gate HEMT with dual-gate structure. Obtained subthreshold slope is less than 120 μV/dec. Based on the measured and simulated data obtained from single-gate device, breakdown of parasitic floating-base bipolar transistor and floating gate charged with holes are responsible to increase abruptly in drain current. In the dual-gate device, on-current degrades with high temperature but subthreshold slope is not changed. To observe the switching speed of dual-gate device and transient response of drain current are measured. According to the transient responses of drain current, switching speed of the dual-gate device is about 10(-5) sec.

High speed gated x-ray imagers

International Nuclear Information System (INIS)

Kilkenny, J.D.; Bell, P.; Hanks, R.; Power, G.; Turner, R.E.; Wiedwald, J.

1988-01-01

Single and multi-frame gated x-ray images with time-resolution as fast as 150 psec are described. These systems are based on the gating of microchannel plates in a stripline configuration. The gating voltage comes from the avalanche breakdown of reverse biased p-n junction producing high power voltage pulses as short as 70 psec. Results from single and four frame x-ray cameras used on Nova are described. 8 refs., 9 figs

The desensitization gating of the MthK K+ channel is governed by its cytoplasmic amino terminus.

Directory of Open Access Journals (Sweden)

Mario Meng-Chiang Kuo

2008-10-01

Full Text Available The RCK-containing MthK channel undergoes two inactivation processes: activation-coupled desensitization and acid-induced inactivation. The acid inactivation is mediated by the C-terminal RCK domain assembly. Here, we report that the desensitization gating is governed by a desensitization domain (DD of the cytoplasmic N-terminal 17 residues. Deletion of DD completely removes the desensitization, and the process can be fully restored by a synthetic DD peptide added in trans. Mutagenesis analyses reveal a sequence-specific determinant for desensitization within the initial hydrophobic segment of DD. Proton nuclear magnetic resonance ((1H NMR spectroscopy analyses with synthetic peptides and isolated RCK show interactions between the two terminal domains. Additionally, we show that deletion of DD does not affect the acid-induced inactivation, indicating that the two inactivation processes are mutually independent. Our results demonstrate that the short N-terminal DD of MthK functions as a complete moveable module responsible for the desensitization. Its interaction with the C-terminal RCK domain may play a role in the gating process.

Low-voltage organic field-effect transistors based on novel high-κ organometallic lanthanide complex for gate insulating materials

Energy Technology Data Exchange (ETDEWEB)

Liu, Qi; Li, Yi; Zhang, Yang; Song, You, E-mail: wangxzh@nju.edu.cn, E-mail: yli@nju.edu.cn, E-mail: yousong@nju.edu.cn; Wang, Xizhang, E-mail: wangxzh@nju.edu.cn, E-mail: yli@nju.edu.cn, E-mail: yousong@nju.edu.cn; Hu, Zheng [Key Laboratory of Mesoscopic Chemistry of MOE, Jiangsu Provincial Lab for Nanotechnology, School of Chemistry and Chemical Engineering, Nanjing University, Nanjing 210093, China. High-Tech Research Institute of Nanjing University (Suzhou), Suzhou 215123 (China); Sun, Huabin; Li, Yun, E-mail: wangxzh@nju.edu.cn, E-mail: yli@nju.edu.cn, E-mail: yousong@nju.edu.cn; Shi, Yi [School of Electronic Science and Engineering and Jiangsu Provincial Key Laboratory of Photonic and Electronic Materials, Nanjing University, Nanjing 210093 (China)

2014-08-15

A novel high-κ organometallic lanthanide complex, Eu(tta){sub 3}L (tta=2-thenoyltrifluoroacetonate, L = 4,5-pinene bipyridine), is used as gate insulating material to fabricate low-voltage pentacene field-effect transistors (FETs). The optimized gate insulator exhibits the excellent properties such as low leakage current density, low surface roughness, and high dielectric constant. When operated under a low voltage of −5 V, the pentacene FET devices show the attractive electrical performance, e.g. carrier mobility (μ{sub FET}) of 0.17 cm{sup 2} V{sup −1} s{sup −1}, threshold voltage (V{sub th}) of −0.9 V, on/off current ratio of 5 × 10{sup 3}, and subthreshold slope (SS) of 1.0 V dec{sup −1}, which is much better than that of devices obtained on conventional 300 nm SiO{sub 2} substrate (0.13 cm{sup 2} V{sup −1} s{sup −1}, −7.3 V and 3.1 V dec{sup −1} for μ{sub FET}, V{sub th} and SS value when operated at −30 V). These results indicate that this kind of high-κ organometallic lanthanide complex becomes a promising candidate as gate insulator for low-voltage organic FETs.

Porogen residues detection in optical properties of low-k dielectrics cured by ultraviolet radiation

Energy Technology Data Exchange (ETDEWEB)

Marsik, Premysl, E-mail: marsik@physics.muni.c [UFKL, Masaryk University, Kotlarska 2, 61137 Brno (Czech Republic); IMEC, Kapeldreef 75, 3001 Leuven (Belgium); Verdonck, Patrick [IMEC, Kapeldreef 75, 3001 Leuven (Belgium); De Roest, David [ASM Belgium, Kapeldreef 75, 3001 Leuven (Belgium); Baklanov, Mikhail R. [IMEC, Kapeldreef 75, 3001 Leuven (Belgium)

2010-05-31

The optical properties of low dielectric constant (low-k) films have been determined by variable angle spectroscopic ellipsometry in the range from 2 eV to 9 eV to characterize the process of porogen removal during the UV-cure. The studied carbon doped oxide (SiCOH) porous dielectric films have been prepared by plasma enhanced chemical vapor deposition. The films have been deposited as a composition of a matrix precursor and an organic porogen. After deposition, the films have been cured by thermal annealing and UV irradiation ({lambda} = 172 nm) to remove the porogen and create a porosity of 33%, reaching a dielectric constant of 2.3. The process of porogen decomposition and removal has been studied on series of low-k samples, UV-cured for various times. Additional samples have been prepared by the deposition and curing of the porogen film, without SiCOH matrix, and the matrix material itself, without porogen. The analysis of the optical response of the porous dielectric as a mixture of matrix material, porogen and voids, together with Fourier transform infrared analysis, allows the sensitive detection of the volume of the porogen and indicates the existence of decomposed porogen residues inside the pores, even for long curing time. The variation of the deposition and curing conditions can control the amount of the porogen residues and the final porosity.

C-V analysis at variable frequency of MOS structures with different gates, containing Hf-Doped Ta2O5

International Nuclear Information System (INIS)

Stojanovska-Georgievska, L.; Novkovski, N.; Atanassova, E.

2012-01-01

The quality of the interface between the insulating layer and the Si substrate in contemporary submicron MOS technology is a critical issue for device functioning. It is characterized through the electrically active defect centers, known as interface states. Their response to the frequency is discussed here, by analyzing capacitance-voltage and conductance-voltage curves. The C-V method is preferred in many cases, since it offers easy measurement, and it is applied to extract information about interface traps and fixed oxide charge, at different frequencies. This technique, related with frequency dependent G-V measurements, can be very useful in characterizing charge trapped in the dielectric and at the interface with Si. By extracting the value of frequency dependent flat band voltage, we have obtained the fixed oxide charges at flat band condition. A comparison between the results obtained by two different methods is made. The samples that are studied are metal-insulator-semiconductor (MIS) structures that include high-k dielectric as insulating layer (Hf doped Ta 2 O 5 ), with thickness of 8 nm, with different metal used as gate electrode. Here the influence of the top electrode on the generation and behavior of the traps in the oxide layer is discussed. The results show that the value of metal work function of the gate material is an issue that should be considered very carefully, especially in the case of high work function metal gates, when generation of extra positive charge than in the case of other metals is observed. (Author)

Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

KAUST Repository

Rojas, Jhonathan Prieto

2013-02-12

In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry\\'s most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

KAUST Repository

Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa; Sevilla, Galo T.

2013-01-01

In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry's most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

Threshold-Voltage Shifts in Organic Transistors Due to Self-Assembled Monolayers at the Dielectric: Evidence for Electronic Coupling and Dipolar Effects.

Science.gov (United States)

Aghamohammadi, Mahdieh; Rödel, Reinhold; Zschieschang, Ute; Ocal, Carmen; Boschker, Hans; Weitz, R Thomas; Barrena, Esther; Klauk, Hagen

2015-10-21

The mechanisms behind the threshold-voltage shift in organic transistors due to functionalizing of the gate dielectric with self-assembled monolayers (SAMs) are still under debate. We address the mechanisms by which SAMs determine the threshold voltage, by analyzing whether the threshold voltage depends on the gate-dielectric capacitance. We have investigated transistors based on five oxide thicknesses and two SAMs with rather diverse chemical properties, using the benchmark organic semiconductor dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene. Unlike several previous studies, we have found that the dependence of the threshold voltage on the gate-dielectric capacitance is completely different for the two SAMs. In transistors with an alkyl SAM, the threshold voltage does not depend on the gate-dielectric capacitance and is determined mainly by the dipolar character of the SAM, whereas in transistors with a fluoroalkyl SAM the threshold voltages exhibit a linear dependence on the inverse of the gate-dielectric capacitance. Kelvin probe force microscopy measurements indicate this behavior is attributed to an electronic coupling between the fluoroalkyl SAM and the organic semiconductor.

Low pull-in voltage electrostatic MEMS switch using liquid dielectric

KAUST Repository

Zidan, Mohammed A.

2014-08-01

In this paper, we present an electrostatic MEMS switch with liquids as dielectric to reduce the actuation voltage. The concept is verified by simulating a lateral dual gate switch, where the required pull-in voltage is reduced by more than 8 times after using water as a dielectric, to become as low as 5.36V. The proposed switch is simulated using COMSOL multiphysics using various liquid volumes to study their effect on the switching performance. Finally, we propose the usage of the lateral switch as a single switch XOR logic gate.

Crystal Structure of the Mammalian GIRK2 K+ Channel and Gating Regulation by G-Proteins, PIP2 and Sodium

Science.gov (United States)

Whorton, Matthew R.; MacKinnon, Roderick

2011-01-01

Summary G-protein-gated K+ channels (Kir3.1–Kir3.4) control electrical excitability in many different cells. Among their functions relevant to human physiology and disease, they regulate the heart rate and govern a wide range of neuronal activities. Here we present the first crystal structures of a G-protein-gated K+ channel. By comparing the wild-type structure to that of a constitutively active mutant, we identify a global conformational change through which G-proteins could open a G-loop gate in the cytoplasmic domain. The structures of both channels in the absence and presence of PIP2 show that G-proteins open only the G-loop gate in the absence of PIP2, but in the presence of PIP2 the G-loop gate and a second inner helix gate become coupled, so that both gates open. We also identify a strategically located Na+ ion-binding site, which would allow intracellular Na+ to modulate GIRK channel activity. These data provide a mechanistic description of multi-ligand regulation of GIRK channel gating. PMID:21962516

Investigation of plasma etch damage to porous oxycarbosilane ultra low-k dielectric

International Nuclear Information System (INIS)

Bruce, R L; Engelmann, S; Purushothaman, S; Volksen, W; Frot, T J; Magbitang, T; Dubois, G; Darnon, M

2013-01-01

There has been much interest recently in porous oxycarbosilane (POCS)-based materials as the ultra-low k dielectric (ULK) in back-end-of-line (BEOL) applications due to their superior mechanical properties compared to traditional organosilicate-based ULK materials at equivalent porosity and dielectric constant. While it is well known that plasma etching and strip processes can cause significant damage to ULK materials in general, little has been reported about the effect of plasma damage to POCS as the ULK material. We investigated the effect of changing the gas discharge chemistry and substrate bias in the dielectric trench etch and also the subsequent effect of the cap-open etch on plasma damage to POCS during BEOL integration. Large differences in surface roughness and damage behaviour were observed by changing the fluorocarbon depositing conditions. These damage behaviour trends will be discussed and potential rationalizations offered based on the formation of pits and craters at the etch front that lead to surface roughness and microtrenching. (paper)

Processing and performance of organic insulators as a gate layer in ...

Indian Academy of Sciences (India)

Fabrication of organic thin film transistor (OTFT) on flexible substrates is a challenge, because of its low softening temperature, high roughness and flexible nature. Although several organic dielectrics have been used as gate insulator, it is difficult to choose one in absence of a comparative study covering processing of ...

Super soft silicone elastomers with high dielectric permittivity

DEFF Research Database (Denmark)

Madsen, Frederikke Bahrt; Yu, Liyun; Hvilsted, Søren

2015-01-01

Dielectric elastomers (DEs) have many favourable properties. The obstacle of high driving voltages, however, limits the commercial viability of the technology at present. Driving voltage can be lowered by decreasing the Young’s modulus and increasing the dielectric permittivity of silicone...... elastomers. A decrease in Young’s modulus, however, is often accompanied by the loss of mechanical stability and thereby the lifetime of the DE. New soft elastomer matrices with high dielectric permittivity and low Young’s modulus, with no loss of mechanical stability, were prepared by two different...... approaches using chloropropyl-functional silicone polymers. The first approach was based on synthesised chloropropyl-functional copolymers that were cross-linkable and thereby formed the basis of new silicone networks with high dielectric permittivity (e.g. a 43% increase). These networks were soft without...

Synthetic Strategies for High Dielectric Constant Silicone Elastomers

DEFF Research Database (Denmark)

Madsen, Frederikke Bahrt

synthetic strategies were developed in this Ph.D. thesis, in order to create silicone elastomers with high dielectric constants and thereby higher energy densities. The work focused on maintaining important properties such as dielectric loss, electrical breakdown strength and elastic modulus....... The methodology therefore involved chemically grafting high dielectric constant chemical groups onto the elastomer network, as this would potentially provide a stable elastomer system upon continued activation of the material. The first synthetic strategy involved the synthesis of a new type of cross...... extender’ that allowed for chemical modifications such as Cu- AAC. This route was promising for one-pot elastomer preparation and as a high dielectric constant additive to commercial silicone systems. The second approach used the borane-catalysed Piers-Rubinsztajn reaction to form spatially well...

Reduction of ambipolar characteristics of vertical channel tunneling field-effect transistor by using dielectric sidewall

International Nuclear Information System (INIS)

Park, Chun Woong; Cho, Il Hwan; Choi, Woo Young; Lee, Jong-Ho

2013-01-01

Ambipolar characteristics of tunneling FETs have been improved by introducing a novel structure which contains dielectric sidewall in the gate region. In the ambipolar operation mode, gate field effect on intrinsic-drain junction region can be reduced with dielectric sidewall. As a result, ambipolar state tunneling probability is decreased at the intrinsic-drain junction. Since the sidewall region is located near the drain region, tunneling probability of source-intrinsic region is not affected by dielectric sidewall. This asymmetric characteristics means only ambipolar current of tunneling FETs can be prohibited by dielectric sidewall. Reduction of ambipolar characteristic of proposed structure has been evaluated with dimension and location of dielectric sidewall. Quantitative analysis of ambipolar characteristics is also investigated with tunneling. (paper)

Physical mechanism for gating and mechanosensitivity of the human TRAAK K+ channel

Science.gov (United States)

Brohawn, Stephen G.; Campbell, Ernest B.; MacKinnon, Roderick

2015-01-01

Summary Activation of mechanosensitive ion channels by physical force underlies many physiological processes including the sensation of touch, hearing and pain1–5. TRAAK ion channels are neuronally expressed members of the two-pore domain K+ (K2P) channel family and are mechanosensitive6. They are involved in controlling mechanical and temperature nociception in mice7. Mechanosensitivity of TRAAK is mediated directly through the lipid bilayer: it is a membrane tension gated channel8. However, the molecular mechanism of TRAAK channel gating and mechanosensitivity is unknown. Here we present crystal structures of TRAAK in conductive and nonconductive conformations defined by the presence of permeant ions along the conduction pathway. In the nonconductive state, a lipid acyl chain accesses the channel cavity through a 5 Å-wide lateral opening in the membrane inner leaflet and physically blocks ion passage. In the conductive state, rotation of a transmembrane helix (TM4) about a central hinge seals the intramembrane opening, preventing lipid block of the cavity and permitting ion entry. Additional rotation of a membrane interacting TM2-TM3 segment, unique to mechanosensitive K2Ps, against TM4 may further stabilize the conductive conformation. Comparison of the structures reveals a biophysical explanation for TRAAK mechanosensitivity: an expansion in cross sectional area up to 2.7 nm2 in the conductive state is expected to create a membrane tension-dependent energy difference between conformations that promotes force activation. Our results show how tension of the lipid bilayer can be harnessed to control gating and mechanosensitivity of a eukaryotic ion channel. PMID:25471887

C-V characterization of Schottky- and MIS-gate SiGe/Si HEMT structures

International Nuclear Information System (INIS)

Onojima, Norio; Kasamatsu, Akihumi; Hirose, Nobumitsu; Mimura, Takashi; Matsui, Toshiaki

2008-01-01

Electrical properties of Schottky- and metal-insulator-semiconductor (MIS)-gate SiGe/Si high electron mobility transistors (HEMTs) were investigated with capacitance-voltage (C-V) measurements. The MIS-gate HEMT structure was fabricated using a SiN gate insulator formed by catalytic chemical vapor deposition (Cat-CVD). The Cat-CVD SiN thin film (5 nm) was found to be an effective gate insulator with good gate controllability and dielectric properties. We previously investigated device characteristics of sub-100-nm-gate-length Schottky- and MIS-gate HEMTs, and reported that the MIS-gate device had larger maximum drain current density and transconductance (g m ) than the Schottky-gate device. The radio frequency (RF) measurement of the MIS-gate device, however, showed a relatively lower current gain cutoff frequency f T compared with that of the Schottky-gate device. In this study, C-V characterization of the MIS-gate HEMT structure demonstrated that two electron transport channels existed, one at the SiGe/Si buried channel and the other at the SiN/Si surface channel

C-V characterization of Schottky- and MIS-gate SiGe/Si HEMT structures

Energy Technology Data Exchange (ETDEWEB)

Onojima, Norio [National Institute of Information and Communications Technology (NICT), Koganei, Tokyo 184-8795 (Japan)], E-mail: nonojima@nict.go.jp; Kasamatsu, Akihumi; Hirose, Nobumitsu [National Institute of Information and Communications Technology (NICT), Koganei, Tokyo 184-8795 (Japan); Mimura, Takashi [National Institute of Information and Communications Technology (NICT), Koganei, Tokyo 184-8795 (Japan); Fujitsu Laboratories Ltd., Atsugi, Kanagawa 243-0197 (Japan); Matsui, Toshiaki [National Institute of Information and Communications Technology (NICT), Koganei, Tokyo 184-8795 (Japan)

2008-07-30

Electrical properties of Schottky- and metal-insulator-semiconductor (MIS)-gate SiGe/Si high electron mobility transistors (HEMTs) were investigated with capacitance-voltage (C-V) measurements. The MIS-gate HEMT structure was fabricated using a SiN gate insulator formed by catalytic chemical vapor deposition (Cat-CVD). The Cat-CVD SiN thin film (5 nm) was found to be an effective gate insulator with good gate controllability and dielectric properties. We previously investigated device characteristics of sub-100-nm-gate-length Schottky- and MIS-gate HEMTs, and reported that the MIS-gate device had larger maximum drain current density and transconductance (g{sub m}) than the Schottky-gate device. The radio frequency (RF) measurement of the MIS-gate device, however, showed a relatively lower current gain cutoff frequency f{sub T} compared with that of the Schottky-gate device. In this study, C-V characterization of the MIS-gate HEMT structure demonstrated that two electron transport channels existed, one at the SiGe/Si buried channel and the other at the SiN/Si surface channel.

Nitride passivation of the interface between high-k dielectrics and SiGe

Energy Technology Data Exchange (ETDEWEB)

Sardashti, Kasra [Department of Chemistry and Biochemistry, University of California, San Diego, La Jolla, California 92093-0358 (United States); Materials Science and Engineering Program, University of California, San Diego, La Jolla, California 92093-0411 (United States); Hu, Kai-Ting [Department of Chemistry and Biochemistry, University of California, San Diego, La Jolla, California 92093-0358 (United States); Department of Mechanical and Aerospace Engineering, University of California, San Diego, La Jolla, California 92093-0411 (United States); Tang, Kechao; McIntyre, Paul [Department of Materials Science and Engineering, Stanford University, Stanford, California 94305 (United States); Madisetti, Shailesh; Oktyabrsky, Serge [Colleges of Nanoscale Science and Engineering, SUNY Polytechnic Institute, Albany, New York 12222 (United States); Siddiqui, Shariq; Sahu, Bhagawan [TD Research, GLOBALFOUNDRIES US, Inc., Albany, New York 12203 (United States); Yoshida, Naomi; Kachian, Jessica; Dong, Lin [Applied Materials, Inc., Santa Clara, California 95054 (United States); Fruhberger, Bernd [California Institute for Telecommunications and Information Technology, University of California San Diego, La Jolla, California 92093-0436 (United States); Kummel, Andrew C., E-mail: akummel@ucsd.edu [Department of Chemistry and Biochemistry, University of California, San Diego, La Jolla, California 92093-0358 (United States)

2016-01-04

In-situ direct ammonia (NH{sub 3}) plasma nitridation has been used to passivate the Al{sub 2}O{sub 3}/SiGe interfaces with Si nitride and oxynitride. X-ray photoelectron spectroscopy of the buried Al{sub 2}O{sub 3}/SiGe interface shows that NH{sub 3} plasma pre-treatment should be performed at high temperatures (300 °C) to fully prevent Ge nitride and oxynitride formation at the interface and Ge out-diffusion into the oxide. C-V and I-V spectroscopy results show a lower density of interface traps and smaller gate leakage for samples with plasma nitridation at 300 °C.

Effect of atomic-arrangement matching on La{sub 2}O{sub 3}/Ge heterostructures for epitaxial high-k-gate-stacks

Energy Technology Data Exchange (ETDEWEB)

Kanashima, T., E-mail: kanashima@ee.es.osaka-u.ac.jp; Zenitaka, M.; Kajihara, Y.; Yamada, S.; Hamaya, K. [Graduate School of Engineering Science, Osaka University, Machkaneyama 1-3, Toyonaka, Osaka 560-8531 (Japan); Nohira, H. [Tokyo City University, 1-28-1 Tamazutumi, Setagaya-ku, Tokyo 158-8557 (Japan)

2015-12-14

We demonstrate a high-quality La{sub 2}O{sub 3} layer on germanium (Ge) as an epitaxial high-k-gate-insulator, where there is an atomic-arrangement matching condition between La{sub 2}O{sub 3}(001) and Ge(111). Structural analyses reveal that (001)-oriented La{sub 2}O{sub 3} layers were grown epitaxially only when we used Ge(111) despite low growth temperatures less than 300 °C. The permittivity (k) of the La{sub 2}O{sub 3} layer is roughly estimated to be ∼19 from capacitance-voltage (C-V) analyses in Au/La{sub 2}O{sub 3}/Ge structures after post-metallization-annealing treatments, although the C-V curve indicates the presence of carrier traps near the interface. By using X-ray photoelectron spectroscopy analyses, we find that only Ge–O–La bonds are formed at the interface, and the thickness of the equivalent interfacial Ge oxide layer is much smaller than that of GeO{sub 2} monolayer. We discuss a model of the interfacial structure between La{sub 2}O{sub 3} and Ge(111) and comment on the C-V characteristics.

High frequency MOSFET gate drivers technologies and applications

CERN Document Server

Zhang, Zhiliang

2017-01-01

This book describes high frequency power MOSFET gate driver technologies, including gate drivers for GaN HEMTs, which have great potential in the next generation of switching power converters. Gate drivers serve as a critical role between control and power devices.

Comparison of precursors for pulsed metal-organic chemical vapor deposition of HfO2 high-K dielectric thin films

International Nuclear Information System (INIS)

Teren, Andrew R.; Thomas, Reji; He, Jiaqing; Ehrhart, Peter

2005-01-01

Hafnium oxide films were deposited on Si(100) substrates using pulsed metal-organic chemical vapor deposition (CVD) and evaluated for high-K dielectric applications. Three types of precursors were tested: two oxygenated ones, Hf butoxide-dmae and Hf butoxide-mmp, and an oxygen-free one, Hf diethyl-amide. Depositions were carried out in the temperature range of 350-650 deg. C, yielding different microstructures ranging from amorphous to crystalline, monoclinic, films. The films were compared on the basis of growth rate, phase development, density, interface characteristics, and electrical properties. Some specific features of the pulsed injection technique are considered. For low deposition temperatures the growth rate for the amide precursor was significantly higher than for the mixed butoxide precursors. A thickness-dependent amorphous to crystalline phase transition temperature was found for all precursors. There is an increase of the film density along with the deposition temperature from values as low as 5 g/cm 3 at 350 deg. C to values close to the bulk value of 9.7 g/cm 3 at 550 deg. C. Crystallization is observed in the same temperature range for films of typically 10-20 nm thickness. However, annealing studies show that this density increase is not simply related to the crystallization of the films. Similar electrical properties could be observed for all precursors and the dielectric constant of the films reaches values similar to the best values reported for bulk crystalline HfO 2

Thermosetting resins with high fractions of free volume and inherently low dielectric constants.

Science.gov (United States)

Lin, Liang-Kai; Hu, Chien-Chieh; Su, Wen-Chiung; Liu, Ying-Ling

2015-08-18

This work demonstrates a new class of thermosetting resins, based on Meldrum's acid (MA) derivatives, which have high fractions of free volume and inherently low k values of about 2.0 at 1 MHz. Thermal decomposition of the MA groups evolves CO2 and acetone to create air-trapped cavities so as to reduce the dielectric constants.

Evolution of interfacial Fermi level in In{sub 0.53}Ga{sub 0.47}As/high-κ/TiN gate stacks

Energy Technology Data Exchange (ETDEWEB)

Carr, Adra; Rozen, John; Frank, Martin M.; Ando, Takashi; Cartier, Eduard A.; Kerber, Pranita; Narayanan, Vijay; Haight, Richard [IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (United States)

2015-07-06

The net charge state was probed of metal-oxide-semiconductor gate stacks consisting of In{sub 0.53}Ga{sub 0.47}As /high-κ dielectric/5 nm TiN, for both Al{sub 2}O{sub 3} and HfO{sub 2} dielectrics, via investigation of band bending at the InGaAs/high-κ interface. Using pump-probe photoelectron spectroscopy, changes to band bending were studied for each sequential layer deposited onto the InGaAs substrate and subsequent annealing up to 600 °C. Two behavioral regions were observed in annealing studies: (1) a lower temperature (<350 °C) region, attributed to changes at the high-κ/TiN interface, and (2) a higher temperature region (> 350 °C), associated with a net positive charge increase within the oxide. These band bending measurements delineate the impact of processing steps inherently inaccessible via capacitance-voltage electrical characterization.

Dielectric-Lined High-Gradient Accelerator Structure

Energy Technology Data Exchange (ETDEWEB)

Jay L. Hirshfield

2012-04-24

Rectangular particle accelerator structures with internal planar dielectric elements have been studied, with a view towards devising structures with lower surface fields for a given accelerating field, as compared with structures without dielectrics. Success with this concept is expected to allow operation at higher accelerating gradients than otherwise on account of reduced breakdown probabilities. The project involves studies of RF breakdown on amorphous dielectrics in test cavities that could enable high-gradient structures to be built for a future multi-TeV collider. The aim is to determine what the limits are for RF fields at the surfaces of selected dielectrics, and the resulting acceleration gradient that could be achieved in a working structure. The dielectric of principal interest in this study is artificial CVD diamond, on account of its advertised high breakdown field ({approx}2 GV/m for dc), low loss tangent, and high thermal conductivity. Experimental studies at mm-wavelengths on materials and structures for achieving high acceleration gradient were based on the availability of the 34.3 GHz third-harmonic magnicon amplifier developed by Omega-P, and installed at the Yale University Beam Physics Laboratory. Peak power from the magnicon was measured to be about 20 MW in 0.5 {micro}s pulses, with a gain of 54 dB. Experiments for studying RF high-field effects on CVD diamond samples failed to show any evidence after more than 10{sup 5} RF pulses of RF breakdown up to a tangential surface field strength of 153 MV/m; studies at higher fields were not possible due to a degradation in magnicon performance. A rebuild of the tube is underway at this writing. Computed performance for a dielectric-loaded rectangular accelerator structure (DLA) shows highly competitive properties, as compared with an existing all-metal structure. For example, comparisons were made of a DLA structure having two planar CVD diamond elements with a all-metal CERN structure HDS

Dielectric-Lined High-Gradient Accelerator Structure

International Nuclear Information System (INIS)

Hirshfield, Jay L.

2012-01-01

Rectangular particle accelerator structures with internal planar dielectric elements have been studied, with a view towards devising structures with lower surface fields for a given accelerating field, as compared with structures without dielectrics. Success with this concept is expected to allow operation at higher accelerating gradients than otherwise on account of reduced breakdown probabilities. The project involves studies of RF breakdown on amorphous dielectrics in test cavities that could enable high-gradient structures to be built for a future multi-TeV collider. The aim is to determine what the limits are for RF fields at the surfaces of selected dielectrics, and the resulting acceleration gradient that could be achieved in a working structure. The dielectric of principal interest in this study is artificial CVD diamond, on account of its advertised high breakdown field (∼2 GV/m for dc), low loss tangent, and high thermal conductivity. Experimental studies at mm-wavelengths on materials and structures for achieving high acceleration gradient were based on the availability of the 34.3 GHz third-harmonic magnicon amplifier developed by Omega-P, and installed at the Yale University Beam Physics Laboratory. Peak power from the magnicon was measured to be about 20 MW in 0.5 (micro)s pulses, with a gain of 54 dB. Experiments for studying RF high-field effects on CVD diamond samples failed to show any evidence after more than 10 5 RF pulses of RF breakdown up to a tangential surface field strength of 153 MV/m; studies at higher fields were not possible due to a degradation in magnicon performance. A rebuild of the tube is underway at this writing. Computed performance for a dielectric-loaded rectangular accelerator structure (DLA) shows highly competitive properties, as compared with an existing all-metal structure. For example, comparisons were made of a DLA structure having two planar CVD diamond elements with a all-metal CERN structure HDS operating at 30

Layered Cu-based electrode for high-dielectric constant oxide thin film-based devices

International Nuclear Information System (INIS)

Fan, W.; Saha, S.; Carlisle, J.A.; Auciello, O.; Chang, R.P.H.; Ramesh, R.

2003-01-01

Ti-Al/Cu/Ta multilayered electrodes were fabricated on SiO 2 /Si substrates by ion beam sputtering deposition, to overcome the problems of Cu diffusion and oxidation encountered during the high dielectric constant (κ) materials integration. The Cu and Ta layers remained intact through the annealing in oxygen environment up to 600 deg. C. The thin oxide layer, formed on the Ti-Al surface, effectively prevented the oxygen penetration toward underneath layers. Complex oxide (Ba x Sr 1-x )TiO 3 (BST) thin films were grown on the layered Ti-Al/Cu/Ta electrodes using rf magnetron sputtering. The deposited BST films exhibited relatively high permittivity (150), low dielectric loss (0.007) at zero bias, and low leakage current -8 A/cm 2 at 100 kV/cm

Volatile and Nonvolatile Characteristics of Asymmetric Dual-Gate Thyristor RAM with Vertical Structure.

Science.gov (United States)

Kim, Hyun-Min; Kwon, Dae Woong; Kim, Sihyun; Lee, Kitae; Lee, Junil; Park, Euyhwan; Lee, Ryoongbin; Kim, Hyungjin; Kim, Sangwan; Park, Byung-Gook

2018-09-01

In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (107) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.

Experimental Study on High Electrical Breakdown of Water Dielectric

International Nuclear Information System (INIS)

Zhang Zicheng; Zhang Jiande; Yang Jianhua

2005-01-01

By means of a coaxial apparatus, pressurized water breakdown experiments with microsecond charging have been carried out with different surface roughness of electrodes and different ethylene glycol concentrations of ethylene glycol/water mixture. The experimental results about the breakdown stress and the effective time are presented. The breakdown stress is normalized to the situation that the effective time is transformed to 1 μs and analyzed. The conclusions are as follows: (1) the breakdown stress formula is modified to E = 0.561M A -1/10 t eff -1/N P 1/8 ; (2) the coefficient M is significantly increased by surface polishing and ethylene glycol additive; (3) it is accumulative for the capacity of improving electrical breakdown strength for surface polishing, ethylene glycol additive, and pressurization, of which pressurization is the most effective method; (4) the highest stress of 235.5 kV/cm is observed in ethylene glycol/water mixture with an ethylene glycol concentration of 80% at a hydrostatic pressure of 1215.9 kPa and is about one time greater than that in pure water at constant pressure; (5) for pressurization and surface polishing, the primary mechanism to improve the breakdown strength of water dielectric is the increase in the breakdown time delay. Research results indicate great potential in the application of the high power pulse conditioning system of water dielectric

Effect of dual-dielectric hydrogen-diffusion barrier layers on the performance of low-temperature processed transparent InGaZnO thin-film transistors

Science.gov (United States)

Tari, Alireza; Wong, William S.

2018-02-01

Dual-dielectric SiOx/SiNx thin-film layers were used as back-channel and gate-dielectric barrier layers for bottom-gate InGaZnO (IGZO) thin-film transistors (TFTs). The concentration profiles of hydrogen, indium, gallium, and zinc oxide were analyzed using secondary-ion mass spectroscopy characterization. By implementing an effective H-diffusion barrier, the hydrogen concentration and the creation of H-induced oxygen deficiency (H-Vo complex) defects during the processing of passivated flexible IGZO TFTs were minimized. A bilayer back-channel passivation layer, consisting of electron-beam deposited SiOx on plasma-enhanced chemical vapor-deposition (PECVD) SiNx films, effectively protected the TFT active region from plasma damage and minimized changes in the chemical composition of the semiconductor layer. A dual-dielectric PECVD SiOx/PECVD SiNx gate-dielectric, using SiOx as a barrier layer, also effectively prevented out-diffusion of hydrogen atoms from the PECVD SiNx-gate dielectric to the IGZO channel layer during the device fabrication.

Effects of vacuum ultraviolet irradiation on trapped charges and leakage currents of low-k organosilicate dielectrics

Energy Technology Data Exchange (ETDEWEB)

Zheng, H.; Guo, X.; Pei, D.; Shohet, J. L. [Plasma Processing and Technology Laboratory and Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States); Ryan, E. T. [GLOBALFOUNDRIES, Albany, New York 12203 (United States); Nishi, Y. [Stanford University, Stanford, California 94305 (United States)

2015-05-11

Vacuum ultraviolet (VUV) photoemission spectroscopy is utilized to investigate the distribution of trapped charges within the bandgap of low dielectric constant (low-k) organosilicate (SiCOH) materials. It was found that trapped charges are continuously distributed within the bandgap of porous SiCOH and the center of the trapped states is 1.3 eV above the valence band of the tested sample. By comparing photoemission spectroscopic results before and after VUV exposure, VUV irradiation with photon energies between 7.6 and 8.9 eV was found to deplete trapped charge while UV exposure with photon energies less than 6.0 eV induces more trapped charges in tested samples. Current-Voltage (IV) characteristics results show that the reliability of dielectrics is improved after VUV irradiation with photon energies between 7.6 and 8.9 eV, while UV exposure results in an increased level of leakage current and a decreased breakdown voltage, both of which are harmful to the reliability of the dielectric. This work shows that VUV irradiation holds the potential to substitute for UV curing in microelectronic processing to improve the reliability of low-k dielectrics by mitigating the leakage currents and trapped charges induced by UV irradiation.

Pulse Power Capability Of High Energy Density Capacitors Based on a New Dielectric Material

Science.gov (United States)

Winsor, Paul; Scholz, Tim; Hudis, Martin; Slenes, Kirk M.

1999-01-01

A new dielectric composite consisting of a polymer coated onto a high-density metallized Kraft has been developed for application in high energy density pulse power capacitors. The polymer coating is custom formulated for high dielectric constant and strength with minimum dielectric losses. The composite can be wound and processed using conventional wound film capacitor manufacturing equipment. This new system has the potential to achieve 2 to 3 J/cu cm whole capacitor energy density at voltage levels above 3.0 kV, and can maintain its mechanical properties to temperatures above 150 C. The technical and manufacturing development of the composite material and fabrication into capacitors are summarized in this paper. Energy discharge testing, including capacitance and charge-discharge efficiency at normal and elevated temperatures, as well as DC life testing were performed on capacitors manufactured using this material. TPL (Albuquerque, NM) has developed the material and Aerovox (New Bedford, MA) has used the material to build and test actual capacitors. The results of the testing will focus on pulse power applications specifically those found in electro-magnetic armor and guns, high power microwave sources and defibrillators.

Characterization, integration and reliability of HfO{sub 2} and LaLuO{sub 3} high-κ/metal gate stacks for CMOS applications

Energy Technology Data Exchange (ETDEWEB)

Nichau, Alexander

2013-07-15

gate electrode to decrease the EOT of HfO{sub 2} gate stacks. A lower limit found was EOT=5 Aa for Al doping inside TiN. The doping of TiN on LaLuO{sub 3} is proven by electron energy loss spectroscopy (EELS) studies to modify the interfacial silicate layer to La-rich silicates or even reduce the layer. The oxide quality in Si/HfO{sub 2}/TiN gate stacks is characterized by charge pumping and carrier mobility measurements on 3d MOSFETs a.k.a. FinFETs. The oxide quality in terms of the number of interface (and oxide) traps on top- and sidewall of FinFETs is compared for three different annealing processes. A high temperature anneal of HfO{sub 2} improves significantly the oxide quality and mobility. The gate oxide integrity (GOI) of gate stacks below 1 nm EOT is determined by time-dependent dielectric breakdown (TDDB) measurements on FinFETs with HfO{sub 2}/TiN gate stacks. A successful EOT scaling has always to consider the oxide quality and resulting reliability. Degraded oxide quality leads to mobility degradation and earlier soft-breakdown, i.e. leakage current increase.