High-Speed On-Board Data Processing for Science Instruments: HOPS

Science.gov (United States)

Beyon, Jeffrey

2015-01-01

The project called High-Speed On-Board Data Processing for Science Instruments (HOPS) has been funded by NASA Earth Science Technology Office (ESTO) Advanced Information Systems Technology (AIST) program during April, 2012 â€" April, 2015. HOPS is an enabler for science missions with extremely high data processing rates. In this three-year effort of HOPS, Active Sensing of CO2 Emissions over Nights, Days, and Seasons (ASCENDS) and 3-D Winds were of interest in particular. As for ASCENDS, HOPS replaces time domain data processing with frequency domain processing while making the real-time on-board data processing possible. As for 3-D Winds, HOPS offers real-time high-resolution wind profiling with 4,096-point fast Fourier transform (FFT). HOPS is adaptable with quick turn-around time. Since HOPS offers reusable user-friendly computational elements, its FPGA IP Core can be modified for a shorter development period if the algorithm changes. The FPGA and memory bandwidth of HOPS is 20 GB/sec while the typical maximum processor-to-SDRAM bandwidth of the commercial radiation tolerant high-end processors is about 130-150 MB/sec. The inter-board communication bandwidth of HOPS is 4 GB/sec while the effective processor-to-cPCI bandwidth of commercial radiation tolerant high-end boards is about 50-75 MB/sec. Also, HOPS offers VHDL cores for the easy and efficient implementation of ASCENDS and 3-D Winds, and other similar algorithms. A general overview of the 3-year development of HOPS is the goal of this presentation.

Study of cutting speed on surface roughness and chip formation when machining nickel-based alloy

International Nuclear Information System (INIS)

Khidhir, Basim A.; Mohamed, Bashir

2010-01-01

Nickel- based alloy is difficult-to-machine because of its low thermal diffusive property and high strength at higher temperature. The machinability of nickel- based Hastelloy C-276 in turning operations has been carried out using different types of inserts under dry conditions on a computer numerical control (CNC) turning machine at different stages of cutting speed. The effects of cutting speed on surface roughness have been investigated. This study explores the types of wear caused by the effect of cutting speed on coated and uncoated carbide inserts. In addition, the effect of burr formation is investigated. The chip burr is found to have different shapes at lower speeds. Triangles and squares have been noticed for both coated and uncoated tips as well. The conclusion from this study is that the transition from thick continuous chip to wider discontinuous chip is caused by different types of inserts. The chip burr has a significant effect on tool damage starting in the line of depth-of-cut. For the coated insert tips, the burr disappears when the speed increases to above 150 m/min with the improvement of surface roughness; increasing the speed above the same limit for uncoated insert tips increases the chip burr size. The results of this study showed that the surface finish of nickel-based alloy is highly affected by the insert type with respect to cutting speed changes and its effect on chip burr formation and tool failure

Chip formation and surface integrity in high-speed machining of hardened steel

Science.gov (United States)

Kishawy, Hossam Eldeen A.

Increasing demands for high production rates as well as cost reduction have emphasized the potential for the industrial application of hard turning technology during the past few years. Machining instead of grinding hardened steel components reduces the machining sequence, the machining time, and the specific cutting energy. Hard turning Is characterized by the generation of high temperatures, the formation of saw toothed chips, and the high ratio of thrust to tangential cutting force components. Although a large volume of literature exists on hard turning, the change in machined surface physical properties represents a major challenge. Thus, a better understanding of the cutting mechanism in hard turning is still required. In particular, the chip formation process and the surface integrity of the machined surface are important issues which require further research. In this thesis, a mechanistic model for saw toothed chip formation is presented. This model is based on the concept of crack initiation on the free surface of the workpiece. The model presented explains the mechanism of chip formation. In addition, experimental investigation is conducted in order to study the chip morphology. The effect of process parameters, including edge preparation and tool wear on the chip morphology, is studied using Scanning Electron Microscopy (SEM). The dynamics of chip formation are also investigated. The surface integrity of the machined parts is also investigated. This investigation focusses on residual stresses as well as surface and sub-surface deformation. A three dimensional thermo-elasto-plastic finite element model is developed to predict the machining residual stresses. The effect of flank wear is introduced during the analysis. Although residual stresses have complicated origins and are introduced by many factors, in this model only the thermal and mechanical factors are considered. The finite element analysis demonstrates the significant effect of the heat generated

Network on chip master control board for neutron acquisition

International Nuclear Information System (INIS)

Ruiz-Martinez, E.; Mary, T.; Mutti, P.; Ratel, J.; Rey, F.

2012-01-01

The acquisition master control board is designed to assemble the various acquisition modes in use at the Institut Laue-Langevin (ILL). The main goal is to make the card common for all the ILL's instruments in a simple, modular and open way, giving the possibility to add new functionalities in order to follow the evolving demand. It has been necessary to define a central element to provide synchronization to the rest of the units. The backbone of the proposed acquisition control system is the denominated master acquisition board. The master board consists on a VME64X configurable high density I/O connection carrier board based on the latest Xilinx Virtex-6T FPGA. The internal architecture of the FPGA is designed as a Network on Chip (NoC) approach. The complete system also includes a display board and n histogram modules for live display of the data from the detectors. (authors)

High speed bending of 2nd level interconnects on printed circuit boards for automotive electronics

NARCIS (Netherlands)

Kouters, M.H.M.; Ubachs, R.; Wiel, H.J. van de; Waal, A. van der; Veer, J. van der

2011-01-01

Standard drop tests for portable electronics are not representative for the qualification of automotive electronics. High-frequency vibrations are more dominant than abrupt shocks during normal operation. In this work a high speed board bending (HSB) method is developed to mimic the constant cyclic

A mixed signal multi-chip module with high speed serial output links for the ATLAS Level-1 trigger

CERN Document Server

Pfeiffer, U

2000-01-01

We have built and tested a mixed signal multi-chip module (MCM) to be used in the Level-1 Pre-Processor system for the Calorimeter Trigger of the ATLAS experiment at CERN. The MCM performs high speed digital signal processing on four analogue input signals. Results are transmitted serially at a serial data rate of 800 MBd. Nine chips of different technologies are mounted on a four layer Cu substrate. ADC converters and serialiser chips are the major consumers of electrical power on the MCM, which amounts to 9 W for all dies. Special cut-out areas are used to dissipate heat directly to the copper substrate. In this paper we report on design criteria, chosen MCM technology for substrate and die mounting, experiences with the MCM operation and measurement results. (4 refs).

Medipix3 array high performance read-out board for synchrotron research

International Nuclear Information System (INIS)

Tartoni, N.; Horswell, I. C.; Marchal, J.; Gimenez, E. N.; Fearn, R. D.; Silfhout, R. G. van

2010-01-01

The Medipix3 ASIC is one of the most advanced chip that is presently available to build photon counting area detectors. The capabilities of the chip include adjacent pixels charge summing circuitry to sort out the distortion due to charge sharing, simultaneous counting and read-out that enables frames to be acquired without dead time, the colour mode of operation that enables up to eight energy bands to be acquired. In order to fully exploit the capabilities of the Medipix3 chip in synchrotron research, a high performance electronic board capable of driving large arrays of chips is necessary. We propose a parallel read-out board of Medipix3 chip arrays with a scalable architecture that allows driving the Medipix3 chip in all of its modes of operation. The board functions include the control of the chip arrays, data formatting and data compression, the management of the communications with the data storage devices, and operation in various trigger modes. In addition to this the board will have some 'intelligence' embedded. This will add some very important features to the final detector such as pattern recognition, capability of variable frame duration as a function of the photon flux, feedback to other equipment and real time calculations of data relevant to experiments such as the autocorrelation function.

High-speed autoverifying technology for printed wiring boards

Science.gov (United States)

Ando, Moritoshi; Oka, Hiroshi; Okada, Hideo; Sakashita, Yorihiro; Shibutani, Nobumi

1996-10-01

We have developed an automated pattern verification technique. The output of an automated optical inspection system contains many false alarms. Verification is needed to distinguish between minor irregularities and serious defects. In the past, this verification was usually done manually, which led to unsatisfactory product quality. The goal of our new automated verification system is to detect pattern features on surface mount technology boards. In our system, we employ a new illumination method, which uses multiple colors and multiple direction illumination. Images are captured with a CCD camera. We have developed a new algorithm that uses CAD data for both pattern matching and pattern structure determination. This helps to search for patterns around a defect and to examine defect definition rules. These are processed with a high speed workstation and a hard-wired circuits. The system can verify a defect within 1.5 seconds. The verification system was tested in a factory. It verified 1,500 defective samples and detected all significant defects with only a 0.1 percent of error rate (false alarm).

Single-board 32-bit computer for the FASTBUS

International Nuclear Information System (INIS)

Kellner, R.; Blossom, J.M.; Hong, J.P.

1985-01-01

The Los Alamos National Laboratory is building a 32bit computer on a FASTBUS board. It will use the National Semiconductor 32032 chip set, including the demand-paged memory management, floating point slave processor and interrupt control chips. The board will support 4 megabytes of memory which can be accessed by the processor over an on-board execution bus at processor speeds and which can be accessed by the FASTBUS at 80 megabytes per second. A windowed, direct memory access mechanism allows transfers of up to all of the memory

Residential High-Speed Internet Among Those Likely to Benefit From an Online Health Insurance Marketplace

Directory of Open Access Journals (Sweden)

Michel H. Boudreaux PhD

2016-01-01

Full Text Available Using data from the 2013 American Community Survey, we found that 24.3 million people (about 1 in 4 who were either eligible for Medicaid/Children’s Health Inusrance Program (CHIP or appeared likely to shop for Qualified Health Plan (QHP lacked residential high-speed Internet. Specifically, 28.6% or 18.9 million people eligible for Medicaid/CHIP and 17.1% or 5.5 million people who appeared likely to shop for a QHP did not have high-speed Internet in the home. For both the Medicaid/CHIP eligible and those likely to shop for a QHP, the proportion of people living in households without Internet varied substantially by race, geography, and other socio-demographic characteristics.

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

Science.gov (United States)

Bartelink, Dirk J.

1998-11-01

The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must

Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

Science.gov (United States)

Pin, Francois G.; Watanabe, Yutaka

1993-01-01

Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

Residential High-Speed Internet Among Those Likely to Benefit From an Online Health Insurance Marketplace.

Science.gov (United States)

Boudreaux, Michel H; Gonzales, Gilbert; Blewett, Lynn; Fried, Brett; Karaca-Mandic, Pinar

2016-01-01

Using data from the 2013 American Community Survey, we found that 24.3 million people (about 1 in 4) who were either eligible for Medicaid/Children's Health Insurance Program (CHIP) or appeared likely to shop for Qualified Health Plan (QHP) lacked residential high-speed Internet. Specifically, 28.6% or 18.9 million people eligible for Medicaid/CHIP and 17.1% or 5.5 million people who appeared likely to shop for a QHP did not have high-speed Internet in the home. For both the Medicaid/CHIP eligible and those likely to shop for a QHP, the proportion of people living in households without Internet varied substantially by race, geography, and other socio-demographic characteristics. © The Author(s) 2016.

Low-power grating detection system chip for high-speed low-cost length and angle precision measurement

Science.gov (United States)

Hou, Ligang; Luo, Rengui; Wu, Wuchen

2006-11-01

This paper forwards a low power grating detection chip (EYAS) on length and angle precision measurement. Traditional grating detection method, such as resister chain divide or phase locked divide circuit are difficult to design and tune. The need of an additional CPU for control and display makes these methods' implementation more complex and costly. Traditional methods also suffer low sampling speed for the complex divide circuit scheme and CPU software compensation. EYAS is an application specific integrated circuit (ASIC). It integrates micro controller unit (MCU), power management unit (PMU), LCD controller, Keyboard interface, grating detection unit and other peripherals. Working at 10MHz, EYAS can afford 5MHz internal sampling rate and can handle 1.25MHz orthogonal signal from grating sensor. With a simple control interface by keyboard, sensor parameter, data processing and system working mode can be configured. Two LCD controllers can adapt to dot array LCD or segment bit LCD, which comprised output interface. PMU alters system between working and standby mode by clock gating technique to save power. EYAS in test mode (system action are more frequently than real world use) consumes 0.9mw, while 0.2mw in real world use. EYAS achieved the whole grating detection system function, high-speed orthogonal signal handling in a single chip with very low power consumption.

A new high speed, Ultrascale+ based board for the ATLAS jet calorimeter trigger system

CERN Document Server

Rocco, Elena; The ATLAS collaboration

2018-01-01

A new high speed Ultrascale+ based board for the ATLAS jet calorimeter trigger system To cope with the enhanced luminosity at the Large Hadron Collider (LHC) in 2021, the ATLAS collaboration is planning a major detector upgrade. As a part of this, the Level 1 trigger based on calorimeter data will be upgraded to exploit the fine granularity readout using a new system of Feature EXtractors (FEX), which each reconstruct different physics objects for the trigger selection. The jet FEX (jFEX) system is conceived to provide jet identification (including large area jets) and measurements of global variables within a latency budget of less then 400ns. It consists of 6 modules. A single jFEX module is an ATCA board with 4 large FPGAs of the Xilinx Ultrascale+ family, that can digest a total input data rate of ~3.6 Tb/s using up to 120 Multi Gigabit Transceiver (MGT), 24 electrical optical devices, board control and power on the mezzanines to allow flexibility in upgrading controls functions and components without aff...

Optical interconnects for in-plane high-speed signal distribution at 10 Gb/s: Analysis and demonstration

Science.gov (United States)

Chang, Yin-Jung

With decreasing transistor size, increasing chip speed, and larger numbers of processors in a system, the performance of a module/system is being limited by the off-chip and off-module bandwidth-distance products. Optical links have moved from fiber-based long distance communications to the cabinet level of 1m--100m, and recently to the backplane-level (10cm--1m). Board-level inter-chip parallel optical interconnects have been demonstrated recently by researchers from Intel, IBM, Fujitsu, NTT and a few research groups in universities. However, the board-level signal/clock distribution function using optical interconnects, the lightwave circuits, the system design, a practically convenient integration scheme committed to the implementation of a system prototype have not been explored or carefully investigated. In this dissertation, the development of a board-level 1 x 4 optical-to-electrical signal distribution at 10Gb/s is presented. In contrast to other prototypes demonstrating board-level parallel optical interconnects that have been drawing much attention for the past decade, the optical link design for the high-speed signal broadcasting is even more complicated and the pitch between receivers could be varying as opposed to fixed-pitch design that has been widely-used in the parallel optical interconnects. New challenges for the board-level high-speed signal broadcasting include, but are not limited to, a new optical link design, a lightwave circuit as a distribution network, and a novel integration scheme that can be a complete radical departure from the traditional assembly method. One of the key building blocks in the lightwave circuit is the distribution network in which a 1 x 4 multimode interference (MMI) splitter is employed. MMI devices operating at high data rates are important in board-level optical interconnects and need to be characterized in the application of board-level signal broadcasting. To determine the speed limitations of MMI devices, the

High-Speed On-Board Data Processing Platform for LIDAR Projects at NASA Langley Research Center

Science.gov (United States)

Beyon, J.; Ng, T. K.; Davis, M. J.; Adams, J. K.; Lin, B.

2015-12-01

The project called High-Speed On-Board Data Processing for Science Instruments (HOPS) has been funded by NASA Earth Science Technology Office (ESTO) Advanced Information Systems Technology (AIST) program during April, 2012 - April, 2015. HOPS is an enabler for science missions with extremely high data processing rates. In this three-year effort of HOPS, Active Sensing of CO2 Emissions over Nights, Days, and Seasons (ASCENDS) and 3-D Winds were of interest in particular. As for ASCENDS, HOPS replaces time domain data processing with frequency domain processing while making the real-time on-board data processing possible. As for 3-D Winds, HOPS offers real-time high-resolution wind profiling with 4,096-point fast Fourier transform (FFT). HOPS is adaptable with quick turn-around time. Since HOPS offers reusable user-friendly computational elements, its FPGA IP Core can be modified for a shorter development period if the algorithm changes. The FPGA and memory bandwidth of HOPS is 20 GB/sec while the typical maximum processor-to-SDRAM bandwidth of the commercial radiation tolerant high-end processors is about 130-150 MB/sec. The inter-board communication bandwidth of HOPS is 4 GB/sec while the effective processor-to-cPCI bandwidth of commercial radiation tolerant high-end boards is about 50-75 MB/sec. Also, HOPS offers VHDL cores for the easy and efficient implementation of ASCENDS and 3-D Winds, and other similar algorithms. A general overview of the 3-year development of HOPS is the goal of this presentation.

High-speed readout of high-Z pixel detectors with the LAMBDA detector

International Nuclear Information System (INIS)

Pennicard, D.; Smoljanin, S.; Sheviakov, I.; Xia, Q.; Rothkirch, A.; Yu, Y.; Struth, B.; Hirsemann, H.; Graafsma, H.

2014-01-01

High-frame-rate X-ray pixel detectors make it possible to perform time-resolved experiments at synchrotron beamlines, and to make better use of these sources by shortening experiment times. LAMBDA is a photon-counting hybrid pixel detector based on the Medipix3 chip, designed to combine a small pixel size of 55 μm, a large tileable module design, high speed, and compatibility with ''high-Z'' sensors for hard X-ray detection. This technical paper focuses on LAMBDA's high-speed-readout functionality, which allows a frame rate of 2000 frames per second with no deadtime between successive images. This takes advantage of the Medipix3 chip's ''continuous read-write'' function and highly parallelised readout. The readout electronics serialise this data and send it back to a server PC over two 10 Gigabit Ethernet links. The server PC controls the detector and receives, processes and stores the data using software designed for the Tango control system. As a demonstration of high-speed readout of a high-Z sensor, a GaAs LAMBDA detector was used to make a high-speed X-ray video of a computer fan

Cadence® High High-Speed PCB Design Flow Workshop

CERN Document Server

2006-01-01

Last release of Cadence High-Speed PCB Design methodology (PE142) based on Concept-HDL schematic editor, Constraint Manager, SPECCTRAQuest signal integrity analysis tool and ALLEGRO layout associated with SPECCTRA auto router tools, is now enough developed and stable to be taken into account for high-speed board designs at CERN. The implementation of this methodology, build around the new Constraint Manager program, is essential when you have to develop a board having a lot of high-speed design rules such as terminated lines, large bus structures, maximum length, timing, crosstalk etc.. that could not be under control by traditional method. On more conventional designs, formal aspect of the methodology could avoid misunderstanding between hardware and ALLEGRO layout designers, minimizing prototype iteration, development time and price. The capability to keep trace of the original digital designer intents in schematic or board layout, loading formal constraints in EDMS, could also be considered for LHC electro...

Integration of microelectronic chips in microfluidic systems on printed circuit board

International Nuclear Information System (INIS)

Burdallo, I; Jimenez-Jorquera, C; Fernández-Sánchez, C; Baldi, A

2012-01-01

A new scheme for the integration of small semiconductor transducer chips with microfluidic structures on printed circuit board (PCB) is presented. The proposed approach is based on a packaging technique that yields a large and flat area with small and shallow (∼44 µm deep) openings over the chips. The photocurable encapsulant material used, based on a diacrylate bisphenol A polymer, enables irreversible bonding of polydimethylsiloxane microfluidic structures at moderate temperatures (80 °C). This integration scheme enables the insertion of transducer chips in microfluidic systems with a lower added volume than previous schemes. Leakage tests have shown that the bonded structures withstand more than 360 kPa of pressure. A prototype microfluidic system with two detection chips, including one inter-digitated electrode (IDE) chip for conductivity and one ion selective field effect transistor (ISFET) chip for pH, has been implemented and characterized. Good electrical insulation of the chip contacts and silicon edge surfaces from the solution in the microchannels has been achieved. This integration procedure opens the door to the low-cost fabrication of complex analytical microsystems that combine the extraordinary potential of both the microfluidics and silicon microtechnology fields. (paper)

Real-Time On-Board Airborne Demonstration of High-Speed On-Board Data Processing for Science Instruments (HOPS)

Science.gov (United States)

Beyon, Jeffrey Y.; Ng, Tak-Kwong; Davis, Mitchell J.; Adams, James K.; Bowen, Stephen C.; Fay, James J.; Hutchinson, Mark A.

2015-01-01

The project called High-Speed On-Board Data Processing for Science Instruments (HOPS) has been funded by NASA Earth Science Technology Office (ESTO) Advanced Information Systems Technology (AIST) program since April, 2012. The HOPS team recently completed two flight campaigns during the summer of 2014 on two different aircrafts with two different science instruments. The first flight campaign was in July, 2014 based at NASA Langley Research Center (LaRC) in Hampton, VA on the NASA's HU-25 aircraft. The science instrument that flew with HOPS was Active Sensing of CO2 Emissions over Nights, Days, and Seasons (ASCENDS) CarbonHawk Experiment Simulator (ACES) funded by NASA's Instrument Incubator Program (IIP). The second campaign was in August, 2014 based at NASA Armstrong Flight Research Center (AFRC) in Palmdale, CA on the NASA's DC-8 aircraft. HOPS flew with the Multifunctional Fiber Laser Lidar (MFLL) instrument developed by Excelis Inc. The goal of the campaigns was to perform an end-to-end demonstration of the capabilities of the HOPS prototype system (HOPS COTS) while running the most computationally intensive part of the ASCENDS algorithm real-time on-board. The comparison of the two flight campaigns and the results of the functionality tests of the HOPS COTS are presented in this paper.

An interface board for developing control loops in power electronics based on microcontrollers and DSPs Cores -Arduino /ChipKit /dsPIC /DSP /TI Piccolo

DEFF Research Database (Denmark)

Pittini, Riccardo; Zhang, Zhe; Andersen, Michael A. E.

2013-01-01

and development environment. Moreover, the interface board can operate with open hardware Arduino-like boards such as the ChipKit Uno32. The paper also describes how to enhance the performance of a ChipKit Uno32 with a dsPIC obtaining a more suitable solution for power electronics. The basic blocks and interfaces...... of the boards are presented in detail as well as the board main specifications. The board operation has been tested with three core platforms: TI Piccolo controlSTICK, a Microchip dsPIC and a ChipKit Uno32 (Arduino-like platform). The board was used for generating test signals for characterizing 1200 V Si...

On-Board Video Recording Unravels Bird Behavior and Mortality Produced by High-Speed Trains

Directory of Open Access Journals (Sweden)

Eladio L. García de la Morena

2017-10-01

Full Text Available Large high-speed railway (HSR networks are planned for the near future to accomplish increased transport demand with low energy consumption. However, high-speed trains produce unknown avian mortality due to birds using the railway and being unable to avoid approaching trains. Safety and logistic difficulties have precluded until now mortality estimation in railways through carcass removal, but information technologies can overcome such problems. We present the results obtained with an experimental on-board system to record bird-train collisions composed by a frontal recording camera, a GPS navigation system and a data storage unit. An observer standing in the cabin behind the driver controlled the system and filled out a form with data of collisions and bird observations in front of the train. Photographs of the train front taken before and after each journey were used to improve the record of killed birds. Trains running the 321.7 km line between Madrid and Albacete (Spain at speeds up to 250–300 km/h were equipped with the system during 66 journeys along a year, totaling approximately 14,700 km of effective recording. The review of videos produced 1,090 bird observations, 29.4% of them corresponding to birds crossing the infrastructure under the catenary and thus facing collision risk. Recordings also showed that 37.7% bird crossings were of animals resting on some element of the infrastructure moments before the train arrival, and that the flight initiation distance of birds (mean ± SD was between 60 ± 33 m (passerines and 136 ± 49 m (raptors. Mortality in the railway was estimated to be 60.5 birds/km year on a line section with 53 runs per day and 26.1 birds/km year in a section with 25 runs per day. Our results are the first published estimation of bird mortality in a HSR and show the potential of information technologies to yield useful data for monitoring the impact of trains on birds via on-board recording systems. Moreover

Ultrahigh-speed Si-integrated on-chip laser with tailored dynamic characteristics

DEFF Research Database (Denmark)

Park, Gyeong Cheol; Xue, Weiqi; Piels, Molly

2016-01-01

-pumped compact optical feedback structure can be realised, which together tailor the frequency response function for achieving a very high speed at low injection currents. Furthermore, light can be emitted laterally into a Si waveguide. From an 1.54-μm optically-pumped laser, a 3-dB frequency of 27 GHz...... was obtained at a pumping level corresponding to sub-mA. Using measured 3-dB frequen-cies and calculated equivalent currents, the modulation current efficiency factor (MCEF) is estimated to be 42.1 GHz/mA(1/2), which is superior among microcavity lasers. This shows a high potential for a very high speed at low......For on-chip interconnects, an ideal light source should have an ultralow energy consumption per bandwidth (operating en-ergy) as well as sufficient output power for error-free detection. Nanocavity lasers have been considered the most ideal for smaller operating energy. However, they have...

On-Chip Enucleation of Bovine Oocytes using Microrobot-Assisted Flow-Speed Control

Directory of Open Access Journals (Sweden)

Akihiko Ichikawa

2013-06-01

Full Text Available In this study, we developed a microfluidic chip with a magnetically driven microrobot for oocyte enucleation. A microfluidic system was specially designed for enucleation, and the microrobot actively controls the local flow-speed distribution in the microfluidic chip. The microrobot can adjust fluid resistances in a channel and can open or close the channel to control the flow distribution. Analytical modeling was conducted to control the fluid speed distribution using the microrobot, and the model was experimentally validated. The novelties of the developed microfluidic system are as follows: (1 the cutting speed improved significantly owing to the local fluid flow control; (2 the cutting volume of the oocyte can be adjusted so that the oocyte undergoes less damage; and (3 the nucleus can be removed properly using the combination of a microrobot and hydrodynamic forces. Using this device, we achieved a minimally invasive enucleation process. The average enucleation time was 2.5 s and the average removal volume ratio was 20%. The proposed new system has the advantages of better operation speed, greater cutting precision, and potential for repeatable enucleation.

Neural chips, neural computers and application in high and superhigh energy physics experiments

International Nuclear Information System (INIS)

Nikityuk, N.M.; )

2001-01-01

Architecture peculiarity and characteristics of series of neural chips and neural computes used in scientific instruments are considered. Tendency of development and use of them in high energy and superhigh energy physics experiments are described. Comparative data which characterize the efficient use of neural chips for useful event selection, classification elementary particles, reconstruction of tracks of charged particles and for search of hypothesis Higgs particles are given. The characteristics of native neural chips and accelerated neural boards are considered [ru

Cadence® High-Speed PCB Layout Flow Workshop

CERN Document Server

2003-01-01

Last release of Cadence High-Speed PCB Design methodology (PE142) based on Concept-HDL schematic editor, Constraint Manager, SPECCTRAQuest signal integrity analysis tool and ALLEGRO layout associated with SPECCTRA auto router tools, is now enough developed and stable to be taken into account for high-speed board designs at CERN. The implementation of this methodology, build around the new Constraint Manager program, is essential when you have to develop a board having a lot of high-speed design rules such as terminated lines, large bus structures, maximum length, timing, crosstalk etc.. that could not be under control by traditional method. On more conventional designs, formal aspect of the methodology could avoid misunderstanding between hardware and ALLEGRO layout designers, minimizing prototype iteration, development time and price. The capability to keep trace of the original digital designer intents in schematic or board layout, loading formal constraints in EDMS, could also be considered for LHC electro...

A High-Speed Design of Montgomery Multiplier

Science.gov (United States)

Fan, Yibo; Ikenaga, Takeshi; Goto, Satoshi

With the increase of key length used in public cryptographic algorithms such as RSA and ECC, the speed of Montgomery multiplication becomes a bottleneck. This paper proposes a high speed design of Montgomery multiplier. Firstly, a modified scalable high-radix Montgomery algorithm is proposed to reduce critical path. Secondly, a high-radix clock-saving dataflow is proposed to support high-radix operation and one clock cycle delay in dataflow. Finally, a hardware-reused architecture is proposed to reduce the hardware cost and a parallel radix-16 design of data path is proposed to accelerate the speed. By using HHNEC 0.25μm standard cell library, the implementation results show that the total cost of Montgomery multiplier is 130 KGates, the clock frequency is 180MHz and the throughput of 1024-bit RSA encryption is 352kbps. This design is suitable to be used in high speed RSA or ECC encryption/decryption. As a scalable design, it supports any key-length encryption/decryption up to the size of on-chip memory.

Exposure to electromagnetic fields aboard high-speed electric multiple unit trains.

Science.gov (United States)

Niu, D; Zhu, F; Qiu, R; Niu, Q

2016-01-01

High-speed electric multiple unit (EMU) trains generate high-frequency electric fields, low-frequency magnetic fields, and high-frequency wideband electromagnetic emissions when running. Potential human health concerns arise because the electromagnetic disturbances are transmitted mainly into the car body from windows, and from there to passengers and train staff. The transmission amount and amplitude distribution characteristics that dominate electromagnetic field emission need to be studied, and the exposure level of electromagnetic field emission to humans should be measured. We conducted a series of tests of the on board electromagnetic field distribution on several high-speed railway lines. While results showed that exposure was within permitted levels, the possibility of long-term health effects should be investigated.

Impact of high-pressure coolant supply on chip formation in milling

Science.gov (United States)

Klocke, F.; Döbbeler, B.; Lakner, T.

2017-10-01

Machining of titanium alloys is considered as difficult, because of their high temperature strength, low thermal conductivity and low E-modulus, which contributes to high mechanical loads and high temperatures in the contact zone between tool and workpiece. The generated heat in the cutting zone can be dissipated only in a low extent. When cutting steel materials, up to 75% of the process heat is transported away by the chips, contrary to only 25% when machining titanium alloys. As a result, the cutting tool heats up, which leads to high tool wear. Therefore, machining of titanium alloys is only possible with relatively low cutting speeds. This leads to low levels of productivity for milling processes with titanium alloys. One way to increase productivity is to use more cutting edges in tools with the same diameter. However, the limiting factor of adding more cutting edges to a milling tool is the minimum size of the chip spaces, which are sufficient for a stable chip evacuation. This paper presents experimental results on the chip formation and chip size influenced by high-pressure coolant supply, which can lead to smaller chips and to smaller sizes of the chip spaces, respectively. Both influences, the pressure of the supplied coolant and the volumetric flow rate were individually examined. Alpha-beta annealed titanium TiAl6V4 was examined in relation to the reference material quenched and tempered steel 42CrMo4+QT (AISI 4140+QT). The work shows that with proper chip control due to high-pressure coolant supply in milling, the number of cutting edges on the same diameter tool can be increased, which leads to improved productivity.

Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

Science.gov (United States)

Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

2003-06-01

We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

CMOS analog integrated circuits high-speed and power-efficient design

CERN Document Server

Ndjountche, Tertulien

2011-01-01

High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

Integrated optoelectronic materials and circuits for optical interconnects

International Nuclear Information System (INIS)

Hutcheson, L.D.

1988-01-01

Conventional interconnect and switching technology is rapidly becoming a critical issue in the realization of systems using high speed silicon and GaAs based technologies. In recent years clock speeds and on-chip density for VLSI/VHSIC technology has made packaging these high speed chips extremely difficult. A strong case can be made for using optical interconnects for on-chip/on-wafer, chip-to-chip and board-to-board high speed communications. GaAs integrated optoelectronic circuits (IOC's) are being developed in a number of laboratories for performing Input/Output functions at all levels. In this paper integrated optoelectronic materials, electronics and optoelectronic devices are presented. IOC's are examined from the standpoint of what it takes to fabricate the devices and what performance can be expected

Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails

Science.gov (United States)

Hashida, Takushi; Nagata, Makoto

Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100Mbps. A pair of transceivers consumes 1.35mA from 3.3V, at 130Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50dB.

Design and characterization of high-speed CMOS pseudo-LVDS transceivers

International Nuclear Information System (INIS)

Kondratenko, S V

2016-01-01

High-speed transceiver for on-board systems of data collection and processing need to meet additional requirements, such as low power consumption and increased radiation hardness. It is therefore necessary to compare and search for alternative variants of transceivers on the physical layer, where high transfer speed is not achieved at the cost of a significant increase in power consumption or a limitation of transmission distance by the size of a printed circuit board. For on-board applications, it is also necessary to solve the problem of increasing the radiation hardness without going to expensive types of technology. In this paper, we studied some variants of implementation of pseudo-LVDS transceivers and analyzed their achievable quantitative characteristics. According to the results of calculations and analysis of the literature, specialized transceivers of this type, intended for the manufacture or manufactured according to the bulk CMOS technology processes in the range of 250-80 nm, can provide data speeds up to 6 Gbps at a specific power consumption of less than 4 mW/Gbps. (paper)

Design and characterization of high-speed CMOS pseudo-LVDS transceivers

Science.gov (United States)

Kondratenko, S. V.

2016-02-01

High-speed transceiver for on-board systems of data collection and processing need to meet additional requirements, such as low power consumption and increased radiation hardness. It is therefore necessary to compare and search for alternative variants of transceivers on the physical layer, where high transfer speed is not achieved at the cost of a significant increase in power consumption or a limitation of transmission distance by the size of a printed circuit board. For on-board applications, it is also necessary to solve the problem of increasing the radiation hardness without going to expensive types of technology. In this paper, we studied some variants of implementation of pseudo-LVDS transceivers and analyzed their achievable quantitative characteristics. According to the results of calculations and analysis of the literature, specialized transceivers of this type, intended for the manufacture or manufactured according to the bulk CMOS technology processes in the range of 250-80 nm, can provide data speeds up to 6 Gbps at a specific power consumption of less than 4 mW/Gbps.

An Analysis of an Ultra-High Speed Content-Addressable Database Retrieval System

National Research Council Canada - National Science Library

Costianes, Peter

2001-01-01

...) and its implementation as a high speed optical chip. The paradigm uses polarization states to represent binary very words and EO modulators to represent database words to perform what is essentially XOR operations...

Plastic straw: future of high-speed signaling

Science.gov (United States)

Song, Ha Il; Jin, Huxian; Bae, Hyeon-Min

2015-11-01

The ever-increasing demand for bandwidth triggered by mobile and video Internet traffic requires advanced interconnect solutions satisfying functional and economic constraints. A new interconnect called E-TUBE is proposed as a cost-and-power-effective all-electrical-domain wideband waveguide solution for high-speed high-volume short-reach communication links. The E-TUBE achieves an unprecedented level of performance in terms of bandwidth-per-carrier frequency, power, and density without requiring a precision manufacturing process unlike conventional optical/waveguide solutions. The E-TUBE exhibits a frequency-independent loss-profile of 4 dB/m and has nearly 20-GHz bandwidth over the V band. A single-sideband signal transmission enabled by the inherent frequency response of the E-TUBE renders two-times data throughput without any physical overhead compared to conventional radio frequency communication technologies. This new interconnect scheme would be attractive to parties interested in high throughput links, including but not limited to, 100/400 Gbps chip-to-chip communications.

Full-field parallel interferometry coherence probe microscope for high-speed optical metrology.

Science.gov (United States)

Safrani, A; Abdulhalim, I

2015-06-01

Parallel detection of several achromatic phase-shifted images is used to obtain a high-speed, high-resolution, full-field, optical coherence probe tomography system based on polarization interferometry. The high enface imaging speed, short coherence gate, and high lateral resolution provided by the system are exploited to determine microbump height uniformity in an integrated semiconductor chip at 50 frames per second. The technique is demonstrated using the Linnik microscope, although it can be implemented on any polarization-based interference microscopy system.

Holistic design in high-speed optical interconnects

Science.gov (United States)

Saeedi, Saman

Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a corresponding increase in inter-chip communication bandwidth. As bandwidth requirements for chip-to-chip interconnection scale, deficiencies of electrical channels become more apparent. Optical links present a viable alternative due to their low frequency-dependent loss and higher bandwidth density in the form of wavelength division multiplexing. As integrated photonics and bonding technologies are maturing, commercialization of hybrid-integrated optical links are becoming a reality. Increasing silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics brings their performance to unprecedented levels. This thesis presents developments in high-speed optical links by co-designing and co-integrating the primary elements of an optical link: receiver, transmitter, and clocking. In the first part of this thesis a 3D-integrated CMOS/Silicon-photonic receiver will be presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. Measured results show -14.9dBm of sensitivity and energy eciency of 170fJ/b at 25Gb/s. The same receiver front-end is also used to implement source-synchronous 4-channel WDM-based parallel optical receiver. Quadrature ILO-based clocking is employed for synchronization and a novel frequency-tracking method that exploits the dynamics of IL in a quadrature ring oscillator to increase the effective locking range. An adaptive body-biasing circuit is designed to maintain the per-bit-energy consumption constant across wide data-rates. The prototype measurements indicate a record-low power consumption of 153fJ/b at 32Gb/s. The

A novel conductive-polymer-based integration process for high-performance flip-chip packages

Science.gov (United States)

Lohokare, Saurabh

Conductive polymers have recently attracted considerable attention for low-temperature fabrication of lead-free, reworkable, and flexible flip-chip interconnects. Using these materials, I demonstrate in this thesis a process that enables low-cost and high-resolution flip-chip interconnects using conventional micro-fabrication techniques. This fabrication process offers improved performance as compared to conventional flip-chip techniques, such as screen-printing, and allows for definition of interconnects with excellent surface uniformity and control over the bump profile. In order to demonstrate the utility and wide applicability of this process, several test implementations that serve as case studies were investigated. Specifically, novel InGaAsSb avalanche photodiodes (APDs), operating around lambda = 2m and targeted for free-space communication and biomedical spectroscopy applications, were fabricated and flip-chip-integrated to test the static electrical characteristics of the polymer bumps. Additionally, the dynamic electrical performance characteristics of the polymer bumps were studied by using AlGaAsSb/AlGaSb p-i-n photodetectors as a case study. The fabrication of these photodetectors, operating around lambda = 1.55mum and targeted for optical communication applications, was accomplished using a customized inductively coupled plasma (ICP) etch process that resulted in a low dark current and excellent speed (3dB bandwidth of 10GHz) and, responsivity (60% external quantum efficiency) characteristics. Furthermore, flip-chip integration was used to demonstrate a three-dimensional, point-to-point micro-optical interconnect, which was 2.33mm-long in a system 15.27mm3 in volume. Lastly, high-speed parallel optical interconnects were demonstrated using polymer-flip-chip-integrated 10GHz vertical-cavity surface-emitting laser (VCSEL) and DOEs. Such interconnects offer the ability to alleviate the communication bottleneck that is projected to occur in future, high

Impedance Discontinuity Reduction Between High-Speed Differential Connectors and PCB Interfaces

Science.gov (United States)

Navidi, Sal; Agdinaoay, Rodell; Walter, Keith

2013-01-01

High-speed serial communication (i.e., Gigabit Ethernet) requires differential transmission and controlled impedances. Impedance control is essential throughout cabling, connector, and circuit board construction. An impedance discontinuity arises at the interface of a high-speed quadrax and twinax connectors and the attached printed circuit board (PCB). This discontinuity usually is lower impedance since the relative dielectric constant of the board is higher (i.e., polyimide approx. = 4) than the connector (Teflon approx. = 2.25). The discontinuity can be observed in transmit or receive eye diagrams, and can reduce the effective link margin of serial data networks. High-speed serial data network transmission improvements can be made at the connector-to-board interfaces as well as improving differential via hole impedances. The impedance discontinuity was improved by 10 percent by drilling a 20-mil (approx. = 0.5-mm) hole in between the pin of a differential connector spaced 55 mils (approx. = 1.4 mm) apart as it is attached to the PCB. The effective dielectric constant of the board can be lowered by drilling holes into the board material between the differential lines in a quadrax or twinax connector attachment points. The differential impedance is inversely proportional to the square root of the relative dielectric constant. This increases the differential impedance and thus reduces the above described impedance discontinuity. The differential via hole impedance can also be increased in the same manner. This technique can be extended to multiple smaller drilled holes as well as tapered holes (i.e., big in the middle followed by smaller ones diagonally).

The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

Directory of Open Access Journals (Sweden)

Amlan Ganguly

2018-02-01

Full Text Available With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.

Design and testing of the high speed signal densely populated ATLAS calorimeter trigger board dedicate to jet identification

CERN Document Server

Vieira De Souza, Julio; The ATLAS collaboration

2018-01-01

The ATLAS experiment has planned a major upgrade in view of the enhanced luminosity of the beam delivered by the Large Hadron Collider (LHC) in 2021. As part of this, the trigger at Level-1 based on calorimeter data will be upgraded to exploit fine-granularity readout using a new system of Feature Extractors (three in total), which each uses different physics objects for the trigger selection. The contribution focusses on the jet Feature EXtractor (jFEX) prototype. Up to a data volume of 2 TB/s has to be processed to provide jet identification (including large area jets) and measurements of global variables within few hundred nanoseconds latency budget. Such requirements translate into the use of large Field Programmable Gate Array (FPGA) with the largest number of Multi Gigabit Transceivers (MGTs) available on the market. The jFEX board prototype hosts four large FPGAs from the Xilinx Ultrascale family with 120 MGTs each, connected to 24 opto-electrical devices, resulting in a densely populated high speed si...

Comparison of microrings and microdisks for high-speed optical modulation in silicon photonics

Science.gov (United States)

Ying, Zhoufeng; Wang, Zheng; Zhao, Zheng; Dhar, Shounak; Pan, David Z.; Soref, Richard; Chen, Ray T.

2018-03-01

The past several decades have witnessed the gradual transition from electrical to optical interconnects, ranging from long-haul telecommunication to chip-to-chip interconnects. As one type of key component in integrated optical interconnect and high-performance computing, optical modulators have been well developed these past few years, including ultrahigh-speed microring and microdisk modulators. In this paper, a comparison between microring and microdisk modulators is well analyzed in terms of dimensions, static and dynamic power consumption, and fabrication tolerance. The results show that microdisks have advantages over microrings in these aspects, which gives instructions to the chip design of high-density integrated systems for optical interconnects and optical computing.

Random On-Board Pixel Sampling (ROPS) X-Ray Camera

Energy Technology Data Exchange (ETDEWEB)

Wang, Zhehui [Los Alamos; Iaroshenko, O. [Los Alamos; Li, S. [Los Alamos; Liu, T. [Fermilab; Parab, N. [Argonne (main); Chen, W. W. [Purdue U.; Chu, P. [Los Alamos; Kenyon, G. [Los Alamos; Lipton, R. [Fermilab; Sun, K.-X. [Nevada U., Las Vegas

2017-09-25

Recent advances in compressed sensing theory and algorithms offer new possibilities for high-speed X-ray camera design. In many CMOS cameras, each pixel has an independent on-board circuit that includes an amplifier, noise rejection, signal shaper, an analog-to-digital converter (ADC), and optional in-pixel storage. When X-ray images are sparse, i.e., when one of the following cases is true: (a.) The number of pixels with true X-ray hits is much smaller than the total number of pixels; (b.) The X-ray information is redundant; or (c.) Some prior knowledge about the X-ray images exists, sparse sampling may be allowed. Here we first illustrate the feasibility of random on-board pixel sampling (ROPS) using an existing set of X-ray images, followed by a discussion about signal to noise as a function of pixel size. Next, we describe a possible circuit architecture to achieve random pixel access and in-pixel storage. The combination of a multilayer architecture, sparse on-chip sampling, and computational image techniques, is expected to facilitate the development and applications of high-speed X-ray camera technology.

Design of a one-chip board microcontrol unit for active vibration control of a naval ship mounting system

International Nuclear Information System (INIS)

Oh, Jong-Seok; Choi, Seung-Bok; Han, Young-Min; Nguyen, Vien-Quoc; Moon, Seok-Jun

2012-01-01

This work presents an experimental implementation of a user-tunable one-chip board microcontrol unit which is specifically designed for vibration control of the active mounting system for naval ships. The proposed mounting system consists of four active mounts supporting vibration-sensitive equipment. Each active mount constitutes a rubber element, an inertial mass and the piezostack actuator. It is designed for particular applications that require effective isolation performance against wide frequency ranges, such as naval ship equipment. After describing the configuration of the active mount, dynamic characteristics of the rubber element and the piezostack actuator are experimentally identified. Accordingly, the proposed mounting system is constructed and the governing equations of motion are formulated. In order to attenuate the unwanted vibrations transferred from the upper mass, a feedforward controller with fast Fourier algorithm is designed and experimentally realized using the one-chip microcontrol board which is specially made for this practical application. In order to evaluate the performance of the one-chip microcontrol unit, vibration control results of the proposed active mounting system are presented in the frequency domain. (technical note)

Ultra-high-speed Optical Signal Processing using Silicon Photonics

DEFF Research Database (Denmark)

Oxenløwe, Leif Katsuo; Ji, Hua; Jensen, Asger Sellerup

with a photonic layer on top to interconnect them. For such systems, silicon is an attractive candidate enabling both electronic and photonic control. For some network scenarios, it may be beneficial to use optical on-chip packet switching, and for high data-density environments one may take advantage...... of the ultra-fast nonlinear response of silicon photonic waveguides. These chips offer ultra-broadband wavelength operation, ultra-high timing resolution and ultra-fast response, and when used appropriately offer energy-efficient switching. In this presentation we review some all-optical functionalities based...... on silicon photonics. In particular we use nano-engineered silicon waveguides (nanowires) [1] enabling efficient phasematched four-wave mixing (FWM), cross-phase modulation (XPM) or self-phase modulation (SPM) for ultra-high-speed optical signal processing of ultra-high bit rate serial data signals. We show...

Faults Detection in a Photovoltaic Generator by Using Matlab Simulink and the chipKIT Max32 Board

Directory of Open Access Journals (Sweden)

Riadh Khenfer

2014-01-01

Full Text Available This paper presents a laboratory with equipment and an algorithm for teaching graduate students the monitoring and the diagnosis of PV arrays. The contribution is the presentation of an algorithm to detect and localize the fault, in photovoltaic generator when a limited number of voltage sensors are used. An I-V curve tracer using a capacitive load is exploited to measure the I-V characteristics of PV arrays. Such measurement allows characterization of PV arrays on-site, under real operating conditions, and provides also information for the detection of potential array anomalies. This I-V curve tracer is based on a microcontroller board family called chipKIT Max32 which is a popular platform for physical computing. A user program can be developed visually on a PC side via the graphical user interface (GUI in Matlab Simulink, where the chipKIT Max32 of Digilent which is a low-cost board is designed for use with the Arduinompid software. The obtained results from the partial shade default showed the effectiveness of the proposed diagnosis method and the good functioning of this board with the Matlab/Simulink environment.

Trigger Data Serializer ASIC chip for the ATLAS New Small Wheel sTGC Detector

CERN Document Server

Wang, Jinhong; The ATLAS collaboration

2014-01-01

The small-strip Thin-Gap Chambers (sTGC) will be used as both trigger and precision tracking muon detectors for the Phase-I upgrade of the ATLAS New Small Wheel (NSW) muon detector. Signals from both the sTGC pad and strip detectors will be first read out by the Amplifier-Shaper-Discriminator (ASD) chip designed by the Brookhaven National Laboratory, and then collected and transmitted by a Trigger Data Serializer (TDS) chip at a rate of 4.8 Gbps to other related circuits. The pad-TDS chip checks the presence of pad hits and sends the information together with Bunching Crossing ID to the pad-trigger logic to define roads of interest. The strip-TDS chip collects and buffers strip charge information and transmits a range of strips within the road of interest to the router board located on the rim of the NSW. The large number of input channels (128 differential input channels), short time available to prepare and transmit trigger data (<100 ns), high speed output data rate (4.8 Gbps), harsh radiation environme...

Development of embedded real-time and high-speed vision platform

Science.gov (United States)

Ouyang, Zhenxing; Dong, Yimin; Yang, Hua

2015-12-01

Currently, high-speed vision platforms are widely used in many applications, such as robotics and automation industry. However, a personal computer (PC) whose over-large size is not suitable and applicable in compact systems is an indispensable component for human-computer interaction in traditional high-speed vision platforms. Therefore, this paper develops an embedded real-time and high-speed vision platform, ER-HVP Vision which is able to work completely out of PC. In this new platform, an embedded CPU-based board is designed as substitution for PC and a DSP and FPGA board is developed for implementing image parallel algorithms in FPGA and image sequential algorithms in DSP. Hence, the capability of ER-HVP Vision with size of 320mm x 250mm x 87mm can be presented in more compact condition. Experimental results are also given to indicate that the real-time detection and counting of the moving target at a frame rate of 200 fps at 512 x 512 pixels under the operation of this newly developed vision platform are feasible.

A high speed dual-gain preamplifier system with multiple channels

International Nuclear Information System (INIS)

Zhao Lei; Liu Shubin; Xian Ze; An Qi

2008-01-01

In this paper, a multiple-channel high speed preamplifier module with dual-gain is presented, together with its design principle, test methods and performance parameter. By proper choice of the chips and careful circuit design, the preamplifier accomplishes a fine performance in high speed analog signal processing. The 3 dB bandwidth is above 440 MHz for gain factor of 2 and 280 MHz for gain factor of 8, with the leading edge time of less than 2 ns. The preamplifier module has been used in the research project of β-delayed neutron emission of radionuclides in neutron-rich region. (authors)

Design of high-speed data transmission system for Lanzhou heavy ion therapy accelerator

International Nuclear Information System (INIS)

Mao Wenyu; Qiao Weimin; Jing Lan; Li Guihua

2012-01-01

In order to satisfy the transmission requirements of partial synchronization data and process data for the heavy ion therapy accelerator, a high-speed, error-correction, long-distance, and real-time data transmission system was proposed and achieved. It can improve the efficiency and reliability of the accelerator control and synchronization. The system optimizes the hardware configuration and layout of the traditional system. FPGA, gigabit fiber module, PXI and SDRAM are the main parts of the system. It replaces the low-speed, short-distance, and poor anti-interference of the traditional data path and the data processing chips. Through the programming in the two FPGA chips, the PXI and DMA transmission mode was used to exchange data with the server of the accelerator. The front-end of the system achieves a real-time, long-distance, and high-speed serial frame transmission with 800 MHz carrier and 100 MHz base band signal. The real-time -data like synchronous event signal, power waveform data of the heavy ion therapy accelerator can be transmitted efficiently between the server and the remote controller through the system. (authors)

Design of the ANTARES LCM-DAQ board test bench using a FPGA-based system-on-chip approach

Energy Technology Data Exchange (ETDEWEB)

Anvar, S. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France); Kestener, P. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France)]. E-mail: pierre.kestener@cea.fr; Le Provost, H. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France)

2006-11-15

The System-on-Chip (SoC) approach consists in using state-of-the-art FPGA devices with embedded RISC processor cores, high-speed differential LVDS links and ready-to-use multi-gigabit transceivers allowing development of compact systems with substantial number of IO channels. Required performances are obtained through a subtle separation of tasks between closely cooperating programmable hardware logic and user-friendly software environment. We report about our experience in using the SoC approach for designing the production test bench of the off-shore readout system for the ANTARES neutrino experiment.

Microstructural characterization of WC-TiC-Co cutting tools during high-speed machining of P20 mold steel

International Nuclear Information System (INIS)

Farhat, Z.N.

2003-01-01

The wear behavior of tungsten carbide (WC)-TiC-Co cutting tools during cutting P20 tool steel was investigated. Orthogonal cutting tests were performed on a CNC lathe using five speeds, namely, 60, 120, 240, 380 and 600 m/min. Wear, as the width of the wear land, was monitored at five time intervals. Wear characterization of the rake and the flank surfaces as well as the collected chips was performed using scanning electron microscopy (SEM), backscattered electron imaging and energy-dispersive X-ray analysis (EDX). Microhardness of collected chips was also performed to monitor strain hardening effects during cutting. Two dominant wear mechanisms were identified: at high speed (380-600 m/min), wear was found to occur by a melt wear mechanism; at low speed (60-120 m/min), adhesion (built-up edge) followed by delamination was found to be the cause of wear damage. It was also found that deformation in the chips occurred by localized shear deformation

High speed ultrasonic system to measure bubbles velocities in a horizontal two-phase flow

International Nuclear Information System (INIS)

Cunha Filho, Jurandyr S.; Jian Su; Farias, Marcos S.; Faccini, Jose L.H.; Lamy, Carlos A.

2009-01-01

In this work, a non invasive technique consisting of a high speed ultrasonic multitransducer pulse-echo system was developed to characterize gas-liquid two-phase flow parameters that are important in the study of the primary refrigeration circuit of nuclear reactors. The high speed ultrasonic system consists of two transducers (10 MHz/φ 6.35 mm), a generator/multiplexer board, and software that selects and has a data acquisition system of the ultrasonic signals. The resolutions of the system and the pulse time generated from each transducer are, respectively, 10 ns and 1.06 ms. The system initially was used in the local instantaneous measurement of gas-liquid interface in a circular horizontal pipe test section made of a 5 m long stainless steel pipe of 51.2 mm inner diameter, where the elongated bubbles velocity was measured (Taylor bubbles). The results show that the high speed ultrasonic pulse-echo system provides good results for the determination of elongated bubbles velocities. (author)

Integrated High-Speed Torque Control System for a Robotic Joint

Science.gov (United States)

Davis, Donald R. (Inventor); Radford, Nicolaus A. (Inventor); Permenter, Frank Noble (Inventor); Valvo, Michael C. (Inventor); Askew, R. Scott (Inventor)

2013-01-01

A control system for achieving high-speed torque for a joint of a robot includes a printed circuit board assembly (PCBA) having a collocated joint processor and high-speed communication bus. The PCBA may also include a power inverter module (PIM) and local sensor conditioning electronics (SCE) for processing sensor data from one or more motor position sensors. Torque control of a motor of the joint is provided via the PCBA as a high-speed torque loop. Each joint processor may be embedded within or collocated with the robotic joint being controlled. Collocation of the joint processor, PIM, and high-speed bus may increase noise immunity of the control system, and the localized processing of sensor data from the joint motor at the joint level may minimize bus cabling to and from each control node. The joint processor may include a field programmable gate array (FPGA).

MACSYM. Towards a system of measurement and control on a single chip

Energy Technology Data Exchange (ETDEWEB)

Zannoli, S

1984-03-01

Since it is now possible to produce A/D and D/A integrated circuits on a single chip at a remarkably low cost, the production of an entire system for the acquisition of measurements and control of data on a single chip can be foreseen. The MACSYM (measurement and control system), produced by Analog Devices Inc., contains all its components on a single circuit board. The MACSYM 150 is a multiprocessor with separate analogue and digital buses. Because it contains three CPUS with special functions, it has high operating speeds and can handle a number of programs simultaneously. Since this model is designed for on line and real time measurements of physical quantities it has a number of different stores, including a central store, a store for graphs in colour and fast output and input stores for metered data. The author describes the interface provided and the terminals to which data can be supplied and mentions the programming language used.

Optimization of high frequency flip-chip interconnects for digital superconducting circuits

International Nuclear Information System (INIS)

Rafique, M R; Engseth, H; Kidiyarova-Shevchenko, A

2006-01-01

This paper presents the results of theoretical optimization of the multi-chip-module (MCM) contact and driver circuitries for gigabit chip-to-chip communication. Optimization has been done using 3D electromagnetic (EM) simulations of MCM contacts and time domain simulations of drivers and receivers. A single optimized MCM contact has a signal reflection of less than -20 dB for more than 400 GHz bandwidth. The MCM data link with the optimized SFQ driver, receiver and two MCM contacts has operational margins on the global bias current of ± 30% at 30 Gbit s -1 speedand can operate above 100 Gbit s -1 speed. Wide bandwidth transmission requires the realization of an advanced flip-chip process with a small dimension of the MCM contact (less than 30 μm diameter of the contact pad) and small height of the flip-chip contact bumps of the order of 2 μm. Current processes with about 7 μm height of the bumps require the application of a double-flux-quantum (DFQ) driver. The data link with the DFQ driver was also simulated. It has operational margins on the global bias current of ± 30% at 30 Gbit s -1 ; however, the maximum speed of operation is 61 Gbit s -1 . Several test structures have been designed for measurements of signal reflection, bit error rate and operational margins of the data link

New Observations on High-Speed Machining of Hardened AISI 4340 Steel Using Alumina-Based Ceramic Tools

Directory of Open Access Journals (Sweden)

Mohamed Shalaby

2018-05-01

Full Text Available High-speed machining (HSM is used in industry to improve the productivity and quality of the cutting operations. In this investigation, pure alumina ceramics with the addition of ZrO2, and mixed alumina (Al2O3 + TiC tools were used in the dry hard turning of AISI 4340 (52 HRC at different high cutting speeds of 150, 250, 700 and 1000 m/min. It was observed that at cutting speeds of 150 and 250 m/min, pure alumina ceramic tools had better wear resistance than mixed alumina ones. However, upon increasing the cutting speed from 700 to 1000 m/min, mixed alumina ceramic tools outperformed pure ceramic ones. Scanning electron microscopy (SEM and X-ray photoelectron spectroscopy (XPS were used to investigate the worn cutting edges and analyze the obtained results. It was found that the tribo-films formed at the cutting zone during machining affected the wear resistances of the tools and influenced the coefficient of friction at the tool-chip interface. These observations were confirmed by the chip compression ratio results at different cutting conditions. Raising cutting speed to 1000 m/min corresponded to a remarkable decrease in cutting force components in the dry hard turning of AISI 4340 steel.

High-Speed Computation using FPGA for Excellent Performance of Direct Torque Control of Induction Machines

Directory of Open Access Journals (Sweden)

Tole Sutikno

2016-03-01

Full Text Available The major problems in hysteresis-based DTC are high torque ripple and variable switching frequency. In order to minimize the torque ripple, high sampling time and fast digital realization should be applied. The high sampling and fast digital realization time can be achieved by utilizing high-speed processor where the operation of the discrete hysteresis regulator is becoming similar to the operation of analog-based comparator. This can be achieved by utilizing field programmable gate array (FPGA which can perform a sampling at a very high speed, compared to the fact that developing an ASIC chip is expensive and laborious.

Adiabatic shear bands as predictors of strain rate in high speed machining of ramax-2

International Nuclear Information System (INIS)

Zeb, M.A.; Irfan, M.A.; Velduis, A.C.

2008-01-01

Shear band formation was studied in the chips obtained by turning of stainless steel- Ramax-2 (AISI 420F). The machining was performed on a CNC lathe using a PVD (Physical Vapor Deposition) cutting tool insert. The cutting speeds ranged from 50 m/ min to 250 m/min. Dry cutting conditions were employed. At cutting speeds higher than 30 m/mill, the chip did not remain intact with the workpiece using quick stop device. It was difficult to get the chip root SEM (Scanning Electron Microscope) micrographs at further higher speeds. Therefore, the width of the shear bands was used as the predictor of the strain rates involved at various cutting speeds. The results showed that the strain rates are quite in agreement with the amount of strain rate found during machining of such types of stainless steels. It was also observed that shear band density increased with increasing cutting speed. (author)

High-speed computation of the EM algorithm for PET image reconstruction

International Nuclear Information System (INIS)

Rajan, K.; Patnaik, L.M.; Ramakrishna, J.

1994-01-01

The PET image reconstruction based on the EM algorithm has several attractive advantages over the conventional convolution backprojection algorithms. However, two major drawbacks have impeded the routine use of the EM algorithm, namely, the long computational time due to slow convergence and the large memory required for the storage of the image, projection data and the probability matrix. In this study, the authors attempts to solve these two problems by parallelizing the EM algorithm on a multiprocessor system. The authors have implemented an extended hypercube (EH) architecture for the high-speed computation of the EM algorithm using the commercially available fast floating point digital signal processor (DSP) chips as the processing elements (PEs). The authors discuss and compare the performance of the EM algorithm on a 386/387 machine, CD 4360 mainframe, and on the EH system. The results show that the computational speed performance of an EH using DSP chips as PEs executing the EM image reconstruction algorithm is about 130 times better than that of the CD 4360 mainframe. The EH topology is expandable with more number of PEs

Development of a Metal Cutting Tool Fase in Order to Create the Conditions of Ringed Chips Wrapping

OpenAIRE

Korchuganova, Mariya Anatolievna; Syrbakov, Andrey Pavlovich; Chernysheva, Tatiana Yurievna; Ivanov, G.; Korchuganov, Maksim Anatolievich

2016-01-01

When processing ductile metals with high cutting speed, there is a need to take additional measures for a comfortable and safe formation and removal of chips. In the conditions of large-scale manufacture, it is recommended to produce flow chips in the form of short fragments, while in the conditions of small-lot and single-piece manufacture, it is reasonable to wrap the chips spirally with a rather small turn radius. Such way of chips formation reduces the time of its removal from the working...

High speed UNIBUS-VME interface

International Nuclear Information System (INIS)

Olmos, P.

1987-01-01

An interface between VME an the UNIBUS of PDP or VAX computer is presented. The system supports high speed parallel communication (up to 1MB/S) and is composed of two modules. One of these is a commercial DR11M board which performs DMA transfers between UNIBUS and the external word. The other is a VME module specifically developed for this application. The interface has been tested under VMS operating system in VAX and VALET-PLUS system for the VME Bus. We describe in detail the VME module and its connection with the DR11M. Software, both in WMS and VALET, is also described. (Author) 7 refs

The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip

Directory of Open Access Journals (Sweden)

Junning Chen

2013-07-01

Full Text Available This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

ChalkBoard: Mapping Functions to Polygons

Science.gov (United States)

Matlage, Kevin; Gill, Andy

ChalkBoard is a domain specific language for describing images. The ChalkBoard language is uncompromisingly functional and encourages the use of modern functional idioms. ChalkBoard uses off-the-shelf graphics cards to speed up rendering of functional descriptions. In this paper, we describe the design of the core ChalkBoard language, and the architecture of our static image generation accelerator.

Variation Tolerant On-Chip Interconnects

CERN Document Server

Nigussie, Ethiopia Enideg

2012-01-01

This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects.  Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems. Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect; Describes design techniques to mitigate problems caused by variation; Includes techniques for design and implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperature variation tolerance.                          

Modelling Of Residual Stresses Induced By High Speed Milling Process

International Nuclear Information System (INIS)

Desmaison, Olivier; Mocellin, Katia; Jardin, Nicolas

2011-01-01

Maintenance processes used in heavy industries often include high speed milling operations. The reliability of the post-process material state has to be studied. Numerical simulation appears to be a very interesting way to supply an efficient residual stresses (RS) distribution prediction.Because the adiabatic shear band and the serrated chip shaping are features of the austenitic stainless steel high speed machining, a 2D high speed orthogonal cutting model is briefly presented. This finite element model, developed on Forge registered software, is based on data taken from Outeiro and al.'s paper [1]. A new behaviour law fully coupling Johnson-Cook's constitutive law and Latham and Cockcroft's damage model is detailed in this paper. It ensures results that fit those found in literature.Then, the numerical tools used on the 2D model are integrated to a 3D high speed milling model. Residual stresses distribution is analysed, on the surface and into the depth of the material. Various revolutions and passes of the two teeth hemispheric mill on the workpiece are simulated. Thus the sensitivity of the residual stresses generation to the cutting conditions can be discussed. In order to validate the 3D model, a comparison of the cutting forces measured by EDF R and D to those given by numerical simulations is achieved.

Embedded systems design for high-speed data acquisition and control

CERN Document Server

Di Paolo Emilio, Maurizio

2015-01-01

This book serves as a practical guide for practicing engineers who need to design embedded systems for high-speed data acquisition and control systems. A minimum amount of theory is presented, along with a review of analog and digital electronics, followed by detailed explanations of essential topics in hardware design and software development. The discussion of hardware focuses on microcontroller design (ARM microcontrollers and FPGAs), techniques of embedded design, high speed data acquisition (DAQ) and control systems. Coverage of software development includes main programming techniques, culminating in the study of real-time operating systems. All concepts are introduced in a manner to be highly-accessible to practicing engineers and lead to the practical implementation of an embedded board that can be used in various industrial fields as a control system and high speed data acquisition system.   • Describes fundamentals of embedded systems design in an accessible manner; • Takes a problem-solving ...

Fundamental study of microelectronic chip response under laser ultrasonic-interferometric inspection using C-scan method

Science.gov (United States)

Yang, Lei; Gong, Jie; Ume, I. Charles

2014-02-01

In modern surface mount packaging technologies, such as flip chips, chip scale packages, and ball grid arrays(BGA), chips are attached to the substrates/printed wiring board (PWB) using solder bump interconnections. The quality of solder bumps between the chips and the substrate/board is difficult to inspect. Laser ultrasonic-interferometric technique was proved to be a promising approach for solder bump inspection because of its noncontact and nondestructive characteristics. Different indicators extracted from received signals have been used to predict the potential defects, such as correlation coefficient, error ratio, frequency shifting, etc. However, the fundamental understanding of the chip behavior under laser ultrasonic inspection is still missing. Specifically, it is not sure whether the laser interferometer detected out-of-plane displacements were due to wave propagation or structural vibration when the chip was excited by pulsed laser. Plus, it is found that the received signals are chip dependent. Both challenges impede the interpretation of acquired signals. In this paper, a C-scan method was proposed to study the underlying phenomenon during laser ultrasonic inspection. The full chip was inspected. The response of the chip under laser excitation was visualized in a movie resulted from acquired signals. Specifically, a BGA chip was investigated to demonstrate the effectiveness of this method. By characterizing signals using discrete wavelet transform(DWT), both ultrasonic wave propagation and vibration were observed. Separation of them was successfully achieved using ideal band-pass filter and visualized in resultant movies, too. The observed ultrasonic waves were characterized and their respective speeds were measured by applying 2-D FFT. The C-scan method, combined with different digital signal processing techniques, was proved to be an very effective methodology to learn the behavior of chips under laser excitation. This general procedure can be

High-speed high-sensitivity infrared spectroscopy using mid-infrared swept lasers (Conference Presentation)

Science.gov (United States)

Childs, David T. D.; Groom, Kristian M.; Hogg, Richard A.; Revin, Dmitry G.; Cockburn, John W.; Rehman, Ihtesham U.; Matcher, Stephen J.

2016-03-01

Infrared spectroscopy is a highly attractive read-out technology for compositional analysis of biomedical specimens because of its unique combination of high molecular sensitivity without the need for exogenous labels. Traditional techniques such as FTIR and Raman have suffered from comparatively low speed and sensitivity however recent innovations are challenging this situation. Direct mid-IR spectroscopy is being speeded up by innovations such as MEMS-based FTIR instruments with very high mirror speeds and supercontinuum sources producing very high sample irradiation levels. Here we explore another possible method - external cavity quantum cascade lasers (EC-QCL's) with high cavity tuning speeds (mid-IR swept lasers). Swept lasers have been heavily developed in the near-infrared where they are used for non-destructive low-coherence imaging (OCT). We adapt these concepts in two ways. Firstly by combining mid-IR quantum cascade gain chips with external cavity designs adapted from OCT we achieve spectral acquisition rates approaching 1 kHz and demonstrate potential to reach 100 kHz. Secondly we show that mid-IR swept lasers share a fundamental sensitivity advantage with near-IR OCT swept lasers. This makes them potentially able to achieve the same spectral SNR as an FTIR instrument in a time x N shorter (N being the number of spectral points) under otherwise matched conditions. This effect is demonstrated using measurements of a PDMS sample. The combination of potentially very high spectral acquisition rates, fundamental SNR advantage and the use of low-cost detector systems could make mid-IR swept lasers a powerful technology for high-throughput biomedical spectroscopy.

Subsurface damage mechanism of high speed grinding process in single crystal silicon revealed by atomistic simulations

International Nuclear Information System (INIS)

Li, Jia; Fang, Qihong; Zhang, Liangchi; Liu, Youwen

2015-01-01

Highlights: • Molecular dynamic model of nanoscale high speed grinding of silicon workpiece has been established. • The effect of grinding speed on subsurface damage and grinding surface integrity by analyzing the chip, dislocation movement, and phase transformation during high speed grinding process are thoroughly investigated. • Subsurface damage is studied by the evolution of surface area at first time for more obvious observation on transition from ductile to brittle. • The hydrostatic stress and von Mises stress by the established analytical model are studied subsurface damage mechanism during nanoscale grinding. - Abstract: Three-dimensional molecular dynamics (MD) simulations are performed to investigate the nanoscale grinding process of single crystal silicon using diamond tool. The effect of grinding speed on subsurface damage and grinding surface integrity by analyzing the chip, dislocation movement, and phase transformation are studied. We also establish an analytical model to calculate several important stress fields including hydrostatic stress and von Mises stress for studying subsurface damage mechanism, and obtain the dislocation density on the grinding subsurface. The results show that a higher grinding velocity in machining brittle material silicon causes a larger chip and a higher temperature, and reduces subsurface damage. However, when grinding velocity is above 180 m s −1 , subsurface damage thickness slightly increases because a higher grinding speed leads to the increase in grinding force and temperature, which accelerate dislocation nucleation and motion. Subsurface damage is studied by the evolution of surface area at first time for more obvious observation on transition from ductile to brittle, that provides valuable reference for machining nanometer devices. The von Mises stress and the hydrostatic stress play an important role in the grinding process, and explain the subsurface damage though dislocation mechanism under high

High-speed architecture for the decoding of trellis-coded modulation

Science.gov (United States)

Osborne, William P.

1992-01-01

Since 1971, when the Viterbi Algorithm was introduced as the optimal method of decoding convolutional codes, improvements in circuit technology, especially VLSI, have steadily increased its speed and practicality. Trellis-Coded Modulation (TCM) combines convolutional coding with higher level modulation (non-binary source alphabet) to provide forward error correction and spectral efficiency. For binary codes, the current stare-of-the-art is a 64-state Viterbi decoder on a single CMOS chip, operating at a data rate of 25 Mbps. Recently, there has been an interest in increasing the speed of the Viterbi Algorithm by improving the decoder architecture, or by reducing the algorithm itself. Designs employing new architectural techniques are now in existence, however these techniques are currently applied to simpler binary codes, not to TCM. The purpose of this report is to discuss TCM architectural considerations in general, and to present the design, at the logic gate level, or a specific TCM decoder which applies these considerations to achieve high-speed decoding.

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

Science.gov (United States)

Lin, Shu; Uehara, Gregory T.

1996-01-01

implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Cutting Temperature Investigation of AISI H13 in High Speed End Milling

Directory of Open Access Journals (Sweden)

Muhammad Riza

2016-10-01

Full Text Available Heat produced at the tool-chip interface during high speed milling operations have been known as a significant factor that affect to tool life and workpiece geometry or properties. This paper aims to investigate cutting temperature behaviours of AISI H13 (48 HRC under high speed machining circumstances during pocketing. The experiments were conducted on CNC vertical machining centre by using PVD coated carbide insert. Milling processes were done at cutting speeds 150, 200 and 250 m/min and feed rate were 0.05, 0.1 and 0.15 mm/tooth. Depths of cut applied were 0.1, 0.15 and 0.2 mm. Tool path method applied in this experiment was contour in. Results presented in this paper indicate that by increasing cutting speed the cutting temperature is lower than low cutting speed. However, by decreasing feed rate leads to cutting temperature low. Cutting temperature phenomena at the corner of pocket milling were also investigated. The phenomena showed that cutting temperature tends to decrease a moment when cutter comes to the corner of pocket and turning point of tool path and increase extremely a moment before leaving the corner and turning point.

On-chip power delivery and management

CERN Document Server

Vaisband, Inna P; Popovich, Mikhail; Mezhiba, Andrey V; Köse, Selçuk; Friedman, Eby G

2016-01-01

This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power delivery and management systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this fourth edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.

Optical bio-sensors in microfluidic chips

NARCIS (Netherlands)

Pollnau, Markus; Dongre, C.; Pham Van So, P.V.S.; Bernhardi, Edward; Worhoff, Kerstin; de Ridder, R.M.; Hoekstra, Hugo

2012-01-01

Direct femtosecond laser writing is used to integrate optical waveguides that intersect the microfluidic channels in a commercial optofluidic chip. With laser excitation, fluorescently labeled DNA molecules of different sizes are separated by capillary electrophoresis with high operating speed and

New generation of single-chip microcomputers focused on cost performance

Energy Technology Data Exchange (ETDEWEB)

Akao, Y.; Iwashita, H. (Hitachi, Ltd., Tokyo (Japan))

1993-06-01

A single-chip microcomputer which incorporates a CPU (central processing unit), memory, and peripheral functions in one chip has been increasingly applied to various fields as the heart of electronic equipment in terms of its economy, compactness, lightness, and suitability for mass production. In response to a wide variety of needs, a lineup must have substantial breadth with regard to performance, on-chip memory capacity, on-chip peripheral functions, operating voltage, and packaging. In particular, low-voltage high-speed operation, high integration, expanded address space, and improved software productivity, which are required for mobile communication terminals, are the common needs for single-chip microcomputers. In accordance with these needs, Hitachi has been actively developing new products. The present paper introduces Hitachi's lineup of single-chip microcomputers. 10 figs., 1 tab.

Wear mechanism of CBN cutting tool during high-speed machining of mold steel

International Nuclear Information System (INIS)

Farhat, Z.N.

2003-01-01

Wear behavior of cubic boron nitride (CBN) cutting tool when cutting P20 tool steel was investigated. Oblique cutting tests were performed on a CNC lathe using five speeds, namely, 240, 600 and 1000 m min -1 . The CBN cutting tools were found to be superior to tungsten carbide (WC) tools. Fourfold increase in productivity and significant reduction in chipping and cratering was achieved for CBN as compared to WC. Wear, as the width of the wear land (VB), was monitored at selected time intervals; furthermore, topography of worn surfaces was performed, using a profilometer. Wear characterization of the rake and the flank surfaces as well as of the collected chips was conducted using a scanning electron microscopy (SEM), backscattered electron imaging and energy depressive X-ray (EDX). It was found that deformation in the chips occurs by localized shear deformation and the dominant wear mechanism at all speeds used was identified to be diffusive wear. At a 1000 m min -1 cutting speed, a secondary wear mechanism was identified, which is melt wear, i.e., formation of low melting point Cr and Mn compounds with the tool material and the subsequent ejection from the cutting zone

Using a High-Speed Camera to Measure the Speed of Sound

Science.gov (United States)

Hack, William Nathan; Baird, William H.

2012-01-01

The speed of sound is a physical property that can be measured easily in the lab. However, finding an inexpensive and intuitive way for students to determine this speed has been more involved. The introduction of affordable consumer-grade high-speed cameras (such as the Exilim EX-FC100) makes conceptually simple experiments feasible. Since the…

Reconfigurable radio-frequency arbitrary waveforms synthesized in a silicon photonic chip.

Science.gov (United States)

Wang, Jian; Shen, Hao; Fan, Li; Wu, Rui; Niu, Ben; Varghese, Leo T; Xuan, Yi; Leaird, Daniel E; Wang, Xi; Gan, Fuwan; Weiner, Andrew M; Qi, Minghao

2015-01-12

Photonic methods of radio-frequency waveform generation and processing can provide performance advantages and flexibility over electronic methods due to the ultrawide bandwidth offered by the optical carriers. However, bulk optics implementations suffer from the lack of integration and slow reconfiguration speed. Here we propose an architecture of integrated photonic radio-frequency generation and processing and implement it on a silicon chip fabricated in a semiconductor manufacturing foundry. Our device can generate programmable radio-frequency bursts or continuous waveforms with only the light source, electrical drives/controls and detectors being off-chip. It modulates an individual pulse in a radio-frequency burst within 4 ns, achieving a reconfiguration speed three orders of magnitude faster than thermal tuning. The on-chip optical delay elements offer an integrated approach to accurately manipulating individual radio-frequency waveform features without constraints set by the speed and timing jitter of electronics, and should find applications ranging from high-speed wireless to defence electronics.

A molecular dynamics investigation into the mechanisms of subsurface damage and material removal of monocrystalline copper subjected to nanoscale high speed grinding

International Nuclear Information System (INIS)

Li, Jia; Fang, Qihong; Liu, Youwen; Zhang, Liangchi

2014-01-01

This paper investigates the mechanisms of subsurface damage and material removal of monocrystalline copper when it is under a nanoscale high speed grinding of a diamond tip. The analysis was carried out with the aid of three-dimensional molecular dynamics simulations. The key factors that would influence the deformation of the material were carefully explored by analyzing the chip, dislocation movement, and workpiece deformation, which include grinding speed, depth of cut, grid tip radius, crystal orientation and machining angle of copper. An analytical model was also established to predict the emission of partial dislocations during the nanoscale high speed grinding. The investigation showed that a higher grinding velocity, a larger tip radius or a larger depth of cut would result in a larger chipping volume and a greater temperature rise in the copper workpiece. A lower grinding velocity would produce more intrinsic stacking faults. It was also found that the transition of deformation mechanisms depends on the competition between the dislocations and deformation twinning. There is a critical machining angle, at which a higher velocity, a smaller tip radius, or a smaller depth of cut will reduce the subsurface damage and improve the smoothness of a ground surface. The established analytical model showed that the Shockley dislocation emission is most likely to occur with the crystal orientations of (0 0 1)[1 0 0] at 45° angle.

Energetic optimization of regenerative braking for high speed railway systems

International Nuclear Information System (INIS)

Frilli, Amedeo; Meli, Enrico; Nocciolini, Daniele; Pugi, Luca; Rindi, Andrea

2016-01-01

Highlights: • A model of longitudinal dynamics of the High-speed train ETR1000 is presented. • The model includes on board traction and braking subsystems. • Interactions between overhead line and power line are modelled. • The model is validated on real experimental data. • An energy storage strategy for a high-speed line is proposed. - Abstract: The current development trend in the railway field has led to an ever increasing interest for the energetic optimization of railway systems (especially considering the braking phases), with a strong attention to the mutual interactions between the loads represented by railway vehicles and the electrical infrastructure, including all the sub-systems related to distribution and smart energy management such as energy storage systems. In this research work, the authors developed an innovative coupled modelling approach suitable for the analysis of the energetic optimization of railway systems and based on the use of the new object oriented language Matlab-Simscape™, which presents several advantages with respect to conventional modelling tools. The proposed model has been validated considering an Italian Direct Current High-speed line and the High-speed train ETR 1000. Furthermore, the model has been used to perform an efficiency analysis, considering the use of energy storage devices. The results obtained with the developed model show that the use of energy recovery systems in high-speed railway can provide great opportunities of energy savings.

Characterization of Tool Wear in High-Speed Milling of Hardened Powder Metallurgical Steels

Directory of Open Access Journals (Sweden)

Fritz Klocke

2011-01-01

Full Text Available In this experimental study, the cutting performance of ball-end mills in high-speed dry-hard milling of powder metallurgical steels was investigated. The cutting performance of the milling tools was mainly evaluated in terms of cutting length, tool wear, and cutting forces. Two different types of hardened steels were machined, the cold working steel HS 4-2-4 PM (K490 Microclean/66 HRC and the high speed steel HS 6-5-3 PM (S790 Microclean/64 HRC. The milling tests were performed at effective cutting speeds of 225, 300, and 400 m/min with a four fluted solid carbide ball-end mill (0 = 6, TiAlN coating. It was observed that by means of analytically optimised chipping parameters and increased cutting speed, the tool life can be drastically enhanced. Further, in machining the harder material HS 4-2-4 PM, the tool life is up to three times in regard to the less harder material HS 6-5-3 PM. Thus, it can be assumed that not only the hardness of the material to be machined plays a vital role for the high-speed dry-hard cutting performance, but also the microstructure and thermal characteristics of the investigated powder metallurgical steels in their hardened state.

Flexible multimode polymer waveguides for high-speed short-reach communication links

Science.gov (United States)

Bamiedakis, N.; Shi, F.; Chu, D.; Penty, R. V.; White, I. H.

2018-02-01

Multimode polymer waveguides have attracted great interest for use in high-speed short-reach communication links as they can be cost-effectively integrated onto standard PCBs using conventional methods of the electronics industry and provide low loss (30 GHz×m) interconnection. The formation of such waveguides on flexible substrates can further provide flexible low-weight low-thickness interconnects and offer additional freedom in the implementation of high-speed short-reach optical links. These attributes make these flexible waveguides particularly attractive for use in low-cost detachable chip-to-chip links and in environments where weight and shape conformity become important, such as in cars and aircraft. However, the highly-multimoded nature of these waveguides raises important questions about their performance under severe flex due to mode loss and mode coupling. In this work therefore, we investigate the loss, crosstalk and bandwidth performance of such waveguides under out-of plane bending and in-plane twisting under different launch conditions and carry out data transmission tests at 40 Gb/s on a 1 m long spiral flexible waveguide under flexure. Excellent optical transmission characteristics are obtained while robust loss, crosstalk and bandwidth performance are demonstrated under flexure. Error-free (BER<10-12) 40 Gb/s data transmission is achieved over the 1 m long spiral waveguide for a 180° bend with a 4 mm radius. The obtained results demonstrate the excellent optical and mechanical properties of this technology and highlight its potential for use in real-world systems.

Development of Neuromorphic Sift Operator with Application to High Speed Image Matching

Science.gov (United States)

Shankayi, M.; Saadatseresht, M.; Bitetto, M. A. V.

2015-12-01

There was always a speed/accuracy challenge in photogrammetric mapping process, including feature detection and matching. Most of the researches have improved algorithm's speed with simplifications or software modifications which increase the accuracy of the image matching process. This research tries to improve speed without enhancing the accuracy of the same algorithm using Neuromorphic techniques. In this research we have developed a general design of a Neuromorphic ASIC to handle algorithms such as SIFT. We also have investigated neural assignment in each step of the SIFT algorithm. With a rough estimation based on delay of the used elements including MAC and comparator, we have estimated the resulting chip's performance for 3 scenarios, Full HD movie (Videogrammetry), 24 MP (UAV photogrammetry), and 88 MP image sequence. Our estimations led to approximate 3000 fps for Full HD movie, 250 fps for 24 MP image sequence and 68 fps for 88MP Ultracam image sequence which can be a huge improvement for current photogrammetric processing systems. We also estimated the power consumption of less than10 watts which is not comparable to current workflows.

Ultrahigh-speed, high-sensitivity color camera with 300,000-pixel single CCD

Science.gov (United States)

Kitamura, K.; Arai, T.; Yonai, J.; Hayashida, T.; Ohtake, H.; Kurita, T.; Tanioka, K.; Maruyama, H.; Namiki, J.; Yanagi, T.; Yoshida, T.; van Kuijk, H.; Bosiers, Jan T.; Etoh, T. G.

2007-01-01

We have developed an ultrahigh-speed, high-sensitivity portable color camera with a new 300,000-pixel single CCD. The 300,000-pixel CCD, which has four times the number of pixels of our initial model, was developed by seamlessly joining two 150,000-pixel CCDs. A green-red-green-blue (GRGB) Bayer filter is used to realize a color camera with the single-chip CCD. The camera is capable of ultrahigh-speed video recording at up to 1,000,000 frames/sec, and small enough to be handheld. We also developed a technology for dividing the CCD output signal to enable parallel, highspeed readout and recording in external memory; this makes possible long, continuous shots up to 1,000 frames/second. As a result of an experiment, video footage was imaged at an athletics meet. Because of high-speed shooting, even detailed movements of athletes' muscles were captured. This camera can capture clear slow-motion videos, so it enables previously impossible live footage to be imaged for various TV broadcasting programs.

SVX Sequencer Board

International Nuclear Information System (INIS)

Utes, M.

1997-01-01

The SVX Sequencer boards are 9U by 280mm circuit boards that reside in slots 2 through 21 of each of eight Eurocard crates in the D0 Detector Platform. The basic purpose is to control the SVX chips for data acquisition and when a trigger occurs, to gather the SVX data and relay the data to the VRB boards in the Movable Counting House. Functions and features are as follows: (1) Initialization of eight SVX chip strings using the MIL-STD-1553 data bus; (2) Real time manipulation of the SVX control lines to effect data acquisition, digitization, and readout based on the NRZ/Clock signals from the Controller; (3) Conversion of 8-bit electrical SVX readout data to an optical signal operating at 1.062 Gbit/sec, sent to the VRB. Eight HDIs will be serviced per board; (4) Built-in logic analyzer which can record the most important control and data lines during a data acquisition cycle and put this recorded information onto the 1553 bus; (5) Identification header and end of data trailer tacked onto data stream; (6) 1553 register which can read the current values of the control and data lines; (7) 1553 register which can test the optical link; (8) 1553 registers for crossing pulse width, calibration pulse voltage, and calibration pipeline select; (9) 1553 register for reading the optical drivers status link; (10) 1553 register for power control of SVX chips and ignoring bad SVX strings; (11) Front panel displays and LEDs show the board status at a glance; (12) In-system programmable EPLDs are programmed via 1553 or Altera's 'Bitblaster'; (13) Automatic readout abort after 45us; (14) Supplies BUSY signal back to Trigger Framework; (15) Supports a heartbeat system to prevent excessive SVX current draw; and (16) Supports a SVX power trip feature if heartbeat failure occurs.

White LEDs and modules in chip-on-board technology for general lighting

Science.gov (United States)

Hartmann, Paul; Wenzl, Franz P.; Sommer, Christian; Pachler, Peter; Hoschopf, Hans; Schweighart, Marko; Hartmann, Martin; Kuna, Ladislav; Jakopic, Georg; Leising, Guenther; Tasch, Stefan

2006-08-01

At present, light-emitting diode (LED) modules in various shapes are developed and designed for the general lighting, advertisement, emergency lighting, design and architectural markets. To compete with and to surpass the performance of traditional lighting systems, enhancement of Lumen output and the white light quality as well as the thermal management and the luminary integration are key factors for success. Regarding these issues, white LEDs based on the chip-on-board (COB) technology show pronounced advantages. State-of-the-art LEDs exploiting this technology are now ready to enter the general lighting segments. We introduce and discuss the specific properties of the Tridonic COB technology dedicated for general lighting. This technology, in combination with a comprehensive set of tools to improve and to enhance the Lumen output and the white light quality, including optical simulation, is the scaffolding for the application of white LEDs in emerging areas, for which an outlook will be given.

Testing and Validation of Timing Properties for High Speed Digital Cameras - A Best Practices Guide

Science.gov (United States)

2016-07-27

range, and frame rate get all the press when it comes to high-speed video viewed in Range Control; however, most optical data is practically...introduction of hydraulic and electrically-driven mount servo systems  The replacement of fixed optics sites with remotely-controlled mobile systems  The...support (e.g., VendorX Timing Tests with staggered 10-μs pulse sequence). (5) Select Press to Locate Board ID. The Define Board ID file should

High-speed uncooled MWIR hostile fire indication sensor

Science.gov (United States)

Zhang, L.; Pantuso, F. P.; Jin, G.; Mazurenko, A.; Erdtmann, M.; Radhakrishnan, S.; Salerno, J.

2011-06-01

Hostile fire indication (HFI) systems require high-resolution sensor operation at extremely high speeds to capture hostile fire events, including rocket-propelled grenades, anti-aircraft artillery, heavy machine guns, anti-tank guided missiles and small arms. HFI must also be conducted in a waveband with large available signal and low background clutter, in particular the mid-wavelength infrared (MWIR). The shortcoming of current HFI sensors in the MWIR is the bandwidth of the sensor is not sufficient to achieve the required frame rate at the high sensor resolution. Furthermore, current HFI sensors require cryogenic cooling that contributes to size, weight, and power (SWAP) in aircraft-mounted applications where these factors are at a premium. Based on its uncooled photomechanical infrared imaging technology, Agiltron has developed a low-SWAP, high-speed MWIR HFI sensor that breaks the bandwidth bottleneck typical of current infrared sensors. This accomplishment is made possible by using a commercial-off-the-shelf, high-performance visible imager as the readout integrated circuit and physically separating this visible imager from the MWIR-optimized photomechanical sensor chip. With this approach, we have achieved high-resolution operation of our MWIR HFI sensor at 1000 fps, which is unprecedented for an uncooled infrared sensor. We have field tested our MWIR HFI sensor for detecting all hostile fire events mentioned above at several test ranges under a wide range of environmental conditions. The field testing results will be presented.

A One Chip Hardened Solution for High Speed SpaceWire System Implementations. Session: Components

Science.gov (United States)

Marshall, Joseph R.; Berger, Richard W.; Rakow, Glenn P.

2007-01-01

An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASIC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a router with 4 SpaceWire ports and two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, and a memory controller for additional external memory use. The SpaceWire cores are also reused in other ASICs under development. The SpaceWire ASIC is planned for use on the Geostationary Operational Environmental Satellites (GOES)-R, the Lunar Reconnaissance Orbiter (LRO) and other missions. Engineering and flight parts have been delivered to programs and users. This paper reviews the SpaceWire protocol and those elements of it that have been built into the current and next SpaceWire reusable cores and features within the core that go beyond the current standard and can be enabled or disabled by the user. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be reviewed and highlighted. Optional configurations within user systems and test boards will be shown. The physical implementation of the design will be described and test results from the hardware will be discussed. Application of this ASIC and other ASICs containing the SpaceWire cores and embedded microcontroller to Plug and Play and reconfigurable implementations will be described. Finally, the BAE Systems roadmap for SpaceWire developments will be updated, including some products already in design as well as longer term plans.

Ultrahigh-speed hybrid laser for silicon photonic integrated chips

DEFF Research Database (Denmark)

Chung, Il-Sug; Park, Gyeong Cheol; Ran, Qijiang

2013-01-01

Increasing power consumption for electrical interconnects between and inside chips is posing a real challenge to continue the performance scaling of processors/computers as predicted by D. Moore. In recent processors, energy consumption for electrical interconnects is half of power supplied...... and will be 80% in near future. This challenge strongly has motivated replacing electrical interconnects with optical ones even in chip level communications [1]. This chip-level optical interconnects need quite different performance of optoelectronic devices than required for conventional optical communications....... For a light source, the energy consumption per sending a bit is required to be

High speed machinability of the aerospace alloy AA7075 T6 under different cooling conditions

Science.gov (United States)

Imbrogno, Stano; Rinaldi, Sergio; Suarez, Asier Gurruchaga; Arrazola, Pedro J.; Umbrello, Domenico

2018-05-01

This paper describes the results of an experimental investigation aimed to st udy the machinability of AA7075 T6 (160 HV) for aerospace industry at high cutting speeds. The paper investigates the effects of different lubri-cooling strategies (cryogenic, M QL and dry) during high speed turning process on cutting forces, tool wear, chip morphology and cutting temperatures. The cutting speeds selected were 1000m/min, 1250m/min and 1500 m/min, while the feed rate values used were 0.1mm/rev and 0.3 mm/rev. The results of cryogenic and M QL application is compared with dry application. It was found that the cryogenic and M QL lubri-cooling techniques could represent a functional alternative to the common dry cutting application in order to implement a more effect ive high speed turning process. Higher cuttingparameters would be able to increase the productivity and reduce the production costs. The effects of the cutting parameters and on the variables object of study were investigated and the role of the different lubri-cooling conditions was assessed.

Using a high-speed movie camera to evaluate slice dropping in clinical image interpretation with stack mode viewers.

Science.gov (United States)

Yakami, Masahiro; Yamamoto, Akira; Yanagisawa, Morio; Sekiguchi, Hiroyuki; Kubo, Takeshi; Togashi, Kaori

2013-06-01

The purpose of this study is to verify objectively the rate of slice omission during paging on picture archiving and communication system (PACS) viewers by recording the images shown on the computer displays of these viewers with a high-speed movie camera. This study was approved by the institutional review board. A sequential number from 1 to 250 was superimposed on each slice of a series of clinical Digital Imaging and Communication in Medicine (DICOM) data. The slices were displayed using several DICOM viewers, including in-house developed freeware and clinical PACS viewers. The freeware viewer and one of the clinical PACS viewers included functions to prevent slice dropping. The series was displayed in stack mode and paged in both automatic and manual paging modes. The display was recorded with a high-speed movie camera and played back at a slow speed to check whether slices were dropped. The paging speeds were also measured. With a paging speed faster than half the refresh rate of the display, some viewers dropped up to 52.4 % of the slices, while other well-designed viewers did not, if used with the correct settings. Slice dropping during paging was objectively confirmed using a high-speed movie camera. To prevent slice dropping, the viewer must be specially designed for the purpose and must be used with the correct settings, or the paging speed must be slower than half of the display refresh rate.

High speed atom source

International Nuclear Information System (INIS)

Hoshino, Hitoshi.

1990-01-01

In a high speed atom source, since the speed is not identical between ions and electrons, no sufficient neutralizing effect for ionic rays due to the mixing of the ionic rays and the electron rays can be obtained failing to obtain high speed atomic rays at high density. In view of the above, a speed control means is disposed for equalizing the speed of ions forming ionic rays and the speed of electrons forming electron rays. Further, incident angle of the electron rays and/or ionic rays to a magnet or an electrode is made variable. As a result, the relative speed between the ions and the electrons to the processing direction is reduced to zero, in which the probability of association between the ions and the electrons due to the coulomb force is increased to improve the neutralizing efficiency to easily obtain fine and high density high speed electron rays. Further, by varying the incident angle, a track capable of obtaining an ideal mixing depending on the energy of the neutralized ionic rays is formed. Since the high speed electron rays has such high density, they can be irradiated easily to the minute region of the specimen. (N.H.)

Findings on pollutant formation in wood and chip board combustion. Erkenntnisse zur Schadstoffbildung bei der Verbrennung von Holz und Spanplatten

Energy Technology Data Exchange (ETDEWEB)

Marutzky, R.

1991-10-01

Combustion experiments were carried out using wood and several types of chip boards with binders on the basis of urea, melamine and phenol formaldehyde resins, polyureas, and PVC. The combustion process was observed, and the flue gas constituents in case of incomplete combustion were analyzed. The origins of the various organic and inorganic materials were discussed taking account of the results of pyrolysis experiments. (orig.).

Innovative on board payload optical architecture for high throughput satellites

Science.gov (United States)

Baudet, D.; Braux, B.; Prieur, O.; Hughes, R.; Wilkinson, M.; Latunde-Dada, K.; Jahns, J.; Lohmann, U.; Fey, D.; Karafolas, N.

2017-11-01

For the next generation of HighThroughPut (HTP) Telecommunications Satellites, space end users' needs will result in higher link speeds and an increase in the number of channels; up to 512 channels running at 10Gbits/s. By keeping electrical interconnections based on copper, the constraints in term of power dissipation, number of electrical wires and signal integrity will become too demanding. The replacement of the electrical links by optical links is the most adapted solution as it provides high speed links with low power consumption and no EMC/EMI. But replacing all electrical links by optical links of an On Board Payload (OBP) is challenging. It is not simply a matter of replacing electrical components with optical but rather the whole concept and architecture have to be rethought to achieve a high reliability and high performance optical solution. In this context, this paper will present the concept of an Innovative OBP Optical Architecture. The optical architecture was defined to meet the critical requirements of the application: signal speed, number of channels, space reliability, power dissipation, optical signals crossing and components availability. The resulting architecture is challenging and the need for new developments is highlighted. But this innovative optically interconnected architecture will substantially outperform standard electrical ones.

Towards Chip Scale Liquid Chromatography and High Throughput Immunosensing

Energy Technology Data Exchange (ETDEWEB)

Ni, Jing [Iowa State Univ., Ames, IA (United States)

2000-09-21

This work describes several research projects aimed towards developing new instruments and novel methods for high throughput chemical and biological analysis. Approaches are taken in two directions. The first direction takes advantage of well-established semiconductor fabrication techniques and applies them to miniaturize instruments that are workhorses in analytical laboratories. Specifically, the first part of this work focused on the development of micropumps and microvalves for controlled fluid delivery. The mechanism of these micropumps and microvalves relies on the electrochemically-induced surface tension change at a mercury/electrolyte interface. A miniaturized flow injection analysis device was integrated and flow injection analyses were demonstrated. In the second part of this work, microfluidic chips were also designed, fabricated, and tested. Separations of two fluorescent dyes were demonstrated in microfabricated channels, based on an open-tubular liquid chromatography (OT LC) or an electrochemically-modulated liquid chromatography (EMLC) format. A reduction in instrument size can potentially increase analysis speed, and allow exceedingly small amounts of sample to be analyzed under diverse separation conditions. The second direction explores the surface enhanced Raman spectroscopy (SERS) as a signal transduction method for immunoassay analysis. It takes advantage of the improved detection sensitivity as a result of surface enhancement on colloidal gold, the narrow width of Raman band, and the stability of Raman scattering signals to distinguish several different species simultaneously without exploiting spatially-separated addresses on a biochip. By labeling gold nanoparticles with different Raman reporters in conjunction with different detection antibodies, a simultaneous detection of a dual-analyte immunoassay was demonstrated. Using this scheme for quantitative analysis was also studied and preliminary dose-response curves from an immunoassay of a

Application of drive circuit based on L298N in direct current motor speed control system

Science.gov (United States)

Yin, Liuliu; Wang, Fang; Han, Sen; Li, Yuchen; Sun, Hao; Lu, Qingjie; Yang, Cheng; Wang, Quanzhao

2016-10-01

In the experiment of researching the nanometer laser interferometer, our design of laser interferometer circuit system is up to the wireless communication technique of the 802.15.4 IEEE standard, and we use the RF TI provided by Basic to receive the data on speed control system software. The system's hardware is connected with control module and the DC motor. However, in the experiment, we found that single chip microcomputer control module is very difficult to drive the DC motor directly. The reason is that the DC motor's starting and braking current is larger than the causing current of the single chip microcomputer control module. In order to solve this problem, we add a driving module that control board can transmit PWM wave signal through I/O port to drive the DC motor, the driving circuit board can come true the function of the DC motor's positive and reversal rotation and speed adjustment. In many various driving module, the L298N module's integrated level is higher compared with other driver module. The L298N model is easy to control, it not only can control the DC motor, but also achieve motor speed control by modulating PWM wave that the control panel output. It also has the over-current protection function, when the motor lock, the L298N model can protect circuit and motor. So we use the driver module based on L298N to drive the DC motor. It is concluded that the L298N driver circuit module plays a very important role in the process of driving the DC motor in the DC motor speed control system.

Cache-aware network-on-chip for chip multiprocessors

Science.gov (United States)

Tatas, Konstantinos; Kyriacou, Costas; Dekoulis, George; Demetriou, Demetris; Avraam, Costas; Christou, Anastasia

2009-05-01

This paper presents the hardware prototype of a Network-on-Chip (NoC) for a chip multiprocessor that provides support for cache coherence, cache prefetching and cache-aware thread scheduling. A NoC with support to these cache related mechanisms can assist in improving systems performance by reducing the cache miss ratio. The presented multi-core system employs the Data-Driven Multithreading (DDM) model of execution. In DDM thread scheduling is done according to data availability, thus the system is aware of the threads to be executed in the near future. This characteristic of the DDM model allows for cache aware thread scheduling and cache prefetching. The NoC prototype is a crossbar switch with output buffering that can support a cache-aware 4-node chip multiprocessor. The prototype is built on the Xilinx ML506 board equipped with a Xilinx Virtex-5 FPGA.

Design and reliability analysis of high-speed and continuous data recording system based on disk array

Science.gov (United States)

Jiang, Changlong; Ma, Cheng; He, Ning; Zhang, Xugang; Wang, Chongyang; Jia, Huibo

2002-12-01

In many real-time fields the sustained high-speed data recording system is required. This paper proposes a high-speed and sustained data recording system based on the complex-RAID 3+0. The system consists of Array Controller Module (ACM), String Controller Module (SCM) and Main Controller Module (MCM). ACM implemented by an FPGA chip is used to split the high-speed incoming data stream into several lower-speed streams and generate one parity code stream synchronously. It also can inversely recover the original data stream while reading. SCMs record lower-speed streams from the ACM into the SCSI disk drivers. In the SCM, the dual-page buffer technology is adopted to implement speed-matching function and satisfy the need of sustainable recording. MCM monitors the whole system, controls ACM and SCMs to realize the data stripping, reconstruction, and recovery functions. The method of how to determine the system scale is presented. At the end, two new ways Floating Parity Group (FPG) and full 2D-Parity Group (full 2D-PG) are proposed to improve the system reliability and compared with the Traditional Parity Group (TPG). This recording system can be used conveniently in many areas of data recording, storing, playback and remote backup with its high-reliability.

Signal Integrity Analysis of High-Speed Interconnects

CERN Document Server

Oltean Karlsson, A

2007-01-01

LHC detectors and future experiments will produce very large amount of data that will be transferred at multi-Gigabit speeds. At such data rates, signal-integrity effects become important and traditional rules of thumb are no longer enough for the design and layout of the traces. Simulations for signal-integrity effects at board level provide a way to study and validate several scenarios before arriving at a set of optimized design rules prior to building the actual printed circuit board (PCB). This article describes some of the available tools at CERN. Two case studies will be used to highlight the capabilities of these programs.

An Integrated Power-Efficient Active Rectifier With Offset-Controlled High Speed Comparators for Inductively Powered Applications

Science.gov (United States)

Lee, Hyung-Min; Ghovanloo, Maysam

2011-01-01

We present an active full-wave rectifier with offset-controlled high speed comparators in standard CMOS that provides high power conversion efficiency (PCE) in high frequency (HF) range for inductively powered devices. This rectifier provides much lower dropout voltage and far better PCE compared to the passive on-chip or off-chip rectifiers. The built-in offset-control functions in the comparators compensate for both turn-on and turn-off delays in the main rectifying switches, thus maximizing the forward current delivered to the load and minimizing the back current to improve the PCE. We have fabricated this active rectifier in a 0.5-μm 3M2P standard CMOS process, occupying 0.18 mm2 of chip area. With 3.8 V peak ac input at 13.56 MHz, the rectifier provides 3.12 V dc output to a 500 Ω load, resulting in the PCE of 80.2%, which is the highest measured at this frequency. In addition, overvoltage protection (OVP) as safety measure and built-in back telemetry capabilities have been incorporated in our design using detuning and load shift keying (LSK) techniques, respectively, and tested. PMID:22174666

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

Science.gov (United States)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Application of high-speed photography to hydrodynamic instability research

International Nuclear Information System (INIS)

Chang Lihua; Li Zuoyou; Xiao Zhengfei; Zou Liyong; Liu Jinhong; Xiong Xueshi

2012-01-01

High-speed photography is used to study the Rayleigh-Taylor instability of air-water interface driven by high- pressure exploding gas. Clear images illustrating the instability are obtained, along with the air bubble peak speed and turbulent mixing speed. The RM (Richtmyer-Meshkov) instability of air/SF 6 interface driven by shock wave is also researched by using high-speed Schlieren technique on the horizontal shock tube and primary experimental results are obtained, which show the change of the turbulent mixing region clearly. (authors)

High-speed charge-to-time converter ASIC for the Super-Kamiokande detector

Energy Technology Data Exchange (ETDEWEB)

Nishino, H., E-mail: nishino@post.kek.j [Institute for Cosmic Ray Research, University of Tokyo, Chiba 277-8582 (Japan); Awai, K.; Hayato, Y.; Nakayama, S.; Okumura, K.; Shiozawa, M.; Takeda, A. [Institute for Cosmic Ray Research, University of Tokyo, Chiba 277-8582 (Japan); Ishikawa, K.; Minegishi, A. [Iwatsu Test Instruments Corporation, Tokyo 168-8511 (Japan); Arai, Y. [The Institute of Particle and Nuclear Studies, KEK, Ibaraki 305-0801 (Japan)

2009-11-11

A new application-specific integrated circuit (ASIC), the high-speed charge-to-time converter (QTC) IWATSU CLC101, provides three channels, each consisting of preamplifier, discriminator, low-pass filter, and charge integration circuitry, optimized for the waveform of a photomultiplier tube (PMT). This ASIC detects PMT signals using individual built-in discriminators and drives output timing signals whose width represents the integrated charge of the PMT signal. Combined with external input circuits composed of passive elements, the QTC provides full analog signal processing for the detector's PMTs, ready for further processing by time-to-digital converters (TDCs). High-rate (>1MHz) signal processing is achieved by short-charge-conversion-time and baseline-restoration circuits. Wide-range charge measurements are enabled by offering three gain ranges while maintaining a short cycle time. QTC chip test results show good analog performance, with efficient detection for a single photoelectron signal, four orders of magnitude dynamic range (0.3mVapprox3V; 0.2approx2500pC), 1% charge linearity, 0.2 pC charge resolution, and 0.1 ns timing resolution. Test results on ambient temperature dependence, channel isolation, and rate dependence also meet specifications.

High-speed charge-to-time converter ASIC for the Super-Kamiokande detector

International Nuclear Information System (INIS)

Nishino, H.; Awai, K.; Hayato, Y.; Nakayama, S.; Okumura, K.; Shiozawa, M.; Takeda, A.; Ishikawa, K.; Minegishi, A.; Arai, Y.

2009-01-01

A new application-specific integrated circuit (ASIC), the high-speed charge-to-time converter (QTC) IWATSU CLC101, provides three channels, each consisting of preamplifier, discriminator, low-pass filter, and charge integration circuitry, optimized for the waveform of a photomultiplier tube (PMT). This ASIC detects PMT signals using individual built-in discriminators and drives output timing signals whose width represents the integrated charge of the PMT signal. Combined with external input circuits composed of passive elements, the QTC provides full analog signal processing for the detector's PMTs, ready for further processing by time-to-digital converters (TDCs). High-rate (>1MHz) signal processing is achieved by short-charge-conversion-time and baseline-restoration circuits. Wide-range charge measurements are enabled by offering three gain ranges while maintaining a short cycle time. QTC chip test results show good analog performance, with efficient detection for a single photoelectron signal, four orders of magnitude dynamic range (0.3mV∼3V; 0.2∼2500pC), 1% charge linearity, 0.2 pC charge resolution, and 0.1 ns timing resolution. Test results on ambient temperature dependence, channel isolation, and rate dependence also meet specifications.

High-speed Imaging of Global Surface Temperature Distributions on Hypersonic Ballistic-Range Projectiles

Science.gov (United States)

Wilder, Michael C.; Reda, Daniel C.

2004-01-01

The NASA-Ames ballistic range provides a unique capability for aerothermodynamic testing of configurations in hypersonic, real-gas, free-flight environments. The facility can closely simulate conditions at any point along practically any trajectory of interest experienced by a spacecraft entering an atmosphere. Sub-scale models of blunt atmospheric entry vehicles are accelerated by a two-stage light-gas gun to speeds as high as 20 times the speed of sound to fly ballistic trajectories through an 24 m long vacuum-rated test section. The test-section pressure (effective altitude), the launch velocity of the model (flight Mach number), and the test-section working gas (planetary atmosphere) are independently variable. The model travels at hypersonic speeds through a quiescent test gas, creating a strong bow-shock wave and real-gas effects that closely match conditions achieved during actual atmospheric entry. The challenge with ballistic range experiments is to obtain quantitative surface measurements from a model traveling at hypersonic speeds. The models are relatively small (less than 3.8 cm in diameter), which limits the spatial resolution possible with surface mounted sensors. Furthermore, since the model is in flight, surface-mounted sensors require some form of on-board telemetry, which must survive the massive acceleration loads experienced during launch (up to 500,000 gravities). Finally, the model and any on-board instrumentation will be destroyed at the terminal wall of the range. For these reasons, optical measurement techniques are the most practical means of acquiring data. High-speed thermal imaging has been employed in the Ames ballistic range to measure global surface temperature distributions and to visualize the onset of transition to turbulent-flow on the forward regions of hypersonic blunt bodies. Both visible wavelength and infrared high-speed cameras are in use. The visible wavelength cameras are intensified CCD imagers capable of integration

UW VLSI chip tester

Science.gov (United States)

McKenzie, Neil

1989-12-01

We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

Investigation of High-Speed Cryogenic Machining Based on Finite Element Approach

Directory of Open Access Journals (Sweden)

Pooyan Vahidi Pashaki

Full Text Available Abstract The simulation of cryogenic machining process because of using a three-dimensional model and high process duration time in the finite element method, have been studied rarely. In this study, to overcome this limitation, a 2.5D finite element model using the commercial finite element software ABAQUS has been developed for the cryogenic machining process and by considering more realistic assumptions, the chip formation procedure investigated. In the proposed method, the liquid nitrogen has been used as a coolant. At the modeling of friction during the interaction of tools - chip, the Coulomb law has been used. In order to simulate the behavior of plasticity and failure criterion, Johnson-Cook model was used, and unlike previous investigations, thermal and mechanical properties of materials as a function of temperature were applied to the software. After examining accuracy of the model with present experimental data, the effect of parameters such as rake angle and the cutting speed as well as dry machining of aluminum alloy by the use of coupled dynamic temperature solution has been studied. Results indicated that at the cutting velocity of 10 m/s, cryogenic cooling has caused into decreasing 60 percent of tools temperature in comparison with the dry cooling. Furthermore, a chip which has been made by cryogenic machining were connected and without fracture in contrast to dry machining.

A low power high speed radiation hard serializer for High Energy Physics experiments

CERN Document Server

AUTHOR|(CDS)2080243; Marchioro, Alessandro; Ottavi, Marco

This Ph.D. thesis focuses on the development and the characterization of novel solutions for electronic systems for high-speed data transmission in extremely high radio-active environment (e.g. high energy physics application). The text proposes two alternative full-custom solutions for a fundamental enabling block for a lowpower serial data transmission system, the serializer. This block will find place in a future transceiver conceived for the future upgraded phase of the Large Hadron Collider, or LHC, at CERN. The first solution proposed, called “triple module redundancy”, is based on hardware redundancy, a well-known solution, to obtain protection against the temporary malfunctioning induced by radiation. In the second case a new architecture, called “code protected”, is proposed. This architecture takes advantage of the error correction code present in the data word to obtain radiation robustness on data and some parts of the control logic and to further reduce the power consumption. A test chip ...

FPGA Flash Memory High Speed Data Acquisition

Science.gov (United States)

Gonzalez, April

2013-01-01

The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

Source-synchronous networks-on-chip circuit and architectural interconnect modeling

CERN Document Server

Mandal, Ayan; Mahapatra, Rabi

2014-01-01

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks.  The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized.  Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.   • Describes novel methods for high-speed network-on-chip (NoC) design; • Enables readers to understand NoC design from both circuit and architectural levels; • Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; • Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.

Development of a Metal Cutting Tool Fase in Order to Create the Conditions of Ringed Chips Wrapping

Science.gov (United States)

Korchuganova, M.; Syrbakov, A.; Chernysheva, T.; Ivanov, G.; Korchuganov, M.

2016-08-01

When processing ductile metals with high cutting speed, there is a need to take additional measures for a comfortable and safe formation and removal of chips. In the conditions of large-scale manufacture, it is recommended to produce flow chips in the form of short fragments, while in the conditions of small-lot and single-piece manufacture, it is reasonable to wrap the chips spirally with a rather small turn radius. Such way of chips formation reduces the time of its removal from the working area as well as facilitates its transportation and processing. In order to solve the problem of chip wrapping and breakage, almost all modern manufacturers of tools with replaceable many-sided plates (RMSP) followed the way of complication of tool faces and determination of the areas of effective chip breaking. On the one hand, the suggested solution turns out to be effective; however, as showed the analysis of recommended cutting modes for complex forms of RMSP made by leading manufacturers, they all correspond to the definite cross section of the cut-layer S/t=0.1.

Level-1 Data Driver Card - A high bandwidth radiation tolerant aggregator board for detectors

CERN Document Server

Gkountoumis, Panagiotis; The ATLAS collaboration

2017-01-01

The Level-1 Data Driver Card (L1DDC) was designed for the needs of the future upgrades of the innermost stations of the ATLAS end-cap muon spectrometer. The L1DDC is a high speed aggregator board capable of communicating with multiple front-end electronic boards. It collects the Level-1 data along with monitoring data and transmits them to a network interface through bidirectional and/or unidirectional fiber links at 4.8 Gbps each. In addition, the L1DDC board distributes trigger, time and configuration data coming from the network interface to the front-end boards. The L1DDC is fully compatible with the Phase II upgrade where the trigger rate is expected to reach the 1 MHz. Three different types of L1DDC boards will be fabricated handling up to 10.080 Gbps of user data. It consist of custom made radiation tolerant ASICs: the GigaBit Transceiver (GBTx), the FEAST DC-DC converter, the Slow Control Adapter (SCA), and the Versatile Tranceivers (VTRX) and transmitters (VTTX). The overall scheme of the data acquis...

Effect of osmotic dehydration and vacuum-frying parameters to produce high-quality mango chips.

Science.gov (United States)

Nunes, Yolanda; Moreira, Rosana G

2009-09-01

Mango (Mangifera indica L.) is a fruit rich in flavor and nutritional values, which is an excellent candidate for producing chips. The objective of this study was to develop high-quality mango chips using vacuum frying. Mango ("Tommy Atkins") slices were pretreated with different maltodextrin concentrations (40, 50, and 65, w/v), osmotic dehydration times (45, 60, and 70 min), and solution temperatures (22 and 40 degrees C). Pretreated slices were vacuum fried at 120, 130, and 138 degrees C and product quality attributes (oil content, texture, color, carotenoid content) determined. The effect of frying temperatures at optimum osmotic dehydration times (65 [w/v] at 40 degrees C) was assessed. All samples were acceptable (scores > 5) to consumer panelists. The best mango chips were those pretreated with 65 (w/v) concentration for 60 min and vacuum fried at 120 degrees C. Mango chips under atmospheric frying had less carotenoid retention (32%) than those under vacuum frying (up to 65%). These results may help further optimize vacuum-frying processing of high-quality fruit-based snacks.

Primer printed circuit boards

CERN Document Server

Argyle, Andrew

2009-01-01

Step-by-step instructions for making your own PCBs at home. Making your own printed circuit board (PCB) might seem a daunting task, but once you master the steps, it's easy to attain professional-looking results. Printed circuit boards, which connect chips and other components, are what make almost all modern electronic devices possible. PCBs are made from sheets of fiberglass clad with copper, usually in multiplelayers. Cut a computer motherboard in two, for instance, and you'll often see five or more differently patterned layers. Making boards at home is relatively easy

A pipeline of associative memory boards for track finding

CERN Document Server

Annovi, A; Bardi, A; Carosi, R; Dell'Orso, Mauro; Giannetti, P; Iannaccone, G; Morsani, F; Pietri, M; Varotto, G

2000-01-01

We present a pipeline of associative memory boards for track finding, which satisfies the requirements of level two triggers of the next LHC experiments. With respect to previous realizations, the pipelined architecture warrants full scalability of the memory bank, increased bandwidth (by one order of magnitude), increased number of detector layers (by a factor 2). Each associative memory board consists of four smaller boards, each containing 32 programmable associative memory chips, implemented with low-cost commercial FPGA. FPGA programming has been optimized for maximum efficiency in terms of pattern density and PCB design has been optimized in terms of modularity and FPGA chip density. A complete AM board has been successfully tested at 40 MHz, and can contain 6.6x10//3 particle trajectories. 7 Refs.

FASTBUS Standard Routines implementation for Fermilab embedded processor boards

International Nuclear Information System (INIS)

Pangburn, J.; Patrick, J.; Kent, S.; Oleynik, G.; Pordes, R.; Votava, M.; Heyes, G.; Watson, W.A. III

1992-10-01

In collaboration with CEBAF, Fermilab's Online Support Department and the CDF experiment have produced a new implementation of the IEEE FASTBUS Standard Routines for two embedded processor FASTBUS boards: the Fermilab Smart Crate Controller (FSCC) and the FASTBUS Readout Controller (FRC). Features of this implementation include: portability (to other embedded processor boards), remote source-level debugging, high speed, optional generation of very high-speed code for readout applications, and built-in Sun RPC support for execution of FASTBUS transactions and lists over the network

A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

International Nuclear Information System (INIS)

Lattuca, A.; Mazza, G.; Rinella, G. Aglieri; Cavicchioli, C.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kofarago, M.; Kugathasan, T.; Chanlek, N.; Collu, A.; Degerli, Y.; Flouzat, C.; Guilloux, F.; Dorokhov, A.; Gajanana, D.; Gao, C.; Kim, D.; Kwon, Y.

2016-01-01

This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented

A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

Science.gov (United States)

Lattuca, A.; Mazza, G.; Aglieri Rinella, G.; Cavicchioli, C.; Chanlek, N.; Collu, A.; Degerli, Y.; Dorokhov, A.; Flouzat, C.; Gajanana, D.; Gao, C.; Guilloux, F.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kim, D.; Kofarago, M.; Kugathasan, T.; Kwon, Y.; Mager, M.; Sielewicz, K. Marek; Marin Tobon, C. Augusto; Marras, D.; Martinengo, P.; Mugnier, H.; Musa, L.; Pham, T. Hung; Puggioni, C.; Reidt, F.; Riedler, P.; Rousset, J.; Siddhanta, S.; Snoeys, W.; Song, M.; Usai, G.; Van Hoorne, J. Willem; Yang, P.

2016-01-01

This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.

Using a high-speed movie camera to evaluate slice dropping in clinical image interpretation with stack mode viewers.

OpenAIRE

Yakami, Masahiro; Yamamoto, Akira; Yanagisawa, Morio; Sekiguchi, Hiroyuki; Kubo, Takeshi; Togashi, Kaori

2013-01-01

The purpose of this study is to verify objectively the rate of slice omission during paging on picture archiving and communication system (PACS) viewers by recording the images shown on the computer displays of these viewers with a high-speed movie camera. This study was approved by the institutional review board. A sequential number from 1 to 250 was superimposed on each slice of a series of clinical Digital Imaging and Communication in Medicine (DICOM) data. The slices were displayed using ...

Cost-effective, compact and high-speed integrable multi-mode interference modulator

NARCIS (Netherlands)

Lenstra, Daan; Yao, Weiming; Cardarelli, Simone; Mink, Jan

2017-01-01

Theoretical analysis of the modulation performance of this wave-guide device shows great potential when combined with a single-mode laser on a monolithic optical chip. On the basis of the reversed-bias electro-optic effect, modulation speeds surmounting 25 Gbit/s with 10 dB extinction ratio are

Analysis of Microstructure and Chip Formation When Machining Ti-6Al-4V

Directory of Open Access Journals (Sweden)

Islam Shyha

2018-03-01

Full Text Available Microstructure and chip formation were evaluated during the step shoulder down-milling of Ti-6Al-4V using a water-miscible vegetable oil-based cutting fluid. Experiments were conducted using the Cut-list fluid supply system previous developed by the authors and a conventional cutting fluid supply system. A thin plastically deformed layer below the machined surface was observed during the metallurgical investigation of the surfaces produced using both systems. Despite noticeable reductions in cutting fluid consumption achieved by Cut-list, no significant disparity was found in microstructural damage. The microstructure of the machined surfaces was strongly affected by cutting speed and fluid flow rate with a discontinuous serrated chip being the principal type. However, increases in cutting fluid flow rate associated with increased cutting speed significantly changed chip morphology where average distance between chip segments increased with cutting speed. Cut-list produced smaller saw-tooth height and larger segmented width, while the transition from aperiodic to periodic serrated chip formation was governed by cutting speed and feed rate. Chip segmentation frequency and shear angle were also sensitive to cutting speed.

Application of Fabry-Perot velocimeter to high-speed experiments

International Nuclear Information System (INIS)

Chaw, H.H.; McMillan, C.F.; Osher, J.E.

1988-01-01

The Fabry-Perot (F-P) velocimeter is a useful instrument for measuring the velocity of objects at speeds ranging from fractions of a kilometer per second to a few tens of kilometers per second and up. Because of its immunity to electromagnetic interference and its velocity resolution, it has become the prime diagnostic tool in our electric-gun facility. Examples of its application to high speed experiments are discussed, including: electric-gun flyer studies, spallation of materials under high-speed impact, momentum-transfer studies, pressure pulse created by high-velocity impact, and detonation-wave studies in high-explosive experiments

Local structure of metallic chips examined by X-ray microdiffraction

International Nuclear Information System (INIS)

Saksl, K.; Rokicki, P.; Siemers, C.; Ostroushko, D.; Bednarčík, J.; Rütt, U.

2013-01-01

Highlights: •We present a detailed microstructure and phase analysis of chips produced by cutting. •3D analysis proved mixed nature of shear bands propagation to the material. •We examine phase composition of the chips by focused X-ray beam. •Crystallites in segment and shear band change their orientation up to 10°. -- Abstract: Nickel-base alloys are used in high-temperature applications whenever steels or titanium alloys cannot be applied anymore. This class of alloys is furthermore used in low-temperature applications in the oil or gas industry in case the corrosion resistance of stainless steels in related liquid media is not sufficient and titanium alloys would be too expensive. Nickel-base alloys, however, due to their high strength and toughness can be machined only at low cutting speeds as otherwise poor surface quality and enhanced tool wear is observed. From all aspects influencing the machinability, the chip formation mechanism is the key factor and only a thorough understanding of this mechanism can lead to an optimisation of the cutting process. In the current study, a detailed microstructure and phase analysis of Alloy 625 chips produced in an orthogonal cutting process at conventional cutting speeds is presented. Utilising hard monochromatic X-rays focused down to micrometre size, microstructural differences between distinct structural units of the chips, namely, the segments and shear bands, are investigated. Scanning cross sections of the chips with this small beam allowed us to determine misorientation between the segments and shear bands crystal lattices which as we found are not changing abruptly but continuously, with an absolute difference up to 10°

Local structure of metallic chips examined by X-ray microdiffraction

Energy Technology Data Exchange (ETDEWEB)

Saksl, K., E-mail: ksaksl@imr.saske.sk [Institut of Materials Research, Slovak Academy of Sciences, Watsonova 47, 040 01 Košice (Slovakia); Rokicki, P. [The Faculty of Mechanical Engineering and Aeronautics, Rzeszow University of Technology, Al. Powstancow Warszawy 12, 35-959 Rzeszow (Poland); Siemers, C. [Institut fuer Werkstoffe, Technische Universitaet Braunschweig, Langer Kamp 8, 38106 Braunschweig (Germany); Ostroushko, D. [Faculty of Metallurgy and Materials Engineering, VŠB – Technical University of Ostrava, 17.listopadu 15, 708 33 Ostrava (Czech Republic); Bednarčík, J.; Rütt, U. [HASYLAB at DESY, Notkestr. 85, D-22607 Hamburg (Germany)

2013-12-25

Highlights: •We present a detailed microstructure and phase analysis of chips produced by cutting. •3D analysis proved mixed nature of shear bands propagation to the material. •We examine phase composition of the chips by focused X-ray beam. •Crystallites in segment and shear band change their orientation up to 10°. -- Abstract: Nickel-base alloys are used in high-temperature applications whenever steels or titanium alloys cannot be applied anymore. This class of alloys is furthermore used in low-temperature applications in the oil or gas industry in case the corrosion resistance of stainless steels in related liquid media is not sufficient and titanium alloys would be too expensive. Nickel-base alloys, however, due to their high strength and toughness can be machined only at low cutting speeds as otherwise poor surface quality and enhanced tool wear is observed. From all aspects influencing the machinability, the chip formation mechanism is the key factor and only a thorough understanding of this mechanism can lead to an optimisation of the cutting process. In the current study, a detailed microstructure and phase analysis of Alloy 625 chips produced in an orthogonal cutting process at conventional cutting speeds is presented. Utilising hard monochromatic X-rays focused down to micrometre size, microstructural differences between distinct structural units of the chips, namely, the segments and shear bands, are investigated. Scanning cross sections of the chips with this small beam allowed us to determine misorientation between the segments and shear bands crystal lattices which as we found are not changing abruptly but continuously, with an absolute difference up to 10°.

Retrofit device to improve vapor compression cooling system performance by dynamic blower speed modulation

Science.gov (United States)

Roth, Robert Paul; Hahn, David C.; Scaringe, Robert P.

2015-12-08

A device and method are provided to improve performance of a vapor compression system using a retrofittable control board to start up the vapor compression system with the evaporator blower initially set to a high speed. A baseline evaporator operating temperature with the evaporator blower operating at the high speed is recorded, and then the device detects if a predetermined acceptable change in evaporator temperature has occurred. The evaporator blower speed is reduced from the initially set high speed as long as there is only a negligible change in the measured evaporator temperature and therefore a negligible difference in the compressor's power consumption so as to obtain a net increase in the Coefficient of Performance.

Development of 40 channel waveform sampling CMOS ASIC board for Positron Emission Tomography

International Nuclear Information System (INIS)

Shimazoe, Kenji; Yeol, Yeom-Jung; Minamikawa, Yasuhiro; Tomida, Yuki; Takahashi, Hiroyuki; Fujita, Kaoru; Nakazawa, Masaharu; Murayama, Hideo

2007-01-01

We have designed and fabricated 10 channel/6-bit waveform sampling ASICs using ROHM 0.35 μm CMOS technology. This chip was designed for GSO-APD γ-ray detector and provides a function of 'waveform recording' at a sampling frequency of 100 MHz. This chip has 10 channel inputs and each channel has preamp/variable gain amplifier/6-bit folding ADC. The folding ADC greatly reduces the number of comparators and the power consumption of the chip. This chip provides a full function of recording a transient behavior of detector charge signals for each pulse. Self-trigger function is equipped with the system and this will enable simultaneous record of all input waveforms. Each channel has 64 words FIFO where each waveform data are stored. Stored data are converted to serial data and passed to an FPGA where we can implement a detailed signal processing. This chip is operated at 3.3 V and the power consumption is 1.2 W/chip. We have developed a data acquisition board using four bare chips. This board has 40 input channels and we plan to use this board for APD-based DOI-PET detector system which utilizes several different crystals to recognize depth positions by the difference in their decay times

High-performance, scalable optical network-on-chip architectures

Science.gov (United States)

Tan, Xianfang

The rapid advance of technology enables a large number of processing cores to be integrated into a single chip which is called a Chip Multiprocessor (CMP) or a Multiprocessor System-on-Chip (MPSoC) design. The on-chip interconnection network, which is the communication infrastructure for these processing cores, plays a central role in a many-core system. With the continuously increasing complexity of many-core systems, traditional metallic wired electronic networks-on-chip (NoC) became a bottleneck because of the unbearable latency in data transmission and extremely high energy consumption on chip. Optical networks-on-chip (ONoC) has been proposed as a promising alternative paradigm for electronic NoC with the benefits of optical signaling communication such as extremely high bandwidth, negligible latency, and low power consumption. This dissertation focus on the design of high-performance and scalable ONoC architectures and the contributions are highlighted as follow: 1. A micro-ring resonator (MRR)-based Generic Wavelength-routed Optical Router (GWOR) is proposed. A method for developing any sized GWOR is introduced. GWOR is a scalable non-blocking ONoC architecture with simple structure, low cost and high power efficiency compared to existing ONoC designs. 2. To expand the bandwidth and improve the fault tolerance of the GWOR, a redundant GWOR architecture is designed by cascading different type of GWORs into one network. 3. The redundant GWOR built with MRR-based comb switches is proposed. Comb switches can expand the bandwidth while keep the topology of GWOR unchanged by replacing the general MRRs with comb switches. 4. A butterfly fat tree (BFT)-based hybrid optoelectronic NoC (HONoC) architecture is developed in which GWORs are used for global communication and electronic routers are used for local communication. The proposed HONoC uses less numbers of electronic routers and links than its counterpart of electronic BFT-based NoC. It takes the advantages of

Research on Dynamic Torque Measurement of High Speed Rotating Axis Based on Whole Optical Fiber Technique

Energy Technology Data Exchange (ETDEWEB)

Ma, H P; Jin, Y Q; Ha, Y W; Liu, L H [Department of Automatic Measurement and Control, Harbin Institute of Technology, PO Box 305, Harbin, 150001 (China)

2006-10-15

Non-contact torque measurement system of fiber grating is proposed in this paper. It is used for the dynamic torque measurement of the rotating axis in the spaceflight servo system. Optical fiber is used as sensing probe with high sensitivity, anti-electromagnetic interference, resistance to high temperature and corrosion. It is suitable to apply in a bad environment. Signals are processed by digital circuit and Single Chip Microcomputer. This project can realize super speed dynamic measurement and it is the first time to apply the project in the spaceflight system.

Research on Dynamic Torque Measurement of High Speed Rotating Axis Based on Whole Optical Fiber Technique

Science.gov (United States)

Ma, H. P.; Jin, Y. Q.; Ha, Y. W.; Liu, L. H.

2006-10-01

Non-contact torque measurement system of fiber grating is proposed in this paper. It is used for the dynamic torque measurement of the rotating axis in the spaceflight servo system. Optical fiber is used as sensing probe with high sensitivity, anti-electromagnetic interference, resistance to high temperature and corrosion. It is suitable to apply in a bad environment. Signals are processed by digital circuit and Single Chip Microcomputer. This project can realize super speed dynamic measurement and it is the first time to apply the project in the spaceflight system.

Research on Dynamic Torque Measurement of High Speed Rotating Axis Based on Whole Optical Fiber Technique

International Nuclear Information System (INIS)

Ma, H P; Jin, Y Q; Ha, Y W; Liu, L H

2006-01-01

Non-contact torque measurement system of fiber grating is proposed in this paper. It is used for the dynamic torque measurement of the rotating axis in the spaceflight servo system. Optical fiber is used as sensing probe with high sensitivity, anti-electromagnetic interference, resistance to high temperature and corrosion. It is suitable to apply in a bad environment. Signals are processed by digital circuit and Single Chip Microcomputer. This project can realize super speed dynamic measurement and it is the first time to apply the project in the spaceflight system

Oxide-confined 2D VCSEL arrays for high-density inter/intra-chip interconnects

Science.gov (United States)

King, Roger; Michalzik, Rainer; Jung, Christian; Grabherr, Martin; Eberhard, Franz; Jaeger, Roland; Schnitzer, Peter; Ebeling, Karl J.

1998-04-01

We have designed and fabricated 4 X 8 vertical-cavity surface-emitting laser (VCSEL) arrays intended to be used as transmitters in short-distance parallel optical interconnects. In order to meet the requirements of 2D, high-speed optical links, each of the 32 laser diodes is supplied with two individual top contacts. The metallization scheme allows flip-chip mounting of the array modules junction-side down on silicon complementary metal oxide semiconductor (CMOS) chips. The optical and electrical characteristics across the arrays with device pitch of 250 micrometers are quite homogeneous. Arrays with 3 micrometers , 6 micrometers and 10 micrometers active diameter lasers have been investigated. The small devices show threshold currents of 600 (mu) A, single-mode output powers as high as 3 mW and maximum wavelength deviations of only 3 nm. The driving characteristics of all arrays are fully compatible to advanced 3.3 V CMOS technology. Using these arrays, we have measured small-signal modulation bandwidths exceeding 10 GHz and transmitted pseudo random data at 8 Gbit/s channel over 500 m graded index multimode fiber. This corresponds to a data transmission rate of 256 Gbit/s per array of 1 X 2 mm2 footprint area.

Sea otter dental enamel is highly resistant to chipping due to its microstructure.

Science.gov (United States)

Ziscovici, Charles; Lucas, Peter W; Constantino, Paul J; Bromage, Timothy G; van Casteren, Adam

2014-10-01

Dental enamel is prone to damage by chipping with large hard objects at forces that depend on chip size and enamel toughness. Experiments on modern human teeth have suggested that some ante-mortem chips on fossil hominin enamel were produced by bite forces near physiological maxima. Here, we show that equivalent chips in sea otter enamel require even higher forces than human enamel. Increased fracture resistance correlates with more intense enamel prism decussation, often seen also in some fossil hominins. It is possible therefore that enamel chips in such hominins may have formed at even greater forces than currently envisaged. © 2014 The Author(s) Published by the Royal Society. All rights reserved.

Analysis of the resistive network in a bio-inspired CMOS vision chip

Science.gov (United States)

Kong, Jae-Sung; Sung, Dong-Kyu; Hyun, Hyo-Young; Shin, Jang-Kyoo

2007-12-01

CMOS vision chips for edge detection based on a resistive circuit have recently been developed. These chips help develop neuromorphic systems with a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends dominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the MOSFET for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160×120 CMOS vision chips have been fabricated by using a standard CMOS technology. The experimental results have been nicely matched with our prediction.

Fully Automated On-Chip Imaging Flow Cytometry System with Disposable Contamination-Free Plastic Re-Cultivation Chip

Directory of Open Access Journals (Sweden)

Tomoyuki Kaneko

2011-06-01

Full Text Available We have developed a novel imaging cytometry system using a poly(methyl methacrylate (PMMA based microfluidic chip. The system was contamination-free, because sample suspensions contacted only with a flammable PMMA chip and no other component of the system. The transparency and low-fluorescence of PMMA was suitable for microscopic imaging of cells flowing through microchannels on the chip. Sample particles flowing through microchannels on the chip were discriminated by an image-recognition unit with a high-speed camera in real time at the rate of 200 event/s, e.g., microparticles 2.5 μm and 3.0 μm in diameter were differentiated with an error rate of less than 2%. Desired cells were separated automatically from other cells by electrophoretic or dielectrophoretic force one by one with a separation efficiency of 90%. Cells in suspension with fluorescent dye were separated using the same kind of microfluidic chip. Sample of 5 μL with 1 × 106 particle/mL was processed within 40 min. Separated cells could be cultured on the microfluidic chip without contamination. The whole operation of sample handling was automated using 3D micropipetting system. These results showed that the novel imaging flow cytometry system is practically applicable for biological research and clinical diagnostics.

Experimental Study of Low Speed Sensorless Control of PMSM Drive Using High Frequency Signal Injection

Directory of Open Access Journals (Sweden)

Jyoti Agrawal

2016-01-01

Full Text Available Conventional techniques for sensorless control of permanent magnet synchronous motor drive (PMSM, which requires information on rotor position, are reviewed, and recent developments in this area are introduced in this paper along with their inherent advantages and drawbacks. The paper presents an improved method for sensorless speed control of PMSM drive with emphasis placed on signal injection method. This signal injection method examines the control performance of sensorless PMSM drive by injecting signal externally and thereby sensing the rotor position. The main objective of this drive system is to have speed control at standstill and low speed regions. Several tests are carried out to demonstrate the ability of proposed models at different operating conditions with the help of simulation results in Matlab/Simulink environment. Simulation results confirm that the proposed sensorless control approach of PMSM can achieve high performance at standstill and low speeds but not at very high speeds. An experimental setup is implemented using a 1HP surface mounted (SM PMSM and DsPICDEM^TM MCHV-2 development board, to check the validity of simulation results.

Application of high voltage electric field (HVEF) drying technology in potato chips

International Nuclear Information System (INIS)

Bai, Yaxiang; Shi, Hua; Yang, Yaxin

2013-01-01

In order to improve the drying efficiency and qualities of vegetable by high voltage electric field (HVEF), potato chips as a representative of vegetable was dried using a high voltage electric drying systems at 20°C. The shrinkage rate, water absorption and rehydration ratio of dried potato chips were measured. The results indicated that the drying rate of potato chips was significantly improved in the high voltage electric drying systems. The shrinkage rate of potato chips dried by high voltage electric field was 1.1% lower than that by oven drying method. And the rehydration rate of high voltage electric field was 24.6% higher than that by oven drying method. High voltage electric field drying is very advantageous and can be used as a substitute for traditional drying method.

Influence of long-wavelength track irregularities on the motion of a high-speed train

Science.gov (United States)

Hung, C. F.; Hsu, W. L.

2018-01-01

Vertical track irregularities over viaducts in high-speed rail systems could be possibly caused by concrete creep if pre-stressed concrete bridges are used. For bridge spans that are almost uniformly distributed, track irregularity exhibits a near-regular wave profile that excites car bodies as a high-speed train moves over the bridge system. A long-wavelength irregularity induces low-frequency excitation that may be close to the natural frequencies of the train suspension system, thereby causing significant vibration of the car body. This paper investigates the relationship between the levels of car vibration, bridge vibration, track irregularity, and the train speed. First, this study investigates the vibration levels of a high-speed train and bridge system using 3D finite-element (FE) transient dynamic analysis, before and after adjustment of vertical track irregularities by means of installing shimming plates under rail pads. The analysis models are validated by in situ measurements and on-board measurement. Parametric studies of car body vibration and bridge vibration under three different levels of track irregularity at five train speeds and over two bridge span lengths are conducted using the FE model. Finally, a discontinuous shimming pattern is proposed to avoid vehicle suspension resonance.

Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network.

Science.gov (United States)

Lee, Dasheng

2008-12-02

In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV) measurement. The energy harvesting wireless sensor network (WSN) was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR) is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an energy efficient

Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network

Science.gov (United States)

Lee, Dasheng

2008-01-01

In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV) measurement. The energy harvesting wireless sensor network (WSN) was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR) is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an energy efficient

Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network

Directory of Open Access Journals (Sweden)

Dasheng Lee

2008-12-01

Full Text Available In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV measurement. The energy harvesting wireless sensor network (WSN was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an

Single-mode glass waveguide technology for optical interchip communication on board level

Science.gov (United States)

Brusberg, Lars; Neitz, Marcel; Schröder, Henning

2012-01-01

The large bandwidth demand in long-distance telecom networks lead to single-mode fiber interconnects as result of low dispersion, low loss and dense wavelength multiplexing possibilities. In contrast, multi-mode interconnects are suitable for much shorter lengths up to 300 meters and are promising for optical links between racks and on board level. Active optical cables based on multi-mode fiber links are at the market and research in multi-mode waveguide integration on board level is still going on. Compared to multi-mode, a single-mode waveguide has much more integration potential because of core diameters of around 20% of a multi-mode waveguide by a much larger bandwidth. But light coupling in single-mode waveguides is much more challenging because of lower coupling tolerances. Together with the silicon photonics technology, a single-mode waveguide technology on board-level will be the straight forward development goal for chip-to-chip optical interconnects integration. Such a hybrid packaging platform providing 3D optical single-mode links bridges the gap between novel photonic integrated circuits and the glass fiber based long-distance telecom networks. Following we introduce our 3D photonic packaging approach based on thin glass substrates with planar integrated optical single-mode waveguides for fiber-to-chip and chip-to-chip interconnects. This novel packaging approach merges micro-system packaging and glass integrated optics. It consists of a thin glass substrate with planar integrated singlemode waveguide circuits, optical mirrors and lenses providing an integration platform for photonic IC assembly and optical fiber interconnect. Thin glass is commercially available in panel and wafer formats and characterizes excellent optical and high-frequency properties. That makes it perfect for microsystem packaging. The paper presents recent results in single-mode waveguide technology on wafer level and waveguide characterization. Furthermore the integration in a

A new high speed, Ultrascale+ based board for the ATLAS jet calorimeter trigger system

CERN Document Server

Rocco, Elena; The ATLAS collaboration

2018-01-01

To cope with the enhanced luminosity at the Large Hadron Collider (LHC) in 2021, the ATLAS collaboration is planning a major detector upgrade. As a part of this, the Level 1 trigger based on calorimeter data will be upgraded to exploit the fine granularity readout using a new system of Feature EXtractors (FEX), which each reconstruct different physics objects for the trigger selection. The jet FEX (jFEX) system is conceived to provide jet identification (including large area jets) and measurements of global variables within a latency budget of less then 400ns. It consists of 6 modules. A single jFEX module is an ATCA board with 4 large FPGAs of the Xilinx Ultrascale+ family, that can digest a total input data rate of ~3.6 Tb/s using up to 120 Multi Gigabit Transceiver (MGT), 24 electrical optical devices, board control and power on the mezzanines to allow flexibility in upgrading controls functions and components without affecting the main board. The 24-layers stack-up was carefully designed to preserve the s...

TECHNICAL APPROACH TO THE EFFICIENCY DETERMINATION OF HIGH-SPEED TRAINS

Directory of Open Access Journals (Sweden)

A. V. Momot

2013-11-01

Full Text Available Purpose. The aim of this article is to develop an approach and formulate arrangements concerning the definition of the economic appropriateness of high-speed movement implementation in Ukraine. Methodology. The economic feasibility for appropriateness of high-speed movement organization in Ukraine is an investment project, which involves step-by-step money investment into the construction. It will let get an annual profits from the passenger carriage. To solve such problems we use net present value, which UZ or newly created companies can get during the project realization and after its completion. Findings. Obtained studies can state the fact that the technical approach for full effectiveness definition of a construction and high-speed passenger trains service taking into account the cost of infrastructure, rolling stock, the impact of environmental factors, etc. was determined. Originality. We propose a scientific approach to determine the economic effectiveness of the construction and high-speed main lines service. It includes improved principles of defining the passenger traffic, the cost of high-speed rails construction, the number of rolling stock; optimizes income and expenditure calculations in the context of competitive advantages and the external factors impact on the company. A technical approach for the calculation of future traffic volumes along the high-speed line was improved. It differs essentially from the European one proposed by the French firm «SYSTRA», as it allows taking into account additional transit traffic through Ukraine. It helps to distribute the passengers on separate sections proportionally to the number of cities population, which are combined by high-speed main line, subject to the average population mobility, travel time and the coefficient that takes into account the frequency of additional passenger trips on a given section, depending on the purpose (business trip, transfer to a plane, recreation, etc

Silicon Chip-to-Chip Mode-Division Multiplexing

DEFF Research Database (Denmark)

Baumann, Jan Markus; Porto da Silva, Edson; Ding, Yunhong

2018-01-01

A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes.......A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes....

A new method for grain refinement in magnesium alloy: High speed extrusion machining

Energy Technology Data Exchange (ETDEWEB)

Liu, Yao, E-mail: liuyao@ustb.edu.cn [School of Mathematics and Physics, University of Science and Technology Beijing, Beijing 100083 (China); Cai, Songlin [China Electric Power Research Institute, State Grid Corporation of China, Beijing 100192 (China); Dai, Lanhong [State Key Laboratory of Nonlinear Mechanics, Institute of Mechanics, Chinese Academy of Science, Beijing 100190 (China)

2016-01-10

Magnesium alloys have received broad attentions in industry due to their competitive strength to density ratio, but the poor ductility and strength limit their wide range of applications as engineering materials. A novel severe plastic deformation (SPD) technique of high speed extrusion machining (HSEM) was used here. This method could improve the aforementioned disadvantages of magnesium alloys by one single processing step. In this work, systematic HSEM experiments with different chip thickness ratios were conducted for magnesium alloy AZ31B. The microstructure of the chips reveals that HSEM is an effective SPD method for attaining magnesium alloys with different grain sizes and textures. The magnesium alloy with bimodal grain size distribution has increased mechanical properties than initial sample. The electron backscatter diffraction (EBSD) analysis shows that the dynamic recrystallization (DRX) affects the grain refinement and resulting hardness in AZ31B. Based on the experimental observations, a new theoretical model is put forward to describe the effect of DRX on materials during HSEM. Compared with the experimental measurements, the theoretical model is effective to predict the mechanical property of materials after HSEM.

Design of light-small high-speed image data processing system

Science.gov (United States)

Yang, Jinbao; Feng, Xue; Li, Fei

2015-10-01

A light-small high speed image data processing system was designed in order to meet the request of image data processing in aerospace. System was constructed of FPGA, DSP and MCU (Micro-controller), implementing a video compress of 3 million pixels@15frames and real-time return of compressed image to the upper system. Programmable characteristic of FPGA, high performance image compress IC and configurable MCU were made best use to improve integration. Besides, hard-soft board design was introduced and PCB layout was optimized. At last, system achieved miniaturization, light-weight and fast heat dispersion. Experiments show that, system's multifunction was designed correctly and worked stably. In conclusion, system can be widely used in the area of light-small imaging.

Development of a high-speed single-photon pixellated detector for visible wavelengths

CERN Document Server

Mac Raighne, Aaron; Mathot, Serge; McPhate, Jason; Vallerga, John; Jarron, Pierre; Brownlee, Colin; O’Shea, Val

2009-01-01

We present the development of a high-speed, single-photon counting, Hybrid Photo Detector (HPD). The HPD consists of a vacuum tube, containing the detector assembly, sealed with a transparent optical input window. Photons incident on the photocathode eject a photoelectron into a large electric field, which accelerates the incident electron onto a silicon detector. The silicon detector is bump bonded to a Medipix readout chip. This set-up allows for the detection and readout of low incident photon intensities at rates that are otherwise unattainable with current camera technology. Reported is the fabrication of the camera that brings together a range of sophisticated design and fabrication techniques and the expected theoretical imaging performance. Applications to cellular and molecular microscopy are also described in which single-photon-counting abilities at high frame rates are crucial

Material constraints on high-speed design

Science.gov (United States)

Bucur, Diana; Militaru, Nicolae

2015-02-01

Current high-speed circuit designs with signal rates up to 100Gbps and above are implying constraints for dielectric and conductive materials and their dependence of frequency, for component elements and for production processes. The purpose of this paper is to highlight through various simulation results the frequency dependence of specific parameters like insertion and return loss, eye diagrams, group delay that are part of signal integrity analyses type. In low-power environment designs become more complex as the operation frequency increases. The need for new materials with spatial uniformity for dielectric constant is a need for higher data rates circuits. The fiber weave effect (FWE) will be analyzed through the eye diagram results for various dielectric materials in a differential signaling scheme given the fact that the FWE is a phenomenon that affects randomly the performance of the circuit on balanced/differential transmission lines which are typically characterized through the above mentioned approaches. Crosstalk between traces is also of concern due to propagated signals that have tight rise and fall times or due to high density of the boards. Criteria should be considered to achieve maximum performance of the designed system requiring critical electronic properties.

Wear evaluation of flank in burins of high speed steel modified with titanium ions

Science.gov (United States)

E Caballero, J.; V-Niño, E. D.

2017-12-01

This report shows the results obtained researching the flank wearing resistance performed by the high-speed steel (HSS) burins without any surface treatment (reference substrate) and others with surface treatment based on Titanium ions. The flank wearing was carried out by means of an industrial process by chip removal with repetitive tests of dry finished turning of AISI/SAE 1045 steel bars. The useful service life of the burins was evaluated according to ISO 3685:1993, and it was found that the burins treated with Titanium ions showed an increase in the flank wearing resistance with respect to the ones used as reference.

Optimized Signaling Method for High-Speed Transmission Channels with Higher Order Transfer Function

Science.gov (United States)

Ševčík, Břetislav; Brančík, Lubomír; Kubíček, Michal

2017-08-01

In this paper, the selected results from testing of optimized CMOS friendly signaling method for high-speed communications over cables and printed circuit boards (PCBs) are presented and discussed. The proposed signaling scheme uses modified concept of pulse width modulated (PWM) signal which enables to better equalize significant channel losses during data high-speed transmission. Thus, the very effective signaling method to overcome losses in transmission channels with higher order transfer function, typical for long cables and multilayer PCBs, is clearly analyzed in the time and frequency domain. Experimental results of the measurements include the performance comparison of conventional PWM scheme and clearly show the great potential of the modified signaling method for use in low power CMOS friendly equalization circuits, commonly considered in modern communication standards as PCI-Express, SATA or in Multi-gigabit SerDes interconnects.

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

Science.gov (United States)

Bartoldus, R.; Claus, R.; Garelli, N.; Herbst, R. T.; Huffer, M.; Iakovidis, G.; Iordanidou, K.; Kwan, K.; Kocian, M.; Lankford, A. J.; Moschovakos, P.; Nelson, A.; Ntekas, K.; Ruckman, L.; Russell, J.; Schernau, M.; Schlenker, S.; Su, D.; Valderanis, C.; Wittgen, M.; Yildiz, S. C.

2016-01-01

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run-2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources. Together with auxiliary memories, all these components form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for high speed input and output fiberoptic links and TTC allowed the full system of 320 input links from the 32 chambers to be processed by 6 COBs in one ATCA shelf. The full system was installed in September 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning for LHC Run 2.

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

International Nuclear Information System (INIS)

Bartoldus, R.; Claus, R.; Garelli, N.; Herbst, R.T.; Huffer, M.; Kocian, M.; Ruckman, L.; Russell, J.; Su, D.; Wittgen, M.; Iakovidis, G.; Iordanidou, K.; Moschovakos, P.; Ntekas, K.; Kwan, K.; Lankford, A.J.; Nelson, A.; Schernau, M.; Schlenker, S.; Valderanis, C.

2016-01-01

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run-2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources. Together with auxiliary memories, all these components form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for high speed input and output fiberoptic links and TTC allowed the full system of 320 input links from the 32 chambers to be processed by 6 COBs in one ATCA shelf. The full system was installed in September 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning for LHC Run 2

A High-Throughput, High-Accuracy System-Level Simulation Framework for System on Chips

Directory of Open Access Journals (Sweden)

Guanyi Sun

2011-01-01

Full Text Available Today's System-on-Chips (SoCs design is extremely challenging because it involves complicated design tradeoffs and heterogeneous design expertise. To explore the large solution space, system architects have to rely on system-level simulators to identify an optimized SoC architecture. In this paper, we propose a system-level simulation framework, System Performance Simulation Implementation Mechanism, or SPSIM. Based on SystemC TLM2.0, the framework consists of an executable SoC model, a simulation tool chain, and a modeling methodology. Compared with the large body of existing research in this area, this work is aimed at delivering a high simulation throughput and, at the same time, guaranteeing a high accuracy on real industrial applications. Integrating the leading TLM techniques, our simulator can attain a simulation speed that is not slower than that of the hardware execution by a factor of 35 on a set of real-world applications. SPSIM incorporates effective timing models, which can achieve a high accuracy after hardware-based calibration. Experimental results on a set of mobile applications proved that the difference between the simulated and measured results of timing performance is within 10%, which in the past can only be attained by cycle-accurate models.

Chip formation in turning S45C medium carbon steel in cryogenic conditions

Directory of Open Access Journals (Sweden)

Jaharah A. Ghani

2017-09-01

Full Text Available This paper presents the tribology issue regarding the chip formation in machining medium carbon steel (S45C using a coated and uncoated carbide tools. The machining parameters under investigation were cutting speed, feed rate, and depth of cut under dry and cryogenic cutting condition using coated and uncoated carbide tools. The chip shape was largely depended on the combination of machining parameters, especially at high depth of cut and feed rate; the favorable chip was produced. Larger value of shear angle results in smaller shear plane area that provides benefits of lower cutting force needed to shear off the chips and lower cutting temperature being generated during the machining process.

Establishing Relationship between Process Parameters and Temperature during High Speed End Milling of Soda Lime Glass

Science.gov (United States)

Nasima Bagum, Mst.; Konneh, Mohamed; Yeakub Ali, Mohammad

2018-01-01

In glass machining crack free surface is required in biomedical and optical industry. Ductile mode machining allows materials removal from brittle materials in a ductile manner rather than by brittle fracture. Although end milling is a versatile process, it has not been applied frequently for machining soda lime glass. Soda lime glass is a strain rate and temperature sensitive material; especially around glass transition temperature Tg, ductility increased and strength decreased. Hence, it is envisaged that the generated temperature by high-speed end milling (HSEM) could be brought close to the glass transition temperature, which promote ductile machining. In this research, the objective is to investigate the effect of high speed machining parameters on generated temperature. The cutting parameters were optimized to generate temperature around glass transition temperature of soda lime using response surface methodology (RSM). Result showed that the most influencing process parameter is feed rate followed by spindle speed and depth of cut to generate temperature. Confirmation test showed that combination of spindle speed 30,173 rpm, feed rate 13.2 mm/min and depth of cut 37.68 µm generate 635°C, hence ductile chip removal with machined surface Ra 0.358 µm was possible to achieve.

High-speed 1.3 -1.55 um InGaAs/InP PIN photodetector for microwave photonics

Science.gov (United States)

Kozyreva, O. A.; Solov'ev, Y. V.; Polukhin, I. S.; Mikhailov, A. K.; Mikhailovskiy, G. A.; Odnoblyudov, M. A.; Gareev, E. Z.; Kolodeznyi, E. S.; Novikov, I. I.; Karachinsky, L. Ya; Egorov, A. Yu; Bougrov, V. E.

2017-11-01

We have fabricated the 1.3-1.55 um PIN photodetector based on InGaAs/InP heterostructure. Measurement results of optical and electrical characteristics of PIN photodetector chip were the following: photoconductivity at 1550 nm was 0.65 A/W and internal capacitance was 0.025 pF. Microwave model of photodetector was developed and verified by measurements of scattering matrix. The implementation of broadband (up to 20 GHz) hybrid integrated matching and biasing circuit for high-speed photodetector is presented.

X-CHIP: an integrated platform for high-throughput protein crystallization and on-the-chip X-ray diffraction data collection

International Nuclear Information System (INIS)

Kisselman, Gera; Qiu, Wei; Romanov, Vladimir; Thompson, Christine M.; Lam, Robert; Battaile, Kevin P.; Pai, Emil F.; Chirgadze, Nickolay Y.

2011-01-01

The X-CHIP (X-ray Crystallography High-throughput Integrated Platform) is a novel microchip that has been developed to combine multiple steps of the crystallographic pipeline from crystallization to diffraction data collection on a single device to streamline the entire process. The X-CHIP (X-ray Crystallization High-throughput Integrated Platform) is a novel microchip that has been developed to combine multiple steps of the crystallographic pipeline from crystallization to diffraction data collection on a single device to streamline the entire process. The system has been designed for crystallization condition screening, visual crystal inspection, initial X-ray screening and data collection in a high-throughput fashion. X-ray diffraction data acquisition can be performed directly on-the-chip at room temperature using an in situ approach. The capabilities of the chip eliminate the necessity for manual crystal handling and cryoprotection of crystal samples, while allowing data collection from multiple crystals in the same drop. This technology would be especially beneficial for projects with large volumes of data, such as protein-complex studies and fragment-based screening. The platform employs hydrophilic and hydrophobic concentric ring surfaces on a miniature plate transparent to visible light and X-rays to create a well defined and stable microbatch crystallization environment. The results of crystallization and data-collection experiments demonstrate that high-quality well diffracting crystals can be grown and high-resolution diffraction data sets can be collected using this technology. Furthermore, the quality of a single-wavelength anomalous dispersion data set collected with the X-CHIP at room temperature was sufficient to generate interpretable electron-density maps. This technology is highly resource-efficient owing to the use of nanolitre-scale drop volumes. It does not require any modification for most in-house and synchrotron beamline systems and offers

X-CHIP: an integrated platform for high-throughput protein crystallization and on-the-chip X-ray diffraction data collection

Energy Technology Data Exchange (ETDEWEB)

Kisselman, Gera; Qiu, Wei; Romanov, Vladimir; Thompson, Christine M.; Lam, Robert [Ontario Cancer Institute, Princess Margaret Hospital, University Health Network, Toronto, Ontario M5G 2C4 (Canada); Battaile, Kevin P. [Argonne National Laboratory, Argonne, Illinois 60439 (United States); Pai, Emil F.; Chirgadze, Nickolay Y., E-mail: nchirgad@uhnresearch.ca [Ontario Cancer Institute, Princess Margaret Hospital, University Health Network, Toronto, Ontario M5G 2C4 (Canada); University of Toronto, Toronto, Ontario M5S 1A8 (Canada)

2011-06-01

The X-CHIP (X-ray Crystallography High-throughput Integrated Platform) is a novel microchip that has been developed to combine multiple steps of the crystallographic pipeline from crystallization to diffraction data collection on a single device to streamline the entire process. The X-CHIP (X-ray Crystallization High-throughput Integrated Platform) is a novel microchip that has been developed to combine multiple steps of the crystallographic pipeline from crystallization to diffraction data collection on a single device to streamline the entire process. The system has been designed for crystallization condition screening, visual crystal inspection, initial X-ray screening and data collection in a high-throughput fashion. X-ray diffraction data acquisition can be performed directly on-the-chip at room temperature using an in situ approach. The capabilities of the chip eliminate the necessity for manual crystal handling and cryoprotection of crystal samples, while allowing data collection from multiple crystals in the same drop. This technology would be especially beneficial for projects with large volumes of data, such as protein-complex studies and fragment-based screening. The platform employs hydrophilic and hydrophobic concentric ring surfaces on a miniature plate transparent to visible light and X-rays to create a well defined and stable microbatch crystallization environment. The results of crystallization and data-collection experiments demonstrate that high-quality well diffracting crystals can be grown and high-resolution diffraction data sets can be collected using this technology. Furthermore, the quality of a single-wavelength anomalous dispersion data set collected with the X-CHIP at room temperature was sufficient to generate interpretable electron-density maps. This technology is highly resource-efficient owing to the use of nanolitre-scale drop volumes. It does not require any modification for most in-house and synchrotron beamline systems and offers

A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

CERN Document Server

AUTHOR|(SzGeCERN)664042

2016-01-01

The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf thr...

A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

CERN Document Server

Claus, Richard; The ATLAS collaboration

2015-01-01

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf thro...

GaN-based integrated photonics chip with suspended LED and waveguide

Science.gov (United States)

Li, Xin; Wang, Yongjin; Hane, Kazuhiro; Shi, Zheng; Yan, Jiang

2018-05-01

We propose a GaN-based integrated photonics chip with suspended LED and straight waveguide with different geometric parameters. The integrated photonics chip is prepared by double-side process. Light transmission performance of the integrated chip verse current is quantitatively analyzed by capturing light transmitted to waveguide tip and BPM (beam propagation method) simulation. Reduction of the waveguide width from 8 μm to 4 μm results in an over linear reduction of the light output power while a doubling of the length from 250 μm to 500 μm only results in under linear decrease of the output power. Free-space data transmission with 80 Mbps random binary sequence of the integrated chip is capable of achieving high speed data transmission via visible light. This study provides a potential approach for GaN-based integrated photonics chip as micro light source and passive optical device in VLC (visible light communication).

A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

CERN Document Server

AUTHOR|(SzGeCERN)696050; Garelli, N.; Herbst, R.T.; Huffer, M.; Iakovidis, G.; Iordanidou, K.; Kwan, K.; Kocian, M.; Lankford, A.J.; Moschovakos, P.; Nelson, A.; Ntekas, K.; Ruckman, L.; Russell, J.; Schernau, M.; Schlenker, S.; Su, D.; Valderanis, C.; Wittgen, M.; Bartoldus, R.

2016-01-01

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambe...

A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

CERN Document Server

ATLAS CSC Collaboration; The ATLAS collaboration

2016-01-01

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgrade during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chamber...

Optimizing residence time, temperature and speed to improve TMP pulp properties and reduce energy

Energy Technology Data Exchange (ETDEWEB)

Sabourin, M.; Xu, E.; Cort, B.; Boileau, I.; Waller, A.

1997-04-01

The concept of reducing energy consumption in pulp mills by increasing the disc speed of refining has been established using single disc and double disc refiners in both pilot plant and mill applications. The RTS study evaluated in this paper reviews the effect of high-speed single disc refining coupled with shortdwell-high pressure retention conditions. Coupling these variables permitted evaluation of an optimum residence time, temperature and speed (RTS) operational window. The objective of the RTS conditions to sufficiently soften the wood chips through high temperature such that the fibre is more receptive to initial defiberization at high intensity. The improved pulp from the primary refiner at high intensity could potentially demonstrate improvements in physical pulp properties at a reduced specific energy requirement. The spruce/fir RTS-TMP described here required significantly less specific energy and produced TMP with slightly improved strength properties and equivalent optical properties compared to conventional TMP pulp. Studies on the radiate pine furnish indicated that the physical pulp property/specific energy relationships could be adjusted by manipulating the residence time. 4 refs., 10 tabs., 10 figs.

High-speed AC motors

Energy Technology Data Exchange (ETDEWEB)

Jokinen, T.; Arkkio, A. [Helsinki University of Technology Laboratory of Electromechanics, Otaniemi (Finland)

1997-12-31

The paper deals with various types of highspeed electric motors, and their limiting powers. Standard machines with laminated rotors can be utilised if the speed is moderate. The solid rotor construction makes it possible to reach higher power and speed levels than those of laminated rotors. The development work on high-speed motors done at Helsinki University of Technology is presented, too. (orig.) 12 refs.

Report on research achievements in fiscal 1999. Research and development of an ultra-high density electron SI technology (development of a technology for energy use rationalization); 1999 nendo chokomitsudo denshi SI gijutsu no kenkyu kaihatsu energy shiyo gorika gijutsu kaihatsu seika hokokusho

Energy Technology Data Exchange (ETDEWEB)

NONE

2000-05-01

A high-density information network society is going to be realized in the 21st century. Information communication devices used therein are demanded of having high speed and high performance including acoustic and image digital processing, reduced size and weight, and low electric power consumption. While explosion in increase is estimated in the quantity of information handled by these information communication devices, there is a trend that the speed increase in CPU cannot follow the quantity increase. The present proposal is intended to make drastic performance enhancement by using the electron SI (comprehensive mounting) technology which includes making the LSI chips three dimensional and compounding light and electric power mounting, as well as design optimization. The present research and development has an objective to integrate the following three elements to achieve an ultra-high density electron SI technology: (1) a three-dimensional lamination technology making shortest wiring between LSI chips possible, (2) a light and electric power compounded mounting technology making high speed and large capacity transmission inside a board possible, and (3) optimal wiring structure design to suppress unnecessary electromagnetic radiation caused by increasing signal speeds. The research plan period lasts for five years. This paper reports the progresses in each theme in fiscal 1999. (NEDO)

On-chip spectroscopy with thermally tuned high-Q photonic crystal cavities

Energy Technology Data Exchange (ETDEWEB)

Liapis, Andreas C., E-mail: andreas.liapis@gmail.com; Gao, Boshen; Siddiqui, Mahmudur R. [The Institute of Optics, University of Rochester, Rochester, New York 14627 (United States); Shi, Zhimin [Department of Physics, University of South Florida, Tampa, Florida 33620 (United States); Boyd, Robert W. [The Institute of Optics, University of Rochester, Rochester, New York 14627 (United States); Department of Physics and School of Electrical Engineering and Computer Science, University of Ottawa, Ottawa, Ontario K1N 6N5 (Canada)

2016-01-11

Spectroscopic methods are a sensitive way to determine the chemical composition of potentially hazardous materials. Here, we demonstrate that thermally tuned high-Q photonic crystal cavities can be used as a compact high-resolution on-chip spectrometer. We have used such a chip-scale spectrometer to measure the absorption spectra of both acetylene and hydrogen cyanide in the 1550 nm spectral band and show that we can discriminate between the two chemical species even though the two materials have spectral features in the same spectral region. Our results pave the way for the development of chip-size chemical sensors that can detect toxic substances.

Development of an ATCA IPMI controller mezzanine board to be used in the ATCA developments for the ATLAS Liquid Argon upgrade

CERN Document Server

Letendre, N; The ATLAS collaboration

2012-01-01

In the context of the LHC upgrade, we develop a new Read Out Driver (ROD) for the ATLAS Liquid Argon (LAr) community. ATCA and μTCA (Advanced/Micro Telecom Computing Architecture) is becoming a standard in high energy physics and a strong candidate to be used for boards and crates. We work to master ATCA and to integrate a large number of high speed links (96 links at 8.5 Gbps) on a ROD evaluation ATCA board. A versatile ATCA IPMI controller for ATCA boards which is FPGA Mezzanine Card (FMC) compliant has been developed to control the ROD evaluation board.

Development and validation of a general-purpose ASIC chip for the control of switched reluctance machines

International Nuclear Information System (INIS)

Chen Haijin; Lu Shengli; Shi Longxing

2009-01-01

A general-purpose application specific integrated circuit (ASIC) chip for the control of switched reluctance machines (SRMs) was designed and validated to fill the gap between the microcontroller capability and the controller requirements of high performance switched reluctance drive (SRD) systems. It can be used for the control of SRM running either in low speed or in high-speed, i.e., either in chopped current control (CCC) mode or in angular position control (APC) mode. Main functions of the chip include filtering and cycle calculation of rotor angular position signals, commutation logic according to rotor cycle and turn-on/turn-off angles (θ on /θ off ), controllable pulse width modulation (PWM) waveforms generation, chopping control with adjustable delay time, and commutation control with adjustable delay time. All the control parameters of the chip are set online by the microcontroller through a serial peripheral interface (SPI). The chip has been designed with the standard cell based design methodology, and implemented in the central semiconductor manufacturing corporation (CSMC) 0.5 μm complementary metal-oxide-semiconductor (CMOS) process technology. After a successful automatic test equipment (ATE) test using the Nextest's Maverick test system, the chip was further validated through an experimental three-phase 6/2-pole SRD system. Both the ATE test and experimental validation results show that the chip can meet the control requirements of high performance SRD systems, and simplify the controller construction. For a resolution of 0.36 deg. (electrical degree), the chip's maximum processable frequency of the rotor angular position signals is 10 kHz, which is 300,000 rev/min when a three-phase 6/2-pole SRM is concerned

Chromatically encoded high-speed photography of cavitation bubble dynamics inside inhomogeneous ophthalmic tissue

Science.gov (United States)

Tinne, N.; Matthias, B.; Kranert, F.; Wetzel, C.; Krüger, A.; Ripken, T.

2016-03-01

The interaction effect of photodisruption, which is used for dissection of biological tissue with fs-laser pulses, has been intensively studied inside water as prevalent sample medium. In this case, the single effect is highly reproducible and, hence, the method of time-resolved photography is sufficiently applicable. In contrast, the reproducibility significantly decreases analyzing more solid and anisotropic media like biological tissue. Therefore, a high-speed photographic approach is necessary in this case. The presented study introduces a novel technique for high-speed photography based on the principle of chromatic encoding. For illumination of the region of interest within the sample medium, the light paths of up to 12 LEDs with various emission wavelengths are overlaid via optical filters. Here, MOSFET-electronics provide a LED flash with a duration diodes are externally triggered with a distinct delay for every LED. Furthermore, the different illumination wavelengths are chromatically separated again for detection via camera chip. Thus, the experimental setup enables the generation of a time-sequence of laser-tissue interaction inside anisotropic biological tissue and for the optimization of the surgical process with high-repetition rate fs-lasers. Additionally, this application is also suitable for the investigation of other microscopic, ultra-fast events in transparent inhomogeneous materials.

Development of an ATCA IPMI Controller Mezzanine Board and its usage on an ATCA ROD Evaluator board for the ATLAS LAr upgrade

CERN Document Server

"DUMONT DAYOT, N; The ATLAS collaboration; "CAP, S; "DUMONT DAYOT, N; "FOURNIER, L; "LETENDRE, N; "PERROT, G; "Wingerter, I

2011-01-01

In the context of the LHC upgrades, a new Read-Out Driver (ROD) board for the ATLAS LAr calorimeter is being developed. xTCA (Advanced/Micro Telecom Computing Architecture) is becoming a standard in high energy physics and is a serious candidate for future readout systems. We will present our current developments to master ATCA and to integrate a large number of very high speed links (96 links/8.5 Gbps) on a ROD Evaluator ATCA board. To manage our ROD Evaluator, we have developed a versatile ATCA IPMI controller for ATCA boards which is FPGA Mezzanine Card (FMC) compliant.

Rotational microfluidic motor for on-chip microcentrifugation

Science.gov (United States)

Shilton, Richie J.; Glass, Nick R.; Chan, Peggy; Yeo, Leslie Y.; Friend, James R.

2011-06-01

We report on the design of a surface acoustic wave (SAW) driven fluid-coupled micromotor which runs at high rotational velocities. A pair of opposing SAWs generated on a lithium niobate substrate are each obliquely passed into either side of a fluid drop to drive rotation of the fluid, and the thin circular disk set on the drop. Using water for the drop, a 5 mm diameter disk was driven with rotation speeds and start-up torques up to 2250 rpm and 60 nN m, respectively. Most importantly for lab-on-a-chip applications, radial accelerations of 172 m/s2 was obtained, presenting possibilities for microcentrifugation, flow sequencing, assays, and cell culturing in truly microscale lab-on-a-chip devices.

A compact PE memory for vision chips

Science.gov (United States)

Cong, Shi; Zhe, Chen; Jie, Yang; Nanjian, Wu; Zhihua, Wang

2014-09-01

This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8 × 8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm2/bit promises a higher integration level of the processor. A prototype chip with a 64 × 64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction.

A compact PE memory for vision chips

International Nuclear Information System (INIS)

Shi Cong; Chen Zhe; Yang Jie; Wu Nanjian; Wang Zhihua

2014-01-01

This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8 × 8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm 2 /bit promises a higher integration level of the processor. A prototype chip with a 64 × 64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction. (semiconductor integrated circuits)

On-chip plasmon-induced transparency based on plasmonic coupled nanocavities.

Science.gov (United States)

Zhu, Yu; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

2014-01-17

On-chip plasmon-induced transparency offers the possibility of realization of ultrahigh-speed information processing chips. Unfortunately, little experimental progress has been made to date because it is difficult to obtain on-chip plasmon-induced transparency using only a single meta-molecule in plasmonic circuits. Here, we report a simple and efficient strategy to realize on-chip plasmon-induced transparency in a nanoscale U-shaped plasmonic waveguide side-coupled nanocavity pair. High tunability in the transparency window is achieved by covering the pair with different organic polymer layers. It is possible to realize ultrafast all-optical tunability based on pump light-induced refractive index change of a graphene cover layer. Compared with previous reports, the overall feature size of the plasmonic nanostructure is reduced by more than three orders of magnitude, while ultrahigh tunability of the transparency window is maintained. This work also provides a superior platform for the study of the various physical effects and phenomena of nonlinear optics and quantum optics.

An automatic system for elaboration of chip breaking diagrams

DEFF Research Database (Denmark)

Andreasen, Jan Lasson; De Chiffre, Leonardo

1998-01-01

A laboratory system for fully automatic elaboration of chip breaking diagrams has been developed and tested. The system is based on automatic chip breaking detection by frequency analysis of cutting forces in connection with programming of a CNC-lathe to scan different feeds, speeds and cutting...

A wireless high-speed data acquisition system for geotechnical centrifuge model testing

Science.gov (United States)

Gaudin, C.; White, D. J.; Boylan, N.; Breen, J.; Brown, T.; DeCatania, S.; Hortin, P.

2009-09-01

This paper describes a novel high-speed wireless data acquisition system (WDAS) developed at the University of Western Australia for operation onboard a geotechnical centrifuge, in an enhanced gravitational field of up to 300 times Earth's gravity. The WDAS system consists of up to eight separate miniature units distributed around the circumference of a 0.8 m diameter drum centrifuge, communicating with the control room via wireless Ethernet. Each unit is capable of powering and monitoring eight instrument channels at a sampling rate of up to 1 MHz at 16-bit resolution. The data are stored within the logging unit in solid-state memory, but may also be streamed in real-time at low frequency (up to 10 Hz) to the centrifuge control room, via wireless transmission. The high-speed logging runs continuously within a circular memory (buffer), allowing for storage of a pre-trigger segment of data prior to an event. To suit typical geotechnical modelling applications, the system can record low-speed data continuously, until a burst of high-speed acquisition is triggered when an experimental event occurs, after which the system reverts back to low-speed acquisition to monitor the aftermath of the event. Unlike PC-based data acquisition solutions, this system performs the full sequence of amplification, conditioning, digitization and storage on a single circuit board via an independent micro-controller allocated to each pair of instrumented channels. This arrangement is efficient, compact and physically robust to suit the centrifuge environment. This paper details the design specification of the WDAS along with the software interface developed to control the units. Results from a centrifuge test of a submarine landslide are used to illustrate the performance of the new WDAS.

A wireless high-speed data acquisition system for geotechnical centrifuge model testing

International Nuclear Information System (INIS)

Gaudin, C; White, D J; Boylan, N; Breen, J; Brown, T; De Catania, S; Hortin, P

2009-01-01

This paper describes a novel high-speed wireless data acquisition system (WDAS) developed at the University of Western Australia for operation onboard a geotechnical centrifuge, in an enhanced gravitational field of up to 300 times Earth's gravity. The WDAS system consists of up to eight separate miniature units distributed around the circumference of a 0.8 m diameter drum centrifuge, communicating with the control room via wireless Ethernet. Each unit is capable of powering and monitoring eight instrument channels at a sampling rate of up to 1 MHz at 16-bit resolution. The data are stored within the logging unit in solid-state memory, but may also be streamed in real-time at low frequency (up to 10 Hz) to the centrifuge control room, via wireless transmission. The high-speed logging runs continuously within a circular memory (buffer), allowing for storage of a pre-trigger segment of data prior to an event. To suit typical geotechnical modelling applications, the system can record low-speed data continuously, until a burst of high-speed acquisition is triggered when an experimental event occurs, after which the system reverts back to low-speed acquisition to monitor the aftermath of the event. Unlike PC-based data acquisition solutions, this system performs the full sequence of amplification, conditioning, digitization and storage on a single circuit board via an independent micro-controller allocated to each pair of instrumented channels. This arrangement is efficient, compact and physically robust to suit the centrifuge environment. This paper details the design specification of the WDAS along with the software interface developed to control the units. Results from a centrifuge test of a submarine landslide are used to illustrate the performance of the new WDAS

Digital circuit boards mach 1 GHz

CERN Document Server

Morrison, Ralph

2012-01-01

A unique, practical approach to the design of high-speed digital circuit boards The demand for ever-faster digital circuit designs is beginning to render the circuit theory used by engineers ineffective. Digital Circuit Boards presents an alternative to the circuit theory approach, emphasizing energy flow rather than just signal interconnection to explain logic circuit behavior. The book shows how treating design in terms of transmission lines will ensure that the logic will function, addressing both storage and movement of electrical energy on these lines. It cove

High speed UNIBUS-VME interface; Interface de alta velocidad VME-UNIBUS

Energy Technology Data Exchange (ETDEWEB)

Olmos, P

1987-07-01

An interface between VME an the UNIBUS of PDP or VAX computer is presented. The system supports high speed parallel communication (up to 1MB/S) and is composed of two modules. One of these is a commercial DR11M board which performs DMA transfers between UNIBUS and the external word. The other is a VME module specifically developed for this application. The interface has been tested under VMS operating system in VAX and VALET-PLUS system for the VME Bus. We describe in detail the VME module and its connection with the DR11M. Software, both in WMS and VALET, is also described. (Author) 7 refs.

Design, Fabrication and Prototype testing of a Chip Integrated Micro PEM Fuel Cell Accumulator combined On-Board Range Extender

International Nuclear Information System (INIS)

Balakrishnan, A; Mueller, C; Reinecke, H

2014-01-01

In this work we present the design, fabrication and prototype testing of Chip Integrated Micro PEM Fuel Cell Accumulator (CIμ-PFCA) combined On-Board Range Extender (O-BRE). CIμ-PFCA is silicon based micro-PEM fuel cell system with an integrated hydrogen storage feature (palladium metal hydride), the run time of CIμ-PFCA is dependent on the stored hydrogen, and in order to extend its run time an O-BRE is realized (catalytic hydrolysis of chemical hydride, NaBH 4 . Combining the CIμ-PFCA and O-BRE on a system level have few important design requirements to be considered; hydrogen regulation, gas -liquid separator between the CIμ-PFCA and the O-RE. The usage of traditional techniques to regulate hydrogen (tubes), gas-liquid phase membranes (porous membrane separators) are less desirable in the micro domain, due to its space constraint. Our approach is to use a passive hydrogen regulation and gas-liquid phase separation concept; to use palladium membrane. Palladium regulates hydrogen by concentration diffusion, and its property to selectively adsorb only hydrogen is used as a passive gas-liquid phase separator. Proof of concept is shown by realizing a prototype system. The system is an assembly of CIμ-PFCA, palladium membrane and the O-BRE. The CIμ-PFCA consist of 2 individually processed silicon chips, copper supported palladium membrane realized by electroplating followed by high temperature annealing process under inter atmosphere and the O-BRE is realized out of a polymer substrate by micromilling process with platinum coated structures, which functions as a catalyst for the hydrolysis of NaBH 4 . The functionality of the assembled prototype system is demonstrated by the measuring a unit cell (area 1 mm 2 ) when driven by the catalytic hydrolysis of chemical hydride (NaBH 4 and the prototype system shows run time more than 15 hours

Polymer Surface Textured with Nanowire Bundles to Repel High-Speed Water Drops.

Science.gov (United States)

Li, Y P; Li, X Y; Zhu, X P; Lei, M K; Lakhtakia, A

2018-05-11

Water drops impacting windshields of high-speed trains and aircraft as well as blades in steam turbine power generators obliquely and at high speeds are difficult to repel. Impacting drops penetrate the void regions of nanotextured and microtextured superhydrophobic coatings, with this pinning resulting in the loss of drop mobility. In order to repel high-speed water drops, we nanotextured polymer surfaces with nanowire bundles separated from their neighbors by microscale void regions, with the nanowires in a bundle separated from their neighbors by nanoscale void regions. Water drops with speeds below a critical speed rebound completely. Water drops with speeds exceeding a critical speed rebound partially, but residual droplets that begin to be pinned undergo a spontaneous dewetting process and slide off. The natural oscillations of residual droplets drive this dewetting process in the interbundle void regions, resulting in a transition from the sticky Wenzel state to the slippery Cassie state without external stimuli.

Numerical analysis of the interaction between high-pressure resin spray and wood chips in a vapour stream

Directory of Open Access Journals (Sweden)

Massimo Milani

2016-04-01

Full Text Available This article investigates the interaction between the resin spray and the wood chips in a vapour stream using a multi-phase multi-component computational fluid dynamics approach. The interaction between the spray and the chips is one of the main issues in the industrial process for manufacturing medium density fibre boards. Thus, the optimization of this process can lead to important benefits, such as the reduction in the emission of formaldehyde-based toxic chemicals, the reduction in energy consumption in the blending process and energy saving in the fibreboard drying process. First step of the study is the numerical analysis of the resin injector in order to extend the experimental measurements carried out with water to the resin spray. The effects of the injector’s geometrical features on the spray formation are highlighted under different injection pressure values and needle displacements. Afterwards, the results obtained in the analysis of the single injector are used for the complete simulation of multi-injector rail where the mixing of the resin spray and wood chips takes place. The influence of the main operating conditions, such as the vapour and the wood chip flow rates, on the resin distribution is addressed in order to optimize the resination process.

Impact and injury response of long track speed skaters

NARCIS (Netherlands)

Forbes, P.A.; Swartjes, F.H.M.; Ruimerman, R.; Willems, J.W.M.

2009-01-01

The following study presents a combined numerical-experimental investigation into the impact and injury response of long track speed skaters when impacting the protective boarding around the track. The high speeds common within the sport combined with the inherent slipperiness of the ice create a

Compact sub-nanosecond pulse seed source with diode laser driven by a high-speed circuit

Science.gov (United States)

Wang, Xiaoqian; Wang, Bo; Wang, Junhua; Cheng, Wenyong

2018-06-01

A compact sub-nanosecond pulse seed source with 1550 nm diode laser (DL) was obtained by employing a high-speed circuit. The circuit mainly consisted of a short pulse generator and a short pulse driver. The short pulse generator, making up of a complex programmable logic device (CPLD), a level translator, two programmable delay chips and an AND gate chip, output a triggering signal to control metal-oxide-semiconductor field-effect transistor (MOSFET) switch of the short pulse driver. The MOSFET switch with fast rising time and falling time both shorter than 1 ns drove the DL to emit short optical pulses. Performances of the pulse seed source were tested. The results showed that continuously adjustable repetition frequency ranging from 500 kHz to 100 MHz and pulse duration in the range of 538 ps to 10 ns were obtained, respectively. 537 μW output was obtained at the highest repetition frequency of 100 MHz with the shortest pulse duration of 538 ps. These seed pulses were injected into an fiber amplifier, and no optical pulse distortions were found.

The Application of Virtex-II Pro FPGA in High-Speed Image Processing Technology of Robot Vision Sensor

International Nuclear Information System (INIS)

Ren, Y J; Zhu, J G; Yang, X Y; Ye, S H

2006-01-01

The Virtex-II Pro FPGA is applied to the vision sensor tracking system of IRB2400 robot. The hardware platform, which undertakes the task of improving SNR and compressing data, is constructed by using the high-speed image processing of FPGA. The lower level image-processing algorithm is realized by combining the FPGA frame and the embedded CPU. The velocity of image processing is accelerated due to the introduction of FPGA and CPU. The usage of the embedded CPU makes it easily to realize the logic design of interface. Some key techniques are presented in the text, such as read-write process, template matching, convolution, and some modules are simulated too. In the end, the compare among the modules using this design, using the PC computer and using the DSP, is carried out. Because the high-speed image processing system core is a chip of FPGA, the function of which can renew conveniently, therefore, to a degree, the measure system is intelligent

The Application of Virtex-II Pro FPGA in High-Speed Image Processing Technology of Robot Vision Sensor

Science.gov (United States)

Ren, Y. J.; Zhu, J. G.; Yang, X. Y.; Ye, S. H.

2006-10-01

The Virtex-II Pro FPGA is applied to the vision sensor tracking system of IRB2400 robot. The hardware platform, which undertakes the task of improving SNR and compressing data, is constructed by using the high-speed image processing of FPGA. The lower level image-processing algorithm is realized by combining the FPGA frame and the embedded CPU. The velocity of image processing is accelerated due to the introduction of FPGA and CPU. The usage of the embedded CPU makes it easily to realize the logic design of interface. Some key techniques are presented in the text, such as read-write process, template matching, convolution, and some modules are simulated too. In the end, the compare among the modules using this design, using the PC computer and using the DSP, is carried out. Because the high-speed image processing system core is a chip of FPGA, the function of which can renew conveniently, therefore, to a degree, the measure system is intelligent.

High speed heterostructure devices

CERN Document Server

Beer, Albert C; Willardson, R K; Kiehl, Richard A; Sollner, T C L Gerhard

1994-01-01

Volume 41 includes an in-depth review of the most important, high-speed switches made with heterojunction technology. This volume is aimed at the graduate student or working researcher who needs a broad overview andan introduction to current literature. Key Features * The first complete review of InP-based HFETs and complementary HFETs, which promise very low power and high speed * Offers a complete, three-chapter review of resonant tunneling * Provides an emphasis on circuits as well as devices.

Applications of High Speed Configurable Logic Devices in Modern Particle Physics Experiments

CERN Document Server

Giorgi, Filippo Maria

Several activities were conducted during my PhD activity. For the NEMO experiment a collaboration between the INFN/University groups of Catania and Bologna led to the development and production of a mixed signal acquisition board for the Nemo Km3 telescope. The research concerned the feasibility study for a different acquisition technique quite far from that adopted in the NEMO Phase 1 telescope. The DAQ board that we realized exploits the LIRA06 front-end chip for the analog acquisition of anodic an dynodic sources of a PMT (Photo-Multiplier Tube). The low-power analog acquisition allows to sample contemporaneously multiple channels of the PMT at different gain factors in order to increase the signal response linearity over a wider dynamic range. Also the auto triggering and self-event-classification features help to improve the acquisition performance and the knowledge on the neutrino event. A fully functional interface towards the first level data concentrator, the Floor Control Module, has been integrated...

Bottom Raking Damage to High-Speed Craft

DEFF Research Database (Denmark)

Simonsen, Bo Cerup

1998-01-01

This paper presents a comparative study of the raking damage to high speed craft (HSC) and conventional ships. The analysis is based on a detailed theoretical model for the raking resistance of an assembled ship bottom structure and on the idea that the impact conditions for various ship types have...

High resolution RGB color line scan camera

Science.gov (United States)

Lynch, Theodore E.; Huettig, Fred

1998-04-01

A color line scan camera family which is available with either 6000, 8000 or 10000 pixels/color channel, utilizes off-the-shelf lenses, interfaces with currently available frame grabbers, includes on-board pixel by pixel offset correction, and is configurable and controllable via RS232 serial port for computer controlled or stand alone operation is described in this paper. This line scan camera is based on an available 8000 element monochrome line scan camera designed by AOA for OEM use. The new color version includes improvements such as better packaging and additional user features which make the camera easier to use. The heart of the camera is a tri-linear CCD sensor with on-chip color balancing for maximum accuracy and pinned photodiodes for low lag response. Each color channel is digitized to 12 bits and all three channels are multiplexed together so that the resulting camera output video is either a 12 or 8 bit data stream at a rate of up to 24Megpixels/sec. Conversion from 12 to 8 bit, or user-defined gamma, is accomplished by on board user-defined video look up tables. The camera has two user-selectable operating modes; lows speed, high sensitivity mode or high speed, reduced sensitivity mode. The intended uses of the camera include industrial inspection, digital archiving, document scanning, and graphic arts applications.

GRAPE-5: A Special-Purpose Computer for N-body Simulation

OpenAIRE

Kawai, Atsushi; Fukushige, Toshiyuki; Makino, Junichiro; Taiji, Makoto

1999-01-01

We have developed a special-purpose computer for gravitational many-body simulations, GRAPE-5. GRAPE-5 is the successor of GRAPE-3. Both consist of eight custom pipeline chips (G5 chip and GRAPE chip). The difference between GRAPE-5 and GRAPE-3 are: (1) The G5 chip contains two pipelines operating at 80 MHz, while the GRAPE chip had one at 20 MHz. Thus, the calculation speed of the G5 chip and that of GRAPE-5 board are 8 times faster than that of GRAPE chip and GRAPE-3 board. (2) The GRAPE-5 ...

Optimization of PAM-4 transmitters based on lumped silicon photonic MZMs for high-speed short-reach optical links.

Science.gov (United States)

Zhou, Shiyu; Wu, Hsin-Ta; Sadeghipour, Khosrov; Scarcella, Carmelo; Eason, Cormac; Rensing, Marc; Power, Mark J; Antony, Cleitus; O'Brien, Peter; Townsend, Paul D; Ossieur, Peter

2017-02-20

We demonstrate how to optimize the performance of PAM-4 transmitters based on lumped Silicon Photonic Mach-Zehnder Modulators (MZMs) for short-reach optical links. Firstly, we analyze the trade-off that occurs between extinction ratio and modulation loss when driving an MZM with a voltage swing less than the MZM's Vπ. This is important when driver circuits are realized in deep submicron CMOS process nodes. Next, a driving scheme based upon a switched capacitor approach is proposed to maximize the achievable bandwidth of the combined lumped MZM and CMOS driver chip. This scheme allows the use of lumped MZM for high speed optical links with reduced RF driver power consumption compared to the conventional approach of driving MZMs (with transmission line based electrodes) with a power amplifier. This is critical for upcoming short-reach link standards such as 400Gb/s 802.3 Ethernet. The driver chip was fabricated using a 65nm CMOS technology and flip-chipped on top of the Silicon Photonic chip (fabricated using IMEC's ISIPP25G technology) that contains the MZM. Open eyes with 4dB extinction ratio for a 36Gb/s (18Gbaud) PAM-4 signal are experimentally demonstrated. The electronic driver chip has a core area of only 0.11mm2 and consumes 236mW from 1.2V and 2.4V supply voltages. This corresponds to an energy efficiency of 6.55pJ/bit including Gray encoder and retiming, or 5.37pJ/bit for the driver circuit only.

Prediction of 3D chip formation in the facing cutting with lathe machine using FEM

Science.gov (United States)

Prasetyo, Yudhi; Tauviqirrahman, Mohamad; Rusnaldy

2016-04-01

This paper presents the prediction of the chip formation at the machining process using a lathe machine in a more specific way focusing on facing cutting (face turning). The main purpose is to propose a new approach to predict the chip formation with the variation of the cutting directions i.e., the backward and forward direction. In addition, the interaction between stress analysis and chip formation on cutting process was also investigated. The simulations were conducted using three dimensional (3D) finite element method based on ABAQUS software with aluminum and high speed steel (HSS) as the workpiece and the tool materials, respectively. The simulation result showed that the chip resulted using a backward direction depicts a better formation than that using a conventional (forward) direction.

Global On-Chip Differential Interconnects with Optimally-Placed Twists

NARCIS (Netherlands)

Mensink, E.; Schinkel, Daniel; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

2005-01-01

Global on-chip communication is receiving quite some attention as global interconnects are rapidly becoming a speed, power and reliability bottleneck for digital CMOS systems. Recently, we proposed a bus-transceiver test chip in 0.13 μm CMOS using 10 mm long uninterrupted differential interconnects

Adaptations to speed endurance training in highly trained soccer players

DEFF Research Database (Denmark)

Nyberg, Michael Permin; Fiorenza, Matteo; Lund, Anders

2016-01-01

PURPOSE: The present study examined whether a period of additional speed endurance training would improve intense intermittent exercise performance in highly trained soccer players during the season and whether the training changed aerobic metabolism and the level of oxidative enzymes in type I...... and II muscle fibers. METHODS: During the last nine weeks of the season, thirteen semi-professional soccer players performed additional speed endurance training sessions consisting of 2-3 sets of 8 - 10 repetitions of 30 m sprints with 10 s of passive recovery (SET). Before and after SET, subjects...... in type I and II fibers did not change. CONCLUSION: In highly trained soccer players, additional speed endurance training is associated with an improved ability to perform repeated high-intensity work. To what extent the training-induced changes in V˙O2 kinetics and mechanical efficiency in type I fibers...

FY1995 trial production of brain functional chip; 1995 nendo no kino shuseki chip no shisaku

Energy Technology Data Exchange (ETDEWEB)

NONE

1997-03-01

The present computer system will run on a program which is prepared in advance. On the other hand, the human brain can acquire some processes from learning with experiments. It would be very useful us human nature, if these learning process should be build up artificially. Our aim is to reveal basic self-acquiring mechanism of information and its processes of the brain, and preliminary research, including theoretical problems, for building up specialized processor chip. Many research on the brain have been held at the views of scientifically and medically. However; we focused on the principle brain learning process itself. The results of the research was directly realized on a specialized processor chip tuned for high-speed simulation of neural network. We could pointed out some problems on the present brain type processor, and discussed about basic technique for implementation of the next age brain type processor and theories. (NEDO)

Chip-package nano-structured copper and nickel interconnections with metallic and polymeric bonding interfaces

Science.gov (United States)

Aggarwal, Ankur

With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 that support computing speed in terabits per second, with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Decreasing I/O pitch together with low cost, high electrical performance and high reliability are the key technological challenges identified by the 2005 International Technology Roadmap for Semiconductors (ITRS). Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. In addition, the materials must be environmentally-friendly, corrosion resistant, thermally stable over a long time, and resistant to electro-migration. A major challenge is also to develop economic processes that can be integrated into back end of the wafer foundry, i.e. with wafer level packaging. Device-to-system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches of the order of 30 microns and less. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. A novel chip-package interconnection technology is

Novel High Pressure Pump-on-a-Chip Technology, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — HJ Science & Technology, Inc. proposes to develop a novel high pressure "pump-on-a-chip" (HPPOC) technology capable of generating high pressure and flow rate on...

Research of high speed data readout and pre-processing system based on xTCA for silicon pixel detector

International Nuclear Information System (INIS)

Zhao Jingzhou; Lin Haichuan; Guo Fang; Liu Zhen'an; Xu Hao; Gong Wenxuan; Liu Zhao

2012-01-01

As the development of the detector, Silicon pixel detectors have been widely used in high energy physics experiments. It needs data processing system with high speed, high bandwidth and high availability to read data from silicon pixel detectors which generate more large data. The same question occurs on Belle II Pixel Detector which is a new style silicon pixel detector used in SuperKEKB accelerator with high luminance. The paper describes the research of High speed data readout and pre-processing system based on xTCA for silicon pixel detector. The system consists of High Performance Computer Node (HPCN) based on xTCA and ATCA frame. The HPCN consists of 4XFPs based on AMC, 1 AMC Carrier ATCA Board (ACAB) and 1 Rear Transmission Module. It characterized by 5 high performance FPGAs, 16 fiber links based on RocketIO, 5 Gbit Ethernet ports and DDR2 with capacity up to 18GB. In a ATCA frame, 14 HPCNs make up a system using the high speed backplane to achieve the function of data pre-processing and trigger. This system will be used on the trigger and data acquisition system of Belle II Pixel detector. (authors)

Development of an ATCA IPMI controller mezzanine board to be used in the ATCA developments for the ATLAS Liquid Argon upgrade

CERN Document Server

Dumont Dayot, N

2012-01-01

In the context of the LHC upgrades, a new Read-Out Driver (ROD) board for the ATLAS LAr calorimeter is being developed. xTCA (Advanced/Micro Telecom Computing Architecture) is becoming a standard in high energy physics and is a serious candidate for future readout systems. We will present our current developments to master ATCA and to integrate a large number of very high speed links (96 links/8.5 Gbps) on a ROD Evaluator ATCA board. To manage our ROD Evaluator, we have developed a versatile ATCA IPMI controller for ATCA boards which is FPGA Mezzanine Card (FMC) compliant.

Development of an ATCA IPMI Controller Mezzanine Board to be used in the ATCA developments for the ATLAS Liquid Argon upgrade

CERN Document Server

"LETENDRE, N; The ATLAS collaboration

2011-01-01

In the context of the LHC upgrades, a new Read-Out Driver (ROD) board for the ATLAS LAr calorimeter is being developed. xTCA (Advanced/Micro Telecom Computing Architecture) is becoming a standard in high energy physics and is a serious candidate for future readout systems. We will present our current developments to master ATCA and to integrate a large number of very high speed links (96 links/8.5 Gbps) on a ROD Evaluator ATCA board. To manage our ROD Evaluator, we have developed a versatile ATCA IPMI controller for ATCA boards which is FPGA Mezzanine Card (FMC) compliant.

High-Speed Data Recorder for Space, Geodesy, and Other High-Speed Recording Applications

Science.gov (United States)

Taveniku, Mikael

2013-01-01

A high-speed data recorder and replay equipment has been developed for reliable high-data-rate recording to disk media. It solves problems with slow or faulty disks, multiple disk insertions, high-altitude operation, reliable performance using COTS hardware, and long-term maintenance and upgrade path challenges. The current generation data recor - ders used within the VLBI community are aging, special-purpose machines that are both slow (do not meet today's requirements) and are very expensive to maintain and operate. Furthermore, they are not easily upgraded to take advantage of commercial technology development, and are not scalable to multiple 10s of Gbit/s data rates required by new applications. The innovation provides a softwaredefined, high-speed data recorder that is scalable with technology advances in the commercial space. It maximally utilizes current technologies without being locked to a particular hardware platform. The innovation also provides a cost-effective way of streaming large amounts of data from sensors to disk, enabling many applications to store raw sensor data and perform post and signal processing offline. This recording system will be applicable to many applications needing realworld, high-speed data collection, including electronic warfare, softwaredefined radar, signal history storage of multispectral sensors, development of autonomous vehicles, and more.

Study on the separation effect of high-speed ultrasonic vibration cutting.

Science.gov (United States)

Zhang, Xiangyu; Sui, He; Zhang, Deyuan; Jiang, Xinggang

2018-07-01

High-speed ultrasonic vibration cutting (HUVC) has been proven to be significantly effective when turning Ti-6Al-4V alloy in recent researches. Despite of breaking through the cutting speed restriction of the ultrasonic vibration cutting (UVC) method, HUVC can also achieve the reduction of cutting force and the improvements in surface quality and cutting efficiency in the high-speed machining field. These benefits all result from the separation effect that occurs during the HUVC process. Despite the fact that the influences of vibration and cutting parameters have been discussed in previous researches, the separation analysis of HUVC should be conducted in detail in real cutting situations, and the tool geometry parameters should also be considered. In this paper, three situations are investigated in details: (1) cutting without negative transient clearance angle and without tool wear, (2) cutting with negative transient clearance angle and without tool wear, and (3) cutting with tool wear. And then, complete separation state, partial separation state and continuous cutting state are deduced according to real cutting processes. All the analysis about the above situations demonstrate that the tool-workpiece separation will take place only if appropriate cutting parameters, vibration parameters, and tool geometry parameters are set up. The best separation effect was obtained with a low feedrate and a phase shift approaching 180 degrees. Moreover, flank face interference resulted from the negative transient clearance angle and tool wear contributes to an improved separation effect that makes the workpiece and tool separate even at zero phase shift. Finally, axial and radial transient cutting force are firstly obtained to verify the separation effect of HUVC, and the cutting chips are collected to weigh the influence of flank face interference. Copyright © 2018 Elsevier B.V. All rights reserved.

SEAL FOR HIGH SPEED CENTRIFUGE

Science.gov (United States)

Skarstrom, C.W.

1957-12-17

A seal is described for a high speed centrifuge wherein the centrifugal force of rotation acts on the gasket to form a tight seal. The cylindrical rotating bowl of the centrifuge contains a closure member resting on a shoulder in the bowl wall having a lower surface containing bands of gasket material, parallel and adjacent to the cylinder wall. As the centrifuge speed increases, centrifugal force acts on the bands of gasket material forcing them in to a sealing contact against the cylinder wall. This arrangememt forms a simple and effective seal for high speed centrifuges, replacing more costly methods such as welding a closure in place.

A low-cost multichannel pulse-height analyzer PHA 256 using single-chip microcomputer

International Nuclear Information System (INIS)

Koehler, M.; Meiling, W.

1985-01-01

The PHA 256 multichannel analyzer on the base of the U8820 single-chip microcomputer applied for radiation measurements, for example in monitoring systems with scintillation detectors, is described. The analyzer contains a power supply unit and 7 boards, namely, the processor board; data and program memory; 8-bit analog-to-digital converter; driver to display device; keyboard with 23 function keys; pulse amplifier and high-voltage supply (up to 2 kV). Software used provides preprocessing of spectra supported by following functions: addition and subtraction of different spectra, spectrum monitoring by use of a 5-point-algorithm, calculation of peak areas with linearly interpolated background

High-Speed Photography

International Nuclear Information System (INIS)

Paisley, D.L.; Schelev, M.Y.

1998-01-01

The applications of high-speed photography to a diverse set of subjects including inertial confinement fusion, laser surgical procedures, communications, automotive airbags, lightning etc. are briefly discussed. (AIP) copyright 1998 Society of Photo-Optical Instrumentation Engineers

Embedded controllers for local board-control

CERN Document Server

Neufeld, Niko; Mini, Giuseppe; Sannino, Mario; Guzik, Zbigniew; Jacobsson, Richard; Jost, Beat

2005-01-01

The LHCb experiment at CERN has a large number of custom electronic boards performing high-speed data-processing. Like in any large experiment the control and monitoring of these crate-mounted boards must be integrated into the overall control-system. Traditionally this has been done by using buses like VME on the back-plane of the crates. LHCb has chosen to equip every board with an embedded micro-controller and connecting them in a large Local Area Network. The intelligence of these devices allows complex (soft) real-time control and monitoring, required for modern powerful FPGA driven electronics. Moreover each board has its own, isolated control access path, which increases the robustness of the entire system. The system is now in pre-production at several sites and will go into full production during next year. The hardware and software will be discussed and experiences from the R&D and pre-production will be reviewed, with an emphasis on advantages and difficulties of this approach to board-control.

Effect of ionic contamination on climatic reliability of printed circuit board assemblies

DEFF Research Database (Denmark)

Verdingovas, Vadimas; Jellesen, Morten Stendahl; Ambat, Rajan

2012-01-01

The effect of NaCl and weak organic acids (WOAs) in “no-clean” wave solder flux residues was studied on electrochemical migration (ECM), leakage current, and corrosion on surface mount chip capacitors using a test printed circuit board assembly (PCBA) substrate having known chip components...

Nanoliter Centrifugal Liquid Dispenser Coupled with Superhydrophobic Microwell Array Chips for High-Throughput Cell Assays

Directory of Open Access Journals (Sweden)

Yuyi Wang

2018-06-01

Full Text Available Microfluidic systems have been regarded as a potential platform for high-throughput screening technology in drug discovery due to their low sample consumption, high integration, and easy operation. The handling of small-volume liquid is an essential operation in microfluidic systems, especially in investigating large-scale combination conditions. Here, we develop a nanoliter centrifugal liquid dispenser (NanoCLD coupled with superhydrophobic microwell array chips for high-throughput cell-based assays in the nanoliter scale. The NanoCLD consists of a plastic stock block with an array of drilled through holes, a reagent microwell array chip (reagent chip, and an alignment bottom assembled together in a fixture. A simple centrifugation at 800 rpm can dispense ~160 nL reagents into microwells in 5 min. The dispensed reagents are then delivered to cells by sandwiching the reagent chip upside down with another microwell array chip (cell chip on which cells are cultured. A gradient of doxorubicin is then dispensed to the cell chip using the NanoCLD for validating the feasibility of performing drug tests on our microchip platform. This novel nanoliter-volume liquid dispensing method is simple, easy to operate, and especially suitable for repeatedly dispensing many different reagents simultaneously to microwells.

Embedded Processor Based Automatic Temperature Control of VLSI Chips

Directory of Open Access Journals (Sweden)

Narasimha Murthy Yayavaram

2009-01-01

Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

Design, Characterization and Test of the Associative Memory Chip AM06 for the Fast TracKer System

CERN Document Server

Liberali, Valentino; The ATLAS collaboration

2016-01-01

We present the performance of the new Associative Memory (AM) chip, designed and manufactured in 65 nm CMOS technology. The AM06 is the 6th version of a highly parallel ASIC processor for pattern recognition in high energy physics experiments. The AM06 is based on the XORAM cell architecture, which has been specifically designed to reduce power consumption and control complexity. The AM06 is a large chip, which contains memory banks that store all data of interest. The basic unit is a word of 18 bit. A group of 8 words (each of them related to a detector layer) is called a “pattern”. Each AM06 chip stores 2^17 patterns. The AM06 integrates serializer and deserializer IP blocks (working up to 2.4 GHz), to avoid routing congestion at the board level. AM06 is a complex VLSI chip, designed combining full-custom memory arrays, standard logic cells and IP blocks. It occupies a silicon area of 168 mm^2 and it contains about 421 millions transistors. The AM06 chip is able to perform a synchronous bitwise comparis...

All-optical ultra-high-speed OFDM to Nyquist-WDM conversion

DEFF Research Database (Denmark)

Guan, Pengyu; Røge, Kasper Meldgaard; Mulvad, Hans Christian Hansen

2015-01-01

We propose an all-optical ultra-high-speed OFDM to Nyquist-WDM conversion scheme based on complete OFT. An 8-subcarrier 640 Gbit/s DPSK OFDM super-channel is converted to eight 80-Gbit/s Nyquist-WDM channels with BER <10−9 performance for all channels.......We propose an all-optical ultra-high-speed OFDM to Nyquist-WDM conversion scheme based on complete OFT. An 8-subcarrier 640 Gbit/s DPSK OFDM super-channel is converted to eight 80-Gbit/s Nyquist-WDM channels with BER

The high speed civil transport and NASA's High Speed Research (HSR) program

Science.gov (United States)

Shaw, Robert J.

1994-01-01

Ongoing studies being conducted not only in this country but in Europe and Asia suggest that a second generation supersonic transport, or High-Speed Civil Transport (HSCT), could become an important part of the 21st century international air transportation system. However, major environmental compatibility and economic viability issues must be resolved if the HSCT is to become a reality. This talk will overview the NASA High-Speed Research (HSR) program which is aimed at providing the U.S. industry with a technology base to allow them to consider launching an HSCT program early in the next century. The talk will also discuss some of the comparable activities going on within Europe and Japan.

High-Tc dc-SQUID gradiometers in flip-chip configuration

International Nuclear Information System (INIS)

Peiselt, K; Schmidl, F; Linzen, S; Anton, A S; Huebner, U; Seidel, P

2003-01-01

We describe a new design of a gradiometric flip-chip antenna, which is inductively coupled to a dc-SQUID gradiometer. Both components are patterned out of thin films of the high-T c superconductor YBa 2 Cu 3 O 7-x (YBCO). For the flip-chip antenna, a 40 mm x 10 mm SrTiO 3 single crystalline substrate is used, while the gradiometer sensors are prepared on 10 mm x 10 mm SrTiO 3 bicrystal substrates. Special attention is paid to the inductive coupling between the flip-chip antenna and the read-out gradiometer antenna. We investigate different designs of coupling loops in order to optimize the coupling inductance between both components of the sensor. With optimized coupling the sensor achieves a field-gradient resolution of 12 fT cm -1 Hz -1/2 in the white noise region and of 310 fT cm -1 Hz -1/2 at 1 Hz in the unshielded laboratory environment

High-Tc dc-SQUID gradiometers in flip-chip configuration

Science.gov (United States)

Peiselt, K.; Schmidl, F.; Linzen, S.; Anton, A. S.; Hübner, U.; Seidel, P.

2003-12-01

We describe a new design of a gradiometric flip-chip antenna, which is inductively coupled to a dc-SQUID gradiometer. Both components are patterned out of thin films of the high-Tc superconductor YBa2Cu3O7-x (YBCO). For the flip-chip antenna, a 40 mm × 10 mm SrTiO3 single crystalline substrate is used, while the gradiometer sensors are prepared on 10 mm × 10 mm SrTiO3 bicrystal substrates. Special attention is paid to the inductive coupling between the flip-chip antenna and the read-out gradiometer antenna. We investigate different designs of coupling loops in order to optimize the coupling inductance between both components of the sensor. With optimized coupling the sensor achieves a field-gradient resolution of 12 fT cm-1 Hz-1/2 in the white noise region and of 310 fT cm-1 Hz-1/2 at 1 Hz in the unshielded laboratory environment.

CHIPS: A New Way to Monitor Colonias Along the United States-Mexico Border

Science.gov (United States)

Parcher, Jean W.; Humberson, Delbert G.

2007-01-01

Colonias, which are unincorporated border settlements in the United States, have emerged in rural areas without the governance and services normally provided by local government. Colonia residents live in poverty and lack adequate health care, potable water, and sanitation systems. These conditions create substantial health risks for colonias and surrounding communities. By 2001, more than 1,400 colonias were identified in Texas. Cooperation with the U.S. Department of Housing and Urban Development, Offices of the Texas Attorney General, Secretary of State, and the Texas Water Development Board has allowed the U.S. Geological Survey (USGS) to improve colonia Geographic Information System (GIS) boundaries and develop the Colonia Health, Infrastructure, and Platting Status tool (CHIPS). Together, the GIS boundaries and CHIPS aid the Texas government in prioritizing the limited funds that are available for infrastructure improvement. CHIPS's report generator can be tailored to the needs of the user, providing either broad or specific output. For example, a congressman could use CHIPS to list colonias with wastewater issues in a specific county, whereas a health researcher could list all colonias without clinical access. To help cities along the United States-Mexico border manage issues related to colonias growth, CHIPS will become publicly available in an Internet-enabled GIS as part of a cooperative study between the USGS, the U.S. Department of Housing and Urban Development, and the Mexican Instituto Nacional de Estadistica Geografia e Informatica.

33 CFR 84.24 - High-speed craft.

Science.gov (United States)

2010-07-01

... 33 Navigation and Navigable Waters 1 2010-07-01 2010-07-01 false High-speed craft. 84.24 Section... RULES ANNEX I: POSITIONING AND TECHNICAL DETAILS OF LIGHTS AND SHAPES § 84.24 High-speed craft. (a) The masthead light of high-speed craft with a length to breadth ratio of less than 3.0 may be placed at a...

Bridging existing governance gaps: five evidence-based actions that boards can take to pursue high quality care.

Science.gov (United States)

Leggat, Sandra G; Balding, Cathy

2017-11-13

Objective To explore the impact of the organisational quality systems on quality of care in Victorian health services. Methods During 2015 a total of 55 focus groups were conducted with more than 350 managers, clinical staff and board members in eight Victorian health services to explore the effectiveness of health service quality systems. A review of the quality and safety goals and strategies outlined in the strategic and operating plans of the participating health services was also undertaken. Results This paper focuses on the data related to the leadership role of health service boards in ensuring safe, high-quality care. The findings suggest that health service boards are not fully meeting their governance accountability to ensure consistently high-quality care. The data uncovered major clinical governance gaps between stated board and executive aspirations for quality and safety and the implementation of these expectations at point of care. These gaps were further compounded by quality system confusion, over-reliance on compliance, and inadequate staff engagement. Conclusion Based on the existing evidence we propose five specific actions boards can take to close the gaps, thereby supporting improved care for all consumers. What is known about this topic? Effective governance is essential for high-quality healthcare delivery. Boards are required to play an active role in their organisation's pursuit of high quality care. What does this paper add? Recent government reports suggest that Australian health service boards are not fully meeting their governance requirements for high quality, safe care delivery, and our research pinpoints key governance gaps. What are the implications for practitioners? Based on our research findings we outline five evidence-based actions for boards to improve their governance of quality care delivery. These actions focus on an organisational strategy for high-quality care, with the chief executive officer held accountable for

Characterization of AGIPD1.0: The full scale chip

Energy Technology Data Exchange (ETDEWEB)

Mezza, D., E-mail: davide.mezza@psi.ch [Paul-Scherrer-Institute (PSI), Villigen (Switzerland); Allahgholi, A.; Arino-Estrada, G.; Bianco, L.; Delfs, A. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Dinapoli, R. [Paul-Scherrer-Institute (PSI), Villigen (Switzerland); Goettlicher, P. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Graafsma, H. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Mid Sweden University, Sundsvall (Sweden); Greiffenberg, D. [Paul-Scherrer-Institute (PSI), Villigen (Switzerland); Hirsemann, H.; Jack, S. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Klanner, R. [University of Hamburg, Hamburg (Germany); Klyuev, A. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Krueger, H. [University of Bonn, Bonn (Germany); Marras, A. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Mozzanica, A. [Paul-Scherrer-Institute (PSI), Villigen (Switzerland); Poehlsen, J. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Schmitt, B. [Paul-Scherrer-Institute (PSI), Villigen (Switzerland); Schwandt, J. [University of Hamburg, Hamburg (Germany); Sheviakov, I. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); and others

2016-12-01

The AGIPD (adaptive gain integrating pixel detector) detector is a high frame rate (4.5 MHz) and high dynamic range (up to 10{sup 4} ·12.4 keV photons) detector with single photon resolution (down to 4 keV taking 5σ as limit and lowest noise settings) developed for the European XFEL (XFEL.EU). This work is focused on the characterization of AGIPD1.0, which is the first full scale version of the chip. The chip is 64×64 pixels and each pixel has a size of 200×200 μm{sup 2}. Each pixel can store up to 352 images at a rate of 4.5 MHz (corresponding to 220 ns). A detailed characterization of the AGIPD1.0 chip has been performed in order to assess the main performance of the ASIC in terms of gain, noise, speed and dynamic range. From the measurements presented in this paper a good uniformity of the gain, a noise around 320 e{sup −} (rms) in standard mode and around 240 e{sup −} (rms) in high gain mode has been measured. Furthermore a detailed discussion about the non-linear behavior after the gain switching is presented with both experimental results and simulations.

An ultra-high-speed direct digital frequency synthesizer implemented in GaAs HBT technology

International Nuclear Information System (INIS)

Chen Gaopeng; Wu Danyu; Jin Zhi; Liu Xinyu

2010-01-01

This paper presents a 10-GHz 8-bit direct digital synthesizer (DDS) microwave monolithic integrated circuit implemented in 1 μm GaAs HBT technology. The DDS takes a double-edge-trigger (DET) 8-stage pipeline accumulator with sine-weighted DAC-based ROM-less architecture, which can maximize the utilization ratio of the GaAs HBT's high-speed potential. With an output frequency up to 5 GHz, the DDS gives an average spurious free dynamic range of 23.24 dBc through the first Nyquist band, and consumes 2.4 W of DC power from a single -4.6 V DC supply. Using 1651 GaAs HBT transistors, the total area of the DDS chip is 2.4 x 2.0 mm 2 . (semiconductor integrated circuits)

An engineer's guide to automated testing of high-speed interfaces

CERN Document Server

Moreira, Jose

2010-01-01

Providing a complete introduction to the state-of-the-art in high-speed digital testing with automated test equipment (ATE), this practical resource is the first book focus exclusively on this increasingly important topic. Featuring clear examples, this one-stop reference covers all critical aspects of the subject, from high-speed digital basics, ATE instrumentation for digital applications, and test and measurements, to production testing, support instrumentation and text fixture design. This in-depth volume also discusses at advanced ATE topics, such as multiplexing of ATE pin channels and t

Highly sensitive bacterial susceptibility test against penicillin using parylene-matrix chip.

Science.gov (United States)

Park, Jong-Min; Kim, Jo-Il; Song, Hyun-Woo; Noh, Joo-Yoon; Kang, Min-Jung; Pyun, Jae-Chul

2015-09-15

This work presented a highly sensitive bacterial antibiotic susceptibility test through β-lactamase assay using Parylene-matrix chip. β-lactamases (EC 3.5.2.6) are an important family of enzymes that confer resistance to β-lactam antibiotics by catalyzing the hydrolysis of these antibiotics. Here we present a highly sensitive assay to quantitate β-lactamase-mediated hydrolysis of penicillin into penicilloic acid. Typically, MALDI-TOF mass spectrometry has been used to quantitate low molecular weight analytes and to discriminate them from noise peaks of matrix fragments that occur at low m/z ratios (m/ztest was carried out using Parylene-matrix chip and MALDI-TOF mass spectrometry. The Parylene-matrix chip was successfully used to quantitate penicillin (m/z: [PEN+H](+)=335.1 and [PEN+Na](+)=357.8) and penicilloic acid (m/z: [PA+H](+)=353.1) in a β-lactamase assay with minimal interference of low molecular weight noise peaks. The β-lactamase assay was carried out with an antibiotic-resistant E. coli strain and an antibiotic-susceptible E. coli strain, revealing that the minimum number of E. coli cells required to screen for antibiotic resistance was 1000 cells for the MALDI-TOF mass spectrometry/Parylene-matrix chip assay. Copyright © 2015 Elsevier B.V. All rights reserved.

Ceramic thermal wind sensor based on advanced direct chip attaching package

International Nuclear Information System (INIS)

Zhou Lin; Qin Ming; Chen Shengqi; Chen Bei

2014-01-01

An advanced direct chip attaching packaged two-dimensional ceramic thermal wind sensor is studied. The thermal wind sensor chip is fabricated by metal lift-off processes on the ceramic substrate. An advanced direct chip attaching (DCA) packaging is adopted and this new packaged method simplifies the processes of packaging further. Simulations of the advanced DCA packaged sensor based on computational fluid dynamics (CFD) model show the sensor can detect wind speed and direction effectively. The wind tunnel testing results show the advanced DCA packaged sensor can detect the wind direction from 0° to 360° and wind speed from 0 to 20 m/s with the error less than 0.5 m/s. The nonlinear fitting based least square method in Matlab is used to analyze the performance of the sensor. (semiconductor devices)

Modern trends in designing high-speed trains

Directory of Open Access Journals (Sweden)

Golubović Snežana D.

2015-01-01

Full Text Available Increased advantages of railway transportation systems over other types of transportation systems in the past sixty years have been a result of an intensive development of the new generations of high-speed trains. Not only do these types of trains comply with the need for increased speed of transportation and make the duration of the journey shorter, but they also meet the demands for increased reliability, safety and direct application of energy efficiency to the transportation system itself. Along with increased train speed, the motion resistance is increased as well, whereby at speeds over 200 km/h the proportion of air resistance becomes the most dominant member. One of the most efficient measures for reducing air resistance, as well as other negative consequences of high-speed motion, is the development of the aerodynamic shape of the train. This paper presents some construction solutions that affect the aerodynamic properties of high-speed trains, first and foremost, the nose shape, as well as the similarities and differences of individual subsystems necessary for the functioning of modern high-speed rail systems. We analysed two approaches to solving the problem of the aerodynamic shape of the train and the appropriate infrastructure using the examples of Japan and France. Two models of high-speed trains, Shinkansen (Japan and TGV, i.e. AGV (France, have been discussed.

AM06: the Associative Memory chip for the Fast TracKer in the upgraded ATLAS detector

CERN Document Server

Annovi, Alberto; The ATLAS collaboration; Calderini, Giovanni; Crescioli, Francesco

2016-01-01

\\abstract{This paper describes the AM06 chip, which is a highly parallel processor for pattern recognition in high energy physics experiments. It contains memory banks that store data organized in 18 bit words; a group of 8 words is called ``pattern''. Each AM06 chip can store up to 2$^{17}$ patterns. The AM06 integrates serializer/deserializer IP blocks at 2 Gbit/s for input/output communication, to avoid routing congestion at the board level. The AM06 is a complex chip. It has been designed in 65 nm CMOS, combining full-custom memory arrays, standard logic cells and IP blocks. It occupies a silicon area of 168 mm$^2$ and contains 421 millions transistors. The AM06 can perform bitwise comparison at a rate of 100 kHz. Thanks to the XORAM cell and to the design optimization, the AM06 consumes about 1 fJ/bit per comparison. The AM06 has been fabricated and successfully tested with a dedicated test system.

14 CFR 23.253 - High speed characteristics.

Science.gov (United States)

2010-01-01

... 14 Aeronautics and Space 1 2010-01-01 2010-01-01 false High speed characteristics. 23.253 Section... Requirements § 23.253 High speed characteristics. If a maximum operating speed VMO/MMO is established under § 23.1505(c), the following speed increase and recovery characteristics must be met: (a) Operating...

From Darwin to Internet at the speed of light

Science.gov (United States)

2002-11-01

Data moving around the Internet are like road traffic in that a car can be driven fast down a straight road but has to slow down a great deal when changing direction at a junction. The same thing happens on information highways. Beams of light carry data along fibre-optic cables at very high speeds. When the data arrive at computers, known as servers, the servers redirect them to their final destinations. Presently, you need to convert the light signals into electricity, and that slows everything down. Electrons move at a speed of a few kilometres per second through a circuit, whereas light travels at nearly 300 000 kilometres per second. Integrated optics would leave the data as light and simply channel it through the chip, in the right direction. Scientists call this area integrated optics, referring to the integrated circuit board on which chips are mounted. Instead of miniaturised electronics, however, miniaturised optics are placed on a microchip. ESA has a strategy to enable more sophisticated searches for extra-solar planets in the future. Two planned developments rely on combining the light from such planets in a number of different telescopes. These are the Darwin mission and its precursor, the ESA/ESO Ground-based European Nulling Interferometer Experiment (GENIE). When you combine light beams, you traditionally need moving mirrors and lenses to divert the light beams to where you want them. However, if the system moves, it can break. As Malcolm Fridlund, Project Scientist for Darwin and GENIE says, “To change to integrated optics, which is much smaller and has no moving parts, would be highly desirable.” Desirable certainly, but also difficult. At present, integrated optics is a science that is far behind integrated circuit technology. For this reason, ESA is funding two studies. Astrium has been asked to study a traditional optics approach and Alcatel is investigating an integrated-optics solution. “We shall take the decision on whether GENIE will

High speed data acquisition

International Nuclear Information System (INIS)

Cooper, P.S.

1997-07-01

A general introduction to high speed data acquisition system techniques in modern particle physics experiments is given. Examples are drawn from the SELEX(E78 1) high statistics charmed baryon production and decay experiment now taking data at Fermilab

Development of a high-throughput Candida albicans biofilm chip.

Directory of Open Access Journals (Sweden)

Anand Srinivasan

2011-04-01

Full Text Available We have developed a high-density microarray platform consisting of nano-biofilms of Candida albicans. A robotic microarrayer was used to print yeast cells of C. albicans encapsulated in a collagen matrix at a volume as low as 50 nL onto surface-modified microscope slides. Upon incubation, the cells grow into fully formed "nano-biofilms". The morphological and architectural complexity of these biofilms were evaluated by scanning electron and confocal scanning laser microscopy. The extent of biofilm formation was determined using a microarray scanner from changes in fluorescence intensities due to FUN 1 metabolic processing. This staining technique was also adapted for antifungal susceptibility testing, which demonstrated that, similar to regular biofilms, cells within the on-chip biofilms displayed elevated levels of resistance against antifungal agents (fluconazole and amphotericin B. Thus, results from structural analyses and antifungal susceptibility testing indicated that despite miniaturization, these biofilms display the typical phenotypic properties associated with the biofilm mode of growth. In its final format, the C. albicans biofilm chip (CaBChip is composed of 768 equivalent and spatially distinct nano-biofilms on a single slide; multiple chips can be printed and processed simultaneously. Compared to current methods for the formation of microbial biofilms, namely the 96-well microtiter plate model, this fungal biofilm chip has advantages in terms of miniaturization and automation, which combine to cut reagent use and analysis time, minimize labor intensive steps, and dramatically reduce assay costs. Such a chip should accelerate the antifungal drug discovery process by enabling rapid, convenient and inexpensive screening of hundreds-to-thousands of compounds simultaneously.

High speed non-latching squid binary ripple counter

International Nuclear Information System (INIS)

Silver, A.H.; Phillips, R.R.; Sandell, R.D.

1985-01-01

High speed, single flux quantum (SFQ) binary scalers are important components in superconducting analog-to-digital converters (ADC). This paper reviews the concept for a SQUID ADC and the design of an SFQ binary ripple counter, and reports the simulation of key components, and fabrication and performance of non-latching SQUID scalers and SFQ binary ripple counters. The SQUIDs were fabricated with Nb/Nb 2 O 5 /PbIn junctions and interconnected by monolithic superconducting transmission lines and isolation resistors. Each SQUID functioned as a bistable flip-flop with the input connected to the center of the device and the output across one junction. All junctions were critically damped to optimize the pulse response. Operation was verified by observing the dc I-V curves of successive SQUIDs driven by a cw pulse train generated on the same chip. Each SQUID exhibited constant-voltage current steps at 1/2 the voltage of the preceding device as expected from the Josephson voltage-to-frequency relation. Steps were observed only for the same voltage polarity of successive devices and for proper phase bias of the SQUID. Binary frequency division was recorded up to 40GHz for devices designed to operate to 28GHz

Research on single-chip microcomputer controlled rotating magnetic field mineralization model

Science.gov (United States)

Li, Yang; Qi, Yulin; Yang, Junxiao; Li, Na

2017-08-01

As one of the method of selecting ore, the magnetic separation method has the advantages of stable operation, simple process flow, high beneficiation efficiency and no chemical environment pollution. But the existing magnetic separator are more mechanical, the operation is not flexible, and can not change the magnetic field parameters according to the precision of the ore needed. Based on the existing magnetic separator is mechanical, the rotating magnetic field can be used for single chip microcomputer control as the research object, design and trial a rotating magnetic field processing prototype, and through the single-chip PWM pulse output to control the rotation of the magnetic field strength and rotating magnetic field speed. This method of using pure software to generate PWM pulse to control rotary magnetic field beneficiation, with higher flexibility, accuracy and lower cost, can give full play to the performance of single-chip.

Wake flow characteristics at high wind speed

DEFF Research Database (Denmark)

Aagaard Madsen, Helge; Larsen, Torben J.; Larsen, Gunner Chr.

2016-01-01

Wake flow characteristic at high wind speeds is the main subject of this paper. Although the wake losses decrease at high wind speeds it has been found in a recent study that for multiple wake inflow the increase in loading due to wake effects are substantial even at wind speeds well above rated ...

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Directory of Open Access Journals (Sweden)

Tooraj Nikoubin

2010-01-01

Full Text Available A new transistor sizing algorithm, SEA (Simple Exact Algorithm, for optimizing low-power and high-speed arithmetic integrated circuits is proposed. In comparison with other transistor sizing algorithms, simplicity, accuracy, independency of order and initial sizing factors of transistors, and flexibility in choosing the optimization parameters such as power consumption, delay, Power-Delay Product (PDP, chip area or the combination of them are considered as the advantages of this new algorithm. More exhaustive rules of grouping transistors are the main trait of our algorithm. Hence, the SEA algorithm dominates some major transistor sizing metrics such as optimization rate, simulation speed, and reliability. According to approximate comparison of the SEA algorithm with MDE and ADC for a number of conventional full adder circuits, delay and PDP have been improved 55.01% and 57.92% on an average, respectively. By comparing the SEA and Chang's algorithm, 25.64% improvement in PDP and 33.16% improvement in delay have been achieved. All the simulations have been performed with 0.13 m technology based on the BSIM3v3 model using HSpice simulator software.

The use of high-speed imaging in education

Science.gov (United States)

Kleine, H.; McNamara, G.; Rayner, J.

2017-02-01

Recent improvements in camera technology and the associated improved access to high-speed camera equipment have made it possible to use high-speed imaging not only in a research environment but also specifically for educational purposes. This includes high-speed sequences that are created both with and for a target audience of students in high schools and universities. The primary goal is to engage students in scientific exploration by providing them with a tool that allows them to see and measure otherwise inaccessible phenomena. High-speed imaging has the potential to stimulate students' curiosity as the results are often surprising or may contradict initial assumptions. "Live" demonstrations in class or student- run experiments are highly suitable to have a profound influence on student learning. Another aspect is the production of high-speed images for demonstration purposes. While some of the approaches known from the application of high speed imaging in a research environment can simply be transferred, additional techniques must often be developed to make the results more easily accessible for the targeted audience. This paper describes a range of student-centered activities that can be undertaken which demonstrate how student engagement and learning can be enhanced through the use of high speed imaging using readily available technologies.

High-speed elevators controlled by inverters

Energy Technology Data Exchange (ETDEWEB)

Sakai, Yoshio; Takahashi, Hideaki; Nakamura, Kiyoshi; Kinoshita, Hiroshi

1988-10-25

The super-high-speed elevator with superiority to 300m/min of speed, requires both the large capacity power and wide range speed controls. Therefore, in order to materialize the smooth and quiet operation characteristics, by applying the inverter control, the low torque ripple control in the low frequency range and high frequency large capacity inverting for lowering the motor in noise are necessary with their being assured of reliability. To satisfy the above necessary items, together with the development of a sine wave pulse width and frequency modulation (PWM/PFM) control system, to more precisely enable the sine wave electric current control, and 3kHz switching power converter, using a 800A power transistor module, a supervoltage control circuit under the extraordinary condition was designed. As a result of commercializing a 360m/min super-high speed inverter elevator, the power source unit, due to the effect of high power factor, could be reduced by 30% in capacity and also the higher harmonic wave including ratio could be considerably lowered to the inferiority to 5%. 2 references, 7 figures, 1 table.

Adiabatic shear banding and scaling laws in chip formation with application to cutting of Ti-6Al-4V

Science.gov (United States)

Molinari, A.; Soldani, X.; Miguélez, M. H.

2013-11-01

The phenomenon of adiabatic shear banding is analyzed theoretically in the context of metal cutting. The mechanisms of material weakening that are accounted for are (i) thermal softening and (ii) material failure related to a critical value of the accumulated plastic strain. Orthogonal cutting is viewed as a unique configuration where adiabatic shear bands can be experimentally produced under well controlled loading conditions by individually tuning the cutting speed, the feed (uncut chip thickness) and the tool geometry. The role of cutting conditions on adiabatic shear banding and chip serration is investigated by combining finite element calculations and analytical modeling. This leads to the characterization and classification of different regimes of shear banding and the determination of scaling laws which involve dimensionless parameters representative of thermal and inertia effects. The analysis gives new insights into the physical aspects of plastic flow instability in chip formation. The originality with respect to classical works on adiabatic shear banding stems from the various facets of cutting conditions that influence shear banding and from the specific role exercised by convective flow on the evolution of shear bands. Shear bands are generated at the tool tip and propagate towards the chip free surface. They grow within the chip formation region while being convected away by chip flow. It is shown that important changes in the mechanism of shear banding take place when the characteristic time of shear band propagation becomes equal to a characteristic convection time. Application to Ti-6Al-4V titanium are considered and theoretical predictions are compared to available experimental data in a wide range of cutting speeds and feeds. The fundamental knowledge developed in this work is thought to be useful not only for the understanding of metal cutting processes but also, by analogy, to similar problems where convective flow is also interfering with

Changes of indicators of high-speed and high-speed and power preparedness at volleyball players of 12–13 years old

Directory of Open Access Journals (Sweden)

Oleg Shevchenko

2016-04-01

Full Text Available Purpose: to define changes of indicators of high-speed and high-speed and power preparedness of volleyball players of 12–13 years old. Material & Methods: the test exercises, which are recommended by the training program of CYSS on volleyball, were used for the definition of the level of development of high-speed and high-speed and power abilities of volleyball players. 25 young volleyball players from the group of the previous basic preparation took part in the experiment. Sports experience of sportsmen is 3–4 years. The analysis of scientifically-methodical literature, pedagogical testing, pedagogical experiment, methods of mathematical statistics were carried out. Results: the analyzed level of high-speed and high-speed and power abilities of volleyball players. Conclusions: the results had reliable changes (t=2,2–2,4 at р<0,05 of the level of high-speed and high-speed and power abilities of volleyball players of 12–13years old in the experimental group at the end of the experiment, except run on 30 m that demonstrates a positive influence of application of special exercises in the educational-training process.

FASTBUS Readout Controller card for high speed data acquisition

International Nuclear Information System (INIS)

Zimmermann, S.

1991-10-01

This article describes a FASTBUS Readout Controller (FRC) for high speed data acquisition in FASTBUS based systems. The controller has two main interfaces: to FASTBUS and to a Readout Port. The FASTBUS interface performs FASTBUS master and slave operations at a maximum transfer rate exceeding 40 MBytes/s. The Readout Port can be adapted for a variety of protocols. Currently, it will be interfaced to a VME bus based processor with a VSB port. The on-board LR33000 embedded processor controls the readout, executing a list of operations download into its memory. It scans the FASTBUS modules and stores the data in a triple port DRAM (TPDRAM), through one of the Serial Access Memory (SAM) ports of the (TPDRAM). Later, it transfers this data to the readout port using the other SAM. The FRC also supports serial communication via RS232 and Ethernet interfaces. This device is intended for use in the data acquisition system at the Collider Detector at Fermilab. 5 refs., 3 figs

High speed ultra-broadband amplitude modulators with ultrahigh extinction >65 dB.

Science.gov (United States)

Liu, S; Cai, H; DeRose, C T; Davids, P; Pomerene, A; Starbuck, A L; Trotter, D C; Camacho, R; Urayama, J; Lentine, A

2017-05-15

We experimentally demonstrate ultrahigh extinction ratio (>65 dB) amplitude modulators (AMs) that can be electrically tuned to operate across a broad spectral range of 160 nm from 1480 - 1640 nm and 95 nm from 1280 - 1375 nm. Our on-chip AMs employ one extra coupler compared with conventional Mach-Zehnder interferometers (MZI), thus form a cascaded MZI (CMZI) structure. Either directional or adiabatic couplers are used to compose the CMZI AMs and experimental comparisons are made between these two different structures. We investigate the performance of CMZI AMs under extreme conditions such as using 95:5 split ratio couplers and unbalanced waveguide losses. Electro-optic phase shifters are also integrated in the CMZI AMs for high-speed operation. Finally, we investigate the output optical phase when the amplitude is modulated, which provides us valuable information when both amplitude and phase are to be controlled. Our demonstration not only paves the road to applications such as quantum information processing that requires high extinction ratio AMs but also significantly alleviates the tight fabrication tolerance needed for large-scale integrated photonics.

14 CFR 25.253 - High-speed characteristics.

Science.gov (United States)

2010-01-01

... 14 Aeronautics and Space 1 2010-01-01 2010-01-01 false High-speed characteristics. 25.253 Section...-speed characteristics. (a) Speed increase and recovery characteristics. The following speed increase and recovery characteristics must be met: (1) Operating conditions and characteristics likely to cause...

Associative Memory computing power and its simulation.

CERN Document Server

Volpi, G; The ATLAS collaboration

2014-01-01

The associative memory (AM) chip is ASIC device specifically designed to perform ``pattern matching'' at very high speed and with parallel access to memory locations. The most extensive use for such device will be the ATLAS Fast Tracker (FTK) processor, where more than 8000 chips will be installed in 128 VME boards, specifically designed for high throughput in order to exploit the chip's features. Each AM chip will store a database of about 130000 pre-calculated patterns, allowing FTK to use about 1 billion patterns for the whole system, with any data inquiry broadcast to all memory elements simultaneously within the same clock cycle (10 ns), thus data retrieval time is independent of the database size. Speed and size of the system are crucial for real-time High Energy Physics applications, such as the ATLAS FTK processor. Using 80 million channels of the ATLAS tracker, FTK finds tracks within 100 $\\mathrm{\\mu s}$. The simulation of such a parallelized system is an extremely complex task when executed in comm...

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

Science.gov (United States)

Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

2018-04-01

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

Application of oblique plane microscopy to high speed live cell imaging

Science.gov (United States)

Kumar, Sunil; Wilding, Dean; Sikkel, Markus B.; Lyon, Alexander R.; MacLeod, Ken T.; Dunsby, Chris

2011-07-01

Oblique Plane Microscopy (OPM) is a light sheet microscopy technique that combines oblique illumination with correction optics that tilt the focal plane of the collection system. OPM can be used to image conventionally mounted specimens on coverslips or tissue culture dishes and has low out-of-plane photobleaching and phototoxicity. No moving parts are required to achieve an optically sectioned image and so high speed optically sectioned imaging is possible. We present high speed 2D and 3D optically sectioned OPM imaging of live cells using a high NA water immersion lens.

High speed global shutter image sensors for professional applications

Science.gov (United States)

Wu, Xu; Meynants, Guy

2015-04-01

Global shutter imagers expand the use to miscellaneous applications, such as machine vision, 3D imaging, medical imaging, space etc. to eliminate motion artifacts in rolling shutter imagers. A low noise global shutter pixel requires more than one non-light sensitive memory to reduce the read noise. But larger memory area reduces the fill-factor of the pixels. Modern micro-lenses technology can compensate this fill-factor loss. Backside illumination (BSI) is another popular technique to improve the pixel fill-factor. But some pixel architecture may not reach sufficient shutter efficiency with backside illumination. Non-light sensitive memory elements make the fabrication with BSI possible. Machine vision like fast inspection system, medical imaging like 3D medical or scientific applications always ask for high frame rate global shutter image sensors. Thanks to the CMOS technology, fast Analog-to-digital converters (ADCs) can be integrated on chip. Dual correlated double sampling (CDS) on chip ADC with high interface digital data rate reduces the read noise and makes more on-chip operation control. As a result, a global shutter imager with digital interface is a very popular solution for applications with high performance and high frame rate requirements. In this paper we will review the global shutter architectures developed in CMOSIS, discuss their optimization process and compare their performances after fabrication.

Chicago-St. Louis high speed rail plan

International Nuclear Information System (INIS)

Stead, M.E.

1994-01-01

The Illinois Department of Transportation (IDOT), in cooperation with Amtrak, undertook the Chicago-St. Louis High Speed Rail Financial and Implementation Plan study in order to develop a realistic and achievable blueprint for implementation of high speed rail in the Chicago-St. Louis corridor. This report presents a summary of the Price Waterhouse Project Team's analysis and the Financial and Implementation Plan for implementing high speed rail service in the Chicago-St. Louis corridor

Chicago-St. Louis high speed rail plan

Energy Technology Data Exchange (ETDEWEB)

Stead, M.E.

1994-12-31

The Illinois Department of Transportation (IDOT), in cooperation with Amtrak, undertook the Chicago-St. Louis High Speed Rail Financial and Implementation Plan study in order to develop a realistic and achievable blueprint for implementation of high speed rail in the Chicago-St. Louis corridor. This report presents a summary of the Price Waterhouse Project Team`s analysis and the Financial and Implementation Plan for implementing high speed rail service in the Chicago-St. Louis corridor.

Design and FPGA-implementation of multilayer neural networks with on-chip learning

International Nuclear Information System (INIS)

Haggag, S.S.M.Y

2008-01-01

Artificial Neural Networks (ANN) is used in many applications in the industry because of their parallel structure, high speed, and their ability to give easy solution to complicated problems. For example identifying the orange and apple in the sorting machine with neural network is easier than using image processing techniques to do the same thing. There are different software for designing, training, and testing the ANN, but in order to use the ANN in the industry, it should be implemented on hardware outside the computer. Neural networks are artificial systems inspired on the brain's cognitive behavior, which can learn tasks with some degree of complexity, such as signal processing, diagnosis, robotics, image processing, and pattern recognition. Many applications demand a high computing power and the traditional software implementation are not sufficient.This thesis presents design and FPGA implementation of Multilayer Neural Networks with On-chip learning in re-configurable hardware. Hardware implementation of neural network algorithm is very interesting due their high performance and they can easily be made parallel. The architecture proposed herein takes advantage of distinct data paths for the forward and backward propagation stages and a pipelined adaptation of the on- line backpropagation algorithm to significantly improve the performance of the learning phase. The architecture is easily scalable and able to cope with arbitrary network sizes with the same hardware. The implementation is targeted diagnosis of the Research Reactor accidents to avoid the risk of occurrence of a nuclear accident. The proposed designed circuits are implemented using Xilinx FPGA Chip XC40150xv and occupied 73% of Chip CLBs. It achieved 10.8 μs to take decision in the forward propagation compared with current software implemented of RPS which take 24 ms. The results show that the proposed architecture leads to significant speed up comparing to high end software solutions. On-chip

NanoTopoChip: High-throughput nanotopographical cell instruction.

Science.gov (United States)

Hulshof, Frits F B; Zhao, Yiping; Vasilevich, Aliaksei; Beijer, Nick R M; de Boer, Meint; Papenburg, Bernke J; van Blitterswijk, Clemens; Stamatialis, Dimitrios; de Boer, Jan

2017-10-15

Surface topography is able to influence cell phenotype in numerous ways and offers opportunities to manipulate cells and tissues. In this work, we develop the Nano-TopoChip and study the cell instructive effects of nanoscale topographies. A combination of deep UV projection lithography and conventional lithography was used to fabricate a library of more than 1200 different defined nanotopographies. To illustrate the cell instructive effects of nanotopography, actin-RFP labeled U2OS osteosarcoma cells were cultured and imaged on the Nano-TopoChip. Automated image analysis shows that of many cell morphological parameters, cell spreading, cell orientation and actin morphology are mostly affected by the nanotopographies. Additionally, by using modeling, the changes of cell morphological parameters could by predicted by several feature shape parameters such as lateral size and spacing. This work overcomes the technological challenges of fabricating high quality defined nanoscale features on unprecedented large surface areas of a material relevant for tissue culture such as PS and the screening system is able to infer nanotopography - cell morphological parameter relationships. Our screening platform provides opportunities to identify and study the effect of nanotopography with beneficial properties for the culture of various cell types. The nanotopography of biomaterial surfaces can be modified to influence adhering cells with the aim to improve the performance of medical implants and tissue culture substrates. However, the necessary knowledge of the underlying mechanisms remains incomplete. One reason for this is the limited availability of high-resolution nanotopographies on relevant biomaterials, suitable to conduct systematic biological studies. The present study shows the fabrication of a library of nano-sized surface topographies with high fidelity. The potential of this library, called the 'NanoTopoChip' is shown in a proof of principle HTS study which

Lubrication and cooling for high speed gears

Science.gov (United States)

Townsend, D. P.

1985-01-01

The problems and failures occurring with the operation of high speed gears are discussed. The gearing losses associated with high speed gearing such as tooth mesh friction, bearing friction, churning, and windage are discussed with various ways shown to help reduce these losses and thereby improve efficiency. Several different methods of oil jet lubrication for high speed gearing are given such as into mesh, out of mesh, and radial jet lubrication. The experiments and analytical results for the various methods of oil jet lubrication are shown with the strengths and weaknesses of each method discussed. The analytical and experimental results of gear lubrication and cooling at various test conditions are presented. These results show the very definite need of improved methods of gear cooling at high speed and high load conditions.

High-sensitivity low-noise miniature fluxgate magnetometers using a flip chip conceptual design.

Science.gov (United States)

Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

2014-07-30

This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current "flip chip" concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or "responsivity" for magnetometers) and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz) magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz(1/2) at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market.

Artificial neural networks contribution to the operational security of embedded systems. Artificial neural networks contribution to fault tolerance of on-board functions in space environment

International Nuclear Information System (INIS)

Vintenat, Lionel

1999-01-01

A good quality often attributed to artificial neural networks is fault tolerance. In general presentation works, this property is almost always introduced as 'natural', i.e. being obtained without any specific precaution during learning. Besides, space environment is known to be aggressive towards on-board hardware, inducing various abnormal operations. Particularly, digital components suffer from upset phenomenon, i.e. misplaced switches of memory flip-flops. These two observations lead to the question: would neural chips constitute an interesting and robust solution to implement some board functions of spacecrafts? First, the various aspects of the problem are detailed: artificial neural networks and their fault tolerance, neural chips, space environment and resulting failures. Further to this presentation, a particular technique to carry out neural chips is selected because of its simplicity, and especially because it requires few memory flip-flops: random pulse streams. An original method for star recognition inside a field-of-view is then proposed for the board function 'attitude computation'. This method relies on a winner-takes-all competition network, and on a Kohonen self-organized map. An hardware implementation of those two neural models is then proposed using random pulse streams. Thanks to this realization, on one hand difficulties related to that particular implementation technique can be highlighted, and on the other hand a first evaluation of its practical fault tolerance can be carried out. (author) [fr

High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip

Science.gov (United States)

Issadore, David; Franke, Thomas; Brown, Keith A.; Hunt, Thomas P.; Westervelt, Robert M.

2010-01-01

A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm2 in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip’s surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications. PMID:20625468

High - speed steel for precise cased tools

International Nuclear Information System (INIS)

Karwiarz, J.; Mazur, A.

2001-01-01

The test results of high-vanadium high - speed steel (SWV9) for precise casted tools are presented. The face -milling cutters of NFCa80A type have been tested in industrial operating conditions. An average life - time of SWV9 steel tools was 3-10 times longer compare to the conventional high - speed milling cutters. Metallography of SWB9 precise casted steel revealed beneficial for tool properties distribution of primary vanadium carbides in the steel matrix. Presented results should be a good argument for wide application of high - vanadium high - speed steel for precise casted tools. (author)

A 16X16 Discrete Cosine Transform Chip

Science.gov (United States)

Sun, M. T.; Chen, T. C.; Gottlieb, A.; Wu, L.; Liou, M. L.

1987-10-01

Among various transform coding techniques for image compression the Discrete Cosine Transform (DCT) is considered to be the most effective method and has been widely used in the laboratory as well as in the market, place. DCT is computationally intensive. For video application at 14.3 MHz sample rate, a direct implementation of a 16x16 DCT requires a throughput, rate of approximately half a billion multiplications per second. In order to reduce the cost of hardware implementation, a single chip DCT implementation is highly desirable. In this paper, the implementation of a 16x16 DCT chip using a concurrent architecture will be presented. The chip is designed for real-time processing of 14.3 MHz sampled video data. It uses row-column decomposition to implement the two-dimensional transform. Distributed arithmetic combined with hit-serial and hit-parallel structures is used to implement the required vector inner products concurrently. Several schemes are utilized to reduce the size of required memory. The resultant circuit only uses memory, shift registers, and adders. No multipliers are required. It achieves high speed performance with a very regular and efficient integrated circuit realization. The chip accepts 0-bit input and produces 14-bit DCT coefficients. 12 bits are maintained after the first one-dimensional transform. The circuit has been laid out using a 2-μm CMOS technology with a symbolic design tool MULGA. The core contains approximately 73,000 transistors in an area of 7.2 x 7.0

Aerodynamic design on high-speed trains

Science.gov (United States)

Ding, San-San; Li, Qiang; Tian, Ai-Qin; Du, Jian; Liu, Jia-Li

2016-04-01

Compared with the traditional train, the operational speed of the high-speed train has largely improved, and the dynamic environment of the train has changed from one of mechanical domination to one of aerodynamic domination. The aerodynamic problem has become the key technological challenge of high-speed trains and significantly affects the economy, environment, safety, and comfort. In this paper, the relationships among the aerodynamic design principle, aerodynamic performance indexes, and design variables are first studied, and the research methods of train aerodynamics are proposed, including numerical simulation, a reduced-scale test, and a full-scale test. Technological schemes of train aerodynamics involve the optimization design of the streamlined head and the smooth design of the body surface. Optimization design of the streamlined head includes conception design, project design, numerical simulation, and a reduced-scale test. Smooth design of the body surface is mainly used for the key parts, such as electric-current collecting system, wheel truck compartment, and windshield. The aerodynamic design method established in this paper has been successfully applied to various high-speed trains (CRH380A, CRH380AM, CRH6, CRH2G, and the Standard electric multiple unit (EMU)) that have met expected design objectives. The research results can provide an effective guideline for the aerodynamic design of high-speed trains.

Reducing Heating In High-Speed Cinematography

Science.gov (United States)

Slater, Howard A.

1989-01-01

Infrared-absorbing and infrared-reflecting glass filters simple and effective means for reducing rise in temperature during high-speed motion-picture photography. "Hot-mirror" and "cold-mirror" configurations, employed in projection of images, helps prevent excessive heating of scenes by powerful lamps used in high-speed photography.

Genome-wide association study for milking speed in French Holstein cows

DEFF Research Database (Denmark)

Marete, Andrew Gitahi; Sahana, Goutam; Fritz, Sebastian

2018-01-01

Using a combination of data from the BovineSNP50 BeadChip SNP array (Illumina, San Diego, CA) and a EuroGenomics (Amsterdam, the Netherlands) custom single nucleotide polymorphism (SNP) chip with SNP pre-selected from whole genome sequence data, we carried out an association study of milking speed...... associated with milking speed. As clinical mastitis and somatic cell score have an unfavorable genetic correlation with milking speed, we tested whether the most significant SNP on these 22 chromosomes associated with milking speed were also associated with clinical mastitis or somatic cell score. Nine...... hundred seventy-one genome-wide significant SNP were associated with milking speed. Of these, 86 were associated with clinical mastitis and 198 with somatic cell score. The most significant association signals for milking speed were observed on chromosomes 7, 8, 10, 14, and 18. The most significant signal...

An Automatic Baseline Regulation in a Highly Integrated Receiver Chip for JUNO

Science.gov (United States)

Muralidharan, P.; Zambanini, A.; Karagounis, M.; Grewing, C.; Liebau, D.; Nielinger, D.; Robens, M.; Kruth, A.; Peters, C.; Parkalian, N.; Yegin, U.; van Waasen, S.

2017-09-01

This paper describes the data processing unit and an automatic baseline regulation of a highly integrated readout chip (Vulcan) for JUNO. The chip collects data continuously at 1 Gsamples/sec. The Primary data processing which is performed in the integrated circuit can aid to reduce the memory and data processing efforts in the subsequent stages. In addition, a baseline regulator compensating a shift in the baseline is described.

Mixed-signal early vision chip with embedded image and programming memories and digital I/O

Science.gov (United States)

Linan-Cembrano, Gustavo; Rodriguez-Vazquez, Angel; Dominguez-Castro, Rafael; Espejo, Servando

2003-04-01

From a system level perspective, this paper presents a 128x128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35μm standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (~7bit) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330GOPs (Giga Operations per second), and uses the power supply (180GOP/Joule) and the silicon area (3.8 GOPS/mm2) efficiently, as it is able to maintain VGA processing throughputs of 100Frames/s with about 15 basic image processing tasks on each frame.

ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

International Nuclear Information System (INIS)

Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

2002-01-01

An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

Prototype detection unit for the CHIPS experiment

Science.gov (United States)

Pfützner, Maciej M.

2017-09-01

CHIPS (CHerenkov detectors In mine PitS) is an R&D project aiming to develop novel cost-effective neutrino detectors, focused on measuring the CP-violating neutrino mixing phase (δ CP). A single detector module, containing an enclosed volume of purified water, would be submerged in an existing lake, located in a neutrino beam. A staged approach is proposed with first detectors deployed in a flooded mine pit in Northern Minnesota, 7 mrad off-axis from the existing NuMI beam. A small proof-of-principle model (CHIPS-M) has already been tested and the first stage of a fully functional 10 kt module (CHIPS-10) is planned for 2018. One of the instruments submerged on board of CHIPS-M in autumn 2015 was a prototype detection unit, constructed at Nikhef. The unit contains hardware borrowed from the KM3NeT experiment, including 16 3 inch photomultiplier tubes and readout electronics. In addition to testing the mechanical design and data acquisition, the detector was used to record a large sample of cosmic ray muon events. The collected data is valuable for characterising the cosmic muon background and validating a Monte Carlo simulation used to optimise future designs. This paper introduces the CHIPS project, describes the design of the prototype unit, and presents the results of a preliminary data analysis.

Perils of using speed zone data to assess real-world compliance to speed limits.

Science.gov (United States)

Chevalier, Anna; Clarke, Elizabeth; Chevalier, Aran John; Brown, Julie; Coxon, Kristy; Ivers, Rebecca; Keay, Lisa

2017-11-17

Real-world driving studies, including those involving speeding alert devices and autonomous vehicles, can gauge an individual vehicle's speeding behavior by comparing measured speed with mapped speed zone data. However, there are complexities with developing and maintaining a database of mapped speed zones over a large geographic area that may lead to inaccuracies within the data set. When this approach is applied to large-scale real-world driving data or speeding alert device data to determine speeding behavior, these inaccuracies may result in invalid identification of speeding. We investigated speeding events based on service provider speed zone data. We compared service provider speed zone data (Speed Alert by Smart Car Technologies Pty Ltd., Ultimo, NSW, Australia) against a second set of speed zone data (Google Maps Application Programming Interface [API] mapped speed zones). We found a systematic error in the zones where speed limits of 50-60 km/h, typical of local roads, were allocated to high-speed motorways, which produced false speed limits in the speed zone database. The result was detection of false-positive high-range speeding. Through comparison of the service provider speed zone data against a second set of speed zone data, we were able to identify and eliminate data most affected by this systematic error, thereby establishing a data set of speeding events with a high level of sensitivity (a true positive rate of 92% or 6,412/6,960). Mapped speed zones can be a source of error in real-world driving when examining vehicle speed. We explored the types of inaccuracies found within speed zone data and recommend that a second set of speed zone data be utilized when investigating speeding behavior or developing mapped speed zone data to minimize inaccuracy in estimates of speeding.

High speed VLSI neural network for high energy physics

NARCIS (Netherlands)

Masa, P.; Masa, P.; Hoen, K.; Hoen, Klaas; Wallinga, Hans

1994-01-01

A CMOS neural network IC is discussed which was designed for very high speed applications. The parallel architecture, analog computing and digital weight storage provides unprecedented computing speed combined with ease of use. The circuit classifies up to 70 dimensional vectors within 20

Adaptation of superconducting fault current limiter to high-speed reclosing

International Nuclear Information System (INIS)

Koyama, T.; Yanabu, S.

2009-01-01

Using a high temperature superconductor, we constructed and tested a model superconducting fault current limiter (SFCL). The superconductor might break in some cases because of its excessive generation of heat. Therefore, it is desirable to interrupt early the current that flows to superconductor. So, we proposed the SFCL using an electromagnetic repulsion switch which is composed of a superconductor, a vacuum interrupter and a by-pass coil, and its structure is simple. Duration that the current flow in the superconductor can be easily minimized to the level of less than 0.5 cycle using this equipment. On the other hand, the fault current is also easily limited by large reactance of the parallel coil. There is duty of high-speed reclosing after interrupting fault current in the electric power system. After the fault current is interrupted, the back-up breaker is re-closed within 350 ms. So, the electromagnetic repulsion switch should return to former state and the superconductor should be recovered to superconducting state before high-speed reclosing. Then, we proposed the SFCL using an electromagnetic repulsion switch which employs our new reclosing function. We also studied recovery time of the superconductor, because superconductor should be recovered to superconducting state within 350 ms. In this paper, the recovery time characteristics of the superconducting wire were investigated. Also, we combined the superconductor with the electromagnetic repulsion switch, and we did performance test. As a result, a high-speed reclosing within 350 ms was proven to be possible.

The Time Lens Concept Applied to Ultra-High-Speed OTDM Signal Processing

DEFF Research Database (Denmark)

Clausen, Anders; Palushani, Evarist; Mulvad, Hans Christian Hansen

2013-01-01

This survey paper presents some of the applications where the versatile time-lens concept successfully can be applied to ultra-high-speed serial systems by offering expected needed functionalities for future optical communication networks.......This survey paper presents some of the applications where the versatile time-lens concept successfully can be applied to ultra-high-speed serial systems by offering expected needed functionalities for future optical communication networks....

A 6.25 Gb/s equalizer in 0.18 μm CMOS technology for high-speed SerDes

International Nuclear Information System (INIS)

Zhang Mingke; Hu Qingsheng

2013-01-01

This paper presents a 0.18 μm CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer (FFE) and a two-tap half-rate decision feedback equalizer (DFE) in order to cancel both pre-cursor and post-cursor ISI. By employing an active-inductive peaking circuit for the delay line, the bandwidth of the FFE is increased and the area cost is minimized. CML-based circuits such as DFFs, summers and multiplexes all help to improve the speed of DFEs. Measurement results illustrate that the equalizer operates well when equalizing 6.25 Gb/s data is passed over a 30-inch channel with a loss of 22 dB and consumes 55.8 mW with the supply voltage of 1.8 V. The overall chip area including pads is 0.3 × 0.5 mm 2 . (semiconductor integrated circuits)

Fish and chips: implementation of a neural network model into computer chips to maximize swimming efficiency in autonomous underwater vehicles.

Science.gov (United States)

Blake, R W; Ng, H; Chan, K H S; Li, J

2008-09-01

Recent developments in the design and propulsion of biomimetic autonomous underwater vehicles (AUVs) have focused on boxfish as models (e.g. Deng and Avadhanula 2005 Biomimetic micro underwater vehicle with oscillating fin propulsion: system design and force measurement Proc. 2005 IEEE Int. Conf. Robot. Auto. (Barcelona, Spain) pp 3312-7). Whilst such vehicles have many potential advantages in operating in complex environments (e.g. high manoeuvrability and stability), limited battery life and payload capacity are likely functional disadvantages. Boxfish employ undulatory median and paired fins during routine swimming which are characterized by high hydromechanical Froude efficiencies (approximately 0.9) at low forward speeds. Current boxfish-inspired vehicles are propelled by a low aspect ratio, 'plate-like' caudal fin (ostraciiform tail) which can be shown to operate at a relatively low maximum Froude efficiency (approximately 0.5) and is mainly employed as a rudder for steering and in rapid swimming bouts (e.g. escape responses). Given this and the fact that bioinspired engineering designs are not obligated to wholly duplicate a biological model, computer chips were developed using a multilayer perception neural network model of undulatory fin propulsion in the knifefish Xenomystus nigri that would potentially allow an AUV to achieve high optimum values of propulsive efficiency at any given forward velocity, giving a minimum energy drain on the battery. We envisage that externally monitored information on flow velocity (sensory system) would be conveyed to the chips residing in the vehicle's control unit, which in turn would signal the locomotor unit to adopt kinematics (e.g. fin frequency, amplitude) associated with optimal propulsion efficiency. Power savings could protract vehicle operational life and/or provide more power to other functions (e.g. communications).

High-speed and high-fidelity system and method for collecting network traffic

Science.gov (United States)

Weigle, Eric H [Los Alamos, NM

2010-08-24

A system is provided for the high-speed and high-fidelity collection of network traffic. The system can collect traffic at gigabit-per-second (Gbps) speeds, scale to terabit-per-second (Tbps) speeds, and support additional functions such as real-time network intrusion detection. The present system uses a dedicated operating system for traffic collection to maximize efficiency, scalability, and performance. A scalable infrastructure and apparatus for the present system is provided by splitting the work performed on one host onto multiple hosts. The present system simultaneously addresses the issues of scalability, performance, cost, and adaptability with respect to network monitoring, collection, and other network tasks. In addition to high-speed and high-fidelity network collection, the present system provides a flexible infrastructure to perform virtually any function at high speeds such as real-time network intrusion detection and wide-area network emulation for research purposes.

Piezoresistive microcantilever based lab-on-a-chip system for detection of macronutrients in the soil

Science.gov (United States)

Patkar, Rajul S.; Ashwin, Mamta; Rao, V. Ramgopal

2017-12-01

Monitoring of soil nutrients is very important in precision agriculture. In this paper, we have demonstrated a micro electro mechanical system based lab-on-a-chip system for detection of various soil macronutrients which are available in ionic form K+, NO3-, and H2PO4-. These sensors are highly sensitive piezoresistive silicon microcantilevers coated with a polymer matrix containing methyltridodecylammonium nitrate ionophore/ nitrate ionophore VI for nitrate sensing, 18-crown-6 ether for potassium sensing and Tributyltin chloride for phosphate detection. A complete lab-on-a-chip system integrating a highly sensitive current excited Wheatstone's bridge based portable electronic setup along with arrays of microcantilever devices mounted on a printed circuit board with a liquid flow cell for on the site experimentation for soil test has been demonstrated.

A novel on-chip high to low voltage power conversion circuit

International Nuclear Information System (INIS)

Wang Hui; Wang Songlin; Mou Zaixin; Guo Baolong; Lai Xinquan; Ye Qiang; Li Xianrui

2009-01-01

A novel power supply transform technique for high voltage IC based on the TSMC 0.6 μm BCD process is achieved. An adjustable bandgap voltage reference is presented which is different from the traditional power supply transform technique. It can be used as an internal power supply for high voltage IC by using the push-pull output stage to enhance its load capability. High-order temperature compensated circuit is designed to ensure the precision of the reference. Only 0.01 mm 2 area is occupied using this novel power supply technique. Compared with traditional technique, 50% of the area is saved, 40% quiescent power loss is decreased, and the temperature coefficient of the reference is only 4.48 ppm/deg. C. Compared with the traditional LDO (low dropout) regulator, this power conversion architecture does not need external output capacitance and decreases the chip-pin and external components, so the PCB area and design cost are also decreased. The testing results show that this circuit works well.

A novel on-chip high to low voltage power conversion circuit

Energy Technology Data Exchange (ETDEWEB)

Wang Hui; Wang Songlin; Mou Zaixin; Guo Baolong [Institute of Mechano-electronic Engineering, Xidian University, Xi' an 71007 (China); Lai Xinquan; Ye Qiang; Li Xianrui, E-mail: whui94@126.co [Institute of Electronic CAD, Xidian University, Xi' an 710071 (China)

2009-03-15

A novel power supply transform technique for high voltage IC based on the TSMC 0.6 mum BCD process is achieved. An adjustable bandgap voltage reference is presented which is different from the traditional power supply transform technique. It can be used as an internal power supply for high voltage IC by using the push-pull output stage to enhance its load capability. High-order temperature compensated circuit is designed to ensure the precision of the reference. Only 0.01 mm{sup 2} area is occupied using this novel power supply technique. Compared with traditional technique, 50% of the area is saved, 40% quiescent power loss is decreased, and the temperature coefficient of the reference is only 4.48 ppm/deg. C. Compared with the traditional LDO (low dropout) regulator, this power conversion architecture does not need external output capacitance and decreases the chip-pin and external components, so the PCB area and design cost are also decreased. The testing results show that this circuit works well.

Mechanisms and FEM Simulation of Chip Formation in Orthogonal Cutting In-Situ TiB₂/7050Al MMC.

Science.gov (United States)

Xiong, Yifeng; Wang, Wenhu; Jiang, Ruisong; Lin, Kunyang; Shao, Mingwei

2018-04-15

The in-situ TiB₂/7050Al composite is a new kind of Al-based metal matrix composite (MMC) with super properties, such as low density, improved strength, and wear resistance. This paper, for a deep insight into its cutting performance, involves a study of the chip formation process and finite element simulation during orthogonal cutting in-situ TiB₂/7050Al MMC. With chips, material properties, cutting forces, and tool geometry parameters, the Johnson-Cook (J-C) constitutive equation of in-situ TiB₂/7050Al composite was established. Then, the cutting simulation model was established by applying the Abaqus-Explicit method, and the serrated chip, shear plane, strain rate, and temperature were analyzed. The experimental and simulation results showed that the obtained material's constitutive equation was of high reliability, and the saw-tooth chips occurred commonly under either low or high cutting speed and small or large feed rate. From result analysis, it was found that the mechanisms of chip formation included plastic deformation, adiabatic shear, shearing slip, and crack extension. In addition, it was found that the existence of small, hard particles reduced the ductility of the MMC and resulted in segmental chips.

Feature-Learning-Based Printed Circuit Board Inspection via Speeded-Up Robust Features and Random Forest

Directory of Open Access Journals (Sweden)

Eun Hye Yuk

2018-06-01

Full Text Available With the coming of the 4th industrial revolution era, manufacturers produce high-tech products. As the production process is refined, inspection technologies become more important. Specifically, the inspection of a printed circuit board (PCB, which is an indispensable part of electronic products, is an essential step to improve the quality of the process and yield. Image processing techniques are utilized for inspection, but there are limitations because the backgrounds of images are different and the kinds of defects increase. In order to overcome these limitations, methods based on machine learning have been used recently. These methods can inspect without a normal image by learning fault patterns. Therefore, this paper proposes a method can detect various types of defects using machine learning. The proposed method first extracts features through speeded-up robust features (SURF, then learns the fault pattern and calculates probabilities. After that, we generate a weighted kernel density estimation (WKDE map weighted by the probabilities to consider the density of the features. Because the probability of the WKDE map can detect an area where the defects are concentrated, it improves the performance of the inspection. To verify the proposed method, we apply the method to PCB images and confirm the performance of the method.

Full-frame, high-speed 3D shape and deformation measurements using stereo-digital image correlation and a single color high-speed camera

Science.gov (United States)

Yu, Liping; Pan, Bing

2017-08-01

Full-frame, high-speed 3D shape and deformation measurement using stereo-digital image correlation (stereo-DIC) technique and a single high-speed color camera is proposed. With the aid of a skillfully designed pseudo stereo-imaging apparatus, color images of a test object surface, composed of blue and red channel images from two different optical paths, are recorded by a high-speed color CMOS camera. The recorded color images can be separated into red and blue channel sub-images using a simple but effective color crosstalk correction method. These separated blue and red channel sub-images are processed by regular stereo-DIC method to retrieve full-field 3D shape and deformation on the test object surface. Compared with existing two-camera high-speed stereo-DIC or four-mirror-adapter-assisted singe-camera high-speed stereo-DIC, the proposed single-camera high-speed stereo-DIC technique offers prominent advantages of full-frame measurements using a single high-speed camera but without sacrificing its spatial resolution. Two real experiments, including shape measurement of a curved surface and vibration measurement of a Chinese double-side drum, demonstrated the effectiveness and accuracy of the proposed technique.

Gate Drive For High Speed, High Power IGBTs

Energy Technology Data Exchange (ETDEWEB)

Nguyen, M.N.; Cassel, R.L.; de Lamare, J.E.; Pappas, G.C.; /SLAC

2007-06-18

A new gate drive for high-voltage, high-power IGBTs has been developed for the SLAC NLC (Next Linear Collider) Solid State Induction Modulator. This paper describes the design and implementation of a driver that allows an IGBT module rated at 800A/3300V to switch up to 3000A at 2200V in 3{micro}S with a rate of current rise of more than 10000A/{micro}S, while still being short circuit protected. Issues regarding fast turn on, high de-saturation voltage detection, and low short circuit peak current will be presented. A novel approach is also used to counter the effect of unequal current sharing between parallel chips inside most high-power IGBT modules. It effectively reduces the collector-emitter peak current, and thus protects the IGBT from being destroyed during soft short circuit conditions at high di/dt.

Gate Drive For High Speed, High Power IGBTs

International Nuclear Information System (INIS)

Nguyen, M.N.; Cassel, R.L.; de Lamare, J.E.; Pappas, G.C.; SLAC

2007-01-01

A new gate drive for high-voltage, high-power IGBTs has been developed for the SLAC NLC (Next Linear Collider) Solid State Induction Modulator. This paper describes the design and implementation of a driver that allows an IGBT module rated at 800A/3300V to switch up to 3000A at 2200V in 3(micro)S with a rate of current rise of more than 10000A/(micro)S, while still being short circuit protected. Issues regarding fast turn on, high de-saturation voltage detection, and low short circuit peak current will be presented. A novel approach is also used to counter the effect of unequal current sharing between parallel chips inside most high-power IGBT modules. It effectively reduces the collector-emitter peak current, and thus protects the IGBT from being destroyed during soft short circuit conditions at high di/dt

Flip chip assembly of thinned chips for hybrid pixel detector applications

CERN Document Server

Fritzsch, T; Woehrmann, M; Rothermund, M; Huegging, F; Ehrmann, O; Oppermann, H; Lang, K.D

2014-01-01

There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump depo...

Modular integration of electronics and microfluidic systems using flexible printed circuit boards.

Science.gov (United States)

Wu, Amy; Wang, Lisen; Jensen, Erik; Mathies, Richard; Boser, Bernhard

2010-02-21

Microfluidic systems offer an attractive alternative to conventional wet chemical methods with benefits including reduced sample and reagent volumes, shorter reaction times, high-throughput, automation, and low cost. However, most present microfluidic systems rely on external means to analyze reaction products. This substantially adds to the size, complexity, and cost of the overall system. Electronic detection based on sub-millimetre size integrated circuits (ICs) has been demonstrated for a wide range of targets including nucleic and amino acids, but deployment of this technology to date has been limited due to the lack of a flexible process to integrate these chips within microfluidic devices. This paper presents a modular and inexpensive process to integrate ICs with microfluidic systems based on standard printed circuit board (PCB) technology to assemble the independently designed microfluidic and electronic components. The integrated system can accommodate multiple chips of different sizes bonded to glass or PDMS microfluidic systems. Since IC chips and flex PCB manufacturing and assembly are industry standards with low cost, the integrated system is economical for both laboratory and point-of-care settings.

Highly expressed loci are vulnerable to misleading ChIP localization of multiple unrelated proteins

NARCIS (Netherlands)

Teytelman, L.; Thurtle, D.M.; Rine, J.; van Oudenaarden, A.

2013-01-01

Chromatin immunoprecipitation (ChIP) is the gold-standard technique for localizing nuclear proteins in the genome. We used ChIP, in combination with deep sequencing (Seq), to study the genome-wide distribution of the Silent information regulator (Sir) complex in Saccharomyces cerevisiae. We analyzed

Flip chip assembly of thinned chips for hybrid pixel detector applications

International Nuclear Information System (INIS)

Fritzsch, T; Zoschke, K; Rothermund, M; Oppermann, H; Woehrmann, M; Ehrmann, O; Lang, K D; Huegging, F

2014-01-01

There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump deposition process the glass-readout chip stack is diced in one step. Finally the glass carrier chip is released by laser illumination after flip chip assembly of the readout chip onto sensor tile. The results of the flip chip assembly process development for the ATLAS IBL upgrade are described more in detail. The new ATLAS FEI4B chip with a size of 20 × 19 mm 2 is flip chip bonded with a thickness of only 150 μm, but the capability of this technology has been demonstrated on hybrid modules with a reduced readout chip thickness of down to 50 μm which is a major step for ultra-thin electronic systems

Interfacing Lab-on-a-Chip Embryo Technology with High-Definition Imaging Cytometry.

Science.gov (United States)

Zhu, Feng; Hall, Christopher J; Crosier, Philip S; Wlodkowic, Donald

2015-08-01

To spearhead deployment of zebrafish embryo biotests in large-scale drug discovery studies, automated platforms are needed to integrate embryo in-test positioning and immobilization (suitable for high-content imaging) with fluidic modules for continuous drug and medium delivery under microperfusion to developing embryos. In this work, we present an innovative design of a high-throughput three-dimensional (3D) microfluidic chip-based device for automated immobilization and culture and time-lapse imaging of developing zebrafish embryos under continuous microperfusion. The 3D Lab-on-a-Chip array was fabricated in poly(methyl methacrylate) (PMMA) transparent thermoplastic using infrared laser micromachining, while the off-chip interfaces were fabricated using additive manufacturing processes (fused deposition modelling and stereolithography). The system's design facilitated rapid loading and immobilization of a large number of embryos in predefined clusters of traps during continuous microperfusion of drugs/toxins. It was conceptually designed to seamlessly interface with both upright and inverted fluorescent imaging systems and also to directly interface with conventional microtiter plate readers that accept 96-well plates. Compared with the conventional Petri dish assays, the chip-based bioassay was much more convenient and efficient as only small amounts of drug solutions were required for the whole perfusion system running continuously over 72 h. Embryos were spatially separated in the traps that assisted tracing single embryos, preventing interembryo contamination and improving imaging accessibility.

A new circuit for at-speed scan SoC testing

International Nuclear Information System (INIS)

Lin Wei; Shi Wenlong

2013-01-01

It is very important to detect transition-delay faults and stuck-at faults in system on chip (SoC) under 90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing method. In this paper, an on-chip clock (OCC) controller with a bypass function based on an internal phase-locked loop is designed to test faults in SoC. Furthermore, a clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by automatic test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by using the Synopsys tool and the correctness of the design is verified. The result shows that the design of an at-speed scan test in this paper is highly efficient for detecting timing-related defects. Finally, the 89.29% transition-delay fault coverage and the 94.50% stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design. (semiconductor integrated circuits)

High-speed ground transportation development outside United States

Energy Technology Data Exchange (ETDEWEB)

Eastham, T.R. [Queen`s Univ., Kingston, Ontario (United Kingdom)

1995-09-01

This paper surveys the state of high-speed (in excess of 200 km/h) ground-transportation developments outside the United States. Both high-speed rail and Maglev systems are covered. Many vehicle systems capable of providing intercity service in the speed range 200--500 km/h are or will soon be available. The current state of various technologies, their implementation, and the near-term plans of countries that are most active in high-speed ground transportation development are reported.

High speed laser tomography system

Science.gov (United States)

Samsonov, D.; Elsaesser, A.; Edwards, A.; Thomas, H. M.; Morfill, G. E.

2008-03-01

A high speed laser tomography system was developed capable of acquiring three-dimensional (3D) images of optically thin clouds of moving micron-sized particles. It operates by parallel-shifting an illuminating laser sheet with a pair of galvanometer-driven mirrors and synchronously recording two-dimensional (2D) images of thin slices of the imaged volume. The maximum scanning speed achieved was 120000slices/s, sequences of 24 volume scans (up to 256 slices each) have been obtained. The 2D slices were stacked to form 3D images of the volume, then the positions of the particles were identified and followed in the consecutive scans. The system was used to image a complex plasma with particles moving at speeds up to cm/s.

A Historical Review of High Speed Metal Forming

OpenAIRE

Zittel, G.

2010-01-01

This paper will present a Historical Review of High Speed Metal Forming beginning with the first thought of forming metal by using an electromagnetic impulse to today, whereby High Speed Metal Forming is an accepted production process. Although this paper will briefly cover the basic physics of the process, it will not dwell on it. It will rather show how the industrial acceptance of High Speed Metal Forming is tightly connected to the knowledge acquired from many applications studies. These ...

Review of High-Speed Fiber Optic Grating Sensors Systems

Energy Technology Data Exchange (ETDEWEB)

Udd, E; Benterou, J; May, C; Mihailov, S J; Lu, P

2010-03-24

Fiber grating sensors can be used to support a wide variety of high speed measurement applications. This includes measurements of vibrations on bridges, traffic monitoring on freeways, ultrasonic detection to support non-destructive tests on metal plates and providing details of detonation events. This paper provides a brief overview of some of the techniques that have been used to support high speed measurements using fiber grating sensors over frequency ranges from 10s of kHz, to MHZ and finally toward frequencies approaching the GHz regime. Very early in the development of fiber grating sensor systems it was realized that a high speed fiber grating sensor system could be realized by placing an optical filter that might be a fiber grating in front of a detector so that spectral changes in the reflection from a fiber grating were amplitude modulated. In principal the only limitation on this type of system involved the speed of the output detector which with the development of high speed communication links moved from the regime of 10s of MHz toward 10s of GHz. The earliest deployed systems involved civil structures including measurements of the strain fields on composite utility poles and missile bodies during break tests, bridges and freeways. This was followed by a series of developments that included high speed fiber grating sensors to support nondestructive testing via ultrasonic wave detection, high speed machining and monitoring ship hulls. Each of these applications involved monitoring mechanical motion of structures and thus interest was in speeds up to a few 10s of MHz. Most recently there has been interest in using fiber grating to monitor the very high speed events such as detonations and this has led to utilization of fiber gratings that are consumed during an event that may require detection speeds of hundreds of MHz and in the future multiple GHz.

Pay as You Speed, ISA with incentives for not speeding

DEFF Research Database (Denmark)

Lahrmann, Harry Spaabæk; Agerholm, Niels; Tradisauskas, Nerius

2012-01-01

The Intelligent Speed Adaptation (ISA) project we describe in this article is based on Pay as You Drive principles. These principles assume that the ISA equipment informs a driver of the speed limit, warns the driver when speeding and calculates penalty points. Each penalty point entails the redu......The Intelligent Speed Adaptation (ISA) project we describe in this article is based on Pay as You Drive principles. These principles assume that the ISA equipment informs a driver of the speed limit, warns the driver when speeding and calculates penalty points. Each penalty point entails...... the reduction of a 30% discount on the driver's car insurance premium, which therefore produced the name, Pay as You Speed. The ISA equipment consists of a GPS-based On Board Unit with a mobile phone connection to a web server. The project was planned for a three-year test period with 300 young car drivers...

High-speed data acquisition with the Solaris and Linux operating systems

International Nuclear Information System (INIS)

Zilker, M.; Heimann, P.

2000-01-01

In this paper, we discuss whether Solaris and Linux are suitable for data acquisition systems in soft real time conditions. As an example we consider a plasma diagnostic (Mirnov coils), which collects data for a complete plasma discharge of about 10 s from up to 72 channels. Each ADC-Channel generates a data stream of 4 MB/s. To receive these data streams an eight-channel Hotlink PCI interface board was designed. With a prototype system using Solaris and the driver developed by us we investigate important properties of the operating system such as the I/O performance and scheduling of processes. We compare the Solaris operating system on the Ultra Sparc platform with Linux on the Intel platform. Finally, some points of user program development are mentioned to show how the application can make the most efficient use of the underlying high-speed I/O system

On-chip high-voltage generator design design methodology for charge pumps

CERN Document Server

Tanzawa, Toru

2016-01-01

This book provides various design techniques for switched-capacitor on-chip high-voltage generators, including charge pump circuits, regulators, level shifters, references, and oscillators.  Readers will see these techniques applied to system design in order to address the challenge of how the on-chip high-voltage generator is designed for Flash memories, LCD drivers, and other semiconductor devices to optimize the entire circuit area and power efficiency with a low voltage supply, while minimizing the cost.  This new edition includes a variety of useful updates, including coverage of power efficiency and comprehensive optimization methodologies for DC-DC voltage multipliers, modeling of extremely low voltage Dickson charge pumps, and modeling and optimum design of AC-DC switched-capacitor multipliers for energy harvesting and power transfer for RFID.

Tractor performance monitor based on a single-chip microcomputer

Energy Technology Data Exchange (ETDEWEB)

Bedri, A.R.; Marley, S.J.; Buchelle, W.F.; Smay, T.A.

1981-01-01

A tractor performance monitor based on a single-chip microcomputer was developed to measure ground speed, slip, fuel consumption (rate and total), total area, theoretical time, and total time. Transducers used are presented in detail. 5 refs.

A Full Mesh ATCA-based General Purpose Data Processing Board: Pulsar II

CERN Document Server

Olsen, J; Okumura, Y

2014-01-01

High luminosity conditions at the LHC pose many unique challenges for potential silicon based track trigger systems. Among those challenges is data formatting, where hits from thousands of silicon modules must first be shared and organized into overlapping trigger towers. Other challenges exist for Level-1 track triggers, where many parallel data paths may be used for 5 high speed time multiplexed data transfers. Communication between processing nodes requires high bandwidth, low latency, and flexible real time data sharing, for which a full mesh backplane is a natural fit. A custom full mesh enabled ATCA board called the Pulsar II has been designed with the goal of creating a scalable architecture abundant in flexible, non-blocking, high bandwidth board- to-board communication channels while keeping the design as simple as possible.

FE-I4 pixel chip characterization with USBpix3 test system

Energy Technology Data Exchange (ETDEWEB)

Filimonov, Viacheslav; Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Janssen, Jens; Krueger, Hans; Pohl, David-Leon; Wermes, Norbert [University of Bonn, Bonn (Germany)

2015-07-01

The USBpix readout system is a small and light weighting test system for the ATLAS pixel readout chips. It is widely used to operate and characterize FE-I4 pixel modules in lab and test beam environments. For multi-chip modules the resources on the Multi-IO board, that is the central control unit of the readout system, are coming to their limits, which makes the simultaneous readout of more than one chip at a time challenging. Therefore an upgrade of the current USBpix system has been developed. The upgraded system is called USBpix3 - the main focus of the talk. Characterization of single chip FE-I4 modules was performed with USBpix3 prototype (digital, analog, threshold and source scans; tuning). PyBAR (Bonn ATLAS Readout in Python scripting language) was used as readout software. PyBAR consists of FEI4 DAQ and Data Analysis Libraries in Python. The presentation describes the USBpix3 system, results of FE-I4 modules characterization and preparation for the multi-chip module and multi-module readout with USBpix3.

High-speed photography. Technique and evolution

International Nuclear Information System (INIS)

Sanchez-Tembleque, R.

1981-01-01

It is intended to present some general considerations about ''Higg-speed photography'' as a tool of work common in mos research laboratories in the world. ''High-speed photography'' relies on the principles of photography of actions, that change rapidly with the time. The evolution of this technique goes along with the discovering of new phenomena in wich higher speeds are involved. At present is normal to deal with changing rates involving picoseconds times (10 -12 s) and new developments on the field of femtosecond (10 -15 s) theoretically are contemplated. (author)

TARGET: A multi-channel digitizer chip for very-high-energy gamma-ray telescopes

Energy Technology Data Exchange (ETDEWEB)

Bechtol, K.; Funk, S.; /Stanford U., HEPL /KIPAC, Menlo Park; Okumura, A.; /JAXA, Sagamihara /Stanford U., HEPL /KIPAC, Menlo Park; Ruckman, L.; /Hawaii U.; Simons, A.; Tajima, H.; Vandenbroucke, J.; /Stanford U., HEPL /KIPAC, Menlo Park; Varner, G.; /Hawaii U.

2011-08-11

The next-generation very-high-energy (VHE) gamma-ray observatory, the Cherenkov Telescope Array, will feature dozens of imaging atmospheric Cherenkov telescopes (IACTs), each with thousands of pixels of photosensors. To be affordable and reliable, reading out such a mega-channel array requires event recording technology that is highly integrated and modular, with a low cost per channel. We present the design and performance of a chip targeted to this application: the TeV Array Readout with GSa/s sampling and Event Trigger (TARGET). This application-specific integrated circuit (ASIC) has 16 parallel input channels, a 4096-sample buffer for each channel, adjustable input termination, self-trigger functionality, and tight window-selected readout. We report the performance of TARGET in terms of sampling frequency, power consumption, dynamic range, current-mode gain, analog bandwidth, and cross talk. The large number of channels per chip allows a low cost per channel ($10 to $20 including front-end and back-end electronics but not including photosensors) to be achieved with a TARGET-based IACT readout system. In addition to basic performance parameters of the TARGET chip itself, we present a camera module prototype as well as a second-generation chip (TARGET 2), both of which have been produced.

High-speed three-dimensional plasma temperature determination of axially symmetric free-burning arcs

International Nuclear Information System (INIS)

Bachmann, B; Ekkert, K; Bachmann, J-P; Marques, J-L; Schein, J; Kozakov, R; Gött, G; Schöpp, H; Uhrlandt, D

2013-01-01

In this paper we introduce an experimental technique that allows for high-speed, three-dimensional determination of electron density and temperature in axially symmetric free-burning arcs. Optical filters with narrow spectral bands of 487.5–488.5 nm and 689–699 nm are utilized to gain two-dimensional spectral information of a free-burning argon tungsten inert gas arc. A setup of mirrors allows one to image identical arc sections of the two spectral bands onto a single camera chip. Two-different Abel inversion algorithms have been developed to reconstruct the original radial distribution of emission coefficients detected with each spectral window and to confirm the results. With the assumption of local thermodynamic equilibrium we calculate emission coefficients as a function of temperature by application of the Saha equation, the ideal gas law, the quasineutral gas condition and the NIST compilation of spectral lines. Ratios of calculated emission coefficients are compared with measured ones yielding local plasma temperatures. In the case of axial symmetry the three-dimensional plasma temperature distributions have been determined at dc currents of 100, 125, 150 and 200 A yielding temperatures up to 20000 K in the hot cathode region. These measurements have been validated by four different techniques utilizing a high-resolution spectrometer at different positions in the plasma. Plasma temperatures show good agreement throughout the different methods. Additionally spatially resolved transient plasma temperatures have been measured of a dc pulsed process employing a high-speed frame rate of 33000 frames per second showing the modulation of the arc isothermals with time and providing information about the sensitivity of the experimental approach. (paper)

High-speed parallel implementation of a modified PBR algorithm on DSP-based EH topology

Science.gov (United States)

Rajan, K.; Patnaik, L. M.; Ramakrishna, J.

1997-08-01

Algebraic Reconstruction Technique (ART) is an age-old method used for solving the problem of three-dimensional (3-D) reconstruction from projections in electron microscopy and radiology. In medical applications, direct 3-D reconstruction is at the forefront of investigation. The simultaneous iterative reconstruction technique (SIRT) is an ART-type algorithm with the potential of generating in a few iterations tomographic images of a quality comparable to that of convolution backprojection (CBP) methods. Pixel-based reconstruction (PBR) is similar to SIRT reconstruction, and it has been shown that PBR algorithms give better quality pictures compared to those produced by SIRT algorithms. In this work, we propose a few modifications to the PBR algorithms. The modified algorithms are shown to give better quality pictures compared to PBR algorithms. The PBR algorithm and the modified PBR algorithms are highly compute intensive, Not many attempts have been made to reconstruct objects in the true 3-D sense because of the high computational overhead. In this study, we have developed parallel two-dimensional (2-D) and 3-D reconstruction algorithms based on modified PBR. We attempt to solve the two problems encountered by the PBR and modified PBR algorithms, i.e., the long computational time and the large memory requirements, by parallelizing the algorithm on a multiprocessor system. We investigate the possible task and data partitioning schemes by exploiting the potential parallelism in the PBR algorithm subject to minimizing the memory requirement. We have implemented an extended hypercube (EH) architecture for the high-speed execution of the 3-D reconstruction algorithm using the commercially available fast floating point digital signal processor (DSP) chips as the processing elements (PEs) and dual-port random access memories (DPR) as channels between the PEs. We discuss and compare the performances of the PBR algorithm on an IBM 6000 RISC workstation, on a Silicon

High-Speed Non-Volatile Optical Memory: Achievements and Challenges

Directory of Open Access Journals (Sweden)

Vadym Zayets

2017-01-01

Full Text Available We have proposed, fabricated, and studied a new design of a high-speed optical non-volatile memory. The recoding mechanism of the proposed memory utilizes a magnetization reversal of a nanomagnet by a spin-polarized photocurrent. It was shown experimentally that the operational speed of this memory may be extremely fast above 1 TBit/s. The challenges to realize both a high-speed recording and a high-speed reading are discussed. The memory is compact, integratable, and compatible with present semiconductor technology. If realized, it will advance data processing and computing technology towards a faster operation speed.

Transportable GPU (General Processor Units) chip set technology for standard computer architectures

Science.gov (United States)

Fosdick, R. E.; Denison, H. C.

1982-11-01

The USAFR-developed GPU Chip Set has been utilized by Tracor to implement both USAF and Navy Standard 16-Bit Airborne Computer Architectures. Both configurations are currently being delivered into DOD full-scale development programs. Leadless Hermetic Chip Carrier packaging has facilitated implementation of both architectures on single 41/2 x 5 substrates. The CMOS and CMOS/SOS implementations of the GPU Chip Set have allowed both CPU implementations to use less than 3 watts of power each. Recent efforts by Tracor for USAF have included the definition of a next-generation GPU Chip Set that will retain the application-proven architecture of the current chip set while offering the added cost advantages of transportability across ISO-CMOS and CMOS/SOS processes and across numerous semiconductor manufacturers using a newly-defined set of common design rules. The Enhanced GPU Chip Set will increase speed by an approximate factor of 3 while significantly reducing chip counts and costs of standard CPU implementations.

High-speed AFM of human chromosomes in liquid

Energy Technology Data Exchange (ETDEWEB)

Picco, L M; Dunton, P G; Ulcinas, A; Engledew, D J; Miles, M J [H H Wills Physics Laboratory and IRC in Nanotechnology, University of Bristol, Tyndall Avenue, Bristol BS8 1TL (United Kingdom); Hoshi, O; Ushiki, T [Division of Microscopic Anatomy and Bio-Imaging, Department of Cellular Function, Niigata University Graduate School of Medical and Dental Sciences, Asahimachi-Dori 1, Niigata, 951-8150 (Japan)], E-mail: m.j.miles@bristol.ac.uk

2008-09-24

Further developments of the previously reported high-speed contact-mode AFM are described. The technique is applied to the imaging of human chromosomes at video rate both in air and in water. These are the largest structures to have been imaged with high-speed AFM and the first imaging in liquid to be reported. A possible mechanism that allows such high-speed contact-mode imaging without significant damage to the sample is discussed in the context of the velocity dependence of the measured lateral force on the AFM tip.

Price of forest chips decreasing

International Nuclear Information System (INIS)

Hakkila, P.

2001-01-01

Use of forest chips was studied in 1999 in the national Puuenergia (Wood Energy) research program. Wood combusting heating plants were questioned about are the main reasons restricting the increment of the use of forest chips. Heating plants, which did not use forest chips at all or which used less than 250 m 3 (625 bulk- m 3 ) in 1999 were excluded. The main restrictions for additional use of forest chips were: too high price of forest chips; lack of suppliers and/or uncertainty of deliveries; technical problems of reception and processing of forest chips; insufficiency of boiler output especially in winter; and unsatisfactory quality of chips. The price of forest chips becomes relatively high because wood biomass used for production of forest chips has to be collected from wide area. Heavy equipment has to be used even though small fragments of wood are processed, which increases the price of chips. It is essential for forest chips that the costs can be pressed down because competition with fossil fuels, peat and industrial wood residues is hard. Low market price leads to the situation in which forest owner gets no price of the raw material, the entrepreneurs operate at the limit of profitability and renovation of machinery is difficult, and forest chips suppliers have to sell the chips at prime costs. Price of forest chips has decreased significantly during the past decade. Nominal price of forest chips is now lower than two decades ago. The real price of chips has decreased even more than the nominal price, 35% during the past decade and 20% during the last five years. Chips, made of small diameter wood, are expensive because the price includes the felling costs and harvesting is carried out at thinning lots. Price is especially high if chips are made of delimbed small diameter wood due to increased the work and reduced amount of chips. The price of logging residue chips is most profitable because cutting does not cause additional costs. Recovery of chips is

Chip-Oriented Fluorimeter Design and Detection System Development for DNA Quantification in Nano-Liter Volumes

Directory of Open Access Journals (Sweden)

Da-Sheng Lee

2009-12-01

Full Text Available The chip-based polymerase chain reaction (PCR system has been developed in recent years to achieve DNA quantification. Using a microstructure and miniature chip, the volume consumption for a PCR can be reduced to a nano-liter. With high speed cycling and a low reaction volume, the time consumption of one PCR cycle performed on a chip can be reduced. However, most of the presented prototypes employ commercial fluorimeters which are not optimized for fluorescence detection of such a small quantity sample. This limits the performance of DNA quantification, especially low experiment reproducibility. This study discusses the concept of a chip-oriented fluorimeter design. Using the analytical model, the current study analyzes the sensitivity and dynamic range of the fluorimeter to fit the requirements for detecting fluorescence in nano-liter volumes. Through the optimized processes, a real-time PCR on a chip system with only one nano-liter volume test sample is as sensitive as the commercial real-time PCR machine using the sample with twenty micro-liter volumes. The signal to noise (S/N ratio of a chip system for DNA quantification with hepatitis B virus (HBV plasmid samples is 3 dB higher. DNA quantification by the miniature chip shows higher reproducibility compared to the commercial machine with respect to samples of initial concentrations from 103 to 105 copies per reaction.

A novel high electrode count spike recording array using an 81,920 pixel transimpedance amplifier-based imaging chip.

Science.gov (United States)

Johnson, Lee J; Cohen, Ethan; Ilg, Doug; Klein, Richard; Skeath, Perry; Scribner, Dean A

2012-04-15

Microelectrode recording arrays of 60-100 electrodes are commonly used to record neuronal biopotentials, and these have aided our understanding of brain function, development and pathology. However, higher density microelectrode recording arrays of larger area are needed to study neuronal function over broader brain regions such as in cerebral cortex or hippocampal slices. Here, we present a novel design of a high electrode count picocurrent imaging array (PIA), based on an 81,920 pixel Indigo ISC9809 readout integrated circuit camera chip. While originally developed for interfacing to infrared photodetector arrays, we have adapted the chip for neuron recording by bonding it to microwire glass resulting in an array with an inter-electrode pixel spacing of 30 μm. In a high density electrode array, the ability to selectively record neural regions at high speed and with good signal to noise ratio are both functionally important. A critical feature of our PIA is that each pixel contains a dedicated low noise transimpedance amplifier (∼0.32 pA rms) which allows recording high signal to noise ratio biocurrents comparable to single electrode voltage amplifier recordings. Using selective sampling of 256 pixel subarray regions, we recorded the extracellular biocurrents of rabbit retinal ganglion cell spikes at sampling rates up to 7.2 kHz. Full array local electroretinogram currents could also be recorded at frame rates up to 100 Hz. A PIA with a full complement of 4 readout circuits would span 1cm and could acquire simultaneous data from selected regions of 1024 electrodes at sampling rates up to 9.3 kHz. Published by Elsevier B.V.

High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip

Directory of Open Access Journals (Sweden)

Hai Wang

2017-01-01

Full Text Available This paper presents the design and implementation of a new digital-to-time converter (DTC. The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL and integral nonlinearity (INL are −0.17~+0.13 LSB and −0.35~+0.62 LSB, respectively. This DTC builds coarse and fine Vernier delay lines constructed by programmable delay lines (PDLs to ensure high performance delay. Benefited by the close-loop feedback mechanism of the PDLs’ control module, the presented DTC has excellent voltage and temperature stability. What is more, the proposed DTC can be implemented in a single field programmable gate array (FPGA chip.

High Speed Blanking: An Experimental Method to Measure Induced Cutting Forces

OpenAIRE

GAUDILLIERE , Camille; Ranc , Nicolas; LARUE , Arnaud; MAILLARD , A; Lorong , Philippe

2013-01-01

Lien vers la version éditeur: http://link.springer.com/article/10.1007/s11340-013-9738-1; International audience; A new blanking process that involves punch speed up to 10 ms −1 has obvious advantages in increased productivity. However, the inherent dynamics of such a process makes it difficult to develop a practical high speed punch press. The fracture phenomenon governing the blanking process has to be well understood to correctly design the machine support and the tooling. To observe this ...

High-speed and intercity passenger rail testing strategy.

Science.gov (United States)

2013-05-01

This high-speed and intercity passenger rail (HSIPR) testing strategy addresses the requirements for testing of high-speed train sets and technology before introduction to the North American railroad system. The report documents the results of a surv...

Automation of a high-speed imaging setup for differential viscosity measurements

Science.gov (United States)

Hurth, C.; Duane, B.; Whitfield, D.; Smith, S.; Nordquist, A.; Zenhausern, F.

2013-12-01

We present the automation of a setup previously used to assess the viscosity of pleural effusion samples and discriminate between transudates and exudates, an important first step in clinical diagnostics. The presented automation includes the design, testing, and characterization of a vacuum-actuated loading station that handles the 2 mm glass spheres used as sensors, as well as the engineering of electronic Printed Circuit Board (PCB) incorporating a microcontroller and their synchronization with a commercial high-speed camera operating at 10 000 fps. The hereby work therefore focuses on the instrumentation-related automation efforts as the general method and clinical application have been reported earlier [Hurth et al., J. Appl. Phys. 110, 034701 (2011)]. In addition, we validate the performance of the automated setup with the calibration for viscosity measurements using water/glycerol standard solutions and the determination of the viscosity of an "unknown" solution of hydroxyethyl cellulose.

Automation of a high-speed imaging setup for differential viscosity measurements

Energy Technology Data Exchange (ETDEWEB)

Hurth, C.; Duane, B.; Whitfield, D.; Smith, S.; Nordquist, A.; Zenhausern, F. [Center for Applied Nanobioscience and Medicine, The University of Arizona College of Medicine, 425 N 5th Street, Phoenix, Arizona 85004 (United States)

2013-12-28

We present the automation of a setup previously used to assess the viscosity of pleural effusion samples and discriminate between transudates and exudates, an important first step in clinical diagnostics. The presented automation includes the design, testing, and characterization of a vacuum-actuated loading station that handles the 2 mm glass spheres used as sensors, as well as the engineering of electronic Printed Circuit Board (PCB) incorporating a microcontroller and their synchronization with a commercial high-speed camera operating at 10 000 fps. The hereby work therefore focuses on the instrumentation-related automation efforts as the general method and clinical application have been reported earlier [Hurth et al., J. Appl. Phys. 110, 034701 (2011)]. In addition, we validate the performance of the automated setup with the calibration for viscosity measurements using water/glycerol standard solutions and the determination of the viscosity of an “unknown” solution of hydroxyethyl cellulose.

Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits.

Science.gov (United States)

Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

2014-01-27

Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.

Combinatorial materials synthesis and high-throughput screening: an integrated materials chip approach to mapping phase diagrams and discovery and optimization of functional materials.

Science.gov (United States)

Xiang, X D

Combinatorial materials synthesis methods and high-throughput evaluation techniques have been developed to accelerate the process of materials discovery and optimization and phase-diagram mapping. Analogous to integrated circuit chips, integrated materials chips containing thousands of discrete different compositions or continuous phase diagrams, often in the form of high-quality epitaxial thin films, can be fabricated and screened for interesting properties. Microspot x-ray method, various optical measurement techniques, and a novel evanescent microwave microscope have been used to characterize the structural, optical, magnetic, and electrical properties of samples on the materials chips. These techniques are routinely used to discover/optimize and map phase diagrams of ferroelectric, dielectric, optical, magnetic, and superconducting materials.

High-speed PIV applied to the wake of the NASA CRM model in ETW at high Re-number stall conditions for sub- and transonic speeds

OpenAIRE

Konrath, Robert; Geisler, Reinhard; Otter, Dirk; Philipp, Florian; Ehlers, Hauke; Agocs, Janos; Quest, Jürgen

2015-01-01

Within the framework of the EU project ESWIRP the Particle Image Velocimetry (PIV) using high-speed camera and laser has been used to measure the turbulent flow in the wake of a stalled aircraft wing. The measurements took place on the Common Research Model (CRM) provided by NASA in the pressurized cryogenic European Transonic Wind tunnel (ETW). A specific cryo-PIV system has been used and adapted for using high-speed PIV components under the cryogenic conditions of the wind tunnel faci...

Highly specific detection of genetic modification events using an enzyme-linked probe hybridization chip.

Science.gov (United States)

Zhang, M Z; Zhang, X F; Chen, X M; Chen, X; Wu, S; Xu, L L

2015-08-10

The enzyme-linked probe hybridization chip utilizes a method based on ligase-hybridizing probe chip technology, with the principle of using thio-primers for protection against enzyme digestion, and using lambda DNA exonuclease to cut multiple PCR products obtained from the sample being tested into single-strand chains for hybridization. The 5'-end amino-labeled probe was fixed onto the aldehyde chip, and hybridized with the single-stranded PCR product, followed by addition of a fluorescent-modified probe that was then enzymatically linked with the adjacent, substrate-bound probe in order to achieve highly specific, parallel, and high-throughput detection. Specificity and sensitivity testing demonstrated that enzyme-linked probe hybridization technology could be applied to the specific detection of eight genetic modification events at the same time, with a sensitivity reaching 0.1% and the achievement of accurate, efficient, and stable results.

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

Directory of Open Access Journals (Sweden)

Nanjian Wu

2009-07-01

Full Text Available A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps. A prototype chip with 64 × 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mm Standard CMOS process. The area size of chip is 1.5 mm × 3.5 mm. Each pixel size is 9.5 μm × 9.5 μm and each processing element size is 23 μm × 29 μm. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

Integrated computer network high-speed parallel interface

International Nuclear Information System (INIS)

Frank, R.B.

1979-03-01

As the number and variety of computers within Los Alamos Scientific Laboratory's Central Computer Facility grows, the need for a standard, high-speed intercomputer interface has become more apparent. This report details the development of a High-Speed Parallel Interface from conceptual through implementation stages to meet current and future needs for large-scle network computing within the Integrated Computer Network. 4 figures

Packaging Technologies for High Temperature Electronics and Sensors

Science.gov (United States)

Chen, Liangyu; Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Spry, David J.; Meredith, Roger D.

2013-01-01

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

UniBoard: generic hardware for radio astronomy signal processing

Science.gov (United States)

Hargreaves, J. E.

2012-09-01

UniBoard is a generic high-performance computing platform for radio astronomy, developed as a Joint Research Activity in the RadioNet FP7 Programme. The hardware comprises eight Altera Stratix IV Field Programmable Gate Arrays (FPGAs) interconnected by a high speed transceiver mesh. Each FPGA is connected to two DDR3 memory modules and three external 10Gbps ports. In addition, a total of 128 low voltage differential input lines permit connection to external ADC cards. The DSP capability of the board exceeds 644E9 complex multiply-accumulate operations per second. The first production run of eight boards was distributed to partners in The Netherlands, France, Italy, UK, China and Korea in May 2011, with a further production runs completed in December 2011 and early 2012. The function of the board is determined by the firmware loaded into its FPGAs. Current applications include beamformers, correlators, digital receivers, RFI mitigation for pulsar astronomy, and pulsar gating and search machines The new UniBoard based correlator for the European VLBI network (EVN) uses an FX architecture with half the resources of the board devoted to station based processing: delay and phase correction and channelization, and half to the correlation function. A single UniBoard can process a 64MHz band from 32 stations, 2 polarizations, sampled at 8 bit. Adding more UniBoards can expand the total bandwidth of the correlator. The design is able to process both prerecorded and real time (eVLBI) data.

Development of ultra high speed photographic system using high repetition rate visible laser

International Nuclear Information System (INIS)

Lee, Jong Min; Cha, Byung Hun; Kim, Sung Ho; Kim, Jung Bog; Lim, Chang Hwan; Cha, Hyung Ki; Song, Kyu Seok; Lee, Byung Deok; Rhi, Jong Hoon; Baik, Dae Hyun; Han, Jae Min; Rho, Si Pyo; Lee, Byung Cheol; Jeong, Do Yung; Choi, An Seong; Jeong, Chan Ik; Park, Dae Ung; Jeong, Sung Min; Lee, Sang Kil; Kim, Heon Jun; Jang, Rae gak; Jo, Do Hun; Park, Min Young

1992-12-01

The goal of this project is to develop and commercialize a high speed photographic system equipped with a high repetition rate visible laser. The developed system provides the characteristics of high time resolution and large number of frames. The system consists of 10 W air cooled CVL or a 30 W water cooled CVL, a rotating drum-type high speed camera with the framing rate of 35,000 fps, and a automatic control device. The system has the performance of 10 nsec time resolution, 35,000 fps framing rate, and 250 picture frames. The high speed photographic systems are widely applied to the fields such as high-efficient engine development, high-speed vibration analysis, shock wave propagation study, flow visualization analysis, weapon development, etc. (Author)

Rat muscle blood flows during high-speed locomotion

International Nuclear Information System (INIS)

Armstrong, R.B.; Laughlin, M.H.

1985-01-01

We previously studied blood flow distribution within and among rat muscles as a function of speed from walking (15 m/min) through galloping (75 m/min) on a motor-driven treadmill. The results showed that muscle blood flows continued to increase as a function of speed through 75 m/min. The purpose of the present study was to have rats run up to maximal treadmill speeds to determine if blood flows in the muscles reach a plateau as a function of running speed over the animals normal range of locomotory speeds. Muscle blood flows were measured with radiolabeled microspheres at 1 min of running at 75, 90, and 105 m/min in male Sprague-Dawley rats. The data indicate that even at these relatively high treadmill speeds there was still no clear evidence of a plateau in blood flow in most of the hindlimb muscles. Flows in most muscles continued to increase as a function of speed. These observed patterns of blood flow vs. running speed may have resulted from the rigorous selection of rats that were capable of performing the high-intensity exercise and thus only be representative of a highly specific population of animals. On the other hand, the data could be interpreted to indicate that the cardiovascular potential during exercise is considerably higher in laboratory rats than has normally been assumed and that inadequate blood flow delivery to the muscles does not serve as a major limitation to their locomotory performance

Minimum Plate Thickness in High-Speed Craft

DEFF Research Database (Denmark)

Pedersen, Preben Terndrup; Zhang, Shengming

1998-01-01

The minimum plate thickness requirements specified by the classification societies for high-speed craft are supposed to ensure adequate resistance to impact loads such as collision with floating objects and objects falling on the deck. The paper presents analytical methods of describing such impact...... phenomena and proposes performance requirements instead of thickness requirements for hull panels in high-speed craft made of different building materials....

Pixel detector readout chip

CERN Multimedia

1991-01-01

Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

Characterizing speed-independence of high-level designs

DEFF Research Database (Denmark)

Kishinevsky, Michael; Staunstrup, Jørgen

1994-01-01

This paper characterizes the speed-independence of high-level designs. The characterization is a condition on the design description ensuring that the behavior of the design is independent of the speeds of its components. The behavior of a circuit is modeled as a transition system, that allows data...... types, and internal as well as external non-determinism. This makes it possible to verify the speed-independence of a design without providing an explicit realization of the environment. The verification can be done mechanically. A number of experimental designs have been verified including a speed-independent...

A high speed digital noise generator

Science.gov (United States)

Obrien, J.; Gaffney, B.; Liu, B.

In testing of digital signal processing hardware, a high speed pseudo-random noise generator is often required to simulate an input noise source to the hardware. This allows the hardware to be exercised in a manner analogous to actual operating conditions. In certain radar and communication environments, a noise generator operating at speeds in excess of 60 MHz may be required. In this paper, a method of generating high speed pseudo-random numbers from an arbitrarily specified distribution (Gaussian, Log-Normal, etc.) using a transformation from a uniform noise source is described. A noise generator operating at 80 MHz has been constructed. Different distributions can be readily obtained by simply changing the ROM set. The hardware and test results will be described. Using this approach, the generation of pseudo-random sequences with arbitrary distributions at word rates in excess of 200 MHz can be readily achieved.

Experimental investigation on the high chip rate of 2D incoherent optical CDMA system

Science.gov (United States)

Su, Guorui; Wang, Rong; Pu, Tao; Fang, Tao; Zheng, Jilin; Zhu, Huatao; Wu, Weijiang

2015-08-01

An innovative approach to realise high chip rate in OCDMA transmission system is proposed and experimentally investigation, the high chip rate is achieved through a 2-D wavelength-hopping time-spreading en/decoder based on the supercontinuum light source. The source used in the experiment is generated by high nonlinear optical fiber (HNLF), Erbium-doped fiber amplifier (EDFA) which output power is 26 dBm, and distributed feed-back laser diode which works in the gain switch state. The span and the flatness of the light source are 20 nm and 3 dB, respectively, after equalization of wavelength selective switch (WSS). The wavelength-hopping time-spreading coder can be changed 20 nm in the wavelength and 400 ps in the time, is consist of WSS and delay lines. Therefore, the experimental results show that the chip rate can achieve 500 Gchip/s, in the case of 2.5 Gbit/s, while keeping a bit error rate below forward error correction limit after 40 km transmission.

Development and applications of a multi-purpose digital controller with a System-on-Chip FPGA for accelerators

Energy Technology Data Exchange (ETDEWEB)

Kurimoto, Yoshinori, E-mail: kurimoto@post.j-parc.jp [High Energy Accelerator Research Organization (KEK), Ibaraki 319-1195 (Japan); Nakamura, Keigo [Department of Physics, Kyoto University, Kyoto 606-8502 (Japan)

2016-12-21

J-PARC Main Ring (MR) is a high intensity proton synchrotron which accelerates protons from 3 GeV to 30 GeV. It has operated at a beam intensity of 390 kW and an upgrade toward the megawatt rating is scheduled. For higher beam intensity, some of the accelerator components require more intelligent and complicated functions. To consolidate such functions among various components, we developed multi-purpose digital boards using a System-on-Chip Field-Programmable Gated Array (SoC FPGA). In this paper, we describe the details of our developed boards as well as their possible applications. As an application of the boards, we have successfully performed the measurement of the betatron amplitude function during beam acceleration in J-PARC MR. The experimental setup and results of the measurement are also described in detail.

A Lab-on-Chip Design for Miniature Autonomous Bio-Chemoprospecting Planetary Rovers

Science.gov (United States)

Santoli, S.

The performance of the so-called ` Lab-on-Chip ' devices, featuring micrometre size components and employed at present for carrying out in a very fast and economic way the extremely high number of sequence determinations required in genomic analyses, can be largely improved as to further size reduction, decrease of power consumption and reaction efficiency through development of nanofluidics and of nano-to-micro inte- grated systems. As is shown, such new technologies would lead to robotic, fully autonomous, microwatt consumption and complete ` laboratory on a chip ' units for accurate, fast and cost-effective astrobiological and planetary exploration missions. The theory and the manufacturing technologies for the ` active chip ' of a miniature bio/chemoprospecting planetary rover working on micro- and nanofluidics are investigated. The chip would include micro- and nanoreactors, integrated MEMS (MicroElectroMechanical System) components, nanoelectronics and an intracavity nanolaser for highly accurate and fast chemical analysis as an application of such recently introduced solid state devices. Nano-reactors would be able to strongly speed up reaction kinetics as a result of increased frequency of reactive collisions. The reaction dynamics may also be altered with respect to standard macroscopic reactors. A built-in miniature telemetering unit would connect a network of other similar rovers and a central, ground-based or orbiting control unit for data collection and transmission to an Earth-based unit through a powerful antenna. The development of the ` Lab-on-Chip ' concept for space applications would affect the economy of space exploration missions, as the rover's ` Lab-on-Chip ' development would link space missions with the ever growing terrestrial market and business concerning such devices, largely employed in modern genomics and bioinformatics, so that it would allow the recoupment of space mission costs.

Compressibility, turbulence and high speed flow

CERN Document Server

Gatski, Thomas B

2013-01-01

Compressibility, Turbulence and High Speed Flow introduces the reader to the field of compressible turbulence and compressible turbulent flows across a broad speed range, through a unique complimentary treatment of both the theoretical foundations and the measurement and analysis tools currently used. The book provides the reader with the necessary background and current trends in the theoretical and experimental aspects of compressible turbulent flows and compressible turbulence. Detailed derivations of the pertinent equations describing the motion of such turbulent flows is provided and an extensive discussion of the various approaches used in predicting both free shear and wall bounded flows is presented. Experimental measurement techniques common to the compressible flow regime are introduced with particular emphasis on the unique challenges presented by high speed flows. Both experimental and numerical simulation work is supplied throughout to provide the reader with an overall perspective of current tre...

Design of an Electro-Optic Modulator for High Speed Communications

Science.gov (United States)

Espinoza, David

The telecommunications and computer technology industries have been requiring higher communications speeds at all levels for devices, components and interconnected systems. Optical devices and optical interconnections are a viable alternative over other traditional technologies such as copper-based interconnections. Latency reductions can be achieved through the use of optical interconnections. Currently, a particular architecture for optical interconnections is being studied at the University of Colorado at Boulder in the EMT/NANO project, called Broadcast Optical Interconnects for Global Communication in Many-Core Chip Multiprocessor. As with most types of networks, including optical networks, one of the most important components are modulators. Therefore adequate design and fabrication techniques for modulators contribute to higher modulation rates which lead to improve the efficiency and reductions in the latency of the optical network. Electro-optical modulators are presented in this study as an alternative to achieve this end. In recent years, nonlinear optical (NLO) materials have been used for the fabrication of high-speed electro-optical modulators. Polymers doped with chromophores are an alternative among NLO materials because they can develop large electro-optic coefficients and low dielectric constants. These two factors are critical for achieving high-speed modulation rates. These polymer-based electro-optical modulators can be fabricated using standard laboratory techniques, such as polymer spin-coating onto substrates, UV bleaching to achieve a refractive index variation and poling techniques to align the chromophores in cured polymers. The design of the electro-optic modulators require the use of the optical parameters of the materials to be used. Therefore the characterization of these materials is a required previous step. This characterization is performed by the fabrication of chromophores-doped polymer samples and conducting transmission and

California statewide model for high-speed rail

OpenAIRE

Outwater, Maren; Tierney, Kevin; Bradley, Mark; Sall, Elizabeth; Kuppam, Arun; Modugala, Vamsee

2010-01-01

The California High Speed Rail Authority (CHSRA) and the Metropolitan Transportation Commission (MTC) have developed a new statewide model to support evaluation of high-speed rail alternatives in the State of California. This statewide model will also support future planning activities of the California Department of Transportation (Caltrans). The approach to this statewide model explicitly recognizes the unique characteristics of intraregional travel demand and interregional travel demand. A...

Route to one-step microstructure mold fabrication for PDMS microfluidic chip

Science.gov (United States)

Lv, Xiaoqing; Geng, Zhaoxin; Fan, Zhiyuan; Wang, Shicai; Su, Yue; Fang, Weihao; Pei, Weihua; Chen, Hongda

2018-04-01

The microstructure mold fabrication for PDMS microfluidic chip remains complex and time-consuming process requiring special equipment and protocols: photolithography and etching. Thus, a rapid and cost-effective method is highly needed. Comparing with the traditional microfluidic chip fabricating process based on the micro-electromechanical system (MEMS), this method is simple and easy to implement, and the whole fabrication process only requires 1-2 h. Different size of microstructure from 100 to 1000 μm was fabricated, and used to culture four kinds of breast cancer cell lines. Cell viability and morphology was assessed when they were cultured in the micro straight channels, micro square holes and the bonding PDMS-glass microfluidic chip. The experimental results indicate that the microfluidic chip is good and meet the experimental requirements. This method can greatly reduce the process time and cost of the microfluidic chip, and provide a simple and effective way for the structure design and in the field of biological microfabrications and microfluidic chips.

A vacuum manifold for rapid world-to-chip connectivity of complex PDMS microdevices.

Science.gov (United States)

Cooksey, Gregory A; Plant, Anne L; Atencia, Javier

2009-05-07

The lack of simple interfaces for microfluidic devices with a large number of inlets significantly limits production and utilization of these devices. In this article, we describe the fabrication of a reusable manifold that provides rapid world-to-chip connectivity. A vacuum network milled into a rigid manifold holds microdevices and prevents leakage of fluids injected into the device from ports in the manifold. A number of different manifold designs were explored, and all performed similarly, yielding an average of 100 kPa (15 psi) fluid holding pressure. The wide applicability of this manifold concept is demonstrated by interfacing with a 51-inlet microfluidic chip containing 144 chambers and hundreds of embedded pneumatic valves. Due to the speed of connectivity, the manifolds are ideal for rapid prototyping and are well suited to serve as "universal" interfaces.

Nugget Structure Evolution with Rotation Speed for High-Rotation-Speed Friction-Stir-Welded 6061 Aluminum Alloy

Science.gov (United States)

Zhang, H. J.; Wang, M.; Zhu, Z.; Zhang, X.; Yu, T.; Wu, Z. Q.

2018-03-01

High-rotation-speed friction stir welding (HRS-FSW) is a promising technique to reduce the welding loads during FSW and thus facilitates the application of FSW for in situ fabrication and repair. In this study, 6061 aluminum alloy was friction stir welded at high-rotation speeds ranging from 3000 to 7000 rpm at a fixed welding speed of 50 mm/min, and the effects of rotation speed on the nugget zone macro- and microstructures were investigated in detail in order to illuminate the process features. Temperature measurements during HRS-FSW indicated that the peak temperature did not increase consistently with rotation speed; instead, it dropped remarkably at 5000 rpm because of the lowering of material shear stress. The nugget size first increased with rotation speed until 5000 rpm and then decreased due to the change of the dominant tool/workpiece contact condition from sticking to sliding. At the rotation speed of 5000 rpm, where the weld material experienced weaker thermal effect and higher-strain-rate plastic deformation, the nugget exhibited relatively small grain size, large textural intensity, and high dislocation density. Consequently, the joint showed superior nugget hardness and simultaneously a slightly low tensile ductility.