Plasma processing for VLSI

CERN Document Server

Einspruch, Norman G

1984-01-01

VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

Artificial immune system algorithm in VLSI circuit configuration

Science.gov (United States)

Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

2017-08-01

In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

Compact MOSFET models for VLSI design

CERN Document Server

Bhattacharyya, A B

2009-01-01

Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

Design Implementation and Testing of a VLSI High Performance ASIC for Extracting the Phase of a Complex Signal

National Research Council Canada - National Science Library

Altmeyer, Ronald

2002-01-01

This thesis documents the research, circuit design, and simulation testing of a VLSI ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: (phi=tan/-1 (Q/1...

Embedded Processor Based Automatic Temperature Control of VLSI Chips

Directory of Open Access Journals (Sweden)

Narasimha Murthy Yayavaram

2009-01-01

Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

Opto-VLSI-based reconfigurable free-space optical interconnects architecture

DEFF Research Database (Denmark)

Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug

2007-01-01

is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

Memory Based Machine Intelligence Techniques in VLSI hardware

OpenAIRE

James, Alex Pappachen

2012-01-01

We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

Lithography for VLSI

CERN Document Server

Einspruch, Norman G

1987-01-01

VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

An efficient interpolation filter VLSI architecture for HEVC standard

Science.gov (United States)

Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

2015-12-01

The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

A novel VLSI processor for high-rate, high resolution spectroscopy

CERN Document Server

Pullia, Antonio; Gatti, E; Longoni, A; Buttler, W

2000-01-01

A novel time-variant VLSI shaper amplifier, suitable for multi-anode Silicon Drift Detectors or other multi-element solid-state X-ray detection systems, is proposed. The new read-out scheme has been conceived for demanding applications with synchrotron light sources, such as X-ray holography or EXAFS, where both high count-rates and high-energy resolutions are required. The circuit is of the linear time-variant class, accepts randomly distributed events and features: a finite-width (1-10 mu s) quasi-optimal weight function, an ultra-low-level energy discrimination (approx 150 eV), and a full compatibility for monolithic integration in CMOS technology. Its impulse response has a staircase-like shape, but the weight function (which is in general different from the impulse response in time-variant systems) is quasi trapezoidal. The operation principles of the new scheme as well as the first experimental results obtained with a prototype of the circuit are presented and discussed in the work.

Surface and interface effects in VLSI

CERN Document Server

Einspruch, Norman G

1985-01-01

VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

Hybrid VLSI/QCA Architecture for Computing FFTs

Science.gov (United States)

Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

2003-01-01

A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

Energy Technology Data Exchange (ETDEWEB)

Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

2014-01-31

The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

VLSI signal processing technology

CERN Document Server

Swartzlander, Earl

1994-01-01

This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

VLSI 'smart' I/O module development

Science.gov (United States)

Kirk, Dan

The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

VLSI Architectures for Computing DFT's

Science.gov (United States)

Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

1986-01-01

Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

The VLSI handbook

CERN Document Server

Chen, Wai-Kai

2007-01-01

Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

Multi-valued LSI/VLSI logic design

Science.gov (United States)

Santrakul, K.

A procedure for synthesizing any large complex logic system, such as LSI and VLSI integrated circuits is described. This scheme uses Multi-Valued Multi-plexers (MVMUX) as the basic building blocks and the tree as the structure of the circuit realization. Simple built-in test circuits included in the network (the main current), provide a thorough functional checking of the network at any time. In brief, four major contributions are made: (1) multi-valued Algorithmic State Machine (ASM) chart for describing an LSI/VLSI behavior; (2) a tree-structured multi-valued multiplexer network which can be obtained directly from an ASM chart; (3) a heuristic tree-structured synthesis method for realizing any combinational logic with minimal or nearly-minimal MVMUX; and (4) a hierarchical design of LSI/VLSI with built-in parallel testing capability.

VLSI implementations for image communications

CERN Document Server

Pirsch, P

1993-01-01

The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

Technology computer aided design simulation for VLSI MOSFET

CERN Document Server

Sarkar, Chandan Kumar

2013-01-01

Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

CERN Document Server

2015-01-01

This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

International Nuclear Information System (INIS)

Jian Haifang; Shi Yin

2009-01-01

The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

Energy Technology Data Exchange (ETDEWEB)

Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

2009-07-15

The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.

Science.gov (United States)

Feng, Lichen; Li, Zunchao; Wang, Yuanfa

2018-02-01

Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three-level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time-frequency domain features reflecting the nonstationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.

Parallel VLSI Architecture

Science.gov (United States)

Truong, T. K.; Reed, I.; Yeh, C.; Shao, H.

1985-01-01

Fermat number transformation convolutes two digital data sequences. Very-large-scale integration (VLSI) applications, such as image and radar signal processing, X-ray reconstruction, and spectrum shaping, linear convolution of two digital data sequences of arbitrary lenghts accomplished using Fermat number transform (ENT).

NASA Space Engineering Research Center for VLSI systems design

Science.gov (United States)

1991-01-01

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

CERN Document Server

Pop, Paul; Madsen, Jan

2016-01-01

This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

Parallel computation of nondeterministic algorithms in VLSI

Energy Technology Data Exchange (ETDEWEB)

Hortensius, P D

1987-01-01

This work examines parallel VLSI implementations of nondeterministic algorithms. It is demonstrated that conventional pseudorandom number generators are unsuitable for highly parallel applications. Efficient parallel pseudorandom sequence generation can be accomplished using certain classes of elementary one-dimensional cellular automata. The pseudorandom numbers appear in parallel on each clock cycle. Extensive study of the properties of these new pseudorandom number generators is made using standard empirical random number tests, cycle length tests, and implementation considerations. Furthermore, it is shown these particular cellular automata can form the basis of efficient VLSI architectures for computations involved in the Monte Carlo simulation of both the percolation and Ising models from statistical mechanics. Finally, a variation on a Built-In Self-Test technique based upon cellular automata is presented. These Cellular Automata-Logic-Block-Observation (CALBO) circuits improve upon conventional design for testability circuitry.

VLSI structures for track finding

International Nuclear Information System (INIS)

Dell'Orso, M.

1989-01-01

We discuss the architecture of a device based on the concept of associative memory designed to solve the track finding problem, typical of high energy physics experiments, in a time span of a few microseconds even for very high multiplicity events. This ''machine'' is implemented as a large array of custom VLSI chips. All the chips are equal and each of them stores a number of ''patterns''. All the patterns in all the chips are compared in parallel to the data coming from the detector while the detector is being read out. (orig.)

VLSI scaling methods and low power CMOS buffer circuit

International Nuclear Information System (INIS)

Sharma Vijay Kumar; Pattanaik Manisha

2013-01-01

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

UW VLSI chip tester

Science.gov (United States)

McKenzie, Neil

1989-12-01

We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

VLSI architecture and design for the Fermat Number Transform implementation

Energy Technology Data Exchange (ETDEWEB)

Pajayakrit, A.

1987-01-01

A new technique of sectioning a pipelined transformer, using the Fermat Number Transform (FNT), is introduced. Also, a novel VLSI design which overcomes the problems of implementing FNTs, for use in fast convolution/correlation, is described. The design comprises one complete section of a pipelined transformer and may be programmed to function at any point in a forward or inverse pipeline, so allowing the construction of a pipelined convolver or correlator using identical chips, thus the favorable properties of the transform can be exploited. This overcomes the difficulty of fitting a complete pipeline onto one chip without resorting to the use of several different designs. The implementation of high-speed convolver/correlator using the VLSI chips has been successfully developed and tested. For impulse response lengths of up to 16 points the sampling rates of 0.5 MHz can be achieved. Finally, the filter speed performance using the FNT chips is compared to other designs and conclusions drawn on the merits of the FNT for this application. Also, the advantages and limitations of the FNT are analyzed, with respect to the more conventional FFT, and the results are provided.

Advanced symbolic analysis for VLSI systems methods and applications

CERN Document Server

Shi, Guoyong; Tlelo Cuautle, Esteban

2014-01-01

This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

Spike Neuromorphic VLSI-Based Bat Echolocation for Micro-Aerial Vehicle Guidance

National Research Council Canada - National Science Library

Horiuchi, Timothy K; Krishnaprasad, P. S

2007-01-01

.... This includes multiple efforts related to a VLSI-based echolocation system being developed in one of our laboratories from algorithm development, bat flight data analysis, to VLSI circuit design...

Nano lasers in photonic VLSI

NARCIS (Netherlands)

Hill, M.T.; Oei, Y.S.; Smit, M.K.

2007-01-01

We examine the use of micro and nano lasers to form digital photonic VLSI building blocks. Problems such as isolation and cascading of building blocks are addressed, and the potential of future nano lasers explored.

VLSI architectures for modern error-correcting codes

CERN Document Server

Zhang, Xinmiao

2015-01-01

Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

An area-efficient path memory structure for VLSI Implementation of high speed Viterbi decoders

DEFF Research Database (Denmark)

Paaske, Erik; Pedersen, Steen; Sparsø, Jens

1991-01-01

Path storage and selection methods for Viterbi decoders are investigated with special emphasis on VLSI implementations. Two well-known algorithms, the register exchange, algorithm, REA, and the trace back algorithm, TBA, are considered. The REA requires the smallest number of storage elements...

The test of VLSI circuits

Science.gov (United States)

Baviere, Ph.

Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

Power gating of VLSI circuits using MEMS switches in low power applications

KAUST Repository

Shobak, Hosam; Ghoneim, Mohamed T.; El Boghdady, Nawal; Halawa, Sarah; Iskander, Sophinese M.; Anis, Mohab H.

2011-01-01

-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result

Las Vegas is better than determinism in VLSI and distributed computing

DEFF Research Database (Denmark)

Mehlhorn, Kurt; Schmidt, Erik Meineche

1982-01-01

In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply to (ac...

Lithography requirements in complex VLSI device fabrication

International Nuclear Information System (INIS)

Wilson, A.D.

1985-01-01

Fabrication of complex very large scale integration (VLSI) circuits requires continual advances in lithography to satisfy: decreasing minimum linewidths, larger chip sizes, tighter linewidth and overlay control, increasing topography to linewidth ratios, higher yield demands, increased throughput, harsher device processing, lower lithography cost, and a larger part number set with quick turn-around time. Where optical, electron beam, x-ray, and ion beam lithography can be applied to judiciously satisfy the complex VLSI circuit fabrication requirements is discussed and those areas that are in need of major further advances are addressed. Emphasis will be placed on advanced electron beam and storage ring x-ray lithography

Handbook of VLSI chip design and expert systems

CERN Document Server

Schwarz, A F

1993-01-01

Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

VLSI micro- and nanophotonics science, technology, and applications

CERN Document Server

Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

2011-01-01

Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

Pursuit, Avoidance, and Cohesion in Flight: Multi-Purpose Control Laws and Neuromorphic VLSI

Science.gov (United States)

2010-10-01

spatial navigation in mammals. We have designed, fabricated, and are now testing a neuromorphic VLSI chip that implements a spike-based, attractor...Control Laws and Neuromorphic VLSI 5a. CONTRACT NUMBER 070402-7705 5b. GRANT NUMBER FA9550-07-1-0446 5c. PROGRAM ELEMENT NUMBER 6. AUTHOR(S...implementations (custom Neuromorphic VLSI and robotics) we will apply important practical constraints that can lead to deeper insight into how and why efficient

VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

Directory of Open Access Journals (Sweden)

Rachmad Vidya Wicaksana Putra

2016-06-01

Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

Power gating of VLSI circuits using MEMS switches in low power applications

KAUST Repository

Shobak, Hosam

2011-12-01

Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

Science.gov (United States)

Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

2014-01-01

This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

Development methods for VLSI-processors

International Nuclear Information System (INIS)

Horninger, K.; Sandweg, G.

1982-01-01

The aim of this project, which was originally planed for 3 years, was the development of modern system and circuit concepts, for VLSI-processors having a 32 bit wide data path. The result of this first years work is the concept of a general purpose processor. This processor is not only logically but also physically (on the chip) divided into four functional units: a microprogrammable instruction unit, an execution unit in slice technique, a fully associative cache memory and an I/O unit. For the ALU of the execution unit circuits in PLA and slice techniques have been realized. On the basis of regularity, area consumption and achievable performance the slice technique has been prefered. The designs utilize selftesting circuitry. (orig.) [de

VLSI Technology for Cognitive Radio

Science.gov (United States)

VIJAYALAKSHMI, B.; SIDDAIAH, P.

2017-08-01

One of the most challenging tasks of cognitive radio is the efficiency in the spectrum sensing scheme to overcome the spectrum scarcity problem. The popular and widely used spectrum sensing technique is the energy detection scheme as it is very simple and doesn’t require any previous information related to the signal. We propose one such approach which is an optimised spectrum sensing scheme with reduced filter structure. The optimisation is done in terms of area and power performance of the spectrum. The simulations of the VLSI structure of the optimised flexible spectrum is done using verilog coding by using the XILINX ISE software. Our method produces performance with 13% reduction in area and 66% reduction in power consumption in comparison to the flexible spectrum sensing scheme. All the results are tabulated and comparisons are made. A new scheme for optimised and effective spectrum sensing opens up with our model.

PERFORMANCE OF LEAKAGE POWER MINIMIZATION TECHNIQUE FOR CMOS VLSI TECHNOLOGY

Directory of Open Access Journals (Sweden)

T. Tharaneeswaran

2012-06-01

Full Text Available Leakage power of CMOS VLSI Technology is a great concern. To reduce leakage power in CMOS circuits, a Leakage Power Minimiza-tion Technique (LPMT is implemented in this paper. Leakage cur-rents are monitored and compared. The Comparator kicks the charge pump to give body voltage (Vbody. Simulations of these circuits are done using TSMC 0.35µm technology with various operating temper-atures. Current steering Digital-to-Analog Converter (CSDAC is used as test core to validate the idea. The Test core (eg.8-bit CSDAC had power consumption of 347.63 mW. LPMT circuit alone consumes power of 6.3405 mW. This technique results in reduction of leakage power of 8-bit CSDAC by 5.51mW and increases the reliability of test core. Mentor Graphics ELDO and EZ-wave are used for simulations.

Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

Science.gov (United States)

Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

2008-01-21

In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

Parallel algorithms for placement and routing in VLSI design. Ph.D. Thesis

Science.gov (United States)

Brouwer, Randall Jay

1991-01-01

The computational requirements for high quality synthesis, analysis, and verification of very large scale integration (VLSI) designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. Two new parallel algorithms are proposed for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithm, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, results are presented which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs. Measurements are presented on the parallel speedups available.

Development of Radhard VLSI electronics for SSC calorimeters

International Nuclear Information System (INIS)

Dawson, J.W.; Nodulman, L.J.

1989-01-01

A new program of development of integrated electronics for liquid argon calorimeters in the SSC detector environment is being started at Argonne National Laboratory. Scientists from Brookhaven National Laboratory and Vanderbilt University together with an industrial participants are expected to collaborate in this work. Interaction rates, segmentation, and the radiation environment dictate that front-end electronics of SSC calorimeters must be implemented in the form of highly integrated, radhard, analog, low noise, VLSI custom monolithic devices. Important considerations are power dissipation, choice of functions integrated on the front-end chips, and cabling requirements. An extensive level of expertise in radhard electronics exists within the industrial community, and a primary objective of this work is to bring that expertise to bear on the problems of SSC detector design. Radiation hardness measurements and requirements as well as calorimeter design will be primarily the responsibility of Argonne scientists and our Brookhaven and Vanderbilt colleagues. Radhard VLSI design and fabrication will be primarily the industrial participant's responsibility. The rapid-cycling synchrotron at Argonne will be used for radiation damage studies involving response to neutrons and charged particles, while damage from gammas will be investigated at Brookhaven. 10 refs., 6 figs., 2 tabs

A Compact VLSI System for Bio-Inspired Visual Motion Estimation.

Science.gov (United States)

Shi, Cong; Luo, Gang

2018-04-01

This paper proposes a bio-inspired visual motion estimation algorithm based on motion energy, along with its compact very-large-scale integration (VLSI) architecture using low-cost embedded systems. The algorithm mimics motion perception functions of retina, V1, and MT neurons in a primate visual system. It involves operations of ternary edge extraction, spatiotemporal filtering, motion energy extraction, and velocity integration. Moreover, we propose the concept of confidence map to indicate the reliability of estimation results on each probing location. Our algorithm involves only additions and multiplications during runtime, which is suitable for low-cost hardware implementation. The proposed VLSI architecture employs multiple (frame, pixel, and operation) levels of pipeline and massively parallel processing arrays to boost the system performance. The array unit circuits are optimized to minimize hardware resource consumption. We have prototyped the proposed architecture on a low-cost field-programmable gate array platform (Zynq 7020) running at 53-MHz clock frequency. It achieved 30-frame/s real-time performance for velocity estimation on 160 × 120 probing locations. A comprehensive evaluation experiment showed that the estimated velocity by our prototype has relatively small errors (average endpoint error < 0.5 pixel and angular error < 10°) for most motion cases.

Drift chamber tracking with a VLSI neural network

International Nuclear Information System (INIS)

Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

1992-10-01

We have tested a commercial analog VLSI neural network chip for finding in real time the intercept and slope of charged particles traversing a drift chamber. Voltages proportional to the drift times were input to the Intel ETANN chip and the outputs were recorded and later compared off line to conventional track fits. We will discuss the chamber and test setup, the chip specifications, and results of recent tests. We'll briefly discuss possible applications in high energy physics detector triggers

Design of a VLSI Decoder for Partially Structured LDPC Codes

Directory of Open Access Journals (Sweden)

Fabrizio Vacca

2008-01-01

of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

Spike Neuromorphic VLSI-Based Bat Echolocation for Micro-Aerial Vehicle Guidance

Science.gov (United States)

2007-03-31

IFinal 03/01/04 - 02/28/07 4. TITLE AND SUBTITLE 5a. CONTRACT NUMBER Neuromorphic VLSI-based Bat Echolocation for Micro-aerial 5b.GRANTNUMBER Vehicle...uncovered interesting new issues in our choice for representing the intensity of signals. We have just finished testing the first chip version of an echo...timing-based algorithm (’openspace’) for sonar-guided navigation amidst multiple obstacles. 15. SUBJECT TERMS Neuromorphic VLSI, bat echolocation

The AMchip: A VLSI associative memory for track finding

International Nuclear Information System (INIS)

Morsani, F.; Galeotti, S.; Passuello, D.; Amendolia, S.R.; Ristori, L.; Turini, N.

1992-01-01

An associative memory to be used for super-fast track finding in future high energy physics experiments, has been implemented on silicon as a full-custom CMOS VLSI chip (the AMchip). The first prototype has been designed and successfully tested at INFN in Pisa. It is implemented in 1.6 μm, double metal, silicon gate CMOS technology and contains about 140 000 MOS transistors on a 1x1 cm 2 silicon chip. (orig.)

Convolving optically addressed VLSI liquid crystal SLM

Science.gov (United States)

Jared, David A.; Stirk, Charles W.

1994-03-01

We designed, fabricated, and tested an optically addressed spatial light modulator (SLM) that performs a 3 X 3 kernel image convolution using ferroelectric liquid crystal on VLSI technology. The chip contains a 16 X 16 array of current-mirror-based convolvers with a fixed kernel for finding edges. The pixels are located on 75 micron centers, and the modulators are 20 microns on a side. The array successfully enhanced edges in illumination patterns. We developed a high-level simulation tool (CON) for analyzing the performance of convolving SLM designs. CON has a graphical interface and simulates SLM functions using SPICE-like device models. The user specifies the pixel function along with the device parameters and nonuniformities. We discovered through analysis, simulation and experiment that the operation of current-mirror-based convolver pixels is degraded at low light levels by the variation of transistor threshold voltages inherent to CMOS chips. To function acceptable, the test SLM required the input image to have an minimum irradiance of 10 (mu) W/cm2. The minimum required irradiance can be further reduced by adding a photodarlington near the photodetector or by increasing the size of the transistors used to calculate the convolution.

Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

Directory of Open Access Journals (Sweden)

Urard Pascal

2006-01-01

Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.

VLSI Architectures for the Multiplication of Integers Modulo a Fermat Number

Science.gov (United States)

Chang, J. J.; Truong, T. K.; Reed, I. S.; Hsu, I. S.

1984-01-01

Multiplication is central in the implementation of Fermat number transforms and other residue number algorithms. There is need for a good multiplication algorithm that can be realized easily on a very large scale integration (VLSI) chip. The Leibowitz multiplier is modified to realize multiplication in the ring of integers modulo a Fermat number. This new algorithm requires only a sequence of cyclic shifts and additions. The designs developed for this new multiplier are regular, simple, expandable, and, therefore, suitable for VLSI implementation.

A VLSI image processor via pseudo-mersenne transforms

International Nuclear Information System (INIS)

Sei, W.J.; Jagadeesh, J.M.

1986-01-01

The computational burden on image processing in medical fields where a large amount of information must be processed quickly and accurately has led to consideration of special-purpose image processor chip design for some time. The very large scale integration (VLSI) resolution has made it cost-effective and feasible to consider the design of special purpose chips for medical imaging fields. This paper describes a VLSI CMOS chip suitable for parallel implementation of image processing algorithms and cyclic convolutions by using Pseudo-Mersenne Number Transform (PMNT). The main advantages of the PMNT over the Fast Fourier Transform (FFT) are: (1) no multiplications are required; (2) integer arithmetic is used. The design and development of this processor, which operates on 32-point convolution or 5 x 5 window image, are described

Synthesis of on-chip control circuits for mVLSI biochips

DEFF Research Database (Denmark)

Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

2017-01-01

them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip......-chip control circuit design and (iii) the integration of on-chip control in the placement and routing design tasks. In this paper we present a design methodology for logic synthesis and physical synthesis of mVLSI biochips that use on-chip control. We show how the proposed methodology can be successfully...... applied to generate biochip layouts with integrated on-chip pneumatic control....

Harnessing VLSI System Design with EDA Tools

CERN Document Server

Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

2012-01-01

This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

CERN Document Server

Turchetta, R; Manolopoulos, S; Tyndel, M; Allport, P P; Bates, R; O'Shea, V; Hall, G; Raymond, M

2003-01-01

Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to ta...

Positron emission tomographic images and expectation maximization: A VLSI architecture for multiple iterations per second

International Nuclear Information System (INIS)

Jones, W.F.; Byars, L.G.; Casey, M.E.

1988-01-01

A digital electronic architecture for parallel processing of the expectation maximization (EM) algorithm for Positron Emission tomography (PET) image reconstruction is proposed. Rapid (0.2 second) EM iterations on high resolution (256 x 256) images are supported. Arrays of two very large scale integration (VLSI) chips perform forward and back projection calculations. A description of the architecture is given, including data flow and partitioning relevant to EM and parallel processing. EM images shown are produced with software simulating the proposed hardware reconstruction algorithm. Projected cost of the system is estimated to be small in comparison to the cost of current PET scanners

Real time track finding in a drift chamber with a VLSI neural network

International Nuclear Information System (INIS)

Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

1992-01-01

In a test setup, a hardware neural network determined track parameters of charged particles traversing a drift chamber. Voltages proportional to the drift times in 6 cells of the 3-layer chamber were inputs to the Intel ETANN neural network chip which had been trained to give the slope and intercept of tracks. We compare network track parameters to those obtained from off-line track fits. To our knowledge this is the first on-line application of a VLSI neural network to a high energy physics detector. This test explored the potential of the chip and the practical problems of using it in a real world setting. We compare the chip performance to a neural network simulation on a conventional computer. We discuss possible applications of the chip in high energy physics detector triggers. (orig.)

A multi coding technique to reduce transition activity in VLSI circuits

International Nuclear Information System (INIS)

Vithyalakshmi, N.; Rajaram, M.

2014-01-01

Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods. (semiconductor technology)

Trace-based post-silicon validation for VLSI circuits

CERN Document Server

Liu, Xiao

2014-01-01

This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

Implementation of a VLSI Level Zero Processing system utilizing the functional component approach

Science.gov (United States)

Shi, Jianfei; Horner, Ward P.; Grebowsky, Gerald J.; Chesney, James R.

1991-01-01

A high rate Level Zero Processing system is currently being prototyped at NASA/Goddard Space Flight Center (GSFC). Based on state-of-the-art VLSI technology and the functional component approach, the new system promises capabilities of handling multiple Virtual Channels and Applications with a combined data rate of up to 20 Megabits per second (Mbps) at low cost.

Design of a Low-Power VLSI Macrocell for Nonlinear Adaptive Video Noise Reduction

Directory of Open Access Journals (Sweden)

Sergio Saponara

2004-09-01

Full Text Available A VLSI macrocell for edge-preserving video noise reduction is proposed in the paper. It is based on a nonlinear rational filter enhanced by a noise estimator for blind and dynamic adaptation of the filtering parameters to the input signal statistics. The VLSI filter features a modular architecture allowing the extension of both mask size and filtering directions. Both spatial and spatiotemporal algorithms are supported. Simulation results with monochrome test videos prove its efficiency for many noise distributions with PSNR improvements up to 3.8 dB with respect to a nonadaptive solution. The VLSI macrocell has been realized in a 0.18 μm CMOS technology using a standard-cells library; it allows for real-time processing of main video formats, up to 30 fps (frames per second 4CIF, with a power consumption in the order of few mW.

A Knowledge Based Approach to VLSI CAD

Science.gov (United States)

1983-09-01

Avail-and/or Dist ISpecial L| OI. SEICURITY CLASIIrCATION OP THIS IPA.lErllm S Daene." A KNOwLEDE BASED APPROACH TO VLSI CAD’ Louis L Steinberg and...major issues lies in building up and managing the knowledge base of oesign expertise. We expect that, as with many recent expert systems, in order to

Carbon nanotube based VLSI interconnects analysis and design

CERN Document Server

Kaushik, Brajesh Kumar

2015-01-01

The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute

CERN Document Server

Williams, John

2008-01-01

This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the

Numerical analysis of electromigration in thin film VLSI interconnections

NARCIS (Netherlands)

Petrescu, V.; Mouthaan, A.J.; Schoenmaker, W.; Angelescu, S.; Vissarion, R.; Dima, G.; Wallinga, Hans; Profirescu, M.D.

1995-01-01

Due to the continuing downscaling of the dimensions in VLSI circuits, electromigration is becoming a serious reliability hazard. A software tool based on finite element analysis has been developed to solve the two partial differential equations of the two particle vacancy/imperfection model.

Heavy ion tests on programmable VLSI

International Nuclear Information System (INIS)

Provost-Grellier, A.

1989-11-01

The radiation from space environment induces operation damages in onboard computers systems. The definition of a strategy, for the Very Large Scale Integrated Circuitry (VLSI) qualification and choice, is needed. The 'upset' phenomena is known to be the most critical integrated circuit radiation effect. The strategies for testing integrated circuits are reviewed. A method and a test device were developed and applied to space applications candidate circuits. Cyclotron, synchrotron and Californium source experiments were carried out [fr

VLSI-based video event triggering for image data compression

Science.gov (United States)

Williams, Glenn L.

1994-02-01

Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

International Nuclear Information System (INIS)

Amendolia, S.R.; Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L.; Turini, N.

1993-01-01

An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used

PLA realizations for VLSI state machines

Science.gov (United States)

Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

1990-01-01

A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

A novel configurable VLSI architecture design of window-based image processing method

Science.gov (United States)

Zhao, Hui; Sang, Hongshi; Shen, Xubang

2018-03-01

Most window-based image processing architecture can only achieve a certain kind of specific algorithms, such as 2D convolution, and therefore lack the flexibility and breadth of application. In addition, improper handling of the image boundary can cause loss of accuracy, or consume more logic resources. For the above problems, this paper proposes a new VLSI architecture of window-based image processing operations, which is configurable and based on consideration of the image boundary. An efficient technique is explored to manage the image borders by overlapping and flushing phases at the end of row and the end of frame, which does not produce new delay and reduce the overhead in real-time applications. Maximize the reuse of the on-chip memory data, in order to reduce the hardware complexity and external bandwidth requirements. To perform different scalar function and reduction function operations in pipeline, this can support a variety of applications of window-based image processing. Compared with the performance of other reported structures, the performance of the new structure has some similarities to some of the structures, but also superior to some other structures. Especially when compared with a systolic array processor CWP, this structure at the same frequency of approximately 12.9% of the speed increases. The proposed parallel VLSI architecture was implemented with SIMC 0.18-μm CMOS technology, and the maximum clock frequency, power consumption, and area are 125Mhz, 57mW, 104.8K Gates, respectively, furthermore the processing time is independent of the different window-based algorithms mapped to the structure

Design of two easily-testable VLSI array multipliers

Energy Technology Data Exchange (ETDEWEB)

Ferguson, J.; Shen, J.P.

1983-01-01

Array multipliers are well-suited to VLSI implementation because of the regularity in their iterative structure. However, most VLSI circuits are very difficult to test. This paper shows that, with appropriate cell design, array multipliers can be designed to be very easily testable. An array multiplier is called c-testable if all its adder cells can be exhaustively tested while requiring only a constant number of test patterns. The testability of two well-known array multiplier structures are studied. The conventional design of the carry-save array multipler is shown to be not c-testable. However, a modified design, using a modified adder cell, is generated and shown to be c-testable and requires only 16 test patterns. Similar results are obtained for the baugh-wooley two's complement array multiplier. A modified design of the baugh-wooley array multiplier is shown to be c-testable and requires 55 test patterns. The implementation of a practical c-testable 16*16 array multiplier is also presented. 10 references.

Applications of VLSI circuits to medical imaging

International Nuclear Information System (INIS)

O'Donnell, M.

1988-01-01

In this paper the application of advanced VLSI circuits to medical imaging is explored. The relationship of both general purpose signal processing chips and custom devices to medical imaging is discussed using examples of fabricated chips. In addition, advanced CAD tools for silicon compilation are presented. Devices built with these tools represent a possible alternative to custom devices and general purpose signal processors for the next generation of medical imaging systems

Built-in self-repair of VLSI memories employing neural nets

Science.gov (United States)

Mazumder, Pinaki

1998-10-01

The decades of the Eighties and the Nineties have witnessed the spectacular growth of VLSI technology, when the chip size has increased from a few hundred devices to a staggering multi-millon transistors. This trend is expected to continue as the CMOS feature size progresses towards the nanometric dimension of 100 nm and less. SIA roadmap projects that, where as the DRAM chips will integrate over 20 billion devices in the next millennium, the future microprocessors may incorporate over 100 million transistors on a single chip. As the VLSI chip size increase, the limited accessibility of circuit components poses great difficulty for external diagnosis and replacement in the presence of faulty components. For this reason, extensive work has been done in built-in self-test techniques, but little research is known concerning built-in self-repair. Moreover, the extra hardware introduced by conventional fault-tolerance techniques is also likely to become faulty, therefore causing the circuit to be useless. This research demonstrates the feasibility of implementing electronic neural networks as intelligent hardware for memory array repair. Most importantly, we show that the neural network control possesses a robust and degradable computing capability under various fault conditions. Overall, a yield analysis performed on 64K DRAM's shows that the yield can be improved from as low as 20 percent to near 99 percent due to the self-repair design, with overhead no more than 7 percent.

Towards an Analogue Neuromorphic VLSI Instrument for the Sensing of Complex Odours

Science.gov (United States)

Ab Aziz, Muhammad Fazli; Harun, Fauzan Khairi Che; Covington, James A.; Gardner, Julian W.

2011-09-01

Almost all electronic nose instruments reported today employ pattern recognition algorithms written in software and run on digital processors, e.g. micro-processors, microcontrollers or FPGAs. Conversely, in this paper we describe the analogue VLSI implementation of an electronic nose through the design of a neuromorphic olfactory chip. The modelling, design and fabrication of the chip have already been reported. Here a smart interface has been designed and characterised for thisneuromorphic chip. Thus we can demonstrate the functionality of the a VLSI neuromorphic chip, producing differing principal neuron firing patterns to real sensor response data. Further work is directed towards integrating 9 separate neuromorphic chips to create a large neuronal network to solve more complex olfactory problems.

VLSI top-down design based on the separation of hierarchies

NARCIS (Netherlands)

Spaanenburg, L.; Broekema, A.; Leenstra, J.; Huys, C.

1986-01-01

Despite the presence of structure, interactions between the three views on VLSI design still lead to lengthy iterations. By separating the hierarchies for the respective views, the interactions are reduced. This separated hierarchy allows top-down design with functional abstractions as exemplified

VLSI Design with Alliance Free CAD Tools: an Implementation Example

Directory of Open Access Journals (Sweden)

Chávez-Bracamontes Ramón

2015-07-01

Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding

VLSI Design of Trusted Virtual Sensors

Directory of Open Access Journals (Sweden)

Macarena C. Martínez-Rodríguez

2018-01-01

Full Text Available This work presents a Very Large Scale Integration (VLSI design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF based on a Static Random Access Memory (SRAM to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time.

VLSI Design of Trusted Virtual Sensors.

Science.gov (United States)

Martínez-Rodríguez, Macarena C; Prada-Delgado, Miguel A; Brox, Piedad; Baturone, Iluminada

2018-01-25

This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time).

Vlsi implementation of flexible architecture for decision tree classification in data mining

Science.gov (United States)

Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak

2017-07-01

The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.

Assimilation of Biophysical Neuronal Dynamics in Neuromorphic VLSI.

Science.gov (United States)

Wang, Jun; Breen, Daniel; Akinin, Abraham; Broccard, Frederic; Abarbanel, Henry D I; Cauwenberghs, Gert

2017-12-01

Representing the biophysics of neuronal dynamics and behavior offers a principled analysis-by-synthesis approach toward understanding mechanisms of nervous system functions. We report on a set of procedures assimilating and emulating neurobiological data on a neuromorphic very large scale integrated (VLSI) circuit. The analog VLSI chip, NeuroDyn, features 384 digitally programmable parameters specifying for 4 generalized Hodgkin-Huxley neurons coupled through 12 conductance-based chemical synapses. The parameters also describe reversal potentials, maximal conductances, and spline regressed kinetic functions for ion channel gating variables. In one set of experiments, we assimilated membrane potential recorded from one of the neurons on the chip to the model structure upon which NeuroDyn was designed using the known current input sequence. We arrived at the programmed parameters except for model errors due to analog imperfections in the chip fabrication. In a related set of experiments, we replicated songbird individual neuron dynamics on NeuroDyn by estimating and configuring parameters extracted using data assimilation from intracellular neural recordings. Faithful emulation of detailed biophysical neural dynamics will enable the use of NeuroDyn as a tool to probe electrical and molecular properties of functional neural circuits. Neuroscience applications include studying the relationship between molecular properties of neurons and the emergence of different spike patterns or different brain behaviors. Clinical applications include studying and predicting effects of neuromodulators or neurodegenerative diseases on ion channel kinetics.

Point DCT VLSI Architecture for Emerging HEVC Standard

OpenAIRE

Ahmed, Ashfaq; Shahid, Muhammad Usman; Rehman, Ata ur

2012-01-01

This work presents a flexible VLSI architecture to compute the -point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4 × 4 up to 3 2 × 3 2 , the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into ...

Using Software Technology to Specify Abstract Interfaces in VLSI Design.

Science.gov (United States)

1985-01-01

with the complexity lev- els inherent in VLSI design, in that they can capitalize on their foundations in discrete mathemat- ics and the theory of...basis, rather than globally. Such a partitioning of module semantics makes the specification easier to construct and verify intelectual !y; it also...access function definitions. A standard language improves executability characteristics by capitalizing on portable, optimized system software developed

Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

Directory of Open Access Journals (Sweden)

HOO, C.-S.

2013-02-01

Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.

An SEU analysis approach for error propagation in digital VLSI CMOS ASICs

International Nuclear Information System (INIS)

Baze, M.P.; Bartholet, W.G.; Dao, T.A.; Buchner, S.

1995-01-01

A critical issue in the development of ASIC designs is the ability to achieve first pass fabrication success. Unsuccessful fabrication runs have serious impact on ASIC costs and schedules. The ability to predict an ASICs radiation response prior to fabrication is therefore a key issue when designing ASICs for military and aerospace systems. This paper describes an analysis approach for calculating static bit error propagation in synchronous VLSI CMOS circuits developed as an aid for predicting the SEU response of ASIC's. The technique is intended for eventual application as an ASIC development simulation tool which can be used by circuit design engineers for performance evaluation during the pre-fabrication design process in much the same way that logic and timing simulators are used

Formal verification an essential toolkit for modern VLSI design

CERN Document Server

Seligman, Erik; Kumar, M V Achutha Kiran

2015-01-01

Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

DPL/Daedalus design environment (for VLSI)

Energy Technology Data Exchange (ETDEWEB)

Batali, J; Mayle, N; Shrobe, H; Sussman, G; Weise, D

1981-01-01

The DPL/Daedalus design environment is an interactive VLSI design system implemented at the MIT Artificial Intelligence Laboratory. The system consists of several components: a layout language called DPL (for design procedure language); an interactive graphics facility (Daedalus); and several special purpose design procedures for constructing complex artifacts such as PLAs and microprocessor data paths. Coordinating all of these is a generalized property list data base which contains both the data representing circuits and the procedures for constructing them. The authors first review the nature of the data base and then turn to DPL and Daedalus, the two most common ways of entering information into the data base. The next two sections review the specialized procedures for constructing PLAs and data paths; the final section describes a tool for hierarchical node extraction. 5 references.

FILTRES: a 128 channels VLSI mixed front-end readout electronic development for microstrip detectors

International Nuclear Information System (INIS)

Anstotz, F.; Hu, Y.; Michel, J.; Sohler, J.L.; Lachartre, D.

1998-01-01

We present a VLSI digital-analog readout electronic chain for silicon microstrip detectors. The characteristics of this circuit have been optimized for the high resolution tracker of the CERN CMS experiment. This chip consists of 128 channels at 50 μm pitch. Each channel is composed by a charge amplifier, a CR-RC shaper, an analog memory, an analog processor, an output FIFO read out serially by a multiplexer. This chip has been processed in the radiation hard technology DMILL. This paper describes the architecture of the circuit and presents test results of the 128 channel full chain chip. (orig.)

Synthesis algorithm of VLSI multipliers for ASIC

Science.gov (United States)

Chua, O. H.; Eldin, A. G.

1993-01-01

Multipliers are critical sub-blocks in ASIC design, especially for digital signal processing and communications applications. A flexible multiplier synthesis tool is developed which is capable of generating multiplier blocks for word size in the range of 4 to 256 bits. A comparison of existing multiplier algorithms is made in terms of speed, silicon area, and suitability for automated synthesis and verification of its VLSI implementation. The algorithm divides the range of supported word sizes into sub-ranges and provides each sub-range with a specific multiplier architecture for optimal speed and area. The algorithm of the synthesis tool and the multiplier architectures are presented. Circuit implementation and the automated synthesis methodology are discussed.

First results from a silicon-strip detector with VLSI readout

International Nuclear Information System (INIS)

Anzivino, G.; Horisberger, R.; Hubbeling, L.; Hyams, B.; Parker, S.; Breakstone, A.; Litke, A.M.; Walker, J.T.; Bingefors, N.

1986-01-01

A 256-strip silicon detector with 25 μm strip pitch, connected to two 128-channel NMOS VLSI chips (Microplex), has been tested using straight-through tracks from a ruthenium beta source. The readout channels have a pitch of 47.5 μm. A single multiplexed output provides voltages proportional to the integrated charge from each strip. The most probable signal height from the beta traversals is approximately 14 times the rms noise in any single channel. (orig.)

VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

Directory of Open Access Journals (Sweden)

Fazal NOORBASHA

2012-08-01

Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

Fast-prototyping of VLSI

International Nuclear Information System (INIS)

Saucier, G.; Read, E.

1987-01-01

Fast-prototyping will be a reality in the very near future if both straightforward design methods and fast manufacturing facilities are available. This book focuses, first, on the motivation for fast-prototyping. Economic aspects and market considerations are analysed by European and Japanese companies. In the second chapter, new design methods are identified, mainly for full custom circuits. Of course, silicon compilers play a key role and the introduction of artificial intelligence techniques sheds a new light on the subject. At present, fast-prototyping on gate arrays or on standard cells is the most conventional technique and the third chapter updates the state-of-the art in this area. The fourth chapter concentrates specifically on the e-beam direct-writing for submicron IC technologies. In the fifth chapter, a strategic point in fast-prototyping, namely the test problem is addressed. The design for testability and the interface to the test equipment are mandatory to fulfill the test requirement for fast-prototyping. Finally, the last chapter deals with the subject of education when many people complain about the lack of use of fast-prototyping in higher education for VLSI

Multi-net optimization of VLSI interconnect

CERN Document Server

Moiseev, Konstantin; Wimer, Shmuel

2015-01-01

This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

Physico-topological methods of increasing stability of the VLSI circuit components to irradiation. Fiziko-topologhicheskie sposoby uluchsheniya radiatsionnoj stojkosti komponentov BIS

Energy Technology Data Exchange (ETDEWEB)

Pereshenkov, V S [MIFI, Moscow, (Russian Federation); Shishianu, F S; Rusanovskij, V I [S. Lazo KPI, Chisinau, (Moldova, Republic of)

1992-01-01

The paper presents the method used and the experimental results obtained for 8-bit microprocessor irradiated with [gamma]-rays and neutrons. The correlation between the electrical and technological parameters with the irradiation ones is revealed. The influence of leakage current between devices incorporated in VLSI circuits was studied. The obtained results create the possibility to determine the technological parameters necessary for designing the circuit able to work at predetermined doses. The necessary substrate doping concentration for isolation which eliminates the leakage current between devices prevents the VLSI circuit break down was determined. (Author).

International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

CERN Document Server

Shirur, Yasha; Prasad, Rekha

2013-01-01

This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

DESIGN OF LOW EPI AND HIGH THROUGHPUT CORDIC CELL TO IMPROVE THE PERFORMANCE OF MOBILE ROBOT

Directory of Open Access Journals (Sweden)

P. VELRAJKUMAR

2014-04-01

Full Text Available This paper mainly focuses on pass logic based design, which gives an low Energy Per Instruction (EPI and high throughput COrdinate Rotation Digital Computer (CORDIC cell for application of robotic exploration. The basic components of CORDIC cell namely register, multiplexer and proposed adder is designed using pass transistor logic (PTL design. The proposed adder is implemented in bit-parallel iterative CORDIC circuit whereas designed using DSCH2 VLSI CAD tool and their layouts are generated by Microwind 3 VLSI CAD tool. The propagation delay, area and power dissipation are calculated from the simulated results for proposed adder based CORDIC cell. The EPI, throughput and effect of temperature are calculated from generated layout. The output parameter of generated layout is analysed using BSIM4 advanced analyzer. The simulated result of the proposed adder based CORDIC circuit is compared with other adder based CORDIC circuits. From the analysis of these simulated results, it was found that the proposed adder based CORDIC circuit dissipates low power, gives faster response, low EPI and high throughput.

An engineering methodology for implementing and testing VLSI (Very Large Scale Integrated) circuits

Science.gov (United States)

Corliss, Walter F., II

1989-03-01

The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix.

Point DCT VLSI Architecture for Emerging HEVC Standard

Directory of Open Access Journals (Sweden)

Ashfaq Ahmed

2012-01-01

Full Text Available This work presents a flexible VLSI architecture to compute the -point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4×4 up to 32×32, the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into sparse submatrices in order to reduce the multiplications. Finally, multiplications are completely eliminated using the lifting scheme. The proposed architecture sustains real-time processing of 1080P HD video codec running at 150 MHz.

A multichip aVLSI system emulating orientation selectivity of primary visual cortical cells.

Science.gov (United States)

Shimonomura, Kazuhiro; Yagi, Tetsuya

2005-07-01

In this paper, we designed and fabricated a multichip neuromorphic analog very large scale integrated (aVLSI) system, which emulates the orientation selective response of the simple cell in the primary visual cortex. The system consists of a silicon retina and an orientation chip. An image, which is filtered by a concentric center-surround (CS) antagonistic receptive field of the silicon retina, is transferred to the orientation chip. The image transfer from the silicon retina to the orientation chip is carried out with analog signals. The orientation chip selectively aggregates multiple pixels of the silicon retina, mimicking the feedforward model proposed by Hubel and Wiesel. The chip provides the orientation-selective (OS) outputs which are tuned to 0 degrees, 60 degrees, and 120 degrees. The feed-forward aggregation reduces the fixed pattern noise that is due to the mismatch of the transistors in the orientation chip. The spatial properties of the orientation selective response were examined in terms of the adjustable parameters of the chip, i.e., the number of aggregated pixels and size of the receptive field of the silicon retina. The multichip aVLSI architecture used in the present study can be applied to implement higher order cells such as the complex cell of the primary visual cortex.

Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform

Directory of Open Access Journals (Sweden)

Sanjay Singh

2017-06-01

Full Text Available Motion detection is the heart of a potentially complex automated video surveillance system, intended to be used as a standalone system. Therefore, in addition to being accurate and robust, a successful motion detection technique must also be economical in the use of computational resources on selected FPGA development platform. This is because many other complex algorithms of an automated video surveillance system also run on the same platform. Keeping this key requirement as main focus, a memory efficient VLSI architecture for real-time motion detection and its implementation on FPGA platform is presented in this paper. This is accomplished by proposing a new memory efficient motion detection scheme and designing its VLSI architecture. The complete real-time motion detection system using the proposed memory efficient architecture along with proper input/output interfaces is implemented on Xilinx ML510 (Virtex-5 FX130T FPGA development platform and is capable of operating at 154.55 MHz clock frequency. Memory requirement of the proposed architecture is reduced by 41% compared to the standard clustering based motion detection architecture. The new memory efficient system robustly and automatically detects motion in real-world scenarios (both for the static backgrounds and the pseudo-stationary backgrounds in real-time for standard PAL (720 × 576 size color video.

A parallel VLSI architecture for a digital filter of arbitrary length using Fermat number transforms

Science.gov (United States)

Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

1982-01-01

A parallel architecture for computation of the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT) is described. In particular a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. A standard barrel shifter circuit is modified so that it performs the required bit rotation operation. The overlap-save method is generalized for the FNT to compute a linear convolution of arbitrary length. A parallel architecture is developed to realize this type of overlap-save method using one FNT and several inverse FNTs of 128 points. The generalized overlap save method alleviates the usual dynamic range limitation in FNTs of long transform lengths. Its architecture is regular, simple, and expandable, and therefore naturally suitable for VLSI implementation.

Operation of a Fast-RICH Prototype with VLSI readout electronics

Energy Technology Data Exchange (ETDEWEB)

Guyonnet, J.L. (CRN, IN2P3-CNRS / Louis Pasteur Univ., Strasbourg (France)); Arnold, R. (CRN, IN2P3-CNRS / Louis Pasteur Univ., Strasbourg (France)); Jobez, J.P. (Coll. de France, 75 - Paris (France)); Seguinot, J. (Coll. de France, 75 - Paris (France)); Ypsilantis, T. (Coll. de France, 75 - Paris (France)); Chesi, E. (CERN / ECP Div., Geneve (Switzerland)); Racz, A. (CERN / ECP Div., Geneve (Switzerland)); Egger, J. (Paul Scherrer Inst., Villigen (Switzerland)); Gabathuler, K. (Paul Scherrer Inst., Villigen (Switzerland)); Joram, C. (Karlsruhe Univ. (Germany)); Adachi, I. (KEK, Tsukuba (Japan)); Enomoto, R. (KEK, Tsukuba (Japan)); Sumiyoshi, T. (KEK, Tsukuba (Japan))

1994-04-01

We discuss the first test results, obtained with cosmic rays, of a full-scale Fast-RICH Prototype with proximity-focused 10 mm thick LiF (CaF[sub 2]) solid radiators, TEA as photosensor in CH[sub 4], and readout of 12 x 10[sup 3] cathode pads (5.334 x 6.604 mm[sup 2]) using dedicated VLSI electronics we have developed. The number of detected photoelectrons is 7.7 (6.9) for the CaF[sub 2] (LiF) radiator, very near to the expected values 6.4 (7.5) from Monte Carlo simulations. The single-photon Cherenkov angle resolution [sigma][sub [theta

An analog VLSI real time optical character recognition system based on a neural architecture

International Nuclear Information System (INIS)

Bo, G.; Caviglia, D.; Valle, M.

1999-01-01

In this paper a real time Optical Character Recognition system is presented: it is based on a feature extraction module and a neural network classifier which have been designed and fabricated in analog VLSI technology. Experimental results validate the circuit functionality. The results obtained from a validation based on a mixed approach (i.e., an approach based on both experimental and simulation results) confirm the soundness and reliability of the system

An analog VLSI real time optical character recognition system based on a neural architecture

Energy Technology Data Exchange (ETDEWEB)

Bo, G.; Caviglia, D.; Valle, M. [Genoa Univ. (Italy). Dip. of Biophysical and Electronic Engineering

1999-03-01

In this paper a real time Optical Character Recognition system is presented: it is based on a feature extraction module and a neural network classifier which have been designed and fabricated in analog VLSI technology. Experimental results validate the circuit functionality. The results obtained from a validation based on a mixed approach (i.e., an approach based on both experimental and simulation results) confirm the soundness and reliability of the system.

Radiation hardness tests with a demonstrator preamplifier circuit manufactured in silicon on sapphire (SOS) VLSI technology

International Nuclear Information System (INIS)

Bingefors, N.; Ekeloef, T.; Eriksson, C.; Paulsson, M.; Moerk, G.; Sjoelund, A.

1992-01-01

Samples of the preamplifier circuit, as well as of separate n and p channel transistors of the type contained in the circuit, were irradiated with gammas from a 60 Co source up to an integrated dose of 3 Mrad (30 kGy). The VLSI manufacturing technology used is the SOS4 process of ABB Hafo. A first analysis of the tests shows that the performance of the amplifier remains practically unaffected by the radiation for total doses up to 1 Mrad. At higher doses up to 3 Mrad the circuit amplification factor decreases by a factor between 4 and 5 whereas the output noise level remains unchanged. It is argued that it may be possible to reduce the decrease in amplification factor in future by optimizing the amplifier circuit design further. (orig.)

Robust Working Memory in an Asynchronously Spiking Neural Network Realized with Neuromorphic VLSI.

Science.gov (United States)

Giulioni, Massimiliano; Camilleri, Patrick; Mattia, Maurizio; Dante, Vittorio; Braun, Jochen; Del Giudice, Paolo

2011-01-01

We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory) of leaky integrate-and-fire (LIF) neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of "high" and "low"-firing activity. Depending on the overall excitability, transitions to the "high" state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the "high" state retains a "working memory" of a stimulus until well after its release. In the latter case, "high" states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated "corrupted" "high" states comprising neurons of both excitatory populations. Within a "basin of attraction," the network dynamics "corrects" such states and re-establishes the prototypical "high" state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

A VLSI-Based High-Performance Raster Image System.

Science.gov (United States)

1986-05-08

and data in broadcast form to the array of memory -hips in the frame buffer, shown in the bottom block. This is simply a physical structure to hold up...Principal Investigator: John Poulton Collaboration on algorithm development: Prof. Jack Goldfeather (Dept. of Mathematics, Carleton Collge ...1983) Cheng-Hong Hsieh (MS, Computer Science, May, 1985) Jeff P. Hultquist Susan Spach Undergraduate ResearLh Assistant: Sonya Holder (BS, Physics , May

Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

Directory of Open Access Journals (Sweden)

I. Hameem Shanavas

2014-01-01

Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

10 K gate I(2)L and 1 K component analog compatible bipolar VLSI technology - HIT-2

Science.gov (United States)

Washio, K.; Watanabe, T.; Okabe, T.; Horie, N.

1985-02-01

An advanced analog/digital bipolar VLSI technology that combines on the same chip 2-ns 10 K I(2)L gates with 1 K analog devices is proposed. The new technology, called high-density integration technology-2, is based on a new structure concept that consists of three major techniques: shallow grooved-isolation, I(2)L active layer etching, and I(2)L current gain increase. I(2)L circuits with 80-MHz maximum toggle frequency have developed compatibly with n-p-n transistors having a BV(CE0) of more than 10 V and an f(T) of 5 GHz, and lateral p-n-p transistors having an f(T) of 150 MHz.

Prototype architecture for a VLSI level zero processing system. [Space Station Freedom

Science.gov (United States)

Shi, Jianfei; Grebowsky, Gerald J.; Horner, Ward P.; Chesney, James R.

1989-01-01

The prototype architecture and implementation of a high-speed level zero processing (LZP) system are discussed. Due to the new processing algorithm and VLSI technology, the prototype LZP system features compact size, low cost, high processing throughput, and easy maintainability and increased reliability. Though extensive control functions have been done by hardware, the programmability of processing tasks makes it possible to adapt the system to different data formats and processing requirements. It is noted that the LZP system can handle up to 8 virtual channels and 24 sources with combined data volume of 15 Gbytes per orbit. For greater demands, multiple LZP systems can be configured in parallel, each called a processing channel and assigned a subset of virtual channels. The telemetry data stream will be steered into different processing channels in accordance with their virtual channel IDs. This super system can cope with a virtually unlimited number of virtual channels and sources. In the near future, it is expected that new disk farms with data rate exceeding 150 Mbps will be available from commercial vendors due to the advance in disk drive technology.

VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE

Directory of Open Access Journals (Sweden)

N.R. Divya

2014-08-01

Full Text Available Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data compression, but implementation concern, it calls more multipliers and adders thus its lead to acquire more area and high power consumption. To contain an account of all, this paper has been dealt with VLSI architecture for image compression using Rom free DA based DCT (Discrete Cosine Transform structure. This technique provides high-throughput and most suitable for real-time implementation. In order to achieve this image matrix is subdivided into odd and even terms then the multiplication functions are removed by shift and add approach. Kogge_Stone_Adder techniques are proposed for obtaining a bit-wise image quality which determines the new trade-off levels as compared to the previous techniques. Overall the proposed architecture produces reduced memory, low power consumption and high throughput. MATLAB is used as a funding tool for receiving an input pixel and obtaining output image. Verilog HDL is used for implementing the design, Model Sim for simulation, Quatres II is used to synthesize and obtain details about power and area.

VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

Directory of Open Access Journals (Sweden)

Georgios Passas

2012-01-01

Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

Initial beam test results from a silicon-strip detector with VLSI readout

International Nuclear Information System (INIS)

Adolphsen, C.; Litke, A.; Schwarz, A.

1986-01-01

Silicon detectors with 256 strips, having a pitch of 25 μm, and connected to two 128 channel NMOS VLSI chips each (Microplex), have been tested in relativistic charged particle beams at CERN and at the Stanford Linear Accelerator Center. The readout chips have an input channel pitch of 47.5 μm and a single multiplexed output which provides voltages proportional to the integrated charge from each strip. The most probable signal height from minimum ionizing tracks was 15 times the rms noise in any single channel. Two-track traversals with a separation of 100 μm were cleanly resolved

Techniques for Computing the DFT Using the Residue Fermat Number Systems and VLSI

Science.gov (United States)

Truong, T. K.; Chang, J. J.; Hsu, I. S.; Pei, D. Y.; Reed, I. S.

1985-01-01

The integer complex multiplier and adder over the direct sum of two copies of a finite field is specialized to the direct sum of the rings of integers modulo Fermat numbers. Such multiplications and additions can be used in the implementation of a discrete Fourier transform (DFT) of a sequence of complex numbers. The advantage of the present approach is that the number of multiplications needed for the DFT can be reduced substantially over the previous approach. The architectural designs using this approach are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

Modeling selective attention using a neuromorphic analog VLSI device.

Science.gov (United States)

Indiveri, G

2000-12-01

Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

Performance improvement in narrow MuGFETs by gate work function and source/drain implant engineering

Science.gov (United States)

Ferain, I.; Duffy, R.; Collaert, N.; van Dal, M. J. H.; Pawlak, B. J.; O'Sullivan, B.; Witters, L.; Rooyackers, R.; Conard, T.; Popovici, M.; van Elshocht, S.; Kaiser, M.; Weemaes, R. G. R.; Swerts, J.; Jurczak, M.; Lander, R. J. P.; De Meyer, K.

2009-07-01

At short gate lengths, narrow multiple-gate FETs (MuGFETs) are known to offer superior short channel effect (SCE) control than their bulk Si counterpart [Doyle BS et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Dev Lett 2003;24(4):263-5, van Dal MJH et al. Highly manufacturable FinFETs with sub-10 nm fin width and high aspect ratio fabricated with immersion lithography. In: VLSI Symp Tech Dig; 2007. p. 110-1 [1,2

An electron undulating ring for VLSI lithography

International Nuclear Information System (INIS)

Tomimasu, T.; Mikado, T.; Noguchi, T.; Sugiyama, S.; Yamazaki, T.

1985-01-01

The development of the ETL storage ring ''TERAS'' as an undulating ring has been continued to achieve a wide area exposure of synchrotron radiation (SR) in VLSI lithography. Stable vertical and horizontal undulating motions of stored beams are demonstrated around a horizontal design orbit of TERAS, using two small steering magnets of which one is used for vertical undulating and another for horizontal one. Each steering magnet is inserted into one of the periodic configulation of guide field elements. As one of useful applications of undulaing electron beams, a vertically wide exposure of SR has been demonstrated in the SR lithography. The maximum vertical deviation from the design orbit nCcurs near the steering magnet. The maximum vertical tilt angle of the undulating beam near the nodes is about + or - 2mrad for a steering magnetic field of 50 gauss. Another proposal is for hith-intensity, uniform and wide exposure of SR from a wiggler installed in TERAS, using vertical and horizontal undulating motions of stored beams. A 1.4 m long permanent magnet wiggler has been installed for this purpose in this April

A novel low-voltage low-power analogue VLSI implementation of neural networks with on-chip back-propagation learning

Science.gov (United States)

Carrasco, Manuel; Garde, Andres; Murillo, Pilar; Serrano, Luis

2005-06-01

In this paper a novel design and implementation of a VLSI Analogue Neural Net based on Multi-Layer Perceptron (MLP) with on-chip Back Propagation (BP) learning algorithm suitable for the resolution of classification problems is described. In order to implement a general and programmable analogue architecture, the design has been carried out in a hierarchical way. In this way the net has been divided in synapsis-blocks and neuron-blocks providing an easy method for the analysis. These blocks basically consist on simple cells, which are mainly, the activation functions (NAF), derivatives (DNAF), multipliers and weight update circuits. The analogue design is based on current-mode translinear techniques using MOS transistors working in the weak inversion region in order to reduce both the voltage supply and the power consumption. Moreover, with the purpose of minimizing the noise, offset and distortion of even order, the topologies are fully-differential and balanced. The circuit, named ANNE (Analogue Neural NEt), has been prototyped and characterized as a proof of concept on CMOS AMI-0.5A technology occupying a total area of 2.7mm2. The chip includes two versions of neural nets with on-chip BP learning algorithm, which are respectively a 2-1 and a 2-2-1 implementations. The proposed nets have been experimentally tested using supply voltages from 2.5V to 1.8V, which is suitable for single cell lithium-ion battery supply applications. Experimental results of both implementations included in ANNE exhibit a good performance on solving classification problems. These results have been compared with other proposed Analogue VLSI implementations of Neural Nets published in the literature demonstrating that our proposal is very efficient in terms of occupied area and power consumption.

High-throughput sample adaptive offset hardware architecture for high-efficiency video coding

Science.gov (United States)

Zhou, Wei; Yan, Chang; Zhang, Jingzhi; Zhou, Xin

2018-03-01

A high-throughput hardware architecture for a sample adaptive offset (SAO) filter in the high-efficiency video coding video coding standard is presented. First, an implementation-friendly and simplified bitrate estimation method of rate-distortion cost calculation is proposed to reduce the computational complexity in the mode decision of SAO. Then, a high-throughput VLSI architecture for SAO is presented based on the proposed bitrate estimation method. Furthermore, multiparallel VLSI architecture for in-loop filters, which integrates both deblocking filter and SAO filter, is proposed. Six parallel strategies are applied in the proposed in-loop filters architecture to improve the system throughput and filtering speed. Experimental results show that the proposed in-loop filters architecture can achieve up to 48% higher throughput in comparison with prior work. The proposed architecture can reach a high-operating clock frequency of 297 MHz with TSMC 65-nm library and meet the real-time requirement of the in-loop filters for 8 K × 4 K video format at 132 fps.

CMOS VLSI Active-Pixel Sensor for Tracking

Science.gov (United States)

Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

Mixed-Dimensionality VLSI-Type Configurable Tools for Virtual Prototyping of Biomicrofluidic Devices and Integrated Systems

Science.gov (United States)

Makhijani, Vinod B.; Przekwas, Andrzej J.

2002-10-01

This report presents results of a DARPA/MTO Composite CAD Project aimed to develop a comprehensive microsystem CAD environment, CFD-ACE+ Multiphysics, for bio and microfluidic devices and complete microsystems. The project began in July 1998, and was a three-year team effort between CFD Research Corporation, California Institute of Technology (CalTech), University of California, Berkeley (UCB), and Tanner Research, with Mr. Don Verlee from Abbott Labs participating as a consultant on the project. The overall objective of this project was to develop, validate and demonstrate several applications of a user-configurable VLSI-type mixed-dimensionality software tool for design of biomicrofluidics devices and integrated systems. The developed tool would provide high fidelity 3-D multiphysics modeling capability, l-D fluidic circuits modeling, and SPICE interface for system level simulations, and mixed-dimensionality design. It would combine tools for layouts and process fabrication, geometric modeling, and automated grid generation, and interfaces to EDA tools (e.g. Cadence) and MCAD tools (e.g. ProE).

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

Science.gov (United States)

Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

1987-01-01

A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

New domain for image analysis: VLSI circuits testing, with Romuald, specialized in parallel image processing

Energy Technology Data Exchange (ETDEWEB)

Rubat Du Merac, C; Jutier, P; Laurent, J; Courtois, B

1983-07-01

This paper describes some aspects of specifying, designing and evaluating a specialized machine, Romuald, for the capture, coding, and processing of video and scanning electron microscope (SEM) pictures. First the authors present the functional organization of the process unit of romuald and its hardware, giving details of its behaviour. Then they study the capture and display unit which, thanks to its flexibility, enables SEM images coding. Finally, they describe an application which is now being developed in their laboratory: testing VLSI circuits with new methods: sem+voltage contrast and image processing. 15 references.

Development of superconductor electronics technology for high-end computing

Energy Technology Data Exchange (ETDEWEB)

Silver, A [Jet Propulsion Laboratory, 4800 Oak Grove Drive, Pasadena, CA 91109-8099 (United States); Kleinsasser, A [Jet Propulsion Laboratory, 4800 Oak Grove Drive, Pasadena, CA 91109-8099 (United States); Kerber, G [Northrop Grumman Space Technology, One Space Park, Redondo Beach, CA 90278 (United States); Herr, Q [Northrop Grumman Space Technology, One Space Park, Redondo Beach, CA 90278 (United States); Dorojevets, M [Department of Electrical and Computer Engineering, SUNY-Stony Brook, NY 11794-2350 (United States); Bunyk, P [Northrop Grumman Space Technology, One Space Park, Redondo Beach, CA 90278 (United States); Abelson, L [Northrop Grumman Space Technology, One Space Park, Redondo Beach, CA 90278 (United States)

2003-12-01

This paper describes our programme to develop and demonstrate ultra-high performance single flux quantum (SFQ) VLSI technology that will enable superconducting digital processors for petaFLOPS-scale computing. In the hybrid technology, multi-threaded architecture, the computational engine to power a petaFLOPS machine at affordable power will consist of 4096 SFQ multi-chip processors, with 50 to 100 GHz clock frequency and associated cryogenic RAM. We present the superconducting technology requirements, progress to date and our plan to meet these requirements. We improved SFQ Nb VLSI by two generations, to a 8 kA cm{sup -2}, 1.25 {mu}m junction process, incorporated new CAD tools into our methodology, demonstrated methods for recycling the bias current and data communication at speeds up to 60 Gb s{sup -1}, both on and between chips through passive transmission lines. FLUX-1 is the most ambitious project implemented in SFQ technology to date, a prototype general-purpose 8 bit microprocessor chip. We are testing the FLUX-1 chip (5K gates, 20 GHz clock) and designing a 32 bit floating-point SFQ multiplier with vector-register memory. We report correct operation of the complete stripline-connected gate library with large bias margins, as well as several larger functional units used in FLUX-1. The next stage will be an SFQ multi-processor machine. Important challenges include further reducing chip supply current and on-chip power dissipation, developing at least 64 kbit, sub-nanosecond cryogenic RAM chips, developing thermally and electrically efficient high data rate cryogenic-to-ambient input/output technology and improving Nb VLSI to increase gate density.

Development of superconductor electronics technology for high-end computing

International Nuclear Information System (INIS)

Silver, A; Kleinsasser, A; Kerber, G; Herr, Q; Dorojevets, M; Bunyk, P; Abelson, L

2003-01-01

This paper describes our programme to develop and demonstrate ultra-high performance single flux quantum (SFQ) VLSI technology that will enable superconducting digital processors for petaFLOPS-scale computing. In the hybrid technology, multi-threaded architecture, the computational engine to power a petaFLOPS machine at affordable power will consist of 4096 SFQ multi-chip processors, with 50 to 100 GHz clock frequency and associated cryogenic RAM. We present the superconducting technology requirements, progress to date and our plan to meet these requirements. We improved SFQ Nb VLSI by two generations, to a 8 kA cm -2 , 1.25 μm junction process, incorporated new CAD tools into our methodology, demonstrated methods for recycling the bias current and data communication at speeds up to 60 Gb s -1 , both on and between chips through passive transmission lines. FLUX-1 is the most ambitious project implemented in SFQ technology to date, a prototype general-purpose 8 bit microprocessor chip. We are testing the FLUX-1 chip (5K gates, 20 GHz clock) and designing a 32 bit floating-point SFQ multiplier with vector-register memory. We report correct operation of the complete stripline-connected gate library with large bias margins, as well as several larger functional units used in FLUX-1. The next stage will be an SFQ multi-processor machine. Important challenges include further reducing chip supply current and on-chip power dissipation, developing at least 64 kbit, sub-nanosecond cryogenic RAM chips, developing thermally and electrically efficient high data rate cryogenic-to-ambient input/output technology and improving Nb VLSI to increase gate density

Design and implementation of interface units for high speed fiber optics local area networks and broadband integrated services digital networks

Science.gov (United States)

Tobagi, Fouad A.; Dalgic, Ismail; Pang, Joseph

1990-01-01

The design and implementation of interface units for high speed Fiber Optic Local Area Networks and Broadband Integrated Services Digital Networks are discussed. During the last years, a number of network adapters that are designed to support high speed communications have emerged. This approach to the design of a high speed network interface unit was to implement package processing functions in hardware, using VLSI technology. The VLSI hardware implementation of a buffer management unit, which is required in such architectures, is described.

Digital VLSI systems design a design manual for implementation of projects on FPGAs and ASICs using Verilog

CERN Document Server

Ramachandran, S

2007-01-01

Digital VLSI Systems Design is written for an advanced level course using Verilog and is meant for undergraduates, graduates and research scholars of Electrical, Electronics, Embedded Systems, Computer Engineering and interdisciplinary departments such as Bio Medical, Mechanical, Information Technology, Physics, etc. It serves as a reference design manual for practicing engineers and researchers as well. Diligent freelance readers and consultants may also start using this book with ease. The book presents new material and theory as well as synthesis of recent work with complete Project Designs

Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System

Directory of Open Access Journals (Sweden)

Horiuchi Timothy

2003-01-01

Full Text Available Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.

Adaptive WTA with an analog VLSI neuromorphic learning chip.

Science.gov (United States)

Häfliger, Philipp

2007-03-01

In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

Science.gov (United States)

Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

2016-12-07

The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

Science.gov (United States)

Zhu, Wenping; Liu, Leibo; Yin, Shouyi; Hu, Siqi; Tang, Eugene Y.; Wei, Shaojun

2014-05-01

With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human-computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.

CAPCAL, 3-D Capacitance Calculator for VLSI Purposes

International Nuclear Information System (INIS)

Seidl, Albert; Klose, Helmut; Svoboda, Mildos

2004-01-01

1 - Description of program or function: CAPCAL is devoted to the calculation of capacitances of three-dimensional wiring configurations are typically used in VLSI circuits. Due to analogies in the mathematical description also conductance and heat transport problems can be treated by CAPCAL. To handle the problem using CAPCAL same approximations have to be applied to the structure under investigation: - the overall geometry has to be confined to a finite domain by using symmetry-properties of the problem - Non-rectangular structures have to be simplified into an artwork of multiple boxes. 2 - Method of solution: The electrical field is described by the Laplace-equation. The differential equation is discretized by using the finite difference method. NEA-1327/01: The linear equation system is solved by using a combined ADI-multigrid method. NEA-1327/04: The linear equation system is solved by using a conjugate gradient method for CAPCAL V1.3. NEA-1327/05: The linear equation system is solved by using a conjugate gradient method for CAPCAL V1.3. 3 - Restrictions on the complexity of the problem: NEA-1327/01: Certain restrictions of use may arise from the dimensioning of arrays. Field lengths are defined via PARAMETER-statements which can easily by modified. If the geometry of the problem is defined such that Neumann boundaries are dominating the convergence of the iterative equation system solver is affected

An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures

DEFF Research Database (Denmark)

Sparsø, Jens; Jørgensen, Henrik Nordtorp; Paaske, Erik

1991-01-01

A topology for single-chip implementation of computing structures based on shuffle-exchange (SE)-type interconnection networks is presented. The topology is suited for structures with a small number of processing elements (i.e. 32-128) whose area cannot be neglected compared to the area required....... The topology has been used in a VLSI implementation of the add-compare-select (ACS) module of a fully parallel K=7, R=1/2 Viterbi decoder. Both the floor-planning issues and some of the important algorithm and circuit-level aspects of this design are discussed. The chip has been designed and fabricated in a 2....... The interconnection network occupies 32% of the area.>...

VLSI IMPLEMENTATION OF NOVEL ROUND KEYS GENERATION SCHEME FOR CRYPTOGRAPHY APPLICATIONS BY ERROR CONTROL ALGORITHM

Directory of Open Access Journals (Sweden)

B. SENTHILKUMAR

2015-05-01

Full Text Available A novel implementation of code based cryptography (Cryptocoding technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size with optimal performance. Error Control Algorithm is employed for both generation of round keys and diffusion of non-linearity among them. Two new functions for bit inversion and its reversal are developed for cryptocoding. Probability of retrieving original key from any other round keys is reduced by diffusing nonlinear selective bit inversions on round keys. Randomized selective bit inversions are done on equal length of key bits by Round Constant Feedback Shift Register within the error correction limits of chosen code. Complexity of retrieving the original key from any other round keys is increased by optimal hardware usage. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA and results are shown. Comparative analysis is done between 128 bit Advanced Encryption Standard round keys and proposed round keys for showing security strength of proposed algorithm. This paper concludes that chip based multi-layer key distribution of proposed algorithm is an enhanced solution to the existing threats on cryptography algorithms.

Biophysical synaptic dynamics in an analog VLSI network of Hodgkin-Huxley neurons.

Science.gov (United States)

Yu, Theodore; Cauwenberghs, Gert

2009-01-01

We study synaptic dynamics in a biophysical network of four coupled spiking neurons implemented in an analog VLSI silicon microchip. The four neurons implement a generalized Hodgkin-Huxley model with individually configurable rate-based kinetics of opening and closing of Na+ and K+ ion channels. The twelve synapses implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The implemented models on the chip are fully configurable by 384 parameters accounting for conductances, reversal potentials, and pre/post-synaptic voltage-dependence of the channel kinetics. We describe the models and present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. The 3mm x 3mm microchip consumes 1.29 mW power making it promising for applications including neuromorphic modeling and neural prostheses.

Digital VLSI design with Verilog a textbook from Silicon Valley Polytechnic Institute

CERN Document Server

Williams, John Michael

2014-01-01

This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics inclu...

A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

Directory of Open Access Journals (Sweden)

Yuan-Jyun Chang

2016-12-01

Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

Science.gov (United States)

McEwan, Alistair; van Schaik, André

2003-12-01

The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a) rate level functions for onset and steady-state response, (b) recovery after masking, (c) additivity, (d) two-component adaptation, (e) phase locking, (f) recovery of spontaneous activity, and (g) computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

Biophysical Neural Spiking, Bursting, and Excitability Dynamics in Reconfigurable Analog VLSI.

Science.gov (United States)

Yu, T; Sejnowski, T J; Cauwenberghs, G

2011-10-01

We study a range of neural dynamics under variations in biophysical parameters underlying extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The extended models are implemented in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. The dynamics exhibit a wide range of time scales extending beyond 100 ms neglected in typical silicon models of tonic spiking neurons. Circuit simulations and measurements show transition from tonic spiking to tonic bursting dynamics through variation of a single conductance parameter governing calcium recovery. We similarly demonstrate transition from graded to all-or-none neural excitability in the onset of spiking dynamics through the variation of channel kinetic parameters governing the speed of potassium activation. Other combinations of variations in conductance and channel kinetic parameters give rise to phasic spiking and spike frequency adaptation dynamics. The NeuroDyn chip consumes 1.29 mW and occupies 3 mm × 3 mm in 0.5 μm CMOS, supporting emerging developments in neuromorphic silicon-neuron interfaces.

A neuromorphic VLSI device for implementing 2-D selective attention systems.

Science.gov (United States)

Indiveri, G

2001-01-01

Selective attention is a mechanism used to sequentially select and process salient subregions of the input space, while suppressing inputs arriving from nonsalient regions. By processing small amounts of sensory information in a serial fashion, rather than attempting to process all the sensory data in parallel, this mechanism overcomes the problem of flooding limited processing capacity systems with sensory inputs. It is found in many biological systems and can be a useful engineering tool for developing artificial systems that need to process in real-time sensory data. In this paper we present a neuromorphic hardware model of a selective attention mechanism implemented on a very large scale integration (VLSI) chip, using analog circuits. The chip makes use of a spike-based representation for receiving input signals, transmitting output signals and for shifting the selection of the attended input stimulus over time. It can be interfaced to neuromorphic sensors and actuators, for implementing multichip selective attention systems. We describe the characteristics of the circuits used in the architecture and present experimental data measured from the system.

State-of-the-art assessment of testing and testability of custom LSI/VLSI circuits. Volume 8: Fault simulation

Science.gov (United States)

Breuer, M. A.; Carlan, A. J.

1982-10-01

Fault simulation is widely used by industry in such applications as scoring the fault coverage of test sequences and construction of fault dictionaries. For use in testing VLSI circuits a simulator is evaluated by its accuracy, i.e., modelling capability. To be accurate simulators must employ multi-valued logic in order to represent unknown signal values, impedance, signal transitions, etc., circuit delays such as transport rise/fall, inertial, and the fault modes it is capable of handling. Of the three basic fault simulators now in use (parallel, deductive and concurrent) concurrent fault simulation appears most promising.

Switched-capacitor techniques for high-accuracy filter and ADC design

NARCIS (Netherlands)

Quinn, P.J.; Roermund, van A.H.M.

2007-01-01

Switched capacitor (SC) techniques are well proven to be excellent candidates for implementing critical analogue functions with high accuracy, surpassing other analogue techniques when embedded in mixed-signal CMOS VLSI. Conventional SC circuits are primarily limited in accuracy by a) capacitor

High speed VLSI neural network for high energy physics

NARCIS (Netherlands)

Masa, P.; Masa, P.; Hoen, K.; Hoen, Klaas; Wallinga, Hans

1994-01-01

A CMOS neural network IC is discussed which was designed for very high speed applications. The parallel architecture, analog computing and digital weight storage provides unprecedented computing speed combined with ease of use. The circuit classifies up to 70 dimensional vectors within 20

A high-performance network for a distributed-control system

International Nuclear Information System (INIS)

Cuttone, G.; Aghion, F.; Giove, D.

1989-01-01

Local area networks play a central rule in modern distributed-control systems for accelerators. For a superconducting cyclotron under construction at the University of Milan, an optical Ethernet network has been implemented for the interconnection of multicomputer-based stations. Controller boards, with VLSI protocol chips, have been used. The higher levels of the ISO OSI model have been implemented to suit real-time control requirements. The experimental setup for measuring the data throughput between stations will be described. The effect of memory-to-memory data transfer with respect to the packet size has been studied for packets ranging from 200 bytes to 10 Kbytes. Results, showing the data throughput to range from 0.2 to 1.1 Mbit/s, will be discussed. (orig.)

An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

Directory of Open Access Journals (Sweden)

Alistair McEwan

2003-06-01

Full Text Available The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a rate level functions for onset and steady-state response, (b recovery after masking, (c additivity, (d two-component adaptation, (e phase locking, (f recovery of spontaneous activity, and (g computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

Directory of Open Access Journals (Sweden)

Jen-Chih Kuo

2003-12-01

Full Text Available The technique of {orthogonal frequency division multiplexing (OFDM} is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the {fast Fourier transform (FFT} and {inverse FFT (IFFT} operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly {processing element (PE} based on the {{coordinate} rotation digital computer (CORDIC} algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35 μm 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256∼2K, DAB, and 2K-mode DVB.

Least reliable bits coding (LRBC) for high data rate satellite communications

Science.gov (United States)

Vanderaar, Mark; Budinger, James; Wagner, Paul

1992-01-01

LRBC, a bandwidth efficient multilevel/multistage block-coded modulation technique, is analyzed. LRBC uses simple multilevel component codes that provide increased error protection on increasingly unreliable modulated bits in order to maintain an overall high code rate that increases spectral efficiency. Soft-decision multistage decoding is used to make decisions on unprotected bits through corrections made on more protected bits. Analytical expressions and tight performance bounds are used to show that LRBC can achieve increased spectral efficiency and maintain equivalent or better power efficiency compared to that of BPSK. The relative simplicity of Galois field algebra vs the Viterbi algorithm and the availability of high-speed commercial VLSI for block codes indicates that LRBC using block codes is a desirable method for high data rate implementations.

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

Directory of Open Access Journals (Sweden)

Ying-Lun Chen

2015-08-01

Full Text Available A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO, and the feature extraction is carried out by the generalized Hebbian algorithm (GHA. To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

Science.gov (United States)

Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

2015-08-13

A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

Science.gov (United States)

Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

2015-01-01

A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction. PMID:26287193

New developments in double sided silicon strip detectors

International Nuclear Information System (INIS)

Becker, H.; Boulos, T.; Cattaneo, P.; Dietl, H.; Hauff, D.; Holl, P.; Lange, E.; Lutz, G.; Moser, H.G.; Schwarz, A.S.; Settles, R.; Struder, L.; Kemmer, J.; Buttler, W.

1990-01-01

A new type of double sided silicon strip detector has been built and tested using highly density VLSI readout electronics connected to both sides. Capacitive coupling of the strips to the readout electronics has been achieved by integrating the capacitors into the detector design, which was made possible by introducing a new detector biasing concept. Schemes to simplify the technology of the fabrication of the detectors are discussed. The static performance properties of the devices as well as implications of the use of VLSI electronics in their readout are described. Prototype detectors of the described design equipped with high density readout electronics have been installed in the ALEPH detector at LEP. Test results on the performance are given

VLSI design of an RSA encryption/decryption chip using systolic array based architecture

Science.gov (United States)

Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

2016-09-01

This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

CASTOR a VLSI CMOS mixed analog-digital circuit for low noise multichannel counting applications

International Nuclear Information System (INIS)

Comes, G.; Loddo, F.; Hu, Y.; Kaplon, J.; Ly, F.; Turchetta, R.; Bonvicini, V.; Vacchi, A.

1996-01-01

In this paper we present the design and first experimental results of a VLSI mixed analog-digital 1.2 microns CMOS circuit (CASTOR) for multichannel radiation detectors applications demanding low noise amplification and counting of radiation pulses. This circuit is meant to be connected to pixel-like detectors. Imaging can be obtained by counting the number of hits in each pixel during a user-controlled exposure time. Each channel of the circuit features an analog and a digital part. In the former one, a charge preamplifier is followed by a CR-RC shaper with an output buffer and a threshold discriminator. In the digital part, a 16-bit counter is present together with some control logic. The readout of the counters is done serially on a common tri-state output. Daisy-chaining is possible. A 4-channel prototype has been built. This prototype has been optimised for use in the digital radiography Syrmep experiment at the Elettra synchrotron machine in Trieste (Italy): its main design parameters are: shaping time of about 850 ns, gain of 190 mV/fC and ENC (e - rms)=60+17 C (pF). The counting rate per channel, limited by the analog part, can be as high as about 200 kHz. Characterisation of the circuit and first tests with silicon microstrip detectors are presented. They show the circuit works according to design specification and can be used for imaging applications. (orig.)

Design and Performance of Soft Gamma-ray Detector for NeXT Mission

Science.gov (United States)

Tajima, H.; Kamae, T.; Madejski, G.; Takahashi, T.; Nakazawa, K.; Watanabe, S.; Mitani, T.; Tanaka, T.; Fukazawa, Y.; Kataoka, J.; Ikagawa, T.; Kokubun, M.; Makishima, K.; Terada, Y.; Nomachi, M.; Tashiro, M.

The Soft Gamma-ray Detector (SGD) on board NeXT (Japanese future high energy astrophysics mission) is a Compton telescope with narrow field of view, which utilizes Compton kinematics to enhance its background rejection capabilities. It is realized as a hybrid semiconductor gamma-ray detector which consists of silicon and Cadmium Telluride (CdTe) detectors. It can detect photons in an energy band 0.05-1 MeV at a background level of 5×10-7 counts/s/cm2/keV; the silicon layers are required to improve the performance at a lower energy band (development of key technologies to realize the SGD; high quality CdTe, low noise front-end VLSI and bump bonding technology. Energy resolutions of 1.7 keV (FWHM) for CdTe pixel detectors and 1.1 keV for silicon strip detectors have been measured. We also present the validation of Monte Carlo simulation used to evaluate the performance of the SGD.

Proceedings of the workshop on new solid state devices for high energy physics

International Nuclear Information System (INIS)

1987-12-01

This paper contains articles on semiconductor devices used in the detection of high energy particles. Some articles reported: Position sensitive semiconductor devices; Scintillation techniques and optical devices; Radiation damage to detectors; VLSI for physics; and experience with Si detectors in NA32

Design of two-terminal PNPN diode for high-density and high-speed memory applications

International Nuclear Information System (INIS)

Tong Xiaodong; Wu Hao; Liang Qingqing; Zhong Huicai; Zhu Huilong; Zhao Chao; Ye Tianchun

2014-01-01

A vertical two-terminal silicon PNPN diode is presented for use in a high-density memory cell. The device design for high-speed operations was studied with experiments and calibrated simulations, which proves that the proposed memory cell can be operated at nanosecond range. The static and dynamic power dissipations were also studied, which indicated the availability of the proposed memory cell for VLSI applications. Moreover, the memory cell is compatible with CMOS process, has little impact from process variation, and has good reliability. (semiconductor devices)

A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

Science.gov (United States)

Kwatra, S. C.; King, Brent

1995-01-01

This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System.

Science.gov (United States)

Sheik, Sadique; Coath, Martin; Indiveri, Giacomo; Denham, Susan L; Wennekers, Thomas; Chicca, Elisabetta

2012-01-01

Many sounds of ecological importance, such as communication calls, are characterized by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamo-cortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP), which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectro-temporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step toward the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

Emergent auditory feature tuning in a real-time neuromorphic VLSI system

Directory of Open Access Journals (Sweden)

Sadique eSheik

2012-02-01

Full Text Available Many sounds of ecological importance, such as communication calls, are characterised by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamocortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP, which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectrotemporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step towards the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

A method to quench and recharge avalanche photo diodes for use in high rate situations

International Nuclear Information System (INIS)

Regan, T.O.; Fenker, H.C.; Thomas, J.; Oliver, J.

1992-06-01

We present a new method of using Avalanche Photo Diodes (APDS) for low level light detection in Geiger mode in high rate situations such as those encountered at the Superconducting Super Collider (SSC). The new technique is readily adaptable to implementation in CMOS VLSI

Flip-flop design in nanometer CMOS from high speed to low energy

CERN Document Server

Alioto, Massimo; Palumbo, Gaetano

2015-01-01

This book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics and process/voltage/temperature variations, as main advances over the existing body of work in the field. The related design tradeoffs are explored in a wide range of applications and the related energy-performance targets. A wide range of existing and recently proposed Flip-Flop topologies are discussed. Theoretical foundations are provided to set the stage for the derivation of design guidelines, and emphasis is given on practical aspects and consequences of the presented results. Analytical models and derivations are introduced when needed to gai...

Implementation of neuromorphic systems: from discrete components to analog VLSI chips (testing and communication issues).

Science.gov (United States)

Dante, V; Del Giudice, P; Mattia, M

2001-01-01

We review a series of implementations of electronic devices aiming at imitating to some extent structure and function of simple neural systems, with particular emphasis on communication issues. We first provide a short overview of general features of such "neuromorphic" devices and the implications of setting up "tests" for them. We then review the developments directly related to our work at the Istituto Superiore di Sanità (ISS): a pilot electronic neural network implementing a simple classifier, autonomously developing internal representations of incoming stimuli; an output network, collecting information from the previous classifier and extracting the relevant part to be forwarded to the observer; an analog, VLSI (very large scale integration) neural chip implementing a recurrent network of spiking neurons and plastic synapses, and the test setup for it; a board designed to interface the standard PCI (peripheral component interconnect) bus of a PC with a special purpose, asynchronous bus for communication among neuromorphic chips; a short and preliminary account of an application-oriented device, taking advantage of the above communication infrastructure.

Robust working memory in an asynchronously spiking neural network realized in neuromorphic VLSI

Directory of Open Access Journals (Sweden)

Massimiliano eGiulioni

2012-02-01

Full Text Available We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory of integrate-and-fire (LIF neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of ‘high’ and ‘low’-firing activity. Depending on the overall excitability, transitions to the ‘high’ state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the ‘high’ state retains a working memory of a stimulus until well after its release. In the latter case, ‘high’ states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated corrupted ‘high’ states comprising neurons of both excitatory populations. Within a basin of attraction, the network dynamics corrects such states and re-establishes the prototypical ‘high’ state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

Development of an integrated circuit VLSI used for time measurement and selective read out in the front end electronics of the DIRC for the Babar experience at SLAC; Developpement d'un circuit integre VLSI assurant mesure de temps et lecture selective dans l'electronique frontale du compteur DIRC de l'experience babar a slac

Energy Technology Data Exchange (ETDEWEB)

Zhang, B

1999-07-01

This thesis deals with the design the development and the tests of an integrated circuit VLSI, supplying selective read and time measure for 16 channels. This circuit has been developed for a experiment of particles physics, BABAR, that will take place at SLAC (Stanford Linear Accelerator Center). A first part describes the physical stakes of the experiment, the electronic architecture and the place of the developed circuit in the research program. The second part presents the technical drawings of the circuit, the prototypes leading to the final design and the validity tests. (A.L.B.)

DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency

Directory of Open Access Journals (Sweden)

David Raphaël

2008-01-01

Full Text Available Abstract Flexibility becomes a major concern for the development of multimedia and mobile communication systems, as well as classical high-performance and low-energy consumption constraints. The use of general-purpose processors solves flexibility problems but fails to cope with the increasing demand for energy efficiency. This paper presents the DART architecture based on the functional-level reconfiguration paradigm which allows a significant improvement in energy efficiency. DART is built around a hierarchical interconnection network allowing high flexibility while keeping the power overhead low. To enable specific optimizations, DART supports two modes of reconfiguration. The compilation framework is built using compilation and high-level synthesis techniques. A 3G mobile communication application has been implemented as a proof of concept. The energy distribution within the architecture and the physical implementation are also discussed. Finally, the VLSI design of a 0.13  m CMOS SoC implementing a specialized DART cluster is presented.

DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency

Directory of Open Access Journals (Sweden)

Sébastien Pillement

2007-12-01

Full Text Available Flexibility becomes a major concern for the development of multimedia and mobile communication systems, as well as classical high-performance and low-energy consumption constraints. The use of general-purpose processors solves flexibility problems but fails to cope with the increasing demand for energy efficiency. This paper presents the DART architecture based on the functional-level reconfiguration paradigm which allows a significant improvement in energy efficiency. DART is built around a hierarchical interconnection network allowing high flexibility while keeping the power overhead low. To enable specific optimizations, DART supports two modes of reconfiguration. The compilation framework is built using compilation and high-level synthesis techniques. A 3G mobile communication application has been implemented as a proof of concept. The energy distribution within the architecture and the physical implementation are also discussed. Finally, the VLSI design of a 0.13 μm CMOS SoC implementing a specialized DART cluster is presented.

Computer-aided design of microfluidic very large scale integration (mVLSI) biochips design automation, testing, and design-for-testability

CERN Document Server

Hu, Kai; Ho, Tsung-Yi

2017-01-01

This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques. Offers the first practical problem formulation for automated control-layer design in flow-based microfluidic biochips and provides a systematic approach for solving this problem; Introduces a wash-optimization method for cross-contamination removal; Presents a design-for-testability (DfT) technique that can achieve 100...

Performance of a beam telescope using double sided silicon microstrip detectors

International Nuclear Information System (INIS)

Fischer, P.; Menke, S.; Wermes, N.

1995-04-01

A beam telescope consisting of four double sided, DC coupled microstrip detectors with VLSI readout electronics has been built and tested in a 70 GeV μ - beam at CERN. A signal to noise ratio of 53:1 and a spatial resolution of 2.7 μm (junction side) and 4.8 μm (ohmic side) have been observed on the best detectors. A telescope performance for a particle track of σ xy =2-3 μm and σ slope =2-3 μrad on the front face of a test object was achieved. (orig.)

High performance homes

DEFF Research Database (Denmark)

Beim, Anne; Vibæk, Kasper Sánchez

2014-01-01

Can prefabrication contribute to the development of high performance homes? To answer this question, this chapter defines high performance in more broadly inclusive terms, acknowledging the technical, architectural, social and economic conditions under which energy consumption and production occur....... Consideration of all these factors is a precondition for a truly integrated practice and as this chapter demonstrates, innovative project delivery methods founded on the manufacturing of prefabricated buildings contribute to the production of high performance homes that are cost effective to construct, energy...

Reliability evaluation of high-performance, low-power FinFET standard cells based on mixed RBB/FBB technique

Science.gov (United States)

Wang, Tian; Cui, Xiaoxin; Ni, Yewen; Liao, Kai; Liao, Nan; Yu, Dunshan; Cui, Xiaole

2017-04-01

With shrinking transistor feature size, the fin-type field-effect transistor (FinFET) has become the most promising option in low-power circuit design due to its superior capability to suppress leakage. To support the VLSI digital system flow based on logic synthesis, we have designed an optimized high-performance low-power FinFET standard cell library based on employing the mixed FBB/RBB technique in the existing stacked structure of each cell. This paper presents the reliability evaluation of the optimized cells under process and operating environment variations based on Monte Carlo analysis. The variations are modelled with Gaussian distribution of the device parameters and 10000 sweeps are conducted in the simulation to obtain the statistical properties of the worst-case delay and input-dependent leakage for each cell. For comparison, a set of non-optimal cells that adopt the same topology without employing the mixed biasing technique is also generated. Experimental results show that the optimized cells achieve standard deviation reduction of 39.1% and 30.7% at most in worst-case delay and input-dependent leakage respectively while the normalized deviation shrinking in worst-case delay and input-dependent leakage can be up to 98.37% and 24.13%, respectively, which demonstrates that our optimized cells are less sensitive to variability and exhibit more reliability. Project supported by the National Natural Science Foundation of China (No. 61306040), the State Key Development Program for Basic Research of China (No. 2015CB057201), the Beijing Natural Science Foundation (No. 4152020), and Natural Science Foundation of Guangdong Province, China (No. 2015A030313147).

Smart AD and DA Converters

NARCIS (Netherlands)

Roermund, van A.H.M.; Hegt, J.A.; Harpe, P.J.A.; Radulov, G.I.; Zanikopoulos, A.; Doris, K.; Quinn, P.J.

2005-01-01

In this paper, a concept is proposed to solve the problems related to the embedding of AD and DA converters in system-on-chips, FPGAs or other VLSI solutions. Problems like embedded testing, yield, reliability and reduced design space become crucial bottlenecks in the integration of high-performance

A VLSI recurrent network of integrate-and-fire neurons connected by plastic synapses with long-term memory.

Science.gov (United States)

Chicca, E; Badoni, D; Dante, V; D'Andreagiovanni, M; Salina, G; Carota, L; Fusi, S; Del Giudice, P

2003-01-01

Electronic neuromorphic devices with on-chip, on-line learning should be able to modify quickly the synaptic couplings to acquire information about new patterns to be stored (synaptic plasticity) and, at the same time, preserve this information on very long time scales (synaptic stability). Here, we illustrate the electronic implementation of a simple solution to this stability-plasticity problem, recently proposed and studied in various contexts. It is based on the observation that reducing the analog depth of the synapses to the extreme (bistable synapses) does not necessarily disrupt the performance of the device as an associative memory, provided that 1) the number of neurons is large enough; 2) the transitions between stable synaptic states are stochastic; and 3) learning is slow. The drastic reduction of the analog depth of the synaptic variable also makes this solution appealing from the point of view of electronic implementation and offers a simple methodological alternative to the technological solution based on floating gates. We describe the full custom analog very large-scale integration (VLSI) realization of a small network of integrate-and-fire neurons connected by bistable deterministic plastic synapses which can implement the idea of stochastic learning. In the absence of stimuli, the memory is preserved indefinitely. During the stimulation the synapse undergoes quick temporary changes through the activities of the pre- and postsynaptic neurons; those changes stochastically result in a long-term modification of the synaptic efficacy. The intentionally disordered pattern of connectivity allows the system to generate a randomness suited to drive the stochastic selection mechanism. We check by a suitable stimulation protocol that the stochastic synaptic plasticity produces the expected pattern of potentiation and depression in the electronic network.

Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition.

Science.gov (United States)

Carvajal, Gonzalo; Figueroa, Miguel

2014-07-01

Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods. Copyright © 2014 Elsevier Ltd. All rights

FastTracker performance using the new“Variable Resolution Associative Memory”for Atlas

CERN Document Server

Iizawa, T; The ATLAS collaboration

2012-01-01

We report on performances of the new “variable resolution Associative Memory (AM)”applied to the reconstruction of top pair events buried in a large pile-up environment using the ATLAS detector. The AM is a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture. The AM is optimized for on-line track finding in high-energy physics experiments. Pattern matching is carried out by finding track candidates in coarse resolution “roads”. A large AM bank stores all trajectories of interest, called “patterns”, for a given detector resolution. The AM extracts roads compatible with a given event during detector read-out. Two important variables characterize the quality of the AM bank: its “coverage” (the fraction of tracks that match at least one pattern in the bank) and the level of “fake candidates” (roughly proportional to the number of patterns in the bank). As the luminosity increases, the fake rate increases rapidly because of the increased silicon occupan...

High Performance Marine Vessels

CERN Document Server

Yun, Liang

2012-01-01

High Performance Marine Vessels (HPMVs) range from the Fast Ferries to the latest high speed Navy Craft, including competition power boats and hydroplanes, hydrofoils, hovercraft, catamarans and other multi-hull craft. High Performance Marine Vessels covers the main concepts of HPMVs and discusses historical background, design features, services that have been successful and not so successful, and some sample data of the range of HPMVs to date. Included is a comparison of all HPMVs craft and the differences between them and descriptions of performance (hydrodynamics and aerodynamics). Readers will find a comprehensive overview of the design, development and building of HPMVs. In summary, this book: Focuses on technology at the aero-marine interface Covers the full range of high performance marine vessel concepts Explains the historical development of various HPMVs Discusses ferries, racing and pleasure craft, as well as utility and military missions High Performance Marine Vessels is an ideal book for student...

CHICSi--a compact ultra-high vacuum compatible detector system for nuclear reaction experiments at storage rings. III. readout system

Energy Technology Data Exchange (ETDEWEB)

Carlen, L.; Foerre, G.; Golubev, P.; Jakobsson, B. E-mail: bo.jakobsson@kosufy.lu.se; Kolozhvari, A.; Marciniewski, P.; Siwek, A.; Veldhuizen, E.J. van; Westerberg, L.; Whitlow, H.J.; Oestby, J.M

2004-01-11

(CHICSi) Celsius Heavy Ion Collaboration Si detector system is a high granularity, modular detector telescope array for operation around the cluster-jet target/circulating beam intersection of the CELSIUS storage ring at the The. Svedberg Laboratory in Uppsala, Sweden. It is able to provide identity and momentum vector of up to 100 charged particles and fragments from proton-nucleus and nucleus-nucleus collisions at intermediate energies, 50-1000A MeV. All detector telescopes as well as the major part of electronic readout system are placed inside the target chamber in ultra-high vacuum (UHV, 10{sup -9}-10{sup -7} Pa). This requires Very Large Scale Integrated (VLSI) microchip for the spectroscopic signal processing and the generation and transport of digital control signals. Eighteen telescopes, read out with chip-on-board technique by ceramics Mother Boards (MB) and corresponding 18 microchips are mounted on a 450x45 mm{sup 2} Grand Mother Board (GMB), processed on FR4 glass-fibre material. Each of these 28 GMB units contains a daisy-chain organisation of the VLSI chips and associated protection circuits. Analogue-to-digital conversion of the spectroscopic signals is performed on a board outside the chamber which is connected on one side to a power distribution board, directly attached to a UHV mounting flange, and on the other side to the VME-based data acquisition system (CHICSiDAQ). This in its turn is connected via a fibre-optic link to the general TSL acquisition system (SVEDAQ), and in this way data from auxiliary detector systems, read out in CAMAC mode, can be stored in coincidence with CHICSi data.

CHICSi--a compact ultra-high vacuum compatible detector system for nuclear reaction experiments at storage rings. III. readout system

International Nuclear Information System (INIS)

Carlen, L.; Foerre, G.; Golubev, P.; Jakobsson, B.; Kolozhvari, A.; Marciniewski, P.; Siwek, A.; Veldhuizen, E.J. van; Westerberg, L.; Whitlow, H.J.; Oestby, J.M.

2004-01-01

(CHICSi) Celsius Heavy Ion Collaboration Si detector system is a high granularity, modular detector telescope array for operation around the cluster-jet target/circulating beam intersection of the CELSIUS storage ring at the The. Svedberg Laboratory in Uppsala, Sweden. It is able to provide identity and momentum vector of up to 100 charged particles and fragments from proton-nucleus and nucleus-nucleus collisions at intermediate energies, 50-1000A MeV. All detector telescopes as well as the major part of electronic readout system are placed inside the target chamber in ultra-high vacuum (UHV, 10 -9 -10 -7 Pa). This requires Very Large Scale Integrated (VLSI) microchip for the spectroscopic signal processing and the generation and transport of digital control signals. Eighteen telescopes, read out with chip-on-board technique by ceramics Mother Boards (MB) and corresponding 18 microchips are mounted on a 450x45 mm 2 Grand Mother Board (GMB), processed on FR4 glass-fibre material. Each of these 28 GMB units contains a daisy-chain organisation of the VLSI chips and associated protection circuits. Analogue-to-digital conversion of the spectroscopic signals is performed on a board outside the chamber which is connected on one side to a power distribution board, directly attached to a UHV mounting flange, and on the other side to the VME-based data acquisition system (CHICSiDAQ). This in its turn is connected via a fibre-optic link to the general TSL acquisition system (SVEDAQ), and in this way data from auxiliary detector systems, read out in CAMAC mode, can be stored in coincidence with CHICSi data

High performance systems

Energy Technology Data Exchange (ETDEWEB)

Vigil, M.B. [comp.

1995-03-01

This document provides a written compilation of the presentations and viewgraphs from the 1994 Conference on High Speed Computing given at the High Speed Computing Conference, {open_quotes}High Performance Systems,{close_quotes} held at Gleneden Beach, Oregon, on April 18 through 21, 1994.

Design and Implementation of a Sort-Free K-Best Sphere Decoder

KAUST Repository

Mondal, Sudip

2012-10-18

This paper describes the design and VLSI architecture for a 4x4 breadth first K-Best MIMO decoder using a 64 QAM scheme. A novel sort free approach to path extension, as well as quantized metrics result in a high throughput VLSI architecture with lower power and area consumption compared to state of the art published systems. Functionality is confirmed via an FPGA implementation on a Xilinx Virtex II Pro FPGA. Comparison of simulation and measurements are given and FPGA utilization figures are provided. Finally, VLSI architectural tradeoffs are explored for a synthesized ASIC implementation in a 65nm CMOS technology.

Telemetry advances in data compression and channel coding

Science.gov (United States)

Miller, Warner H.; Morakis, James C.; Yeh, Pen-Shu

1990-01-01

Addressed in this paper is the dependence of telecommunication channel, forward error correcting coding and source data compression coding on integrated circuit technology. Emphasis is placed on real time high speed Reed Solomon (RS) decoding using full custom VLSI technology. Performance curves of NASA's standard channel coder and a proposed standard lossless data compression coder are presented.

Possible applications of the sigma delta digitizer in particle physics

International Nuclear Information System (INIS)

Hallgren, B.

1991-01-01

The sigma delta (ΣΔ) principle is an analog-to-digital conversion technique based on high-frequency sampling and low-pass filtering of the quantization noise. Resolution in time is exchanged for that in amplitude so as to avoid the difficulty of implementing complex precision analog circuits, in favour of digital circuits. The approach is attractive because it will make it possible to integrate complete channels of high resolution analog-to-digital converters and time digitizers in submicron digital VLSI technologies. Advantage is taken of the fact that the state-of-the-art VLSI is better suited for providing fast digital circuits than for providing precise analog circuits. This article describes the principle and the performance of the ideal ΣΔ digitizer. The design and measurements of a new 10 MHz prototype circuit of a second-order ΣΔ is presented to show the high speed operation of such a circuit. The expected performance of a CMOS test design using the same principles is discussed. Digital filters, useful for particle physics, are introduced. A comparison to other digitizing techniques is made and the potential applications of the ΣΔ digitizer in particle physics are outlined. (orig.)

High performance work practices, innovation and performance

DEFF Research Database (Denmark)

Jørgensen, Frances; Newton, Cameron; Johnston, Kim

2013-01-01

Research spanning nearly 20 years has provided considerable empirical evidence for relationships between High Performance Work Practices (HPWPs) and various measures of performance including increased productivity, improved customer service, and reduced turnover. What stands out from......, and Africa to examine these various questions relating to the HPWP-innovation-performance relationship. Each paper discusses a practice that has been identified in HPWP literature and potential variables that can facilitate or hinder the effects of these practices of innovation- and performance...

Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

Science.gov (United States)

Pin, Francois G.; Watanabe, Yutaka

1993-01-01

Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

RavenDB high performance

CERN Document Server

Ritchie, Brian

2013-01-01

RavenDB High Performance is comprehensive yet concise tutorial that developers can use to.This book is for developers & software architects who are designing systems in order to achieve high performance right from the start. A basic understanding of RavenDB is recommended, but not required. While the book focuses on advanced topics, it does not assume that the reader has a great deal of prior knowledge of working with RavenDB.

High-performance computing using FPGAs

CERN Document Server

Benkrid, Khaled

2013-01-01

This book is concerned with the emerging field of High Performance Reconfigurable Computing (HPRC), which aims to harness the high performance and relative low power of reconfigurable hardware–in the form Field Programmable Gate Arrays (FPGAs)–in High Performance Computing (HPC) applications. It presents the latest developments in this field from applications, architecture, and tools and methodologies points of view. We hope that this work will form a reference for existing researchers in the field, and entice new researchers and developers to join the HPRC community.  The book includes:  Thirteen application chapters which present the most important application areas tackled by high performance reconfigurable computers, namely: financial computing, bioinformatics and computational biology, data search and processing, stencil computation e.g. computational fluid dynamics and seismic modeling, cryptanalysis, astronomical N-body simulation, and circuit simulation.     Seven architecture chapters which...

High-Performance Networking

CERN Multimedia

CERN. Geneva

2003-01-01

The series will start with an historical introduction about what people saw as high performance message communication in their time and how that developed to the now to day known "standard computer network communication". It will be followed by a far more technical part that uses the High Performance Computer Network standards of the 90's, with 1 Gbit/sec systems as introduction for an in depth explanation of the three new 10 Gbit/s network and interconnect technology standards that exist already or emerge. If necessary for a good understanding some sidesteps will be included to explain important protocols as well as some necessary details of concerned Wide Area Network (WAN) standards details including some basics of wavelength multiplexing (DWDM). Some remarks will be made concerning the rapid expanding applications of networked storage.

High Performance Concrete

Directory of Open Access Journals (Sweden)

Traian Oneţ

2009-01-01

Full Text Available The paper presents the last studies and researches accomplished in Cluj-Napoca related to high performance concrete, high strength concrete and self compacting concrete. The purpose of this paper is to raid upon the advantages and inconveniences when a particular concrete type is used. Two concrete recipes are presented, namely for the concrete used in rigid pavement for roads and another one for self-compacting concrete.

HPTA: High-Performance Text Analytics

OpenAIRE

Vandierendonck, Hans; Murphy, Karen; Arif, Mahwish; Nikolopoulos, Dimitrios S.

2017-01-01

One of the main targets of data analytics is unstructured data, which primarily involves textual data. High-performance processing of textual data is non-trivial. We present the HPTA library for high-performance text analytics. The library helps programmers to map textual data to a dense numeric representation, which can be handled more efficiently. HPTA encapsulates three performance optimizations: (i) efficient memory management for textual data, (ii) parallel computation on associative dat...

Pressurized planar electrochromatography, high-performance thin-layer chromatography and high-performance liquid chromatography--comparison of performance.

Science.gov (United States)

Płocharz, Paweł; Klimek-Turek, Anna; Dzido, Tadeusz H

2010-07-16

Kinetic performance, measured by plate height, of High-Performance Thin-Layer Chromatography (HPTLC), High-Performance Liquid Chromatography (HPLC) and Pressurized Planar Electrochromatography (PPEC) was compared for the systems with adsorbent of the HPTLC RP18W plate from Merck as the stationary phase and the mobile phase composed of acetonitrile and buffer solution. The HPLC column was packed with the adsorbent, which was scrapped from the chromatographic plate mentioned. An additional HPLC column was also packed with adsorbent of 5 microm particle diameter, C18 type silica based (LiChrosorb RP-18 from Merck). The dependence of plate height of both HPLC and PPEC separating systems on flow velocity of the mobile phase and on migration distance of the mobile phase in TLC system was presented applying test solute (prednisolone succinate). The highest performance, amongst systems investigated, was obtained for the PPEC system. The separation efficiency of the systems investigated in the paper was additionally confirmed by the separation of test component mixture composed of six hormones. 2010 Elsevier B.V. All rights reserved.

High Performance Computing in Science and Engineering '15 : Transactions of the High Performance Computing Center

CERN Document Server

Kröner, Dietmar; Resch, Michael

2016-01-01

This book presents the state-of-the-art in supercomputer simulation. It includes the latest findings from leading researchers using systems from the High Performance Computing Center Stuttgart (HLRS) in 2015. The reports cover all fields of computational science and engineering ranging from CFD to computational physics and from chemistry to computer science with a special emphasis on industrially relevant applications. Presenting findings of one of Europe’s leading systems, this volume covers a wide variety of applications that deliver a high level of sustained performance. The book covers the main methods in high-performance computing. Its outstanding results in achieving the best performance for production codes are of particular interest for both scientists and engineers. The book comes with a wealth of color illustrations and tables of results.

High Performance Computing in Science and Engineering '17 : Transactions of the High Performance Computing Center

CERN Document Server

Kröner, Dietmar; Resch, Michael; HLRS 2017

2018-01-01

This book presents the state-of-the-art in supercomputer simulation. It includes the latest findings from leading researchers using systems from the High Performance Computing Center Stuttgart (HLRS) in 2017. The reports cover all fields of computational science and engineering ranging from CFD to computational physics and from chemistry to computer science with a special emphasis on industrially relevant applications. Presenting findings of one of Europe’s leading systems, this volume covers a wide variety of applications that deliver a high level of sustained performance.The book covers the main methods in high-performance computing. Its outstanding results in achieving the best performance for production codes are of particular interest for both scientists and engineers. The book comes with a wealth of color illustrations and tables of results.

1 million-Q optomechanical microdisk resonators for sensing with very large scale integration

Science.gov (United States)

Hermouet, M.; Sansa, M.; Banniard, L.; Fafin, A.; Gely, M.; Allain, P. E.; Santos, E. Gil; Favero, I.; Alava, T.; Jourdan, G.; Hentz, S.

2018-02-01

Cavity optomechanics have become a promising route towards the development of ultrasensitive sensors for a wide range of applications including mass, chemical and biological sensing. In this study, we demonstrate the potential of Very Large Scale Integration (VLSI) with state-of-the-art low-loss performance silicon optomechanical microdisks for sensing applications. We report microdisks exhibiting optical Whispering Gallery Modes (WGM) with 1 million quality factors, yielding high displacement sensitivity and strong coupling between optical WGMs and in-plane mechanical Radial Breathing Modes (RBM). Such high-Q microdisks with mechanical resonance frequencies in the 102 MHz range were fabricated on 200 mm wafers with Variable Shape Electron Beam lithography. Benefiting from ultrasensitive readout, their Brownian motion could be resolved with good Signal-to-Noise ratio at ambient pressure, as well as in liquid, despite high frequency operation and large fluidic damping: the mechanical quality factor reduced from few 103 in air to 10's in liquid, and the mechanical resonance frequency shifted down by a few percent. Proceeding one step further, we performed an all-optical operation of the resonators in air using a pump-probe scheme. Our results show our VLSI process is a viable approach for the next generation of sensors operating in vacuum, gas or liquid phase.

High-Performance Operating Systems

DEFF Research Database (Denmark)

Sharp, Robin

1999-01-01

Notes prepared for the DTU course 49421 "High Performance Operating Systems". The notes deal with quantitative and qualitative techniques for use in the design and evaluation of operating systems in computer systems for which performance is an important parameter, such as real-time applications......, communication systems and multimedia systems....

A high performance cost-effective digital complex correlator for an X-band polarimetry survey.

Science.gov (United States)

Bergano, Miguel; Rocha, Armando; Cupido, Luís; Barbosa, Domingos; Villela, Thyrso; Boas, José Vilas; Rocha, Graça; Smoot, George F

2016-01-01

The detailed knowledge of the Milky Way radio emission is important to characterize galactic foregrounds masking extragalactic and cosmological signals. The update of the global sky models describing radio emissions over a very large spectral band requires high sensitivity experiments capable of observing large sky areas with long integration times. Here, we present the design of a new 10 GHz (X-band) polarimeter digital back-end to map the polarization components of the galactic synchrotron radiation field of the Northern Hemisphere sky. The design follows the digital processing trends in radio astronomy and implements a large bandwidth (1 GHz) digital complex cross-correlator to extract the Stokes parameters of the incoming synchrotron radiation field. The hardware constraints cover the implemented VLSI hardware description language code and the preliminary results. The implementation is based on the simultaneous digitized acquisition of the Cartesian components of the two linear receiver polarization channels. The design strategy involves a double data rate acquisition of the ADC interleaved parallel bus, and field programmable gate array device programming at the register transfer mode. The digital core of the back-end is capable of processing 32 Gbps and is built around an Altera field programmable gate array clocked at 250 MHz, 1 GSps analog to digital converters and a clock generator. The control of the field programmable gate array internal signal delays and a convenient use of its phase locked loops provide the timing requirements to achieve the target bandwidths and sensitivity. This solution is convenient for radio astronomy experiments requiring large bandwidth, high functionality, high volume availability and low cost. Of particular interest, this correlator was developed for the Galactic Emission Mapping project and is suitable for large sky area polarization continuum surveys. The solutions may also be adapted to be used at signal processing

VLSI for High-Speed Digital Signal Processing

Science.gov (United States)

1994-09-30

particular, the design, layout and fab - rication of integrated circuits. The primary project for this grant has been the design and implementation of a...targeted at 33.36 dB, and PSNR (dB) Rate ( bpp ) the FRSBC algorithm, targeted at 0.5 bits/pixel, respec- Filter FDSBC FRSBC FDSBC FRSBC tively. The filter...to mean square error d by as shown in Fig. 6, is used, yielding a total of 16 subbands. 255’ The rates, in bits per pixel ( bpp ), and the peak signal

Custom VLSI circuits for high energy physics

International Nuclear Information System (INIS)

Parker, S.

1998-06-01

This article provides a brief guide to integrated circuits, including their design, fabrication, testing, radiation hardness, and packaging. It was requested by the Panel on Instrumentation, Innovation, and Development of the International Committee for Future Accelerators, as one of a series of articles on instrumentation for future experiments. Their original request emphasized a description of available custom circuits and a set of recommendations for future developments. That has been done, but while traps that stop charge in solid-state devices are well known, those that stop physicists trying to develop the devices are not. Several years spent dodging the former and developing the latter made clear the need for a beginner's guide through the maze, and that is the main purpose of this text

Custom VLSI circuits for high energy physics

Energy Technology Data Exchange (ETDEWEB)

Parker, S. [Univ. of Hawaii, Honolulu, HI (United States)

1998-06-01

This article provides a brief guide to integrated circuits, including their design, fabrication, testing, radiation hardness, and packaging. It was requested by the Panel on Instrumentation, Innovation, and Development of the International Committee for Future Accelerators, as one of a series of articles on instrumentation for future experiments. Their original request emphasized a description of available custom circuits and a set of recommendations for future developments. That has been done, but while traps that stop charge in solid-state devices are well known, those that stop physicists trying to develop the devices are not. Several years spent dodging the former and developing the latter made clear the need for a beginner`s guide through the maze, and that is the main purpose of this text.

Compact Interconnection Networks Based on Quantum Dots

Science.gov (United States)

Fijany, Amir; Toomarian, Nikzad; Modarress, Katayoon; Spotnitz, Matthew

2003-01-01

Architectures that would exploit the distinct characteristics of quantum-dot cellular automata (QCA) have been proposed for digital communication networks that connect advanced digital computing circuits. In comparison with networks of wires in conventional very-large-scale integrated (VLSI) circuitry, the networks according to the proposed architectures would be more compact. The proposed architectures would make it possible to implement complex interconnection schemes that are required for some advanced parallel-computing algorithms and that are difficult (and in many cases impractical) to implement in VLSI circuitry. The difficulty of implementation in VLSI and the major potential advantage afforded by QCA were described previously in Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), NASA Tech Briefs, Vol. 25, No. 10 (October 2001), page 42. To recapitulate: Wherever two wires in a conventional VLSI circuit cross each other and are required not to be in electrical contact with each other, there must be a layer of electrical insulation between them. This, in turn, makes it necessary to resort to a noncoplanar and possibly a multilayer design, which can be complex, expensive, and even impractical. As a result, much of the cost of designing VLSI circuits is associated with minimization of data routing and assignment of layers to minimize crossing of wires. Heretofore, these considerations have impeded the development of VLSI circuitry to implement complex, advanced interconnection schemes. On the other hand, with suitable design and under suitable operating conditions, QCA-based signal paths can be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes. The proposed architectures require two advances in QCA-based circuitry beyond basic QCA-based binary

Signal Processing in Medical Ultrasound B-mode Imaging

International Nuclear Information System (INIS)

Song, Tai Kyong

2000-01-01

Ultrasonic imaging is the most widely used modality among modern imaging device for medical diagnosis and the system performance has been improved dramatically since early 90's due to the rapid advances in DSP performance and VLSI technology that made it possible to employ more sophisticated algorithms. This paper describes 'main stream' digital signal processing functions along with the associated implementation considerations in modern medical ultrasound imaging systems. Topics covered include signal processing methods for resolution improvement, ultrasound imaging system architectures, roles and necessity of the applications of DSP and VLSI technology in the development of the medical ultrasound imaging systems, and array signal processing techniques for ultrasound focusing

High performance fuel technology development

Energy Technology Data Exchange (ETDEWEB)

Koon, Yang Hyun; Kim, Keon Sik; Park, Jeong Yong; Yang, Yong Sik; In, Wang Kee; Kim, Hyung Kyu [KAERI, Daejeon (Korea, Republic of)

2012-01-15

{omicron} Development of High Plasticity and Annular Pellet - Development of strong candidates of ultra high burn-up fuel pellets for a PCI remedy - Development of fabrication technology of annular fuel pellet {omicron} Development of High Performance Cladding Materials - Irradiation test of HANA claddings in Halden research reactor and the evaluation of the in-pile performance - Development of the final candidates for the next generation cladding materials. - Development of the manufacturing technology for the dual-cooled fuel cladding tubes. {omicron} Irradiated Fuel Performance Evaluation Technology Development - Development of performance analysis code system for the dual-cooled fuel - Development of fuel performance-proving technology {omicron} Feasibility Studies on Dual-Cooled Annular Fuel Core - Analysis on the property of a reactor core with dual-cooled fuel - Feasibility evaluation on the dual-cooled fuel core {omicron} Development of Design Technology for Dual-Cooled Fuel Structure - Definition of technical issues and invention of concept for dual-cooled fuel structure - Basic design and development of main structure components for dual- cooled fuel - Basic design of a dual-cooled fuel rod.

High performance homes

DEFF Research Database (Denmark)

Beim, Anne; Vibæk, Kasper Sánchez

2014-01-01

. Consideration of all these factors is a precondition for a truly integrated practice and as this chapter demonstrates, innovative project delivery methods founded on the manufacturing of prefabricated buildings contribute to the production of high performance homes that are cost effective to construct, energy...

Strategy Guideline: High Performance Residential Lighting

Energy Technology Data Exchange (ETDEWEB)

Holton, J.

2012-02-01

The Strategy Guideline: High Performance Residential Lighting has been developed to provide a tool for the understanding and application of high performance lighting in the home. The high performance lighting strategies featured in this guide are drawn from recent advances in commercial lighting for application to typical spaces found in residential buildings. This guide offers strategies to greatly reduce lighting energy use through the application of high quality fluorescent and light emitting diode (LED) technologies. It is important to note that these strategies not only save energy in the home but also serve to satisfy the homeowner's expectations for high quality lighting.

High performance conductometry

International Nuclear Information System (INIS)

Saha, B.

2000-01-01

Inexpensive but high performance systems have emerged progressively for basic and applied measurements in physical and analytical chemistry on one hand, and for on-line monitoring and leak detection in plants and facilities on the other. Salient features of the developments will be presented with specific examples

INL High Performance Building Strategy

Energy Technology Data Exchange (ETDEWEB)

Jennifer D. Morton

2010-02-01

High performance buildings, also known as sustainable buildings and green buildings, are resource efficient structures that minimize the impact on the environment by using less energy and water, reduce solid waste and pollutants, and limit the depletion of natural resources while also providing a thermally and visually comfortable working environment that increases productivity for building occupants. As Idaho National Laboratory (INL) becomes the nation’s premier nuclear energy research laboratory, the physical infrastructure will be established to help accomplish this mission. This infrastructure, particularly the buildings, should incorporate high performance sustainable design features in order to be environmentally responsible and reflect an image of progressiveness and innovation to the public and prospective employees. Additionally, INL is a large consumer of energy that contributes to both carbon emissions and resource inefficiency. In the current climate of rising energy prices and political pressure for carbon reduction, this guide will help new construction project teams to design facilities that are sustainable and reduce energy costs, thereby reducing carbon emissions. With these concerns in mind, the recommendations described in the INL High Performance Building Strategy (previously called the INL Green Building Strategy) are intended to form the INL foundation for high performance building standards. This revised strategy incorporates the latest federal and DOE orders (Executive Order [EO] 13514, “Federal Leadership in Environmental, Energy, and Economic Performance” [2009], EO 13423, “Strengthening Federal Environmental, Energy, and Transportation Management” [2007], and DOE Order 430.2B, “Departmental Energy, Renewable Energy, and Transportation Management” [2008]), the latest guidelines, trends, and observations in high performance building construction, and the latest changes to the Leadership in Energy and Environmental Design

High Performance Networks for High Impact Science

Energy Technology Data Exchange (ETDEWEB)

Scott, Mary A.; Bair, Raymond A.

2003-02-13

This workshop was the first major activity in developing a strategic plan for high-performance networking in the Office of Science. Held August 13 through 15, 2002, it brought together a selection of end users, especially representing the emerging, high-visibility initiatives, and network visionaries to identify opportunities and begin defining the path forward.

High performance fuel technology development : Development of high performance cladding materials

International Nuclear Information System (INIS)

Park, Jeongyong; Jeong, Y. H.; Park, S. Y.

2012-04-01

The superior in-pile performance of the HANA claddings have been verified by the successful irradiation test and in the Halden research reactor up to the high burn-up of 67GWD/MTU. The in-pile corrosion and creep resistances of HANA claddings were improved by 40% and 50%, respectively, over Zircaloy-4. HANA claddings have been also irradiated in the commercial reactor up to 2 reactor cycles, showing the corrosion resistance 40% better than that of ZIRLO in the same fuel assembly. Long-term out-of-pile performance tests for the candidates of the next generation cladding materials have produced the highly reliable test results. The final candidate alloys were selected and they showed the corrosion resistance 50% better than the foreign advanced claddings, which is beyond the original target. The LOCA-related properties were also improved by 20% over the foreign advanced claddings. In order to establish the optimal manufacturing process for the inner and outer claddings of the dual-cooled fuel, 18 different kinds of specimens were fabricated with various cold working and annealing conditions. Based on the performance tests and various out-of-pile test results obtained from the specimens, the optimal manufacturing process was established for the inner and outer cladding tubes of the dual-cooled fuel

Carbon nanomaterials for high-performance supercapacitors

OpenAIRE

Tao Chen; Liming Dai

2013-01-01

Owing to their high energy density and power density, supercapacitors exhibit great potential as high-performance energy sources for advanced technologies. Recently, carbon nanomaterials (especially, carbon nanotubes and graphene) have been widely investigated as effective electrodes in supercapacitors due to their high specific surface area, excellent electrical and mechanical properties. This article summarizes the recent progresses on the development of high-performance supercapacitors bas...

Clojure high performance programming

CERN Document Server

Kumar, Shantanu

2013-01-01

This is a short, practical guide that will teach you everything you need to know to start writing high performance Clojure code.This book is ideal for intermediate Clojure developers who are looking to get a good grip on how to achieve optimum performance. You should already have some experience with Clojure and it would help if you already know a little bit of Java. Knowledge of performance analysis and engineering is not required. For hands-on practice, you should have access to Clojure REPL with Leiningen.

Highly Parallel Computing Architectures by using Arrays of Quantum-dot Cellular Automata (QCA): Opportunities, Challenges, and Recent Results

Science.gov (United States)

Fijany, Amir; Toomarian, Benny N.

2000-01-01

There has been significant improvement in the performance of VLSI devices, in terms of size, power consumption, and speed, in recent years and this trend may also continue for some near future. However, it is a well known fact that there are major obstacles, i.e., physical limitation of feature size reduction and ever increasing cost of foundry, that would prevent the long term continuation of this trend. This has motivated the exploration of some fundamentally new technologies that are not dependent on the conventional feature size approach. Such technologies are expected to enable scaling to continue to the ultimate level, i.e., molecular and atomistic size. Quantum computing, quantum dot-based computing, DNA based computing, biologically inspired computing, etc., are examples of such new technologies. In particular, quantum-dots based computing by using Quantum-dot Cellular Automata (QCA) has recently been intensely investigated as a promising new technology capable of offering significant improvement over conventional VLSI in terms of reduction of feature size (and hence increase in integration level), reduction of power consumption, and increase of switching speed. Quantum dot-based computing and memory in general and QCA specifically, are intriguing to NASA due to their high packing density (10(exp 11) - 10(exp 12) per square cm ) and low power consumption (no transfer of current) and potentially higher radiation tolerant. Under Revolutionary Computing Technology (RTC) Program at the NASA/JPL Center for Integrated Space Microelectronics (CISM), we have been investigating the potential applications of QCA for the space program. To this end, exploiting the intrinsic features of QCA, we have designed novel QCA-based circuits for co-planner (i.e., single layer) and compact implementation of a class of data permutation matrices, a class of interconnection networks, and a bit-serial processor. Building upon these circuits, we have developed novel algorithms and QCA

Delivering high performance BWR fuel reliably

International Nuclear Information System (INIS)

Schardt, J.F.

1998-01-01

Utilities are under intense pressure to reduce their production costs in order to compete in the increasingly deregulated marketplace. They need fuel, which can deliver high performance to meet demanding operating strategies. GE's latest BWR fuel design, GE14, provides that high performance capability. GE's product introduction process assures that this performance will be delivered reliably, with little risk to the utility. (author)

High performance bio-integrated devices

Science.gov (United States)

Kim, Dae-Hyeong; Lee, Jongha; Park, Minjoon

2014-06-01

In recent years, personalized electronics for medical applications, particularly, have attracted much attention with the rise of smartphones because the coupling of such devices and smartphones enables the continuous health-monitoring in patients' daily life. Especially, it is expected that the high performance biomedical electronics integrated with the human body can open new opportunities in the ubiquitous healthcare. However, the mechanical and geometrical constraints inherent in all standard forms of high performance rigid wafer-based electronics raise unique integration challenges with biotic entities. Here, we describe materials and design constructs for high performance skin-mountable bio-integrated electronic devices, which incorporate arrays of single crystalline inorganic nanomembranes. The resulting electronic devices include flexible and stretchable electrophysiology electrodes and sensors coupled with active electronic components. These advances in bio-integrated systems create new directions in the personalized health monitoring and/or human-machine interfaces.

High Performance Macromolecular Material

National Research Council Canada - National Science Library

Forest, M

2002-01-01

.... In essence, most commercial high-performance polymers are processed through fiber spinning, following Nature and spider silk, which is still pound-for-pound the toughest liquid crystalline polymer...

Delivering high performance BWR fuel reliably

Energy Technology Data Exchange (ETDEWEB)

Schardt, J.F. [GE Nuclear Energy, Wilmington, NC (United States)

1998-07-01

Utilities are under intense pressure to reduce their production costs in order to compete in the increasingly deregulated marketplace. They need fuel, which can deliver high performance to meet demanding operating strategies. GE's latest BWR fuel design, GE14, provides that high performance capability. GE's product introduction process assures that this performance will be delivered reliably, with little risk to the utility. (author)

Carpet Aids Learning in High Performance Schools

Science.gov (United States)

Hurd, Frank

2009-01-01

The Healthy and High Performance Schools Act of 2002 has set specific federal guidelines for school design, and developed a federal/state partnership program to assist local districts in their school planning. According to the Collaborative for High Performance Schools (CHPS), high-performance schools are, among other things, healthy, comfortable,…

High-performance-vehicle technology. [fighter aircraft propulsion

Science.gov (United States)

Povinelli, L. A.

1979-01-01

Propulsion needs of high performance military aircraft are discussed. Inlet performance, nozzle performance and cooling, and afterburner performance are covered. It is concluded that nonaxisymmetric nozzles provide cleaner external lines and enhanced maneuverability, but the internal flows are more complex. Swirl afterburners show promise for enhanced performance in the high altitude, low Mach number region.

Academic performance in high school as factor associated to academic performance in college

Directory of Open Access Journals (Sweden)

Mileidy Salcedo Barragán

2008-12-01

Full Text Available This study intends to find the relationship between academic performance in High School and College, focusing on Natural Sciences and Mathematics. It is a descriptive correlational study, and the variables were academic performance in High School, performance indicators and educational history. The correlations between variables were established with Spearman’s correlation coefficient. Results suggest that there is a positive relationship between academic performance in High School and Educational History, and a very weak relationship between performance in Science and Mathematics in High School and performance in College.

High Performance Grinding and Advanced Cutting Tools

CERN Document Server

Jackson, Mark J

2013-01-01

High Performance Grinding and Advanced Cutting Tools discusses the fundamentals and advances in high performance grinding processes, and provides a complete overview of newly-developing areas in the field. Topics covered are grinding tool formulation and structure, grinding wheel design and conditioning and applications using high performance grinding wheels. Also included are heat treatment strategies for grinding tools, using grinding tools for high speed applications, laser-based and diamond dressing techniques, high-efficiency deep grinding, VIPER grinding, and new grinding wheels.

Highlighting High Performance: Whitman Hanson Regional High School; Whitman, Massachusetts

Energy Technology Data Exchange (ETDEWEB)

2006-06-01

This brochure describes the key high-performance building features of the Whitman-Hanson Regional High School. The brochure was paid for by the Massachusetts Technology Collaborative as part of their Green Schools Initiative. High-performance features described are daylighting and energy-efficient lighting, indoor air quality, solar and wind energy, building envelope, heating and cooling systems, water conservation, and acoustics. Energy cost savings are also discussed.

High performance polymeric foams

International Nuclear Information System (INIS)

Gargiulo, M.; Sorrentino, L.; Iannace, S.

2008-01-01

The aim of this work was to investigate the foamability of high-performance polymers (polyethersulfone, polyphenylsulfone, polyetherimide and polyethylenenaphtalate). Two different methods have been used to prepare the foam samples: high temperature expansion and two-stage batch process. The effects of processing parameters (saturation time and pressure, foaming temperature) on the densities and microcellular structures of these foams were analyzed by using scanning electron microscopy

A neural network device for on-line particle identification in cosmic ray experiments

International Nuclear Information System (INIS)

Scrimaglio, R.; Finetti, N.; D'Altorio, L.; Rantucci, E.; Raso, M.; Segreto, E.; Tassoni, A.; Cardarilli, G.C.

2004-01-01

On-line particle identification is one of the main goals of many experiments in space both for rare event studies and for optimizing measurements along the orbital trajectory. Neural networks can be a useful tool for signal processing and real time data analysis in such experiments. In this document we report on the performances of a programmable neural device which was developed in VLSI analog/digital technology. Neurons and synapses were accomplished by making use of Operational Transconductance Amplifier (OTA) structures. In this paper we report on the results of measurements performed in order to verify the agreement of the characteristic curves of each elementary cell with simulations and on the device performances obtained by implementing simple neural structures on the VLSI chip. A feed-forward neural network (Multi-Layer Perceptron, MLP) was implemented on the VLSI chip and trained to identify particles by processing the signals of two-dimensional position-sensitive Si detectors. The radiation monitoring device consisted of three double-sided silicon strip detectors. From the analysis of a set of simulated data it was found that the MLP implemented on the neural device gave results comparable with those obtained with the standard method of analysis confirming that the implemented neural network could be employed for real time particle identification

Responsive design high performance

CERN Document Server

Els, Dewald

2015-01-01

This book is ideal for developers who have experience in developing websites or possess minor knowledge of how responsive websites work. No experience of high-level website development or performance tweaking is required.

Therese: presentation of the project

Energy Technology Data Exchange (ETDEWEB)

Pendibidu, J M

1982-05-01

Therese (Terabit Reseau) is a project built around a powerful local network with high transmission speed. A lot of goodies have been incorporated to the product in order that it can be used as a general multi-purpose tool in such areas as software engineering, artificial intelligence, robotics, office automation, VLSI design, fundamental mechanics, theoretical physics, applied mathematics, computer assisted education, high speed satellite communications, performance evaluation, general system theory, reliability, high resolution graphics, public messages, private messages, fast Fourier transform, personal computing, image processing, etc. 11 references.

Striving for Excellence Sometimes Hinders High Achievers: Performance-Approach Goals Deplete Arithmetical Performance in Students with High Working Memory Capacity

Science.gov (United States)

Crouzevialle, Marie; Smeding, Annique; Butera, Fabrizio

2015-01-01

We tested whether the goal to attain normative superiority over other students, referred to as performance-approach goals, is particularly distractive for high-Working Memory Capacity (WMC) students—that is, those who are used to being high achievers. Indeed, WMC is positively related to high-order cognitive performance and academic success, a record of success that confers benefits on high-WMC as compared to low-WMC students. We tested whether such benefits may turn out to be a burden under performance-approach goal pursuit. Indeed, for high achievers, aiming to rise above others may represent an opportunity to reaffirm their positive status—a stake susceptible to trigger disruptive outcome concerns that interfere with task processing. Results revealed that with performance-approach goals—as compared to goals with no emphasis on social comparison—the higher the students’ WMC, the lower their performance at a complex arithmetic task (Experiment 1). Crucially, this pattern appeared to be driven by uncertainty regarding the chances to outclass others (Experiment 2). Moreover, an accessibility measure suggested the mediational role played by status-related concerns in the observed disruption of performance. We discuss why high-stake situations can paradoxically lead high-achievers to sub-optimally perform when high-order cognitive performance is at play. PMID:26407097

High-performance ceramics. Fabrication, structure, properties

International Nuclear Information System (INIS)

Petzow, G.; Tobolski, J.; Telle, R.

1996-01-01

The program ''Ceramic High-performance Materials'' pursued the objective to understand the chaining of cause and effect in the development of high-performance ceramics. This chain of problems begins with the chemical reactions for the production of powders, comprises the characterization, processing, shaping and compacting of powders, structural optimization, heat treatment, production and finishing, and leads to issues of materials testing and of a design appropriate to the material. The program ''Ceramic High-performance Materials'' has resulted in contributions to the understanding of fundamental interrelationships in terms of materials science, which are summarized in the present volume - broken down into eight special aspects. (orig./RHM)

Future evolution of the Fast TracKer (FTK) processing unit

CERN Document Server

Gentsos, C; The ATLAS collaboration; Giannetti, P; Magalotti, D; Nikolaidis, S

2014-01-01

The Fast Tracker (FTK) processor [1] for the ATLAS experiment has a computing core made of 128 Processing Units that reconstruct tracks in the silicon detector in a ~100 μsec deep pipeline. The track parameter resolution provided by FTK enables the HLT trigger to identify efficiently and reconstruct significant samples of fermionic Higgs decays. Data processing speed is achieved with custom VLSI pattern recognition, linearized track fitting executed inside modern FPGAs, pipelining, and parallel processing. One large FPGA executes full resolution track fitting inside low resolution candidate tracks found by a set of 16 custom Asic devices, called Associative Memories (AM chips) [2]. The FTK dual structure, based on the cooperation of VLSI dedicated AM and programmable FPGAs, is maintained to achieve further technology performance, miniaturization and integration of the current state of the art prototypes. This allows to fully exploit new applications within and outside the High Energy Physics field. We plan t...

Three-dimensional design methodologies for tree-based FPGA architecture

CERN Document Server

Pangracious, Vinod; Mehrez, Habib

2015-01-01

This book focuses on the development of 3D design and implementation methodologies for Tree-based FPGA architecture. It also stresses the needs for new and augmented 3D CAD tools to support designs such as, the design for 3D, to manufacture high performance 3D integrated circuits and reconfigurable FPGA-based systems. This book was written as a text that covers the foundations of 3D integrated system design and FPGA architecture design. It was written for the use in an elective or core course at the graduate level in field of Electrical Engineering, Computer Engineering and Doctoral Research programs. No previous background on 3D integration is required, nevertheless fundamental understanding of 2D CMOS VLSI design is required. It is assumed that reader has taken the core curriculum in Electrical Engineering or Computer Engineering, with courses like CMOS VLSI design, Digital System Design and Microelectronics Circuits being the most important. It is accessible for self-study by both senior students and profe...

High performance data transfer

Science.gov (United States)

Cottrell, R.; Fang, C.; Hanushevsky, A.; Kreuger, W.; Yang, W.

2017-10-01

The exponentially increasing need for high speed data transfer is driven by big data, and cloud computing together with the needs of data intensive science, High Performance Computing (HPC), defense, the oil and gas industry etc. We report on the Zettar ZX software. This has been developed since 2013 to meet these growing needs by providing high performance data transfer and encryption in a scalable, balanced, easy to deploy and use way while minimizing power and space utilization. In collaboration with several commercial vendors, Proofs of Concept (PoC) consisting of clusters have been put together using off-the- shelf components to test the ZX scalability and ability to balance services using multiple cores, and links. The PoCs are based on SSD flash storage that is managed by a parallel file system. Each cluster occupies 4 rack units. Using the PoCs, between clusters we have achieved almost 200Gbps memory to memory over two 100Gbps links, and 70Gbps parallel file to parallel file with encryption over a 5000 mile 100Gbps link.

Strategy Guideline. Partnering for High Performance Homes

Energy Technology Data Exchange (ETDEWEB)

Prahl, Duncan [IBACOS, Inc., Pittsburgh, PA (United States)

2013-01-01

High performance houses require a high degree of coordination and have significant interdependencies between various systems in order to perform properly, meet customer expectations, and minimize risks for the builder. Responsibility for the key performance attributes is shared across the project team and can be well coordinated through advanced partnering strategies. For high performance homes, traditional partnerships need to be matured to the next level and be expanded to all members of the project team including trades, suppliers, manufacturers, HERS raters, designers, architects, and building officials as appropriate. This guide is intended for use by all parties associated in the design and construction of high performance homes. It serves as a starting point and features initial tools and resources for teams to collaborate to continually improve the energy efficiency and durability of new houses.

High performance parallel I/O

CERN Document Server

Prabhat

2014-01-01

Gain Critical Insight into the Parallel I/O EcosystemParallel I/O is an integral component of modern high performance computing (HPC), especially in storing and processing very large datasets to facilitate scientific discovery. Revealing the state of the art in this field, High Performance Parallel I/O draws on insights from leading practitioners, researchers, software architects, developers, and scientists who shed light on the parallel I/O ecosystem.The first part of the book explains how large-scale HPC facilities scope, configure, and operate systems, with an emphasis on choices of I/O har

ADVANCED HIGH PERFORMANCE SOLID WALL BLANKET CONCEPTS

International Nuclear Information System (INIS)

WONG, CPC; MALANG, S; NISHIO, S; RAFFRAY, R; SAGARA, S

2002-01-01

OAK A271 ADVANCED HIGH PERFORMANCE SOLID WALL BLANKET CONCEPTS. First wall and blanket (FW/blanket) design is a crucial element in the performance and acceptance of a fusion power plant. High temperature structural and breeding materials are needed for high thermal performance. A suitable combination of structural design with the selected materials is necessary for D-T fuel sufficiency. Whenever possible, low afterheat, low chemical reactivity and low activation materials are desired to achieve passive safety and minimize the amount of high-level waste. Of course the selected fusion FW/blanket design will have to match the operational scenarios of high performance plasma. The key characteristics of eight advanced high performance FW/blanket concepts are presented in this paper. Design configurations, performance characteristics, unique advantages and issues are summarized. All reviewed designs can satisfy most of the necessary design goals. For further development, in concert with the advancement in plasma control and scrape off layer physics, additional emphasis will be needed in the areas of first wall coating material selection, design of plasma stabilization coils, consideration of reactor startup and transient events. To validate the projected performance of the advanced FW/blanket concepts the critical element is the need for 14 MeV neutron irradiation facilities for the generation of necessary engineering design data and the prediction of FW/blanket components lifetime and availability

DOE research in utilization of high-performance computers

International Nuclear Information System (INIS)

Buzbee, B.L.; Worlton, W.J.; Michael, G.; Rodrigue, G.

1980-12-01

Department of Energy (DOE) and other Government research laboratories depend on high-performance computer systems to accomplish their programatic goals. As the most powerful computer systems become available, they are acquired by these laboratories so that advances can be made in their disciplines. These advances are often the result of added sophistication to numerical models whose execution is made possible by high-performance computer systems. However, high-performance computer systems have become increasingly complex; consequently, it has become increasingly difficult to realize their potential performance. The result is a need for research on issues related to the utilization of these systems. This report gives a brief description of high-performance computers, and then addresses the use of and future needs for high-performance computers within DOE, the growing complexity of applications within DOE, and areas of high-performance computer systems warranting research. 1 figure

Sputtering materials for VLSI and thin film devices

CERN Document Server

Sarkar, Jaydeep

2010-01-01

An important resource for students, engineers and researchers working in the area of thin film deposition using physical vapor deposition (e.g. sputtering) for semiconductor, liquid crystal displays, high density recording media and photovoltaic device (e.g. thin film solar cell) manufacturing. This book also reviews microelectronics industry topics such as history of inventions and technology trends, recent developments in sputtering technologies, manufacturing steps that require sputtering of thin films, the properties of thin films and the role of sputtering target performance on overall p

High-performance mass storage system for workstations

Science.gov (United States)

Chiang, T.; Tang, Y.; Gupta, L.; Cooperman, S.

1993-01-01

Reduced Instruction Set Computer (RISC) workstations and Personnel Computers (PC) are very popular tools for office automation, command and control, scientific analysis, database management, and many other applications. However, when using Input/Output (I/O) intensive applications, the RISC workstations and PC's are often overburdened with the tasks of collecting, staging, storing, and distributing data. Also, by using standard high-performance peripherals and storage devices, the I/O function can still be a common bottleneck process. Therefore, the high-performance mass storage system, developed by Loral AeroSys' Independent Research and Development (IR&D) engineers, can offload a RISC workstation of I/O related functions and provide high-performance I/O functions and external interfaces. The high-performance mass storage system has the capabilities to ingest high-speed real-time data, perform signal or image processing, and stage, archive, and distribute the data. This mass storage system uses a hierarchical storage structure, thus reducing the total data storage cost, while maintaining high-I/O performance. The high-performance mass storage system is a network of low-cost parallel processors and storage devices. The nodes in the network have special I/O functions such as: SCSI controller, Ethernet controller, gateway controller, RS232 controller, IEEE488 controller, and digital/analog converter. The nodes are interconnected through high-speed direct memory access links to form a network. The topology of the network is easily reconfigurable to maximize system throughput for various applications. This high-performance mass storage system takes advantage of a 'busless' architecture for maximum expandability. The mass storage system consists of magnetic disks, a WORM optical disk jukebox, and an 8mm helical scan tape to form a hierarchical storage structure. Commonly used files are kept in the magnetic disk for fast retrieval. The optical disks are used as archive

Ground Glass Pozzolan in Conventional, High, and Ultra-High Performance Concrete

OpenAIRE

Tagnit-Hamou Arezki; Zidol Ablam; Soliman Nancy; Deschamps Joris; Omran Ahmed

2018-01-01

Ground-glass pozzolan (G) obtained by grinding the mixed-waste glass to same fineness of cement can act as a supplementary-cementitious material (SCM), given that it is an amorphous and a pozzolanic material. The G showed promising performances in different concrete types such as conventional concrete (CC), high-performance concrete (HPC), and ultra-high performance concrete (UHPC). The current paper reports on the characteristics and performance of G in these concrete types. The use of G pro...

On the impact of communication complexity in the design of parallel numerical algorithms

Science.gov (United States)

Gannon, D.; Vanrosendale, J.

1984-01-01

This paper describes two models of the cost of data movement in parallel numerical algorithms. One model is a generalization of an approach due to Hockney, and is suitable for shared memory multiprocessors where each processor has vector capabilities. The other model is applicable to highly parallel nonshared memory MIMD systems. In the second model, algorithm performance is characterized in terms of the communication network design. Techniques used in VLSI complexity theory are also brought in, and algorithm independent upper bounds on system performance are derived for several problems that are important to scientific computation.

Indoor Air Quality in High Performance Schools

Science.gov (United States)

High performance schools are facilities that improve the learning environment while saving energy, resources, and money. The key is understanding the lifetime value of high performance schools and effectively managing priorities, time, and budget.

Advanced high performance solid wall blanket concepts

International Nuclear Information System (INIS)

Wong, C.P.C.; Malang, S.; Nishio, S.; Raffray, R.; Sagara, A.

2002-01-01

First wall and blanket (FW/blanket) design is a crucial element in the performance and acceptance of a fusion power plant. High temperature structural and breeding materials are needed for high thermal performance. A suitable combination of structural design with the selected materials is necessary for D-T fuel sufficiency. Whenever possible, low afterheat, low chemical reactivity and low activation materials are desired to achieve passive safety and minimize the amount of high-level waste. Of course the selected fusion FW/blanket design will have to match the operational scenarios of high performance plasma. The key characteristics of eight advanced high performance FW/blanket concepts are presented in this paper. Design configurations, performance characteristics, unique advantages and issues are summarized. All reviewed designs can satisfy most of the necessary design goals. For further development, in concert with the advancement in plasma control and scrape off layer physics, additional emphasis will be needed in the areas of first wall coating material selection, design of plasma stabilization coils, consideration of reactor startup and transient events. To validate the projected performance of the advanced FW/blanket concepts the critical element is the need for 14 MeV neutron irradiation facilities for the generation of necessary engineering design data and the prediction of FW/blanket components lifetime and availability

High-performance OPCPA laser system

International Nuclear Information System (INIS)

Zuegel, J.D.; Bagnoud, V.; Bromage, J.; Begishev, I.A.; Puth, J.

2006-01-01

Optical parametric chirped-pulse amplification (OPCPA) is ideally suited for amplifying ultra-fast laser pulses since it provides broadband gain across a wide range of wavelengths without many of the disadvantages of regenerative amplification. A high-performance OPCPA system has been demonstrated as a prototype for the front end of the OMEGA Extended Performance (EP) Laser System. (authors)

High-performance OPCPA laser system

Energy Technology Data Exchange (ETDEWEB)

Zuegel, J.D.; Bagnoud, V.; Bromage, J.; Begishev, I.A.; Puth, J. [Rochester Univ., Lab. for Laser Energetics, NY (United States)

2006-06-15

Optical parametric chirped-pulse amplification (OPCPA) is ideally suited for amplifying ultra-fast laser pulses since it provides broadband gain across a wide range of wavelengths without many of the disadvantages of regenerative amplification. A high-performance OPCPA system has been demonstrated as a prototype for the front end of the OMEGA Extended Performance (EP) Laser System. (authors)

High performance in software development

CERN Multimedia

CERN. Geneva; Haapio, Petri; Liukkonen, Juha-Matti

2015-01-01

What are the ingredients of high-performing software? Software development, especially for large high-performance systems, is one the most complex tasks mankind has ever tried. Technological change leads to huge opportunities but challenges our old ways of working. Processing large data sets, possibly in real time or with other tight computational constraints, requires an efficient solution architecture. Efficiency requirements span from the distributed storage and large-scale organization of computation and data onto the lowest level of processor and data bus behavior. Integrating performance behavior over these levels is especially important when the computation is resource-bounded, as it is in numerics: physical simulation, machine learning, estimation of statistical models, etc. For example, memory locality and utilization of vector processing are essential for harnessing the computing power of modern processor architectures due to the deep memory hierarchies of modern general-purpose computers. As a r...

High Performance Computing in Science and Engineering '16 : Transactions of the High Performance Computing Center, Stuttgart (HLRS) 2016

CERN Document Server

Kröner, Dietmar; Resch, Michael

2016-01-01

This book presents the state-of-the-art in supercomputer simulation. It includes the latest findings from leading researchers using systems from the High Performance Computing Center Stuttgart (HLRS) in 2016. The reports cover all fields of computational science and engineering ranging from CFD to computational physics and from chemistry to computer science with a special emphasis on industrially relevant applications. Presenting findings of one of Europe’s leading systems, this volume covers a wide variety of applications that deliver a high level of sustained performance. The book covers the main methods in high-performance computing. Its outstanding results in achieving the best performance for production codes are of particular interest for both scientists and engineers. The book comes with a wealth of color illustrations and tables of results.

High-performance computing — an overview

Science.gov (United States)

Marksteiner, Peter

1996-08-01

An overview of high-performance computing (HPC) is given. Different types of computer architectures used in HPC are discussed: vector supercomputers, high-performance RISC processors, various parallel computers like symmetric multiprocessors, workstation clusters, massively parallel processors. Software tools and programming techniques used in HPC are reviewed: vectorizing compilers, optimization and vector tuning, optimization for RISC processors; parallel programming techniques like shared-memory parallelism, message passing and data parallelism; and numerical libraries.

Team Development for High Performance Management.

Science.gov (United States)

Schermerhorn, John R., Jr.

1986-01-01

The author examines a team development approach to management that creates shared commitments to performance improvement by focusing the attention of managers on individual workers and their task accomplishments. It uses the "high-performance equation" to help managers confront shared beliefs and concerns about performance and develop realistic…

System Theoretic Models for High Density VLSI Structures

Science.gov (United States)

1989-01-01

vector is also called a stable We first present a simple example to help visualize how vector of the AMN. The set of all stable vectors is denoted these...New York: Springer- Verlag. 1978. 1980 [34] B. De Finetti. "Funtzione catatteristica di un fenomeno aleato- , [16] W A Little. "The existence of

High Performance Walls in Hot-Dry Climates

Energy Technology Data Exchange (ETDEWEB)

Hoeschele, Marc [Alliance for Residential Building Innovation (ARBI), Davis, CA (United States); Springer, David [Alliance for Residential Building Innovation (ARBI), Davis, CA (United States); Dakin, Bill [Alliance for Residential Building Innovation (ARBI), Davis, CA (United States); German, Alea [Alliance for Residential Building Innovation (ARBI), Davis, CA (United States)

2015-01-01

High performance walls represent a high priority measure for moving the next generation of new homes to the Zero Net Energy performance level. The primary goal in improving wall thermal performance revolves around increasing the wall framing from 2x4 to 2x6, adding more cavity and exterior rigid insulation, achieving insulation installation criteria meeting ENERGY STAR's thermal bypass checklist. To support this activity, in 2013 the Pacific Gas & Electric Company initiated a project with Davis Energy Group (lead for the Building America team, Alliance for Residential Building Innovation) to solicit builder involvement in California to participate in field demonstrations of high performance wall systems. Builders were given incentives and design support in exchange for providing site access for construction observation, cost information, and builder survey feedback. Information from the project was designed to feed into the 2016 Title 24 process, but also to serve as an initial mechanism to engage builders in more high performance construction strategies. This Building America project utilized information collected in the California project.

Flexible nanoscale high-performance FinFETs

KAUST Repository

Sevilla, Galo T.

2014-10-28

With the emergence of the Internet of Things (IoT), flexible high-performance nanoscale electronics are more desired. At the moment, FinFET is the most advanced transistor architecture used in the state-of-the-art microprocessors. Therefore, we show a soft-etch based substrate thinning process to transform silicon-on-insulator (SOI) based nanoscale FinFET into flexible FinFET and then conduct comprehensive electrical characterization under various bending conditions to understand its electrical performance. Our study shows that back-etch based substrate thinning process is gentler than traditional abrasive back-grinding process; it can attain ultraflexibility and the electrical characteristics of the flexible nanoscale FinFET show no performance degradation compared to its rigid bulk counterpart indicating its readiness to be used for flexible high-performance electronics.

The Role of Performance Management in Creating and Maintaining a High-Performance Organization

Directory of Open Access Journals (Sweden)

André A. de Waal

2015-04-01

Full Text Available There is still a good deal of confusion in the literature about how the use of a performance management system affects overall organizational performance. Some researchers find that performance management enhances both the financial and non-financial results of an organization, while others do not find any positive effects or, at most, ambiguous effects. An important step toward getting more clarity in this relationship is to investigate the role performance management plays in creating and maintaining a high-performance organization (HPO. The purpose of this study is to integrate performance management analysis (PMA and high-performance organization (HPO. A questionnaire combining questions on PMA dimensions and HPO factors was administered to two European-based multinational firms. Based on 468 valid questionnaires, a correlation analysis was performed on the PMA dimensions and the HPO factors in order to test the impact of performance management on the factors of high organizational performance. The results show strong and significant correlations between all the PMA dimensions and all the HPO factors, indicating that a performance management system that fosters performance-driven behavior in the organization is of critical importance to strengthen overall financial and non-financial performance.

30 nm T-gate enhancement-mode InAlN/AlN/GaN HEMT on SiC substrates for future high power RF applications

Science.gov (United States)

Murugapandiyan, P.; Ravimaran, S.; William, J.

2017-08-01

The DC and RF performance of 30 nm gate length enhancement mode (E-mode) InAlN/AlN/GaN high electron mobility transistor (HEMT) on SiC substrate with heavily doped source and drain region have been investigated using the Synopsys TCAD tool. The proposed device has the features of a recessed T-gate structure, InGaN back barrier and Al2O3 passivated device surface. The proposed HEMT exhibits a maximum drain current density of 2.1 A/mm, transconductance {g}{{m}} of 1050 mS/mm, current gain cut-off frequency {f}{{t}} of 350 GHz and power gain cut-off frequency {f}\\max of 340 GHz. At room temperature the measured carrier mobility (μ), sheet charge carrier density ({n}{{s}}) and breakdown voltage are 1580 cm2/(V \\cdot s), 1.9× {10}13 {{cm}}-2, and 10.7 V respectively. The superlatives of the proposed HEMTs are bewitching competitor or future sub-millimeter wave high power RF VLSI circuit applications.

Development of new high-performance stainless steels

International Nuclear Information System (INIS)

Park, Yong Soo

2002-01-01

This paper focused on high-performance stainless steels and their development status. Effect of nitrogen addition on super-stainless steel was discussed. Research activities at Yonsei University, on austenitic and martensitic high-performance stainless, steels, and the next-generation duplex stainless steels were introduced

vSphere high performance cookbook

CERN Document Server

Sarkar, Prasenjit

2013-01-01

vSphere High Performance Cookbook is written in a practical, helpful style with numerous recipes focusing on answering and providing solutions to common, and not-so common, performance issues and problems.The book is primarily written for technical professionals with system administration skills and some VMware experience who wish to learn about advanced optimization and the configuration features and functions for vSphere 5.1.

High Burnup Fuel Performance and Safety Research

Energy Technology Data Exchange (ETDEWEB)

Bang, Je Keun; Lee, Chan Bok; Kim, Dae Ho (and others)

2007-03-15

The worldwide trend of nuclear fuel development is to develop a high burnup and high performance nuclear fuel with high economies and safety. Because the fuel performance evaluation code, INFRA, has a patent, and the superiority for prediction of fuel performance was proven through the IAEA CRP FUMEX-II program, the INFRA code can be utilized with commercial purpose in the industry. The INFRA code was provided and utilized usefully in the universities and relevant institutes domesticallly and it has been used as a reference code in the industry for the development of the intrinsic fuel rod design code.

Danish High Performance Concretes

DEFF Research Database (Denmark)

Nielsen, M. P.; Christoffersen, J.; Frederiksen, J.

1994-01-01

In this paper the main results obtained in the research program High Performance Concretes in the 90's are presented. This program was financed by the Danish government and was carried out in cooperation between The Technical University of Denmark, several private companies, and Aalborg University...... concretes, workability, ductility, and confinement problems....

Promising high monetary rewards for future task performance increases intermediate task performance.

Directory of Open Access Journals (Sweden)

Claire M Zedelius

Full Text Available In everyday life contexts and work settings, monetary rewards are often contingent on future performance. Based on research showing that the anticipation of rewards causes improved task performance through enhanced task preparation, the present study tested the hypothesis that the promise of monetary rewards for future performance would not only increase future performance, but also performance on an unrewarded intermediate task. Participants performed an auditory Simon task in which they responded to two consecutive tones. While participants could earn high vs. low monetary rewards for fast responses to every second tone, their responses to the first tone were not rewarded. Moreover, we compared performance under conditions in which reward information could prompt strategic performance adjustments (i.e., when reward information was presented for a relatively long duration to conditions preventing strategic performance adjustments (i.e., when reward information was presented very briefly. Results showed that high (vs. low rewards sped up both rewarded and intermediate, unrewarded responses, and the effect was independent of the duration of reward presentation. Moreover, long presentation led to a speed-accuracy trade-off for both rewarded and unrewarded tones, whereas short presentation sped up responses to rewarded and unrewarded tones without this trade-off. These results suggest that high rewards for future performance boost intermediate performance due to enhanced task preparation, and they do so regardless whether people respond to rewards in a strategic or non-strategic manner.

Promising high monetary rewards for future task performance increases intermediate task performance.

Science.gov (United States)

Zedelius, Claire M; Veling, Harm; Bijleveld, Erik; Aarts, Henk

2012-01-01

In everyday life contexts and work settings, monetary rewards are often contingent on future performance. Based on research showing that the anticipation of rewards causes improved task performance through enhanced task preparation, the present study tested the hypothesis that the promise of monetary rewards for future performance would not only increase future performance, but also performance on an unrewarded intermediate task. Participants performed an auditory Simon task in which they responded to two consecutive tones. While participants could earn high vs. low monetary rewards for fast responses to every second tone, their responses to the first tone were not rewarded. Moreover, we compared performance under conditions in which reward information could prompt strategic performance adjustments (i.e., when reward information was presented for a relatively long duration) to conditions preventing strategic performance adjustments (i.e., when reward information was presented very briefly). Results showed that high (vs. low) rewards sped up both rewarded and intermediate, unrewarded responses, and the effect was independent of the duration of reward presentation. Moreover, long presentation led to a speed-accuracy trade-off for both rewarded and unrewarded tones, whereas short presentation sped up responses to rewarded and unrewarded tones without this trade-off. These results suggest that high rewards for future performance boost intermediate performance due to enhanced task preparation, and they do so regardless whether people respond to rewards in a strategic or non-strategic manner.

Imbalance aware lithography hotspot detection: a deep learning approach

Science.gov (United States)

Yang, Haoyu; Luo, Luyang; Su, Jing; Lin, Chenxi; Yu, Bei

2017-07-01

With the advancement of very large scale integrated circuits (VLSI) technology nodes, lithographic hotspots become a serious problem that affects manufacture yield. Lithography hotspot detection at the post-OPC stage is imperative to check potential circuit failures when transferring designed patterns onto silicon wafers. Although conventional lithography hotspot detection methods, such as machine learning, have gained satisfactory performance, with the extreme scaling of transistor feature size and layout patterns growing in complexity, conventional methodologies may suffer from performance degradation. For example, manual or ad hoc feature extraction in a machine learning framework may lose important information when predicting potential errors in ultra-large-scale integrated circuit masks. We present a deep convolutional neural network (CNN) that targets representative feature learning in lithography hotspot detection. We carefully analyze the impact and effectiveness of different CNN hyperparameters, through which a hotspot-detection-oriented neural network model is established. Because hotspot patterns are always in the minority in VLSI mask design, the training dataset is highly imbalanced. In this situation, a neural network is no longer reliable, because a trained model with high classification accuracy may still suffer from a high number of false negative results (missing hotspots), which is fatal in hotspot detection problems. To address the imbalance problem, we further apply hotspot upsampling and random-mirror flipping before training the network. Experimental results show that our proposed neural network model achieves comparable or better performance on the ICCAD 2012 contest benchmark compared to state-of-the-art hotspot detectors based on deep or representative machine leaning.

Comparison of ultra high performance supercritical fluid chromatography, ultra high performance liquid chromatography, and gas chromatography for the separation of synthetic cathinones.

Science.gov (United States)

Carnes, Stephanie; O'Brien, Stacey; Szewczak, Angelica; Tremeau-Cayel, Lauriane; Rowe, Walter F; McCord, Bruce; Lurie, Ira S

2017-09-01

A comparison of ultra high performance supercritical fluid chromatography, ultra high performance liquid chromatography, and gas chromatography for the separation of synthetic cathinones has been conducted. Nine different mixtures of bath salts were analyzed in this study. The three different chromatographic techniques were examined using a general set of controlled synthetic cathinones as well as a variety of other synthetic cathinones that exist as positional isomers. Overall 35 different synthetic cathinones were analyzed. A variety of column types and chromatographic modes were examined for developing each separation. For the ultra high performance supercritical fluid chromatography separations, analyses were performed using a series of Torus and Trefoil columns with either ammonium formate or ammonium hydroxide as additives, and methanol, ethanol or isopropanol organic solvents as modifiers. Ultra high performance liquid chromatographic separations were performed in both reversed phase and hydrophilic interaction chromatographic modes using SPP C18 and SPP HILIC columns. Gas chromatography separations were performed using an Elite-5MS capillary column. The orthogonality of ultra high performance supercritical fluid chromatography, ultra high performance liquid chromatography, and gas chromatography was examined using principal component analysis. For the best overall separation of synthetic cathinones, the use of ultra high performance supercritical fluid chromatography in combination with gas chromatography is recommended. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High Performance Electronics on Flexible Silicon

KAUST Repository

Sevilla, Galo T.

2016-09-01

Over the last few years, flexible electronic systems have gained increased attention from researchers around the world because of their potential to create new applications such as flexible displays, flexible energy harvesters, artificial skin, and health monitoring systems that cannot be integrated with conventional wafer based complementary metal oxide semiconductor processes. Most of the current efforts to create flexible high performance devices are based on the use of organic semiconductors. However, inherent material\\'s limitations make them unsuitable for big data processing and high speed communications. The objective of my doctoral dissertation is to develop integration processes that allow the transformation of rigid high performance electronics into flexible ones while maintaining their performance and cost. In this work, two different techniques to transform inorganic complementary metal-oxide-semiconductor electronics into flexible ones have been developed using industry compatible processes. Furthermore, these techniques were used to realize flexible discrete devices and circuits which include metal-oxide-semiconductor field-effect-transistors, the first demonstration of flexible Fin-field-effect-transistors, and metal-oxide-semiconductors-based circuits. Finally, this thesis presents a new technique to package, integrate, and interconnect flexible high performance electronics using low cost additive manufacturing techniques such as 3D printing and inkjet printing. This thesis contains in depth studies on electrical, mechanical, and thermal properties of the fabricated devices.

High Performance Computing in Science and Engineering '02 : Transactions of the High Performance Computing Center

CERN Document Server

Jäger, Willi

2003-01-01

This book presents the state-of-the-art in modeling and simulation on supercomputers. Leading German research groups present their results achieved on high-end systems of the High Performance Computing Center Stuttgart (HLRS) for the year 2002. Reports cover all fields of supercomputing simulation ranging from computational fluid dynamics to computer science. Special emphasis is given to industrially relevant applications. Moreover, by presenting results for both vector sytems and micro-processor based systems the book allows to compare performance levels and usability of a variety of supercomputer architectures. It therefore becomes an indispensable guidebook to assess the impact of the Japanese Earth Simulator project on supercomputing in the years to come.

Critical Factors Explaining the Leadership Performance of High-Performing Principals

Science.gov (United States)

Hutton, Disraeli M.

2018-01-01

The study explored critical factors that explain leadership performance of high-performing principals and examined the relationship between these factors based on the ratings of school constituents in the public school system. The principal component analysis with the use of Varimax Rotation revealed that four components explain 51.1% of the…

High Performance Walls in Hot-Dry Climates

Energy Technology Data Exchange (ETDEWEB)

Hoeschele, Marc [National Renewable Energy Lab. (NREL), Golden, CO (United States); Springer, David [National Renewable Energy Lab. (NREL), Golden, CO (United States); Dakin, Bill [National Renewable Energy Lab. (NREL), Golden, CO (United States); German, Alea [National Renewable Energy Lab. (NREL), Golden, CO (United States)

2015-01-01

High performance walls represent a high priority measure for moving the next generation of new homes to the Zero Net Energy performance level. The primary goal in improving wall thermal performance revolves around increasing the wall framing from 2x4 to 2x6, adding more cavity and exterior rigid insulation, achieving insulation installation criteria meeting ENERGY STAR's thermal bypass checklist, and reducing the amount of wood penetrating the wall cavity.

High-performance liquid chromatography of oligoguanylates at high pH

Science.gov (United States)

Stribling, R.; Deamer, D. (Principal Investigator)

1991-01-01

Because of the stable self-structures formed by oligomers of guanosine, standard high-performance liquid chromatography techniques for oligonucleotide fractionation are not applicable. Previously, oligoguanylate separations have been carried out at pH 12 using RPC-5 as the packing material. While RPC-5 provides excellent separations, there are several limitations, including the lack of a commercially available source. This report describes a new anion-exchange high-performance liquid chromatography method using HEMA-IEC BIO Q, which successfully separates different forms of the guanosine monomer as well as longer oligoguanylates. The reproducibility and stability at high pH suggests a versatile role for this material.

Development of high-performance concrete having high resistance to chloride penetration

International Nuclear Information System (INIS)

Oh, Byung Hwan; Cha, Soo Won; Jang, Bong Seok; Jang, Seung Yup

2002-01-01

The resistance to chloride penetration is one of the simplest measures to determine the durability of concrete, e.g. resistance to freezing and thawing, corrosion of steel in concrete and other chemical attacks. Thus, high-performance concrete may be defined as the concrete having high resistance to chloride penetration as well as high strength. The purpose of this paper is to investigate the resistance to chloride penetration of different types of concrete and to develop high-performance concrete that has very high resistance to chloride penetration, and thus, can guarantee high durability. A large number of concrete specimens have been tested by the rapid chloride permeability test method as designated in AASHTO T 277 and ASTM C 1202. The major test variables include water-to-binder ratios, type of cement, type and amount of mineral admixtures (silica fume, fly ash and blast-furnace slag), maximum size of aggregates and air-entrainment. Test results show that concrete containing optimal amount of silica fume shows very high resistance to chloride penetration, and high-performance concrete developed in this study can be efficiently employed to enhance the durability of concrete structures in severe environments such as nuclear power plants, water-retaining structures and other offshore structures

Identifying High Performance ERP Projects

OpenAIRE

Stensrud, Erik; Myrtveit, Ingunn

2002-01-01

Learning from high performance projects is crucial for software process improvement. Therefore, we need to identify outstanding projects that may serve as role models. It is common to measure productivity as an indicator of performance. It is vital that productivity measurements deal correctly with variable returns to scale and multivariate data. Software projects generally exhibit variable returns to scale, and the output from ERP projects is multivariate. We propose to use Data Envelopment ...

Complexity optimization and high-throughput low-latency hardware implementation of a multi-electrode spike-sorting algorithm.

Science.gov (United States)

Dragas, Jelena; Jackel, David; Hierlemann, Andreas; Franke, Felix

2015-03-01

Reliable real-time low-latency spike sorting with large data throughput is essential for studies of neural network dynamics and for brain-machine interfaces (BMIs), in which the stimulation of neural networks is based on the networks' most recent activity. However, the majority of existing multi-electrode spike-sorting algorithms are unsuited for processing high quantities of simultaneously recorded data. Recording from large neuronal networks using large high-density electrode sets (thousands of electrodes) imposes high demands on the data-processing hardware regarding computational complexity and data transmission bandwidth; this, in turn, entails demanding requirements in terms of chip area, memory resources and processing latency. This paper presents computational complexity optimization techniques, which facilitate the use of spike-sorting algorithms in large multi-electrode-based recording systems. The techniques are then applied to a previously published algorithm, on its own, unsuited for large electrode set recordings. Further, a real-time low-latency high-performance VLSI hardware architecture of the modified algorithm is presented, featuring a folded structure capable of processing the activity of hundreds of neurons simultaneously. The hardware is reconfigurable “on-the-fly” and adaptable to the nonstationarities of neuronal recordings. By transmitting exclusively spike time stamps and/or spike waveforms, its real-time processing offers the possibility of data bandwidth and data storage reduction.

Impact of line edge roughness on the performance of 14-nm FinFET: Device-circuit Co-design

Science.gov (United States)

Rathore, Rituraj Singh; Rana, Ashwani K.

2018-01-01

With the evolution of sub-20 nm FinFET technology, line edge roughness (LER) has been identified as a critical problem and may result in critical device parameter variation and performance limitation in the future VLSI circuit application. In the present work, an analytical model of fin-LER has been presented, which shows the impact of correlated and uncorrelated LER on FinFET structure. Further, the influence of correlated and uncorrelated fin- LER on all electrical performance parameters is thoroughly investigated using the three-dimensional (3-D) Technology Computer Aided Design (TCAD) simulations for 14-nm technology node. Moreover, the impact of all possible fin shapes on threshold voltage (VTH), drain induced barrier lowering (DIBL), on-current (ION), and off-current (IOFF) has been compared with the well calibrated rectangular FinFET structure. In addition, the influence of all possible fin geometries on the read stability of six-transistor (6-T) Static-Random-Access-Memory (SRAM) has been investigated. The study reveals that fin-LER plays a vital role as it directly governs the electrostatics of the FinFET structure. This has been found that there is a high degree of fluctuations in all performance parameters for uncorrelated fin-LER type FinFETs as compared to correlated fin-LER with respect to rectangular FinFET structure. This paper gives physical insight of FinFET design, especially in sub-20 nm technology nodes by concluding that the impact of LER on electrical parameters are minimum for correlated LER.

Integrated plasma control for high performance tokamaks

International Nuclear Information System (INIS)

Humphreys, D.A.; Deranian, R.D.; Ferron, J.R.; Johnson, R.D.; LaHaye, R.J.; Leuer, J.A.; Penaflor, B.G.; Walker, M.L.; Welander, A.S.; Jayakumar, R.J.; Makowski, M.A.; Khayrutdinov, R.R.

2005-01-01

Sustaining high performance in a tokamak requires controlling many equilibrium shape and profile characteristics simultaneously with high accuracy and reliability, while suppressing a variety of MHD instabilities. Integrated plasma control, the process of designing high-performance tokamak controllers based on validated system response models and confirming their performance in detailed simulations, provides a systematic method for achieving and ensuring good control performance. For present-day devices, this approach can greatly reduce the need for machine time traditionally dedicated to control optimization, and can allow determination of high-reliability controllers prior to ever producing the target equilibrium experimentally. A full set of tools needed for this approach has recently been completed and applied to present-day devices including DIII-D, NSTX and MAST. This approach has proven essential in the design of several next-generation devices including KSTAR, EAST, JT-60SC, and ITER. We describe the method, results of design and simulation tool development, and recent research producing novel approaches to equilibrium and MHD control in DIII-D. (author)

Highlighting High Performance: Blackstone Valley Regional Vocational Technical High School; Upton, Massachusetts

Energy Technology Data Exchange (ETDEWEB)

2006-10-01

This brochure describes the key high-performance building features of the Blackstone Valley High School. The brochure was paid for by the Massachusetts Technology Collaborative as part of their Green Schools Initiative. High-performance features described are daylighting and energy-efficient lighting, indoor air quality, solar energy, building envelope, heating and cooling systems, and water conservation. Energy cost savings are also discussed.

Ground Glass Pozzolan in Conventional, High, and Ultra-High Performance Concrete

Directory of Open Access Journals (Sweden)

Tagnit-Hamou Arezki

2018-01-01

Full Text Available Ground-glass pozzolan (G obtained by grinding the mixed-waste glass to same fineness of cement can act as a supplementary-cementitious material (SCM, given that it is an amorphous and a pozzolanic material. The G showed promising performances in different concrete types such as conventional concrete (CC, high-performance concrete (HPC, and ultra-high performance concrete (UHPC. The current paper reports on the characteristics and performance of G in these concrete types. The use of G provides several advantages (technological, economical, and environmental. It reduces the production cost of concrete and decrease the carbon footprint of a traditional concrete structures. The rheology of fresh concrete can be improved due to the replacement of cement by non-absorptive glass particles. Strength and rigidity improvements in the concrete containing G are due to the fact that glass particles act as inclusions having a very high strength and elastic modulus that have a strengthening effect on the overall hardened matrix.

Mood states and motor performance: a study with high performance voleybol athletes

Directory of Open Access Journals (Sweden)

Lenamar Fiorese Vieira

2008-07-01

Full Text Available http://dx.doi.org/10.5007/1980-0037.2008v10n1p62 The objective of this research was to investigate the relationship between the sporting performance and mood states of high performance volleyball athletes. Twenty-three adult athletes of both sexes were assessed. The measurement instrument adopted was the POMS questionnaire. Data collection was carried out individually during the state championships. Dada were analyzed using descriptive statistics; the Friedman test for analysis of variance and the Mann-Whitney test for differences between means. The results demonstrated that both teams exhibited the mood state profi le corresponding to the “iceberg” profile. In the male team, vigor remained constant throughout all phases of the competition, while in the female team this element was unstable. The male team’s fatigue began low, during the training phase, with rates that rose as the competition progressed, with statistically significant differences between the fi rst and last matches the team played. In the female team, the confusion factor, which was at a high level during training, reduced progressively throughout the competition, with a difference that was signifi cant to p ≤ 0.05. With relation to performance and mood profi le, the female team exhibited statistically significant differences between the mean vigor and fatigue factors of high and low performance athletes. It is therefore concluded that the mood state profi le is a factor that impacts on the motor performance of these high performance teams.

Performances of photodiode detectors for top and bottom counting detectors of ISS-CREAM experiment

International Nuclear Information System (INIS)

Hyun, H.J.; Anderson, T.; Angelaszek, D.; Baek, S.J.; Copley, M.; Coutu, S.; Han, J.H.; Huh, H.G.; Hwang, Y.S.; Im, S.; Jeon, H.B.; Kah, D.H.; Kang, K.H.; Kim, H.J.; Kim, K.C.; Kwashnak, K.; Lee, J.; Lee, M.H.; Link, J.T.; Lutz, L.

2015-01-01

The Cosmic Ray Energetics and Mass (CREAM) experiment at the International Space Station (ISS) aims to elucidate the source and acceleration mechanisms of high-energy cosmic rays by measuring the energy spectra from protons to iron. The instrument is planned for launch in 2015 at the ISS, and it comprises a silicon charge detector, a carbon target, top and bottom counting detectors, a calorimeter, and a boronated scintillator detector. The top and bottom counting detectors are developed for separating the electrons from the protons, and each of them comprises a plastic scintillator and a 20×20 silicon photodiode array. Each photodiode is 2.3 cm×2.3 cm in size and exhibits good electrical characteristics. The leakage current is measured to be less than 20 nA/cm 2 at an operating voltage. The signal-to-noise ratio is measured to be better than 70 using commercial electronics, and the radiation hardness is tested using a proton beam. A signal from the photodiode is amplified by VLSI (very-large-scale integration) charge amp/hold circuits, the VA-TA viking chip. Environmental tests are performed using whole assembled photodiode detectors of a flight version. Herein, we present the characteristics of the developed photodiode along with the results of the environmental tests

Performances of photodiode detectors for top and bottom counting detectors of ISS-CREAM experiment

Energy Technology Data Exchange (ETDEWEB)

Hyun, H.J. [Kyungpook National University, Daegu 702-701 (Korea, Republic of); Anderson, T. [Pennsylvania State University, University Park, PA 16802 (United States); Angelaszek, D. [University of Maryland, College Park, MD 20740 (United States); Baek, S.J. [Sungkyunkwan University, Suwon 440-746 (Korea, Republic of); Copley, M. [University of Maryland, College Park, MD 20740 (United States); Coutu, S. [Pennsylvania State University, University Park, PA 16802 (United States); Han, J.H.; Huh, H.G. [University of Maryland, College Park, MD 20740 (United States); Hwang, Y.S. [Kyungpook National University, Daegu 702-701 (Korea, Republic of); Im, S. [Pennsylvania State University, University Park, PA 16802 (United States); Jeon, H.B.; Kah, D.H.; Kang, K.H.; Kim, H.J. [Kyungpook National University, Daegu 702-701 (Korea, Republic of); Kim, K.C.; Kwashnak, K. [University of Maryland, College Park, MD 20740 (United States); Lee, J. [Sungkyunkwan University, Suwon 440-746 (Korea, Republic of); Lee, M.H. [University of Maryland, College Park, MD 20740 (United States); Link, J.T. [NASA GSFC, Greenbelt, MD 20771 (United States); CRESST(USRA), Columbia, MD 21044 (United States); Lutz, L. [University of Maryland, College Park, MD 20740 (United States); and others

2015-07-01

The Cosmic Ray Energetics and Mass (CREAM) experiment at the International Space Station (ISS) aims to elucidate the source and acceleration mechanisms of high-energy cosmic rays by measuring the energy spectra from protons to iron. The instrument is planned for launch in 2015 at the ISS, and it comprises a silicon charge detector, a carbon target, top and bottom counting detectors, a calorimeter, and a boronated scintillator detector. The top and bottom counting detectors are developed for separating the electrons from the protons, and each of them comprises a plastic scintillator and a 20×20 silicon photodiode array. Each photodiode is 2.3 cm×2.3 cm in size and exhibits good electrical characteristics. The leakage current is measured to be less than 20 nA/cm{sup 2} at an operating voltage. The signal-to-noise ratio is measured to be better than 70 using commercial electronics, and the radiation hardness is tested using a proton beam. A signal from the photodiode is amplified by VLSI (very-large-scale integration) charge amp/hold circuits, the VA-TA viking chip. Environmental tests are performed using whole assembled photodiode detectors of a flight version. Herein, we present the characteristics of the developed photodiode along with the results of the environmental tests.

High performance leadership in unusually challenging educational circumstances

Directory of Open Access Journals (Sweden)

Andy Hargreaves

2015-04-01

Full Text Available This paper draws on findings from the results of a study of leadership in high performing organizations in three sectors. Organizations were sampled and included on the basis of high performance in relation to no performance, past performance, performance among similar peers and performance in the face of limited resources or challenging circumstances. The paper concentrates on leadership in four schools that met the sample criteria.  It draws connections to explanations of the high performance ofEstoniaon the OECD PISA tests of educational achievement. The article argues that leadership in these four schools that performed above expectations comprised more than a set of competencies. Instead, leadership took the form of a narrative or quest that pursued an inspiring dream with relentless determination; took improvement pathways that were more innovative than comparable peers; built collaboration and community including with competing schools; and connected short-term success to long-term sustainability.

High-performance computing in seismology

Energy Technology Data Exchange (ETDEWEB)

NONE

1996-09-01

The scientific, technical, and economic importance of the issues discussed here presents a clear agenda for future research in computational seismology. In this way these problems will drive advances in high-performance computing in the field of seismology. There is a broad community that will benefit from this work, including the petroleum industry, research geophysicists, engineers concerned with seismic hazard mitigation, and governments charged with enforcing a comprehensive test ban treaty. These advances may also lead to new applications for seismological research. The recent application of high-resolution seismic imaging of the shallow subsurface for the environmental remediation industry is an example of this activity. This report makes the following recommendations: (1) focused efforts to develop validated documented software for seismological computations should be supported, with special emphasis on scalable algorithms for parallel processors; (2) the education of seismologists in high-performance computing technologies and methodologies should be improved; (3) collaborations between seismologists and computational scientists and engineers should be increased; (4) the infrastructure for archiving, disseminating, and processing large volumes of seismological data should be improved.

High performance flexible CMOS SOI FinFETs

KAUST Repository

Fahad, Hossain M.

2014-06-01

We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

Evaluation framework for K-best sphere decoders

KAUST Repository

Shen, Chungan; Eltawil, Ahmed M.; Salama, Khaled N.

2010-01-01

or receive antennas. Tree-searching type decoder structures such as Sphere decoder and K-best decoder present an interesting trade-off between complexity and performance. Many algorithmic developments and VLSI implementations have been reported in literature

FPGA Implementation of one-dimensional and two-dimensional cellular automata

International Nuclear Information System (INIS)

D'Antone, I.

1999-01-01

This report describes the hardware implementation of one-dimensional and two-dimensional cellular automata (CAs). After a general introduction to the cellular automata, we consider a one-dimensional CA used to implement pseudo-random techniques in built-in self test for VLSI. Due to the increase in digital ASIC complexity, testing is becoming one of the major costs in the VLSI production. The high electronics complexity, used in particle physics experiments, demands higher reliability than in the past time. General criterions are given to evaluate the feasibility of the circuit used for testing and some quantitative parameters are underlined to optimize the architecture of the cellular automaton. Furthermore, we propose a two-dimensional CA that performs a peak finding algorithm in a matrix of cells mapping a sub-region of a calorimeter. As in a two-dimensional filtering process, the peaks of the energy clusters are found in one evolution step. This CA belongs to Wolfram class II cellular automata. Some quantitative parameters are given to optimize the architecture of the cellular automaton implemented in a commercial field programmable gate array (FPGA)

Architecting Web Sites for High Performance

Directory of Open Access Journals (Sweden)

Arun Iyengar

2002-01-01

Full Text Available Web site applications are some of the most challenging high-performance applications currently being developed and deployed. The challenges emerge from the specific combination of high variability in workload characteristics and of high performance demands regarding the service level, scalability, availability, and costs. In recent years, a large body of research has addressed the Web site application domain, and a host of innovative software and hardware solutions have been proposed and deployed. This paper is an overview of recent solutions concerning the architectures and the software infrastructures used in building Web site applications. The presentation emphasizes three of the main functions in a complex Web site: the processing of client requests, the control of service levels, and the interaction with remote network caches.

The effects of advanced digital signal processing concepts on VLSIC/VHSIC design

Science.gov (United States)

Jankowski, C.

Implementations of sophisticated mathematical techniques in advanced digital signal processors can significantly improve performance. Future VLSI and VHSI circuit designs must include the practical realization of these algorithms. A structured design approach is described and illustrated with examples from a RNS FIR filter processor development project. The CAE hardware and software required to support tasks of this complexity are also discussed. An EWS is recommended for controlling essential functions such as logic optimization, simulation and verification. The total IC design system is illustrated with the implementation of a new high performance algorithm for computing complex magnitude.

The Software Reliability of Large Scale Integration Circuit and Very Large Scale Integration Circuit

OpenAIRE

Artem Ganiyev; Jan Vitasek

2010-01-01

This article describes evaluation method of faultless function of large scale integration circuits (LSI) and very large scale integration circuits (VLSI). In the article there is a comparative analysis of factors which determine faultless of integrated circuits, analysis of already existing methods and model of faultless function evaluation of LSI and VLSI. The main part describes a proposed algorithm and program for analysis of fault rate in LSI and VLSI circuits.

Development of a high performance liquid chromatography method ...

African Journals Online (AJOL)

Development of a high performance liquid chromatography method for simultaneous ... Purpose: To develop and validate a new low-cost high performance liquid chromatography (HPLC) method for ..... Several papers have reported the use of ...

Toward a theory of high performance.

Science.gov (United States)

Kirby, Julia

2005-01-01

What does it mean to be a high-performance company? The process of measuring relative performance across industries and eras, declaring top performers, and finding the common drivers of their success is such a difficult one that it might seem a fool's errand to attempt. In fact, no one did for the first thousand or so years of business history. The question didn't even occur to many scholars until Tom Peters and Bob Waterman released In Search of Excellence in 1982. Twenty-three years later, we've witnessed several more attempts--and, just maybe, we're getting closer to answers. In this reported piece, HBR senior editor Julia Kirby explores why it's so difficult to study high performance and how various research efforts--including those from John Kotter and Jim Heskett; Jim Collins and Jerry Porras; Bill Joyce, Nitin Nohria, and Bruce Roberson; and several others outlined in a summary chart-have attacked the problem. The challenge starts with deciding which companies to study closely. Are the stars the ones with the highest market caps, the ones with the greatest sales growth, or simply the ones that remain standing at the end of the game? (And when's the end of the game?) Each major study differs in how it defines success, which companies it therefore declares to be worthy of emulation, and the patterns of activity and attitude it finds in common among them. Yet, Kirby concludes, as each study's method incrementally solves problems others have faced, we are progressing toward a consensus theory of high performance.

Development of high performance cladding materials

International Nuclear Information System (INIS)

Park, Jeong Yong; Jeong, Y. H.; Park, S. Y.

2010-04-01

The irradiation test for HANA claddings conducted and a series of evaluation for next-HANA claddings as well as their in-pile and out-of pile performances tests were also carried out at Halden research reactor. The 6th irradiation test have been completed successfully in Halden research reactor. As a result, HANA claddings showed high performance, such as corrosion resistance increased by 40% compared to Zircaloy-4. The high performance of HANA claddings in Halden test has enabled lead test rod program as the first step of the commercialization of HANA claddings. DB has been established for thermal and LOCA-related properties. It was confirmed from the thermal shock test that the integrity of HANA claddings was maintained in more expanded region than the criteria regulated by NRC. The manufacturing process of strips was established in order to apply HANA alloys, which were originally developed for the claddings, to the spacer grids. 250 kinds of model alloys for the next-generation claddings were designed and manufactured over 4 times and used to select the preliminary candidate alloys for the next-generation claddings. The selected candidate alloys showed 50% better corrosion resistance and 20% improved high temperature oxidation resistance compared to the foreign advanced claddings. We established the manufacturing condition controlling the performance of the dual-cooled claddings by changing the reduction rate in the cold working steps

Integrated optoelectronic materials and circuits for optical interconnects

International Nuclear Information System (INIS)

Hutcheson, L.D.

1988-01-01

Conventional interconnect and switching technology is rapidly becoming a critical issue in the realization of systems using high speed silicon and GaAs based technologies. In recent years clock speeds and on-chip density for VLSI/VHSIC technology has made packaging these high speed chips extremely difficult. A strong case can be made for using optical interconnects for on-chip/on-wafer, chip-to-chip and board-to-board high speed communications. GaAs integrated optoelectronic circuits (IOC's) are being developed in a number of laboratories for performing Input/Output functions at all levels. In this paper integrated optoelectronic materials, electronics and optoelectronic devices are presented. IOC's are examined from the standpoint of what it takes to fabricate the devices and what performance can be expected

Transistor analogs of emergent iono-neuronal dynamics.

Science.gov (United States)

Rachmuth, Guy; Poon, Chi-Sang

2008-06-01

Neuromorphic analog metal-oxide-silicon (MOS) transistor circuits promise compact, low-power, and high-speed emulations of iono-neuronal dynamics orders-of-magnitude faster than digital simulation. However, their inherently limited input voltage dynamic range vs power consumption and silicon die area tradeoffs makes them highly sensitive to transistor mismatch due to fabrication inaccuracy, device noise, and other nonidealities. This limitation precludes robust analog very-large-scale-integration (aVLSI) circuits implementation of emergent iono-neuronal dynamics computations beyond simple spiking with limited ion channel dynamics. Here we present versatile neuromorphic analog building-block circuits that afford near-maximum voltage dynamic range operating within the low-power MOS transistor weak-inversion regime which is ideal for aVLSI implementation or implantable biomimetic device applications. The fabricated microchip allowed robust realization of dynamic iono-neuronal computations such as coincidence detection of presynaptic spikes or pre- and postsynaptic activities. As a critical performance benchmark, the high-speed and highly interactive iono-neuronal simulation capability on-chip enabled our prompt discovery of a minimal model of chaotic pacemaker bursting, an emergent iono-neuronal behavior of fundamental biological significance which has hitherto defied experimental testing or computational exploration via conventional digital or analog simulations. These compact and power-efficient transistor analogs of emergent iono-neuronal dynamics open new avenues for next-generation neuromorphic, neuroprosthetic, and brain-machine interface applications.

High performance computing in Windows Azure cloud

OpenAIRE

Ambruš, Dejan

2013-01-01

High performance, security, availability, scalability, flexibility and lower costs of maintenance have essentially contributed to the growing popularity of cloud computing in all spheres of life, especially in business. In fact cloud computing offers even more than this. With usage of virtual computing clusters a runtime environment for high performance computing can be efficiently implemented also in a cloud. There are many advantages but also some disadvantages of cloud computing, some ...

High Performance Work System, HRD Climate and Organisational Performance: An Empirical Study

Science.gov (United States)

Muduli, Ashutosh

2015-01-01

Purpose: This paper aims to study the relationship between high-performance work system (HPWS) and organizational performance and to examine the role of human resource development (HRD) Climate in mediating the relationship between HPWS and the organizational performance in the context of the power sector of India. Design/methodology/approach: The…

Governance among Malaysian high performing companies

Directory of Open Access Journals (Sweden)

Asri Marsidi

2016-07-01

Full Text Available Well performed companies have always been linked with effective governance which is generally reflected through effective board of directors. However many issues concerning the attributes for effective board of directors remained unresolved. Nowadays diversity has been perceived as able to influence the corporate performance due to the likelihood of meeting variety of needs and demands from diverse customers and clients. The study therefore aims to provide a fundamental understanding on governance among high performing companies in Malaysia.

Powder metallurgical high performance materials. Proceedings. Volume 1: high performance P/M metals

International Nuclear Information System (INIS)

Kneringer, G.; Roedhammer, P.; Wildner, H.

2001-01-01

The proceedings of this sequence of seminars form an impressive chronicle of the continued progress in the understanding of refractory metals and cemented carbides and in their manufacture and application. There the ingenuity and assiduous work of thousands of scientists and engineers striving for progress in the field of powder metallurgy is documented in more than 2000 contributions covering some 30000 pages. The 15th Plansee Seminar was convened under the general theme 'Powder Metallurgical High Performance Materials'. Under this broadened perspective the seminar will strive to look beyond the refractory metals and cemented carbides, which remain at its focus, to novel classes of materials, such as intermetallic compounds, with potential for high temperature applications. (author)

Powder metallurgical high performance materials. Proceedings. Volume 1: high performance P/M metals

Energy Technology Data Exchange (ETDEWEB)

Kneringer, G; Roedhammer, P; Wildner, H [eds.

2001-07-01

The proceedings of this sequence of seminars form an impressive chronicle of the continued progress in the understanding of refractory metals and cemented carbides and in their manufacture and application. There the ingenuity and assiduous work of thousands of scientists and engineers striving for progress in the field of powder metallurgy is documented in more than 2000 contributions covering some 30000 pages. The 15th Plansee Seminar was convened under the general theme 'Powder Metallurgical High Performance Materials'. Under this broadened perspective the seminar will strive to look beyond the refractory metals and cemented carbides, which remain at its focus, to novel classes of materials, such as intermetallic compounds, with potential for high temperature applications. (author)

High-Speed, High-Performance DQPSK Optical Links with Reduced Complexity VDFE Equalizers

Directory of Open Access Journals (Sweden)

Maki Nanou

2017-02-01

Full Text Available Optical transmission technologies optimized for optical network segments sensitive to power consumption and cost, comprise modulation formats with direct detection technologies. Specifically, non-return to zero differential quaternary phase shift keying (NRZ-DQPSK in deployed fiber plants, combined with high-performance, low-complexity electronic equalizers to compensate residual impairments at the receiver end, can be proved as a viable solution for high-performance, high-capacity optical links. Joint processing of the constructive and the destructive signals at the single-ended DQPSK receiver provides improved performance compared to the balanced configuration, however, at the expense of higher hardware requirements, a fact that may not be neglected especially in the case of high-speed optical links. To overcome this bottleneck, the use of partially joint constructive/destructive DQPSK equalization is investigated in this paper. Symbol-by-symbol equalization is performed by means of Volterra decision feedback-type equalizers, driven by a reduced subset of signals selected from the constructive and the destructive ports of the optical detectors. The proposed approach offers a low-complexity alternative for electronic equalization, without sacrificing much of the performance compared to the fully-deployed counterpart. The efficiency of the proposed equalizers is demonstrated by means of computer simulation in a typical optical transmission scenario.

Design of JMTR high-performance fuel element

International Nuclear Information System (INIS)

Sakurai, Fumio; Shimakawa, Satoshi; Komori, Yoshihiro; Tsuchihashi, Keiichiro; Kaminaga, Fumito

1999-01-01

For test and research reactors, the core conversion to low-enriched uranium fuel is required from the viewpoint of non-proliferation of nuclear weapon material. Improvements of core performance are also required in order to respond to recent advanced utilization needs. In order to meet both requirements, a high-performance fuel element of high uranium density with Cd wires as burnable absorbers was adopted for JMTR core conversion to low-enriched uranium fuel. From the result of examination of an adaptability of a few group constants generated by a conventional transport-theory calculation with an isotropic scattering approximation to a few group diffusion-theory core calculation for design of the JMTR high-performance fuel element, it was clear that the depletion of Cd wires was not able to be predicted accurately using group constants generated by the conventional method. Therefore, a new generation method of a few group constants in consideration of an incident neutron spectrum at Cd wire was developed. As the result, the most suitable high-performance fuel element for JMTR was designed successfully, and that allowed extension of operation duration without refueling to almost twice as long and offer of irradiation field with constant neutron flux. (author)

ELMs IN DIII-D HIGH PERFORMANCE DISCHARGES

International Nuclear Information System (INIS)

TURNBULL, A.D; LAO, L.L; OSBORNE, T.H; SAUTER, O; STRAIT, E.J; TAYLOR, T.S; CHU, M.S; FERRON, J.R; GREENFIELD, C.M; LEONARD, A.W; MILLER, R.L; SNYDER, P.B; WILSON, H.R; ZOHM, H

2003-01-01

A new understanding of edge localized modes (ELMs) in tokamak discharges is emerging [P.B. Snyder, et al., Phys. Plasmas, 9, 2037 (2002)], in which the ELM is an essentially ideal magnetohydrodynamic (MHD) instability and the ELM severity is determined by the radial width of the linearly unstable MHD kink modes. A detailed, comparative study of the penetration into the core of the respective linear instabilities in a standard DIII-D ELMing, high confinement mode (H-mode) discharge, with that for two relatively high performance discharges shows that these are also encompassed within the framework of the new model. These instabilities represent the key, limiting factor in extending the high performance of these discharges. In the standard ELMing H-mode, the MHD instabilities are highly localized in the outer few percent flux surfaces and the ELM is benign, causing only a small temporary drop in the energy confinement. In contrast, for both a very high confinement mode (VH-mode) and an H-mode with a broad internal transport barrier (ITB) extending over the entire core and coalesced with the edge transport barrier, the linearly unstable modes penetrate well into the mid radius and the corresponding consequences for global confinement are significantly more severe. The ELM accordingly results in an irreversible loss of the high performance

The path toward HEP High Performance Computing

CERN Document Server

Apostolakis, John; Carminati, Federico; Gheata, Andrei; Wenzel, Sandro

2014-01-01

High Energy Physics code has been known for making poor use of high performance computing architectures. Efforts in optimising HEP code on vector and RISC architectures have yield limited results and recent studies have shown that, on modern architectures, it achieves a performance between 10% and 50% of the peak one. Although several successful attempts have been made to port selected codes on GPUs, no major HEP code suite has a 'High Performance' implementation. With LHC undergoing a major upgrade and a number of challenging experiments on the drawing board, HEP cannot any longer neglect the less-than-optimal performance of its code and it has to try making the best usage of the hardware. This activity is one of the foci of the SFT group at CERN, which hosts, among others, the Root and Geant4 project. The activity of the experiments is shared and coordinated via a Concurrency Forum, where the experience in optimising HEP code is presented and discussed. Another activity is the Geant-V project, centred on th...

Turbo decoder architecture for beyond-4G applications

CERN Document Server

Wong, Cheng-Chi

2013-01-01

This book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications. The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time. Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respec

Quantum Computing

Indian Academy of Sciences (India)

performance driven optimization ofVLSI ... start-up company at lIT. Mumbai. ... 1 The best known algorithms for factorization ... make a measurement the quantum state continues to be ... cally in this way: if there is a source producing identical.

3D printed high performance strain sensors for high temperature applications

Science.gov (United States)

Rahman, Md Taibur; Moser, Russell; Zbib, Hussein M.; Ramana, C. V.; Panat, Rahul

2018-01-01

Realization of high temperature physical measurement sensors, which are needed in many of the current and emerging technologies, is challenging due to the degradation of their electrical stability by drift currents, material oxidation, thermal strain, and creep. In this paper, for the first time, we demonstrate that 3D printed sensors show a metamaterial-like behavior, resulting in superior performance such as high sensitivity, low thermal strain, and enhanced thermal stability. The sensors were fabricated using silver (Ag) nanoparticles (NPs), using an advanced Aerosol Jet based additive printing method followed by thermal sintering. The sensors were tested under cyclic strain up to a temperature of 500 °C and showed a gauge factor of 3.15 ± 0.086, which is about 57% higher than that of those available commercially. The sensor thermal strain was also an order of magnitude lower than that of commercial gages for operation up to a temperature of 500 °C. An analytical model was developed to account for the enhanced performance of such printed sensors based on enhanced lateral contraction of the NP films due to the porosity, a behavior akin to cellular metamaterials. The results demonstrate the potential of 3D printing technology as a pathway to realize highly stable and high-performance sensors for high temperature applications.

High performance carbon nanocomposites for ultracapacitors

Science.gov (United States)

Lu, Wen

2012-10-02

The present invention relates to composite electrodes for electrochemical devices, particularly to carbon nanotube composite electrodes for high performance electrochemical devices, such as ultracapacitors.

High-Performance Java Codes for Computational Fluid Dynamics

Science.gov (United States)

Riley, Christopher; Chatterjee, Siddhartha; Biswas, Rupak; Biegel, Bryan (Technical Monitor)

2001-01-01

The computational science community is reluctant to write large-scale computationally -intensive applications in Java due to concerns over Java's poor performance, despite the claimed software engineering advantages of its object-oriented features. Naive Java implementations of numerical algorithms can perform poorly compared to corresponding Fortran or C implementations. To achieve high performance, Java applications must be designed with good performance as a primary goal. This paper presents the object-oriented design and implementation of two real-world applications from the field of Computational Fluid Dynamics (CFD): a finite-volume fluid flow solver (LAURA, from NASA Langley Research Center), and an unstructured mesh adaptation algorithm (2D_TAG, from NASA Ames Research Center). This work builds on our previous experience with the design of high-performance numerical libraries in Java. We examine the performance of the applications using the currently available Java infrastructure and show that the Java version of the flow solver LAURA performs almost within a factor of 2 of the original procedural version. Our Java version of the mesh adaptation algorithm 2D_TAG performs within a factor of 1.5 of its original procedural version on certain platforms. Our results demonstrate that object-oriented software design principles are not necessarily inimical to high performance.

Strategy Guideline: Partnering for High Performance Homes

Energy Technology Data Exchange (ETDEWEB)

Prahl, D.

2013-01-01

High performance houses require a high degree of coordination and have significant interdependencies between various systems in order to perform properly, meet customer expectations, and minimize risks for the builder. Responsibility for the key performance attributes is shared across the project team and can be well coordinated through advanced partnering strategies. For high performance homes, traditional partnerships need to be matured to the next level and be expanded to all members of the project team including trades, suppliers, manufacturers, HERS raters, designers, architects, and building officials as appropriate. In an environment where the builder is the only source of communication between trades and consultants and where relationships are, in general, adversarial as opposed to cooperative, the chances of any one building system to fail are greater. Furthermore, it is much harder for the builder to identify and capitalize on synergistic opportunities. Partnering can help bridge the cross-functional aspects of the systems approach and achieve performance-based criteria. Critical success factors for partnering include support from top management, mutual trust, effective and open communication, effective coordination around common goals, team building, appropriate use of an outside facilitator, a partnering charter progress toward common goals, an effective problem-solving process, long-term commitment, continuous improvement, and a positive experience for all involved.

Quantum Accelerators for High-performance Computing Systems

Energy Technology Data Exchange (ETDEWEB)

Humble, Travis S. [ORNL; Britt, Keith A. [ORNL; Mohiyaddin, Fahd A. [ORNL

2017-11-01

We define some of the programming and system-level challenges facing the application of quantum processing to high-performance computing. Alongside barriers to physical integration, prominent differences in the execution of quantum and conventional programs challenges the intersection of these computational models. Following a brief overview of the state of the art, we discuss recent advances in programming and execution models for hybrid quantum-classical computing. We discuss a novel quantum-accelerator framework that uses specialized kernels to offload select workloads while integrating with existing computing infrastructure. We elaborate on the role of the host operating system to manage these unique accelerator resources, the prospects for deploying quantum modules, and the requirements placed on the language hierarchy connecting these different system components. We draw on recent advances in the modeling and simulation of quantum computing systems with the development of architectures for hybrid high-performance computing systems and the realization of software stacks for controlling quantum devices. Finally, we present simulation results that describe the expected system-level behavior of high-performance computing systems composed from compute nodes with quantum processing units. We describe performance for these hybrid systems in terms of time-to-solution, accuracy, and energy consumption, and we use simple application examples to estimate the performance advantage of quantum acceleration.

Development and characterization of high-resolution neutron pixel detectors based on Timepix read-out chips

Czech Academy of Sciences Publication Activity Database

Krejčí, F.; Žemlička, J.; Jakoubek, J.; Dudák, J.; Vavřík, D.; Koster, U.; Atkins, D.; Kaestner, A.; Šoltéš, J.; Viererbl, L.; Vacík, Jiří; Tomandl, Ivo

2016-01-01

Roč. 11, DEC (2016), č. článku C12026. ISSN 1748-0221 R&D Projects: GA TA ČR TA01010237 Institutional support: RVO:61389005 Keywords : neutron detector s * Pixalated detector s and associated VLSI electronics Subject RIV: BG - Nuclear, Atomic and Molecular Physics, Colliders OBOR OECD: Nuclear physics Impact factor: 1.220, year: 2016

High Performance Commercial Fenestration Framing Systems

Energy Technology Data Exchange (ETDEWEB)

Mike Manteghi; Sneh Kumar; Joshua Early; Bhaskar Adusumalli

2010-01-31

A major objective of the U.S. Department of Energy is to have a zero energy commercial building by the year 2025. Windows have a major influence on the energy performance of the building envelope as they control over 55% of building energy load, and represent one important area where technologies can be developed to save energy. Aluminum framing systems are used in over 80% of commercial fenestration products (i.e. windows, curtain walls, store fronts, etc.). Aluminum framing systems are often required in commercial buildings because of their inherent good structural properties and long service life, which is required from commercial and architectural frames. At the same time, they are lightweight and durable, requiring very little maintenance, and offer design flexibility. An additional benefit of aluminum framing systems is their relatively low cost and easy manufacturability. Aluminum, being an easily recyclable material, also offers sustainable features. However, from energy efficiency point of view, aluminum frames have lower thermal performance due to the very high thermal conductivity of aluminum. Fenestration systems constructed of aluminum alloys therefore have lower performance in terms of being effective barrier to energy transfer (heat loss or gain). Despite the lower energy performance, aluminum is the choice material for commercial framing systems and dominates the commercial/architectural fenestration market because of the reasons mentioned above. In addition, there is no other cost effective and energy efficient replacement material available to take place of aluminum in the commercial/architectural market. Hence it is imperative to improve the performance of aluminum framing system to improve the energy performance of commercial fenestration system and in turn reduce the energy consumption of commercial building and achieve zero energy building by 2025. The objective of this project was to develop high performance, energy efficient commercial

High-Performance Management Practices and Employee Outcomes in Denmark

DEFF Research Database (Denmark)

Cristini, Annalisa; Eriksson, Tor; Pozzoli, Dario

High-performance work practices are frequently considered to have positive effects on corporate performance, but what do they do for employees? After showing that organizational innovation is indeed positively associated with firm performance, we investigate whether high-involvement work practices...

Optical interconnection networks for high-performance computing systems

International Nuclear Information System (INIS)

Biberman, Aleksandr; Bergman, Keren

2012-01-01

Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. Chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, offer unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of our work, we demonstrate such feasibility of waveguides, modulators, switches and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. We propose novel silicon photonic devices, subsystems, network topologies and architectures to enable unprecedented performance of these photonic interconnection networks. Furthermore, the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers. (review article)

High-performance, stretchable, wire-shaped supercapacitors.

Science.gov (United States)

Chen, Tao; Hao, Rui; Peng, Huisheng; Dai, Liming

2015-01-07

A general approach toward extremely stretchable and highly conductive electrodes was developed. The method involves wrapping a continuous carbon nanotube (CNT) thin film around pre-stretched elastic wires, from which high-performance, stretchable wire-shaped supercapacitors were fabricated. The supercapacitors were made by twisting two such CNT-wrapped elastic wires, pre-coated with poly(vinyl alcohol)/H3PO4 hydrogel, as the electrolyte and separator. The resultant wire-shaped supercapacitors exhibited an extremely high elasticity of up to 350% strain with a high device capacitance up to 30.7 F g(-1), which is two times that of the state-of-the-art stretchable supercapacitor under only 100% strain. The wire-shaped structure facilitated the integration of multiple supercapacitors into a single wire device to meet specific energy and power needs for various potential applications. These supercapacitors can be repeatedly stretched from 0 to 200% strain for hundreds of cycles with no change in performance, thus outperforming all the reported state-of-the-art stretchable electronics. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High-Sensitivity Temperature-Independent Silicon Photonic Microfluidic Biosensors

Science.gov (United States)

Kim, Kangbaek

Optical biosensors that can precisely quantify the presence of specific molecular species in real time without the need for labeling have seen increased use in the drug discovery industry and molecular biology in general. Of the many possible optical biosensors, the TM mode Si biosensor is shown to be very attractive in the sensing application because of large field amplitude on the surface and cost effective CMOS VLSI fabrication. Noise is the most fundamental factor that limits the performance of sensors in development of high-sensitivity biosensors, and noise reduction techniques require precise studies and analysis. One such example stems from thermal fluctuations. Generally SOI biosensors are vulnerable to ambient temperature fluctuations because of large thermo-optic coefficient of silicon (˜2x10 -4 RIU/K), typically requiring another reference ring and readout sequence to compensate temperature induced noise. To address this problem, we designed sensors with a novel TM-mode shallow-ridge waveguide that provides both large surface amplitude for bulk and surface sensing. With proper design, this also provides large optical confinement in the aqueous cladding that renders the device athermal using the negative thermo-optic coefficient of water (~ --1x10-4RIU/K), demonstrating cancellation of thermo-optic effects for aqueous solution operation near 300K. Additional limitations resulting from mechanical actuator fluctuations, stability of tunable lasers, and large 1/f noise of lasers and sensor electronics can limit biosensor performance. Here we also present a simple harmonic feedback readout technique that obviates the need for spectrometers and tunable lasers. This feedback technique reduces the impact of 1/f noise to enable high-sensitivity, and a DSP lock-in with 256 kHz sampling rate can provide down to micros time scale monitoring for fast transitions in biomolecular concentration with potential for small volume and low cost. In this dissertation, a novel

High Performance Computing in Science and Engineering '14

CERN Document Server

Kröner, Dietmar; Resch, Michael

2015-01-01

This book presents the state-of-the-art in supercomputer simulation. It includes the latest findings from leading researchers using systems from the High Performance Computing Center Stuttgart (HLRS). The reports cover all fields of computational science and engineering ranging from CFD to computational physics and from chemistry to computer science with a special emphasis on industrially relevant applications. Presenting findings of one of Europe’s leading systems, this volume covers a wide variety of applications that deliver a high level of sustained performance. The book covers the main methods in high-performance computing. Its outstanding results in achieving the best performance for production codes are of particular interest for both scientists and   engineers. The book comes with a wealth of color illustrations and tables of results.  

Department of Energy research in utilization of high-performance computers

International Nuclear Information System (INIS)

Buzbee, B.L.; Worlton, W.J.; Michael, G.; Rodrigue, G.

1980-08-01

Department of Energy (DOE) and other Government research laboratories depend on high-performance computer systems to accomplish their programmatic goals. As the most powerful computer systems become available, they are acquired by these laboratories so that advances can be made in their disciplines. These advances are often the result of added sophistication to numerical models, the execution of which is made possible by high-performance computer systems. However, high-performance computer systems have become increasingly complex, and consequently it has become increasingly difficult to realize their potential performance. The result is a need for research on issues related to the utilization of these systems. This report gives a brief description of high-performance computers, and then addresses the use of and future needs for high-performance computers within DOE, the growing complexity of applications within DOE, and areas of high-performance computer systems warranting research. 1 figure

Mechanical Properties of High Performance Cementitious Grout (II)

DEFF Research Database (Denmark)

Sørensen, Eigil V.

The present report is an update of the report “Mechanical Properties of High Performance Cementitious Grout (I)” [1] and describes tests carried out on the high performance grout MASTERFLOW 9500, marked “WMG 7145 FP”, developed by BASF Construction Chemicals A/S and designed for use in grouted...

A Linux Workstation for High Performance Graphics

Science.gov (United States)

Geist, Robert; Westall, James

2000-01-01

The primary goal of this effort was to provide a low-cost method of obtaining high-performance 3-D graphics using an industry standard library (OpenGL) on PC class computers. Previously, users interested in doing substantial visualization or graphical manipulation were constrained to using specialized, custom hardware most often found in computers from Silicon Graphics (SGI). We provided an alternative to expensive SGI hardware by taking advantage of third-party, 3-D graphics accelerators that have now become available at very affordable prices. To make use of this hardware our goal was to provide a free, redistributable, and fully-compatible OpenGL work-alike library so that existing bodies of code could simply be recompiled. for PC class machines running a free version of Unix. This should allow substantial cost savings while greatly expanding the population of people with access to a serious graphics development and viewing environment. This should offer a means for NASA to provide a spectrum of graphics performance to its scientists, supplying high-end specialized SGI hardware for high-performance visualization while fulfilling the requirements of medium and lower performance applications with generic, off-the-shelf components and still maintaining compatibility between the two.

Strategies and Experiences Using High Performance Fortran

National Research Council Canada - National Science Library

Shires, Dale

2001-01-01

.... High performance Fortran (HPF) is a relative new addition to the Fortran dialect It is an attempt to provide an efficient high-level Fortran parallel programming language for the latest generation of been debatable...

Controlling Underwater Robots with Electronic Nervous Systems

Directory of Open Access Journals (Sweden)

Joseph Ayers

2010-01-01

Full Text Available We are developing robot controllers based on biomimetic design principles. The goal is to realise the adaptive capabilities of the animal models in natural environments. We report feasibility studies of a hybrid architecture that instantiates a command and coordinating level with computed discrete-time map-based (DTM neuronal networks and the central pattern generators with analogue VLSI (Very Large Scale Integration electronic neuron (aVLSI networks. DTM networks are realised using neurons based on a 1-D or 2-D Map with two additional parameters that define silent, spiking and bursting regimes. Electronic neurons (ENs based on Hindmarsh–Rose (HR dynamics can be instantiated in analogue VLSI and exhibit similar behaviour to those based on discrete components. We have constructed locomotor central pattern generators (CPGs with aVLSI networks that can be modulated to select different behaviours on the basis of selective command input. The two technologies can be fused by interfacing the signals from the DTM circuits directly to the aVLSI CPGs. Using DTMs, we have been able to simulate complex sensory fusion for rheotaxic behaviour based on both hydrodynamic and optical flow senses. We will illustrate aspects of controllers for ambulatory biomimetic robots. These studies indicate that it is feasible to fabricate an electronic nervous system controller integrating both aVLSI CPGs and layered DTM exteroceptive reflexes.

High performance anode for advanced Li batteries

Energy Technology Data Exchange (ETDEWEB)

Lake, Carla [Applied Sciences, Inc., Cedarville, OH (United States)

2015-11-02

The overall objective of this Phase I SBIR effort was to advance the manufacturing technology for ASI’s Si-CNF high-performance anode by creating a framework for large volume production and utilization of low-cost Si-coated carbon nanofibers (Si-CNF) for the battery industry. This project explores the use of nano-structured silicon which is deposited on a nano-scale carbon filament to achieve the benefits of high cycle life and high charge capacity without the consequent fading of, or failure in the capacity resulting from stress-induced fracturing of the Si particles and de-coupling from the electrode. ASI’s patented coating process distinguishes itself from others, in that it is highly reproducible, readily scalable and results in a Si-CNF composite structure containing 25-30% silicon, with a compositionally graded interface at the Si-CNF interface that significantly improve cycling stability and enhances adhesion of silicon to the carbon fiber support. In Phase I, the team demonstrated the production of the Si-CNF anode material can successfully be transitioned from a static bench-scale reactor into a fluidized bed reactor. In addition, ASI made significant progress in the development of low cost, quick testing methods which can be performed on silicon coated CNFs as a means of quality control. To date, weight change, density, and cycling performance were the key metrics used to validate the high performance anode material. Under this effort, ASI made strides to establish a quality control protocol for the large volume production of Si-CNFs and has identified several key technical thrusts for future work. Using the results of this Phase I effort as a foundation, ASI has defined a path forward to commercialize and deliver high volume and low-cost production of SI-CNF material for anodes in Li-ion batteries.

Evaluation of high-performance computing software

Energy Technology Data Exchange (ETDEWEB)

Browne, S.; Dongarra, J. [Univ. of Tennessee, Knoxville, TN (United States); Rowan, T. [Oak Ridge National Lab., TN (United States)

1996-12-31

The absence of unbiased and up to date comparative evaluations of high-performance computing software complicates a user`s search for the appropriate software package. The National HPCC Software Exchange (NHSE) is attacking this problem using an approach that includes independent evaluations of software, incorporation of author and user feedback into the evaluations, and Web access to the evaluations. We are applying this approach to the Parallel Tools Library (PTLIB), a new software repository for parallel systems software and tools, and HPC-Netlib, a high performance branch of the Netlib mathematical software repository. Updating the evaluations with feed-back and making it available via the Web helps ensure accuracy and timeliness, and using independent reviewers produces unbiased comparative evaluations difficult to find elsewhere.

High Performance Proactive Digital Forensics

International Nuclear Information System (INIS)

Alharbi, Soltan; Traore, Issa; Moa, Belaid; Weber-Jahnke, Jens

2012-01-01

With the increase in the number of digital crimes and in their sophistication, High Performance Computing (HPC) is becoming a must in Digital Forensics (DF). According to the FBI annual report, the size of data processed during the 2010 fiscal year reached 3,086 TB (compared to 2,334 TB in 2009) and the number of agencies that requested Regional Computer Forensics Laboratory assistance increasing from 689 in 2009 to 722 in 2010. Since most investigation tools are both I/O and CPU bound, the next-generation DF tools are required to be distributed and offer HPC capabilities. The need for HPC is even more evident in investigating crimes on clouds or when proactive DF analysis and on-site investigation, requiring semi-real time processing, are performed. Although overcoming the performance challenge is a major goal in DF, as far as we know, there is almost no research on HPC-DF except for few papers. As such, in this work, we extend our work on the need of a proactive system and present a high performance automated proactive digital forensic system. The most expensive phase of the system, namely proactive analysis and detection, uses a parallel extension of the iterative z algorithm. It also implements new parallel information-based outlier detection algorithms to proactively and forensically handle suspicious activities. To analyse a large number of targets and events and continuously do so (to capture the dynamics of the system), we rely on a multi-resolution approach to explore the digital forensic space. Data set from the Honeynet Forensic Challenge in 2001 is used to evaluate the system from DF and HPC perspectives.

Sex Differences in Mathematics Performance among Senior High ...

African Journals Online (AJOL)

This study explored sex differences in mathematics performance of students in the final year of high school and changes in these differences over a 3-year period in Ghana. A convenience sample of 182 students, 109 boys and 72 girls in three high schools in Ghana was used. Mathematics performance was assessed using ...

Embedded High Performance Scalable Computing Systems

National Research Council Canada - National Science Library

Ngo, David

2003-01-01

The Embedded High Performance Scalable Computing Systems (EHPSCS) program is a cooperative agreement between Sanders, A Lockheed Martin Company and DARPA that ran for three years, from Apr 1995 - Apr 1998...

High-performance vertical organic transistors.

Science.gov (United States)

Kleemann, Hans; Günther, Alrun A; Leo, Karl; Lüssem, Björn

2013-11-11

Vertical organic thin-film transistors (VOTFTs) are promising devices to overcome the transconductance and cut-off frequency restrictions of horizontal organic thin-film transistors. The basic physical mechanisms of VOTFT operation, however, are not well understood and VOTFTs often require complex patterning techniques using self-assembly processes which impedes a future large-area production. In this contribution, high-performance vertical organic transistors comprising pentacene for p-type operation and C60 for n-type operation are presented. The static current-voltage behavior as well as the fundamental scaling laws of such transistors are studied, disclosing a remarkable transistor operation with a behavior limited by injection of charge carriers. The transistors are manufactured by photolithography, in contrast to other VOTFT concepts using self-assembled source electrodes. Fluorinated photoresist and solvent compounds allow for photolithographical patterning directly and strongly onto the organic materials, simplifying the fabrication protocol and making VOTFTs a prospective candidate for future high-performance applications of organic transistors. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High-performance non-volatile organic ferroelectric memory on banknotes

KAUST Repository

Khan, Yasser; Bhansali, Unnat Sampatraj; Alshareef, Husam N.

2012-01-01

High-performance non-volatile polymer ferroelectric memory are fabricated on banknotes using poly(vinylidene fluoride trifluoroethylene). The devices show excellent performance with high remnant polarization, low operating voltages, low leakage

High-performance non-volatile organic ferroelectric memory on banknotes

KAUST Repository

Khan, Yasser

2012-03-21

High-performance non-volatile polymer ferroelectric memory are fabricated on banknotes using poly(vinylidene fluoride trifluoroethylene). The devices show excellent performance with high remnant polarization, low operating voltages, low leakage, high mobility, and long retention times. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High-performance non-volatile organic ferroelectric memory on banknotes.

Science.gov (United States)

Khan, M A; Bhansali, Unnat S; Alshareef, H N

2012-04-24

High-performance non-volatile polymer ferroelectric memory are fabricated on banknotes using poly(vinylidene fluoride trifluoroethylene). The devices show excellent performance with high remnant polarization, low operating voltages, low leakage, high mobility, and long retention times. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

THE RELATION OF HIGH-PERFORMANCE WORK SYSTEMS WITH EMPLOYEE INVOLVEMENT

Directory of Open Access Journals (Sweden)

Bilal AFSAR

2010-01-01

Full Text Available The basic aim of high performance work systems is to enable employees to exercise decision making, leading to flexibility, innovation, improvement and skill sharing. By facilitating the development of high performance work systems we help organizations make continuous improvement a way of life.The notion of a high-performance work system (HPWS constitutes a claim that there exists a system of work practices for core workers in an organisation that leads in some way to superior performance. This article will discuss the relation that HPWS has with the improvement of firms’ performance and high involvement of the employees.

Contemporary high performance computing from petascale toward exascale

CERN Document Server

Vetter, Jeffrey S

2013-01-01

Contemporary High Performance Computing: From Petascale toward Exascale focuses on the ecosystems surrounding the world's leading centers for high performance computing (HPC). It covers many of the important factors involved in each ecosystem: computer architectures, software, applications, facilities, and sponsors. The first part of the book examines significant trends in HPC systems, including computer architectures, applications, performance, and software. It discusses the growth from terascale to petascale computing and the influence of the TOP500 and Green500 lists. The second part of the

Pengaruh High Performance Work Practice (Hpwp) Terhadap Job Performance Pada Frontliner Bank

OpenAIRE

Ihdaryanti, Monica Amani; Panggabean, Mutiara S

2014-01-01

Generally High Performance Work Practice (HPWP) is a part of management human resources. The objectives of this research are getting and analyzing the effect of HPWPs with Job Satisfaction; HPWPs with Organizational Commitment; Job Satisfaction with Organizational Commitment; Job Satisfaction with Job Performance; and Organizational Commitment with Job Performance. The total of sample in this research is 100 respondents which are as Front liner BNI and Mandiri. The result of th...

High performance liquid chromatographic determination of ...

African Journals Online (AJOL)

STORAGESEVER

2010-02-08

) high performance liquid chromatography (HPLC) grade .... applications. These are important requirements if the reagent is to be applicable to on-line pre or post column derivatisation in a possible automation of the analytical.

Can Knowledge of the Characteristics of "High Performers" Be Generalised?

Science.gov (United States)

McKenna, Stephen

2002-01-01

Two managers described as high performing constructed complexity maps of their organization/world. The maps suggested that high performance is socially constructed and negotiated in specific contexts and management competencies associated with it are context specific. Development of high performers thus requires personalized coaching more than…

Comparing Dutch and British high performing managers

NARCIS (Netherlands)

Waal, A.A. de; Heijden, B.I.J.M. van der; Selvarajah, C.; Meyer, D.

2016-01-01

National cultures have a strong influence on the performance of organizations and should be taken into account when studying the traits of high performing managers. At the same time, many studies that focus upon the attributes of successful managers show that there are attributes that are similar

Micromagnetics on high-performance workstation and mobile computational platforms

Science.gov (United States)

Fu, S.; Chang, R.; Couture, S.; Menarini, M.; Escobar, M. A.; Kuteifan, M.; Lubarda, M.; Gabay, D.; Lomakin, V.

2015-05-01

The feasibility of using high-performance desktop and embedded mobile computational platforms is presented, including multi-core Intel central processing unit, Nvidia desktop graphics processing units, and Nvidia Jetson TK1 Platform. FastMag finite element method-based micromagnetic simulator is used as a testbed, showing high efficiency on all the platforms. Optimization aspects of improving the performance of the mobile systems are discussed. The high performance, low cost, low power consumption, and rapid performance increase of the embedded mobile systems make them a promising candidate for micromagnetic simulations. Such architectures can be used as standalone systems or can be built as low-power computing clusters.

A CMOS front-end for SiPM devices aimed to TOF applications with adjustable threshold and high dynamical range

International Nuclear Information System (INIS)

Badoni, D.; Gonnella, F.; Messi, R.; Moricciani, D.; Archilli, F.; Iafolla, L.

2010-01-01

In recent works we presented the results of the characterization and the study of performance of several Silicon Photomultipliers delivered from MEPHI (Moscow Engineering and Physics Institute) and we proposed an electrical model of the SiPM to be used in analog simulations for the VLSI design of the pilot chip with 0.35μm technology produced. The results of the simulations was also presented. In this work we present the results of several test performed on the SiPM connected to the pilot chip. We also describe the prototype board with a micro-controller designed to adjust the parameters of the chip and to provide an adjustable and temperature controlled power supply to the SiPM. The results of the tests obtained allow us to refine the circuits design for the next chip. This chip has been developed inside the ALTCRISS and KLOE collaboration.

High performance light water reactor

International Nuclear Information System (INIS)

Squarer, D.; Schulenberg, T.; Struwe, D.; Oka, Y.; Bittermann, D.; Aksan, N.; Maraczy, C.; Kyrki-Rajamaeki, R.; Souyri, A.; Dumaz, P.

2003-01-01

The objective of the high performance light water reactor (HPLWR) project is to assess the merit and economic feasibility of a high efficiency LWR operating at thermodynamically supercritical regime. An efficiency of approximately 44% is expected. To accomplish this objective, a highly qualified team of European research institutes and industrial partners together with the University of Tokyo is assessing the major issues pertaining to a new reactor concept, under the co-sponsorship of the European Commission. The assessment has emphasized the recent advancement achieved in this area by Japan. Additionally, it accounts for advanced European reactor design requirements, recent improvements, practical design aspects, availability of plant components and the availability of high temperature materials. The final objective of this project is to reach a conclusion on the potential of the HPLWR to help sustain the nuclear option, by supplying competitively priced electricity, as well as to continue the nuclear competence in LWR technology. The following is a brief summary of the main project achievements:-A state-of-the-art review of supercritical water-cooled reactors has been performed for the HPLWR project.-Extensive studies have been performed in the last 10 years by the University of Tokyo. Therefore, a 'reference design', developed by the University of Tokyo, was selected in order to assess the available technological tools (i.e. computer codes, analyses, advanced materials, water chemistry, etc.). Design data and results of the analysis were supplied by the University of Tokyo. A benchmark problem, based on the 'reference design' was defined for neutronics calculations and several partners of the HPLWR project carried out independent analyses. The results of these analyses, which in addition help to 'calibrate' the codes, have guided the assessment of the core and the design of an improved HPLWR fuel assembly. Preliminary selection was made for the HPLWR scale

Strategy Guideline. High Performance Residential Lighting

Energy Technology Data Exchange (ETDEWEB)

Holton, J. [IBACOS, Inc., Pittsburgh, PA (United States)

2012-02-01

This report has been developed to provide a tool for the understanding and application of high performance lighting in the home. The strategies featured in this guide are drawn from recent advances in commercial lighting for application to typical spaces found in residential buildings. This guide offers strategies to greatly reduce lighting energy use through the application of high quality fluorescent and light emitting diode (LED) technologies. It is important to note that these strategies not only save energy in the home but also serve to satisfy the homeowner’s expectations for high quality lighting.

Improving UV Resistance of High Performance Fibers

Science.gov (United States)

Hassanin, Ahmed

High performance fibers are characterized by their superior properties compared to the traditional textile fibers. High strength fibers have high modules, high strength to weight ratio, high chemical resistance, and usually high temperature resistance. It is used in application where superior properties are needed such as bulletproof vests, ropes and cables, cut resistant products, load tendons for giant scientific balloons, fishing rods, tennis racket strings, parachute cords, adhesives and sealants, protective apparel and tire cords. Unfortunately, Ultraviolet (UV) radiation causes serious degradation to the most of high performance fibers. UV lights, either natural or artificial, cause organic compounds to decompose and degrade, because the energy of the photons of UV light is high enough to break chemical bonds causing chain scission. This work is aiming at achieving maximum protection of high performance fibers using sheathing approaches. The sheaths proposed are of lightweight to maintain the advantage of the high performance fiber that is the high strength to weight ratio. This study involves developing three different types of sheathing. The product of interest that need be protected from UV is braid from PBO. First approach is extruding a sheath from Low Density Polyethylene (LDPE) loaded with different rutile TiO2 % nanoparticles around the braid from the PBO. The results of this approach showed that LDPE sheath loaded with 10% TiO2 by weight achieved the highest protection compare to 0% and 5% TiO2. The protection here is judged by strength loss of PBO. This trend noticed in different weathering environments, where the sheathed samples were exposed to UV-VIS radiations in different weatheromter equipments as well as exposure to high altitude environment using NASA BRDL balloon. The second approach is focusing in developing a protective porous membrane from polyurethane loaded with rutile TiO2 nanoparticles. Membrane from polyurethane loaded with 4

High performance computing in linear control

International Nuclear Information System (INIS)

Datta, B.N.

1993-01-01

Remarkable progress has been made in both theory and applications of all important areas of control. The theory is rich and very sophisticated. Some beautiful applications of control theory are presently being made in aerospace, biomedical engineering, industrial engineering, robotics, economics, power systems, etc. Unfortunately, the same assessment of progress does not hold in general for computations in control theory. Control Theory is lagging behind other areas of science and engineering in this respect. Nowadays there is a revolution going on in the world of high performance scientific computing. Many powerful computers with vector and parallel processing have been built and have been available in recent years. These supercomputers offer very high speed in computations. Highly efficient software, based on powerful algorithms, has been developed to use on these advanced computers, and has also contributed to increased performance. While workers in many areas of science and engineering have taken great advantage of these hardware and software developments, control scientists and engineers, unfortunately, have not been able to take much advantage of these developments

High Performance Bulk Thermoelectric Materials

Energy Technology Data Exchange (ETDEWEB)

Ren, Zhifeng [Boston College, Chestnut Hill, MA (United States)

2013-03-31

Over 13 plus years, we have carried out research on electron pairing symmetry of superconductors, growth and their field emission property studies on carbon nanotubes and semiconducting nanowires, high performance thermoelectric materials and other interesting materials. As a result of the research, we have published 104 papers, have educated six undergraduate students, twenty graduate students, nine postdocs, nine visitors, and one technician.

Performance characterization of solid oxide cells under high pressure

DEFF Research Database (Denmark)

Sun, Xiufu; Bonaccorso, Alfredo Damiano; Graves, Christopher R.

2014-01-01

in both fuel cell mode and electrolysis mode. In electrolysis mode at low current density, the performance improvement was counteracted by the increase in open circuit voltage, but it has to be born in mind that the pressurised gas contains higher molar free energy. Operating at high current density...... hydrocarbon fuels, which is normally performed at high pressure to achieve a high yield. Operation of SOECs at elevated pressure will therefore facilitate integration with the downstream fuel synthesis and is furthermore advantageous as it increases the cell performance. In this work, recent pressurised test...... results of a planar Ni-YSZ (YSZ: Yttria stabilized Zirconia) supported solid oxide cell are presented. The test was performed at 800 °C at pressures up to 15 bar. A comparison of the electrochemical performance of the cell at 1 and 3 bar shows a significant and equal performance gain at higher pressure...

Design practice and operational experience of highly irradiated, high-performance normal magnets

International Nuclear Information System (INIS)

Schultz, J.H.

1982-09-01

The limitations of high performance magnets are discussed in terms of mechanical, temperature, and electrical limits. The limitations of magnets that are highly irradiated by neutrons, gamma radiation, or x radiation are discussed

Gradient High Performance Liquid Chromatography Method ...

African Journals Online (AJOL)

Purpose: To develop a gradient high performance liquid chromatography (HPLC) method for the simultaneous determination of phenylephrine (PHE) and ibuprofen (IBU) in solid ..... nimesulide, phenylephrine. Hydrochloride, chlorpheniramine maleate and caffeine anhydrous in pharmaceutical dosage form. Acta Pol.

High performance sapphire windows

Science.gov (United States)

Bates, Stephen C.; Liou, Larry

1993-02-01

High-quality, wide-aperture optical access is usually required for the advanced laser diagnostics that can now make a wide variety of non-intrusive measurements of combustion processes. Specially processed and mounted sapphire windows are proposed to provide this optical access to extreme environment. Through surface treatments and proper thermal stress design, single crystal sapphire can be a mechanically equivalent replacement for high strength steel. A prototype sapphire window and mounting system have been developed in a successful NASA SBIR Phase 1 project. A large and reliable increase in sapphire design strength (as much as 10x) has been achieved, and the initial specifications necessary for these gains have been defined. Failure testing of small windows has conclusively demonstrated the increased sapphire strength, indicating that a nearly flawless surface polish is the primary cause of strengthening, while an unusual mounting arrangement also significantly contributes to a larger effective strength. Phase 2 work will complete specification and demonstration of these windows, and will fabricate a set for use at NASA. The enhanced capabilities of these high performance sapphire windows will lead to many diagnostic capabilities not previously possible, as well as new applications for sapphire.

Stretchable and High-Performance Supercapacitors with Crumpled Graphene Papers

Science.gov (United States)

Zang, Jianfeng; Cao, Changyong; Feng, Yaying; Liu, Jie; Zhao, Xuanhe

2014-01-01

Fabrication of unconventional energy storage devices with high stretchability and performance is challenging, but critical to practical operations of fully power-independent stretchable electronics. While supercapacitors represent a promising candidate for unconventional energy-storage devices, existing stretchable supercapacitors are limited by their low stretchability, complicated fabrication process, and high cost. Here, we report a simple and low-cost method to fabricate extremely stretchable and high-performance electrodes for supercapacitors based on new crumpled-graphene papers. Electrolyte-mediated-graphene paper bonded on a compliant substrate can be crumpled into self-organized patterns by harnessing mechanical instabilities in the graphene paper. As the substrate is stretched, the crumpled patterns unfold, maintaining high reliability of the graphene paper under multiple cycles of large deformation. Supercapacitor electrodes based on the crumpled graphene papers exhibit a unique combination of high stretchability (e.g., linear strain ~300%, areal strain ~800%), high electrochemical performance (e.g., specific capacitance ~196 F g−1), and high reliability (e.g., over 1000 stretch/relax cycles). An all-solid-state supercapacitor capable of large deformation is further fabricated to demonstrate practical applications of the crumpled-graphene-paper electrodes. Our method and design open a wide range of opportunities for manufacturing future energy-storage devices with desired deformability together with high performance. PMID:25270673

Stretchable and High-Performance Supercapacitors with Crumpled Graphene Papers

Science.gov (United States)

Zang, Jianfeng; Cao, Changyong; Feng, Yaying; Liu, Jie; Zhao, Xuanhe

2014-10-01

Fabrication of unconventional energy storage devices with high stretchability and performance is challenging, but critical to practical operations of fully power-independent stretchable electronics. While supercapacitors represent a promising candidate for unconventional energy-storage devices, existing stretchable supercapacitors are limited by their low stretchability, complicated fabrication process, and high cost. Here, we report a simple and low-cost method to fabricate extremely stretchable and high-performance electrodes for supercapacitors based on new crumpled-graphene papers. Electrolyte-mediated-graphene paper bonded on a compliant substrate can be crumpled into self-organized patterns by harnessing mechanical instabilities in the graphene paper. As the substrate is stretched, the crumpled patterns unfold, maintaining high reliability of the graphene paper under multiple cycles of large deformation. Supercapacitor electrodes based on the crumpled graphene papers exhibit a unique combination of high stretchability (e.g., linear strain ~300%, areal strain ~800%), high electrochemical performance (e.g., specific capacitance ~196 F g-1), and high reliability (e.g., over 1000 stretch/relax cycles). An all-solid-state supercapacitor capable of large deformation is further fabricated to demonstrate practical applications of the crumpled-graphene-paper electrodes. Our method and design open a wide range of opportunities for manufacturing future energy-storage devices with desired deformability together with high performance.

High Performance Design of 100Gb/s DPSK Optical Transmitter

DEFF Research Database (Denmark)

Das, Bhagwan; Abdullah, M.F.L; Shah, Nor Shahihda Mohd

2016-01-01

and optical transmitter have taken plenty of time for transmitting signal. When proposed design is operated at 1 GHz, 5 GHz, 10 GHz and 20 GHz using time constraint technique, it is observed that among all these frequencies, at 10 GHz high performance output is achieved for designed optical transmitter....... This high performance design of optical transmitter has zero timing error, low timing score and high slack time due to synchronization between input data and clock frequency. It is also determined that 99% timing score is reduced in comparison with 1 GHz frequency that has high jitters, high timing error......, high time score and low slack time. The high performance design is realized without disturbing actual bandwidth, power consumption and other parameters of the design. The proposed high performance design of 100Gb/s optical transmitter can be used with existing optical communication system to develop...

Engineering High-Energy Interfacial Structures for High-Performance Oxygen-Involving Electrocatalysis.

Science.gov (United States)

Guo, Chunxian; Zheng, Yao; Ran, Jingrun; Xie, Fangxi; Jaroniec, Mietek; Qiao, Shi-Zhang

2017-07-10

Engineering high-energy interfacial structures for high-performance electrocatalysis is achieved by chemical coupling of active CoO nanoclusters and high-index facet Mn 3 O 4 nano-octahedrons (hi-Mn 3 O 4 ). A thorough characterization, including synchrotron-based near edge X-ray absorption fine structure, reveals that strong interactions between both components promote the formation of high-energy interfacial Mn-O-Co species and high oxidation state CoO, from which electrons are drawn by Mn III -O present in hi-Mn 3 O 4 . The CoO/hi-Mn 3 O 4 demonstrates an excellent catalytic performance over the conventional metal oxide-based electrocatalysts, which is reflected by 1.2 times higher oxygen evolution reaction (OER) activity than that of Ru/C and a comparable oxygen reduction reaction (ORR) activity to that of Pt/C as well as a better stability than that of Ru/C (95 % vs. 81 % retained OER activity) and Pt/C (92 % vs. 78 % retained ORR activity after 10 h running) in alkaline electrolyte. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Flexible nanoscale high-performance FinFETs

KAUST Repository

Sevilla, Galo T.; Ghoneim, Mohamed T.; Fahad, Hossain M.; Rojas, Jhonathan Prieto; Hussain, Aftab M.; Hussain, Muhammad Mustafa

2014-01-01

With the emergence of the Internet of Things (IoT), flexible high-performance nanoscale electronics are more desired. At the moment, FinFET is the most advanced transistor architecture used in the state-of-the-art microprocessors. Therefore, we show

Teacher Accountability at High Performing Charter Schools

Science.gov (United States)

Aguirre, Moises G.

2016-01-01

This study will examine the teacher accountability and evaluation policies and practices at three high performing charter schools located in San Diego County, California. Charter schools are exempted from many laws, rules, and regulations that apply to traditional school systems. By examining the teacher accountability systems at high performing…

Improvement of performance of ultra-high performance concrete based composite material added with nano materials

Directory of Open Access Journals (Sweden)

Pang Jinchang

2016-03-01

Full Text Available Ultra-high performance concrete (UHPC, a kind of composite material characterized by ultra high strength, high toughness and high durability. It has a wide application prospect in engineering practice. But there are some defects in concrete. How to improve strength and toughness of UHPC remains to be the target of researchers. To obtain UHPC with better performance, this study introduced nano-SiO2 and nano-CaCO3 into UHPC. Moreover, hydration heat analysis, X-Ray Diffraction (XRD, mercury intrusion porosimetry (MIP and nanoindentation tests were used to explore hydration process and microstructure. Double-doped nanomaterials can further enhance various mechanical performances of materials. Nano-SiO2 can promote early progress of cement hydration due to its high reaction activity and C-S-H gel generates when it reacts with cement hydration product Ca(OH2. Nano-CaCO3 mainly plays the role of crystal nucleus effect and filling effect. Under the combined action of the two, the composite structure is denser, which provides a way to improve the performance of UHPC in practical engineering.

Performance of high-rate gravel-packed oil wells

Energy Technology Data Exchange (ETDEWEB)

Unneland, Trond

2001-05-01

Improved methods for the prediction, evaluation, and monitoring of performance in high-rate cased-hole gravel-packed oil wells are presented in this thesis. The ability to predict well performance prior to the gravel-pack operations, evaluate the results after the operation, and monitor well performance over time has been improved. This lifetime approach to performance analysis of gravel-packed oil wells contributes to increase oil production and field profitability. First, analytical models available for prediction of performance in gravel-packed oil wells are reviewed, with particular emphasis on high-velocity flow effects. From the analysis of field data from three North Sea oil fields, improved and calibrated cased-hole gravel-pack performance prediction models are presented. The recommended model is based on serial flow through formation sand and gravel in the perforation tunnels. In addition, new correlations for high-velocity flow in high-rate gravel-packed oil wells are introduced. Combined, this improves the performance prediction for gravel-packed oil wells, and specific areas can be targeted for optimized well design. Next, limitations in the current methods and alternative methods for evaluation and comparison of well performance are presented. The most widely used parameter, the skin factor, remains a convenient and important parameter. However, using the skin concept in direct comparisons between wells with different reservoir properties may result in misleading or even invalid conclusions. A discussion of the parameters affecting the skin value, with a clarification of limitations, is included. A methodology for evaluation and comparison of gravel-packed well performance is presented, and this includes the use of results from production logs and the use of effective perforation tunnel permeability as a parameter. This contributes to optimized operational procedures from well to well and from field to field. Finally, the data sources available for

High-Performance, Space-Storable, Bi-Propellant Program Status

Science.gov (United States)

Schneider, Steven J.

2002-01-01

Bipropellant propulsion systems currently represent the largest bus subsystem for many missions. These missions range from low Earth orbit satellite to geosynchronous communications and planetary exploration. The payoff of high performance bipropellant systems is illustrated by the fact that Aerojet Redmond has qualified a commercial NTO/MMH engine based on the high Isp technology recently delivered by this program. They are now qualifying a NTO/hydrazine version of this engine. The advanced rhenium thrust chambers recently provided by this program have raised the performance of earth storable propellants from 315 sec to 328 sec of specific impulse. The recently introduced rhenium technology is the first new technology introduced to satellite propulsion in 30 years. Typically, the lead time required to develop and qualify new chemical thruster technology is not compatible with program development schedules. These technology development programs must be supported by a long term, Base R&T Program, if the technology s to be matured. This technology program then addresses the need for high performance, storable, on-board chemical propulsion for planetary rendezvous and descent/ascent. The primary NASA customer for this technology is Space Science, which identifies this need for such programs as Mars Surface Return, Titan Explorer, Neptune Orbiter, and Europa Lander. High performance (390 sec) chemical propulsion is estimated to add 105% payload to the Mars Sample Return mission or alternatively reduce the launch mass by 33%. In many cases, the use of existing (flight heritage) propellant technology is accommodated by reducing mission objectives and/or increasing enroute travel times sacrificing the science value per unit cost of the program. Therefore, a high performance storable thruster utilizing fluorinated oxidizers with hydrazine is being developed.

WOMBAT: A Scalable and High-performance Astrophysical Magnetohydrodynamics Code

Energy Technology Data Exchange (ETDEWEB)

Mendygral, P. J.; Radcliffe, N.; Kandalla, K. [Cray Inc., St. Paul, MN 55101 (United States); Porter, D. [Minnesota Supercomputing Institute for Advanced Computational Research, Minneapolis, MN USA (United States); O’Neill, B. J.; Nolting, C.; Donnert, J. M. F.; Jones, T. W. [School of Physics and Astronomy, University of Minnesota, Minneapolis, MN 55455 (United States); Edmon, P., E-mail: pjm@cray.com, E-mail: nradclif@cray.com, E-mail: kkandalla@cray.com, E-mail: oneill@astro.umn.edu, E-mail: nolt0040@umn.edu, E-mail: donnert@ira.inaf.it, E-mail: twj@umn.edu, E-mail: dhp@umn.edu, E-mail: pedmon@cfa.harvard.edu [Institute for Theory and Computation, Center for Astrophysics, Harvard University, Cambridge, MA 02138 (United States)

2017-02-01

We present a new code for astrophysical magnetohydrodynamics specifically designed and optimized for high performance and scaling on modern and future supercomputers. We describe a novel hybrid OpenMP/MPI programming model that emerged from a collaboration between Cray, Inc. and the University of Minnesota. This design utilizes MPI-RMA optimized for thread scaling, which allows the code to run extremely efficiently at very high thread counts ideal for the latest generation of multi-core and many-core architectures. Such performance characteristics are needed in the era of “exascale” computing. We describe and demonstrate our high-performance design in detail with the intent that it may be used as a model for other, future astrophysical codes intended for applications demanding exceptional performance.

WOMBAT: A Scalable and High-performance Astrophysical Magnetohydrodynamics Code

International Nuclear Information System (INIS)

Mendygral, P. J.; Radcliffe, N.; Kandalla, K.; Porter, D.; O’Neill, B. J.; Nolting, C.; Donnert, J. M. F.; Jones, T. W.; Edmon, P.

2017-01-01

We present a new code for astrophysical magnetohydrodynamics specifically designed and optimized for high performance and scaling on modern and future supercomputers. We describe a novel hybrid OpenMP/MPI programming model that emerged from a collaboration between Cray, Inc. and the University of Minnesota. This design utilizes MPI-RMA optimized for thread scaling, which allows the code to run extremely efficiently at very high thread counts ideal for the latest generation of multi-core and many-core architectures. Such performance characteristics are needed in the era of “exascale” computing. We describe and demonstrate our high-performance design in detail with the intent that it may be used as a model for other, future astrophysical codes intended for applications demanding exceptional performance.

High resolution micro-CT of low attenuating organic materials using large area photon-counting detector

Czech Academy of Sciences Publication Activity Database

Kumpová, Ivana; Vavřík, Daniel; Fíla, Tomáš; Koudelka_ml., Petr; Jandejsek, Ivan; Jakůbek, Jan; Kytýř, Daniel; Zlámal, Petr; Vopálenský, Michal; Gantar, A.

2016-01-01

Roč. 11, č. 2 (2016), č. článku C02003. ISSN 1748-0221 R&D Projects: GA MŠk(CZ) LO1219 Keywords : computerized tomography (CT) * computed radiography (CR) * pixelated detectors and associated VLSI electronics Subject RIV: AL - Art, Architecture, Cultural Heritage Impact factor: 1.220, year: 2016 http://iopscience.iop.org/article/10.1088/1748-0221/11/02/C02003

Computational Biology and High Performance Computing 2000

Energy Technology Data Exchange (ETDEWEB)

Simon, Horst D.; Zorn, Manfred D.; Spengler, Sylvia J.; Shoichet, Brian K.; Stewart, Craig; Dubchak, Inna L.; Arkin, Adam P.

2000-10-19

The pace of extraordinary advances in molecular biology has accelerated in the past decade due in large part to discoveries coming from genome projects on human and model organisms. The advances in the genome project so far, happening well ahead of schedule and under budget, have exceeded any dreams by its protagonists, let alone formal expectations. Biologists expect the next phase of the genome project to be even more startling in terms of dramatic breakthroughs in our understanding of human biology, the biology of health and of disease. Only today can biologists begin to envision the necessary experimental, computational and theoretical steps necessary to exploit genome sequence information for its medical impact, its contribution to biotechnology and economic competitiveness, and its ultimate contribution to environmental quality. High performance computing has become one of the critical enabling technologies, which will help to translate this vision of future advances in biology into reality. Biologists are increasingly becoming aware of the potential of high performance computing. The goal of this tutorial is to introduce the exciting new developments in computational biology and genomics to the high performance computing community.

Control switching in high performance and fault tolerant control

DEFF Research Database (Denmark)

Niemann, Hans Henrik; Poulsen, Niels Kjølstad

2010-01-01

The problem of reliability in high performance control and in fault tolerant control is considered in this paper. A feedback controller architecture for high performance and fault tolerance is considered. The architecture is based on the Youla-Jabr-Bongiorno-Kucera (YJBK) parameterization. By usi...

Design and Implementation of High-Performance GIS Dynamic Objects Rendering Engine

Science.gov (United States)

Zhong, Y.; Wang, S.; Li, R.; Yun, W.; Song, G.

2017-12-01

Spatio-temporal dynamic visualization is more vivid than static visualization. It important to use dynamic visualization techniques to reveal the variation process and trend vividly and comprehensively for the geographical phenomenon. To deal with challenges caused by dynamic visualization of both 2D and 3D spatial dynamic targets, especially for different spatial data types require high-performance GIS dynamic objects rendering engine. The main approach for improving the rendering engine with vast dynamic targets relies on key technologies of high-performance GIS, including memory computing, parallel computing, GPU computing and high-performance algorisms. In this study, high-performance GIS dynamic objects rendering engine is designed and implemented for solving the problem based on hybrid accelerative techniques. The high-performance GIS rendering engine contains GPU computing, OpenGL technology, and high-performance algorism with the advantage of 64-bit memory computing. It processes 2D, 3D dynamic target data efficiently and runs smoothly with vast dynamic target data. The prototype system of high-performance GIS dynamic objects rendering engine is developed based SuperMap GIS iObjects. The experiments are designed for large-scale spatial data visualization, the results showed that the high-performance GIS dynamic objects rendering engine have the advantage of high performance. Rendering two-dimensional and three-dimensional dynamic objects achieve 20 times faster on GPU than on CPU.

High-performance carbon nanotube-reinforced bioplastic

CSIR Research Space (South Africa)

Ramontja, J

2009-12-01

Full Text Available -1 High-Performance Carbon Nanotube-Reinforced Bioplastic 1. James Ramontja1,2, 2. Suprakas Sinha Ray1,*, 3. Sreejarani K. Pillai1, 4. Adriaan S. Luyt2 1. 1 DST/CSIR Nanotechnology Innovation Centre, National Centre for Nano-Structured Materials...

High-Performance Liquid Chromatography-Mass Spectrometry.

Science.gov (United States)

Vestal, Marvin L.

1984-01-01

Reviews techniques for online coupling of high-performance liquid chromatography with mass spectrometry, emphasizing those suitable for application to nonvolatile samples. Also summarizes the present status, strengths, and weaknesses of various techniques and discusses potential applications of recently developed techniques for combined liquid…

High performance cloud auditing and applications

CERN Document Server

Choi, Baek-Young; Song, Sejun

2014-01-01

This book mainly focuses on cloud security and high performance computing for cloud auditing. The book discusses emerging challenges and techniques developed for high performance semantic cloud auditing, and presents the state of the art in cloud auditing, computing and security techniques with focus on technical aspects and feasibility of auditing issues in federated cloud computing environments.   In summer 2011, the United States Air Force Research Laboratory (AFRL) CyberBAT Cloud Security and Auditing Team initiated the exploration of the cloud security challenges and future cloud auditing research directions that are covered in this book. This work was supported by the United States government funds from the Air Force Office of Scientific Research (AFOSR), the AFOSR Summer Faculty Fellowship Program (SFFP), the Air Force Research Laboratory (AFRL) Visiting Faculty Research Program (VFRP), the National Science Foundation (NSF) and the National Institute of Health (NIH). All chapters were partially suppor...

High-performance scientific computing in the cloud

Science.gov (United States)

Jorissen, Kevin; Vila, Fernando; Rehr, John

2011-03-01

Cloud computing has the potential to open up high-performance computational science to a much broader class of researchers, owing to its ability to provide on-demand, virtualized computational resources. However, before such approaches can become commonplace, user-friendly tools must be developed that hide the unfamiliar cloud environment and streamline the management of cloud resources for many scientific applications. We have recently shown that high-performance cloud computing is feasible for parallelized x-ray spectroscopy calculations. We now present benchmark results for a wider selection of scientific applications focusing on electronic structure and spectroscopic simulation software in condensed matter physics. These applications are driven by an improved portable interface that can manage virtual clusters and run various applications in the cloud. We also describe a next generation of cluster tools, aimed at improved performance and a more robust cluster deployment. Supported by NSF grant OCI-1048052.

High-performance phase-field modeling

KAUST Repository

Vignal, Philippe; Sarmiento, Adel; Cortes, Adriano Mauricio; Dalcin, L.; Collier, N.; Calo, Victor M.

2015-01-01

and phase-field crystal equation will be presented, which corroborate the theoretical findings, and illustrate the robustness of the method. Results related to more challenging examples, namely the Navier-Stokes Cahn-Hilliard and a diusion-reaction Cahn-Hilliard system, will also be presented. The implementation was done in PetIGA and PetIGA-MF, high-performance Isogeometric Analysis frameworks [1, 3], designed to handle non-linear, time-dependent problems.

Multi-petascale highly efficient parallel supercomputer

Science.gov (United States)

Asaad, Sameh; Bellofatto, Ralph E.; Blocksome, Michael A.; Blumrich, Matthias A.; Boyle, Peter; Brunheroto, Jose R.; Chen, Dong; Cher, Chen -Yong; Chiu, George L.; Christ, Norman; Coteus, Paul W.; Davis, Kristan D.; Dozsa, Gabor J.; Eichenberger, Alexandre E.; Eisley, Noel A.; Ellavsky, Matthew R.; Evans, Kahn C.; Fleischer, Bruce M.; Fox, Thomas W.; Gara, Alan; Giampapa, Mark E.; Gooding, Thomas M.; Gschwind, Michael K.; Gunnels, John A.; Hall, Shawn A.; Haring, Rudolf A.; Heidelberger, Philip; Inglett, Todd A.; Knudson, Brant L.; Kopcsay, Gerard V.; Kumar, Sameer; Mamidala, Amith R.; Marcella, James A.; Megerian, Mark G.; Miller, Douglas R.; Miller, Samuel J.; Muff, Adam J.; Mundy, Michael B.; O'Brien, John K.; O'Brien, Kathryn M.; Ohmacht, Martin; Parker, Jeffrey J.; Poole, Ruth J.; Ratterman, Joseph D.; Salapura, Valentina; Satterfield, David L.; Senger, Robert M.; Smith, Brian; Steinmacher-Burow, Burkhard; Stockdell, William M.; Stunkel, Craig B.; Sugavanam, Krishnan; Sugawara, Yutaka; Takken, Todd E.; Trager, Barry M.; Van Oosten, James L.; Wait, Charles D.; Walkup, Robert E.; Watson, Alfred T.; Wisniewski, Robert W.; Wu, Peng

2015-07-14

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

Highly segmented large-area hybrid photodiodes with bialkali photocathodes and enclosed VLSI readout electronics

CERN Document Server

Braem, André; Filthaut, Frank; Go, A; Joram, C; Weilhammer, Peter; Wicht, P; Dulinski, W; Séguinot, Jacques; Wenzel, H; Ypsilantis, Thomas

2000-01-01

We report on the principles, design, fabrication, and operation of a highly segmented, large-area hybrid photodiode, which is being developed in the framework of the LHCb RICH project. The device consists of a cylindrical, 127 mm diameter vacuum envelope capped with a spherical borosilicate UV-glass entrance window, with an active-to-total-area fraction of 81A fountain-focusing electron optics is used to demagnify the image onto a 50 mm diameter silicon sensor, containing 2048 pads of size 1*1 mm/sup 2/. (10 refs).

High-calorie food-cues impair working memory performance in high and low food cravers.

Science.gov (United States)

Meule, Adrian; Skirde, Ann Kathrin; Freund, Rebecca; Vögele, Claus; Kübler, Andrea

2012-10-01

The experience of food craving can lead to cognitive impairments. Experimentally induced chocolate craving exhausts cognitive resources and, therefore, impacts working memory, particularly in trait chocolate cravers. In the current study, we investigated the effects of exposure to food-cues on working memory task performance in a group with frequent and intense (high cravers, n=28) and less pronounced food cravings (low cravers, n=28). Participants performed an n-back task that contained either pictures of high-calorie sweets, high-calorie savory foods, or neutral objects. Current subjective food craving was assessed before and after the task. All participants showed slower reaction times and made more omission errors in response to food-cues, particularly savory foods. There were no differences in task performance between groups. State cravings did not differ between groups before the task, but increased more in high cravers compared to low cravers during the task. Results support findings about food cravings impairing visuo-spatial working memory performance independent of trait cravings. They further show that this influence is not restricted to chocolate, but also applies to high-calorie savory foods. Limiting working memory capacity may be especially crucial in persons who are more prone to high-calorie food-cues and experience such cravings habitually. Copyright © 2012 Elsevier Ltd. All rights reserved.

High-performance noncontact thermal diode via asymmetric nanostructures

Science.gov (United States)

Shen, Jiadong; Liu, Xianglei; He, Huan; Wu, Weitao; Liu, Baoan

2018-05-01

Electric diodes, though laying the foundation of modern electronics and information processing industries, suffer from ineffectiveness and even failure at high temperatures. Thermal diodes are promising alternatives to relieve above limitations, but usually possess low rectification ratios, and how to obtain a high-performance thermal rectification effect is still an open question. This paper proposes an efficient contactless thermal diode based on the near-field thermal radiation of asymmetric doped silicon nanostructures. The rectification ratio computed via exact scattering theories is demonstrated to be as high as 10 at a nanoscale gap distance and period, outperforming the counterpart flat-plate diode by more than one order of magnitude. This extraordinary performance mainly lies in the higher forward and lower reverse radiative heat flux within the low frequency band compared with the counterpart flat-plate diode, which is caused by a lower loss and smaller cut-off wavevector of nanostructures for the forward and reversed scheme, respectively. This work opens new routes to realize high performance thermal diodes, and may have wide applications in efficient thermal computing, thermal information processing, and thermal management.

High Performance Computing Modernization Program Kerberos Throughput Test Report

Science.gov (United States)

2017-10-26

Naval Research Laboratory Washington, DC 20375-5320 NRL/MR/5524--17-9751 High Performance Computing Modernization Program Kerberos Throughput Test ...NUMBER 5d. PROJECT NUMBER 5e. TASK NUMBER 5f. WORK UNIT NUMBER 2. REPORT TYPE1. REPORT DATE (DD-MM-YYYY) 4. TITLE AND SUBTITLE 6. AUTHOR(S) 8. PERFORMING...PAGE 18. NUMBER OF PAGES 17. LIMITATION OF ABSTRACT High Performance Computing Modernization Program Kerberos Throughput Test Report Daniel G. Gdula* and

High performance computing on vector systems

CERN Document Server

Roller, Sabine

2008-01-01

Presents the developments in high-performance computing and simulation on modern supercomputer architectures. This book covers trends in hardware and software development in general and specifically the vector-based systems and heterogeneous architectures. It presents innovative fields like coupled multi-physics or multi-scale simulations.

A new high performance current transducer

International Nuclear Information System (INIS)

Tang Lijun; Lu Songlin; Li Deming

2003-01-01

A DC-100 kHz current transducer is developed using a new technique on zero-flux detecting principle. It was shown that the new current transducer is of high performance, its magnetic core need not be selected very stringently, and it is easy to manufacture

High-definition television evaluation for remote handling task performance

International Nuclear Information System (INIS)

Fujita, Y.; Omori, E.; Hayashi, S.; Draper, J.V.; Herndon, J.N.

1986-01-01

In a plant that employs remote handling techniques for equipment maintenance, operators perform maintenance tasks primarily by using the information from television systems. The efficiency of the television system has a significant impact on remote maintenance task performance. High-definition television (HDTV) transmits a video image with more than twice the number of horizontal scan lines as standard-resolution television (1125 for HDTV to 525 for standard-resolution NTSC television). The added scan lines dramatically improve the resolution of images on the HDTV monitors. This paper describes experiments designed to evaluate the impact of HDTV on the performance of typical remote tasks. The experiments described in this paper compared the performance of four operators using HDTV with their performance while using other television systems. The experiments included four television systems: (a) high-definition color television, (b) high-definition monochromatic television, (c) standard-resolution monochromatic television, and (d) standard-resolution stereoscopic monochromatic television

High Performance Work Systems for Online Education

Science.gov (United States)

Contacos-Sawyer, Jonna; Revels, Mark; Ciampa, Mark

2010-01-01

The purpose of this paper is to identify the key elements of a High Performance Work System (HPWS) and explore the possibility of implementation in an online institution of higher learning. With the projected rapid growth of the demand for online education and its importance in post-secondary education, providing high quality curriculum, excellent…

Performance concerns for high duty fuel cycle

International Nuclear Information System (INIS)

Esposito, V.J.; Gutierrez, J.E.

1999-01-01

One of the goals of the nuclear industry is to achieve economic performance such that nuclear power plants are competitive in a de-regulated market. The manner in which nuclear fuel is designed and operated lies at the heart of economic viability. In this sense reliability, operating flexibility and low costs are the three major requirements of the NPP today. The translation of these three requirements to the design is part of our work. The challenge today is to produce a fuel design which will operate with long operating cycles, high discharge burnup, power up-rating and while still maintaining all design and safety margins. European Fuel Group (EFG) understands that to achieve the required performance high duty/energy fuel designs are needed. The concerns for high duty design includes, among other items, core design methods, advanced Safety Analysis methodologies, performance models, advanced material and operational strategies. The operational aspects require the trade-off and evaluation of various parameters including coolant chemistry control, material corrosion, boiling duty, boron level impacts, etc. In this environment MAEF is the design that EFG is now offering based on ZIRLO alloy and a robust skeleton. This new design is able to achieve 70 GWd/tU and Lead Test Programs are being executed to demonstrate this capability. A number of performance issues which have been a concern with current designs have been resolved such as cladding corrosion and incomplete RCCA insertion (IRI). As the core duty becomes more aggressive other new issues need to be addressed such as Axial Offset Anomaly. These new issues are being addressed by combination of the new design in concert with advanced methodologies to meet the demanding needs of NPP. The ability and strategy to meet high duty core requirements, flexibility of operation and maintain acceptable balance of all technical issues is the discussion in this paper. (authors)

High performance separation of lanthanides and actinides

International Nuclear Information System (INIS)

Sivaraman, N.; Vasudeva Rao, P.R.

2011-01-01

The major advantage of High Performance Liquid Chromatography (HPLC) is its ability to provide rapid and high performance separations. It is evident from Van Deemter curve for particle size versus resolution that packing materials with particle sizes less than 2 μm provide better resolution for high speed separations and resolving complex mixtures compared to 5 μm based supports. In the recent past, chromatographic support material using monolith has been studied extensively at our laboratory. Monolith column consists of single piece of porous, rigid material containing mesopores and micropores, which provide fast analyte mass transfer. Monolith support provides significantly higher separation efficiency than particle-packed columns. A clear advantage of monolith is that it could be operated at higher flow rates but with lower back pressure. Higher operating flow rate results in higher column permeability, which drastically reduces analysis time and provides high separation efficiency. The above developed fast separation methods were applied to assay the lanthanides and actinides from the dissolver solutions of nuclear reactor fuels

High rate response of ultra-high-performance fiber-reinforced concretes under direct tension

Energy Technology Data Exchange (ETDEWEB)

Tran, Ngoc Thanh [Department of Civil and Environmental Engineering, Sejong University, 98 Gunja-Dong, Gwangjin-Gu, Seoul 143-747 (Korea, Republic of); Tran, Tuan Kiet [Department of Civil and Environmental Engineering, Sejong University, 98 Gunja-Dong, Gwangjin-Gu, Seoul 143-747 (Korea, Republic of); Department of Civil Engineering and Applied Mechanics, Ho Chi Minh City University of Technology and Education, 01 Vo Van Ngan, Thu Duc District, Ho Chi Minh City (Viet Nam); Kim, Dong Joo, E-mail: djkim75@sejong.ac.kr [Department of Civil and Environmental Engineering, Sejong University, 98 Gunja-Dong, Gwangjin-Gu, Seoul 143-747 (Korea, Republic of)

2015-03-15

The tensile response of ultra-high-performance fiber-reinforced concretes (UHPFRCs) at high strain rates (5–24 s{sup −} {sup 1}) was investigated. Three types of steel fibers, including twisted, long and short smooth steel fibers, were added by 1.5% volume content in an ultra high performance concrete (UHPC) with a compressive strength of 180 MPa. Two different cross sections, 25 × 25 and 25 × 50 mm{sup 2}, of tensile specimens were used to investigate the effect of the cross section area on the measured tensile response of UHPFRCs. Although all the three fibers generated strain hardening behavior even at high strain rates, long smooth fibers produced the highest tensile resistance at high rates whereas twisted fiber did at static rate. The breakages of twisted fibers were observed from the specimens tested at high strain rates unlike smooth steel fibers. The tensile behavior of UHPFRCs at high strain rates was clearly influenced by the specimen size, especially in post-cracking strength.

Turbostratic stacked CVD graphene for high-performance devices

Science.gov (United States)

Uemura, Kohei; Ikuta, Takashi; Maehashi, Kenzo

2018-03-01

We have fabricated turbostratic stacked graphene with high-transport properties by the repeated transfer of CVD monolayer graphene. The turbostratic stacked CVD graphene exhibited higher carrier mobility and conductivity than CVD monolayer graphene. The electron mobility for the three-layer turbostratic stacked CVD graphene surpassed 10,000 cm2 V-1 s-1 at room temperature, which is five times greater than that for CVD monolayer graphene. The results indicate that the high performance is derived from maintenance of the linear band dispersion, suppression of the carrier scattering, and parallel conduction. Therefore, turbostratic stacked CVD graphene is a superior material for high-performance devices.

High performance parallel computers for science

International Nuclear Information System (INIS)

Nash, T.; Areti, H.; Atac, R.; Biel, J.; Cook, A.; Deppe, J.; Edel, M.; Fischler, M.; Gaines, I.; Hance, R.

1989-01-01

This paper reports that Fermilab's Advanced Computer Program (ACP) has been developing cost effective, yet practical, parallel computers for high energy physics since 1984. The ACP's latest developments are proceeding in two directions. A Second Generation ACP Multiprocessor System for experiments will include $3500 RISC processors each with performance over 15 VAX MIPS. To support such high performance, the new system allows parallel I/O, parallel interprocess communication, and parallel host processes. The ACP Multi-Array Processor, has been developed for theoretical physics. Each $4000 node is a FORTRAN or C programmable pipelined 20 Mflops (peak), 10 MByte single board computer. These are plugged into a 16 port crossbar switch crate which handles both inter and intra crate communication. The crates are connected in a hypercube. Site oriented applications like lattice gauge theory are supported by system software called CANOPY, which makes the hardware virtually transparent to users. A 256 node, 5 GFlop, system is under construction

High performance MEAs. Final report

Energy Technology Data Exchange (ETDEWEB)

NONE

2012-07-15

The aim of the present project is through modeling, material and process development to obtain significantly better MEA performance and to attain the technology necessary to fabricate stable catalyst materials thereby providing a viable alternative to current industry standard. This project primarily focused on the development and characterization of novel catalyst materials for the use in high temperature (HT) and low temperature (LT) proton-exchange membrane fuel cells (PEMFC). New catalysts are needed in order to improve fuel cell performance and reduce the cost of fuel cell systems. Additional tasks were the development of new, durable sealing materials to be used in PEMFC as well as the computational modeling of heat and mass transfer processes, predominantly in LT PEMFC, in order to improve fundamental understanding of the multi-phase flow issues and liquid water management in fuel cells. An improved fundamental understanding of these processes will lead to improved fuel cell performance and hence will also result in a reduced catalyst loading to achieve the same performance. The consortium have obtained significant research results and progress for new catalyst materials and substrates with promising enhanced performance and fabrication of the materials using novel methods. However, the new materials and synthesis methods explored are still in the early research and development phase. The project has contributed to improved MEA performance using less precious metal and has been demonstrated for both LT-PEM, DMFC and HT-PEM applications. New novel approach and progress of the modelling activities has been extremely satisfactory with numerous conference and journal publications along with two potential inventions concerning the catalyst layer. (LN)

Silicon microstrip detector development in the Institute for High Energy Physics Zeuthen, GDR

International Nuclear Information System (INIS)

Lange, W.; Nowak, W.D.; Truetzschler, K.

1990-01-01

This paper reports that in regard of the growing interest to study short living particles demanding for high resolution vertex detectors the authors started to build Si microstrip detectors. The first detector generation was characterized by a small area of silicon and a readout via printed circuit board fan out. Now they can assemble detectors with larger areas and VLSI readout. A special cleanroom has been built. Equipment and tools necessary are available. Silicon wafers and thick film hybrid circuits are fabricated under collaboration by the GDR industry. Applications of their detectors were several test-runs at CERN to calibrate the L3 time expansion chamber (TEC) and the L3 muon chambers. A 10-layer telescope is designed now and it is planned to calibrate a high resolution scintillation fiber target. Future applications will be high resolution vertex detectors, e.g. L3 upgrading (LEP, CERN) or KEDR (VEPP-5, Novosibirsk). Further investigations will concern AC coupled strip detectors (single and double sided) and pixel and/or pad detectors

Technical Training: ELEC-2005: Electronics in High Energy Physics

CERN Multimedia

Monique Duval

2005-01-01

CERN Technical Training 2005: Learning for the LHC! ELEC-2005: Electronics in High Energy Physics - Spring Term ELEC-2005 is a new course series on modern electronics, given by CERN physicists and engineers within the framework of the 2005 Technical Training Programme, in an extended format of the successful ELEC-2002 course series. This comprehensive course series is designed for people who are not electronics specialists, for example physicists, engineers and technicians working at or visiting the laboratory, who use or will use electronics in their present or future activities, in particular in the context of the LHC accelerator and experiments. ELEC-2005 is composed of four Terms: the Winter Term, Introduction to electronics in HEP, already took place; the next three Terms will run throughout the year: Spring Term: Integrated circuits and VLSI technology for physics (March, 6 lectures) - now open for registration Summer Term: System electronics for physics: Issues (May, 7 lectures) Autumn Term: Ele...

Optical Thermal Characterization Enables High-Performance Electronics Applications

Energy Technology Data Exchange (ETDEWEB)

2016-02-01

NREL developed a modeling and experimental strategy to characterize thermal performance of materials. The technique provides critical data on thermal properties with relevance for electronics packaging applications. Thermal contact resistance and bulk thermal conductivity were characterized for new high-performance materials such as thermoplastics, boron-nitride nanosheets, copper nanowires, and atomically bonded layers. The technique is an important tool for developing designs and materials that enable power electronics packaging with small footprint, high power density, and low cost for numerous applications.

Visualization and Data Analysis for High-Performance Computing

Energy Technology Data Exchange (ETDEWEB)

Sewell, Christopher Meyer [Los Alamos National Lab. (LANL), Los Alamos, NM (United States)

2016-09-27

This is a set of slides from a guest lecture for a class at the University of Texas, El Paso on visualization and data analysis for high-performance computing. The topics covered are the following: trends in high-performance computing; scientific visualization, such as OpenGL, ray tracing and volume rendering, VTK, and ParaView; data science at scale, such as in-situ visualization, image databases, distributed memory parallelism, shared memory parallelism, VTK-m, "big data", and then an analysis example.

Designing a High Performance Parallel Personal Cluster

OpenAIRE

Kapanova, K. G.; Sellier, J. M.

2016-01-01

Today, many scientific and engineering areas require high performance computing to perform computationally intensive experiments. For example, many advances in transport phenomena, thermodynamics, material properties, computational chemistry and physics are possible only because of the availability of such large scale computing infrastructures. Yet many challenges are still open. The cost of energy consumption, cooling, competition for resources have been some of the reasons why the scientifi...

High Performance Home Building Guide for Habitat for Humanity Affiliates

Energy Technology Data Exchange (ETDEWEB)

Lindsey Marburger

2010-10-01

This guide covers basic principles of high performance Habitat construction, steps to achieving high performance Habitat construction, resources to help improve building practices, materials, etc., and affiliate profiles and recommendations.

Progress on high-performance rapid prototype aluminum mirrors

Science.gov (United States)

Woodard, Kenneth S.; Myrick, Bruce H.

2017-05-01

Near net shape parts can be produced using some very old processes (investment casting) and the relatively new direct metal laser sintering (DMLS) process. These processes have significant advantages for complex blank lightweighting and costs but are not inherently suited for producing high performance mirrors. The DMLS process can provide extremely complex lightweight structures but the high residual stresses left in the material results in unstable mirror figure retention. Although not to the extreme intricacy of DMLS, investment casting can also provide complex lightweight structures at considerably lower costs than DMLS and even conventional wrought mirror blanks but the less than 100% density for casting (and also DMLS) limits finishing quality. This paper will cover the progress that has been made to make both the DMLS and investment casting processes into viable near net shape blank options for high performance aluminum mirrors. Finish and figure results will be presented to show performance commensurate with existing conventional processes.

Porous Graphene Microflowers for High-Performance Microwave Absorption

Science.gov (United States)

Chen, Chen; Xi, Jiabin; Zhou, Erzhen; Peng, Li; Chen, Zichen; Gao, Chao

2018-06-01

Graphene has shown great potential in microwave absorption (MA) owing to its high surface area, low density, tunable electrical conductivity and good chemical stability. To fully realize graphene's MA ability, the microstructure of graphene should be carefully addressed. Here we prepared graphene microflowers (Gmfs) with highly porous structure for high-performance MA filler material. The efficient absorption bandwidth (reflection loss ≤ -10 dB) reaches 5.59 GHz and the minimum reflection loss is up to -42.9 dB, showing significant increment compared with stacked graphene. Such performance is higher than most graphene-based materials in the literature. Besides, the low filling content (10 wt%) and low density (40-50 mg cm-3) are beneficial for the practical applications. Without compounding with magnetic materials or conductive polymers, Gmfs show outstanding MA performance with the aid of rational microstructure design. Furthermore, Gmfs exhibit advantages in facile processibility and large-scale production compared with other porous graphene materials including aerogels and foams.

High performance sealing - meeting nuclear and aerospace requirements

International Nuclear Information System (INIS)

Wensel, R.; Metcalfe, R.

1994-11-01

Although high performance sealing is required in many places, two industries lead all others in terms of their demand-nuclear and aerospace. The factors that govern the high reliability and integrity of seals, particularly elastomer seals, for both industries are discussed. Aerospace requirements include low structural weight and a broad range of conditions, from the cold vacuum of space to the hot, high pressures of rocket motors. It is shown, by example, how a seal can be made an integral part of a structure in order to improve performance, rather than using a conventional handbook design. Typical processes are then described for selection, specification and procurement of suitable elastomers, functional and accelerated performance testing, database development and service-life prediction. Methods for quality assurance of elastomer seals are summarized. Potentially catastrophic internal dejects are a particular problem for conventional non-destructive inspection techniques. A new method of elastodynamic testing for these is described. (author)

System-Level Modeling and Synthesis Techniques for Flow-Based Microfluidic Very Large Scale Integration Biochips

DEFF Research Database (Denmark)

Minhass, Wajid Hassan

Microfluidic biochips integrate different biochemical analysis functionalities on-chip and offer several advantages over the conventional biochemical laboratories. In this thesis, we focus on the flow-based biochips. The basic building block of such a chip is a valve which can be fabricated at very...... propose a framework for mapping the biochemical applications onto the mVLSI biochips, binding and scheduling the operations and performing fluid routing. A control synthesis framework for determining the exact valve activation sequence required to execute the application is also proposed. In order...... to reduce the macro-assembly around the chip and enhance chip scalability, we propose an approach for the biochip pin count minimization. We also propose a throughput maximization scheme for the cell culture mVLSI biochips, saving time and reducing costs. We have extensively evaluated the proposed...

Building Trust in High-Performing Teams

Directory of Open Access Journals (Sweden)

Aki Soudunsaari

2012-06-01

Full Text Available Facilitation of growth is more about good, trustworthy contacts than capital. Trust is a driving force for business creation, and to create a global business you need to build a team that is capable of meeting the challenge. Trust is a key factor in team building and a needed enabler for cooperation. In general, trust building is a slow process, but it can be accelerated with open interaction and good communication skills. The fast-growing and ever-changing nature of global business sets demands for cooperation and team building, especially for startup companies. Trust building needs personal knowledge and regular face-to-face interaction, but it also requires empathy, respect, and genuine listening. Trust increases communication, and rich and open communication is essential for the building of high-performing teams. Other building materials are a shared vision, clear roles and responsibilities, willingness for cooperation, and supporting and encouraging leadership. This study focuses on trust in high-performing teams. It asks whether it is possible to manage trust and which tools and operation models should be used to speed up the building of trust. In this article, preliminary results from the authors’ research are presented to highlight the importance of sharing critical information and having a high level of communication through constant interaction.

JT-60U high performance regimes

International Nuclear Information System (INIS)

Ishida, S.

1999-01-01

High performance regimes of JT-60U plasmas are presented with an emphasis upon the results from the use of a semi-closed pumped divertor with W-shaped geometry. Plasma performance in transient and quasi steady states has been significantly improved in reversed shear and high- βp regimes. The reversed shear regime elevated an equivalent Q DT eq transiently up to 1.25 (n D (0)τ E T i (0)=8.6x10 20 m-3·s·keV) in a reactor-relevant thermonuclear dominant regime. Long sustainment of enhanced confinement with internal transport barriers (ITBs) with a fully non-inductive current drive in a reversed shear discharge was successfully demonstrated with LH wave injection. Performance sustainment has been extended in the high- bp regime with a high triangularity achieving a long sustainment of plasma conditions equivalent to Q DT eq ∼0.16 (n D (0)τ E T i (0)∼1.4x10 20 m -3 ·s·keV) for ∼4.5 s with a large non-inductive current drive fraction of 60-70% of the plasma current. Thermal and particle transport analyses show significant reduction of thermal and particle diffusivities around ITB resulting in a strong Er shear in the ITB region. The W-shaped divertor is effective for He ash exhaust demonstrating steady exhaust capability of τ He */τ E ∼3-10 in support of ITER. Suppression of neutral back flow and chemical sputtering effect have been observed while MARFE onset density is rather decreased. Negative-ion based neutral beam injection (N-NBI) experiments have created a clear H-mode transition. Enhanced ionization cross- section due to multi-step ionization processes was confirmed as theoretically predicted. A current density profile driven by N-NBI is measured in a good agreement with theoretical prediction. N-NBI induced TAE modes characterized as persistent and bursting oscillations have been observed from a low hot beta of h >∼0.1-0.2% without a significant loss of fast ions. (author)

High performance light-colored nitrile-butadiene rubber nanocomposites.

Science.gov (United States)

Lei, Yanda; Guo, Baochun; Chen, Feng; Zhu, Lixin; Zhou, Wenyou; Jia, Demin

2011-12-01

High mechanical performance nitrile-butadiene rubber (NBR) with light color was fabricated by the method of in situ formation of zinc disorbate (ZDS) or magnesium disorbate (MDS). The in situ formed ZDS and its polymerization via internal mixing was confirmed by X-ray diffaraction. The mechanical properties, ageing resistance, morphology and the dynamic mechanical analysis were fully studied. It was found that with increasing loading of metallic disorbate both the curing rate and the ionic crosslink density was largely increased. The modulus, tensile strength and tear strength were largely increased. With a comparison between internal mixing and opening mixing, the mechanical performance for the former one was obviously better than the latter one. The high performance was ascribed to the finely dispersion nano domains with irregular shape and obscure interfacial structures. Except for the NBR vulcanizate with a high loading of MDS, the others' ageing resistance with incorporation of these two metallic disorbate was found to be good. Dynamic mechanical analysis (DMA) showed that, with increasing loading of metallic disorbate, the highly increased storage modulus above -20 degrees C, the up-shifted glass transition temperature (Tg) and the reduced mechanical loss were ascribed to strengthened interfacial interactions.

High Performance Fiber Reinforced Cement Composites 6 HPFRCC 6

CERN Document Server

Reinhardt, Hans; Naaman, A

2012-01-01

High Performance Fiber Reinforced Cement Composites (HPFRCC) represent a class of cement composites whose stress-strain response in tension undergoes strain hardening behaviour accompanied by multiple cracking, leading to a high strain prior to failure. The primary objective of this International Workshop was to provide a compendium of up-to-date information on the most recent developments and research advances in the field of High Performance Fiber Reinforced Cement Composites. Approximately 65 contributions from leading world experts are assembled in these proceedings and provide an authoritative perspective on the subject. Special topics include fresh and hardening state properties; self-compacting mixtures; mechanical behavior under compressive, tensile, and shear loading; structural applications; impact, earthquake and fire resistance; durability issues; ultra-high performance fiber reinforced concrete; and textile reinforced concrete. Target readers: graduate students, researchers, fiber producers, desi...

Debugging a high performance computing program

Science.gov (United States)

Gooding, Thomas M.

2013-08-20

Methods, apparatus, and computer program products are disclosed for debugging a high performance computing program by gathering lists of addresses of calling instructions for a plurality of threads of execution of the program, assigning the threads to groups in dependence upon the addresses, and displaying the groups to identify defective threads.

Playa: High-Performance Programmable Linear Algebra

Directory of Open Access Journals (Sweden)

Victoria E. Howle

2012-01-01

Full Text Available This paper introduces Playa, a high-level user interface layer for composing algorithms for complex multiphysics problems out of objects from other Trilinos packages. Among other features, Playa provides very high-performance overloaded operators implemented through an expression template mechanism. In this paper, we give an overview of the central Playa objects from a user's perspective, show application to a sequence of increasingly complex solver algorithms, provide timing results for Playa's overloaded operators and other functions, and briefly survey some of the implementation issues involved.

High performance direct methanol fuel cell with thin electrolyte membrane

Science.gov (United States)

Wan, Nianfang

2017-06-01

A high performance direct methanol fuel cell is achieved with thin electrolyte membrane. 320 mW cm-2 of peak power density and over 260 mW cm-2 at 0.4 V are obtained when working at 90 °C with normal pressure air supply. It is revealed that the increased anode half-cell performance with temperature contributes primarily to the enhanced performance at elevated temperature. From the comparison of iR-compensated cathode potential of methanol/air with that of H2/air fuel cell, the impact of methanol crossover on cathode performance decreases with current density and becomes negligible at high current density. Current density is found to influence fuel efficiency and methanol crossover significantly from the measurement of fuel efficiency at different current density. At high current density, high fuel efficiency can be achieved even at high temperature, indicating decreased methanol crossover.

Analog circuit design designing high performance amplifiers

CERN Document Server

Feucht, Dennis

2010-01-01

The third volume Designing High Performance Amplifiers applies the concepts from the first two volumes. It is an advanced treatment of amplifier design/analysis emphasizing both wideband and precision amplification.

Distributed control software of high-performance control-loop algorithm

CERN Document Server

Blanc, D

1999-01-01

The majority of industrial cooling and ventilation plants require the control of complex processes. All these processes are highly important for the operation of the machines. The stability and reliability of these processes are leading factors identifying the quality of the service provided. The control system architecture and software structure, as well, are required to have high dynamical performance and robust behaviour. The intelligent systems based on PID or RST controllers are used for their high level of stability and accuracy. The design and tuning of these complex controllers require the dynamic model of the plant to be known (generally obtained by identification) and the desired performance of the various control loops to be specified for achieving good performances. The concept of having a distributed control algorithm software provides full automation facilities with well-adapted functionality and good performances, giving methodology, means and tools to master the dynamic process optimization an...

Optimizing the design of very high power, high performance converters

International Nuclear Information System (INIS)

Edwards, R.J.; Tiagha, E.A.; Ganetis, G.; Nawrocky, R.J.

1980-01-01

This paper describes how various technologies are used to achieve the desired performance in a high current magnet power converter system. It is hoped that the discussions of the design approaches taken will be applicable to other power supply systems where stringent requirements in stability, accuracy and reliability must be met

Laser additive manufacturing of high-performance materials

CERN Document Server

Gu, Dongdong

2015-01-01

This book entitled “Laser Additive Manufacturing of High-Performance Materials” covers the specific aspects of laser additive manufacturing of high-performance new materials components based on an unconventional materials incremental manufacturing philosophy, in terms of materials design and preparation, process control and optimization, and theories of physical and chemical metallurgy. This book describes the capabilities and characteristics of the development of new metallic materials components by laser additive manufacturing process, including nanostructured materials, in situ composite materials, particle reinforced metal matrix composites, etc. The topics presented in this book, similar as laser additive manufacturing technology itself, show a significant interdisciplinary feature, integrating laser technology, materials science, metallurgical engineering, and mechanical engineering. This is a book for researchers, students, practicing engineers, and manufacturing industry professionals interested i...

Monitoring SLAC High Performance UNIX Computing Systems

International Nuclear Information System (INIS)

Lettsome, Annette K.

2005-01-01

Knowledge of the effectiveness and efficiency of computers is important when working with high performance systems. The monitoring of such systems is advantageous in order to foresee possible misfortunes or system failures. Ganglia is a software system designed for high performance computing systems to retrieve specific monitoring information. An alternative storage facility for Ganglia's collected data is needed since its default storage system, the round-robin database (RRD), struggles with data integrity. The creation of a script-driven MySQL database solves this dilemma. This paper describes the process took in the creation and implementation of the MySQL database for use by Ganglia. Comparisons between data storage by both databases are made using gnuplot and Ganglia's real-time graphical user interface

Governing highly performing lean team behaviors : A mixed-methods longitudinal study

NARCIS (Netherlands)

Van Dun, Desirée H.; Wilderom, Celeste P.M.

2015-01-01

Work teams go through multiple performance cycles; initially highly performing teams may experience a decline in subsequent performance and vice-versa. This inductive study focuses on team-behavioral and contextual predictors of high lean team performance. Rooted in both the IMOI model and reviewing

Design study of a low-power, low-noise front-end for multianode silicon drift detectors

International Nuclear Information System (INIS)

Caponetto, L.; Presti, D. Lo; Randazzo, N.; Russo, G.V.; Leonora, E.; Lo Nigro, L.; Petta, C.; Reito, S.; Sipala, V.

2005-01-01

The read-out for Silicon Drift Detectors in the form of a VLSI chip is presented, with a view to applications in High Energy Physics and space experiments. It is characterised by extremely low power dissipation, small noise and size

Principals' Perceptions of Professional Development in High- and Low-Performing High-Poverty Schools

Science.gov (United States)

Moore, Sheila; Kochan, Frances

2013-01-01

This is the second part of a two-part study examining issues related to professional development in high-poverty schools. The findings from the initial study indicated that principals in high-poverty, high-performing schools perceived higher levels of implementation of quality professional development standards in their schools than did principals…

Neo4j high performance

CERN Document Server

Raj, Sonal

2015-01-01

If you are a professional or enthusiast who has a basic understanding of graphs or has basic knowledge of Neo4j operations, this is the book for you. Although it is targeted at an advanced user base, this book can be used by beginners as it touches upon the basics. So, if you are passionate about taming complex data with the help of graphs and building high performance applications, you will be able to get valuable insights from this book.

High performance APCS conceptual design and evaluation scoping study

International Nuclear Information System (INIS)

Soelberg, N.; Liekhus, K.; Chambers, A.; Anderson, G.

1998-02-01

This Air Pollution Control System (APCS) Conceptual Design and Evaluation study was conducted to evaluate a high-performance (APC) system for minimizing air emissions from mixed waste thermal treatment systems. Seven variations of high-performance APCS designs were conceptualized using several design objectives. One of the system designs was selected for detailed process simulation using ASPEN PLUS to determine material and energy balances and evaluate performance. Installed system capital costs were also estimated. Sensitivity studies were conducted to evaluate the incremental cost and benefit of added carbon adsorber beds for mercury control, specific catalytic reduction for NO x control, and offgas retention tanks for holding the offgas until sample analysis is conducted to verify that the offgas meets emission limits. Results show that the high-performance dry-wet APCS can easily meet all expected emission limits except for possibly mercury. The capability to achieve high levels of mercury control (potentially necessary for thermally treating some DOE mixed streams) could not be validated using current performance data for mercury control technologies. The engineering approach and ASPEN PLUS modeling tool developed and used in this study identified APC equipment and system performance, size, cost, and other issues that are not yet resolved. These issues need to be addressed in feasibility studies and conceptual designs for new facilities or for determining how to modify existing facilities to meet expected emission limits. The ASPEN PLUS process simulation with current and refined input assumptions and calculations can be used to provide system performance information for decision-making, identifying best options, estimating costs, reducing the potential for emission violations, providing information needed for waste flow analysis, incorporating new APCS technologies in existing designs, or performing facility design and permitting activities

BioCMOS Interfaces and Co-Design

CERN Document Server

Carrara, Sandro

2013-01-01

The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

A High Performance COTS Based Computer Architecture

Science.gov (United States)

Patte, Mathieu; Grimoldi, Raoul; Trautner, Roland

2014-08-01

Using Commercial Off The Shelf (COTS) electronic components for space applications is a long standing idea. Indeed the difference in processing performance and energy efficiency between radiation hardened components and COTS components is so important that COTS components are very attractive for use in mass and power constrained systems. However using COTS components in space is not straightforward as one must account with the effects of the space environment on the COTS components behavior. In the frame of the ESA funded activity called High Performance COTS Based Computer, Airbus Defense and Space and its subcontractor OHB CGS have developed and prototyped a versatile COTS based architecture for high performance processing. The rest of the paper is organized as follows: in a first section we will start by recapitulating the interests and constraints of using COTS components for space applications; then we will briefly describe existing fault mitigation architectures and present our solution for fault mitigation based on a component called the SmartIO; in the last part of the paper we will describe the prototyping activities executed during the HiP CBC project.

Management issues for high performance storage systems

Energy Technology Data Exchange (ETDEWEB)

Louis, S. [Lawrence Livermore National Lab., CA (United States); Burris, R. [Oak Ridge National Lab., TN (United States)

1995-03-01

Managing distributed high-performance storage systems is complex and, although sharing common ground with traditional network and systems management, presents unique storage-related issues. Integration technologies and frameworks exist to help manage distributed network and system environments. Industry-driven consortia provide open forums where vendors and users cooperate to leverage solutions. But these new approaches to open management fall short addressing the needs of scalable, distributed storage. We discuss the motivation and requirements for storage system management (SSM) capabilities and describe how SSM manages distributed servers and storage resource objects in the High Performance Storage System (HPSS), a new storage facility for data-intensive applications and large-scale computing. Modem storage systems, such as HPSS, require many SSM capabilities, including server and resource configuration control, performance monitoring, quality of service, flexible policies, file migration, file repacking, accounting, and quotas. We present results of initial HPSS SSM development including design decisions and implementation trade-offs. We conclude with plans for follow-on work and provide storage-related recommendations for vendors and standards groups seeking enterprise-wide management solutions.

High-performance nanostructured supercapacitors on a sponge

KAUST Repository

Chen, Wei

2011-12-14

A simple and scalable method has been developed to fabricate nanostructured MnO 2-carbon nanotube (CNT)-sponge hybrid electrodes. A novel supercapacitor, henceforth referred to as "sponge supercapacitor", has been fabricated using these hybrid electrodes with remarkable performance. A specific capacitance of 1230 F/g (based on the mass of MnO 2) can be reached. Capacitors based on CNT-sponge substrates (without MnO 2) can be operated even under a high scan rate of 200 V/s, and they exhibit outstanding cycle performance with only 2% degradation after 100000 cycles under a scan rate of 10 V/s. The MnO 2-CNT-sponge supercapacitors show only 4% of degradation after 10000 cycles at a charge-discharge specific current of 5 A/g. The specific power and energy of the MnO 2-CNT-sponge supercapacitors are high with values of 63 kW/kg and 31 Wh/kg, respectively. The attractive performances exhibited by these sponge supercapacitors make them potentially promising candidates for future energy storage systems. © 2011 American Chemical Society.

High Performance OLED Panel and Luminaire

Energy Technology Data Exchange (ETDEWEB)

Spindler, Jeffrey [OLEDWorks LLC, Rochester, NY (United States)

2017-02-20

In this project, OLEDWorks developed and demonstrated the technology required to produce OLED lighting panels with high energy efficiency and excellent light quality. OLED panels developed in this program produce high quality warm white light with CRI greater than 85 and efficacy up to 80 lumens per watt (LPW). An OLED luminaire employing 24 of the high performance panels produces practical levels of illumination for general lighting, with a flux of over 2200 lumens at 60 LPW. This is a significant advance in the state of the art for OLED solid-state lighting (SSL), which is expected to be a complementary light source to the more advanced LED SSL technology that is rapidly replacing all other traditional forms of lighting.

High-performance computing for airborne applications

International Nuclear Information System (INIS)

Quinn, Heather M.; Manuzatto, Andrea; Fairbanks, Tom; Dallmann, Nicholas; Desgeorges, Rose

2010-01-01

Recently, there has been attempts to move common satellite tasks to unmanned aerial vehicles (UAVs). UAVs are significantly cheaper to buy than satellites and easier to deploy on an as-needed basis. The more benign radiation environment also allows for an aggressive adoption of state-of-the-art commercial computational devices, which increases the amount of data that can be collected. There are a number of commercial computing devices currently available that are well-suited to high-performance computing. These devices range from specialized computational devices, such as field-programmable gate arrays (FPGAs) and digital signal processors (DSPs), to traditional computing platforms, such as microprocessors. Even though the radiation environment is relatively benign, these devices could be susceptible to single-event effects. In this paper, we will present radiation data for high-performance computing devices in a accelerated neutron environment. These devices include a multi-core digital signal processor, two field-programmable gate arrays, and a microprocessor. From these results, we found that all of these devices are suitable for many airplane environments without reliability problems.

Micromachined high-performance RF passives in CMOS substrate

International Nuclear Information System (INIS)

Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

2016-01-01

This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications. (topical review)

Strategies of high-performing paramedic educational programs.

Science.gov (United States)

Margolis, Gregg S; Romero, Gabriel A; Fernandez, Antonio R; Studnek, Jonathan R

2009-01-01

To identify the specific educational strategies used by paramedic educational programs that have attained consistently high success rates on the National Registry of Emergency Medical Technicians (NREMT) examination. NREMT data from 2003-2007 were analyzed to identify consistently high-performing paramedic educational programs. Representatives from 12 programs that have maintained a 75% first-attempt pass rate for at least four of five years and had more than 20 graduates per year were invited to participate in a focus group. Using the nominal group technique (NGT), participants were asked to answer the following question: "What are specific strategies that lead to a successful paramedic educational program?" All 12 emergency medical services (EMS) educational programs meeting the eligibility requirements participated. After completing the seven-step NGT process, 12 strategies were identified as leading to a successful paramedic educational program: 1) achieve and maintain national accreditation; 2) maintain high-level entry requirements and prerequisites; 3) provide students with a clear idea of expectations for student success; 4) establish a philosophy and foster a culture that values continuous review and improvement; 5) create your own examinations, lesson plans, presentations, and course materials using multiple current references; 6) emphasize emergency medical technician (EMT)-Basic concepts throughout the class; 7) use frequent case-based classroom scenarios; 8) expose students to as many prehospital advanced life support (ALS) patient contacts as possible, preferably where they are in charge; 9) create and administer valid examinations that have been through a review process (such as qualitative analysis); 10) provide students with frequent detailed feedback regarding their performance (such as formal examination reviews); 11) incorporate critical thinking and problem solving into all testing; and 12) deploy predictive testing with analysis prior to

High-Speed 3D Printing of High-Performance Thermosetting Polymers via Two-Stage Curing.

Science.gov (United States)

Kuang, Xiao; Zhao, Zeang; Chen, Kaijuan; Fang, Daining; Kang, Guozheng; Qi, Hang Jerry

2018-04-01

Design and direct fabrication of high-performance thermosets and composites via 3D printing are highly desirable in engineering applications. Most 3D printed thermosetting polymers to date suffer from poor mechanical properties and low printing speed. Here, a novel ink for high-speed 3D printing of high-performance epoxy thermosets via a two-stage curing approach is presented. The ink containing photocurable resin and thermally curable epoxy resin is used for the digital light processing (DLP) 3D printing. After printing, the part is thermally cured at elevated temperature to yield an interpenetrating polymer network epoxy composite, whose mechanical properties are comparable to engineering epoxy. The printing speed is accelerated by the continuous liquid interface production assisted DLP 3D printing method, achieving a printing speed as high as 216 mm h -1 . It is also demonstrated that 3D printing structural electronics can be achieved by combining the 3D printed epoxy composites with infilled silver ink in the hollow channels. The new 3D printing method via two-stage curing combines the attributes of outstanding printing speed, high resolution, low volume shrinkage, and excellent mechanical properties, and provides a new avenue to fabricate 3D thermosetting composites with excellent mechanical properties and high efficiency toward high-performance and functional applications. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A high-performance, low-cost, leading edge discriminator

Indian Academy of Sciences (India)

Abstract. A high-performance, low-cost, leading edge discriminator has been designed with a timing performance comparable to state-of-the-art, commercially available discrim- inators. A timing error of 16 ps is achieved under ideal operating conditions. Under more realistic operating conditions the discriminator displays a ...

Design of High Performance Permanent-Magnet Synchronous Wind Generators

Directory of Open Access Journals (Sweden)

Chun-Yu Hsiao

2014-11-01

Full Text Available This paper is devoted to the analysis and design of high performance permanent-magnet synchronous wind generators (PSWGs. A systematic and sequential methodology for the design of PMSGs is proposed with a high performance wind generator as a design model. Aiming at high induced voltage, low harmonic distortion as well as high generator efficiency, optimal generator parameters such as pole-arc to pole-pitch ratio and stator-slot-shoes dimension, etc. are determined with the proposed technique using Maxwell 2-D, Matlab software and the Taguchi method. The proposed double three-phase and six-phase winding configurations, which consist of six windings in the stator, can provide evenly distributed current for versatile applications regarding the voltage and current demands for practical consideration. Specifically, windings are connected in series to increase the output voltage at low wind speed, and in parallel during high wind speed to generate electricity even when either one winding fails, thereby enhancing the reliability as well. A PMSG is designed and implemented based on the proposed method. When the simulation is performed with a 6 Ω load, the output power for the double three-phase winding and six-phase winding are correspondingly 10.64 and 11.13 kW. In addition, 24 Ω load experiments show that the efficiencies of double three-phase winding and six-phase winding are 96.56% and 98.54%, respectively, verifying the proposed high performance operation.

Building and measuring a high performance network architecture

Energy Technology Data Exchange (ETDEWEB)

Kramer, William T.C.; Toole, Timothy; Fisher, Chuck; Dugan, Jon; Wheeler, David; Wing, William R; Nickless, William; Goddard, Gregory; Corbato, Steven; Love, E. Paul; Daspit, Paul; Edwards, Hal; Mercer, Linden; Koester, David; Decina, Basil; Dart, Eli; Paul Reisinger, Paul; Kurihara, Riki; Zekauskas, Matthew J; Plesset, Eric; Wulf, Julie; Luce, Douglas; Rogers, James; Duncan, Rex; Mauth, Jeffery

2001-04-20

Once a year, the SC conferences present a unique opportunity to create and build one of the most complex and highest performance networks in the world. At SC2000, large-scale and complex local and wide area networking connections were demonstrated, including large-scale distributed applications running on different architectures. This project was designed to use the unique opportunity presented at SC2000 to create a testbed network environment and then use that network to demonstrate and evaluate high performance computational and communication applications. This testbed was designed to incorporate many interoperable systems and services and was designed for measurement from the very beginning. The end results were key insights into how to use novel, high performance networking technologies and to accumulate measurements that will give insights into the networks of the future.

High-speed architecture for the decoding of trellis-coded modulation

Science.gov (United States)

Osborne, William P.

1992-01-01

Since 1971, when the Viterbi Algorithm was introduced as the optimal method of decoding convolutional codes, improvements in circuit technology, especially VLSI, have steadily increased its speed and practicality. Trellis-Coded Modulation (TCM) combines convolutional coding with higher level modulation (non-binary source alphabet) to provide forward error correction and spectral efficiency. For binary codes, the current stare-of-the-art is a 64-state Viterbi decoder on a single CMOS chip, operating at a data rate of 25 Mbps. Recently, there has been an interest in increasing the speed of the Viterbi Algorithm by improving the decoder architecture, or by reducing the algorithm itself. Designs employing new architectural techniques are now in existence, however these techniques are currently applied to simpler binary codes, not to TCM. The purpose of this report is to discuss TCM architectural considerations in general, and to present the design, at the logic gate level, or a specific TCM decoder which applies these considerations to achieve high-speed decoding.

HIGH PERFORMANCE CERIA BASED OXYGEN MEMBRANE

DEFF Research Database (Denmark)

2014-01-01

The invention describes a new class of highly stable mixed conducting materials based on acceptor doped cerium oxide (CeO2-8 ) in which the limiting electronic conductivity is significantly enhanced by co-doping with a second element or co- dopant, such as Nb, W and Zn, so that cerium and the co......-dopant have an ionic size ratio between 0.5 and 1. These materials can thereby improve the performance and extend the range of operating conditions of oxygen permeation membranes (OPM) for different high temperature membrane reactor applications. The invention also relates to the manufacturing of supported...

GPU-based high-performance computing for radiation therapy

International Nuclear Information System (INIS)

Jia, Xun; Jiang, Steve B; Ziegenhein, Peter

2014-01-01

Recent developments in radiotherapy therapy demand high computation powers to solve challenging problems in a timely fashion in a clinical environment. The graphics processing unit (GPU), as an emerging high-performance computing platform, has been introduced to radiotherapy. It is particularly attractive due to its high computational power, small size, and low cost for facility deployment and maintenance. Over the past few years, GPU-based high-performance computing in radiotherapy has experienced rapid developments. A tremendous amount of study has been conducted, in which large acceleration factors compared with the conventional CPU platform have been observed. In this paper, we will first give a brief introduction to the GPU hardware structure and programming model. We will then review the current applications of GPU in major imaging-related and therapy-related problems encountered in radiotherapy. A comparison of GPU with other platforms will also be presented. (topical review)

An Introduction to High Performance Fortran

Directory of Open Access Journals (Sweden)

John Merlin

1995-01-01

Full Text Available High Performance Fortran (HPF is an informal standard for extensions to Fortran 90 to assist its implementation on parallel architectures, particularly for data-parallel computation. Among other things, it includes directives for specifying data distribution across multiple memories, and concurrent execution features. This article provides a tutorial introduction to the main features of HPF.

Long duration performance of high temperature irradiation resistant thermocouples

International Nuclear Information System (INIS)

Rempe, J.; Knudson, D.; Condie, K.; Cole, J.; Wilkins, S.C.

2007-01-01

Many advanced nuclear reactor designs require new fuel, cladding, and structural materials. Data are needed to characterize the performance of these new materials in high temperature, radiation conditions. However, traditional methods for measuring temperature in-pile degrade at temperatures above 1100 C degrees. To address this instrumentation need, the Idaho National Laboratory (INL) developed and evaluated the performance of a high temperature irradiation-resistant thermocouple that contains alloys of molybdenum and niobium. To verify the performance of INL's recommended thermocouple design, a series of high temperature (from 1200 to 1800 C) long duration (up to six months) tests has been initiated. This paper summarizes results from the tests that have been completed. Data are presented from 4000 hour tests conducted at 1200 and 1400 C that demonstrate the stability of this thermocouple (less than 2% drift). In addition, post test metallographic examinations are discussed which confirm the compatibility of thermocouple materials throughout these long duration, high temperature tests. (authors)

Highly featured amorphous silicon nanorod arrays for high-performance lithium-ion batteries

International Nuclear Information System (INIS)

Soleimani-Amiri, Samaneh; Safiabadi Tali, Seied Ali; Azimi, Soheil; Sanaee, Zeinab; Mohajerzadeh, Shamsoddin

2014-01-01

High aspect-ratio vertical structures of amorphous silicon have been realized using hydrogen-assisted low-density plasma reactive ion etching. Amorphous silicon layers with the thicknesses ranging from 0.5 to 10 μm were deposited using radio frequency plasma enhanced chemical vapor deposition technique. Standard photolithography and nanosphere colloidal lithography were employed to realize ultra-small features of the amorphous silicon. The performance of the patterned amorphous silicon structures as a lithium-ion battery electrode was investigated using galvanostatic charge-discharge tests. The patterned structures showed a superior Li-ion battery performance compared to planar amorphous silicon. Such structures are suitable for high current Li-ion battery applications such as electric vehicles

Highly featured amorphous silicon nanorod arrays for high-performance lithium-ion batteries

Energy Technology Data Exchange (ETDEWEB)

Soleimani-Amiri, Samaneh; Safiabadi Tali, Seied Ali; Azimi, Soheil; Sanaee, Zeinab; Mohajerzadeh, Shamsoddin, E-mail: mohajer@ut.ac.ir [Thin Film and Nanoelectronics Lab, Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Tehran 143957131 (Iran, Islamic Republic of)

2014-11-10

High aspect-ratio vertical structures of amorphous silicon have been realized using hydrogen-assisted low-density plasma reactive ion etching. Amorphous silicon layers with the thicknesses ranging from 0.5 to 10 μm were deposited using radio frequency plasma enhanced chemical vapor deposition technique. Standard photolithography and nanosphere colloidal lithography were employed to realize ultra-small features of the amorphous silicon. The performance of the patterned amorphous silicon structures as a lithium-ion battery electrode was investigated using galvanostatic charge-discharge tests. The patterned structures showed a superior Li-ion battery performance compared to planar amorphous silicon. Such structures are suitable for high current Li-ion battery applications such as electric vehicles.

Two Profiles of the Dutch High Performing Employee

Science.gov (United States)

de Waal, A. A.; Oudshoorn, Michella

2015-01-01

Purpose: The purpose of this study is to explore the profile of an ideal employee, to be more precise the behavioral characteristics of the Dutch high-performing employee (HPE). Organizational performance depends for a large part on the commitment of employees. Employees provide their knowledge, skills, experiences and creativity to the…

High Performance Computing Software Applications for Space Situational Awareness

Science.gov (United States)

Giuliano, C.; Schumacher, P.; Matson, C.; Chun, F.; Duncan, B.; Borelli, K.; Desonia, R.; Gusciora, G.; Roe, K.

The High Performance Computing Software Applications Institute for Space Situational Awareness (HSAI-SSA) has completed its first full year of applications development. The emphasis of our work in this first year was in improving space surveillance sensor models and image enhancement software. These applications are the Space Surveillance Network Analysis Model (SSNAM), the Air Force Space Fence simulation (SimFence), and physically constrained iterative de-convolution (PCID) image enhancement software tool. Specifically, we have demonstrated order of magnitude speed-up in those codes running on the latest Cray XD-1 Linux supercomputer (Hoku) at the Maui High Performance Computing Center. The software applications improvements that HSAI-SSA has made, has had significant impact to the warfighter and has fundamentally changed the role of high performance computing in SSA.

Family and academic performance: identifying high school student profiles

Directory of Open Access Journals (Sweden)

Alicia Aleli Chaparro Caso López

2016-01-01

Full Text Available The objective of this study was to identify profiles of high school students, based on variables related to academic performance, socioeconomic status, cultural capital and family organization. A total of 21,724 high school students, from the five municipalities of the state of Baja California, took part. A K-means cluster analysis was performed to identify the profiles. The analyses identified two clearly-defined clusters: Cluster 1 grouped together students with high academic performance and who achieved higher scores for socioeconomic status, cultural capital and family involvement, whereas Cluster 2 brought together students with low academic achievement, and who also obtained lower scores for socioeconomic status and cultural capital, and had less family involvement. It is concluded that the family variables analyzed form student profiles that can be related to academic achievement.

Performance Issues in High Performance Fortran Implementations of Sensor-Based Applications

Directory of Open Access Journals (Sweden)

David R. O'hallaron

1997-01-01

Full Text Available Applications that get their inputs from sensors are an important and often overlooked application domain for High Performance Fortran (HPF. Such sensor-based applications typically perform regular operations on dense arrays, and often have latency and through put requirements that can only be achieved with parallel machines. This article describes a study of sensor-based applications, including the fast Fourier transform, synthetic aperture radar imaging, narrowband tracking radar processing, multibaseline stereo imaging, and medical magnetic resonance imaging. The applications are written in a dialect of HPF developed at Carnegie Mellon, and are compiled by the Fx compiler for the Intel Paragon. The main results of the study are that (1 it is possible to realize good performance for realistic sensor-based applications written in HPF and (2 the performance of the applications is determined by the performance of three core operations: independent loops (i.e., loops with no dependences between iterations, reductions, and index permutations. The article discusses the implications for HPF implementations and introduces some simple tests that implementers and users can use to measure the efficiency of the loops, reductions, and index permutations generated by an HPF compiler.

Efficient high-performance ultrasound beamforming using oversampling

Science.gov (United States)

Freeman, Steven R.; Quick, Marshall K.; Morin, Marc A.; Anderson, R. C.; Desilets, Charles S.; Linnenbrink, Thomas E.; O'Donnell, Matthew

1998-05-01

High-performance and efficient beamforming circuitry is very important in large channel count clinical ultrasound systems. Current state-of-the-art digital systems using multi-bit analog to digital converters (A/Ds) have matured to provide exquisite image quality with moderate levels of integration. A simplified oversampling beamforming architecture has been proposed that may a low integration of delta-sigma A/Ds onto the same chip as digital delay and processing circuitry to form a monolithic ultrasound beamformer. Such a beamformer may enable low-power handheld scanners for high-end systems with very large channel count arrays. This paper presents an oversampling beamformer architecture that generates high-quality images using very simple; digitization, delay, and summing circuits. Additional performance may be obtained with this oversampled system for narrow bandwidth excitations by mixing the RF signal down in frequency to a range where the electronic signal to nose ratio of the delta-sigma A/D is optimized. An oversampled transmit beamformer uses the same delay circuits as receive and eliminates the need for separate transmit function generators.

A one-semester course in modeling of VSLI interconnections

CERN Document Server

Goel, Ashok

2015-01-01

Quantitative understanding of the parasitic capacitances and inductances, and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-of-the-art integrated circuits. More than 65 percent of the delays on the integrated circuit chip occur in the interconnections and not in the transistors on the chip. Mathematical techniques to model the parasitic capacitances, inductances, propagation delays, crosstalk noise, and electromigration-induced failure associated with the interconnections in the realistic high-density environment on a chip will be discussed. A One-Semester Course in Modeling of VLSI Interconnections also includes an overview of the future interconnection technologies for the nanotechnology circuits.

High temperature performance limit of containment system of transport cask

International Nuclear Information System (INIS)

Kato, Osamu; Saegusa, Toshiari

1998-01-01

The containment performance of a containment system using elastomer gaskets for transport casks under a high temperature and high pressure was clarified. Major results are as follows; (1) The deformation characteristics of the gaskets were represented by the compressive permanent strain rate (Dp). The temperature and time dependence was shown by Larson-Miller Parameter (LMP). (2) Generally, the high temperature performance limit is obtained by a value of LMP when the Dp value reaches 80%. However, the gaskets (FKM, VMQ, EPDM) used for real transport casks were not damaged and the containment performance was not deteriorated as a conservative condition. (3) Assuming that the service period of the gaskets for transport casks is 3 months or 1 year, the high temperature performance limit of the gasket made of fluorine rubber (FKM) is 202degC or 182degC, respectively, which includes safety margin. (author)

Designing 3D highly ordered nanoporous CuO electrodes for high-performance asymmetric supercapacitors.

Science.gov (United States)

Moosavifard, Seyyed E; El-Kady, Maher F; Rahmanifar, Mohammad S; Kaner, Richard B; Mousavi, Mir F

2015-03-04

The increasing demand for energy has triggered tremendous research efforts for the development of lightweight and durable energy storage devices. Herein, we report a simple, yet effective, strategy for high-performance supercapacitors by building three-dimensional pseudocapacitive CuO frameworks with highly ordered and interconnected bimodal nanopores, nanosized walls (∼4 nm) and large specific surface area of 149 m(2) g(-1). This interesting electrode structure plays a key role in providing facilitated ion transport, short ion and electron diffusion pathways and more active sites for electrochemical reactions. This electrode demonstrates excellent electrochemical performance with a specific capacitance of 431 F g(-1) (1.51 F cm(-2)) at 3.5 mA cm(-2) and retains over 70% of this capacitance when operated at an ultrafast rate of 70 mA cm(-2). When this highly ordered CuO electrode is assembled in an asymmetric cell with an activated carbon electrode, the as-fabricated device demonstrates remarkable performance with an energy density of 19.7 W h kg(-1), power density of 7 kW kg(-1), and excellent cycle life. This work presents a new platform for high-performance asymmetric supercapacitors for the next generation of portable electronics and electric vehicles.

A high-performance channel engineered charge-plasma-based MOSFET with high-κ spacer

Science.gov (United States)

Shan, Chan; Wang, Ying; Luo, Xin; Bao, Meng-tian; Yu, Cheng-hao; Cao, Fei

2017-12-01

In this paper, the performance of graded channel double-gate MOSFET (GC-DGFET) that utilizes the charge-plasma concept and a high-κ spacer is investigated through 2-D device simulations. The results demonstrate that GC-DGFET with high-κ spacer can effectively improve the ON-state driving current (ION) and reduce the OFF-leakage current (IOFF). We find that reduction of the initial energy barrier between the source and channel is the origin of this ION enhancement. The reason for the IOFF reduction is identified to be the extension of the effective channel length owing to the fringing field via high-κ spacers. Consequently, these devices offer enhanced performance by reducing the total gate-to-gate capacitance (Cgg) and decreasing the intrinsic delay (τ).

Enabling High-Performance Computing as a Service

KAUST Repository

AbdelBaky, Moustafa; Parashar, Manish; Kim, Hyunjoo; Jordan, Kirk E.; Sachdeva, Vipin; Sexton, James; Jamjoom, Hani; Shae, Zon-Yin; Pencheva, Gergina; Tavakoli, Reza; Wheeler, Mary F.

2012-01-01

With the right software infrastructure, clouds can provide scientists with as a service access to high-performance computing resources. An award-winning prototype framework transforms the Blue Gene/P system into an elastic cloud to run a

Multijunction Photovoltaic Technologies for High-Performance Concentrators: Preprint

Energy Technology Data Exchange (ETDEWEB)

McConnell, R.; Symko-Davies, M.

2006-05-01

Multijunction solar cells provide high-performance technology pathways leading to potentially low-cost electricity generated from concentrated sunlight. The National Center for Photovoltaics at the National Renewable Energy Laboratory has funded different III-V multijunction solar cell technologies and various solar concentration approaches. Within this group of projects, III-V solar cell efficiencies of 41% are close at hand and will likely be reported in these conference proceedings. Companies with well-developed solar concentrator structures foresee installed system costs of $3/watt--half of today's costs--within the next 2 to 5 years as these high-efficiency photovoltaic technologies are incorporated into their concentrator photovoltaic systems. These technology improvements are timely as new large-scale multi-megawatt markets, appropriate for high performance PV concentrators, open around the world.

New buses and links for data acquisition

International Nuclear Information System (INIS)

Mueller, H.; Bogaerts, A.; McLaren, R.; Parkman, C.; Linnhoefer, D.

1992-01-01

Bus standards for data acquisition have been vital for the construction and operation of medium and large HEP experiments. The recent industry bus standardisation effort will soon release the next generation of high performance buses and links for scalable systems. Prototype components, VLSI chips and board-level systems are already announced. Layers of the new bus specifications cover wide areas of applications and provide possibilities to define specific bus profiles by interest groups. New, innovative solutions which are needed for high rate experiments are becoming visible. These will provide novel architectural possibilities, very high bandwidth, fast silicon, industry support and new metric mechanical standards. Interconnected via standard bridges, different bus standards can be used to cover the varying requirements from the front ends to the computers. (orig.)

Hardware Descriptive Languages: An Efficient Approach to Device ...

African Journals Online (AJOL)

Contemporarily, owing to astronomical advancements in the very large scale integration (VLSI) market segments, hardware engineers are now focusing on how to develop their new digital system designs in programmable languages like very high speed integrated circuit hardwaredescription language (VHDL) and Verilog ...

A High Performance Block Eigensolver for Nuclear Configuration Interaction Calculations

International Nuclear Information System (INIS)

Aktulga, Hasan Metin; Afibuzzaman, Md.; Williams, Samuel; Buluc, Aydin; Shao, Meiyue

2017-01-01

As on-node parallelism increases and the performance gap between the processor and the memory system widens, achieving high performance in large-scale scientific applications requires an architecture-aware design of algorithms and solvers. We focus on the eigenvalue problem arising in nuclear Configuration Interaction (CI) calculations, where a few extreme eigenpairs of a sparse symmetric matrix are needed. Here, we consider a block iterative eigensolver whose main computational kernels are the multiplication of a sparse matrix with multiple vectors (SpMM), and tall-skinny matrix operations. We then present techniques to significantly improve the SpMM and the transpose operation SpMM T by using the compressed sparse blocks (CSB) format. We achieve 3-4× speedup on the requisite operations over good implementations with the commonly used compressed sparse row (CSR) format. We develop a performance model that allows us to correctly estimate the performance of our SpMM kernel implementations, and we identify cache bandwidth as a potential performance bottleneck beyond DRAM. We also analyze and optimize the performance of LOBPCG kernels (inner product and linear combinations on multiple vectors) and show up to 15× speedup over using high performance BLAS libraries for these operations. The resulting high performance LOBPCG solver achieves 1.4× to 1.8× speedup over the existing Lanczos solver on a series of CI computations on high-end multicore architectures (Intel Xeons). We also analyze the performance of our techniques on an Intel Xeon Phi Knights Corner (KNC) processor.

High Performance Computing in Science and Engineering '99 : Transactions of the High Performance Computing Center

CERN Document Server

Jäger, Willi

2000-01-01

The book contains reports about the most significant projects from science and engineering of the Federal High Performance Computing Center Stuttgart (HLRS). They were carefully selected in a peer-review process and are showcases of an innovative combination of state-of-the-art modeling, novel algorithms and the use of leading-edge parallel computer technology. The projects of HLRS are using supercomputer systems operated jointly by university and industry and therefore a special emphasis has been put on the industrial relevance of results and methods.

Highly automated driving, secondary task performance, and driver state.

Science.gov (United States)

Merat, Natasha; Jamson, A Hamish; Lai, Frank C H; Carsten, Oliver

2012-10-01

A driving simulator study compared the effect of changes in workload on performance in manual and highly automated driving. Changes in driver state were also observed by examining variations in blink patterns. With the addition of a greater number of advanced driver assistance systems in vehicles, the driver's role is likely to alter in the future from an operator in manual driving to a supervisor of highly automated cars. Understanding the implications of such advancements on drivers and road safety is important. A total of 50 participants were recruited for this study and drove the simulator in both manual and highly automated mode. As well as comparing the effect of adjustments in driving-related workload on performance, the effect of a secondary Twenty Questions Task was also investigated. In the absence of the secondary task, drivers' response to critical incidents was similar in manual and highly automated driving conditions. The worst performance was observed when drivers were required to regain control of driving in the automated mode while distracted by the secondary task. Blink frequency patterns were more consistent for manual than automated driving but were generally suppressed during conditions of high workload. Highly automated driving did not have a deleterious effect on driver performance, when attention was not diverted to the distracting secondary task. As the number of systems implemented in cars increases, an understanding of the implications of such automation on drivers' situation awareness, workload, and ability to remain engaged with the driving task is important.

Towards high-performance materials for road construction

Science.gov (United States)

Gladkikh, V.; Korolev, E.; Smirnov, V.

2017-10-01

Due to constant increase of traffic, modern road construction is in need of high-performance pavement materials. The operational performance of such materials can be characterized by many properties. Nevertheless, the most important ones are resistance to rutting and resistance to dynamical loads. It was proposed earlier to use sulfur extended asphalt concrete in road construction practice. To reduce the emission of sulfur dioxide and hydrogen sulfide during the concrete mix preparation and pavement production stages, it is beneficial to make such a concrete on the base of complex sulfur modifier. In the present work the influence of the complex modifier to mechanical properties of sulfur extended asphalt concrete was examined. It was shown that sulfur extended asphalt concrete is of high mechanical properties. It was also revealed that there as an anomalous negative correlations between strain capacity, fatigue life and fracture toughness.

Quantification of Quercetin and Rutin from Benincasa hispida Seeds and Carissa Congesta Roots by High-performance Thin Layer Chromatography and High-performance Liquid Chromatography.

Science.gov (United States)

Doshi, Gaurav Mahesh; Une, Hemant Devidas

2016-01-01

In Indian Ayurvedic system, Benincasa hispida (BH) and Carissa congesta (CC) are well-known plants used for major and minor ailments. BH has been regarded as Kushmanda, whereas CC has been used in immune-related disorders of the human system. Quercetin and rutin identified from the vast plethora of plant extracts have proved to possess ethnopharmacological relevance. In present studies, we have determined quercetin and rutin in terms of percentage in BH seeds and CC roots by high-performance thin layer chromatography (HPTLC) and high-performance liquid chromatography (HPLC). After extraction and phytochemical screening, the extracts were subjected to quantification for the presence of quercetin and rutin by HPTLC and HPLC. HPTLC showed quercetin as 44.60, 27.13% and rutin as 32.00, 36.31% w/w, whereas HPLC revealed quercetin as 34.00, 35.00% and rutin as 21.99, 45.03% w/v in BH and CC extracts, respectively. The BH and CC extracts have elucidated peaks that were corresponding with standard peaks on undertaking chromatographic studies. Quercetin and rutin are isolated from BH seeds and CC roots by High Performance. Thin Layer Chromatography and High Performance Liquid Chromatography. HPTLC revealed presence of quercetin as 44.60, 27.13 % and rutin as 32.00, 36.31 % w/w. HPLC revealed presence of quercetin as 34.00, 35.00 % and rutin as 21.99, 45.03 % w/v. Abbreviation Used: HPTLC: High Performance Thin Layer Chromatography; HPLC: High Pressure Liquid Chromatography, UV: Ultraviolet, CC: Carissa congesta, BH: Benincasa hispida.

Quantification of Quercetin and Rutin from Benincasa hispida Seeds and Carissa Congesta Roots by High-performance Thin Layer Chromatography and High-performance Liquid Chromatography

Science.gov (United States)

Doshi, Gaurav Mahesh; Une, Hemant Devidas

2016-01-01

Objective: In Indian Ayurvedic system, Benincasa hispida (BH) and Carissa congesta (CC) are well-known plants used for major and minor ailments. BH has been regarded as Kushmanda, whereas CC has been used in immune-related disorders of the human system. Quercetin and rutin identified from the vast plethora of plant extracts have proved to possess ethnopharmacological relevance. Materials and Methods: In present studies, we have determined quercetin and rutin in terms of percentage in BH seeds and CC roots by high-performance thin layer chromatography (HPTLC) and high-performance liquid chromatography (HPLC). After extraction and phytochemical screening, the extracts were subjected to quantification for the presence of quercetin and rutin by HPTLC and HPLC. Results: HPTLC showed quercetin as 44.60, 27.13% and rutin as 32.00, 36.31% w/w, whereas HPLC revealed quercetin as 34.00, 35.00% and rutin as 21.99, 45.03% w/v in BH and CC extracts, respectively. Conclusion: The BH and CC extracts have elucidated peaks that were corresponding with standard peaks on undertaking chromatographic studies. SUMMARY Quercetin and rutin are isolated from BH seeds and CC roots by High Performance. Thin Layer Chromatography and High Performance Liquid Chromatography. HPTLC revealed presence of quercetin as 44.60, 27.13 % and rutin as 32.00, 36.31 % w/w. HPLC revealed presence of quercetin as 34.00, 35.00 % and rutin as 21.99, 45.03 % w/v. Abbreviation Used: HPTLC: High Performance Thin Layer Chromatography; HPLC: High Pressure Liquid Chromatography, UV: Ultraviolet, CC: Carissa congesta, BH: Benincasa hispida PMID:26941534

High performance co-polyimide nanofiber reinforced composites

NARCIS (Netherlands)

Yao, Jian; Li, Guang; Bastiaansen, Cees; Peijs, Ton

2015-01-01

Electrospun co-polyimide BPDA (3, 3′, 4, 4′-Biphenyltetracarboxylic dianhydride)/PDA (p-Phenylenediamine)/ODA (4, 4′-oxydianiline) nanofiber reinforced flexible composites were manufactured by impregnating these high performance nanofibers with styrene-butadiene-styrene (SBS) triblock copolymer

VLSI PARTITIONING ALGORITHM WITH ADAPTIVE CONTROL PARAMETER

Directory of Open Access Journals (Sweden)

P. N. Filippenko

2013-03-01

Full Text Available The article deals with the problem of very large-scale integration circuit partitioning. A graph is selected as a mathematical model describing integrated circuit. Modification of ant colony optimization algorithm is presented, which is used to solve graph partitioning problem. Ant colony optimization algorithm is an optimization method based on the principles of self-organization and other useful features of the ants’ behavior. The proposed search system is based on ant colony optimization algorithm with the improved method of the initial distribution and dynamic adjustment of the control search parameters. The experimental results and performance comparison show that the proposed method of very large-scale integration circuit partitioning provides the better search performance over other well known algorithms.

Research on high performance mirrors for free electron lasers

International Nuclear Information System (INIS)

Kitatani, Fumito

1996-01-01

For the stable functioning of free electron laser, high performance optical elements are required because of its characteristics. In particular in short wavelength free electron laser, since its gain is low, the optical elements having very high reflectivity are required. Also in free electron laser, since high energy noise light exists, the optical elements must have high optical breaking strength. At present in Power Reactor and Nuclear Fuel Development Corporation, the research for heightening the performance of dielectric multi-layer film elements for short wavelength is carried out. For manufacturing such high performance elements, it is necessary to develop the new materials for vapor deposition, new vapor deposition process, and the techniques of accurate substrate polishing and inspection. As the material that satisfies the requirements, there is diamond-like carbon (DLC) film, of which the properties are explained. As for the manufacture of the DLC films for short wavelength optics, the test equipment for forming the DLC films, the test of forming the DLC films, the change of the film quality due to gas conditions, discharge conditions and substrate materials, and the measurement of the optical breaking strength are reported. (K.I.)

NINJA: Java for High Performance Numerical Computing

Directory of Open Access Journals (Sweden)

José E. Moreira

2002-01-01

Full Text Available When Java was first introduced, there was a perception that its many benefits came at a significant performance cost. In the particularly performance-sensitive field of numerical computing, initial measurements indicated a hundred-fold performance disadvantage between Java and more established languages such as Fortran and C. Although much progress has been made, and Java now can be competitive with C/C++ in many important situations, significant performance challenges remain. Existing Java virtual machines are not yet capable of performing the advanced loop transformations and automatic parallelization that are now common in state-of-the-art Fortran compilers. Java also has difficulties in implementing complex arithmetic efficiently. These performance deficiencies can be attacked with a combination of class libraries (packages, in Java that implement truly multidimensional arrays and complex numbers, and new compiler techniques that exploit the properties of these class libraries to enable other, more conventional, optimizations. Two compiler techniques, versioning and semantic expansion, can be leveraged to allow fully automatic optimization and parallelization of Java code. Our measurements with the NINJA prototype Java environment show that Java can be competitive in performance with highly optimized and tuned Fortran code.

An integrated framework for high level design of high performance signal processing circuits on FPGAs

Science.gov (United States)

Benkrid, K.; Belkacemi, S.; Sukhsawas, S.

2005-06-01

This paper proposes an integrated framework for the high level design of high performance signal processing algorithms' implementations on FPGAs. The framework emerged from a constant need to rapidly implement increasingly complicated algorithms on FPGAs while maintaining the high performance needed in many real time digital signal processing applications. This is particularly important for application developers who often rely on iterative and interactive development methodologies. The central idea behind the proposed framework is to dynamically integrate high performance structural hardware description languages with higher level hardware languages in other to help satisfy the dual requirement of high level design and high performance implementation. The paper illustrates this by integrating two environments: Celoxica's Handel-C language, and HIDE, a structural hardware environment developed at the Queen's University of Belfast. On the one hand, Handel-C has been proven to be very useful in the rapid design and prototyping of FPGA circuits, especially control intensive ones. On the other hand, HIDE, has been used extensively, and successfully, in the generation of highly optimised parameterisable FPGA cores. In this paper, this is illustrated in the construction of a scalable and fully parameterisable core for image algebra's five core neighbourhood operations, where fully floorplanned efficient FPGA configurations, in the form of EDIF netlists, are generated automatically for instances of the core. In the proposed combined framework, highly optimised data paths are invoked dynamically from within Handel-C, and are synthesized using HIDE. Although the idea might seem simple prima facie, it could have serious implications on the design of future generations of hardware description languages.

High-performance flexible microwave passives on plastic

Science.gov (United States)

Ma, Zhenqiang; Seo, Jung-Hun; Cho, Sang June; Zhou, Weidong

2014-06-01

We report the demonstration of bendable inductors, capacitors and switches fabricated on a polyethylene terephthalate (PET) substrate that can operate at high microwave frequencies. By employing bendable dielectric and single crystalline semiconductor materials, spiral inductors and metal-insulator-metal (MIM) capacitors with high quality factors and high resonance frequencies and single-pole, single-throw (SPST) switches were archived. The effects of mechanical bending on the performance of inductors, capacitors and switches were also measured and analyzed. We further investigated the highest possible resonance frequencies and quality factors of inductors and capacitors and, high frequency responses and insertion loss. These demonstrations will lead to flexible radio-frequency and microwave systems in the future.

CUDA/GPU Technology : Parallel Programming For High Performance Scientific Computing

OpenAIRE

YUHENDRA; KUZE, Hiroaki; JOSAPHAT, Tetuko Sri Sumantyo

2009-01-01

[ABSTRACT]Graphics processing units (GP Us) originally designed for computer video cards have emerged as the most powerful chip in a high-performance workstation. In the high performance computation capabilities, graphic processing units (GPU) lead to much more powerful performance than conventional CPUs by means of parallel processing. In 2007, the birth of Compute Unified Device Architecture (CUDA) and CUDA-enabled GPUs by NVIDIA Corporation brought a revolution in the general purpose GPU a...

Transport in JET high performance plasmas

International Nuclear Information System (INIS)

2001-01-01

Two type of high performance scenarios have been produced in JET during DTE1 campaign. One of them is the well known and extensively used in the past ELM-free hot ion H-mode scenario which has two distinct regions- plasma core and the edge transport barrier. The results obtained during DTE-1 campaign with D, DT and pure T plasmas confirms our previous conclusion that the core transport scales as a gyroBohm in the inner half of plasma volume, recovers its Bohm nature closer to the separatrix and behaves as ion neoclassical in the transport barrier. Measurements on the top of the barrier suggest that the width of the barrier is dependent upon isotope and moreover suggest that fast ions play a key role. The other high performance scenario is a relatively recently developed Optimised Shear Scenario with small or slightly negative magnetic shear in plasma core. Different mechanisms of Internal Transport Barrier (ITB) formation have been tested by predictive modelling and the results are compared with experimentally observed phenomena. The experimentally observed non-penetration of the heavy impurities through the strong ITB which contradicts to a prediction of the conventional neo-classical theory is discussed. (author)

Transport in JET high performance plasmas

International Nuclear Information System (INIS)

1999-01-01

Two type of high performance scenarios have been produced in JET during DTE1 campaign. One of them is the well known and extensively used in the past ELM-free hot ion H-mode scenario which has two distinct regions- plasma core and the edge transport barrier. The results obtained during DTE-1 campaign with D, DT and pure T plasmas confirms our previous conclusion that the core transport scales as a gyroBohm in the inner half of plasma volume, recovers its Bohm nature closer to the separatrix and behaves as ion neoclassical in the transport barrier. Measurements on the top of the barrier suggest that the width of the barrier is dependent upon isotope and moreover suggest that fast ions play a key role. The other high performance scenario is a relatively recently developed Optimised Shear Scenario with small or slightly negative magnetic shear in plasma core. Different mechanisms of Internal Transport Barrier (ITB) formation have been tested by predictive modelling and the results are compared with experimentally observed phenomena. The experimentally observed non-penetration of the heavy impurities through the strong ITB which contradicts to a prediction of the conventional neo-classical theory is discussed. (author)

Toward High Performance in Industrial Refrigeration Systems

DEFF Research Database (Denmark)

Thybo, C.; Izadi-Zamanabadi, Roozbeh; Niemann, H.

2002-01-01

Achieving high performance in complex industrial systems requires information manipulation at different system levels. The paper shows how different models of same subsystems, but using different quality of information/data, are used for fault diagnosis as well as robust control design...

Towards high performance in industrial refrigeration systems

DEFF Research Database (Denmark)

Thybo, C.; Izadi-Zamanabadi, R.; Niemann, Hans Henrik

2002-01-01

Achieving high performance in complex industrial systems requires information manipulation at different system levels. The paper shows how different models of same subsystems, but using different quality of information/data, are used for fault diagnosis as well as robust control design...

Global floor planning approach for VLSI design

International Nuclear Information System (INIS)

LaPotin, D.P.

1986-01-01

Within a hierarchical design environment, initial decisions regarding the partitioning and choice of module attributes greatly impact the quality of the resulting IC in terms of area and electrical performance. This dissertation presents a global floor-planning approach which allows designers to quickly explore layout issues during the initial stages of the IC design process. In contrast to previous efforts, which address the floor-planning problem from a strict module placement point of view, this approach considers floor-planning from an area planning point of view. The approach is based upon a combined min-cut and slicing paradigm, which ensures routability. To provide flexibility, modules may be specified as having a number of possible dimensions and orientations, and I/O pads as well as layout constraints are considered. A slicing-tree representation is employed, upon which a sequence of traversal operations are applied in order to obtain an area efficient layout. An in-place partitioning technique, which provides an improvement over previous min-cut and slicing-based efforts, is discussed. Global routing and module I/O pin assignment are provided for floor-plan evaluation purposes. A computer program, called Mason, has been developed which efficiently implements the approach and provides an interactive environment for designers to perform floor-planning. Performance of this program is illustrated via several industrial examples

High Performance Low Mass Nanowire Enabled Heatpipe, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — Heat pipes are widely used for passive, two-phase electronics cooling. As advanced high power, high performance electronics in space based and terrestrial...

The Creation and Operation of Internal High Performance Modern Enterprises Team

Institute of Scientific and Technical Information of China (English)

Shengyu WANG

2015-01-01

The future of enterprises mainly depends on product research and development. For the modern enterprises, high performance project team is the most important means of R ＆ D projects. According to the interviews and survey found of a plurality of enterprise project R ＆ D team. the internal high performance team of modern business is good or bad, its key lies in whether the team managers for the team creation and management is in place, this is the most difficult place for the high performance team management system, especially the team leadership. Based on this, this paper discusses on the creation and management of high performance modern enterprise team, aiming to provide valuable reference for the enterprise team management.

A multichannel compact readout system for single photon detection: Design and performances

Energy Technology Data Exchange (ETDEWEB)

Argentieri, A.G. [Istituto Nazionale di Fisica Nucleare, via E. Orabona 4, 70126 Bari (Italy); Cisbani, E.; Colilli, S.; Cusanno, F. [Istituto Superiore di Sanita, viale Regina Elena 299, 00161 Roma (Italy); De Leo, R. [Istituto Nazionale di Fisica Nucleare, via E. Orabona 4, 70126 Bari (Italy); Fratoni, R.; Garibaldi, F.; Giuliani, F.; Gricia, M.; Lucentini, M. [Istituto Superiore di Sanita, viale Regina Elena 299, 00161 Roma (Italy); Marra, M. [Istituto Nazionale di Fisica Nucleare, via E. Orabona 4, 70126 Bari (Italy); Musico, Paolo, E-mail: Paolo.Musico@ge.infn.i [Istituto Nazionale di Fisica Nucleare, via Dodecaneso 33, 16146 Genova (Italy); Santavenere, F.; Torrioli, S. [Istituto Superiore di Sanita, viale Regina Elena 299, 00161 Roma (Italy)

2010-05-21

Optimal exploitation of Multi Anode PhotoMultiplier Tubes (MAPMT) as imaging devices requires the acquisition of a large number of independent channels; despite the rather wide demand, on-the-shelf electronics for this purpose does not exist. A compact independent channel readout system for an array of MAPMTs has been developed and tested . The system can handle up to 4096 independent channels, covering an area of about 20x20cm{sup 2} with pixel size of 3x3mm{sup 2}, using Hamamatsu H-9500 devices. The front-end is based on a 64 channels VLSI custom chip called MAROC, developed by IN2P3 Orsay (France) group, controlled by means of a Field Programmable Gate Array (FPGA) which implements configuration, triggering and data conversion controls. Up to 64 front-end cards can be housed in four backplanes and a central unit collects data from all of them, communicating with a control Personal Computer (PC) using an high speed USB 2.0 connection. A complete system has been built and tested. Eight Flat MAPMTs (256 anodes Hamamatsu H-9500) have been arranged on a boundary of a 3x3 matrix for a grand total of 2048 channels. This detector has been used to verify the performances of a focusing aerogel RICH prototype using an electron beam at the Frascati (Rome) INFN National Laboratory Beam Test Facility (BTF) during the last week of January 2009. Data analysis is ongoing: the first results are encouraging, showing that the Cherenkov rings are well identified by this system.

A multichannel compact readout system for single photon detection: Design and performances

Science.gov (United States)

Argentieri, A. G.; Cisbani, E.; Colilli, S.; Cusanno, F.; De Leo, R.; Fratoni, R.; Garibaldi, F.; Giuliani, F.; Gricia, M.; Lucentini, M.; Marra, M.; Musico, Paolo; Santavenere, F.; Torrioli, S.

2010-05-01

Optimal exploitation of Multi Anode PhotoMultiplier Tubes (MAPMT) as imaging devices requires the acquisition of a large number of independent channels; despite the rather wide demand, on-the-shelf electronics for this purpose does not exist. A compact independent channel readout system for an array of MAPMTs has been developed and tested [1,2]. The system can handle up to 4096 independent channels, covering an area of about 20×20 cm2 with pixel size of 3×3 mm2, using Hamamatsu H-9500 devices. The front-end is based on a 64 channels VLSI custom chip called MAROC, developed by IN2P3 Orsay (France) group, controlled by means of a Field Programmable Gate Array (FPGA) which implements configuration, triggering and data conversion controls. Up to 64 front-end cards can be housed in four backplanes and a central unit collects data from all of them, communicating with a control Personal Computer (PC) using an high speed USB 2.0 connection. A complete system has been built and tested. Eight Flat MAPMTs (256 anodes Hamamatsu H-9500) have been arranged on a boundary of a 3×3 matrix for a grand total of 2048 channels. This detector has been used to verify the performances of a focusing aerogel RICH prototype using an electron beam at the Frascati (Rome) INFN National Laboratory Beam Test Facility (BTF) during the last week of January 2009. Data analysis is ongoing: the first results are encouraging, showing that the Cherenkov rings are well identified by this system.

The Scalable Coherent Interface and related standards projects

International Nuclear Information System (INIS)

Gustavson, D.B.

1991-09-01

The Scalable Coherent Interface (SCI) project (IEEE P1596) found a way to avoid the limits that are inherent in bus technology. SCI provides bus-like services by transmitting packets on a collection of point-to-point unidirectional links. The SCI protocols support cache coherence in a distributed-shared-memory multiprocessor model, message passing, I/O, and local-area-network-like communication over fiber optic or wire links. VLSI circuits that operate parallel links at 1000 MByte/s and serial links at 1000 Mbit/s will be available early in 1992. Several ongoing SCI-related projects are applying the SCI technology to new areas or extending it to more difficult problems. P1596.1 defines the architecture of a bridge between SCI and VME; P1596.2 compatibly extends the cache coherence mechanism for efficient operation with kiloprocessor systems; P1596.3 defines new low-voltage (about 0.25 V) differential signals suitable for low power interfaces for CMOS or GaAs VLSI implementations of SCI; P1596.4 defines a high performance memory chip interface using these signals; P1596.5 defines data transfer formats for efficient interprocessor communication in heterogeneous multiprocessor systems. This paper reports the current status of SCI, related standards, and new projects. 16 refs

Planning for high performance project teams

International Nuclear Information System (INIS)

Reed, W.; Keeney, J.; Westney, R.

1997-01-01

Both industry-wide research and corporate benchmarking studies confirm the significant savings in cost and time that result from early planning of a project. Amoco's Team Planning Workshop combines long-term strategic project planning and short-term tactical planning with team building to provide the basis for high performing project teams, better project planning, and effective implementation of the Amoco Common Process for managing projects

Studies on high performance Timeslice building on the CBM FLES

Energy Technology Data Exchange (ETDEWEB)

Hartmann, Helvi [Frankfurt Institute for Advanced Studies, Goethe University, Frankfurt (Germany); Collaboration: CBM-Collaboration

2015-07-01

In contrast to already existing high energy physics experiments the Compressed Baryonic Matter (CBM) experiment collects all data untriggered. The First-level Event Selector (FLES), which denotes a high performance computer cluster, processes the very high incoming data rate of 1 TByte/s and performs a full online event reconstruction. For this task it needs to access the raw detector data in time intervals referred to as Timeslices. In order to construct the Timeslices, the FLES Timeslice building has to combine data from all input links and distribute them via a high-performance network to the compute nodes. For fast data transfer the Infiniband network has proven to be appropriate. One option to address the network is using Infiniband (RDMA) Verbs directly and potentially making best use of Infiniband. However, it is a very low-level implementation relying on the hardware and neglecting other possible network technologies in the future. Another approach is to apply a high-level API like MPI which is independent of the underlying hardware and suitable for less error prone software development. I present the given possibilities and show the results of benchmarks ran on high-performance computing clusters. The solutions are evaluated regarding the Timeslice building in CBM.

Ultra high performance concrete dematerialization study