Microprocessors principles and applications

CERN Document Server

Debenham, Michael J

1979-01-01

Microprocessors: Principles and Applications deals with the principles and applications of microprocessors and covers topics ranging from computer architecture and programmed machines to microprocessor programming, support systems and software, and system design. A number of microprocessor applications are considered, including data processing, process control, and telephone switching. This book is comprised of 10 chapters and begins with a historical overview of computers and computing, followed by a discussion on computer architecture and programmed machines, paying particular attention to t

Microprocessor controller for phasing the accelerator

International Nuclear Information System (INIS)

Howry, S.K.; Wilmunder, A.R.

1977-03-01

A microprocessor controller is being developed to perform automatic phasing of the SLAC accelerator. It will replace the existing relay/analog boxes which are ten years old. The new system is all solid state except for the stepping motors that drive the phase shifters. A description is given of the components of the system, the control algorithm, microprocessor hardware and software design and development, and interaction with SLAC's computer control system

Newnes microprocessor pocket book

CERN Document Server

Money, Steve

2014-01-01

Newnes Microprocessor Pocket Book explains the basic hardware operation of a microprocessor and describes the actions of the various types of instruction that can be executed. A summary of the characteristics of many of the popular microprocessors is presented. Apart from the popular 8- and 16-bit microprocessors, some details are also given of the popular single chip microcomputers and of the reduced instruction set computer (RISC) type processors such as the Transputer, Novix FORTH processor, and Acorn ARM processor.Comprised of 15 chapters, this book discusses the principles involved in bot

Microprocessor monitored Auger spectrometer

International Nuclear Information System (INIS)

Sapin, Michel; Ghaleb, Dominique; Pernot, Bernard.

1982-05-01

The operation of an Auger spectrometer, used for studying surface impurity diffusion, has been fully automatized with the help of a microprocessor. The characteristics, performance and practical use of the system are described together with the main advantage for the experimentator [fr

Application of multiwall carbon nanotubes for thermal dissipation in a micro-processor

Energy Technology Data Exchange (ETDEWEB)

Bui Hung Thang; Phan Ngoc Hong; Phan Hong Khoi; Phan Ngoc Minh [Institute of Materials Science, Vietnam Academy of Science and Technology, 18 Hoang Quoc Viet Road, Cau Giay District, Hanoi (Viet Nam)], E-mail: minhpn@ims.vast.ac.vn

2009-09-01

One of the most valuable properties of the carbon nanotubes materials is its high thermal conductivity with 2000 W/m.K (compared to thermal conductivity of Ag 419 W/m.K). It suggested an approach in applying the CNTs in thermal dissipation media to improve the performance of computer processors and other high power electronic devices. In this research, the multiwall carbon nanotubes (MWCNTs) made by thermal chemical vapour deposition (CVD) at our laboratory was employed as the heat dissipation media in a microprocessor a Personal Computer with configuration: Intel Pentium IV 3.066 GHz, 512Mb of RAM and Windows XP Service Pack 2 Operating System. We directly measured the temperature of the microprocessor during the operation of the computer in two modes: 100% usage CPU mode and over-clocking mode. The measured results showed that when using our thermal dissipation media (a mixture of the mentioned commercial thermal compound and 2 wt.%. MWCNTs), the temperature of the microprocessor decreased 5 deg. C, and the time for increasing the temperature of the microprocessor was three times longer than that when using commercial thermal compound. In over-clocking mode, the processor speed reached 3.8 GHz with 165 MHz of system bus clock speed; it was 1.24 times higher than that in non over-clocking mode. The results confirmed a promising way of using MWCNTs as the thermal dissipation media for microprocessor and high power electronic devices.

Application of multiwall carbon nanotubes for thermal dissipation in a micro-processor

Science.gov (United States)

Thang, Bui Hung; Hong, Phan Ngoc; Khoi, Phan Hong; Minh, Phan Ngoc

2009-09-01

One of the most valuable properties of the carbon nanotubes materials is its high thermal conductivity with 2000 W/m.K (compared to thermal conductivity of Ag 419 W/m.K). It suggested an approach in applying the CNTs in thermal dissipation media to improve the performance of computer processors and other high power electronic devices. In this research, the multiwall carbon nanotubes (MWCNTs) made by thermal chemical vapour deposition (CVD) at our laboratory was employed as the heat dissipation media in a microprocessor a Personal Computer with configuration: Intel Pentium IV 3.066 GHz, 512Mb of RAM and Windows XP Service Pack 2 Operating System. We directly measured the temperature of the microprocessor during the operation of the computer in two modes: 100% usage CPU mode and over-clocking mode. The measured results showed that when using our thermal dissipation media (a mixture of the mentioned commercial thermal compound and 2 wt.%. MWCNTs), the temperature of the microprocessor decreased 5°C, and the time for increasing the temperature of the microprocessor was three times longer than that when using commercial thermal compound. In over-clocking mode, the processor speed reached 3.8 GHz with 165 MHz of system bus clock speed; it was 1.24 times higher than that in non over-clocking mode. The results confirmed a promising way of using MWCNTs as the thermal dissipation media for microprocessor and high power electronic devices.

Application of multiwall carbon nanotubes for thermal dissipation in a micro-processor

International Nuclear Information System (INIS)

Bui Hung Thang; Phan Ngoc Hong; Phan Hong Khoi; Phan Ngoc Minh

2009-01-01

One of the most valuable properties of the carbon nanotubes materials is its high thermal conductivity with 2000 W/m.K (compared to thermal conductivity of Ag 419 W/m.K). It suggested an approach in applying the CNTs in thermal dissipation media to improve the performance of computer processors and other high power electronic devices. In this research, the multiwall carbon nanotubes (MWCNTs) made by thermal chemical vapour deposition (CVD) at our laboratory was employed as the heat dissipation media in a microprocessor a Personal Computer with configuration: Intel Pentium IV 3.066 GHz, 512Mb of RAM and Windows XP Service Pack 2 Operating System. We directly measured the temperature of the microprocessor during the operation of the computer in two modes: 100% usage CPU mode and over-clocking mode. The measured results showed that when using our thermal dissipation media (a mixture of the mentioned commercial thermal compound and 2 wt.%. MWCNTs), the temperature of the microprocessor decreased 5 deg. C, and the time for increasing the temperature of the microprocessor was three times longer than that when using commercial thermal compound. In over-clocking mode, the processor speed reached 3.8 GHz with 165 MHz of system bus clock speed; it was 1.24 times higher than that in non over-clocking mode. The results confirmed a promising way of using MWCNTs as the thermal dissipation media for microprocessor and high power electronic devices.

Real-time fetal ECG system design using embedded microprocessors

Science.gov (United States)

Meyer-Baese, Uwe; Muddu, Harikrishna; Schinhaerl, Sebastian; Kumm, Martin; Zipf, Peter

2016-05-01

The emphasis of this project lies in the development and evaluation of new robust and high fidelity fetal electrocardiogram (FECG) systems to determine the fetal heart rate (FHR). Recently several powerful algorithms have been suggested to improve the FECG fidelity. Until now it is unknown if these algorithms allow a real-time processing, can be used in mobile systems (low power), and which algorithm produces the best error rate for a given system configuration. In this work we have developed high performance, low power microprocessor-based biomedical systems that allow a fair comparison of proposed, state-of-the-art FECG algorithms. We will evaluate different soft-core microprocessors and compare these solutions to other commercial off-the-shelf (COTS) hardcore solutions in terms of price, size, power, and speed.

A microarchitecture for resource-limited superscalar microprocessors

Science.gov (United States)

Basso, Todd David

1999-11-01

Microelectronic components in space and satellite systems must be resistant to total dose radiation, single-even upset, and latchup in order to accomplish their missions. The demand for inexpensive, high-volume, radiation hardened (rad-hard) integrated circuits (ICs) is expected to increase dramatically as the communication market continues to expand. Motorola's Complementary Gallium Arsenide (CGaAsTM) technology offers superior radiation tolerance compared to traditional CMOS processes, while being more economical than dedicated rad-hard CMOS processes. The goals of this dissertation are to optimize a superscalar microarchitecture suitable for CGaAsTM microprocessors, develop circuit techniques for such applications, and evaluate the potential of CGaAsTM for the development of digital VLSI circuits. Motorola's 0.5 mum CGaAsTM process is summarized and circuit techniques applicable to digital CGaAsTM are developed. Direct coupled FET, complementary, and domino logic circuits are compared based on speed, power, area, and noise margins. These circuit techniques are employed in the design of a 600 MHz PowerPCTM arithmetic logic unit. The dissertation emphasizes CGaASTM-specific design considerations, specifically, low integration level. A baseline superscalar microarchitecture is defined and SPEC95 integer benchmark simulations are used to evaluate the applicability of advanced architectural features to microprocessors having low integration levels. The performance simulations center around the optimization of a simple superscalar core, small-scale branch prediction, instruction prefetching, and an off-chip primary data cache. The simulation results are used to develop a superscalar microarchitecture capable of outperforming a comparable sequential pipeline, while using only 500,000 transistors. The architecture, running at 200 MHz, is capable of achieving an estimated 153 MIPS, translating to a 27% performance increase over a comparable traditional pipelined

Microprocessors in detectors and analysis

International Nuclear Information System (INIS)

Siskind, E.J.

1982-01-01

The increasing need in high energy physics experiments for computation power for both online and offline applications, coupled with the current microprocessor revolution, has led to the examination of the use of microprocessors in various aspects of HEP computing. A brief (and admittedly somewhat biased) review is given of current hardware products, the costs of developing and producing hardware systems, and the costs of providing appropriate software support tools which allow one to make effective use of physicists' time, and the applicability of certain systems to the various needs of HEP computing

Microprocessors in detectors and analysis

International Nuclear Information System (INIS)

Siskind, E.J.

1982-01-01

The increasing need in high energy physics experiments for computation power for both online and offline applications, coupled with the current microprocessor revolution, has led us to examine the use of microprocessors in various aspects of HEP computing. The following article is a brief (and admittedly somewhat biased) review of current hardware products, the costs of developing and producing hardware systems, and the costs of providing appropriate software support tools which allow one to make effective use of physicists' time, and the applicability of certain systems to the various needs of HEP computing

Microprocessors in automatic chemical analysis

International Nuclear Information System (INIS)

Goujon de Beauvivier, M.; Perez, J.-J.

1979-01-01

Application of microprocessors to programming and computing of solutions chemical analysis by a sequential technique is examined. Safety, performances reliability are compared to other methods. An example is given on uranium titration by spectrophotometry [fr

A microprocessor based on a two-dimensional semiconductor

Science.gov (United States)

Wachter, Stefan; Polyushkin, Dmitry K.; Bethge, Ole; Mueller, Thomas

2017-04-01

The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor--molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.

CFD-simulation of radiator for air cooling of microprocessors in a limitided space

Directory of Open Access Journals (Sweden)

Trofimov V. E.

2016-12-01

Full Text Available One of the final stages of microprocessors development is heat test. This procedure is performed on a special stand, the main element of which is the switching PCB with one or more mounted microprocessor sockets, chipsets, interfaces, jumpers and other components which provide various modes of microprocessor operation. The temperature of microprocessor housing is typically changed using thermoelectric module. The cold surface of the module with controlled temperature is in direct thermal contact with the microprocessor housing designed for cooler installation. On the hot surface of the module a radiator is mounted. The radiator dissipates the cumulative heat flow from both the microprocessor and the module. High density PCB layout, the requirement of free access to the jumpers and interfaces, and the presence of numerous sensors limit the space for radiator mounting and require the use of an extremely compact radiator, especially in air cooling conditions. One of the possible solutions for this problem may reduce the area of the radiator heat-transfer surfaces due to a sharp growth of the heat transfer coefficient without increasing the air flow rate. To ensure a sharp growth of heat transfer coefficient on the heat-transfer surface one should make in the surface one or more dead-end cavities into which the impact air jets would flow. CFD simulation of this type of radiator has been conducted. The heat-aerodynamic characteristics and design recommendations for removing heat from microprocessors in a limited space have been determined.

The micro-processor controlled process radiation monitoring system for reactor safety systems

International Nuclear Information System (INIS)

Mizuno, K.; Noguchi, A.; Kumagami, S.; Gotoh, Y.; Kumahara, T.; Arita, S.

1986-01-01

Digital computers are soon expected to be applied to various real-time safety and safety-related systems in nuclear power plants. Hitachi is now engaged in the development of a micro-processor controlled process radiation monitoring system, which operates on digital processing methods employed with a log ratemeter. A newly defined methodology of design and test procedures is being applied as a means of software program verification for these safety systems. Recently implemented micro-processor technology will help to achieve an advanced man-machine interface and highly reliable performance. (author)

Flexible nanoscale high-performance FinFETs

KAUST Repository

Sevilla, Galo T.; Ghoneim, Mohamed T.; Fahad, Hossain M.; Rojas, Jhonathan Prieto; Hussain, Aftab M.; Hussain, Muhammad Mustafa

2014-01-01

With the emergence of the Internet of Things (IoT), flexible high-performance nanoscale electronics are more desired. At the moment, FinFET is the most advanced transistor architecture used in the state-of-the-art microprocessors. Therefore, we show

CFD-simulation of radiator for air cooling of microprocessors in a limitided space

OpenAIRE

Trofimov V. E.; Pavlov A. L.; Mokrousova E. A.

2016-01-01

One of the final stages of microprocessors development is heat test. This procedure is performed on a special stand, the main element of which is the switching PCB with one or more mounted microprocessor sockets, chipsets, interfaces, jumpers and other components which provide various modes of microprocessor operation. The temperature of microprocessor housing is typically changed using thermoelectric module. The cold surface of the module with controlled temperature is in direct thermal c...

Dynamic instruction set extension of microprocessors with embedded FPGAs

OpenAIRE

Bauer, Heiner

2017-01-01

Increasingly complex applications and recent shifts in technology scaling have created a large demand for microprocessors which can perform tasks more quickly and more energy efficient. Conventional microarchitectures exploit multiple levels of parallelism to increase instruction throughput and use application specific instruction sets or hardware accelerators to increase energy efficiency. Reconfigurable microprocessors adopt the same principle of providing application specific hardware, how...

Microprocessor based techniques at CESR

International Nuclear Information System (INIS)

Giannini, G.; Cornell Univ., Ithaca, NY

1981-01-01

Microprocessor based systems succesfully used in connection with the High Energy Physics experimental program at the Cornell Electron Storage Ring are described. The multiprocessor calibration system for the CUSB calorimeter is analyzed in view of present and future applications. (orig.)

Architecture of 32 bit CISC (Complex Instruction Set Computer) microprocessors

International Nuclear Information System (INIS)

Jove, T.M.; Ayguade, E.; Valero, M.

1988-01-01

In this paper we describe the main topics about the architecture of the best known 32-bit CISC microprocessors; i80386, MC68000 family, NS32000 series and Z80000. We focus on the high level languages support, operating system design facilities, memory management, techniques to speed up the overall performance and program debugging facilities. (Author)

Memory, microprocessor, and ASIC

CERN Document Server

Chen, Wai-Kai

2003-01-01

System Timing. ROM/PROM/EPROM. SRAM. Embedded Memory. Flash Memories. Dynamic Random Access Memory. Low-Power Memory Circuits. Timing and Signal Integrity Analysis. Microprocessor Design Verification. Microprocessor Layout Method. Architecture. ASIC Design. Logic Synthesis for Field Programmable Gate Array (EPGA) Technology. Testability Concepts and DFT. ATPG and BIST. CAD Tools for BIST/DFT and Delay Faults.

High speed serial link for UA1 microprocessor network

CERN Document Server

Cittolin, S; Zurfluh, E

1981-01-01

The UA1 data acquisition system consists of a set of distributed microprocessor units. An interprocessor link, independent of the CAMAC data readout, has been developed in order to have continuous remote control and run-time data handling, e.g. transmission of calibration programs/parameters, equipment test/status and histogram accumulation. The data transmission system is designed to be used in a loop configuration equipped with transceivers for twisted pair cables (RS-422). As an economical system, it is running as an ancillary serial loop-link between microprocessors, like Data Acquisition Crate Controllers and systems with distributed intelligence. The software driver consists of a loop-controller package, which may run in a BAMBI Computer Language environment and a fully interrupt controlled program for all other secondary stations. A special single-character mode provides a handy link for remote debugging in a pseudo-full-duplex mode. The format is based on the HDLC protocol without sequence numbering. ...

High speed serial link for UA1 microprocessor network

CERN Document Server

Cittolin, Sergio; Zurfluh, E

1981-01-01

The UA1 data acquisition system consists of a set of distributed microprocessor units. An interprocessor link, independent of the CAMAC data readout, has been developed in order to have continuous remote control and run-time data handling, e.g. transmission of calibration programs/parameters, equipment test/status and histogram accumulation. The data transmission system is designed to be used in a loop configuration equipped with transceivers for twisted pair cables (RS-422). As an economical system, it is running as an ancillary serial loop-link between microprocessors, like data acquisition crate controllers and systems with distributed intelligence. The software driver consists of a loop-controller package, which may run in a BAMBI computer language environment and a fully interrupt controlled program for all other secondary stations. A special single-character mode provides a handy link for remote debugging in a pseudo-full-duplex mode. The format is based on the HDLC protocol without sequence numbering. ...

Microprocessors applications in the nuclear industry

International Nuclear Information System (INIS)

Ethridge, C.D.

1980-01-01

Microprocessors in the nuclear industry, particularly at the Los Alamos Scientific Laboratory, have been and are being utilized in a wide variety of applications ranging from data acquisition and control for basic physics research to monitoring special nuclear material in long-term storage. Microprocessor systems have been developed to support weapons diagnostics measurements during underground weapons testing at the Nevada Test Site. Multiple single-component microcomputers are now controlling the measurement and recording of nuclear reactor operating power levels. The CMOS microprocessor data-acquisition instrumentation has operated on balloon flights to monitor power plant emissions. Target chamber mirror-positioning equipment for laser fusion facilities employs microprocessors

OS Friendly Microprocessor Architecture

Science.gov (United States)

2017-04-01

NOTES Patrick La Fratta is now affiliated with Micron Technology, Inc., Boise, Idaho. 14. ABSTRACT We present an introduction to the patented ...Operating System Friendly Microprocessor Architecture (OSFA). The software framework to support the hardware-level security features is currently patent ...Army is assignee. OS Friendly Microprocessor Architecture. United States Patent 9122610. 2015 Sep. 2. Jungwirth P, inventor; US Army is assignee

A microprocessor based area monitor system for neutron and gamma radiation

International Nuclear Information System (INIS)

Wilhelm, R.; Heusser, G.

1980-01-01

The conventional electronics of the area monitors at the MPI-Heidelberg accelerators have been replaced by a microprocessor system consisting of individual detector-microprocessors and a central microcomputer. The detector microprocessors convert the count rates of BF3 and GM counter tubes into dose rates and control three different radiation thresholds (failure, low and high level). Different warning signals are operated directly by the detector processors, whereas the dose rates are transferred to the central microcomputer. Here the data are processed for recording on tape and displaying on TV monitors. The detector as well as the central processors have been developed on the basis of a 16-bit microprocessor. In the control rooms the dose rates of the individual monitors are displayed and on an indicator board showing the different locations, the high radiation level and the state of the doors (open, locked, and closed, locked but open) are sianaled by different LED. If a high radiation threshold is surpassed, the doors adjacent to that area can be locked either by switches on the indicator board or automatically. Within the experimental area, the low and high radiation level is indicated by acoustic and light signals. The whole concept permits keeping the absorbed doses of the personnel as low as possible without affecting the flexibility of the experimental operations. The independence of the microprocessor driven area monitors guarantees a high reliability. Compared to conventional electronics the advantages of the system are its reliability and cost. (Author)

Fermilab advanced computer program multi-microprocessor project

International Nuclear Information System (INIS)

Nash, T.; Areti, H.; Biel, J.

1985-06-01

Fermilab's Advanced Computer Program is constructing a powerful 128 node multi-microprocessor system for data analysis in high-energy physics. The system will use commercial 32-bit microprocessors programmed in Fortran-77. Extensive software supports easy migration of user applications from a uniprocessor environment to the multiprocessor and provides sophisticated program development, debugging, and error handling and recovery tools. This system is designed to be readily copied, providing computing cost effectiveness of below $2200 per VAX 11/780 equivalent. The low cost, commercial availability, compatibility with off-line analysis programs, and high data bandwidths (up to 160 MByte/sec) make the system an ideal choice for applications to on-line triggers as well as an offline data processor

High-performance computing for airborne applications

International Nuclear Information System (INIS)

Quinn, Heather M.; Manuzatto, Andrea; Fairbanks, Tom; Dallmann, Nicholas; Desgeorges, Rose

2010-01-01

Recently, there has been attempts to move common satellite tasks to unmanned aerial vehicles (UAVs). UAVs are significantly cheaper to buy than satellites and easier to deploy on an as-needed basis. The more benign radiation environment also allows for an aggressive adoption of state-of-the-art commercial computational devices, which increases the amount of data that can be collected. There are a number of commercial computing devices currently available that are well-suited to high-performance computing. These devices range from specialized computational devices, such as field-programmable gate arrays (FPGAs) and digital signal processors (DSPs), to traditional computing platforms, such as microprocessors. Even though the radiation environment is relatively benign, these devices could be susceptible to single-event effects. In this paper, we will present radiation data for high-performance computing devices in a accelerated neutron environment. These devices include a multi-core digital signal processor, two field-programmable gate arrays, and a microprocessor. From these results, we found that all of these devices are suitable for many airplane environments without reliability problems.

Microprocessor-controlled CAMAC data link module

International Nuclear Information System (INIS)

Potter, J.M.

1978-05-01

Communication between the central control computer and remote, satellite data-acquisition/control stations at the Clinton P. Anderson Meson Physics Facility (LAMPF) is presently accomplished through the use of CAMAC-based Data Link modules. With the advent of the microprocessor, a new philosophy for digital data communications has evolved. Data Link modules containing microprocessor controllers provide link management and communication network protocol through algorithms executed in the Data Link microprocessor. 13 figures

High speed serial link for UA1 microprocessor network

International Nuclear Information System (INIS)

Cittolin, S.; Loefstedt, B.; Zurfluh, E.

1981-01-01

The UA1 data acquisition system consists of a set of distributed microprocessor units. An interprocessor link, independent of the CAMAC data readout, has been developed in order to have continuous remote control and run-time data handling, e.g. transmission of calibration programs/parameters, equipment rest/status and histogram accumulation. The data transmission system is designed to be used in a loop configuration equipped with transceivers for twisted pair cables (RS-422). As an economical system it is running as an ancillary serial loop-link between microprocessors Like Data Acquisition Crate Controllers and systems with distributed intelligence. The software driver consists of a loop-controller package, which may run in a BAMBI Computer Language environment and a fully interrupt controlled program for all other secondary stations. A special single-character mode provides a handy link for remote debugging in a pseudo-full-duplex mode. The format is based on the HDLC protocol without sequence numbering. The Chip MC-6854 from Motorola, Inc. enables an implementation with few components. (orig.)

Mold heating and cooling microprocessor conversion

Science.gov (United States)

Hoffman, D. P.

1995-07-01

Conversion of the microprocessors and software for the Mold Heating and Cooling (MHAC) pump package control systems was initiated to allow required system enhancements and provide data communications capabilities with the Plastics Information and Control System (PICS). The existing microprocessor-based control systems for the pump packages use an Intel 8088-based microprocessor board with a maximum of 64 Kbytes of program memory. The requirements for the system conversion were developed, and hardware has been selected to allow maximum reuse of existing hardware and software while providing the required additional capabilities and capacity. The new hardware will incorporate an Intel 80286-based microprocessor board with an 80287 math coprocessor, the system includes additional memory, I/O, and RS232 communication ports.

Microprocessor protection relays: new prospects or new problems?

OpenAIRE

Gurevich, Vladimir

2006-01-01

The internal architecture and principles of operation of microprocessor-based devices including so-called "microprocessor protective relays" have little in common with devices called "electric relays". But microprocessor-based relay protection devices are gradually driving out the traditional electromechanical and even electronic relay protection of virtually from all fields of power and electrical engineering. Advantages of microprocessor-based protection means over traditional ones are far ...

An INTEL 8080 microprocessor development system

International Nuclear Information System (INIS)

Horne, P.J.

1977-01-01

The INTEL 8080 has become one of the two most widely used microprocessors at CERN, the other being the MOTOROLA 6800. Even thouth this is the case, there have been, to date, only rudimentary facilities available for aiding the development of application programs for this microprocessor. An ideal development system is one which has a sophisticated editing and filing system, an assembler/compiler, and access to the microprocessor application. In many instances access to a PROM programmer is also required, as the application may utilize only PROMs for program storage. With these thoughts in mind, an INTEL 8080 microprocessor development system was implemented in the Proton Synchrotron (PS) Division. This system utilizes a PDP 11/45 as the editing and file-handling machine, and an MSC 8/MOD 80 microcomputer for assembling, PROM programming and debugging user programs at run time. The two machines are linked by an existing CAMAC crate system which will also provide the means of access to microprocessor applications in CAMAC and the interface of the development system to any other application. (Auth.)

Microprocessors in physics experiments at SLAC

International Nuclear Information System (INIS)

Rochester, L.S.

1981-01-01

The increasing size and complexity of high energy physics experiments is changing the way data are collected. To implement a trigger or event filter requires complex logic which may have to be modified as the experiment proceeds. Simply to monitor a detector, large amounts of data must be processed online. The use of microprocessors or other programmable devices can help to achieve these ends flexibly and economically. At SLAC, a number of microprocessor-based systems have been built and are in use in experimental setups, and others are now being developed. This talk is a review of existing systems and their use in experiments, and of developments in progress and future plans. (orig.)

Microprocessors in physics experiments at SLAC

International Nuclear Information System (INIS)

Rochester, L.S.

1981-04-01

The increasing size and complexity of high energy physics experiments is changing the way data are collected. To implement a trigger or event filter requires complex logic which may have to be modified as the experiment proceeds. Simply to monitor a detector, large amounts of data must be processed on line. The use of microprocessors or other programmable devices can help to achieve these ends flexibly and economically. At SLAC, a number of microprocessor-based systems have been built and are in use in experimental setups, and others are now being developed. This talk is a review of existing systems and their use in experiments, and of developments in progress and future plans

Microprocessor based systems for the higher technician

CERN Document Server

Vears, RE

2013-01-01

Microprocessor Based Systems for the Higher Technician provides coverage of the BTEC level 4 unit in Microprocessor Based Systems (syllabus U80/674). This book is composed of 10 chapters and concentrates on the development of 8-bit microcontrollers specifically constructed around the Z80 microprocessor. The design cycle for the development of such a microprocessor based system and the use of a disk-based development system (MDS) as an aid to design are both described in detail. The book deals with the Control Program Monitor (CP/M) operating system and gives background information on file hand

Microprocessor-based data acquisition systems for Hera experiments

International Nuclear Information System (INIS)

Haynes, W.J.

1989-09-01

Sophisticated multi-microprocessor configurations are envisaged to cope with the technical challenges of the HERA electron-proton collider and the high data rates from the two large experiments H1 and ZEUS. These lecture notes concentrate on many of the techniques employed, with much emphasis being placed on the use of the IEEE standard VMEbus as a unifying element. The role of modern 32-bit CISC and RISC microprocessors, in the handling of data and the filtering of physics information, is highlighted together with the integration of personal computer stations for monitoring and control. (author)

Radiation-hardened bulk Si-gate CMOS microprocessor family

International Nuclear Information System (INIS)

Stricker, R.E.; Dingwall, A.G.F.; Cohen, S.; Adams, J.R.; Slemmer, W.C.

1979-01-01

RCA and Sandia Laboratories jointly developed a radiation-hardened bulk Si-gate CMOS technology which is used to fabricate the CDP-1800 series microprocessor family. Total dose hardness of 1 x 10 6 rads (Si) and transient upset hardness of 5 x 10 8 rads (Si)/sec with no latch up at any transient level was achieved. Radiation-hardened parts manufactured to date include the CDP-1802 microprocessor, the CDP-1834 ROM, the CDP-1852 8-bit I/O port, the CDP-1856 N-bit 1 of 8 decoder, and the TCC-244 256 x 4 Static RAM. The paper is divided into three parts. In the first section, the basic fundamentals of the non-hardened C 2 L technology used for the CDP-1800 series microprocessor parts is discussed along with the primary reasons for hardening this technology. The second section discusses the major changes in the fabrication sequence that are required to produce radiation-hardened devices. The final section details the electrical performance characteristics of the hardened devices as well as the effects of radiation on device performance. Also included in this section is a discussion of the TCC-244 256 x 4 Static RAM designed jointly by RCA and Sandia Laboratories for this application

Small private key MQPKS on an embedded microprocessor.

Science.gov (United States)

Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

2014-03-19

Multivariate quadratic (MQ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to MQ cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key MQ scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key MQ scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing MQ on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key MQ scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES) accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012.

Small Private Key PKS on an Embedded Microprocessor

Science.gov (United States)

Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

2014-01-01

Multivariate quadratic ( ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES) accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012. PMID:24651722

Microprocessing in European High Energy Physics Experiments - ECFA Working Group on Data Processing Standards - Report of the Microprocessor Subgroup May 1982

CERN Document Server

European Committee for Future Accelerators (ECFA)

1982-01-01

This document contains two reports on the use of microprocessors in European High-Energy Physics experiments. The first is a presentation of data collected by a sub-group of the ECFA working group on data procesing standards. The working group is organised by E. Lillestol, University of Bergen and E.M. Rimmer, CERN, DD Division; the Microprocessor sub-group organiser is L.O. Hertzberger, NIKHEF, Amsterdam. Data are given from projects numbered 81 - 194, and some CERN projects are included. Even though there is some duplication of information, a second report has been appended which covers a wider range of CERN projects. This was the result of a microprocessor survey made at CERN by P. Scharff-Hansen, DD Division, at the request of E. Gabthuler. The ECFA working group intends to have reports for all the sub-groups (10 in number) available in machine-readable form at the CERN computer centre. However, it was felt that the information herein is most valuable to designers and users of microprocessors, and that it...

Energy conservation applications of microprocessors

Energy Technology Data Exchange (ETDEWEB)

Shih, James Y.

1979-07-01

A survey of the application of microprocessors for industrial and commercial energy conservation has been made. Microprocessor applications for HVAC, chiller control, and automotive equipment are discussed. A case study of successful replacement of a conventional cooling plant control is recounted. The rapid advancement of microelectronic technology will affect efficient energy control, more sophisticated control methodology, and more investment in controls.

A light-powered sub-threshold microprocessor

Energy Technology Data Exchange (ETDEWEB)

Liu Ming; Chen Hong; Zhang Chun; Li Changmeng; Wang Zhihua, E-mail: lium02@mails.tsinghua.edu.cn [Institute of Microelectronics, Tsinghua University, Beijing 100084 (China)

2010-11-15

This paper presents an 8-bit sub-threshold microprocessor which can be powered by an integrated photosensitive diode. With a custom designed sub-threshold standard cell library and 1 kbit sub-threshold SRAM design, the leakage power of 58 nW, dynamic power of 385 nW - 165 kHz, EDP 13 pJ/inst and the operating voltage of 350 mV are achieved. Under a light of about 150 kLux, the microprocessor can run at a rate of up to 500 kHz. The microprocessor can be used for wireless-sensor-network nodes.

Instrument for bone mineral measurement using a microprocessor as the control and arithmetic element

International Nuclear Information System (INIS)

Alberi, J.L.; Hardy, W.H. II.

1975-11-01

A self-contained instrument for the determination of bone mineral content by photon absorptometry is described. A high-resolution detection system allows measurements to be made at up to 16 photon energies. Control and arithmetic functions are performed by a microprocessor. Analysis capability and limitations are discussed

Design of microprocessor-based hardware for number theoretic transform implementation

Energy Technology Data Exchange (ETDEWEB)

Anwar Ahmed Shamim

1985-01-01

The Winograd (1976) Fourier Transform algorithm (WFTA) was implemented on a TMS9900 microprocessor to compute NTTs. Since multiplication conducted modulo m is very time consuming a special purpose external hardware modular multiplier was designed, constructed and interfaced with the TMS9900 microprocessor. This external hardware modular multiplier allowed an improvement in the transform execution time. Computation time may further be reduced by employing several microprocessors. Taking advantage of the inherent parallelism of the WFTA, a dedicated parallel microprocessor system was designed and constructed to implement a 15-point WFTA in parallel. Benchmark programs were written to choose a suitable microprocessor for the parallel microprocessor system. A master or a host microprocessor is used to control the parallel microprocessor system and provides an interface to the outside world. An analogue to digital (a/d) and a digital to analogue (d/a) converter allows real time digital signal processing.

G-cueing microcontroller (a microprocessor application in simulators)

Science.gov (United States)

Horattas, C. G.

1980-01-01

A g cueing microcontroller is described which consists of a tandem pair of microprocessors, dedicated to the task of simulating pilot sensed cues caused by gravity effects. This task includes execution of a g cueing model which drives actuators that alter the configuration of the pilot's seat. The g cueing microcontroller receives acceleration commands from the aerodynamics model in the main computer and creates the stimuli that produce physical acceleration effects of the aircraft seat on the pilots anatomy. One of the two microprocessors is a fixed instruction processor that performs all control and interface functions. The other, a specially designed bipolar bit slice microprocessor, is a microprogrammable processor dedicated to all arithmetic operations. The two processors communicate with each other by a shared memory. The g cueing microcontroller contains its own dedicated I/O conversion modules for interface with the seat actuators and controls, and a DMA controller for interfacing with the simulation computer. Any application which can be microcoded within the available memory, the available real time and the available I/O channels, could be implemented in the same controller.

Neutron beam irradiation study of workload dependence of SER in a microprocessor

Energy Technology Data Exchange (ETDEWEB)

Michalak, Sarah E [Los Alamos National Laboratory; Graves, Todd L [Los Alamos National Laboratory; Hong, Ted [STANFORD; Ackaret, Jerry [IBM; Sonny, Rao [IBM; Subhasish, Mitra [STANFORD; Pia, Sanda [IBM

2009-01-01

It is known that workloads are an important factor in soft error rates (SER), but it is proving difficult to find differentiating workloads for microprocessors. We have performed neutron beam irradiation studies of a commercial microprocessor under a wide variety of workload conditions from idle, performing no operations, to very busy workloads resembling real HPC, graphics, and business applications. There is evidence that the mean times to first indication of failure, MTFIF defined in Section II, may be different for some of the applications.

Small Private Key MQPKS on an Embedded Microprocessor

Directory of Open Access Journals (Sweden)

Hwajeong Seo

2014-03-01

Full Text Available Multivariate quadratic (MQ cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to MQ cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011, a small public key MQ scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key MQ scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing MQ on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key MQ scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012.

A realtime feedback microprocessor for the TEVATRON

International Nuclear Information System (INIS)

Herrup, D.A.; Chapman, L.; Franck, A.; Groves, T.; Lublinsky, B.

1993-01-01

A feedback microprocessor has been built for the TEVATRON. Its inputs are realtime accelerator measurements, data describing the state of the TEVATRON, and ramp tables. The microprocessor includes a finite state machine. Each state corresponds to a specific TEVATRON operation. Transitions between states are initiated by the global TEVATRON clock. Each state includes a cyclic routine which is called periodically and where all calculations are performed. The output corrections are inserted onto a fast TEVATRON-wide link from which the power supplies will read the realtime correction. The authors also store all of the input data and output corrections in a set of buffers which can easily be retrieved for diagnostic analysis. This talk will describe use of this device to control the TEVATRON tunes and discuss other uses

Multiple microprocessor based nuclear reactor power monitor

International Nuclear Information System (INIS)

Lewis, P.S.; Ethridge, C.D.

1979-01-01

The reactor power monitor is a portable multiple-microprocessor controlled data acquisition device being built for the International Atomic Energy Association. Its function is to measure and record the hourly integrated operating thermal power level of a nuclear reactor for the purpose of detecting unannounced plutonium production. The monitor consists of a 3 He proportional neutron detector, a write-only cassette tape drive and control electronics based on two INTEL 8748 microprocessors. The reactor power monitor operates from house power supplied by the plant operator, but has eight hours of battery backup to cover power interruptions. Both the hourly power levels and any line power interruptions are recorded on tape and in memory. Intermediate dumps from the memory to a data terminal or strip chart recorder can be performed without interrupting data collection

Microprocessor controller for stepping motors

International Nuclear Information System (INIS)

Strait, B.G.; Thuot, M.E.

1977-01-01

A new concept for digital computer control of multiple stepping motors which operate in a severe electromagnetic pulse environment is presented. The motors position mirrors in the beam-alignment system of a 100-kJ CO 2 laser. An asynchronous communications channel of a computer is used to send coded messages, containing the motor address and stepping-command information, to the stepping-motor controller in a bit serial format over a fiber-optics communications link. The addressed controller responds by transmitting to the computer its address and other motor information, thus confirming the received message. Each controller is capable of controlling three stepping motors. The controller contains the fiber-optics interface, a microprocessor, and the stepping-motor driven circuits. The microprocessor program, which resides in an EPROM, decodes the received messages, transmits responses, performs the stepping-motor sequence logic, maintains motor-position information, and monitors the motor's reference switch. For multiple stepping-motor application, the controllers are connected in a daisy chain providing control of many motors from one asynchronous communications channel of the computer

A feedback microprocessor for hadron colliders

International Nuclear Information System (INIS)

Herrup, D.A.; Chapman, L.; Franck, A.; Groves, T.; Lublinsky, B.

1992-12-01

A feedback microprocessor has been built for the TEVATRON. It has been constructed to be applicable to hadron colliders in general. Its inputs are realtime accelerator measurements, data describing the state of the TEVATRON, and ramp tables. The microprocessor software includes a finite state machine. Each state corresponds to a specific TEVATRON operation and has a state-specific TEVATRON model. Transitions between states are initiated by the global TEVATRON clock. Each state includes a cyclic routine which is called periodically and where all calculations are performed. The output corrections are inserted onto a fast TEVATRON-wide link from which the power supplies will read the realtime corrections. We also store all of the input data and output corrections in a set of buffers which can easily be retrieved for diagnostic analysis. In this paper we will describe this device and its use to control the TEVATRON tunes as well as other possible applications

High Performance Computing in Science and Engineering '02 : Transactions of the High Performance Computing Center

CERN Document Server

Jäger, Willi

2003-01-01

This book presents the state-of-the-art in modeling and simulation on supercomputers. Leading German research groups present their results achieved on high-end systems of the High Performance Computing Center Stuttgart (HLRS) for the year 2002. Reports cover all fields of supercomputing simulation ranging from computational fluid dynamics to computer science. Special emphasis is given to industrially relevant applications. Moreover, by presenting results for both vector sytems and micro-processor based systems the book allows to compare performance levels and usability of a variety of supercomputer architectures. It therefore becomes an indispensable guidebook to assess the impact of the Japanese Earth Simulator project on supercomputing in the years to come.

Microprocessorized NMR measurement

International Nuclear Information System (INIS)

Rijllart, A.

1984-01-01

An MC68000 CAMAC microprocessor system for fast and accurate NMR signal measurement will be presented. A stand-alone CAMAC microprocessor system (MC68000 STAC) with a special purpose interface sweeps a digital frequency synthesizer and digitizes the NMR signal with a 16-bit ADC of 17 μs conversion time. It averages the NMR signal data over many sweeps and then transfers it through CAMAC to a computer for calculation of the signal parameters. The computer has full software control over the timing and sweep settings of this signal averager, and thus allows optimization of noise suppression. Several of these processor systems can be installed in the same crate for parallel processing, and the flexibility of the STAC also allows easy adaptation to other applications such as transient recording or phase-sensitive detection. (orig.)

Multi-core Microprocessors

Indian Academy of Sciences (India)

Based on empirical data, Gordon Moore .... there are numerous models of the same Intel microprocessor such as Pentium. 3). ... returns. The limit on instruction and thread-level processing coupled with ..... This style of parallel programming is.

Microprocessor multi-task monitor

International Nuclear Information System (INIS)

Ludemann, C.A.

1983-01-01

This paper describes a multi-task monitor program for microprocessors. Although written for the Intel 8085, it incorporates features that would be beneficial for implementation in other microprocessors used in controlling and monitoring experiments and accelerators. The monitor places permanent programs (tasks) arbitrarily located throughout ROM in a priority ordered queue. The programmer is provided with the flexibility to add new tasks or modified versions of existing tasks, without having to comply with previously defined task boundaries or having to reprogram all of ROM. Scheduling of tasks is triggered by timers, outside stimuli (interrupts), or inter-task communications. Context switching time is of the order of tenths of a milllisecond

Microprocessor Protection of Power Reducing Transformers

OpenAIRE

F. A. Romanuk; S. P. Korolev; M. S. Loman

2011-01-01

The paper contains analysis of advantages and disadvantages of existing differential protection terminals of power reducing transformers. The paper shows that there are good reasons to develop microprocessor protection of power reducing transformer which contains required functions and settings and which is based on Belarusian principles of relay protection system construction. The paper presents functional structure of microprocessor terminal of power reducing transformer which is developed. 

''NICRO'' microprogramming language for sectional microprocessors

International Nuclear Information System (INIS)

Semenov, Yu.A.; Chudakov, V.N.

1982-01-01

''MICRO'' microprogramming input language developed for sectional microprocessors is described. The structure of micromanual, purpose of particular fields, the corresponding mne-- mocodes and requirements they have to meet are considered. Program for integer division with a sign written in the ''MICRO'' language is given as an example. The possibilities of modif ying the translator for its adaptation to different types of processor and microprocessor sets are analyzed

Microprocessor Protection of Power Reducing Transformers

Directory of Open Access Journals (Sweden)

F. A. Romanuk

2011-01-01

Full Text Available The paper contains analysis of advantages and disadvantages of existing differential protection terminals of power reducing transformers. The paper shows that there are good reasons to develop microprocessor protection of power reducing transformer which contains required functions and settings and which is based on Belarusian principles of relay protection system construction. The paper presents functional structure of microprocessor terminal of power reducing transformer which is developed. 

Introduction to 6800/6802 microprocessor systems hardware, software and experimentation

CERN Document Server

Simpson, Robert J

1987-01-01

Introduction to 6800/6802 Microprocessor Systems: Hardware, Software and Experimentation introduces the reader to the features, characteristics, operation, and applications of the 6800/6802 microprocessor and associated family of devices. Many worked examples are included to illustrate the theoretical and practical aspects of the 6800/6802 microprocessor.Comprised of six chapters, this book begins by presenting several aspects of digital systems before introducing the concepts of fetching and execution of a microprocessor instruction. Details and descriptions of hardware elements (MPU, RAM, RO

Process control by microprocessors

Energy Technology Data Exchange (ETDEWEB)

Arndt, W [ed.

1978-12-01

Papers from the workshop Process Control by Microprocessors being organized by the Karlsruhe Nuclear Research Center, Project PDV, together with the VDI/VDE-Gesellschaft fuer Mess- und Regelungstechnik are presented. The workshop was held on December 13 and 14, 1978 at the facilities of the Nuclear Research Center. The papers are arranged according to the topics of the workshop; one chapter deals with today's state of the art of microprocessor hardware and software technology; 5 chapters are dedicated to applications. The report also contains papers which will not be presented at the workshop. Both the workshop and the report are expected to improve and distribute the know-how about this modern technology.

Design analysis and microprocessor based control of a nuclear reactor

International Nuclear Information System (INIS)

Sabbakh, N.J.

1988-01-01

The object of this thesis is to design and test a microprocessor based controller, to a simulated nuclear reactor system. The mathematical model that describes the dynamics of a typical nuclear reactor of one group of delayed neutrons approximations with temperature feedback was chosen. A digital computer program has been developed for the design and analysis of a simulated model based on the concept of state-variable feedback in order to meet a desired system response with maximum overshoot of 3.4% and setting time of 4 sec. The state variable feedback coefficients are designed for the continuous system, then an approximation is used to obtain in the state variable feedback vector for the discrete system. System control was implemented utilizing Direct Digital Control (DDC) of a nuclear reactor simulated model through a control algorithm that was performed by means of a microprocessor based system. The controller performance was satisfactorily tested by exciting the reactor system with a transient reactivity disturbance and by a step change in power demand. Direct digital control, when implemented on a microprocessor adds versatility, flexibility in system design with the added advantage of possible use of optimal control algorithms. 6 tabs.; 30 figs.; 46 refs.; 6 apps

Microprocessor Controlled Maximum Power Point Tracker for Photovoltaic Application

International Nuclear Information System (INIS)

Jiya, J. D.; Tahirou, G.

2002-01-01

This paper presents a microprocessor controlled maximum power point tracker for photovoltaic module. Input current and voltage are measured and multiplied within the microprocessor, which contains an algorithm to seek the maximum power point. The duly cycle of the DC-DC converter, at which the maximum power occurs is obtained, noted and adjusted. The microprocessor constantly seeks for improvement of obtained power by varying the duty cycle

Flexible nanoscale high-performance FinFETs

KAUST Repository

Sevilla, Galo T.

2014-10-28

With the emergence of the Internet of Things (IoT), flexible high-performance nanoscale electronics are more desired. At the moment, FinFET is the most advanced transistor architecture used in the state-of-the-art microprocessors. Therefore, we show a soft-etch based substrate thinning process to transform silicon-on-insulator (SOI) based nanoscale FinFET into flexible FinFET and then conduct comprehensive electrical characterization under various bending conditions to understand its electrical performance. Our study shows that back-etch based substrate thinning process is gentler than traditional abrasive back-grinding process; it can attain ultraflexibility and the electrical characteristics of the flexible nanoscale FinFET show no performance degradation compared to its rigid bulk counterpart indicating its readiness to be used for flexible high-performance electronics.

CAMAC based computer--computer communications via microprocessor data links

International Nuclear Information System (INIS)

Potter, J.M.; Machen, D.R.; Naivar, F.J.; Elkins, E.P.; Simmonds, D.D.

1976-01-01

Communications between the central control computer and remote, satellite data acquisition/control stations at The Clinton P. Anderson Meson Physics Facility (LAMPF) is presently accomplished through the use of CAMAC based Data Link Modules. With the advent of the microprocessor, a new philosophy for digital data communications has evolved. Data Link modules containing microprocessor controllers provide link management and communication network protocol through algorithms executed in the Data Link microprocessor

SNOOP module CAMAC interface to the 168/E microprocessor

International Nuclear Information System (INIS)

Bernstein, D.; Carroll, J.T.; Mitnick, V.H.; Paffrath, L.; Parker, D.B.

1979-10-01

A pair of 168/E microprocessors will be used to meet the realtime computing requirements of the SLAC Hybrid Facility. A SNOOP module and 168/E Interface provide the link between the host computer and the microprocessors. By eavesdropping on normal CAMAC read operations, the SNOOP provides a direct data transfer from CAMAC to microprocessor memory. The host computer controls the processors using standard CAMAC programmed I/O to the SNOOP

Recent applications of microprocessor-based instruments in nuclear power stations

International Nuclear Information System (INIS)

Cash, N.R.; Dennis, U.E.

1988-01-01

The incorporation of microprocessors in the design of nuclear power plant instrumentation has led to levels of measurement and control not available previously. In addition to the expected expansion of functional (system) capability, numerous desirable features now are possible. The added ability to both self-calibrate and perform compensation algorithms has led to dramatic improvements in accuracies, response times, and noise rejection. Automated performance checking and self-testing simplify troubleshooting and required periodic surveillance. Alphanumeric displays allow both menu-driven operation and user-prompting, which, in turn, contribute to mistake avoidance. New features of these microprocessor-based instruments are of specific benefit in nuclear power reactors, were safety is of prime concern. Greater reliability and accuracy can be provided. Shortened calibration, surveillance, and repair times reduce the exposure to unnecessary challenges of the plant's protection systems that can arise from spurious noise signals

A new design approach for control circuits of pipelined single-flux-quantum microprocessors

International Nuclear Information System (INIS)

Yamanashi, Y; Akimoto, A; Yoshikawa, N; Tanaka, M; Kawamoto, T; Kamiya, Y; Fujimaki, A; Terai, H; Yorozu, S

2006-01-01

A novel method of design for controllers of pipelined microprocessors using single-flux-quantum (SFQ) logic has been proposed. The proposed design approach is based on one hot encoding and is very suitable for designing a finite state machine using SFQ logic circuits, where each internal state of the microprocessor is represented by a flip-flop. In this approach, decoding of the internal state can be performed instantaneously, in contrast to the case in the conventional method using a binary state register. Moreover, pipelining is effectively implemented without increasing the circuit size because no pipeline registers are required in the one hot encoding. By using this method, we have designed a controller for our new SFQ microprocessors, which employs pipelining. The number of Josephson junctions of the newly designed controller is 1067, while the previous version without pipelining contains 1721 Josephson junctions. These results indicate that the proposed design approach is very effective for pipelined SFQ microprocessors. We have implemented a new controller using the NEC 2.5 kA cm -2 Nb standard process and confirmed its correct operation experimentally

Microprocessor system design a practical introduction

CERN Document Server

Spinks, Michael J

2013-01-01

Microprocessor System Design: A Practical Introduction describes the concepts and techniques incorporated into the design of electronic circuits, particularly microprocessor boards and their peripherals. The book reviews the basic building blocks of the electronic systems composed of digital (logic levels, gate output circuitry) and analog components (resistors, capacitors, diodes, transistors). The text also describes operational amplifiers (op-amp) that use a negative feedback technique to improve the parameters of the op-amp. The design engineer can use programmable array logic (PAL) to rep

Proceedings of the meeting on applications of microprocessors in accelerator controls and physics experiments, Tsukuba, March 15, 1978

International Nuclear Information System (INIS)

Shibata, Shinkichi; Katoh, Tadahiko

1978-05-01

The microprocessor was first made public in 1971. In the ensuing few years, its performance has risen, cost lowered and interface more in IC, so it is now easily incorporated in instrumentation and control. Since it is used as electronic component unlike the case of a minicomputer, it has so much larger influence. It differs from the conventional electronic components in that software is required. In the National Laboratory for High Energy Physics, microprocessors are used for performance improvements of the measuring and control instruments and for labor saving. For new component not to induce new other problems, support system and standardization are proceeding for utilization development etc. The present meeting was intended for discussions by people in the field of usage, planning, and means of joint uses for software and hardware. (Mori, K.)

Microprocessor-controlled scanning densitometer system

International Nuclear Information System (INIS)

Shurtliff, R.W.

1980-04-01

An Automated Scanning Densitometer System has been developed by uniting a microprocessor with a low energy x-ray densitometer system. The microprocessor controls the detector movement, provides self-calibration, compensates raw readings to provide time-linear output, controls both data storage and the host computer interface, and provides measurement output in engineering units for immediate reading. The densitometer, when used in a scanning mode, is a precision reference instrument that provides chordal average density measurements over the cross section of a pipe under steady-state flow conditions. Results have shown an improvement over the original densitometer in reliability and repeatability of the system, an a factor-of-five improvement in accuracy

The engineering of microprocessor systems guidelines on system development

CERN Document Server

1979-01-01

The Engineering of Microprocessor Systems: Guidelines on System Development provides economical and technical guidance for use when incorporating microprocessors in products or production processes and assesses the alternatives that are available. This volume is part of Project 0251 undertaken by The Electrical Research Association, which aims to give managers and development engineers advice and comment on the development process and the hardware and software needed to support the engineering of microprocessor systems. The results of Phase 1 of the five-phase project are contained in this fir

Microprocessor Activity Controls Differential miRNA Biogenesis In Vivo

Directory of Open Access Journals (Sweden)

Thomas Conrad

2014-10-01

Full Text Available In miRNA biogenesis, pri-miRNA transcripts are converted into pre-miRNA hairpins. The in vivo properties of this process remain enigmatic. Here, we determine in vivo transcriptome-wide pri-miRNA processing using next-generation sequencing of chromatin-associated pri-miRNAs. We identify a distinctive Microprocessor signature in the transcriptome profile from which efficiency of the endogenous processing event can be accurately quantified. This analysis reveals differential susceptibility to Microprocessor cleavage as a key regulatory step in miRNA biogenesis. Processing is highly variable among pri-miRNAs and a better predictor of miRNA abundance than primary transcription itself. Processing is also largely stable across three cell lines, suggesting a major contribution of sequence determinants. On the basis of differential processing efficiencies, we define functionality for short sequence features adjacent to the pre-miRNA hairpin. In conclusion, we identify Microprocessor as the main hub for diversified miRNA output and suggest a role for uncoupling miRNA biogenesis from host gene expression.

Microprocessor based data acquisition system for Moessbauer spectrometer

International Nuclear Information System (INIS)

Patwardhan, P.K.; Indurkar, V.S.

1981-01-01

A data acquisition system, for Moessbauer spectrometer and other probability distribution spectrum is described. This utilizes the advantages of incorporating a microcomputer for providing a flexible analytical capability and speed of hard wired MCS unit updating channel contents in DMA. Holbourn, Player and Woodhams have recently described a microprocessor controlled Moessbauer spectrometer where microprocessor performs the task of updating channel contents, requiring about 60 micro seconds in interrupt mode. This imposes restrictions on increasing the channel number and on increasing the velocity scan frequency in order to cover higher velocity ranges. The system described in this article performs data acquisition in faster direct memory access. It is a two module system, (1) MCS module (2) Microcomputer module, arranged around a common address, data and control buses. The microcomputer module has an access to the system data during flyback periods and can be programmed for the task of monitor on progess of experiment and as a manipulator of various control operations needed during experiment. The system firmware includes: (1) MONITOR (2) BLOCK-TRANSFER (3) DATA-SMOOTHING (4) DECIMAL-CONVERTER (5) MATH. The scope of this firmware is briefly described. (author)

Microprocessor event analysis in parallel with Camac data acquisition

International Nuclear Information System (INIS)

Cords, D.; Eichler, R.; Riege, H.

1981-01-01

The Plessey MIPROC-16 microprocessor (16 bits, 250 ns execution time) has been connected to a Camac System (GEC-ELLIOTT System Crate) and shares the Camac access with a Nord-1OS computer. Interfaces have been designed and tested for execution of Camac cycles, communication with the Nord-1OS computer and DMA-transfer from Camac to the MIPROC-16 memory. The system is used in the JADE data-acquisition-system at PETRA where it receives the data from the detector in parallel with the Nord-1OS computer via DMA through the indirect-data-channel mode. The microprocessor performs an on-line analysis of events and the result of various checks is appended to the event. In case of spurious triggers or clear beam gas events, the Nord-1OS buffer will be reset and the event omitted from further processing. (orig.)

Leak detection system with distributed microprocessor in the primary containment vessel

International Nuclear Information System (INIS)

Inahara, K.; Yoshioka, K.; Tomizawa, T.

1980-01-01

Responding to the demand for greater improvements of the safety monitoring system, less public radiation exposure, and increase of plant availability, measuring and control systems in nuclear power plants have undergone many improvements. Leak detection systems are also required to give earlier warning, additional accuracy, and continuous monitoring function. This paper describes the drywell sump leakage detection system utilizing a distributed microprocessor, which is a successful application owing to its versatile function and ease of installation. The microprocessor performs various functions such as a rate of level change computation, conversion to leakage flow rate, initiation of alarm, and sump pump control. This system has already been applied to three operating BWR plants that demonstrate its efficiency. (auth)

An integrated high performance Fastbus slave interface

International Nuclear Information System (INIS)

Christiansen, J.; Ljuslin, C.

1993-01-01

A high performance CMOS Fastbus slave interface ASIC (Application Specific Integrated Circuit) supporting all addressing and data transfer modes defined in the IEEE 960 - 1986 standard is presented. The FAstbus Slave Integrated Circuit (FASIC) is an interface between the asynchronous Fastbus and a clock synchronous processor/memory bus. It can work stand-alone or together with a 32 bit microprocessor. The FASIC is a programmable device enabling its direct use in many different applications. A set of programmable address mapping windows can map Fastbus addresses to convenient memory addresses and at the same time act as address decoding logic. Data rates of 100 MBytes/sec to Fastbus can be obtained using an internal FIFO in the FASIC to buffer data between the two buses during block transfers. Message passing from Fastbus to a microprocessor on the slave module is supported. A compact (70 mm x 170 mm) Fastbus slave piggy back sub-card interface including level conversion between ECL and TTL signal levels has been implemented using surface mount components and the 208 pin FASIC chip

The HXR80M-balloon experiment: a microprocessor-controlled transatlantic payload

International Nuclear Information System (INIS)

Ubertini, P.; Bazzano, A.; Boccaccini, L.

1980-01-01

Following the results obtained from the succesful transatlantic flight launched during the summer 1976 from the CNR Milo Base, Sicily, the Laboratorio di Astrofisica Spaziale has started a new program in the hard X-ray astronomy field. It basically consists in the development of high resolution large area Multiwire Proportional Chambers to be employed in long duration balloon flights to study and monitor galactic and extragalactic sources. This note will describe the flight configuration and performances of the HXR80M payload. The experiment is expected to fly during July 1980 from the Milo Base in the framework of the CNR experimental balloon campaign. The note will analyze the main characteristics of the detectors employed, of the data handling electronics and in particular of the hardware and the software of the on-board microprocessor controlled multichannel analyzer. In fact the limitation due to the low bit rate HF link (1.2kbit/s) and the long flight duration (about one week) make imperative the use of an on-board microprocessor system to handle and select in real time the scientific data and to control the housekeeping and the telecommand systems

Use of a microprocessor in a remote working level monitor

International Nuclear Information System (INIS)

Keffe, D.J.; McDowell, W.P.; Groer, P.G.

1975-01-01

A remote working level monitor was designed to measure short-lived radon-daughter concentrations in sealed chambers having potentially high radiation levels (up to 2000 WL). The system is comprised of surface barrier detectors, multiplexer and buffers, microprocessor and teletype

Microprocessor event analysis in parallel with CAMAC data acquisition

CERN Document Server

Cords, D; Riege, H

1981-01-01

The Plessey MIPROC-16 microprocessor (16 bits, 250 ns execution time) has been connected to a CAMAC System (GEC-ELLIOTT System Crate) and shares the CAMAC access with a Nord-10S computer. Interfaces have been designed and tested for execution of CAMAC cycles, communication with the Nord-10S computer and DMA-transfer from CAMAC to the MIPROC-16 memory. The system is used in the JADE data-acquisition-system at PETRA where it receives the data from the detector in parallel with the Nord-10S computer via DMA through the indirect-data-channel mode. The microprocessor performs an on-line analysis of events and the results of various checks is appended to the event. In case of spurious triggers or clear beam gas events, the Nord-10S buffer will be reset and the event omitted from further processing. (5 refs).

Application of microprocessor based controller in the Breeder Reactor Program

International Nuclear Information System (INIS)

Messick, N.C.; Lukas, M.P.

1985-01-01

This paper treats Argonne National Laboratory's experience using microprocessor based controllers presently in use on several control loops within the EBR-II reactor facility as well as tests being performed by these controllers. Also included is a discussion of the expandability, modularity, range of capabilities and higher level functions possible using such equipment

Regulation of Plant Microprocessor Function in Shaping microRNA Landscape

Directory of Open Access Journals (Sweden)

Jakub Dolata

2018-06-01

Full Text Available MicroRNAs are small molecules (∼21 nucleotides long that are key regulators of gene expression. They originate from long stem–loop RNAs as a product of cleavage by a protein complex called Microprocessor. The core components of the plant Microprocessor are the RNase type III enzyme Dicer-Like 1 (DCL1, the zinc finger protein Serrate (SE, and the double-stranded RNA binding protein Hyponastic Leaves 1 (HYL1. Microprocessor assembly and its processing of microRNA precursors have been reported to occur in discrete nuclear bodies called Dicing bodies. The accessibility of and modifications to Microprocessor components affect microRNA levels and may have dramatic consequences in plant development. Currently, numerous lines of evidence indicate that plant Microprocessor activity is tightly regulated. The cellular localization of HYL1 is dependent on a specific KETCH1 importin, and the E3 ubiquitin ligase COP1 indirectly protects HYL1 from degradation in a light-dependent manner. Furthermore, proper localization of HYL1 in Dicing bodies is regulated by MOS2. On the other hand, the Dicing body localization of DCL1 is regulated by NOT2b, which also interacts with SE in the nucleus. Post-translational modifications are substantial factors that contribute to protein functional diversity and provide a fine-tuning system for the regulation of protein activity. The phosphorylation status of HYL1 is crucial for its activity/stability and is a result of the interplay between kinases (MPK3 and SnRK2 and phosphatases (CPL1 and PP4. Additionally, MPK3 and SnRK2 are known to phosphorylate SE. Several other proteins (e.g., TGH, CDF2, SIC, and RCF3 that interact with Microprocessor have been found to influence its RNA-binding and processing activities. In this minireview, recent findings on the various modes of Microprocessor activity regulation are discussed.

High-Performance Computing Paradigm and Infrastructure

CERN Document Server

Yang, Laurence T

2006-01-01

With hyperthreading in Intel processors, hypertransport links in next generation AMD processors, multi-core silicon in today's high-end microprocessors from IBM and emerging grid computing, parallel and distributed computers have moved into the mainstream

Application of microprocessors to radiation protection measurements

International Nuclear Information System (INIS)

Zappe, D.; Meldes, C.

1982-01-01

In radiation protection measurements signals from radiation detectors or dosemeters have to be transformed into quantities relevant to radiation protection. In most cases this can only be done by taking into account various parameters (e.g. the quality factor). Moreover, the characteristics of the statistical laws of nuclear radiation emission have to be considered. These problems can properly be solved by microprocessors. After reviewing the main properties of microprocessors, some typical examples of applying them to problems of radiation protection measurement are given. (author)

An integrated high performance fastbus slave interface

International Nuclear Information System (INIS)

Christiansen, J.; Ljuslin, C.

1992-01-01

A high performance Fastbus slave interface ASIC is presented. The Fastbus slave integrated circuit (FASIC) is a programmable device, enabling its direct use in many different applications. The FASIC acts as an interface between Fastbus and a 'standard' processor/memory bus. It can work stand-alone or together with a microprocessor. A set of address mapping windows can map Fastbus addresses to convenient memory addresses and at the same time act as address decoding logic. Data rates of 100 MBytes/s to Fastbus can be obtained using an internal FIFO buffer in the FASIC. (orig.)

Front-end data processing using the bit-sliced microprocessor

International Nuclear Information System (INIS)

Machen, D.R.

1979-01-01

A state-of-the-art computing device, based upon the high-speed bit-sliced microprocessor, was developed into hardware for front-end data processing in both control and experiment applications at the Los Alamos Scientific Laboratory. The CAMAC Instrumentation Standard provides the framework for the high-speed hardware, allowing data acquisition and processing to take place at the data source in a CAMAC crate. 5 figures

FPGAs Emulate Microprocessors-A Successful Case for HFC NPP Digital I and C Upgrade

International Nuclear Information System (INIS)

Hsu, Allen; Crow, Ivan; Reese, Carl; Kim, Jong; Yang, Steve

2014-01-01

Field Programmable Gate Arrays (FPGAs), as programmable logic devices (PLDs) have gained a great deal of interests for implementing safety I and C applications in nuclear power plants (NPPs) largely owing to the FPGAs'potential advantage over the currently more common microprocessor-based digital I and C applications. First of all, FPGAs have adequate capabilities for most digital I and C applications in NPPs. Secondly, FPGAs provide products with longer lifetime, improve testability, and reduce the drift which occurs in analog-based systems, from hardware perspective. Thirdly, FPGAs, from software perspective, can be made simpler, less reliant on complex software such as operating systems, which should make FPGAs easier to qualify for nuclear safety applications. Fourthly, FPGAs are less vulnerable to cyber attacks when FPGAs implement the I and C systems that do not contain high-level, general purpose software that may be easily subjected to malicious modifications. Finally, FPGAs can bring cost reduction in an I and C digital upgrade because FPGAs can provide simpler licensing process than microprocessor-based digital I and C, and FPGAs can be implemented more efficiently. This paper will present one successful case for YGN Unit I and C upgrade using FPGA-based components to replace the obsolete Intel 8085 Microprocessor-based controllers. In this case, FPGAs emulated the process of the existing microprocessors and interpreted the execution of CPU processing. More than 160 of the FPGA-based SBC-01 controllers replacing the Intel 8085 Microprocessor-based Printed Circuit Boards have been installed and running successfully for safety I and C applications over the last five years. In this upgrade, the new FPGA-based controller board SBC-01 emulated the functions of Intel 8085 microprocessor correctly. It is a successful and cost-effective upgrade.vIn this paper, lifecycle design and implementation process and rigorous V and V activities that were used in the

FPGAs Emulate Microprocessors-A Successful Case for HFC NPP Digital I and C Upgrade

Energy Technology Data Exchange (ETDEWEB)

Hsu, Allen; Crow, Ivan; Reese, Carl; Kim, Jong; Yang, Steve [Doosan HF Controls Corp, Carrollton (United States)

2014-08-15

Field Programmable Gate Arrays (FPGAs), as programmable logic devices (PLDs) have gained a great deal of interests for implementing safety I and C applications in nuclear power plants (NPPs) largely owing to the FPGAs'potential advantage over the currently more common microprocessor-based digital I and C applications. First of all, FPGAs have adequate capabilities for most digital I and C applications in NPPs. Secondly, FPGAs provide products with longer lifetime, improve testability, and reduce the drift which occurs in analog-based systems, from hardware perspective. Thirdly, FPGAs, from software perspective, can be made simpler, less reliant on complex software such as operating systems, which should make FPGAs easier to qualify for nuclear safety applications. Fourthly, FPGAs are less vulnerable to cyber attacks when FPGAs implement the I and C systems that do not contain high-level, general purpose software that may be easily subjected to malicious modifications. Finally, FPGAs can bring cost reduction in an I and C digital upgrade because FPGAs can provide simpler licensing process than microprocessor-based digital I and C, and FPGAs can be implemented more efficiently. This paper will present one successful case for YGN Unit I and C upgrade using FPGA-based components to replace the obsolete Intel 8085 Microprocessor-based controllers. In this case, FPGAs emulated the process of the existing microprocessors and interpreted the execution of CPU processing. More than 160 of the FPGA-based SBC-01 controllers replacing the Intel 8085 Microprocessor-based Printed Circuit Boards have been installed and running successfully for safety I and C applications over the last five years. In this upgrade, the new FPGA-based controller board SBC-01 emulated the functions of Intel 8085 microprocessor correctly. It is a successful and cost-effective upgrade.vIn this paper, lifecycle design and implementation process and rigorous V and V activities that were used in the

Future microprocessor farms: Offline and online

International Nuclear Information System (INIS)

Areti, H.

1990-01-01

Microprocessor farms have been successfully employed in high energy physics for both offline analysis and online triggers. As the experiments continue to grow in size, so do the demands for processing power. The preliminary indications are that the large collider experiments will require at least a million VAX-11/780 equivalents of processing power for online trigger decisions and offline event reconstruction. This paper examines the current technology trends and projects the processing power that may be expected with the current farm architectures. 3 refs., 6 figs

A microprocessor based picture analysis system for automatic track measurements

International Nuclear Information System (INIS)

Heinrich, W.; Trakowski, W.; Beer, J.; Schucht, R.

1982-01-01

In the last few years picture analysis became a powerful technique for measurements of nuclear tracks in plastic detectors. For this purpose rather expensive commercial systems are available. Two inexpensive microprocessor based systems with different resolution were developed. The video pictures of particles seen through a microscope are digitized in real time and the picture analysis is done by software. The microscopes are equipped with stages driven by stepping motors, which are controlled by separate microprocessors. A PDP 11/03 supervises the operation of all microprocessors and stores the measured data on its mass storage devices. (author)

General-purpose microprocessor-based control chassis

International Nuclear Information System (INIS)

Halbig, J.K.; Klosterbuer, S.F.; Swenson, D.A.

1979-12-01

The objective of the Pion Generation for Medical Irradiations (PIGMI) program at the Los Alamos Scientific Laboratory is to develop the technology to build smaller, less expensive, and more reliable proton linear accelerators for medical applications. For this program, a powerful, simple, inexpensive, and reliable control and data acquisition system was developed. The system has a NOVA 3D computer with a real time disk-operating system (RDOS) that communicates with distributed microprocessor-based controllers which directly control data input/output chassis. At the heart of the controller is a microprocessor crate which was conceived at the Fermi National Accelerator Laboratory. This idea was applied to the design of the hardware and software of the controller

Satisfying STEM Education Using the Arduino Microprocessor in C Programming

Science.gov (United States)

Hoffer, Brandyn M.

There exists a need to promote better Science Technology Engineering and Math (STEM) education at the high school level. To satisfy this need a series of hands-on laboratory assignments were created to be accompanied by 2 educational trainers that contain various electronic components. This project provides an interdisciplinary, hands-on approach to teaching C programming that meets several standards defined by the Tennessee Board of Education. Together the trainers and lab assignments also introduce key concepts in math and science while allowing students hands-on experience with various electronic components. This will allow students to mimic real world applications of using the C programming language while exposing them to technology not currently introduced in many high school classrooms. The developed project is targeted at high school students performing at or above the junior level and uses the Arduino Mega open-source Microprocessor and software as the primary control unit.

Microprocessor based mobile radiation survey system

International Nuclear Information System (INIS)

Gilbert, R.W.; McCormack, W.D.

1983-12-01

A microprocessor-based system has been designed and constructed to enhance the performance of routine radiation surveys on roads within the Hanford site. This device continually monitors system performance and output from four sodium iodide detectors mounted on the rear bumper of a 4-wheel drive truck. The gamma radiation count rate in counts-per-second is monitored, and a running average computed, with the results compared to predefined limits. If an abnormal instantaneous or average count rate is detected, an alarm is sounded with responsible data displayed on a liquid crystal panel in the cab of the vehicle. The system also has the capability to evaluate detector output using multiple time constants and to perform more complex tests and comparison of the data. Data can be archived for later analysis on conventional chart recorders or stored in digital form on magnetic tape or other digital storage media. 4 figures

Microprocessor tester for the treat upgrade reactor trip system

International Nuclear Information System (INIS)

Lenkszus, F.R.; Bucher, R.G.

1984-01-01

The upgrading of the Transient Reactor Test (TREAT) Facility at ANL-Idaho has been designed to provide additional experimental capabilities for the study of core disruptive accident (CDA) phenomena. In addition, a programmable Automated Reactor Control System (ARCS) will permit high-power transients up to 11,000 MW having a controlled reactor period of from 15 to 0.1 sec. These modifications to the core neutronics will improve simulation of LMFBR accident conditions. Finally, a sophisticated, multiply-redundant safety system, the Reactor Trip System (RTS), will provide safe operation for both steady state and transient production operating modes. To insure that this complex safety system is functioning properly, a Dedicated Microprocessor Tester (DMT) has been implemented to perform a thorough checkout of the RTS prior to all TREAT operations

Genomic analysis suggests that mRNA destabilization by the microprocessor is specialized for the auto-regulation of Dgcr8.

Directory of Open Access Journals (Sweden)

Archana Shenoy

2009-09-01

Full Text Available The Microprocessor, containing the RNA binding protein Dgcr8 and RNase III enzyme Drosha, is responsible for processing primary microRNAs to precursor microRNAs. The Microprocessor regulates its own levels by cleaving hairpins in the 5'UTR and coding region of the Dgcr8 mRNA, thereby destabilizing the mature transcript.To determine whether the Microprocessor has a broader role in directly regulating other coding mRNA levels, we integrated results from expression profiling and ultra high-throughput deep sequencing of small RNAs. Expression analysis of mRNAs in wild-type, Dgcr8 knockout, and Dicer knockout mouse embryonic stem (ES cells uncovered mRNAs that were specifically upregulated in the Dgcr8 null background. A number of these transcripts had evolutionarily conserved predicted hairpin targets for the Microprocessor. However, analysis of deep sequencing data of 18 to 200nt small RNAs in mouse ES, HeLa, and HepG2 indicates that exonic sequence reads that map in a pattern consistent with Microprocessor activity are unique to Dgcr8.We conclude that the Microprocessor's role in directly destabilizing coding mRNAs is likely specifically targeted to Dgcr8 itself, suggesting a specialized cellular mechanism for gene auto-regulation.

Microprocessor-controlled surface testing

Energy Technology Data Exchange (ETDEWEB)

Droscha, H

1982-09-01

For the quality inspection on continuous flow material webs with transverse scanning laser beam, the microprocessor control, realized now for the first time in combination with appropriate units, shows a considerable progress. Thanks to the here used electronics, surface errors can be localized within the web according to their x-y-position, quantitative analysis can be carried out and automatic sorting and registration functions can be used.

A fastbus master based on a risc microprocessor

International Nuclear Information System (INIS)

Cerrito, L.; Chorowicz, V.; Lebbolo, H.; Vallereau, A.

1990-01-01

SISIFUS is a general purpose Fastbus Master and Slave able to perform any operation on both Fastbus segments. Master operations are directed either by the processor or by two fast sequencers. A Block Mover function is implemented allowing direct data block transfers between two Slaves. SISIFUS uses the AM 29000 RISC microprocessor which can execute every assembler instruction in 40ns. The on-board monitor/debugger allows programs to be written in assembler from a terminal connected to the module or written in C and cross compiled on a host computer (PC)

Cross software for microprocessor program development at CERN

International Nuclear Information System (INIS)

Eicken, H. von; Montuelle, J.; Willers, I.; Blake, J.

1981-01-01

Programs for a variety of microprocessors (including Intel 8080; Motorola 6800 and 6809 and 68000; and Texas Instruments 9900) can be prepared on different host computers (such as IBM 370, CDC 6000, and Nord 10) using portable programs developed at CERN. The range of cross software consists of: an assembler for each target microprocessor, a single linkage editor, a single object module librarian, and a variety of pre-loaders which convert object modules from CERN's format (CUFOM) into manufacturers' formats. The programs are written in BCPL and PASCAL, programming languages which are available on a wide range of computers. (orig.)

Microprocessor system to recover data from a self-scanning photodiode array

International Nuclear Information System (INIS)

Koppel, L.N.; Gadd, T.J.

1975-01-01

A microprocessor system developed at Lawrence Livermore Laboratory has expedited the recovery of data describing the low energy x-ray spectra radiated by laser-fusion targets. An Intel microprocessor controls the digitization and scanning of the data stream of an x-ray-sensitive self-scanning photodiode array incorporated in a crystal diffraction spectrometer

Commercialization issues and funding opportunities for high-performance optoelectronic computing modules

Science.gov (United States)

Hessenbruch, John M.; Guilfoyle, Peter S.

1997-01-01

Low power, optoelectronic integrated circuits are being developed for high speed switching and data processing applications. These high performance optoelectronic computing modules consist of three primary components: vertical cavity surface emitting lasers, diffractive optical interconnect elements, and detector/amplifier/laser driver arrays. Following the design and fabrication of an HPOC module prototype, selected commercial funding sources will be evaluated to support a product development stage. These include the formation of a strategic alliance with one or more microprocessor or telecommunications vendors, and/or equity investment from one or more venture capital firms.

Design description of a microprocessor based Engine Monitoring and Control unit (EMAC) for small turboshaft

Science.gov (United States)

Baez, A. N.

1985-01-01

Research programs have demonstrated that digital electronic controls are more suitable for advanced aircraft/rotorcraft turbine engine systems than hydromechanical controls. Commercially available microprocessors are believed to have the speed and computational capability required for implementing advanced digital control algorithms. Thus, it is desirable to demonstrate that off-the-shelf microprocessors are indeed capable of performing real time control of advanced gas turbine engines. The engine monitoring and control (EMAC) unit was designed and fabricated specifically to meet the requirements of an advanced gas turbine engine control system. The EMAC unit is fully operational in the Army/NASA small turboshaft engine digital research program.

LSI microprocessor circuit families based on integrated injection logic. Mikroprotsessornyye komplekty bis na osnove integral'noy inzhektsionnoy logiki

Energy Technology Data Exchange (ETDEWEB)

Borisov, V.S.; Vlasov, F.S.; Kaloshkin, E.P.; Serzhanovich, D.S.; Sukhoparov, A.I.

1984-01-01

Progress in developing microprocessor computer hardware is based on progress and improvement in systems engineering, circuit engineering and manufacturing process methods of design and development of large-scale integrated circuits (BIS). Development of these methods with widespread use of computer-aided design (CAD) systems has allowed developing 4- and 8-bit microprocessor families (MPK) of LSI circuits based on integrated injection logic (I/sup 2/L), characterized by relatively high speed and low dissipated power. The emergence of LSI and VLSI microprocessor circuits required computer system developers to make changes to theory and practice of computer system design. Progress in technology upset the established relation between hardware and software component development costs in systems being designed. A characteristic feature of using LSI circuits is also the necessity of building devices from standard modules with large functional complexity. The existing directions of forming compositions of LSI microprocessor families allow the system developer to choose a particular methodology of design, proceeding from the efficiency function and field of application of the system being designed. The efficiency of using microprocessor families is largely governed by the user's understanding in depth of the structure of LSI microprocessor family circuits and the features of using them to implement a broad class of computer devices and modules being developed. This book is devoted to solving this problem.

FY1995 study of design methodology and environment of high-performance processor architectures; 1995 nendo koseino processor architecture sekkeiho to sekkei kankyo no kenkyu

Energy Technology Data Exchange (ETDEWEB)

NONE

1997-03-01

The aim of our project is to develop high-performance processor architectures for both general purpose and application-specific purpose. We also plan to develop basic softwares, such as compliers, and various design aid tools for those architectures. We are particularly interested in performance evaluation at architecture design phase, design optimization, automatic generation of compliers from processor designs, and architecture design methodologies combined with circuit layout. We have investigated both microprocessor architectures and design methodologies / environments for the processors. Our goal is to establish design technologies for high-performance, low-power, low-cost and highly-reliable systems in system-on-silicon era. We have proposed PPRAM architecture for high-performance system using DRAM and logic mixture technology, Softcore processor architecture for special purpose processors in embedded systems, and Power-Pro architecture for low power systems. We also developed design methodologies and design environments for the above architectures as well as a new method for design verification of microprocessors. (NEDO)

Reliability of microprocessor-based relay protection devices: Myths and reality

Directory of Open Access Journals (Sweden)

Gurevich Vladimir

2009-01-01

Full Text Available The article examines four basic theses about the ostensibly extremely high reliability of microprocessor-based relay protection (MP touted by supporters of MP. Through detailed analysis based on many references it is shown that the basis of these theses are widespread myths, and actually MP reliability is lower than the reliability of electromechanical and electronic protective relays on discrete components.

Sectional microprocessor based microcomputer and its application to express analysis using interactive language

International Nuclear Information System (INIS)

Lang, I.; Leveleki, L.; Salai, M.; Turani, D.

1984-01-01

Sectional microprocessor TPA-L/128H based mini-computer being a part of the TPA-8 computer family is developed. A substantial increase of the computer operation rate is attained at the expense of microprogram monitoring. The central processor is constructed on the base of the AM2900 sectional microprocessor elements. The TPA-L/128H computer is program compatible with TPA-8 computer, perfectly equipped with software: high level languages as well as OS/L, COS/H, RTS/H, PAL/128, WPS, TEASYS-8 and IL 128 ensuring statistical data processing, physical experiments automation and interactive experimental data processing. The real time basis problems and CAMAC devices monitoring are efficiently solved

Supply system with microprocessor control for electron gun

International Nuclear Information System (INIS)

Duplin, N.I.; Sergeev, N.N.

1988-01-01

Precision supply system for electron gun used in Auger-spectrometer is described. The supply system consists of control and high-voltage parts, made as separate units. Supply high-voltage unit includes system supply module, filament module to supply electron gun cathode and 6 high-volt modules to supply accelerating, modulating and three focusing electrodes of the gun. High-voltage modules have the following characteristics: U-(100-1000)V output voltage, 5x10 -5 U stability, 10 -5 xU pulsation amplitude, J-(0-5)A filament current change range at 10 -4 xJ stability. Control unit including microprocessor, timer and storage devices forms control voltage for all modules and regulates voltage and current of filament at electrodes

Single event effect testing of the Intel 80386 family and the 80486 microprocessor

International Nuclear Information System (INIS)

Moran, A.; LaBel, K.; Gates, M.; Seidleck, C.; McGraw, R.; Broida, M.; Firer, J.; Sprehn, S.

1996-01-01

The authors present single event effect test results for the Intel 80386 microprocessor, the 80387 coprocessor, the 82380 peripheral device, and on the 80486 microprocessor. Both single event upset and latchup conditions were monitored

The European Logarithmic Microprocessor

Czech Academy of Sciences Publication Activity Database

Coleman, J. N.; Softley, C. I.; Kadlec, Jiří; Matoušek, R.; Tichý, Milan; Pohl, Zdeněk; Heřmánek, Antonín; Benschop, N. F.

2008-01-01

Roč. 57, č. 4 (2008), s. 532-546 ISSN 0018-9340 Grant - others:Evropská komise(BE) ESPRIT 33544 Institutional research plan: CEZ:AV0Z10750506 Source of funding: R - rámcový projekt EK Keywords : Processor architecture * arithmetic unit * logarithmic arithmetic Subject RIV: JC - Computer Hardware ; Software Impact factor: 2.611, year: 2008 http://library.utia.cas.cz/separaty/2008/ZS/kadlec-the%20european%20logarithmic%20microprocessor.pdf

Integration in a nuclear physics experiment of a visualization unit managed by a microprocessor

International Nuclear Information System (INIS)

Lefebvre, M.

1976-01-01

A microprocessor (Intel 8080) is introduced in the equipment controlling the (e,e'p) experiment that will take place at the linear accelerator operating in the premises of CEA (Orme des Merisiers, Gif-sur-Yvette, France). The purpose of the microprocessor is to handle the visualization tasks that are necessary to have a continuous control of the experiment. By doing so more time and more memory will be left for data processing by the calculator unit. In a forward version of the system, the controlling of the level of helium in the target might also be in charge of the microprocessor. This work is divided into 7 main parts: 1) a presentation of the linear accelerator and its experimental facilities, 2) the Intel 8080 micro-processor and its programming, 3) the implementation of the micro-processor in the electronic system, 4) the management of the memory, 5) data acquisition, 6) the keyboard, and 7) the visualization unit [fr

Concept report: Microprocessor control of electrical power system

Science.gov (United States)

Perry, E.

1977-01-01

An electrical power system which uses a microprocessor for systems control and monitoring is described. The microprocessor controlled system permits real time modification of system parameters for optimizing a system configuration, especially in the event of an anomaly. By reducing the components count, the assembling and testing of the unit is simplified, and reliability is increased. A resuable modular power conversion system capable of satisfying a large percentage of space applications requirements is examined along with the programmable power processor. The PC global controller which handles systems control and external communication is analyzed, and a software description is given. A systems application summary is also included.

A microprocessor based mobile radiation survey system

International Nuclear Information System (INIS)

Gilbert, R.W.; McCormack, W.D.

1984-01-01

A microprocessor-based system has been designed and constructed to enhance the performance of routine radiation surveys on roads within the Hanford site. This device continually monitors system performance and output from four sodium iodide detectors mounted on the rear bumper of a 4-wheel drive truck. The gamma radiation count rate in counts-per-second is monitored, and a running average computed, with the results compared to predefined limits. If an abnormal instantaneous or average count rate is detected, an alarm is sounded with responsible data displayed on a liquid crystal panel in the cab of the vehicle. The system also has the capability to evaluate detector output using multiple time constants and to perform more complex tests and comparison of the data. Data can be archived for later analysis on conventional chart recorders or stored in digital form on magnetic tape or other digital storage media

Auxiliary/Master microprocessor CAMAC Crate Controller applications

International Nuclear Information System (INIS)

Barsotti, E.

1975-01-01

The need for further sophistication of an already complex serial CAMAC control system at Fermilab led to the development of an Auxilary/Master CAMAC Crate Controller. The controller contains a Motorola 6800 microprocessor, 2K bytes of RAM, and 8K bytes of PROM memory. Bussed dataway lines are time shared with CAMAC signals to provide memory expansion and direct addressing of peripheral devices without the need of external cabling. The Auxiliary/Master Crate Controller (A/MCC) can function as either a Master, i.e., stand alone, crate controller or as an Auxiliary controller to Fermilab's Serial Crate Controller (SCC). Two modules, one single- and one double-width, make up an A/MCC. The microprocessor has one nonmaskable and one maskable vectored interrupt. Time sharing the dataway between SCC programmed and block transfer generated dataway cycles and A/MCC operations still allows a 99 percent microprocessor CPU busy time. Since the conception of the A/MCC, there has been an increasing number of control system-related projects proposed which would not have been possible or would have been very difficult to implement without such a device. The first such application now in use at Fermilab is a stand-alone control system for a mass spectrometer experiment in the Main Ring Internal Target Area. This application in addition to other proposed A/MCC applications, both stand-alone and auxiliary, is discussed

Software tools for microprocessor based systems

International Nuclear Information System (INIS)

Halatsis, C.

1981-01-01

After a short review of the hardware and/or software tools for the development of single-chip, fixed instruction set microprocessor-based sytems we focus on the software tools for designing systems based on microprogrammed bit-sliced microprocessors. Emphasis is placed on meta-microassemblers and simulation facilties at the register-transfer-level and architecture level. We review available meta-microassemblers giving their most important features, advantages and disadvantages. We also make extentions to higher-level microprogramming languages and associated systems specifically developed for bit-slices. In the area of simulation facilities we first discuss the simulation objectives and the criteria for chosing the right simulation language. We consertrate to simulation facilities already used in bit-slices projects and discuss the gained experience. We conclude by describing the way the Signetics meta-microassembler and the ISPS simulation tool have been employed in the design of a fast microprogrammed machine, called MICE, made out of ECL bit-slices. (orig.)

An SEU rate prediction method for microprocessors of space applications

International Nuclear Information System (INIS)

Gao Jie; Li Qiang

2012-01-01

In this article,the relationship between static SEU (Single Event Upset) rate and dynamic SEU rate in microprocessors for satellites is studied by using process duty cycle concept and fault injection technique. The results are compared to in-orbit flight monitoring data. The results show that dynamic SEU rate by using process duty cycle can estimate in-orbit SEU rate of microprocessor reasonable; and the fault injection technique is a workable method to estimate SEU rate. (authors)

Microprocessor control unit of thyristor regulator of microhydroelectric power station ballast load

International Nuclear Information System (INIS)

Nomokonova, Yu; Bogdanov, E

2014-01-01

The operational principle of microhydroelectric power station ballast load is presented. The comparative overview of the mathematical modeling methods is performed. The ranges of thyristors optimal work are shown as a result of the regulator regimes analysis. Shows the necessity of regulation the ballast load in microhydroelectric power station with help of developed algorithm of the program for microprocessor control

Microprocessors & their operating systems a comprehensive guide to 8, 16 & 32 bit hardware, assembly language & computer architecture

CERN Document Server

Holland, R C

1989-01-01

Provides a comprehensive guide to all of the major microprocessor families (8, 16 and 32 bit). The hardware aspects and software implications are described, giving the reader an overall understanding of microcomputer architectures. The internal processor operation of each microprocessor device is presented, followed by descriptions of the instruction set and applications for the device. Software considerations are expanded with descriptions and examples of the main high level programming languages (BASIC, Pascal and C). The book also includes detailed descriptions of the three main operatin

Design of a microprocessor-based Control, Interface and Monitoring (CIM unit for turbine engine controls research

Science.gov (United States)

Delaat, J. C.; Soeder, J. F.

1983-01-01

High speed minicomputers were used in the past to implement advanced digital control algorithms for turbine engines. These minicomputers are typically large and expensive. It is desirable for a number of reasons to use microprocessor-based systems for future controls research. They are relatively compact, inexpensive, and are representative of the hardware that would be used for actual engine-mounted controls. The Control, Interface, and Monitoring Unit (CIM) contains a microprocessor-based controls computer, necessary interface hardware and a system to monitor while it is running an engine. It is presently being used to evaluate an advanced turbofan engine control algorithm.

Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System

Science.gov (United States)

Liu, Yuan-Kwei

1991-01-01

The feasibility is analyzed of upgrading the Intel 386 microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 microprocessors. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (Space) qualification schedule, and performance. The advantages of the i486 over the 386 are (1) lower power consumption; and (2) higher floating point performance. The i486 on-chip cache does not have parity check or error detection and correction circuitry. The i486 with on-chip cache disabled, however, has lower integer performance than the 386 without cache, which is the current DMS design choice. Adding cache to the 386/386 DX memory hierachy appears to be the most beneficial change to the current DMS design at this time.

Microprocessor-controlled system for automatic acquisition of potentiometric data and their non-linear least-squares fit in equilibrium studies.

Science.gov (United States)

Gampp, H; Maeder, M; Zuberbühler, A D; Kaden, T A

1980-06-01

A microprocessor-controlled potentiometric titration apparatus for equilibrium studies is described. The microprocessor controls the stepwise addition of reagent, monitors the pH until it becomes constant and stores the constant value. The data are recorded on magnetic tape by a cassette recorder with an RS232 input-output interface. A non-linear least-squares program based on Marquardt's modification of the Newton-Gauss method is discussed and its performance in the calculation of equilibrium constants is exemplified. An HP 9821 desk-top computer accepts the data from the magnetic tape recorder. In addition to a fully automatic fitting procedure, the program allows manual adjustment of the parameters. Three examples are discussed with regard to performance and reproducibility.

A Fault-tolerant RISC Microprocessor for Spacecraft Applications

Science.gov (United States)

Timoc, Constantin; Benz, Harry

1990-01-01

Viewgraphs on a fault-tolerant RISC microprocessor for spacecraft applications are presented. Topics covered include: reduced instruction set computer; fault tolerant registers; fault tolerant ALU; and double rail CMOS logic.

Multichannel analyzer based on microprocessors

International Nuclear Information System (INIS)

Soares, M.

1983-06-01

A multichannel analyser for nuclear spectrometry, that would attend the needs of research laboratories and could be industrialized in Brazil, was developed. The design was based on INTEL 8080/85 microprocessors; other processors were also used to implement specific functions, such as shared busbar using direct memory access. A prototype was developed and tested through simulation, using a nuclear spectrometry chain. The results were fully satisfactory. (Author) [pt

Cardiac output measurement instruments controlled by microprocessors

International Nuclear Information System (INIS)

Spector, M.; Barritault, L.; Boeri, C.; Fauchet, M.; Gambini, D.; Vernejoul, P. de

The nuclear medicine and biophysics laboratory of the Necker-Enfants malades University Hospital Centre has built a microprocessor controlled Cardiac flowmetre. The principle of the cardiac output measurement from a radiocardiogram is well established. After injection of a radioactive indicator upstream from the heart cavities the dilution curve is obtained by the use of a gamma-ray precordial detector. This curve normally displays two peaks due to passage of the indicator into the right and left sides of the heart respectively. The output is then obtained from the stewart Hamilton principle once recirculation is eliminated. The graphic method used for the calculation however is long and tedious. The decreasing fraction of the dilution curve is projected in logarithmic space in order to eliminate recirculation by determining the mean straight line from which the decreasing exponential is obtained. The principle of the use of microprocessors is explained (electronics, logics) [fr

Intel Xeon Phi coprocessor high performance programming

CERN Document Server

Jeffers, James

2013-01-01

Authors Jim Jeffers and James Reinders spent two years helping educate customers about the prototype and pre-production hardware before Intel introduced the first Intel Xeon Phi coprocessor. They have distilled their own experiences coupled with insights from many expert customers, Intel Field Engineers, Application Engineers and Technical Consulting Engineers, to create this authoritative first book on the essentials of programming for this new architecture and these new products. This book is useful even before you ever touch a system with an Intel Xeon Phi coprocessor. To ensure that your applications run at maximum efficiency, the authors emphasize key techniques for programming any modern parallel computing system whether based on Intel Xeon processors, Intel Xeon Phi coprocessors, or other high performance microprocessors. Applying these techniques will generally increase your program performance on any system, and better prepare you for Intel Xeon Phi coprocessors and the Intel MIC architecture. It off...

A microprocessor-controlled assay for the estimation of human placental lactogen

International Nuclear Information System (INIS)

Adam, T.; Roulston, J.E.; Bagshawe, K.D.

1979-01-01

A radioimmunoassay for human placental lactogen (HPL) is described using the KEMTEK 3000, which is a modular radioimmunoassay apparatus controlled by a microprocessor. Operation of the KEMTEK 3000 is largely automatic and it requires minimal intervention from the operator. It is capable of 300 reactions per hour so that a large number of estimations can readily be performed. HPL was assayed by a double antibody method on serum samples from pregnant women and patients with trophoblastic tumours. (Auth.)

TRIESTE: College on Microprocessors

International Nuclear Information System (INIS)

Anon.

1981-01-01

The International Centre for Theoretical Physics, set up at Trieste in 1964, has as its major task the provision of a stimulating intellectual environment for physicists from developing countries. This goal is furthered by a varied programme of courses for visiting scientists. Not all the courses remain in the rarefied atmosphere of theory and in September a very successful 'College on Microprocessors: Technology and Applications in Physics' was held. It was a prime example of the efforts being made to spread important modern technology into the developing countries

Microprocessor-controlled data-acquisition instrument for neutron-activation measurements

International Nuclear Information System (INIS)

Jones, B.A.

1981-01-01

This paper describes a microprocessor controlled data acquisition instrument designed at Lawrence Livermore National Laboratory to provide experimenters with a diagnostic tool for measuring the performance of laser imploded fusion targets via neutron activation techniques. This instrument features the ability to count four independent inputs simultaneously while providing a front panel readout of these inputs, plus a time of day clock. A hardcopy printout of the data is also provided by a built-in thermal printer. All running modes and parameters are user selectable via a front panel keypad, and a complete set of internal self-testing diagnostics are available for debug

The use of distributed microprocessors for control devices

International Nuclear Information System (INIS)

Lejon, J.C.

1978-01-01

The use of distributed individual microprocessors provided the basis for the development of the μZ system, which is a modular numerical control device which in its main part contains no elements whatever with multiple functions. With this system, total availability of control is achieved and the failure of any individual element causes loss of automatic control only over one actuator or over a small group of interdependent actuators. The human operator, who cannot be omitted even with an inherently safe control system, can operate the single faulty channel manually. The microprocessors have a free-format with which all possible algorithms within the limits of the memory size of the various cards can be performed. This program can be loaded either in random access memory (RAM) or in read-only memory (ROM). The configuration is made either by assembling software modules in a hard-copy dialogue without any knowledge of data processing being necessary, or from a program written in Fortran. If the user does not have a configurator he can use read-only memories supplied by the manufacter either in the standard form or in a requested design. The parameters are loaded by means of a portable microconsole whose keyboard and displays can be used for a hard-copy dialogue with the regulating cards. Manual control and indications can be carried out from three completely independent configurations which can be used separately or in parallel: individual station, multiple-function station or cathode colour console. (author)

A microprocessor-based power control data acquisition system

International Nuclear Information System (INIS)

Greenberg, S.

1982-10-01

The project reported deals with one of the aspects of power plant control and management. In order to perform optimal distribution of power and load switching, one has to solve a specific optimization problem. In order to solve this problem one needs to collect current and power expenditure data from a large number of channels and have them processed. This particular procedure is defined as data acquisition and it constitutes the main topic of this project. A microprocessor-based data acquisition system for power management is investigated and developed. The current and power data of about 100 analog channels are sampled and collected in real-time. These data are subsequently processed to calculate the power factor (cos phi) for each channel and the maximum demand. The data is processed by an AMD 9511 Arithmetic Processing Unit and the whole system is controlled by an Intel 8080A CPU. All this information is then transfered to a universal computer through a synchronized communication channel. The optimization computations would be performed by the high level computer. Different ways of performing the search of data over a large number of channels have been investigated. A particular solution to overcome the gain and offset drift of the A/D converter, using software, has been proposed. The 8080A supervises the collection and routing of data in real time, while the 9511 performs calculation, using these data. (Author)

Microprocessors: From basic chips to complete systems

International Nuclear Information System (INIS)

Dobinson, R.W.

1985-01-01

These lectures aim to present and explain in general terms some of the characteristics of microprocessor chips and associated components. They show how systems are synthesized from the basic integrated circuit building blocks which are currently available; processor, memory, input-output (I/0) devices, etc. (orig./HSI)

Microprocessor Controlled Capacitor Bank Switching System for ...

African Journals Online (AJOL)

In this work, analysis and development of a microprocessor controlled capacitor bank switching system for deployment in a smart distribution network was carried out. This system was implemented by the use of discreet components such as resistors, capacitors, transistor, diode, automatic voltage regulator, with the ...

Design and Implementation of O/C relay using Microprocessor

Directory of Open Access Journals (Sweden)

Dr.Abdul-Sattar H. Jasim

2012-03-01

Full Text Available This work presents the design and implementation of a versatile digital overcurrent (O/C relay using a single microprocessor. The relay is implemented by a combination of a look-up table and a counter. The software development and hardware testing are done using a microcomputer module based on a 8-bit microprocessor. The digital processing of measured currents enables a separate setting of operating values selection of all types of inverse or constant time characteristics overcurrent protection. This protection provides reasonably fast tripping, even at terminal close to the power source were the most serve faults can occur excluding the transient condition. So this method has an excellent compromise between accuracy hardware and speed

14th annual Results and Review Workshop on High Performance Computing in Science and Engineering

CERN Document Server

Nagel, Wolfgang E; Resch, Michael M; Transactions of the High Performance Computing Center, Stuttgart (HLRS) 2011; High Performance Computing in Science and Engineering '11

2012-01-01

This book presents the state-of-the-art in simulation on supercomputers. Leading researchers present results achieved on systems of the High Performance Computing Center Stuttgart (HLRS) for the year 2011. The reports cover all fields of computational science and engineering, ranging from CFD to computational physics and chemistry, to computer science, with a special emphasis on industrially relevant applications. Presenting results for both vector systems and microprocessor-based systems, the book allows readers to compare the performance levels and usability of various architectures. As HLRS

An Asynchronous Circuit Design Technique for a Flexible 8-Bit Microprocessor

Science.gov (United States)

Karaki, Nobuo; Nanmoto, Takashi; Inoue, Satoshi

This paper presents an asynchronous design technique, an enabler for the emerging technology of flexible microelectronics that feature low-temperature processed polysilicon (LTPS) thin-film transistors (TFT) and surface-free technology by laser annealing/ablation (SUFTLA®). The first design instance chosen is an 8-bit microprocessor. LTPS TFTs are good for realizing displays having integrated VLSI circuit at lower costs. However, LTPS TFTs have drawbacks, including substantial deviations in characteristics and the self-heating phenomenon. To solve these problems, the authors adopted the asynchronous circuit design technique and developed an asynchronous design language called Verilog+, which is based on a subset of Verilog HDL® and includes minimal primitives used for describing the communications between modules, and the dedicated tools including a translator called xlator and a synthesizer called ctrlsyn. The flexible 8-bit microprocessor stably operates at 500kHz, drawing 180μA from a 5V power source. The microprocessor's electromagnetic emissions are 21dB less than those of the synchronous counterpart.

Microprocessors control of fermentation process

Energy Technology Data Exchange (ETDEWEB)

Fawzy, A S; Hinton, O R

1980-01-01

This paper presents three schemes for the solution of the optimal control of fermentation process. It also shows the advantages of using microprocessors in controlling and monitoring this process. A linear model of the system is considered. An optimal feedback controller is determined which maintains the states (substrate and organisms concentration) at desired values when the system is subjected to disturbances in the influent substrate and organisms concentration. Simulation results are presented for the three cases.

Microprocessor-based stepping motor driver

International Nuclear Information System (INIS)

Halbig, J.K.; Klosterbuer, S.F.

1979-09-01

The Pion Generation for Medical Irradiations (PIGMI) program at the Los Alamos Scientific Laboratory requires a versatile stepping motor driver to do beam diagnostic measurements. A driver controlled by a microprocessor that can move eight stepping motors simultaneously was designed. The driver can monitor and respond to clockwise- and counterclockwise-limit switches, and it can monitor a 0- to 10-V dc position signal. The software controls start and stop ramping and maximum stepping rates. 2 figures, 1 table

Microprocessor protection devices: The present and the future

Directory of Open Access Journals (Sweden)

Gurevich Vladimir

2008-01-01

Full Text Available Paper presents the analysis of the basic constructive disadvantages of the present day microprocessor-based protective devices (MBR and offers the basic principles for creating a new MBR that can be used in newly constructed devices.

Microprocessor based beam loss monitor system for the AGS

International Nuclear Information System (INIS)

Witkover, R.L.

1979-01-01

An array of 120 long radiation monitors (LRM) have been installed around the AGS. Each monitor is an extended coaxial ion chamber, 5 meters long, made from hollow core coaxial transmission cable pressured with argon. The LRM's are each connected to a low current preamplifier and voltage-to-frequency converter (VFC). The digital output of each channel is fed to a 16 bit counter chip which bridges the bus of an 8085 microprocessor. This circuit is connected to the AGS PD-10 for data taking or may function as a stand-alone unit. Various operating modes can be selected for data readout. System design and operating performance are described

The Microprocessor controls the activity of mammalian retrotransposons

DEFF Research Database (Denmark)

Heras, Sara R.; Macias, Sara; Plass, Mireya

2013-01-01

RNA biogenesis, also recognizes and binds RNAs derived from human long interspersed element 1 (LINE-1), Alu and SVA retrotransposons. Expression analyses demonstrate that cells lacking a functional Microprocessor accumulate LINE-1 mRNA and encoded proteins. Furthermore, we show that structured regions...

A high resolution wire scanner beam profile monitor with a microprocessor data acquisition system

International Nuclear Information System (INIS)

Cutler, R.I.; Mohr, D.L.; Whittaker, J.K.; Yoder, N.R.

1983-01-01

A beam profile monitor has been constructed for the NBS-LANL Racetrack Microtron. The monitor consists of two perpendicular 30 μm diameter carbon wires that are driven through an electron beam by a pneumatic actuator. A long-lifetime, electroformed nickel bellows is used for the linear-motion vacuum feedthrough. Secondary emission current from the wires and a signal from a transducer measuring the position of the wires are simultaneously digitized by a microprocessor to yield beam current density profiles in two dimensions. The wire scanner is designed for use with both pulsed and cw beams

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

Science.gov (United States)

Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

2006-01-01

Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.

Microprocessor-controlled portable neutron spectrometer

International Nuclear Information System (INIS)

Hunt, G.F.; Kaifer, R.C.; Slaughter, D.R.; Strout, R.E. II; Rueppel, D.W.

1979-01-01

A neutron spectrometer that acquires and unfolds data in the field has been developed for use in the energy range from 1 to 20 MeV. The system includes an NE213 organic scintillation detector, automatic gain stabilization, automatically stabilized pulseshape discrimination, an LSl-11 microprocessor for control and data reduction, and a multichannel analyzer for data acquisition. The system, with the exception of the multichannel analyzer, is mounted in a suitcase 47 by 66 by 23.5 cm. The mass is 23.5 kg

Microprocessor-based integrated LMFBR core surveillance

International Nuclear Information System (INIS)

Gmeiner, L.

1984-06-01

This report results from a joint study of KfK and INTERATOM. The aim of this study is to explore the advantages of microprocessors and microelectronics for a more sophisticated core surveillance, which is based on the integration of separate surveillance techniques. Due to new developments in microelectronics and related software an approach to LMFBR core surveillance can be conceived that combines a number of measurements into a more intelligent decision-making data processing system. The following techniques are considered to contribute essentially to an integrated core surveillance system: - subassembly state and thermal hydraulics performance monitoring, - temperature noise analysis, - acoustic core surveillance, - failure characterization and failure prediction based on DND- and cover gas signals, and - flux tilting techniques. Starting from a description of these techniques it is shown that by combination and correlation of these individual techniques a higher degree of cost-effectiveness, reliability and accuracy can be achieved. (orig./GL) [de

A low-cost high-performance embedded platform for accelerator controls

International Nuclear Information System (INIS)

Cleva, Stefano; Bogani, Alessio Igor; Pivetta, Lorenzo

2012-01-01

Over the last years the mobile and hand-held device market has seen a dramatic performance improvement of the microprocessors employed for these systems. As an interesting side effect, this brings the opportunity of adopting these microprocessors to build small low-cost embedded boards, featuring lots of processing power and input/output capabilities. Moreover, being capable of running a full featured operating system such as Gnu/Linux, and even a control system toolkit such as Tango, these boards can also be used in control systems as front-end or embedded computers. In order to evaluate the feasibility of this idea, an activity has started at Elettra to select, evaluate and validate a commercial embedded device able to guarantee production grade reliability, competitive costs and an open source platform. The preliminary results of this work are presented. (author)

Hardware math for the 6502 microprocessor

Science.gov (United States)

Kissel, R.; Currie, J.

1985-01-01

A floating-point arithmetic unit is described which is being used in the Ground Facility of Large Space Structures Control Verification (GF/LSSCV). The experiment uses two complete inertial measurement units and a set of three gimbal torquers in a closed loop to control the structural vibrations in a flexible test article (beam). A 6502 (8-bit) microprocessor controls four AMD 9511A floating-point arithmetic units to do all the computation in 20 milliseconds.

Design and implementation of a microprocessor based room ...

African Journals Online (AJOL)

This paper describes the development of a microprocessor based room illumination control system that offers advantage of improved efficiency in the use of electrical energy and reduced cost of electricity over manually controlled lighting systems. This system is developed to regulate the intensity of light from direct current ...

The specifications a multichannel analyser using microprocessor

International Nuclear Information System (INIS)

Pontes, E.W.

The idea of a small nuclear data acquisition system (stand - alone CAMAC system) used for spectroscopy, is presented. The system is composed by an autonomous controller with microprocessor with one fast programable unit (1-2 μsec/CAMAC instructions) and with modulus of general functions as: CAMAC memory, interface for video, interface for analogy to digital converter and temporizing. (E.G.) [pt

A microprocessor-based gamma-ray spectrometer with gain stabilized single-channel analyzers

International Nuclear Information System (INIS)

Borg, P.J.; Huppert, P.; Phillips, P.L.; Waddington, P.J.

1985-01-01

The design and performance of a self-contained microprocessor-based gamma-ray spectrometer for use in geophysical measurements using nuclear techniques is described. The instrument uses single-channel analyzers which are inherently simpler and faster than the Wilkinson or successive approximation ADC. A novel technique of gain stabilization together with a simple means of energy calibration has been developed. The modular design of the equipment makes it suitable for multidetector usage, required in a number of nucleonic gauges for the quantitative measurement of chemical constituents. (orig.)

MicroShell Minimalist Shell for Xilinx Microprocessors

Science.gov (United States)

Werne, Thomas A.

2011-01-01

MicroShell is a lightweight shell environment for engineers and software developers working with embedded microprocessors in Xilinx FPGAs. (MicroShell has also been successfully ported to run on ARM Cortex-M1 microprocessors in Actel ProASIC3 FPGAs, but without project-integration support.) Micro Shell decreases the time spent performing initial tests of field-programmable gate array (FPGA) designs, simplifies running customizable one-time-only experiments, and provides a familiar-feeling command-line interface. The program comes with a collection of useful functions and enables the designer to add an unlimited number of custom commands, which are callable from the command-line. The commands are parameterizable (using the C-based command-line parameter idiom), so the designer can use one function to exercise hardware with different values. Also, since many hardware peripherals instantiated in FPGAs have reasonably simple register-mapped I/O interfaces, the engineer can edit and view hardware parameter settings at any time without stopping the processor. MicroShell comes with a set of support scripts that interface seamlessly with Xilinx's EDK tool. Adding an instance of MicroShell to a project is as simple as marking a check box in a library configuration dialog box and specifying a software project directory. The support scripts then examine the hardware design, build design-specific functions, conditionally include processor-specific functions, and complete the compilation process. For code-size constrained designs, most of the stock functionality can be excluded from the compiled library. When all of the configurable options are removed from the binary, MicroShell has an unoptimized memory footprint of about 4.8 kB and a size-optimized footprint of about 2.3 kB. Since MicroShell allows unfettered access to all processor-accessible memory locations, it is possible to perform live patching on a running system. This can be useful, for instance, if a bug is

RISC Processors and High Performance Computing

Science.gov (United States)

Bailey, David H.; Saini, Subhash; Craw, James M. (Technical Monitor)

1995-01-01

This tutorial will discuss the top five RISC microprocessors and the parallel systems in which they are used. It will provide a unique cross-machine comparison not available elsewhere. The effective performance of these processors will be compared by citing standard benchmarks in the context of real applications. The latest NAS Parallel Benchmarks, both absolute performance and performance per dollar, will be listed. The next generation of the NPB will be described. The tutorial will conclude with a discussion of future directions in the field. Technology Transfer Considerations: All of these computer systems are commercially available internationally. Information about these processors is available in the public domain, mostly from the vendors themselves. The NAS Parallel Benchmarks and their results have been previously approved numerous times for public release, beginning back in 1991.

Some software algorithms for microprocessor ratemeters

International Nuclear Information System (INIS)

Savic, Z.

1991-01-01

After a review of the basic theoretical ratemeter problem and a general discussion of microprocessor ratemeters, a short insight into their hardware organization is given. Three software algorithms are described: the old ones the quasi-exponential and floating mean algorithm, and a new weighted moving average algorithm. The equations for statistical characterization of the new algorithm are given and an intercomparison is made. It is concluded that the new algorithm has statistical advantages over the old ones. (orig.)

Some software algorithms for microprocessor ratemeters

Energy Technology Data Exchange (ETDEWEB)

Savic, Z. (Military Technical Inst., Belgrade (Yugoslavia))

1991-03-15

After a review of the basic theoretical ratemeter problem and a general discussion of microprocessor ratemeters, a short insight into their hardware organization is given. Three software algorithms are described: the old ones the quasi-exponential and floating mean algorithm, and a new weighted moving average algorithm. The equations for statistical characterization of the new algorithm are given and an intercomparison is made. It is concluded that the new algorithm has statistical advantages over the old ones. (orig.).

How to harness the performance potential of current multi-core processors

International Nuclear Information System (INIS)

Jarp, Sverre; Lazzaro, Alfio; Leduc, Julien; Nowak, Andrzej

2011-01-01

Leakage currents have put a stop to the semiconductor industry's ability to increase processor frequency in order to enhance the performance of new microprocessors. Instead, we observe a slew of changes inside the micro-architecture with an aim of enhancing the performance. Several of these changes, however, do not translate into automatic speed improvements for the software. This paper discusses the increased complexity of modern microprocessors by separating out into dimensions each feature that impacts performance and mentions briefly ways of improving software, in particular that of the High Energy Physics community, to take full advantage.

Nonconformance in electromechanical output relays of microprocessor-based protection devices under actual operating conditions

OpenAIRE

Gurevich, Vladimir

2006-01-01

Microprocessor-based protection relays are gradually driving out traditional electromechanical and even electronic protection devices from virtually all fields of power and electrical engineering. In this paper, one of many problems of microprocessor-based relays is discussed: nonconformance of miniature electromechanical output relays under actual operation conditions: switching inductive loads (with tripping CB coils or lockout relay coils) at 220 VDC, and "dry" switching of some control ci...

Application of a 16-bit microprocessor to the digital control of machine tools

International Nuclear Information System (INIS)

Issaly, Alain

1979-01-01

After an overview of machine tools (various types, definition standardization, associated technologies for motors and position sensors), this research thesis describes the principles of computer-based digital control: classification of machine tool command systems, machining programming, programming languages, dialog function, interpolation function, servo-control function, tool compensation function. The author reports the application of a 16-bit microprocessor to the computer-based digital control of a machine tool: feasibility, selection of microprocessor, hardware presentation, software development and description, machining mode, translation-loading mode

Microprocessor, Setx, Xrn2, and Rrp6 Co-operate to Induce Premature Termination of Transcription by RNAPII

NARCIS (Netherlands)

Wagschal, Alexandre; Rousset, Emilie; Basavarajaiah, Poornima; Contreras, Xavier; Harwig, Alex; Laurent-Chabalier, Sabine; Nakamura, Mirai; Chen, Xin; Zhang, Ke; Meziane, Oussama; Boyer, Frédéric; Parrinello, Hugues; Berkhout, Ben; Terzian, Christophe; Benkirane, Monsef; Kiernan, Rosemary

2012-01-01

Transcription elongation is increasingly recognized as an important mechanism of gene regulation. Here, we show that microprocessor controls gene expression in an RNAi-independent manner. Microprocessor orchestrates the recruitment of termination factors Setx and Xrn2, and the 30-50 exoribonuclease,

INVESTIGATION OF MICROPROCESSOR CURRENT PROTECTION LINES WITH IMPROVED INDICES OF TECHNICAL PERFECTION

Directory of Open Access Journals (Sweden)

E. V. Buloichyk

2014-01-01

Full Text Available Technical perfection improvement of microprocessor current protection of distribution networks lines is provided by introduction of asymmetrical fault mode determination and fault location functions in the algorithm of its functioning. As a result of computing experiment the basic indices of the technical perfection of current protection have been obtained in the paper. The paper proves high efficiency of the proposed methods that ensure selective and proper operation in the different modes of the controlled line.

Microprocessor-based accelerating power level detector

Energy Technology Data Exchange (ETDEWEB)

Nagpal, M.; Zarecki, W.; Albrecht, J.C.

1994-01-01

An accelerating power level detector was built using state-of-the-art microprocessor technology at Powertech Labs Inc. The detector will monitor the real power flowing in two 300 kV transmission lines out of Kemano Hydroelectric Generating Station and will detect any sudden loss of load due to a fault on either line under certain pre-selected power flow conditions. This paper discusses the criteria of operation for the detector and its implementation details, including digital processing, hardware, and software.

Microprocessor-controlled, programmable ramp voltage generator

International Nuclear Information System (INIS)

Hopwood, J.

1978-11-01

A special-purpose voltage generator has been developed for driving the quadrupole mass filter of a residual gas analyzer. The generator is microprocessor-controlled with desired ramping parameters programmed by setting front-panel digital thumb switches. The start voltage, stop voltage, and time of each excursion are selectable. A maximum of five start-stop levels may be pre-selected for each program. The ramp voltage is 0 to 10 volts with sweep times from 0.1 to 999.99 seconds

Microprocessor controlled pulse charge and testing of batteries

International Nuclear Information System (INIS)

Kerezov, A.; Gishin, S.; Ivanov, Ratcho; Savov, S.

2002-01-01

The principle of the developed new method for pulse charge of batteries with microprocessor control of the electrochemical processes is the use of current pulses with microprocessor control of the period and the amplitude according to the dynamically changing state of the electrochemical system. In order to realize the method described above a programmable current source was developed. It is connected with a Personal Computer via RS232 standard serial interface in order to control the electrochemical processes. The parameters to be set, the graphical presentation of the pulse current and tension, the used quantity of electricity and electrical energy for every pulse and for the process as a hole are shown on the PC display. In order to test dry-charged and wet-charged batteries a specialized current generator was developed. It is connected also with a Personal Computer via R5232 standard serial interface in order to con-trol the testing of the starting capability of the batteries according to the requirements of the Bulgarian State Standard Ell 60095-1. (Author)

Trust versus confidence: Microprocessors and personnel monitoring

International Nuclear Information System (INIS)

Chiaro, P.J. Jr.

1993-01-01

Due to recent technological advances, substantial improvements have been made in personnel contamination monitoring. In all likelihood, these advances will close out the days of manually frisking personnel for radioactive contamination. Unfortunately, as microprocessor-based monitors become more widely used, not only at commercial power reactors but also at government facilities, questions concerning their trustworthiness arise. Algorithms make decisions that were previously made by technicians. Trust is placed not in technicians but in machines. In doing this it is assumed that the machine never misses. Inevitably, this trust drops, due largely to ''false alarms''. This is especially true when monitoring for alpha contamination. What is a ''false alarm''? Do these machines and their algorithms that we put our trust in make mistakes? An analysis was performed on half-body and hand-and-foot monitors at Oak Ridge National Laboratory (ORNL) in order to justify the suggested confidence level used for alarm point determination. Sources used in this analysis had activities approximating ORNL's contamination limits

Trust versus confidence: Microprocessors and personnel monitoring

International Nuclear Information System (INIS)

Chiaro, P.J. Jr.

1994-01-01

Due to recent technological advances, substantial improvements have been made in personnel contamination monitoring. In all likelihood, these advances will close out the days of manually frisking personnel for radioactive contamination. Unfortunately, as microprocessor-based monitors become more widely used, not only at commercial power reactors but also at government facilities, questions concerning their trustworthiness arise. Algorithms make decisions that were previously made by technicians. Trust is placed not in technicians but in machines. In doing this it is assumed that the machine never misses. Inevitably, this trust drops, due largely to ''false alarms''. This is especially true when monitoring for alpha contamination. What is a ''false alarm''? Do these machines and their algorithms that they put their trust in make mistakes? An analysis was performed on half-body and hand-and-foot monitors at Oak Ridge National Laboratory (ORNL) in order to justify the suggested confidence level used for alarm point determination. Sources used in this analysis had activities approximating ORNL's contamination limits

API testing program - calibration of microprocessor based flowmeters for integrated metering systems

Energy Technology Data Exchange (ETDEWEB)

Elliot, Kenneth D. [Omni Flow Computers, Inc., Stafford, TX (United States)

2005-07-01

Microprocessor based flowmeter technologies for liquids, such as Coriolis mass meters, and Ultrasonic flowmeters hold great promise. These technologies offer many advantages, such as no rotating parts, self-diagnostic checks, which can help anticipate and warn of impending failures before they have a major impact on the measurement. These meters are substantially different though than other primary devices due to their heavy reliance on the accompanying secondary electronics. One method to prove that they are accurate would be proving the flowmeter, using a pipe prover or small volume prover (SVP), but these proving methods are designed to count 'real time' pulses from a turbine or PD meter between a known volume, they are not designed to count 'time delayed' 'manufactured pulses' from a microprocessor. There are limitations of the manufactured pulse train and it affects the ability of the flowmeter to be proved using current proving technology. The author of this paper, a chairman of an American Petroleum Institute working group, investigated how the 'microprocessor generated pulses' produced by these types of flowmeters, interacted with the existing measurement technologies in use today. Several microprocessor based flowmeter technologies have been tested, including; Ultrasonic, Coriolis, and Helical Turbine with pulse multiplying preamplifier. Wherever possible, flowmeters of various sizes, and from several vendors have been tested. A significant amount of data has been collected which sheds light into why these types of flowmeters are sometimes difficult to prove. This paper describes the API testing program, and the methodology behind it. It presents results and findings, and offers specific recommendations that may eventually be incorporated into API documents and/or standards in the future. (author)

Quo vadis: Hydrologic inverse analyses using high-performance computing and a D-Wave quantum annealer

Science.gov (United States)

O'Malley, D.; Vesselinov, V. V.

2017-12-01

Classical microprocessors have had a dramatic impact on hydrology for decades, due largely to the exponential growth in computing power predicted by Moore's law. However, this growth is not expected to continue indefinitely and has already begun to slow. Quantum computing is an emerging alternative to classical microprocessors. Here, we demonstrated cutting edge inverse model analyses utilizing some of the best available resources in both worlds: high-performance classical computing and a D-Wave quantum annealer. The classical high-performance computing resources are utilized to build an advanced numerical model that assimilates data from O(10^5) observations, including water levels, drawdowns, and contaminant concentrations. The developed model accurately reproduces the hydrologic conditions at a Los Alamos National Laboratory contamination site, and can be leveraged to inform decision-making about site remediation. We demonstrate the use of a D-Wave 2X quantum annealer to solve hydrologic inverse problems. This work can be seen as an early step in quantum-computational hydrology. We compare and contrast our results with an early inverse approach in classical-computational hydrology that is comparable to the approach we use with quantum annealing. Our results show that quantum annealing can be useful for identifying regions of high and low permeability within an aquifer. While the problems we consider are small-scale compared to the problems that can be solved with modern classical computers, they are large compared to the problems that could be solved with early classical CPUs. Further, the binary nature of the high/low permeability problem makes it well-suited to quantum annealing, but challenging for classical computers.

Microprocessor controlled digital period meter

International Nuclear Information System (INIS)

Keefe, D.J.; McDowell, W.P.; Rusch, G.K.

1980-01-01

A microprocessor controlled digital period meter has been developed and tested operationally on a reactor at Argonne National Laboratory. The principle of operation is the mathematical relationship between asymptotic periods and pulse counting circuitry. This relationship is used to calculate and display the reactor periods over a range of /plus or minus/1 second to /plus or minus/999 seconds. The time interval required to update each measurement automatically varies from 8 seconds at the lowest counting rates to 2 seconds at higher counting rates. The paper will describe hardware and software design details and show the advantages of this type of Period Meter over the conventional circuits. 1 ref

Fuzzy Concurrent Object Oriented Expert System for Fault Diagnosis in 8085 Microprocessor Based System Board

OpenAIRE

Mr.D. V. Kodavade; Dr. Mrs.S.D.Apte

2014-01-01

With the acceptance of artificial intelligence paradigm, a number of successful artificial intelligence systems were created. Fault diagnosis in microprocessor based boards needs lot of empirical knowledge and expertise and is a true artificial intelligence problem. Research on fault diagnosis in microprocessor based system boards using new fuzzy-object oriented approach is presented in this paper. There are many uncertain situations observed during fault diagnosis. These uncertain situations...

Failure analysis on false call probe pins of microprocessor test equipment

Science.gov (United States)

Tang, L. W.; Ong, N. R.; Mohamad, I. S. B.; Alcain, J. B.; Retnasamy, V.

2017-09-01

A study has been conducted to investigate failure analysis on probe pins of test modules for microprocessor. The `health condition' of the probe pin is determined by the resistance value. A test module of 5V power supplied from Arduino UNO with "Four-wire Ohm measurement" method is implemented in this study to measure the resistance of the probe pins of a microprocessor. The probe pins from a scrapped computer motherboard is used as the test sample in this study. The functionality of the test module was validated with the pre-measurement experiment via VEE Pro software. Lastly, the experimental work have demonstrated that the implemented test module have the capability to identify the probe pin's `health condition' based on the measured resistance value.

Development of a microprocessor controller for stand-alone photovoltaic power systems

Science.gov (United States)

Millner, A. R.; Kaufman, D. L.

1984-01-01

A controller for stand-alone photovoltaic systems has been developed using a low power CMOS microprocessor. It performs battery state of charge estimation, array control, load management, instrumentation, automatic testing, and communications functions. Array control options are sequential subarray switching and maximum power control. A calculator keypad and LCD display provides manual control, fault diagnosis and digital multimeter functions. An RS-232 port provides data logging or remote control capability. A prototype 5 kW unit has been built and tested successfully. The controller is expected to be useful in village photovoltaic power systems, large solar water pumping installations, and other battery management applications.

A microprocessor based exchange data collection and analysis terminal application to A.E.A. PABX

International Nuclear Information System (INIS)

Mohammed, F.A.; Ezzat, A.K.; Ayad, N.M.A.

1978-01-01

The traffic data acquisition and analysis comprises micro-processer based data collection, terminals (MBDCT) and a centralized computer. The MBDCT's can communicate with the computer through a data set system. Each (MBDCT) remote terminal is connected to about two hundreds subscriber lines. It scans the trunk lines to detect the on/off hook states and to calculate the call time and the called number. If the called subscriber is not from the 200 local lines, its status should be detected though the computer communication with the two terminals. The data collected by the terminal can be slightly analysed using the microprocessor programming capability. More-over short quality performance reports can be printed on a printer interfaced to the microprocessor. Also, data can be transmitted to the central computer for further data traffic investigation. The analysis outcome can be utilized for telephone line maintenance and reorganization. This report is concerned with the terminal details as applied to the A-E-A. PABX. It consists mainly of five external lines and about 300 internal lines

Environmental qualification and functional issues for microprocessor-based reactor protection systems

International Nuclear Information System (INIS)

Korsah, K.; Kisner, R.; Wood, R.T.; Antonescu, C.

1992-01-01

Issues of obsolescence and lack of intrastructural support in (analog) spare parts, coupled with the potential benefits of digital systems, are driving the nuclear industry to retrofit analog instrumentation and control (I ampersand C) systems with digital and microprocessor-based systems. This movement away from analog can be expected to increase in advanced light-water reactors (ALWRs), which will make extensive use of fiber optic transmission, multiplexing techniques, and microprocessor-based technology. Although these technologies have several advantages and, in fact, have been in widespread use in the non-nuclear industry for several years, their application to safety-related systems in nuclear power plants raises key issues relating to the systems' environmental and functional reliability. For example, does the new hardware introduce additional system aging degradation mechanisms that could adversely impact the safety of the plant? Do the systems introduce the possibility of new and different malfunction scenarios or increase the probability of common-mode failures that could reduce the reliability of the safety system?. Are current environmental qualification standards adequate for microprocessor-based I ampersand C systems? Accordingly in 1991 the Nuclear Regulatory Commission (NRC) initiated the qualification of advanced Instrumentation and Control Systems program at ORNL to investigate issues that may arise with the use of advanced digital I ampersand C in ALWRs. The results of our studies to date are summarized in this paper

Total dose and dose rate radiation characterization of EPI-CMOS radiation hardened memory and microprocessor devices

International Nuclear Information System (INIS)

Gingerich, B.L.; Hermsen, J.M.; Lee, J.C.; Schroeder, J.E.

1984-01-01

The process, circuit discription, and total dose radiation characteristics are presented for two second generation hardened 4K EPI-CMOS RAMs and a first generation 80C85 microprocessor. Total dose radiation performance is presented to 10M rad-Si and effects of biasing and operating conditions are discussed. The dose rate sensitivity of the 4K RAMs is also presented along with single event upset (SEU) test data

Distributed microprocessor automation network for synthesizing radiotracers used in positron emission tomography

International Nuclear Information System (INIS)

Russell, J.A.G.; Alexoff, D.L.; Wolf, A.P.

1984-01-01

This presentation describes an evolving distributed microprocessor network for automating the routine production synthesis of radiotracers used in Positron Emission Tomography. We first present a brief overview of the PET method for measuring biological function, and then outline the general procedure for producing a radiotracer. The paper identifies several reasons for our automating the syntheses of these compounds. There is a description of the distributed microprocessor network architecture chosen and the rationale for that choice. Finally, we speculate about how this network may be exploited to extend the power of the PET method from the large university or National Laboratory to the biomedical research and clinical community at large. 20 refs. (DT)

A measurement of cosmic-ray LET-spectra using a microprocessor supported microscope

International Nuclear Information System (INIS)

Beer, J.; Heinrich, W.

1982-01-01

A microprocessor supported semi-automatic system for measurements of nuclear tracks in plastic detectors is presented. It consists of a microscope and a stepping motor driven stage. A Motorola microprocessor MC 6800 controls the measurement. It accepts the co-ordinates of the stage as well as the position of the focus and computes cone length and dip angle from the three-dimensional co-ordinates. LET-spectra were measured from two cellulose nitrate foils of the Biostack III experiment flown with the Apollo-Soyus-Test-Project in 1975. One of these foils was shielded by 3 g/cm 2 and the other one by 15 g/cm 2 . The two spectra show no statistically significant decrease of intensity. (author)

15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

Science.gov (United States)

2010-01-01

... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17...: END-USER AND END-USE BASED § 744.17 Restrictions on certain exports and reexports of general purpose microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the...

Technology transfer of military space microprocessor developments

Science.gov (United States)

Gorden, C.; King, D.; Byington, L.; Lanza, D.

1999-01-01

Over the past 13 years the Air Force Research Laboratory (AFRL) has led the development of microprocessors and computers for USAF space and strategic missile applications. As a result of these Air Force development programs, advanced computer technology is available for use by civil and commercial space customers as well. The Generic VHSIC Spaceborne Computer (GVSC) program began in 1985 at AFRL to fulfill a deficiency in the availability of space-qualified data and control processors. GVSC developed a radiation hardened multi-chip version of the 16-bit, Mil-Std 1750A microprocessor. The follow-on to GVSC, the Advanced Spaceborne Computer Module (ASCM) program, was initiated by AFRL to establish two industrial sources for complete, radiation-hardened 16-bit and 32-bit computers and microelectronic components. Development of the Control Processor Module (CPM), the first of two ASCM contract phases, concluded in 1994 with the availability of two sources for space-qualified, 16-bit Mil-Std-1750A computers, cards, multi-chip modules, and integrated circuits. The second phase of the program, the Advanced Technology Insertion Module (ATIM), was completed in December 1997. ATIM developed two single board computers based on 32-bit reduced instruction set computer (RISC) processors. GVSC, CPM, and ATIM technologies are flying or baselined into the majority of today's DoD, NASA, and commercial satellite systems.

Automatic Energy Schemes for High Performance Applications

Energy Technology Data Exchange (ETDEWEB)

Sundriyal, Vaibhav [Iowa State Univ., Ames, IA (United States)

2013-01-01

Although high-performance computing traditionally focuses on the efficient execution of large-scale applications, both energy and power have become critical concerns when approaching exascale. Drastic increases in the power consumption of supercomputers affect significantly their operating costs and failure rates. In modern microprocessor architectures, equipped with dynamic voltage and frequency scaling (DVFS) and CPU clock modulation (throttling), the power consumption may be controlled in software. Additionally, network interconnect, such as Infiniband, may be exploited to maximize energy savings while the application performance loss and frequency switching overheads must be carefully balanced. This work first studies two important collective communication operations, all-to-all and allgather and proposes energy saving strategies on the per-call basis. Next, it targets point-to-point communications to group them into phases and apply frequency scaling to them to save energy by exploiting the architectural and communication stalls. Finally, it proposes an automatic runtime system which combines both collective and point-to-point communications into phases, and applies throttling to them apart from DVFS to maximize energy savings. The experimental results are presented for NAS parallel benchmark problems as well as for the realistic parallel electronic structure calculations performed by the widely used quantum chemistry package GAMESS. Close to the maximum energy savings were obtained with a substantially low performance loss on the given platform.

Microprocessor architectures RISC, CISC and DSP

CERN Document Server

Heath, Steve

1995-01-01

'Why are there all these different processor architectures and what do they all mean? Which processor will I use? How should I choose it?' Given the task of selecting an architecture or design approach, both engineers and managers require a knowledge of the whole system and an explanation of the design tradeoffs and their effects. This is information that rarely appears in data sheets or user manuals. This book fills that knowledge gap.Section 1 provides a primer and history of the three basic microprocessor architectures. Section 2 describes the ways in which the architectures react with the

Distributed Microprocessor Automation Network for Synthesizing Radiotracers Used in Positron Emission Tomography [PET

Science.gov (United States)

Russell, J. A. G.; Alexoff, D. L.; Wolf, A. P.

1984-09-01

This presentation describes an evolving distributed microprocessor network for automating the routine production synthesis of radiotracers used in Positron Emission Tomography. We first present a brief overview of the PET method for measuring biological function, and then outline the general procedure for producing a radiotracer. The paper identifies several reasons for our automating the syntheses of these compounds. There is a description of the distributed microprocessor network architecture chosen and the rationale for that choice. Finally, we speculate about how this network may be exploited to extend the power of the PET method from the large university or National Laboratory to the biomedical research and clinical community at large. (DT)

Trust versus confidence: Microprocessors and personnel monitoring

International Nuclear Information System (INIS)

Chiaro, P.J. Jr.

1993-01-01

Due to recent technological advances, substantial improvements have been made in personnel contamination monitoring. In all likelihood, these advances will close out the days of manually frisking personnel for radioactive contamination. Unfortunately, as microprocessor-based monitors become more widely used, not only at commercial power reactors but also at government facilities, questions concerning their trustworthiness arise. Algorithms make decisions that were previously made by technicians. Trust is placed not in technicians but in machines. In doing this it is assumed that the machine never misses. Inevitably, this trust drops, due largely to open-quotes false alarms.close quotes This is especially true when monitoring for alpha contamination. What is a open-quotes false alarm?close quotes Do these machines and their algorithms that we put our trust in make mistakes? An analysis was performed on half-body and hand-and-foot monitors at Oak Ridge National Laboratory (ORNL) in order to justify the suggested confidence level used for alarm point determination. Sources used in this analysis had activities approximating ORNL's contamination limits

Tests of microprocessor-based relay protection devices: Problems and solutions

Directory of Open Access Journals (Sweden)

Gurevich Vladimir

2009-01-01

Full Text Available Usually, the operational condition of relay protection devices is checked with specific settings used for the relay operation in a certain network point. In the author's opinion in order to verify the proper operation of complex multifunctional microprocessor-based protection devices (MPD at their inspection, start-up after repairs or during periodic tests there is no need to use the actual settings at which the relay is to be operated in a certain network's point. It should be tested for proper operation at several of its most critical preset characteristic points as well as in several preset characteristics constituting its most complicated (combined operation modes, including the dynamic operation modes with preset transition processes specific for standard power networks (not necessarily for a specific point. The proposed set of actions for the unification of software platforms of the modern, microprocessor-based relay protection test systems will enable examination of modern MPD in an absolutely new way. .

The bit slice micro-processor 'GESPRO' as a project in the UA2 experiment

CERN Document Server

Becam, C; Delanghe, J; Fest, H M; Lecoq, J; Martin, H; Mencik, M; MerkeI, B; Meyer, J M; Perrin, M; Plothow, H; Rampazzo, J P; Schittly, A

1981-01-01

The bit slice micro-processor GESPRO is a CAMAC module plugged into a standard Elliot system crate via which it communicates as a slave with its host computer. It has full control of CAMAC as a master unit. GESPRO is a 24 bit machine with multi-mode memory addressing capacity of 64K words. The micro-processor structure uses 5 buses including pipe-line registers to mask access time and 16 interrupt levels. The micro-program memory capacity is 2K (RAM) words of 48 bits each. A special hardwired module allows floating point, as well as integer, multiplication of 24*24 bits, result in 48 bits, in about 200 ns. This micro-processor could be used in the UA2 data acquisition chain and trigger system for the following tasks: (a) online data reduction, i.e. to read DURANDAL, process the information resulting in accepting or rejecting the event; (b) readout and analysis of the accepted data; (c) preprocess the data. The UA2 version of GESPRO is under construction, programs and micro-programs are under development. Hard...

Microprocessor-based integrated LMFBR core surveillance. Pt. 2

International Nuclear Information System (INIS)

Elies, V.

1985-12-01

This report is the result of the KfK part of a joint study of KfK and INTERATOM. The aim of this study is to explore the advantages of microprocessors and microelectronics for a more sophisticated core surveillance, which is based on the integration of separate surveillance techniques. After a description of the experimental results gained with the different surveillance techniques so far, it is shown which kinds of correlation can be done using the evaluation results obtained from the single surveillance systems. The main part of this report contains the systems analysis of a microcomputer-based system integrating different surveillance methods. After an analysis of the hardware requirements a hardware structure for the integrated system is proposed. The software structure is then described for the subsystem performing the different surveillance algorithms as well as for the system which does the correlation thus deriving additional information from the single results. (orig.) [de

Microprocessor system for data acquisition and processing for the Flora device

International Nuclear Information System (INIS)

Klimov, V.M.

1986-01-01

''VEhFORMIKA'' microprocessor system for data collection and processing when conducting experiments at the ''Flora'' device is described, its application is grounded. The complex allows one to conduct investigations using multichannel methods and exercise the device electrophysical control

Stability of nano-fluids and their use for thermal management of a microprocessor: an experimental and numerical study

Science.gov (United States)

Shoukat, Ahmad Adnan; Shaban, Muhammad; Israr, Asif; Shah, Owaisur Rahman; Khan, Muhammad Zubair; Anwar, Muhammad

2018-03-01

We investigate the heat transfer effect of different types of Nano-fluids on the pin fin heat sinks used in computer's microprocessor. Nano-particles of Aluminum oxide have been used with volumetric concentrations of 0.002% and Silver oxide with volumetric concentrations of 0.001% in the base fluid of deionized water. We have also used Aluminum oxide with ethylene glycol at volumetric concentrations of 0.002%. We report the cooling rates of Nano-fluids for pin-fin heat to cool the microprocessor and compare these with the cooling rate of pure water. We use a microprocessor heat generator in this investigation. The base temperature is obtained using surface heater of power 130 W. The main purpose of this work is to minimize the base temperature, and increase the heat transfer rate of the water block and radiator. The temperature of the heat sink is maintained at 110 °C which is nearly equal to the observed computer microprocessor temperature. We also provide the base temperature at different Reynolds's number using the above mention Nano-fluids with different volumetric concentrations.

CAMAC multipurpose microprocessor controller

International Nuclear Information System (INIS)

Belyakova, M.P.; Nemesh, T.; Buj Zoan Chong.

1978-01-01

The use of CAMAC controllers in an autonomous system of data acquisition and measurement is considered. The system consists of a control intelligence controller, memory modules, and user modules in the CAMAC standard. The controller and all the modules have an output into the highway and this permits to exchange data among them without using special external cables. To increase the servicing rate, an auxiliary controller which has direct access to memory and controls the user modules, is additionally connected to the data acquisition and measurement system. In this case, the intelligence controller is passive. The system of data acquisition can be realized in the form of a multiple system with branch usage. The controller module width is three units, and the controller incorporates the Intel-8080-type microprocessor and the following interfaces: of CAMAC highways, of interruption, of memory bootstrap, and of data sequence channel

Small Private Key PKS on an Embedded Microprocessor

OpenAIRE

Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

2014-01-01

Multivariate quadratic (MQ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to MQ cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key MQ scheme, was proposed, and its feasible implementation on an embedded microprocessor...

Design of microprocessor data acquisition system for pedestrian portal SNM monitor

International Nuclear Information System (INIS)

Zhang Wenliang

2003-01-01

The paper introduces the hardware structure and composition of data acquisition system for pedestrian portal special nuclear material (SNM) monitor. The hardware and software of single chip microprocessor AT89C52, LCM, keyboard and serial communication interface software are also discussed. (authors)

A microprocessor controlled read out system for drift chambers

CERN Document Server

Centro, Sandro; Cittolin, Sergio; Dreesen, P; Petrolo, E; Rubbia, Carlo; Schinzel, D

1981-01-01

Summary form only given, as follows. A General Purpose Microprocessor Controller GPMC has been developed for applications where CAMAC modules with complex control functions are needed. Each application requires an appropriate Interface Module (IM) to be connected to the GPMC. The GPMC consists of a 6800 Microprocessor, 16K EPROM, 2K RAM, CAMAC I/O ports and interface, a RS 232C serial interface, an Advanced Data Link controller and a port for controlling the IM, GPMC and IM are housed in a 2-U wide CAMAC module. A special IM has been designed, which has 1K bute of RAM with its own control and which allows autonomous setting and reading analog voltages through a DAC and ADC. The GPMC can take control of the IM memory and set new voltages. This system is used to control pedestals and gains of a driftchamber readout system, which is housed in a 5-U wide CAMAC module, holding 24 data cards corresponding to 24 sense wires. The data card receives pulses from the left and right end of a sense wire, amplifies and int...

Advanced Transport Operating System (ATOPS) color displays software description microprocessor system

Science.gov (United States)

Slominski, Christopher J.; Plyler, Valerie E.; Dickson, Richard W.

1992-01-01

This document describes the software created for the Sperry Microprocessor Color Display System used for the Advanced Transport Operating Systems (ATOPS) project on the Transport Systems Research Vehicle (TSRV). The software delivery known as the 'baseline display system', is the one described in this document. Throughout this publication, module descriptions are presented in a standardized format which contains module purpose, calling sequence, detailed description, and global references. The global reference section includes procedures and common variables referenced by a particular module. The system described supports the Research Flight Deck (RFD) of the TSRV. The RFD contains eight cathode ray tubes (CRTs) which depict a Primary Flight Display, Navigation Display, System Warning Display, Takeoff Performance Monitoring System Display, and Engine Display.

Microprocessor-controlled wide-range streak camera

Science.gov (United States)

Lewis, Amy E.; Hollabaugh, Craig

2006-08-01

Bechtel Nevada/NSTec recently announced deployment of their fifth generation streak camera. This camera incorporates many advanced features beyond those currently available for streak cameras. The arc-resistant driver includes a trigger lockout mechanism, actively monitors input trigger levels, and incorporates a high-voltage fault interrupter for user safety and tube protection. The camera is completely modular and may deflect over a variable full-sweep time of 15 nanoseconds to 500 microseconds. The camera design is compatible with both large- and small-format commercial tubes from several vendors. The embedded microprocessor offers Ethernet connectivity, and XML [extensible markup language]-based configuration management with non-volatile parameter storage using flash-based storage media. The camera's user interface is platform-independent (Microsoft Windows, Unix, Linux, Macintosh OSX) and is accessible using an AJAX [asynchronous Javascript and XML]-equipped modem browser, such as Internet Explorer 6, Firefox, or Safari. User interface operation requires no installation of client software or browser plug-in technology. Automation software can also access the camera configuration and control using HTTP [hypertext transfer protocol]. The software architecture supports multiple-simultaneous clients, multiple cameras, and multiple module access with a standard browser. The entire user interface can be customized.

Microprocessor-controlled, wide-range streak camera

International Nuclear Information System (INIS)

Amy E. Lewis; Craig Hollabaugh

2006-01-01

Bechtel Nevada/NSTec recently announced deployment of their fifth generation streak camera. This camera incorporates many advanced features beyond those currently available for streak cameras. The arc-resistant driver includes a trigger lockout mechanism, actively monitors input trigger levels, and incorporates a high-voltage fault interrupter for user safety and tube protection. The camera is completely modular and may deflect over a variable full-sweep time of 15 nanoseconds to 500 microseconds. The camera design is compatible with both large- and small-format commercial tubes from several vendors. The embedded microprocessor offers Ethernet connectivity, and XML [extensible markup language]-based configuration management with non-volatile parameter storage using flash-based storage media. The camera's user interface is platform-independent (Microsoft Windows, Unix, Linux, Macintosh OSX) and is accessible using an AJAX [asynchronous Javascript and XML]-equipped modem browser, such as Internet Explorer 6, Firefox, or Safari. User interface operation requires no installation of client software or browser plug-in technology. Automation software can also access the camera configuration and control using HTTP [hypertext transfer protocol]. The software architecture supports multiple-simultaneous clients, multiple cameras, and multiple module access with a standard browser. The entire user interface can be customized

Overview of real-time operating systems on microprocessor platforms

International Nuclear Information System (INIS)

Luong, T.T.

1994-01-01

This paper attempts to overview the real-time operating systems on microprocessor platforms in the field of experimental physics facility controls. The key issues regarding operating systems as well as standards and development environment are discussed. As an illustration, some current industrial products are indicated. Also, real-time systems operating in some institutes of the EPS/EPCS inter divisional group are reviewed. (author). 3 refs., 4 figs

A microprocessor based multiscaling data acquisition system for moessbauer spectroscopy

International Nuclear Information System (INIS)

Bohm, C.; Ekdahl, T.

1985-01-01

A microprocessor based data acquisition system is described, which was developed for use in Moessbauer spectroscopy. It is designed to record two spectra simultaneously, one of which could be a calibration spectrum. It is autonomous, but uses a host computer for initialization and permanent storage of data. The host communication software is also described. (Author)

Microprocessor Recruitment to Elongating RNA Polymerase II Is Required for Differential Expression of MicroRNAs

Directory of Open Access Journals (Sweden)

Victoria A. Church

2017-09-01

Full Text Available The cellular abundance of mature microRNAs (miRNAs is dictated by the efficiency of nuclear processing of primary miRNA transcripts (pri-miRNAs into pre-miRNA intermediates. The Microprocessor complex of Drosha and DGCR8 carries this out, but it has been unclear what controls Microprocessor’s differential processing of various pri-miRNAs. Here, we show that Drosophila DGCR8 (Pasha directly associates with the C-terminal domain of the RNA polymerase II elongation complex when it is phosphorylated by the Cdk9 kinase (pTEFb. When association is blocked by loss of Cdk9 activity, a global change in pri-miRNA processing is detected. Processing of pri-miRNAs with a UGU sequence motif in their apical junction domain increases, while processing of pri-miRNAs lacking this motif decreases. Therefore, phosphorylation of RNA polymerase II recruits Microprocessor for co-transcriptional processing of non-UGU pri-miRNAs that would otherwise be poorly processed. In contrast, UGU-positive pri-miRNAs are robustly processed by Microprocessor independent of RNA polymerase association.

Digital Fractional Order Controllers Realized by PIC Microprocessor: Experimental Results

OpenAIRE

Petras, I.; Grega, S.; Dorcak, L.

2003-01-01

This paper deals with the fractional-order controllers and their possible hardware realization based on PIC microprocessor and numerical algorithm coded in PIC Basic. The mathematical description of the digital fractional -order controllers and approximation in the discrete domain are presented. An example of realization of the particular case of digital fractional-order PID controller is shown and described.

Microprocessor controlled dual parameter ADC system with a CAMAC interface

Energy Technology Data Exchange (ETDEWEB)

Perry, D G; Nickell, Jr, J D [Los Alamos Scientific Lab., NM (USA)

1978-09-01

Presented here is the design of a dual parameter ADC system which is controlled by a microprocessor and also interfaced to CAMAC. The system was designed to be mobile in that it may work wherever there is a CAMAC crate. In such cases where the CAMAC system is inoperative, the system may operate in a stand-alone mode.

THE METHOD OF SELECTION OF THE SETPOINT HIGH SPEED FEEDER SWITCH OF 3,3KV DC WITH MICROPROCESSOR-BASED PROTECTION SYSTEMS

Directory of Open Access Journals (Sweden)

P. Ye. Mykhalichenko

2009-10-01

Full Text Available In the article a new procedure of choice of minimum current jump for action of fast-acting switches of 3.3 kV DC traction substations intended for the use in the microprocessor protection system of feeders is described. This procedure is more perfect than existing one on the current increment and uses the results of mathematical simulation of the traction electric supply system.

Real time computer system with distributed microprocessors

International Nuclear Information System (INIS)

Heger, D.; Steusloff, H.; Syrbe, M.

1979-01-01

The usual centralized structure of computer systems, especially of process computer systems, cannot sufficiently use the progress of very large-scale integrated semiconductor technology with respect to increasing the reliability and performance and to decreasing the expenses especially of the external periphery. This and the increasing demands on process control systems has led the authors to generally examine the structure of such systems and to adapt it to the new surroundings. Computer systems with distributed, optical fibre-coupled microprocessors allow a very favourable problem-solving with decentralized controlled buslines and functional redundancy with automatic fault diagnosis and reconfiguration. A fit programming system supports these hardware properties: PEARL for multicomputer systems, dynamic loader, processor and network operating system. The necessary design principles for this are proved mainly theoretically and by value analysis. An optimal overall system of this new generation of process control systems was established, supported by results of 2 PDV projects (modular operating systems, input/output colour screen system as control panel), for the purpose of testing by apllying the system for the control of 28 pit furnaces of a steel work. (orig.) [de

Applications of microprocessors in upgrading of accelerator controls

International Nuclear Information System (INIS)

Mallory, K.B.

1977-03-01

Experience at SLAC demonstrates that the criteria for selection and use of microprocessors in modifying an existing control system may differ from the criteria that apply during installation of the control system of a new accelerator. Considerations such as cost of individual projects, progressive installation without disruption of operations and training of on-board personnel can outweigh ''obvious'' goals such as standardization of hardware, uniformity of software, or even a rigid specification of link protocols with the main computer system

System architecture for microprocessor based protection system

International Nuclear Information System (INIS)

Gallagher, J.M. Jr.; Lilly, G.M.

1976-01-01

This paper discusses the architectural design features to be employed by Westinghouse in the application of distributed digital processing techniques to the protection system. While the title of the paper makes specific reference to microprocessors, this is only one (and the newest) of the building blocks which constitutes a distributed digital processing system. The actual system structure (as realized through utilization of the various building blocks) is established through considerations of reliability, licensability, and cost. It is the intent of the paper to address these considerations licenstions as they relate to the architectural design features. (orig.) [de

The use of microprocessors at TRIUMF in the control of radiation safety interlock systems

International Nuclear Information System (INIS)

King, L.

1988-01-01

At TRIUMF the cyclotron vault, all primary beam lines, and each experimental area has a dedicated control unit to manage the safety interlock control of the area lockup sequence, beam blocker drive and area access. Typically each area has 24 devices which are monitored to control 16 outputs. These control units (Area Safety Units) were first implemented through the use of relay logic. The relay logic was reliable but difficult to modify to incorporate changes to the areas. In 1979 it was decided to use microprocessors in the form of single board computers to control the Area Safety Units. The details of the hardware and software is discussed as well as the advantages of microprocessor control

Unified microprocessor CAMAC module for preliminary data processing

International Nuclear Information System (INIS)

Zaushitsin, V.L.; Kulik, O.V.; Repin, V.M.

1984-01-01

The UP-80 unified active module is described. It is made in the CAMAC standard on the base of the K580IK80 microprocessor allowing to increase the rate of large-volume experimental spectroscopic data processing by an order. Loading of 5 different programs for data processing is possible. Data from the operative storage with 1K capacity (8 bits) are recorded and read out trhough the CAMAC line (the regime of unit exchange is possible) or through the joint of the external line

Microprocessor-controlled, wide-range streak camera

Energy Technology Data Exchange (ETDEWEB)

Amy E. Lewis, Craig Hollabaugh

2006-09-01

Bechtel Nevada/NSTec recently announced deployment of their fifth generation streak camera. This camera incorporates many advanced features beyond those currently available for streak cameras. The arc-resistant driver includes a trigger lockout mechanism, actively monitors input trigger levels, and incorporates a high-voltage fault interrupter for user safety and tube protection. The camera is completely modular and may deflect over a variable full-sweep time of 15 nanoseconds to 500 microseconds. The camera design is compatible with both large- and small-format commercial tubes from several vendors. The embedded microprocessor offers Ethernet connectivity, and XML [extensible markup language]-based configuration management with non-volatile parameter storage using flash-based storage media. The camera’s user interface is platform-independent (Microsoft Windows, Unix, Linux, Macintosh OSX) and is accessible using an AJAX [asynchronous Javascript and XML]-equipped modem browser, such as Internet Explorer 6, Firefox, or Safari. User interface operation requires no installation of client software or browser plug-in technology. Automation software can also access the camera configuration and control using HTTP [hypertext transfer protocol]. The software architecture supports multiple-simultaneous clients, multiple cameras, and multiple module access with a standard browser. The entire user interface can be customized.

Tools for developing software for different types of microprocessors, to be used, in particular, for the acquisition and processing of nuclear data

International Nuclear Information System (INIS)

Maloeuvre, Michel.

1982-04-01

It is difficult to imagine the realization of a system with a microprocessor without the use of an adapted development system. As these systems are prohibitively expensive, it is difficult for a laboratory to acquire them. A computer, such as the Multi 20 is provided with programme generating tools and supervisors to put the computer's ressources at the microprocessor's disposal. An electronic crate assures interface functions with the computer, the emulation of the microprocessor and the loading of EROM and the live memory lank in order to execute the different units integrated into the crate, enables the crate to be used as a portable repair and maintenance outfit for the materials installed. In the first part of the text, we present the principles of the development tools showing how they are used to realize microprocessor equipment. In the second part, the software is optimized together with the choice of materials in order to define a low cost development system [fr

Implementation of the Two-Point Angular Correlation Function on a High-Performance Reconfigurable Computer

Directory of Open Access Journals (Sweden)

Volodymyr V. Kindratenko

2009-01-01

Full Text Available We present a parallel implementation of an algorithm for calculating the two-point angular correlation function as applied in the field of computational cosmology. The algorithm has been specifically developed for a reconfigurable computer. Our implementation utilizes a microprocessor and two reconfigurable processors on a dual-MAP SRC-6 system. The two reconfigurable processors are used as two application-specific co-processors. Two independent computational kernels are simultaneously executed on the reconfigurable processors while data pre-fetching from disk and initial data pre-processing are executed on the microprocessor. The overall end-to-end algorithm execution speedup achieved by this implementation is over 90× as compared to a sequential implementation of the algorithm executed on a single 2.8 GHz Intel Xeon microprocessor.

The Effect of a Microprocessor Prosthetic Foot on Function and Quality of Life in Transtibial Amputees Who Are Limited Community Ambulators

Science.gov (United States)

2017-09-01

motion and active power , will translate into improved functional performance, ambulatory safety (risk of falls) and quality of life in trans-tibial...clinical trial designed to determine if a microprocessor controlled prosthetic foot (MPF), with greater range of motion and active power , will...contact over a 6 month period of time and receive physical therapy training to minimize deviations resulting from habit or lack of training, education

Microprocessor Control Design for a Low-Head Crossflow Turbine.

Science.gov (United States)

1985-03-01

Controllers For a Typical 10 KW Hydroturbine ............ 1-5 I-1 Ely’s Crossflow Turbine . ........ 11-2 11-2 Basic Turbine * * 0 * 0 11-5 11-3 Turbine...the systems. For example, a 25 kilowatt hydroturbine built and installed by Bell Hydroelectric would cost approximately $20,000 in 1978 (6:49). The...O Manual Controller S2 E- Microprocessor Controller 1 2 3 4 5 6 7 8 YEARS Fig. 1-2 Comparative Costs of Controllers For a Typical 10 KW Hydroturbine

Microprocessor system for data acquisition processing and display for Auger electrons spectrometer

International Nuclear Information System (INIS)

Pawlowski, Z.; Cudny, W.; Hildebrandt, S.; Marzec, J.; Walentek, J.; Zaremba, K.

1984-01-01

Data acquisition system for Auger electron spectrometry is developed. The system is used for chemical and structural analysis of materials and consists of a cylindrical mirror analyzer being a measuring spectrometer device, CAMAC unit and control unit. The control unit comprises a microcomputer based on INTEL 8080 microprocessor and display

The design of an asynchronous Tiny RISC TM/TR4101 microprocessor core

DEFF Research Database (Denmark)

Christensen, Kåre Tais; Jensen, P.; Korger, P.

1998-01-01

This paper presents the design of an asynchronous version of the TR4101 embedded microprocessor core developed by LSI Logic Inc. The asynchronous processor, called ARISC, was designed using the same CAD tools and the same standard cell library that was used to implement the TR4101. The paper repo...

Adapting to change: influence of a microprocessor-controlled prosthetic knee on gait adaptations

NARCIS (Netherlands)

Prinsen, Erik Christiaan

2016-01-01

Advancement in prosthetic knee design have led to the introduction of microprocessor-controlled prosthetic knees (MPKs). MPKs incorporate sensors that are able to measure prosthetic loading, the knee angle, and knee angular velocity. Based on the sensor information, MPKs determine the optimal level

Microprocessor based image processing system

International Nuclear Information System (INIS)

Mirza, M.I.; Siddiqui, M.N.; Rangoonwala, A.

1987-01-01

Rapid developments in the production of integrated circuits and introduction of sophisticated 8,16 and now 32 bit microprocessor based computers, have set new trends in computer applications. Nowadays the users by investing much less money can make optimal use of smaller systems by getting them custom-tailored according to their requirements. During the past decade there have been great advancements in the field of computer Graphics and consequently, 'Image Processing' has emerged as a separate independent field. Image Processing is being used in a number of disciplines. In the Medical Sciences, it is used to construct pseudo color images from computer aided tomography (CAT) or positron emission tomography (PET) scanners. Art, advertising and publishing people use pseudo colours in pursuit of more effective graphics. Structural engineers use Image Processing to examine weld X-rays to search for imperfections. Photographers use Image Processing for various enhancements which are difficult to achieve in a conventional dark room. (author)

Microprocessor system for temperature regulation and stabilization

International Nuclear Information System (INIS)

Nguyen Nhi Dien; Rodionov, K.G.

1989-01-01

Microprocessor based system for temperature regulation and stabilization of an operation external object is described. The system has the direct current amplifier working according to modulator-demodulator principle. The overal gain is 100, 1000, 2000. The maximum output signal is ±10 V. The power amplifier is a thyristor one and its line voltage is 220 V, 50 Hz. The output power is 0-2 kVA. The microcontroller has a remote display terminal. Data input is 8 and data output is one. Input and output voltage is ±(0-10) V. The preselection time for stabilization is within 1 s - 18 h. The program algorithm is given. 5 figs.; 1 tab

Thermal treatment system of hazardous residuals in three heating zones based on a microprocessor

International Nuclear Information System (INIS)

Luna H, C.L.

1997-01-01

Thermal treatment system consists of a high power electric oven of three heating zones where each zone works up to 1200 Centigrades; it has the capacity of rising the central zone temperature up to 1000 Centigrades in 58 minutes approximately. This configuration of three zones could be programmed to different temperatures and they will be digitally controlled by a control microprocessor, which has been controlled by its own assembler language, in function of the PID control. There are also other important controls based on this microprocessor, as a signal amplification, starting and shutdown of high power step relays, activation and deactivation of both analogic/digital and digital/analogic convertors, port activation and basic data storage of the system. Two main characteristics were looked for this oven design; the first was the possibility of controlling the three zone temperature and the second was to reduce the rising and stabilization operation time and its digitized control. The principal function of the three zone oven is to accelerate the degradation of hazardous residuals by an oxidation instead combustion, through relatively high temperatures (minimum 800 Centigrades and maximum 1200 Centigrades); this process reduces the ash and volatile particulate production. The hazardous residuals will be pumped into the degradation system and after atomized through a packaged column; this step will avoid the direct contact of the residuals with the oven cores. These features make this system as closed process, which means that the residuals can not leak to the working area, reducing the exposure risk to the personnel. This three step oven system is the first stage of the complete hazardous residuals degradation system; after this, the flow will go into a cold plasma region where the process is completed, making a closed system. (Author)

Microprocessor-controlled time domain reflectometer for dynamic shock position measurements

International Nuclear Information System (INIS)

Virchow, C.F.; Conrad, G.E.; Holt, D.M.; Hodson, E.K.

1980-01-01

Time-domain reflectometry is used in a novel way to measure dynamically shock propagation in various media. The primary component in this measurement system is a digital time domain reflectometer, which uses local intelligence, a Motorola 6800 microprocessor, to make the unit adaptable and versatile. The recorder, its operating theory and its method of implementation are described and typical data are reviewed. Applications include nuclear explosion yield estimates and explosive energy flow measurements

The bit slice micro-processor 'GESPRO' as a project in the UA2 experiment

International Nuclear Information System (INIS)

Becam, C.; Bernaudin, P.; Delanghe, J.; Mencik, M.; Merkel, B.; Plothow, H.; Fest, H.M.; Lecoq, J.; Martin, H.; Meyer, J.M.

1981-01-01

The bit slice micro-processor GESPRO, as it is proposed for use in the UA 2 data acquisition chain and trigger system, is a CAMAC module plugged into a standard Elliott System crate via which it communicates as a slave with its host computer (ND, DEC). It has full control of CAMAC as a master unit. GESPRO is a 24 bit machine (150 ns effective cycle time) with multi-mode memory addressing capacity of 64 K words. The micro-processor structure uses 5 busses including pipe-line registers to mask access time and 16 interrupt levels. The micro-program memory capacity is 2 K (RAM) words of 48 bits each. A special hardwired module allows floating point (as well as integer) multiplication of 24 x 24 bits, result in 48 bits, in about 200 ns. This micro-processor could be used in the UA2 data acquisition chain and trigger system for the following tasks: a) online data reduction, i.e. to read DURANDAL (fast ADC's = the hardware trigger in the experiment), process the information (effective mass calculation, etc.) resulting in accepting or rejecting the event. b) read out and analysis of the accepted data (collect statistical information). c) preprocess the data (calculation of pointers, address decoding, etc.). The UA2 version of GESPRO is under construction, programs and micro-programs are under development. Hardware and software will be tested with simulated data. First results are expected in about one year from now. (orig.)

A CAMAC-resident microprocessor for the monitoring of polarimeter spin states

International Nuclear Information System (INIS)

Reid, D.; DuPlantis, D.; Yoder, N.; Dale, D.

1992-01-01

A CAMAC module for the reporting of polarimeter spin states is being developed using a resident microcontroller. The module will allow experimenters at the Indiana University Cyclotron Facility to monitor spin states and correlate spin information with other experimental data. The use of a microprocessor allows for adaptation of the module as new requirements ensue without change to the printed circuit board layout. (author)

Use of a microprocessor in the CAMAC standard. The dedicated microcomputer: JCAM-10

International Nuclear Information System (INIS)

Gallice, Pierre.

1978-01-01

The general purpose minicomputers and dedicated crate controllers currently used in small CAMAC systems are now being superseded by autonomous crate controllers with built-in microprocessor such as the JCAM-10, which is in fact a CAMAC dedicated microcomputer. This controller has been designed around the INTEL-8080 microprocessor and employs a semiconductor memory. The very much reduced price and smaller packaging of this module, and the relatively large potential market of CAMAC systems justify the tremendous efforts required for the study of its complete system as well in hardware than in software. After a short description of the CAMAC standard this paper will describe the principle of the microcomputer JCAM-10, and its complementary system: hardware (peripheral modules) and software (TTY command processor, Input Output, Control system, interrupt system, text editor, local macro-assembler, LP and BASICAM local compilers). As application examples, an autonomous counting system and a distributed intelligence system will be described [fr

Microprocessor-based control for independently-phased RF linac cavities

International Nuclear Information System (INIS)

Dawson, J.W.

1979-01-01

A microprocessor based system has been built to control the RF amplifiers associated with independently phased linac cavities. The system has an 8080A at each amplifier station, together with associated ROM, RAM, I/O, etc. At a central NOVA 3 computer an additional 8080A system is incorporated in the interface to the NOVA I/O bus. The NOVA interface is connected by a bus of eighteen twisted pairs to each amplifier station, providing bilateral transmission between each station and the NOVA. The system architecture, bus protocol, and operating characteristics are described

Practical design of digital circuits basic logic to microprocessors

CERN Document Server

Kampel, Ian

1983-01-01

Practical Design of Digital Circuits: Basic Logic to Microprocessors demonstrates the practical aspects of digital circuit design. The intention is to give the reader sufficient confidence to embark upon his own design projects utilizing digital integrated circuits as soon as possible. The book is organized into three parts. Part 1 teaches the basic principles of practical design, and introduces the designer to his """"tools"""" - or rather, the range of devices that can be called upon. Part 2 shows the designer how to put these together into viable designs. It includes two detailed descriptio

Application of Microprocessor-Based Equipment in Nuclear Power Plants - Technical Basis for a Qualification Methodology

International Nuclear Information System (INIS)

Korsah, K.

2001-01-01

This document (1) summarizes the most significant findings of the ''Qualification of Advanced Instrumentation and Control (I and C) Systems'' program initiated by the Nuclear Regulatory Commission (NRC); (2) documents a comparative analysis of U.S. and European qualification standards; and (3) provides recommendations for enhancing regulatory guidance for environmental qualification of microprocessor-based safety-related systems. Safety-related I and C system upgrades of present-day nuclear power plants, as well as I and C systems of Advanced Light-Water Reactors (ALWRs), are expected to make increasing use of microprocessor-based technology. The Nuclear Regulatory Commission (NRC) recognized that the use of such technology may pose environmental qualification challenges different from current, analog-based I and C systems. Hence, it initiated the ''Qualification of Advanced Instrumentation and Control Systems'' program. The objectives of this confirmatory research project are to (1) identify any unique environmental-stress-related failure modes posed by digital technologies and their potential impact on the safety systems and (2) develop the technical basis for regulatory guidance using these findings. Previous findings from this study have been documented in several technical reports. This final report in the series documents a comparative analysis of two environmental qualification standards--Institute of Electrical and Electronics Engineers (IEEE) Std 323-1983 and International Electrotechnical Commission (IEC) 60780 (1998)--and provides recommendations for environmental qualification of microprocessor-based systems based on this analysis as well as on the findings documented in the previous reports. The two standards were chosen for this analysis because IEEE 323 is the standard used in the U.S. for the qualification of safety-related equipment in nuclear power plants, and IEC 60780 is its European counterpart. In addition, the IEC document was published in

AFRRI's conversion to a microprocessor-based reactor instrumentation and control system

International Nuclear Information System (INIS)

Moore, Mark L.; Hodgdon, Kenneth M.

1986-01-01

The Armed Forces Radiobiology Research Institute (AFRRI) is procuring a state-of- the-art microprocessor-based instrumentation and control system to operate AFRRI's 1 MW (steady-state), 3000 MW (pulse) TRIGA Mark-F reactor. This system will replace the current control console while improving or maintaining the existing operational capabilities and safety characteristics. The new unit will have a 15-year design life using state-of-the-art components

Use of a microprocessor in a remote working level monitor

International Nuclear Information System (INIS)

Keefe, D.J.; McDowell, W.P.; Groer, P.G.

1976-01-01

The instrument described measures the short-lived 222 Rn-daughter concentrations and the Working Level (WL) in sealed ''hot chambers'' located in uranium mines. Radiation-induced pulses from two separate sensors are transmitted through 500 ft. cables to a microprocessor, which processes the pulses and controls the operation of the system. A read-only memory stores a fixed program which is used to calculate the desired concentrations. The results are printed as pCi/l (Rn-daughter concentrations) and WL

EOSCOR: a light weight, microprocessor controlled solar neutron detector

International Nuclear Information System (INIS)

Koga, R.; Albats, P.; Frye, G.M. Jr.; Schindler, S.M.; Denehy, B.V.; Hopper, V.D.; Mace, O.B.

1979-01-01

A light weight high energy neutron detector with vertical detection efficiency of 0.005 at 40 MeV and 1.4 m 2 sensitive area has been developed for long duration super-pressure balloon flight observations of solar neutrons and gamma rays. It consists of two sets of four plastic scintillator hodoscopes separated by a 1 m time-of-flight path to observe n-p, C(n,p), and C(n,d) interactions. The neutron interactions are separated from gamma ray events through TOF measurements. For a large flare, the signal from solar neutrons is expected to be an order of magnitude greater than that of the atmospheric background. The microprocessor controls the data acquisition, accumulation of histograms, and the encoding of data for the telemetry systems. A test flight of the detector was made with a zero-pressure balloon. The expected many-week duration of a super-pressure balloon flight would significantly increase the probability of observing 20-150 MeV neutrons from a medium or large flare. (Auth.)

Microprocessor-assisted calibration for a remote working level monitor

International Nuclear Information System (INIS)

McDowell, W.P.; Keefe, D.J.; Groer, P.G.; Witek, R.T.

1977-01-01

A method is described for calibrating a Remote Working Level Monitor, an instrument which measures Working Level and Rn-daughter concentrations in the atmosphere. The method makes use of a microprocessor to calculate beta efficiencies for RaB and RaC from the counts accumulated in the RaA, Ra(B + C) and RaC' channels of the instrument. Both the alpha spectroscopic and total-alpha methods are used to determine the Rn-daughter concentrations. These methods require the processor to solve systems of linear equations with several unknowns. No assumptions about Rn-daughter equilibrium are made

Microprocessor-assisted calibration for a remote working level monitor

International Nuclear Information System (INIS)

McDowell, W.P.; Keefe, D.J.; Groer, P.G.; Witek, R.T.

1976-01-01

A method is described for calibrating a Remote Working Level Monitor, an instrument which measures Working Level and Rn-daughter concentrations in the atmosphere. The method makes use of a microprocessor to calculate beta efficiencies for RaB and RaC from the counts accumulated in the RaA, Ra(B + C) and RaC' channels of the instrument. Both the alpha spectroscopic and total-alpha methods are used to determine the Rn-daughter concentrations. These methods require the processor to solve systems of linear equations with several unknowns. No assumptions about Rn-daughter equilibrium are made

Microprocessor-controlled inhalation system for repeated exposure of animals to aerosols

International Nuclear Information System (INIS)

Carpenter, R.L.; Barr, F.P.; Leydig, R.L.; Rajala, R.E.

1979-01-01

A microprocessor-controlled inhalation exposure system (MCIES) has been built to automate aerosol generation and sampling while controlling exposure time for animal toxicity studies. The system has a time resolution of 0.1 s and automatically sequences the exposure events from initiation to temination of the exposure. The operator is required to preset all airflows, read in a paper tape containing the time sequence of events, and initiate the automatic sequence by closing a switch

A monitoring and protective system for mine hoists using a microprocessor

Energy Technology Data Exchange (ETDEWEB)

Jianlin, Zhu

1981-11-01

In view of the existing problems of depth indicators and tachometers currently used in mine hoists, a measuring technique using a 'wire cable magnetic stripe' and a tentative proposal for a monitoring system with a microprocessor are described. The system can be used for measuring and indicating the depth, speed of the hoisting system, and can provide protection against overwinding, overspeeding and slack rope as well as monitoring the direction of hoisting. (In Chinese)

A lightweight security scheme for wireless body area networks: design, energy evaluation and proposed microprocessor design.

Science.gov (United States)

Selimis, Georgios; Huang, Li; Massé, Fabien; Tsekoura, Ioanna; Ashouei, Maryam; Catthoor, Francky; Huisken, Jos; Stuyt, Jan; Dolmans, Guido; Penders, Julien; De Groot, Harmke

2011-10-01

In order for wireless body area networks to meet widespread adoption, a number of security implications must be explored to promote and maintain fundamental medical ethical principles and social expectations. As a result, integration of security functionality to sensor nodes is required. Integrating security functionality to a wireless sensor node increases the size of the stored software program in program memory, the required time that the sensor's microprocessor needs to process the data and the wireless network traffic which is exchanged among sensors. This security overhead has dominant impact on the energy dissipation which is strongly related to the lifetime of the sensor, a critical aspect in wireless sensor network (WSN) technology. Strict definition of the security functionality, complete hardware model (microprocessor and radio), WBAN topology and the structure of the medium access control (MAC) frame are required for an accurate estimation of the energy that security introduces into the WBAN. In this work, we define a lightweight security scheme for WBAN, we estimate the additional energy consumption that the security scheme introduces to WBAN based on commercial available off-the-shelf hardware components (microprocessor and radio), the network topology and the MAC frame. Furthermore, we propose a new microcontroller design in order to reduce the energy consumption of the system. Experimental results and comparisons with other works are given.

Very High-Performance Embedded Computing Will Allow Ambitious Space Science Investigation

National Research Council Canada - National Science Library

Pignol, Michel

2005-01-01

.... developed on radiation tolerant technologies. Unfortunately, the microprocessors today available on such technologies have the computing throughput which was available about 10 years ago on the commercial market...

Autonomous controller (JCAM 10) for CAMAC crate with 8080 (INTEL) microprocessor

International Nuclear Information System (INIS)

Gallice, P.; Mathis, M.

1975-01-01

The CAMAC crate autonomous controller JCAM-10 is designed around an INTEL 8080 microprocessor in association with a 5K RAM and 4K REPROM memory. The concept of the module is described, in which data transfers between CAMAC modules and the memory are optimised from software point of view as well as from execution time. In fact, the JCAM-10 is a microcomputer with a set of 1000 peripheral units represented by the CAMAC modules commercially available

Monitoring with new microprocessor cuts cost of control system

Energy Technology Data Exchange (ETDEWEB)

Maehling, K L

1985-08-01

Programmable logic controllers (PLC) were originally developed as an alternative to relays, counters and timers for sequential and interlock control systems. They are now also used as part of distributive control systems which include diagnostic monitoring functions. The paper describes how a wiring scheme can be simplified and installation costs reduced by incorporating a newly-developed microprocessor-based monitoring device as an interface between remote devices and a PLC. An industrial application, the 400 tph coal handling facility at Bowater Southern Paper Co's mill in Calhoun, Tennessee, is considered. The control system design is outlined, the micro-monitor is described and the benefits of simplicity are stated in the paper.

Use of a Microprocessor to Implement an ADCCP Protocol (Federal Standard 1003).

Science.gov (United States)

1980-07-01

results of other studies, to evaluate the operational and economic impact of incorporating various options in Federal Standard 1003. The effort...the LSI interface and the microprocessor; the LSI chip deposits bytes in its buffer as the producer, and the MPU reads this data as the consumer...on the interface between the MPU and the LSI protocol chip. This requires two main processes to be running at the same time--transmit and receive. The

Low cost design of microprocessor EDAC circuit

International Nuclear Information System (INIS)

Hao Li; Yu Lixin; Peng Heping; Zhuang Wei

2015-01-01

An optimization method of error detection and correction (EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies. (paper)

Data acquisition and processing system of energy dispersive X-ray spectrometer with microprocessor

International Nuclear Information System (INIS)

Horkay, G.; Kis-Varga, M.; Lakatos, T.; Molnar, J.; Zsurzs, M.

1984-01-01

For quantitative analysis of chemical elements by the method of X-ray spectroscopy a multichannel analyzer on the base of minicomputer with the INTEL 8080 A microprocessor is developed. The data acquisition and data processing systems which comprise a central processor, memory unit, ADC and display are described. Major system subprograms are enumerated. An example of Pb concentration determinating in a bronze specimen is given

FPGAs in High Perfomance Computing: Results from Two LDRD Projects.

Energy Technology Data Exchange (ETDEWEB)

Underwood, Keith D; Ulmer, Craig D.; Thompson, David; Hemmert, Karl Scott

2006-11-01

Field programmable gate arrays (FPGAs) have been used as alternative computational de-vices for over a decade; however, they have not been used for traditional scientific com-puting due to their perceived lack of floating-point performance. In recent years, there hasbeen a surge of interest in alternatives to traditional microprocessors for high performancecomputing. Sandia National Labs began two projects to determine whether FPGAs wouldbe a suitable alternative to microprocessors for high performance scientific computing and,if so, how they should be integrated into the system. We present results that indicate thatFPGAs could have a significant impact on future systems. FPGAs have thepotentialtohave order of magnitude levels of performance wins on several key algorithms; however,there are serious questions as to whether the system integration challenge can be met. Fur-thermore, there remain challenges in FPGA programming and system level reliability whenusing FPGA devices.4 AcknowledgmentArun Rodrigues provided valuable support and assistance in the use of the Structural Sim-ulation Toolkit within an FPGA context. Curtis Janssen and Steve Plimpton provided valu-able insights into the workings of two Sandia applications (MPQC and LAMMPS, respec-tively).5

A fail-safe microprocessor-based protection system utilising low-level multiplexed sensor signals

International Nuclear Information System (INIS)

Orme, S.; Evans, N.J.; Wey, B.O.

1985-01-01

The paper describes a fail-safe reactor protection system, called the individual sub-assembly temperature monitoring system (ISAT). It is being developed for the commercial demonstration fast reactor. The system incorporates recent advances in solid-state electronics and in particular microprocessors to implement time-shared data acquisition techniques to obtain and process data from around 1400 fast response thermocouples whilst meeting the required levels for reliability and availability. (author)

Electric protections based in microprocessors in power plants; Protecciones electricas basadas en microprocesadores en centrales generadoras

Energy Technology Data Exchange (ETDEWEB)

Libreros, Domitilo; Castanon Jimenez, Jose Ismael [Instituto de Investigaciones Electricas, Cuernavaca (Mexico)

1988-12-31

This article is centered around the substitution of the conventional electric protections of a power plant in connection type unit for protections based in microprocessors. A general model of conventional protection of a power plant is described and the number of analogic and digital signals that intervene in that model are quantified. A model is setup for power plant protection with microprocessors, analyzing each one of the modules that would form it. Finally, the algorithms to carry on such protection are presented. [Espanol] Este articulo se centra en torno a la sustitucion de las protecciones electricas convencionales de una central generadora en conexion tipo unidad por protecciones basadas en microprocesadores. Se describe el modelo general de proteccion convencional de una central generadora y se cuantifica el numero de senales analogicas y digitales que interviene en dicho modelo. Se propone un modelo para proteccion de centrales generadoras mediante microprocesadores, analizandose cada uno de los modulos que lo conformarian. Finalmente, se presentan los algoritmos para realizar dicha proteccion.

Electric protections based in microprocessors in power plants; Protecciones electricas basadas en microprocesadores en centrales generadoras

Energy Technology Data Exchange (ETDEWEB)

Libreros, Domitilo; Castanon Jimenez, Jose Ismael [Instituto de Investigaciones Electricas, Cuernavaca (Mexico)

1987-12-31

This article is centered around the substitution of the conventional electric protections of a power plant in connection type unit for protections based in microprocessors. A general model of conventional protection of a power plant is described and the number of analogic and digital signals that intervene in that model are quantified. A model is setup for power plant protection with microprocessors, analyzing each one of the modules that would form it. Finally, the algorithms to carry on such protection are presented. [Espanol] Este articulo se centra en torno a la sustitucion de las protecciones electricas convencionales de una central generadora en conexion tipo unidad por protecciones basadas en microprocesadores. Se describe el modelo general de proteccion convencional de una central generadora y se cuantifica el numero de senales analogicas y digitales que interviene en dicho modelo. Se propone un modelo para proteccion de centrales generadoras mediante microprocesadores, analizandose cada uno de los modulos que lo conformarian. Finalmente, se presentan los algoritmos para realizar dicha proteccion.

Microprocessor-based data acquisition system for extensive air shower studies

International Nuclear Information System (INIS)

Mazumdar, G.K.D.; Kalita, P.M.; Bordoloi, T.C.; Pathak, K.M.

1989-01-01

Studies on electromagnetic radiation from large extensive air showers (Esub(p) ≥> 10 16 eV) have been of recent importance in the investigation of properties of EAS in problems involving mass composition, arrival time, radio emission. Cerenkov radiation etc. Such studies need fast electronic circuitry preferably for digitisation. A microprocessor based data acquisition system having scintillation counters, PA, MA, Pd, S/H and control unit has been developed and is being used in the EAS studies at Gauhati University Cosmic Ray Research Laboratory. Description of the different units along with their functioning and method of standardisation is presented in this paper. (author). 3 figs

Stair ascent with an innovative microprocessor-controlled exoprosthetic knee joint.

Science.gov (United States)

Bellmann, Malte; Schmalz, Thomas; Ludwigs, Eva; Blumentritt, Siegmar

2012-12-01

Climbing stairs can pose a major challenge for above-knee amputees as a result of compromised motor performance and limitations to prosthetic design. A new, innovative microprocessor-controlled prosthetic knee joint, the Genium, incorporates a function that allows an above-knee amputee to climb stairs step over step. To execute this function, a number of different sensors and complex switching algorithms were integrated into the prosthetic knee joint. The function is intuitive for the user. A biomechanical study was conducted to assess objective gait measurements and calculate joint kinematics and kinetics as subjects ascended stairs. Results demonstrated that climbing stairs step over step is more biomechanically efficient for an amputee using the Genium prosthetic knee than the previously possible conventional method where the extended prosthesis is trailed as the amputee executes one or two steps at a time. There is a natural amount of stress on the residual musculoskeletal system, and it has been shown that the healthy contralateral side supports the movements of the amputated side. The mechanical power that the healthy contralateral knee joint needs to generate during the extension phase is also reduced. Similarly, there is near normal loading of the hip joint on the amputated side.

Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

OpenAIRE

Abdul Kareem PARCHUR; Ram Asaray SINGH

2012-01-01

High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310). The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many ke...

ITRA 084 - a microprocessor controlled rapid analyzer in mining and metallurgy

International Nuclear Information System (INIS)

Kliem, V.; Kreher, M.; Boy, N.

1986-01-01

A new rapid analyzer of the ITRA series has been developed at the Freiberg Research Institute of Non-Ferrous Metals for single and multi-element analysis in mining and non-ferrous metallurgy. INTRA-08 represents an efficient microprocessor-controlled on-line X-ray fluorescence analyzer based on the main principles utilized with success hitherto in device engineering (isotope excitation, four-channel modification, balance filter method). A U880 single-chip microcomputer provides the central control of the device including the execution of an extensive program for the matrix correction. The efficiency of the analyzer is demonstrated taking measured values as a basis

Wide-bandwidth low-voltage PLL for powerPC(sup TM) microprocessors

Science.gov (United States)

Alvarez, Jose; Sanchez, Hector; Gerosa, Gianfranco; Countryman, Roger

1995-04-01

A 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 micron CMOS technology is described. The PLL supports internal to external clock frequency ratios of 1, 1.5, 2, 3, and 4 as well as numerous static power down modes for PowerPC(sup TM) microprocessors. The CPU clock lock range spans from 6 to 175 MHz. Lock times below 15 mu s, PLL power dissipation below 10mW as well as phase error and jitter below +/- 100 ps have been measured. The total area of the PLL is 0.52 mm(exp 2).

Dual photon absorptiometer utilizing a HpGe detector and microprocessor controller

International Nuclear Information System (INIS)

Ellis, K.J.; Vartsky, D.; Pearlstein, T.B.; Alberi, J.L.; Cohn, S.H.

1978-01-01

The analysis of bone mineral content (BMC) using a single energy-photon beam assumes that there are only two materials present, bone mineral and a uniform soft tissue component. Uncertainty in the value of BMC increases with different adipose tissue components in the transmitted beam. These errors, however, are reduced by the dual energy technique. Also, extension to additional energies further identifies the separate constituents of the soft tissue component. A multi-energy bone scanning apparatus with data acquisition and analysis capability sufficient to perform multi-energy analysis of bone mineral content was designed and developed. The present work reports on the development of device operated in the dual energy mode. The high purity germanium (HpGe) detector is an integral component of the scanner. Errors in BMC due to multiple small angle scatters are reduced due to the excellent energy resolution of the detector (530 eV at 60 keV). Also, the need to filter the source or additional collimation on the detector is eliminated. A new dual source holder was designed using 200 mCi 125 I and 100 mCi 241 Am. The active areas of the two source capsules are aligned on a common axis. The congruence of the dual source was verified by measuring the collimator response function. This new holder design insures that the same tissue mass simultaneously attenuates both sources. The controller portion of the microprocessor allows for variation in total scan length, step size, and counting time per step. These options allow for multiple measurements without changes in the detector, source, or collimator. The system has been successfully used to determine the BMC content of different bones

Application of a microprocessor system to stream monitoring

International Nuclear Information System (INIS)

Oakes, T.W.; Shank, K.E.

1978-01-01

Low-level liquid wastes originating from the Oak Ridge National Laboratory (ORNL) are discharged, after treatment, into White Oak Creek, which is a small tributary of the Clinch River located in East Tennessee. Samples of White Oak Creek discharges are collected at White Oak Dam by a continuous digital proportional water sampler and analyzed weekly for radioactivity. The sampler contains a control system with a microprocessor that has been programmed to solve nonlinear weir equations. This system was designed and installed at ORNL by the Instrumentation and Controls Division and was tested by the Environmental Surveillance and Evaluation Section of the Industrial Safety and Applied Health Physics Division. The control system was designed to measure water flow rates from 0 to 334 ft 3 /sec to within 0.1%. Results of our test program and possible applications to other liquid sampling needs are discussed

A low cost, microprocessor-based battery charge controller

Energy Technology Data Exchange (ETDEWEB)

Pulfrey, D L; Hacker, J [Pulfrey Solar Inc., Vancouver, BC (Canada)

1990-01-01

This report describes the design, construction, testing, and evaluation of a microprocessor-based battery charge controller that uses charge integration as the method of battery state-of-charge estimation. The controller is intended for use in medium-size (100-1000W) photovoltaic systems that employ 12V lead-acid batteries for charge storage. The controller regulates the charge flow to the battery and operates in three, automatically-determined modes, namely: charge, equalize, and float. The prototype controller is modular in nature and can handle charge/discharge currents of magnitude up to 80A, depending on the number of circuit boards employed. Evaluation tests and field trials have shown the controller to be very accurate and reliable. Based on the cost of the prototype, it appears that an original equipment manufacturer's selling price of $400 for a 40A (500W) unit may be realistic. 18 figs., 2 tabs.

Microprocessor-controlled tester for evaluation of the Self-Energized Credential System (SECS)

International Nuclear Information System (INIS)

Corlis, N.E.

1980-03-01

The Self-Energized Credential System (SECS) was developed for use in the Plutonium Protection System (PPS) installed at Hanford, Washington. Evaluation and development of the SECS system was enhanced by the use of a microprocessor-controlled portal tester. This tester used infrared (ir) beam sensors to provide information on the direction of travel of the credential wearer and to detect inoperative credentials. A printed record of the portal number, actual code read, time, and direction of the credential passage provided information essential to an assessment of the operability of the SECS

Microprocessor-based system for continuous monitoring of radiation levels around the CERN PS and PSB accelerators

Energy Technology Data Exchange (ETDEWEB)

Agoritsas, V.; Beck, F.; Benincasa, G.P.; Bovigny, J.P.

1986-06-01

This paper describes a new beam loss monitor system which has been installed in the PS and PSB machines, replacing an earlier system. The new system is controlled by a microprocessor which can operate independently of the accelerator control system, though setting up and central display are usually done remotely, using the standard control system facilities.

Emulation of MS DOS Operational System on the Autonomous Crate-Controller with I8086 microprocessor

International Nuclear Information System (INIS)

Hons, Z.; Cizek, P.; Streit, V.

1988-01-01

KM-DOS operating system for CAMAC autonomous crate-controller based on Intel 8086/8087 microprocessor connected with Pravec-16 IBM PC is described. The KM-DOS system fully emulates the MS DOS environment on the CAMAC controller. Thus ASSEMBLER, FORTRAN, C and PASCAL programs compiled and linked on IBM PC and compatible can be run on the CAMAC controller and parall work of both computers is enabled

Equipment calibration with a microprocessor connected to a time-sharing system

International Nuclear Information System (INIS)

Fontaine, G.; Guglielmi, L.; Jaeger, J.J.; Szafran, S.

1981-01-01

In H.E.P., it is common practice to test and calibrate equipment at different stages (design, construction checks, setting up and running periods) with a dedicated mini or micro-computer (such as CERN CAVIAR). An alternative solution has been developed in which such tasks are split between a microprocessor (Motorola 6800), and a host computer; this allows an easy and cheap multiplication of independant testing set-ups. The local processor is limited to CAMAC data acquisition, histogramming and simple processing, but its computing power is enhanced by a connection to a host time-sharing system via a MUMM multiplexor described in a separate paper. It is thus possible to perform sophisticated computations (fits etc...) and to use the host disk space to store calibration results for later use. In spite of the use of assembly language, a software structure has been devised to ease the constitution of an application program. This is achieved by the interplay of three levels of facilities: macro-instructions, library of subroutines, and Patchy controlled pieces of programs. A comprehensive collection of these is kept in the form of PAM files on the host computer. This system has been used to test calorimeter modules for the UA 1 experiment. (orig.)

Software support for Motorola 68000 microprocessor at CERN. M68MIL cross macro assembler

International Nuclear Information System (INIS)

Eicken, H. von.

1983-01-01

This document is a user's guide for programming the Motorola 68000 microprocessor in assembly language. It describes the programming model, addressing modes and instruction set of the M 68000 as well as the use of the M68mil cross macro assembler. Version 3.6 of the assembler has been installed at CERN on CDC, DEC VAX, IBM, Norsk Data and Siemens computers. The source code of the assembler is available from CERN on request. (orig.)

Microprocessor isotope gauges for measurement of coating thickness and of air dust pollution

International Nuclear Information System (INIS)

Machaj, B.; Zrudelny, F.; Sikora, A.; Jaszczuk, J.

1986-01-01

The article describes a coating thickness gauge based on measurement of backscattered beta particles, and an air dust pollution gauge based on measurement of dust deposited from known volume of ambient air passed through a filter, by attenuation of beta radiation. In both cases to control the gauges and to process head signals microcomputer system based on Intel 8080 microprocessor is employed. Algorithms for processing and control of the gauges and corresponding flow charts are presented. Block diagram of microcomputer system used is presented, as well as the manner of operation of the gauges. (author)

Development of the self-learning machine for creating models of microprocessor of single-phase earth fault protection devices in networks with isolated neutral voltage above 1000 V

Science.gov (United States)

Utegulov, B. B.; Utegulov, A. B.; Meiramova, S.

2018-02-01

The paper proposes the development of a self-learning machine for creating models of microprocessor-based single-phase ground fault protection devices in networks with an isolated neutral voltage higher than 1000 V. Development of a self-learning machine for creating models of microprocessor-based single-phase earth fault protection devices in networks with an isolated neutral voltage higher than 1000 V. allows to effectively implement mathematical models of automatic change of protection settings. Single-phase earth fault protection devices.

GPS/MEMS IMU/Microprocessor Board for Navigation

Science.gov (United States)

Gender, Thomas K.; Chow, James; Ott, William E.

2009-01-01

A miniaturized instrumentation package comprising a (1) Global Positioning System (GPS) receiver, (2) an inertial measurement unit (IMU) consisting largely of surface-micromachined sensors of the microelectromechanical systems (MEMS) type, and (3) a microprocessor, all residing on a single circuit board, is part of the navigation system of a compact robotic spacecraft intended to be released from a larger spacecraft [e.g., the International Space Station (ISS)] for exterior visual inspection of the larger spacecraft. Variants of the package may also be useful in terrestrial collision-detection and -avoidance applications. The navigation solution obtained by integrating the IMU outputs is fed back to a correlator in the GPS receiver to aid in tracking GPS signals. The raw GPS and IMU data are blended in a Kalman filter to obtain an optimal navigation solution, which can be supplemented by range and velocity data obtained by use of (l) a stereoscopic pair of electronic cameras aboard the robotic spacecraft and/or (2) a laser dynamic range imager aboard the ISS. The novelty of the package lies mostly in those aspects of the design of the MEMS IMU that pertain to controlling mechanical resonances and stabilizing scale factors and biases.

A microprocessor-based system for continuous monitoring of radiation levels around the CERN PS and PSB accelerators

Science.gov (United States)

Agoritsas, V.; Beck, F.; Benincasa, G. P.; Bovigny, J. P.

1986-06-01

This paper describes a new beam loss monitor system which has been installed in the PS and PSB machines, replacing an earlier system. The new system is controlled by a microprocessor which can operate independently of the accelerator control system, though setting up and central display are usually done remotely, using the standard control system facilities.

MONICA - a programmable microprocessor for track recognition in an e+e- experiment at PETRA

International Nuclear Information System (INIS)

Schildt, P.; Stuckenberg, H.J.; Wermes, N.

1981-01-01

The microprocessor device MONICA is used in the TASSO experiment at PETRA. Its task is to reconstruct events in the cylindrical driftchamber on-line. Used as an event filter MONICA provides a 2 prong trigger without any further requirements. The speed of the processor (event reconstruction times must be in the order of 1 ms) is achieved by a 4 x 4 bit slice processor in ECL technology, content addressable memories and table look up. The track finding efficiency is 80%. (orig.)

A Fourier transform with speed improvements for microprocessor applications

Science.gov (United States)

Lokerson, D. C.; Rochelle, R.

1980-01-01

A fast Fourier transform algorithm for the RCA 1802microprocessor was developed for spacecraft instrument applications. The computations were tailored for the restrictions an eight bit machine imposes. The algorithm incorporates some aspects of Walsh function sequency to improve operational speed. This method uses a register to add a value proportional to the period of the band being processed before each computation is to be considered. If the result overflows into the DF register, the data sample is used in computation; otherwise computation is skipped. This operation is repeated for each of the 64 data samples. This technique is used for both sine and cosine portions of the computation. The processing uses eight bit data, but because of the many computations that can increase the size of the coefficient, floating point form is used. A method to reduce the alias problem in the lower bands is also described.

Proposal for the award of a blanket order contract for the supply of microprocessor-based protection and control devices for the CERN HV distribution network

CERN Document Server

2004-01-01

This document concerns the award of a blanket contract for the supply of microprocessor-based protection and control devices for the CERN HV distribution network. The Finance Committee is invited to agree to the negotiation of a blanket order contract with SCHNEIDER ELECTRIC (PT), the lowest technically acceptable bidder after realignment, for the supply of microprocessor-based protection and control devices for the CERN HV distribution network for a total amount of 1 900 000 euros (2 924 128 Swiss francs), subject to revision for inflation after 1 January 2007. The rate of exchange used is that stipulated in the tender

SEU simulation and testing of resistor-hardened D-latches in the SA3300 microprocessor

International Nuclear Information System (INIS)

Sexton, F.W.; Corbett, W.T.; Treece, R.K.; Hass, K.J.; Axness, C.L.; Hash, G.L.; Shaneyfelt, M.R.; Wunsch, T.F.; Hughes, K.L.

1991-01-01

In this paper the SEU tolerance of the SA3300 microprocessor with feedback resistors is presented and compared to the SA3300 without feedback resistors and to the commercial version (NS32016). Upset threshold at room temperature increased from 23 MeV-cm 2 /mg and 180 MeV-cm 2 /mg with feedback resistors of 50 kΩ and 160 kΩ, respectively. The performance goal of 10 MHz over the full temperature range of -55 degrees C to +125 degrees C is exceeded for feedback resistors of 160 kΩ and less. Error rate calculations for this design predict that the error rate is less than once every 100 years when 50 kΩ feedback resistors are used in the D-latch design. Analysis of the SEU response using a lumped-parameter circuit simulator imply a charge collection depth of 4.5 μm. This is much deeper than the authors would expect for prompt collection in the epi and funnel regions and has been explained in terms of diffusion current in the heavily doped substrate

A rapid high-performance liquid-chromatographic method for simultaneously determining the concentrations of TFM and Bayer 73 in water during lampricide treatments

Science.gov (United States)

Dawson, V.K.

1982-01-01

The high-performance liquid-chromatography (HPLC) procedure requires only minutes per sample, is specific, and is relatively sensitive (limit of detection 18 disposable cartridge. The cartridge adsorbs and retains both the lampricides and the internal standard. The quantitative elution of the three chemicals from the cartridge with a small volume of methanol effectively concentrates the sample and provides sample cleanup. The methanol extract is then analyzed directly by HPLC on an MCH 10 reverse phase column by using a methanol:0.01 mol/L acetate buffer (87:13, v:v) as the mobile phase at 2 mL/min and detected by ultraviolet spectrophotometry at 330 (or 254) nm. A microprocessor data system further facilitates the procedure by quantifying off-scale peaks and yielding results directly in units of concentration (mg/L).

Front end embedded microprocessors in the JET computer-based control system, past, present and future

International Nuclear Information System (INIS)

Steed, C.A.; VanderBeken, H.; Browne, M.L.; Fullard, K.; Reed, K.; Tilley, M.; Schmidt, V.

1987-01-01

A brief history of the use of Front End Microprocessors in the JET Control and Data Acquisition System (CODAS) is presented. The present expansion in their use from 2 or 3 in 1983 to 27 now, is covered along with the reasoning behind their present usage. Finally, their future planned use in the area of remote handling is discussed and the authors present views on the use of front end processing in future large distributed control systems are presented

A microprocessor based monitoring system for a small nuclear reactor facility

International Nuclear Information System (INIS)

Miller, G.E.; DeKeyser, C.F.

1980-01-01

An inexpensive microprocessor based system has been designed and constructed for our 250 kilowatt TRIGA reactor facility. The system, which is beginning operational testing, can monitor on a continuous basis the status of up to 54 devices and maintain a record of events. These devices include fixed radiation monitors, pool water level trips, security alarms and an access control unit. In the latter case, the unit permits selection of different levels of access permission based on the time of day. The system can alert security and other personnel in the event of abnormalities. Because of the inclusion of this in the security system, special reliability and failure mode operation. The unit must also be simple to install, program and operate. (author)

Advances in Sensors-Centric Microprocessors and System-on-Chip

Directory of Open Access Journals (Sweden)

Juan A. Gómez-Pulido

2012-04-01

Full Text Available Sensors-based systems are nowadays an extended technology for many markets due to their great potential in the collection of data from the environment and the processing of such data for different purposes. A typical example is the wireless sensor devices, where the outer temperature, humidity, luminosity and many other parameters can be acquired, measured and processed in order to build useful and fascinating applications that contribute to human welfare. In this scenario, the processing architectures of the sensors-based systems play a very important role. The requirements that are necessary for many such applications (real-time processing, low-power consumption, reduced size, reliability, security and many others means that research on advanced architectures of Microprocessors and System-on-Chips (SoC is needed to design and implement a successful product. In this sense, there are many challenges and open questions in this area that need to be addressed. [...

Data acquisition and command system for use with a microprocessor-based control chassis

International Nuclear Information System (INIS)

Halbig, J.K.; Klosterbuer, S.F.; Martinez, V.A. Jr.

1980-01-01

The Pion Generation for Medical Irradiations (PIGMI) program at the Los Alamos Scientific Laboratory is developing the technology to build smaller, less expensive, and more reliable proton linear accelerators for medical applications, and has designed a powerful, simple, inexpensive, and reliable control and data acquisition system that is central to the program development. The system is a NOVA-3D minicomputer interfaced to several outlying microprocessor-based controllers, which accomplish control and data acquisition through data I/O chasis. The equipment interface chassis, which can issue binary commands, read binary data, issue analog commands, and read timed and untimed analog data is described

An Embedded System for Safe, Secure and Reliable Execution of High Consequence Software

Energy Technology Data Exchange (ETDEWEB)

MCCOY,JAMES A.

2000-08-29

As more complex and functionally diverse requirements are placed on high consequence embedded applications, ensuring safe and secure operation requires an execution environment that is ultra reliable from a system viewpoint. In many cases the safety and security of the system depends upon the reliable cooperation between the hardware and the software to meet real-time system throughput requirements. The selection of a microprocessor and its associated development environment for an embedded application has the most far-reaching effects on the development and production of the system than any other element in the design. The effects of this choice ripple through the remainder of the hardware design and profoundly affect the entire software development process. While state-of-the-art software engineering principles indicate that an object oriented (OO) methodology provides a superior development environment, traditional programming languages available for microprocessors targeted for deeply embedded applications do not directly support OO techniques. Furthermore, the microprocessors themselves do not typically support nor do they enforce an OO environment. This paper describes a system level approach for the design of a microprocessor intended for use in deeply embedded high consequence applications that both supports and enforces an OO execution environment.

Microprocessor-controlled meter of high Q-values

International Nuclear Information System (INIS)

Bun'kov, S.N.; Konstantinov, V.I.; Masalov, V.L.; Sevrukova, L.M.; Tokarev, A.D.; Usiv, Yu.V.

1990-01-01

The paper describes the functional model of a high-precision microcomputer-controlled test facility for studying the electric and physical parameters of superconducting cavities. The basic unit of the test facility is high-stability retunable RF oscillator. It is designed following the scheme of the frequency phase tuning using standard equipment. The systematic error in measuring the loaded Q-value of reentrant cavities is not larger than 5%. A dedicated built-in microcomputer is used to control the measuring test facility and to make the commutations required. 2 refs.; 2 figs

Contribution to the automatic command in robotics - Application to the command by microprocessors of the articulated systems

International Nuclear Information System (INIS)

Al Mouhamed, Mayez

1982-01-01

The first part of the present paper deals with the main methods of changing the coordinates for a general articulated system. After a definition of the coordinates changing, we propose a coordination system designed for easy programming of the movements. Its characteristic is to permit the action anywhere on the manipulated object. The second part deals with the force regulation problem. For this purpose we have developed a general force sensor. The informations delivered by the sensor are used by force regulators which are intended for the automatic assembly of subsystems. In the third part the dynamic problem of the articulated systems is exposed. We present a new method which allows to determine dynamic parameters from appropriate motions of the robot. These parameters are then used to implement the dynamic control. Several applications, using the powerful microprocessor INTEL 8086 and its arithmetic coprocessor 8087, are presented, in order to demonstrate the performances gained. (author) [fr

Experience in installing a microprocessor-based protection system on a UK nuclear power plant

International Nuclear Information System (INIS)

Jones, C.D.; Smith, I.C.

1993-01-01

This paper describes a recently completed project to install a microprocessor-based reactor protection system on a twin reactor station in the United Kingdom. This represented the first application of digital technology as part of such a system in the UK. The background of the application and details of the chosen solution are provided. The experience gained during the installation, commissioning and early operation of the equipment is reviewed by the operators. Interactions between the utility and the regulatory body are outlined and the impact of the regulatory process on the utility's resources and the project timescales are discussed

The Use of a Microprocessor-Controlled, Video Output Atomic Absorption Spectrometer as an Educational Tool in a Two-Year Technical Curriculum.

Science.gov (United States)

Kerfoot, Henry B.

Based on instructional experiences at Charles County Community College, Maryland, this report examines the pedagogical advantage of teaching atomic absorption (AA) spectroscopy with an AA spectrophotometer that is equipped with a microprocessor and video output mechanism. The report first discusses the growing importance of AA spectroscopy in…

System and method for leveraging human physiological traits to control microprocessor frequency

Energy Technology Data Exchange (ETDEWEB)

Shye, Alex; Pan, Yan; Scholbrock, Benjamin; Miller, J. Scott; Memik, Gokhan; Dinda, Peter A; Dick, Robert P

2014-03-25

A system and method for leveraging physiological traits to control microprocessor frequency are disclosed. In some embodiments, the system and method may optimize, for example, a particular processor-based architecture based on, for example, end user satisfaction. In some embodiments, the system and method may determine, for example, whether their users are satisfied to provide higher efficiency, improved reliability, reduced power consumption, increased security, and a better user experience. The system and method may use, for example, biometric input devices to provide information about a user's physiological traits to a computer system. Biometric input devices may include, for example, one or more of the following: an eye tracker, a galvanic skin response sensor, and/or a force sensor.

Nuclear criticality evacuation with telemonitoring and microprocessors

International Nuclear Information System (INIS)

Fergus, R.W.; Moe, H.J. Sr.

1979-01-01

At Argonne National Laboratory, criticality alarms are required at widely separated locations to evacuate personnel in case of accident while emergency teams or maintenance personnel respond from a central location. The system functions have been divided in a similar manner. The alarm site hardware can independently detect a criticality and sound the evacuation signal while general monitoring and routine tests are handled by a communication link to a central monitoring station. The radiation detectors and evacuation sounders at each site are interconnected by a common two conductor cable in a unique telemonitoring format. This format allows both control and data information to be received or transmitted at any point on the cable which can be up to 3000 meters total length. The site microprocessor maintains a current data table, detects several faults, drives a printer, and communicates with the central telemonitoring station. The radiation detectors are made with plastic scintillators and photomultiplier tubes operated in a constant current mode with a 4 decade measurement range. The detectors also respond within microseconds to the criticality radiation burst. These characteristics can be tested with an internal light emitting diode either completely with a manual procedure or routinely with a system test initiated by the central monitoring station. Although the system was developed for a criticality alarm which requires reliable and redundant features, the basic techniques are useable for other monitoring and instrumentation applications

Multichannel analyzer with real-time correction of counting losses based on a fast 16/32 bit microprocessor

International Nuclear Information System (INIS)

Westphal, G.P.; Kasa, T.

1984-01-01

It is demonstrated that from a modern microprocessor with 32 bit architecture and from standard VLSI peripheral chips a multichannel analyzer with real-time correction of counting losses may be designed in a very flexible yet cost-effective manner. Throughput rates of 100,000 events/second are a good match even for high-rate spectroscopy systems and may be further enhanced by the use of already available CPU chips with higher clock frequency. Low power consumption and a very compact form factor make the design highly recommendable for portable applications. By means of a simple and easily reproducible rotating sample device the dynamic response of the VPG counting loss correction method have been tested and found to be more than sufficient for conceivable real-time applications. Enhanced statistical accuracy of correction factors may be traded against speed of response by the mere change of one preset value which lends itself to the simple implementation of self-adapting systems. Reliability as well as user convenience is improved by self-calibration of pulse evolution time in the VPG counting loss correction unit

Biosorption of gold from computer microprocessor leachate solutions using chitin.

Science.gov (United States)

Côrtes, Letícia N; Tanabe, Eduardo H; Bertuol, Daniel A; Dotto, Guilherme L

2015-11-01

The biosorption of gold from discarded computer microprocessor (DCM) leachate solutions was studied using chitin as a biosorbent. The DCM components were leached with thiourea solutions, and two procedures were tested for recovery of gold from the leachates: (1) biosorption and (2) precipitation followed by biosorption. For each procedure, the biosorption was evaluated considering kinetic, equilibrium, and thermodynamic aspects. The general order model was able to represent the kinetic behavior, and the equilibrium was well represented by the BET model. The maximum biosorption capacities were around 35 mg g(-1) for both procedures. The biosorption of gold on chitin was a spontaneous, favorable, and exothermic process. It was found that precipitation followed by biosorption resulted in the best gold recovery, because other species were removed from the leachate solution in the precipitation step. This method enabled about 80% of the gold to be recovered, using 20 g L(-1) of chitin at 298 K for 4 h. Copyright © 2015 Elsevier Ltd. All rights reserved.

A procedure for solving the neutron diffusion equation on a parallel micro-processor; modifications to the nodal expansion codes RECNEC and HEXNEC to implement the procedure

International Nuclear Information System (INIS)

Putney, J.M.

1983-05-01

The characteristics of a simple parallel micro-processor (PMP) are reviewed and its software requirements discussed. One of the more immediate applications is the multi-spatial simulation of a nuclear reactor station. This is of particular interest because 3D reactor simulation might then be possible as part of operating procedure for PFR and CDFR. A major part of a multi-spatial reactor simulator is the solution of the neutron diffusion equation. A procedure is described for solving the equation on a PMP, which is applied to the nodal expansion method with modifications to the nodal expansion codes RECNEC and HEXNEC. Estimations of the micro-processor requirements for the simulation of both PFR and CDFR are given. (U.K.)

A Low Cost Matching Motion Estimation Sensor Based on the NIOS II Microprocessor

Directory of Open Access Journals (Sweden)

Diego González

2012-09-01

Full Text Available This work presents the implementation of a matching-based motion estimation sensor on a Field Programmable Gate Array (FPGA and NIOS II microprocessor applying a C to Hardware (C2H acceleration paradigm. The design, which involves several matching algorithms, is mapped using Very Large Scale Integration (VLSI technology. These algorithms, as well as the hardware implementation, are presented here together with an extensive analysis of the resources needed and the throughput obtained. The developed low-cost system is practical for real-time throughput and reduced power consumption and is useful in robotic applications, such as tracking, navigation using an unmanned vehicle, or as part of a more complex system.

Use of a Microprocessor to Implement an ADCCP Protocol (Federal Std-1003) Operating in the Unbalanced Normal Mode.

Science.gov (United States)

1980-05-01

andcoptrpormigfrteublne nra ls fpoeue nacrac with Federal Standard 1003 fTelecommunications: Synchronous Bit Oriented Data Link Control Procedures...and the higher level user. The solution to the producer/consumer problem involves the use of PASS and SICHAL primitives and event variables or... semaphores . The event variables have been defined for the LS-microprocessor interface as part of I-1 the internal registers that are included in the F6856

Software support for Motorola 68000 microprocessor at CERN. CERN convention for programming the MC68000 family

International Nuclear Information System (INIS)

Cailliau, R.; Carpenter, B.

1984-01-01

The CERN convention for programming the MC68000 family of microprocessors gives a set of rules describing the layout of the memory and stack frames used by routines as they should appear before and after their calling sequences. It does not deal with the instructions used to achieve these states. The aim of the convention is to allow programming language mixing as well as debugging of programs built from units written in different languages. It is to be followed by programmers and programming-language compilers. (orig.)

Environmental dose measurement with microprocessor based portable TLD reader

International Nuclear Information System (INIS)

Deme, S.; Apathy, I.; Feher, I.

1996-01-01

Application of TL method for environmental gamma-radiation dosimetry involves uncertainty caused by the dose collected during the transport from the point of annealing to the place of exposure and back to the place of evaluation. Should an accident occur read out is delayed due to the need to transport to a laboratory equipped with a TLD reader. A portable reader capable of reading out the TL dosemeter at the place of exposure ('in situ TLD reader') eliminates the above mentioned disadvantages. We have developed a microprocessor based portable TLD reader for monitoring environmental gamma-radiation doses and for on board reading out of doses on space stations. The first version of our portable, battery operated reader (named Pille - 'butterfly') was made at the beginning of the 80s. These devices used CaSO 4 bulb dosemeters and the evaluation technique was based on analogue timing circuits and analogue to digital conversion of the photomultiplier current with a read out precision of 1 μGy and a measuring range up to 10 Gy. The measured values were displayed and manually recorded. The version with an external power supply was used for space dosimetry as an onboard TLD reader

High Performance Programming Using Explicit Shared Memory Model on Cray T3D1

Science.gov (United States)

Simon, Horst D.; Saini, Subhash; Grassi, Charles

1994-01-01

The Cray T3D system is the first-phase system in Cray Research, Inc.'s (CRI) three-phase massively parallel processing (MPP) program. This system features a heterogeneous architecture that closely couples DEC's Alpha microprocessors and CRI's parallel-vector technology, i.e., the Cray Y-MP and Cray C90. An overview of the Cray T3D hardware and available programming models is presented. Under Cray Research adaptive Fortran (CRAFT) model four programming methods (data parallel, work sharing, message-passing using PVM, and explicit shared memory model) are available to the users. However, at this time data parallel and work sharing programming models are not available to the user community. The differences between standard PVM and CRI's PVM are highlighted with performance measurements such as latencies and communication bandwidths. We have found that the performance of neither standard PVM nor CRI s PVM exploits the hardware capabilities of the T3D. The reasons for the bad performance of PVM as a native message-passing library are presented. This is illustrated by the performance of NAS Parallel Benchmarks (NPB) programmed in explicit shared memory model on Cray T3D. In general, the performance of standard PVM is about 4 to 5 times less than obtained by using explicit shared memory model. This degradation in performance is also seen on CM-5 where the performance of applications using native message-passing library CMMD on CM-5 is also about 4 to 5 times less than using data parallel methods. The issues involved (such as barriers, synchronization, invalidating data cache, aligning data cache etc.) while programming in explicit shared memory model are discussed. Comparative performance of NPB using explicit shared memory programming model on the Cray T3D and other highly parallel systems such as the TMC CM-5, Intel Paragon, Cray C90, IBM-SP1, etc. is presented.

Automated microprocessor-controlled atomic absorption analysis of natural water for arsenic and selenium

International Nuclear Information System (INIS)

Morrow, R.W.; Futrell, T.L.; Adams, T.T.

1978-08-01

An automated, dual-channel atomic absorption spectrophotometer for the simultaneous determination of arsenic and selenium in natural water is now in operation. The instrument was constructed from commercially available optical components, spectral sources, and a sample changer. Automation was achieved by using an in-house-fabricated and programmed microprocessor. The instrument will analyze samples at a rate of 37 per hour, and a quantitative determination of arsenic and selenium to 0.2 μg/l (ppB) can be achieved. Arsenic can be determined with a precision of 19% at 1 μg/l and 6% at 10 μg/l, while selenium can be determined with a precision of 17% at 1 μg/l and 4% at 10 μg/l

Different microprocessor controlled devices for ITU TRIGA Mark II reactor

International Nuclear Information System (INIS)

Can, B.; Omuz, S.; Uzun, S.; Apan, H.

1990-01-01

In this paper the design of a period meter and multichannel thermometer, which are controlled by a microprocessor, in order to be used at ITU TRIGA Mark-II Reactor is presented. The system works as a simple microcomputer, which includes a CPU, a EPROM, a RAM, a CTC, a PIO, a PIA a keyboard and displays, using the assembly language. The period meter can work either with pulse signal or with analog signal depending on demand of the user. The period is calculated by software and its range is -99,9 sec, to +2.1 sec. When the period drops +3 sec, the system gives alarm illuminating a LED. The multichannel thermometer has eight temperature channels. Temperature channels can manually or automatically be selected. The channel selection time can be adjusted. The thermometer gives alarm illuminating a LED, when the temperature rises to 600 C. Temperature data is stored in the RAM and is shown on a display. This system provides us to use four spare thermocouples in the reactor. (orig.)

Ways of Telecommunications Interaction Arrangement for Microprocessor Devices of Different Types in Composition of Multi-Motor Electric Drives

Science.gov (United States)

Shpenst, V. A.; Vasiliev, B. Y.; Kalashnikov, O. V.; Oleynikova, A. M.

2018-05-01

The article covers a consideration of various state-of-the-art industrial data transfer protocols, e.g. Modbus, Profibus, Industrial Ethernet and CAN. Their pros and cons are analyzed and conclusions made on advisability of the use of each protocol. It is shown that for the arrangement of effective telecommunication interaction of microprocessor devices of different types in the composition of multi-motor electric drives, it is advisable to use highlevel CAN-protocols, such as CANopen and DeviceNet.

User's guide for the portable microprocessor equipment: 'KfK K-edge densitometer' for quantitative determination of Th, U, Np, Pu, Am in solutions

International Nuclear Information System (INIS)

Michel-Piper, I.; Matussek, P.

1985-06-01

This report describes the hardware and software features, and the use of the microprocessor-controlled multichannel analyzer system SILENA + IRIS. The self-contained portable system, which permits independent accumulation and evaluation of spectral data from the KfK K-edge densitometer, provides one of the possible means for the authentication of resident instruments by safeguards inspectors. The 'K-Edge' program, written in PL/M language for compatibility with the system's firmware, allows fully automated assays of heavy element concentrations in solutions by means of X-ray absorption edge spectrometry. It is primarily intended for highly accurate determinations of the U and Pu content in process- and product solutions of a reprocessing plant. (orig.)

Microprocessor Card for Cuban Series polarimeters Laserpol

International Nuclear Information System (INIS)

Arista Romeu, E.; Mora Mazorra, W.

2012-01-01

We present the design consists of a card based on a micro-processor 8-bit adds new software components and their basic living, which allow to deliver new services and expand the possibilities for use in other applications of the polarimeter LASERPOL series, as the polarimetric detection. Given the limitations of the original card it was necessary to introduce a series of changes that would allow to address new user requirements, and expand the possible applications of the instruments. This was done the expansion of the capacity of the EPROM and RAM memory, the decoder circuit was implemented memory map using a programmable integrated circuit, and introduced a real time clock with nonvolatile RAM, these features are exploited to the introduction of new features such as the realization of the polarimeter calibration by the user from a sample pattern or a calibration pattern used as a reference, and the incorporation of the time and date to the reports of measurements required industry for quality control processes. Card that is achieved along with the rest of the components is compatible with polarimeters LASERPOL 101M Series, 3M and LP4, pin to pin, which facilitates their incorporation into the polarimeters in operation in the industry 'in situ' replacement cards from previous models, allowing to extend the possibilities of statistical processing, precision and accuracy of the instruments. Improved measurements in the industry, resulting in significant savings by elimination of losses in production and raw materials. The improved response speed of reading the polarimeters LASERPOL Use and polarimetric detectors. (Author)

Use of a bipolar microprocessor in a multi-window discriminator for a system studying reactor fuel pins

International Nuclear Information System (INIS)

Frueh, J.

1977-01-01

An automatic evaluation system for non-destructive reactor fuel rod analysis is described. The characteristic γ radiation of certain radioisotopes is measured, and the isotope concentration is derived from this. To determine the radioisotope concentration, a digital multi-window discriminator is installed in the system to isolate the desired γ lines from the total spectrum; in addition, background subtraction is carried out. The multi-window discriminator was constructed of bipolar bit-slice microprocessor modules. A microinstruction set of 4 basic commands was defined by which the functional sequences in the instrument were programmed. (orig.) [de

Microprocessor-based, on-line decision aid for resolving conflicting nuclear reactor instrumentation

International Nuclear Information System (INIS)

Alesso, H.P.

1981-01-01

We describe one design for a microprocessor-based, on-line decision aid for identifying and resolving false, conflicting, or misleading instrument indications resulting from certain systems interactions for a pressurized water reactor. The system processes sensor signals from groups of instruments that track together under nominal transient and certain accident conditions, and alarms when they do not track together. We examine multiple-casualty systems interaction and formulate a trial grouping of variables that track together under specified conditions. A two-of-three type redundancy check of key variables provides alarm and indication of conflicting information when one signal suddenly tracks in opposition due to multiple casualty, instrument failure, and/or locally abnormal conditions. Since a vote count of two of three variables in conflict as inconclusive evidence, the system is not designed to provide tripping or corrective action, but improves the operator/instrument interface by providing additional and partially digested information

Microprocessor based beam intensity and efficiency display system for the Fermilab accelerator

International Nuclear Information System (INIS)

Biwer, R.

1979-01-01

The Main Accelerator display system for the Fermilab accelerator gathers charge data and displays it including processed transfer efficiencies of each of the accelerators. To accomplish this, strategically located charge converters monitor the circulating internal beam of each of the Fermilab accelerators. Their outputs are processed via an asynchronously triggered, multiplexed analog-to-digital converter. The data is converted into a digital byte containing address code and data, then stores it into two 16-bit memories. One memory outputs the interleaved data as a data pulse train while the other interfaces directly to a local host computer for further analysis. The microprocessor based display unit synchronizes displayed data during normal operation as well as special storage modes. The display unit outputs data to the fron panel in the form of a numeric value and also makes digital-to-analog conversions of displayed data for external peripheral devices. 5 refs

A CAMAC-resident microprocessor used for field control of a dipole magnet

International Nuclear Information System (INIS)

Sharp, F.J.; Greiner, B.F.

1990-01-01

An inexpensive, self-contained microprocessor supporting an on-chip BASIC interpreter has been incorporated into a CAMAC auxiliary-crate controller, with an EEPROM and a terminal port. Used with an ASCII computer terminal, the intelligent auxiliary controller is a self-contained program-development system. One application for the intelligent auxiliary controller is closed-loop control of the analyzing dipoles at the negative-ion injector of the TASCC (tandem accelerator superconducting cyclotron) heavy-ion accelerators. A BASIC program stored in the EEPROM runs on power-up of the controller. The program reads control numbers from a CAMAC mailbox, converts the ASCII character string from a precision Hall-probe teslameter to a digital field reading, and writes a control number to the dipole controller. The program iterates until the dipole reaches the demand field, while updating another CAMAC mailbox with a field readback for the main control system. (orig.)

The first IA-64 microprocessor

CERN Document Server

Rusu, S

2000-01-01

The first implementation of the IA-64 architecture achieves high performance by using a highly parallel execution core, while maintaining binary compatibility with the IA-32 instruction set. Explicitly parallel instruction computing (EPIC) design maximizes performance through hardware and software synergy. The processor contains 25.4 million transistors and operates at 800 MHz. The chip is fabricated in a 0.18- mu m CMOS process with six metal layers and packaged in a 1012-pad organic land grid array using C4 (flip chip) assembly technology. A core speed back-side bus connects the processor to a 4-MB L3 cache. (6 refs).

Thermal interface pastes nanostructured for high performance

Science.gov (United States)

Lin, Chuangang

Thermal interface materials in the form of pastes are needed to improve thermal contacts, such as that between a microprocessor and a heat sink of a computer. High-performance and low-cost thermal pastes have been developed in this dissertation by using polyol esters as the vehicle and various nanoscale solid components. The proportion of a solid component needs to be optimized, as an excessive amount degrades the performance, due to the increase in the bond line thickness. The optimum solid volume fraction tends to be lower when the mating surfaces are smoother, and higher when the thermal conductivity is higher. Both a low bond line thickness and a high thermal conductivity help the performance. When the surfaces are smooth, a low bond line thickness can be even more important than a high thermal conductivity, as shown by the outstanding performance of the nanoclay paste of low thermal conductivity in the smooth case (0.009 mum), with the bond line thickness less than 1 mum, as enabled by low storage modulus G', low loss modulus G" and high tan delta. However, for rough surfaces, the thermal conductivity is important. The rheology affects the bond line thickness, but it does not correlate well with the performance. This study found that the structure of carbon black is an important parameter that governs the effectiveness of a carbon black for use in a thermal paste. By using a carbon black with a lower structure (i.e., a lower DBP value), a thermal paste that is more effective than the previously reported carbon black paste was obtained. Graphite nanoplatelet (GNP) was found to be comparable in effectiveness to carbon black (CB) pastes for rough surfaces, but it is less effective for smooth surfaces. At the same filler volume fraction, GNP gives higher thermal conductivity than carbon black paste. At the same pressure, GNP gives higher bond line thickness than CB (Tokai or Cabot). The effectiveness of GNP is limited, due to the high bond line thickness. A

The effects of environmental factors and experimental method on the results of low dose rate microprocessor irradiation tests

Energy Technology Data Exchange (ETDEWEB)

Laviron, A; Gerard, G [Commissariat a l' Energie Atomique, IPSN, Centre d' Etudes de Valduc, Is-sur-Tille (France); Gauthier, G; Henry, J Y; Le Meur, M [Commissariat a l' Energie Atomique, IPSN, Fontenay-aux-Roses (France)

1992-02-01

As part of the safety studies of nuclear facilities, a series of experiments have been in progress over a number of years to determine the principal parameters for which allowance needs to be made in the testing of microprocessors in low dose rate nuclear irradiation environments. This paper contains a brief description of the results already published, followed by a review of the latest results obtained, specifically as concerns the effects of temperature, the origin of the batch, the angle of incidence of the radiation and the test routine used. (author)

Immediate effects of a new microprocessor-controlled prosthetic knee joint: a comparative biomechanical evaluation.

Science.gov (United States)

Bellmann, Malte; Schmalz, Thomas; Ludwigs, Eva; Blumentritt, Siegmar

2012-03-01

To investigate the immediate biomechanical effects after transition to a new microprocessor-controlled prosthetic knee joint. Intervention cross-over study with repeated measures. Only prosthetic knee joints were changed. Motion analysis laboratory. Men (N=11; mean age ± SD, 36.7±10.2y; Medicare functional classification level, 3-4) with unilateral transfemoral amputation. Two microprocessor-controlled prosthetic knee joints: C-Leg and a new prosthetic knee joint, Genium. Static prosthetic alignment, time-distance parameters, kinematic and kinetic parameters, and center of pressure. After a half-day training and an additional half-day accommodation, improved biomechanical outcomes were demonstrated by the Genium: lower ground reaction forces at weight acceptance during level walking at various velocities, increased swing phase flexion angles during walking on a ramp, and level walking with small steps. Maximum knee flexion angle during swing phase at various velocities was nearly equal for Genium. Step-over-step stair ascent with the Genium knee was more physiologic as demonstrated by a more equal load distribution between the prosthetic and contralateral sides and a more natural gait pattern. When descending stairs and ramps, knee flexion moments with the Genium tended to increase. During quiet stance on a decline, subjects using Genium accepted higher loading of the prosthetic side knee joint, thus reducing same side hip joint loading as well as postural sway. In comparision to the C-Leg, the Genium demonstrated immediate biomechanical advantages during various daily ambulatory activities, which may lead to an increase in range and diversity of activity of people with above-knee amputations. Results showed that use of the Genium facilitated more natural gait biomechanics and load distribution throughout the affected and sound musculoskeletal structure. This was observed during quiet stance on a decline, walking on level ground, and walking up and down ramps and

Portable regional cerebral blood flow system based on IBM PC/AT and microprocessor electronics

International Nuclear Information System (INIS)

Mun, S.K.; Mun, I.K.; Petite, J.; Cohan, S.L.; Fahey, F.H.

1986-01-01

A portable 16-channel reginal cerebral blood flow (rCBF) measuring system has been developed using an IBM PC/AT and new microelectronics to improve processing speed and portability. The detector electronics were developed by Scan Detectronics A/S of Denmark. The counter module contains 18 16-bit counters, each programmable in four different modes. The rate meter has three independent microprocessor controllers for rate meter functions, window controller, and channel controller. The detector electronics and detection parameters can be fully controlled by the host PC/AT. The menu-driven system (Better Basic) assists the operator at each step. The collected data from 16 channels can be processed automatically or postprocessed using more flexible and sophisticated techniques within 20 minutes. The headgear holding 16 sodium iodide detectors is fabricated by modifying a motorcycle helmet

The Pajarito Monitor: a high-sensitivity monitoring system for highly enriched uranium

International Nuclear Information System (INIS)

Fehlau, P.E.; Coop, K.; Garcia, C.; Martinez, J.

1984-01-01

The Pajarito Monitor for Special Nuclear Material is a high-sensitivity gamma-ray monitoring system for detecting small quantities of highly enriched uranium transported by pedestrians or motor vehicles. The monitor consists of two components: a walk-through personnel monitor and a vehicle monitor. The personnel monitor has a plastic-scintillator detector portal, a microwave occupancy monitor, and a microprocessor control unit that measures the radiation intensity during background and monitoring periods to detect transient diversion signals. The vehicle monitor examines stationary motor vehicles while the vehicle's occupants pass through the personnel portal to exchange their badges. The vehicle monitor has four groups of large plastic scintillators that scan the vehicle from above and below. Its microprocessor control unit measures separate radiation intensities in each detector group. Vehicle occupancy is sensed by a highway traffic detection system. Each monitor's controller is responsible for detecting diversion as well as serving as a calibration and trouble-shooting aid. Diversion signals are detected by a sequential probability ratio hypothesis test that minimizes the monitoring time in the vehicle monitor and adapts itself well to variations in individual passage speed in the personnel monitor. Designed to be highly sensitive to diverted enriched uranium, the monitoring system also exhibits exceptional sensitivity for plutonium

High performance homes

DEFF Research Database (Denmark)

Beim, Anne; Vibæk, Kasper Sánchez

2014-01-01

Can prefabrication contribute to the development of high performance homes? To answer this question, this chapter defines high performance in more broadly inclusive terms, acknowledging the technical, architectural, social and economic conditions under which energy consumption and production occur....... Consideration of all these factors is a precondition for a truly integrated practice and as this chapter demonstrates, innovative project delivery methods founded on the manufacturing of prefabricated buildings contribute to the production of high performance homes that are cost effective to construct, energy...

A technique of building a value function at the stage of conceptual design of microprocessor systems

Directory of Open Access Journals (Sweden)

B. N. Chugaev

2017-01-01

Full Text Available The aim of this study is to formalize the selection of optimal technical solutions early in the design of microprocessor-based systems, which allows developers to analyze the recommended solutions, and has, in comparison with the traditional «intuitive» approach, at least two undeniable merits. First, the accepted assumptions and limitations are clearly formed. Secondly, it is defined precisely, in what sense the decision is optimal. When designing microprocessor systems (systems hereafter, several characteristics have to be taken into account at the same time. In general, when n properties are taken into account for each of the compared systems, then the solution of the task of choosing “the best” system depends on choosing a function-criterion. Such function is called a value function in the article. A simple quadratic function is suggested as the value function, it can be interpreted as the distance in Euclidean space of systems technical data. The system, which corresponds to the point nearest to the point characterizing the master system with “limiting” characteristics, is considered the best one. This function approximates the designer’s system of preferences signifi cantly better than a “classical” linear value function. In conclusion, note that the developed recommendations allow the designer of complex technical systems to analyze the proposed solutions in the early stages of design and, in case of disagreement with them, to indicate the reasons why he considers them inadequate. The designed machine optimization of technical solutions in conjunction with the traditional engineering approach should allow more reasonable choosing the structure of systems at the stage of systems conceptual design.

Experience in the installation of a microprocessor system for controlling converter units of the Vyborg substation

International Nuclear Information System (INIS)

Gusakovskii, K. B.; Zmaznov, E. Yu.; Katantsev, S. V.; Mazurenko, A. K.; Mestergazi, V. A.; Prochan, G. G.; Funtikova, S. F.

2006-01-01

The experience in the installation of modern digital systems for controlling converter units at the Vyborg converter substation on the basis of advanced microprocessor devices is considered. It is shown that debugging of a control and protection system on mathematical and physical models does not guarantee optimum control of actual converter devices. Examples of advancing the control and protection system are described, the necessity for which has become obvious in tests of actual equipment. Comparison of oscillograms of processes before optimization of the control system and after its optimization and adjustment shows that the digital control system makes it possible to improve substantially the algorithms of control and protection in the short term and without changing the hardware component

Médicarte software developed for the Quebec microprocessor health card project.

Science.gov (United States)

Lavoie, G; Tremblay, L; Durant, P; Papillon, M J; Bérubé, J; Fortin, J P

1995-01-01

The Quebec Patient Smart Card Project is a Provincial Government initiative under the responsibility of the Rgie de l'assurance-maladie du Québec (Quebec Health Insurance Board). Development, implementation, and assessment duties were assigned to a team from Université Laval, which in turn joined a group from the Direction de la santé publique du Bas-St-Laurent in Rimouski, where the experiment is taking place. The pilot project seeks to evaluate the use and acceptance of a microprocessor card as a way to improve the exchange of clinical information between card users and various health professionals. The card can be best described as a résumé containing information pertinent to an individual's health history. It is not a complete medical file; rather, it is a summary to be used as a starting point for a discussion between health professionals and patients. The target population is composed of persons 60 years and over, pregnant women, infants under 18 months, and the residents of a small town located in the target area, St-Fabien, regardless of age. The health professionals involved are general practitioners, specialists, pharmacists, nurses, and ambulance personnel. Participation in the project is on a voluntary basis. Each health care provider participating in the project has a personal identification number (PIN) and must use both an access card and a user card to access information. This prevents unauthorized access to a patient's card and allows the staff to sign and date information entered onto the patient card. To test the microprocessor card, we developed software based on a problem-oriented approach integrating diagnosis, investigations, treatments, and referrals. This software is not an expert system that constrains the clinician to a particular decisional algorithm. Instead, the software supports the physician in decision making. The software was developed with a graphical interface (Windows 3.1) to maximize its user friendliness. A version of the

Zilog UPC, a higher performance slave peripheral controller

Energy Technology Data Exchange (ETDEWEB)

Walters, S.M.

1982-01-01

The universal peripheral controllers Z8090 and Z8590 (UPC) is an intelligent peripheral controller. It may be mask-programmed to execute dedicated I/O tasks that would otherwise need to be done by the host microprocessor. The UPC is actually a single-chip microcomputer with a complete host bus interface on-chip. It offers the hardware features of a programmable parallel I/O port, a programmable counter/timer, an I/O buffer RAM, and an intelligent interrupt controller. In addition, it provides a stored program processing element that is capable of pre-processing information before it is transferred to the host. Perhaps as important as its features is the fact that when used in volume, the UPC will be comparable in cost to non-programmable LSI parallel I/O and counter/timer functions. The UPC, simply stated, offers a cost effective multi-processor approach for offloading the host microprocessor of routine peripheral control tasks in high volume applications.

Modern control technology for improved nuclear reactor performance

International Nuclear Information System (INIS)

Oakes, L.C.

1986-01-01

One of the main complaints leveled at reactor control systems by utility spokesmen is complexity. One only has to look inside a power reactor control room to appreciate this viewpoint. The high reliability and versatility of modern microprocessors makes possible distributed control systems with only performance data and abnormal conditions being relayed to the control room. In a sense, this emulates the human-body control system where routine repetitive actions are handled in an involuntary manner. The significance of expert systems to the nuclear reactor control and safety systems is their ability to capture human and other expertise and make it available, upon demand, and under almost all circumstances. Thus, human problem-solving skills acquired by the learning process over a long period of time can be captured and employed with the reliability inherent in computers. This is especially important in nuclear plants when human operators are burdened by stress and emotional factors that have a dramatic effect on performance level

Patmos: a time-predictable microprocessor

DEFF Research Database (Denmark)

Schoeberl, Martin; Puffitsch, Wolfgang; Hepp, Stefan

2018-01-01

rather than for high average-case performance. Patmos is a dual-issue, statically scheduled RISC processor. A method cache serves as the cache for the instructions and a split cache organization simplifies the WCET analysis of the data cache. To fill the dual-issue pipeline with enough useful...

In Orbit Performance of a Fully Autonomous Star Tracker

DEFF Research Database (Denmark)

Jørgensen, John Leif

1999-01-01

The Department of Automation at DTU has developed the Advanced Stellar Compass (ASC), a fully autonomous star tracker, for use as high precision attitude reference onboard spacecrafts. The ASC is composed of a CCD-based camera and a powerful microprocessor containing star catalogue, image......-analysis software and a search engine. The unit autonomously performs all tasks necessary to calculate the inertial attitude from a star image. To allow for flexible attitude manoeuvres, the ASC can, simultaneously, drive from one to four cameras, efficiently removing dropouts from, e.g., sun blinding of one camera......, it is difficult to test and verify the true robustness and accuracy of a star tracker on ground. This is caused by the fact that only real-sky tests offer high fidelity stimulation of the sensor, while the atmosphere instabilities result in a dominant noise source intrinsically limiting the achievable accuracy...

Guidelines for design and development of computer/microprocessor based systems in research and power reactors

International Nuclear Information System (INIS)

Dhodapkar, S.D.; Chandra, A.K.

1993-01-01

Computer systems are being used in Indian research reactors and nuclear power plants in the areas of data acquisition, process monitoring and control, alarm annunciation and safety. The design and evaluation of these systems requires a special approach particularly due to the unique nature of the software which is an essential constituent of these systems. It was decided to evolve guidelines for designing and review of computer/microprocessor based systems for use in nuclear power plants in India. The present document tries to address various issues and presents guidelines which are as comprehensive as possible and cover all issues relating to the design and development of computer based systems. These guidelines are expected to be useful to the specifiers, designers and reviewers of such systems. (author). 6 refs., 1 fig

Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

Directory of Open Access Journals (Sweden)

Abdul Kareem PARCHUR

2012-08-01

Full Text Available High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310. The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many key application areas in modern generation. The scaling of performance in two major series of Intel Xeon processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310 has been analyzed using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. The results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.

Thermal treatment system of hazardous residuals in three heating zones based on a microprocessor; Sistema de tratamiento termico de residuos peligrosos en tres zonas de calentamiento a base de un microcontrolador.

Energy Technology Data Exchange (ETDEWEB)

Luna H, C L

1997-12-01

Thermal treatment system consists of a high power electric oven of three heating zones where each zone works up to 1200 Centigrades; it has the capacity of rising the central zone temperature up to 1000 Centigrades in 58 minutes approximately. This configuration of three zones could be programmed to different temperatures and they will be digitally controlled by a control microprocessor, which has been controlled by its own assembler language, in function of the PID control. There are also other important controls based on this microprocessor, as a signal amplification, starting and shutdown of high power step relays, activation and deactivation of both analogic/digital and digital/analogic convertors, port activation and basic data storage of the system. Two main characteristics were looked for this oven design; the first was the possibility of controlling the three zone temperature and the second was to reduce the rising and stabilization operation time and its digitized control. The principal function of the three zone oven is to accelerate the degradation of hazardous residuals by an oxidation instead combustion, through relatively high temperatures (minimum 800 Centigrades and maximum 1200 Centigrades); this process reduces the ash and volatile particulate production. The hazardous residuals will be pumped into the degradation system and after atomized through a packaged column; this step will avoid the direct contact of the residuals with the oven cores. These features make this system as closed process, which means that the residuals can not leak to the working area, reducing the exposure risk to the personnel. This three step oven system is the first stage of the complete hazardous residuals degradation system; after this, the flow will go into a cold plasma region where the process is completed, making a closed system. (Author).

Integrating existing radiation monitors into a microprocessor-based display system

International Nuclear Information System (INIS)

Kalita, R, S.; Bartucci, C.M.; Mason, R.G.; Greaves, C.

1992-01-01

Plantwide digital radiation monitoring systems (RMSs) have been generally installed as part of the original design for newer nuclear reactors. For older plants, area and process radiation monitors were either analog or a combination of analog and digital but were not part of an integrated system design. At some plants, individual monitors have been replaced or modified, resulting in a rainbow of different monitors and vendors being represented at the plant. Usually at some point, consideration is given to replacing these monitors with a state-of-the-art RMS to improve overall reliability and achieve the benefits of sound human factors engineering. This can be a very costly project in terms of expenditures for engineering, equipment, construction, startup, and time. When human engineering deficiencies (HEDs) became an issue at Zion station, Commonwealth Edison elected to install a computer-based radiation monitoring display system (RMDS) that would interface existing raidation monitors. After reviewing the existing as-built RMS configuration and internal circuits of the various monitors, it was concluded that a microprocessor-based RMDS could be successfully designed and installed that would solve the HEDs and would tie the older analog channels into a system configuration. Although in many cases, internal modifications were made to existing RMS monitors, the RMDS upgrade allowed the existing RMS monitors to retain their original functionality and location

High Performance Marine Vessels

CERN Document Server

Yun, Liang

2012-01-01

High Performance Marine Vessels (HPMVs) range from the Fast Ferries to the latest high speed Navy Craft, including competition power boats and hydroplanes, hydrofoils, hovercraft, catamarans and other multi-hull craft. High Performance Marine Vessels covers the main concepts of HPMVs and discusses historical background, design features, services that have been successful and not so successful, and some sample data of the range of HPMVs to date. Included is a comparison of all HPMVs craft and the differences between them and descriptions of performance (hydrodynamics and aerodynamics). Readers will find a comprehensive overview of the design, development and building of HPMVs. In summary, this book: Focuses on technology at the aero-marine interface Covers the full range of high performance marine vessel concepts Explains the historical development of various HPMVs Discusses ferries, racing and pleasure craft, as well as utility and military missions High Performance Marine Vessels is an ideal book for student...

Microprocessor-based integration of microfluidic control for the implementation of automated sensor monitoring and multithreaded optimization algorithms.

Science.gov (United States)

Ezra, Elishai; Maor, Idan; Bavli, Danny; Shalom, Itai; Levy, Gahl; Prill, Sebastian; Jaeger, Magnus S; Nahmias, Yaakov

2015-08-01

Microfluidic applications range from combinatorial synthesis to high throughput screening, with platforms integrating analog perfusion components, digitally controlled micro-valves and a range of sensors that demand a variety of communication protocols. Currently, discrete control units are used to regulate and monitor each component, resulting in scattered control interfaces that limit data integration and synchronization. Here, we present a microprocessor-based control unit, utilizing the MS Gadgeteer open framework that integrates all aspects of microfluidics through a high-current electronic circuit that supports and synchronizes digital and analog signals for perfusion components, pressure elements, and arbitrary sensor communication protocols using a plug-and-play interface. The control unit supports an integrated touch screen and TCP/IP interface that provides local and remote control of flow and data acquisition. To establish the ability of our control unit to integrate and synchronize complex microfluidic circuits we developed an equi-pressure combinatorial mixer. We demonstrate the generation of complex perfusion sequences, allowing the automated sampling, washing, and calibrating of an electrochemical lactate sensor continuously monitoring hepatocyte viability following exposure to the pesticide rotenone. Importantly, integration of an optical sensor allowed us to implement automated optimization protocols that require different computational challenges including: prioritized data structures in a genetic algorithm, distributed computational efforts in multiple-hill climbing searches and real-time realization of probabilistic models in simulated annealing. Our system offers a comprehensive solution for establishing optimization protocols and perfusion sequences in complex microfluidic circuits.

Microprocessor control and data acquisition at the LLNL 100-MeV accelerator

International Nuclear Information System (INIS)

Mendonca, M.L.

1981-01-01

A distributed microprocessor control and data acquisition network has been designed for implementation on the Lawrence Livermore National Laboratory 100 MeV electron/positron accelerator (LINAC). The system has been designed to be as transparent to the user as possible by stressing responsiveness, reliability, and relevance of data presented to the user. Implementation of the network will take place in modular fashion in three stages, so as to minimize disruption of normal operations. The first elements to be installed will be the beam transport system controls, beam set-up time. Beam diagnostic equipment is now being position monitors, and accelerator operating status monitors. These units will reduce beam set-up time. Beam diagnostic equipment is now being designed that will be used in a second stage implementation. This stage will concentrate on determining beam parameters and allowing the user to optimize the beam for a given parameter. The final stage will be to install experimenter data acquisition equipment. The equipment will augment the presently existing data acquisition system. The completed network will allow a more efficient operation of the LINAC, resulting in reduced experiment costs, and more controllable beam parameters, both of which are major concerns of experimenters

High speed imaging system for nuclear diagnostics

International Nuclear Information System (INIS)

Eyer, H.H.

1976-01-01

A high speed imaging system based on state-of-the-art photosensor arrays has been designed for use in nuclear diagnostics. The system is comprised of a front-end rapid-scan solid-state camera, a high speed digitizer, and a PCM line driver in a downhole package and a memory buffer system in a uphole trailer. The downhole camera takes a ''snapshot'' of a nuclear device created flux stream, digitizes the image and transmits it to the uphole memory system before being destroyed. The memory system performs two functions: it retains the data for local display and processing by a microprocessor, and it buffers the data for retransmission at slower rates to the LLL computational facility (NADS). The impetus for such a system as well as its operation are discussed. Also discussed are new systems under development which incorporate higher data rates and more resolution

High speed imaging system for nuclear diagnostics

International Nuclear Information System (INIS)

Eyer, H.H.

1976-01-01

A high speed imaging system based on state-of-the-art photosensor arrays has been designed for use in nuclear diagnostics. The system is comprised of a front-end rapid-scan solid-state camera, a high speed digitizer, and a PCM line driver in a downhole package and a memory buffer system in an uphole trailer. The downhole camera takes a ''snapshot'' of a nuclear device created flux stream, digitizes the image and transmits it to the uphole memory system before being destroyed. The memory system performs two functions: it retains the data for local display and processing by a microprocessor, and it buffers the data for retransmission at slower rates to the LLL computational facility (NADS). The impetus for such a system as well as its operation is discussed. Also discussed are new systems under development which incorporate higher data rates and more resolution

High performance systems

Energy Technology Data Exchange (ETDEWEB)

Vigil, M.B. [comp.

1995-03-01

This document provides a written compilation of the presentations and viewgraphs from the 1994 Conference on High Speed Computing given at the High Speed Computing Conference, {open_quotes}High Performance Systems,{close_quotes} held at Gleneden Beach, Oregon, on April 18 through 21, 1994.

Model based design introduction: modeling game controllers to microprocessor architectures

Science.gov (United States)

Jungwirth, Patrick; Badawy, Abdel-Hameed

2017-04-01

We present an introduction to model based design. Model based design is a visual representation, generally a block diagram, to model and incrementally develop a complex system. Model based design is a commonly used design methodology for digital signal processing, control systems, and embedded systems. Model based design's philosophy is: to solve a problem - a step at a time. The approach can be compared to a series of steps to converge to a solution. A block diagram simulation tool allows a design to be simulated with real world measurement data. For example, if an analog control system is being upgraded to a digital control system, the analog sensor input signals can be recorded. The digital control algorithm can be simulated with the real world sensor data. The output from the simulated digital control system can then be compared to the old analog based control system. Model based design can compared to Agile software develop. The Agile software development goal is to develop working software in incremental steps. Progress is measured in completed and tested code units. Progress is measured in model based design by completed and tested blocks. We present a concept for a video game controller and then use model based design to iterate the design towards a working system. We will also describe a model based design effort to develop an OS Friendly Microprocessor Architecture based on the RISC-V.

A supercomputer for parallel data analysis

International Nuclear Information System (INIS)

Kolpakov, I.F.; Senner, A.E.; Smirnov, V.A.

1987-01-01

The project of a powerful multiprocessor system is proposed. The main purpose of the project is to develop a low cost computer system with a processing rate of a few tens of millions of operations per second. The system solves many problems of data analysis from high-energy physics spectrometers. It includes about 70 MOTOROLA-68020 based powerful slave microprocessor boards liaisoned through the VME crates to a host VAX micro computer. Each single microprocessor board performs the same algorithm requiring large computing time. The host computer distributes data over the microprocessor board, collects and combines obtained results. The architecture of the system easily allows one to use it in the real time mode

Event parallelism: Distributed memory parallel computing for high energy physics experiments

International Nuclear Information System (INIS)

Nash, T.

1989-05-01

This paper describes the present and expected future development of distributed memory parallel computers for high energy physics experiments. It covers the use of event parallel microprocessor farms, particularly at Fermilab, including both ACP multiprocessors and farms of MicroVAXES. These systems have proven very cost effective in the past. A case is made for moving to the more open environment of UNIX and RISC processors. The 2nd Generation ACP Multiprocessor System, which is based on powerful RISC systems, is described. Given the promise of still more extraordinary increases in processor performance, a new emphasis on point to point, rather than bussed, communication will be required. Developments in this direction are described. 6 figs

Event parallelism: Distributed memory parallel computing for high energy physics experiments

International Nuclear Information System (INIS)

Nash, T.

1989-01-01

This paper describes the present and expected future development of distributed memory parallel computers for high energy physics experiments. It covers the use of event parallel microprocessor farms, particularly at Fermilab, including both ACP multiprocessors and farms of MicroVAXES. These systems have proven very cost effective in the past. A case is made for moving to the more open environment of UNIX and RISC processors. The 2nd Generation ACP Multiprocessor System, which is based on powerful RISC systems, is described. Given the promise of still more extraordinary increases in processor performance, a new emphasis on point to point, rather than bussed, communication will be required. Developments in this direction are described. (orig.)

Event parallelism: Distributed memory parallel computing for high energy physics experiments

Science.gov (United States)

Nash, Thomas

1989-12-01

This paper describes the present and expected future development of distributed memory parallel computers for high energy physics experiments. It covers the use of event parallel microprocessor farms, particularly at Fermilab, including both ACP multiprocessors and farms of MicroVAXES. These systems have proven very cost effective in the past. A case is made for moving to the more open environment of UNIX and RISC processors. The 2nd Generation ACP Multiprocessor System, which is based on powerful RISC system, is described. Given the promise of still more extraordinary increases in processor performance, a new emphasis on point to point, rather than bussed, communication will be required. Developments in this direction are described.

Technical basis for environmental qualification of microprocessor-based safety-related equipment in nuclear power plants

International Nuclear Information System (INIS)

Korsah, K.; Wood, R.T.; Hassan, M.; Tanaka, T.J.

1998-01-01

This document presents the results of studies sponsored by the Nuclear Regulatory Commission (NRC) to provide the technical basis for environmental qualification of computer-based safety equipment in nuclear power plants. The studies were conducted by Oak Ridge National Laboratory (ORNL), Sandia National Laboratories (SNL), and Brookhaven National Laboratory (BNL). The studies address the following: (1) adequacy of the present test methods for qualification of digital I and C systems; (2) preferred (i.e., Regulatory Guide-endorsed) standards; (3) recommended stressors to be included in the qualification process during type testing; (4) resolution of need for accelerated aging for equipment to be located in a benign environment; and (5) determination of an appropriate approach for addressing the impact of smoke in digital equipment qualification programs. Significant findings from the studies form the technical basis for a recommended approach to the environmental qualification of microprocessor-based safety-related equipment in nuclear power plants

Technical basis for environmental qualification of microprocessor-based safety-related equipment in nuclear power plants

Energy Technology Data Exchange (ETDEWEB)

Korsah, K.; Wood, R.T. [Oak Ridge National Lab., TN (United States); Hassan, M. [Brookhaven National Lab., Upton, NY (United States); Tanaka, T.J. [Sandia National Labs., Albuquerque, NM (United States)

1998-01-01

This document presents the results of studies sponsored by the Nuclear Regulatory Commission (NRC) to provide the technical basis for environmental qualification of computer-based safety equipment in nuclear power plants. The studies were conducted by Oak Ridge National Laboratory (ORNL), Sandia National Laboratories (SNL), and Brookhaven National Laboratory (BNL). The studies address the following: (1) adequacy of the present test methods for qualification of digital I and C systems; (2) preferred (i.e., Regulatory Guide-endorsed) standards; (3) recommended stressors to be included in the qualification process during type testing; (4) resolution of need for accelerated aging for equipment to be located in a benign environment; and (5) determination of an appropriate approach for addressing the impact of smoke in digital equipment qualification programs. Significant findings from the studies form the technical basis for a recommended approach to the environmental qualification of microprocessor-based safety-related equipment in nuclear power plants.

High performance work practices, innovation and performance

DEFF Research Database (Denmark)

Jørgensen, Frances; Newton, Cameron; Johnston, Kim

2013-01-01

Research spanning nearly 20 years has provided considerable empirical evidence for relationships between High Performance Work Practices (HPWPs) and various measures of performance including increased productivity, improved customer service, and reduced turnover. What stands out from......, and Africa to examine these various questions relating to the HPWP-innovation-performance relationship. Each paper discusses a practice that has been identified in HPWP literature and potential variables that can facilitate or hinder the effects of these practices of innovation- and performance...

Expression levels of the microRNA maturing microprocessor complex component DGCR8 and the RNA-induced silencing complex (RISC) components argonaute-1, argonaute-2, PACT, TARBP1, and TARBP2 in epithelial skin cancer.

Science.gov (United States)

Sand, Michael; Skrygan, Marina; Georgas, Dimitrios; Arenz, Christoph; Gambichler, Thilo; Sand, Daniel; Altmeyer, Peter; Bechara, Falk G

2012-11-01

The microprocessor complex mediates intranuclear biogenesis of precursor microRNAs from the primary microRNA transcript. Extranuclear, mature microRNAs are incorporated into the RNA-induced silencing complex (RISC) before interaction with complementary target mRNA leads to transcriptional repression or cleavage. In this study, we investigated the expression profiles of the microprocessor complex subunit DiGeorge syndrome critical region gene 8 (DGCR8) and the RISC components argonaute-1 (AGO1), argonaute-2 (AGO2), as well as double-stranded RNA-binding proteins PACT, TARBP1, and TARBP2 in epithelial skin cancer and its premalignant stage. Patients with premalignant actinic keratoses (AK, n = 6), basal cell carcinomas (BCC, n = 15), and squamous cell carcinomas (SCC, n = 7) were included in the study. Punch biopsies were harvested from the center of the tumors (lesional), from healthy skin sites (intraindividual controls), and from healthy skin sites in a healthy control group (n = 16; interindividual control). The DGCR8, AGO1, AGO2, PACT, TARBP1, and TARBP2 mRNA expression levels were detected by quantitative real-time reverse transcriptase polymerase chain reaction. The DGCR8, AGO1, AGO2, PACT, and TARBP1 expression levels were significantly higher in the AK, BCC, and SCC groups than the healthy controls (P  0.05). This study indicates that major components of the miRNA pathway, such as the microprocessor complex and RISC, are dysregulated in epithelial skin cancer. Copyright © 2011 Wiley Periodicals, Inc.

Computer applications: Automatic control system for high-voltage accelerator

International Nuclear Information System (INIS)

Bryukhanov, A.N.; Komissarov, P.Yu.; Lapin, V.V.; Latushkin, S.T.. Fomenko, D.E.; Yudin, L.I.

1992-01-01

An automatic control system for a high-voltage electrostatic accelerator with an accelerating potential of up to 500 kV is described. The electronic apparatus on the high-voltage platform is controlled and monitored by means of a fiber-optic data-exchange system. The system is based on CAMAC modules that are controlled by a microprocessor crate controller. Data on accelerator operation are represented and control instructions are issued by means of an alphanumeric terminal. 8 refs., 6 figs

RavenDB high performance

CERN Document Server

Ritchie, Brian

2013-01-01

RavenDB High Performance is comprehensive yet concise tutorial that developers can use to.This book is for developers & software architects who are designing systems in order to achieve high performance right from the start. A basic understanding of RavenDB is recommended, but not required. While the book focuses on advanced topics, it does not assume that the reader has a great deal of prior knowledge of working with RavenDB.

Development of microprocessor based ionization gauge controller for variable energy cyclotron project [Paper No.:P5

International Nuclear Information System (INIS)

Srilakshmi, B.R.; Rao, M.K.V.

1993-01-01

The ion gauge uses energetic electrons to ionize gas molecules, the magnitude of ion current thus produced is a measure of the molecular density or the pressure which is the most commonly measured parameter in vacuum technology. The relationship between ion current (I p ) and pressure (P) is given by the equation P=I p /(I E .S.G) where S = sensitivity of a particular gauge head, G = gas constant depending on the nature of the gas appearing in the system. I E = emission current. Hence P becomes directly proportional to I p if I E is maintained constant. The present scheme incorporates a microprocessor based circuit for automatic display of pressure in the mantissa and exponent form. While the exponent is displayed through a look up table stored in the EPROM, the mantissa is computed by the processor after multiple sampling, conversion through ADC and averaging technique. (author). 2 refs., 1 fig

Development of a Wiimote-based Gesture Recognizer in a Microprocessor Laboratory Course

Directory of Open Access Journals (Sweden)

Alberto Lorente Leal

2011-03-01

Full Text Available This gesture recognizer, developed by students in a third-year microprocessor-based laboratory course, takes Wii remote (Wiimote as an input device to estimate the movements of the user and to compare the detected trajectory with the previously learnt movements, in order to carry out the associated actions. Such a cheap state-of-the-art wireless user interface is very attractive for the students and can be used in many interactive applications, from robotics to virtual reality and multimedia presentations. By combining commercially-available hardware, pattern-matching techniques and programming skills, we are able to foster students' interest on developing innovative potentially-marketable systems. This freeware project, implemented as a configurable publicly-available library, can be adapted to the needs of any course or student. In our laboratory this open-source DLL is used for remotely controlling a robot (based on an open-hardware Arduino platform, using a PC and the Wiimote, although the DLL can be integrated in any C, C++, Java or C# project. A GUI application (based on a Model-View-Presenter paradigm is also provided and can be used as a template for new applications or just for debugging purposes. Although the developed application only uses data from the accelerometers, data from the infrared camera and buttons of the Wiimote is also available.

High-performance computing using FPGAs

CERN Document Server

Benkrid, Khaled

2013-01-01

This book is concerned with the emerging field of High Performance Reconfigurable Computing (HPRC), which aims to harness the high performance and relative low power of reconfigurable hardware–in the form Field Programmable Gate Arrays (FPGAs)–in High Performance Computing (HPC) applications. It presents the latest developments in this field from applications, architecture, and tools and methodologies points of view. We hope that this work will form a reference for existing researchers in the field, and entice new researchers and developers to join the HPRC community.  The book includes:  Thirteen application chapters which present the most important application areas tackled by high performance reconfigurable computers, namely: financial computing, bioinformatics and computational biology, data search and processing, stencil computation e.g. computational fluid dynamics and seismic modeling, cryptanalysis, astronomical N-body simulation, and circuit simulation.     Seven architecture chapters which...

High-Performance Networking

CERN Multimedia

CERN. Geneva

2003-01-01

The series will start with an historical introduction about what people saw as high performance message communication in their time and how that developed to the now to day known "standard computer network communication". It will be followed by a far more technical part that uses the High Performance Computer Network standards of the 90's, with 1 Gbit/sec systems as introduction for an in depth explanation of the three new 10 Gbit/s network and interconnect technology standards that exist already or emerge. If necessary for a good understanding some sidesteps will be included to explain important protocols as well as some necessary details of concerned Wide Area Network (WAN) standards details including some basics of wavelength multiplexing (DWDM). Some remarks will be made concerning the rapid expanding applications of networked storage.

Transient Performance Improvement Circuit (TPIC)s for DC-DC converter applications

Science.gov (United States)

Lim, Sungkeun

Gordon Moore famously predicted the exponential increase in transistor integration and computing power that has been witnessed in recent decades [1]. In the near future, it is expected that more than one billion transistors will be integrated per chip, and advanced microprocessors will require clock speeds in excess of several GHz. The increasing number of transistors and high clock speeds will necessitate the consumption of more power. By 2014, it is expected that the maximum power consumption of the microprocessor will reach approximately 150W, and the maximum load current will be around 150A. Today's trend in power and thermal management is to reduce supply voltage as low as possible to reduce delivered power. It is anticipated that the Intel cores will operate on 0.8V of supply voltage by 2014 [2]. A significant challenge in Voltage Regulator Module (VRM) development for next generation microprocessors is to regulate the supply voltage within a certain tolerance band during high slew rate load transitions, since the required supply voltage tolerance band will be much narrower than the current requirement. If VR output impedance is maintained at a constant value from DC to high frequency, large output voltage spikes can be avoided during load cur- rent transients. Based on this, the Adaptive Voltage Position (AVP) concept was developed to achieve constant VR output impedance to improve transient response performance [3]. However, the VR output impedance can not be made constant over the entire frequency range with AVP design, because the AVP design makes the VR output impedance constant only at low frequencies. To make the output impedance constant at high frequencies, many bulk capacitors and ceramic capacitors are required. The tight supply voltage tolerance for the next generation of microprocessors during high slew rate load transitions requires fast transient response power supplies. A VRM can not follow the high slew rate load current transients, because

High Performance Concrete

Directory of Open Access Journals (Sweden)

Traian Oneţ

2009-01-01

Full Text Available The paper presents the last studies and researches accomplished in Cluj-Napoca related to high performance concrete, high strength concrete and self compacting concrete. The purpose of this paper is to raid upon the advantages and inconveniences when a particular concrete type is used. Two concrete recipes are presented, namely for the concrete used in rigid pavement for roads and another one for self-compacting concrete.

HPTA: High-Performance Text Analytics

OpenAIRE

Vandierendonck, Hans; Murphy, Karen; Arif, Mahwish; Nikolopoulos, Dimitrios S.

2017-01-01

One of the main targets of data analytics is unstructured data, which primarily involves textual data. High-performance processing of textual data is non-trivial. We present the HPTA library for high-performance text analytics. The library helps programmers to map textual data to a dense numeric representation, which can be handled more efficiently. HPTA encapsulates three performance optimizations: (i) efficient memory management for textual data, (ii) parallel computation on associative dat...

Pressurized planar electrochromatography, high-performance thin-layer chromatography and high-performance liquid chromatography--comparison of performance.

Science.gov (United States)

Płocharz, Paweł; Klimek-Turek, Anna; Dzido, Tadeusz H

2010-07-16

Kinetic performance, measured by plate height, of High-Performance Thin-Layer Chromatography (HPTLC), High-Performance Liquid Chromatography (HPLC) and Pressurized Planar Electrochromatography (PPEC) was compared for the systems with adsorbent of the HPTLC RP18W plate from Merck as the stationary phase and the mobile phase composed of acetonitrile and buffer solution. The HPLC column was packed with the adsorbent, which was scrapped from the chromatographic plate mentioned. An additional HPLC column was also packed with adsorbent of 5 microm particle diameter, C18 type silica based (LiChrosorb RP-18 from Merck). The dependence of plate height of both HPLC and PPEC separating systems on flow velocity of the mobile phase and on migration distance of the mobile phase in TLC system was presented applying test solute (prednisolone succinate). The highest performance, amongst systems investigated, was obtained for the PPEC system. The separation efficiency of the systems investigated in the paper was additionally confirmed by the separation of test component mixture composed of six hormones. 2010 Elsevier B.V. All rights reserved.

Analysis of performance improvements for host and GPU interface of the APENet+ 3D Torus network

International Nuclear Information System (INIS)

Ammendola A, R; Biagioni, A; Frezza, O; Lo Cicero, F; Lonardo, A; Paolucci, P S; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P

2014-01-01

APEnet+ is an INFN (Italian Institute for Nuclear Physics) project aiming to develop a custom 3-Dimensional torus interconnect network optimized for hybrid clusters CPU-GPU dedicated to High Performance scientific Computing. The APEnet+ interconnect fabric is built on a FPGA-based PCI-express board with 6 bi-directional off-board links showing 34 Gbps of raw bandwidth per direction, and leverages upon peer-to-peer capabilities of Fermi and Kepler-class NVIDIA GPUs to obtain real zero-copy, GPU-to-GPU low latency transfers. The minimization of APEnet+ transfer latency is achieved through the adoption of RDMA protocol implemented in FPGA with specialized hardware blocks tightly coupled with embedded microprocessor. This architecture provides a high performance low latency offload engine for both trasmit and receive side of data transactions: preliminary results are encouraging, showing 50% of bandwidth increase for large packet size transfers. In this paper we describe the APEnet+ architecture, detailing the hardware implementation and discuss the impact of such RDMA specialized hardware on host interface latency and bandwidth

Analysis of performance improvements for host and GPU interface of the APENet+ 3D Torus network

Science.gov (United States)

Ammendola A, R.; Biagioni, A.; Frezza, O.; Lo Cicero, F.; Lonardo, A.; Paolucci, P. S.; Rossetti, D.; Simula, F.; Tosoratto, L.; Vicini, P.

2014-06-01

APEnet+ is an INFN (Italian Institute for Nuclear Physics) project aiming to develop a custom 3-Dimensional torus interconnect network optimized for hybrid clusters CPU-GPU dedicated to High Performance scientific Computing. The APEnet+ interconnect fabric is built on a FPGA-based PCI-express board with 6 bi-directional off-board links showing 34 Gbps of raw bandwidth per direction, and leverages upon peer-to-peer capabilities of Fermi and Kepler-class NVIDIA GPUs to obtain real zero-copy, GPU-to-GPU low latency transfers. The minimization of APEnet+ transfer latency is achieved through the adoption of RDMA protocol implemented in FPGA with specialized hardware blocks tightly coupled with embedded microprocessor. This architecture provides a high performance low latency offload engine for both trasmit and receive side of data transactions: preliminary results are encouraging, showing 50% of bandwidth increase for large packet size transfers. In this paper we describe the APEnet+ architecture, detailing the hardware implementation and discuss the impact of such RDMA specialized hardware on host interface latency and bandwidth.

Analysis of performance improvements for host and GPU interface of the APENet+ 3D Torus network

Energy Technology Data Exchange (ETDEWEB)

Ammendola A, R [INFN Roma II, Via della Ricerca Scientifica 1 – 00133 Roma (Italy); Biagioni, A; Frezza, O; Lo Cicero, F; Lonardo, A; Paolucci, P S; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P [INFN Roma I, P.le Aldo Moro 2 – 00185 Roma (Italy)

2014-06-06

APEnet+ is an INFN (Italian Institute for Nuclear Physics) project aiming to develop a custom 3-Dimensional torus interconnect network optimized for hybrid clusters CPU-GPU dedicated to High Performance scientific Computing. The APEnet+ interconnect fabric is built on a FPGA-based PCI-express board with 6 bi-directional off-board links showing 34 Gbps of raw bandwidth per direction, and leverages upon peer-to-peer capabilities of Fermi and Kepler-class NVIDIA GPUs to obtain real zero-copy, GPU-to-GPU low latency transfers. The minimization of APEnet+ transfer latency is achieved through the adoption of RDMA protocol implemented in FPGA with specialized hardware blocks tightly coupled with embedded microprocessor. This architecture provides a high performance low latency offload engine for both trasmit and receive side of data transactions: preliminary results are encouraging, showing 50% of bandwidth increase for large packet size transfers. In this paper we describe the APEnet+ architecture, detailing the hardware implementation and discuss the impact of such RDMA specialized hardware on host interface latency and bandwidth.

High Performance Computing in Science and Engineering '15 : Transactions of the High Performance Computing Center

CERN Document Server

Kröner, Dietmar; Resch, Michael

2016-01-01

This book presents the state-of-the-art in supercomputer simulation. It includes the latest findings from leading researchers using systems from the High Performance Computing Center Stuttgart (HLRS) in 2015. The reports cover all fields of computational science and engineering ranging from CFD to computational physics and from chemistry to computer science with a special emphasis on industrially relevant applications. Presenting findings of one of Europe’s leading systems, this volume covers a wide variety of applications that deliver a high level of sustained performance. The book covers the main methods in high-performance computing. Its outstanding results in achieving the best performance for production codes are of particular interest for both scientists and engineers. The book comes with a wealth of color illustrations and tables of results.

High Performance Computing in Science and Engineering '17 : Transactions of the High Performance Computing Center

CERN Document Server

Kröner, Dietmar; Resch, Michael; HLRS 2017

2018-01-01

This book presents the state-of-the-art in supercomputer simulation. It includes the latest findings from leading researchers using systems from the High Performance Computing Center Stuttgart (HLRS) in 2017. The reports cover all fields of computational science and engineering ranging from CFD to computational physics and from chemistry to computer science with a special emphasis on industrially relevant applications. Presenting findings of one of Europe’s leading systems, this volume covers a wide variety of applications that deliver a high level of sustained performance.The book covers the main methods in high-performance computing. Its outstanding results in achieving the best performance for production codes are of particular interest for both scientists and engineers. The book comes with a wealth of color illustrations and tables of results.

High-Performance Operating Systems

DEFF Research Database (Denmark)

Sharp, Robin

1999-01-01

Notes prepared for the DTU course 49421 "High Performance Operating Systems". The notes deal with quantitative and qualitative techniques for use in the design and evaluation of operating systems in computer systems for which performance is an important parameter, such as real-time applications......, communication systems and multimedia systems....

Multi-processor developments in the United States for future high energy physics experiments and accelerators

International Nuclear Information System (INIS)

Gaines, I.

1988-03-01

The use of multi-processors for analysis and high-level triggering in High Energy Physics experiments, pioneered by the early emulator systems, has reached maturity, in particular with the multiple microprocessor systems in use at Fermilab. It is widely acknowledged that such systems will fulfill the major portion of the computing needs of future large experiments. Recent developments at Fermilab's Advanced Computer Program will make such systems even more powerful, cost-effective, and easier to use than they are at present. The next generation of microprocessors, already available, will provide CPU power of about one VAX 780 equivalent/$300, while supporting most VMS FORTRAN extensions and large (>8MB) amounts of memory. Low cost high density mass storage devices (based on video tape cartridge technology) will allow parallel I/O to remove potential I/O bottlenecks in systems of over 1000 VAX equipment processors. New interconnection schemes and system software will allow more flexible topologies and extremely high data bandwidth, especially for on-line systems. This talk will summarize the work at the Advanced Computer Program and the rest of the US in this field. 3 refs., 4 figs

Sliding Mode Pulsed Averaging IC Drivers for High Brightness Light Emitting Diodes

Energy Technology Data Exchange (ETDEWEB)

Dr. Anatoly Shteynberg, PhD

2006-08-17

This project developed new Light Emitting Diode (LED) driver ICs associated with specific (uniquely operated) switching power supplies that optimize performance for High Brightness LEDs (HB-LEDs). The drivers utilize a digital control core with a newly developed nonlinear, hysteretic/sliding mode controller with mixed-signal processing. The drivers are flexible enough to allow both traditional microprocessor interface as well as other options such as “on the fly” adjustment of color and brightness. Some other unique features of the newly developed drivers include • AC Power Factor Correction; • High power efficiency; • Substantially fewer external components should be required, leading to substantial reduction of Bill of Materials (BOM). Thus, the LED drivers developed in this research : optimize LED performance by increasing power efficiency and power factor. Perhaps more remarkably, the LED drivers provide this improved performance at substantially reduced costs compared to the present LED power electronic driver circuits. Since one of the barriers to market penetration for HB-LEDs (in particular “white” light LEDs) is cost/lumen, this research makes important contributions in helping the advancement of SSL consumer acceptance and usage.

The FORCE: A highly portable parallel programming language

Science.gov (United States)

Jordan, Harry F.; Benten, Muhammad S.; Alaghband, Gita; Jakob, Ruediger

1989-01-01

Here, it is explained why the FORCE parallel programming language is easily portable among six different shared-memory microprocessors, and how a two-level macro preprocessor makes it possible to hide low level machine dependencies and to build machine-independent high level constructs on top of them. These FORCE constructs make it possible to write portable parallel programs largely independent of the number of processes and the specific shared memory multiprocessor executing them.

High performance fuel technology development

Energy Technology Data Exchange (ETDEWEB)

Koon, Yang Hyun; Kim, Keon Sik; Park, Jeong Yong; Yang, Yong Sik; In, Wang Kee; Kim, Hyung Kyu [KAERI, Daejeon (Korea, Republic of)

2012-01-15

{omicron} Development of High Plasticity and Annular Pellet - Development of strong candidates of ultra high burn-up fuel pellets for a PCI remedy - Development of fabrication technology of annular fuel pellet {omicron} Development of High Performance Cladding Materials - Irradiation test of HANA claddings in Halden research reactor and the evaluation of the in-pile performance - Development of the final candidates for the next generation cladding materials. - Development of the manufacturing technology for the dual-cooled fuel cladding tubes. {omicron} Irradiated Fuel Performance Evaluation Technology Development - Development of performance analysis code system for the dual-cooled fuel - Development of fuel performance-proving technology {omicron} Feasibility Studies on Dual-Cooled Annular Fuel Core - Analysis on the property of a reactor core with dual-cooled fuel - Feasibility evaluation on the dual-cooled fuel core {omicron} Development of Design Technology for Dual-Cooled Fuel Structure - Definition of technical issues and invention of concept for dual-cooled fuel structure - Basic design and development of main structure components for dual- cooled fuel - Basic design of a dual-cooled fuel rod.

Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

Science.gov (United States)

Popović, Miloš A.; Wade, Mark T.; Orcutt, Jason S.; Shainline, Jeffrey M.; Sun, Chen; Georgas, Michael; Moss, Benjamin; Kumar, Rajesh; Alloatti, Luca; Pavanello, Fabio; Chen, Yu-Hsin; Nammari, Kareem; Notaros, Jelena; Atabaki, Amir; Leu, Jonathan; Stojanović, Vladimir; Ram, Rajeev J.

2015-02-01

We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a "More-than- Moore" technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.

Development of a highly selective muon trigger exploiting the high spatial resolution of monitored drift-tube chambers for the ATLAS experiment at the HL-LHC

CERN Document Server

Kortner, Oliver; The ATLAS collaboration

2018-01-01

The High-Luminosity LHC will provide the unique opportunity to explore the nature of physics beyond the Standard Model. Highly selective first level triggers are essential for the physics programme of the ATLAS experiment at the HL-LHC, where the instantaneous luminosity will exceed the LHC design instantaneous luminosity by almost an order of magnitude. The ATLAS first level muon trigger rate is dominated by low momentum muons, selected due to the moderate momentum resolution of the current system. This first level trigger limitation can be overcome by including data from the precision muon drift tube (MDT) chambers. This requires the fast continuous transfer of the MDT hits to the off-detector trigger logic and a fast track reconstruction algorithm performed in the trigger logic. The feasibility of this approach was studied with LHC collision data and simulated data. Two main options for the hardware implementation will be studied with demonstrators: an FPGA based option with an embedded ARM microprocessor ...

High performance homes

DEFF Research Database (Denmark)

Beim, Anne; Vibæk, Kasper Sánchez

2014-01-01

. Consideration of all these factors is a precondition for a truly integrated practice and as this chapter demonstrates, innovative project delivery methods founded on the manufacturing of prefabricated buildings contribute to the production of high performance homes that are cost effective to construct, energy...

A peek into the world of chip design

CERN Document Server

CERN. Geneva; Marquina, Miguel Angel

2005-01-01

This lecture will give some insight into how the Microprocessor Design Group approaches the daunting task of the design of a lead microprocessor as complex as the Pentium IV while under very specific schedule constraints. For a historical perspective, we will start with a quick comparison of the complexity/performance of the Willamette and Prescott (Pentium IV) class of microprocessor with the generations before the Pentium IV (Bob was a member of the design teams for a number of lead microprocessor projects including the 486DX2, Pentium Pr

Strategy Guideline: High Performance Residential Lighting

Energy Technology Data Exchange (ETDEWEB)

Holton, J.

2012-02-01

The Strategy Guideline: High Performance Residential Lighting has been developed to provide a tool for the understanding and application of high performance lighting in the home. The high performance lighting strategies featured in this guide are drawn from recent advances in commercial lighting for application to typical spaces found in residential buildings. This guide offers strategies to greatly reduce lighting energy use through the application of high quality fluorescent and light emitting diode (LED) technologies. It is important to note that these strategies not only save energy in the home but also serve to satisfy the homeowner's expectations for high quality lighting.

High performance conductometry

International Nuclear Information System (INIS)

Saha, B.

2000-01-01

Inexpensive but high performance systems have emerged progressively for basic and applied measurements in physical and analytical chemistry on one hand, and for on-line monitoring and leak detection in plants and facilities on the other. Salient features of the developments will be presented with specific examples

Modernization of the Control Systems of High-Frequency, Brush-Free, and Collector Exciters of Turbogenerators

Energy Technology Data Exchange (ETDEWEB)

Popov, E. N., E-mail: enpo@ruselmash.ru; Komkov, A. L.; Ivanov, S. L.; Timoshchenko, K. P. [JSC “Scientific and Industrial Enterprise “Rusélprom-Élektromash” (Russian Federation)

2016-11-15

Methods of modernizing the regulation systems of electric machinery exciters with high-frequency, brush-free, and collector exciters by means of microprocessor technology are examined. The main problems of modernization are to increase the response speed of a system and to use a system stabilizer to increase the stability of the power system.

Increased control and data acquisition capabilities via microprocessor-based timed reading and time plot CAMAC modules

International Nuclear Information System (INIS)

Barsotti, E.J.; Purvis, D.M.; Loveless, R.L.; Hance, R.D.

1977-01-01

By implementing a microprocessor-based CAMAC module capable of being programmed to function as a time plot or a timed reading controller, the capabilities of the experimental area serial CAMAC control and data acquisition system at Fermilab have been extensively increased. These modules provide real-time data gathering and pre-processing functions synchronized to the main accelerator cycle clock while adding only a minimal amount to the host computer's CPU time and memory requirements. Critical data requiring a fast system response can be read by the host computer immediately following the request for this data. The vast majority of data, being non-critical, can be read via a block transfer during a non-busy time in the main accelerator cycle. Each of Fermilab's experimental areas, Meson, Neutrino and Proton, are controlled primarily by a Lockheed MAC-16 computer. Each of these three minicomputers is linked to a larger Digital Equipment Corporation PDP-11/50 computer. The PDP-11 computers are used primarily for data analysis and reduction. Presently two PDP-11's are linked to the three MAC-16 computers

INL High Performance Building Strategy

Energy Technology Data Exchange (ETDEWEB)

Jennifer D. Morton

2010-02-01

High performance buildings, also known as sustainable buildings and green buildings, are resource efficient structures that minimize the impact on the environment by using less energy and water, reduce solid waste and pollutants, and limit the depletion of natural resources while also providing a thermally and visually comfortable working environment that increases productivity for building occupants. As Idaho National Laboratory (INL) becomes the nation’s premier nuclear energy research laboratory, the physical infrastructure will be established to help accomplish this mission. This infrastructure, particularly the buildings, should incorporate high performance sustainable design features in order to be environmentally responsible and reflect an image of progressiveness and innovation to the public and prospective employees. Additionally, INL is a large consumer of energy that contributes to both carbon emissions and resource inefficiency. In the current climate of rising energy prices and political pressure for carbon reduction, this guide will help new construction project teams to design facilities that are sustainable and reduce energy costs, thereby reducing carbon emissions. With these concerns in mind, the recommendations described in the INL High Performance Building Strategy (previously called the INL Green Building Strategy) are intended to form the INL foundation for high performance building standards. This revised strategy incorporates the latest federal and DOE orders (Executive Order [EO] 13514, “Federal Leadership in Environmental, Energy, and Economic Performance” [2009], EO 13423, “Strengthening Federal Environmental, Energy, and Transportation Management” [2007], and DOE Order 430.2B, “Departmental Energy, Renewable Energy, and Transportation Management” [2008]), the latest guidelines, trends, and observations in high performance building construction, and the latest changes to the Leadership in Energy and Environmental Design

High Performance Networks for High Impact Science

Energy Technology Data Exchange (ETDEWEB)

Scott, Mary A.; Bair, Raymond A.

2003-02-13

This workshop was the first major activity in developing a strategic plan for high-performance networking in the Office of Science. Held August 13 through 15, 2002, it brought together a selection of end users, especially representing the emerging, high-visibility initiatives, and network visionaries to identify opportunities and begin defining the path forward.

High performance fuel technology development : Development of high performance cladding materials

International Nuclear Information System (INIS)

Park, Jeongyong; Jeong, Y. H.; Park, S. Y.

2012-04-01

The superior in-pile performance of the HANA claddings have been verified by the successful irradiation test and in the Halden research reactor up to the high burn-up of 67GWD/MTU. The in-pile corrosion and creep resistances of HANA claddings were improved by 40% and 50%, respectively, over Zircaloy-4. HANA claddings have been also irradiated in the commercial reactor up to 2 reactor cycles, showing the corrosion resistance 40% better than that of ZIRLO in the same fuel assembly. Long-term out-of-pile performance tests for the candidates of the next generation cladding materials have produced the highly reliable test results. The final candidate alloys were selected and they showed the corrosion resistance 50% better than the foreign advanced claddings, which is beyond the original target. The LOCA-related properties were also improved by 20% over the foreign advanced claddings. In order to establish the optimal manufacturing process for the inner and outer claddings of the dual-cooled fuel, 18 different kinds of specimens were fabricated with various cold working and annealing conditions. Based on the performance tests and various out-of-pile test results obtained from the specimens, the optimal manufacturing process was established for the inner and outer cladding tubes of the dual-cooled fuel

Carbon nanomaterials for high-performance supercapacitors

OpenAIRE

Tao Chen; Liming Dai

2013-01-01

Owing to their high energy density and power density, supercapacitors exhibit great potential as high-performance energy sources for advanced technologies. Recently, carbon nanomaterials (especially, carbon nanotubes and graphene) have been widely investigated as effective electrodes in supercapacitors due to their high specific surface area, excellent electrical and mechanical properties. This article summarizes the recent progresses on the development of high-performance supercapacitors bas...

Clojure high performance programming

CERN Document Server

Kumar, Shantanu

2013-01-01

This is a short, practical guide that will teach you everything you need to know to start writing high performance Clojure code.This book is ideal for intermediate Clojure developers who are looking to get a good grip on how to achieve optimum performance. You should already have some experience with Clojure and it would help if you already know a little bit of Java. Knowledge of performance analysis and engineering is not required. For hands-on practice, you should have access to Clojure REPL with Leiningen.

Surface-restrained growth of vertically aligned carbon nanotube arrays with excellent thermal transport performance.

Science.gov (United States)

Ping, Linquan; Hou, Peng-Xiang; Liu, Chang; Li, Jincheng; Zhao, Yang; Zhang, Feng; Ma, Chaoqun; Tai, Kaiping; Cong, Hongtao; Cheng, Hui-Ming

2017-06-22

A vertically aligned carbon nanotube (VACNT) array is a promising candidate for a high-performance thermal interface material in high-power microprocessors due to its excellent thermal transport property. However, its rough and entangled free tips always cause poor interfacial contact, which results in serious contact resistance dominating the total thermal resistance. Here, we employed a thin carbon cover to restrain the disorderly growth of the free tips of a VACNT array. As a result, all the free tips are seamlessly connected by this thin carbon cover and the top surface of the array is smoothed. This unique structure guarantees the participation of all the carbon nanotubes in the array in the heat transport. Consequently the VACNT array grown on a Cu substrate shows a record low thermal resistance of 0.8 mm 2 K W -1 including the two-sided contact resistances, which is 4 times lower than the best result previously reported. Remarkably, the VACNT array can be easily peeled away from the Cu substrate and act as a thermal pad with excellent flexibility, adhesive ability and heat transport capability. As a result the CNT array with a thin carbon cover shows great potential for use as a high-performance flexible thermal interface material.

Delivering high performance BWR fuel reliably

International Nuclear Information System (INIS)

Schardt, J.F.

1998-01-01

Utilities are under intense pressure to reduce their production costs in order to compete in the increasingly deregulated marketplace. They need fuel, which can deliver high performance to meet demanding operating strategies. GE's latest BWR fuel design, GE14, provides that high performance capability. GE's product introduction process assures that this performance will be delivered reliably, with little risk to the utility. (author)

High performance bio-integrated devices

Science.gov (United States)

Kim, Dae-Hyeong; Lee, Jongha; Park, Minjoon

2014-06-01

In recent years, personalized electronics for medical applications, particularly, have attracted much attention with the rise of smartphones because the coupling of such devices and smartphones enables the continuous health-monitoring in patients' daily life. Especially, it is expected that the high performance biomedical electronics integrated with the human body can open new opportunities in the ubiquitous healthcare. However, the mechanical and geometrical constraints inherent in all standard forms of high performance rigid wafer-based electronics raise unique integration challenges with biotic entities. Here, we describe materials and design constructs for high performance skin-mountable bio-integrated electronic devices, which incorporate arrays of single crystalline inorganic nanomembranes. The resulting electronic devices include flexible and stretchable electrophysiology electrodes and sensors coupled with active electronic components. These advances in bio-integrated systems create new directions in the personalized health monitoring and/or human-machine interfaces.

High Performance Macromolecular Material

National Research Council Canada - National Science Library

Forest, M

2002-01-01

.... In essence, most commercial high-performance polymers are processed through fiber spinning, following Nature and spider silk, which is still pound-for-pound the toughest liquid crystalline polymer...

Delivering high performance BWR fuel reliably

Energy Technology Data Exchange (ETDEWEB)

Schardt, J.F. [GE Nuclear Energy, Wilmington, NC (United States)

1998-07-01

Utilities are under intense pressure to reduce their production costs in order to compete in the increasingly deregulated marketplace. They need fuel, which can deliver high performance to meet demanding operating strategies. GE's latest BWR fuel design, GE14, provides that high performance capability. GE's product introduction process assures that this performance will be delivered reliably, with little risk to the utility. (author)

Carpet Aids Learning in High Performance Schools

Science.gov (United States)

Hurd, Frank

2009-01-01

The Healthy and High Performance Schools Act of 2002 has set specific federal guidelines for school design, and developed a federal/state partnership program to assist local districts in their school planning. According to the Collaborative for High Performance Schools (CHPS), high-performance schools are, among other things, healthy, comfortable,…

High-performance-vehicle technology. [fighter aircraft propulsion

Science.gov (United States)

Povinelli, L. A.

1979-01-01

Propulsion needs of high performance military aircraft are discussed. Inlet performance, nozzle performance and cooling, and afterburner performance are covered. It is concluded that nonaxisymmetric nozzles provide cleaner external lines and enhanced maneuverability, but the internal flows are more complex. Swirl afterburners show promise for enhanced performance in the high altitude, low Mach number region.

Academic performance in high school as factor associated to academic performance in college

Directory of Open Access Journals (Sweden)

Mileidy Salcedo Barragán

2008-12-01

Full Text Available This study intends to find the relationship between academic performance in High School and College, focusing on Natural Sciences and Mathematics. It is a descriptive correlational study, and the variables were academic performance in High School, performance indicators and educational history. The correlations between variables were established with Spearman’s correlation coefficient. Results suggest that there is a positive relationship between academic performance in High School and Educational History, and a very weak relationship between performance in Science and Mathematics in High School and performance in College.

High Performance Grinding and Advanced Cutting Tools

CERN Document Server

Jackson, Mark J

2013-01-01

High Performance Grinding and Advanced Cutting Tools discusses the fundamentals and advances in high performance grinding processes, and provides a complete overview of newly-developing areas in the field. Topics covered are grinding tool formulation and structure, grinding wheel design and conditioning and applications using high performance grinding wheels. Also included are heat treatment strategies for grinding tools, using grinding tools for high speed applications, laser-based and diamond dressing techniques, high-efficiency deep grinding, VIPER grinding, and new grinding wheels.

'Intelligent' approach to radioimmunoassay sample counting employing a microprocessor controlled sample counter

International Nuclear Information System (INIS)

Ekins, R.P.; Sufi, S.; Malan, P.G.

1977-01-01

The enormous impact on medical science in the last two decades of microanalytical techniques employing radioisotopic labels has, in turn, generated a large demand for automatic radioisotopic sample counters. Such instruments frequently comprise the most important item of capital equipment required in the use of radioimmunoassay and related techniques and often form a principle bottleneck in the flow of samples through a busy laboratory. It is therefore particularly imperitive that such instruments should be used 'intelligently' and in an optimal fashion to avoid both the very large capital expenditure involved in the unnecessary proliferation of instruments and the time delays arising from their sub-optimal use. The majority of the current generation of radioactive sample counters nevertheless rely on primitive control mechanisms based on a simplistic statistical theory of radioactive sample counting which preclude their efficient and rational use. The fundamental principle upon which this approach is based is that it is useless to continue counting a radioactive sample for a time longer than that required to yield a significant increase in precision of the measurement. Thus, since substantial experimental errors occur during sample preparation, these errors should be assessed and must be releted to the counting errors for that sample. It is the objective of this presentation to demonstrate that the combination of a realistic statistical assessment of radioactive sample measurement, together with the more sophisticated control mechanisms that modern microprocessor technology make possible, may often enable savings in counter usage of the order of 5-10 fold to be made. (orig.) [de

Highlighting High Performance: Whitman Hanson Regional High School; Whitman, Massachusetts

Energy Technology Data Exchange (ETDEWEB)

2006-06-01

This brochure describes the key high-performance building features of the Whitman-Hanson Regional High School. The brochure was paid for by the Massachusetts Technology Collaborative as part of their Green Schools Initiative. High-performance features described are daylighting and energy-efficient lighting, indoor air quality, solar and wind energy, building envelope, heating and cooling systems, water conservation, and acoustics. Energy cost savings are also discussed.

Online high sensitivity measurement system for transuranic aerosols

International Nuclear Information System (INIS)

Kordas, J.F.; Phelps, P.L.

1976-01-01

A measurement system for transuranic aerosols has been designed that will be able to withstand the corrosive nature of stack effluents and yet have extremely high sensitivity. It will be capable of measuring 1 maximum permissible concentration (MPC) of plutonium or americium in 30 minutes with a fractional standard deviation of less than 0.33. Background resulting from 218 Po is eliminated by alpha energy discrimination and a decay scheme analysis. A microprocessor controls all data acquisition, data reduction, and instrument calibration

High performance polymeric foams

International Nuclear Information System (INIS)

Gargiulo, M.; Sorrentino, L.; Iannace, S.

2008-01-01

The aim of this work was to investigate the foamability of high-performance polymers (polyethersulfone, polyphenylsulfone, polyetherimide and polyethylenenaphtalate). Two different methods have been used to prepare the foam samples: high temperature expansion and two-stage batch process. The effects of processing parameters (saturation time and pressure, foaming temperature) on the densities and microcellular structures of these foams were analyzed by using scanning electron microscopy

Responsive design high performance

CERN Document Server

Els, Dewald

2015-01-01

This book is ideal for developers who have experience in developing websites or possess minor knowledge of how responsive websites work. No experience of high-level website development or performance tweaking is required.

The performance analysis of linux networking - packet receiving

Energy Technology Data Exchange (ETDEWEB)

Wu, Wenji; Crawford, Matt; Bowden, Mark; /Fermilab

2006-11-01

The computing models for High-Energy Physics experiments are becoming ever more globally distributed and grid-based, both for technical reasons (e.g., to place computational and data resources near each other and the demand) and for strategic reasons (e.g., to leverage equipment investments). To support such computing models, the network and end systems, computing and storage, face unprecedented challenges. One of the biggest challenges is to transfer scientific data sets--now in the multi-petabyte (10{sup 15} bytes) range and expected to grow to exabytes within a decade--reliably and efficiently among facilities and computation centers scattered around the world. Both the network and end systems should be able to provide the capabilities to support high bandwidth, sustained, end-to-end data transmission. Recent trends in technology are showing that although the raw transmission speeds used in networks are increasing rapidly, the rate of advancement of microprocessor technology has slowed down. Therefore, network protocol-processing overheads have risen sharply in comparison with the time spent in packet transmission, resulting in degraded throughput for networked applications. More and more, it is the network end system, instead of the network, that is responsible for degraded performance of network applications. In this paper, the Linux system's packet receive process is studied from NIC to application. We develop a mathematical model to characterize the Linux packet receiving process. Key factors that affect Linux systems network performance are analyzed.

Performance of Сellular Automata-based Stream Ciphers in GPU Implementation

Directory of Open Access Journals (Sweden)

P. G. Klyucharev

2016-01-01

Full Text Available Earlier the author had developed methods to build high-performance generalized cellular automata-based symmetric ciphers, which allow obtaining the encryption algorithms that show extremely high performance in hardware implementation. However, their implementation based on the conventional microprocessors lacks high performance. The mere fact is quite common - it shows a scope of applications for these ciphers. Nevertheless, the use of graphic processors enables achieving an appropriate performance for a software implementation.The article is extension of a series of the articles, which study various aspects to construct and implement cryptographic algorithms based on the generalized cellular automata. The article is aimed at studying the capabilities to implement the GPU-based cryptographic algorithms under consideration.Representing a key generator, the implemented encryption algorithm comprises 2k generalized cellular automata. The cellular automata graphs are Ramanujan’s ones. The cells of produced k gamma streams alternate, thereby allowing the GPU capabilities to be better used.To implement was used OpenCL, as the most universal and platform-independent API. The software written in C ++ was designed so that the user could set various parameters, including the encryption key, the graph structure, the local communication function, various constants, etc. To test were used a variety of graphics processors (NVIDIA GTX 650; NVIDIA GTX 770; AMD R9 280X.Depending on operating conditions, and GPU used, a performance range is from 0.47 to 6.61 Gb / s, which is comparable to the performance of the countertypes.Thus, the article has demonstrated that using the GPU makes it is possible to provide efficient software implementation of stream ciphers based on the generalized cellular automata.This work was supported by the RFBR, the project №16-07-00542.

Striving for Excellence Sometimes Hinders High Achievers: Performance-Approach Goals Deplete Arithmetical Performance in Students with High Working Memory Capacity

Science.gov (United States)

Crouzevialle, Marie; Smeding, Annique; Butera, Fabrizio

2015-01-01

We tested whether the goal to attain normative superiority over other students, referred to as performance-approach goals, is particularly distractive for high-Working Memory Capacity (WMC) students—that is, those who are used to being high achievers. Indeed, WMC is positively related to high-order cognitive performance and academic success, a record of success that confers benefits on high-WMC as compared to low-WMC students. We tested whether such benefits may turn out to be a burden under performance-approach goal pursuit. Indeed, for high achievers, aiming to rise above others may represent an opportunity to reaffirm their positive status—a stake susceptible to trigger disruptive outcome concerns that interfere with task processing. Results revealed that with performance-approach goals—as compared to goals with no emphasis on social comparison—the higher the students’ WMC, the lower their performance at a complex arithmetic task (Experiment 1). Crucially, this pattern appeared to be driven by uncertainty regarding the chances to outclass others (Experiment 2). Moreover, an accessibility measure suggested the mediational role played by status-related concerns in the observed disruption of performance. We discuss why high-stake situations can paradoxically lead high-achievers to sub-optimally perform when high-order cognitive performance is at play. PMID:26407097

High-performance ceramics. Fabrication, structure, properties

International Nuclear Information System (INIS)

Petzow, G.; Tobolski, J.; Telle, R.

1996-01-01

The program ''Ceramic High-performance Materials'' pursued the objective to understand the chaining of cause and effect in the development of high-performance ceramics. This chain of problems begins with the chemical reactions for the production of powders, comprises the characterization, processing, shaping and compacting of powders, structural optimization, heat treatment, production and finishing, and leads to issues of materials testing and of a design appropriate to the material. The program ''Ceramic High-performance Materials'' has resulted in contributions to the understanding of fundamental interrelationships in terms of materials science, which are summarized in the present volume - broken down into eight special aspects. (orig./RHM)

Microprocessor-controlled Nd:YAG laser for hyperthermia induction in the RIF-1 tumor.

Science.gov (United States)

Waldow, S M; Russell, G E; Wallner, P E

1992-01-01

Near-infrared radiation from a Nd:YAG laser at 1,064 nm was used interstitially or superficially to induce hyperthermia in RIF-1 tumors in C3H male mice. A single 600-microns quartz fiber with a 0.5-cm cylindrical diffusor or a weakly diverging microlens at its distal end was used to deliver laser energy to tumors in the hind leg (mean volume = 100 mm3). Two thermocouples were inserted into each tumor. One thermocouple controlled a microprocessor-driven hyperthermia program (maximum output of 3.5 Watts) to maintain the desired temperature. Tumors were exposed to various temperature-time combinations (42-45 degrees C/30 min). Our initial results indicated that excellent temperature control to within 0.2 degrees C of the desired temperature at the feedback thermocouple was achievable during both superficial and interstitial heat treatments. Temperatures at the second thermocouple, however, were found to be lower by as much as 2.3 degrees C (using the cylindrical diffusor) or higher by up to 4.6 degrees C (using the microlens) when compared to the feedback thermocouple temperature. Several correlations were seen between total dose, tumor growth delay, percent skin necrosis, and temperature at the second thermocouple after several superficial and interstitial treatments. Statistically significant improvements in tumor growth delay (at 42 and 45 degrees C) and increased percent skin necrosis at all temperatures were observed after superficial versus interstitial treatment.

Testing and interfacing intelligent power supplies for the Los Alamos National Laboratory Accelerator Complex

International Nuclear Information System (INIS)

Sturrock, J.C.; Cohen, S.; Weintraub, B.L.; Hayden, D.J.; Archuleta, S.F.

1992-01-01

New high-current, high-precision microprocessor-controlled power supplies, built by Alpha Scientific Electronics of Hayward, CA, have been installed at the Los Alamos National Laboratory Accelerator Complex. Each unit has sophisticated microprocessor control on-board and communicates via RS-422 (serial communications). The units use a high level ASCII-based control protocol. Performance tests were conducted to verify adherence to specification and to ascertain ultimate long-term stability. The ''front-end'' software used by the accelerator control system has been written to accommodate these new devices. The supplies are interfaced to the control system through a terminal server port connected to the site-wide ediernet backbone. Test design and results as well as details of the software implementation for the analog and digital control of the supplies through the accelerator control system are presented

High performance data transfer

Science.gov (United States)

Cottrell, R.; Fang, C.; Hanushevsky, A.; Kreuger, W.; Yang, W.

2017-10-01

The exponentially increasing need for high speed data transfer is driven by big data, and cloud computing together with the needs of data intensive science, High Performance Computing (HPC), defense, the oil and gas industry etc. We report on the Zettar ZX software. This has been developed since 2013 to meet these growing needs by providing high performance data transfer and encryption in a scalable, balanced, easy to deploy and use way while minimizing power and space utilization. In collaboration with several commercial vendors, Proofs of Concept (PoC) consisting of clusters have been put together using off-the- shelf components to test the ZX scalability and ability to balance services using multiple cores, and links. The PoCs are based on SSD flash storage that is managed by a parallel file system. Each cluster occupies 4 rack units. Using the PoCs, between clusters we have achieved almost 200Gbps memory to memory over two 100Gbps links, and 70Gbps parallel file to parallel file with encryption over a 5000 mile 100Gbps link.

Strategy Guideline. Partnering for High Performance Homes

Energy Technology Data Exchange (ETDEWEB)

Prahl, Duncan [IBACOS, Inc., Pittsburgh, PA (United States)

2013-01-01

High performance houses require a high degree of coordination and have significant interdependencies between various systems in order to perform properly, meet customer expectations, and minimize risks for the builder. Responsibility for the key performance attributes is shared across the project team and can be well coordinated through advanced partnering strategies. For high performance homes, traditional partnerships need to be matured to the next level and be expanded to all members of the project team including trades, suppliers, manufacturers, HERS raters, designers, architects, and building officials as appropriate. This guide is intended for use by all parties associated in the design and construction of high performance homes. It serves as a starting point and features initial tools and resources for teams to collaborate to continually improve the energy efficiency and durability of new houses.

High performance parallel I/O

CERN Document Server

Prabhat

2014-01-01

Gain Critical Insight into the Parallel I/O EcosystemParallel I/O is an integral component of modern high performance computing (HPC), especially in storing and processing very large datasets to facilitate scientific discovery. Revealing the state of the art in this field, High Performance Parallel I/O draws on insights from leading practitioners, researchers, software architects, developers, and scientists who shed light on the parallel I/O ecosystem.The first part of the book explains how large-scale HPC facilities scope, configure, and operate systems, with an emphasis on choices of I/O har

ADVANCED HIGH PERFORMANCE SOLID WALL BLANKET CONCEPTS

International Nuclear Information System (INIS)

WONG, CPC; MALANG, S; NISHIO, S; RAFFRAY, R; SAGARA, S

2002-01-01

OAK A271 ADVANCED HIGH PERFORMANCE SOLID WALL BLANKET CONCEPTS. First wall and blanket (FW/blanket) design is a crucial element in the performance and acceptance of a fusion power plant. High temperature structural and breeding materials are needed for high thermal performance. A suitable combination of structural design with the selected materials is necessary for D-T fuel sufficiency. Whenever possible, low afterheat, low chemical reactivity and low activation materials are desired to achieve passive safety and minimize the amount of high-level waste. Of course the selected fusion FW/blanket design will have to match the operational scenarios of high performance plasma. The key characteristics of eight advanced high performance FW/blanket concepts are presented in this paper. Design configurations, performance characteristics, unique advantages and issues are summarized. All reviewed designs can satisfy most of the necessary design goals. For further development, in concert with the advancement in plasma control and scrape off layer physics, additional emphasis will be needed in the areas of first wall coating material selection, design of plasma stabilization coils, consideration of reactor startup and transient events. To validate the projected performance of the advanced FW/blanket concepts the critical element is the need for 14 MeV neutron irradiation facilities for the generation of necessary engineering design data and the prediction of FW/blanket components lifetime and availability

Upset due to a single particle caused propagated transients in a bulk CMOS microprocessor

International Nuclear Information System (INIS)

Leavy, J.F.; Hoffmann, L.F.; Shoran, R.W.; Johnson, M.T.

1991-01-01

This paper reports on data pattern advances observed in preset, single event upset (SEU) hardened clocked flip-flops, during static Cf-252 exposures on a bulk CMOS microprocessor, that were attributable to particle caused anomalous clock signals, or propagated transients. SPICE simulations established that particle strikes in the output nodes of a clock control logic flip-flop could produce transients of sufficient amplitude and duration to be accepted as legitimate pulses by clock buffers fed by the flip-flop's output nodes. The buffers would then output false clock pulses, thereby advancing the state of the present flip-flops. Masking the clock logic on one of the test chips made the flip-flop data advance cease, confirming the clock logic as the source of the SEU. By introducing N 2 gas, at reduced pressures, into the SEU test chamber to attenuate Cf-252 particle LET's, a 24-26 MeV-cm 2 /mg LET threshold was deduced. Subsequent tests, at the 88-inch cyclotron at Berkeley, established an LET threshold of 30 MeV-cm 2 /mg (283 MeV Cu at 0 degrees) for the generation of false clocks. Cyclotron SEU tests are considered definitive, while Cf-252 data usually is not. However, in this instance Cf-252 tests proved analytically useful, providing SEU characterization data that was both timely and inexpensive

DOE research in utilization of high-performance computers

International Nuclear Information System (INIS)

Buzbee, B.L.; Worlton, W.J.; Michael, G.; Rodrigue, G.

1980-12-01

Department of Energy (DOE) and other Government research laboratories depend on high-performance computer systems to accomplish their programatic goals. As the most powerful computer systems become available, they are acquired by these laboratories so that advances can be made in their disciplines. These advances are often the result of added sophistication to numerical models whose execution is made possible by high-performance computer systems. However, high-performance computer systems have become increasingly complex; consequently, it has become increasingly difficult to realize their potential performance. The result is a need for research on issues related to the utilization of these systems. This report gives a brief description of high-performance computers, and then addresses the use of and future needs for high-performance computers within DOE, the growing complexity of applications within DOE, and areas of high-performance computer systems warranting research. 1 figure

High-performance mass storage system for workstations

Science.gov (United States)

Chiang, T.; Tang, Y.; Gupta, L.; Cooperman, S.

1993-01-01

Reduced Instruction Set Computer (RISC) workstations and Personnel Computers (PC) are very popular tools for office automation, command and control, scientific analysis, database management, and many other applications. However, when using Input/Output (I/O) intensive applications, the RISC workstations and PC's are often overburdened with the tasks of collecting, staging, storing, and distributing data. Also, by using standard high-performance peripherals and storage devices, the I/O function can still be a common bottleneck process. Therefore, the high-performance mass storage system, developed by Loral AeroSys' Independent Research and Development (IR&D) engineers, can offload a RISC workstation of I/O related functions and provide high-performance I/O functions and external interfaces. The high-performance mass storage system has the capabilities to ingest high-speed real-time data, perform signal or image processing, and stage, archive, and distribute the data. This mass storage system uses a hierarchical storage structure, thus reducing the total data storage cost, while maintaining high-I/O performance. The high-performance mass storage system is a network of low-cost parallel processors and storage devices. The nodes in the network have special I/O functions such as: SCSI controller, Ethernet controller, gateway controller, RS232 controller, IEEE488 controller, and digital/analog converter. The nodes are interconnected through high-speed direct memory access links to form a network. The topology of the network is easily reconfigurable to maximize system throughput for various applications. This high-performance mass storage system takes advantage of a 'busless' architecture for maximum expandability. The mass storage system consists of magnetic disks, a WORM optical disk jukebox, and an 8mm helical scan tape to form a hierarchical storage structure. Commonly used files are kept in the magnetic disk for fast retrieval. The optical disks are used as archive

Ground Glass Pozzolan in Conventional, High, and Ultra-High Performance Concrete

OpenAIRE

Tagnit-Hamou Arezki; Zidol Ablam; Soliman Nancy; Deschamps Joris; Omran Ahmed

2018-01-01

Ground-glass pozzolan (G) obtained by grinding the mixed-waste glass to same fineness of cement can act as a supplementary-cementitious material (SCM), given that it is an amorphous and a pozzolanic material. The G showed promising performances in different concrete types such as conventional concrete (CC), high-performance concrete (HPC), and ultra-high performance concrete (UHPC). The current paper reports on the characteristics and performance of G in these concrete types. The use of G pro...

Design of a family of integrated parallel co-processors for images processing

International Nuclear Information System (INIS)

Court, Thierry

1991-01-01

The design of parallel image processing Systems joining in a same architecture, sophisticated microprocessors and specialised operators is a difficult task, because of the various problems to be taken into account. The current study identifies a certain way of realizing and interfacing such dedicated operators to a central unit with microprocessor type. The two guide lines of this work are the search for polyvalent specialized and re-configurated operators as well as their connections to a System bus, and not to specialized video buses. This research work proposes a certain architecture of circuits dedicated to image processing and two realization proposals of them. One of them was be realized in this study by using silicon compiler tools. This work belongs to a more important project, whose aim is the development of an industrial image processing System, high performing, modular, based on the parallelization, in MIMD structures, of an elementary, autonomous image processing unit integrating a microprocessor equipped with a parallel coprocessor suited to image processing. (author) [fr

Indoor Air Quality in High Performance Schools

Science.gov (United States)

High performance schools are facilities that improve the learning environment while saving energy, resources, and money. The key is understanding the lifetime value of high performance schools and effectively managing priorities, time, and budget.

Advanced high performance solid wall blanket concepts

International Nuclear Information System (INIS)

Wong, C.P.C.; Malang, S.; Nishio, S.; Raffray, R.; Sagara, A.

2002-01-01

First wall and blanket (FW/blanket) design is a crucial element in the performance and acceptance of a fusion power plant. High temperature structural and breeding materials are needed for high thermal performance. A suitable combination of structural design with the selected materials is necessary for D-T fuel sufficiency. Whenever possible, low afterheat, low chemical reactivity and low activation materials are desired to achieve passive safety and minimize the amount of high-level waste. Of course the selected fusion FW/blanket design will have to match the operational scenarios of high performance plasma. The key characteristics of eight advanced high performance FW/blanket concepts are presented in this paper. Design configurations, performance characteristics, unique advantages and issues are summarized. All reviewed designs can satisfy most of the necessary design goals. For further development, in concert with the advancement in plasma control and scrape off layer physics, additional emphasis will be needed in the areas of first wall coating material selection, design of plasma stabilization coils, consideration of reactor startup and transient events. To validate the projected performance of the advanced FW/blanket concepts the critical element is the need for 14 MeV neutron irradiation facilities for the generation of necessary engineering design data and the prediction of FW/blanket components lifetime and availability

High-performance OPCPA laser system

International Nuclear Information System (INIS)

Zuegel, J.D.; Bagnoud, V.; Bromage, J.; Begishev, I.A.; Puth, J.

2006-01-01

Optical parametric chirped-pulse amplification (OPCPA) is ideally suited for amplifying ultra-fast laser pulses since it provides broadband gain across a wide range of wavelengths without many of the disadvantages of regenerative amplification. A high-performance OPCPA system has been demonstrated as a prototype for the front end of the OMEGA Extended Performance (EP) Laser System. (authors)

High-performance OPCPA laser system

Energy Technology Data Exchange (ETDEWEB)

Zuegel, J.D.; Bagnoud, V.; Bromage, J.; Begishev, I.A.; Puth, J. [Rochester Univ., Lab. for Laser Energetics, NY (United States)

2006-06-15

Optical parametric chirped-pulse amplification (OPCPA) is ideally suited for amplifying ultra-fast laser pulses since it provides broadband gain across a wide range of wavelengths without many of the disadvantages of regenerative amplification. A high-performance OPCPA system has been demonstrated as a prototype for the front end of the OMEGA Extended Performance (EP) Laser System. (authors)

High-Resolution Gas Metering and Nonintrusive Appliance Load Monitoring System

Science.gov (United States)

Tewolde, Mahder

This thesis deals with design and implementation of a high-resolution metering system for residential natural gas meters. Detailed experimental measurements are performed on the meter to characterize and understand its measurement properties. Results from these experiments are used to develop a simple, fast and accurate technique to non-intrusively monitor the gas consumption of individual appliances in homes by resolving small amounts of gas usage. The technique is applied on an existing meter retrofitted with a module that includes a high-resolution encoder to collect gas flow data and a microprocessor to analyze and identify appliance load profiles. This approach provides a number of appealing features including low cost, easy installation and integration with automated meter reading (AMR) systems. The application of this method to residential gas meters currently deployed is also given. This is done by performing a load simulation on realistic gas loads with the aim of identifying the necessary parameters that minimize the cost and complexity of the mechanical encoder module. The primary benefits of the system are efficiency analysis, appliance health monitoring and real-time customer feedback of gas usage. Additional benefits of include the ability to detect very small leaks and theft. This system has the potential for wide scale market adoption.

High performance in software development

CERN Multimedia

CERN. Geneva; Haapio, Petri; Liukkonen, Juha-Matti

2015-01-01

What are the ingredients of high-performing software? Software development, especially for large high-performance systems, is one the most complex tasks mankind has ever tried. Technological change leads to huge opportunities but challenges our old ways of working. Processing large data sets, possibly in real time or with other tight computational constraints, requires an efficient solution architecture. Efficiency requirements span from the distributed storage and large-scale organization of computation and data onto the lowest level of processor and data bus behavior. Integrating performance behavior over these levels is especially important when the computation is resource-bounded, as it is in numerics: physical simulation, machine learning, estimation of statistical models, etc. For example, memory locality and utilization of vector processing are essential for harnessing the computing power of modern processor architectures due to the deep memory hierarchies of modern general-purpose computers. As a r...

High Performance Computing in Science and Engineering '16 : Transactions of the High Performance Computing Center, Stuttgart (HLRS) 2016

CERN Document Server

Kröner, Dietmar; Resch, Michael

2016-01-01

This book presents the state-of-the-art in supercomputer simulation. It includes the latest findings from leading researchers using systems from the High Performance Computing Center Stuttgart (HLRS) in 2016. The reports cover all fields of computational science and engineering ranging from CFD to computational physics and from chemistry to computer science with a special emphasis on industrially relevant applications. Presenting findings of one of Europe’s leading systems, this volume covers a wide variety of applications that deliver a high level of sustained performance. The book covers the main methods in high-performance computing. Its outstanding results in achieving the best performance for production codes are of particular interest for both scientists and engineers. The book comes with a wealth of color illustrations and tables of results.

High-performance computing — an overview

Science.gov (United States)

Marksteiner, Peter

1996-08-01

An overview of high-performance computing (HPC) is given. Different types of computer architectures used in HPC are discussed: vector supercomputers, high-performance RISC processors, various parallel computers like symmetric multiprocessors, workstation clusters, massively parallel processors. Software tools and programming techniques used in HPC are reviewed: vectorizing compilers, optimization and vector tuning, optimization for RISC processors; parallel programming techniques like shared-memory parallelism, message passing and data parallelism; and numerical libraries.

Team Development for High Performance Management.

Science.gov (United States)

Schermerhorn, John R., Jr.

1986-01-01

The author examines a team development approach to management that creates shared commitments to performance improvement by focusing the attention of managers on individual workers and their task accomplishments. It uses the "high-performance equation" to help managers confront shared beliefs and concerns about performance and develop realistic…

An 'intelligent' approach to radioimmunoassay sample counting employing a microprocessor-controlled sample counter

International Nuclear Information System (INIS)

Ekins, R.P.; Sufi, S.; Malan, P.G.

1978-01-01

The enormous impact on medical science in the last two decades of microanalytical techniques employing radioisotopic labels has, in turn, generated a large demand for automatic radioisotopic sample counters. Such instruments frequently comprise the most important item of capital equipment required in the use of radioimmunoassay and related techniques and often form a principle bottleneck in the flow of samples through a busy laboratory. It is therefore imperative that such instruments should be used 'intelligently' and in an optimal fashion to avoid both the very large capital expenditure involved in the unnecessary proliferation of instruments and the time delays arising from their sub-optimal use. Most of the current generation of radioactive sample counters nevertheless rely on primitive control mechanisms based on a simplistic statistical theory of radioactive sample counting which preclude their efficient and rational use. The fundamental principle upon which this approach is based is that it is useless to continue counting a radioactive sample for a time longer than that required to yield a significant increase in precision of the measurement. Thus, since substantial experimental errors occur during sample preparation, these errors should be assessed and must be related to the counting errors for that sample. The objective of the paper is to demonstrate that the combination of a realistic statistical assessment of radioactive sample measurement, together with the more sophisticated control mechanisms that modern microprocessor technology make possible, may often enable savings in counter usage of the order of 5- to 10-fold to be made. (author)

PASSOLAR - user handbook for microprocessors. Calculations in the planning stage of solar systems. PASSOLAR - Benutzer-Handbuch fuer Mikrocomputer. Berechnungen bei der Planung von passiven Sonnenenergie-Systemen

Energy Technology Data Exchange (ETDEWEB)

Graeff, R.W.; Martin, N.H.; Lovy, D.; Lawton, L.

1983-01-01

PASSOLAR is an interactive program for microprocessors permitting to carry through a computer evaluation of parts of buildings designed for passive solar energy use. It follows the methods described in the 'Passive Solar Design Handbook, Volume Three' (7). Users are to be enabled to calculate the monthly values for the heating load, its solar fraction and the auxiliary heating load as easily as possible. These calculations are not only possible for 94 different types of solar energy supply systems in winter gardens and by direct and indirect solar radiation but also for many other systems varying more or less from the supply systems. (orig./BWI).

High Performance Walls in Hot-Dry Climates

Energy Technology Data Exchange (ETDEWEB)

Hoeschele, Marc [Alliance for Residential Building Innovation (ARBI), Davis, CA (United States); Springer, David [Alliance for Residential Building Innovation (ARBI), Davis, CA (United States); Dakin, Bill [Alliance for Residential Building Innovation (ARBI), Davis, CA (United States); German, Alea [Alliance for Residential Building Innovation (ARBI), Davis, CA (United States)

2015-01-01

High performance walls represent a high priority measure for moving the next generation of new homes to the Zero Net Energy performance level. The primary goal in improving wall thermal performance revolves around increasing the wall framing from 2x4 to 2x6, adding more cavity and exterior rigid insulation, achieving insulation installation criteria meeting ENERGY STAR's thermal bypass checklist. To support this activity, in 2013 the Pacific Gas & Electric Company initiated a project with Davis Energy Group (lead for the Building America team, Alliance for Residential Building Innovation) to solicit builder involvement in California to participate in field demonstrations of high performance wall systems. Builders were given incentives and design support in exchange for providing site access for construction observation, cost information, and builder survey feedback. Information from the project was designed to feed into the 2016 Title 24 process, but also to serve as an initial mechanism to engage builders in more high performance construction strategies. This Building America project utilized information collected in the California project.

Pattern recognition in high energy physics

International Nuclear Information System (INIS)

Tenner, A.G.

1980-01-01

In high energy physics experiments tracks of elementary particles are recorded by different types of equipment. Coordinates of points of these tracks have to be measured for the geometrical reconstruction and the further analysis of the observed events. Pattern recognition methods may facilitate the detection of tracks or whole events and the separation of relevant from non-relevant information. They may also serve for the automation of measurement. Generally, all work is done by digital computation. In a bubble chamber tracks appear as strings of vapour bubbles that can be recorded photographically. Two methods of pattern recognition are discussed. The flying spot digitizer encodes the pattern on the photograph into point coordinates in the memory of a computer. The computer carries out the pattern recognition procedure entirely on the basis of the stored information. Cathode ray instruments scan the photograph by means of a computer steered optical device. Data acquisition from the film is performed in a feedback loop of the computation. In electronic experimental equipment tracks are defined by the spacial distribution of hits of counters (wire counters, scintillation counters, spark chambers). Pattern recognition is generally performed in various stages both by on-line and off-line equipment. Problems in the data handling arise both from the great abundance of data and from the time limits imposed on the on-line computation by high measuring rates. The on-line computation is carried out by hardwired logic, small computers, and to an increasing extent by microprocessors. (Auth.)

The Role of Performance Management in Creating and Maintaining a High-Performance Organization

Directory of Open Access Journals (Sweden)

André A. de Waal

2015-04-01

Full Text Available There is still a good deal of confusion in the literature about how the use of a performance management system affects overall organizational performance. Some researchers find that performance management enhances both the financial and non-financial results of an organization, while others do not find any positive effects or, at most, ambiguous effects. An important step toward getting more clarity in this relationship is to investigate the role performance management plays in creating and maintaining a high-performance organization (HPO. The purpose of this study is to integrate performance management analysis (PMA and high-performance organization (HPO. A questionnaire combining questions on PMA dimensions and HPO factors was administered to two European-based multinational firms. Based on 468 valid questionnaires, a correlation analysis was performed on the PMA dimensions and the HPO factors in order to test the impact of performance management on the factors of high organizational performance. The results show strong and significant correlations between all the PMA dimensions and all the HPO factors, indicating that a performance management system that fosters performance-driven behavior in the organization is of critical importance to strengthen overall financial and non-financial performance.

Development of new high-performance stainless steels

International Nuclear Information System (INIS)

Park, Yong Soo

2002-01-01

This paper focused on high-performance stainless steels and their development status. Effect of nitrogen addition on super-stainless steel was discussed. Research activities at Yonsei University, on austenitic and martensitic high-performance stainless, steels, and the next-generation duplex stainless steels were introduced

vSphere high performance cookbook

CERN Document Server

Sarkar, Prasenjit

2013-01-01

vSphere High Performance Cookbook is written in a practical, helpful style with numerous recipes focusing on answering and providing solutions to common, and not-so common, performance issues and problems.The book is primarily written for technical professionals with system administration skills and some VMware experience who wish to learn about advanced optimization and the configuration features and functions for vSphere 5.1.

High Burnup Fuel Performance and Safety Research

Energy Technology Data Exchange (ETDEWEB)

Bang, Je Keun; Lee, Chan Bok; Kim, Dae Ho (and others)

2007-03-15

The worldwide trend of nuclear fuel development is to develop a high burnup and high performance nuclear fuel with high economies and safety. Because the fuel performance evaluation code, INFRA, has a patent, and the superiority for prediction of fuel performance was proven through the IAEA CRP FUMEX-II program, the INFRA code can be utilized with commercial purpose in the industry. The INFRA code was provided and utilized usefully in the universities and relevant institutes domesticallly and it has been used as a reference code in the industry for the development of the intrinsic fuel rod design code.

Danish High Performance Concretes

DEFF Research Database (Denmark)

Nielsen, M. P.; Christoffersen, J.; Frederiksen, J.

1994-01-01

In this paper the main results obtained in the research program High Performance Concretes in the 90's are presented. This program was financed by the Danish government and was carried out in cooperation between The Technical University of Denmark, several private companies, and Aalborg University...... concretes, workability, ductility, and confinement problems....

Promising high monetary rewards for future task performance increases intermediate task performance.

Directory of Open Access Journals (Sweden)

Claire M Zedelius

Full Text Available In everyday life contexts and work settings, monetary rewards are often contingent on future performance. Based on research showing that the anticipation of rewards causes improved task performance through enhanced task preparation, the present study tested the hypothesis that the promise of monetary rewards for future performance would not only increase future performance, but also performance on an unrewarded intermediate task. Participants performed an auditory Simon task in which they responded to two consecutive tones. While participants could earn high vs. low monetary rewards for fast responses to every second tone, their responses to the first tone were not rewarded. Moreover, we compared performance under conditions in which reward information could prompt strategic performance adjustments (i.e., when reward information was presented for a relatively long duration to conditions preventing strategic performance adjustments (i.e., when reward information was presented very briefly. Results showed that high (vs. low rewards sped up both rewarded and intermediate, unrewarded responses, and the effect was independent of the duration of reward presentation. Moreover, long presentation led to a speed-accuracy trade-off for both rewarded and unrewarded tones, whereas short presentation sped up responses to rewarded and unrewarded tones without this trade-off. These results suggest that high rewards for future performance boost intermediate performance due to enhanced task preparation, and they do so regardless whether people respond to rewards in a strategic or non-strategic manner.

Promising high monetary rewards for future task performance increases intermediate task performance.

Science.gov (United States)

Zedelius, Claire M; Veling, Harm; Bijleveld, Erik; Aarts, Henk

2012-01-01

In everyday life contexts and work settings, monetary rewards are often contingent on future performance. Based on research showing that the anticipation of rewards causes improved task performance through enhanced task preparation, the present study tested the hypothesis that the promise of monetary rewards for future performance would not only increase future performance, but also performance on an unrewarded intermediate task. Participants performed an auditory Simon task in which they responded to two consecutive tones. While participants could earn high vs. low monetary rewards for fast responses to every second tone, their responses to the first tone were not rewarded. Moreover, we compared performance under conditions in which reward information could prompt strategic performance adjustments (i.e., when reward information was presented for a relatively long duration) to conditions preventing strategic performance adjustments (i.e., when reward information was presented very briefly). Results showed that high (vs. low) rewards sped up both rewarded and intermediate, unrewarded responses, and the effect was independent of the duration of reward presentation. Moreover, long presentation led to a speed-accuracy trade-off for both rewarded and unrewarded tones, whereas short presentation sped up responses to rewarded and unrewarded tones without this trade-off. These results suggest that high rewards for future performance boost intermediate performance due to enhanced task preparation, and they do so regardless whether people respond to rewards in a strategic or non-strategic manner.

Comparison of ultra high performance supercritical fluid chromatography, ultra high performance liquid chromatography, and gas chromatography for the separation of synthetic cathinones.

Science.gov (United States)

Carnes, Stephanie; O'Brien, Stacey; Szewczak, Angelica; Tremeau-Cayel, Lauriane; Rowe, Walter F; McCord, Bruce; Lurie, Ira S

2017-09-01

A comparison of ultra high performance supercritical fluid chromatography, ultra high performance liquid chromatography, and gas chromatography for the separation of synthetic cathinones has been conducted. Nine different mixtures of bath salts were analyzed in this study. The three different chromatographic techniques were examined using a general set of controlled synthetic cathinones as well as a variety of other synthetic cathinones that exist as positional isomers. Overall 35 different synthetic cathinones were analyzed. A variety of column types and chromatographic modes were examined for developing each separation. For the ultra high performance supercritical fluid chromatography separations, analyses were performed using a series of Torus and Trefoil columns with either ammonium formate or ammonium hydroxide as additives, and methanol, ethanol or isopropanol organic solvents as modifiers. Ultra high performance liquid chromatographic separations were performed in both reversed phase and hydrophilic interaction chromatographic modes using SPP C18 and SPP HILIC columns. Gas chromatography separations were performed using an Elite-5MS capillary column. The orthogonality of ultra high performance supercritical fluid chromatography, ultra high performance liquid chromatography, and gas chromatography was examined using principal component analysis. For the best overall separation of synthetic cathinones, the use of ultra high performance supercritical fluid chromatography in combination with gas chromatography is recommended. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High Performance Electronics on Flexible Silicon

KAUST Repository

Sevilla, Galo T.

2016-09-01

Over the last few years, flexible electronic systems have gained increased attention from researchers around the world because of their potential to create new applications such as flexible displays, flexible energy harvesters, artificial skin, and health monitoring systems that cannot be integrated with conventional wafer based complementary metal oxide semiconductor processes. Most of the current efforts to create flexible high performance devices are based on the use of organic semiconductors. However, inherent material\\'s limitations make them unsuitable for big data processing and high speed communications. The objective of my doctoral dissertation is to develop integration processes that allow the transformation of rigid high performance electronics into flexible ones while maintaining their performance and cost. In this work, two different techniques to transform inorganic complementary metal-oxide-semiconductor electronics into flexible ones have been developed using industry compatible processes. Furthermore, these techniques were used to realize flexible discrete devices and circuits which include metal-oxide-semiconductor field-effect-transistors, the first demonstration of flexible Fin-field-effect-transistors, and metal-oxide-semiconductors-based circuits. Finally, this thesis presents a new technique to package, integrate, and interconnect flexible high performance electronics using low cost additive manufacturing techniques such as 3D printing and inkjet printing. This thesis contains in depth studies on electrical, mechanical, and thermal properties of the fabricated devices.

Critical Factors Explaining the Leadership Performance of High-Performing Principals

Science.gov (United States)

Hutton, Disraeli M.

2018-01-01

The study explored critical factors that explain leadership performance of high-performing principals and examined the relationship between these factors based on the ratings of school constituents in the public school system. The principal component analysis with the use of Varimax Rotation revealed that four components explain 51.1% of the…

High Performance Walls in Hot-Dry Climates

Energy Technology Data Exchange (ETDEWEB)

Hoeschele, Marc [National Renewable Energy Lab. (NREL), Golden, CO (United States); Springer, David [National Renewable Energy Lab. (NREL), Golden, CO (United States); Dakin, Bill [National Renewable Energy Lab. (NREL), Golden, CO (United States); German, Alea [National Renewable Energy Lab. (NREL), Golden, CO (United States)

2015-01-01

High performance walls represent a high priority measure for moving the next generation of new homes to the Zero Net Energy performance level. The primary goal in improving wall thermal performance revolves around increasing the wall framing from 2x4 to 2x6, adding more cavity and exterior rigid insulation, achieving insulation installation criteria meeting ENERGY STAR's thermal bypass checklist, and reducing the amount of wood penetrating the wall cavity.

High-performance liquid chromatography of oligoguanylates at high pH

Science.gov (United States)

Stribling, R.; Deamer, D. (Principal Investigator)

1991-01-01

Because of the stable self-structures formed by oligomers of guanosine, standard high-performance liquid chromatography techniques for oligonucleotide fractionation are not applicable. Previously, oligoguanylate separations have been carried out at pH 12 using RPC-5 as the packing material. While RPC-5 provides excellent separations, there are several limitations, including the lack of a commercially available source. This report describes a new anion-exchange high-performance liquid chromatography method using HEMA-IEC BIO Q, which successfully separates different forms of the guanosine monomer as well as longer oligoguanylates. The reproducibility and stability at high pH suggests a versatile role for this material.

Peculiarities of the relays intended for operating trip coils of the high-voltage circuit breakers

Directory of Open Access Journals (Sweden)

Gurevich Vladimir

2007-01-01

Full Text Available Parameters of the subminiature electromagnetic relays used as output elements in microprocessor relay protection, do not correspond to technical specifications on these relay protection. The reasons of this discrepancy are analyzed. Contradictions and discrepancies of the international standards in this area are considered. It is shown, that absence of clearness in standards and mistakes in technical specifications of manufacturers of microprocessor protection do not allow estimating correctly technical parameters and lead to decrease in reliability of relay protection.

Development of high reliability dual redundant FADEC. Koshinraisei nijukei FADEC no kaihatsu

Energy Technology Data Exchange (ETDEWEB)

Endo, M [Ishikawajima-Harima Heavy Industries, Co. Ltd., Tokyo (Japan)

1994-05-01

The control unit of gas turbine for the aircraft jet engine use must draw overall performance in compliance with the thrust commanded by the pilot under all flying conditions of the engine. High reliability is required in flight safety. The present paper explains a developed unit of dual redundant FADEC (full authority digital electronic control) and high-density mounting technology for the electronic devices required by the FADEC. The FADEC unit is composed of two hardware systems with their respective microprocessors of the same structure. Each of both systems can solely control the engine, while they are both commanded by a necessary signal for the dual system operation and connected through a digital by-pass which can exchange the input/output data between them. For the operational confirmation of FADEC unit, its control characteristics were inspected by intentionally putting it out of order at the time of engine acceleration/deceleration and other transient operations. The control system could be switched without control characteristics lost of the engine. 9 figs., 2 tabs.

Development of high-performance concrete having high resistance to chloride penetration

International Nuclear Information System (INIS)

Oh, Byung Hwan; Cha, Soo Won; Jang, Bong Seok; Jang, Seung Yup

2002-01-01

The resistance to chloride penetration is one of the simplest measures to determine the durability of concrete, e.g. resistance to freezing and thawing, corrosion of steel in concrete and other chemical attacks. Thus, high-performance concrete may be defined as the concrete having high resistance to chloride penetration as well as high strength. The purpose of this paper is to investigate the resistance to chloride penetration of different types of concrete and to develop high-performance concrete that has very high resistance to chloride penetration, and thus, can guarantee high durability. A large number of concrete specimens have been tested by the rapid chloride permeability test method as designated in AASHTO T 277 and ASTM C 1202. The major test variables include water-to-binder ratios, type of cement, type and amount of mineral admixtures (silica fume, fly ash and blast-furnace slag), maximum size of aggregates and air-entrainment. Test results show that concrete containing optimal amount of silica fume shows very high resistance to chloride penetration, and high-performance concrete developed in this study can be efficiently employed to enhance the durability of concrete structures in severe environments such as nuclear power plants, water-retaining structures and other offshore structures

Identifying High Performance ERP Projects

OpenAIRE

Stensrud, Erik; Myrtveit, Ingunn

2002-01-01

Learning from high performance projects is crucial for software process improvement. Therefore, we need to identify outstanding projects that may serve as role models. It is common to measure productivity as an indicator of performance. It is vital that productivity measurements deal correctly with variable returns to scale and multivariate data. Software projects generally exhibit variable returns to scale, and the output from ERP projects is multivariate. We propose to use Data Envelopment ...

Extended performance electric propulsion power processor design study. Volume 2: Technical summary

Science.gov (United States)

Biess, J. J.; Inouye, L. Y.; Schoenfeld, A. D.

1977-01-01

Electric propulsion power processor technology has processed during the past decade to the point that it is considered ready for application. Several power processor design concepts were evaluated and compared. Emphasis was placed on a 30 cm ion thruster power processor with a beam power rating supply of 2.2KW to 10KW for the main propulsion power stage. Extension in power processor performance were defined and were designed in sufficient detail to determine efficiency, component weight, part count, reliability and thermal control. A detail design was performed on a microprocessor as the thyristor power processor controller. A reliability analysis was performed to evaluate the effect of the control electronics redesign. Preliminary electrical design, mechanical design and thermal analysis were performed on a 6KW power transformer for the beam supply. Bi-Mod mechanical, structural and thermal control configurations were evaluated for the power processor and preliminary estimates of mechanical weight were determined.

Multi-faceted data gathering and analyzing system

International Nuclear Information System (INIS)

Gustavson, D.B.; Rich, K.

1977-10-01

A low-cost general purpose data gathering and analyzing system based on a microprocessor, an interface to CAMAC, and a phone link to a time-sharing system was implemented. The parts cost for the microprocessor system was about $6000. The microprocessor buffers the data such that the variable response of the time-sharing system is acceptable for performing real-time data acquisition. The full power and flexibility of the time-sharing system excels at the task of on-line data analysis once this buffering problem is solved. 4 figures

Integrated plasma control for high performance tokamaks

International Nuclear Information System (INIS)

Humphreys, D.A.; Deranian, R.D.; Ferron, J.R.; Johnson, R.D.; LaHaye, R.J.; Leuer, J.A.; Penaflor, B.G.; Walker, M.L.; Welander, A.S.; Jayakumar, R.J.; Makowski, M.A.; Khayrutdinov, R.R.

2005-01-01

Sustaining high performance in a tokamak requires controlling many equilibrium shape and profile characteristics simultaneously with high accuracy and reliability, while suppressing a variety of MHD instabilities. Integrated plasma control, the process of designing high-performance tokamak controllers based on validated system response models and confirming their performance in detailed simulations, provides a systematic method for achieving and ensuring good control performance. For present-day devices, this approach can greatly reduce the need for machine time traditionally dedicated to control optimization, and can allow determination of high-reliability controllers prior to ever producing the target equilibrium experimentally. A full set of tools needed for this approach has recently been completed and applied to present-day devices including DIII-D, NSTX and MAST. This approach has proven essential in the design of several next-generation devices including KSTAR, EAST, JT-60SC, and ITER. We describe the method, results of design and simulation tool development, and recent research producing novel approaches to equilibrium and MHD control in DIII-D. (author)

Highlighting High Performance: Blackstone Valley Regional Vocational Technical High School; Upton, Massachusetts

Energy Technology Data Exchange (ETDEWEB)

2006-10-01

This brochure describes the key high-performance building features of the Blackstone Valley High School. The brochure was paid for by the Massachusetts Technology Collaborative as part of their Green Schools Initiative. High-performance features described are daylighting and energy-efficient lighting, indoor air quality, solar energy, building envelope, heating and cooling systems, and water conservation. Energy cost savings are also discussed.

Ground Glass Pozzolan in Conventional, High, and Ultra-High Performance Concrete

Directory of Open Access Journals (Sweden)

Tagnit-Hamou Arezki

2018-01-01

Full Text Available Ground-glass pozzolan (G obtained by grinding the mixed-waste glass to same fineness of cement can act as a supplementary-cementitious material (SCM, given that it is an amorphous and a pozzolanic material. The G showed promising performances in different concrete types such as conventional concrete (CC, high-performance concrete (HPC, and ultra-high performance concrete (UHPC. The current paper reports on the characteristics and performance of G in these concrete types. The use of G provides several advantages (technological, economical, and environmental. It reduces the production cost of concrete and decrease the carbon footprint of a traditional concrete structures. The rheology of fresh concrete can be improved due to the replacement of cement by non-absorptive glass particles. Strength and rigidity improvements in the concrete containing G are due to the fact that glass particles act as inclusions having a very high strength and elastic modulus that have a strengthening effect on the overall hardened matrix.

Mood states and motor performance: a study with high performance voleybol athletes

Directory of Open Access Journals (Sweden)

Lenamar Fiorese Vieira

2008-07-01

Full Text Available http://dx.doi.org/10.5007/1980-0037.2008v10n1p62 The objective of this research was to investigate the relationship between the sporting performance and mood states of high performance volleyball athletes. Twenty-three adult athletes of both sexes were assessed. The measurement instrument adopted was the POMS questionnaire. Data collection was carried out individually during the state championships. Dada were analyzed using descriptive statistics; the Friedman test for analysis of variance and the Mann-Whitney test for differences between means. The results demonstrated that both teams exhibited the mood state profi le corresponding to the “iceberg” profile. In the male team, vigor remained constant throughout all phases of the competition, while in the female team this element was unstable. The male team’s fatigue began low, during the training phase, with rates that rose as the competition progressed, with statistically significant differences between the fi rst and last matches the team played. In the female team, the confusion factor, which was at a high level during training, reduced progressively throughout the competition, with a difference that was signifi cant to p ≤ 0.05. With relation to performance and mood profi le, the female team exhibited statistically significant differences between the mean vigor and fatigue factors of high and low performance athletes. It is therefore concluded that the mood state profi le is a factor that impacts on the motor performance of these high performance teams.

High performance leadership in unusually challenging educational circumstances

Directory of Open Access Journals (Sweden)

Andy Hargreaves

2015-04-01

Full Text Available This paper draws on findings from the results of a study of leadership in high performing organizations in three sectors. Organizations were sampled and included on the basis of high performance in relation to no performance, past performance, performance among similar peers and performance in the face of limited resources or challenging circumstances. The paper concentrates on leadership in four schools that met the sample criteria.  It draws connections to explanations of the high performance ofEstoniaon the OECD PISA tests of educational achievement. The article argues that leadership in these four schools that performed above expectations comprised more than a set of competencies. Instead, leadership took the form of a narrative or quest that pursued an inspiring dream with relentless determination; took improvement pathways that were more innovative than comparable peers; built collaboration and community including with competing schools; and connected short-term success to long-term sustainability.

High-performance computing in seismology

Energy Technology Data Exchange (ETDEWEB)

NONE

1996-09-01

The scientific, technical, and economic importance of the issues discussed here presents a clear agenda for future research in computational seismology. In this way these problems will drive advances in high-performance computing in the field of seismology. There is a broad community that will benefit from this work, including the petroleum industry, research geophysicists, engineers concerned with seismic hazard mitigation, and governments charged with enforcing a comprehensive test ban treaty. These advances may also lead to new applications for seismological research. The recent application of high-resolution seismic imaging of the shallow subsurface for the environmental remediation industry is an example of this activity. This report makes the following recommendations: (1) focused efforts to develop validated documented software for seismological computations should be supported, with special emphasis on scalable algorithms for parallel processors; (2) the education of seismologists in high-performance computing technologies and methodologies should be improved; (3) collaborations between seismologists and computational scientists and engineers should be increased; (4) the infrastructure for archiving, disseminating, and processing large volumes of seismological data should be improved.

High performance flexible CMOS SOI FinFETs

KAUST Repository

Fahad, Hossain M.

2014-06-01

We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

Architecting Web Sites for High Performance

Directory of Open Access Journals (Sweden)

Arun Iyengar

2002-01-01

Full Text Available Web site applications are some of the most challenging high-performance applications currently being developed and deployed. The challenges emerge from the specific combination of high variability in workload characteristics and of high performance demands regarding the service level, scalability, availability, and costs. In recent years, a large body of research has addressed the Web site application domain, and a host of innovative software and hardware solutions have been proposed and deployed. This paper is an overview of recent solutions concerning the architectures and the software infrastructures used in building Web site applications. The presentation emphasizes three of the main functions in a complex Web site: the processing of client requests, the control of service levels, and the interaction with remote network caches.

Development of a high performance liquid chromatography method ...

African Journals Online (AJOL)

Development of a high performance liquid chromatography method for simultaneous ... Purpose: To develop and validate a new low-cost high performance liquid chromatography (HPLC) method for ..... Several papers have reported the use of ...

Toward a theory of high performance.

Science.gov (United States)

Kirby, Julia

2005-01-01

What does it mean to be a high-performance company? The process of measuring relative performance across industries and eras, declaring top performers, and finding the common drivers of their success is such a difficult one that it might seem a fool's errand to attempt. In fact, no one did for the first thousand or so years of business history. The question didn't even occur to many scholars until Tom Peters and Bob Waterman released In Search of Excellence in 1982. Twenty-three years later, we've witnessed several more attempts--and, just maybe, we're getting closer to answers. In this reported piece, HBR senior editor Julia Kirby explores why it's so difficult to study high performance and how various research efforts--including those from John Kotter and Jim Heskett; Jim Collins and Jerry Porras; Bill Joyce, Nitin Nohria, and Bruce Roberson; and several others outlined in a summary chart-have attacked the problem. The challenge starts with deciding which companies to study closely. Are the stars the ones with the highest market caps, the ones with the greatest sales growth, or simply the ones that remain standing at the end of the game? (And when's the end of the game?) Each major study differs in how it defines success, which companies it therefore declares to be worthy of emulation, and the patterns of activity and attitude it finds in common among them. Yet, Kirby concludes, as each study's method incrementally solves problems others have faced, we are progressing toward a consensus theory of high performance.

Development of high performance cladding materials

International Nuclear Information System (INIS)

Park, Jeong Yong; Jeong, Y. H.; Park, S. Y.

2010-04-01

The irradiation test for HANA claddings conducted and a series of evaluation for next-HANA claddings as well as their in-pile and out-of pile performances tests were also carried out at Halden research reactor. The 6th irradiation test have been completed successfully in Halden research reactor. As a result, HANA claddings showed high performance, such as corrosion resistance increased by 40% compared to Zircaloy-4. The high performance of HANA claddings in Halden test has enabled lead test rod program as the first step of the commercialization of HANA claddings. DB has been established for thermal and LOCA-related properties. It was confirmed from the thermal shock test that the integrity of HANA claddings was maintained in more expanded region than the criteria regulated by NRC. The manufacturing process of strips was established in order to apply HANA alloys, which were originally developed for the claddings, to the spacer grids. 250 kinds of model alloys for the next-generation claddings were designed and manufactured over 4 times and used to select the preliminary candidate alloys for the next-generation claddings. The selected candidate alloys showed 50% better corrosion resistance and 20% improved high temperature oxidation resistance compared to the foreign advanced claddings. We established the manufacturing condition controlling the performance of the dual-cooled claddings by changing the reduction rate in the cold working steps

Klystron control software in the SLC

International Nuclear Information System (INIS)

Jobe, R.K.; Thompson, K.; Phinney, N.

1985-05-01

Triggering, control, and monitoring of 240 high-power klystrons will be supported by the SLC control system this summer. The control software is distributed among a VAX host computer, a local microprocessor cluster, and a dedicated intelligent CAMAC module. The functions performed by these three components and the algorithms used are discussed

High performance computing in Windows Azure cloud

OpenAIRE

Ambruš, Dejan

2013-01-01

High performance, security, availability, scalability, flexibility and lower costs of maintenance have essentially contributed to the growing popularity of cloud computing in all spheres of life, especially in business. In fact cloud computing offers even more than this. With usage of virtual computing clusters a runtime environment for high performance computing can be efficiently implemented also in a cloud. There are many advantages but also some disadvantages of cloud computing, some ...

High Performance Work System, HRD Climate and Organisational Performance: An Empirical Study

Science.gov (United States)

Muduli, Ashutosh

2015-01-01

Purpose: This paper aims to study the relationship between high-performance work system (HPWS) and organizational performance and to examine the role of human resource development (HRD) Climate in mediating the relationship between HPWS and the organizational performance in the context of the power sector of India. Design/methodology/approach: The…

Governance among Malaysian high performing companies

Directory of Open Access Journals (Sweden)

Asri Marsidi

2016-07-01

Full Text Available Well performed companies have always been linked with effective governance which is generally reflected through effective board of directors. However many issues concerning the attributes for effective board of directors remained unresolved. Nowadays diversity has been perceived as able to influence the corporate performance due to the likelihood of meeting variety of needs and demands from diverse customers and clients. The study therefore aims to provide a fundamental understanding on governance among high performing companies in Malaysia.

The electrochemical fluorination of polymeric materials for high energy density aqueous and non-aqueous battery and fuel cell separators

Science.gov (United States)

Liu, C. C.

1983-01-01

A computerized system was established and the electrochemical fluorination of trichloroethylene, polyacrylic acid and polyvinyl alcohol in anhydrous hydrogen fluoride was attempted. Both solid substrates as well as membranes were used. Some difficulties were found in handling and analyzing the solid substrates and membranes. Further studies are needed in this area. A microprocessor aided electrochemical fluorination system capable of obtaining highly reproducible experimental results was established.

Powder metallurgical high performance materials. Proceedings. Volume 1: high performance P/M metals

International Nuclear Information System (INIS)

Kneringer, G.; Roedhammer, P.; Wildner, H.

2001-01-01

The proceedings of this sequence of seminars form an impressive chronicle of the continued progress in the understanding of refractory metals and cemented carbides and in their manufacture and application. There the ingenuity and assiduous work of thousands of scientists and engineers striving for progress in the field of powder metallurgy is documented in more than 2000 contributions covering some 30000 pages. The 15th Plansee Seminar was convened under the general theme 'Powder Metallurgical High Performance Materials'. Under this broadened perspective the seminar will strive to look beyond the refractory metals and cemented carbides, which remain at its focus, to novel classes of materials, such as intermetallic compounds, with potential for high temperature applications. (author)

Powder metallurgical high performance materials. Proceedings. Volume 1: high performance P/M metals

Energy Technology Data Exchange (ETDEWEB)

Kneringer, G; Roedhammer, P; Wildner, H [eds.

2001-07-01

The proceedings of this sequence of seminars form an impressive chronicle of the continued progress in the understanding of refractory metals and cemented carbides and in their manufacture and application. There the ingenuity and assiduous work of thousands of scientists and engineers striving for progress in the field of powder metallurgy is documented in more than 2000 contributions covering some 30000 pages. The 15th Plansee Seminar was convened under the general theme 'Powder Metallurgical High Performance Materials'. Under this broadened perspective the seminar will strive to look beyond the refractory metals and cemented carbides, which remain at its focus, to novel classes of materials, such as intermetallic compounds, with potential for high temperature applications. (author)

High-Speed, High-Performance DQPSK Optical Links with Reduced Complexity VDFE Equalizers

Directory of Open Access Journals (Sweden)

Maki Nanou

2017-02-01

Full Text Available Optical transmission technologies optimized for optical network segments sensitive to power consumption and cost, comprise modulation formats with direct detection technologies. Specifically, non-return to zero differential quaternary phase shift keying (NRZ-DQPSK in deployed fiber plants, combined with high-performance, low-complexity electronic equalizers to compensate residual impairments at the receiver end, can be proved as a viable solution for high-performance, high-capacity optical links. Joint processing of the constructive and the destructive signals at the single-ended DQPSK receiver provides improved performance compared to the balanced configuration, however, at the expense of higher hardware requirements, a fact that may not be neglected especially in the case of high-speed optical links. To overcome this bottleneck, the use of partially joint constructive/destructive DQPSK equalization is investigated in this paper. Symbol-by-symbol equalization is performed by means of Volterra decision feedback-type equalizers, driven by a reduced subset of signals selected from the constructive and the destructive ports of the optical detectors. The proposed approach offers a low-complexity alternative for electronic equalization, without sacrificing much of the performance compared to the fully-deployed counterpart. The efficiency of the proposed equalizers is demonstrated by means of computer simulation in a typical optical transmission scenario.

Design of JMTR high-performance fuel element

International Nuclear Information System (INIS)

Sakurai, Fumio; Shimakawa, Satoshi; Komori, Yoshihiro; Tsuchihashi, Keiichiro; Kaminaga, Fumito

1999-01-01

For test and research reactors, the core conversion to low-enriched uranium fuel is required from the viewpoint of non-proliferation of nuclear weapon material. Improvements of core performance are also required in order to respond to recent advanced utilization needs. In order to meet both requirements, a high-performance fuel element of high uranium density with Cd wires as burnable absorbers was adopted for JMTR core conversion to low-enriched uranium fuel. From the result of examination of an adaptability of a few group constants generated by a conventional transport-theory calculation with an isotropic scattering approximation to a few group diffusion-theory core calculation for design of the JMTR high-performance fuel element, it was clear that the depletion of Cd wires was not able to be predicted accurately using group constants generated by the conventional method. Therefore, a new generation method of a few group constants in consideration of an incident neutron spectrum at Cd wire was developed. As the result, the most suitable high-performance fuel element for JMTR was designed successfully, and that allowed extension of operation duration without refueling to almost twice as long and offer of irradiation field with constant neutron flux. (author)

ELMs IN DIII-D HIGH PERFORMANCE DISCHARGES

International Nuclear Information System (INIS)

TURNBULL, A.D; LAO, L.L; OSBORNE, T.H; SAUTER, O; STRAIT, E.J; TAYLOR, T.S; CHU, M.S; FERRON, J.R; GREENFIELD, C.M; LEONARD, A.W; MILLER, R.L; SNYDER, P.B; WILSON, H.R; ZOHM, H

2003-01-01

A new understanding of edge localized modes (ELMs) in tokamak discharges is emerging [P.B. Snyder, et al., Phys. Plasmas, 9, 2037 (2002)], in which the ELM is an essentially ideal magnetohydrodynamic (MHD) instability and the ELM severity is determined by the radial width of the linearly unstable MHD kink modes. A detailed, comparative study of the penetration into the core of the respective linear instabilities in a standard DIII-D ELMing, high confinement mode (H-mode) discharge, with that for two relatively high performance discharges shows that these are also encompassed within the framework of the new model. These instabilities represent the key, limiting factor in extending the high performance of these discharges. In the standard ELMing H-mode, the MHD instabilities are highly localized in the outer few percent flux surfaces and the ELM is benign, causing only a small temporary drop in the energy confinement. In contrast, for both a very high confinement mode (VH-mode) and an H-mode with a broad internal transport barrier (ITB) extending over the entire core and coalesced with the edge transport barrier, the linearly unstable modes penetrate well into the mid radius and the corresponding consequences for global confinement are significantly more severe. The ELM accordingly results in an irreversible loss of the high performance

The path toward HEP High Performance Computing

CERN Document Server

Apostolakis, John; Carminati, Federico; Gheata, Andrei; Wenzel, Sandro

2014-01-01

High Energy Physics code has been known for making poor use of high performance computing architectures. Efforts in optimising HEP code on vector and RISC architectures have yield limited results and recent studies have shown that, on modern architectures, it achieves a performance between 10% and 50% of the peak one. Although several successful attempts have been made to port selected codes on GPUs, no major HEP code suite has a 'High Performance' implementation. With LHC undergoing a major upgrade and a number of challenging experiments on the drawing board, HEP cannot any longer neglect the less-than-optimal performance of its code and it has to try making the best usage of the hardware. This activity is one of the foci of the SFT group at CERN, which hosts, among others, the Root and Geant4 project. The activity of the experiments is shared and coordinated via a Concurrency Forum, where the experience in optimising HEP code is presented and discussed. Another activity is the Geant-V project, centred on th...

3D printed high performance strain sensors for high temperature applications

Science.gov (United States)

Rahman, Md Taibur; Moser, Russell; Zbib, Hussein M.; Ramana, C. V.; Panat, Rahul

2018-01-01

Realization of high temperature physical measurement sensors, which are needed in many of the current and emerging technologies, is challenging due to the degradation of their electrical stability by drift currents, material oxidation, thermal strain, and creep. In this paper, for the first time, we demonstrate that 3D printed sensors show a metamaterial-like behavior, resulting in superior performance such as high sensitivity, low thermal strain, and enhanced thermal stability. The sensors were fabricated using silver (Ag) nanoparticles (NPs), using an advanced Aerosol Jet based additive printing method followed by thermal sintering. The sensors were tested under cyclic strain up to a temperature of 500 °C and showed a gauge factor of 3.15 ± 0.086, which is about 57% higher than that of those available commercially. The sensor thermal strain was also an order of magnitude lower than that of commercial gages for operation up to a temperature of 500 °C. An analytical model was developed to account for the enhanced performance of such printed sensors based on enhanced lateral contraction of the NP films due to the porosity, a behavior akin to cellular metamaterials. The results demonstrate the potential of 3D printing technology as a pathway to realize highly stable and high-performance sensors for high temperature applications.

High performance carbon nanocomposites for ultracapacitors

Science.gov (United States)

Lu, Wen

2012-10-02

The present invention relates to composite electrodes for electrochemical devices, particularly to carbon nanotube composite electrodes for high performance electrochemical devices, such as ultracapacitors.

High-Performance Java Codes for Computational Fluid Dynamics

Science.gov (United States)

Riley, Christopher; Chatterjee, Siddhartha; Biswas, Rupak; Biegel, Bryan (Technical Monitor)

2001-01-01

The computational science community is reluctant to write large-scale computationally -intensive applications in Java due to concerns over Java's poor performance, despite the claimed software engineering advantages of its object-oriented features. Naive Java implementations of numerical algorithms can perform poorly compared to corresponding Fortran or C implementations. To achieve high performance, Java applications must be designed with good performance as a primary goal. This paper presents the object-oriented design and implementation of two real-world applications from the field of Computational Fluid Dynamics (CFD): a finite-volume fluid flow solver (LAURA, from NASA Langley Research Center), and an unstructured mesh adaptation algorithm (2D_TAG, from NASA Ames Research Center). This work builds on our previous experience with the design of high-performance numerical libraries in Java. We examine the performance of the applications using the currently available Java infrastructure and show that the Java version of the flow solver LAURA performs almost within a factor of 2 of the original procedural version. Our Java version of the mesh adaptation algorithm 2D_TAG performs within a factor of 1.5 of its original procedural version on certain platforms. Our results demonstrate that object-oriented software design principles are not necessarily inimical to high performance.

Strategy Guideline: Partnering for High Performance Homes

Energy Technology Data Exchange (ETDEWEB)

Prahl, D.

2013-01-01

High performance houses require a high degree of coordination and have significant interdependencies between various systems in order to perform properly, meet customer expectations, and minimize risks for the builder. Responsibility for the key performance attributes is shared across the project team and can be well coordinated through advanced partnering strategies. For high performance homes, traditional partnerships need to be matured to the next level and be expanded to all members of the project team including trades, suppliers, manufacturers, HERS raters, designers, architects, and building officials as appropriate. In an environment where the builder is the only source of communication between trades and consultants and where relationships are, in general, adversarial as opposed to cooperative, the chances of any one building system to fail are greater. Furthermore, it is much harder for the builder to identify and capitalize on synergistic opportunities. Partnering can help bridge the cross-functional aspects of the systems approach and achieve performance-based criteria. Critical success factors for partnering include support from top management, mutual trust, effective and open communication, effective coordination around common goals, team building, appropriate use of an outside facilitator, a partnering charter progress toward common goals, an effective problem-solving process, long-term commitment, continuous improvement, and a positive experience for all involved.

Quantum Accelerators for High-performance Computing Systems

Energy Technology Data Exchange (ETDEWEB)

Humble, Travis S. [ORNL; Britt, Keith A. [ORNL; Mohiyaddin, Fahd A. [ORNL

2017-11-01

We define some of the programming and system-level challenges facing the application of quantum processing to high-performance computing. Alongside barriers to physical integration, prominent differences in the execution of quantum and conventional programs challenges the intersection of these computational models. Following a brief overview of the state of the art, we discuss recent advances in programming and execution models for hybrid quantum-classical computing. We discuss a novel quantum-accelerator framework that uses specialized kernels to offload select workloads while integrating with existing computing infrastructure. We elaborate on the role of the host operating system to manage these unique accelerator resources, the prospects for deploying quantum modules, and the requirements placed on the language hierarchy connecting these different system components. We draw on recent advances in the modeling and simulation of quantum computing systems with the development of architectures for hybrid high-performance computing systems and the realization of software stacks for controlling quantum devices. Finally, we present simulation results that describe the expected system-level behavior of high-performance computing systems composed from compute nodes with quantum processing units. We describe performance for these hybrid systems in terms of time-to-solution, accuracy, and energy consumption, and we use simple application examples to estimate the performance advantage of quantum acceleration.

Multi-sensor Array for High Altitude Balloon Missions to the Stratosphere

Science.gov (United States)

Davis, Tim; McClurg, Bryce; Sohl, John

2008-10-01

We have designed and built a microprocessor controlled and expandable multi-sensor array for data collection on near space missions. Weber State University has started a high altitude research balloon program called HARBOR. This array has been designed to data log a base set of measurements for every flight and has room for six guest instruments. The base measurements are absolute pressure, on-board temperature, 3-axis accelerometer for attitude measurement, and 2-axis compensated magnetic compass. The system also contains a real time clock and circuitry for logging data directly to a USB memory stick. In typical operation the measurements will be cycled through in sequence and saved to the memory stick along with the clock's time stamp. The microprocessor can be reprogrammed to adapt to guest experiments with either analog or digital interfacing. This system will fly with every mission and will provide backup data collection for other instrumentation for which the primary task is measuring atmospheric pressure and temperature. The attitude data will be used to determine the orientation of the onboard camera systems to aid in identifying features in the images. This will make these images easier to use for any future GIS (geographic information system) remote sensing missions.

A microprogrammable high-speed data collection system for position sensitive X-ray detectors

International Nuclear Information System (INIS)

Hashizume, H.

1984-01-01

A high-speed data acquisition system has been designed which collects digital data from one- and two-dimensional position sensitive X-ray detectors at a maximum average data rate of 1 MHz. The system consists of two separate fast buffer memories, a 64 K word by 20-bit main storage, two timers, a display controller, a computer interface and a keyboard, controlled by a specially designed microprogrammable microprocessor. Data collection is performed by executing a microprogram stored in the control storage; data coming from a detector are first accumulated in a small but fast buffer memory by hardware and transferred to the main storage under control of the microprogram. This design not only permits time-resolved data collections but also provides maximum speed, flexibility and cost-effectiveness simultaneously. The system also accepts data from integrated detectors such as TV cameras. The system has been designed for use in experiments at conventional and synchrotron X-ray sources. (orig.)

High Performance Commercial Fenestration Framing Systems

Energy Technology Data Exchange (ETDEWEB)

Mike Manteghi; Sneh Kumar; Joshua Early; Bhaskar Adusumalli

2010-01-31

A major objective of the U.S. Department of Energy is to have a zero energy commercial building by the year 2025. Windows have a major influence on the energy performance of the building envelope as they control over 55% of building energy load, and represent one important area where technologies can be developed to save energy. Aluminum framing systems are used in over 80% of commercial fenestration products (i.e. windows, curtain walls, store fronts, etc.). Aluminum framing systems are often required in commercial buildings because of their inherent good structural properties and long service life, which is required from commercial and architectural frames. At the same time, they are lightweight and durable, requiring very little maintenance, and offer design flexibility. An additional benefit of aluminum framing systems is their relatively low cost and easy manufacturability. Aluminum, being an easily recyclable material, also offers sustainable features. However, from energy efficiency point of view, aluminum frames have lower thermal performance due to the very high thermal conductivity of aluminum. Fenestration systems constructed of aluminum alloys therefore have lower performance in terms of being effective barrier to energy transfer (heat loss or gain). Despite the lower energy performance, aluminum is the choice material for commercial framing systems and dominates the commercial/architectural fenestration market because of the reasons mentioned above. In addition, there is no other cost effective and energy efficient replacement material available to take place of aluminum in the commercial/architectural market. Hence it is imperative to improve the performance of aluminum framing system to improve the energy performance of commercial fenestration system and in turn reduce the energy consumption of commercial building and achieve zero energy building by 2025. The objective of this project was to develop high performance, energy efficient commercial

HIGLE is a bifunctional homing endonuclease that directly interacts with HYL1 and SERRATE in Arabidopsis thaliana

DEFF Research Database (Denmark)

Cho, Seok Keun; Ryu, Moon Young; Poulsen, Christian

2017-01-01

A highly coordinated complex known as the microprocessor precisely processes primary transcripts of MIRNA genes into mature miRNAs. In plants, the microprocessor minimally consists of three components: Dicer-like protein 1 (DCL1), HYPONASTIC LEAF 1 (HYL1), and SERRATE (SE). To precisely modulate ...

High-Performance Management Practices and Employee Outcomes in Denmark

DEFF Research Database (Denmark)

Cristini, Annalisa; Eriksson, Tor; Pozzoli, Dario

High-performance work practices are frequently considered to have positive effects on corporate performance, but what do they do for employees? After showing that organizational innovation is indeed positively associated with firm performance, we investigate whether high-involvement work practices...

Optical interconnection networks for high-performance computing systems

International Nuclear Information System (INIS)

Biberman, Aleksandr; Bergman, Keren

2012-01-01

Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. Chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, offer unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of our work, we demonstrate such feasibility of waveguides, modulators, switches and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. We propose novel silicon photonic devices, subsystems, network topologies and architectures to enable unprecedented performance of these photonic interconnection networks. Furthermore, the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers. (review article)

High-performance, stretchable, wire-shaped supercapacitors.

Science.gov (United States)

Chen, Tao; Hao, Rui; Peng, Huisheng; Dai, Liming

2015-01-07

A general approach toward extremely stretchable and highly conductive electrodes was developed. The method involves wrapping a continuous carbon nanotube (CNT) thin film around pre-stretched elastic wires, from which high-performance, stretchable wire-shaped supercapacitors were fabricated. The supercapacitors were made by twisting two such CNT-wrapped elastic wires, pre-coated with poly(vinyl alcohol)/H3PO4 hydrogel, as the electrolyte and separator. The resultant wire-shaped supercapacitors exhibited an extremely high elasticity of up to 350% strain with a high device capacitance up to 30.7 F g(-1), which is two times that of the state-of-the-art stretchable supercapacitor under only 100% strain. The wire-shaped structure facilitated the integration of multiple supercapacitors into a single wire device to meet specific energy and power needs for various potential applications. These supercapacitors can be repeatedly stretched from 0 to 200% strain for hundreds of cycles with no change in performance, thus outperforming all the reported state-of-the-art stretchable electronics. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Computer-aided orbital welding reaches a new level of performance

International Nuclear Information System (INIS)

Galloway, J.G.; Maak, P.Y.Y.; McNabb, S.C.

1993-01-01

This article documents the development of a custom-built microprocessor controller which overcomes the major shortcomings of existing commercially available pipe welding systems. This unique control design effectively extends the one-knob-control concept of the power source industry to the control of a complete mechanized welding system. Magnatech, East Granby, Conn., a manufacturer of orbital welding equipment, will be commercializing this technology into its Pipeliner welding system in the near future. Ontario Hydro Research Div. purchased a commercial pipe welding system for both laboratory welding development and field trials. Its applications were targeted for pressure piping in both nuclear power and fossil fuel fired electricity generating plants. They demonstrated the feasibility of using a mechanized continuous wire welding process to weld the fill passes of carbon steel piping to stringent inspection standards of nuclear pressure piping. They also concluded that significant improvements to commercial pipe welding systems can be achieved through the use of microprocessor controls

High Performance Computing in Science and Engineering '14

CERN Document Server

Kröner, Dietmar; Resch, Michael

2015-01-01

This book presents the state-of-the-art in supercomputer simulation. It includes the latest findings from leading researchers using systems from the High Performance Computing Center Stuttgart (HLRS). The reports cover all fields of computational science and engineering ranging from CFD to computational physics and from chemistry to computer science with a special emphasis on industrially relevant applications. Presenting findings of one of Europe’s leading systems, this volume covers a wide variety of applications that deliver a high level of sustained performance. The book covers the main methods in high-performance computing. Its outstanding results in achieving the best performance for production codes are of particular interest for both scientists and   engineers. The book comes with a wealth of color illustrations and tables of results.  

Department of Energy research in utilization of high-performance computers

International Nuclear Information System (INIS)

Buzbee, B.L.; Worlton, W.J.; Michael, G.; Rodrigue, G.

1980-08-01

Department of Energy (DOE) and other Government research laboratories depend on high-performance computer systems to accomplish their programmatic goals. As the most powerful computer systems become available, they are acquired by these laboratories so that advances can be made in their disciplines. These advances are often the result of added sophistication to numerical models, the execution of which is made possible by high-performance computer systems. However, high-performance computer systems have become increasingly complex, and consequently it has become increasingly difficult to realize their potential performance. The result is a need for research on issues related to the utilization of these systems. This report gives a brief description of high-performance computers, and then addresses the use of and future needs for high-performance computers within DOE, the growing complexity of applications within DOE, and areas of high-performance computer systems warranting research. 1 figure

Mechanical Properties of High Performance Cementitious Grout (II)

DEFF Research Database (Denmark)

Sørensen, Eigil V.

The present report is an update of the report “Mechanical Properties of High Performance Cementitious Grout (I)” [1] and describes tests carried out on the high performance grout MASTERFLOW 9500, marked “WMG 7145 FP”, developed by BASF Construction Chemicals A/S and designed for use in grouted...

A Linux Workstation for High Performance Graphics

Science.gov (United States)

Geist, Robert; Westall, James

2000-01-01

The primary goal of this effort was to provide a low-cost method of obtaining high-performance 3-D graphics using an industry standard library (OpenGL) on PC class computers. Previously, users interested in doing substantial visualization or graphical manipulation were constrained to using specialized, custom hardware most often found in computers from Silicon Graphics (SGI). We provided an alternative to expensive SGI hardware by taking advantage of third-party, 3-D graphics accelerators that have now become available at very affordable prices. To make use of this hardware our goal was to provide a free, redistributable, and fully-compatible OpenGL work-alike library so that existing bodies of code could simply be recompiled. for PC class machines running a free version of Unix. This should allow substantial cost savings while greatly expanding the population of people with access to a serious graphics development and viewing environment. This should offer a means for NASA to provide a spectrum of graphics performance to its scientists, supplying high-end specialized SGI hardware for high-performance visualization while fulfilling the requirements of medium and lower performance applications with generic, off-the-shelf components and still maintaining compatibility between the two.

Strategies and Experiences Using High Performance Fortran

National Research Council Canada - National Science Library

Shires, Dale

2001-01-01

.... High performance Fortran (HPF) is a relative new addition to the Fortran dialect It is an attempt to provide an efficient high-level Fortran parallel programming language for the latest generation of been debatable...

General distributed control system for fusion experiments

International Nuclear Information System (INIS)

Klingner, P.L.; Levings, S.J.; Wilkins, R.W.

1986-01-01

A general control system using distributed LSI-11 microprocessors is being developed. Common software residues in each LSI-11 and is tailored to an application by control specifications downloaded from a host computer. The microprocessors, their control interfaces, and the micro-to-host communications are CAMAC based. The host computer also supports an operator interface, coordination of multiple microprocessors, and utilities to create and maintain the control specifications. Typical applications include monitoring safety interlocks as well as controlling vacuum systems, high voltage charging systems, and diagnostics

High performance anode for advanced Li batteries

Energy Technology Data Exchange (ETDEWEB)

Lake, Carla [Applied Sciences, Inc., Cedarville, OH (United States)

2015-11-02

The overall objective of this Phase I SBIR effort was to advance the manufacturing technology for ASI’s Si-CNF high-performance anode by creating a framework for large volume production and utilization of low-cost Si-coated carbon nanofibers (Si-CNF) for the battery industry. This project explores the use of nano-structured silicon which is deposited on a nano-scale carbon filament to achieve the benefits of high cycle life and high charge capacity without the consequent fading of, or failure in the capacity resulting from stress-induced fracturing of the Si particles and de-coupling from the electrode. ASI’s patented coating process distinguishes itself from others, in that it is highly reproducible, readily scalable and results in a Si-CNF composite structure containing 25-30% silicon, with a compositionally graded interface at the Si-CNF interface that significantly improve cycling stability and enhances adhesion of silicon to the carbon fiber support. In Phase I, the team demonstrated the production of the Si-CNF anode material can successfully be transitioned from a static bench-scale reactor into a fluidized bed reactor. In addition, ASI made significant progress in the development of low cost, quick testing methods which can be performed on silicon coated CNFs as a means of quality control. To date, weight change, density, and cycling performance were the key metrics used to validate the high performance anode material. Under this effort, ASI made strides to establish a quality control protocol for the large volume production of Si-CNFs and has identified several key technical thrusts for future work. Using the results of this Phase I effort as a foundation, ASI has defined a path forward to commercialize and deliver high volume and low-cost production of SI-CNF material for anodes in Li-ion batteries.

Evaluation of high-performance computing software

Energy Technology Data Exchange (ETDEWEB)

Browne, S.; Dongarra, J. [Univ. of Tennessee, Knoxville, TN (United States); Rowan, T. [Oak Ridge National Lab., TN (United States)

1996-12-31

The absence of unbiased and up to date comparative evaluations of high-performance computing software complicates a user`s search for the appropriate software package. The National HPCC Software Exchange (NHSE) is attacking this problem using an approach that includes independent evaluations of software, incorporation of author and user feedback into the evaluations, and Web access to the evaluations. We are applying this approach to the Parallel Tools Library (PTLIB), a new software repository for parallel systems software and tools, and HPC-Netlib, a high performance branch of the Netlib mathematical software repository. Updating the evaluations with feed-back and making it available via the Web helps ensure accuracy and timeliness, and using independent reviewers produces unbiased comparative evaluations difficult to find elsewhere.

High Performance Proactive Digital Forensics

International Nuclear Information System (INIS)

Alharbi, Soltan; Traore, Issa; Moa, Belaid; Weber-Jahnke, Jens

2012-01-01

With the increase in the number of digital crimes and in their sophistication, High Performance Computing (HPC) is becoming a must in Digital Forensics (DF). According to the FBI annual report, the size of data processed during the 2010 fiscal year reached 3,086 TB (compared to 2,334 TB in 2009) and the number of agencies that requested Regional Computer Forensics Laboratory assistance increasing from 689 in 2009 to 722 in 2010. Since most investigation tools are both I/O and CPU bound, the next-generation DF tools are required to be distributed and offer HPC capabilities. The need for HPC is even more evident in investigating crimes on clouds or when proactive DF analysis and on-site investigation, requiring semi-real time processing, are performed. Although overcoming the performance challenge is a major goal in DF, as far as we know, there is almost no research on HPC-DF except for few papers. As such, in this work, we extend our work on the need of a proactive system and present a high performance automated proactive digital forensic system. The most expensive phase of the system, namely proactive analysis and detection, uses a parallel extension of the iterative z algorithm. It also implements new parallel information-based outlier detection algorithms to proactively and forensically handle suspicious activities. To analyse a large number of targets and events and continuously do so (to capture the dynamics of the system), we rely on a multi-resolution approach to explore the digital forensic space. Data set from the Honeynet Forensic Challenge in 2001 is used to evaluate the system from DF and HPC perspectives.

Sex Differences in Mathematics Performance among Senior High ...

African Journals Online (AJOL)

This study explored sex differences in mathematics performance of students in the final year of high school and changes in these differences over a 3-year period in Ghana. A convenience sample of 182 students, 109 boys and 72 girls in three high schools in Ghana was used. Mathematics performance was assessed using ...

Real-time monitoring of Hanford nuclear waste

International Nuclear Information System (INIS)

McNeece, S.G.; Glasscock, J.A.; Rosnick, C.K.

1979-10-01

Two minicomputers are used to perform real time monitoring of radioactive waste storage tanks on the Hanford Nuclear Reservation. The Computer Automated Surveillance System, CASS, consists of a network of six field microprocessors, a central microprocessor and two central Eclipse minicomputers. The field microprocessors are each responsible for monitoring alarm sensors, liquid levels and temperatures. The field microprocessors report alarm conditions immediately to the central microprocessor. The central minicomputer reports all alarm conditions to the user terminals, requests data from the field on a scheduled and requested basis, and generates reports. It handles all requests for information from the user and stores all incoming data for historical purposes. The CASS software consists of five major segments: (1) process creation, (2) report generation, (3) file updating, (4) terminal communication, and (5) microprocessor communication. Since CASS must operate 24 hours a day, 7 days a week, the system cannot be allowed to abnormally terminate. For this reason all processes are started by the creation process. Having a single process responsible for creating all other processes provides the ability to detect a failure of a subordinate process and to automatically restart the failed process. The report generation process schedules reports, requests the data to be gathered to produce the reports, forms the reports, and distributes the reports to the user terminals. The file updating process handles all data file modifications. There is a terminal communication process for each user terminal which is responsible for printing scheduled reports and for allowing the user to request information from the CASS system. The microprocessor communication process handles all communication with the central microprocessor

Embedded High Performance Scalable Computing Systems

National Research Council Canada - National Science Library

Ngo, David

2003-01-01

The Embedded High Performance Scalable Computing Systems (EHPSCS) program is a cooperative agreement between Sanders, A Lockheed Martin Company and DARPA that ran for three years, from Apr 1995 - Apr 1998...

High-performance vertical organic transistors.

Science.gov (United States)

Kleemann, Hans; Günther, Alrun A; Leo, Karl; Lüssem, Björn

2013-11-11

Vertical organic thin-film transistors (VOTFTs) are promising devices to overcome the transconductance and cut-off frequency restrictions of horizontal organic thin-film transistors. The basic physical mechanisms of VOTFT operation, however, are not well understood and VOTFTs often require complex patterning techniques using self-assembly processes which impedes a future large-area production. In this contribution, high-performance vertical organic transistors comprising pentacene for p-type operation and C60 for n-type operation are presented. The static current-voltage behavior as well as the fundamental scaling laws of such transistors are studied, disclosing a remarkable transistor operation with a behavior limited by injection of charge carriers. The transistors are manufactured by photolithography, in contrast to other VOTFT concepts using self-assembled source electrodes. Fluorinated photoresist and solvent compounds allow for photolithographical patterning directly and strongly onto the organic materials, simplifying the fabrication protocol and making VOTFTs a prospective candidate for future high-performance applications of organic transistors. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach

DEFF Research Database (Denmark)

Schoeberl, Martin; Schleuniger, Pascal; Puffitsch, Wolfgang

2011-01-01

for low WCET bounds rather than high average case performance. Patmos is a dualissue, statically scheduled RISC processor. The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. To fill the dual-issue pipeline...

High-performance non-volatile organic ferroelectric memory on banknotes

KAUST Repository

Khan, Yasser; Bhansali, Unnat Sampatraj; Alshareef, Husam N.

2012-01-01

High-performance non-volatile polymer ferroelectric memory are fabricated on banknotes using poly(vinylidene fluoride trifluoroethylene). The devices show excellent performance with high remnant polarization, low operating voltages, low leakage

Device for detecting imminent failure of high-dielectric stress capacitors. [Patent application

Science.gov (United States)

McDuff, G.G.

1980-11-05

A device is described for detecting imminent failure of a high-dielectric stress capacitor utilizing circuitry for detecting pulse width variations and pulse magnitude variations. Inexpensive microprocessor circuitry is utilized to make numerical calculations of digital data supplied by detection circuitry for comparison of pulse width data and magnitude data to determine if preselected ranges have been exceeded, thereby indicating imminent failure of a capacitor. Detection circuitry may be incorporated in transmission lines, pulse power circuitry, including laser pulse circuitry or any circuitry where capacitors or capacitor banks are utilized.

Design and operation of the LAMPF Auxiliary Controller. High-speed remote processing on the CAMAC dataway

International Nuclear Information System (INIS)

Machen, D.R.

1979-02-01

A CAMAC Auxiliary Controller has been developed to further the concepts of distributed processing in both process control and experiment data-acquisition systems. The Auxiliary Controller is built around a commercially available 16-bit microcomputer and a high-speed bit-sliced microprocessor capable of instruction execution times of 140 ns. The modular nature of the controller allows the user to tailor the controller capabilities to the system problem, while maintaining the interface techniques of the CAMAC Standard

High-performance non-volatile organic ferroelectric memory on banknotes

KAUST Repository

Khan, Yasser

2012-03-21

High-performance non-volatile polymer ferroelectric memory are fabricated on banknotes using poly(vinylidene fluoride trifluoroethylene). The devices show excellent performance with high remnant polarization, low operating voltages, low leakage, high mobility, and long retention times. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High-performance non-volatile organic ferroelectric memory on banknotes.

Science.gov (United States)

Khan, M A; Bhansali, Unnat S; Alshareef, H N

2012-04-24

High-performance non-volatile polymer ferroelectric memory are fabricated on banknotes using poly(vinylidene fluoride trifluoroethylene). The devices show excellent performance with high remnant polarization, low operating voltages, low leakage, high mobility, and long retention times. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

THE RELATION OF HIGH-PERFORMANCE WORK SYSTEMS WITH EMPLOYEE INVOLVEMENT

Directory of Open Access Journals (Sweden)

Bilal AFSAR

2010-01-01

Full Text Available The basic aim of high performance work systems is to enable employees to exercise decision making, leading to flexibility, innovation, improvement and skill sharing. By facilitating the development of high performance work systems we help organizations make continuous improvement a way of life.The notion of a high-performance work system (HPWS constitutes a claim that there exists a system of work practices for core workers in an organisation that leads in some way to superior performance. This article will discuss the relation that HPWS has with the improvement of firms’ performance and high involvement of the employees.

Contemporary high performance computing from petascale toward exascale

CERN Document Server

Vetter, Jeffrey S

2013-01-01

Contemporary High Performance Computing: From Petascale toward Exascale focuses on the ecosystems surrounding the world's leading centers for high performance computing (HPC). It covers many of the important factors involved in each ecosystem: computer architectures, software, applications, facilities, and sponsors. The first part of the book examines significant trends in HPC systems, including computer architectures, applications, performance, and software. It discusses the growth from terascale to petascale computing and the influence of the TOP500 and Green500 lists. The second part of the

Pengaruh High Performance Work Practice (Hpwp) Terhadap Job Performance Pada Frontliner Bank

OpenAIRE

Ihdaryanti, Monica Amani; Panggabean, Mutiara S

2014-01-01

Generally High Performance Work Practice (HPWP) is a part of management human resources. The objectives of this research are getting and analyzing the effect of HPWPs with Job Satisfaction; HPWPs with Organizational Commitment; Job Satisfaction with Organizational Commitment; Job Satisfaction with Job Performance; and Organizational Commitment with Job Performance. The total of sample in this research is 100 respondents which are as Front liner BNI and Mandiri. The result of th...

High performance liquid chromatographic determination of ...

African Journals Online (AJOL)

STORAGESEVER

2010-02-08

) high performance liquid chromatography (HPLC) grade .... applications. These are important requirements if the reagent is to be applicable to on-line pre or post column derivatisation in a possible automation of the analytical.

Single event effects and performance predictions for space applications of RISC processors

International Nuclear Information System (INIS)

Kimbrough, J.R.; Colella, N.J.; Denton, S.M.; Shaeffer, D.L.; Shih, D.; Wilburn, J.W.; Coakley, P.G.; Casteneda, C.; Koga, R.; Clark, D.A.; Ullmann, J.L.

1994-01-01

Proton and ion Single Event Phenomena (SEP) tests were performed on 32-b processors including R3000A's from all commercial manufacturers along with the Performance PR3400 family, Integrated Device Technology Inc. 79R3081, LSI Logic Corporation LR33000HC, and Intel i80960MX parts. The microprocessors had acceptable upset rates for operation in a low earth orbit or a lunar mission such as CLEMENTINE with a wide range in proton total dose failure. Even though R3000A devices are 60% smaller in physical area than R3000 devices, there was a 340% increase in device Single Event Upset (SEU) cross section. Software tests of varying complexity demonstrate that registers and other functional blocks using register architecture dominate the cross section. The current approach of giving a single upset cross section can lead to erroneous upset rates depending on the application software

Can Knowledge of the Characteristics of "High Performers" Be Generalised?

Science.gov (United States)

McKenna, Stephen

2002-01-01

Two managers described as high performing constructed complexity maps of their organization/world. The maps suggested that high performance is socially constructed and negotiated in specific contexts and management competencies associated with it are context specific. Development of high performers thus requires personalized coaching more than…

Comparing Dutch and British high performing managers

NARCIS (Netherlands)

Waal, A.A. de; Heijden, B.I.J.M. van der; Selvarajah, C.; Meyer, D.

2016-01-01

National cultures have a strong influence on the performance of organizations and should be taken into account when studying the traits of high performing managers. At the same time, many studies that focus upon the attributes of successful managers show that there are attributes that are similar

Performance evaluation of the multidetector gamma counter Multigamma 1260

International Nuclear Information System (INIS)

Dolezal, L.; Fingerova, H.; Husak, V.; Erban, J.

1981-01-01

Clinical trials were carried out in co-operation with the Nuclear Medicine Department of the Teaching Hospital, of MULTIGAMMA 1260 by LKB WALLAC, Finland, an instrument for gamma counting of samples in RIA. The experience is summed up gained with the operation of the instrument, a brief description is presented and a comparison is given with the NE 1612 multidetector instrument and a conventional automatic single-detector gamma counter by Searle which has been used for some time in routine operation. The major advantage of the instrument being tested is its high speed evaluation given by the simultaneous measurement of 12 samples and immediate processing of the results by a microprocessor unit. Concentration values are printed out immediately after the last point of the curve has been measured, calculated and plotted. The accuracy, efficiency and stability of measurement at this high speed remains comparable to conventional instruments. (author)

Micromagnetics on high-performance workstation and mobile computational platforms

Science.gov (United States)

Fu, S.; Chang, R.; Couture, S.; Menarini, M.; Escobar, M. A.; Kuteifan, M.; Lubarda, M.; Gabay, D.; Lomakin, V.

2015-05-01

The feasibility of using high-performance desktop and embedded mobile computational platforms is presented, including multi-core Intel central processing unit, Nvidia desktop graphics processing units, and Nvidia Jetson TK1 Platform. FastMag finite element method-based micromagnetic simulator is used as a testbed, showing high efficiency on all the platforms. Optimization aspects of improving the performance of the mobile systems are discussed. The high performance, low cost, low power consumption, and rapid performance increase of the embedded mobile systems make them a promising candidate for micromagnetic simulations. Such architectures can be used as standalone systems or can be built as low-power computing clusters.

High performance light water reactor

International Nuclear Information System (INIS)

Squarer, D.; Schulenberg, T.; Struwe, D.; Oka, Y.; Bittermann, D.; Aksan, N.; Maraczy, C.; Kyrki-Rajamaeki, R.; Souyri, A.; Dumaz, P.

2003-01-01

The objective of the high performance light water reactor (HPLWR) project is to assess the merit and economic feasibility of a high efficiency LWR operating at thermodynamically supercritical regime. An efficiency of approximately 44% is expected. To accomplish this objective, a highly qualified team of European research institutes and industrial partners together with the University of Tokyo is assessing the major issues pertaining to a new reactor concept, under the co-sponsorship of the European Commission. The assessment has emphasized the recent advancement achieved in this area by Japan. Additionally, it accounts for advanced European reactor design requirements, recent improvements, practical design aspects, availability of plant components and the availability of high temperature materials. The final objective of this project is to reach a conclusion on the potential of the HPLWR to help sustain the nuclear option, by supplying competitively priced electricity, as well as to continue the nuclear competence in LWR technology. The following is a brief summary of the main project achievements:-A state-of-the-art review of supercritical water-cooled reactors has been performed for the HPLWR project.-Extensive studies have been performed in the last 10 years by the University of Tokyo. Therefore, a 'reference design', developed by the University of Tokyo, was selected in order to assess the available technological tools (i.e. computer codes, analyses, advanced materials, water chemistry, etc.). Design data and results of the analysis were supplied by the University of Tokyo. A benchmark problem, based on the 'reference design' was defined for neutronics calculations and several partners of the HPLWR project carried out independent analyses. The results of these analyses, which in addition help to 'calibrate' the codes, have guided the assessment of the core and the design of an improved HPLWR fuel assembly. Preliminary selection was made for the HPLWR scale

Strategy Guideline. High Performance Residential Lighting

Energy Technology Data Exchange (ETDEWEB)

Holton, J. [IBACOS, Inc., Pittsburgh, PA (United States)

2012-02-01

This report has been developed to provide a tool for the understanding and application of high performance lighting in the home. The strategies featured in this guide are drawn from recent advances in commercial lighting for application to typical spaces found in residential buildings. This guide offers strategies to greatly reduce lighting energy use through the application of high quality fluorescent and light emitting diode (LED) technologies. It is important to note that these strategies not only save energy in the home but also serve to satisfy the homeowner’s expectations for high quality lighting.

Mass storage for microprocessor farms

International Nuclear Information System (INIS)

Areti, H.

1990-01-01

Experiments in high energy physics require high density and high speed mass storage. Mass storage is needed for data logging during the online data acquisition, data retrieval and storage during the event reconstruction and data manipulation during the physics analysis. This paper examines the storage and speed requirements at the first two stages of the experiments and suggests a possible starting point to deal with the problem. 3 refs., 3 figs

Improving UV Resistance of High Performance Fibers

Science.gov (United States)

Hassanin, Ahmed

High performance fibers are characterized by their superior properties compared to the traditional textile fibers. High strength fibers have high modules, high strength to weight ratio, high chemical resistance, and usually high temperature resistance. It is used in application where superior properties are needed such as bulletproof vests, ropes and cables, cut resistant products, load tendons for giant scientific balloons, fishing rods, tennis racket strings, parachute cords, adhesives and sealants, protective apparel and tire cords. Unfortunately, Ultraviolet (UV) radiation causes serious degradation to the most of high performance fibers. UV lights, either natural or artificial, cause organic compounds to decompose and degrade, because the energy of the photons of UV light is high enough to break chemical bonds causing chain scission. This work is aiming at achieving maximum protection of high performance fibers using sheathing approaches. The sheaths proposed are of lightweight to maintain the advantage of the high performance fiber that is the high strength to weight ratio. This study involves developing three different types of sheathing. The product of interest that need be protected from UV is braid from PBO. First approach is extruding a sheath from Low Density Polyethylene (LDPE) loaded with different rutile TiO2 % nanoparticles around the braid from the PBO. The results of this approach showed that LDPE sheath loaded with 10% TiO2 by weight achieved the highest protection compare to 0% and 5% TiO2. The protection here is judged by strength loss of PBO. This trend noticed in different weathering environments, where the sheathed samples were exposed to UV-VIS radiations in different weatheromter equipments as well as exposure to high altitude environment using NASA BRDL balloon. The second approach is focusing in developing a protective porous membrane from polyurethane loaded with rutile TiO2 nanoparticles. Membrane from polyurethane loaded with 4