Establishment of design space for high current gain in III-N hot electron transistors

Science.gov (United States)

Gupta, Geetak; Ahmadi, Elaheh; Suntrup, Donald J., III; Mishra, Umesh K.

2018-01-01

This paper establishes the design space of III-N hot electron transistors (HETs) for high current gain by designing and fabricating HETs with scaled base thickness. The device structure consists of GaN-based emitter, base and collector regions where emitter and collector barriers are implemented using AlN and InGaN layers, respectively, as polarization-dipoles. Electrons tunnel through the AlN layer to be injected into the base at a high energy where they travel in a quasi-ballistic manner before being collected. Current gain increases from 1 to 3.5 when base thickness is reduced from 7 to 4 nm. The extracted mean free path (λ mfp) is 5.8 nm at estimated injection energy of 1.5 eV.

Investigation of surface related leakage current in AlGaN/GaN High Electron Mobility Transistors

Energy Technology Data Exchange (ETDEWEB)

Kaushik, J.K., E-mail: janeshkaushik@sspl.drdo.in [Solid State Physics Laboratory, Delhi 110054 (India); Balakrishnan, V.R.; Mongia, D.; Kumar, U.; Dayal, S. [Solid State Physics Laboratory, Delhi 110054 (India); Panwar, B.S. [Indian Institute of Technology Delhi, Hauz Khas, New Delhi 110016 (India); Muralidharan, R. [Indian Institute of Science, Bengaluru, Karnataka 560012 (India)

2016-08-01

This paper reports the study of surface-related mechanisms to explain the high reverse leakage current observed in the in-house fabricated Si{sub 3}N{sub 4} passivated AlGaN/GaN High Electron Mobility Transistors. We propose that the Si{sub 3}N{sub 4}/AlGaN interface in the un-gated regions provides an additional leakage path between the gate and source/drain and may constitute a large component of reverse current. This surface related leakage component of current exhibits both temperature and electric field dependence and its Arrhenius behavior has been experimentally verified using Conductance Deep Level Transient Spectroscopy and temperature dependent reverse leakage current measurements. A thin interfacial amorphous semiconductor layer formed due to inter diffusion at Si{sub 3}N{sub 4}/AlGaN interface has been presumed as the source for this surface related leakage. We, therefore, conclude that optimum Si{sub 3}N{sub 4} deposition conditions and careful surface preparation prior to passivation can limit the extent of surface leakage and can thus vastly improve the device performance. - Highlights: • Enhanced leakage in AlGaN/GaN High Electron Mobility Transistors after passivation • Experimental evidence of the presence of extrinsic traps at Si{sub 3}N{sub 4}/AlGaN interface • Electron hopping in shallower extended defects and band tail traps at the interface. • Reduction in current collapse due to the virtual gate inhibition by this conduction • However, limitation on the operating voltages due to decrease in breakdown voltage.

Oscillation of Critical Current by Gate Voltage in Cooper Pair Transistor

International Nuclear Information System (INIS)

Kim, N.; Cheong, Y.; Song, W.

2010-01-01

We measured the critical current of a Cooper pair transistor consisting of two Josephson junctions and a gate electrode. The Cooper pair transistors were fabricated by using electron-beam lithography and double-angle evaporation technique. The Gate voltage dependence of critical current was measured by observing voltage jumps at various gate voltages while sweeping bias current. The observed oscillation was 2e-periodic, which shows the Cooper pair transistor had low level of quasiparticle poisoning.

Demonstration of high current carbon nanotube enabled vertical organic field effect transistors at industrially relevant voltages

Science.gov (United States)

McCarthy, Mitchell

The display market is presently dominated by the active matrix liquid crystal display (LCD). However, the active matrix organic light emitting diode (AMOLED) display is argued to become the successor to the LCD, and is already beginning its way into the market, mainly in small size displays. But, for AMOLED technology to become comparable in market share to LCD, larger size displays must become available at a competitive price with their LCD counterparts. A major issue preventing low-cost large AMOLED displays is the thin-film transistor (TFT) technology. Unlike the voltage driven LCD, the OLEDs in the AMOLED display are current driven. Because of this, the mature amorphous silicon TFT backplane technology used in the LCD must be upgraded to a material possessing a higher mobility. Polycrystalline silicon and transparent oxide TFT technologies are being considered to fill this need. But these technologies bring with them significant manufacturing complexity and cost concerns. Carbon nanotube enabled vertical organic field effect transistors (CN-VFETs) offer a unique solution to this problem (now known as the AMOLED backplane problem). The CN-VFET allows the use of organic semiconductors to be used for the semiconductor layer. Organics are known for their low-cost large area processing compatibility. Although the mobility of the best organics is only comparable to that of amorphous silicon, the CN-VFET makes up for this by orienting the channel vertically, as opposed to horizontally (like in conventional TFTs). This allows the CN-VFET to achieve sub-micron channel lengths without expensive high resolution patterning. Additionally, because the CN-VFET can be easily converted into a light emitting transistor (called the carbon nanotube enabled vertical organic light emitting transistor---CN-VOLET) by essentially stacking an OLED on top of the CN-VFET, more potential benefits can be realized. These potential benefits include, increased aperture ratio, increased OLED

Parametrization of the radiation induced leakage current increase of NMOS transistors

CERN Document Server

Backhaus, Malte

2017-01-13

The increase of the leakage current of NMOS transistors during exposure to ionizing radiation is known and well studied. Radiation hardness by design techniques have been developed to mitigate this effect and have been successfully used. More recent developments in smaller feature size technologies do not make use of these techniques due to their drawbacks in terms of logic density and requirement of dedicated libraries. During operation the resulting increase of the supply current is a serious challenge and needs to be considered during the system design. A simple parametrization of the leakage current of NMOS transistors as a function of total ionizing dose is presented. The parametrization uses a transistor transfer characteristics of the parasitic transistor along the shallow trench isolation to describe the leakage current of the nominal transistor. Together with a parametrization of the number of positive charges trapped in the silicon dioxide and number of activated interface traps in the silicon to si...

Investigation of effective base transit time and current gain modulation of light-emitting transistors under different ambient temperatures

Energy Technology Data Exchange (ETDEWEB)

Yang, Hao-Hsiang; Tu, Wen-Chung; Wang, Hsiao-Lun [Graduate Institute of Photonics and Optoelectronics, National Taiwan University, 1, Roosevelt Road, Sec. 4, Taipei 106, Taiwan (China); Wu, Chao-Hsin, E-mail: chaohsinwu@ntu.edu.tw [Graduate Institute of Photonics and Optoelectronics, National Taiwan University, 1, Roosevelt Road, Sec. 4, Taipei 106, Taiwan (China); Graduate Institute of Electronics Engineering, National Taiwan University, 1, Roosevelt Road, Sec. 4, Taipei106, Taiwan (China)

2014-11-03

In this report, the modulation of current gain of InGaP/GaAs light-emitting transistors under different ambient temperatures are measured and analyzed using thermionic emission model of quantum well embedded in the transistor base region. Minority carriers captured by quantum wells gain more energy at high temperatures and escape from quantum wells resulting in an increase of current gain and lower optical output, resulting in different I-V characteristics from conventional heterojunction bipolar transistors. The effect of the smaller thermionic lifetime thus reduces the effective base transit time of transistors at high temperatures. The unique current gain enhancement of 27.61% is achieved when operation temperature increase from 28 to 85 °C.

Temperature dependence of the current in Schottky-barrier source-gated transistors

Science.gov (United States)

Sporea, R. A.; Overy, M.; Shannon, J. M.; Silva, S. R. P.

2015-05-01

The temperature dependence of the drain current is an important parameter in thin-film transistors. In this paper, we propose that in source-gated transistors (SGTs), this temperature dependence can be controlled and tuned by varying the length of the source electrode. SGTs comprise a reverse biased potential barrier at the source which controls the current. As a result, a large activation energy for the drain current may be present which, although useful in specific temperature sensing applications, is in general deleterious in many circuit functions. With support from numerical simulations with Silvaco Atlas, we describe how increasing the length of the source electrode can be used to reduce the activation energy of SGT drain current, while maintaining the defining characteristics of SGTs: low saturation voltage, high output impedance in saturation, and tolerance to geometry variations. In this study, we apply the dual current injection modes to obtain drain currents with high and low activation energies and propose mechanisms for their exploitation in future large-area integrated circuit designs.

High-mobility pyrene-based semiconductor for organic thin-film transistors.

Science.gov (United States)

Cho, Hyunduck; Lee, Sunyoung; Cho, Nam Sung; Jabbour, Ghassan E; Kwak, Jeonghun; Hwang, Do-Hoon; Lee, Changhee

2013-05-01

Numerous conjugated oligoacenes and polythiophenes are being heavily studied in the search for high-mobility organic semiconductors. Although many researchers have designed fused aromatic compounds as organic semiconductors for organic thin-film transistors (OTFTs), pyrene-based organic semiconductors with high mobilities and on-off current ratios have not yet been reported. Here, we introduce a new pyrene-based p-type organic semiconductor showing liquid crystal behavior. The thin film characteristics of this material are investigated by varying the substrate temperature during the deposition and the gate dielectric condition using the surface modification with a self-assembled monolayer, and systematically studied in correlation with the performances of transistor devices with this compound. OTFT fabricated under the optimum deposition conditions of this compound, namely, 1,6-bis(5'-octyl-2,2'-bithiophen-5-yl)pyrene (BOBTP) shows a high-performance transistor behavior with a field-effect mobility of 2.1 cm(2) V(-1) s(-1) and an on-off current ratio of 7.6 × 10(6) and enhanced long-term stability compared to the pentacene thin-film transistor.

A High-Voltage Level Tolerant Transistor Circuit

NARCIS (Netherlands)

Annema, Anne J.; Geelen, Godefridus Johannes Gertrudis Maria

2001-01-01

A high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor (T1) operatively connected to a high-voltage level node (3) and a second transistor (T2) operatively connected to a low-voltage level node (2). The first transistor (T1)

A III-V nanowire channel on silicon for high-performance vertical transistors.

Science.gov (United States)

Tomioka, Katsuhiro; Yoshimura, Masatoshi; Fukui, Takashi

2012-08-09

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

Study of surface leakage current of AlGaN/GaN high electron mobility transistors

International Nuclear Information System (INIS)

Chen, YongHe; Zhang, Kai; Cao, MengYi; Zhao, ShengLei; Zhang, JinCheng; Hao, Yue; Ma, XiaoHua

2014-01-01

Temperature-dependent surface current measurements were performed to analyze the mechanism of surface conductance of AlGaN/GaN channel high-electron-mobility transistors by utilizing process-optimized double gate structures. Different temperatures and electric field dependence have been found in surface current measurements. At low electric field, the mechanism of surface conductance is considered to be two-dimensional variable range hopping. At elevated electric field, the Frenkel–Poole trap assisted emission governs the main surface electrons transportation. The extracted energy barrier height of electrons emitting from trapped state near Fermi energy level into a threading dislocations-related continuum state is 0.38 eV. SiN passivation reduces the surface leakage current by two order of magnitude and nearly 4 orders of magnitude at low and high electric fields, respectively. SiN also suppresses the Frenkel–Poole conductance at high temperature by improving the surface states of AlGaN/GaN. A surface treatment process has been introduced to further suppress the surface leakage current at high temperature and high field, which results in a decrease in surface current of almost 3 orders of magnitude at 476 K

High-frequency self-aligned graphene transistors with transferred gate stacks

Science.gov (United States)

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-01-01

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra–high-frequency circuits. PMID:22753503

Controlling charge current through a DNA based molecular transistor

Energy Technology Data Exchange (ETDEWEB)

Behnia, S., E-mail: s.behnia@sci.uut.ac.ir; Fathizadeh, S.; Ziaei, J.

2017-01-05

Molecular electronics is complementary to silicon-based electronics and may induce electronic functions which are difficult to obtain with conventional technology. We have considered a DNA based molecular transistor and study its transport properties. The appropriate DNA sequence as a central chain in molecular transistor and the functional interval for applied voltages is obtained. I–V characteristic diagram shows the rectifier behavior as well as the negative differential resistance phenomenon of DNA transistor. We have observed the nearly periodic behavior in the current flowing through DNA. It is reported that there is a critical gate voltage for each applied bias which above it, the electrical current is always positive. - Highlights: • Modeling a DNA based molecular transistor and studying its transport properties. • Choosing the appropriate DNA sequence using the quantum chaos tools. • Choosing the functional interval for voltages via the inverse participation ratio tool. • Detecting the rectifier and negative differential resistance behavior of DNA.

Giant current fluctuations in an overheated single-electron transistor

Science.gov (United States)

Laakso, M. A.; Heikkilä, T. T.; Nazarov, Yuli V.

2010-11-01

Interplay of cotunneling and single-electron tunneling in a thermally isolated single-electron transistor leads to peculiar overheating effects. In particular, there is an interesting crossover interval where the competition between cotunneling and single-electron tunneling changes to the dominance of the latter. In this interval, the current exhibits anomalous sensitivity to the effective electron temperature of the transistor island and its fluctuations. We present a detailed study of the current and temperature fluctuations at this interesting point. The methods implemented allow for a complete characterization of the distribution of the fluctuating quantities, well beyond the Gaussian approximation. We reveal and explore the parameter range where, for sufficiently small transistor islands, the current fluctuations become gigantic. In this regime, the optimal value of the current, its expectation value, and its standard deviation differ from each other by parametrically large factors. This situation is unique for transport in nanostructures and for electron transport in general. The origin of this spectacular effect is the exponential sensitivity of the current to the fluctuating effective temperature.

Impact of doped boron concentration in emitter on high- and low-dose-rate damage in lateral PNP transistors

International Nuclear Information System (INIS)

Zheng Yuzhan; Lu Wu; Ren Diyuan; Wang Yiyuan; Wang Zhikuan; Yang Yonghui

2010-01-01

The characteristics of radiation damage under a high or low dose rate in lateral PNP transistors with a heavily or lightly doped emitter is investigated. Experimental results show that as the total dose increases, the base current of transistors would increase and the current gain decreases. Furthermore, more degradation has been found in lightly-doped PNP transistors, and an abnormal effect is observed in heavily doped transistors. The role of radiation defects, especially the double effects of oxide trapped charge, is discussed in heavily or lightly doped transistors. Finally, through comparison between the high- and low-dose-rate response of the collector current in heavily doped lateral PNP transistors, the abnormal effect can be attributed to the annealing of the oxide trapped charge. The response of the collector current, in heavily doped PNP transistors under high- and low-dose-rate irradiation is described in detail. (semiconductor integrated circuits)

High Stability Pentacene Transistors Using Polymeric Dielectric Surface Modifier.

Science.gov (United States)

Wang, Xiaohong; Lin, Guangqing; Li, Peng; Lv, Guoqiang; Qiu, Longzhen; Ding, Yunsheng

2015-08-01

1,6-bis(trichlorosilyl)hexane (C6Cl), polystyrene (PS), and cross-linked polystyrene (CPS) were investigated as gate dielectric modified layers for high performance organic transistors. The influence of the surface energy, roughness and morphology on the charge transport of the organic thin-film transistors (OTFTs) was investigated. The surface energy and roughness both affect the grain size of the pentacene films which will control the charge carrier mobility of the devices. Pentacene thin-film transistors fabricated on the CPS modified dielectric layers exhibited charge carrier mobility as high as 1.11 cm2 V-1 s-1. The bias stress stability for the CPS devices shows that the drain current only decays 1% after 1530 s and the mobility never decreases until 13530 s.

Comparison of Surface Passivation Films for Reduction of Current Collapse in AlGaN/GaN High Electron Mobility Transistors (HEMTs)

National Research Council Canada - National Science Library

Fitch, R

2002-01-01

Three different passivation layers (SiN(x), MgO, and Sc2O3) were examined for their effectiveness in mitigating surface-state-induced current collapse in AlGaN/GaN high electron mobility transistors (HEMTs...

Transistor reset preamplifier for high-rate high-resolution spectroscopy

International Nuclear Information System (INIS)

Landis, D.A.; Cork, C.P.; Madden, N.W.; Goulding, F.S.

1981-10-01

Pulsed transistor reset of high resolution charge sensitive preamplifiers used in cooled semiconductor spectrometers can sometimes have an advantage over pulsed light reset systems. Several versions of transistor reset spectrometers using both silicon and germanium detectors have been built. This paper discusses the advantages of the transistor reset system and illustrates several configurations of the packages used for the FET and reset transistor. It also describes the preamplifer circuit and shows the performance of the spectrometer at high rates

Nonlinear photoresponse of field effect transistors terahertz detectors at high irradiation intensities

International Nuclear Information System (INIS)

But, D. B.; Drexler, C.; Ganichev, S. D.; Sakhno, M. V.; Sizov, F. F.; Dyakonova, N.; Drachenko, O.; Gutin, A.; Knap, W.

2014-01-01

Terahertz power dependence of the photoresponse of field effect transistors, operating at frequencies from 0.1 to 3 THz for incident radiation power density up to 100 kW/cm 2 was studied for Si metal–oxide–semiconductor field-effect transistors and InGaAs high electron mobility transistors. The photoresponse increased linearly with increasing radiation intensity up to the kW/cm 2 range. Nonlinearity followed by saturation of the photoresponse was observed for all investigated field effect transistors for intensities above several kW/cm 2 . The observed photoresponse nonlinearity is explained by nonlinearity and saturation of the transistor channel current. A theoretical model of terahertz field effect transistor photoresponse at high intensity was developed. The model explains quantitative experimental data both in linear and nonlinear regions. Our results show that dynamic range of field effect transistors is very high and can extend over more than six orders of magnitudes of power densities (from ∼0.5 mW/cm 2 to ∼5 kW/cm 2 )

Research of the voltage and current stabilization processes by using the silicon field-effect transistor

International Nuclear Information System (INIS)

Karimov, A.V.; Yodgorova, D.M.; Kamanov, B.M.; Giyasova, F.A.; Yakudov, A.A.

2012-01-01

The silicon field-effect transistors were investigated to use in circuits for stabilization of current and voltage. As in gallium arsenide field-effect transistors, in silicon field-effect transistors with p-n-junction a new mechanism of saturation of the drain current is experimentally found out due to both transverse and longitudinal compression of channel by additional resistance between the source and the gate of the transistor. The criteria for evaluating the coefficients of stabilization of transient current suppressors and voltage stabilizator based on the field-effect transistor are considered. (authors)

Current-Induced Transistor Sensorics with Electrogenic Cells

Directory of Open Access Journals (Sweden)

Peter Fromherz

2016-04-01

Full Text Available The concepts of transistor recording of electroactive cells are considered, when the response is determined by a current-induced voltage in the electrolyte due to cellular activity. The relationship to traditional transistor recording, with an interface-induced response due to interactions with the open gate oxide, is addressed. For the geometry of a cell-substrate junction, the theory of a planar core-coat conductor is described with a one-compartment approximation. The fast electrical relaxation of the junction and the slow change of ion concentrations are pointed out. On that basis, various recording situations are considered and documented by experiments. For voltage-gated ion channels under voltage clamp, the effects of a changing extracellular ion concentration and the enhancement/depletion of ion conductances in the adherent membrane are addressed. Inhomogeneous ion conductances are crucial for transistor recording of neuronal action potentials. For a propagating action potential, the effects of an axon-substrate junction and the surrounding volume conductor are distinguished. Finally, a receptor-transistor-sensor is described, where the inhomogeneity of a ligand–activated ion conductance is achieved by diffusion of the agonist and inactivation of the conductance. Problems with regard to a development of reliable biosensors are mentioned.

High-voltage, high-current, solid-state closing switch

Science.gov (United States)

Focia, Ronald Jeffrey

2017-08-22

A high-voltage, high-current, solid-state closing switch uses a field-effect transistor (e.g., a MOSFET) to trigger a high-voltage stack of thyristors. The switch can have a high hold-off voltage, high current carrying capacity, and high time-rate-of-change of current, di/dt. The fast closing switch can be used in pulsed power applications.

High transconductance organic electrochemical transistors

Science.gov (United States)

Khodagholy, Dion; Rivnay, Jonathan; Sessolo, Michele; Gurfinkel, Moshe; Leleux, Pierre; Jimison, Leslie H.; Stavrinidou, Eleni; Herve, Thierry; Sanaur, Sébastien; Owens, Róisín M.; Malliaras, George G.

2013-07-01

The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications.

High transconductance organic electrochemical transistors

Science.gov (United States)

Khodagholy, Dion; Rivnay, Jonathan; Sessolo, Michele; Gurfinkel, Moshe; Leleux, Pierre; Jimison, Leslie H.; Stavrinidou, Eleni; Herve, Thierry; Sanaur, Sébastien; Owens, Róisín M.; Malliaras, George G.

2013-01-01

The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications. PMID:23851620

High-performance radio frequency transistors based on diameter-separated semiconducting carbon nanotubes

Energy Technology Data Exchange (ETDEWEB)

Cao, Yu; Che, Yuchi; Zhou, Chongwu, E-mail: chongwuz@usc.edu [Department of Electrical Engineering, University of Southern California, Los Angeles, California 90089 (United States); Seo, Jung-Woo T.; Hersam, Mark C. [Department of Materials Science and Engineering and Department of Chemistry, Northwestern University, Evanston, Illinois 60208 (United States); Gui, Hui [Department of Chemical Engineering and Materials Science, University of Southern California, Los Angeles, California 90089 (United States)

2016-06-06

In this paper, we report the high-performance radio-frequency transistors based on the single-walled semiconducting carbon nanotubes with a refined average diameter of ∼1.6 nm. These diameter-separated carbon nanotube transistors show excellent transconductance of 55 μS/μm and desirable drain current saturation with an output resistance of ∼100 KΩ μm. An exceptional radio-frequency performance is also achieved with current gain and power gain cut-off frequencies of 23 GHz and 20 GHz (extrinsic) and 65 GHz and 35 GHz (intrinsic), respectively. These radio-frequency metrics are among the highest reported for the carbon nanotube thin-film transistors. This study provides demonstration of radio frequency transistors based on carbon nanotubes with tailored diameter distributions, which will guide the future application of carbon nanotubes in radio-frequency electronics.

Investigation of defect-induced abnormal body current in fin field-effect-transistors

International Nuclear Information System (INIS)

Liu, Kuan-Ju; Tsai, Jyun-Yu; Lu, Ying-Hsin; Liu, Xi-Wen; Chang, Ting-Chang; Chen, Ching-En; Yang, Ren-Ya; Cheng, Osbert; Huang, Cheng-Tung

2015-01-01

This letter investigates the mechanism of abnormal body current at the linear region in n-channel high-k/metal gate stack fin field effect transistors. Unlike body current, which is generated by impact ionization at high drain voltages, abnormal body current was found to increase with decreasing drain voltages. Notably, the unusual body leakage only occurs in three-dimensional structure devices. Based on measurements under different operation conditions, the abnormal body current can be attributed to fin surface defect-induced leakage current, and the mechanism is electron tunneling to the fin via the defects, resulting in holes left at the body terminal

High-Performance Vertical Organic Electrochemical Transistors.

Science.gov (United States)

Donahue, Mary J; Williamson, Adam; Strakosas, Xenofon; Friedlein, Jacob T; McLeod, Robert R; Gleskova, Helena; Malliaras, George G

2018-02-01

Organic electrochemical transistors (OECTs) are promising transducers for biointerfacing due to their high transconductance, biocompatibility, and availability in a variety of form factors. Most OECTs reported to date, however, utilize rather large channels, limiting the transistor performance and resulting in a low transistor density. This is typically a consequence of limitations associated with traditional fabrication methods and with 2D substrates. Here, the fabrication and characterization of OECTs with vertically stacked contacts, which overcome these limitations, is reported. The resulting vertical transistors exhibit a reduced footprint, increased intrinsic transconductance of up to 57 mS, and a geometry-normalized transconductance of 814 S m -1 . The fabrication process is straightforward and compatible with sensitive organic materials, and allows exceptional control over the transistor channel length. This novel 3D fabrication method is particularly suited for applications where high density is needed, such as in implantable devices. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High mobility solution-processed hybrid light emitting transistors

International Nuclear Information System (INIS)

Walker, Bright; Kim, Jin Young; Ullah, Mujeeb; Burn, Paul L.; Namdas, Ebinazar B.; Chae, Gil Jo; Cho, Shinuk; Seo, Jung Hwa

2014-01-01

We report the design, fabrication, and characterization of high-performance, solution-processed hybrid (inorganic-organic) light emitting transistors (HLETs). The devices employ a high-mobility, solution-processed cadmium sulfide layer as the switching and transport layer, with a conjugated polymer Super Yellow as an emissive material in non-planar source/drain transistor geometry. We demonstrate HLETs with electron mobilities of up to 19.5 cm 2 /V s, current on/off ratios of >10 7 , and external quantum efficiency of 10 −2 % at 2100 cd/m 2 . These combined optical and electrical performance exceed those reported to date for HLETs. Furthermore, we provide full analysis of charge injection, charge transport, and recombination mechanism of the HLETs. The high brightness coupled with a high on/off ratio and low-cost solution processing makes this type of hybrid device attractive from a manufacturing perspective

Radio Frequency Transistors Using Aligned Semiconducting Carbon Nanotubes with Current-Gain Cutoff Frequency and Maximum Oscillation Frequency Simultaneously Greater than 70 GHz.

Science.gov (United States)

Cao, Yu; Brady, Gerald J; Gui, Hui; Rutherglen, Chris; Arnold, Michael S; Zhou, Chongwu

2016-07-26

In this paper, we report record radio frequency (RF) performance of carbon nanotube transistors based on combined use of a self-aligned T-shape gate structure, and well-aligned, high-semiconducting-purity, high-density polyfluorene-sorted semiconducting carbon nanotubes, which were deposited using dose-controlled, floating evaporative self-assembly method. These transistors show outstanding direct current (DC) performance with on-current density of 350 μA/μm, transconductance as high as 310 μS/μm, and superior current saturation with normalized output resistance greater than 100 kΩ·μm. These transistors create a record as carbon nanotube RF transistors that demonstrate both the current-gain cutoff frequency (ft) and the maximum oscillation frequency (fmax) greater than 70 GHz. Furthermore, these transistors exhibit good linearity performance with 1 dB gain compression point (P1dB) of 14 dBm and input third-order intercept point (IIP3) of 22 dBm. Our study advances state-of-the-art of carbon nanotube RF electronics, which have the potential to be made flexible and may find broad applications for signal amplification, wireless communication, and wearable/flexible electronics.

Suppression of tunneling leakage current in junctionless nanowire transistors

International Nuclear Information System (INIS)

Lou, Haijun; Li, Dan; Dong, Yan; Lin, Xinnan; He, Jin; Yang, Shengqi; Chan, Mansun

2013-01-01

In this paper, the characteristics of tunneling leakage current for the dual-material gate junctionless nanowire transistor (DMG-JNT) are investigated by three-dimensional numerical simulations and compared with conventional junctionless nanowire transistor (JNT). The suppression of the tunneling leakage current on the JNT by introducing an energy band step with the DMG structure is verified and presented for the first time. The effects of channel length on the DMG-JNT and the JNT are also studied. Results showed that the tunneling leakage current of the DMG-JNT is two orders smaller than that of the JNT, and further, the DMG-JNT exhibits superior scaling capability. Two key design parameters of the DMG-JNT, control gate ratio (Ra) and work function difference (δW), have been optimized and the optimal ranges of Ra and δW are pointed out. (paper)

Suppression of tunneling leakage current in junctionless nanowire transistors

Science.gov (United States)

Lou, Haijun; Li, Dan; Dong, Yan; Lin, Xinnan; He, Jin; Yang, Shengqi; Chan, Mansun

2013-12-01

In this paper, the characteristics of tunneling leakage current for the dual-material gate junctionless nanowire transistor (DMG-JNT) are investigated by three-dimensional numerical simulations and compared with conventional junctionless nanowire transistor (JNT). The suppression of the tunneling leakage current on the JNT by introducing an energy band step with the DMG structure is verified and presented for the first time. The effects of channel length on the DMG-JNT and the JNT are also studied. Results showed that the tunneling leakage current of the DMG-JNT is two orders smaller than that of the JNT, and further, the DMG-JNT exhibits superior scaling capability. Two key design parameters of the DMG-JNT, control gate ratio (Ra) and work function difference (δW), have been optimized and the optimal ranges of Ra and δW are pointed out.

High-current and low acceleration voltage arsenic ion implanted polysilicon-gate and source-drain electrode Si mos transistor

International Nuclear Information System (INIS)

Saito, Yasuyuki; Sugimura, Yoshiro; Sugihara, Michiyuki

1993-01-01

The fabrication process of high current arsenic (As) ion implanted polysilicon (Si) gate and source drain (SD) electrode Si n-channel metal oxide-semiconductor field effect transistor (MOSFET) was examined. Poly Si film n-type doping was performed by using high current (typical current: 2mA) and relatively low acceleration voltage (40keV) As ion implantation technique (Lintott series 3). It was observed that high dose As implanted poly Si films as is show refractoriness against radical fluorine excited by microwave. Using GCA MANN4800 (m/c ID No.2, resist: OFPR) mask pattern printing technique, the high current As ion implantation technique and radical fluorine gas phase etching (Chemical dry etching: CDE) technique, the n-channel Poly Si gate (ρs = ≅100Ω/□) enhancement MQSFETs(ρs source drain = ≅50Ω/□, SiO 2 gate=380 angstrom) with off-leak-less were obtained on 3 inch Czochralski grown 2Ωcm boron doped p type wafers (Osaka titanium). By the same process, a 8 bit single chip μ-processor with 26MHz full operation was performed

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

Science.gov (United States)

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

Silicon heterojunction transistor

International Nuclear Information System (INIS)

Matsushita, T.; Oh-uchi, N.; Hayashi, H.; Yamoto, H.

1979-01-01

SIPOS (Semi-insulating polycrystalline silicon) which is used as a surface passivation layer for highly reliable silicon devices constitutes a good heterojunction for silicon. P- or B-doped SIPOS has been used as the emitter material of a heterojunction transistor with the base and collector of silicon. An npn SIPOS-Si heterojunction transistor showing 50 times the current gain of an npn silicon homojunction transistor has been realized by high-temperature treatments in nitrogen and low-temperature annealing in hydrogen or forming gas

Few-layer SnSe{sub 2} transistors with high on/off ratios

Energy Technology Data Exchange (ETDEWEB)

Pei, Tengfei; Bao, Lihong, E-mail: lhbao@iphy.ac.cn; Wang, Guocai; Ma, Ruisong; Yang, Haifang; Li, Junjie; Gu, Changzhi; Du, Shixuan; Gao, Hong-jun [Institute of Physics, Chinese Academy of Sciences, P. O. Box 603, Beijing 100190 (China); Pantelides, Sokrates [Department of Physics and Astronomy, Vanderbilt University, Nashville, Tennessee 37235 (United States); Material Science and Technology Division, Oak Ridge National Laboratory, Oak Ridge, Tennessee 37381 (United States)

2016-02-01

We report few-layer SnSe{sub 2} field effect transistors (FETs) with high current on/off ratios. By trying different gate configurations, 300 nm SiO{sub 2} and 70 nm HfO{sub 2} as back gate only and 70 nm HfO{sub 2} as back gate combined with a top capping layer of polymer electrolyte, few-layer SnSe{sub 2} FET with a current on/off ratio of 10{sup 4} can be obtained. This provides a reliable solution for electrically modulating quasi-two-dimensional materials with high electron density (over 10{sup 13} cm{sup −2}) for field-effect transistor applications.

Investigation of the current collapse induced in InGaN back barrier AlGaN/GaN high electron mobility transistors

International Nuclear Information System (INIS)

Wan Xiaojia; Wang Xiaoliang; Xiao Hongling; Feng Chun; Jiang Lijuan; Qu Shenqi; Wang Zhanguo; Hou Xun

2013-01-01

Current collapses were studied, which were observed in AlGaN/GaN high electron mobility transistors (HEMTs) with and without InGaN back barrier (BB) as a result of short-term bias stress. More serious drain current collapses were observed in InGaN BB AlGaN/GaN HEMTs compared with the traditional HEMTs. The results indicate that the defects and surface states induced by the InGaN BB layer may enhance the current collapse. The surface states may be the primary mechanism of the origination of current collapse in AlGaN/GaN HEMTs for short-term direct current stress. (semiconductor devices)

Vertical organic transistors

International Nuclear Information System (INIS)

Lüssem, Björn; Günther, Alrun; Fischer, Axel; Kasemann, Daniel; Leo, Karl

2015-01-01

Organic switching devices such as field effect transistors (OFETs) are a key element of future flexible electronic devices. So far, however, a commercial breakthrough has not been achieved because these devices usually lack in switching speed (e.g. for logic applications) and current density (e.g. for display pixel driving). The limited performance is caused by a combination of comparatively low charge carrier mobilities and the large channel length caused by the need for low-cost structuring. Vertical Organic Transistors are a novel technology that has the potential to overcome these limitations of OFETs. Vertical Organic Transistors allow to scale the channel length of organic transistors into the 100 nm regime without cost intensive structuring techniques. Several different approaches have been proposed in literature, which show high output currents, low operation voltages, and comparatively high speed even without sub-μm structuring technologies. In this review, these different approaches are compared and recent progress is highlighted. (topical review)

Vertical organic transistors.

Science.gov (United States)

Lüssem, Björn; Günther, Alrun; Fischer, Axel; Kasemann, Daniel; Leo, Karl

2015-11-11

Organic switching devices such as field effect transistors (OFETs) are a key element of future flexible electronic devices. So far, however, a commercial breakthrough has not been achieved because these devices usually lack in switching speed (e.g. for logic applications) and current density (e.g. for display pixel driving). The limited performance is caused by a combination of comparatively low charge carrier mobilities and the large channel length caused by the need for low-cost structuring. Vertical Organic Transistors are a novel technology that has the potential to overcome these limitations of OFETs. Vertical Organic Transistors allow to scale the channel length of organic transistors into the 100 nm regime without cost intensive structuring techniques. Several different approaches have been proposed in literature, which show high output currents, low operation voltages, and comparatively high speed even without sub-μm structuring technologies. In this review, these different approaches are compared and recent progress is highlighted.

An Investigation of Carbon-Doping-Induced Current Collapse in GaN-on-Si High Electron Mobility Transistors

Directory of Open Access Journals (Sweden)

An-Jye Tzou

2016-06-01

Full Text Available This paper reports the successful fabrication of a GaN-on-Si high electron mobility transistor (HEMT with a 1702 V breakdown voltage (BV and low current collapse. The strain and threading dislocation density were well-controlled by 100 pairs of AlN/GaN superlattice buffer layers. Relative to the carbon-doped GaN spacer layer, we grew the AlGaN back barrier layer at a high temperature, resulting in a low carbon-doping concentration. The high-bandgap AlGaN provided an effective barrier for blocking leakage from the channel to substrate, leading to a BV comparable to the ordinary carbon-doped GaN HEMTs. In addition, the AlGaN back barrier showed a low dispersion of transiently pulsed ID under substrate bias, implying that the buffer traps were effectively suppressed. Therefore, we obtained a low-dynamic on-resistance with this AlGaN back barrier. These two approaches of high BV with low current collapse improved the device performance, yielding a device that is reliable in power device applications.

Highly Crumpled All-Carbon Transistors for Brain Activity Recording.

Science.gov (United States)

Yang, Long; Zhao, Yan; Xu, Wenjing; Shi, Enzheng; Wei, Wenjing; Li, Xinming; Cao, Anyuan; Cao, Yanping; Fang, Ying

2017-01-11

Neural probes based on graphene field-effect transistors have been demonstrated. Yet, the minimum detectable signal of graphene transistor-based probes is inversely proportional to the square root of the active graphene area. This fundamentally limits the scaling of graphene transistor-based neural probes for improved spatial resolution in brain activity recording. Here, we address this challenge using highly crumpled all-carbon transistors formed by compressing down to 16% of its initial area. All-carbon transistors, chemically synthesized by seamless integration of graphene channels and hybrid graphene/carbon nanotube electrodes, maintained structural integrity and stable electronic properties under large mechanical deformation, whereas stress-induced cracking and junction failure occurred in conventional graphene/metal transistors. Flexible, highly crumpled all-carbon transistors were further verified for in vivo recording of brain activity in rats. These results highlight the importance of advanced material and device design concepts to make improvements in neuroelectronics.

Analytical Model of Subthreshold Drain Current Characteristics of Ballistic Silicon Nanowire Transistors

Directory of Open Access Journals (Sweden)

Wanjie Xu

2015-01-01

Full Text Available A physically based subthreshold current model for silicon nanowire transistors working in the ballistic regime is developed. Based on the electric potential distribution obtained from a 2D Poisson equation and by performing some perturbation approximations for subband energy levels, an analytical model for the subthreshold drain current is obtained. The model is further used for predicting the subthreshold slopes and threshold voltages of the transistors. Our results agree well with TCAD simulation with different geometries and under different biasing conditions.

Polarization sensitive detection of 100 GHz radiation by high mobility field-effect transistors

International Nuclear Information System (INIS)

Sakowicz, M.; Lusakowski, J.; Karpierz, K.; Grynberg, M.; Knap, W.; Gwarek, W.

2008-01-01

Detection of 100 GHz electromagnetic radiation by a GaAs/AlGaAs high electron mobility field-effect transistor was investigated at 300 K as a function of the angle α between the direction of linear polarization of the radiation and the symmetry axis of the transistor. The angular dependence of the detected signal was found to be A 0 cos 2 (α-α 0 )+C with A 0 , α 0 , and C dependent on the electrical polarization of the transistor gate. This dependence is interpreted as due to excitation of two crossed phase-shifted oscillators. A response of the transistor chip (including bonding wires and the substrate) to 100 GHz radiation was numerically simulated. Results of calculations confirmed experimentally observed dependencies and showed that the two oscillators result from an interplay of 100 GHz currents defined by the transistor impedance together with bonding wires and substrate related modes

High mobility and quantum well transistors design and TCAD simulation

CERN Document Server

Hellings, Geert

2013-01-01

For many decades, the semiconductor industry has miniaturized transistors, delivering increased computing power to consumers at decreased cost. However, mere transistor downsizing does no longer provide the same improvements. One interesting option to further improve transistor characteristics is to use high mobility materials such as germanium and III-V materials. However, transistors have to be redesigned in order to fully benefit from these alternative materials. High Mobility and Quantum Well Transistors: Design and TCAD Simulation investigates planar bulk Germanium pFET technology in chapters 2-4, focusing on both the fabrication of such a technology and on the process and electrical TCAD simulation. Furthermore, this book shows that Quantum Well based transistors can leverage the benefits of these alternative materials, since they confine the charge carriers to the high-mobility material using a heterostructure. The design and fabrication of one particular transistor structure - the SiGe Implant-Free Qu...

Subthreshold Schottky-barrier thin-film transistors with ultralow power and high intrinsic gain

Science.gov (United States)

Lee, Sungsik; Nathan, Arokia

2016-10-01

The quest for low power becomes highly compelling in newly emerging application areas related to wearable devices in the Internet of Things. Here, we report on a Schottky-barrier indium-gallium-zinc-oxide thin-film transistor operating in the deep subthreshold regime (i.e., near the OFF state) at low supply voltages (400) that was both bias and geometry independent. The transistor reported here is useful for sensor interface circuits in wearable devices where high current sensitivity and ultralow power are vital for battery-less operation.

Current Enhancement with Contact-Area-Limited Doping for Bottom-Gate, Bottom-Contact Organic Thin-Film Transistors

Science.gov (United States)

Noda, Kei; Wakatsuki, Yusuke; Yamagishi, Yuji; Wada, Yasuo; Toyabe, Toru; Matsushige, Kazumi

2013-02-01

The current enhancement mechanism in contact-area-limited doping for bottom-gate, bottom-contact (BGBC) p-channel organic thin-film transistors (OTFTs) was investigated both by simulation and experiment. Simulation results suggest that carrier shortage and large potential drop occur in the source-electrode/channel interface region in a conventional BGBC OTFT during operation, which results in a decrease in the effective field-effect mobility. These phenomena are attributed to the low carrier concentration of active semiconductor layers in OTFTs and can be alleviated by contact-area-limited doping, where highly doped layers are prepared over source-drain electrodes. According to two-dimensional current distribution obtained from the device simulation, a current flow from the source electrode to the channel region via highly doped layers is generated in addition to the direct carrier injection from the source electrode to the channel, leading to the enhancement of the drain current and effective field-effect mobility. The expected current enhancement mechanism in contact-area-limited doping was experimentally confirmed in typical α-sexithiophene (α-6T) BGBC thin-film transistors.

High current, high bandwidth laser diode current driver

Science.gov (United States)

Copeland, David J.; Zimmerman, Robert K., Jr.

1991-01-01

A laser diode current driver has been developed for free space laser communications. The driver provides 300 mA peak modulation current and exhibits an optical risetime of less than 400 ps. The current and optical pulses are well behaved and show minimal ringing. The driver is well suited for QPPM modulation at data rates up to 440 Mbit/s. Much previous work has championed current steering circuits; in contrast, the present driver is a single-ended on/off switch. This results in twice the power efficiency as a current steering driver. The driver electrical efficiency for QPPM data is 34 percent. The high speed switch is realized with a Ku-band GaAsFET transistor, with a suitable pre-drive circuit, on a hybrid microcircuit adjacent to the laser diode.

Photoionization spectroscopy of deep defects responsible for current collapse in nitride-based field effect transistors

International Nuclear Information System (INIS)

Klein, P B; Binari, S C

2003-01-01

This review is concerned with the characterization and identification of the deep centres that cause current collapse in nitride-based field effect transistors. Photoionization spectroscopy is an optical technique that has been developed to probe the characteristics of these defects. Measured spectral dependences provide information on trap depth, lattice coupling and on the location of the defects in the device structure. The spectrum of an individual trap may also be regarded as a 'fingerprint' of the defect, allowing the trap to be followed in response to the variation of external parameters. The basis for these measurements is derived through a modelling procedure that accounts quantitatively for the light-induced drain current increase in the collapsed device. Applying the model to fit the measured variation of drain current increase with light illumination provides an estimate of the concentrations and photoionization cross-sections of the deep defects. The results of photoionization studies of GaN metal-semiconductor field effect transistors and AlGaN/GaN high electron mobility transistors (HEMTs) grown by metal-organic chemical vapour deposition (MOCVD) are presented and the conclusions regarding the nature of the deep traps responsible are discussed. Finally, recent photoionization studies of current collapse induced by short-term (several hours) bias stress in AlGaN/GaN HEMTs are described and analysed for devices grown by both MOCVD and molecular beam epitaxy. (topical review)

An analytic current-voltage model for quasi-ballistic III-nitride high electron mobility transistors

Science.gov (United States)

Li, Kexin; Rakheja, Shaloo

2018-05-01

We present an analytic model to describe the DC current-voltage (I-V) relationship in scaled III-nitride high electron mobility transistors (HEMTs) in which transport within the channel is quasi-ballistic in nature. Following Landauer's transport theory and charge calculation based on two-dimensional electrostatics that incorporates negative momenta states from the drain terminal, an analytic expression for current as a function of terminal voltages is developed. The model interprets the non-linearity of access regions in non-self-aligned HEMTs. Effects of Joule heating with temperature-dependent thermal conductivity are incorporated in the model in a self-consistent manner. With a total of 26 input parameters, the analytic model offers reduced empiricism compared to existing GaN HEMT models. To verify the model, experimental I-V data of InAlN/GaN with InGaN back-barrier HEMTs with channel lengths of 42 and 105 nm are considered. Additionally, the model is validated against numerical I-V data obtained from DC hydrodynamic simulations of an unintentionally doped AlGaN-on-GaN HEMT with 50-nm gate length. The model is also verified against pulsed I-V measurements of a 150-nm T-gate GaN HEMT. Excellent agreement between the model and experimental and numerical results for output current, transconductance, and output conductance is demonstrated over a broad range of bias and temperature conditions.

EDITORIAL: Reigniting innovation in the transistor Reigniting innovation in the transistor

Science.gov (United States)

Demming, Anna

2012-09-01

Today the transistor is integral to the electronic circuitry that wires our lives. When Bardeen and Brattain first observed an amplified signal by connecting electrodes to a germanium crystal they saw that their 'semiconductor triode' could prove a useful alternative to the more cumbersome vacuum tubes used at the time [1]. But it was perhaps William Schottky who recognized the extent of the transistor's potential. A basic transistor has three or more terminals and current across one pair of terminals can switch or amplify current through another pair. Bardeen, Brattain and Schottky were jointly awarded a Nobel Prize in 1956 'for their researches on semiconductors and their discovery of the transistor effect' [2]. Since then many new forms of the transistor have been developed and understanding of the underlying properties is constantly advancing. In this issue Chen and Shih and colleagues at Taiwan National University and Drexel University report a pyroelectrics transistor. They show how a novel optothermal gating mechanism can modulate the current, allowing a range of developments in nanoscale optoelectronics and wireless devices [3]. The explosion of interest in nanoscale devices in the 1990s inspired electronics researchers to look for new systems that can act as transistors, such as carbon nanotube [4] and silicon nanowire [5] transistors. Generally these transistors function by raising and lowering an energy barrier of kBT -1, but researchers in the US and Canada have demonstrated that the quantum interference between two electronic pathways through aromatic molecules can also modulate the current flow [6]. The device has advantages for further miniaturization where energy dissipation in conventional systems may eventually cause complications. Interest in transistor technology has also led to advances in fabrication techniques for achieving high production quantities, such as printing [7]. Researchers in Florida in the US demonstrated field effect transistor

Two-Dimensional Modeling of Aluminum Gallium Nitride/Gallium Nitride High Electron Mobility Transistor

National Research Council Canada - National Science Library

Holmes, Kenneth

2002-01-01

Gallium Nitride (GaN) High Electron Mobility Transistors (HEMT's) are microwave power devices that have the performance characteristics to improve the capabilities of current and future Navy radar and communication systems...

Wavy channel transistor for area efficient high performance operation

KAUST Repository

Fahad, Hossain M.

2013-04-05

We report a wavy channel FinFET like transistor where the channel is wavy to increase its width without any area penalty and thereby increasing its drive current. Through simulation and experiments, we show the effectiveness of such device architecture is capable of high performance operation compared to conventional FinFETs with comparatively higher area efficiency and lower chip latency as well as lower power consumption.

Anomalous high photoconductivity in short channel indium-zinc-oxide photo-transistors

International Nuclear Information System (INIS)

Choi, Hyun-Sik; Jeon, Sanghun

2015-01-01

Upon light exposure, an indium-zinc-oxide (IZO) thin-film transistor (TFT) presents higher photoconductivity by several orders of magnitude at the negative gate bias region. Among various device geometrical factors, scaling down the channel length of the photo-transistor results in an anomalous increase in photoconductivity. To probe the origin of this high photoconductivity in short-channel device, we measured transient current, current–voltage, and capacitance–voltage characteristics of IZO–TFTs with various channel lengths and widths before and after illumination. Under the illumination, the equilibrium potential region which lies far from front interface exists only in short-channel devices, forming the un-depleted conducting back channel. This region plays an important role in carrier transport under the illumination, leading to high photoconductivity in short-channel devices. Photon exposure coupled with gate-modulated band bending for short-channel devices leads to the accumulation of V o ++ at the front channel and screening negative gate bias, thereby generating high current flow in the un-depleted back-channel region

Osteoblastic cells trigger gate currents on nanocrystalline diamond transistor

Czech Academy of Sciences Publication Activity Database

Ižák, Tibor; Krátká, Marie; Kromka, Alexander; Rezek, Bohuslav

2015-01-01

Roč. 129, May (2015), 95-99 ISSN 0927-7765 R&D Projects: GA ČR GAP108/12/0996 Grant - others:AVČR(CZ) M100101209 Institutional support: RVO:68378271 Keywords : field-effect transistors * nanocrystalline diamond * osteoblastic cells * leakage currents Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 3.902, year: 2015

Removing the current-limit of vertical organic field effect transistors

Science.gov (United States)

Sheleg, Gil; Greenman, Michael; Lussem, Bjorn; Tessler, Nir

2017-11-01

The reported Vertical Organic Field Effect Transistors (VOFETs) show either superior current and switching speeds or well-behaved transistor performance, especially saturation in the output characteristics. Through the study of the relationship between the device architecture or dimensions and the device performance, we find that achieving a saturation regime in the output characteristics requires that the device operates in the injection limited regime. In current structures, the existence of the injection limited regime depends on the source's injection barrier as well as on the buried semiconductor layer thickness. To overcome the injection limit imposed by the necessity of injection barrier, we suggest a new architecture to realize VOFETs. This architecture shows better gate control and is independent of the injection barrier at the source, thus allowing for several A cm-2 for a semiconductor having a mobility value of 0.1 cm2 V-1 s-1.

Field-Effect Transistors Based on Networks of Highly Aligned, Chemically Synthesized N = 7 Armchair Graphene Nanoribbons.

Science.gov (United States)

Passi, Vikram; Gahoi, Amit; Senkovskiy, Boris V; Haberer, Danny; Fischer, Felix R; Grüneis, Alexander; Lemme, Max C

2018-03-28

We report on the experimental demonstration and electrical characterization of N = 7 armchair graphene nanoribbon (7-AGNR) field effect transistors. The back-gated transistors are fabricated from atomically precise and highly aligned 7-AGNRs, synthesized with a bottom-up approach. The large area transfer process holds the promise of scalable device fabrication with atomically precise nanoribbons. The channels of the FETs are approximately 30 times longer than the average nanoribbon length of 30 nm to 40 nm. The density of the GNRs is high, so that transport can be assumed well-above the percolation threshold. The long channel transistors exhibit a maximum I ON / I OFF current ratio of 87.5.

Protonic transistors from thin reflecting films

Energy Technology Data Exchange (ETDEWEB)

Ordinario, David D.; Phan, Long; Jocson, Jonah-Micah [Department of Chemical Engineering and Materials Science, University of California, Irvine, California 92697 (United States); Nguyen, Tam [Department of Chemistry, University of California, Irvine, California 92697 (United States); Gorodetsky, Alon A., E-mail: alon.gorodetsky@uci.edu [Department of Chemical Engineering and Materials Science, University of California, Irvine, California 92697 (United States); Department of Chemistry, University of California, Irvine, California 92697 (United States)

2015-01-01

Ionic transistors from organic and biological materials hold great promise for bioelectronics applications. Thus, much research effort has focused on optimizing the performance of these devices. Herein, we experimentally validate a straightforward strategy for enhancing the high to low current ratios of protein-based protonic transistors. Upon reducing the thickness of the transistors’ active layers, we increase their high to low current ratios 2-fold while leaving the other figures of merit unchanged. The measured ratio of 3.3 is comparable to the best values found for analogous devices. These findings underscore the importance of the active layer geometry for optimum protonic transistor functionality.

β-Ga2O3 on insulator field-effect transistors with drain currents exceeding 1.5 A/mm and their self-heating effect

Science.gov (United States)

Zhou, Hong; Maize, Kerry; Qiu, Gang; Shakouri, Ali; Ye, Peide D.

2017-08-01

We have demonstrated that depletion/enhancement-mode β-Ga2O3 on insulator field-effect transistors can achieve a record high drain current density of 1.5/1.0 A/mm by utilizing a highly doped β-Ga2O3 nano-membrane as the channel. β-Ga2O3 on insulator field-effect transistor (GOOI FET) shows a high on/off ratio of 1010 and low subthreshold slope of 150 mV/dec even with 300 nm thick SiO2. The enhancement-mode GOOI FET is achieved through surface depletion. An ultra-fast, high resolution thermo-reflectance imaging technique is applied to study the self-heating effect by directly measuring the local surface temperature. High drain current, low Rc, and wide bandgap make the β-Ga2O3 on insulator field-effect transistor a promising candidate for future power electronics applications.

Tungsten trioxide as high-{kappa} gate dielectric for highly transparent and temperature-stable zinc-oxide-based thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Lorenz, Michael; Wenckstern, Holger von; Grundmann, Marius [Universitaet Leipzig, Fakultaet fuer Physik und Geowissenschaften, Institut fuer Experimentelle Physik II, Linnestr. 5, 04103 Leipzig (Germany)

2012-07-01

We demonstrate metal-insulator-semiconductor field-effect transistors with high-{kappa}, room-temperature deposited, highly transparent tungsten trioxide (WO{sub 3}) as gate dielectric. The channel material consists of a zinc oxide (ZnO) thin-film. The transmittance and resistivity of WO{sub 3} films was tuned in order to obtain a highly transparent and insulating WO{sub 3} dielectric. The devices were processed by standard photolithography using lift-off technique. On top of the WO{sub 3} dielectric a highly transparent and conductive oxide consisting of ZnO: Al 3% wt. was deposited. The gate structure of the devices exhibits an average transmittance in the visible spectral range of 86%. The on/off-current ratio is larger than 10{sup 8} with off- and gate leakage-currents below 3 x 10{sup -8} A/cm{sup 2}. Due to the high relative permittivity of {epsilon}{sub r} {approx} 70, a gate voltage sweep of only 2 V is necessary to turn the transistor on and off with a minimum subthreshold swing of 80 mV/decade. The channel mobility of the transistors equals the Hall-effect mobility with a value of 5 cm{sup 2}/Vs. It is furthermore shown, that the devices are stable up to operating temperatures of at least 150 C.

ON current enhancement of nanowire Schottky barrier tunnel field effect transistors

Science.gov (United States)

Takei, Kohei; Hashimoto, Shuichiro; Sun, Jing; Zhang, Xu; Asada, Shuhei; Xu, Taiyu; Matsukawa, Takashi; Masahara, Meishoku; Watanabe, Takanobu

2016-04-01

Silicon nanowire Schottky barrier tunnel field effect transistors (NW-SBTFETs) are promising structures for high performance devices. In this study, we fabricated NW-SBTFETs to investigate the effect of nanowire structure on the device characteristics. The NW-SBTFETs were operated with a backgate bias, and the experimental results demonstrate that the ON current density is enhanced by narrowing the width of the nanowire. We confirmed using the Fowler-Nordheim plot that the drain current in the ON state mainly comprises the quantum tunneling component through the Schottky barrier. Comparison with a technology computer aided design (TCAD) simulation revealed that the enhancement is attributed to the electric field concentration at the corners of cross-section of the NW. The study findings suggest an effective approach to securing the ON current by Schottky barrier width modulation.

High mobility polymer gated organic field effect transistor using zinc ...

Indian Academy of Sciences (India)

Organic thin film transistors were fabricated using evaporated zinc phthalocyanine as the active layer. Parylene film ... At room temperature, these transistors exhibit p-type conductivity with field-effect ... Keywords. Organic semiconductor; field effect transistor; phthalocyanine; high mobility. ... The evaporation rate was kept at ...

Negative Offset Operation of Four-Transistor CMOS Image Pixels for Increased Well Capacity and Suppressed Dark Current

NARCIS (Netherlands)

Mheen, B.; Song, Y.J.; Theuwissen, J.P.

2008-01-01

This letter presents an electrical method to reduce dark current as well as increase well capacity of four-transistor pixels in a CMOS image sensor, utilizing a small negative offset voltage to the gate of the transfer (TX) transistor particularly only when the TX transistor is off. As a result,

Viscosity-dependent drain current noise of AlGaN/GaN high electron mobility transistor in polar liquids

International Nuclear Information System (INIS)

Fang, J. Y.; Hsu, C. P.; Kang, Y. W.; Fang, K. C.; Kao, W. L.; Yao, D. J.; Chen, C. C.; Li, S. S.; Yeh, J. A.; Wang, Y. L.; Lee, G. Y.; Chyi, J. I.; Hsu, C. H.; Huang, Y. F.; Ren, F.

2013-01-01

The drain current fluctuation of ungated AlGaN/GaN high electron mobility transistors (HEMTs) measured in different fluids at a drain-source voltage of 0.5 V was investigated. The HEMTs with metal on the gate region showed good current stability in deionized water, while a large fluctuation in drain current was observed for HEMTs without gate metal. The fluctuation in drain current for the HEMTs without gate metal was observed and calculated as standard deviation from a real-time measurement in air, deionized water, ethanol, dimethyl sulfoxide, ethylene glycol, 1,2-butanediol, and glycerol. At room temperature, the fluctuation in drain current for the HEMTs without gate metal was found to be relevant to the dipole moment and the viscosity of the liquids. A liquid with a larger viscosity showed a smaller fluctuation in drain current. The viscosity-dependent fluctuation of the drain current was ascribed to the Brownian motions of the liquid molecules, which induced a variation in the surface dipole of the gate region. This study uncovers the causes of the fluctuation in drain current of HEMTs in fluids. The results show that the AlGaN/GaN HEMTs may be used as sensors to measure the viscosity of liquids within a certain range of viscosity

A built-in current sensor using thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Hatzopoulos, A A [Department of Electrical and Computer Eng., Electronics Lab., Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece); Siskos, S [Department of Physics, Electronics Lab., Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece); Dimitriadis, C A [Department of Physics, Microelectronic device characterization and design Lab., Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece); Papadopoulos, N [Department of Electrical and Computer Eng., Electronics Lab., Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece); Pappas, I [Department of Physics, Electronics Lab., Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece); Nalpantidis, L [Department of Physics, Electronics Lab., Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece)

2005-01-01

A simple current mirror using TFTs with input terminals which are capacitively coupled to the TFT gate, is used in this work, to design a built-in current sensor (BICS). The important feature in this application is that the voltage drop across the sensing TFT device can be reduced to almost zero value, while preserving transistor operation in the saturation region. This makes the proposed BICS appropriate for TFT applications without affecting the circuit operation. It also results in adequate linearity for the current monitoring, making the structure applicable to digital as well as to analog and mixed-signal circuit testing.

Negative Offset Operation of Four-Transistor CMOS Image Pixels for Increased Well Capacity and Suppressed Dark Current

OpenAIRE

Mheen, B.; Song, Y.J.; Theuwissen, J.P.

2008-01-01

This letter presents an electrical method to reduce dark current as well as increase well capacity of four-transistor pixels in a CMOS image sensor, utilizing a small negative offset voltage to the gate of the transfer (TX) transistor particularly only when the TX transistor is off. As a result, using a commercial pixel in a 0.18 ?m CMOS process, the voltage drop due to dark current of the pinned photodiode (PPD) is reduced by 6.1 dB and the well capacity is enhanced by 4.4 dB, which is attri...

Fabrication of enhancement-mode AlGaN/GaN high electron mobility transistors using double plasma treatment

Energy Technology Data Exchange (ETDEWEB)

Lim, Jong-Won, E-mail: jwlim@etri.re.kr [Photonic/Wireless Convergence Components Dept., IT Materials and Components Lab., Electronics and Telecommunications Research Institute, Daejeon 305-700 (Korea, Republic of); Ahn, Ho-Kyun; Kim, Seong-il; Kang, Dong-Min; Lee, Jong-Min; Min, Byoung-Gue; Lee, Sang-Heung; Yoon, Hyung-Sup; Ju, Chull-Won; Kim, Haecheon; Mun, Jae-Kyoung; Nam, Eun-Soo [Photonic/Wireless Convergence Components Dept., IT Materials and Components Lab., Electronics and Telecommunications Research Institute, Daejeon 305-700 (Korea, Republic of); Park, Hyung-Moo [Photonic/Wireless Convergence Components Dept., IT Materials and Components Lab., Electronics and Telecommunications Research Institute, Daejeon 305-700 (Korea, Republic of); Division of Electronics and Electrical Engineering, Dongguk University, Seoul (Korea, Republic of)

2013-11-29

We report the fabrication and DC and microwave characteristics of 0.5 μm AlGaN/GaN high electron mobility transistors using double plasma treatment process. Silicon nitride layers 700 and 150 Å thick were deposited by plasma-enhanced chemical vapor deposition at 260 °C to protect the device and to define the gate footprint. The double plasma process was carried out by two different etching techniques to obtain enhancement-mode AlGaN/GaN high electron mobility transistors with 0.5 μm gate lengths. The enhancement-mode AlGaN/GaN high electron mobility transistor was prepared in parallel to the depletion-mode AlGaN/GaN high electron mobility transistor device on one wafer. Completed double plasma treated 0.5 μm AlGaN/GaN high electron mobility transistor devices fabricated by dry etching exhibited a peak transconductance, gm, of 330 mS/mm, a breakdown voltage of 115 V, a current-gain cutoff frequency (f{sub T}) of 18 GHz, and a maximum oscillation frequency (f{sub max}) of 66 GHz. - Highlights: • The double plasma process was carried out by two different etching techniques. • Double plasma treated device exhibited a transconductance of 330 mS/mm. • Completed 0.5 μm gate device exhibited a current-gain cutoff frequency of 18 GHz. • The off-state breakdown voltage of 115 V for 0.5 μm gate device was obtained. • Continuous-wave output power density of 4.3 W/mm was obtained at 2.4 GHz.

Fabrication of enhancement-mode AlGaN/GaN high electron mobility transistors using double plasma treatment

International Nuclear Information System (INIS)

Lim, Jong-Won; Ahn, Ho-Kyun; Kim, Seong-il; Kang, Dong-Min; Lee, Jong-Min; Min, Byoung-Gue; Lee, Sang-Heung; Yoon, Hyung-Sup; Ju, Chull-Won; Kim, Haecheon; Mun, Jae-Kyoung; Nam, Eun-Soo; Park, Hyung-Moo

2013-01-01

We report the fabrication and DC and microwave characteristics of 0.5 μm AlGaN/GaN high electron mobility transistors using double plasma treatment process. Silicon nitride layers 700 and 150 Å thick were deposited by plasma-enhanced chemical vapor deposition at 260 °C to protect the device and to define the gate footprint. The double plasma process was carried out by two different etching techniques to obtain enhancement-mode AlGaN/GaN high electron mobility transistors with 0.5 μm gate lengths. The enhancement-mode AlGaN/GaN high electron mobility transistor was prepared in parallel to the depletion-mode AlGaN/GaN high electron mobility transistor device on one wafer. Completed double plasma treated 0.5 μm AlGaN/GaN high electron mobility transistor devices fabricated by dry etching exhibited a peak transconductance, gm, of 330 mS/mm, a breakdown voltage of 115 V, a current-gain cutoff frequency (f T ) of 18 GHz, and a maximum oscillation frequency (f max ) of 66 GHz. - Highlights: • The double plasma process was carried out by two different etching techniques. • Double plasma treated device exhibited a transconductance of 330 mS/mm. • Completed 0.5 μm gate device exhibited a current-gain cutoff frequency of 18 GHz. • The off-state breakdown voltage of 115 V for 0.5 μm gate device was obtained. • Continuous-wave output power density of 4.3 W/mm was obtained at 2.4 GHz

Electric-stress reliability and current collapse of different thickness SiNx passivated AlGaN/GaN high electron mobility transistors

International Nuclear Information System (INIS)

Ling, Yang; Gui-Zhou, Hu; Yue, Hao; Xiao-Hua, Ma; Si, Quan; Li-Yuan, Yang; Shou-Gao, Jiang

2010-01-01

This paper investigates the impact of electrical degradation and current collapse on different thickness SiN x passivated AlGaN/GaN high electron mobility transistors. It finds that higher thickness SiN x passivation can significantly improve the high-electric-field reliability of a device. The degradation mechanism of the SiN x passivation layer under ON-state stress has also been discussed in detail. Under the ON-state stress, the strong electric-field led to degradation of SiN x passivation located in the gate-drain region. As the thickness of SiN x passivation increases, the density of the surface state will be increased to some extent. Meanwhile, it is found that the high NH 3 flow in the plasma enhanced chemical vapour deposition process could reduce the surface state and suppress the current collapse. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Effects of SiNx on two-dimensional electron gas and current collapse of AlGaN/GaN high electron mobility transistors

International Nuclear Information System (INIS)

Fan, Ren; Zhi-Biao, Hao; Lei, Wang; Lai, Wang; Hong-Tao, Li; Yi, Luo

2010-01-01

SiN x is commonly used as a passivation material for AlGaN/GaN high electron mobility transistors (HEMTs). In this paper, the effects of SiN x passivation film on both two-dimensional electron gas characteristics and current collapse of AlGaN/GaN HEMTs are investigated. The SiN x films are deposited by high- and low-frequency plasma-enhanced chemical vapour deposition, and they display different strains on the AlGaN/GaN heterostructure, which can explain the experiment results. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Multiple-channel detection of cellular activities by ion-sensitive transistors

Science.gov (United States)

Machida, Satoru; Shimada, Hideto; Motoyama, Yumi

2018-04-01

An ion-sensitive field-effect transistor to record cellular activities was demonstrated. This field-effect transistor (bio transistor) includes cultured cells on the gate insulator instead of gate electrode. The bio transistor converts a change in potential underneath the cells into variation of the drain current when ion channels open. The bio transistor has high detection sensitivity to even minute variations in potential utilizing a subthreshold swing region. To open ion channels, a reagent solution (acetylcholine) was added to a human-originating cell cultured on the bio transistor. The drain current was successfully decreased with the addition of acetylcholine. Moreover, we attempted to detect the opening of ion channels using a multiple-channel measurement circuit containing several bio transistors. As a consequence, the drain current distinctly decreased only after the addition of acetylcholine. We confirmed that this measurement system including bio transistors enables to observation of cellular activities sensitively and simultaneously.

High sensitivity pH sensing on the BEOL of industrial FDSOI transistors

Science.gov (United States)

Rahhal, Lama; Ayele, Getenet Tesega; Monfray, Stéphane; Cloarec, Jean-Pierre; Fornacciari, Benjamin; Pardoux, Eric; Chevalier, Celine; Ecoffey, Serge; Drouin, Dominique; Morin, Pierre; Garnier, Philippe; Boeuf, Frederic; Souifi, Abdelkader

2017-08-01

In this work we demonstrate the use of Fully Depleted Silicon On Insulator (FDSOI) transistors as pH sensors with a 23 nm silicon nitride sensing layer built in the Back-End-Of-Line (BEOL). The back end process to deposit the sensing layer and fabricate the electrical structures needed for testing is detailed. A series of tests employing different pH buffer solutions has been performed on transistors of different geometries, controlled via the back gate. The main findings show a shift of the drain current (ID) as a function of the back gate voltage (VB) when different pH buffer solutions are probed in the range of pH 6 to pH 8. This shift is observed at VB voltages swept from 0 V to 3 V, demonstrating the sensor operation at low voltage. A high sensitivity of up to 250 mV/pH unit (more than 4-fold larger than Nernstian response) is observed on FDSOI MOS transistors of 0.06 μm gate length and 0.08 μm gate width. She is currently working as a Postdoctoral researcher at Institut des nanotechnologies de Lyon in collaboration with STMicroelectronics and Université de Sherbrook (Canada) working on ;Integration of ultra-low-power gas and pH sensors with advanced technologies;. Her research interest includes selection, machining, optimisation and electrical characterisation of the sensitive layer for a low power consumption gas sensor based on advanced MOS transistors.

Microwave annealing effect for highly reliable biosensor: dual-gate ion-sensitive field-effect transistor using amorphous InGaZnO thin-film transistor.

Science.gov (United States)

Lee, In-Kyu; Lee, Kwan Hyi; Lee, Seok; Cho, Won-Ju

2014-12-24

We used a microwave annealing process to fabricate a highly reliable biosensor using amorphous-InGaZnO (a-IGZO) thin-film transistors (TFTs), which usually experience threshold voltage instability. Compared with furnace-annealed a-IGZO TFTs, the microwave-annealed devices showed superior threshold voltage stability and performance, including a high field-effect mobility of 9.51 cm(2)/V·s, a low threshold voltage of 0.99 V, a good subthreshold slope of 135 mV/dec, and an outstanding on/off current ratio of 1.18 × 10(8). In conclusion, by using the microwave-annealed a-IGZO TFT as the transducer in an extended-gate ion-sensitive field-effect transistor biosensor, we developed a high-performance biosensor with excellent sensing properties in terms of pH sensitivity, reliability, and chemical stability.

Analysis of current instabilities of thin AlN/GaN/AlN double heterostructure high electron mobility transistors

International Nuclear Information System (INIS)

Zervos, Ch; Adikimenakis, A; Bairamis, A; Kostopoulos, A; Kayambaki, M; Tsagaraki, K; Konstantinidis, G; Georgakilas, A

2016-01-01

The current instabilities of high electron mobility transistors (HEMTs), based on thin double AlN/GaN/AlN heterostructures (∼0.5 μm total thickness), directly grown on sapphire substrates, have been analyzed and compared for different AlN top barrier thicknesses. The structures were capped by 1 nm GaN and non-passivated 1 μm gate-length devices were processed. Pulsed I–V measurements resulted in a maximum cold pulsed saturation current of 1.4 A mm −1 at a gate-source voltage of +3 V for 3.7 nm AlN thickness. The measured gate and drain lag for 500 ns pulse-width varied between 6%–12% and 10%–18%, respectively. Furthermore, a small increase in the threshold voltage was observed for all the devices, possibly due to the trapping of electrons under the gate contact. The off-state breakdown voltage of V br  = 70 V, for gate-drain spacing of 2 μm, was approximately double the value measured for a single AlN/GaN HEMT structure grown on a thick GaN buffer layer. The results suggest that the double AlN/GaN/AlN heterostructures may offer intrinsic advantages for the breakdown and current stability characteristics of high current HEMTs. (paper)

Rendering high charge density of states in ionic liquid-gated MoS 2 transistors

NARCIS (Netherlands)

Lee, Y.; Lee, J.; Kim, S.; Park, H.S.

2014-01-01

We investigated high charge density of states (DOS) in the bandgap of MoS2 nanosheets with variable temperature measurements on ionic liquid-gated MoS2 transistors. The thermally activated charge transport indicates that the electrical current in the two-dimensional MoS 2 nanosheets under high

High temperature study of flexible silicon-on-insulator fin field-effect transistors

KAUST Repository

Diab, Amer El Hajj

2014-09-29

We report high temperature electrical transport characteristics of a flexible version of the semiconductor industry\\'s most advanced architecture: fin field-effect transistor on silicon-on-insulator with sub-20 nm fins and high-κ/metal gate stacks. Characterization from room to high temperature (150 °C) was completed to determine temperature dependence of drain current (Ids), gate leakage current (Igs), transconductance (gm), and extracted low-field mobility (μ0). Mobility degradation with temperature is mainly caused by phonon scattering. The other device characteristics show insignificant difference at high temperature which proves the suitability of inorganic flexible electronics with advanced device architecture.

Radio frequency and linearity performance of transistors using high-purity semiconducting carbon nanotubes.

Science.gov (United States)

Wang, Chuan; Badmaev, Alexander; Jooyaie, Alborz; Bao, Mingqiang; Wang, Kang L; Galatsis, Kosmas; Zhou, Chongwu

2011-05-24

This paper reports the radio frequency (RF) and linearity performance of transistors using high-purity semiconducting carbon nanotubes. High-density, uniform semiconducting nanotube networks are deposited at wafer scale using our APTES-assisted nanotube deposition technique, and RF transistors with channel lengths down to 500 nm are fabricated. We report on transistors exhibiting a cutoff frequency (f(t)) of 5 GHz and with maximum oscillation frequency (f(max)) of 1.5 GHz. Besides the cutoff frequency, the other important figure of merit for the RF transistors is the device linearity. For the first time, we report carbon nanotube RF transistor linearity metrics up to 1 GHz. Without the use of active probes to provide the high impedance termination, the measurement bandwidth is therefore not limited, and the linearity measurements can be conducted at the frequencies where the transistors are intended to be operating. We conclude that semiconducting nanotube-based transistors are potentially promising building blocks for highly linear RF electronics and circuit applications.

Enhanced plasma wave detection of terahertz radiation using multiple high electron-mobility transistors connected in series

KAUST Repository

Elkhatib, Tamer A.; Kachorovskiǐ, Valentin Yu; Stillman, William J.; Veksler, Dmitry B.; Salama, Khaled N.; Zhang, Xicheng; Shur, Michael S.

2010-01-01

We report on enhanced room-temperature detection of terahertz radiation by several connected field-effect transistors. For this enhanced nonresonant detection, we have designed, fabricated, and tested plasmonic structures consisting of multiple InGaAs/GaAs pseudomorphic high electron-mobility transistors connected in series. Results show a 1.63-THz response that is directly proportional to the number of detecting transistors biased by a direct drain current at the same gate-to-source bias voltages. The responsivity in the saturation regime was found to be 170 V/W with the noise equivalent power in the range of 10-7 W/Hz0.5. The experimental data are in agreement with the detection mechanism based on the rectification of overdamped plasma waves excited by terahertz radiation in the transistor channel. © 2010 IEEE.

Enhanced plasma wave detection of terahertz radiation using multiple high electron-mobility transistors connected in series

KAUST Repository

Elkhatib, Tamer A.

2010-02-01

We report on enhanced room-temperature detection of terahertz radiation by several connected field-effect transistors. For this enhanced nonresonant detection, we have designed, fabricated, and tested plasmonic structures consisting of multiple InGaAs/GaAs pseudomorphic high electron-mobility transistors connected in series. Results show a 1.63-THz response that is directly proportional to the number of detecting transistors biased by a direct drain current at the same gate-to-source bias voltages. The responsivity in the saturation regime was found to be 170 V/W with the noise equivalent power in the range of 10-7 W/Hz0.5. The experimental data are in agreement with the detection mechanism based on the rectification of overdamped plasma waves excited by terahertz radiation in the transistor channel. © 2010 IEEE.

Radiation effects on junction field-effect transistors (JFETS), MOSFETs, and bipolar transistors, as related to SSC circuit design

International Nuclear Information System (INIS)

Kennedy, E.J.; Alley, G.T.; Britton, C.L. Jr.; Skubic, P.L.; Gray, B.; Wu, A.

1990-01-01

Some results of radiation effects on selected junction field-effect transistors, MOS field-effect transistors, and bipolar junction transistors are presented. The evaluations include dc parameters, as well as capacitive variations and noise evaluations. The tests are made at the low current and voltage levels (in particular, at currents ≤1 mA) that are essential for the low-power regimes required by SSC circuitry. Detailed noise data are presented both before and after 5-Mrad (gamma) total-dose exposure. SPICE radiation models for three high-frequency bipolar processes are compared for a typical charge-sensitive preamplifier

Superconducting transistor

International Nuclear Information System (INIS)

Gray, K.E.

1978-01-01

A three film superconducting tunneling device, analogous to a semiconductor transistor, is presented, including a theoretical description and experimental results showing a current gain of four. Much larger current gains are shown to be feasible. Such a development is particularly interesting because of its novelty and the striking analogies with the semiconductor junction transistor

DEVICE TECHNOLOGY. Nanomaterials in transistors: From high-performance to thin-film applications.

Science.gov (United States)

Franklin, Aaron D

2015-08-14

For more than 50 years, silicon transistors have been continuously shrunk to meet the projections of Moore's law but are now reaching fundamental limits on speed and power use. With these limits at hand, nanomaterials offer great promise for improving transistor performance and adding new applications through the coming decades. With different transistors needed in everything from high-performance servers to thin-film display backplanes, it is important to understand the targeted application needs when considering new material options. Here the distinction between high-performance and thin-film transistors is reviewed, along with the benefits and challenges to using nanomaterials in such transistors. In particular, progress on carbon nanotubes, as well as graphene and related materials (including transition metal dichalcogenides and X-enes), outlines the advances and further research needed to enable their use in transistors for high-performance computing, thin films, or completely new technologies such as flexible and transparent devices. Copyright © 2015, American Association for the Advancement of Science.

Gallium nitride based transistors for high-efficiency microwave switch-mode amplifiers

Energy Technology Data Exchange (ETDEWEB)

Maroldt, Stephan

2012-07-01

circuit efficiency of >80% were achieved for an operation at 0.45 GHz when adjusting the transistor size for lower operation frequencies. A further decisive improvement of speed and circuit complexity was found by the implementation of enhancement-mode GaN transistors based on a high-transconductance gate-recess technology. Transistors with a threshold voltage of +1 V were demonstrated with a high current drive capability and a maximum transconductance of up to 600 mS/mm. Their reduced input voltage swing tremendously increases the compatibility of digital power amplifier circuits based on GaN and external digital driver and modulator circuits based on silicon technology. Moreover, an innovative development, the series-diode GaN transistor, replaces an off-chip hybrid diode in the class-S amplifier with an integrated solution. It reduces parasitic switching losses and improves the total amplifier properties in terms of operation frequency, efficiency, and circuit complexity. A differential switch-mode core chip featuring series-diode transistors and additional onchip filter elements enabled our partner EADS to realize the first class-S amplifier at 2 GHz worldwide in a module.

Transistor data book

International Nuclear Information System (INIS)

1988-03-01

It introduces how to use this book. It lists transistor data and index, which are Type No, Cross index, Germanium PNP low power transistors, silicon NPN low power transistors, Germanium PNP high power transistors, Switching transistors, transistor arrays, Miscellaneous transistors, types with U.S military specifications, direct replacement transistors, suggested replacement transistors, schematic drawings, outline drawings, device number keys and manufacturer's logos.

Graphene as tunable contact for high performance thin film transistor

Science.gov (United States)

Liu, Yuan

Graphene has been one of the most extensively studied materials due to its unique band structure, the linear dispersion at the K point. It gives rise to novel phenomena, such as the anomalous quantum Hall effect, and has opened up a new category of "Fermi-Dirac" physics. Graphene has also attracted enormous attention for future electronics because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. However, graphene has zero intrinsic band gap, thus can not be used as the active channel material for logic transistors with sufficient on/off current ratio. Previous approaches to address this challenge include the induction of a transport gap in graphene nanostructures or bilayer graphene. However, these approaches have proved successful in improving the on-- off ratio of the resulting devices, but often at a severe sacrifice of the deliverable current density. Alternatively, with a finite density of states, tunable work-function and optical transparency, graphene can function as a unique tunable contact material to create a new structure of electronic devices. In this thesis, I will present my effort toward on-off ratio of graphene based vertical thin film transistor. I will include the work form four of my first author publication. I will first present my research studies on the a dramatic enhancement of the overall quantum efficiency and spectral selectivity of graphene photodetector, by coupling with plasmonic nanostructures. It is observed that metallic plasmonic nanostructures can be integrated with graphene photodetectors to greatly enhance the photocurrent and external quantum efficiency by up to 1,500%. Plasmonic nanostructures of variable resonance frequencies selectively amplify the photoresponse of graphene to light of different wavelengths, enabling highly specific detection of multicolours. Then I will show a new design of highly flexible vertical TFTs (VTFTs) with superior electrical

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

Energy Technology Data Exchange (ETDEWEB)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina [Department of Materials Science and Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen D-91058 (Germany); Institute for Physical Chemistry, Universität Heidelberg, Heidelberg D-69120 (Germany); Miehler, Dominik [Department of Materials Science and Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen D-91058 (Germany); Zaumseil, Jana, E-mail: zaumseil@uni-heidelberg.de [Institute for Physical Chemistry, Universität Heidelberg, Heidelberg D-69120 (Germany)

2015-08-24

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.

Various Recipes of SiNx Passivated AlGaN/GaN High Electron Mobility Transistors in Correlation with Current Slump

International Nuclear Information System (INIS)

Ling, Yang; Yue, Hao; Xiao-Hua, Ma; Si, Quan; Gui-Zhou, Hu; Shou-Gao, Jiang; Li-Yuan, Yang

2009-01-01

The current slump of different recipes of SiN x passivated AlGaN/GaN high electron mobility transistors (HEMTs) is investigated. The dc and pulsed current-voltage curves of AlGaN/GaN HEMTs using different recipes are analyzed. It is found that passivation leakage has a strong relationship with NH 3 flow in the plasma-enhanced chemical vapor phase deposition process, which has impacted on the current collapse of SiN x passivated devices. We analyze the pulsed I DS – V DS characteristics of different recipes of SiN x passivation devices for different combinations of gate and drain quiescent biases (V GS0 , V DS0 ) of (0, 0), (−6, 0), (−6, 15) and (0, 15)V. The possible mechanisms are the traps in SiN x passivation capturing the electrons and the surface states at the SiN x /AlGaN interface, which can affect the channel of two-dimensional electron gas and cause the current collapse. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Combined effects of 60Co dose and high frequency interferences on a discrete bipolar transistor

International Nuclear Information System (INIS)

Doridant, A.; Raoult, J.; Jarrix, S.; Blain, A.; Dusseau, L.; Hoffmann, P.; Chatry, N.; Calvel, P.

2012-01-01

This paper concerns bipolar transistors subject to a double aggression: dose irradiation and high-frequency interference. The electromagnetic interference is injected in a contactless way in the near-field zone around the device. Parameters of the interference are power and frequency, the latter largely out of band of operation of the transistors. The output voltage of the transistor exhibits changes, due to rectification and to some extent to current crowding. The importance of the base bias set-up for the type of change occurring in voltage is displayed. After irradiation with a 60 Co source, the voltage output will change under electromagnetic interference but sometimes in an opposite way as initially measured. The impact of the irradiation with respect to electromagnetic susceptibility is highlighted from a physical point of view. Finally preliminary results of simulation for susceptibility prediction are given and a discussion is given on the limits of the transistor model used. (authors)

Low Noise Bias Current/Voltage References Based on Floating-Gate MOS Transistors

DEFF Research Database (Denmark)

Igor, Mucha

1997-01-01

The exploitation of floating-gate MOS transistors as reference current and voltage sources is investigated. Test structures of common source and common drain floating-gate devices have been implemented in a commercially available 0.8 micron double-poly CMOS process. The measurements performed...

High-conductance low-voltage organic thin film transistor with locally rearranged poly(3-hexylthiophene) domain by current annealing on plastic substrate

Science.gov (United States)

Pei, Zingway; Tsai, Hsing-Wang; Lai, Hsin-Cheng

2016-02-01

The organic material based thin film transistors (TFTs) are attractive for flexible optoelectronics applications due to the ability of lager area fabrication by solution and low temperature process on plastic substrate. Recently, the research of organic TFT focus on low operation voltage and high output current to achieve a low power organic logic circuit for optoelectronic device,such as e-paper or OLED displayer. To obtain low voltage and high output current, high gate capacitance and high channel mobility are key factors. The well-arranged polymer chain by a high temperature postannealing, leading enhancement conductivity of polymer film was a general method. However, the thermal annealing applying heat for all device on the substrate and may not applicable to plastic substrate. Therefore, in this work, the low operation voltage and high output current of polymer TFTs was demonstrated by locally electrical bias annealing. The poly(styrene-comethyl methacrylate) (PS-r-PMMA) with ultra-thin thickness is used as gate dielectric that the thickness is controlled by thermal treatment after spin coated on organic electrode. In electrical bias-annealing process, the PS-r- PMMA is acted a heating layer. After electrical bias-annealing, the polymer TFTs obtain high channel mobility at low voltage that lead high output current by a locally annealing of P3HT film. In the future, the locally electrical biasannealing method could be applied on plastic substrate for flexible optoelectronic application.

Unijunction transistors

International Nuclear Information System (INIS)

1981-01-01

The electrical characteristics of unijunction transistors can be modified by irradiation with electron beams in excess of 400 KeV and at a dose rate of 10 13 to 10 16 e/cm 2 . Examples are given of the effect of exposing the emitter-base junctions of transistors to such lattice defect causing radiation for a time sufficient to change the valley current of the transistor. (U.K.)

Ultrasensitive detection of Hg2+ using oligonucleotide-functionalized AlGaN/GaN high electron mobility transistor

International Nuclear Information System (INIS)

Cheng, Junjie; Li, Jiadong; Miao, Bin; Wu, Dongmin; Wang, Jine; Pei, Renjun; Wu, Zhengyan

2014-01-01

An oligonucleotide-functionalized ion sensitive AlGaN/GaN high electron mobility transistor (HEMT) was fabricated to detect trace amounts of Hg 2+ . The advantages of ion sensitive AlGaN/GaN HEMT and highly specific binding interaction between Hg 2+ and thymines were combined. The current response of this Hg 2+ ultrasensitive transistor was characterized. The current increased due to the accumulation of Hg 2+ ions on the surface by the highly specific thymine-Hg 2+ -thymine recognition. The dynamic linear range for Hg 2+ detection has been determined in the concentrations from 10 −14 to 10 −8 M and a detection limit below 10 −14 M level was estimated, which is the best result of AlGaN/GaN HEMT biosensors for Hg 2+ detection till now.

Biofunctionalized Zinc Oxide Field Effect Transistors for Selective Sensing of Riboflavin with Current Modulation

Directory of Open Access Journals (Sweden)

Morley O. Stone

2011-06-01

Full Text Available Zinc oxide field effect transistors (ZnO-FET, covalently functionalized with single stranded DNA aptamers, provide a highly selective platform for label-free small molecule sensing. The nanostructured surface morphology of ZnO provides high sensitivity and room temperature deposition allows for a wide array of substrate types. Herein we demonstrate the selective detection of riboflavin down to the pM level in aqueous solution using the negative electrical current response of the ZnO-FET by covalently attaching a riboflavin binding aptamer to the surface. The response of the biofunctionalized ZnO-FET was tuned by attaching a redox tag (ferrocene to the 3’ terminus of the aptamer, resulting in positive current modulation upon exposure to riboflavin down to pM levels.

Controlling the dimensionality of charge transport in organic thin-film transistors

Science.gov (United States)

Laiho, Ari; Herlogsson, Lars; Forchheimer, Robert; Crispin, Xavier; Berggren, Magnus

2011-01-01

Electrolyte-gated organic thin-film transistors (OTFTs) can offer a feasible platform for future flexible, large-area and low-cost electronic applications. These transistors can be divided into two groups on the basis of their operation mechanism: (i) field-effect transistors that switch fast but carry much less current than (ii) the electrochemical transistors which, on the contrary, switch slowly. An attractive approach would be to combine the benefits of the field-effect and the electrochemical transistors into one transistor that would both switch fast and carry high current densities. Here we report the development of a polyelectrolyte-gated OTFT based on conjugated polyelectrolytes, and we demonstrate that the OTFTs can be controllably operated either in the field-effect or the electrochemical regime. Moreover, we show that the extent of electrochemical doping can be restricted to a few monolayers of the conjugated polyelectrolyte film, which allows both high current densities and fast switching speeds at the same time. We propose an operation mechanism based on self-doping of the conjugated polyelectrolyte backbone by its ionic side groups. PMID:21876143

Performance Enhancement of Power Transistors and Radiation effect

International Nuclear Information System (INIS)

Hassn, Th.A.A.

2012-01-01

The main objective of this scientific research is studying the characteristic of bipolar junction transistor device and its performance under radiation fields and temperature effect as a control element in many power circuits. In this work we present the results of experimental measurements and analytical simulation of gamma – radiation effects on the electrical characteristics and operation of power transistor types 2N3773, 2N3055(as complementary silicon power transistor are designed for general-purpose switching and amplifier applications), three samples of each type were irradiated by gamma radiation with doses, 1 K rad, 5 K rad, 10 K rad, 30 K rad, and 10 Mrad, the experimental data are utilized to establish an analytical relation between the total absorbed dose of gamma irradiation and corresponding to effective density of generated charge in the internal structure of transistor, the electrical parameters which can be measured to estimate the generated defects in the power transistor are current gain, collector current and collected emitter leakage current , these changes cause the circuit to case proper functioning. Collector current and transconductance of each device are calibrated as a function of irradiated dose. Also the threshold voltage and transistor gain can be affected and also calibrated as a function of dose. A silicon NPN power transistor type 2N3773 intended for general purpose applications, were used in this work. It was designed for medium current and high power circuits. Performance and characteristic were discusses under temperature and gamma radiation doses. Also the internal junction thermal system of the transistor represented in terms of a junction thermal resistance (Rjth). The thermal resistance changed by ΔRjth, due to the external intended, also due to the gamma doses intended. The final result from the model analysis reveals that the emitter-bias configuration is quite stable by resistance ratio RB/RE. Also the current

Interface-controlled, high-mobility organic transistors

NARCIS (Netherlands)

Jurchescu, Oana D.; Popinciuc, Mihaita; van Wees, Bart J.; Palstra, Thomas T. M.

2007-01-01

The achievement of high mobilities in field-effect transistors (FETs) is one of the main challenges for the widespread application of organic conductors in devices. Good device performance of a single-crystal pentacene FET requires both removal of impurity molecules from the bulk and the

Improving the Stability of High-Performance Multilayer MoS2 Field-Effect Transistors.

Science.gov (United States)

Liu, Na; Baek, Jongyeol; Kim, Seung Min; Hong, Seongin; Hong, Young Ki; Kim, Yang Soo; Kim, Hyun-Suk; Kim, Sunkook; Park, Jozeph

2017-12-13

In this study, we propose a method for improving the stability of multilayer MoS 2 field-effect transistors (FETs) by O 2 plasma treatment and Al 2 O 3 passivation while sustaining the high performance of bulk MoS 2 FET. The MoS 2 FETs were exposed to O 2 plasma for 30 s before Al 2 O 3 encapsulation to achieve a relatively small hysteresis and high electrical performance. A MoO x layer formed during the plasma treatment was found between MoS 2 and the top passivation layer. The MoO x interlayer prevents the generation of excess electron carriers in the channel, owing to Al 2 O 3 passivation, thereby minimizing the shift in the threshold voltage (V th ) and increase of the off-current leakage. However, prolonged exposure of the MoS 2 surface to O 2 plasma (90 and 120 s) was found to introduce excess oxygen into the MoO x interlayer, leading to more pronounced hysteresis and a high off-current. The stable MoS 2 FETs were also subjected to gate-bias stress tests under different conditions. The MoS 2 transistors exhibited negligible decline in performance under positive bias stress, positive bias illumination stress, and negative bias stress, but large negative shifts in V th were observed under negative bias illumination stress, which is attributed to the presence of sulfur vacancies. This simple approach can be applied to other transition metal dichalcogenide materials to understand their FET properties and reliability, and the resulting high-performance hysteresis-free MoS 2 transistors are expected to open up new opportunities for the development of sophisticated electronic applications.

Accurate characterization of organic thin film transistors in the presence of gate leakage current

Directory of Open Access Journals (Sweden)

Vinay K. Singh

2011-12-01

Full Text Available The presence of gate leakage through polymer dielectric in organic thin film transistors (OTFT prevents accurate estimation of transistor characteristics especially in subthreshold regime. To mitigate the impact of gate leakage on transfer characteristics and allow accurate estimation of mobility, subthreshold slope and on/off current ratio, a measurement technique involving simultaneous sweep of both gate and drain voltages is proposed. Two dimensional numerical device simulation is used to illustrate the validity of the proposed technique. Experimental results obtained with Pentacene/PMMA OTFT with significant gate leakage show a low on/off current ratio of ∼ 102 and subthreshold is 10 V/decade obtained using conventional measurement technique. The proposed technique reveals that channel on/off current ratio is more than two orders of magnitude higher at ∼104 and subthreshold slope is 4.5 V/decade.

High-performance a-IGZO thin-film transistor with conductive indium-tin-oxide buried layer

Science.gov (United States)

Ahn, Min-Ju; Cho, Won-Ju

2017-10-01

In this study, we fabricated top-contact top-gate (TCTG) structure of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with a thin buried conductive indium-tin oxide (ITO) layer. The electrical performance of a-IGZO TFTs was improved by inserting an ITO buried layer under the IGZO channel. Also, the effect of the buried layer's length on the electrical characteristics of a-IGZO TFTs was investigated. The electrical performance of the transistors improved with increasing the buried layer's length: a large on/off current ratio of 1.1×107, a high field-effect mobility of 35.6 cm2/Vs, a small subthreshold slope of 116.1 mV/dec, and a low interface trap density of 4.2×1011 cm-2eV-1 were obtained. The buried layer a-IGZO TFTs exhibited enhanced transistor performance and excellent stability against the gate bias stress.

Revisiting the role of trap-assisted-tunneling process on current-voltage characteristics in tunnel field-effect transistors

Science.gov (United States)

Omura, Yasuhisa; Mori, Yoshiaki; Sato, Shingo; Mallik, Abhijit

2018-04-01

This paper discusses the role of trap-assisted-tunneling process in controlling the ON- and OFF-state current levels and its impacts on the current-voltage characteristics of a tunnel field-effect transistor. Significant impacts of high-density traps in the source region are observed that are discussed in detail. With regard to recent studies on isoelectronic traps, it has been discovered that deep level density must be minimized to suppress the OFF-state leakage current, as is well known, whereas shallow levels can be utilized to control the ON-state current level. A possible mechanism is discussed based on simulation results.

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

Science.gov (United States)

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

Wavy channel transistor for area efficient high performance operation

KAUST Repository

Fahad, Hossain M.; Hussain, Aftab M.; Hussain, Muhammad Mustafa; Sevilla, Galo T.

2013-01-01

We report a wavy channel FinFET like transistor where the channel is wavy to increase its width without any area penalty and thereby increasing its drive current. Through simulation and experiments, we show the effectiveness of such device

Effect of germanium concentrations on tunnelling current calculation of Si/Si1-xGex/Si heterojunction bipolar transistor

Science.gov (United States)

Hasanah, L.; Suhendi, E.; Khairrurijal

2018-05-01

Tunelling current calculation on Si/Si1-xGex/Si heterojunction bipolar transistor was carried out by including the coupling between transversal and longitudinal components of electron motion. The calculation results indicated that the coupling between kinetic energy in parallel and perpendicular to S1-xGex barrier surface affected tunneling current significantly when electron velocity was faster than 1x105 m/s. This analytical tunneling current model was then used to study how the germanium concentration in base to Si/Si1-xGex/Si heterojunction bipolar transistor influenced the tunneling current. It is obtained that tunneling current increased as the germanium concentration given in base decreased.

Charge fluctuations in high-electron-mobility transistors: a review

International Nuclear Information System (INIS)

Green, F.

1993-01-01

The quasi-two-dimensional carrier population, free to move within a near-perfect crystalline matrix, is the key to remarkable improvements in signal gain, current density and quiet operation. Current-fluctuation effects are central to all of these properties. Some of these are easily understood within linear-response theory, but other fluctuation phenomena are less tractable. In particular, nonequilibrium noise poses significant theoretical challenges, both descriptive and predictive. This paper examines a few of the basic physical issues which motivate device-noise theory. The structure and operation of high-electron-mobility transistor are first reviewed. The recent nonlinear fluctuation theory of Stanton and Wilkins (1987) help to identify at least some of the complicated noise physics which can arise when carriers in GaAs-like conduction bands are subjected to high fields. Simple examples of fluctuation-dominated behaviour are discussed, with numerical illustrations. 20 refs., 9 figs

Analysis of Co-Tunneling Current in Fullerene Single-Electron Transistor

Science.gov (United States)

KhademHosseini, Vahideh; Dideban, Daryoosh; Ahmadi, MohammadTaghi; Ismail, Razali

2018-05-01

Single-electron transistors (SETs) are nano devices which can be used in low-power electronic systems. They operate based on coulomb blockade effect. This phenomenon controls single-electron tunneling and it switches the current in SET. On the other hand, co-tunneling process increases leakage current, so it reduces main current and reliability of SET. Due to co-tunneling phenomenon, main characteristics of fullerene SET with multiple islands are modelled in this research. Its performance is compared with silicon SET and consequently, research result reports that fullerene SET has lower leakage current and higher reliability than silicon counterpart. Based on the presented model, lower co-tunneling current is achieved by selection of fullerene as SET island material which leads to smaller value of the leakage current. Moreover, island length and the number of islands can affect on co-tunneling and then they tune the current flow in SET.

Investigation on pseudomorphic InGaAs/InAlAs/InP High Electron Mobility Transistors with regard to cryogenic applications

International Nuclear Information System (INIS)

Toennesmann, A.

2003-03-01

A wide variety of new data communication applications demand ever-increasing transmission capacities. The InGaAs/InAlAs/InP layer stack based high electron mobility transistor (HEMT) is currently regarded as the most promising active device in communication systems as it has the highest cut-off frequencies of all transistor types. Due to reduced phonon scattering of the charge carriers, the HEMT is expected to exhibit even better noise and high frequency characteristics for operations at cryogenic temperatures, for instance in mixers or oscillators located in satellites or ground based systems with appropriate cooling equipment. This work focuses on the reduction of access resistances and the fabrication of very short gate lengths as the biggest technological challenges realizing highest cut-off frequencies at any temperature. In addition, the reproducibility and robustness of the implemented gate technologies are fundamental criteria for applications. In comparison to other transistor designs, the InAlAs/InGaAs HEMTs are stronger affected by undesirable, partly material dependent, short channel effects like early breakdown, high gate currents, impact ionization, the kink effect, and a shift in the threshold voltage. Measurements at liquid nitrogen temperature on transistors produced in this work provide further insight into the poorly understood interrelationship between these effects. At liquid nitrogen temperature, the cut-off frequency of 180 GHz and the maximum oscillation frequency of 300 GHz of short channel transistors at room temperature increase by 20% and 30%, respectively, while the breakdown voltage remains at high values above 8 V. (orig.)

Shootthrough fault protection system for bipolar transistors in a voltage source transistor inverter

International Nuclear Information System (INIS)

Wirth, W.F.

1982-01-01

Faulted bipolar transistors in a voltage source transistor inverter are protected against shootthrough fault current, from the filter capacitor of the d-c voltage source which drives the inverter over the d-c bus, by interposing a small choke in series with the filter capacitor to limit the rate of rise of that fault current while at the same time causing the d-c bus voltage to instantly drop to essentially zero volts at the beginning of a shootthrough fault. In this way, the load lines of the faulted transistors are effectively shaped so that they do not enter the second breakdown area, thereby preventing second breakdown destruction of the transistors

Current collapse imaging of Schottky gate AlGaN/GaN high electron mobility transistors by electric field-induced optical second-harmonic generation measurement

International Nuclear Information System (INIS)

Katsuno, Takashi; Ishikawa, Tsuyoshi; Ueda, Hiroyuki; Uesugi, Tsutomu; Manaka, Takaaki; Iwamoto, Mitsumasa

2014-01-01

Two-dimensional current collapse imaging of a Schottky gate AlGaN/GaN high electron mobility transistor device was achieved by optical electric field-induced second-harmonic generation (EFISHG) measurements. EFISHG measurements can detect the electric field produced by carriers trapped in the on-state of the device, which leads to current collapse. Immediately after (e.g., 1, 100, or 800 μs) the completion of drain-stress voltage (200 V) in the off-state, the second-harmonic (SH) signals appeared within 2 μm from the gate edge on the drain electrode. The SH signal intensity became weak with time, which suggests that the trapped carriers are emitted from the trap sites. The SH signal location supports the well-known virtual gate model for current collapse.

Ultra Low Voltage Class AB Switched Current Memory Cells Based on Floating Gate Transistors

DEFF Research Database (Denmark)

Mucha, Igor

1999-01-01

current memory cells were designed using a CMOS process with threshold voltages V-T0n = \\V-T0p\\ = 0.9 V for the n- and p-channel devices. Both hand calculations and PSPICE simulations showed that the designed example switched current memory cell allowed a maximum signal range better than +/-18 mu......A proposal for a class AB switched current memory cell, suitable for ultra-low-voltage applications is presented. The proposal employs transistors with floating gates, allowing to build analog building blocks for ultralow supply voltage operation also in CMOS processes with high threshold voltages....... This paper presents the theoretical basis for the design of "floating-gate'' switched current memory cells by giving a detailed description and analysis of the most important impacts degrading the performance of the cells. To support the theoretical assumptions circuits based on "floating-gate'' switched...

Strain-effect transistors: Theoretical study on the effects of external strain on III-nitride high-electron-mobility transistors on flexible substrates

Energy Technology Data Exchange (ETDEWEB)

Shervin, Shahab; Asadirad, Mojtaba [Department of Mechanical Engineering, University of Houston, Houston, Texas 77204-4006 (United States); Materials Science and Engineering Program, University of Houston, Houston, Texas 77204 (United States); Kim, Seung-Hwan; Ravipati, Srikanth; Lee, Keon-Hwa [Department of Mechanical Engineering, University of Houston, Houston, Texas 77204-4006 (United States); Bulashevich, Kirill [STR Group, Inc., Engels av. 27, P.O. Box 89, 194156, St. Petersburg (Russian Federation); Ryou, Jae-Hyun, E-mail: jryou@uh.edu [Department of Mechanical Engineering, University of Houston, Houston, Texas 77204-4006 (United States); Materials Science and Engineering Program, University of Houston, Houston, Texas 77204 (United States); Texas Center for Superconductivity at the University of Houston (TcSUH), University of Houston, Houston, Texas 77204 (United States)

2015-11-09

This paper presents strain-effect transistors (SETs) based on flexible III-nitride high-electron-mobility transistors (HEMTs) through theoretical calculations. We show that the electronic band structures of InAlGaN/GaN thin-film heterostructures on flexible substrates can be modified by external bending with a high degree of freedom using polarization properties of the polar semiconductor materials. Transfer characteristics of the HEMT devices, including threshold voltage and transconductance, are controlled by varied external strain. Equilibrium 2-dimensional electron gas (2DEG) is enhanced with applied tensile strain by bending the flexible structure with the concave-side down (bend-down condition). 2DEG density is reduced and eventually depleted with increasing compressive strain in bend-up conditions. The operation mode of different HEMT structures changes from depletion- to enchantment-mode or vice versa depending on the type and magnitude of external strain. The results suggest that the operation modes and transfer characteristics of HEMTs can be engineered with an optimum external bending strain applied in the device structure, which is expected to be beneficial for both radio frequency and switching applications. In addition, we show that drain currents of transistors based on flexible InAlGaN/GaN can be modulated only by external strain without applying electric field in the gate. The channel conductivity modulation that is obtained by only external strain proposes an extended functional device, gate-free SETs, which can be used in electro-mechanical applications.

Universal power transistor base drive control unit

Science.gov (United States)

Gale, Allan R.; Gritter, David J.

1988-01-01

A saturation condition regulator system for a power transistor which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition.

Current Analysis and Modeling of Fullerene Single-Electron Transistor at Room Temperature

Science.gov (United States)

Khadem Hosseini, Vahideh; Ahmadi, Mohammad Taghi; Afrang, Saeid; Ismail, Razali

2017-07-01

Single-electron transistors (SETs) are interesting electronic devices that have become key elements in modern nanoelectronic systems. SETs operate quickly because they use individual electrons, with the number transferred playing a key role in their switching behavior. However, rapid transmission of electrons can cause their accumulation at the island, affecting the I- V characteristic. Selection of fullerene as a nanoscale zero-dimensional material with high stability, and controllable size in the fabrication process, can overcome this charge accumulation issue and improve the reliability of SETs. Herein, the current in a fullerene SET is modeled and compared with experimental data for a silicon SET. Furthermore, a weaker Coulomb staircase and improved reliability are reported. Moreover, the applied gate voltage and fullerene diameter are found to be directly associated with the I- V curve, enabling the desired current to be achieved by controlling the fullerene diameter.

Synergetic effects of radiation stress and hot-carrier stress on the current gain of npn bipolar junction transistors

International Nuclear Information System (INIS)

Witczak, S.C.; Kosier, S.L.; Schrimpf, R.D.; Galloway, K.F.

1994-01-01

The combined effects of ionizing radiation and hot-carrier stress on the current gain of npn bipolar junction transistors were investigated. The analysis was carried out experimentally by examining the consequences of interchanging the order in which the two stress types were applied to identical transistors which were stressed to various levels of damage. The results indicate that the hot-carrier response of the transistor is improved by radiation damage, whereas hot-carrier damage has little effect on subsequent radiation stress. Characterization of the temporal progression of hot-carrier effects revealed that hot-carrier stress acts initially to reduce excess base current and improve current gain in irradiated transistors. PISCES simulations show that the magnitude of the peak electric-field within the emitter-base depletion region is reduced significantly by net positive oxide charges induced by radiation. The interaction of the two stress types is explained in a qualitative model based on the probability of hot-carrier injection determined by radiation damage and on the neutralization and compensation of radiation-induced positive oxide charges by injected electrons. The result imply that a bound on damage due to the combined stress types is achieved when hot-carrier stress precedes any irradiation

Irradiation of graphene field effect transistors with highly charged ions

Energy Technology Data Exchange (ETDEWEB)

Ernst, P.; Kozubek, R.; Madauß, L.; Sonntag, J.; Lorke, A.; Schleberger, M., E-mail: marika.schleberger@uni-due.de

2016-09-01

In this work, graphene field-effect transistors are used to detect defects due to irradiation with slow, highly charged ions. In order to avoid contamination effects, a dedicated ultra-high vacuum set up has been designed and installed for the in situ cleaning and electrical characterization of graphene field-effect transistors during irradiation. To investigate the electrical and structural modifications of irradiated graphene field-effect transistors, their transfer characteristics as well as the corresponding Raman spectra are analyzed as a function of ion fluence for two different charge states. The irradiation experiments show a decreasing mobility with increasing fluences. The mobility reduction scales with the potential energy of the ions. In comparison to Raman spectroscopy, the transport properties of graphene show an extremely high sensitivity with respect to ion irradiation: a significant drop of the mobility is observed already at fluences below 15 ions/μm{sup 2}, which is more than one order of magnitude lower than what is required for Raman spectroscopy.

Ultrashort Channel Length Black Phosphorus Field-Effect Transistors.

Science.gov (United States)

Miao, Jinshui; Zhang, Suoming; Cai, Le; Scherr, Martin; Wang, Chuan

2015-09-22

This paper reports high-performance top-gated black phosphorus (BP) field-effect transistors with channel lengths down to 20 nm fabricated using a facile angle evaporation process. By controlling the evaporation angle, the channel length of the transistors can be reproducibly controlled to be anywhere between 20 and 70 nm. The as-fabricated 20 nm top-gated BP transistors exhibit respectable on-state current (174 μA/μm) and transconductance (70 μS/μm) at a VDS of 0.1 V. Due to the use of two-dimensional BP as the channel material, the transistors exhibit relatively small short channel effects, preserving a decent on-off current ratio of 10(2) even at an extremely small channel length of 20 nm. Additionally, unlike the unencapsulated BP devices, which are known to be chemically unstable in ambient conditions, the top-gated BP transistors passivated by the Al2O3 gate dielectric layer remain stable without noticeable degradation in device performance after being stored in ambient conditions for more than 1 week. This work demonstrates the great promise of atomically thin BP for applications in ultimately scaled transistors.

Carbon nanotube feedback-gate field-effect transistor: suppressing current leakage and increasing on/off ratio.

Science.gov (United States)

Qiu, Chenguang; Zhang, Zhiyong; Zhong, Donglai; Si, Jia; Yang, Yingjun; Peng, Lian-Mao

2015-01-27

Field-effect transistors (FETs) based on moderate or large diameter carbon nanotubes (CNTs) usually suffer from ambipolar behavior, large off-state current and small current on/off ratio, which are highly undesirable for digital electronics. To overcome these problems, a feedback-gate (FBG) FET structure is designed and tested. This FBG FET differs from normal top-gate FET by an extra feedback-gate, which is connected directly to the drain electrode of the FET. It is demonstrated that a FBG FET based on a semiconducting CNT with a diameter of 1.5 nm may exhibit low off-state current of about 1 × 10(-13) A, high current on/off ratio of larger than 1 × 10(8), negligible drain-induced off-state leakage current, and good subthreshold swing of 75 mV/DEC even at large source-drain bias and room temperature. The FBG structure is promising for CNT FETs to meet the standard for low-static-power logic electronics applications, and could also be utilized for building FETs using other small band gap semiconductors to suppress leakage current.

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

Science.gov (United States)

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Planar transistors and impatt diodes with ion implantation

International Nuclear Information System (INIS)

Dorendorf, H.; Glawischnig, H.; Grasser, L.; Hammerschmitt, J.

1975-03-01

Low frequency planar npn and pnp transistors have been developed in which the base and emitter have been fabricated using ion implantation of boron and phosphorus by a drive-in diffusion. Electrical parameters of the transistors are comparable with conventionally produced transistors; the noise figure was improved and production tolerances were significantly reduced. Silicon-impatt diodes for the microwave range were also fabricated with implanted pn junctions and tested for their high frequency characteristics. These diodes, made in an improved upside down technology, delivered output power up to 40 mW (burn out power) at 30 GHz. Reverse leakage current and current carrying capability of these diodes were comparable to diffused structures. (orig.) 891 ORU 892 MB [de

Transistor-based particle detection systems and methods

Science.gov (United States)

Jain, Ankit; Nair, Pradeep R.; Alam, Muhammad Ashraful

2015-06-09

Transistor-based particle detection systems and methods may be configured to detect charged and non-charged particles. Such systems may include a supporting structure contacting a gate of a transistor and separating the gate from a dielectric of the transistor, and the transistor may have a near pull-in bias and a sub-threshold region bias to facilitate particle detection. The transistor may be configured to change current flow through the transistor in response to a change in stiffness of the gate caused by securing of a particle to the gate, and the transistor-based particle detection system may configured to detect the non-charged particle at least from the change in current flow.

Carbon nanotube transistor based high-frequency electronics

Science.gov (United States)

Schroter, Michael

At the nanoscale carbon nanotubes (CNTs) have higher carrier mobility and carrier velocity than most incumbent semiconductors. Thus CNT based field-effect transistors (FETs) are being considered as strong candidates for replacing existing MOSFETs in digital applications. In addition, the predicted high intrinsic transit frequency and the more recent finding of ways to achieve highly linear transfer characteristics have inspired investigations on analog high-frequency (HF) applications. High linearity is extremely valuable for an energy efficient usage of the frequency spectrum, particularly in mobile communications. Compared to digital applications, the much more relaxed constraints for CNT placement and lithography combined with already achieved operating frequencies of at least 10 GHz for fabricated devices make an early entry in the low GHz HF market more feasible than in large-scale digital circuits. Such a market entry would be extremely beneficial for funding the development of production CNTFET based process technology. This talk will provide an overview on the present status and feasibility of HF CNTFET technology will be given from an engineering point of view, including device modeling, experimental results, and existing roadblocks. Carbon nanotube transistor based high-frequency electronics.

Development and characterization of vertical double-gate MOS field-effect transistors

International Nuclear Information System (INIS)

Trellenkamp, S.

2004-07-01

Planar MOS-field-effect transistors are common devices today used by the computer industry. When their miniaturization reaches its limit, alternate transistor concepts become necessary. In this thesis the development of vertical Double-Gate-MOS-field-effect transistors is presented. These types of transistors have a vertically aligned p-n-p junction (or n-p-n junction, respectively). Consequently, the source-drain current flows perpendicular with respect to the surface of the wafer. A Double-Gate-field-effect transistor is characterized by a very thin channel region framed by two parallel gates. Due to the symmetry of the structure and less bulk volume better gate control and hence better short channel behavior is expected, as well as an improved scaling potential. Nanostructuring of the transistor's active region is very challenging. Approximately 300 nm high and down to 30 nm wide silicon ridges are requisite. They can be realized using hydrogen silsesquioxane (HSQ) as inorganic high resolution resist for electron beam lithography. Structures defined in HSQ are then transferred with high anisotropy and selectivity into silicon using ICP-RIE (reactive ion etching with inductive coupled plasma). 25 nm wide and 330 nm high silicon ridges are achieved. Different transistor layouts are realized. The channel length is defined by epitaxial growth of doped silicon layers before or by ion implantation after nanostructuring, respectively. The transistors show source-drain currents up to 380 μA/μm and transconductances up to 480 μS/μm. Improved short channel behavior for decreasing width of the silicon ridges is demonstrated. (orig.)

Sub-50 nm gate length SOI transistor development for high performance microprocessors

International Nuclear Information System (INIS)

Horstmann, M.; Greenlaw, D.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, R. van; Grasshoff, G.; Schwan, C.; Cheek, J.; Buller, J.; Krishnan, S.; Raab, M.; Kepler, N.

2004-01-01

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI

Wavy channel Thin Film Transistor for area efficient, high performance and low power applications

KAUST Repository

Hanna, Amir

2014-06-01

We report a new Thin Film Transistor (TFT) architecture that allows expansion of the device width using wavy (continuous without separation) fin features - termed as wavy channel (WC) architecture. This architecture allows expansion of transistor width in a direction perpendicular to the substrate, thus not consuming extra chip area, achieving area efficiency. The devices have shown for a 13% increase in the device width resulting in a maximum 2.4x increase in \\'ON\\' current value of the WCTFT, when compared to planar devices consuming the same chip area, while using atomic layer deposition based zinc oxide (ZnO) as the channel material. The WCTFT devices also maintain similar \\'OFF\\' current value, similar to 100 pA, when compared to planar devices, thus not compromising on power consumption for performance which usually happens with larger width devices. This work offers a pragmatic opportunity to use WCTFTs as backplane circuitry for large-area high-resolution display applications without any limitation any TFT materials.

High-performance indium gallium phosphide/gallium arsenide heterojunction bipolar transistors

Science.gov (United States)

Ahmari, David Abbas

Heterojunction bipolar transistors (HBTs) have demonstrated the high-frequency characteristics as well as the high linearity, gain, and power efficiency necessary to make them attractive for a variety of applications. Specific applications for which HBTs are well suited include amplifiers, analog-to-digital converters, current sources, and optoelectronic integrated circuits. Currently, most commercially available HBT-based integrated circuits employ the AlGaAs/GaAs material system in applications such as a 4-GHz gain block used in wireless phones. As modern systems require higher-performance and lower-cost devices, HBTs utilizing the newer, InGaP/GaAs and InP/InGaAs material systems will begin to dominate the HBT market. To enable the widespread use of InGaP/GaAs HBTs, much research on the fabrication, performance, and characterization of these devices is required. This dissertation will discuss the design and implementation of high-performance InGaP/GaAs HBTs as well as study HBT device physics and characterization.

Base profile design for high-performance operation of bipolar transistors at liquid-nitrogen temperature

International Nuclear Information System (INIS)

Stork, J.M.C.; Harame, D.L.; Meyerson, B.S.; Nguyen, T.N.

1989-01-01

The base profile requirements of Si bipolar junction transistors (BJT's) high-performance operation at liquid-nitrogen temperature are examined. Measurements of thin epitaxial-base polysilicon-emitter n-p-n transistors with increasing base doping show the effects of bandgap narrowing, mobility changes, and carrier freezeout. At room temperature the collector current at low injection is proportional to the integrated base charge, independent of the impurity distribution. At temperatures below 150 Κ, however, minority injection is dominated by the peak base doping because of the greater effectiveness of bandgap narrowing. When the peak doping in the base approaches 10 19 cm -3 , the bandgap difference between emitter and base is sufficiently small that the current gain no longer monotonically decreases with lower temperature but instead shows a maximum as low as 180 Κ. The device design window appears limited at the low-current end by increased base-emitter leakage due to tunneling and by resistance control at the high-current end. Using the measured dc characteristics, circuit delay calculations are made to estimate the performance of an ECL ring oscillator at room and liquid-nitrogen temperatures. It is shown that if the base doping can be raised to 10 19 cm -3 while keeping the base thickness constant, the minimum delay at liquid nitrogen can approach the delay of optimized devices at room temperature

Ultrasensitive detection of Hg{sup 2+} using oligonucleotide-functionalized AlGaN/GaN high electron mobility transistor

Energy Technology Data Exchange (ETDEWEB)

Cheng, Junjie [Key Laboratory of Ion Beam Bioengineering, Hefei Institutes of Physical Science, Chinese Academy of Sciences, Hefei 230031 (China); Division of Nanobiomedicine, Key Laboratory for Nano-Bio Interface Research, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences, Suzhou 215123 (China); Li, Jiadong; Miao, Bin; Wu, Dongmin, E-mail: dmwu2008@sinano.ac.cn [i-Lab, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences, Suzhou 215125 (China); Key Laboratory of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences, Suzhou 215123 (China); Wang, Jine; Pei, Renjun, E-mail: rjpei2011@sinano.ac.cn [Division of Nanobiomedicine, Key Laboratory for Nano-Bio Interface Research, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences, Suzhou 215123 (China); Wu, Zhengyan, E-mail: zywu@ipp.ac.cn [Key Laboratory of Ion Beam Bioengineering, Hefei Institutes of Physical Science, Chinese Academy of Sciences, Hefei 230031 (China)

2014-08-25

An oligonucleotide-functionalized ion sensitive AlGaN/GaN high electron mobility transistor (HEMT) was fabricated to detect trace amounts of Hg{sup 2+}. The advantages of ion sensitive AlGaN/GaN HEMT and highly specific binding interaction between Hg{sup 2+} and thymines were combined. The current response of this Hg{sup 2+} ultrasensitive transistor was characterized. The current increased due to the accumulation of Hg{sup 2+} ions on the surface by the highly specific thymine-Hg{sup 2+}-thymine recognition. The dynamic linear range for Hg{sup 2+} detection has been determined in the concentrations from 10{sup −14} to 10{sup −8} M and a detection limit below 10{sup −14} M level was estimated, which is the best result of AlGaN/GaN HEMT biosensors for Hg{sup 2+} detection till now.

Measurement of low-frequency base and collector current noise and coherence in SiGe heterojunction bipolar transistors using transimpedance amplifiers

NARCIS (Netherlands)

Bruce, S.P.O.; Vandamme, L.K.J.; Rydberg, A.

1999-01-01

Transimpedance amplifiers have been used for direct study of current noise in silicon germanium (SiGe) heterojunction bipolar transistors (HBT's) at different biasing conditions. This has facilitated a wider range of resistances in the measurement circuit around the transistor than is possible when

A self-amplified transistor immunosensor under dual gate operation: highly sensitive detection of hepatitis B surface antigen

Science.gov (United States)

Lee, I.-K.; Jeun, M.; Jang, H.-J.; Cho, W.-J.; Lee, K. H.

2015-10-01

Ion-sensitive field-effect transistors (ISFETs), although they have attracted considerable attention as effective immunosensors, have still not been adopted for practical applications owing to several problems: (1) the poor sensitivity caused by the short Debye screening length in media with high ion concentration, (2) time-consuming preconditioning processes for achieving the highly-diluted media, and (3) the low durability caused by undesirable ions such as sodium chloride in the media. Here, we propose a highly sensitive immunosensor based on a self-amplified transistor under dual gate operation (immuno-DG ISFET) for the detection of hepatitis B surface antigen. To address the challenges in current ISFET-based immunosensors, we have enhanced the sensitivity of an immunosensor by precisely tailoring the nanostructure of the transistor. In the pH sensing test, the immuno-DG ISFET showed superior sensitivity (2085.53 mV per pH) to both standard ISFET under single gate operation (58.88 mV per pH) and DG ISFET with a non-tailored transistor (381.14 mV per pH). Moreover, concerning the detection of hepatitis B surface antigens (HBsAg) using the immuno-DG ISFET, we have successfully detected trace amounts of HBsAg (22.5 fg mL-1) in a non-diluted 1× PBS medium with a high sensitivity of 690 mV. Our results demonstrate that the proposed immuno-DG ISFET can be a biosensor platform for practical use in the diagnosis of various diseases.Ion-sensitive field-effect transistors (ISFETs), although they have attracted considerable attention as effective immunosensors, have still not been adopted for practical applications owing to several problems: (1) the poor sensitivity caused by the short Debye screening length in media with high ion concentration, (2) time-consuming preconditioning processes for achieving the highly-diluted media, and (3) the low durability caused by undesirable ions such as sodium chloride in the media. Here, we propose a highly sensitive immunosensor

Pushing the Performance Limit of Sub-100 nm Molybdenum Disulfide Transistors.

Science.gov (United States)

Liu, Yuan; Guo, Jian; Wu, Yecun; Zhu, Enbo; Weiss, Nathan O; He, Qiyuan; Wu, Hao; Cheng, Hung-Chieh; Xu, Yang; Shakir, Imran; Huang, Yu; Duan, Xiangfeng

2016-10-12

Two-dimensional semiconductors (2DSCs) such as molybdenum disulfide (MoS 2 ) have attracted intense interest as an alternative electronic material in the postsilicon era. However, the ON-current density achieved in 2DSC transistors to date is considerably lower than that of silicon devices, and it remains an open question whether 2DSC transistors can offer competitive performance. A high current device requires simultaneous minimization of the contact resistance and channel length, which is a nontrivial challenge for atomically thin 2DSCs, since the typical low contact resistance approaches for 2DSCs either degrade the electronic properties of the channel or are incompatible with the fabrication process for short channel devices. Here, we report a new approach toward high-performance MoS 2 transistors by using a physically assembled nanowire as a lift-off mask to create ultrashort channel devices with pristine MoS 2 channel and self-aligned low resistance metal/graphene hybrid contact. With the optimized contact in short channel devices, we demonstrate sub-100 nm MoS 2 transistor delivering a record high ON-current of 0.83 mA/μm at 300 K and 1.48 mA/μm at 20 K, which compares well with that of silicon devices. Our study, for the first time, demonstrates that the 2DSC transistors can offer comparable performance to the 2017 target for silicon transistors in International Technology Roadmap for Semiconductors (ITRS), marking an important milestone in 2DSC electronics.

Highly Conductive Graphene/Ag Hybrid Fibers for Flexible Fiber-Type Transistors.

Science.gov (United States)

Yoon, Sang Su; Lee, Kang Eun; Cha, Hwa-Jin; Seong, Dong Gi; Um, Moon-Kwang; Byun, Joon-Hyung; Oh, Youngseok; Oh, Joon Hak; Lee, Wonoh; Lee, Jea Uk

2015-11-09

Mechanically robust, flexible, and electrically conductive textiles are highly suitable for use in wearable electronic applications. In this study, highly conductive and flexible graphene/Ag hybrid fibers were prepared and used as electrodes for planar and fiber-type transistors. The graphene/Ag hybrid fibers were fabricated by the wet-spinning/drawing of giant graphene oxide and subsequent functionalization with Ag nanoparticles. The graphene/Ag hybrid fibers exhibited record-high electrical conductivity of up to 15,800 S cm(-1). As the graphene/Ag hybrid fibers can be easily cut and placed onto flexible substrates by simply gluing or stitching, ion gel-gated planar transistors were fabricated by using the hybrid fibers as source, drain, and gate electrodes. Finally, fiber-type transistors were constructed by embedding the graphene/Ag hybrid fiber electrodes onto conventional polyurethane monofilaments, which exhibited excellent flexibility (highly bendable and rollable properties), high electrical performance (μh = 15.6 cm(2) V(-1) s(-1), Ion/Ioff > 10(4)), and outstanding device performance stability (stable after 1,000 cycles of bending tests and being exposed for 30 days to ambient conditions). We believe that our simple methods for the fabrication of graphene/Ag hybrid fiber electrodes for use in fiber-type transistors can potentially be applied to the development all-organic wearable devices.

Very high channel conductivity in low-defect AlN/GaN high electron mobility transistor structures

International Nuclear Information System (INIS)

Dabiran, A. M.; Wowchak, A. M.; Osinsky, A.; Xie, J.; Hertog, B.; Cui, B.; Chow, P. P.; Look, D. C.

2008-01-01

Low defect AlN/GaN high electron mobility transistor (HEMT) structures, with very high values of electron mobility (>1800 cm 2 /V s) and sheet charge density (>3x10 13 cm -2 ), were grown by rf plasma-assisted molecular beam epitaxy (MBE) on sapphire and SiC, resulting in sheet resistivity values down to ∼100 Ω/□ at room temperature. Fabricated 1.2 μm gate devices showed excellent current-voltage characteristics, including a zero gate saturation current density of ∼1.3 A/mm and a peak transconductance of ∼260 mS/mm. Here, an all MBE growth of optimized AlN/GaN HEMT structures plus the results of thin-film characterizations and device measurements are presented

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

Science.gov (United States)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Current linearity and operation stability in Al2O3-gate AlGaN/GaN MOS high electron mobility transistors

Science.gov (United States)

Nishiguchi, Kenya; Kaneki, Syota; Ozaki, Shiro; Hashizume, Tamotsu

2017-10-01

To investigate current linearity and operation stability of metal-oxide-semiconductor (MOS) AlGaN/GaN high electron mobility transistors (HEMTs), we have fabricated and characterized the Al2O3-gate MOS-HEMTs without and with a bias annealing in air at 300 °C. Compared with the as-fabricated (unannealed) MOS HEMTs, the bias-annealed devices showed improved linearity of I D-V G curves even in the forward bias regime, resulting in increased maximum drain current. Lower subthreshold slope was also observed after bias annealing. From the precise capacitance-voltage analysis on a MOS diode fabricated on the AlGaN/GaN heterostructure, it was found that the bias annealing effectively reduced the state density at the Al2O3/AlGaN interface. This led to efficient modulation of the AlGaN surface potential close to the conduction band edge, resulting in good gate control of two-dimensional electron gas density even at forward bias. In addition, the bias-annealed MOS HEMT showed small threshold voltage shift after applying forward bias stress and stable operation even at high temperatures.

Total dose induced latch in short channel NMOS/SOI transistors

International Nuclear Information System (INIS)

Ferlet-Cavrois, V.; Quoizola, S.; Musseau, O.; Flament, O.; Leray, J.L.; Pelloie, J.L.; Raynaud, C.; Faynot, O.

1998-01-01

A latch effect induced by total dose irradiation is observed in short channel SOI transistors. This effect appears on NMOS transistors with either a fully or a partially depleted structure. It is characterized by a hysteresis behavior of the Id-Vg characteristics at high drain bias for a given critical dose. Above this dose, the authors still observe a limited leakage current at low drain bias (0.1 V), but a high conduction current at high drain bias (2 V) as the transistor should be in the off-state. The critical dose above which the latch appears strongly depends on gate length, transistor structure (fully or partially depleted), buried oxide thickness and supply voltage. Two-dimensional (2D) numerical simulations indicate that the parasitic condition is due to the latch of the back gate transistor triggered by charge trapping in the buried oxide. To avoid the latch induced by the floating body effect, different techniques can be used: doping engineering, body contacts, etc. The study of the main parameters influencing the latch (gate length, supply voltage) shows that the scaling of technologies does not necessarily imply an increased latch sensitivity. Some technological parameters like the buried oxide hardness and thickness can be used to avoid latch, even at high cumulated dose, on highly integrated SOI technologies

High-performance ambipolar self-assembled Au/Ag nanowire based vertical quantum dot field effect transistor.

Science.gov (United States)

Song, Xiaoxian; Zhang, Yating; Zhang, Haiting; Yu, Yu; Cao, Mingxuan; Che, Yongli; Wang, Jianlong; Dai, Haitao; Yang, Junbo; Ding, Xin; Yao, Jianquan

2016-10-07

Most lateral PbSe quantum dot field effect transistors (QD FETs) show a low on current/off current (I on/I off) ratio in charge transport measurements. A new strategy to provide generally better performance is to design PbSe QD FETs with vertical architecture, in which the structure parameters can be tuned flexibly. Here, we fabricated a novel room-temperature operated vertical quantum dot field effect transistor with a channel of 580 nm, where self-assembled Au/Ag nanowires served as source transparent electrodes and PbSe quantum dots as active channels. Through investigating the electrical characterization, the ambipolar device exhibited excellent characteristics with a high I on/I off current ratio of about 1 × 10(5) and a low sub-threshold slope (0.26 V/decade) in the p-type regime. The all-solution processing vertical architecture provides a convenient way for low cost, large-area integration of the device.

T-gate aligned nanotube radio frequency transistors and circuits with superior performance.

Science.gov (United States)

Che, Yuchi; Lin, Yung-Chen; Kim, Pyojae; Zhou, Chongwu

2013-05-28

In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics.

The Complete Semiconductor Transistor and Its Incomplete Forms

International Nuclear Information System (INIS)

Jie Binbin; Sah, C.-T.

2009-01-01

This paper describes the definition of the complete transistor. For semiconductor devices, the complete transistor is always bipolar, namely, its electrical characteristics contain both electron and hole currents controlled by their spatial charge distributions. Partially complete or incomplete transistors, via coined names or/and designed physical geometries, included the 1949 Shockley p/n junction transistor (later called Bipolar Junction Transistor, BJT), the 1952 Shockley unipolar 'field-effect' transistor (FET, later called the p/n Junction Gate FET or JGFET), as well as the field-effect transistors introduced by later investigators. Similarities between the surface-channel MOS-gate FET (MOSFET) and the volume-channel BJT are illustrated. The bipolar currents, identified by us in a recent nanometer FET with 2-MOS-gates on thin and nearly pure silicon base, led us to the recognition of the physical makeup and electrical current and charge compositions of a complete transistor and its extension to other three or more terminal signal processing devices, and also the importance of the terminal contacts.

Electron density and currents of AlN/GaN high electron mobility transistors with thin GaN/AlN buffer layer

Energy Technology Data Exchange (ETDEWEB)

Bairamis, A.; Zervos, Ch.; Georgakilas, A., E-mail: alexandr@physics.uoc.gr [Microelectronics Research Group, IESL, Foundation for Research and Technology-Hellas (FORTH), P.O. Box 1385, GR-71110 Heraklion, Crete (Greece); Department of Physics, University of Crete, P.O. Box 2208, GR-71003 Heraklion, Crete (Greece); Adikimenakis, A.; Kostopoulos, A.; Kayambaki, M.; Tsagaraki, K.; Konstantinidis, G. [Microelectronics Research Group, IESL, Foundation for Research and Technology-Hellas (FORTH), P.O. Box 1385, GR-71110 Heraklion, Crete (Greece)

2014-09-15

AlN/GaN high electron mobility transistor (HEMT) structures with thin GaN/AlN buffer layer have been analyzed theoretically and experimentally, and the effects of the AlN barrier and GaN buffer layer thicknesses on two-dimensional electron gas (2DEG) density and transport properties have been evaluated. HEMT structures consisting of [300 nm GaN/ 200 nm AlN] buffer layer on sapphire were grown by plasma-assisted molecular beam epitaxy and exhibited a remarkable agreement with the theoretical calculations, suggesting a negligible influence of the crystalline defects that increase near the heteroepitaxial interface. The 2DEG density varied from 6.8 × 10{sup 12} to 2.1 × 10{sup 13} cm{sup −2} as the AlN barrier thickness increased from 2.2 to 4.5 nm, while a 4.5 nm AlN barrier would result to 3.1 × 10{sup 13} cm{sup −2} on a GaN buffer layer. The 3.0 nm AlN barrier structure exhibited the highest 2DEG mobility of 900 cm{sup 2}/Vs for a density of 1.3 × 10{sup 13} cm{sup −2}. The results were also confirmed by the performance of 1 μm gate-length transistors. The scaling of AlN barrier thickness from 1.5 nm to 4.5 nm could modify the drain-source saturation current, for zero gate-source voltage, from zero (normally off condition) to 0.63 A/mm. The maximum drain-source current was 1.1 A/mm for AlN barrier thickness of 3.0 nm and 3.7 nm, and the maximum extrinsic transconductance was 320 mS/mm for 3.0 nm AlN barrier.

Electron density and currents of AlN/GaN high electron mobility transistors with thin GaN/AlN buffer layer

International Nuclear Information System (INIS)

Bairamis, A.; Zervos, Ch.; Georgakilas, A.; Adikimenakis, A.; Kostopoulos, A.; Kayambaki, M.; Tsagaraki, K.; Konstantinidis, G.

2014-01-01

AlN/GaN high electron mobility transistor (HEMT) structures with thin GaN/AlN buffer layer have been analyzed theoretically and experimentally, and the effects of the AlN barrier and GaN buffer layer thicknesses on two-dimensional electron gas (2DEG) density and transport properties have been evaluated. HEMT structures consisting of [300 nm GaN/ 200 nm AlN] buffer layer on sapphire were grown by plasma-assisted molecular beam epitaxy and exhibited a remarkable agreement with the theoretical calculations, suggesting a negligible influence of the crystalline defects that increase near the heteroepitaxial interface. The 2DEG density varied from 6.8 × 10 12 to 2.1 × 10 13 cm −2 as the AlN barrier thickness increased from 2.2 to 4.5 nm, while a 4.5 nm AlN barrier would result to 3.1 × 10 13 cm −2 on a GaN buffer layer. The 3.0 nm AlN barrier structure exhibited the highest 2DEG mobility of 900 cm 2 /Vs for a density of 1.3 × 10 13 cm −2 . The results were also confirmed by the performance of 1 μm gate-length transistors. The scaling of AlN barrier thickness from 1.5 nm to 4.5 nm could modify the drain-source saturation current, for zero gate-source voltage, from zero (normally off condition) to 0.63 A/mm. The maximum drain-source current was 1.1 A/mm for AlN barrier thickness of 3.0 nm and 3.7 nm, and the maximum extrinsic transconductance was 320 mS/mm for 3.0 nm AlN barrier.

High-frequency, scaled graphene transistors on diamond-like carbon

NARCIS (Netherlands)

Wu, Y.; Lin, Y.M.; Bol, A.A.; Jenkins, K.A.; Xia, F.; Farmer, D.B.; Zu, Y.; Avouris, Ph.

2011-01-01

Owing to its high carrier mobility and saturation velocity, graphene has attracted enormous attention in recent years In particular, high-performance graphene transistors for radio-frequency (r.f.) applications are of great interest. Synthesis of large-scale graphene sheets of high quality and at

Analysis of transistor and snubber turn-off dynamics in high-frequency high-voltage high-power converters

Science.gov (United States)

Wilson, P. M.; Wilson, T. G.; Owen, H. A., Jr.

Dc to dc converters which operate reliably and efficiently at switching frequencies high enough to effect substantial reductions in the size and weight of converter energy storage elements are studied. A two winding current or voltage stepup (buck boost) dc-to-dc converter power stage submodule designed to operate in the 2.5-kW range, with an input voltage range of 110 to 180 V dc, and an output voltage of 250 V dc is emphasized. In order to assess the limitations of present day component and circuit technologies, a design goal switching frequency of 10 kHz was maintained. The converter design requirements represent a unique combination of high frequency, high voltage, and high power operation. The turn off dynamics of the primary circuit power switching transistor and its associated turn off snubber circuitry are investigated.

High reliability EPI-base radiation hardened power transistor

International Nuclear Information System (INIS)

Clark, L.E.; Saltich, J.L.

1978-01-01

A high-voltage power transistor is described which is able to withstand fluences as high as 3 x 10 14 neutrons per square centimeter and still be able to operate satisfactorily. The collector may be made essentially half as thick and twice as heavily doped as normally and its base is made in two regions which together are essentially four times as thick as the normal power transistor base region. The base region has a heavily doped upper region and a lower region intermediate the upper heavily doped region and the collector. The doping in the intermediate region is as close to intrinsic as possible, in any event less than about 3 x 10 15 impurities per cubic centimeter. The second base region has small width in comparison to the first base region, the ratio of the first to the second being at least about 5 to 1. The base region having the upper heavily doped region and the intermediate or lower low doped region contributes to the higher breakdown voltage which the transistor is able to withstand. The high doping of the collector region essentially lowers that portion of the breakdown voltage achieved by the collector region. Accordingly, it is necessary to transfer certain of this breakdown capability to the base region and this is achieved by using the upper region of heavily doped and an intermediate or lower region of low doping

High-k dielectrics as bioelectronic interface for field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Borstlap, D

2007-03-15

Ion-sensitive field-effect transistors (ISFETs) are employed as bioelectronic sensors for the cell-transistor coupling and for the detection of DNA sequences. For these applications, thermally grown SiO{sub 2} films are used as standard gate dielectric. In the first part of this dissertation, the suitability of high-k dielectrics was studied to increase the gate capacitance and hence the signal-to-noise ratio of bioelectronic ISFETs: Upon culturing primary rat neurons on the corresponding high-k dielectrics, Al{sub 2}O{sub 3}, yttria stabilised zirkonia (YSZ), DyScO{sub 3}, CeO{sub 2}, LaAlO{sub 3}, GdScO{sub 3} and LaScO{sub 3} proved to be biocompatible substrates. Comprehensive electrical and electrochemical current-voltage measurements and capacitance-voltage measurements were performed for the determination of the dielectric properties of the high-k dielectrics. In the second part of the dissertation, standard SiO{sub 2} ISFETs with lower input capacitance and high-k dielectric Al{sub 2}O{sub 3}, YSZ und DyScO{sub 3} ISFETs were comprehensively characterised and compared with each other regarding their signal-to-noise ratio, their ion sensitivity and their drift behaviour. The ion sensitivity measurements showed that the YSZ ISFETs were considerably more sensitive to K{sup +} and Na{sup +} ions than the SiO{sub 2}, Al{sub 2}O{sub 3} und DyScO{sub 3} ISFETs. In the final third part of the dissertation, bioelectronic experiments were performed with the high-k ISFETs. The shape of the signals, which were measured from HL-1 cells with YSZ ISFETs, differed considerably from the corresponding measurements with SiO{sub 2} and DyScO{sub 3} ISFETs: After the onset of the K{sup +} current, the action potentials measured with YSZ ISFETs showed a strong drift in the direction opposite to the K{sup +} current signal. First coupling experiments between HEK 293 cells, which were transfected with a K{sup +} ion channel, and YSZ ISFETs affirmed the assumption from the HL-1

Transistor design considerations for low-noise preamplifiers

International Nuclear Information System (INIS)

Fair, R.B.

1976-01-01

A review is presented of design considerations for GaAs Schottky-barrier FETs and other types of transistors in low-noise amplifiers for capacitive sources which are used in nuclear radiation detectors and high speed fiber-optic communication systems. Ultimate limits on performance are evaluated in terms of the g/sub m//C/sub i/ ratio and the gate leakage current to minimize the noise sources. Si bipolar transistors and the future prospects of GaAs, Si and InAs MISFETs are discussed, and performance is compared to FETs currently being used in low-noise preamplifiers

Transistors using crystalline silicon devices on glass

Science.gov (United States)

McCarthy, Anthony M.

1995-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Wavy channel thin film transistor architecture for area efficient, high performance and low power displays

KAUST Repository

Hanna, Amir

2013-12-23

We demonstrate a new thin film transistor (TFT) architecture that allows expansion of the device width using continuous fin features - termed as wavy channel (WC) architecture. This architecture allows expansion of transistor width in a direction perpendicular to the substrate, thus not consuming extra chip area, achieving area efficiency. The devices have shown for a 13% increase in the device width resulting in a maximum 2.5× increase in \\'ON\\' current value of the WCTFT, when compared to planar devices consuming the same chip area, while using atomic layer deposition based zinc oxide (ZnO) as the channel material. The WCTFT devices also maintain similar \\'OFF\\' current value, ~100 pA, when compared to planar devices, thus not compromising on power consumption for performance which usually happens with larger width devices. This work offers an interesting opportunity to use WCTFTs as backplane circuitry for large-area high-resolution display applications. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Quantitative analysis of Josephson-quasiparticle current in superconducting single-electron transistors

International Nuclear Information System (INIS)

Nakamura, Y.; Chen, C.D.; Tsai, J.S.

1996-01-01

We have investigated Josephson-quasiparticle (JQP) current in superconducting single-electron transistors in which charging energy E C was larger than superconducting gap energy Δ and junction resistances were much larger than R Q ≡h/4e 2 . We found that not only the shapes of the JQP peaks but also their absolute height were reproduced quantitatively with a theory by Averin and Aleshkin using a Josephson energy of Ambegaokar-Baratoff close-quote s value. copyright 1996 The American Physical Society

Controllable film densification and interface flatness for high-performance amorphous indium oxide based thin film transistors

Energy Technology Data Exchange (ETDEWEB)

Ou-Yang, Wei, E-mail: OUYANG.Wei@nims.go.jp, E-mail: TSUKAGOSHI.Kazuhito@nims.go.jp; Mitoma, Nobuhiko; Kizu, Takio; Gao, Xu; Lin, Meng-Fang; Tsukagoshi, Kazuhito, E-mail: OUYANG.Wei@nims.go.jp, E-mail: TSUKAGOSHI.Kazuhito@nims.go.jp [International Center for Materials Nanoarchitectronics (WPI-MANA), National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Nabatame, Toshihide [MANA Foundry and MANA Advanced Device Materials Group, National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan)

2014-10-20

To avoid the problem of air sensitive and wet-etched Zn and/or Ga contained amorphous oxide transistors, we propose an alternative amorphous semiconductor of indium silicon tungsten oxide as the channel material for thin film transistors. In this study, we employ the material to reveal the relation between the active thin film and the transistor performance with aid of x-ray reflectivity study. By adjusting the pre-annealing temperature, we find that the film densification and interface flatness between the film and gate insulator are crucial for achieving controllable high-performance transistors. The material and findings in the study are believed helpful for realizing controllable high-performance stable transistors.

Thermal transistor utilizing gas-liquid transition

KAUST Repository

Komatsu, Teruhisa S.

2011-01-25

We propose a simple thermal transistor, a device to control heat current. In order to effectively change the current, we utilize the gas-liquid transition of the heat-conducting medium (fluid) because the gas region can act as a good thermal insulator. The three terminals of the transistor are located at both ends and the center of the system, and are put into contact with distinct heat baths. The key idea is a special arrangement of the three terminals. The temperature at one end (the gate temperature) is used as an input signal to control the heat current between the center (source, hot) and another end (drain, cold). Simulating the nanoscale systems of this transistor, control of heat current is demonstrated. The heat current is effectively cut off when the gate temperature is cold and it flows normally when it is hot. By using an extended version of this transistor, we also simulate a primitive application for an inverter. © 2011 American Physical Society.

Low-frequency noise in single electron tunneling transistor

DEFF Research Database (Denmark)

Tavkhelidze, A.N.; Mygind, Jesper

1998-01-01

The noise in current biased aluminium single electron tunneling (SET) transistors has been investigated in the frequency range of 5 mHz ..., we find the same input charge noise, typically QN = 5 × 10–4 e/Hz1/2 at 10 Hz, with and without the HF shielding. At lower frequencies, the noise is due to charge trapping, and the voltage noise pattern superimposed on the V(Vg) curve (voltage across transistor versus gate voltage) strongly depends...... when ramping the junction voltage. Dynamic trapping may limit the high frequency applications of the SET transistor. Also reported on are the effects of rf irradiation and the dependence of the SET transistor noise on bias voltage. ©1998 American Institute of Physics....

Large-current-controllable carbon nanotube field-effect transistor in electrolyte solution

Science.gov (United States)

Myodo, Miho; Inaba, Masafumi; Ohara, Kazuyoshi; Kato, Ryogo; Kobayashi, Mikinori; Hirano, Yu; Suzuki, Kazuma; Kawarada, Hiroshi

2015-05-01

Large-current-controllable carbon nanotube field-effect transistors (CNT-FETs) were fabricated with mm-long CNT sheets. The sheets, synthesized by remote-plasma-enhanced CVD, contained both single- and double-walled CNTs. Titanium was deposited on the sheet as source and drain electrodes, and an electrolyte solution was used as a gate electrode (solution gate) to apply a gate voltage to the CNTs through electric double layers formed around the CNTs. The drain current came to be well modulated as electrolyte solution penetrated into the sheets, and one of the solution gate CNT-FETs was able to control a large current of over 2.5 A. In addition, we determined the transconductance parameter per tube and compared it with values for other CNT-FETs. The potential of CNT sheets for applications requiring the control of large current is exhibited in this study.

A high-performance complementary inverter based on transition metal dichalcogenide field-effect transistors.

Science.gov (United States)

Cho, Ah-Jin; Park, Kee Chan; Kwon, Jang-Yeon

2015-01-01

For several years, graphene has been the focus of much attention due to its peculiar characteristics, and it is now considered to be a representative 2-dimensional (2D) material. Even though many research groups have studied on the graphene, its intrinsic nature of a zero band-gap, limits its use in practical applications, particularly in logic circuits. Recently, transition metal dichalcogenides (TMDs), which are another type of 2D material, have drawn attention due to the advantage of having a sizable band-gap and a high mobility. Here, we report on the design of a complementary inverter, one of the most basic logic elements, which is based on a MoS2 n-type transistor and a WSe2 p-type transistor. The advantages provided by the complementary metal-oxide-semiconductor (CMOS) configuration and the high-performance TMD channels allow us to fabricate a TMD complementary inverter that has a high-gain of 13.7. This work demonstrates the operation of the MoS2 n-FET and WSe2 p-FET on the same substrate, and the electrical performance of the CMOS inverter, which is based on a different driving current, is also measured.

Organic transistors with high thermal stability for medical applications.

Science.gov (United States)

Kuribara, Kazunori; Wang, He; Uchiyama, Naoya; Fukuda, Kenjiro; Yokota, Tomoyuki; Zschieschang, Ute; Jaye, Cherno; Fischer, Daniel; Klauk, Hagen; Yamamoto, Tatsuya; Takimiya, Kazuo; Ikeda, Masaaki; Kuwabara, Hirokazu; Sekitani, Tsuyoshi; Loo, Yueh-Lin; Someya, Takao

2012-03-06

The excellent mechanical flexibility of organic electronic devices is expected to open up a range of new application opportunities in electronics, such as flexible displays, robotic sensors, and biological and medical electronic applications. However, one of the major remaining issues for organic devices is their instability, especially their thermal instability, because low melting temperatures and large thermal expansion coefficients of organic materials cause thermal degradation. Here we demonstrate the fabrication of flexible thin-film transistors with excellent thermal stability and their viability for biomedical sterilization processes. The organic thin-film transistors comprise a high-mobility organic semiconductor, dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene, and thin gate dielectrics comprising a 2-nm-thick self-assembled monolayer and a 4-nm-thick aluminium oxide layer. The transistors exhibit a mobility of 1.2 cm(2) V(-1)s(-1) within a 2 V operation and are stable even after exposure to conditions typically used for medical sterilization.

Water-gel for gating graphene transistors.

Science.gov (United States)

Kim, Beom Joon; Um, Soong Ho; Song, Woo Chul; Kim, Yong Ho; Kang, Moon Sung; Cho, Jeong Ho

2014-05-14

Water, the primary electrolyte in biology, attracts significant interest as an electrolyte-type dielectric material for transistors compatible with biological systems. Unfortunately, the fluidic nature and low ionic conductivity of water prevents its practical usage in such applications. Here, we describe the development of a solid state, megahertz-operating, water-based gate dielectric system for operating graphene transistors. The new electrolyte systems were prepared by dissolving metal-substituted DNA polyelectrolytes into water. The addition of these biocompatible polyelectrolytes induced hydrogelation to provide solid-state integrity to the system. They also enhanced the ionic conductivities of the electrolytes, which in turn led to the quick formation of an electric double layer at the graphene/electrolyte interface that is beneficial for modulating currents in graphene transistors at high frequencies. At the optimized conditions, the Na-DNA water-gel-gated flexible transistors and inverters were operated at frequencies above 1 MHz and 100 kHz, respectively.

Germanium field-effect transistor made from a high-purity substrate

International Nuclear Information System (INIS)

Hansen, W.L.; Goulding, F.S.; Haller, E.E.

1978-11-01

Field effect transistors have been fabricated on high-purity germanium substrates using low-temperature technology. The aim of this work is to preserve the low density of trapping centers in high-quality starting material by low-temperature ( 0 C) processing. The use of germanium promises to eliminate some of the traps which cause generation-recombination noise in silicon field-effect transistors (FET's) at low temperatures. Typically, the transconductance (g/sub m/) in the germanium FET's is 10 mA/V and the gate leakage can be less than 10 -12 A. Present devices exhibit a large 1/f noise component and most of this noise must be eliminated if they are to be competitive with silicon FET's commonly used in high-resolution nuclear spectrometers

Materials and devices with applications in high-end organic transistors

International Nuclear Information System (INIS)

Takeya, J.; Uemura, T.; Sakai, K.; Okada, Y.

2014-01-01

The development of functional materials typically benefits from an understanding of the microscopic mechanisms by which those materials operate. To accelerate the development of organic semiconductor devices with industrial applications in flexible and printed electronics, it is essential to elucidate the mechanisms of charge transport associated with molecular-scale charge transfer. In this study, we employed Hall effect measurements to differentiate coherent band transport from site-to-site hopping. The results of tests using several different molecular systems as the active semiconductor layers demonstrate that high-mobility charge transport in recently-developed solution-crystallized organic transistors is the result of a band-like mechanism. These materials, which have the potential to be organic transistors exhibiting the highest speeds ever obtained, are significantly different from the conventional lower-mobility organic semiconductors with incoherent hopping-like transport mechanisms which were studied in the previous century. They may be categorized as “high-end” organic semiconductors, characterized by their coherent electronic states and high values of mobility which are close to or greater than 10 cm 2 /Vs. - Highlights: • Transport in high-mobility solution-crystallized organic transistors is band-like. • High-end organic semiconductors carry coherent electrons with mobility > 10 cm 2 /Vs. • Hall-effect measurement differentiates coherent band transport from hopping. • We found an anomalous pressure effect in organic semiconductors

A Drain Current Model Based on the Temperature Effect of a-Si:H Thin-Film Transistors

International Nuclear Information System (INIS)

Qiang Lei; Yao Ruo-He

2012-01-01

Based on the differential Ohm's law and Poisson's equation, an analytical model of the drain current for a-Si:H thin-film transistors is developed. This model is proposed to elaborate the temperature effect on the drain current, which indicates that the drain current is linear with temperature in the range of 290-360 K, and the results fit well with the experimental data

The Bipolar Field-Effect Transistor: XIII. Physical Realizations of the Transistor and Circuits (One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)

International Nuclear Information System (INIS)

Sah, C.-T.; Jie Binbin

2009-01-01

This paper reports the physical realization of the Bipolar Field-Effect Transistor (BiFET) and its one-transistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These examples include the one-MOS-gate on semi-infinite thick impure base transistor (the bulk transistor) and the impurethin-base Silicon-on-Insulator (SOI) transistor and the two-MOS-gates on thin base transistors (the FinFET and the Thin Film Transistor TFT). Figures are given with the cross-section views containing the electron and hole concentration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.

Non-Planar Nanotube and Wavy Architecture Based Ultra-High Performance Field Effect Transistors

KAUST Repository

Hanna, Amir

2016-11-01

This dissertation presents a unique concept for a device architecture named the nanotube (NT) architecture, which is capable of higher drive current compared to the Gate-All-Around Nanowire architecture when applied to heterostructure Tunnel Field Effect Transistors. Through the use of inner/outer core-shell gates, heterostructure NT TFET leverages physically larger tunneling area thus achieving higher driver current (ION) and saving real estates by eliminating arraying requirement. We discuss the physics of p-type (Silicon/Indium Arsenide) and n-type (Silicon/Germanium hetero-structure) based TFETs. Numerical TCAD simulations have shown that NT TFETs have 5x and 1.6 x higher normalized ION when compared to GAA NW TFET for p and n-type TFETs, respectively. This is due to the availability of larger tunneling junction cross sectional area, and lower Shockley-Reed-Hall recombination, while achieving sub 60 mV/dec performance for more than 5 orders of magnitude of drain current, thus enabling scaling down of Vdd to 0.5 V. This dissertation also introduces a novel thin-film-transistors architecture that is named the Wavy Channel (WC) architecture, which allows for extending device width by integrating vertical fin-like substrate corrugations giving rise to up to 50% larger device width, without occupying extra chip area. The novel architecture shows 2x higher output drive current per unit chip area when compared to conventional planar architecture. The current increase is attributed to both the extra device width and 50% enhancement in field effect mobility due to electrostatic gating effects. Digital circuits are fabricated to demonstrate the potential of integrating WC TFT based circuits. WC inverters have shown 2× the peak-to-peak output voltage for the same input, and ~2× the operation frequency of the planar inverters for the same peak-to-peak output voltage. WC NAND circuits have shown 2× higher peak-to-peak output voltage, and 3× lower high-to-low propagation

Dual-Gate p-GaN Gate High Electron Mobility Transistors for Steep Subthreshold Slope.

Science.gov (United States)

Bae, Jong-Ho; Lee, Jong-Ho

2016-05-01

A steep subthreshold slope characteristic is achieved through p-GaN gate HEMT with dual-gate structure. Obtained subthreshold slope is less than 120 μV/dec. Based on the measured and simulated data obtained from single-gate device, breakdown of parasitic floating-base bipolar transistor and floating gate charged with holes are responsible to increase abruptly in drain current. In the dual-gate device, on-current degrades with high temperature but subthreshold slope is not changed. To observe the switching speed of dual-gate device and transient response of drain current are measured. According to the transient responses of drain current, switching speed of the dual-gate device is about 10(-5) sec.

High Temperature Terahertz Detectors Realized by a GaN High Electron Mobility Transistor

Science.gov (United States)

Hou, H. W.; Liu, Z.; Teng, J. H.; Palacios, T.; Chua, S. J.

2017-04-01

In this work, a high temperature THz detector based on a GaN high electron mobility transistor (HEMT) with nano antenna structures was fabricated and demonstrated to be able to work up to 200 °C. The THz responsivity and noise equivalent power (NEP) of the device were characterized at 0.14 THz radiation over a wide temperature range from room temperature to 200 °C. A high responsivity Rv of 15.5 and 2.7 kV/W and a low NEP of 0.58 and 10 pW/Hz0.5 were obtained at room temperature and 200 °C, respectively. The advantages of the GaN HEMT over other types of field effect transistors for high temperature terahertz detection are discussed. The physical mechanisms responsible for the temperature dependence of the responsivity and NEP of the GaN HEMT are also analyzed thoroughly.

3D NANOTUBE FIELD EFFECT TRANSISTORS FOR HYBRID HIGH-PERFORMANCE AND LOW-POWER OPERATION WITH HIGH CHIP-AREA EFFICIENCY

KAUST Repository

Fahad, Hossain M.

2014-03-01

Information anytime and anywhere has ushered in a new technological age where massive amounts of ‘big data’ combined with self-aware and ubiquitous interactive computing systems is shaping our daily lives. As society gravitates towards a smart living environment and a sustainable future, the demand for faster and more computationally efficient electronics will continue to rise. Keeping up with this demand requires extensive innovation at the transistor level, which is at the core of all electronics. Up until recently, classical silicon transistor technology has traditionally been weary of disruptive innovation. But with the aggressive scaling trend, there has been two dramatic changes to the transistor landscape. The first was the re-introduction of metal/high-K gate stacks with strain engineering in the 45 nm technology node, which enabled further scaling on silicon to smaller nodes by alleviating the problem of gate leakage and improving the channel mobility. The second innovation was the use of non-planar 3D silicon fins as opposed to classical planar architectures for stronger electrostatic control leading to significantly lower off-state leakage and other short-channel effects. Both these innovations have prolonged the life of silicon based electronics by at least another 1-2 decades. The next generation 14 nm technology node will utilize silicon fin channels that have gate lengths of 14 nm and fin thicknesses of 7 nm. These dimensions are almost at the extreme end of current lithographic capabilities. Moreover, as fins become smaller, the parasitic capacitances and resistances increase significantly resulting in degraded performance. It is of popular consensus that the next evolutionary step in transistor technology is in the form of gate-all-around silicon nanowires (GAA NWFETs), which offer the tightest electrostatic configuration leading to the lowest possible leakage and short channel characteristics in over-the-barrier type devices. However, to keep

Investigation of 6T SRAM memory circuit using high-k dielectrics based nano scale junctionless transistor

Science.gov (United States)

Charles Pravin, J.; Nirmal, D.; Prajoon, P.; Mohan Kumar, N.; Ajayan, J.

2017-04-01

In this paper the Dual Metal Surround Gate Junctionless Transistor (DMSGJLT) has been implemented with various high-k dielectric. The leakage current in the device is analysed in detail by obtaining the band structure for different high-k dielectric material. It is noticed that with increasing dielectric constant the device provides more resistance for the direct tunnelling of electron in off state. The gate oxide capacitance also shows 0.1 μF improvement with Hafnium Oxide (HfO2) than Silicon Oxide (SiO2). This paved the way for a better memory application when high-k dielectric is used. The Six Transistor (6T) Static Random Access Memory (SRAM) circuit implemented shows 41.4% improvement in read noise margin for HfO2 than SiO2. It also shows 37.49% improvement in write noise margin and 30.16% improvement in hold noise margin for HfO2 than SiO2.

High-performance integrated field-effect transistor-based sensors

Energy Technology Data Exchange (ETDEWEB)

Adzhri, R., E-mail: adzhri@gmail.com [Institute of Nano Electronic Engineering (INEE), Universiti Malaysia Perlis (UniMAP), Kangar, Perlis (Malaysia); Md Arshad, M.K., E-mail: mohd.khairuddin@unimap.edu.my [Institute of Nano Electronic Engineering (INEE), Universiti Malaysia Perlis (UniMAP), Kangar, Perlis (Malaysia); School of Microelectronic Engineering (SoME), Universiti Malaysia Perlis (UniMAP), Kangar, Perlis (Malaysia); Gopinath, Subash C.B., E-mail: subash@unimap.edu.my [Institute of Nano Electronic Engineering (INEE), Universiti Malaysia Perlis (UniMAP), Kangar, Perlis (Malaysia); School of Bioprocess Engineering (SBE), Universiti Malaysia Perlis (UniMAP), Arau, Perlis (Malaysia); Ruslinda, A.R., E-mail: ruslinda@unimap.edu.my [Institute of Nano Electronic Engineering (INEE), Universiti Malaysia Perlis (UniMAP), Kangar, Perlis (Malaysia); Fathil, M.F.M., E-mail: faris.fathil@gmail.com [Institute of Nano Electronic Engineering (INEE), Universiti Malaysia Perlis (UniMAP), Kangar, Perlis (Malaysia); Ayub, R.M., E-mail: ramzan@unimap.edu.my [Institute of Nano Electronic Engineering (INEE), Universiti Malaysia Perlis (UniMAP), Kangar, Perlis (Malaysia); Nor, M. Nuzaihan Mohd, E-mail: m.nuzaihan@unimap.edu.my [Institute of Nano Electronic Engineering (INEE), Universiti Malaysia Perlis (UniMAP), Kangar, Perlis (Malaysia); Voon, C.H., E-mail: chvoon@unimap.edu.my [Institute of Nano Electronic Engineering (INEE), Universiti Malaysia Perlis (UniMAP), Kangar, Perlis (Malaysia)

2016-04-21

Field-effect transistors (FETs) have succeeded in modern electronics in an era of computers and hand-held applications. Currently, considerable attention has been paid to direct electrical measurements, which work by monitoring changes in intrinsic electrical properties. Further, FET-based sensing systems drastically reduce cost, are compatible with CMOS technology, and ease down-stream applications. Current technologies for sensing applications rely on time-consuming strategies and processes and can only be performed under recommended conditions. To overcome these obstacles, an overview is presented here in which we specifically focus on high-performance FET-based sensor integration with nano-sized materials, which requires understanding the interaction of surface materials with the surrounding environment. Therefore, we present strategies, material depositions, device structures and other characteristics involved in FET-based devices. Special attention was given to silicon and polyaniline nanowires and graphene, which have attracted much interest due to their remarkable properties in sensing applications. - Highlights: • Performance of FET-based biosensors for the detection of biomolecules is presented. • Silicon nanowire, polyaniline and graphene are the highlighted nanoscaled materials as sensing transducers. • The importance of surface material interaction with the surrounding environment is discussed. • Different device structure architectures for ease in fabrication and high sensitivity of sensing are presented.

High-performance integrated field-effect transistor-based sensors

International Nuclear Information System (INIS)

Adzhri, R.; Md Arshad, M.K.; Gopinath, Subash C.B.; Ruslinda, A.R.; Fathil, M.F.M.; Ayub, R.M.; Nor, M. Nuzaihan Mohd; Voon, C.H.

2016-01-01

Field-effect transistors (FETs) have succeeded in modern electronics in an era of computers and hand-held applications. Currently, considerable attention has been paid to direct electrical measurements, which work by monitoring changes in intrinsic electrical properties. Further, FET-based sensing systems drastically reduce cost, are compatible with CMOS technology, and ease down-stream applications. Current technologies for sensing applications rely on time-consuming strategies and processes and can only be performed under recommended conditions. To overcome these obstacles, an overview is presented here in which we specifically focus on high-performance FET-based sensor integration with nano-sized materials, which requires understanding the interaction of surface materials with the surrounding environment. Therefore, we present strategies, material depositions, device structures and other characteristics involved in FET-based devices. Special attention was given to silicon and polyaniline nanowires and graphene, which have attracted much interest due to their remarkable properties in sensing applications. - Highlights: • Performance of FET-based biosensors for the detection of biomolecules is presented. • Silicon nanowire, polyaniline and graphene are the highlighted nanoscaled materials as sensing transducers. • The importance of surface material interaction with the surrounding environment is discussed. • Different device structure architectures for ease in fabrication and high sensitivity of sensing are presented.

Transistor challenges - A DRAM perspective

International Nuclear Information System (INIS)

Faul, Juergen W.; Henke, Dietmar

2005-01-01

Key challenges of the transistor scaling from a DRAM perspective will be reviewed. Both, array transistors as well as DRAM support devices face challenges that differ essentially from high performance logic device scaling. As a major difference, retention time and standby current requirements characterize special boundary conditions in the DRAM device design. Array device scaling is determined by a chip size driven aggressive node scaling. To continue scaling, major innovations need to be introduced into state-of-the-art planar array transistors. Alternatively, non planar device concepts will have to be evaluated. Support device design for DRAMs is driven by today's market demand for increased chip performances at little to no extra cost. Major innovations are required to continue that path. Besides this strive for performance increase, special limitations for 'on pitch' circuits at the array edge will come up due to the aggressive cell size scaling

Degradation Mechanisms for GaN and GaAs High Speed Transistors

Directory of Open Access Journals (Sweden)

Fan Ren

2012-11-01

Full Text Available We present a review of reliability issues in AlGaN/GaN and AlGaAs/GaAs high electron mobility transistors (HEMTs as well as Heterojunction Bipolar Transistors (HBTs in the AlGaAs/GaAs materials systems. Because of the complex nature and multi-faceted operation modes of these devices, reliability studies must go beyond the typical Arrhenius accelerated life tests. We review the electric field driven degradation in devices with different gate metallization, device dimensions, electric field mitigation techniques (such as source field plate, and the effect of device fabrication processes for both DC and RF stress conditions. We summarize the degradation mechanisms that limit the lifetime of these devices. A variety of contact and surface degradation mechanisms have been reported, but differ in the two device technologies: For HEMTs, the layers are thin and relatively lightly doped compared to HBT structures and there is a metal Schottky gate that is directly on the semiconductor. By contrast, the HBT relies on pn junctions for current modulation and has only Ohmic contacts. This leads to different degradation mechanisms for the two types of devices.

Degradation Mechanisms for GaN and GaAs High Speed Transistors

Science.gov (United States)

Cheney, David J.; Douglas, Erica A.; Liu, Lu; Lo, Chien-Fong; Gila, Brent P.; Ren, Fan; Pearton, Stephen J.

2012-01-01

We present a review of reliability issues in AlGaN/GaN and AlGaAs/GaAs high electron mobility transistors (HEMTs) as well as Heterojunction Bipolar Transistors (HBTs) in the AlGaAs/GaAs materials systems. Because of the complex nature and multi-faceted operation modes of these devices, reliability studies must go beyond the typical Arrhenius accelerated life tests. We review the electric field driven degradation in devices with different gate metallization, device dimensions, electric field mitigation techniques (such as source field plate), and the effect of device fabrication processes for both DC and RF stress conditions. We summarize the degradation mechanisms that limit the lifetime of these devices. A variety of contact and surface degradation mechanisms have been reported, but differ in the two device technologies: For HEMTs, the layers are thin and relatively lightly doped compared to HBT structures and there is a metal Schottky gate that is directly on the semiconductor. By contrast, the HBT relies on pn junctions for current modulation and has only Ohmic contacts. This leads to different degradation mechanisms for the two types of devices.

Optimization of ultra-low-power CMOS transistors

International Nuclear Information System (INIS)

Stockinger, M.

2000-01-01

Ultra-low-power CMOS integrated circuits have constantly gained importance due to the fast growing portable electronics market. High-performance applications like mobile telephones ask for high-speed computations and low stand-by power consumption to increase the actual operating time. This means that transistors with low leakage currents and high drive currents have to be provided. Common fabrication methods will soon reach their limits if the on-chip feature size of CMOS technology continues to shrink at this very fast rate. New device architectures will help to keep track with the roadmap of the semiconductor industry. Especially doping profiles offer much freedom for performance improvements as they determine the 'inner functioning' of a transistor. In this work automated doping profile optimization is performed on MOS transistors within the TCAD framework SIESTA. The doping between and under the source/drain wells is discretized on an orthogonal optimization grid facilitating almost arbitrary two-dimensional shapes. A linear optimizer issued to find the optimum doping profile by variation of the doping parameters utilizing numerical device simulations with MINIMOS-NT. Gaussian functions are used in further optimization runs to make the doping profiles smooth. Two device generations are considered, one with 0.25 μm, the other with 0.1 μm gate length. The device geometries and source/drain doping profiles are kept fixed during optimization and supply voltages are chosen suitable for ultra-low-power purposes. In a first optimization study the drive current of NMOS transistors is maximized while keeping the leakage current below a limit of 1 pA/μm. This results in peaking channel doping devices (PCD) with narrow doping peaks placed asymmetrically in the channel. Drive current improvements of 45 % and 71 % for the 0.25 μm and 0.1 μm devices, respectively, are achieved compared to uniformly doped devices. The PCD device is studied in detail and explanations for

High performance tunnel field-effect transistor by gate and source engineering.

Science.gov (United States)

Huang, Ru; Huang, Qianqian; Chen, Shaowen; Wu, Chunlei; Wang, Jiaxin; An, Xia; Wang, Yangyuan

2014-12-19

As one of the most promising candidates for future nanoelectronic devices, tunnel field-effect transistors (TFET) can overcome the subthreshold slope (SS) limitation of MOSFET, whereas high ON-current, low OFF-current and steep switching can hardly be obtained at the same time for experimental TFETs. In this paper, we developed a new nanodevice technology based on TFET concepts. By designing the gate configuration and introducing the optimized Schottky junction, a multi-finger-gate TFET with a dopant-segregated Schottky source (mFSB-TFET) is proposed and experimentally demonstrated. A steeper SS can be achieved in the fabricated mFSB-TFET on the bulk Si substrate benefiting from the coupled quantum band-to-band tunneling (BTBT) mechanism, as well as a high I(ON)/I(OFF) ratio (∼ 10(7)) at V(DS) = 0.2 V without an area penalty. By compatible SOI CMOS technology, the fabricated Si mFSB-TFET device was further optimized with a high ION/IOFF ratio of ∼ 10(8) and a steeper SS of over 5.5 decades of current. A minimum SS of below 60 mV dec(-1) was experimentally obtained, indicating its dominant quantum BTBT mechanism for switching.

Accelerating the life of transistors

International Nuclear Information System (INIS)

Qi Haochun; Lü Changzhi; Zhang Xiaoling; Xie Xuesong

2013-01-01

Choosing small and medium power switching transistors of the NPN type in a 3DK set as the study object, the test of accelerating life is conducted in constant temperature and humidity, and then the data are statistically analyzed with software developed by ourselves. According to degradations of such sensitive parameters as the reverse leakage current of transistors, the lifetime order of transistors is about more than 10 4 at 100 °C and 100% relative humidity (RH) conditions. By corrosion fracture of transistor outer leads and other failure modes, with the failure truncated testing, the average lifetime rank of transistors in different distributions is extrapolated about 10 3 . Failure mechanism analyses of degradation of electrical parameters, outer lead fracture and other reasons that affect transistor lifetime are conducted. The findings show that the impact of external stress of outer leads on transistor reliability is more serious than that of parameter degradation. (semiconductor devices)

A Klein-tunneling transistor with ballistic graphene

Energy Technology Data Exchange (ETDEWEB)

Wilmart, Quentin; Fève, Gwendal; Berroir, Jean-Marc; Plaçais, Bernard [Laboratoire Pierre Aigrain, Ecole Normale Supérieure, CNRS (UMR 8551), Université P et M Curie, Université D Diderot, 24, rue Lhomond, 75231 Paris Cedex 05 (France); Berrada, Salim; Hung Nguyen, V; Dollfus, Philippe [Institute of Fundamental Electronics, Univ. Paris-Sud, CNRS, Orsay (France); Torrin, David [Département de Physique, Ecole Polytechnique, 91128 Palaiseau (France)

2014-06-15

Today, the availability of high mobility graphene up to room temperature makes ballistic transport in nanodevices achievable. In particular, p-n-p transistors in the ballistic regime give access to Klein tunneling physics and allow the realization of devices exploiting the optics-like behavior of Dirac Fermions (DFs) as in the Veselago lens or the Fabry–Pérot cavity. Here we propose a Klein tunneling transistor based on the geometrical optics of DFs. We consider the case of a prismatic active region delimited by a triangular gate, where total internal reflection may occur, which leads to the tunable suppression of transistor transmission. We calculate the transmission and the current by means of scattering theory and the finite bias properties using non-equilibrium Green's function (NEGF) simulation. (letter)

Controlling the mode of operation of organic transistors through side-chain engineering

KAUST Repository

Giovannitti, Alexander

2016-10-11

Electrolyte-gated organic transistors offer low bias operation facilitated by direct contact of the transistor channel with an electrolyte. Their operation mode is generally defined by the dimensionality of charge transport, where a field-effect transistor allows for electrostatic charge accumulation at the electrolyte/semiconductor interface, whereas an organic electrochemical transistor (OECT) facilitates penetration of ions into the bulk of the channel, considered a slow process, leading to volumetric doping and electronic transport. Conducting polymer OECTs allow for fast switching and high currents through incorporation of excess, hygroscopic ionic phases, but operate in depletion mode. Here, we show that the use of glycolated side chains on a thiophene backbone can result in accumulation mode OECTs with high currents, transconductance, and sharp subthreshold switching, while maintaining fast switching speeds. Compared with alkylated analogs of the same backbone, the triethylene glycol side chains shift the mode of operation of aqueous electrolyte-gated transistors from interfacial to bulk doping/transport and show complete and reversible electrochromism and high volumetric capacitance at low operating biases. We propose that the glycol side chains facilitate hydration and ion penetration, without compromising electronic mobility, and suggest that this synthetic approach can be used to guide the design of organic mixed conductors.

Controlling the mode of operation of organic transistors through side-chain engineering

Science.gov (United States)

Giovannitti, Alexander; Sbircea, Dan-Tiberiu; Inal, Sahika; Nielsen, Christian B.; Bandiello, Enrico; Hanifi, David A.; Sessolo, Michele; Malliaras, George G.; McCulloch, Iain; Rivnay, Jonathan

2016-01-01

Electrolyte-gated organic transistors offer low bias operation facilitated by direct contact of the transistor channel with an electrolyte. Their operation mode is generally defined by the dimensionality of charge transport, where a field-effect transistor allows for electrostatic charge accumulation at the electrolyte/semiconductor interface, whereas an organic electrochemical transistor (OECT) facilitates penetration of ions into the bulk of the channel, considered a slow process, leading to volumetric doping and electronic transport. Conducting polymer OECTs allow for fast switching and high currents through incorporation of excess, hygroscopic ionic phases, but operate in depletion mode. Here, we show that the use of glycolated side chains on a thiophene backbone can result in accumulation mode OECTs with high currents, transconductance, and sharp subthreshold switching, while maintaining fast switching speeds. Compared with alkylated analogs of the same backbone, the triethylene glycol side chains shift the mode of operation of aqueous electrolyte-gated transistors from interfacial to bulk doping/transport and show complete and reversible electrochromism and high volumetric capacitance at low operating biases. We propose that the glycol side chains facilitate hydration and ion penetration, without compromising electronic mobility, and suggest that this synthetic approach can be used to guide the design of organic mixed conductors. PMID:27790983

Increase the threshold voltage of high voltage GaN transistors by low temperature atomic hydrogen treatment

Energy Technology Data Exchange (ETDEWEB)

Erofeev, E. V., E-mail: erofeev@micran.ru [Tomsk State University of Control Systems and Radioelectronics, Research Institute of Electrical-Communication Systems (Russian Federation); Fedin, I. V.; Kutkov, I. V. [Research and Production Company “Micran” (Russian Federation); Yuryev, Yu. N. [National Research Tomsk Polytechnic University, Institute of Physics and Technology (Russian Federation)

2017-02-15

High-electron-mobility transistors (HEMTs) based on AlGaN/GaN epitaxial heterostructures are a promising element base for the fabrication of high voltage electronic devices of the next generation. This is caused by both the high mobility of charge carriers in the transistor channel and the high electric strength of the material, which makes it possible to attain high breakdown voltages. For use in high-power switches, normally off-mode GaN transistors operating under enhancement conditions are required. To fabricate normally off GaN transistors, one most frequently uses a subgate region based on magnesium-doped p-GaN. However, optimization of the p-GaN epitaxial-layer thickness and the doping level makes it possible to attain a threshold voltage of GaN transistors close to V{sub th} = +2 V. In this study, it is shown that the use of low temperature treatment in an atomic hydrogen flow for the p-GaN-based subgate region before the deposition of gate-metallization layers makes it possible to increase the transistor threshold voltage to V{sub th} = +3.5 V. The effects under observation can be caused by the formation of a dipole layer on the p-GaN surface induced by the effect of atomic hydrogen. The heat treatment of hydrogen-treated GaN transistors in a nitrogen environment at a temperature of T = 250°C for 12 h reveals no degradation of the transistor’s electrical parameters, which can be caused by the formation of a thermally stable dipole layer at the metal/p-GaN interface as a result of hydrogenation.

Increase the threshold voltage of high voltage GaN transistors by low temperature atomic hydrogen treatment

International Nuclear Information System (INIS)

Erofeev, E. V.; Fedin, I. V.; Kutkov, I. V.; Yuryev, Yu. N.

2017-01-01

High-electron-mobility transistors (HEMTs) based on AlGaN/GaN epitaxial heterostructures are a promising element base for the fabrication of high voltage electronic devices of the next generation. This is caused by both the high mobility of charge carriers in the transistor channel and the high electric strength of the material, which makes it possible to attain high breakdown voltages. For use in high-power switches, normally off-mode GaN transistors operating under enhancement conditions are required. To fabricate normally off GaN transistors, one most frequently uses a subgate region based on magnesium-doped p-GaN. However, optimization of the p-GaN epitaxial-layer thickness and the doping level makes it possible to attain a threshold voltage of GaN transistors close to V_t_h = +2 V. In this study, it is shown that the use of low temperature treatment in an atomic hydrogen flow for the p-GaN-based subgate region before the deposition of gate-metallization layers makes it possible to increase the transistor threshold voltage to V_t_h = +3.5 V. The effects under observation can be caused by the formation of a dipole layer on the p-GaN surface induced by the effect of atomic hydrogen. The heat treatment of hydrogen-treated GaN transistors in a nitrogen environment at a temperature of T = 250°C for 12 h reveals no degradation of the transistor’s electrical parameters, which can be caused by the formation of a thermally stable dipole layer at the metal/p-GaN interface as a result of hydrogenation.

Distributed amplifier using Josephson vortex flow transistors

International Nuclear Information System (INIS)

McGinnis, D.P.; Beyer, J.B.; Nordman, J.E.

1986-01-01

A wide-band traveling wave amplifier using vortex flow transistors is proposed. A vortex flow transistor is a long Josephson junction used as a current controlled voltage source. The dual nature of this device to the field effect transistor is exploited. A circuit model of this device is proposed and a distributed amplifier utilizing 50 vortex flow transistors is predicted to have useful gain to 100 GHz

Highly stable thin film transistors using multilayer channel structure

KAUST Repository

Nayak, Pradipta K.; Wang, Zhenwei; Anjum, Dalaver H.; Hedhili, Mohamed N.; Alshareef, Husam N.

2015-01-01

We report highly stable gate-bias stress performance of thin film transistors (TFTs) using zinc oxide (ZnO)/hafnium oxide (HfO2) multilayer structure as the channel layer. Positive and negative gate-bias stress stability of the TFTs was measured

Dual-mode operation of 2D material-base hot electron transistors

KAUST Repository

Lan, Yann-Wen; Jr., Carlos M. Torres,; Zhu, Xiaodan; Qasem, Hussam; Adleman, James R.; Lerner, Mitchell B.; Tsai, Shin-Hung; Shi, Yumeng; Li, Lain-Jong; Yeh, Wen-Kuan; Wang, Kang L.

2016-01-01

Vertical hot electron transistors incorporating atomically-thin 2D materials, such as graphene or MoS2, in the base region have been proposed and demonstrated in the development of electronic and optoelectronic applications. To the best of our knowledge, all previous 2D material-base hot electron transistors only considered applying a positive collector-base potential (V-CB > 0) as is necessary for the typical unipolar hot-electron transistor behavior. Here we demonstrate a novel functionality, specifically a dual-mode operation, in our 2D material-base hot electron transistors (e.g. with either graphene or MoS2 in the base region) with the application of a negative collector-base potential (V-CB < 0). That is, our 2D material-base hot electron transistors can operate in either a hot-electron or a reverse-current dominating mode depending upon the particular polarity of VCB. Furthermore, these devices operate at room temperature and their current gains can be dynamically tuned by varying VCB. We anticipate our multi-functional dual-mode transistors will pave the way towards the realization of novel flexible 2D material-based high-density and low-energy hot-carrier electronic applications.

Dual-mode operation of 2D material-base hot electron transistors

KAUST Repository

Lan, Yann-Wen

2016-09-01

Vertical hot electron transistors incorporating atomically-thin 2D materials, such as graphene or MoS2, in the base region have been proposed and demonstrated in the development of electronic and optoelectronic applications. To the best of our knowledge, all previous 2D material-base hot electron transistors only considered applying a positive collector-base potential (V-CB > 0) as is necessary for the typical unipolar hot-electron transistor behavior. Here we demonstrate a novel functionality, specifically a dual-mode operation, in our 2D material-base hot electron transistors (e.g. with either graphene or MoS2 in the base region) with the application of a negative collector-base potential (V-CB < 0). That is, our 2D material-base hot electron transistors can operate in either a hot-electron or a reverse-current dominating mode depending upon the particular polarity of VCB. Furthermore, these devices operate at room temperature and their current gains can be dynamically tuned by varying VCB. We anticipate our multi-functional dual-mode transistors will pave the way towards the realization of novel flexible 2D material-based high-density and low-energy hot-carrier electronic applications.

Dual-mode operation of 2D material-base hot electron transistors.

Science.gov (United States)

Lan, Yann-Wen; Torres, Carlos M; Zhu, Xiaodan; Qasem, Hussam; Adleman, James R; Lerner, Mitchell B; Tsai, Shin-Hung; Shi, Yumeng; Li, Lain-Jong; Yeh, Wen-Kuan; Wang, Kang L

2016-09-01

Vertical hot electron transistors incorporating atomically-thin 2D materials, such as graphene or MoS2, in the base region have been proposed and demonstrated in the development of electronic and optoelectronic applications. To the best of our knowledge, all previous 2D material-base hot electron transistors only considered applying a positive collector-base potential (VCB > 0) as is necessary for the typical unipolar hot-electron transistor behavior. Here we demonstrate a novel functionality, specifically a dual-mode operation, in our 2D material-base hot electron transistors (e.g. with either graphene or MoS2 in the base region) with the application of a negative collector-base potential (VCB transistors can operate in either a hot-electron or a reverse-current dominating mode depending upon the particular polarity of VCB. Furthermore, these devices operate at room temperature and their current gains can be dynamically tuned by varying VCB. We anticipate our multi-functional dual-mode transistors will pave the way towards the realization of novel flexible 2D material-based high-density and low-energy hot-carrier electronic applications.

Patterning solution-processed organic single-crystal transistors with high device performance

Directory of Open Access Journals (Sweden)

Yun Li

2011-06-01

Full Text Available We report on the patterning of organic single-crystal transistors with high device performance fabricated via a solution process under ambient conditions. The semiconductor was patterned on substrates via surface selective deposition. Subsequently, solvent-vapor annealing was performed to reorganize the semiconductor into single crystals. The transistors exhibited field-effect mobility (μFET of up to 3.5 cm2/V s. Good reliability under bias-stress conditions indicates low density of intrinsic defects in crystals and low density of traps at the active interfaces. Furthermore, the Y function method clearly suggests that the variation of μFET of organic crystal transistors was caused by contact resistance. Further improvement of the device with higher μFET with smaller variation can be expected when lower and more uniform contact resistance is achieved.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons.

Science.gov (United States)

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; Shi, Wu; Lee, Kyunghoon; Wu, Shuang; Yong Choi, Byung; Braganza, Rohit; Lear, Jordan; Kau, Nicholas; Choi, Wonwoo; Chen, Chen; Pedramrazi, Zahra; Dumslaff, Tim; Narita, Akimitsu; Feng, Xinliang; Müllen, Klaus; Fischer, Felix; Zettl, Alex; Ruffieux, Pascal; Yablonovitch, Eli; Crommie, Michael; Fasel, Roman; Bokor, Jeffrey

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch  ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on  > 1 μA at V d  = -1 V) and high I on /I off  ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.Graphene nanoribbons show promise for high-performance field-effect transistors, however they often suffer from short lengths and wide band gaps. Here, the authors use a bottom-up synthesis approach to fabricate 9- and 13-atom wide ribbons, enabling short-channel transistors with 10 5 on-off current ratio.

Impurity Deionization Effects on Surface Recombination DC Current-Voltage Characteristics in MOS Transistors

International Nuclear Information System (INIS)

Chen Zuhui; Jie Binbin; Sah Chihtang

2010-01-01

Impurity deionization on the direct-current current-voltage characteristics from electron-hole recombination (R-DCIV) at SiO 2 /Si interface traps in MOS transistors is analyzed using the steady-state Shockley-Read-Hall recombination kinetics and the Fermi distributions for electrons and holes. Insignificant distortion is observed over 90% of the bell-shaped R-DCIV curves centered at their peaks when impurity deionization is excluded in the theory. This is due to negligible impurity deionization because of the much lower electron and hole concentrations at the interface than the impurity concentration in the 90% range. (invited papers)

Sub-bandgap photonic base current method for characterization of interface states at heterointerfaces in heterojunction bipolar transistors

International Nuclear Information System (INIS)

Shin, H. T.; Kim, K. H.; Kim, K. S.

2004-01-01

In this paper, we propose a novel photonic base current analysis method to characterize the interface states in heterojunction bipolar transistors (HBTs) by using the photonic I-V characteristics under sub-bandgap photonic excitation. For the photonic current-voltage characterization of HBTs, an optical source with a photon energy less than the bandgap energy of Al 0.3 Ga 0.7 As and GaAs (E ph = 0.95 eV g,AlGaAs = 1.79 eV, E g,GaAs = 1.45 eV) is employed for the characterization of the interface states distributed in the photo-responsive energy band (E C - 0.95 ≤ E it ≤ E C ) in emitter-base heterojunction at HBTs. The proposed novel method, which is applied to bipolar junction transistors for the first time, is simple, and an accurate analysis of interface traps in HBTs is possible. By using the photonic base-current and the dark-base-current, we qualitatively analyze the interface trap at the Al 0.3 Ga 0.7 As/GaAs heterojunction interface in HBTs.

Evolution of the MOS transistor - From conception to VLSI

International Nuclear Information System (INIS)

Sah, C.T.

1988-01-01

Historical developments of the metal-oxide-semiconductor field-effect-transistor (MOSFET) during the last sixty years are reviewed, from the 1928 patent disclosures of the field-effect conductivity modulation concept and the semiconductor triodes structures proposed by Lilienfeld to the 1947 Shockley-originated efforts which led to the laboratory demonstration of the modern silicon MOSFET thirty years later in 1960. A survey is then made of the milestones of the past thirty years leading to the latest submicron silicon logic CMOS (Complementary MOS) and BICMOS (Bipolar-Junction-Transistor CMOS combined) arrays and the three-dimensional and ferroelectric extensions of Dennard's one-transistor dynamic random access memory (DRAM) cell. Status of the submicron lithographic technologies (deep ultra-violet light, X-ray, electron-beam) are summarized. Future trends of memory cell density and logic gate speed are projected. Comparisons of the switching speed of the silicon MOSFET with that of silicon bipolar and GaAs field-effect transistors are reviewed. Use of high-temperature superconducting wires and GaAs-on-Si monolithic semiconductor optical clocks to break the interconnect-wiring delay barrier is discussed. Further needs in basic research and mathematical modeling on the failure mechanisms in submicron silicon transistors at high electric fields (hot electron effects) and in interconnection conductors at high current densities and low as well as high electric fields (electromigration) are indicated

A Klein-tunneling transistor with ballistic graphene

International Nuclear Information System (INIS)

Wilmart, Quentin; Fève, Gwendal; Berroir, Jean-Marc; Plaçais, Bernard; Berrada, Salim; Hung Nguyen, V; Dollfus, Philippe; Torrin, David

2014-01-01

Today, the availability of high mobility graphene up to room temperature makes ballistic transport in nanodevices achievable. In particular, p-n-p transistors in the ballistic regime give access to Klein tunneling physics and allow the realization of devices exploiting the optics-like behavior of Dirac Fermions (DFs) as in the Veselago lens or the Fabry–Pérot cavity. Here we propose a Klein tunneling transistor based on the geometrical optics of DFs. We consider the case of a prismatic active region delimited by a triangular gate, where total internal reflection may occur, which leads to the tunable suppression of transistor transmission. We calculate the transmission and the current by means of scattering theory and the finite bias properties using non-equilibrium Green's function (NEGF) simulation. (letter)

Planar edge Schottky barrier-tunneling transistors using epitaxial graphene/SiC junctions.

Science.gov (United States)

Kunc, Jan; Hu, Yike; Palmer, James; Guo, Zelei; Hankinson, John; Gamal, Salah H; Berger, Claire; de Heer, Walt A

2014-09-10

A purely planar graphene/SiC field effect transistor is presented here. The horizontal current flow over one-dimensional tunneling barrier between planar graphene contact and coplanar two-dimensional SiC channel exhibits superior on/off ratio compared to conventional transistors employing vertical electron transport. Multilayer epitaxial graphene (MEG) grown on SiC(0001̅) was adopted as the transistor source and drain. The channel is formed by the accumulation layer at the interface of semi-insulating SiC and a surface silicate that forms after high vacuum high temperature annealing. Electronic bands between the graphene edge and SiC accumulation layer form a thin Schottky barrier, which is dominated by tunneling at low temperatures. A thermionic emission prevails over tunneling at high temperatures. We show that neglecting tunneling effectively causes the temperature dependence of the Schottky barrier height. The channel can support current densities up to 35 A/m.

Area and energy efficient high-performance ZnO wavy channel thin-film transistor

KAUST Repository

Hanna, Amir

2014-09-01

Increased output current while maintaining low power consumption in thin-film transistors (TFTs) is essential for future generation large-area high-resolution displays. Here, we show wavy channel (WC) architecture in TFT that allows the expansion of the transistor width in the direction perpendicular to the substrate through integrating continuous fin features on the underlying substrate. This architecture enables expanding the TFT width without consuming any additional chip area, thus enabling increased performance while maintaining the real estate integrity. The experimental WCTFTs show a linear increase in output current as a function of number of fins per device resulting in (3.5×) increase in output current when compared with planar counterparts that consume the same chip area. The new architecture also allows tuning the threshold voltage as a function of the number of fin features included in the device, as threshold voltage linearly decreased from 6.8 V for planar device to 2.6 V for WC devices with 32 fins. This makes the new architecture more power efficient as lower operation voltages could be used for WC devices compared with planar counterparts. It was also found that field effect mobility linearly increases with the number of fins included in the device, showing almost \\\\(1.8×) enhancements in the field effect mobility than that of the planar counterparts. This can be attributed to higher electric field in the channel due to the fin architecture and threshold voltage shift. © 2014 IEEE.

Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon

KAUST Repository

Lin, Che-Yu

2017-10-04

High-frequency operation with ultra-thin, lightweight and extremely flexible semiconducting electronics are highly desirable for the development of mobile devices, wearable electronic systems and defense technologies. In this work, the first experimental observation of quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe2-MoS2 junctions as the conducting p-n channel is demonstrated. Both lateral n-p-n and p-n-p heterojunction bipolar transistors are fabricated to exhibit the output characteristics and current gain. A maximum common-emitter current gain of around 3 is obtained in our prototype two-dimensional quasi-heterojunction bipolar transistors. Interestingly, we also observe the negative differential resistance in the electrical characteristics. A potential mechanism is that the negative differential resistance is induced by resonant tunneling phenomenon due to the formation of quantum well under applying high bias voltages. Our results open the door to two-dimensional materials for high-frequency, high-speed, high-density and flexible electronics.

Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon

KAUST Repository

Lin, Che-Yu; Zhu, Xiaodan; Tsai, Shin-Hung; Tsai, Shiao-Po; Lei, Sidong; Li, Ming-Yang; Shi, Yumeng; Li, Lain-Jong; Huang, Shyh-Jer; Wu, Wen-Fa; Yeh, Wen-Kuan; Su, Yan-Kuin; Wang, Kang L.; Lan, Yann-Wen

2017-01-01

High-frequency operation with ultra-thin, lightweight and extremely flexible semiconducting electronics are highly desirable for the development of mobile devices, wearable electronic systems and defense technologies. In this work, the first experimental observation of quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe2-MoS2 junctions as the conducting p-n channel is demonstrated. Both lateral n-p-n and p-n-p heterojunction bipolar transistors are fabricated to exhibit the output characteristics and current gain. A maximum common-emitter current gain of around 3 is obtained in our prototype two-dimensional quasi-heterojunction bipolar transistors. Interestingly, we also observe the negative differential resistance in the electrical characteristics. A potential mechanism is that the negative differential resistance is induced by resonant tunneling phenomenon due to the formation of quantum well under applying high bias voltages. Our results open the door to two-dimensional materials for high-frequency, high-speed, high-density and flexible electronics.

Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon.

Science.gov (United States)

Lin, Che-Yu; Zhu, Xiaodan; Tsai, Shin-Hung; Tsai, Shiao-Po; Lei, Sidong; Shi, Yumeng; Li, Lain-Jong; Huang, Shyh-Jer; Wu, Wen-Fa; Yeh, Wen-Kuan; Su, Yan-Kuin; Wang, Kang L; Lan, Yann-Wen

2017-11-28

High-frequency operation with ultrathin, lightweight, and extremely flexible semiconducting electronics is highly desirable for the development of mobile devices, wearable electronic systems, and defense technologies. In this work, the experimental observation of quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe 2 -MoS 2 junctions as the conducting p-n channel is demonstrated. Both lateral n-p-n and p-n-p heterojunction bipolar transistors are fabricated to exhibit the output characteristics and current gain. A maximum common-emitter current gain of around 3 is obtained in our prototype two-dimensional quasi-heterojunction bipolar transistors. Interestingly, we also observe the negative differential resistance in the electrical characteristics. A potential mechanism is that the negative differential resistance is induced by resonant tunneling phenomenon due to the formation of quantum well under applying high bias voltages. Our results open the door to two-dimensional materials for high-frequency, high-speed, high-density, and flexible electronics.

Organic electrochemical transistors

Science.gov (United States)

Rivnay, Jonathan; Inal, Sahika; Salleo, Alberto; Owens, Róisín M.; Berggren, Magnus; Malliaras, George G.

2018-02-01

Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume of the channel endows OECTs with high transconductance compared with that of field-effect transistors, but also limits their response time. The synthetic tunability, facile deposition and biocompatibility of organic materials make OECTs particularly suitable for applications in biological interfacing, printed logic circuitry and neuromorphic devices. In this Review, we discuss the physics and the mechanism of operation of OECTs, focusing on their identifying characteristics. We highlight organic materials that are currently being used in OECTs and survey the history of OECT technology. In addition, form factors, fabrication technologies and applications such as bioelectronics, circuits and memory devices are examined. Finally, we take a critical look at the future of OECT research and development.

Organic electrochemical transistors

KAUST Repository

Rivnay, Jonathan

2018-01-16

Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume of the channel endows OECTs with high transconductance compared with that of field-effect transistors, but also limits their response time. The synthetic tunability, facile deposition and biocompatibility of organic materials make OECTs particularly suitable for applications in biological interfacing, printed logic circuitry and neuromorphic devices. In this Review, we discuss the physics and the mechanism of operation of OECTs, focusing on their identifying characteristics. We highlight organic materials that are currently being used in OECTs and survey the history of OECT technology. In addition, form factors, fabrication technologies and applications such as bioelectronics, circuits and memory devices are examined. Finally, we take a critical look at the future of OECT research and development.

Achievement of normally-off AlGaN/GaN high-electron mobility transistor with p-NiO{sub x} capping layer by sputtering and post-annealing

Energy Technology Data Exchange (ETDEWEB)

Huang, Shyh-Jer [Department of Electrical Engineering, Institute of Microelectronics and Advanced Optoelectronic Technology Center, National Cheng Kung University, Tainan, Taiwan (China); Chou, Cheng-Wei, E-mail: j2222222229@gmail.com [Department of Electrical Engineering, Institute of Microelectronics and Advanced Optoelectronic Technology Center, National Cheng Kung University, Tainan, Taiwan (China); Su, Yan-Kuin, E-mail: yksu@mail.ncku.edu.tw [Department of Electrical Engineering, Institute of Microelectronics and Advanced Optoelectronic Technology Center, National Cheng Kung University, Tainan, Taiwan (China); Lin, Jyun-Hao; Yu, Hsin-Chieh; Chen, De-Long [Department of Electrical Engineering, Institute of Microelectronics and Advanced Optoelectronic Technology Center, National Cheng Kung University, Tainan, Taiwan (China); Ruan, Jian-Long [National Chung-Shan Institute of Science and Technology, Taoyuan, Taiwan (China)

2017-04-15

Highlights: • A technique to fabricate normally off GaN-based high-electron mobility transistor (HEMT) by sputtering and post-annealing p-NiO{sub x} capping layer. • The V{sub th} shifts from −3 V in the conventional transistor to 0.33 V, and on/off current ratio became 10{sup 7}. • The reverse gate leakage current is 10{sup −9} A/mm, and the off-state drain-leakage current is 10{sup −8} A/mm. • The V{sub th} hysteresis is extremely small at about 33 mV. - Abstract: In this paper, we present a technique to fabricate normally off GaN-based high-electron mobility transistor (HEMT) by sputtering and post-annealing p-NiO{sub x} capping layer. The p-NiO{sub x} layer is produced by sputtering at room temperature and post-annealing at 500 °C for 30 min in pure O{sub 2} environment to achieve high hole concentration. The V{sub th} shifts from −3 V in the conventional transistor to 0.33 V, and on/off current ratio became 10{sup 7}. The forward and reverse gate breakdown increase from 3.5 V and −78 V to 10 V and −198 V, respectively. The reverse gate leakage current is 10{sup −9} A/mm, and the off-state drain-leakage current is 10{sup −8} A/mm. The V{sub th} hysteresis is extremely small at about 33 mV. We also investigate the mechanism that increases hole concentration of p-NiO{sub x} after annealing in oxygen environment resulted from the change of Ni{sup 2+} to Ni{sup 3+} and the surge of (111)-orientation.

Drain current enhancement induced by hole injection from gate of 600-V-class normally off gate injection transistor under high temperature conditions up to 200 °C

Science.gov (United States)

Ishii, Hajime; Ueno, Hiroaki; Ueda, Tetsuzo; Endoh, Tetsuo

2018-06-01

In this paper, the current–voltage (I–V) characteristics of a 600-V-class normally off GaN gate injection transistor (GIT) from 25 to 200 °C are analyzed, and it is revealed that the drain current of the GIT increases during high-temperature operation. It is found that the maximum drain current (I dmax) of the GIT is 86% higher than that of a conventional 600-V-class normally off GaN metal insulator semiconductor hetero-FET (MIS-HFET) at 150 °C, whereas the GIT obtains 56% I dmax even at 200 °C. Moreover, the mechanism of the drain current increase of the GIT is clarified by examining the relationship between the temperature dependence of the I–V characteristics of the GIT and the gate hole injection effect determined from the shift of the second transconductance (g m) peak of the g m–V g characteristic. From the above, the GIT is a promising device with enough drivability for future power switching applications even under high-temperature conditions.

Gold nanoparticle-pentacene memory-transistors

OpenAIRE

Novembre , Christophe; Guerin , David; Lmimouni , Kamal; Gamrat , Christian; Vuillaume , Dominique

2008-01-01

We demonstrate an organic memory-transistor device based on a pentacene-gold nanoparticles active layer. Gold (Au) nanoparticles are immobilized on the gate dielectric (silicon dioxide) of a pentacene transistor by an amino-terminated self-assembled monolayer. Under the application of writing and erasing pulses on the gate, large threshold voltage shift (22 V) and on/off drain current ratio of ~3E4 are obtained. The hole field-effect mobility of the transistor is similar in the on and off sta...

Polymer-Sorted Semiconducting Carbon Nanotube Networks for High-Performance Ambipolar Field-Effect Transistors

Science.gov (United States)

2014-01-01

Efficient selection of semiconducting single-walled carbon nanotubes (SWNTs) from as-grown nanotube samples is crucial for their application as printable and flexible semiconductors in field-effect transistors (FETs). In this study, we use atactic poly(9-dodecyl-9-methyl-fluorene) (a-PF-1-12), a polyfluorene derivative with asymmetric side-chains, for the selective dispersion of semiconducting SWNTs with large diameters (>1 nm) from plasma torch-grown SWNTs. Lowering the molecular weight of the dispersing polymer leads to a significant improvement of selectivity. Combining dense semiconducting SWNT networks deposited from an enriched SWNT dispersion with a polymer/metal-oxide hybrid dielectric enables transistors with balanced ambipolar, contact resistance-corrected mobilities of up to 50 cm2·V–1·s–1, low ohmic contact resistance, steep subthreshold swings (0.12–0.14 V/dec) and high on/off ratios (106) even for short channel lengths (<10 μm). These FETs operate at low voltages (<3 V) and show almost no current hysteresis. The resulting ambipolar complementary-like inverters exhibit gains up to 61. PMID:25493421

Carbon nanotube transistors scaled to a 40-nanometer footprint.

Science.gov (United States)

Cao, Qing; Tersoff, Jerry; Farmer, Damon B; Zhu, Yu; Han, Shu-Jen

2017-06-30

The International Technology Roadmap for Semiconductors challenges the device research community to reduce the transistor footprint containing all components to 40 nanometers within the next decade. We report on a p-channel transistor scaled to such an extremely small dimension. Built on one semiconducting carbon nanotube, it occupies less than half the space of leading silicon technologies, while delivering a significantly higher pitch-normalized current density-above 0.9 milliampere per micrometer at a low supply voltage of 0.5 volts with a subthreshold swing of 85 millivolts per decade. Furthermore, we show transistors with the same small footprint built on actual high-density arrays of such nanotubes that deliver higher current than that of the best-competing silicon devices under the same overdrive, without any normalization. We achieve this using low-resistance end-bonded contacts, a high-purity semiconducting carbon nanotube source, and self-assembly to pack nanotubes into full surface-coverage aligned arrays. Copyright © 2017 The Authors, some rights reserved; exclusive licensee American Association for the Advancement of Science. No claim to original U.S. Government Works.

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

International Nuclear Information System (INIS)

Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.; Hussain, A. M.; Hussain, M. M.

2013-01-01

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

KAUST Repository

Hanna, Amir; Ghoneim, Mohamed T.; Bahabry, Rabab R.; Hussain, Aftab M.; Hussain, Muhammad Mustafa

2013-01-01

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

KAUST Repository

Hanna, Amir

2013-11-26

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Copper atomic-scale transistors.

Science.gov (United States)

Xie, Fangqing; Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen; Schimmel, Thomas

2017-01-01

We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO 4 + H 2 SO 4 ) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and -170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes ( U bias ) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1 G 0 ( G 0 = 2e 2 /h; with e being the electron charge, and h being Planck's constant) or 2 G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.

MHz repetition rate solid-state driver for high current induction accelerators

International Nuclear Information System (INIS)

Brooksby, C; Caporaso, G; Goerz, D; Hanks, R; Hickman, B; Kirbie, H; Lee, B; Saethre, R.

1999-01-01

A research team from the Lawrence Livermore National Laboratory and Bechtel Nevada Corporation is developing an all solid-state power source for high current induction accelerators. The original power system design, developed for heavy-ion fusion accelerators, is based on the simple idea of using an array of field effect transistors to switch energy from a pre-charged capacitor bank to an induction accelerator cell. Recently, that idea has been expanded to accommodate the greater power needs of a new class of high-current electron accelerators for advanced radiography. For this purpose, we developed a 3-stage induction adder that uses over 4,000 field effect transistors to switch peak voltages of 45 kV at currents up to 4.8 kA with pulse repetition rates of up to 2 MHz. This radically advanced power system can generate a burst of five or more pulses that vary from 200 ns to 2 ampersand micro;s at a duty cycle of up to 25%. Our new source is precise, robust, flexible, and exceeds all previous drivers for induction machines by a factor of 400 in repetition rate and a factor of 1000 in duty cycle

High performance tunnel field-effect transistor by gate and source engineering

International Nuclear Information System (INIS)

Huang, Ru; Huang, Qianqian; Chen, Shaowen; Wu, Chunlei; Wang, Jiaxin; An, Xia; Wang, Yangyuan

2014-01-01

As one of the most promising candidates for future nanoelectronic devices, tunnel field-effect transistors (TFET) can overcome the subthreshold slope (SS) limitation of MOSFET, whereas high ON-current, low OFF-current and steep switching can hardly be obtained at the same time for experimental TFETs. In this paper, we developed a new nanodevice technology based on TFET concepts. By designing the gate configuration and introducing the optimized Schottky junction, a multi-finger-gate TFET with a dopant-segregated Schottky source (mFSB-TFET) is proposed and experimentally demonstrated. A steeper SS can be achieved in the fabricated mFSB-TFET on the bulk Si substrate benefiting from the coupled quantum band-to-band tunneling (BTBT) mechanism, as well as a high I ON /I OFF ratio (∼10 7 ) at V DS  = 0.2 V without an area penalty. By compatible SOI CMOS technology, the fabricated Si mFSB-TFET device was further optimized with a high I ON /I OFF ratio of ∼10 8 and a steeper SS of over 5.5 decades of current. A minimum SS of below 60 mV dec −1 was experimentally obtained, indicating its dominant quantum BTBT mechanism for switching. (paper)

Balancing Hole and Electron Conduction in Ambipolar Split-Gate Thin-Film Transistors.

Science.gov (United States)

Yoo, Hocheon; Ghittorelli, Matteo; Lee, Dong-Kyu; Smits, Edsger C P; Gelinck, Gerwin H; Ahn, Hyungju; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2017-07-10

Complementary organic electronics is a key enabling technology for the development of new applications including smart ubiquitous sensors, wearable electronics, and healthcare devices. High-performance, high-functionality and reliable complementary circuits require n- and p-type thin-film transistors with balanced characteristics. Recent advancements in ambipolar organic transistors in terms of semiconductor and device engineering demonstrate the great potential of this route but, unfortunately, the actual development of ambipolar organic complementary electronics is currently hampered by the uneven electron (n-type) and hole (p-type) conduction in ambipolar organic transistors. Here we show ambipolar organic thin-film transistors with balanced n-type and p-type operation. By manipulating air exposure and vacuum annealing conditions, we show that well-balanced electron and hole transport properties can be easily obtained. The method is used to control hole and electron conductions in split-gate transistors based on a solution-processed donor-acceptor semiconducting polymer. Complementary logic inverters with balanced charging and discharging characteristics are demonstrated. These findings may open up new opportunities for the rational design of complementary electronics based on ambipolar organic transistors.

Design and simulation of a novel GaN based resonant tunneling high electron mobility transistor on a silicon substrate

International Nuclear Information System (INIS)

Chowdhury, Subhra; Biswas, Dhrubes; Chattaraj, Swarnabha

2015-01-01

For the first time, we have introduced a novel GaN based resonant tunneling high electron mobility transistor (RTHEMT) on a silicon substrate. A monolithically integrated GaN based inverted high electron mobility transistor (HEMT) and a resonant tunneling diode (RTD) are designed and simulated using the ATLAS simulator and MATLAB in this study. The 10% Al composition in the barrier layer of the GaN based RTD structure provides a peak-to-valley current ratio of 2.66 which controls the GaN based HEMT performance. Thus the results indicate an improvement in the current–voltage characteristics of the RTHEMT by controlling the gate voltage in this structure. The introduction of silicon as a substrate is a unique step taken by us for this type of RTHEMT structure. (paper)

Solution-processable precursor route for fabricating ultrathin silica film for high performance and low voltage organic transistors

Institute of Scientific and Technical Information of China (English)

Shujing Guo; Liqiang Li; Zhongwu Wang; Zeyang Xu; Shuguang Wang; Kunjie Wu; Shufeng Chen; Zongbo Zhang; Caihong Xu; Wenfeng Qiu

2017-01-01

Silica is one of the most commonly used materials for dielectric layer in organic thin-film transistors due to its excellent stability,excellent electrical properties,mature preparation process,and good compatibility with organic semiconductors.However,most of conventional preparation methods for silica film are generally performed at high temperature and/or high vacuum.In this paper,we introduce a simple solution spin-coating method to fabricate silica thin film from precursor route,which possesses a low leakage current,high capacitance,and low surface roughness.The silica thin film can be produced in the condition of low temperature and atmospheric environment.To meet various demands,the thickness of film can be adjusted by means of preparation conditions such as the speed of spin-coating and the concentration of solution.The p-type and n-type organic field effect transistors fabricated by using this film as gate electrodes exhibit excellent electrical performance including low voltage and high performance.This method shows great potential for industrialization owing to its characteristic of low consumption and energy saving,time-saving and easy to operate.

High current high accuracy IGBT pulse generator

International Nuclear Information System (INIS)

Nesterov, V.V.; Donaldson, A.R.

1995-05-01

A solid state pulse generator capable of delivering high current triangular or trapezoidal pulses into an inductive load has been developed at SLAC. Energy stored in a capacitor bank of the pulse generator is switched to the load through a pair of insulated gate bipolar transistors (IGBT). The circuit can then recover the remaining energy and transfer it back to the capacitor bank without reversing the capacitor voltage. A third IGBT device is employed to control the initial charge to the capacitor bank, a command charging technique, and to compensate for pulse to pulse power losses. The rack mounted pulse generator contains a 525 μF capacitor bank. It can deliver 500 A at 900V into inductive loads up to 3 mH. The current amplitude and discharge time are controlled to 0.02% accuracy by a precision controller through the SLAC central computer system. This pulse generator drives a series pair of extraction dipoles

A CURRENT MIRROR BASED TWO STAGE CMOS CASCODE OP-AMP FOR HIGH FREQUENCY APPLICATION

Directory of Open Access Journals (Sweden)

RAMKRISHNA KUNDU

2017-03-01

Full Text Available This paper presents a low power, high slew rate, high gain, ultra wide band two stage CMOS cascode operational amplifier for radio frequency application. Current mirror based cascoding technique and pole zero cancelation technique is used to ameliorate the gain and enhance the unity gain bandwidth respectively, which is the novelty of the circuit. In cascading technique a common source transistor drive a common gate transistor. The cascoding is used to enhance the output resistance and hence improve the overall gain of the operational amplifier with less complexity and less power dissipation. To bias the common gate transistor, a current mirror is used in this paper. The proposed circuit is designed and simulated using Cadence analog and digital system design tools of 45 nanometer CMOS technology. The simulated results of the circuit show DC gain of 63.62 dB, unity gain bandwidth of 2.70 GHz, slew rate of 1816 V/µs, phase margin of 59.53º, power supply of the proposed operational amplifier is 1.4 V (rail-to-rail ±700 mV, and power consumption is 0.71 mW. This circuit specification has encountered the requirements of radio frequency application.

Very High Frequency Two-Port Characterization of Transistors

DEFF Research Database (Denmark)

Hertel, Jens Christian; Nour, Yasser; Jørgensen, Ivan Harald Holger

To properly use transistors in VHF converters, they need to be characterized under similar conditions. This research presents a two-port method, using a network analyzer (NWA) with a S-port setup. The method is a one-shot method, providing fast results of the off-state parasitics of the transistors....

Current transport modeling and experimental study of THz room temperature ballistic deflection transistors

Energy Technology Data Exchange (ETDEWEB)

Kaushal, Vikas; Margala, Martin [Department of Electrical and Computer Engineering, University of Massachusetts Lowell, MA, 01854 (United States); Yu Qiaoyan; Ampadu, Paul; Guarino, Gregg; Sobolewski, Roman, E-mail: vikas_kaushal@student.uml.ed [Department of Electrical and Computer Engineering, University of Rochester, NY, 14627 (United States)

2009-11-15

In this paper, two different theoretical models, Comsol Multiphysics{sup TM} (a Finite Element Analysis tool), and a field solver Atlas/Blaze from Silvaco, are compared qualitatively to study the effect of the deflector position, its size and electric field on the charge transport and its distribution along the channel, resulting in current outputs and leakages in ballistic deflection transistors (BDT). Silvaco simulations and experimental results were then used to study the lateral charge transport as a result of variation in electric field distribution, which controls the charge current along the channel in BDT. The electric field dependence of gain is also studied with experimental and theoretical results.

Current transport modeling and experimental study of THz room temperature ballistic deflection transistors

International Nuclear Information System (INIS)

Kaushal, Vikas; Margala, Martin; Yu Qiaoyan; Ampadu, Paul; Guarino, Gregg; Sobolewski, Roman

2009-01-01

In this paper, two different theoretical models, Comsol Multiphysics TM (a Finite Element Analysis tool), and a field solver Atlas/Blaze from Silvaco, are compared qualitatively to study the effect of the deflector position, its size and electric field on the charge transport and its distribution along the channel, resulting in current outputs and leakages in ballistic deflection transistors (BDT). Silvaco simulations and experimental results were then used to study the lateral charge transport as a result of variation in electric field distribution, which controls the charge current along the channel in BDT. The electric field dependence of gain is also studied with experimental and theoretical results.

Silicon nanowire transistors

CERN Document Server

Bindal, Ahmet

2016-01-01

This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology’s true potential for the next generation VLSI. Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types...

Radiation effects on JFETS, MOSFETS, and bipolar transistors, as related to SSC circuit design

Energy Technology Data Exchange (ETDEWEB)

Kennedy, E J; Gray, B; Wu, A [Dept. of Electrical and Computer Engineering, Univ. of Tennessee, Knoxville, TN (United States); Alley, G T; Britton, Jr, C L [Oak Ridge National Lab., TN (United States); Skubic, P L [Univ. of Oklahoma, Dept. of Physics and Astronomy, Norman, OK (United States)

1991-10-01

Some results of radiation effects on selected junction field-effect transistors, MOS field-effect transistors, and bipolar junction transistors are presented. The evaluations include dc parameters, as well as capacitive variations and noise evaluations. The tests are made at the low current and voltage levels (in particular at currents {<=} 1 mA) that are essential for the low-power regimes required by SSC circuitry. Detailed noise data are presented both before and after 5-Mrad (gamma) total-dose exposure. SPICE radiation models for three high-frequency bipolar processes are compared for a typical charge-sensitive preamplifier. (orig.).

Piezotronic effect tuned AlGaN/GaN high electron mobility transistor

Science.gov (United States)

Jiang, Chunyan; Liu, Ting; Du, Chunhua; Huang, Xin; Liu, Mengmeng; Zhao, Zhenfu; Li, Linxuan; Pu, Xiong; Zhai, Junyi; Hu, Weiguo; Wang, Zhong Lin

2017-11-01

The piezotronic effect utilizes strain-induced piezoelectric polarization charges to tune the carrier transportation across the interface/junction. We fabricated a high-performance AlGaN/GaN high electron mobility transistor (HEMT), and the transport property was proven to be enhanced by applying an external stress for the first time. The enhanced source-drain current was also observed at any gate voltage and the maximum enhancement of the saturation current was up to 21% with 15 N applied stress (0.18 GPa at center) at -1 V gate voltage. The physical mechanism of HEMT with/without external compressive stress conditions was carefully illustrated and further confirmed by a self-consistent solution of the Schrödinger-Poisson equations. This study proves the cause-and-effect relationship between the piezoelectric polarization effect and 2D electron gas formation, which provides a tunable solution to enhance the device performance. The strain tuned HEMT has potential applications in human-machine interface and the security control of the power system.

Molecular gated-AlGaN/GaN high electron mobility transistor for pH detection.

Science.gov (United States)

Ding, Xiangzhen; Yang, Shuai; Miao, Bin; Gu, Le; Gu, Zhiqi; Zhang, Jian; Wu, Baojun; Wang, Hong; Wu, Dongmin; Li, Jiadong

2018-04-18

A molecular gated-AlGaN/GaN high electron mobility transistor has been developed for pH detection. The sensing surface of the sensor was modified with 3-aminopropyltriethoxysilane to provide amphoteric amine groups, which would play the role of receptors for pH detection. On modification with 3-aminopropyltriethoxysilane, the transistor exhibits good chemical stability in hydrochloric acid solution and is sensitive for pH detection. Thus, our molecular gated-AlGaN/GaN high electron mobility transistor acheived good electrical performances such as chemical stability (remained stable in hydrochloric acid solution), good sensitivity (37.17 μA/pH) and low hysteresis. The results indicate a promising future for high-quality sensors for pH detection.

On-Chip Sorting of Long Semiconducting Carbon Nanotubes for Multiple Transistors along an Identical Array.

Science.gov (United States)

Otsuka, Keigo; Inoue, Taiki; Maeda, Etsuo; Kometani, Reo; Chiashi, Shohei; Maruyama, Shigeo

2017-11-28

Ballistic transport and sub-10 nm channel lengths have been achieved in transistors containing one single-walled carbon nanotube (SWNT). To fill the gap between single-tube transistors and high-performance logic circuits for the replacement of silicon, large-area, high-density, and purely semiconducting (s-) SWNT arrays are highly desired. Here we demonstrate the fabrication of multiple transistors along a purely semiconducting SWNT array via an on-chip purification method. Water- and polymer-assisted burning from site-controlled nanogaps is developed for the reliable full-length removal of metallic SWNTs with the damage to s-SWNTs minimized even in high-density arrays. All the transistors with various channel lengths show large on-state current and excellent switching behavior in the off-state. Since our method potentially provides pure s-SWNT arrays over a large area with negligible damage, numerous transistors with arbitrary dimensions could be fabricated using a conventional semiconductor process, leading to SWNT-based logic, high-speed communication, and other next-generation electronic devices.

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Directory of Open Access Journals (Sweden)

Tooraj Nikoubin

2010-01-01

Full Text Available A new transistor sizing algorithm, SEA (Simple Exact Algorithm, for optimizing low-power and high-speed arithmetic integrated circuits is proposed. In comparison with other transistor sizing algorithms, simplicity, accuracy, independency of order and initial sizing factors of transistors, and flexibility in choosing the optimization parameters such as power consumption, delay, Power-Delay Product (PDP, chip area or the combination of them are considered as the advantages of this new algorithm. More exhaustive rules of grouping transistors are the main trait of our algorithm. Hence, the SEA algorithm dominates some major transistor sizing metrics such as optimization rate, simulation speed, and reliability. According to approximate comparison of the SEA algorithm with MDE and ADC for a number of conventional full adder circuits, delay and PDP have been improved 55.01% and 57.92% on an average, respectively. By comparing the SEA and Chang's algorithm, 25.64% improvement in PDP and 33.16% improvement in delay have been achieved. All the simulations have been performed with 0.13 m technology based on the BSIM3v3 model using HSpice simulator software.

Effects of Energy Relaxation via Quantum Coupling Among Three-Dimensional Motion on the Tunneling Current of Graphene Field-Effect Transistors.

Science.gov (United States)

Mao, Ling-Feng; Ning, Huansheng; Li, Xijun

2015-12-01

We report theoretical study of the effects of energy relaxation on the tunneling current through the oxide layer of a two-dimensional graphene field-effect transistor. In the channel, when three-dimensional electron thermal motion is considered in the Schrödinger equation, the gate leakage current at a given oxide field largely increases with the channel electric field, electron mobility, and energy relaxation time of electrons. Such an increase can be especially significant when the channel electric field is larger than 1 kV/cm. Numerical calculations show that the relative increment of the tunneling current through the gate oxide will decrease with increasing the thickness of oxide layer when the oxide is a few nanometers thick. This highlights that energy relaxation effect needs to be considered in modeling graphene transistors.

Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process

Science.gov (United States)

Song, Ki-Whan; Lee, Yong Kyu; Sim, Jae Sung; Kim, Kyung Rok; Lee, Jong Duk; Park, Byung-Gook; You, Young Sub; Park, Joo-On; Jin, You Seung; Kim, Young-Wug

2005-04-01

We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

Low-background transistors for application in nuclear electronics

International Nuclear Information System (INIS)

Krasnokutskij, R.N.; Kurchaninov, L.L.; Fedyakin, N.N.; Shuvalov, R.S.

1988-01-01

Investigations of silicon transistors were carried out to determine transistors with low value of base distributed resistance (R). Measurement results for R and current amplification coefficient β are presented for bipolar transistor several types. Correlations between R and β were studied. KT 399A, 2T640A and KT3117B transistors are found to be most adequate ones as a base for low-background amplifier development

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

Science.gov (United States)

Deen, David A.; Storm, David F.; Scott Katzer, D.; Bass, R.; Meyer, David J.

2016-08-01

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain current after bias stressed in subthreshold. These structures additionally achieved small signal metrics ft/fmax of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with ft/fmax of 48/60 GHz.

Controllable electrical properties of metal-doped In2O3 nanowires for high-performance enhancement-mode transistors.

Science.gov (United States)

Zou, Xuming; Liu, Xingqiang; Wang, Chunlan; Jiang, Ying; Wang, Yong; Xiao, Xiangheng; Ho, Johnny C; Li, Jinchai; Jiang, Changzhong; Xiong, Qihua; Liao, Lei

2013-01-22

In recent years, In(2)O(3) nanowires (NWs) have been widely explored in many technological areas due to their excellent electrical and optical properties; however, most of these devices are based on In(2)O(3) NW field-effect transistors (FETs) operating in the depletion mode, which induces relatively higher power consumption and fancier circuit integration design. Here, n-type enhancement-mode In(2)O(3) NW FETs are successfully fabricated by doping different metal elements (Mg, Al, and Ga) in the NW channels. Importantly, the resulting threshold voltage can be effectively modulated through varying the metal (Mg, Ga, and Al) content in the NWs. A series of scaling effects in the mobility, transconductance, threshold voltage, and source-drain current with respect to the device channel length are also observed. Specifically, a small gate delay time (0.01 ns) and high on-current density (0.9 mA/μm) are obtained at 300 nm channel length. Furthermore, Mg-doped In(2)O(3) NWs are then employed to fabricate NW parallel array FETs with a high saturation current (0.5 mA), on/off ratio (>10(9)), and field-effect mobility (110 cm(2)/V·s), while the subthreshold slope and threshold voltage do not show any significant changes. All of these results indicate the great potency for metal-doped In(2)O(3) NWs used in the low-power, high-performance thin-film transistors.

Botulinum toxin detection using AlGaN /GaN high electron mobility transistors

Science.gov (United States)

Wang, Yu-Lin; Chu, B. H.; Chen, K. H.; Chang, C. Y.; Lele, T. P.; Tseng, Y.; Pearton, S. J.; Ramage, J.; Hooten, D.; Dabiran, A.; Chow, P. P.; Ren, F.

2008-12-01

Antibody-functionalized, Au-gated AlGaN /GaN high electron mobility transistors (HEMTs) were used to detect botulinum toxin. The antibody was anchored to the gate area through immobilized thioglycolic acid. The AlGaN /GaN HEMT drain-source current showed a rapid response of less than 5s when the target toxin in a buffer was added to the antibody-immobilized surface. We could detect a range of concentrations from 1to10ng/ml. These results clearly demonstrate the promise of field-deployable electronic biological sensors based on AlGaN /GaN HEMTs for botulinum toxin detection.

Diketopyrrolopyrrole-diketopyrrolopyrrole-based conjugated copolymer for high-mobility organic field-effect transistors

KAUST Repository

Kanimozhi, Catherine K.

2012-10-10

In this communication, we report the synthesis of a novel diketopyrrolopyrrole-diketopyrrolopyrrole (DPP-DPP)-based conjugated copolymer and its application in high-mobility organic field-effect transistors. Copolymerization of DPP with DPP yields a copolymer with exceptional properties such as extended absorption characteristics (up to ∼1100 nm) and field-effect electron mobility values of >1 cm 2 V -1 s -1. The synthesis of this novel DPP-DPP copolymer in combination with the demonstration of transistors with extremely high electron mobility makes this work an important step toward a new family of DPP-DPP copolymers for application in the general area of organic optoelectronics. © 2012 American Chemical Society.

Flexible Graphene Transistor Architecture for Optical Sensor Technology

Science.gov (United States)

Ordonez, Richard Christopher

The unique electrical and optoelectronic properties of graphene allow tunable conductivity and broadband electromagnetic absorption that spans the ultraviolet and infrared regimes. However, in the current state-of-art graphene sensor architectures, junction resistance and doping concentration are predominant factors that affect signal strength and sensitivity. Unfortunately, graphene produces high contact resistances with standard electrode materials ( few kilo-ohms), therefore, signal is weak and large carrier concentrations are required to probe sensitivity. Moreover, the atomic thickness of graphene enables the potential for flexible electronics, but there has not been a successful graphene sensor architecture that demonstrates stable operation on flexible substrates and with minimal fabrication cost. In this study, the author explores a novel 3-terminal transistor architecture that integrates twodimensional graphene, liquid metal, and electrolytic gate dielectrics (LM-GFETs: Liquid Metal and Graphene Field-Effect Transistors ). The goal is to deliver a sensitive, flexible, and lightweight transistor architecture that will improve sensor technology and maneuverability. The reported high thermal conductivity of graphene provides potential for room-temperature thermal management without the need of thermal-electric and gas cooling systems that are standard in sensor platforms. Liquid metals provide a unique opportunity for conformal electrodes that maximize surface area contact, therefore, enable flexibility, lower contact resistance, and reduce damage to the graphene materials involved. Lastly, electrolytic gate dielectrics provide conformability and high capacitances needed for high on/off rations and electrostatic gating. Results demonstrated that with minimal fabrication steps the proposed flexible graphene transistor architecture demonstrated ambipolar current-voltage transfer characteristics that are comparable to the current state-of-the-art. An additional

Thermal Investigation of Three-Dimensional GaN-on-SiC High Electron Mobility Transistors

Science.gov (United States)

2017-07-01

University of L’Aquila, (2011). 23 Rao, H. & Bosman, G. Hot-electron induced defect generation in AlGaN/GaN high electron mobility transistors. Solid...AFRL-RY-WP-TR-2017-0143 THERMAL INVESTIGATION OF THREE- DIMENSIONAL GaN-on-SiC HIGH ELECTRON MOBILITY TRANSISTORS Qing Hao The University of Arizona...clarification memorandum dated 16 Jan 09. This report is available to the general public, including foreign nationals. Copies may be obtained from the

Flexible low-voltage organic transistors with high thermal stability at 250 °C.

Science.gov (United States)

Yokota, Tomoyuki; Kuribara, Kazunori; Tokuhara, Takeyoshi; Zschieschang, Ute; Klauk, Hagen; Takimiya, Kazuo; Sadamitsu, Yuji; Hamada, Masahiro; Sekitani, Tsuyoshi; Someya, Takao

2013-07-19

Low-operating-voltage flexible organic thin-film transistors with high thermal stability using DPh-DNTT and SAM gate dielectrics are reported. The mobility of the transistors are decreased by 23% after heating to 250 °C for 30 min. Furthermore, flexible organic pseudo-CMOS inverter circuits, which are functional after heating to 200 °C, are demonstrated. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Large magnetocurrents in double-barrier tunneling transistors

International Nuclear Information System (INIS)

Lee, J.H.; Jun, K.-I.; Shin, K.-H.; Park, S.Y.; Hong, J.K.; Rhie, K.; Lee, B.C.

2005-01-01

Magnetic tunneling transistors (MTT) with double tunneling barriers are fabricated. The structure of the transistor is AFM/FM/I/FM/I/FM/AFM, and ferromagnetic layers serve as the emitter, base and collector. This double-barrier tunneling transistor (DBTT) has an advantage of controlling the potential between the base and collector, compared to the Schottky-barrier-based base and collector of MTT. We found that the collector current density of DBTT is at least 10 3 times larger than that of conventional MTT, since tunneling through AlO x barrier provides much larger current density than that through Schottky barrier

Atmospheric pressure chemical vapor deposition (APCVD) grown bi-layer graphene transistor characteristics at high temperature

KAUST Repository

Qaisi, Ramy M.; Smith, Casey; Hussain, Muhammad Mustafa

2014-01-01

We report the characteristics of atmospheric chemical vapor deposition grown bilayer graphene transistors fabricated on ultra-scaled (10 nm) high-κ dielectric aluminum oxide (Al2O3) at elevated temperatures. We observed that the drive current increased by >400% as temperature increased from room temperature to 250 °C. Low gate leakage was maintained for prolonged exposure at 100 °C but increased significantly at temperatures >200 °C. These results provide important insights for considering chemical vapor deposition graphene on aluminum oxide for high temperature applications where low power and high frequency operation are required. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Atmospheric pressure chemical vapor deposition (APCVD) grown bi-layer graphene transistor characteristics at high temperature

KAUST Repository

Qaisi, Ramy M.

2014-05-15

We report the characteristics of atmospheric chemical vapor deposition grown bilayer graphene transistors fabricated on ultra-scaled (10 nm) high-κ dielectric aluminum oxide (Al2O3) at elevated temperatures. We observed that the drive current increased by >400% as temperature increased from room temperature to 250 °C. Low gate leakage was maintained for prolonged exposure at 100 °C but increased significantly at temperatures >200 °C. These results provide important insights for considering chemical vapor deposition graphene on aluminum oxide for high temperature applications where low power and high frequency operation are required. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with reduced leakage current and enhanced breakdown voltage using aluminum ion implantation

Energy Technology Data Exchange (ETDEWEB)

Sun, Shichuang [Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan 430074 (China); Key Laboratory of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, CAS, Suzhou 215123 (China); Fu, Kai, E-mail: kfu2009@sinano.ac.cn, E-mail: cqchen@mail.hust.edu.cn; Yu, Guohao; Zhang, Zhili; Song, Liang; Deng, Xuguang; Li, Shuiming; Sun, Qian; Cai, Yong; Zhang, Baoshun [Key Laboratory of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, CAS, Suzhou 215123 (China); Qi, Zhiqiang; Dai, Jiangnan; Chen, Changqing, E-mail: kfu2009@sinano.ac.cn, E-mail: cqchen@mail.hust.edu.cn [Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan 430074 (China)

2016-01-04

This letter has studied the performance of AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors on silicon substrate with GaN buffer treated by aluminum ion implantation for insulating followed by a channel regrown by metal–organic chemical vapor deposition. For samples with Al ion implantation of multiple energies of 140 keV (dose: 1.4 × 10{sup 14} cm{sup −2}) and 90 keV (dose: 1 × 10{sup 14} cm{sup −2}), the OFF-state leakage current is decreased by more than 3 orders and the breakdown voltage is enhanced by nearly 6 times compared to the samples without Al ion implantation. Besides, little degradation of electrical properties of the 2D electron gas channel is observed where the maximum drain current I{sub DSmax} at a gate voltage of 3 V was 701 mA/mm and the maximum transconductance g{sub mmax} was 83 mS/mm.

Efficient simulation of power MOS transistors

NARCIS (Netherlands)

Ugryumova, M.; Schilders, W.H.A.

2011-01-01

In this report we present a few industrial problems related to modeling of MOS transistors. We suggest an efficient algorithm for computing output current at the top ports of power MOS transistors for given voltage excitations. The suggested algorithm exploits the connection between the resistor and

GaN-on-silicon high-electron-mobility transistor technology with ultra-low leakage up to 3000 V using local substrate removal and AlN ultra-wide bandgap

Science.gov (United States)

Dogmus, Ezgi; Zegaoui, Malek; Medjdoub, Farid

2018-03-01

We report on extremely low off-state leakage current in AlGaN/GaN-on-silicon metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) up to a high blocking voltage. Remarkably low off-state gate and drain leakage currents below 1 µA/mm up to 3 kV have been achieved owing to the use of a thick in situ SiN gate dielectric under the gate, and a local Si substrate removal technique combined with a cost effective 15-µm-thick AlN dielectric layer followed by a Cu deposition. This result establishes a manufacturable state-of-the-art high-voltage GaN-on-silicon power transistors while maintaining a low specific on-resistance of approximately 10 mΩ·cm2.

Outlook and emerging semiconducting materials for ambipolar transistors.

Science.gov (United States)

Bisri, Satria Zulkarnaen; Piliego, Claudia; Gao, Jia; Loi, Maria Antonietta

2014-02-26

Ambipolar or bipolar transistors are transistors in which both holes and electrons are mobile inside the conducting channel. This device allows switching among several states: the hole-dominated on-state, the off-state, and the electron-dominated on-state. In the past year, it has attracted great interest in exotic semiconductors, such as organic semiconductors, nanostructured materials, and carbon nanotubes. The ability to utilize both holes and electrons inside one device opens new possibilities for the development of more compact complementary metal-oxide semiconductor (CMOS) circuits, and new kinds of optoelectronic device, namely, ambipolar light-emitting transistors. This progress report highlights the recent progresses in the field of ambipolar transistors, both from the fundamental physics and application viewpoints. Attention is devoted to the challenges that should be faced for the realization of ambipolar transistors with different material systems, beginning with the understanding of the importance of interface modification, which heavily affects injections and trapping of both holes and electrons. The recent development of advanced gating applications, including ionic liquid gating, that open up more possibility to realize ambipolar transport in materials in which one type of charge carrier is highly dominant is highlighted. Between the possible applications of ambipolar field-effect transistors, we focus on ambipolar light-emitting transistors. We put this new device in the framework of its prospective for general lightings, embedded displays, current-driven laser, as well as for photonics-electronics interconnection. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Transistor Effect in Improperly Connected Transistors.

Science.gov (United States)

Luzader, Stephen; Sanchez-Velasco, Eduardo

1996-01-01

Discusses the differences between the standard representation and a realistic representation of a transistor. Presents an experiment that helps clarify the explanation of the transistor effect and shows why transistors should be connected properly. (JRH)

High performance dendrimer functionalized single-walled carbon nanotubes field effect transistor biosensor for protein detection

Science.gov (United States)

Rajesh, Sharma, Vikash; Puri, Nitin K.; Mulchandani, Ashok; Kotnala, Ravinder K.

2016-12-01

We report a single-walled carbon nanotube (SWNT) field-effect transistor (FET) functionalized with Polyamidoamine (PAMAM) dendrimer with 128 carboxyl groups as anchors for site specific biomolecular immobilization of protein antibody for C-reactive protein (CRP) detection. The FET device was characterized by scanning electron microscopy and current-gate voltage (I-Vg) characteristic studies. A concentration-dependent decrease in the source-drain current was observed in the regime of clinical significance, with a detection limit of ˜85 pM and a high sensitivity of 20% change in current (ΔI/I) per decade CRP concentration, showing SWNT being locally gated by the binding of CRP to antibody (anti-CRP) on the FET device. The low value of the dissociation constant (Kd = 0.31 ± 0.13 μg ml-1) indicated a high affinity of the device towards CRP analyte arising due to high anti-CRP loading with a better probe orientation on the 3-dimensional PAMAM structure.

Characteristics in AlN/AlGaN/GaN Multilayer-Structured High-Electron-Mobility Transistors

International Nuclear Information System (INIS)

Gui-Zhou, Hu; Ling, Yang; Li-Yuan, Yang; Si, Quan; Shou-Gao, Jiang; Ji-Gang, Ma; Xiao-Hua, Ma; Yue, Hao

2010-01-01

A new multilayer-structured AlN/AlGaN/GaN heterostructure high-electron-mobility transistor (HEMT) is demonstrated. The AlN/AlGaN/GaN HEMT exhibits the maximum drain current density of 800 mA/mm and the maximum extrinsic transconductance of 170 mS/mm. Due to the increase of the distance between the gate and the two-dimensional electron-gas channel, the threshold voltage shifts slightly to the negative. The reduced drain current collapse and higher breakdown voltage are observed on this AlN/AlGaN/GaN HEMT. The current gain cut-off frequency and the maximum frequency of oscillation are 18.5 GHz and 29.0 GHz, respectively. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Monolithic acoustic graphene transistors based on lithium niobate thin film

Science.gov (United States)

Liang, J.; Liu, B.-H.; Zhang, H.-X.; Zhang, H.; Zhang, M.-L.; Zhang, D.-H.; Pang, W.

2018-05-01

This paper introduces an on-chip acoustic graphene transistor based on lithium niobate thin film. The graphene transistor is embedded in a microelectromechanical systems (MEMS) acoustic wave device, and surface acoustic waves generated by the resonator induce a macroscopic current in the graphene due to the acousto-electric (AE) effect. The acoustic resonator and the graphene share the lithium niobate film, and a gate voltage is applied through the back side of the silicon substrate. The AE current induced by the Rayleigh and Sezawa modes was investigated, and the transistor outputs a larger current in the Rayleigh mode because of a larger coupling to velocity ratio. The output current increases linearly with the input radiofrequency power and can be effectively modulated by the gate voltage. The acoustic graphene transistor realized a five-fold enhancement in the output current at an optimum gate voltage, outperforming its counterpart with a DC input. The acoustic graphene transistor demonstrates a paradigm for more-than-Moore technology. By combining the benefits of MEMS and graphene circuits, it opens an avenue for various system-on-chip applications.

Lifetime prediction of InGaZnO thin film transistor for the application of display device and BEOL-transistors

Science.gov (United States)

Kim, Sang Min; Cho, Won Ju; Yu, Chong Gun; Park, Jong Tae

2018-04-01

In this work, the lifetime prediction models of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were suggested for the application of display device and BEOL (Back End Of line) transistors with embedded a-IGZO TFTs. Four different types of test devices according to the active layer thickness, source/drain electrode materials and thermal treatments have been used to verify the suggested model. The device lifetimes under high gate bias stress and hot carrier stress were extracted through fittings of the stretched-exponential equation for threshold voltage shifts and the current estimation method for drain current degradations. Our suggested lifetime prediction models could be used in any kinds of structures of a-IGZO TFTs for the application of display device and BEOL transistors. The a-IGZO TFTs with embedded ITO local conducting layer under source/drain is better for BEOL transistor application and a-IGZO TFTs with InGaZnO thin film as source/drain electrodes may be better for the application of display devices. From 1983 to 1985, he was a Researcher at Gold-Star Semiconductor, Inc., Korea, where he worked on the development of SRAM. He joined the Department of Electronics Engineering, University of Incheon, Incheon, Korea, in 1987, where he is a Professor. As a visiting scientist at Massachusetts Institute of Technology, Cambridge, in 1991, he conducted research in hot carrier reliability of CMOS. As a visiting scholar at University of California, Davis, in 2001, he conducted research on the device structure of Nano-scale SOI CMOS. His recent interests are device structure and reliability of Nano-scale CMOS devices, flash memory, and thin film transistors.

Unipolar n-Type Black Phosphorus Transistors with Low Work Function Contacts.

Science.gov (United States)

Wang, Ching-Hua; Incorvia, Jean Anne C; McClellan, Connor J; Yu, Andrew C; Mleczko, Michal J; Pop, Eric; Wong, H-S Philip

2018-05-09

Black phosphorus (BP) is a promising two-dimensional (2D) material for nanoscale transistors, due to its expected higher mobility than other 2D semiconductors. While most studies have reported ambipolar BP with a stronger p-type transport, it is important to fabricate both unipolar p- and n-type transistors for low-power digital circuits. Here, we report unipolar n-type BP transistors with low work function Sc and Er contacts, demonstrating a record high n-type current of 200 μA/μm in 6.5 nm thick BP. Intriguingly, the electrical transport of the as-fabricated, capped devices changes from ambipolar to n-type unipolar behavior after a month at room temperature. Transmission electron microscopy analysis of the contact cross-section reveals an intermixing layer consisting of partly oxidized metal at the interface. This intermixing layer results in a low n-type Schottky barrier between Sc and BP, leading to the unipolar behavior of the BP transistor. This unipolar transport with a suppressed p-type current is favorable for digital logic circuits to ensure a lower off-power consumption.

Top-gate hybrid complementary inverters using pentacene and amorphous InGaZnO thin-film transistors with high operational stability

Directory of Open Access Journals (Sweden)

J. B. Kim

2012-03-01

Full Text Available We report on the operational stability of low-voltage hybrid organic-inorganic complementary inverters with a top-gate bottom source-drain geometry. The inverters are comprised of p-channel pentacene and n-channel amorphous InGaZnO thin-film transistors (TFTs with bi-layer gate dielectrics formed from an amorphous layer of a fluoropolymer (CYTOP and a high-k layer of Al2O3. The p- and n- channel TFTs show saturation mobility values of 0.1 ± 0.01 and 5.0 ± 0.5 cm2/Vs, respectively. The individual transistors show high electrical stability with less than 6% drain-to-source current variations after 1 h direct current (DC bias stress. Complementary inverters yield hysteresis-free voltage transfer characteristics for forward and reverse input biases with static DC gain values larger than 45 V/V at 8 V before and after being subjected to different conditions of electrical stress. Small and reversible variations of the switching threshold voltage of the inverters during these stress tests are compatible with the observed stability of the individual TFTs.

Optimizing switching frequency of the soliton transistor by numerical simulation

Energy Technology Data Exchange (ETDEWEB)

Izadyar, S., E-mail: S_izadyar@yahoo.co [Department of Electronics, Khaje Nasir Toosi University of Technology, Shariati Ave., Tehran (Iran, Islamic Republic of); Niazzadeh, M.; Raissi, F. [Department of Electronics, Khaje Nasir Toosi University of Technology, Shariati Ave., Tehran (Iran, Islamic Republic of)

2009-10-15

In this paper, by numerical simulations we have examined different ways to increase the soliton transistor's switching frequency. Speed of the solitons in a soliton transistor depends on various parameters such as the loss of the junction, the applied bias current, and the transmission line characteristics. Three different ways have been examined; (i) decreasing the size of the transistor without losing transistor effect. (ii) Decreasing the amount of loss of the junction to increase the soliton speed. (iii) Optimizing the bias current to obtain maximum possible speed. We have obtained the shortest possible length to have at least one working soliton inside the transistor. The dimension of the soliton can be decreased by changing the inductance of the transmission line, causing a further decrease in the size of the transistor, however, a trade off between the size and the inductance is needed to obtain the optimum switching speed. Decreasing the amount of loss can be accomplished by increasing the characteristic tunneling resistance of the device, however, a trade off is again needed to make soliton and antisoliton annihilation possible. By increasing the bias current, the forces acting the solitons increases and so does their speed. Due to nonuniform application of bias current a self induced magnetic field is created which can result in creation of unwanted solitons. Optimum bias current application can result in larger bias currents and larger soliton speed. Simulations have provided us with such an arrangement of bias current paths.

Optimizing switching frequency of the soliton transistor by numerical simulation

International Nuclear Information System (INIS)

Izadyar, S.; Niazzadeh, M.; Raissi, F.

2009-01-01

In this paper, by numerical simulations we have examined different ways to increase the soliton transistor's switching frequency. Speed of the solitons in a soliton transistor depends on various parameters such as the loss of the junction, the applied bias current, and the transmission line characteristics. Three different ways have been examined; (i) decreasing the size of the transistor without losing transistor effect. (ii) Decreasing the amount of loss of the junction to increase the soliton speed. (iii) Optimizing the bias current to obtain maximum possible speed. We have obtained the shortest possible length to have at least one working soliton inside the transistor. The dimension of the soliton can be decreased by changing the inductance of the transmission line, causing a further decrease in the size of the transistor, however, a trade off between the size and the inductance is needed to obtain the optimum switching speed. Decreasing the amount of loss can be accomplished by increasing the characteristic tunneling resistance of the device, however, a trade off is again needed to make soliton and antisoliton annihilation possible. By increasing the bias current, the forces acting the solitons increases and so does their speed. Due to nonuniform application of bias current a self induced magnetic field is created which can result in creation of unwanted solitons. Optimum bias current application can result in larger bias currents and larger soliton speed. Simulations have provided us with such an arrangement of bias current paths.

Transport and performance of a gate all around InAs nanowire transistor

International Nuclear Information System (INIS)

Alam, Khairul

2009-01-01

The transport physics and performance metrics of a gate all around an InAs nanowire transistor are studied using a three-dimensional quantum simulation. The transistor action of an InAs nanowire transistor occurs by modulating the transmission coefficient of the device. This action is different from a conventional metal-oxide-semiconductor field effect transistor, where the transistor action occurs by modulating the charge in the channel. The device has 82% tunneling current in the off-state and 81% thermal current in the on-state. The two current components become equal at a gate bias at which an approximate source-channel flat-band condition is achieved. Prior to this gate bias, the tunneling current dominates and the thermal current dominates beyond it. The device has an on/off current ratio of 7.84 × 10 5 and an inverse subthreshold slope of 63 mV dec −1 . The transistor operates in the quantum capacitance limit with a normalized transconductance value of 14.43 mS µm −1 , an intrinsic switching delay of 90.1675 fs, and an intrinsic unity current gain frequency of 6.8697 THz

Carbon Nanotube Thin Film Transistors for Flat Panel Display Application.

Science.gov (United States)

Liang, Xuelei; Xia, Jiye; Dong, Guodong; Tian, Boyuan; Peng, Lianmao

2016-12-01

Carbon nanotubes (CNTs) are promising materials for both high performance transistors for high speed computing and thin film transistors for macroelectronics, which can provide more functions at low cost. Among macroelectronics applications, carbon nanotube thin film transistors (CNT-TFT) are expected to be used soon for backplanes in flat panel displays (FPDs) due to their superior performance. In this paper, we review the challenges of CNT-TFT technology for FPD applications. The device performance of state-of-the-art CNT-TFTs are compared with the requirements of TFTs for FPDs. Compatibility of the fabrication processes of CNT-TFTs and current TFT technologies are critically examined. Though CNT-TFT technology is not yet ready for backplane production line of FPDs, the challenges can be overcome by close collaboration between research institutes and FPD manufacturers in the short term.

SOI Transistor measurement techniques using body contacted transistors

International Nuclear Information System (INIS)

Worley, E.R.; Williams, R.

1989-01-01

Measurements of body contacted SOI transistors are used to isolate parameters of the back channel and island edge transistor. Properties of the edge and back channel transistor have been measured before and after X-ray irradiation (ARACOR). The unique properties of the edge transistor are shown to be a result of edge geometry as confirmed by a two dimensional transistor simulator

Giant current fluctuations in an overheated single-electron transistor

NARCIS (Netherlands)

Laakso, M.A.; Heikkilä, T.T.; Nazarov, Y.V.

2010-01-01

Interplay of cotunneling and single-electron tunneling in a thermally isolated single-electron transistor leads to peculiar overheating effects. In particular, there is an interesting crossover interval where the competition between cotunneling and single-electron tunneling changes to the dominance

Comparison of MOS capacitor and transistor postirradiation response

International Nuclear Information System (INIS)

McWhorter, P.J.; Fleetwood, D.M.; Pastorek, R.A.; Zimmerman, G.T.

1989-01-01

The postirradiation response of MOS capacitors and transistors fabricated on the same chip has been examined as a function of dose and anneal bias. A variety of analysis techniques are used to evaluate the postirradiation response of these structures, including low and high frequency capacitance-voltage techniques, subthreshold current-voltage techniques, and charge pumping. Though there are changes in the postirradiation energy spectrum of ΔD it , no clear evidence of defect transformation is observed on transistors or capacitors under any conditions examined. Postirradiation response at 80 degrees C is found to be similar in the two structures for low levels of damage (100 krad). For both structures, interface-trap densities continue to grow following irradiation under these conditions. In contrast, the postirradiation response of capacitors and transistors can differ qualitatively at higher levels of damage (1 Mrad), with interface-traps increasing postirradiation at 80 degrees C for transistors and annealing for capacitors. These results indicate that capacitor structures may not be suitable for hardness assurance studies that involve elevated temperature irradiations or postirradiation anneals

Methods of high current magnetic field generator for transcranial magnetic stimulation application

Science.gov (United States)

Bouda, N. R.; Pritchard, J.; Weber, R. J.; Mina, M.

2015-05-01

This paper describes the design procedures and underlying concepts of a novel High Current Magnetic Field Generator (HCMFG) with adjustable pulse width for transcranial magnetic stimulation applications. This is achieved by utilizing two different switching devices, the MOSFET and insulated gate bipolar transistor (IGBT). Results indicate that currents as high as ±1200 A can be generated with inputs of +/-20 V. Special attention to tradeoffs between field generators utilizing IGBT circuits (HCMFG1) and MOSFET circuits (HCMFG2) was considered. The theory of operation, design, experimental results, and electronic setup are presented and analyzed.

Significant performance enhancement in AlGaN/GaN high electron mobility transistor by high-κ organic dielectric

International Nuclear Information System (INIS)

Ze-Gao, Wang; Yuan-Fu, Chen; Cao, Chen; Ben-Lang, Tian; Fu-Tong, Chu; Xing-Zhao, Liu; Yan-Rong, Li

2010-01-01

The electrical properties of AlGaN/GaN high electron mobility transistor (HEMT) with and without high-κ organic dielectrics are investigated. The maximum drain current I D max and the maximum transconductance g m max of the organic dielectric/AlGaN/GaN structure can be enhanced by 74.5%, and 73.7% compared with those of the bare AlGaN/GaN HEMT, respectively. Both the threshold voltage V T and g m max of the dielectric/AlGaN/GaN HEMT are strongly dielectric-constant-dependent. Our results suggest that it is promising to significantly improve the performance of the AlGaN/GaN HEMT by introducing the high-κ organic dielectric. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Rf Gun with High-Current Density Field Emission Cathode

International Nuclear Information System (INIS)

Jay L. Hirshfield

2005-01-01

High current-density field emission from an array of carbon nanotubes, with field-emission-transistor control, and with secondary electron channel multiplication in a ceramic facing structure, have been combined in a cold cathode for rf guns and diode guns. Electrodynamic and space-charge flow simulations were conducted to specify the cathode configuration and range of emission current density from the field emission cold cathode. Design of this cathode has been made for installation and testing in an existing S-band 2-1/2 cell rf gun. With emission control and modulation, and with current density in the range of 0.1-1 kA/cm2, this cathode could provide performance and long-life not enjoyed by other currently-available cathodes

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics.

Science.gov (United States)

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-10-08

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT~0.9 GHz, fMAX~1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics.

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics

Science.gov (United States)

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-01-01

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT ~ 0.9 GHz, fMAX ~ 1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics. PMID:25295573

Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

KAUST Repository

Fahad, Hossain M.; Smith, Casey; Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

2011-01-01

We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

KAUST Repository

Fahad, Hossain M.

2011-10-12

We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

Direct-current substrate bias effects on amorphous silicon sputter-deposited films for thin film transistor fabrication

International Nuclear Information System (INIS)

Jun, Seung-Ik; Rack, Philip D.; McKnight, Timothy E.; Melechko, Anatoli V.; Simpson, Michael L.

2005-01-01

The effect that direct current (dc) substrate bias has on radio frequency-sputter-deposited amorphous silicon (a-Si) films has been investigated. The substrate bias produces a denser a-Si film with fewer defects compared to unbiased films. The reduced number of defects results in a higher resistivity because defect-mediated conduction paths are reduced. Thin film transistors (TFTs) that were completely sputter deposited were fabricated and characterized. The TFT with the biased a-Si film showed lower leakage (off-state) current, higher on/off current ratio, and higher transconductance (field effect mobility) than the TFT with the unbiased a-Si film

AlGaN/GaN High Electron Mobility Transistors with Multi-MgxNy/GaN Buffer

OpenAIRE

Chang, P. C.; Lee, K. H.; Wang, Z. H.; Chang, S. J.

2014-01-01

We report the fabrication of AlGaN/GaN high electron mobility transistors with multi-MgxNy/GaN buffer. Compared with conventional HEMT devices with a low-temperature GaN buffer, smaller gate and source-drain leakage current could be achieved with this new buffer design. Consequently, the electron mobility was larger for the proposed device due to the reduction of defect density and the corresponding improvement of crystalline quality as result of using the multi-MgxNy/GaN buffer.

Understanding noise suppression in heterojunction field-effect transistors

International Nuclear Information System (INIS)

Green, F.

1996-01-01

Full text: The enhanced transport properties displayed by quantum-well-confined, two-dimensional, electron systems underpin the success of heterojunction, field-effect transistors. At cryogenic temperatures, these devices exhibit impressive mobilities and, as a result, high signal gain and low noise. Conventional wisdom has it that the same favourable conditions also hold for normal room-temperature operation. In that case, however, high mobilities are precluded by abundant electron-phonon scattering. Our recent study of nonequilibrium current noise shows that quantum confinement, not high mobility, is the principal source of noise in these devices; this opens up new and exciting opportunities in low-noise transistor design. As trends in millimetre-wave technology push frequencies beyond 100 GHz, it is essential to develop a genuine understanding of noise processes in heterojunction devices

Transistorized PWM inverter-induction motor drive system

Science.gov (United States)

Peak, S. C.; Plunkett, A. B.

1982-01-01

This paper describes the development of a transistorized PWM inverter-induction motor traction drive system. A vehicle performance analysis was performed to establish the vehicle tractive effort-speed requirements. These requirements were then converted into a set of inverter and motor specifications. The inverter was a transistorized three-phase bridge using General Electric power Darlington transistors. The description of the design and development of this inverter is the principal object of this paper. The high-speed induction motor is a design which is optimized for use with an inverter power source. The primary feedback control is a torque angle control with voltage and torque outer loop controls. A current-controlled PWM technique is used to control the motor voltage. The drive has a constant torque output with PWM operation to base motor speed and a constant horsepower output with square wave operation to maximum speed. The drive system was dynamometer tested and the results are presented.

High gain, low noise, fully complementary logic inverter based on bi-layer WSe{sub 2} field effect transistors

Energy Technology Data Exchange (ETDEWEB)

Das, Saptarshi; Roelofs, Andreas [Center for Nanoscale Material, Argonne National Laboratory, Argonne, Illinois 60439 (United States); Dubey, Madan [U.S. Army Research Laboratory, Adelphi, Maryland 20783 (United States)

2014-08-25

In this article, first, we show that by contact work function engineering, electrostatic doping and proper scaling of both the oxide thickness and the flake thickness, high performance p- and n-type WSe{sub 2} field effect transistors (FETs) can be realized. We report record high drive current of 98 μA/μm for the electron conduction and 110 μA/μm for the hole conduction in Schottky barrier WSe{sub 2} FETs. Then, we combine high performance WSe{sub 2} PFET with WSe{sub 2} NFET in double gated transistor geometry to demonstrate a fully complementary logic inverter. We also show that by adjusting the threshold voltages for the NFET and the PFET, the gain and the noise margin of the inverter can be significantly enhanced. The maximum gain of our chemical doping free WSe{sub 2} inverter was found to be ∼25 and the noise margin was close to its ideal value of ∼2.5 V for a supply voltage of V{sub DD} = 5.0 V.

Ambipolar organic tri-gate transistor for low-power complementary electronics

NARCIS (Netherlands)

Torricelli, F.; Ghittorelli, M.; Smits, E.C.P.; Roelofs, C.; Janssen, R.A.J.; Gelinck, G.H.; Kovács-Vajna, Z.M.; Cantatore, E.

2016-01-01

Ambipolar transistors typically suffer from large off-current inherently due to ambipolar conduction. Using a tri-gate transistor it is shown that it is possible to electrostatically switch ambipolar polymer transistors from ambipolar to unipolar mode. In unipolar mode, symmetric characteristics

"Liquid-liquid-solid"-type superoleophobic surfaces to pattern polymeric semiconductors towards high-quality organic field-effect transistors.

Science.gov (United States)

Wu, Yuchen; Su, Bin; Jiang, Lei; Heeger, Alan J

2013-12-03

Precisely aligned organic-liquid-soluble semiconductor microwire arrays have been fabricated by "liquid-liquid-solid" type superoleophobic surfaces directed fluid drying. Aligned organic 1D micro-architectures can be built as high-quality organic field-effect transistors with high mobilities of >10 cm(2) ·V(-1) ·s(-1) and current on/off ratio of more than 10(6) . All these studies will boost the development of 1D microstructures of organic semiconductor materials for potential application in organic electronics. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Photosensitive graphene transistors.

Science.gov (United States)

Li, Jinhua; Niu, Liyong; Zheng, Zijian; Yan, Feng

2014-08-20

High performance photodetectors play important roles in the development of innovative technologies in many fields, including medicine, display and imaging, military, optical communication, environment monitoring, security check, scientific research and industrial processing control. Graphene, the most fascinating two-dimensional material, has demonstrated promising applications in various types of photodetectors from terahertz to ultraviolet, due to its ultrahigh carrier mobility and light absorption in broad wavelength range. Graphene field effect transistors are recognized as a type of excellent transducers for photodetection thanks to the inherent amplification function of the transistors, the feasibility of miniaturization and the unique properties of graphene. In this review, we will introduce the applications of graphene transistors as photodetectors in different wavelength ranges including terahertz, infrared, visible, and ultraviolet, focusing on the device design, physics and photosensitive performance. Since the device properties are closely related to the quality of graphene, the devices based on graphene prepared with different methods will be addressed separately with a view to demonstrating more clearly their advantages and shortcomings in practical applications. It is expected that highly sensitive photodetectors based on graphene transistors will find important applications in many emerging areas especially flexible, wearable, printable or transparent electronics and high frequency communications. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Kink effect and noise performance in isolated-gate InAs/AlSb high electron mobility transistors

International Nuclear Information System (INIS)

Vasallo, B G; González, T; Mateos, J; Rodilla, H; Moschetti, G; Grahn, J

2012-01-01

The kink effect can spoil the otherwise excellent low noise performance of InAs/AlSb high electron mobility transistors. It has its origin in the pile-up of holes (generated by impact ionization) taking place mainly at the drain side of the buffer, which leads to a reduction of the gate-induced channel depletion and results in a drain current enhancement. Our results indicate that the generation of holes by impact ionization and their further recombination lead to fluctuations in the charge of the hole pile-up, which provoke an important increase in the drain current noise, even when the kink effect is hardly perceptible in the output characteristics. (paper)

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

International Nuclear Information System (INIS)

Deen, David A.; Storm, David F.; Scott Katzer, D.; Bass, R.; Meyer, David J.

2016-01-01

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain current after bias stressed in subthreshold. These structures additionally achieved small signal metrics f_t/f_m_a_x of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with f_t/f_m_a_x of 48/60 GHz.

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

Energy Technology Data Exchange (ETDEWEB)

Deen, David A., E-mail: david.deen@alumni.nd.edu; Storm, David F.; Scott Katzer, D.; Bass, R.; Meyer, David J. [Naval Research Laboratory, Electronics Science and Technology Division, Washington, DC 20375 (United States)

2016-08-08

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain current after bias stressed in subthreshold. These structures additionally achieved small signal metrics f{sub t}/f{sub max} of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with f{sub t}/f{sub max} of 48/60 GHz.

Optimization of L-shaped tunneling field-effect transistor for ambipolar current suppression and Analog/RF performance enhancement

Science.gov (United States)

Li, Cong; Zhao, Xiaolong; Zhuang, Yiqi; Yan, Zhirui; Guo, Jiaming; Han, Ru

2018-03-01

L-shaped tunneling field-effect transistor (LTFET) has larger tunnel area than planar TFET, which leads to enhanced on-current ION . However, LTFET suffers from severe ambipolar behavior, which needs to be further optimized for low power and high-frequency applications. In this paper, both hetero-gate-dielectric (HGD) and lightly doped drain (LDD) structures are introduced into LTFET for suppression of ambipolarity and improvement of analog/RF performance of LTFET. Current-voltage characteristics, the variation of energy band diagrams, distribution of band-to-band tunneling (BTBT) generation and distribution of electric field are analyzed for our proposed HGD-LDD-LTFET. In addition, the effect of LDD on the ambipolar behavior of LTFET is investigated, the length and doping concentration of LDD is also optimized for better suppression of ambipolar current. Finally, analog/RF performance of HGD-LDD-LTFET are studied in terms of gate-source capacitance, gate-drain capacitance, cut-off frequency, and gain bandwidth production. TCAD simulation results show that HGD-LDD-LTFET not only drastically suppresses ambipolar current but also improves analog/RF performance compared with conventional LTFET.

Pentacene based thin film transistors with high-k dielectric Nd2O3 as a gate insulator

International Nuclear Information System (INIS)

Sarma, R.; Saikia, D.

2010-01-01

We have investigated the pentacene based Organic Thin Film Transistors (OTFTs) with high-k dielectric Nd 2 O 3 . Use of high dielectric constant (high-k) gate insulator Nd 2 O 3 reduces the threshold voltage and sub threshold swing of the OTFTs. The calculated threshold voltage -2.2V and sub-threshold swing 1V/decade, current ON-OFF ratio is 1.7 X 10 4 and mobility is 0.13cm 2 /V.s. Pentacene film is deposited on Nd 2 O 3 surface using two step deposition method. Deposited pentacene film is found poly crystalline in nature. (author)

Bottom-Up Tri-gate Transistors and Submicrosecond Photodetectors from Guided CdS Nanowalls.

Science.gov (United States)

Xu, Jinyou; Oksenberg, Eitan; Popovitz-Biro, Ronit; Rechav, Katya; Joselevich, Ernesto

2017-11-08

Tri-gate transistors offer better performance than planar transistors by exerting additional gate control over a channel from two lateral sides of semiconductor nanowalls (or "fins"). Here we report the bottom-up assembly of aligned CdS nanowalls by a simultaneous combination of horizontal catalytic vapor-liquid-solid growth and vertical facet-selective noncatalytic vapor-solid growth and their parallel integration into tri-gate transistors and photodetectors at wafer scale (cm 2 ) without postgrowth transfer or alignment steps. These tri-gate transistors act as enhancement-mode transistors with an on/off current ratio on the order of 10 8 , 4 orders of magnitude higher than the best results ever reported for planar enhancement-mode CdS transistors. The response time of the photodetector is reduced to the submicrosecond level, 1 order of magnitude shorter than the best results ever reported for photodetectors made of bottom-up semiconductor nanostructures. Guided semiconductor nanowalls open new opportunities for high-performance 3D nanodevices assembled from the bottom up.

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors

Directory of Open Access Journals (Sweden)

Nandu B Chaure, Andrew N Cammidge, Isabelle Chambrier, Michael J Cook, Markys G Cain, Craig E Murphy, Chandana Pal and Asim K Ray

2011-01-01

Full Text Available Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl copper phthalocyanine (CuPc6 were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO2 as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS resulted in values of 4×10−2 cm2 V−1 s−1 and 106 for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones.

High-Performance Flexible Thin-Film Transistors Based on Single-Crystal-like Silicon Epitaxially Grown on Metal Tape by Roll-to-Roll Continuous Deposition Process.

Science.gov (United States)

Gao, Ying; Asadirad, Mojtaba; Yao, Yao; Dutta, Pavel; Galstyan, Eduard; Shervin, Shahab; Lee, Keon-Hwa; Pouladi, Sara; Sun, Sicong; Li, Yongkuan; Rathi, Monika; Ryou, Jae-Hyun; Selvamanickam, Venkat

2016-11-02

Single-crystal-like silicon (Si) thin films on bendable and scalable substrates via direct deposition are a promising material platform for high-performance and cost-effective devices of flexible electronics. However, due to the thick and unintentionally highly doped semiconductor layer, the operation of transistors has been hampered. We report the first demonstration of high-performance flexible thin-film transistors (TFTs) using single-crystal-like Si thin films with a field-effect mobility of ∼200 cm 2 /V·s and saturation current, I/l W > 50 μA/μm, which are orders-of-magnitude higher than the device characteristics of conventional flexible TFTs. The Si thin films with a (001) plane grown on a metal tape by a "seed and epitaxy" technique show nearly single-crystalline properties characterized by X-ray diffraction, Raman spectroscopy, reflection high-energy electron diffraction, and transmission electron microscopy. The realization of flexible and high-performance Si TFTs can establish a new pathway for extended applications of flexible electronics such as amplification and digital circuits, more than currently dominant display switches.

Wafer-Scale Gigahertz Graphene Field Effect Transistors on SiC Substrates

Institute of Scientific and Technical Information of China (English)

潘洪亮; 金智; 麻芃; 郭建楠; 刘新宇; 叶甜春; 李佳; 敦少博; 冯志红

2011-01-01

Wafer-scale graphene field-effect transistors are fabricated using benzocyclobutene and atomic layer deposition Al2O3 as the top-gate dielectric.The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate.The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found.For the intrinsic characteristic of this particular channel material,the devices cannot be switched off.The cut-off frequencies of these graphene field-effect transistors,which have a gate length of l μm,are larger than 800 MHz.The largest one can reach 1.24 GHz.There are greater than 95％ active devices that can be successfully applied.We thus succeed in fabricating wafer-scale gigahertz graphene field-effect transistors,which paves the way for high-performance graphene devices and circuits.%Wafer-scale graphene Beld-effect transistors are fabricated using benzocyclobutene and atomic layer deposition AI2O3 as the top-gate dielectric. The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate. The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found. For the intrinsic characteristic of this particular channel material, the devices cannot be switched off. The cut-off frequencies of these graphene field-effect transistors, which have a gate length of l μm, are larger than 800MHz. The largest one can reach 1.24 GHz. There are greater than 95% active devices that can be successfully applied. We thus succeed in fabricating wafer-scale gigahertz graphene Geld-effect transistors, which paves the way for high-performance graphene devices and circuits.

Current gain above 10 in sub-10 nm base III-Nitride tunneling hot electron transistors with GaN/AlN emitter

Energy Technology Data Exchange (ETDEWEB)

Yang, Zhichao, E-mail: zcyang.phys@gmail.com; Zhang, Yuewei; Krishnamoorthy, Sriram; Nath, Digbijoy N. [Department of Electrical and Computer Engineering, The Ohio State University, Columbus, Ohio 43210 (United States); Khurgin, Jacob B. [Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, Maryland 21218 (United States); Rajan, Siddharth [Department of Electrical and Computer Engineering, The Ohio State University, Columbus, Ohio 43210 (United States); Department of Materials Science and Engineering, The Ohio State University, Columbus, Ohio 43210 (United States)

2016-05-09

We report on a tunneling hot electron transistor amplifier with common-emitter current gain greater than 10 at a collector current density in excess of 40 kA/cm{sup 2}. The use of a wide-bandgap GaN/AlN (111 nm/2.5 nm) emitter was found to greatly improve injection efficiency of the emitter and reduce cold electron leakage. With an ultra-thin (8 nm) base, 93% of the injected hot electrons were collected, enabling a common-emitter current gain up to 14.5. This work improves understanding of the quasi-ballistic hot electron transport and may impact the development of high speed devices based on unipolar hot electron transport.

AlGaN/GaN High Electron Mobility Transistors with Multi-MgxNy/GaN Buffer

Directory of Open Access Journals (Sweden)

P. C. Chang

2014-01-01

Full Text Available We report the fabrication of AlGaN/GaN high electron mobility transistors with multi-MgxNy/GaN buffer. Compared with conventional HEMT devices with a low-temperature GaN buffer, smaller gate and source-drain leakage current could be achieved with this new buffer design. Consequently, the electron mobility was larger for the proposed device due to the reduction of defect density and the corresponding improvement of crystalline quality as result of using the multi-MgxNy/GaN buffer.

Photolithographically Patterned TiO2 Films for Electrolyte-Gated Transistors.

Science.gov (United States)

Valitova, Irina; Kumar, Prajwal; Meng, Xiang; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2016-06-15

Metal oxides constitute a class of materials whose properties cover the entire range from insulators to semiconductors to metals. Most metal oxides are abundant and accessible at moderate cost. Metal oxides are widely investigated as channel materials in transistors, including electrolyte-gated transistors, where the charge carrier density can be modulated by orders of magnitude upon application of relatively low electrical bias (2 V). Electrolyte gating offers the opportunity to envisage new applications in flexible and printed electronics as well as to improve our current understanding of fundamental processes in electronic materials, e.g. insulator/metal transitions. In this work, we employ photolithographically patterned TiO2 films as channels for electrolyte-gated transistors. TiO2 stands out for its biocompatibility and wide use in sensing, electrochromics, photovoltaics and photocatalysis. We fabricated TiO2 electrolyte-gated transistors using an original unconventional parylene-based patterning technique. By using a combination of electrochemical and charge carrier transport measurements we demonstrated that patterning improves the performance of electrolyte-gated TiO2 transistors with respect to their unpatterned counterparts. Patterned electrolyte-gated (EG) TiO2 transistors show threshold voltages of about 0.9 V, ON/OFF ratios as high as 1 × 10(5), and electron mobility above 1 cm(2)/(V s).

Diketopyrrolopyrrole-diketopyrrolopyrrole-based conjugated copolymer for high-mobility organic field-effect transistors

KAUST Repository

Kanimozhi, Catherine K.; Yaacobi-Gross, Nir; Chou, Kang Wei; Amassian, Aram; Anthopoulos, Thomas D.; Patil, Satish P.

2012-01-01

In this communication, we report the synthesis of a novel diketopyrrolopyrrole-diketopyrrolopyrrole (DPP-DPP)-based conjugated copolymer and its application in high-mobility organic field-effect transistors. Copolymerization of DPP with DPP yields a

Methods of high current magnetic field generator for transcranial magnetic stimulation application

International Nuclear Information System (INIS)

Bouda, N. R.; Pritchard, J.; Weber, R. J.; Mina, M.

2015-01-01

This paper describes the design procedures and underlying concepts of a novel High Current Magnetic Field Generator (HCMFG) with adjustable pulse width for transcranial magnetic stimulation applications. This is achieved by utilizing two different switching devices, the MOSFET and insulated gate bipolar transistor (IGBT). Results indicate that currents as high as ±1200 A can be generated with inputs of +/−20 V. Special attention to tradeoffs between field generators utilizing IGBT circuits (HCMFG 1 ) and MOSFET circuits (HCMFG 2 ) was considered. The theory of operation, design, experimental results, and electronic setup are presented and analyzed

Methods of high current magnetic field generator for transcranial magnetic stimulation application

Energy Technology Data Exchange (ETDEWEB)

Bouda, N. R., E-mail: nybouda@iastate.edu; Pritchard, J.; Weber, R. J.; Mina, M. [Department of Electrical and Computer engineering, Iowa State University, Ames, Iowa 50011 (United States)

2015-05-07

This paper describes the design procedures and underlying concepts of a novel High Current Magnetic Field Generator (HCMFG) with adjustable pulse width for transcranial magnetic stimulation applications. This is achieved by utilizing two different switching devices, the MOSFET and insulated gate bipolar transistor (IGBT). Results indicate that currents as high as ±1200 A can be generated with inputs of +/−20 V. Special attention to tradeoffs between field generators utilizing IGBT circuits (HCMFG{sub 1}) and MOSFET circuits (HCMFG{sub 2}) was considered. The theory of operation, design, experimental results, and electronic setup are presented and analyzed.

The Influence of Morphology on High-Performance Polymer Field-Effect Transistors

DEFF Research Database (Denmark)

Tsao, Hoi Nok; Cho, Don; Andreasen, Jens Wenzel

2009-01-01

The influence of molecular packing on the performance of polymer organic field-effect transistors is illustrated in this work. Both close -stacking distance and long-range order are important for achieving high mobilities. By aligning the polymers from solution, long-range order is induced...

Total dose effects on the matching properties of deep submicron MOS transistors

International Nuclear Information System (INIS)

Wang Yuxin; Hu Rongbin; Li Ruzhang; Chen Guangbing; Fu Dongbing; Lu Wu

2014-01-01

Based on 0.18 μm MOS transistors, for the first time, the total dose effects on the matching properties of deep submicron MOS transistors are studied. The experimental results show that the total dose radiation magnifies the mismatch among identically designed MOS transistors. In our experiments, as the radiation total dose rises to 200 krad, the threshold voltage and drain current mismatch percentages of NMOS transistors increase from 0.55% and 1.4% before radiation to 17.4% and 13.5% after radiation, respectively. PMOS transistors seem to be resistant to radiation damage. For all the range of radiation total dose, the threshold voltage and drain current mismatch percentages of PMOS transistors keep under 0.5% and 2.72%, respectively. (semiconductor devices)

Fully transparent thin-film transistor devices based on SnO2 nanowires.

Science.gov (United States)

Dattoli, Eric N; Wan, Qing; Guo, Wei; Chen, Yanbin; Pan, Xiaoqing; Lu, Wei

2007-08-01

We report on studies of field-effect transistor (FET) and transparent thin-film transistor (TFT) devices based on lightly Ta-doped SnO2 nano-wires. The nanowire-based devices exhibit uniform characteristics with average field-effect mobilities exceeding 100 cm2/V x s. Prototype nano-wire-based TFT (NW-TFT) devices on glass substrates showed excellent optical transparency and transistor performance in terms of transconductance, bias voltage range, and on/off ratio. High on-currents and field-effect mobilities were obtained from the NW-TFT devices even at low nanowire coverage. The SnO2 nanowire-based TFT approach offers a number of desirable properties such as low growth cost, high electron mobility, and optical transparency and low operation voltage, and may lead to large-scale applications of transparent electronics on diverse substrates.

Investigation of abrupt degradation of drain current caused by under-gate crack in AlGaN/GaN high electron mobility transistors during high temperature operation stress

Energy Technology Data Exchange (ETDEWEB)

Zeng, Chang; Liao, XueYang; Li, RuGuan; Wang, YuanSheng; Chen, Yiqiang, E-mail: yiqiang-chen@hotmail.com; Su, Wei; Liu, Yuan; Wang, Li Wei; Lai, Ping; Huang, Yun; En, YunFei [Science and Technology on Reliability Physics and Application of Electronic Component Laboratory, The 5th Electronics Research Institute of the Ministry of Industry and Information Technology, 510610 Guangzhou (China)

2015-09-28

In this paper, we investigate the degradation mode and mechanism of AlGaN/GaN based high electron mobility transistors (HEMTs) during high temperature operation (HTO) stress. It demonstrates that there was abrupt degradation mode of drain current during HTO stress. The abrupt degradation is ascribed to the formation of crack under the gate which was the result of the brittle fracture of epilayer based on failure analysis. The origin of the mechanical damage under the gate is further investigated and discussed based on top-down scanning electron microscope, cross section transmission electron microscope and energy dispersive x-ray spectroscopy analysis, and stress simulation. Based on the coupled analysis of the failure physical feature and stress simulation considering the coefficient of thermal expansion (CTE) mismatch in different materials in gate metals/semiconductor system, the mechanical damage under the gate is related to mechanical stress induced by CTE mismatch in Au/Ti/Mo/GaN system and stress concentration caused by the localized structural damage at the drain side of the gate edge. These results indicate that mechanical stress induced by CTE mismatch of materials inside the device plays great important role on the reliability of AlGaN/GaN HEMTs during HTO stress.

A Robust Highly Aligned DNA Nanowire Array-Enabled Lithography for Graphene Nanoribbon Transistors.

Science.gov (United States)

Kang, Seok Hee; Hwang, Wan Sik; Lin, Zhiqun; Kwon, Se Hun; Hong, Suck Won

2015-12-09

Because of its excellent charge carrier mobility at the Dirac point, graphene possesses exceptional properties for high-performance devices. Of particular interest is the potential use of graphene nanoribbons or graphene nanomesh for field-effect transistors. Herein, highly aligned DNA nanowire arrays were crafted by flow-assisted self-assembly of a drop of DNA aqueous solution on a flat polymer substrate. Subsequently, they were exploited as "ink" and transfer-printed on chemical vapor deposited (CVD)-grown graphene substrate. The oriented DNA nanowires served as the lithographic resist for selective removal of graphene, forming highly aligned graphene nanoribbons. Intriguingly, these graphene nanoribbons can be readily produced over a large area (i.e., millimeter scale) with a high degree of feature-size controllability and a low level of defects, rendering the fabrication of flexible two terminal devices and field-effect transistors.

High-performance carbon-nanotube-based complementary field-effect-transistors and integrated circuits with yttrium oxide

Energy Technology Data Exchange (ETDEWEB)

Liang, Shibo; Zhang, Zhiyong, E-mail: zyzhang@pku.edu.cn; Si, Jia; Zhong, Donglai; Peng, Lian-Mao, E-mail: lmpeng@pku.edu.cn [Key Laboratory for the Physics and Chemistry of Nanodevices, Department of Electronics, Peking University, Beijing 100871 (China)

2014-08-11

High-performance p-type carbon nanotube (CNT) transistors utilizing yttrium oxide as gate dielectric are presented by optimizing oxidization and annealing processes. Complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) are then fabricated on CNTs, and the p- and n-type devices exhibit symmetrical high performances, especially with low threshold voltage near to zero. The corresponding CMOS CNT inverter is demonstrated to operate at an ultra-low supply voltage down to 0.2 V, while displaying sufficient voltage gain, high noise margin, and low power consumption. Yttrium oxide is proven to be a competitive gate dielectric for constructing high-performance CNT CMOS FETs and integrated circuits.

High total dose proton irradiation effects on silicon NPN rf power transistors

International Nuclear Information System (INIS)

Bharathi, M. N.; Praveen, K. C.; Prakash, A. P. Gnana; Pushpa, N.

2014-01-01

The effects of 3 MeV proton irradiation on the I-V characteristics of NPN rf power transistors were studied in the dose range of 100 Krad to 100 Mrad. The different electrical characteristics like Gummel, current gain and output characteristics were systematically studied before and after irradiation. The recovery in the I-V characteristics of irradiated NPN BJTs were studied by isochronal and isothermal annealing methods

High total dose proton irradiation effects on silicon NPN rf power transistors

Energy Technology Data Exchange (ETDEWEB)

Bharathi, M. N.; Praveen, K. C.; Prakash, A. P. Gnana, E-mail: gnanaprakash@physics.uni-mysore.ac.in [Department of Studies in Physics, University of Mysore, Manasagangotri, Mysore-570006, Karnataka (India); Pushpa, N. [Department of PG Studies in Physics, JSS College, Ooty Road, Mysore-570025, Karnataka (India)

2014-04-24

The effects of 3 MeV proton irradiation on the I-V characteristics of NPN rf power transistors were studied in the dose range of 100 Krad to 100 Mrad. The different electrical characteristics like Gummel, current gain and output characteristics were systematically studied before and after irradiation. The recovery in the I-V characteristics of irradiated NPN BJTs were studied by isochronal and isothermal annealing methods.

Mobility overestimation due to gated contacts in organic field-effect transistors

Science.gov (United States)

Bittle, Emily G.; Basham, James I.; Jackson, Thomas N.; Jurchescu, Oana D.; Gundlach, David J.

2016-01-01

Parameters used to describe the electrical properties of organic field-effect transistors, such as mobility and threshold voltage, are commonly extracted from measured current–voltage characteristics and interpreted by using the classical metal oxide–semiconductor field-effect transistor model. However, in recent reports of devices with ultra-high mobility (>40 cm2 V−1 s−1), the device characteristics deviate from this idealized model and show an abrupt turn-on in the drain current when measured as a function of gate voltage. In order to investigate this phenomenon, here we report on single crystal rubrene transistors intentionally fabricated to exhibit an abrupt turn-on. We disentangle the channel properties from the contact resistance by using impedance spectroscopy and show that the current in such devices is governed by a gate bias dependence of the contact resistance. As a result, extracted mobility values from d.c. current–voltage characterization are overestimated by one order of magnitude or more. PMID:26961271

Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs

Science.gov (United States)

Brady, Gerald J.; Way, Austin J.; Safron, Nathaniel S.; Evensen, Harold T.; Gopalan, Padma; Arnold, Michael S.

2016-01-01

Carbon nanotubes (CNTs) are tantalizing candidates for semiconductor electronics because of their exceptional charge transport properties and one-dimensional electrostatics. Ballistic transport approaching the quantum conductance limit of 2G0 = 4e2/h has been achieved in field-effect transistors (FETs) containing one CNT. However, constraints in CNT sorting, processing, alignment, and contacts give rise to nonidealities when CNTs are implemented in densely packed parallel arrays such as those needed for technology, resulting in a conductance per CNT far from 2G0. The consequence has been that, whereas CNTs are ultimately expected to yield FETs that are more conductive than conventional semiconductors, CNTs, instead, have underperformed channel materials, such as Si, by sixfold or more. We report quasi-ballistic CNT array FETs at a density of 47 CNTs μm−1, fabricated through a combination of CNT purification, solution-based assembly, and CNT treatment. The conductance is as high as 0.46 G0 per CNT. In parallel, the conductance of the arrays reaches 1.7 mS μm−1, which is seven times higher than the previous state-of-the-art CNT array FETs made by other methods. The saturated on-state current density is as high as 900 μA μm−1 and is similar to or exceeds that of Si FETs when compared at and equivalent gate oxide thickness and at the same off-state current density. The on-state current density exceeds that of GaAs FETs as well. This breakthrough in CNT array performance is a critical advance toward the exploitation of CNTs in logic, high-speed communications, and other semiconductor electronics technologies. PMID:27617293

High Magnetic Field in THz Plasma Wave Detection by High Electron Mobility Transistors

Science.gov (United States)

Sakowicz, M.; Łusakowski, J.; Karpierz, K.; Grynberg, M.; Valusis, G.

The role of gated and ungated two dimensional (2D) electron plasma in THz detection by high electron mobility transistors (HEMTs) was investigated. THz response of GaAs/AlGaAs and GaN/AlGaN HEMTs was measured at 4.4K in quantizing magnetic fields with a simultaneous modulation of the gate voltage UGS. This allowed us to measure both the detection signal, S, and its derivative dS/dUGS. Shubnikov - de-Haas oscillations (SdHO) of both S and dS/dUGS were observed. A comparison of SdHO observed in detection and magnetoresistance measurements allows us to associate unambiguously SdHO in S and dS/dUGS with the ungated and gated parts of the transistor channel, respectively. This allows us to conclude that the entire channel takes part in the detection process. Additionally, in the case of GaAlAs/GaAs HEMTs, a structure related to the cyclotron resonance transition was observed.

Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

International Nuclear Information System (INIS)

Jiang Zhi; Zhuang Yi-Qi; Li Cong; Wang Ping; Liu Yu-Qi

2016-01-01

Trap-assisted tunneling (TAT) has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor (TFET). In this paper, we assess subthreshold performance of double gate TFET (DG-TFET) through a band-to-band tunneling (BTBT) model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile (D it ) and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current. (paper)

Effect of traps and defects on high temperature performance of Ge channel junctionless nanowire transistors

Directory of Open Access Journals (Sweden)

Chuanchuan Sun

2017-07-01

Full Text Available We investigate the effect of traps and defects on high temperature performance of p-type germanium-on-insulator (GOI based junctionless nanowire transistors (JNTs at temperatures ranging from 300 to 450 K. Temperature dependence of the main electrical parameters, such as drive current (Ion, leakage current (Ioff, threshold voltage (Vt, transconductance (Gm and subthreshold slope (SS are extracted and compared with the reported results of conventional inversion mode (IM MOSFETs and Si based JNTs. The results show that the high interface trap density (Dit and defects can degrade high temperature reliability of GOI based JNTs significantly, in terms of Ioff, Vt variation, Gm-max and SS values. The Ioff is much more dependent on temperature than Ion and mainly affected by trap-assisted-tunneling (TAT current. The Vt variation with temperature is larger than that for IM MOSFETs and SOI based JNTs, which can be mostly attributed to the high Dit. The high Dit can also induce high SS values. The maximum Gm has a weak dependence on temperature and is significantly influenced by neutral defects scattering. Limiting the Dit and neutral defect densities is critical for the reliability of GOI based JNTs working at high temperatures.

Concept of rewritable organic ferroelectric random access memory in two lateral transistors-in-one cell architecture

International Nuclear Information System (INIS)

Kim, Min-Hoi; Lee, Gyu Jeong; Keum, Chang-Min; Lee, Sin-Doo

2014-01-01

We propose a concept of rewritable ferroelectric random access memory (RAM) with two lateral organic transistors-in-one cell architecture. Lateral integration of a paraelectric organic field-effect transistor (OFET), being a selection transistor, and a ferroelectric OFET as a memory transistor is realized using a paraelectric depolarizing layer (PDL) which is patterned on a ferroelectric insulator by transfer-printing. For the selection transistor, the key roles of the PDL are to reduce the dipolar strength and the surface roughness of the gate insulator, leading to the low memory on–off ratio and the high switching on–off current ratio. A new driving scheme preventing the crosstalk between adjacent memory cells is also demonstrated for the rewritable operation of the ferroelectric RAM. (paper)

High performance printed oxide field-effect transistors processed using photonic curing

Science.gov (United States)

Garlapati, Suresh Kumar; Cadilha Marques, Gabriel; Gebauer, Julia Susanne; Dehm, Simone; Bruns, Michael; Winterer, Markus; Baradaran Tahoori, Mehdi; Aghassi-Hagmann, Jasmin; Hahn, Horst; Dasgupta, Subho

2018-06-01

Oxide semiconductors are highly promising candidates for the most awaited, next-generation electronics, namely, printed electronics. As a fabrication route for the solution-processed/printed oxide semiconductors, photonic curing is becoming increasingly popular, as compared to the conventional thermal curing method; the former offers numerous advantages over the latter, such as low process temperatures and short exposure time and thereby, high throughput compatibility. Here, using dissimilar photonic curing concepts (UV–visible light and UV-laser), we demonstrate facile fabrication of high performance In2O3 field-effect transistors (FETs). Beside the processing related issues (temperature, time etc.), the other known limitation of oxide electronics is the lack of high performance p-type semiconductors, which can be bypassed using unipolar logics from high mobility n-type semiconductors alone. Interestingly, here we have found that our chosen distinct photonic curing methods can offer a large variation in threshold voltage, when they are fabricated from the same precursor ink. Consequently, both depletion and enhancement-mode devices have been achieved which can be used as the pull-up and pull-down transistors in unipolar inverters. The present device fabrication recipe demonstrates fast processing of low operation voltage, high performance FETs with large threshold voltage tunability.

GaN transistors for efficient power conversion

CERN Document Server

Lidow, Alex; de Rooij, Michael; Reusch, David

2014-01-01

The first edition of GaN Transistors for Efficient Power Conversion was self-published by EPC in 2012, and is currently the only other book to discuss GaN transistor technology and specific applications for the technology. More than 1,200 copies of the first edition have been sold through Amazon or distributed to selected university professors, students and potential customers, and a simplified Chinese translation is also available. The second edition has expanded emphasis on applications for GaN transistors and design considerations. This textbook provides technical and application-focused i

Deformable Organic Nanowire Field-Effect Transistors.

Science.gov (United States)

Lee, Yeongjun; Oh, Jin Young; Kim, Taeho Roy; Gu, Xiaodan; Kim, Yeongin; Wang, Ging-Ji Nathan; Wu, Hung-Chin; Pfattner, Raphael; To, John W F; Katsumata, Toru; Son, Donghee; Kang, Jiheong; Matthews, James R; Niu, Weijun; He, Mingqian; Sinclair, Robert; Cui, Yi; Tok, Jeffery B-H; Lee, Tae-Woo; Bao, Zhenan

2018-02-01

Deformable electronic devices that are impervious to mechanical influence when mounted on surfaces of dynamically changing soft matters have great potential for next-generation implantable bioelectronic devices. Here, deformable field-effect transistors (FETs) composed of single organic nanowires (NWs) as the semiconductor are presented. The NWs are composed of fused thiophene diketopyrrolopyrrole based polymer semiconductor and high-molecular-weight polyethylene oxide as both the molecular binder and deformability enhancer. The obtained transistors show high field-effect mobility >8 cm 2 V -1 s -1 with poly(vinylidenefluoride-co-trifluoroethylene) polymer dielectric and can easily be deformed by applied strains (both 100% tensile and compressive strains). The electrical reliability and mechanical durability of the NWs can be significantly enhanced by forming serpentine-like structures of the NWs. Remarkably, the fully deformable NW FETs withstand 3D volume changes (>1700% and reverting back to original state) of a rubber balloon with constant current output, on the surface of which it is attached. The deformable transistors can robustly operate without noticeable degradation on a mechanically dynamic soft matter surface, e.g., a pulsating balloon (pulse rate: 40 min -1 (0.67 Hz) and 40% volume expansion) that mimics a beating heart, which underscores its potential for future biomedical applications. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

The Integration and Applications of Organic Thin Film Transistors and Ferroelectric Polymers

Science.gov (United States)

Hsu, Yu-Jen

Organic thin film transistors and ferroelectric polymer (polyvinylidene difluoride) sheet material are integrated to form various sensors for stress/strain, acoustic wave, and Infrared (heat) sensing applications. Different from silicon-based transistors, organic thin film transistors can be fabricated and processed in room-temperature and integrated with a variety of substrates. On the other hand, polyvinylidene difluoride (PVDF) exhibits ferroelectric properties that are highly useful for sensor applications. The wide frequency bandwidth (0.001 Hz to 10 GHz), vast dynamic range (100n to 10M psi), and high elastic compliance (up to 3 percent) make PVDF a more suitable candidate over ceramic piezoelectric materials for thin and flexible sensor applications. However, the low Curie temperature may have impeded its integration with silicon technology. Organic thin film transistors, however, do not have the limitation of processing temperature, hence can serve as transimpedance amplifiers to convert the charge signal generated by PVDF into current signal that are more measurable and less affected by any downstream parasitics. Piezoelectric sensors are useful for a range of applications, but passive arrays suffer from crosstalk and signal attenuation which have complicated the development of array-based PVDF sensors. We have used organic field effect transistors, which are compatible with the low Curie temperature of a flexible piezoelectric polymer,PVDF, to monolithically fabricate transimpedance amplifiers directly on the sensor surface and convert the piezoelectric charge signal into a current signal which can be detected even in the presence of parasitic capacitances. The device couples the voltage generated by the PVDF film under strain into the gate of the organic thin film transistors (OFET) using an arrangement that allows the full piezoelectric voltage to couple to the channel, while also increasing the charge retention time. A bipolar detector is created by

A miniature microcontroller curve tracing circuit for space flight testing transistors.

Science.gov (United States)

Prokop, N; Greer, L; Krasowski, M; Flatico, J; Spina, D

2015-02-01

This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results.

Field-effect transistor memories based on ferroelectric polymers

Science.gov (United States)

Zhang, Yujia; Wang, Haiyang; Zhang, Lei; Chen, Xiaomeng; Guo, Yu; Sun, Huabin; Li, Yun

2017-11-01

Field-effect transistors based on ferroelectrics have attracted intensive interests, because of their non-volatile data retention, rewritability, and non-destructive read-out. In particular, polymeric materials that possess ferroelectric properties are promising for the fabrications of memory devices with high performance, low cost, and large-area manufacturing, by virtue of their good solubility, low-temperature processability, and good chemical stability. In this review, we discuss the material characteristics of ferroelectric polymers, providing an update on the current development of ferroelectric field-effect transistors (Fe-FETs) in non-volatile memory applications. Program supported partially by the NSFC (Nos. 61574074, 61774080), NSFJS (No. BK20170075), and the Open Partnership Joint Projects of NSFC-JSPS Bilateral Joint Research Projects (No. 61511140098).

Novel field-effect schottky barrier transistors based on graphene-MoS 2 heterojunctions

KAUST Repository

Tian, He

2014-08-11

Recently, two-dimensional materials such as molybdenum disulphide (MoS 2) have been demonstrated to realize field effect transistors (FET) with a large current on-off ratio. However, the carrier mobility in backgate MoS2 FET is rather low (typically 0.5-20 cm2/V.s). Here, we report a novel field-effect Schottky barrier transistors (FESBT) based on graphene-MoS2 heterojunction (GMH), where the characteristics of high mobility from graphene and high on-off ratio from MoS2 are properly balanced in the novel transistors. Large modulation on the device current (on/off ratio of 105) is achieved by adjusting the backgate (through 300 nm SiO2) voltage to modulate the graphene-MoS2 Schottky barrier. Moreover, the field effective mobility of the FESBT is up to 58.7 cm2/V.s. Our theoretical analysis shows that if the thickness of oxide is further reduced, a subthreshold swing (SS) of 40 mV/decade can be maintained within three orders of drain current at room temperature. This provides an opportunity to overcome the limitation of 60 mV/decade for conventional CMOS devices. The FESBT implemented with a high on-off ratio, a relatively high mobility and a low subthreshold promises low-voltage and low-power applications for future electronics.

Novel Field-Effect Schottky Barrier Transistors Based on Graphene-MoS2 Heterojunctions

Science.gov (United States)

Tian, He; Tan, Zhen; Wu, Can; Wang, Xiaomu; Mohammad, Mohammad Ali; Xie, Dan; Yang, Yi; Wang, Jing; Li, Lain-Jong; Xu, Jun; Ren, Tian-Ling

2014-01-01

Recently, two-dimensional materials such as molybdenum disulphide (MoS2) have been demonstrated to realize field effect transistors (FET) with a large current on-off ratio. However, the carrier mobility in backgate MoS2 FET is rather low (typically 0.5–20 cm2/V·s). Here, we report a novel field-effect Schottky barrier transistors (FESBT) based on graphene-MoS2 heterojunction (GMH), where the characteristics of high mobility from graphene and high on-off ratio from MoS2 are properly balanced in the novel transistors. Large modulation on the device current (on/off ratio of 105) is achieved by adjusting the backgate (through 300 nm SiO2) voltage to modulate the graphene-MoS2 Schottky barrier. Moreover, the field effective mobility of the FESBT is up to 58.7 cm2/V·s. Our theoretical analysis shows that if the thickness of oxide is further reduced, a subthreshold swing (SS) of 40 mV/decade can be maintained within three orders of drain current at room temperature. This provides an opportunity to overcome the limitation of 60 mV/decade for conventional CMOS devices. The FESBT implemented with a high on-off ratio, a relatively high mobility and a low subthreshold promises low-voltage and low-power applications for future electronics. PMID:25109609

Individual SnO2 nanowire transistors fabricated by the gold microwire mask method

International Nuclear Information System (INIS)

Sun Jia; Tang Qingxin; Lu Aixia; Jiang Xuejiao; Wan Qing

2009-01-01

A gold microwire mask method is developed for the fabrication of transistors based on single lightly Sb-doped SnO 2 nanowires. Damage of the nanowire's surface can be avoided without any thermal annealing and surface modification, which is very convenient for the fundamental electrical and photoelectric characterization of one-dimensional inorganic nanomaterials. Transport measurements of the individual SnO 2 nanowire devices demonstrate the high-performance n-type field effect transistor characteristics without significant hysteresis in the transfer curves. The current on/off ratio and the subthreshold swing of the nanowire transistors are found to be 10 6 and 240 mV/decade, respectively.

DC modeling and characterization of AlGaAs/GaAs heterojunction bipolar transistors for high-temperature applications

International Nuclear Information System (INIS)

Dikmen, C.T.; Dogan, N.S.; Osman, M.A.

1994-01-01

There is currently a demand for active electronic devices operating reliably over wide range of temperatures. Potential applications for the high-temperature devices and integrated circuits are in the areas of jet engine and control instrumentation for nuclear power plants. Here, the large signal dc characteristics of AlGaAs/GaAs heterojunction bipolar transistors (HBT) at high temperatures (27--300 C) are reported. A high-temperature SPICE model is developed which includes the recombination-generation current components and avalanche multiplication which become extremely important at high temperatures. The effect of avalanche breakdown is also included to model the current due to thermal generation of electron/hole pairs causing breakdown at high temperatures. A parameter extraction program is developed used to extract the model parameters of HBT's at different temperatures. Fitting functions for the model parameters as a function of temperature are developed. These parameters are then used in the SPICE Ebers-Moll model for the dc characterization of the HBT at any temperature between (27--300 C)

Nanoscale conductive pattern of the homoepitaxial AlGaN/GaN transistor.

Science.gov (United States)

Pérez-Tomás, A; Catalàn, G; Fontserè, A; Iglesias, V; Chen, H; Gammon, P M; Jennings, M R; Thomas, M; Fisher, C A; Sharma, Y K; Placidi, M; Chmielowska, M; Chenot, S; Porti, M; Nafría, M; Cordier, Y

2015-03-20

The gallium nitride (GaN)-based buffer/barrier mode of growth and morphology, the transistor electrical response (25-310 °C) and the nanoscale pattern of a homoepitaxial AlGaN/GaN high electron mobility transistor (HEMT) have been investigated at the micro and nanoscale. The low channel sheet resistance and the enhanced heat dissipation allow a highly conductive HEMT transistor (Ids > 1 A mm(-1)) to be defined (0.5 A mm(-1) at 300 °C). The vertical breakdown voltage has been determined to be ∼850 V with the vertical drain-bulk (or gate-bulk) current following the hopping mechanism, with an activation energy of 350 meV. The conductive atomic force microscopy nanoscale current pattern does not unequivocally follow the molecular beam epitaxy AlGaN/GaN morphology but it suggests that the FS-GaN substrate presents a series of preferential conductive spots (conductive patches). Both the estimated patches density and the apparent random distribution appear to correlate with the edge-pit dislocations observed via cathodoluminescence. The sub-surface edge-pit dislocations originating in the FS-GaN substrate result in barrier height inhomogeneity within the HEMT Schottky gate producing a subthreshold current.

Multiple negative differential resistance devices with ultra-high peak-to-valley current ratio for practical multi-valued logic and memory applications

Science.gov (United States)

Shin, Sunhae; Rok Kim, Kyung

2015-06-01

In this paper, we propose a novel multiple negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) over 106 by combining tunnel diode with a conventional MOSFET, which suppresses the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) in tunnel junction provides the first peak, and the second peak and valley are generated from the suppression of diffusion current in tunnel diode by the off-state MOSFET. The multiple NDR curves can be controlled by doping concentration of tunnel junction and the threshold voltage of MOSFET. By using complementary multiple NDR devices, five-state memory is demonstrated only with six transistors.

Tetracene-based organic light-emitting transistors: optoelectronic properties and electron injection mechanism

NARCIS (Netherlands)

Santato, C.; Capelli, R.; Loi, M.A.; Murgia, M.; Cicoira, F.; Roy, Arunesh; Stallinga, P; Zamboni, R.; Rost, C.; Karg, S.F.; Muccini, M.

2004-01-01

Optoelectronic properties of light-emitting field-effect transistors (LETs) fabricated on bottom-contact transistor structures using a tetracene film as charge-transport and light-emitting material are investigated. Electroluminescence generation and transistor current are correlated, and the bias

Electrolyte-Sensing Transistor Decals Enabled by Ultrathin Microbial Nanocellulose

Science.gov (United States)

Yuen, Jonathan D.; Walper, Scott A.; Melde, Brian J.; Daniele, Michael A.; Stenger, David A.

2017-01-01

We report an ultra-thin electronic decal that can simultaneously collect, transmit and interrogate a bio-fluid. The described technology effectively integrates a thin-film organic electrochemical transistor (sensing component) with an ultrathin microbial nanocellulose wicking membrane (sample handling component). As far as we are aware, OECTs have not been integrated in thin, permeable membrane substrates for epidermal electronics. The design of the biocompatible decal allows for the physical isolation of the electronics from the human body while enabling efficient bio-fluid delivery to the transistor via vertical wicking. High currents and ON-OFF ratios were achieved, with sensitivity as low as 1 mg·L-1.

Enhancement of tunneling current in phosphorene tunnel field effect transistors by surface defects.

Science.gov (United States)

Lu, Juan; Fan, Zhi-Qiang; Gong, Jian; Chen, Jie-Zhi; ManduLa, Huhe; Zhang, Yan-Yang; Yang, Shen-Yuan; Jiang, Xiang-Wei

2018-02-21

The effects of the staggered double vacancies, hydrogen (H), 3d transition metals, for example cobalt, and semiconductor covalent atoms, for example, germanium, nitrogen, phosphorus (P) and silicon adsorption on the transport properties of monolayer phosphorene were studied using density functional theory and non-equilibrium Green's function formalism. It was observed that the performance of the phosphorene tunnel field effect transistors (TFETs) with an 8.8 nm scaling channel length could be improved most effectively, if the adatoms or vacancies were introduced at the source channel interface. For H and P doped devices, the upper limit of on-state currents of phosphorene TFETs were able to be quickly increased to 2465 μA μm -1 and 1652 μA μm -1 , respectively, which not only outperformed the pristine sample, but also met the requirements for high performance logic applications for the next decade in the International Technology Roadmap for Semiconductors (ITRS). It was proved that the defect-induced band gap states make the effective tunneling path between the conduction band (CB) and valence band (VB) much shorter, so that the carriers can be injected easily from the left electrode, then transfer to the channel. In this regard, the tunneling properties of phosphorene TFETs can be manipulated using surface defects. In addition, the effects of spin polarization on the transport properties of doped phosphorene TFETs were also rigorously considered, H and P doped TFETs could achieve a high ON current of 1795 μA μm -1 and 1368 μA μm -1 , respectively, which is closer to realistic nanodevices.

On the choice of a head element for low-noise bipolar transistor amplifier

International Nuclear Information System (INIS)

Krasnokutskij, R.N.; Kurchaninov, L.L.; Fedyakin, N.N.; Shuvalov, R.S.

1988-01-01

The measurement results of equivalent noise charge (ENC) for KT382 transistor depending on detector capacity, formation duration and collector current are given. It is shown that the measurement results for this transistor in good agreement with calculations according to the noise model, time-consuming ENC measurements can be replaced by preliminary transistor rejection according to the distributed base resistance, current gain and simple calculations. In applications in the field of nuclear electronics the KT382 transistor enables to attain the same noise parameters as NE578, NE021 transistors (Japan) and it can be recommended for using as a head element of amplifiers

Graphene-based flexible and stretchable thin film transistors.

Science.gov (United States)

Yan, Chao; Cho, Jeong Ho; Ahn, Jong-Hyun

2012-08-21

Graphene has been attracting wide attention owing to its superb electronic, thermal and mechanical properties. These properties allow great applications in the next generation of optoelectronics, where flexibility and stretchability are essential. In this context, the recent development of graphene growth/transfer and its applications in field-effect transistors are involved. In particular, we provide a detailed review on the state-of-the-art of graphene-based flexible and stretchable thin film transistors. We address the principles of fabricating high-speed graphene analog transistors and the key issues of producing an array of graphene-based transistors on flexible and stretchable substrates. It provides a platform for future work to focus on understanding and realizing high-performance graphene-based transistors.

Flexible Textile-Based Organic Transistors Using Graphene/Ag Nanoparticle Electrode

Science.gov (United States)

Kim, Youn; Kwon, Yeon Ju; Lee, Kang Eun; Oh, Youngseok; Um, Moon-Kwang; Seong, Dong Gi; Lee, Jea Uk

2016-01-01

Highly flexible and electrically-conductive multifunctional textiles are desirable for use in wearable electronic applications. In this study, we fabricated multifunctional textile composites by vacuum filtration and wet-transfer of graphene oxide films on a flexible polyethylene terephthalate (PET) textile in association with embedding Ag nanoparticles (AgNPs) to improve the electrical conductivity. A flexible organic transistor can be developed by direct transfer of a dielectric/semiconducting double layer on the graphene/AgNP textile composite, where the textile composite was used as both flexible substrate and conductive gate electrode. The thermal treatment of a textile-based transistor enhanced the electrical performance (mobility = 7.2 cm2·V−1·s−1, on/off current ratio = 4 × 105, and threshold voltage = −1.1 V) due to the improvement of interfacial properties between the conductive textile electrode and the ion-gel dielectric layer. Furthermore, the textile transistors exhibited highly stable device performance under extended bending conditions (with a bending radius down to 3 mm and repeated tests over 1000 cycles). We believe that our simple methods for the fabrication of graphene/AgNP textile composite for use in textile-type transistors can potentially be applied to the development of flexible large-area electronic clothes. PMID:28335276

Bimodal gate-dielectric deposition for improved performance of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

International Nuclear Information System (INIS)

Pang Liang; Kim, Kyekyoon

2012-01-01

A bimodal deposition scheme combining radiofrequency magnetron sputtering and plasma enhanced chemical vapour deposition (PECVD) is proposed as a means for improving the performance of GaN-based metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs). High-density sputtered-SiO 2 is utilized to reduce the gate leakage current and enhance the breakdown voltage while low-density PECVD-SiO 2 is employed to buffer the sputtering damage and further increase the drain current by engineering the stress-induced-polarization. Thus-fabricated MOSHEMT exhibited a low leakage current of 4.21 × 10 -9 A mm -1 and high breakdown voltage of 634 V for a gate-drain distance of 6 µm, demonstrating the promise of bimodal-SiO 2 deposition scheme for the development of GaN-based MOSHEMTs for high-power application. (paper)

Transistor Small Signal Analysis under Radiation Effects

International Nuclear Information System (INIS)

Sharshar, K.A.A.

2004-01-01

A Small signal transistor parameters dedicate the operation of bipolar transistor before and after exposed to gamma radiation (1 Mrad up to 5 Mrads) and electron beam(1 MeV, 25 mA) with the same doses as a radiation sources, the electrical parameters of the device are changed. The circuit Model has been discussed.Parameters, such as internal emitter resistance (re), internal base resistance, internal collector resistance (re), emitter base photocurrent (Ippe) and base collector photocurrent (Ippe). These parameters affect on the operation of the device in its applications, which work as an effective element, such as current gain (hFE≡β)degradation it's and effective parameter in the device operation. Also the leakage currents (IcBO) and (IEBO) are most important parameters, Which increased with radiation doses. Theoretical representation of the change in the equivalent circuit for NPN and PNP bipolar transistor were discussed, the input and output parameters of the two types were discussed due to the change in small signal input resistance of the two types. The emitter resistance(re) were changed by the effect of gamma and electron beam irradiation, which makes a change in the role of matching impedances between transistor stages. Also the transistor stability factors S(Ico), S(VBE) and S(β are detected to indicate the transistor operations after exposed to radiation fields. In low doses the gain stability is modified due to recombination of induced charge generated during device fabrication. Also the load resistance values are connected to compensate the effect

A photocurrent compensation method of bipolar transistors under high dose rate radiation and its experimental research

International Nuclear Information System (INIS)

Yin Xuesong; Liu Zhongli; Li Chunji; Yu Fang

2005-01-01

Experiment using discrete bipolar transistors has been performed to verify the effect of the photocurrent compensation method. The theory of the dose rate effects of bipolar transistors and the photocurrent compensation method are introduced. The comparison between the response of hardened and unhardened circuits under high dose rate radiation is discussed. The experimental results show instructiveness to the hardness of bipolar integrated circuits under transient radiation. (authors)

A study of s new power semiconductor insulated gate bipolar transistor (IGBT) characteristics and its application to automotive ignition

International Nuclear Information System (INIS)

Rabah, K.V.O.

1995-05-01

Assessment has been made of the problem of the on-resistance and temperature effects in the three power transistor combinations, such as Darlington-types or IGBT. The IGBT is a device in which the drain of the MOSFET feeds the bipolar base in monolithic (IC and Power on the same chip) to give it both the MOS and bipolar advantages. The high temperature operating characteristics of the device are discussed and compared to that of power bipolar transistor. Unlike the power bipolar transistor whose operating current density shows current crowding at above forward collector current of 4Amps and forward voltage drop above 0.4V, the IGBT is found to maintain its high current density above forward collector of current 1Amp (or a forward voltage drop above 1.2V). The results also indicate that these devices (IGBTs) can be interdigited (paralleled) without current hogging problems if the forward conduction occurs at forward voltage drops in excess of 1.2V, and this makes it the best candidate for automotive ignition power switches. (author). 20 refs, 10 figs, 1 tab

Neutron Radiation Effect On 2N2222 And NTE 123 NPN Silicon Bipolar Junction Transistors

International Nuclear Information System (INIS)

Oo, Myo Min; Rashid, N K A Md; Hasbullah, N F; Karim, J Abdul; Zin, M R Mohamed

2013-01-01

This paper examines neutron radiation with PTS (Pneumatic Transfer System) effect on silicon NPN bipolar junction transistors (2N2222 and NTE 123) and analysis of the transistors in terms of electrical characterization such as current gain after neutron radiation. The key parameters are measured with Keithley 4200SCS. Experiment results show that the current gain degradation of the transistors is very sensitive to neutron radiation. The neutron radiation can cause displacement damage in the bulk layer of the transistor structure. The current degradation is believed to be governed by increasing recombination current between the base and emitter depletion region

Field-effect transistors based on self-organized molecular nanostripes

DEFF Research Database (Denmark)

Cavallini, M.; Stoliare, P.; Moulin, J.-F.

2005-01-01

Charge transport properties in organic semiconductors depend strongly on molecular order. Here we demonstrate field-effect transistors where drain current flows through a precisely defined array of nanostripes made of crystalline and highly ordered molecules. The molecular stripes are fabricated ...... by the menisci once the critical concentration is reached and self-organizes into molecularly ordered stripes 100-200 nm wide and a few monolayers high. The charge mobility measured along the stripes is 2 orders of magnitude larger than the values measured for spin-coated thin films....... across the channel of the transistor by a stamp-assisted deposition of the molecular semiconductors from a solution. As the solvent evaporates, the capillary forces drive the solution to form menisci under the stamp protrusions. The solute precipitates only in the regions where the solution is confined...

Carbon Based Transistors and Nanoelectronic Devices

Science.gov (United States)

Rouhi, Nima

Carbon based materials (carbon nanotube and graphene) has been extensively researched during the past decade as one of the promising materials to be used in high performance device technology. In long term it is thought that they may replace digital and/or analog electronic devices, due to their size, near-ballistic transport, and high stability. However, a more realistic point of insertion into market may be the printed nanoelectronic circuits and sensors. These applications include printed circuits for flexible electronics and displays, large-scale bendable electrical contacts, bio-membranes and bio sensors, RFID tags, etc. In order to obtain high performance thin film transistors (as the basic building block of electronic circuits) one should be able to manufacture dense arrays of all semiconducting nanotubes. Besides, graphene synthesize and transfer technology is in its infancy and there is plenty of room to improve the current techniques. To realize the performance of nanotube and graphene films in such systems, we need to economically fabricate large-scale devices based on these materials. Following that the performance control over such devices should also be considered for future design variations for broad range of applications. Here we have first investigated carbon nanotube ink as the base material for our devices. The primary ink used consisted of both metallic and semiconducting nanotubes which resulted in networks suitable for moderate-resistivity electrical connections (such as interconnects) and rfmatching circuits. Next, purified all-semiconducting nanotube ink was used to fabricate waferscale, high performance (high mobility, and high on/off ratio) thin film transistors for printed electronic applications. The parameters affecting device performance were studied in detail to establish a roadmap for the future of purified nanotube ink printed thin film transistors. The trade of between mobility and on/off ratio of such devices was studied and the

Switching current imbalance mitigation in power modules with parallel connected SiC MOSFETs

DEFF Research Database (Denmark)

Beczkowski, Szymon; Jørgensen, Asger Bjørn; Li, Helong

2017-01-01

Multichip power modules use parallel connected chips to achieve high current rating. Due to a finite flexibility in a DBC layout, some electrical asymmetries will occur in the module. Parallel connected transistors will exhibit uneven static and dynamic current sharing due to these asymmetries....... Especially important are the couplings between gate and power loops of individual transistors. Fast changing source currents cause gate voltage imbalances yielding uneven switching currents. Equalizing gate voltages seen by paralleled transistors, done by adjusting source bond wires, is proposed...... in this paper. Analysis is performed on an industry standard DBC layout using numerically extracted module parasitics. The method of tuning individual source inductances shows clear improvement in dynamic current balancing and prevents excessive current overshoot during transistors turn-on....

A silicon doped hafnium oxide ferroelectric p–n–p–n SOI tunneling field–effect transistor with steep subthreshold slope and high switching state current ratio

Directory of Open Access Journals (Sweden)

Saeid Marjani

2016-09-01

Full Text Available In this paper, a silicon–on–insulator (SOI p–n–p–n tunneling field–effect transistor (TFET with a silicon doped hafnium oxide (Si:HfO2 ferroelectric gate stack is proposed and investigated via 2D device simulation with a calibrated nonlocal band–to–band tunneling model. Utilization of Si:HfO2 instead of conventional perovskite ferroelectrics such as lead zirconium titanate (PbZrTiO3 and strontium bismuth tantalate (SrBi2Ta2O9 provides compatibility to the CMOS process as well as improved device scalability. By using Si:HfO2 ferroelectric gate stack, the applied gate voltage is effectively amplified that causes increased electric field at the tunneling junction and reduced tunneling barrier width. Compared with the conventional p–n–p–n SOI TFET, the on–state current and switching state current ratio are appreciably increased; and the average subthreshold slope (SS is effectively reduced. The simulation results of Si:HfO2 ferroelectric p–n–p–n SOI TFET show significant improvement in transconductance (∼9.8X enhancement at high overdrive voltage and average subthreshold slope (∼35% enhancement over nine decades of drain current at room temperature, indicating that this device is a promising candidate to strengthen the performance of p–n–p–n and conventional TFET for a switching performance.

Study on ionizing radiation effects of bipolar transistor with BPSG films

International Nuclear Information System (INIS)

Lu Man; Zhang Xiaoling; Xie Xuesong; Sun Jiangchao; Wang Pengpeng; Lu Changzhi; Zhang Yanxiu

2013-01-01

Background: Because of the damage induced by ionizing radiation, bipolar transistors in integrated voltage regulator could induce the current gain degradation and increase leakage current. This will bring serious problems to electronic system. Purpose: In order to ensure the reliability of the device work in the radiation environments, the device irradiation reinforcement technology is used. Methods: The characteristics of 60 Co γ irradiation and annealing at different temperatures in bipolar transistors and voltage regulators (JW117) with different passive films for SiO 2 +BPSG+SiO 2 and SiO 2 +SiN have been investigated. Results: The devices with BPSG film enhanced radiation tolerance significantly. Because BPSG films have better absorption for Na + in SiO 2 layer, the surface recombination rate of base region in a bipolar transistor and the excess base current have been reduced. It may be the main reason for BJT with BPSG film having a good radiation hardness. And annealing experiments at different temperatures after irradiation ensure the reliability of the devices with BPSG films. Conclusions: A method of improving the ionizing irradiation hardness of bipolar transistors is proposed. As well as the linear integrated circuits which containing bipolar transistors, an experimental basis for the anti-ionizing radiation effects of bipolar transistors is provided. (authors)

AlGaN/GaN high-electron-mobility transistors with transparent gates by Al-doped ZnO

International Nuclear Information System (INIS)

Wang Chong; He Yun-Long; Zheng Xue-Feng; Ma Xiao-Hua; Zhang Jin-Cheng; Hao Yue

2013-01-01

AlGaN/GaN high-electron-mobility transistors (HEMTs) with Al-doped ZnO (AZO) transparent gate electrodes are fabricated, and Ni/Au/Ni-gated HEMTs are produced in comparison. The AZO-gated HEMTs show good DC characteristics and Schottky rectifying characteristics, and the gate electrodes achieve excellent transparencies. Compared with Ni/Au/Ni-gated HEMTs, AZO-gated HEMTs show a low saturation current, high threshold voltage, high Schottky barrier height, and low gate reverse leakage current. Due to the higher gate resistivity, AZO-gated HEMTs exhibit a current—gain cutoff frequency (f T ) of 10 GHz and a power gain cutoff frequency (f max ) of 5 GHz, and lower maximum oscillation frequency than Ni/Au/Ni-gated HEMTs. Moreover, the C—V characteristics are measured and the gate interface characteristics of the AZO-gated devices are investigated by a C—V dual sweep

Proton conducting sodium alginate electrolyte laterally coupled low-voltage oxide-based transistors

Energy Technology Data Exchange (ETDEWEB)

Liu, Yang Hui; Wan, Qing, E-mail: wanqing@nju.edu.cn [Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); School of Electronic Science and Engineering, Nanjing University, Nanjing 210093 (China); Qiang Zhu, Li, E-mail: lqzhu@nimte.ac.cn [Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Shi, Yi [School of Electronic Science and Engineering, Nanjing University, Nanjing 210093 (China)

2014-03-31

Solution-processed sodium alginate electrolyte film shows a high proton conductivity of ∼5.5 × 10{sup −3} S/cm and a high lateral electric-double-layer (EDL) capacitance of ∼2.0 μF/cm{sup 2} at room temperature with a relative humidity of 57%. Low-voltage in-plane-gate indium-zinc-oxide-based EDL transistors laterally gated by sodium alginate electrolytes are fabricated on glass substrates. The field-effect mobility, current ON/OFF ratio, and subthreshold swing of such EDL transistors are estimated to be 4.2 cm{sup 2} V{sup −1} s{sup −1}, 2.8 × 10{sup 6}, and 130 mV/decade, respectively. At last, a low-voltage driven resistor-load inverter is also demonstrated. Such in-plane-gate EDL transistors have potential applications in portable electronics and low-cost biosensors.

Liquid crystals for organic transistors (Conference Presentation)

Science.gov (United States)

Hanna, Jun-ichi; Iino, Hiroaki

2016-09-01

Liquid crystals are a new type of organic semiconductors exhibiting molecular orientation in self-organizing manner, and have high potential for device applications. In fact, various device applications have been proposed so far, including photosensors, solar cells, light emitting diodes, field effect transistors, and so on.. However, device performance in those fabricated with liquid crystals is less than those of devices fabricated with conventional materials in spite of unique features of liquid crystals. Here we discuss how we can utilize the liquid crystallinity in organic transistors and how we can overcome conventional non-liquid crystalline organic transistor materials. Then, we demonstrate high performance organic transistors fabricated with a smectic E liquid crystal of Ph-BTBT-10, which show high mobility of over 10cm2/Vs and high thermal durability of over 200oC in OFETs fabricated with its spin-coated polycrystalline thin films.

Performance improvement for solution-processed high-mobility ZnO thin-film transistors

International Nuclear Information System (INIS)

Li Chensha; Loutfy, Rafik O; Li Yuning; Wu Yiliang; Ong, Beng S

2008-01-01

The fabrication technology of stable, non-toxic, transparent, high performance zinc oxide (ZnO) thin-film semiconductors via the solution process was investigated. Two methods, which were, respectively, annealing a spin-coated precursor solution and annealing a drop-coated precursor solution, were compared. The prepared ZnO thin-film semiconductor transistors have well-controlled, preferential crystal orientation and exhibit superior field-effect performance characteristics. But the ZnO thin-film transistor (TFT) fabricated by annealing a drop-coated precursor solution has a distinctly elevated linear mobility, which further approaches the saturated mobility, compared with that fabricated by annealing a spin-coated precursor solution. The performance of the solution-processed ZnO TFT was further improved when substituting the spin-coating process by the drop-coating process

Performance improvement for solution-processed high-mobility ZnO thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Li Chensha; Loutfy, Rafik O [Department of Chemical Engineering, McMaster University, 1280 Main Street West, Hamilton, Ontario L8S 4L7 (Canada); Li Yuning; Wu Yiliang; Ong, Beng S [Materials Design and Integration Laboratory, Xerox Research Centre of Canada, 2660 Speakman Drive, Mississauga, Ontario L5K 2L1 (Canada)], E-mail: lichnsa@163.com

2008-06-21

The fabrication technology of stable, non-toxic, transparent, high performance zinc oxide (ZnO) thin-film semiconductors via the solution process was investigated. Two methods, which were, respectively, annealing a spin-coated precursor solution and annealing a drop-coated precursor solution, were compared. The prepared ZnO thin-film semiconductor transistors have well-controlled, preferential crystal orientation and exhibit superior field-effect performance characteristics. But the ZnO thin-film transistor (TFT) fabricated by annealing a drop-coated precursor solution has a distinctly elevated linear mobility, which further approaches the saturated mobility, compared with that fabricated by annealing a spin-coated precursor solution. The performance of the solution-processed ZnO TFT was further improved when substituting the spin-coating process by the drop-coating process.

Nanoscale investigation of AlGaN/GaN-on-Si high electron mobility transistors.

Science.gov (United States)

Fontserè, A; Pérez-Tomás, A; Placidi, M; Llobet, J; Baron, N; Chenot, S; Cordier, Y; Moreno, J C; Jennings, M R; Gammon, P M; Fisher, C A; Iglesias, V; Porti, M; Bayerl, A; Lanza, M; Nafría, M

2012-10-05

AlGaN/GaN HEMTs are devices which are strongly influenced by surface properties such as donor states, roughness or any kind of inhomogeneity. The electron gas is only a few nanometers away from the surface and the transistor forward and reverse currents are considerably affected by any variation of surface property within the atomic scale. Consequently, we have used the technique known as conductive AFM (CAFM) to perform electrical characterization at the nanoscale. The AlGaN/GaN HEMT ohmic (drain and source) and Schottky (gate) contacts were investigated by the CAFM technique. The estimated area of these highly conductive pillars (each of them of approximately 20-50 nm radius) represents around 5% of the total contact area. Analogously, the reverse leakage of the gate Schottky contact at the nanoscale seems to correlate somehow with the topography of the narrow AlGaN barrier regions producing larger currents.

Vertical architecture for enhancement mode power transistors based on GaN nanowires

Science.gov (United States)

Yu, F.; Rümmler, D.; Hartmann, J.; Caccamo, L.; Schimpke, T.; Strassburg, M.; Gad, A. E.; Bakin, A.; Wehmann, H.-H.; Witzigmann, B.; Wasisto, H. S.; Waag, A.

2016-05-01

The demonstration of vertical GaN wrap-around gated field-effect transistors using GaN nanowires is reported. The nanowires with smooth a-plane sidewalls have hexagonal geometry made by top-down etching. A 7-nanowire transistor exhibits enhancement mode operation with threshold voltage of 1.2 V, on/off current ratio as high as 108, and subthreshold slope as small as 68 mV/dec. Although there is space charge limited current behavior at small source-drain voltages (Vds), the drain current (Id) and transconductance (gm) reach up to 314 mA/mm and 125 mS/mm, respectively, when normalized with hexagonal nanowire circumference. The measured breakdown voltage is around 140 V. This vertical approach provides a way to next-generation GaN-based power devices.

Stretchable transistors with buckled carbon nanotube films as conducting channels

Science.gov (United States)

Arnold, Michael S; Xu, Feng

2015-03-24

Thin-film transistors comprising buckled films comprising carbon nanotubes as the conductive channel are provided. Also provided are methods of fabricating the transistors. The transistors, which are highly stretchable and bendable, exhibit stable performance even when operated under high tensile strains.

AlN metal-semiconductor field-effect transistors using Si-ion implantation

Science.gov (United States)

Okumura, Hironori; Suihkonen, Sami; Lemettinen, Jori; Uedono, Akira; Zhang, Yuhao; Piedra, Daniel; Palacios, Tomás

2018-04-01

We report on the electrical characterization of Si-ion implanted AlN layers and the first demonstration of metal-semiconductor field-effect transistors (MESFETs) with an ion-implanted AlN channel. The ion-implanted AlN layers with Si dose of 5 × 1014 cm-2 exhibit n-type characteristics after thermal annealing at 1230 °C. The ion-implanted AlN MESFETs provide good drain current saturation and stable pinch-off operation even at 250 °C. The off-state breakdown voltage is 2370 V for drain-to-gate spacing of 25 µm. These results show the great potential of AlN-channel transistors for high-temperature and high-power applications.

Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor

Science.gov (United States)

Madan, Jaya; Gupta, R. S.; Chaujar, Rishu

2015-09-01

In this work, an analytical drain current model for gate dielectric engineered (hetero dielectric)-dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed. Parabolic approximation has been used to solve the two-dimensional (2D) Poisson equation with appropriate boundary conditions and continuity equations to evaluate analytical expressions for surface potential, electric field, tunneling barrier width and drain current. Further, the analog performance of the device is studied for three high-k dielectrics (Si3N4, HfO2, and ZrO2), and it has been investigated that the problem of lower ION, can be overcome by using the hetero-gate architecture. Moreover, the impact of scaling the gate oxide thickness and bias variations has also been studied. The HD-DMG-GAA-TFET shows an enhanced ION of the order of 10-4 A. The effectiveness of the proposed model is validated by comparing it with ATLAS device simulations.

Highly Sensitive Flexible Pressure Sensors Based on Printed Organic Transistors with Centro-Apically Self-Organized Organic Semiconductor Microstructures.

Science.gov (United States)

Yeo, So Young; Park, Sangsik; Yi, Yeon Jin; Kim, Do Hwan; Lim, Jung Ah

2017-12-13

A highly sensitive pressure sensor based on printed organic transistors with three-dimensionally self-organized organic semiconductor microstructures (3D OSCs) was demonstrated. A unique organic transistor with semiconductor channels positioned at the highest summit of printed cylindrical microstructures was achieved simply by printing an organic semiconductor and polymer blend on the plastic substrate without the use of additional etching or replication processes. A combination of the printed organic semiconductor microstructure and an elastomeric top-gate dielectric resulted in a highly sensitive organic field-effect transistor (FET) pressure sensor with a high pressure sensitivity of 1.07 kPa -1 and a rapid response time of <20 ms with a high reliability over 1000 cycles. The flexibility and high performance of the 3D OSC FET pressure sensor were exploited in the successful application of our sensors to real-time monitoring of the radial artery pulse, which is useful for healthcare monitoring, and to touch sensing in the e-skin of a realistic prosthetic hand.

Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

Science.gov (United States)

Zhi, Jiang; Yi-Qi, Zhuang; Cong, Li; Ping, Wang; Yu-Qi, Liu

2016-02-01

Trap-assisted tunneling (TAT) has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor (TFET). In this paper, we assess subthreshold performance of double gate TFET (DG-TFET) through a band-to-band tunneling (BTBT) model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile (Dit) and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current. Project supported by the National Natural Science Foundation of China (Grant Nos. 61574109 and 61204092).

Electrical pulse burnout of transistors in intense ionizing radiation

International Nuclear Information System (INIS)

Hartman, E.F.; Evans, D.C.

1975-01-01

Tests examining possible synergistic effects of electrical pulses and ionizing radiation on transistors were performed and energy/power thresholds for transistor burnout determined. The effect of ionizing radiation on burnout thresholds was found to be minimal, indicating that electrical pulse testing in the absence of radiation produces burnout-threshold results which are applicable to IEMP studies. The conditions of ionized transistor junctions and radiation induced current surges at semiconductor device terminals are inherent in IEMP studies of electrical circuits

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices.

Science.gov (United States)

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines.

Mapping brain activity with flexible graphene micro-transistors

Science.gov (United States)

Blaschke, Benno M.; Tort-Colet, Núria; Guimerà-Brunet, Anton; Weinert, Julia; Rousseau, Lionel; Heimann, Axel; Drieschner, Simon; Kempski, Oliver; Villa, Rosa; Sanchez-Vives, Maria V.; Garrido, Jose A.

2017-06-01

Establishing a reliable communication interface between the brain and electronic devices is of paramount importance for exploiting the full potential of neural prostheses. Current microelectrode technologies for recording electrical activity, however, evidence important shortcomings, e.g. challenging high density integration. Solution-gated field-effect transistors (SGFETs), on the other hand, could overcome these shortcomings if a suitable transistor material were available. Graphene is particularly attractive due to its biocompatibility, chemical stability, flexibility, low intrinsic electronic noise and high charge carrier mobilities. Here, we report on the use of an array of flexible graphene SGFETs for recording spontaneous slow waves, as well as visually evoked and also pre-epileptic activity in vivo in rats. The flexible array of graphene SGFETs allows mapping brain electrical activity with excellent signal-to-noise ratio (SNR), suggesting that this technology could lay the foundation for a future generation of in vivo recording implants.

Electrical characterization of commercial NPN bipolar junction transistors under neutron and gamma irradiation

Directory of Open Access Journals (Sweden)

OO Myo Min

2014-01-01

Full Text Available Electronics components such as bipolar junction transistors, diodes, etc. which are used in deep space mission are required to be tolerant to extensive exposure to energetic neutrons and ionizing radiation. This paper examines neutron radiation with pneumatic transfer system of TRIGA Mark-II reactor at the Malaysian Nuclear Agency. The effects of the gamma radiation from Co-60 on silicon NPN bipolar junction transistors is also be examined. Analyses on irradiated transistors were performed in terms of the electrical characteristics such as current gain, collector current and base current. Experimental results showed that the current gain on the devices degraded significantly after neutron and gamma radiations. Neutron radiation can cause displacement damage in the bulk layer of the transistor structure and gamma radiation can induce ionizing damage in the oxide layer of emitter-base depletion layer. The current gain degradation is believed to be governed by the increasing recombination current in the base-emitter depletion region.

Highly selective and sensitive phosphate anion sensors based on AlGaN/GaN high electron mobility transistors functionalized by ion imprinted polymer.

Science.gov (United States)

Jia, Xiuling; Chen, Dunjun; Bin, Liu; Lu, Hai; Zhang, Rong; Zheng, Youdou

2016-06-09

A novel ion-imprinted electrochemical sensor based on AlGaN/GaN high electron mobility transistors (HEMTs) was developed to detect trace amounts of phosphate anion. This sensor combined the advantages of the ion sensitivity of AlGaN/GaN HEMTs and specific recognition of ion imprinted polymers. The current response showed that the fabricated sensor is highly sensitive and selective to phosphate anions. The current change exhibited approximate linear dependence for phosphate concentration from 0.02 mg L(-1) to 2 mg L(-1), the sensitivity and detection limit of the sensor is 3.191 μA/mg L(-1) and 1.97 μg L(-1), respectively. The results indicated that this AlGaN/GaN HEMT-based electrochemical sensor has the potential applications on phosphate anion detection.

Cryogenic preamplification of a single-electron-transistor using a silicon-germanium heterojunction-bipolar-transistor

Energy Technology Data Exchange (ETDEWEB)

Curry, M. J. [Department of Physics and Astronomy, University of New Mexico, Albuquerque, New Mexico 87131 (United States); Center for Quantum Information and Control, University of New Mexico, Albuquerque, New Mexico 87131 (United States); Sandia National Laboratories, 1515 Eubank Blvd SE, Albuquerque, New Mexico 87123 (United States); England, T. D.; Bishop, N. C.; Ten-Eyck, G.; Wendt, J. R.; Pluym, T.; Lilly, M. P.; Carroll, M. S. [Sandia National Laboratories, 1515 Eubank Blvd SE, Albuquerque, New Mexico 87123 (United States); Carr, S. M. [Center for Quantum Information and Control, University of New Mexico, Albuquerque, New Mexico 87131 (United States); Sandia National Laboratories, 1515 Eubank Blvd SE, Albuquerque, New Mexico 87123 (United States)

2015-05-18

We examine a silicon-germanium heterojunction bipolar transistor (HBT) for cryogenic pre-amplification of a single electron transistor (SET). The SET current modulates the base current of the HBT directly. The HBT-SET circuit is immersed in liquid helium, and its frequency response from low frequency to several MHz is measured. The current gain and the noise spectrum with the HBT result in a signal-to-noise-ratio (SNR) that is a factor of 10–100 larger than without the HBT at lower frequencies. The transition frequency defined by SNR = 1 has been extended by as much as a factor of 10 compared to without the HBT amplification. The power dissipated by the HBT cryogenic pre-amplifier is approximately 5 nW to 5 μW for the investigated range of operation. The circuit is also operated in a single electron charge read-out configuration in the time-domain as a proof-of-principle demonstration of the amplification approach for single spin read-out.

Current fluctuation of electron and hole carriers in multilayer WSe{sub 2} field effect transistors

Energy Technology Data Exchange (ETDEWEB)

Ko, Seung-Pil; Shin, Jong Mok; Jang, Ho-Kyun; Jin, Jun Eon; Kim, Gyu-Tae, E-mail: gtkim@korea.ac.kr [School of Electrical Engineering, Korea University, Seoul 02481 (Korea, Republic of); Kim, Yong Jin; Kim, Young Keun [Department of Materials Science and Engineering, Korea University, Seoul 02481 (Korea, Republic of); Shin, Minju [School of Electrical Engineering, Korea University, Seoul 02481 (Korea, Republic of); IMEP-LAHC, Grenoble INP-MINATEC, 3 Parvis Louis Neel, 38016 Grenoble (France)

2015-12-14

Two-dimensional materials have outstanding scalability due to their structural and electrical properties for the logic devices. Here, we report the current fluctuation in multilayer WSe{sub 2} field effect transistors (FETs). In order to demonstrate the impact on carrier types, n-type and p-type WSe{sub 2} FETs are fabricated with different work function metals. Each device has similar electrical characteristics except for the threshold voltage. In the low frequency noise analysis, drain current power spectral density (S{sub I}) is inversely proportional to frequency, indicating typical 1/f noise behaviors. The curves of the normalized drain current power spectral density (NS{sub I}) as a function of drain current at the 10 Hz of frequency indicate that our devices follow the carrier number fluctuation with correlated mobility fluctuation model. This means that current fluctuation depends on the trapping-detrapping motion of the charge carriers near the channel interface. No significant difference is observed in the current fluctuation according to the charge carrier type, electrons and holes that occurred in the junction and channel region.

Barrier reduction via implementation of InGaN interlayer in wafer-bonded current aperture vertical electron transistors consisting of InGaAs channel and N-polar GaN drain

International Nuclear Information System (INIS)

Kim, Jeonghee; Laurent, Matthew A.; Li, Haoran; Lal, Shalini; Mishra, Umesh K.

2015-01-01

This letter reports the influence of the added InGaN interlayer on reducing the inherent interfacial barrier and hence improving the electrical characteristics of wafer-bonded current aperture vertical electron transistors consisting of an InGaAs channel and N-polar GaN drain. The current-voltage characteristics of the transistors show that the implementation of N-polar InGaN interlayer effectively reduces the barrier to electron transport across the wafer-bonded interface most likely due to its polarization induced downward band bending, which increases the electron tunneling probability. Fully functional wafer-bonded transistors with nearly 600 mA/mm of drain current at V GS  = 0 V and L go  = 2 μm have been achieved, and thus demonstrate the feasibility of using wafer-bonded heterostructures for applications that require active carrier transport through both materials

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

International Nuclear Information System (INIS)

Nedic, Stanko; Welland, Mark; Tea Chun, Young; Chu, Daping; Hong, Woong-Ki

2014-01-01

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ∼16.5 V, a high drain current on/off ratio of ∼10 5 , a gate leakage current below ∼300 pA, and excellent retention characteristics for over 10 4 s

Demonstration of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with silicon-oxy-nitride as the gate insulator

International Nuclear Information System (INIS)

Balachander, K.; Arulkumaran, S.; Egawa, T.; Sano, Y.; Baskar, K.

2005-01-01

AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs) were fabricated with plasma enhanced chemical vapor deposited silicon oxy-nitride (SiON) as an insulating layer. The compositions of SiON thin films were confirmed using X-ray photoelectron spectroscopy. The fabricated MOSHEMTs exhibited a very high saturation current density of 1.1 A/mm coupled with high positive operational gate voltage up to +7 V. The MOSHEMTs also exhibited four orders of low gate leakage current and high forward-on voltage when compared with the conventional HEMTs. The drain current collapse using gate pulse measurements showed only a negligible difference in the saturation current density revealing the drastic improvement in passivation of the surface states due to the high quality of dielectric thin films deposited. Thus, based on the improved direct-current operation, SiON can be considered to be a potential gate oxide comparable with other dielectric insulators

Investigation of Impact of the Gate Circuitry on IGBT Transistor Dynamic Parameters

Directory of Open Access Journals (Sweden)

Vytautas Bleizgys

2011-03-01

Full Text Available The impact of Insulated Gate Bipolar Transistor driver circuit parameters on the rise and fall time of the collector current and voltage collector-emitter was investigated. The influence of transistor driver circuit parameters on heating of Insulated Gate Bipolar Transistors was investigated as well.Article in Lithuanian

Kinase detection with gallium nitride based high electron mobility transistors.

Science.gov (United States)

Makowski, Matthew S; Bryan, Isaac; Sitar, Zlatko; Arellano, Consuelo; Xie, Jinqiao; Collazo, Ramon; Ivanisevic, Albena

2013-07-01

A label-free kinase detection system was fabricated by the adsorption of gold nanoparticles functionalized with kinase inhibitor onto AlGaN/GaN high electron mobility transistors (HEMTs). The HEMTs were operated near threshold voltage due to the greatest sensitivity in this operational region. The Au NP/HEMT biosensor system electrically detected 1 pM SRC kinase in ionic solutions. These results are pertinent to drug development applications associated with kinase sensing.

AlN Surface Passivation of GaN-Based High Electron Mobility Transistors by Plasma-Enhanced Atomic Layer Deposition.

Science.gov (United States)

Tzou, An-Jye; Chu, Kuo-Hsiung; Lin, I-Feng; Østreng, Erik; Fang, Yung-Sheng; Wu, Xiao-Peng; Wu, Bo-Wei; Shen, Chang-Hong; Shieh, Jia-Ming; Yeh, Wen-Kuan; Chang, Chun-Yen; Kuo, Hao-Chung

2017-12-01

We report a low current collapse GaN-based high electron mobility transistor (HEMT) with an excellent thermal stability at 150 °C. The AlN was grown by N 2 -based plasma enhanced atomic layer deposition (PEALD) and shown a refractive index of 1.94 at 633 nm of wavelength. Prior to deposit AlN on III-nitrides, the H 2 /NH 3 plasma pre-treatment led to remove the native gallium oxide. The X-ray photoelectron spectroscopy (XPS) spectroscopy confirmed that the native oxide can be effectively decomposed by hydrogen plasma. Following the in situ ALD-AlN passivation, the surface traps can be eliminated and corresponding to a 22.1% of current collapse with quiescent drain bias (V DSQ ) at 40 V. Furthermore, the high temperature measurement exhibited a shift-free threshold voltage (V th ), corresponding to a 40.2% of current collapse at 150 °C. The thermal stable HEMT enabled a breakdown voltage (BV) to 687 V at high temperature, promising a good thermal reliability under high power operation.

AlN Surface Passivation of GaN-Based High Electron Mobility Transistors by Plasma-Enhanced Atomic Layer Deposition

Science.gov (United States)

Tzou, An-Jye; Chu, Kuo-Hsiung; Lin, I.-Feng; Østreng, Erik; Fang, Yung-Sheng; Wu, Xiao-Peng; Wu, Bo-Wei; Shen, Chang-Hong; Shieh, Jia-Ming; Yeh, Wen-Kuan; Chang, Chun-Yen; Kuo, Hao-Chung

2017-04-01

We report a low current collapse GaN-based high electron mobility transistor (HEMT) with an excellent thermal stability at 150 °C. The AlN was grown by N2-based plasma enhanced atomic layer deposition (PEALD) and shown a refractive index of 1.94 at 633 nm of wavelength. Prior to deposit AlN on III-nitrides, the H2/NH3 plasma pre-treatment led to remove the native gallium oxide. The X-ray photoelectron spectroscopy (XPS) spectroscopy confirmed that the native oxide can be effectively decomposed by hydrogen plasma. Following the in situ ALD-AlN passivation, the surface traps can be eliminated and corresponding to a 22.1% of current collapse with quiescent drain bias ( V DSQ) at 40 V. Furthermore, the high temperature measurement exhibited a shift-free threshold voltage ( V th), corresponding to a 40.2% of current collapse at 150 °C. The thermal stable HEMT enabled a breakdown voltage (BV) to 687 V at high temperature, promising a good thermal reliability under high power operation.

Wavy Architecture Thin-Film Transistor for Ultrahigh Resolution Flexible Displays

KAUST Repository

Hanna, Amir Nabil

2017-11-13

A novel wavy-shaped thin-film-transistor (TFT) architecture, capable of achieving 70% higher drive current per unit chip area when compared with planar conventional TFT architectures, is reported for flexible display application. The transistor, due to its atypical architecture, does not alter the turn-on voltage or the OFF current values, leading to higher performance without compromising static power consumption. The concept behind this architecture is expanding the transistor\\'s width vertically through grooved trenches in a structural layer deposited on a flexible substrate. Operation of zinc oxide (ZnO)-based TFTs is shown down to a bending radius of 5 mm with no degradation in the electrical performance or cracks in the gate stack. Finally, flexible low-power LEDs driven by the respective currents of the novel wavy, and conventional coplanar architectures are demonstrated, where the novel architecture is able to drive the LED at 2 × the output power, 3 versus 1.5 mW, which demonstrates the potential use for ultrahigh resolution displays in an area efficient manner.

Intrinsically stretchable and healable semiconducting polymer for organic transistors.

Science.gov (United States)

Oh, Jin Young; Rondeau-Gagné, Simon; Chiu, Yu-Cheng; Chortos, Alex; Lissel, Franziska; Wang, Ging-Ji Nathan; Schroeder, Bob C; Kurosawa, Tadanori; Lopez, Jeffrey; Katsumata, Toru; Xu, Jie; Zhu, Chenxin; Gu, Xiaodan; Bae, Won-Gyu; Kim, Yeongin; Jin, Lihua; Chung, Jong Won; Tok, Jeffrey B-H; Bao, Zhenan

2016-11-17

Thin-film field-effect transistors are essential elements of stretchable electronic devices for wearable electronics. All of the materials and components of such transistors need to be stretchable and mechanically robust. Although there has been recent progress towards stretchable conductors, the realization of stretchable semiconductors has focused mainly on strain-accommodating engineering of materials, or blending of nanofibres or nanowires into elastomers. An alternative approach relies on using semiconductors that are intrinsically stretchable, so that they can be fabricated using standard processing methods. Molecular stretchability can be enhanced when conjugated polymers, containing modified side-chains and segmented backbones, are infused with more flexible molecular building blocks. Here we present a design concept for stretchable semiconducting polymers, which involves introducing chemical moieties to promote dynamic non-covalent crosslinking of the conjugated polymers. These non-covalent crosslinking moieties are able to undergo an energy dissipation mechanism through breakage of bonds when strain is applied, while retaining high charge transport abilities. As a result, our polymer is able to recover its high field-effect mobility performance (more than 1 square centimetre per volt per second) even after a hundred cycles at 100 per cent applied strain. Organic thin-film field-effect transistors fabricated from these materials exhibited mobility as high as 1.3 square centimetres per volt per second and a high on/off current ratio exceeding a million. The field-effect mobility remained as high as 1.12 square centimetres per volt per second at 100 per cent strain along the direction perpendicular to the strain. The field-effect mobility of damaged devices can be almost fully recovered after a solvent and thermal healing treatment. Finally, we successfully fabricated a skin-inspired stretchable organic transistor operating under deformations that might be

High performance ring oscillators from 10-nm wide silicon nanowire field-effect transistors

KAUST Repository

Huang, Ruo-Gu; Tham, Douglas; Wang, Dunwei; Heath, James R.

2011-01-01

We explore 10-nm wide Si nanowire (SiNW) field-effect transistors (FETs) for logic applications, via the fabrication and testing of SiNW-based ring oscillators. We report on SiNW surface treatments and dielectric annealing, for producing SiNW FETs that exhibit high performance in terms of large on/off-state current ratio (~108), low drain-induced barrier lowering (~30 mV) and low subthreshold swing (~80 mV/decade). The performance of inverter and ring-oscillator circuits fabricated from these nanowire FETs are also explored. The inverter demonstrates the highest voltage gain (~148) reported for a SiNW-based NOT gate, and the ring oscillator exhibits near rail-to-rail oscillation centered at 13.4 MHz. The static and dynamic characteristics of these NW devices indicate that these SiNW-based FET circuits are excellent candidates for various high-performance nanoelectronic applications. © 2011 Tsinghua University Press and Springer-Verlag Berlin Heidelberg.

High performance ring oscillators from 10-nm wide silicon nanowire field-effect transistors

KAUST Repository

Huang, Ruo-Gu

2011-06-24

We explore 10-nm wide Si nanowire (SiNW) field-effect transistors (FETs) for logic applications, via the fabrication and testing of SiNW-based ring oscillators. We report on SiNW surface treatments and dielectric annealing, for producing SiNW FETs that exhibit high performance in terms of large on/off-state current ratio (~108), low drain-induced barrier lowering (~30 mV) and low subthreshold swing (~80 mV/decade). The performance of inverter and ring-oscillator circuits fabricated from these nanowire FETs are also explored. The inverter demonstrates the highest voltage gain (~148) reported for a SiNW-based NOT gate, and the ring oscillator exhibits near rail-to-rail oscillation centered at 13.4 MHz. The static and dynamic characteristics of these NW devices indicate that these SiNW-based FET circuits are excellent candidates for various high-performance nanoelectronic applications. © 2011 Tsinghua University Press and Springer-Verlag Berlin Heidelberg.

Amorphous Zinc Oxide Integrated Wavy Channel Thin Film Transistor Based High Performance Digital Circuits

KAUST Repository

Hanna, Amir; Hussain, Aftab M.; Omran, Hesham; Alshareef, Sarah; Salama, Khaled N.; Hussain, Muhammad Mustafa

2015-01-01

High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (Zn

Large-area WSe2 electric double layer transistors on a plastic substrate

KAUST Repository

Funahashi, Kazuma; Pu, Jiang; Li, Ming Yang; Li, Lain-Jong; Iwasa, Yoshihiro; Takenobu, Taishi

2015-01-01

Due to the requirements for large-area, uniform films, currently transition metal dichalcogenides (TMDC) cannot be used in flexible transistor industrial applications. In this study, we first transferred chemically grown large-area WSe2 monolayer films from the as-grown sapphire substrates to the flexible plastic substrates. We also fabricated electric double layer transistors using the WSe2 films on the plastic substrates. These transistors exhibited ambipolar operation and an ON/OFF current ratio of ∼104, demonstrating chemically grown WSe2 transistors on plastic substrates for the first time. This achievement can be an important first step for the next-generation TMDC based flexible devices. © 2015 The Japan Society of Applied Physics.

Large-area WSe2 electric double layer transistors on a plastic substrate

KAUST Repository

Funahashi, Kazuma

2015-04-27

Due to the requirements for large-area, uniform films, currently transition metal dichalcogenides (TMDC) cannot be used in flexible transistor industrial applications. In this study, we first transferred chemically grown large-area WSe2 monolayer films from the as-grown sapphire substrates to the flexible plastic substrates. We also fabricated electric double layer transistors using the WSe2 films on the plastic substrates. These transistors exhibited ambipolar operation and an ON/OFF current ratio of ∼104, demonstrating chemically grown WSe2 transistors on plastic substrates for the first time. This achievement can be an important first step for the next-generation TMDC based flexible devices. © 2015 The Japan Society of Applied Physics.

Organic semiconductors for organic field-effect transistors

International Nuclear Information System (INIS)

Yamashita, Yoshiro

2009-01-01

The advantages of organic field-effect transistors (OFETs), such as low cost, flexibility and large-area fabrication, have recently attracted much attention due to their electronic applications. Practical transistors require high mobility, large on/off ratio, low threshold voltage and high stability. Development of new organic semiconductors is key to achieving these parameters. Recently, organic semiconductors have been synthesized showing comparable mobilities to amorphous-silicon-based FETs. These materials make OFETs more attractive and their applications have been attempted. New organic semiconductors resulting in high-performance FET devices are described here and the relationship between transistor characteristics and chemical structure is discussed. (topical review)

Organic semiconductors for organic field-effect transistors

Directory of Open Access Journals (Sweden)

Yoshiro Yamashita

2009-01-01

Full Text Available The advantages of organic field-effect transistors (OFETs, such as low cost, flexibility and large-area fabrication, have recently attracted much attention due to their electronic applications. Practical transistors require high mobility, large on/off ratio, low threshold voltage and high stability. Development of new organic semiconductors is key to achieving these parameters. Recently, organic semiconductors have been synthesized showing comparable mobilities to amorphous-silicon-based FETs. These materials make OFETs more attractive and their applications have been attempted. New organic semiconductors resulting in high-performance FET devices are described here and the relationship between transistor characteristics and chemical structure is discussed.

Leakage current suppression with a combination of planarized gate and overlap/off-set structure in metal-induced laterally crystallized polycrystalline-silicon thin-film transistors

Science.gov (United States)

Chae, Hee Jae; Seok, Ki Hwan; Lee, Sol Kyu; Joo, Seung Ki

2018-04-01

A novel inverted staggered metal-induced laterally crystallized (MILC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with a combination of a planarized gate and an overlap/off-set at the source-gate/drain-gate structure were fabricated and characterized. While the MILC process is advantageous for fabricating inverted staggered poly-Si TFTs, MILC TFTs reveal higher leakage current than TFTs crystallized by other processes due to their high trap density of Ni contamination. Due to this drawback, the planarized gate and overlap/off-set structure were applied to inverted staggered MILC TFTs. The proposed device shows drastic suppression of leakage current and pinning phenomenon by reducing the lateral electric field and the space-charge limited current from the gate to the drain.

Junctionless Thin-Film Transistors Gated by an H₃PO₄-Incorporated Chitosan Proton Conductor.

Science.gov (United States)

Liu, Huixuan; Xun, Damao

2018-04-01

We fabricated an H3PO4-incorporated chitosan proton conductor film that exhibited the electric double layer effect and showed a high specific capacitance of 4.42 μF/cm2. Transparent indium tin oxide thin-film transistors gated by H3PO4-incorporated chitosan films were fabricated by sputtering through a shadow mask. The operating voltage was as low as 1.2 V because of the high specific capacitance of the H3PO4-incorporated chitosan dielectrics. The junctionless transparent indium tin oxide thin film transistors exhibited good performance, including an estimated current on/off ratio and field-effect mobility of 1.2 × 106 and 6.63 cm2V-1s-1, respectively. These low-voltage thin-film electric-double-layer transistors gated by H3PO4-incorporated chitosan are promising for next generation battery-powered "see-through" portable sensors.

Doped Organic Transistors.

Science.gov (United States)

Lüssem, Björn; Keum, Chang-Min; Kasemann, Daniel; Naab, Ben; Bao, Zhenan; Leo, Karl

2016-11-23

Organic field-effect transistors hold the promise of enabling low-cost and flexible electronics. Following its success in organic optoelectronics, the organic doping technology is also used increasingly in organic field-effect transistors. Doping not only increases device performance, but it also provides a way to fine-control the transistor behavior, to develop new transistor concepts, and even improve the stability of organic transistors. This Review summarizes the latest progress made in the understanding of the doping technology and its application to organic transistors. It presents the most successful doping models and an overview of the wide variety of materials used as dopants. Further, the influence of doping on charge transport in the most relevant polycrystalline organic semiconductors is reviewed, and a concise overview on the influence of doping on transistor behavior and performance is given. In particular, recent progress in the understanding of contact doping and channel doping is summarized.

Principles of an atomtronic transistor

International Nuclear Information System (INIS)

Caliga, Seth C; Anderson, Dana Z; Straatsma, Cameron J E; Zozulya, Alex A

2016-01-01

A semiclassical formalism is used to investigate the transistor-like behavior of ultracold atoms in a triple-well potential. Atom current flows from the source well, held at fixed chemical potential and temperature, into an empty drain well. In steady-state, the gate well located between the source and drain is shown to acquire a well-defined chemical potential and temperature, which are controlled by the relative height of the barriers separating the three wells. It is shown that the gate chemical potential can exceed that of the source and have a lower temperature. In electronics terminology, the source–gate junction can be reverse-biased. As a result, the device exhibits regimes of negative resistance and transresistance, indicating the presence of gain. Given an external current input to the gate, transistor-like behavior is characterized both in terms of the current gain, which can be greater than unity, and the power output of the device. (paper)

Theory and application of dual-transistor charge separation analysis

International Nuclear Information System (INIS)

Fleetwood, D.M.; Schwank, J.R.; Winokur, P.S.; Sexton, F.W.; Shaneyfelt, M.R.

1989-01-01

The authors describe a dual-transistor charge separation method to evaluate the radiation response of MOS transistors. This method requires that n- and p-channel transistors with identically processed oxides be irradiated under identical conditions at the same oxide electric fields. Combining features of single-transistor midgap and mobility methods, the authors show how one may determine threshold voltage shifts due to oxide-trapped and interface-trapped charge from standard threshold voltage and mobility measurements. These measurements can be made at currents 2-5 orders of magnitude higher than those required for midgap, subthreshold slope, and charge-pumping methods. The dual-transistor method contains no adjustable parameters, and includes an internal self-consistency check. The accuracy of the method is verified by comparison to midgap, subthreshold slope, and charge-pumping methods for several MOS processes and technologies

Utilizing Schottky barriers to suppress short-channel effects in organic transistors

Science.gov (United States)

Fernández, Anton F.; Zojer, Karin

2017-10-01

Transistors with short channel lengths exhibit profound deviations from the ideally expected behavior. One of the undesired short-channel effects is an enlarged OFF current that is associated with a premature turn on of the transistor. We present an efficient approach to suppress the OFF current, defined as the current at zero gate source bias, in short-channel organic transistors. We employ two-dimensional device simulations based on the drift-diffusion model to demonstrate that intentionally incorporating a Schottky barrier for injection enhances the ON-OFF ratio in both staggered and coplanar transistor architectures. The Schottky barrier is identified to directly counteract the origin of enlarged OFF currents: Short channels promote a drain-induced barrier lowering. The latter permits unhindered injection of charges even at reverse gate-source bias. An additional Schottky barrier hampers injection for such points of operations. We explain how it is possible to find the Schottky barrier of the smallest height necessary to exactly compensate for the premature turn on. This approach offers a substantial enhancement of the ON-OFF ratio. We show that this roots in the fact that such optimal barrier heights offer an excellent compromise between an OFF current diminished by orders of magnitude and an only slightly reduced ON current.

Implementation of Self-Bias Transistor on Voting Logic

International Nuclear Information System (INIS)

Harzawardi Hasim; Syirrazie Che Soh

2014-01-01

Study in the eld of digital integrated circuit (IC) already become common to the modern industrial. Day by day we have been introduced with new gadget that was developed based on transistor. This paper will study the implementation of self-bias transistor on voting logic. The self-bias transistor will connected both on pull-up network and pull-down network. On previous research, study on comparison of total number of transistors, time propagation delay, and frequency between NAND and NOR gate of voting logic. It's show, with the same number of transistor, NAND gate achieve high frequency and low time propagation delay compare to NOR gate. We extend this analysis by comparing the total number of transistor, time propagation delay, frequency and power dissipation between common NAND gate with self-bias NAND gate. Extensive LTSpice simulations were performed using IBM 90 nm CMOS(Complementary Metal Oxide Semiconductor) process technology. The result show self-bias voting NAND gate consumes 54 % less power dissipation, 43% slow frequency and 43 % high time propagation delay compare to common voting NAND gate. (author)

Dosimetric properties of MOS transistors

International Nuclear Information System (INIS)

Frank, H.; Petr, I.

1977-01-01

The structure of MOS transistors is described and their characteristics given. The experiments performed and data in the literature show the following dosimetric properties of MOS transistors: while for low gamma doses the transistor response to exposure is linear, it shows saturation for higher doses (exceeding 10 3 Gy in tissue). The response is independent of the energy of radiation and of the dose rate (within 10 -2 to 10 5 Gy/s). The spontaneous reduction with time of the spatial charge captured by the oxide layer (fading) is small and acceptable from the point of view of dosimetry. Curves are given of isochronous annealing of the transistors following irradiation with 137 Cs and 18 MeV electrons for different voltages during irradiation. The curves show that in MOS transistors irradiated with high-energy electrons the effect of annealing is less than in transistors irradiated with 137 Cs. In view of the requirement of using higher temperatures (approx. 400 degC) for the complete ''erasing'' of the captured charge, unsealed systems must be used for dosimetric purposes. The effect was also studied of neutron radiation, proton radiation and electron radiation on the MOS transistor structure. For MOS transistor irradiation with 14 MeV neutrons from a neutron generator the response was 4% of that for gamma radiation at the same dose equivalent. The effect of proton radiation was studied as related to the changes in MOS transistor structure during space flights. The response curve shapes are similar to those of gamma radiation curves. The effect of electron radiation on the MOS structure was studied by many authors. The experiments show that for each thickness of the SiO 2 layer an electron energy exists at which the size of the charge captured in SiO 2 is the greatest. All data show that MOS transistors are promising for radiation dosimetry. The main advantage of MOS transistors as gamma dosemeters is the ease and speed of evaluation, low sensitivity to neutron

Poole-Frenkel behavior in amorphous oxide thin-film transistors prepared on SiOC

International Nuclear Information System (INIS)

Oh, Teresa

2014-01-01

The electron behavior in amorphous indium-gallium-zinc-oxide thin film transistors (a-IGZO TFTs) depends on the polar characteristics of SiOC, which is used as a gate dielectric. The properties of the interface between the semiconductor and SiOC were defined by using a Schottky contact with a low potential barrier and Poole-Frenkel contacts with a high potential barrier. The leakage current of SiOC, which was used as a gate insulator, decreased at the Poole-Frenkel contacts because of the high potential barrier. The ambipolar properties in the field effect transistor were observed to depend on the various characteristics of SiOC, which ranged from its behaving as an ideal insulator or as a material with a high dielectric constant. The resistance of the a-IGZO channel changed from positive to negative at SiOC, which had the lowest polarity. As to the conduction due to the diffusion current, the mobility increased with increasing carrier concentrations. However, the drift carrier conduction was related to the reduced mobility at higher carrier concentrations. The performance of the transistors was enhanced by the tunneling and the diffusion currents Rather than by the drift current caused by trapping. The Schottky contact and the Poole-Frenkel (PF) contacts at an interface between the IGZO channel and the SiOC were defined according to the heights of potential barriers caused by the depletion layer. The leakage current was very low about 10 -12 A at SiOC with PF contacts because of the height of potential barrier was double that with a Schottky contact because the tunneling conductance due to the diffusion current originated from the PF contacts of non-polar SiOC.

Poole-Frenkel behavior in amorphous oxide thin-film transistors prepared on SiOC

Energy Technology Data Exchange (ETDEWEB)

Oh, Teresa [Cheongju University, Cheongju (Korea, Republic of)

2014-05-15

The electron behavior in amorphous indium-gallium-zinc-oxide thin film transistors (a-IGZO TFTs) depends on the polar characteristics of SiOC, which is used as a gate dielectric. The properties of the interface between the semiconductor and SiOC were defined by using a Schottky contact with a low potential barrier and Poole-Frenkel contacts with a high potential barrier. The leakage current of SiOC, which was used as a gate insulator, decreased at the Poole-Frenkel contacts because of the high potential barrier. The ambipolar properties in the field effect transistor were observed to depend on the various characteristics of SiOC, which ranged from its behaving as an ideal insulator or as a material with a high dielectric constant. The resistance of the a-IGZO channel changed from positive to negative at SiOC, which had the lowest polarity. As to the conduction due to the diffusion current, the mobility increased with increasing carrier concentrations. However, the drift carrier conduction was related to the reduced mobility at higher carrier concentrations. The performance of the transistors was enhanced by the tunneling and the diffusion currents Rather than by the drift current caused by trapping. The Schottky contact and the Poole-Frenkel (PF) contacts at an interface between the IGZO channel and the SiOC were defined according to the heights of potential barriers caused by the depletion layer. The leakage current was very low about 10{sup -12} A at SiOC with PF contacts because of the height of potential barrier was double that with a Schottky contact because the tunneling conductance due to the diffusion current originated from the PF contacts of non-polar SiOC.

Vertically stacked multi-heterostructures of layered materials for logic transistors and complementary inverters

Science.gov (United States)

Yu, Woo Jong; Li, Zheng; Zhou, Hailong; Chen, Yu; Wang, Yang; Huang, Yu; Duan, Xiangfeng

2014-01-01

The layered materials such as graphene have attracted considerable interest for future electronics. Here we report the vertical integration of multi-heterostructures of layered materials to enable high current density vertical field-effect transistors (VFETs). An n-channel VFET is created by sandwiching few-layer molybdenum disulfide (MoS2) as the semiconducting channel between a monolayer graphene and a metal thin film. The VFETs exhibit a room temperature on-off ratio >103, while at same time deliver a high current density up to 5,000 A/cm2, sufficient for high performance logic applications. This study offers a general strategy for the vertical integration of various layered materials to obtain both p- and n-channel transistors for complementary logic functions. A complementary inverter with larger than unit voltage gain is demonstrated by vertically stacking the layered materials of graphene, Bi2Sr2Co2O8 (p-channel), graphene, MoS2 (n-channel), and metal thin film in sequence. The ability to simultaneously achieve high on-off ratio, high current density, and logic integration in the vertically stacked multi-heterostructures can open up a new dimension for future electronics to enable three-dimensional integration. PMID:23241535

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.

Science.gov (United States)

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-10-20

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.

Dithiopheneindenofluorene (TIF) Semiconducting Polymers with Very High Mobility in Field-Effect Transistors

KAUST Repository

Chen, Hu

2017-07-19

The charge-carrier mobility of organic semiconducting polymers is known to be enhanced when the energetic disorder of the polymer is minimized. Fused, planar aromatic ring structures contribute to reducing the polymer conformational disorder, as demonstrated by polymers containing the indacenodithiophene (IDT) repeat unit, which have both a low Urbach energy and a high mobility in thin-film-transistor (TFT) devices. Expanding on this design motif, copolymers containing the dithiopheneindenofluorene repeat unit are synthesized, which extends the fused aromatic structure with two additional phenyl rings, further rigidifying the polymer backbone. A range of copolymers are prepared and their electrical properties and thin-film morphology evaluated, with the co-benzothiadiazole polymer having a twofold increase in hole mobility when compared to the IDT analog, reaching values of almost 3 cm2 V−1 s−1 in bottom-gate top-contact organic field-effect transistors.

High performance and transparent multilayer MoS2 transistors: Tuning Schottky barrier characteristics

Directory of Open Access Journals (Sweden)

Young Ki Hong

2016-05-01

Full Text Available Various strategies and mechanisms have been suggested for investigating a Schottky contact behavior in molybdenum disulfide (MoS2 thin-film transistor (TFT, which are still in much debate and controversy. As one of promising breakthrough for transparent electronics with a high device performance, we have realized MoS2 TFTs with source/drain electrodes consisting of transparent bi-layers of a conducting oxide over a thin film of low work function metal. Intercalation of a low work function metal layer, such as aluminum, between MoS2 and transparent source/drain electrodes makes it possible to optimize the Schottky contact characteristics, resulting in about 24-fold and 3 orders of magnitude enhancement of the field-effect mobility and on-off current ratio, respectively, as well as transmittance of 87.4 % in the visible wavelength range.

Comparative study of InGaP/GaAs high electron mobility transistors with upper and lower delta-doped supplied layers

International Nuclear Information System (INIS)

Tsai, Jung-Hui; Ye, Sheng-Shiun; Guo, Der-Feng; Lour, Wen-Shiung

2012-01-01

Influence corresponding to the position of δ-doped supplied layer on InGaP/GaAs high electron mobility transistors is comparatively studied by two-dimensional simulation analysis. The simulated results exhibit that the device with lower δ-doped supplied layer shows a higher gate potential barrier height, a higher saturation output current, a larger magnitude of negative threshold voltage, and broader gate voltage swing, as compared to the device with upper δ-doped supplied layer. Nevertheless, it has smaller transconductance and inferior high-frequency characteristics in the device with lower δ-doped supplied layer. Furthermore, a knee effect in current-voltage curves is observed at low drain-to-source voltage in the two devices, which is investigated in this article.

AlN/GaN heterostructures for normally-off transistors

Energy Technology Data Exchange (ETDEWEB)

Zhuravlev, K. S., E-mail: zhur@isp.nsc.ru; Malin, T. V.; Mansurov, V. G.; Tereshenko, O. E. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation); Abgaryan, K. K.; Reviznikov, D. L. [Dorodnicyn Computing Centre of the Russian Academy of Sciences (Russian Federation); Zemlyakov, V. E.; Egorkin, V. I. [National Research University of Electronic Technology (MIET) (Russian Federation); Parnes, Ya. M.; Tikhomirov, V. G. [Joint Stock Company “Svetlana-Electronpribor” (Russian Federation); Prosvirin, I. P. [Russian Academy of Sciences, Boreskov Institute of Catalysis, Siberian Branch (Russian Federation)

2017-03-15

The structure of AlN/GaN heterostructures with an ultrathin AlN barrier is calculated for normally-off transistors. The molecular-beam epitaxy technology of in situ passivated SiN/AlN/GaN heterostructures with a two-dimensional electron gas is developed. Normally-off transistors with a maximum current density of ~1 A/mm, a saturation voltage of 1 V, a transconductance of 350 mS/mm, and a breakdown voltage of more than 60 V are demonstrated. Gate lag and drain lag effects are almost lacking in these transistors.

Analysis of the background noise of field effect transistors in MOS complementary technology and application in the construction of a current-sensitive integrated amplifier

International Nuclear Information System (INIS)

Beuville, E.

1989-10-01

A low noise amplifier for use in high energy physics is developed. The origin and the mechanisms of the noise in MOSFET transistors is carried out with the aim of minimizing such effects in amplifiers. The research is applied in the construction of a current-sensitive integrated amplifier. The time scale continuous filtering principle is used and allows the detection of particles arriving in the counter in a random distribution. The rules which must be taken into account in the construction of an analog integrated circuit are shown [fr

Millimeter-wave small-signal modeling with optimizing sensitive-parameters for metamorphic high electron mobility transistors

International Nuclear Information System (INIS)

Moon, S-W; Baek, Y-H; Han, M; Rhee, J-K; Kim, S-D; Oh, J-H

2010-01-01

In this paper, we present a simple and reliable technique for determining the small-signal equivalent circuit model parameters of the 0.1 µm metamorphic high electron mobility transistors (MHEMTs) in a millimeter-wave frequency range. The initial eight extrinsic parameters of the MHEMT are extracted using two S-parameter (scattering parameter) sets measured under the pinched-off and zero-biased cold field-effect transistor conditions by avoiding the forward gate biasing. Furthermore, highly calibration-sensitive values of the R s , L s and C pd are optimized by using a gradient optimization method to improve the modeling accuracy. The accuracy enhancement of this procedure is successfully verified with an excellent correlation between the measured and calculated S-parameters up to 65 GHz

Fabrication of amorphous InGaZnO thin-film transistor-driven flexible thermal and pressure sensors

International Nuclear Information System (INIS)

Park, Ick-Joon; Jeong, Chan-Yong; Song, Sang-Hun; Kwon, Hyuck-In; Cho, In-Tak; Lee, Jong-Ho; Cho, Eou-Sik; Kwon, Sang Jik; Kim, Bosul; Cheong, Woo-Seok

2012-01-01

In this work, we present the results concerning the use of amorphous indium–gallium–zinc–oxide (a-IGZO) thin-film transistor (TFT) as a driving transistor of the flexible thermal and pressure sensors which are applicable to artificial skin systems. Although the a-IGZO TFT has been attracting much attention as a driving transistor of the next-generation flat panel displays, no study has been performed about the application of this new device to the driving transistor of the flexible sensors yet. The proposed thermal sensor pixel is composed of the series-connected a-IGZO TFT and ZnO-based thermistor fabricated on a polished metal foil, and the ZnO-based thermistor is replaced by the pressure sensitive rubber in the pressure sensor pixel. In both sensor pixels, the a-IGZO TFT acts as the driving transistor and the temperature/pressure-dependent resistance of the ZnO-based thermistor/pressure-sensitive rubber mainly determines the magnitude of the output currents. The fabricated a-IGZO TFT-driven flexible thermal sensor shows around a seven times increase in the output current as the temperature increases from 20 °C to 100 °C, and the a-IGZO TFT-driven flexible pressure sensors also exhibit high sensitivity under various pressure environments. (paper)

Towards high frequency heterojunction transistors: Electrical characterization of N-doped amorphous silicon-graphene diodes

Science.gov (United States)

Strobel, C.; Chavarin, C. A.; Kitzmann, J.; Lupina, G.; Wenger, Ch.; Albert, M.; Bartha, J. W.

2017-06-01

N-type doped amorphous hydrogenated silicon (a-Si:H) is deposited on top of graphene (Gr) by means of very high frequency (VHF) and radio frequency plasma-enhanced chemical vapor deposition (PECVD). In order to preserve the structural integrity of the monolayer graphene, a plasma excitation frequency of 140 MHz was successfully applied during the a-Si:H VHF-deposition. Raman spectroscopy results indicate the absence of a defect peak in the graphene spectrum after the VHF-PECVD of (n)-a-Si:H. The diode junction between (n)-a-Si:H and graphene was characterized using temperature dependent current-voltage (IV) and capacitance-voltage measurements, respectively. We demonstrate that the current at the (n)-a-Si:H-graphene interface is dominated by thermionic emission and recombination in the space charge region. The Schottky barrier height (qΦB), derived by temperature dependent IV-characteristics, is about 0.49 eV. The junction properties strongly depend on the applied deposition method of (n)-a-Si:H with a clear advantage of the VHF(140 MHz)-technology. We have demonstrated that (n)-a-Si:H-graphene junctions are a promising technology approach for high frequency heterojunction transistors.

Amorphous Zinc Oxide Integrated Wavy Channel Thin Film Transistor Based High Performance Digital Circuits

KAUST Repository

Hanna, Amir

2015-12-04

High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (ZnO) present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it to the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared to the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field effect mobility due to higher gate field electrostatics control.

Cylindrical Field Effect Transistor: A Full Volume Inversion Device

KAUST Repository

Fahad, Hossain M.

2010-12-01

The increasing demand for high performance as well as low standby power devices has been the main reason for the aggressive scaling of conventional CMOS transistors. Current devices are at the 32nm technology node. However, due to physical limitations as well as increase in short-channel effects, leakage, power dissipation, this scaling trend cannot continue and will eventually hit a barrier. In order to overcome this, alternate device topologies have to be considered altogether. Extensive research on ultra thin body double gate FETs and gate all around nanowire FETs has shown a lot of promise. Under strong inversion, these devices have demonstrated increased performance over their bulk counterparts. This is mainly attributed to full carrier inversion in the body. However, these devices are still limited by lithographic and processing challenges making them unsuitable for commercial production. This thesis explores a unique device structure called the CFET (Cylindrical Field Effect Transistors) which also like the above, relies on complete inversion of carriers in the body/bulk. Using dual gates; an outer and an inner gate, full-volume inversion is possible with benefits such as enhanced drive currents, high Ion/Ioff ratios and reduced short channel effects.

Organic High Electron Mobility Transistors Realized by 2D Electron Gas.

Science.gov (United States)

Zhang, Panlong; Wang, Haibo; Yan, Donghang

2017-09-01

A key breakthrough in inorganic modern electronics is the energy-band engineering that plays important role to improve device performance or develop novel functional devices. A typical application is high electron mobility transistors (HEMTs), which utilizes 2D electron gas (2DEG) as transport channel and exhibits very high electron mobility over traditional field-effect transistors (FETs). Recently, organic electronics have made very rapid progress and the band transport model is demonstrated to be more suitable for explaining carrier behavior in high-mobility crystalline organic materials. Therefore, there emerges a chance for applying energy-band engineering in organic semiconductors to tailor their optoelectronic properties. Here, the idea of energy-band engineering is introduced and a novel device configuration is constructed, i.e., using quantum well structures as active layers in organic FETs, to realize organic 2DEG. Under the control of gate voltage, electron carriers are accumulated and confined at quantized energy levels, and show efficient 2D transport. The electron mobility is up to 10 cm 2 V -1 s -1 , and the operation mechanisms of organic HEMTs are also argued. Our results demonstrate the validity of tailoring optoelectronic properties of organic semiconductors by energy-band engineering, offering a promising way for the step forward of organic electronics. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Self-Consistent Study of Conjugated Aromatic Molecular Transistors

International Nuclear Information System (INIS)

Jing, Wang; Yun-Ye, Liang; Hao, Chen; Peng, Wang; Note, R.; Mizuseki, H.; Kawazoe, Y.

2010-01-01

We study the current through conjugated aromatic molecular transistors modulated by a transverse field. The self-consistent calculation is realized with density function theory through the standard quantum chemistry software Gaussian03 and the non-equilibrium Green's function formalism. The calculated I – V curves controlled by the transverse field present the characteristics of different organic molecular transistors, the transverse field effect of which is improved by the substitutions of nitrogen atoms or fluorine atoms. On the other hand, the asymmetry of molecular configurations to the axis connecting two sulfur atoms is in favor of realizing the transverse field modulation. Suitably designed conjugated aromatic molecular transistors possess different I – V characteristics, some of them are similar to those of metal-oxide-semiconductor field-effect transistors (MOSFET). Some of the calculated molecular devices may work as elements in graphene electronics. Our results present the richness and flexibility of molecular transistors, which describe the colorful prospect of next generation devices. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Fabrication and electrical properties of MoS2 nanodisc-based back-gated field effect transistors.

Science.gov (United States)

Gu, Weixia; Shen, Jiaoyan; Ma, Xiying

2014-02-28

Two-dimensional (2D) molybdenum disulfide (MoS2) is an attractive alternative semiconductor material for next-generation low-power nanoelectronic applications, due to its special structure and large bandgap. Here, we report the fabrication of large-area MoS2 nanodiscs and their incorporation into back-gated field effect transistors (FETs) whose electrical properties we characterize. The MoS2 nanodiscs, fabricated via chemical vapor deposition (CVD), are homogeneous and continuous, and their thickness of around 5 nm is equal to a few layers of MoS2. In addition, we find that the MoS2 nanodisc-based back-gated field effect transistors with nickel electrodes achieve very high performance. The transistors exhibit an on/off current ratio of up to 1.9 × 105, and a maximum transconductance of up to 27 μS (5.4 μS/μm). Moreover, their mobility is as high as 368 cm2/Vs. Furthermore, the transistors have good output characteristics and can be easily modulated by the back gate. The electrical properties of the MoS2 nanodisc transistors are better than or comparable to those values extracted from single and multilayer MoS2 FETs.

Performance of AlGaN/GaN Heterostructure Field-Effect Transistors for High-Frequency and High-Power Electronics

Directory of Open Access Journals (Sweden)

Peter Kordos

2005-01-01

Full Text Available Preparation and properties of GaN-based heterostructure field-effect transistors (HFETs for high-frequency and high-power applications are studied in this work. Performance of unpassivated and SiO2 passivated AlGaN/GaN HFETs, as well as passivated SiO2/AlGaN/GaN MOSHFETs (metal-oxide-semicondutor HFETs is compared. It is found that MOSHFETs exhibit better DC and RF properties than simple HFET counterparts. Deposited SiO2 yielded an increase of the sheet carrier density from 7.6x10^12 cm^-2 to 9.2x10^12 cm^-2 and subsequent increase of the static drain saturation current from 0.75 A/mm to 1.09 A/mm. Small-signal RF characterisation of MOSHFETs showed an extrinsic current gain cut-off frequency fT of 24 GHz and a maximum frequency of oscillation fmax of 40 GHz. These are fully comparable values with state-of-the-art AlGaN/GaN HFETs. Finnaůůy, microwave power measurements confirmed excellent performance of MOSHFETs:the output power measured at 7 GHz is about two-times larger than that of simple unpassived HFET. Thus, a great potential in application of GaN-based MOSHFETs is documented. 

Suppression of self-heating effect in AlGaN/GaN high electron mobility transistors by substrate-transfer technology using h-BN

International Nuclear Information System (INIS)

Hiroki, Masanobu; Kumakura, Kazuhide; Kobayashi, Yasuyuki; Akasaka, Tetsuya; Makimoto, Toshiki; Yamamoto, Hideki

2014-01-01

We fabricated AlGaN/GaN high electron mobility transistors (HEMTs) on h-BN/sapphire substrates and transferred them from the host substrates to copper plates using h-BN as a release layer. In current–voltage characteristics, the saturation drain current decreased by about 30% under a high-bias condition before release by self-heating effect. In contrast, after transfer, the current decrement was as small as 8% owing to improved heat dissipation: the device temperature increased to 50 °C in the as-prepared HEMT, but only by several degrees in the transferred HEMT. An effective way to improve AlGaN/GaN HEMT performance by a suppression of self-heating effect has been demonstrated

Suppression of self-heating effect in AlGaN/GaN high electron mobility transistors by substrate-transfer technology using h-BN

Energy Technology Data Exchange (ETDEWEB)

Hiroki, Masanobu, E-mail: hiroki.masanobu@lab.ntt.co.jp; Kumakura, Kazuhide; Kobayashi, Yasuyuki; Akasaka, Tetsuya; Makimoto, Toshiki; Yamamoto, Hideki [NTT Basic Research Laboratories, NTT Corporation 3-1 Morinosato Wakamiya, Atsugi-shi 243-0198 (Japan)

2014-11-10

We fabricated AlGaN/GaN high electron mobility transistors (HEMTs) on h-BN/sapphire substrates and transferred them from the host substrates to copper plates using h-BN as a release layer. In current–voltage characteristics, the saturation drain current decreased by about 30% under a high-bias condition before release by self-heating effect. In contrast, after transfer, the current decrement was as small as 8% owing to improved heat dissipation: the device temperature increased to 50 °C in the as-prepared HEMT, but only by several degrees in the transferred HEMT. An effective way to improve AlGaN/GaN HEMT performance by a suppression of self-heating effect has been demonstrated.

Design Optimization of Transistors Used for Neural Recording

Directory of Open Access Journals (Sweden)

Eric Basham

2012-01-01

Full Text Available Neurons cultured directly over open-gate field-effect transistors result in a hybrid device, the neuron-FET. Neuron-FET amplifier circuits reported in the literature employ the neuron-FET transducer as a current-mode device in conjunction with a transimpedance amplifier. In this configuration, the transducer does not provide any signal gain, and characterization of the transducer out of the amplification circuit is required. Furthermore, the circuit requires a complex biasing scheme that must be retuned to compensate for drift. Here we present an alternative strategy based on the gm/Id design approach to optimize a single-stage common-source amplifier design. The gm/Id design approach facilitates in circuit characterization of the neuron-FET and provides insight into approaches to improving the transistor process design for application as a neuron-FET transducer. Simulation data for a test case demonstrates optimization of the transistor design and significant increase in gain over a current mode implementation.

Simulation of a spintronic transistor: A study of its performance

International Nuclear Information System (INIS)

Pela, R.R.; Teles, L.K.

2009-01-01

We study theoretically the magnetic bipolar transistor, and compare its performance with common bipolar transistor. We present not only the simulation results for the characteristic curves, but also other relevant parameters related with its performance, such as: the current amplification factor, the open-loop gain, the hybrid parameters and the cutoff frequency. We noted that the spin-charge coupling introduces new phenomena that enrich the functionality characteristics of the magnetic bipolar transistor. Among other things, it has an adjustable band structure, which may be modified during the device operation; it exhibits the already known spin-voltaic effect. On the other hand, we observed that it is necessary a large g-factor to analyze the influence of the field B over the transistor. Nevertheless, we consider the magnetic bipolar transistor as a promising device for spintronic applications

Charge injection engineering of ambipolar field-effect transistors for high-performance organic complementary circuits.

Science.gov (United States)

Baeg, Kang-Jun; Kim, Juhwan; Khim, Dongyoon; Caironi, Mario; Kim, Dong-Yu; You, In-Kyu; Quinn, Jordan R; Facchetti, Antonio; Noh, Yong-Young

2011-08-01

Ambipolar π-conjugated polymers may provide inexpensive large-area manufacturing of complementary integrated circuits (CICs) without requiring micro-patterning of the individual p- and n-channel semiconductors. However, current-generation ambipolar semiconductor-based CICs suffer from higher static power consumption, low operation frequencies, and degraded noise margins compared to complementary logics based on unipolar p- and n-channel organic field-effect transistors (OFETs). Here, we demonstrate a simple methodology to control charge injection and transport in ambipolar OFETs via engineering of the electrical contacts. Solution-processed caesium (Cs) salts, as electron-injection and hole-blocking layers at the interface between semiconductors and charge injection electrodes, significantly decrease the gold (Au) work function (∼4.1 eV) compared to that of a pristine Au electrode (∼4.7 eV). By controlling the electrode surface chemistry, excellent p-channel (hole mobility ∼0.1-0.6 cm(2)/(Vs)) and n-channel (electron mobility ∼0.1-0.3 cm(2)/(Vs)) OFET characteristics with the same semiconductor are demonstrated. Most importantly, in these OFETs the counterpart charge carrier currents are highly suppressed for depletion mode operation (I(off) 0.1-0.2 mA). Thus, high-performance, truly complementary inverters (high gain >50 and high noise margin >75% of ideal value) and ring oscillators (oscillation frequency ∼12 kHz) based on a solution-processed ambipolar polymer are demonstrated.

Effect of 1MeV electron beam on transistors and circuits

International Nuclear Information System (INIS)

Lee, Tae Hoon

1998-02-01

It has been known that semiconductor devices operating in a radiation environment exhibited significant alterations of their electrical responses. Since an electron beam bombardment produces lattice damage in Si and charged defects in SiO 2 , several electrical parameters of transistors exhibit significant changes. Those parameters are the current gain of BJT (Bipolar Junction Transistor) and the threshold voltage of MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The degradation of transistors brings about that of circuits. This paper presents the results of experiments and simulations performed to study the effects of 1MeV electron beam irradiation on selected silicon transistors and circuits. For BJTs, the current gains of npn (2N3904) and pnp (2N3906) linearly decreased as the irradiation dose increased, and from this result, the damage constants, Ks were obtained as 13.65 for 2N3904 and 22.52 for 2N3906 in MGy, indicating a more stable operation in the electron radiation environment for pnp than that for npn. The decrease of current gain was due to that of minority-carrier lifetime in the base region. For MOSFETs (CD4007s), the threshold voltages of NMOS and PMOS shifted to the lower values, which was resulted from the accumulation of charge in SiO 2 . The charges could be categorized into fixed oxide charge and interfacial trap charge. From experimental results, the amounts of the induced charges could be quantitatively estimated. These degradations of transistors brought about the decrease in the voltage gain of CE (Common Emitter) amplifier and the shifts in the inverting voltage of inverter. Additionally, PSpice simulations of these circuits were carried out by modeling of irradiated transistors. The comparison of simulation with experiment showed the relatively good agreement of simulation for the degradation of circuits after irradiation

Analysis of Proton Radiation Effects on Gallium Nitride High Electron Mobility Transistors

Science.gov (United States)

2017-03-01

non - ionizing proton radiation damage effects at different energy levels on a GaN-on-silicon high electron mobility transistor...DISTRIBUTION CODE 13. ABSTRACT (maximum 200 words) In this work, a physics-based simulation of non - ionizing proton radiation damage effects at different...Polarization . . . . . . . . . . . . . . 6 2.3 Non - Ionizing Radiation Damage Effects . . . . . . . . . . . . . . . 10 2.4 Non - Ionizing Radiation Damage in

Progresses in organic field-effect transistors and molecular electronics

Institute of Scientific and Technical Information of China (English)

Wu Weiping; Xu Wei; Hu Wenping; Liu Yunqi; Zhu Daoben

2006-01-01

In the past years,organic semiconductors have been extensively investigated as electronic materials for organic field-effect transistors (OFETs).In this review,we briefly summarize the current status of organic field-effect transistors including materials design,device physics,molecular electronics and the applications of carbon nanotubes in molecular electronics.Future prospects and investigations required to improve the OFET performance are also involved.

Molecular materials for organic field-effect transistors

International Nuclear Information System (INIS)

Mori, T

2008-01-01

Organic field-effect transistors are important applications of thin films of molecular materials. A variety of materials have been explored for improving the performance of organic transistors. The materials are conventionally classified as p-channel and n-channel, but not only the performance but also even the carrier polarity is greatly dependent on the combinations of organic semiconductors and electrode materials. In this review, particular emphasis is laid on multi-sulfur compounds such as tetrathiafulvalenes and metal dithiolates. These compounds are components of highly conducting materials such as organic superconductors, but are also used in organic transistors. The charge-transfer complexes are used in organic transistors as active layers as well as electrodes. (topical review)

High Electron Mobility Thin-Film Transistors Based on Solution-Processed Semiconducting Metal Oxide Heterojunctions and Quasi-Superlattices

KAUST Repository

Lin, Yen-Hung; Faber, Hendrik; Labram, John G.; Stratakis, Emmanuel; Sygellou, Labrini; Kymakis, Emmanuel; Hastas, Nikolaos A.; Li, Ruipeng; Zhao, Kui; Amassian, Aram; Treat, Neil D.; McLachlan, Martyn; Anthopoulos, Thomas D.

2015-01-01

High mobility thin-film transistor technologies that can be implemented using simple and inexpensive fabrication methods are in great demand because of their applicability in a wide range of emerging optoelectronics. Here, a novel concept of thin-film transistors is reported that exploits the enhanced electron transport properties of low-dimensional polycrystalline heterojunctions and quasi-superlattices (QSLs) consisting of alternating layers of In2O3, Ga2O3, and ZnO grown by sequential spin casting of different precursors in air at low temperatures (180–200 °C). Optimized prototype QSL transistors exhibit band-like transport with electron mobilities approximately a tenfold greater (25–45 cm2 V−1 s−1) than single oxide devices (typically 2–5 cm2 V−1 s−1). Based on temperature-dependent electron transport and capacitance-voltage measurements, it is argued that the enhanced performance arises from the presence of quasi 2D electron gas-like systems formed at the carefully engineered oxide heterointerfaces. The QSL transistor concept proposed here can in principle extend to a range of other oxide material systems and deposition methods (sputtering, atomic layer deposition, spray pyrolysis, roll-to-roll, etc.) and can be seen as an extremely promising technology for application in next-generation large area optoelectronics such as ultrahigh definition optical displays and large-area microelectronics where high performance is a key requirement.

High Electron Mobility Thin-Film Transistors Based on Solution-Processed Semiconducting Metal Oxide Heterojunctions and Quasi-Superlattices