Material parameters from frequency dispersion simulation of floating gate memory with Ge nanocrystals in HfO2

Science.gov (United States)

Palade, C.; Lepadatu, A. M.; Slav, A.; Lazanu, S.; Teodorescu, V. S.; Stoica, T.; Ciurea, M. L.

2018-01-01

Trilayer memory capacitors with Ge nanocrystals (NCs) floating gate in HfO2 were obtained by magnetron sputtering deposition on p-type Si substrate followed by rapid thermal annealing at relatively low temperature of 600 °C. The frequency dispersion of capacitance and resistance was measured in accumulation regime of Al/HfO2 gate oxide/Ge NCs in HfO2 floating gate/HfO2 tunnel oxide/SiOx/p-Si/Al memory capacitors. For simulation of the frequency dispersion a complex circuit model was used considering an equivalent parallel RC circuit for each layer of the trilayer structure. A series resistance due to metallic contacts and Si substrate was necessary to be included in the model. A very good fit to the experimental data was obtained and the parameters of each layer in the memory capacitor, i.e. capacitances and resistances were determined and in turn the intrinsic material parameters, i.e. dielectric constants and resistivities of layers were evaluated. The results are very important for the study and optimization of the hysteresis behaviour of floating gate memories based on NCs embedded in oxide.

Impact and Origin of Interface States in MOS Capacitor with Monolayer MoS2 and HfO2 High-k Dielectric.

Science.gov (United States)

Xia, Pengkun; Feng, Xuewei; Ng, Rui Jie; Wang, Shijie; Chi, Dongzhi; Li, Cequn; He, Zhubing; Liu, Xinke; Ang, Kah-Wee

2017-01-13

Two-dimensional layered semiconductors such as molybdenum disulfide (MoS 2 ) at the quantum limit are promising material for nanoelectronics and optoelectronics applications. Understanding the interface properties between the atomically thin MoS 2 channel and gate dielectric is fundamentally important for enhancing the carrier transport properties. Here, we investigate the frequency dispersion mechanism in a metal-oxide-semiconductor capacitor (MOSCAP) with a monolayer MoS 2 and an ultra-thin HfO 2 high-k gate dielectric. We show that the existence of sulfur vacancies at the MoS 2 -HfO 2 interface is responsible for the generation of interface states with a density (D it ) reaching ~7.03 × 10 11  cm -2  eV -1 . This is evidenced by a deficit S:Mo ratio of ~1.96 using X-ray photoelectron spectroscopy (XPS) analysis, which deviates from its ideal stoichiometric value. First-principles calculations within the density-functional theory framework further confirms the presence of trap states due to sulfur deficiency, which exist within the MoS 2 bandgap. This corroborates to a voltage-dependent frequency dispersion of ~11.5% at weak accumulation which decreases monotonically to ~9.0% at strong accumulation as the Fermi level moves away from the mid-gap trap states. Further reduction in D it could be achieved by thermally diffusing S atoms to the MoS 2 -HfO 2 interface to annihilate the vacancies. This work provides an insight into the interface properties for enabling the development of MoS 2 devices with carrier transport enhancement.

Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor

Science.gov (United States)

Madan, Jaya; Gupta, R. S.; Chaujar, Rishu

2015-09-01

In this work, an analytical drain current model for gate dielectric engineered (hetero dielectric)-dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed. Parabolic approximation has been used to solve the two-dimensional (2D) Poisson equation with appropriate boundary conditions and continuity equations to evaluate analytical expressions for surface potential, electric field, tunneling barrier width and drain current. Further, the analog performance of the device is studied for three high-k dielectrics (Si3N4, HfO2, and ZrO2), and it has been investigated that the problem of lower ION, can be overcome by using the hetero-gate architecture. Moreover, the impact of scaling the gate oxide thickness and bias variations has also been studied. The HD-DMG-GAA-TFET shows an enhanced ION of the order of 10-4 A. The effectiveness of the proposed model is validated by comparing it with ATLAS device simulations.

Chemical vapor deposited monolayer MoS2 top-gate MOSFET with atomic-layer-deposited ZrO2 as gate dielectric

Science.gov (United States)

Hu, Yaoqiao; Jiang, Huaxing; Lau, Kei May; Li, Qiang

2018-04-01

For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec-1, and a field-effect electron mobility of 12.1 cm2 V-1 s-1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm-1 at V DS = 5 V. The gate leakage current is below 10-2 A cm-2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm-1 is obtained. Gate hysteresis and frequency-dependent capacitance-voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ˜3 × 1012 cm-2 eV-1.

Photo-induced tunneling currents in MOS structures with various HfO2/SiO2 stacking dielectrics

Directory of Open Access Journals (Sweden)

Chin-Sheng Pang

2014-04-01

Full Text Available In this study, the current conduction mechanisms of structures with tandem high-k dielectric in illumination are discussed. Samples of Al/SiO2/Si (S, Al/HfO2/SiO2/Si (H, and Al/3HfO2/SiO2/Si (3H were examined. The significant observation of electron traps of sample H compares to sample S is found under the double bias capacitance-voltage (C-V measurements in illumination. Moreover, the photo absorption sensitivity of sample H is higher than S due to the formation of HfO2 dielectric layer, which leads to larger numbers of carriers crowded through the sweep of VG before the domination of tunneling current. Additionally, the HfO2 dielectric layer would block the electrons passing through oxide from valance band, which would result in less electron-hole (e−-h+ pairs recombination effect. Also, it was found that both of the samples S and H show perimeter dependency of positive bias currents due to strong fringing field effect in dark and illumination; while sample 3H shows area dependency of positive bias currents in strong illumination. The non-uniform tunneling current through thin dielectric and through HfO2 stacking layers are importance to MOS(p tunneling photo diodes.

Study of Direct-Contact HfO2/Si Interfaces

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Noriyuki Miyata

2012-03-01

Full Text Available Controlling monolayer Si oxide at the HfO2/Si interface is a challenging issue in scaling the equivalent oxide thickness of HfO2/Si gate stack structures. A concept that the author proposes to control the Si oxide interface by using ultra-high vacuum electron-beam HfO2 deposition is described in this review paper, which enables the so-called direct-contact HfO2/Si structures to be prepared. The electrical characteristics of the HfO2/Si metal-oxide-semiconductor capacitors are reviewed, which suggest a sufficiently low interface state density for the operation of metal-oxide-semiconductor field-effect-transistors (MOSFETs but reveal the formation of an unexpected strong interface dipole. Kelvin probe measurements of the HfO2/Si structures provide obvious evidence for the formation of dipoles at the HfO2/Si interfaces. The author proposes that one-monolayer Si-O bonds at the HfO2/Si interface naturally lead to a large potential difference, mainly due to the large dielectric constant of the HfO2. Dipole scattering is demonstrated to not be a major concern in the channel mobility of MOSFETs.

Band Alignment and Optical Properties of (ZrO20.66(HfO20.34 Gate Dielectrics Thin Films on p-Si (100

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Dahlang Tahir

2011-11-01

Full Text Available (ZrO20.66(HfO20.34 dielectric films on p-Si (100 were grown by atomic layer deposition method, for which the conduction band offsets, valence band offsets and band gaps were obtained by using X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy. The band gap, valence and conduction band offset values for (ZrO20.66(HfO20.34 dielectric thin film, grown on Si substrate were about 5.34, 2.35 and 1.87 eV respectively. This band alignment was similar to that of ZrO2. In addition, The dielectric function ε (k, ω, index of refraction n and the extinction coefficient k for the (ZrO20.66(HfO20.34 thin films were obtained from a quantitative analysis of REELS data by comparison to detailed dielectric response model calculations using the QUEELS-ε (k,ω-REELS software package. These optical properties are similar with ZrO2 dielectric thin films.

SHI induced effects on the electrical and optical properties of HfO_2 thin films deposited by RF sputtering

International Nuclear Information System (INIS)

Manikanthababu, N.; Dhanunjaya, M.; Nageswara Rao, S.V.S.; Pathak, A.P.

2016-01-01

The continuous downscaling of Metal Oxide Semiconductor (MOS) devices has reached a limit with SiO_2 as a gate dielectric material. Introducing high-k dielectric materials as a replacement for the conservative SiO_2 is the only alternative to reduce the leakage current. HfO_2 is a reliable and an impending material for the wide usage as a gate dielectric in semiconductor industry. HfO_2 thin films were synthesized by RF sputtering technique. Here, we present a study of Swift Heavy Ion (SHI) irradiation with100 MeV Ag ions for studying the optical properties as well as 80 MeV Ni ions for studying the electrical properties of HfO_2/Si thin films. Rutherford Backscattering Spectrometry (RBS), Field Emission Scanning Electron Microscope (FESEM), energy-dispersive X-ray spectroscopy (EDS), profilometer and I–V (leakage current) measurements have been employed to study the SHI induced effects on both the structural, electrical and optical properties.

Photoemission study on electrical dipole at SiO_2/Si and HfO_2/SiO_2 interfaces

International Nuclear Information System (INIS)

Fujimura, Nobuyuki; Ohta, Akio; Ikeda, Mitsuhisa; Makihara, Katsunori; Miyazaki, Seiichi

2017-01-01

Electrical dipole at SiO_2/Si and HfO_2/SiO_2 interfaces have been investigated by X-ray photoelectron spectroscopy (XPS) under monochromatized Al Kα radiation. From the analysis of the cut-off energy for secondary photoelectrons measured at each thinning step of a dielectric layer by wet-chemical etching, an abrupt potential change caused by electrical dipole at SiO_2/Si and HfO_2/SiO_2 interfaces has been clearly detected. Al-gate MOS capacitors with thermally-grown SiO_2 and a HfO_2/SiO_2 dielectric stack were fabricated to evaluate the Al work function from the flat band voltage shift of capacitance-voltage (C-V) characteristics. Comparing the results of XPS and C-V measurements, we have verified that electrical dipole formed at the interface can be directly measured by photoemission measurements. (author)

Characterization, integration and reliability of HfO2 and LaLuO3 high-κ/metal gate stacks for CMOS applications

International Nuclear Information System (INIS)

Nichau, Alexander

2013-01-01

. A lower limit found was EOT=5 Aa for Al doping inside TiN. The doping of TiN on LaLuO 3 is proven by electron energy loss spectroscopy (EELS) studies to modify the interfacial silicate layer to La-rich silicates or even reduce the layer. The oxide quality in Si/HfO 2 /TiN gate stacks is characterized by charge pumping and carrier mobility measurements on 3d MOSFETs a.k.a. FinFETs. The oxide quality in terms of the number of interface (and oxide) traps on top- and sidewall of FinFETs is compared for three different annealing processes. A high temperature anneal of HfO 2 improves significantly the oxide quality and mobility. The gate oxide integrity (GOI) of gate stacks below 1 nm EOT is determined by time-dependent dielectric breakdown (TDDB) measurements on FinFETs with HfO 2 /TiN gate stacks. A successful EOT scaling has always to consider the oxide quality and resulting reliability. Degraded oxide quality leads to mobility degradation and earlier soft-breakdown, i.e. leakage current increase.

Improvement in negative bias illumination stress stability of In-Ga-Zn-O thin film transistors using HfO2 gate insulators by controlling atomic-layer-deposition conditions

Science.gov (United States)

Na, So-Yeong; Kim, Yeo-Myeong; Yoon, Da-Jeong; Yoon, Sung-Min

2017-12-01

The effects of atomic layer deposition (ALD) conditions for the HfO2 gate insulators (GI) on the device characteristics of the InGaZnO (IGZO) thin film transistors (TFTs) were investigated when the ALD temperature and Hf precursor purge time were varied to 200, 225, and 250 °C, and 15 and 30 s, respectively. The HfO2 thin films showed low leakage current density of 10-8 A cm-2, high dielectric constant of over 20, and smooth surface roughness at all ALD conditions. The IGZO TFTs using the HfO2 GIs showed good device characteristics such as a saturation mobility as high as 11 cm2 V-1 s-1, a subthreshold swing as low as 0.10 V/dec, and all the devices could be operated at a gate voltage as low as  ±3 V. While there were no marked differences in transfer characteristics and PBS stabilities among the fabricated devices, the NBIS instabilities could be improved by increasing the ALD temperature for the formation of HfO2 GIs by reducing the oxygen vacancies within the IGZO channel.

Atomic scale engineering of HfO2-based dielectrics for future DRAM applications

International Nuclear Information System (INIS)

Dudek, Piotr

2011-01-01

Modern dielectrics in combination with appropriate metal electrodes have a great potential to solve many difficulties associated with continuing miniaturization process in the microelectronic industry. One significant branch of microelectronics incorporates dynamic random access memory (DRAM) market. The DRAM devices scaled for over 35 years starting from 4 kb density to several Gb nowadays. The scaling process led to the dielectric material thickness reduction, resulting in higher leakage current density, and as a consequence higher power consumption. As a possible solution for this problem, alternative dielectric materials with improved electrical and material science parameters were intensively studied by many research groups. The higher dielectric constant allows the use of physically thicker layers with high capacitance but strongly reduced leakage current density. This work focused on deposition and characterization of thin insulating layers. The material engineering process was based on Si cleanroom compatible HfO 2 thin films deposited on TiN metal electrodes. A combined materials science and dielectric characterization study showed that Ba-added HfO 2 (BaHfO 3 ) films and Ti-added BaHfO 3 (BaHf 0.5 Ti 0.5 O 3 ) layers are promising candidates for future generation of state-of-the-art DRAMs. In especial a strong increase of the dielectric permittivity k was achieved for thin films of cubic BaHfO 3 (k∝38) and BaHf 0.5 Ti 0.5 O 3 (k∝90) with respect to monoclinic HfO 2 (k∝19). Meanwhile the CET values scaled down to 1 nm for BaHfO 3 and ∝0.8 nm for BaHf 0.5 Ti 0.5 O 3 with respect to HfO 2 (CET=1.5 nm). The Hf 4+ ions substitution in BaHfO 3 by Ti 4+ ions led to a significant decrease of thermal budget from 900 C for BaHfO 3 to 700 C for BaHf 0.5 Ti 0.5 O 3 . Future studies need to focus on the use of appropriate metal electrodes (high work function) and on film deposition process (homogeneity) for better current leakage control. (orig.)

PAC study in the HfO2-SiO2 system

International Nuclear Information System (INIS)

Chain, C.Y.; Damonte, L.C.; Ferrari, S.; Munoz, E.; Torres, C. Rodriguez; Pasquevich, A.F.

2010-01-01

A high-k HfO 2 /SiO 2 gate stack is taking the place of SiO 2 as a gate dielectric in field effect transistors. This fact makes the study of the solid-state reaction between these oxides very important. Nanostructure characterization of a high-energy ball milled and post-annealed equimolar HfO 2 and amorphous SiO 2 powder mixture has been carried out by perturbed angular correlations (PAC) technique. The study was complemented with X-ray diffraction and positron annihilation lifetime spectroscopy (PALS). The experimental results revealed that the ball milling of equimolar mixtures increases the defects concentration in hafnium oxide. No solid-state reaction occurred even after 8 h of milling. The formation of HfSiO 4 (hafnon) was observed in the milled blends annealed at high temperatures.The PAC results of the milled samples are compared with those obtained for pure m-ZrO 2 subjected to high-energy ball milling and with reported microstructure data for the system ZrO 2 -SiO 2 .

Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

KAUST Repository

Salas-Villasenor, A. L.; Mejia, I.; Hovarth, J.; Alshareef, Husam N.; Cha, D. K.; Ramirez-Bon, R.; Gnade, B. E.; Quevedo-Lopez, M. A.

2010-01-01

Cadmium sulfide thin film transistors were demonstrated as the n-type device for use in flexible electronics. CdS thin films were deposited by chemical bath deposition (70° C) on either 100 nm HfO2 or SiO2 as the gate dielectrics. Common gate transistors with channel lengths of 40-100 μm were fabricated with source and drain aluminum top contacts defined using a shadow mask process. No thermal annealing was performed throughout the device process. X-ray diffraction results clearly show the hexagonal crystalline phase of CdS. The electrical performance of HfO 2 /CdS -based thin film transistors shows a field effect mobility and threshold voltage of 25 cm2 V-1 s-1 and 2 V, respectively. Improvement in carrier mobility is associated with better nucleation and growth of CdS films deposited on HfO2. © 2010 The Electrochemical Society.

Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

KAUST Repository

Salas-Villasenor, A. L.

2010-06-29

Cadmium sulfide thin film transistors were demonstrated as the n-type device for use in flexible electronics. CdS thin films were deposited by chemical bath deposition (70° C) on either 100 nm HfO2 or SiO2 as the gate dielectrics. Common gate transistors with channel lengths of 40-100 μm were fabricated with source and drain aluminum top contacts defined using a shadow mask process. No thermal annealing was performed throughout the device process. X-ray diffraction results clearly show the hexagonal crystalline phase of CdS. The electrical performance of HfO 2 /CdS -based thin film transistors shows a field effect mobility and threshold voltage of 25 cm2 V-1 s-1 and 2 V, respectively. Improvement in carrier mobility is associated with better nucleation and growth of CdS films deposited on HfO2. © 2010 The Electrochemical Society.

Effect of Dielectric Interface on the Performance of MoS2 Transistors.

Science.gov (United States)

Li, Xuefei; Xiong, Xiong; Li, Tiaoyang; Li, Sichao; Zhang, Zhenfeng; Wu, Yanqing

2017-12-27

Because of their wide bandgap and ultrathin body properties, two-dimensional materials are currently being pursued for next-generation electronic and optoelectronic applications. Although there have been increasing numbers of studies on improving the performance of MoS 2 field-effect transistors (FETs) using various methods, the dielectric interface, which plays a decisive role in determining the mobility, interface traps, and thermal transport of MoS 2 FETs, has not been well explored and understood. In this article, we present a comprehensive experimental study on the effect of high-k dielectrics on the performance of few-layer MoS 2 FETs from 300 to 4.3 K. Results show that Al 2 O 3 /HfO 2 could boost the mobility and drain current. Meanwhile, MoS 2 transistors with Al 2 O 3 /HfO 2 demonstrate a 2× reduction in oxide trap density compared to that of the devices with the conventional SiO 2 substrate. Also, we observe a negative differential resistance effect on the device with 1 μm-channel length when using conventional SiO 2 as the gate dielectric due to self-heating, and this is effectively eliminated by using the Al 2 O 3 /HfO 2 gate dielectric. This dielectric engineering provides a highly viable route to realizing high-performance transition metal dichalcogenide-based FETs.

Electrical characterization of ALD HfO2 high-k dielectrics on ( 2 ¯ 01) β-Ga2O3

Science.gov (United States)

Shahin, David I.; Tadjer, Marko J.; Wheeler, Virginia D.; Koehler, Andrew D.; Anderson, Travis J.; Eddy, Charles R.; Christou, Aris

2018-01-01

The electrical quality of HfO2 dielectrics grown by thermal atomic layer deposition at 175 °C on n-type ( 2 ¯ 01) β-Ga2O3 has been studied through capacitance- and current-voltage measurements on metal-oxide-semiconductor capacitors. These capacitors exhibited excellent electrical characteristics, including dual-sweep capacitance-voltage curves with low hysteresis and stretch-out and a frequency-stable dielectric constant of k˜14 when measured between 10 kHz and 1 MHz. The C-V curves exhibited a uniform and repeatable +1.05 V shift relative to the ideal case when swept from 3.5 to -5 V, yielding positively measured flatband (+2.15 V) and threshold (+1.05 V) voltages that may be useful for normally off n-channel Ga2O3 devices. Using the Terman method, an average interface trap density of 1.3 × 1011 cm-2.eV-1 was obtained between 0.2 and 0.6 eV below the conduction band edge. The forward bias current-voltage characteristic was successfully fitted to the Fowler-Nordheim tunneling model at a field strength of 5 MV/cm, allowing an extraction of a 1.3 eV conduction band offset between HfO2 and Ga2O3, which matches the value previously determined from x-ray photoelectron spectroscopy. However, a temperature dependence in the leakage current was observed. These results suggest that HfO2 is an appealing dielectric for Ga2O3 device applications.

Memory Effect of Metal-Oxide-Silicon Capacitors with Self-Assembly Double-Layer Au Nanocrystals Embedded in Atomic-Layer-Deposited HfO2 Dielectric

International Nuclear Information System (INIS)

Yue, Huang; Hong-Yan, Gou; Qing-Qing, Sun; Shi-Jin, Ding; Wei, Zhang; Shi-Li, Zhang

2009-01-01

We report the chemical self-assembly growth of Au nanocrystals on atomic-layer-deposited HfO 2 films aminosilanized by (3-Aminopropyl)-trimethoxysilane aforehand for memory applications. The resulting Au nanocrystals show a density of about 4 × 10 11 cm −2 and a diameter range of 5–8nm. The metal-oxide-silicon capacitor with double-layer Au nanocrystals embedded in HfO 2 dielectric exhibits a large C – V hysteresis window of 11.9V for ±11 V gate voltage sweeps at 1 MHz, a flat-band voltage shift of 1.5 V after the electrical stress under 7 V for 1 ms, a leakage current density of 2.9 × 10 −8 A/cm −2 at 9 V and room temperature. Compared to single-layer Au nanocrystals, the double-layer Au nanocrystals increase the hysteresis window significantly, and the underlying mechanism is thus discussed

Band Offsets and Interfacial Properties of HfAlO Gate Dielectric Grown on InP by Atomic Layer Deposition.

Science.gov (United States)

Yang, Lifeng; Wang, Tao; Zou, Ying; Lu, Hong-Liang

2017-12-01

X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy have been used to determine interfacial properties of HfO 2 and HfAlO gate dielectrics grown on InP by atomic layer deposition. An undesirable interfacial InP x O y layer is easily formed at the HfO 2 /InP interface, which can severely degrade the electrical performance. However, an abrupt interface can be achieved when the growth of the HfAlO dielectric on InP starts with an ultrathin Al 2 O 3 layer. The valence and conduction band offsets for HfAlO/InP heterojunctions have been determined to be 1.87 ± 0.1 and 2.83 ± 0.1 eV, respectively. These advantages make HfAlO a potential dielectric for InP MOSFETs.

Growth Related Carrier Mobility Enhancement of Pentacene Thin-Film Transistors with High-k Oxide Gate Dielectric

International Nuclear Information System (INIS)

Ai-Fang, Yu; Qiong, Qi; Peng, Jiang; Chao, Jiang

2009-01-01

Carrier mobility enhancement from 0.09 to 0.59 cm 2 /Vs is achieved for pentacene-based thin-film transistors (TFTs) by modifying the HfO 2 gate dielectric with a polystyrene (PS) thin film. The improvement of the transistor's performance is found to be strongly related to the initial film morphologies of pentacene on the dielectrics. In contrast to the three-dimensional island-like growth mode on the HfO 2 surface, the Stranski-Krastanov growth mode on the smooth and nonpolar PS/HfO 2 surface is believed to be the origin of the excellent carrier mobility of the TFTs. A large well-connected first monolayer with fewer boundaries is formed via the Stranski–Krastanov growth mode, which facilitates a charge transport parallel to the substrate and promotes higher carrier mobility. (cross-disciplinary physics and related areas of science and technology)

Interfacial, Electrical, and Band Alignment Characteristics of HfO2/Ge Stacks with In Situ-Formed SiO2 Interlayer by Plasma-Enhanced Atomic Layer Deposition

Science.gov (United States)

Cao, Yan-Qiang; Wu, Bing; Wu, Di; Li, Ai-Dong

2017-05-01

In situ-formed SiO2 was introduced into HfO2 gate dielectrics on Ge substrate as interlayer by plasma-enhanced atomic layer deposition (PEALD). The interfacial, electrical, and band alignment characteristics of the HfO2/SiO2 high-k gate dielectric stacks on Ge have been well investigated. It has been demonstrated that Si-O-Ge interlayer is formed on Ge surface during the in situ PEALD SiO2 deposition process. This interlayer shows fantastic thermal stability during annealing without obvious Hf-silicates formation. In addition, it can also suppress the GeO2 degradation. The electrical measurements show that capacitance equivalent thickness of 1.53 nm and a leakage current density of 2.1 × 10-3 A/cm2 at gate bias of Vfb + 1 V was obtained for the annealed sample. The conduction (valence) band offsets at the HfO2/SiO2/Ge interface with and without PDA are found to be 2.24 (2.69) and 2.48 (2.45) eV, respectively. These results indicate that in situ PEALD SiO2 may be a promising interfacial control layer for the realization of high-quality Ge-based transistor devices. Moreover, it can be demonstrated that PEALD is a much more powerful technology for ultrathin interfacial control layer deposition than MOCVD.

Nanopore fabricated in pyramidal HfO2 film by dielectric breakdown method

Science.gov (United States)

Wang, Yifan; Chen, Qi; Deng, Tao; Liu, Zewen

2017-10-01

The dielectric breakdown method provides an innovative solution to fabricate solid-state nanopores on insulating films. A nanopore generation event via this method is considered to be caused by random charged traps (i.e., structural defects) and high electric fields in the membrane. Thus, the position and number of nanopores on planar films prepared by the dielectric breakdown method is hard to control. In this paper, we propose to fabricate nanopores on pyramidal HfO2 films (10-nm and 15-nm-thick) to improve the ability to control the location and number during the fabrication process. Since the electric field intensity gets enhanced at the corners of the pyramid-shaped film, the probability of nanopore occurrence at vertex and edge areas increases. This priority of appearance provides us chance to control the location and number of nanopores by monitoring a sudden irreversible discrete increase in current. The experimental results showed that the probability of nanopore occurrence decreases in an order from the vertex area, the edge area to the side face area. The sizes of nanopores ranging from 30 nm to 10 nm were obtained. Nanopores fabricated on the pyramid-shaped HfO2 film also showed an obvious ion current rectification characteristic, which might improve the nanopore performance as a biomolecule sequencing platform.

Influence of Optimization of Process Parameters on Threshold Voltage for Development of HfO2/TiSi2 18 nm PMOS

Directory of Open Access Journals (Sweden)

Atan N.

2016-01-01

Full Text Available Manufacturing a 18-nm transistor requires a variety of parameters, materials, temperatures, and methods. In this research, HfO2 was used as the gate dielectric ad TiO2 was used as the gate material. The transistor HfO2/TiSi2 18-nm PMOS was invented using SILVACO TCAD. Ion implantation was adopted in the fabrication process for the method’s practicality and ability to be used to suppress short channel effects. The study involved ion implantation methods: compensation implantation, halo implantation energy, halo tilt, and source–drain implantation. Taguchi method is the best optimization process for a threshold voltage of HfO2/TiSi2 18-nm PMOS. In this case, the method adopted was Taguchi orthogonal array L9. The process parameters (ion implantations and noise factors were evaluated by examining the Taguchi’s signal-to-noise ratio (SNR and nominal-the-best for the threshold voltage (VTH. After optimization, the result showed that the VTH value of the 18-nm PMOS device was -0.291339.

Electrical Properties of Ultrathin Hf-Ti-O Higher k Gate Dielectric Films and Their Application in ETSOI MOSFET.

Science.gov (United States)

Xiong, Yuhua; Chen, Xiaoqiang; Wei, Feng; Du, Jun; Zhao, Hongbin; Tang, Zhaoyun; Tang, Bo; Wang, Wenwu; Yan, Jiang

2016-12-01

Ultrathin Hf-Ti-O higher k gate dielectric films (~2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) ~9.4%, low equivalent gate oxide thickness (EOT) of ~0.69 nm and acceptable gate leakage current density of 0.61 A/cm 2 @ (V fb  - 1)V could be obtained. The conduction mechanism through the gate dielectric is dominated by the F-N tunneling in the gate voltage range of -0.5 to -2 V. Under the same physical thickness and process flow, lower EOT and higher I on /I off ratio could be obtained while using Hf-Ti-O as gate dielectric compared with HfO 2 . With Hf-Ti-O as gate dielectric, two ETSOI PMOSFETs with gate width/gate length (W/L) of 0.5 μm/25 nm and 3 μm/40 nm show good performances such as high I on , I on /I off ratio in the magnitude of 10 5 , and peak transconductance, as well as suitable threshold voltage (-0.3~-0.2 V). Particularly, ETSOI PMOSFETs show superior short-channel control capacity with DIBL <82 mV/V and subthreshold swing <70 mV/decade.

Insights into thermal diffusion of germanium and oxygen atoms in HfO2/GeO2/Ge gate stacks and their suppressed reaction with atomically thin AlOx interlayers

International Nuclear Information System (INIS)

Ogawa, Shingo; Asahara, Ryohei; Minoura, Yuya; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji; Sako, Hideki; Kawasaki, Naohiko; Yamada, Ichiko; Miyamoto, Takashi

2015-01-01

The thermal diffusion of germanium and oxygen atoms in HfO 2 /GeO 2 /Ge gate stacks was comprehensively evaluated by x-ray photoelectron spectroscopy and secondary ion mass spectrometry combined with an isotopic labeling technique. It was found that 18 O-tracers composing the GeO 2 underlayers diffuse within the HfO 2 overlayers based on Fick's law with the low activation energy of about 0.5 eV. Although out-diffusion of the germanium atoms through HfO 2 also proceeded at the low temperatures of around 200 °C, the diffusing germanium atoms preferentially segregated on the HfO 2 surfaces, and the reaction was further enhanced at high temperatures with the assistance of GeO desorption. A technique to insert atomically thin AlO x interlayers between the HfO 2 and GeO 2 layers was proven to effectively suppress both of these independent germanium and oxygen intermixing reactions in the gate stacks

Analyses of desorbed H2O with temperature programmed desorption technique in sol-gel derived HfO2 thin films

International Nuclear Information System (INIS)

Shimizu, H.; Nemoto, D.; Ikeda, M.; Nishide, T.

2009-01-01

Hafnium oxide (HfO 2 ) is a promising material for the gate insulator in highly miniaturized silicon (Si) ultra-large-scale-integration (ULSI) devices (32 nm and beyond). In the field chemistry, a sol-gel processing has been used to fabricate HfO 2 thin film with the advantages of low cost, relative simplicity, and easy control of the composition of the layers formed. Temperature-programmed desorption (TPD) has been used not only for analyzing adsorbed gases on the surfaces of bulk sol-gel-derived HfO 2 of sol-gel-derived HfO 2 thin film fired at 350, 450, 550 and 700 deg C in sol-gel derived HfO 2 films in air is investigated using TPD, and also the material characterization of HfO 2 thin films is evaluated by X-ray diffraction (XRD) method. The dielectric constant of the films was also estimated using the capacitance-voltage (C-V) method. TPD is essentially a method of analyzing desorped gases from samples heated by infra-red light as a function of temperature under vacuum conditions using a detector of quadruple mass spectroscopy (QMS). Sol-gel-derived HfO 2 films were fabricated on 76-mm-diameter Si(100) wafers as follows. Hafnia sol solutions were prepared by dissolving HfCl 4 in NH 4 OH solution, followed by the of HCOOH. (author)

Thermal response of Ru electrodes in contact with SiO2 and Hf-based high-k gate dielectrics

International Nuclear Information System (INIS)

Wen, H.-C.; Lysaght, P.; Alshareef, H.N.; Huffman, C.; Harris, H.R.; Choi, K.; Senzaki, Y.; Luan, H.; Majhi, P.; Lee, B.H.; Campin, M. J.; Foran, B.; Lian, G.D.; Kwong, D.-L.

2005-01-01

A systematic experimental evaluation of the thermal stability of Ru metal gate electrodes in direct contact with SiO 2 and Hf-based dielectric layers was performed and correlated with electrical device measurements. The distinctly different interfacial reactions in the Ru/SiO 2 , Ru/HfO 2 , and Ru/HfSiO x film systems were observed through cross-sectional high-resolution transmission electron microscopy, high angle annular dark field scanning transmission electron microscopy with electron-energy-loss spectra, and energy dispersive x-ray spectra analysis. Ru interacted with SiO 2 , but remained stable on HfO 2 at 1000 deg. C. The onset of Ru/SiO 2 interfacial interactions is identified via silicon substrate pitting possibly from Ru diffusion into the dielectric in samples exposed to a 900 deg. C/10-s anneal. The dependence of capacitor device degradation with decreasing SiO 2 thickness suggests Ru diffuses through SiO 2 , followed by an abrupt, rapid, nonuniform interaction of ruthenium silicide as Ru contacts the Si substrate. Local interdiffusion detected on Ru/HfSiO x samples may be due to phase separation of HfSiO x into HfO 2 grains within a SiO 2 matrix, suggesting that SiO 2 provides a diffusion pathway for Ru. Detailed evidence consistent with a dual reaction mechanism for the Ru/SiO 2 system at 1000 deg. C is presented

Stable tetragonal phase and magnetic properties of Fe-doped HfO2 nanoparticles

Science.gov (United States)

Sales, T. S. N.; Cavalcante, F. H. M.; Bosch-Santos, B.; Pereira, L. F. D.; Cabrera-Pasca, G. A.; Freitas, R. S.; Saxena, R. N.; Carbonari, A. W.

2017-05-01

In this paper, the effect in structural and magnetic properties of iron doping with concentration of 20% in hafnium dioxide (HfO2) nanoparticles is investigated. HfO2 is a wide band gap oxide with great potential to be used as high-permittivity gate dielectrics, which can be improved by doping. Nanoparticle samples were prepared by sol-gel chemical method and had their structure, morphology, and magnetic properties, respectively, investigated by X-ray diffraction (XRD), transmission electron microscopy (TEM) and scanning electron microscopy (SEM) with electron back scattering diffraction (EBSD), and magnetization measurements. TEM and SEM results show size distribution of particles in the range from 30 nm to 40 nm with small dispersion. Magnetization measurements show the blocking temperature at around 90 K with a strong paramagnetic contribution. XRD results show a major tetragonal phase (94%).

Stable tetragonal phase and magnetic properties of Fe-doped HfO2 nanoparticles

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T. S. N. Sales

2017-05-01

Full Text Available In this paper, the effect in structural and magnetic properties of iron doping with concentration of 20% in hafnium dioxide (HfO2 nanoparticles is investigated. HfO2 is a wide band gap oxide with great potential to be used as high-permittivity gate dielectrics, which can be improved by doping. Nanoparticle samples were prepared by sol-gel chemical method and had their structure, morphology, and magnetic properties, respectively, investigated by X-ray diffraction (XRD, transmission electron microscopy (TEM and scanning electron microscopy (SEM with electron back scattering diffraction (EBSD, and magnetization measurements. TEM and SEM results show size distribution of particles in the range from 30 nm to 40 nm with small dispersion. Magnetization measurements show the blocking temperature at around 90 K with a strong paramagnetic contribution. XRD results show a major tetragonal phase (94%.

Investigation of 6T SRAM memory circuit using high-k dielectrics based nano scale junctionless transistor

Science.gov (United States)

Charles Pravin, J.; Nirmal, D.; Prajoon, P.; Mohan Kumar, N.; Ajayan, J.

2017-04-01

In this paper the Dual Metal Surround Gate Junctionless Transistor (DMSGJLT) has been implemented with various high-k dielectric. The leakage current in the device is analysed in detail by obtaining the band structure for different high-k dielectric material. It is noticed that with increasing dielectric constant the device provides more resistance for the direct tunnelling of electron in off state. The gate oxide capacitance also shows 0.1 μF improvement with Hafnium Oxide (HfO2) than Silicon Oxide (SiO2). This paved the way for a better memory application when high-k dielectric is used. The Six Transistor (6T) Static Random Access Memory (SRAM) circuit implemented shows 41.4% improvement in read noise margin for HfO2 than SiO2. It also shows 37.49% improvement in write noise margin and 30.16% improvement in hold noise margin for HfO2 than SiO2.

Optimization of pH sensing using silicon nanowire field effect transistors with HfO2 as the sensing surface

International Nuclear Information System (INIS)

Zafar, Sufi; D'Emic, Christopher; Afzali, Ali; Fletcher, Benjamin; Zhu, Y; Ning, Tak

2011-01-01

Silicon nanowire field effect transistor sensors with SiO 2 /HfO 2 as the gate dielectric sensing surface are fabricated using a top down approach. These sensors are optimized for pH sensing with two key characteristics. First, the pH sensitivity is shown to be independent of buffer concentration. Second, the observed pH sensitivity is enhanced and is equal to the Nernst maximum sensitivity limit of 59 mV/pH with a corresponding subthreshold drain current change of ∼ 650%/pH. These two enhanced pH sensing characteristics are attributed to the use of HfO 2 as the sensing surface and an optimized fabrication process compatible with silicon processing technology.

Optimization of pH sensing using silicon nanowire field effect transistors with HfO2 as the sensing surface.

Science.gov (United States)

Zafar, Sufi; D'Emic, Christopher; Afzali, Ali; Fletcher, Benjamin; Zhu, Y; Ning, Tak

2011-10-07

Silicon nanowire field effect transistor sensors with SiO(2)/HfO(2) as the gate dielectric sensing surface are fabricated using a top down approach. These sensors are optimized for pH sensing with two key characteristics. First, the pH sensitivity is shown to be independent of buffer concentration. Second, the observed pH sensitivity is enhanced and is equal to the Nernst maximum sensitivity limit of 59 mV/pH with a corresponding subthreshold drain current change of ∼ 650%/pH. These two enhanced pH sensing characteristics are attributed to the use of HfO(2) as the sensing surface and an optimized fabrication process compatible with silicon processing technology.

Interfacial microstructure of NiSi x/HfO2/SiO x/Si gate stacks

International Nuclear Information System (INIS)

Gribelyuk, M.A.; Cabral, C.; Gusev, E.P.; Narayanan, V.

2007-01-01

Integration of NiSi x based fully silicided metal gates with HfO 2 high-k gate dielectrics offers promise for further scaling of complementary metal-oxide- semiconductor devices. A combination of high resolution transmission electron microscopy and small probe electron energy loss spectroscopy (EELS) and energy dispersive X-ray analysis has been applied to study interfacial reactions in the undoped gate stack. NiSi was found to be polycrystalline with the grain size decreasing from top to bottom of NiSi x film. Ni content varies near the NiSi/HfO x interface whereby both Ni-rich and monosilicide phases were observed. Spatially non-uniform distribution of oxygen along NiSi x /HfO 2 interface was observed by dark field Scanning Transmission Electron Microscopy and EELS. Interfacial roughness of NiSi x /HfO x was found higher than that of poly-Si/HfO 2 , likely due to compositional non-uniformity of NiSi x . No intermixing between Hf, Ni and Si beyond interfacial roughness was observed

Improved linearity and reliability in GaN metal-oxide-semiconductor high-electron-mobility transistors using nanolaminate La2O3/SiO2 gate dielectric

Science.gov (United States)

Hsu, Ching-Hsiang; Shih, Wang-Cheng; Lin, Yueh-Chin; Hsu, Heng-Tung; Hsu, Hisang-Hua; Huang, Yu-Xiang; Lin, Tai-Wei; Wu, Chia-Hsun; Wu, Wen-Hao; Maa, Jer-Shen; Iwai, Hiroshi; Kakushima, Kuniyuki; Chang, Edward Yi

2016-04-01

Improved device performance to enable high-linearity power applications has been discussed in this study. We have compared the La2O3/SiO2 AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with other La2O3-based (La2O3/HfO2, La2O3/CeO2 and single La2O3) MOS-HEMTs. It was found that forming lanthanum silicate films can not only improve the dielectric quality but also can improve the device characteristics. The improved gate insulation, reliability, and linearity of the 8 nm La2O3/SiO2 MOS-HEMT were demonstrated.

The electrical performance and gate bias stability of an amorphous InGaZnO thin-film transistor with HfO2 high-k dielectrics

Science.gov (United States)

Wang, Ruo Zheng; Wu, Sheng Li; Li, Xin Yu; Zhang, Jin Tao

2017-07-01

In this study, we set out to fabricate an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with SiNx/HfO2/SiNx (SHS) sandwiched dielectrics. The J-V and C-V of this SHS film were extracted by the Au/p-Si/SHS/Ti structure. At room temperature the a-IGZO with SHS dielectrics showed the following electrical properties: a threshold voltage of 2.9 V, a subthreshold slope of 0.35 V/decade, an on/off current ratio of 3.5 × 107, and a mobility of 12.8 cm2 V-1 s-1. Finally, we tested the influence of gate bias stress on the TFT, and the result showed that the threshold voltage shifted to a positive voltage when applying a positive gate voltage to the TFT.

Tunnel field-effect transistor with two gated intrinsic regions

Directory of Open Access Journals (Sweden)

Y. Zhang

2014-07-01

Full Text Available In this paper, we propose and validate (using simulations a novel design of silicon tunnel field-effect transistor (TFET, based on a reverse-biased p+-p-n-n+ structure. 2D device simulation results show that our devices have significant improvements of switching performance compared with more conventional devices based on p-i-n structure. With independent gate voltages applied to two gated intrinsic regions, band-to-band tunneling (BTBT could take place at the p-n junction, and no abrupt degenerate doping profile is required. We developed single-side-gate (SSG structure and double-side-gate (DSG structure. SSG devices with HfO2 gate dielectric have a point subthreshold swing of 9.58 mV/decade, while DSG devices with polysilicon gate electrode material and HfO2 gate dielectric have a point subthreshold swing of 16.39 mV/decade. These DSG devices have ON-current of 0.255 μA/μm, while that is lower for SSG devices. Having two nano-scale independent gates will be quite challenging to realize with good uniformity across the wafer and the improved behavior of our TFET makes it a promising steep-slope switch candidate for further investigations.

Chemical reaction at the interface between pentacene and HfO2

International Nuclear Information System (INIS)

Kang, S.J.; Yi, Y.; Kim, K.H.; Yoo, C.Y.; Moewes, A.; Cho, M.H.; Denlinger, J.D.; Whang, C.N.; Chang, G.S.

2005-01-01

The electronic structure and the interface formation at the interface region between pentacene and HfO2 are investigated using x-ray photoelectron spectroscopy (XPS), ultraviolet photoelectron spectroscopy (UPS), and x-ray emission spectroscopy (XES). The measured C 1s XPS spectra of pentacene indicate that chemical bonding occurs at the interface between pentacene and HfO2. The carbon of pentacene reacts with oxygen belonging to HfO2 and band bending occurs at the interface due to a redistribution of charge. The determined interface dipole and band bending between pentacene and HfO2 are 0.04 and 0.1 eV, respectively. The highest occupied molecular orbital (HOMO) level is observed at 0.68 eV below the Fermi level. This chemical reaction allows us to grow a pentacene film with large grains onto HfO2. We conclude that high performance pentacene thin film transistors can be obtained by inserting an ultrathin HfO2 layer between pentacene and a gate insulator

Interface engineering and reliability characteristics of hafnium dioxide with poly silicon gate and dual metal (ruthenium-tantalum alloy, ruthenium) gate electrode for beyond 65 nm technology

Science.gov (United States)

Kim, Young-Hee

Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is

Analytical Modeling of Triple-Metal Hetero-Dielectric DG SON TFET

Science.gov (United States)

Mahajan, Aman; Dash, Dinesh Kumar; Banerjee, Pritha; Sarkar, Subir Kumar

2018-02-01

In this paper, a 2-D analytical model of triple-metal hetero-dielectric DG TFET is presented by combining the concepts of triple material gate engineering and hetero-dielectric engineering. Three metals with different work functions are used as both front- and back gate electrodes to modulate the barrier at source/channel and channel/drain interface. In addition to this, front gate dielectric consists of high-K HfO2 at source end and low-K SiO2 at drain side, whereas back gate dielectric is replaced by air to further improve the ON current of the device. Surface potential and electric field of the proposed device are formulated solving 2-D Poisson's equation and Young's approximation. Based on this electric field expression, tunneling current is obtained by using Kane's model. Several device parameters are varied to examine the behavior of the proposed device. The analytical model is validated with TCAD simulation results for proving the accuracy of our proposed model.

Top-gated chemical vapor deposition grown graphene transistors with current saturation.

Science.gov (United States)

Bai, Jingwei; Liao, Lei; Zhou, Hailong; Cheng, Rui; Liu, Lixin; Huang, Yu; Duan, Xiangfeng

2011-06-08

Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.

Atomic layer deposition grown composite dielectric oxides and ZnO for transparent electronic applications

International Nuclear Information System (INIS)

Gieraltowska, S.; Wachnicki, L.; Witkowski, B.S.; Godlewski, M.; Guziewicz, E.

2012-01-01

In this paper, we report on transparent transistor obtained using laminar structure of two high-k dielectric oxides (hafnium dioxide, HfO 2 and aluminum oxide, Al 2 O 3 ) and zinc oxide (ZnO) layer grown at low temperature (60 °C–100 °C) using Atomic Layer Deposition (ALD) technology. Our research was focused on the optimization of technological parameters for composite layers Al 2 O 3 /HfO 2 /Al 2 O 3 for thin film transistor structures with ZnO as a channel and a gate layer. We elaborate on the ALD growth of these oxides, finding that the 100 nm thick layers of HfO 2 and Al 2 O 3 exhibit fine surface flatness and required amorphous microstructure. Growth parameters are optimized for the monolayer growth mode and maximum smoothness required for gating.

A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

Science.gov (United States)

Wallace, Robert M.

2001-03-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Electronic States of High-k Oxides in Gate Stack Structures

Science.gov (United States)

Zhu, Chiyu

In this dissertation, in-situ X-ray and ultraviolet photoemission spectroscopy have been employed to study the interface chemistry and electronic structure of potential high-k gate stack materials. In these gate stack materials, HfO2 and La2O3 are selected as high-k dielectrics, VO2 and ZnO serve as potential channel layer materials. The gate stack structures have been prepared using a reactive electron beam system and a plasma enhanced atomic layer deposition system. Three interrelated issues represent the central themes of the research: 1) the interface band alignment, 2) candidate high-k materials, and 3) band bending, internal electric fields, and charge transfer. 1) The most highlighted issue is the band alignment of specific high-k structures. Band alignment relationships were deduced by analysis of XPS and UPS spectra for three different structures: a) HfO2/VO2/SiO2/Si, b) HfO 2-La2O3/ZnO/SiO2/Si, and c) HfO 2/VO2/ HfO2/SiO2/Si. The valence band offset of HfO2/VO2, ZnO/SiO2 and HfO 2/SiO2 are determined to be 3.4 +/- 0.1, 1.5 +/- 0.1, and 0.7 +/- 0.1 eV. The valence band offset between HfO2-La2O3 and ZnO was almost negligible. Two band alignment models, the electron affinity model and the charge neutrality level model, are discussed. The results show the charge neutrality model is preferred to describe these structures. 2) High-k candidate materials were studied through comparison of pure Hf oxide, pure La oxide, and alloyed Hf-La oxide films. An issue with the application of pure HfO2 is crystallization which may increase the leakage current in gate stack structures. An issue with the application of pure La2O3 is the presence of carbon contamination in the film. Our study shows that the alloyed Hf-La oxide films exhibit an amorphous structure along with reduced carbon contamination. 3) Band bending and internal electric fields in the gate stack structure were observed by XPS and UPS and indicate the charge transfer during the growth and process. The oxygen

Self-aligned top-gate InGaZnO thin film transistors using SiO{sub 2}/Al{sub 2}O{sub 3} stack gate dielectric

Energy Technology Data Exchange (ETDEWEB)

Chen, Rongsheng; Zhou, Wei; Zhang, Meng; Wong, Man; Kwok, Hoi Sing

2013-12-02

Self-aligned top-gate amorphous indium–gallium–zinc oxide (a-IGZO) thin film transistors (TFTs) utilizing SiO{sub 2}/Al{sub 2}O{sub 3} stack thin films as gate dielectric are developed in this paper. Due to high quality of the high-k Al{sub 2}O{sub 3} and good interface between active layer and gate dielectric, the resulting a-IGZO TFT exhibits good electrical performance including field-effect mobility of 9 cm{sup 2}/Vs, threshold voltage of 2.2 V, subthreshold swing of 0.2 V/decade, and on/off current ratio of 1 × 10{sup 7}. With scaling down of the channel length, good characteristics are also obtained with a small shift of the threshold voltage and no degradation of subthreshold swing. - Highlights: • Self-aligned top-gate indium–gallium–zinc oxide thin-film transistor is proposed. • SiO{sub 2}/Al{sub 2}O{sub 3} stack gate dielectric is proposed. • The source/drain areas are hydrogen-doped by CHF{sub 3} plasma. • The devices show good electrical performance and scaling down behavior.

Influence of gate recess on the electronic characteristics of β-Ga2O3 MOSFETs

Science.gov (United States)

Lv, Yuanjie; Mo, Jianghui; Song, Xubo; He, Zezhao; Wang, Yuangang; Tan, Xin; Zhou, Xingye; Gu, Guodong; Guo, Hongyu; Feng, Zhihong

2018-05-01

Gallium oxide (Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with gate recess depths of 110 nm and 220 nm, respectively. The gate recess was formed by dry plasma etching with Cr metal as the mask. The fabricated devices with a 25-nm HfO2 gate dielectric both showed a low off-state drain current of about 1.8 × 10-10 A/mm. The effects of recess depth on the electronic characteristics of Ga2O3 MOSFETs were investigated. Upon increasing the recess depth from 110 nm to 220 nm, the saturated drain current decreased from 20.7 mA/mm to 2.6 mA/mm, while the threshold voltage moved increased to +3 V. Moreover, the breakdown voltage increased from 122 V to 190 V. This is mainly because the inverted-trapezoidal gate played the role of a gate-field plate, which suppressed the peak electric field close to the gate.

Simulation of dual-gate SOI MOSFET with different dielectric layers

Science.gov (United States)

Yadav, Jyoti; Chaudhary, R.; Mukhiya, R.; Sharma, R.; Khanna, V. K.

2016-04-01

The paper presents the process design and simulation of silicon-on-insulator (SOI)-based dual-gate metal oxide field-effect transistor (DG-MOSFET) stacked with different dielectric layers on the top of gate oxide. A detailed 2D process simulation of SOI-MOSFETs and its electrical characterization has been done using SILVACO® TCAD tool. A variation in transconductance was observed with different dielectric layers, AlN-gate MOSFET having the highest tranconductance value as compared to other three dielectric layers (SiO2, Si3N4 and Al2O3).

Chemical states and electronic structure of a HfO(-2)/Ge(001) interface

International Nuclear Information System (INIS)

Seo, Kang-ill; McIntyre, Paul C.; Stanford U., Materials Sci. Dept.; Sun, Shiyu; Lee, Dong-Ick; Pianetta, Piero; SLAC, SSRL; Saraswat, Krishna C.; Stanford U., Elect. Eng. Dept.

2005-01-01

We report the chemical bonding structure and valence band alignment at the HfO 2 /Ge (001) interface by systematically probing various core level spectra as well as valence band spectra using soft x-rays at the Stanford Synchrotron Radiation Laboratory. We investigated the chemical bonding changes as a function of depth through the dielectric stack by taking a series of synchrotron photoemission spectra as we etched through the HfO 2 film using a dilute HF-solution. We found that a very non-stoichiometric GeO x layer exists at the HfO 2 /Ge interface. The valence band spectra near the Fermi level in each different film structure were carefully analyzed, and as a result, the valence band offset between Ge and GeO x was determined to be ΔE v (Ge-GeO x ) = 2.2 ± 0.15 eV, and that between Ge and HfO 2 , ΔE v (Ge-HfO 2 ) = 2.7 ± 0.15 eV

Al2O3 nanocrystals embedded in amorphous Lu2O3 high-k gate dielectric for floating gate memory application

International Nuclear Information System (INIS)

Yuan, C L; Chan, M Y; Lee, P S; Darmawan, P; Setiawan, Y

2007-01-01

The integration of nanoparticles has high potential in technological applications and opens up possibilities of the development of new devices. Compared to the conventional floating gate memory, a structure containing nanocrystals embedded in dielectrics shows high potential to produce a memory with high endurance, low operating voltage, fast write-erase speeds and better immunity to soft errors [S. Tiwari, F. Rana, H. Hanafi et al. 1996 Appl.Phys. Lett. 68, 1377]. A significant improvement on data retention [J. J. Lee, X. Wang et al. 2003 Proceedings of the VLSI Technol. Symposium, p33] can be observed when discrete nanodots are used instead of continuous floating gate as charge storage nodes because local defect related leakage can be reduced efficiently. Furthermore, using a high-k dielectric in place of the conventional SiO2 based dielectric, nanodots flash memory is able to achieve significantly improved programming efficiency and data retention [A. Thean and J. -P. Leburton, 2002 IEEE Potentials 21, 35; D. W. Kim, T. Kim and S. K. Banerjee, 2003 IEEE Trans. Electron Devices 50, 1823]. We have recently successfully developed a method to produce nanodots embedded in high-k gate dielectrics [C. L. Yuan, P. Darmawan, Y. Setiawan and P. S. Lee, 2006 Electrochemical and Solid-State Letters 9, F53; C. L. Yuan, P. Darmawan, Y. Setiawan and P. S. Lee, 2006 Europhys. Lett. 74, 177]. In this paper, we fabricated the memory structure of Al 2 O 3 nanocrystals embedded in amorphous Lu 2 O 3 high k dielectric using pulsed laser ablation. The mean size and density of the Al 2 O 3 nanocrystals are estimated to be about 5 nm and 7x1011 cm -2 , respectively. Good electrical performances in terms of large memory window and good data retention were observed. Our preparation method is simple, fast and economical

Ion/Ioff ratio enhancement and scalability of gate-all-around nanowire negative-capacitance FET with ferroelectric HfO2

Science.gov (United States)

Jang, Kyungmin; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2017-10-01

We have investigated the energy efficiency and scalability of ferroelectric HfO2 (FE:HfO2)-based negative-capacitance field-effect-transistor (NCFET) with gate-all-around (GAA) nanowire (NW) channel structure. Analytic simulation is conducted to characterize NW-NCFET by varying NW diameter and/or thickness of gate insulator as device structural parameters. Due to the negative-capacitance effect and GAA NW channel structure, NW-NCFET is found to have 5× higher Ion/Ioff ratio than classical NW-MOSFET and 2× higher than double-gate (DG) NCFET, which results in wider design window for high Ion/Ioff ratio. To analyze these obtained results from the viewpoint of the device scalability, we have considered constraints regarding very limited device structural spaces to fit by the gate insulator and NW channel for aggresively scaled gate length (Lg) and/or very tight NW pitch. NW-NCFET still has design point with very thinned gate insulator and/or narrowed NW. Therefore, FE:HfO2-based NW-NCFET is applicable to the aggressively scaled technology node of sub-10 nm Lg and to the very tight NW integration of sub-30 nm NW pitch for beyond 7 nm technology. From 2011 to 2014, he engaged in developing high-speed optical transceiver module as an alternative military service in Republic of Korea. His research interest includes the development of steep slope MOSFETs for high energy-efficient operation and ferroelectric HfO2-based semiconductor devices, and fabrication of nanostructured devices. He joined the IBM T.J. Watson Research Center, Yorktown Heights, NY, in 2010, where he worked on advanced CMOS technologies such as FinFET, nanowire FET, SiGe channel and III-V channel. He was also engaged in launching 14 nm SOI FinFET and RMG technology development. Since 2014, he has been an Associate Professor in Institute of Industrial Science, University of Tokyo, Tokyo, Japan, where he has been working on ultralow power transistor and memory technology. Dr. Kobayashi is a member of IEEE

Evolutionary search for new high-k dielectric materials: methodology and applications to hafnia-based oxides.

Science.gov (United States)

Zeng, Qingfeng; Oganov, Artem R; Lyakhov, Andriy O; Xie, Congwei; Zhang, Xiaodong; Zhang, Jin; Zhu, Qiang; Wei, Bingqing; Grigorenko, Ilya; Zhang, Litong; Cheng, Laifei

2014-02-01

High-k dielectric materials are important as gate oxides in microelectronics and as potential dielectrics for capacitors. In order to enable computational discovery of novel high-k dielectric materials, we propose a fitness model (energy storage density) that includes the dielectric constant, bandgap, and intrinsic breakdown field. This model, used as a fitness function in conjunction with first-principles calculations and the global optimization evolutionary algorithm USPEX, efficiently leads to practically important results. We found a number of high-fitness structures of SiO2 and HfO2, some of which correspond to known phases and some of which are new. The results allow us to propose characteristics (genes) common to high-fitness structures--these are the coordination polyhedra and their degree of distortion. Our variable-composition searches in the HfO2-SiO2 system uncovered several high-fitness states. This hybrid algorithm opens up a new avenue for discovering novel high-k dielectrics with both fixed and variable compositions, and will speed up the process of materials discovery.

Interfacial Cation-Defect Charge Dipoles in Stacked TiO2/Al2O3 Gate Dielectrics.

Science.gov (United States)

Zhang, Liangliang; Janotti, Anderson; Meng, Andrew C; Tang, Kechao; Van de Walle, Chris G; McIntyre, Paul C

2018-02-14

Layered atomic-layer-deposited and forming-gas-annealed TiO 2 /Al 2 O 3 dielectric stacks, with the Al 2 O 3 layer interposed between the TiO 2 and a p-type germanium substrate, are found to exhibit a significant interface charge dipole that causes a ∼-0.2 V shift of the flat-band voltage and suppresses the leakage current density for gate injection of electrons. These effects can be eliminated by the formation of a trilayer dielectric stack, consistent with the cancellation of one TiO 2 /Al 2 O 3 interface dipole by the addition of another dipole of opposite sign. Density functional theory calculations indicate that the observed interface-dependent properties of TiO 2 /Al 2 O 3 dielectric stacks are consistent in sign and magnitude with the predicted behavior of Al Ti and Ti Al point-defect dipoles produced by local intermixing of the Al 2 O 3 /TiO 2 layers across the interface. Evidence for such intermixing is found in both electrical and physical characterization of the gate stacks.

High-κ gate dielectrics: Current status and materials properties considerations

Science.gov (United States)

Wilk, G. D.; Wallace, R. M.; Anthony, J. M.

2001-05-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward successful integration into the expected processing conditions for future CMOS technologies, especially due to their tendency to form at interfaces with Si (e.g. silicates). These pseudobinary systems also thereby enable the use of other high-κ materials by serving as an interfacial high-κ layer. While work is ongoing, much research is still required, as it is clear that any material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Perpendicular magnetic anisotropy of CoFeB\\Ta bilayers on ALD HfO2

Directory of Open Access Journals (Sweden)

Bart F. Vermeulen

2017-05-01

Full Text Available Perpendicular magnetic anisotropy (PMA is an essential condition for CoFe thin films used in magnetic random access memories. Until recently, interfacial PMA was mainly known to occur in materials stacks with MgO\\CoFe(B interfaces or using an adjacent crystalline heavy metal film. Here, PMA is reported in a CoFeB\\Ta bilayer deposited on amorphous high-κ dielectric (relative permittivity κ=20 HfO2, grown by atomic layer deposition (ALD. PMA with interfacial anisotropy energy Ki up to 0.49 mJ/m2 appears after annealing the stacks between 200°C and 350°C, as shown with vibrating sample magnetometry. Transmission electron microscopy shows that the decrease of PMA starting from 350°C coincides with the onset of interdiffusion in the materials. High-κ dielectrics are potential enablers for giant voltage control of magnetic anisotropy (VCMA. The absence of VCMA in these experiments is ascribed to a 0.6 nm thick magnetic dead layer between HfO2 and CoFeB. The results show PMA can be easily obtained on ALD high-κ dielectrics.

Electrical and materials properties of ZrO2 gate dielectrics grown by atomic layer chemical vapor deposition

Science.gov (United States)

Perkins, Charles M.; Triplett, Baylor B.; McIntyre, Paul C.; Saraswat, Krishna C.; Haukka, Suvi; Tuominen, Marko

2001-04-01

Structural and electrical properties of gate stack structures containing ZrO2 dielectrics were investigated. The ZrO2 films were deposited by atomic layer chemical vapor deposition (ALCVD) after different substrate preparations. The structure, composition, and interfacial characteristics of these gate stacks were examined using cross-sectional transmission electron microscopy and x-ray photoelectron spectroscopy. The ZrO2 films were polycrystalline with either a cubic or tetragonal crystal structure. An amorphous interfacial layer with a moderate dielectric constant formed between the ZrO2 layer and the substrate during ALCVD growth on chemical oxide-terminated silicon. Gate stacks with a measured equivalent oxide thickness (EOT) of 1.3 nm showed leakage values of 10-5 A/cm2 at a bias of -1 V from flatband, which is significantly less than that seen with SiO2 dielectrics of similar EOT. A hysteresis of 8-10 mV was seen for ±2 V sweeps while a midgap interface state density (Dit) of ˜3×1011 states/cm eV was determined from comparisons of measured and ideal capacitance curves.

Effect of gate dielectrics on the performance of p-type Cu2O TFTs processed at room temperature

KAUST Repository

Al-Jawhari, Hala A.

2013-12-01

Single-phase Cu2O films with p-type semiconducting properties were successfully deposited by reactive DC magnetron sputtering at room temperature followed by post annealing process at 200°C. Subsequently, such films were used to fabricate bottom gate p-channel Cu2O thin film transistors (TFTs). The effect of using high-κ SrTiO3 (STO) as a gate dielectric on the Cu2O TFT performance was investigated. The results were then compared to our baseline process which uses a 220 nm aluminum titanium oxide (ATO) dielectric deposited on a glass substrate coated with a 200 nm indium tin oxide (ITO) gate electrode. We found that with a 150 nm thick STO, the Cu2O TFTs exhibited a p-type behavior with a field-effect mobility of 0.54 cm2.V-1.s-1, an on/off ratio of around 44, threshold voltage equaling -0.62 V and a sub threshold swing of 1.64 V/dec. These values were obtained at a low operating voltage of -2V. The advantages of using STO as a gate dielectric relative to ATO are discussed. © (2014) Trans Tech Publications, Switzerland.

Mechanisms and selectivity for etching of HfO2 and Si in BCl3 plasmas

International Nuclear Information System (INIS)

Wang Chunyu; Donnelly, Vincent M.

2008-01-01

The authors have investigated plasma etching of HfO 2 , a high dielectric constant material, and poly-Si in BCl 3 plasmas. Etching rates were measured as a function of substrate temperature (T s ) at several source powers. Activation energies range from 0.2 to 1.0 kcal/mol for HfO 2 and from 0.8 to 1.8 kcal/mol for Si, with little or no dependence on source power (20-200 W). These low activation energies suggest that product removal is limited by chemical sputtering of the chemisorbed Hf or Si-containing layer, with a higher T s only modestly increasing the chemical sputtering rate. The slightly lower activation energy for HfO 2 results in a small improvement in selectivity over Si at low temperature. The surface layers formed on HfO 2 and Si after etching in BCl 3 plasmas were also investigated by vacuum-transfer x-ray photoelectron spectroscopy. A thin boron-containing layer was observed on partially etched HfO 2 and on poly-Si after etching through HfO 2 films. For HfO 2 , a single B(1s) feature at 194 eV was ascribed to a heavily oxidized species with bonding similar to B 2 O 3 . B(1s) features were observed for poly-Si surfaces at 187.6 eV (B bound to Si), 189.8 eV, and 193 eV (both ascribed to BO x Cl y ). In the presence of a deliberately added 0.5% air, the B-containing layer on HfO 2 is largely unaffected, while that on Si converts to a thick layer with a single B(1s) peak at 194 eV and an approximate stoichiometry of B 3 O 4 Cl

Anomalous positive flatband voltage shifts in metal gate stacks containing rare-earth oxide capping layers

KAUST Repository

Caraveo-Frescas, J. A.

2012-03-09

It is shown that the well-known negative flatband voltage (VFB) shift, induced by rare-earth oxide capping in metal gate stacks, can be completely reversed in the absence of the silicon overlayer. Using TaN metal gates and Gd2O3-doped dielectric, we measure a ∼350 mV negative shift with the Si overlayer present and a ∼110 mV positive shift with the Si overlayer removed. This effect is correlated to a positive change in the average electrostatic potential at the TaN/dielectric interface which originates from an interfacial dipole. The dipole is created by the replacement of interfacial oxygen atoms in the HfO2 lattice with nitrogen atoms from TaN.

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

Science.gov (United States)

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J

2016-06-09

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

Total Ionizing Dose Effects of Si Vertical Diffused MOSFET with SiO2 and Si3N4/SiO2 Gate Dielectrics

Directory of Open Access Journals (Sweden)

Jiongjiong Mo

2017-01-01

Full Text Available The total ionizing dose irradiation effects are investigated in Si vertical diffused MOSFETs (VDMOSs with different gate dielectrics including single SiO2 layer and double Si3N4/SiO2 layer. Radiation-induced holes trapping is greater for single SiO2 layer than for double Si3N4/SiO2 layer. Dielectric oxidation temperature dependent TID effects are also studied. Holes trapping induced negative threshold voltage shift is smaller for SiO2 at lower oxidation temperature. Gate bias during irradiation leads to different VTH shift for different gate dielectrics. Single SiO2 layer shows the worst negative VTH at VG=0 V, while double Si3N4/SiO2 shows negative VTH shift at VG=-5 V, positive VTH shift at VG=10 V, and negligible VTH shift at VG=0 V.

Ambipolar transport in CVD grown MoSe2 monolayer using an ionic liquid gel gate dielectric

Directory of Open Access Journals (Sweden)

Deliris N. Ortiz

2018-03-01

Full Text Available CVD grown MoSe2 monolayers were electrically characterized at room temperature in a field effect transistor (FET configuration using an ionic liquid (IL as the gate dielectric. During the growth, instead of using MoO3 powder, ammonium heptamolybdate was used for better Mo control of the source and sodium cholate added for lager MoSe2 growth areas. In addition, a high specific capacitance (∼7 μF/cm2 IL was used as the gate dielectric to significantly reduce the operating voltage. The device exhibited ambipolar charge transport at low voltages with enhanced parameters during n- and p-FET operation. IL gating thins the Schottky barrier at the metal/semiconductor interface permitting efficient charge injection into the channel and reduces the effects of contact resistance on device performance. The large specific capacitance of the IL was also responsible for a much higher induced charge density compared to the standard SiO2 dielectric. The device was successfully tested as an inverter with a gain of ∼2. Using a common metal for contacts simplifies fabrication of this ambipolar device, and the possibility of radiative recombination of holes and electrons could further extend its use in low power optoelectronic applications.

Development of III-V p-MOSFETs with high-kappa gate stack for future CMOS applications

Science.gov (United States)

Nagaiah, Padmaja

As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, non-silicon materials and new device architectures are gradually being introduced to improve Si integrated circuit performance and continue transistor scaling. Recently, the replacement of SiO2 with a high-k material (HfO2) as gate dielectric has essentially removed one of the biggest advantages of Si as channel material. As a result, alternate high mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. III-V materials in particular have become of great interest as channel materials, owing to their superior electron transport properties. However, there are several critical challenges that need to be addressed before III-V based CMOS can replace Si CMOS technology. Some of these challenges include development of a high quality, thermally stable gate dielectric/III-V interface, and improvement in III-V p-channel hole mobility to complement the n-channel mobility, low source/drain resistance and integration onto Si substrate. In this thesis, we would be addressing the first two issues i.e. the development high performance III-V p-channels and obtaining high quality III-V/high-k interface. We start with using the device architecture of the already established InGaAs n-channels as a baseline to understand the effect of remote scattering from the high-k oxide and oxide/semiconductor interface on channel transport properties such as electron mobility and channel electron concentration. Temperature dependent Hall electron mobility measurements were performed to separate various scattering induced mobility limiting factors. Dependence of channel mobility on proximity of the channel to the oxide interface, oxide thickness, annealing conditions are discussed. The results from this work will be used in the design of the p-channel MOSFETs. Following this, InxGa1-xAs (x>0.53) is chosen as channel material for developing p

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors.

Science.gov (United States)

Chen, Fa-Hsyang; Her, Jim-Long; Shao, Yu-Hsuan; Matsuda, Yasuhiro H; Pan, Tung-Ming

2013-01-08

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric.

Poly(methyl methacrylate) as a self-assembled gate dielectric for graphene field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Sanne, A.; Movva, H. C. P.; Kang, S.; McClellan, C.; Corbet, C. M.; Banerjee, S. K. [Microelectronics Research Center, University of Texas, Austin, Texas 78758 (United States)

2014-02-24

We investigate poly(methyl methacrylate) (PMMA) as a low thermal budget organic gate dielectric for graphene field effect-transistors (GFETs) based on a simple process flow. We show that high temperature baking steps above the glass transition temperature (∼130 °C) can leave a self-assembled, thin PMMA film on graphene, where we get a gate dielectric almost for “free” without additional atomic layer deposition type steps. Electrical characterization of GFETs with PMMA as a gate dielectric yields a dielectric constant of k = 3.0. GFETs with thinner PMMA dielectrics have a lower dielectric constant due to decreased polarization arising from neutralization of dipoles and charged carriers as baking temperatures increase. The leakage through PMMA gate dielectric increases with decreasing dielectric thickness and increasing electric field. Unlike conventional high-k gate dielectrics, such low-k organic gate dielectrics are potentially attractive for devices such as the proposed Bilayer pseudoSpin Field-Effect Transistor or flexible high speed graphene electronics.

Ge interactions on HfO2 surfaces and kinetically driven patterning of Ge nanocrystals on HfO2

International Nuclear Information System (INIS)

Stanley, Scott K.; Joshi, Sachin V.; Banerjee, Sanjay K.; Ekerdt, John G.

2006-01-01

Germanium interactions are studied on HfO 2 surfaces, which are prepared through physical vapor deposition (PVD) and by atomic layer deposition. X-ray photoelectron spectroscopy and temperature-programed desorption are used to follow the reactions of germanium on HfO 2 . Germanium chemical vapor deposition at 870 K on HfO 2 produces a GeO x adhesion layer, followed by growth of semiconducting Ge 0 . PVD of 0.7 ML Ge (accomplished by thermally cracking GeH 4 over a hot filament) also produces an initial GeO x layer, which is stable up to 800 K. PVD above 2.0 ML deposits semiconducting Ge 0 . Temperature programed desorption experiments of ∼1.0 ML Ge from HfO 2 at 400-1100 K show GeH 4 desorption below 600 K and GeO desorption above 850 K. These results are compared to Ge on SiO 2 where GeO desorption is seen at 550 K. Exploiting the different reactivity of Ge on HfO 2 and SiO 2 allows a kinetically driven patterning scheme for high-density Ge nanoparticle growth on HfO 2 surfaces that is demonstrated

Direct deposition of aluminum oxide gate dielectric on graphene channel using nitrogen plasma treatment

International Nuclear Information System (INIS)

Lim, Taekyung; Kim, Dongchool; Ju, Sanghyun

2013-01-01

Deposition of high-quality dielectric on a graphene channel is an essential technology to overcome structural constraints for the development of nano-electronic devices. In this study, we investigated a method for directly depositing aluminum oxide (Al 2 O 3 ) on a graphene channel through nitrogen plasma treatment. The deposited Al 2 O 3 thin film on graphene demonstrated excellent dielectric properties with negligible charge trapping and de-trapping in the gate insulator. A top-gate-structural graphene transistor was fabricated using Al 2 O 3 as the gate dielectric with nitrogen plasma treatment on graphene channel region, and exhibited p-type transistor characteristics

SiO2/AlON stacked gate dielectrics for AlGaN/GaN MOS heterojunction field-effect transistors

Science.gov (United States)

Watanabe, Kenta; Terashima, Daiki; Nozaki, Mikito; Yamada, Takahiro; Nakazawa, Satoshi; Ishida, Masahiro; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

Stacked gate dielectrics consisting of wide bandgap SiO2 insulators and thin aluminum oxynitride (AlON) interlayers were systematically investigated in order to improve the performance and reliability of AlGaN/GaN metal–oxide–semiconductor (MOS) devices. A significantly reduced gate leakage current compared with that in a single AlON layer was achieved with these structures, while maintaining the superior thermal stability and electrical properties of the oxynitride/AlGaN interface. Consequently, distinct advantages in terms of the reliability of the gate dielectrics, such as an improved immunity against electron injection and an increased dielectric breakdown field, were demonstrated for AlGaN/GaN MOS capacitors with optimized stacked structures having a 3.3-nm-thick AlON interlayer.

Towards the accurate electronic structure descriptions of typical high-constant dielectrics

Science.gov (United States)

Jiang, Ting-Ting; Sun, Qing-Qing; Li, Ye; Guo, Jiao-Jiao; Zhou, Peng; Ding, Shi-Jin; Zhang, David Wei

2011-05-01

High-constant dielectrics have gained considerable attention due to their wide applications in advanced devices, such as gate oxides in metal-oxide-semiconductor devices and insulators in high-density metal-insulator-metal capacitors. However, the theoretical investigations of these materials cannot fulfil the requirement of experimental development, especially the requirement for the accurate description of band structures. We performed first-principles calculations based on the hybrid density functionals theory to investigate several typical high-k dielectrics such as Al2O3, HfO2, ZrSiO4, HfSiO4, La2O3 and ZrO2. The band structures of these materials are well described within the framework of hybrid density functionals theory. The band gaps of Al2O3, HfO2, ZrSiO4, HfSiO4, La2O3 and ZrO2are calculated to be 8.0 eV, 5.6 eV, 6.2 eV, 7.1 eV, 5.3 eV and 5.0 eV, respectively, which are very close to the experimental values and far more accurate than those obtained by the traditional generalized gradient approximation method.

Hysteresis behaviour of low-voltage organic field-effect transistors employing high dielectric constant polymer gate dielectrics

International Nuclear Information System (INIS)

Kim, Se Hyun; Yun, Won Min; Kwon, Oh-Kwan; Hong, Kipyo; Yang, Chanwoo; Park, Chan Eon; Choi, Woon-Seop

2010-01-01

Here, we report on the fabrication of low-voltage-operating pentacene-based organic field-effect transistors (OFETs) that utilize crosslinked cyanoethylated poly(vinyl alcohol) (CR-V) gate dielectrics. The crosslinked CR-V-based OFET could be operated successfully at low voltages (below 4 V), but abnormal behaviour during device operation, such as uncertainty in the field-effect mobility (μ) and hysteresis, was induced by the slow polarization of moieties embedded in the gate dielectric (e.g. polar functionalities, ionic impurities, water and solvent molecules). In an effort to improve the stability of OFET operation, we measured the dependence of μ and hysteresis on dielectric thickness, CR-V crosslinking conditions and sweep rate of the gate bias. The influence of the CR-V surface properties on μ, hysteresis, and the structural and morphological features of the pentacene layer grown on the gate dielectric was characterized and compared with the properties of pentacene grown on a polystyrene surface.

Energy-loss return gate via liquid dielectric polarization.

Science.gov (United States)

Kim, Taehun; Yong, Hyungseok; Kim, Banseok; Kim, Dongseob; Choi, Dukhyun; Park, Yong Tae; Lee, Sangmin

2018-04-12

There has been much research on renewable energy-harvesting techniques. However, owing to increasing energy demands, significant energy-related issues remain to be solved. Efforts aimed at reducing the amount of energy loss in electric/electronic systems are essential for reducing energy consumption and protecting the environment. Here, we design an energy-loss return gate system that reduces energy loss from electric/electronic systems by utilizing the polarization of liquid dielectrics. The use of a liquid dielectric material in the energy-loss return gate generates electrostatic potential energy while reducing the dielectric loss of the electric/electronic system. Hence, an energy-loss return gate can make breakthrough impacts possible by amplifying energy-harvesting efficiency, lowering the power consumption of electronics, and storing the returned energy. Our study indicates the potential for enhancing energy-harvesting technologies for electric/electronics systems, while increasing the widespread development of these systems.

Physical and electrical properties of bilayer CeO{sub 2}/TiO{sub 2} gate dielectric stack

Energy Technology Data Exchange (ETDEWEB)

Chong, M.M.V. [School of Materials Science and Engineering, Nanyang Technological University of Singapore, Block N 4.1Nanyang Avenue, Singapore 639798 (Singapore); GlobalFoundries Singapore Private Limited, 60 Woodlands Industrial Park D Street 2, Singapore 738406 (Singapore); Lee, P.S. [School of Materials Science and Engineering, Nanyang Technological University of Singapore, Block N 4.1Nanyang Avenue, Singapore 639798 (Singapore); Tok, A.I.Y., E-mail: MIYTOK@ntu.edu.sg [School of Materials Science and Engineering, Nanyang Technological University of Singapore, Block N 4.1Nanyang Avenue, Singapore 639798 (Singapore)

2016-08-15

Highlights: • A bilayer gate dielectric stack of CeO{sub 2}/TiO{sub 2} to study the dependency of film growth with varying annealing temperatures is proposed. • The study demonstrates CeO{sub 2}/TiO{sub 2} bilayer stack with comparable κ-value as that of HfO{sub 2} but with reduced leakage current density of 4 orders of magnitude. • Schottky emission is the dominant leakage conduction mechanism of annealed CeO{sub 2}/TiO{sub 2} stack due to thermionic effect of interface properties. - Abstract: This study demonstrates a bilayer gate oxide structure of cerium oxide deposited via pulsed laser deposition and titanium oxide using conventional atomic layer deposition. Samples were deposited on p-type Si (100) substrate and exhibit interesting physical and electrical properties such that 600 °C annealed CeO{sub 2}/TiO{sub 2} samples having κ-value of 18 whereas pure CeO{sub 2} deposited samples have dielectric constant of 17.1 with leakage current density of 8.94 × 10{sup −6} A/cm{sup 2} at 1 V applied voltage. The result shows promising usage of the synthesized rare earth oxides as gate dielectric where ideal κ-value and significant reduction of the leakage current by 5 orders of magnitude is achieved. Leakage current conduction mechanism for as-deposited sample is found to be dominated by Poole–Frenkel (PF) emission; the trap level is found to be at 1.29 eV whereas annealed samples (600 °C and 800 °C) exhibited Schottky emission with trap levels at 1.45 eV and 0.81 eV, respectively.

Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics

KAUST Repository

Alshareef, Husam N.

2010-11-19

Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.

Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics

KAUST Repository

Alshareef, Husam N.; Caraveo-Frescas, J. A.; Cha, D. K.

2010-01-01

Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.

Pulsed laser deposition of oxide gate dielectrics for pentacene organic field-effect transistors

International Nuclear Information System (INIS)

Yaginuma, S.; Yamaguchi, J.; Itaka, K.; Koinuma, H.

2005-01-01

We have fabricated Al 2 O 3 , LaAlO 3 (LAO), CaHfO 3 (CHO) and CaZrO 3 (CZO) thin films for the dielectric layers of field-effect transistors (FETs) by pulsed laser deposition (PLD). The films exhibited very smooth surfaces with root-mean-squares (rms) roughnesses of ∼1.3 A as evaluated by using atomic force microscopy (AFM). The breakdown electric fields of Al 2 O 3 , LAO, CHO and CZO films were 7, 6, 10 and 2 MV/cm, respectively. The magnitude of the leak current in each film was low enough to operate FET. We performed a comparative study of pentacene FET fabricated using these oxide dielectrics as gate insulators. High field-effect mobility of 1.4 cm 2 /V s and on/off current ratio of 10 7 were obtained in the pentacene FET using LAO gate insulating film. Use of the LAO films as gate dielectrics has been found to suppress the hysteresis of pentacene FET operations. The LAO films are relevant to the dielectric layer of organic FETs

Atomic layer deposition of HfO2 on graphene through controlled ion beam treatment

International Nuclear Information System (INIS)

Kim, Ki Seok; Oh, Il-Kwon; Jung, Hanearl; Kim, Hyungjun; Yeom, Geun Young; Kim, Kyong Nam

2016-01-01

The polymer residue generated during the graphene transfer process to the substrate tends to cause problems (e.g., a decrease in electron mobility, unwanted doping, and non-uniform deposition of the dielectric material). In this study, by using a controllable low-energy Ar + ion beam, we cleaned the polymer residue without damaging the graphene network. HfO 2 grown by atomic layer deposition on graphene cleaned using an Ar + ion beam showed a dense uniform structure, whereas that grown on the transferred graphene (before Ar + ion cleaning) showed a non-uniform structure. A graphene–HfO 2 –metal capacitor fabricated by growing 20-nm thick HfO 2 on graphene exhibited a very low leakage current (<10 −11 A/cm 2 ) for Ar + ion-cleaned graphene, whereas a similar capacitor grown using the transferred graphene showed high leakage current.

Integration issues of high-k and metal gate into conventional CMOS technology

International Nuclear Information System (INIS)

Song, S.C.; Zhang, Z.; Huffman, C.; Bae, S.H.; Sim, J.H.; Kirsch, P.; Majhi, P.; Moumen, N.; Lee, B.H.

2006-01-01

Issues surrounding the integration of Hf-based high-k dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate stack process as well as optimization of other CMOS process steps enables robust CMOSFETs with a wide process latitude. HfO 2 of a 2 nm physical thickness shows complete suppression of transient charge trapping resulting from a significant reduction in film volume as well as kinetically suppressed crystallization. Metal thickness is also critical when optimizing physical stress effects and minimizing dopant diffusion. A high temperature anneal after source and drain implantation in a conventional CMOSFET process reduces the interface state density and improves electron mobility

Effects of annealing temperature on the characteristics of ALD-deposited HfO2 in MIM capacitors

International Nuclear Information System (INIS)

Jeong, S.-W.; Lee, H.J.; Kim, K.S.; You, M.T.; Roh, Y.; Noguchi, T.; Xianyu, W.; Jung, J.

2006-01-01

We have investigated the annealing effects of HfO 2 films deposited by an atomic layer deposition (ALD) method on the electrical and physical properties in the Si/SiO 2 /Pt/ALD-HfO 2 /Pd metal-insulator-metal (MIM) capacitors. If the annealing temperature for HfO 2 films was restricted below 500 deg. C, an annealing step using a rapid thermal processor (RTP) improves the electrical properties such as the dissipation factor and the dielectric constant. On the other hand, annealing at 700 deg. C degrades the electrical characteristics in general; the dissipation factor increases over the frequency range of 1∼4 MHz, and the leakage current increases up to 2 orders at the low electric field regions. We found that the degradation of electrical properties is due to the grain growth in the HfO 2 film (i.e., poly-crystallization of the film) by the high temperature annealing processing. We suggested that the annealing temperature must be restricted below 500 deg. C to obtain the high quality high-k film for the MIM capacitors

Yttrium scandate thin film as alternative high-permittivity dielectric for germanium gate stack formation

Energy Technology Data Exchange (ETDEWEB)

Lu, Cimang, E-mail: cimang@adam.t.u-tokyo.ac.jp; Lee, Choong Hyun; Nishimura, Tomonori; Toriumi, Akira [Department of Materials Engineering, The University of Tokyo, 7-3-1 Hongo, Tokyo 113-8656 (Japan); JST, CREST, 7-3-1 Hongo, Tokyo 113-8656 (Japan)

2015-08-17

We investigated yttrium scandate (YScO{sub 3}) as an alternative high-permittivity (k) dielectric thin film for Ge gate stack formation. Significant enhancement of k-value is reported in YScO{sub 3} comparing to both of its binary compounds, Y{sub 2}O{sub 3} and Sc{sub 2}O{sub 3}, without any cost of interface properties. It suggests a feasible approach to a design of promising high-k dielectrics for Ge gate stack, namely, the formation of high-k ternary oxide out of two medium-k binary oxides. Aggressive scaling of equivalent oxide thickness (EOT) with promising interface properties is presented by using YScO{sub 3} as high-k dielectric and yttrium-doped GeO{sub 2} (Y-GeO{sub 2}) as interfacial layer, for a demonstration of high-k gate stack on Ge. In addition, we demonstrate Ge n-MOSFET performance showing the peak electron mobility over 1000 cm{sup 2}/V s in sub-nm EOT region by YScO{sub 3}/Y-GeO{sub 2}/Ge gate stack.

Surface Passivation of Silicon Using HfO2 Thin Films Deposited by Remote Plasma Atomic Layer Deposition System.

Science.gov (United States)

Zhang, Xiao-Ying; Hsu, Chia-Hsun; Lien, Shui-Yang; Chen, Song-Yan; Huang, Wei; Yang, Chih-Hsiang; Kung, Chung-Yuan; Zhu, Wen-Zhang; Xiong, Fei-Bing; Meng, Xian-Guo

2017-12-01

Hafnium oxide (HfO 2 ) thin films have attracted much attention owing to their usefulness in equivalent oxide thickness scaling in microelectronics, which arises from their high dielectric constant and thermodynamic stability with silicon. However, the surface passivation properties of such films, particularly on crystalline silicon (c-Si), have rarely been reported upon. In this study, the HfO 2 thin films were deposited on c-Si substrates with and without oxygen plasma pretreatments, using a remote plasma atomic layer deposition system. Post-annealing was performed using a rapid thermal processing system at different temperatures in N 2 ambient for 10 min. The effects of oxygen plasma pretreatment and post-annealing on the properties of the HfO 2 thin films were investigated. They indicate that the in situ remote plasma pretreatment of Si substrate can result in the formation of better SiO 2 , resulting in a better chemical passivation. The deposited HfO 2 thin films with oxygen plasma pretreatment and post-annealing at 500 °C for 10 min were effective in improving the lifetime of c-Si (original lifetime of 1 μs) to up to 67 μs.

Transparent nanoscale floating gate memory using self-assembled bismuth nanocrystals in Bi(2) Mg(2/3) Nb(4/3) O(7) (BMN) pyrochlore thin films grown at room temperature.

Science.gov (United States)

Jung, Hyun-June; Yoon, Soon-Gil; Hong, Soon-Ku; Lee, Jeong-Yong

2012-07-03

Bismuth nanocrystals for a nanoscale floating gate memory device are self-assembled in Bi(2) Mg(2/3) Nb(4/3) O(7) (BMN) dielectric films grown at room temperature by radio-frequency sputtering. The TEM cross-sectional image shows the "real" structure grown on a Si (001) substrate. The image magnified from the dotted box (red color) in the the cross-sectional image clearly shows bismuth nanoparticles at the interface between the Al(2) O(3) and HfO(2) layer (right image). Nanoparticles approximately 3 nm in size are regularly distributed at the interface. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Science.gov (United States)

Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

2018-06-01

The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

MeV-Si ion irradiation effects on the electrical properties of HfO2 thin films on Si

International Nuclear Information System (INIS)

Yu Xiangkun; Shao Lin; Chen, Q.Y.; Trombetta, L.; Wang Chunyu; Dharmaiahgari, Bhanu; Wang Xuemei; Chen Hui; Ma, K.B.; Liu Jiarui; Chu, W.-K.

2006-01-01

We studied the irradiation effect of 2-MeV Si ions on HfO 2 films deposited on Si substrates. HfO 2 films ∼11 nm thick were deposited onto Si substrates by chemical vapor deposition. The samples were then irradiated by 2-MeV Si ions at a fluence of 1 x 10 14 cm -2 at room temperature, followed by rapid thermal annealing at 1000 deg. C for 10 s. After annealing, a layer of aluminum was deposited on the samples as the gate electrode to form metal-oxide-semiconductor (MOS) capacitor structures. Rutherford backscattering spectrometry and electrical measurement of both capacitance and current as a function of voltage were used to characterize the samples before and after annealing. Non-insulating properties of the HfO 2 films deteriorated immediately after the ion irradiation, but rapid thermal annealing effectively repaired the irradiation damages, as reflected in improved capacitance versus voltage characteristics and significant reduction of leakage current in the MOS capacitors

Effect of nanocomposite gate-dielectric properties on pentacene microstructure and field-effect transistor characteristics.

Science.gov (United States)

Lee, Wen-Hsi; Wang, Chun-Chieh

2010-02-01

In this study, the effect of surface energy and roughness of the nanocomposite gate dielectric on pentacene morphology and electrical properties of pentacene OTFT are reported. Nanoparticles TiO2 were added in the polyimide matrix to form a nanocomposite which has a significantly different surface characteristic from polyimide, leading to a discrepancy in the structural properties of pentacene growth. A growth mode of pentacene deposited on the nanocomposite is proposed to explain successfully the effect of surface properties of nanocomposite gate dielectric such as surface energy and roughness on the pentacene morphology and electrical properties of OTFT. To obtain the lower surface energy and smoother surface of nanocomposite gate dielectric that is responsible for the desired crystalline, microstructure of pentacene and electrical properties of device, a bottom contact OTFT-pentacene deposited on the double-layer nanocomposite gate dielectric consisting of top smoothing layer of the neat polyimide and bottom layer of (PI+ nano-TiO2 particles) nanocomposite has been successfully demonstrated to exhibit very promising performance including high current on to off ratio of about 6 x 10(5), threshold voltage of -10 V and moderately high filed mobility of 0.15 cm2V(-1)s(-1).

High-Mobility 6,13-Bis(triisopropylsilylethynyl) Pentacene Transistors Using Solution-Processed Polysilsesquioxane Gate Dielectric Layers.

Science.gov (United States)

Matsuda, Yu; Nakahara, Yoshio; Michiura, Daisuke; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) is a low-temperature curable polymer that is compatible with low-cost plastic substrates. We cured PSQ gate dielectric layers by irradiation with ultraviolet light at ~60 °C, and used them for 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) thin film transistors (TFTs). The fabricated TFTs have shown the maximum and average hole mobility of 1.3 and 0.78 ± 0.3 cm2V-1s-1, which are comparable to those of the previously reported transistors using single-crystalline TIPS-pentacene micro-ribbons for their active layers and thermally oxidized SiO2 for their gate dielectric layers. Itis therefore demonstrated that PSQ is a promising polymer gate dielectric material for low-cost organic TFTs.

Enhanced ZnO Thin-Film Transistor Performance Using Bilayer Gate Dielectrics

KAUST Repository

Alshammari, Fwzah Hamud; Nayak, Pradipta K.; Wang, Zhenwei; Alshareef, Husam N.

2016-01-01

We report ZnO TFTs using Al2O3/Ta2O5 bilayer gate dielectrics grown by atomic layer deposition. The saturation mobility of single layer Ta2O5 dielectric TFT was 0.1 cm2 V-1 s-1, but increased to 13.3 cm2 V-1 s-1 using Al2O3/Ta2O5 bilayer dielectric with significantly lower leakage current and hysteresis. We show that point defects present in ZnO film, particularly VZn, are the main reason for the poor TFT performance with single layer dielectric, although interfacial roughness scattering effects cannot be ruled out. Our approach combines the high dielectric constant of Ta2O5 and the excellent Al2O3/ZnO interface quality, resulting in improved device performance. © 2016 American Chemical Society.

Enhanced ZnO Thin-Film Transistor Performance Using Bilayer Gate Dielectrics

KAUST Repository

Alshammari, Fwzah Hamud

2016-08-24

We report ZnO TFTs using Al2O3/Ta2O5 bilayer gate dielectrics grown by atomic layer deposition. The saturation mobility of single layer Ta2O5 dielectric TFT was 0.1 cm2 V-1 s-1, but increased to 13.3 cm2 V-1 s-1 using Al2O3/Ta2O5 bilayer dielectric with significantly lower leakage current and hysteresis. We show that point defects present in ZnO film, particularly VZn, are the main reason for the poor TFT performance with single layer dielectric, although interfacial roughness scattering effects cannot be ruled out. Our approach combines the high dielectric constant of Ta2O5 and the excellent Al2O3/ZnO interface quality, resulting in improved device performance. © 2016 American Chemical Society.

Surface modelling on heavy atom crystalline compounds: HfO2 and UO2 fluorite structures

International Nuclear Information System (INIS)

Evarestov, Robert; Bandura, Andrei; Blokhin, Eugeny

2009-01-01

The study of the bulk and surface properties of cubic (fluorite structure) HfO 2 and UO 2 was performed using the hybrid Hartree-Fock density functional theory linear combination of atomic orbitals simulations via the CRYSTAL06 computer code. The Stuttgart small-core pseudopotentials and corresponding basis sets were used for the core-valence interactions. The influence of relativistic effects on the structure and properties of the systems was studied. It was found that surface properties of Mott-Hubbard dielectric UO 2 differ from those found for other metal oxides with the closed-shell configuration of d-electrons

Effect of incorporation of nitrogen atoms in Al2O3 gate dielectric of wide-bandgap-semiconductor MOSFET on gate leakage current and negative fixed charge

Science.gov (United States)

Kojima, Eiji; Chokawa, Kenta; Shirakawa, Hiroki; Araidai, Masaaki; Hosoi, Takuji; Watanabe, Heiji; Shiraishi, Kenji

2018-06-01

We performed first-principle calculations to investigate the effect of incorporation of N atoms into Al2O3 gate dielectrics. Our calculations show that the defect levels generated by VO in Al2O3 are the origin of the stress-induced gate leakage current and that VOVAl complexes in Al2O3 cause negative fixed charge. We revealed that the incorporation of N atoms into Al2O3 eliminates the VO defect levels, reducing the stress-induced gate leakage current. Moreover, this suppresses the formation of negatively charged VOVAl complexes. Therefore, AlON can reduce both stress-induced gate leakage current and negative fixed charge in wide-bandgap-semiconductor MOSFETs.

High performance solution processed zirconium oxide gate dielectric appropriate for low temperature device application

Energy Technology Data Exchange (ETDEWEB)

Hasan, Musarrat; Nguyen, Manh-Cuong; Kim, Hyojin; You, Seung-Won; Jeon, Yoon-Seok; Tong, Duc-Tai; Lee, Dong-Hwi; Jeong, Jae Kyeong; Choi, Rino, E-mail: rino.choi@inha.ac.kr

2015-08-31

This paper reports a solution processed electrical device with zirconium oxide gate dielectric that was fabricated at a low enough temperature appropriate for flexible electronics. Both inorganic dielectric and channel materials were synthesized in the same organic solvent. The dielectric constant achieved was 13 at 250 °C with a reasonably low leakage current. The bottom gate transistor devices showed the highest mobility of 75 cm{sup 2}/V s. The device is operated at low voltage with high-k dielectric with excellent transconductance and low threshold voltage. Overall, the results highlight the potential of low temperature solution based deposition in fabricating more complicated circuits for a range of applications. - Highlights: • We develop a low temperature inorganic dielectric deposition process. • We fabricate oxide semiconductor channel devices using all-solution processes. • Same solvent is used for dielectric and oxide semiconductor deposition.

Effects of nitrogen incorporation in HfO(2) grown on InP by atomic layer deposition: an evolution in structural, chemical, and electrical characteristics.

Science.gov (United States)

Kang, Yu-Seon; Kim, Dae-Kyoung; Kang, Hang-Kyu; Jeong, Kwang-Sik; Cho, Mann-Ho; Ko, Dae-Hong; Kim, Hyoungsub; Seo, Jung-Hye; Kim, Dong-Chan

2014-03-26

We investigated the effects of postnitridation on the structural characteristics and interfacial reactions of HfO2 thin films grown on InP by atomic layer deposition (ALD) as a function of film thickness. By postdeposition annealing under NH3 vapor (PDN) at 600 °C, an InN layer formed at the HfO2/InP interface, and ionized NHx was incorporated in the HfO2 film. We demonstrate that structural changes resulting from nitridation of HfO2/InP depend on the film thickness (i.e., a single-crystal interfacial layer of h-InN formed at thin (2 nm) HfO2/InP interfaces, whereas an amorphous InN layer formed at thick (>6 nm) HfO2/InP interfaces). Consequently, the tetragonal structure of HfO2 transformed into a mixture structure of tetragonal and monoclinic because the interfacial InN layer relieved interfacial strain between HfO2 and InP. During postdeposition annealing (PDA) in HfO2/InP at 600 °C, large numbers of oxidation states were generated as a result of interfacial reactions between interdiffused oxygen impurities and out-diffused InP substrate elements. However, in the case of the PDN of HfO2/InP structures at 600 °C, nitrogen incorporation in the HfO2 film effectively blocked the out-diffusion of atomic In and P, thus suppressing the formation of oxidation states. Accordingly, the number of interfacial defect states (Dit) within the band gap of InP was significantly reduced, which was also supported by DFT calculations. Interfacial InN in HfO2/InP increased the electron-barrier height to ∼0.6 eV, which led to low-leakage-current density in the gate voltage region over 2 V.

HfO2 and SiO2 as barriers in magnetic tunneling junctions

Science.gov (United States)

Shukla, Gokaran; Archer, Thomas; Sanvito, Stefano

2017-05-01

SiO2 and HfO2 are both high-k, wide-gap semiconductors, currently used in the microelectronic industry as gate barriers. Here we investigate whether the same materials can be employed to make magnetic tunnel junctions, which in principle can be amenable for integration in conventional Si technology. By using a combination of density functional theory and the nonequilibrium Green's functions method for quantum transport we have studied the transport properties of Co [0001 ] /SiO2[001 ] /Co [0001 ] and Fe [001 ] /HfO2[001 ] /Fe [001 ] junctions. In both cases we found a quite large magnetoresistance, which is explained through the analysis of the real band structure of the magnets and the complex one of the insulator. We find that there is no symmetry spin filtering for the Co-based junction since the high transmission Δ2' band crosses the Fermi level, EF, for both spin directions. However, the fact that Co is a strong ferromagnet makes the orbital contribution to the two Δ2' spin subbands different, yielding magnetoresistance. In contrast for the Fe-based junction symmetry filtering is active for an energy window spanning between the Fermi level and 1 eV below EF, with Δ1 symmetry contributing to the transmission.

Effects of Annealing Time on the Performance of OTFT on Glass with ZrO2 as Gate Dielectric

Directory of Open Access Journals (Sweden)

W. M. Tang

2012-01-01

Full Text Available Copper phthalocyanine-based organic thin-film transistors (OTFTs with zirconium oxide (ZrO2 as gate dielectric have been fabricated on glass substrates. The gate dielectric is annealed in N2 at different durations (5, 15, 40, and 60 min to investigate the effects of annealing time on the electrical properties of the OTFTs. Experimental results show that the longer the annealing time for the OTFT, the better the performance. Among the devices studied, OTFTs with gate dielectric annealed at 350°C in N2 for 60 min exhibit the best device performance. They have a small threshold voltage of −0.58 V, a low subthreshold slope of 0.8 V/decade, and a low off-state current of 0.73 nA. These characteristics demonstrate that the fabricated device is suitable for low-voltage and low-power operations. When compared with the TFT samples annealed for 5 min, the ones annealed for 60 min have 20% higher mobility and nearly two times smaller the subthreshold slope and off-state current. The extended annealing can effectively reduce the defects in the high-k film and produces a better insulator/organic interface. This results in lower amount of carrier scattering and larger CuPc grains for carrier transport.

Improvement on the electrical characteristics of Pd/HfO2/6H-SiC MIS capacitors using post deposition annealing and post metallization annealing

Science.gov (United States)

Esakky, Papanasam; Kailath, Binsu J.

2017-08-01

HfO2 as a gate dielectric enables high electric field operation of SiC MIS structure and as gas sensor HfO2/SiC capacitors offer higher sensitivity than SiO2/SiC capacitors. The issue of higher density of oxygen vacancies and associated higher leakage current necessitates better passivation of HfO2/SiC interface. Effect of post deposition annealing in N2O plasma and post metallization annealing in forming gas on the structural and electrical characteristics of Pd/HfO2/SiC MIS capacitors are reported in this work. N2O plasma annealing suppresses crystallization during high temperature annealing thereby improving the thermal stability and plasma annealing followed by rapid thermal annealing in N2 result in formation of Hf silicate at the HfO2/SiC interface resulting in order of magnitude lower density of interface states and gate leakage current. Post metallization annealing in forming gas for 40 min reduces interface state density by two orders while gate leakage current density is reduced by thrice. Post deposition annealing in N2O plasma and post metallization annealing in forming gas are observed to be effective passivation techniques improving the electrical characteristics of HfO2/SiC capacitors.

Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

International Nuclear Information System (INIS)

Besleaga, C.; Stan, G.E.; Pintilie, I.; Barquinha, P.; Fortunato, E.; Martins, R.

2016-01-01

Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

Energy Technology Data Exchange (ETDEWEB)

Besleaga, C.; Stan, G.E.; Pintilie, I. [National Institute of Materials Physics, 405A Atomistilor, 077125 Magurele-Ilfov (Romania); Barquinha, P.; Fortunato, E. [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal); Martins, R., E-mail: rm@uninova.pt [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal)

2016-08-30

Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

Materials Fundamentals of Gate Dielectrics

CERN Document Server

Demkov, Alexander A

2006-01-01

This book presents materials fundamentals of novel gate dielectrics that are being introduced into semiconductor manufacturing to ensure the continuous scalling of the CMOS devices. This is a very fast evolving field of research so we choose to focus on the basic understanding of the structure, thermodunamics, and electronic properties of these materials that determine their performance in device applications. Most of these materials are transition metal oxides. Ironically, the d-orbitals responsible for the high dielectric constant cause sever integration difficulties thus intrinsically limiting high-k dielectrics. Though new in the electronics industry many of these materials are wel known in the field of ceramics, and we describe this unique connection. The complexity of the structure-property relations in TM oxides makes the use of the state of the art first-principles calculations necessary. Several chapters give a detailed description of the modern theory of polarization, and heterojunction band discont...

Pentacene based thin film transistors with high-k dielectric Nd2O3 as a gate insulator

International Nuclear Information System (INIS)

Sarma, R.; Saikia, D.

2010-01-01

We have investigated the pentacene based Organic Thin Film Transistors (OTFTs) with high-k dielectric Nd 2 O 3 . Use of high dielectric constant (high-k) gate insulator Nd 2 O 3 reduces the threshold voltage and sub threshold swing of the OTFTs. The calculated threshold voltage -2.2V and sub-threshold swing 1V/decade, current ON-OFF ratio is 1.7 X 10 4 and mobility is 0.13cm 2 /V.s. Pentacene film is deposited on Nd 2 O 3 surface using two step deposition method. Deposited pentacene film is found poly crystalline in nature. (author)

High-performance pentacene OTFT by incorporating Ti in LaON gate dielectric

Science.gov (United States)

Ma, Y. X.; Han, C. Y.; Tang, W. M.; Lai, P. T.

2017-07-01

Pentacene organic thin-film transistors (OTFT) using high-k LaTiON gate dielectric with different Ti contents are investigated. The LaxTi(1-x)ON films (with x = 1, 0.87, 0.76, and 0.67) are deposited by reactive sputtering followed by an annealing in N2 at 200 °C. The OTFT with La0.87Ti0.13ON can achieve a high carrier mobility of 2.6 cm2/V.s, a small threshold voltage of -1.5 V, a small sub-threshold swing of 0.07 V/dec, and a small hysteresis of 0.17 V. AFM and X-ray photoelectron spectroscopy reveal that Ti can suppress the hygroscopicity of La oxide to achieve a smoother dielectric surface, which can result in larger pentacene grains and thus higher carrier mobility. All the devices show a clockwise hysteresis because both the LaOH formation and Ti incorporation can generate acceptor-like traps in the gate dielectric.

Comparison of precursors for pulsed metal-organic chemical vapor deposition of HfO2 high-K dielectric thin films

International Nuclear Information System (INIS)

Teren, Andrew R.; Thomas, Reji; He, Jiaqing; Ehrhart, Peter

2005-01-01

Hafnium oxide films were deposited on Si(100) substrates using pulsed metal-organic chemical vapor deposition (CVD) and evaluated for high-K dielectric applications. Three types of precursors were tested: two oxygenated ones, Hf butoxide-dmae and Hf butoxide-mmp, and an oxygen-free one, Hf diethyl-amide. Depositions were carried out in the temperature range of 350-650 deg. C, yielding different microstructures ranging from amorphous to crystalline, monoclinic, films. The films were compared on the basis of growth rate, phase development, density, interface characteristics, and electrical properties. Some specific features of the pulsed injection technique are considered. For low deposition temperatures the growth rate for the amide precursor was significantly higher than for the mixed butoxide precursors. A thickness-dependent amorphous to crystalline phase transition temperature was found for all precursors. There is an increase of the film density along with the deposition temperature from values as low as 5 g/cm 3 at 350 deg. C to values close to the bulk value of 9.7 g/cm 3 at 550 deg. C. Crystallization is observed in the same temperature range for films of typically 10-20 nm thickness. However, annealing studies show that this density increase is not simply related to the crystallization of the films. Similar electrical properties could be observed for all precursors and the dielectric constant of the films reaches values similar to the best values reported for bulk crystalline HfO 2

Combining a multi deposition multi annealing technique with a scavenging (Ti) to improve the high-k/metal gate stack performance for a gate-last process

International Nuclear Information System (INIS)

Zhang ShuXiang; Yang Hong; Tang Bo; Tang Zhaoyun; Xu Yefeng; Xu Jing; Yan Jiang

2014-01-01

ALD HfO 2 films fabricated by a novel multi deposition multi annealing (MDMA) technique are investigated, we have included samples both with and without a Ti scavenging layer. As compared to the reference gate stack treated by conventional one-time deposition and annealing (D and A), devices receiving MDMA show a significant reduction in leakage current. Meanwhile, EOT growth is effectively controlled by the Ti scavenging layer. This improvement strongly correlates with the cycle number of D and A (while keeping the total annealing time and total dielectrics thickness the same). Transmission electron microscope and energy-dispersive X-ray spectroscopy analysis suggests that oxygen incorporation into both the high-k film and the interfacial layer is likely to be responsible for the improvement of the device. This novel MDMA is promising for the development of gate stack technology in a gate last integration scheme. (semiconductor technology)

Analyzing the effect of gate dielectric on the leakage currents

Directory of Open Access Journals (Sweden)

Sakshi

2016-01-01

Full Text Available An analytical threshold voltage model for MOSFETs has been developed using different gate dielectric oxides by using MATLAB software. This paper explains the dependency of threshold voltage on the dielectric material. The variation in the subthreshold currents with the change in the threshold voltage sue to the change of dielectric material has also been studied.

Solid phase crystallisation of HfO2 thin films

International Nuclear Information System (INIS)

Modreanu, M.; Sancho-Parramon, J.; O'Connell, D.; Justice, J.; Durand, O.; Servet, B.

2005-01-01

In this paper, we report on the solid phase crystallisation of carbon-free HfO 2 thin films deposited by plasma ion assisted deposition (PIAD). After deposition, the HfO 2 films were annealed in N 2 ambient for 3 h at 350, 550 and 750 deg. C. Several characterisation techniques including X-ray reflectometry (XRR), X-ray diffraction (XRD), spectroscopic ellipsometry (SE) and atomic force microscopy (AFM) were used for the physical characterisation of as-deposited and annealed HfO 2 . XRD has revealed that the as-deposited HfO 2 film is in an amorphous-like state with only traces of crystalline phase and that the annealed films are in a highly crystalline state. These results are in good agreement with the SE results showing an increase of refractive index by increasing the annealing temperature. XRR results show a significant density gradient over the as-deposited film thickness, which is characteristic of the PIAD method. The AFM measurements show that the HfO 2 layers have a smooth surface even after annealing at 750 deg. C. The present study demonstrates that the solid phase crystallisation of HfO 2 PIAD thin films starts at a temperature as low as 550 deg. C

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

Science.gov (United States)

Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

2013-06-01

In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

Science.gov (United States)

Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

The effect of a HfO2 insulator on the improvement of breakdown voltage in field-plated GaN-based HEMT

International Nuclear Information System (INIS)

Mao Wei; Hao Yue; Ma Xiao-Hua; Wang Chong; Zhang Jin-Cheng; Liu Hong-Xia; Bi Zhi-Wei; Xu Sheng-Rui; Yang Lin-An; Yang Ling; Zhang Kai; Zhang Nai-Qian; Pei Yi; Yang Cui

2011-01-01

A GaN/Al 0.3 Ga 0.7 N/AlN/GaN high-electron mobility transistor utilizing a field plate (with a 0.3 μm overhang towards the drain and a 0.2 μm overhang towards the source) over a 165-nm sputtered HfO 2 insulator (HfO 2 -FP-HEMT) is fabricated on a sapphire substrate. Compared with the conventional field-plated HEMT, which has the same geometric structure but uses a 60-nm SiN insulator beneath the field plate (SiN-FP-HEMT), the HfO 2 -FP-HEMT exhibits a significant improvement of the breakdown voltage (up to 181 V) as well as a record field-plate efficiency (up to 276 V/μm). This is because the HfO 2 insulator can further improve the modulation of the field plate on the electric field distribution in the device channel, which is proved by the numerical simulation results. Based on the simulation results, a novel approach named the proportional design is proposed to predict the optimal dielectric thickness beneath the field plate. It can simplify the field-plated HEMT design significantly. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Fabrication and electrical properties of metal-oxide semiconductor capacitors based on polycrystalline p-Cu{sub x}O and HfO{sub 2}/SiO{sub 2} high-{kappa} stack gate dielectrics

Energy Technology Data Exchange (ETDEWEB)

Zou Xiao [Department of Electronic Science and Technology, School of Physical Science and Technology, Wuhan University, Wuhan, 430074 (China); Department of Electromachine Engineering, Jianghan University, Wuhan, 430056 (China); Fang Guojia, E-mail: gjfang@whu.edu.c [Department of Electronic Science and Technology, School of Physical Science and Technology, Wuhan University, Wuhan, 430074 (China); Yuan Longyan; Liu Nishuang; Long Hao; Zhao Xingzhong [Department of Electronic Science and Technology, School of Physical Science and Technology, Wuhan University, Wuhan, 430074 (China)

2010-05-31

Polycrystalline p-type Cu{sub x}O films were deposited after the growth of HfO{sub 2} dielectric on Si substrate by pulsed laser deposition, and Cu{sub x}O metal-oxide-semiconductor (MOS) capacitors with HfO{sub 2}/SiO{sub 2} stack gate dielectric were primarily fabricated and investigated. X-ray diffraction and X-ray photoelectron spectroscopy were applied to analyze crystalline structure and Cu{sup +}/Cu{sup 2+} ratios of Cu{sub x}O films respectively. SiO{sub 2} interlayer formed between the high-{kappa} dielectric and substrate was estimated by the transmission electron microscope. Results of electrical characteristic measurement indicate that the permittivity of HfO{sub 2} is about 22, and the gate leakage current density of MOS capacitor with 11.3 nm HfO{sub 2}/SiO{sub 2} stack dielectrics is {approx} 10{sup -4} A/cm{sup 2}. Results also show that the annealing in N{sub 2} can improve the quality of Cu{sub x}O/HfO{sub 2} interface and thus reduce the gate leakage density.

SEMICONDUCTOR DEVICES: Structural and electrical characteristics of lanthanum oxide gate dielectric film on GaAs pHEMT technology

Science.gov (United States)

Chia-Song, Wu; Hsing-Chung, Liu

2009-11-01

This paper investigates the feasibility of using a lanthanum oxide thin film (La2O3) with a high dielectric constant as a gate dielectric on GaAs pHEMTs to reduce gate leakage current and improve the gate to drain breakdown voltage relative to the conventional GaAs pHEMT. An E/D mode pHEMT in a single chip was realized by selecting the appropriate La2O3 thickness. The thin La2O3 film was characterized: its chemical composition and crystalline structure were determined by X-ray photoelectron spectroscopy and X-ray diffraction, respectively. La2O3 exhibited good thermal stability after post-deposition annealing at 200, 400 and 600 °C because of its high binding-energy (835.6 eV). Experimental results clearly demonstrated that the La2O3 thin film was thermally stable. The DC and RF characteristics of Pt/La2O3/Ti/Au gate and conventional Pt/Ti/Au gate pHEMTs were examined. The measurements indicated that the transistor with the Pt/La2O3/Ti/Au gate had a higher breakdown voltage and lower gate leakage current. Accordingly, the La2O3 thin film is a potential high-k material for use as a gate dielectric to improve electrical performance and the thermal effect in high-power applications.

Effect of ion implantation energy for the synthesis of Ge nanocrystals in SiN films with HfO2/SiO2 stack tunnel dielectrics for memory application

Directory of Open Access Journals (Sweden)

Gloux Florence

2011-01-01

Full Text Available Abstract Ge nanocrystals (Ge-NCs embedded in SiN dielectrics with HfO2/SiO2 stack tunnel dielectrics were synthesized by utilizing low-energy (≤5 keV ion implantation method followed by conventional thermal annealing at 800°C, the key variable being Ge+ ion implantation energy. Two different energies (3 and 5 keV have been chosen for the evolution of Ge-NCs, which have been found to possess significant changes in structural and chemical properties of the Ge+-implanted dielectric films, and well reflected in the charge storage properties of the Al/SiN/Ge-NC + SiN/HfO2/SiO2/Si metal-insulator-semiconductor (MIS memory structures. No Ge-NC was detected with a lower implantation energy of 3 keV at a dose of 1.5 × 1016 cm-2, whereas a well-defined 2D-array of nearly spherical and well-separated Ge-NCs within the SiN matrix was observed for the higher-energy-implanted (5 keV sample for the same implanted dose. The MIS memory structures implanted with 5 keV exhibits better charge storage and retention characteristics compared to the low-energy-implanted sample, indicating that the charge storage is predominantly in Ge-NCs in the memory capacitor. A significant memory window of 3.95 V has been observed under the low operating voltage of ± 6 V with good retention properties, indicating the feasibility of these stack structures for low operating voltage, non-volatile memory devices.

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

Science.gov (United States)

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

Study of surface-modified PVP gate dielectric in organic thin film transistors with the nano-particle silver ink source/drain electrode.

Science.gov (United States)

Yun, Ho-Jin; Ham, Yong-Hyun; Shin, Hong-Sik; Jeong, Kwang-Seok; Park, Jeong-Gyu; Choi, Deuk-Sung; Lee, Ga-Won

2011-07-01

We have fabricated the flexible pentacene based organic thin film transistors (OTFTs) with formulated poly[4-vinylphenol] (PVP) gate dielectrics treated by CF4/O2 plasma on poly[ethersulfones] (PES) substrate. The solution of gate dielectrics is made by adding methylated poly[melamine-co-formaldehyde] (MMF) to PVP. The PVP gate dielectric layer was cross linked at 90 degrees under UV ozone exposure. Source/drain electrodes are formed by micro contact printing (MCP) method using nano particle silver ink for the purposes of low cost and high throughput. The optimized OTFT shows the device performance with field effect mobility of the 0.88 cm2/V s, subthreshold slope of 2.2 V/decade, and on/off current ratios of 1.8 x 10(-6) at -40 V gate bias. We found that hydrophobic PVP gate dielectric surface can influence on the initial film morphologies of pentacene making dense, which is more important for high performance OTFTs than large grain size. Moreover, hydrophobic gate dielelctric surface reduces voids and -OH groups that interrupt the carrier transport in OTFTs.

Polycrystalline diamond RF MOSFET with MoO3 gate dielectric

Directory of Open Access Journals (Sweden)

Zeyang Ren

2017-12-01

Full Text Available We report the radio frequency characteristics of the diamond metal-oxide-semiconductor field effect transistor with MoO3 gate dielectric for the first time. The device with 2-μm gate length was fabricated on high quality polycrystalline diamond. The maximum drain current of 150 mA/mm at VGS = -5 V and the maximum transconductance of 27 mS/mm were achieved. The extrinsic cutoff frequency of 1.2 GHz and the maximum oscillation frequency of 1.9 GHz have been measured. The moderate frequency characteristics are attributed to the moderate transconductance limited by the series resistance along the channel. We expect that the frequency characteristics of the device can be improved by increasing the magnitude of gm, or fundamentally decreasing the gate-controlled channel resistance and series resistance along the channel, and down-scaling the gate length.

Medium band gap polymer based solution-processed high-κ composite gate dielectrics for ambipolar OFET

Science.gov (United States)

Canımkurbey, Betül; Unay, Hande; Çakırlar, Çiğdem; Büyükköse, Serkan; Çırpan, Ali; Berber, Savas; Altürk Parlak, Elif

2018-03-01

The authors present a novel ambipolar organic filed-effect transistors (OFETs) composed of a hybrid dielectric thin film of Ta2O5:PMMA nanocomposite material, and solution processed poly(selenophene, benzotriazole and dialkoxy substituted [1,2-b:4, 5-b‧] dithiophene (P-SBTBDT)-based organic semiconducting material as the active layer of the device. We find that the Ta2O5:PMMA insulator shows n-type conduction character, and its combination with the p-type P-SBTBDT organic semiconductor leads to an ambipolar OFET device. Top-gated OFETs were fabricated on glass substrate consisting of interdigitated ITO electrodes. P-SBTBDT-based material was spin coated on the interdigitated ITO electrodes. Subsequently, a solution processed Ta2O5:PMMA nanocomposite material was spin coated, thereby creating the gate dielectric layer. Finally, as a gate metal, an aluminum layer was deposited by thermal evaporation. The fabricated OFETs exhibited an ambipolar performance with good air-stability, high field-induced current and relatively high electron and hole mobilities although Ta2O5:PMMA nanocomposite films have slightly higher leakage current compared to the pure Ta2O5 films. Dielectric properties of the devices with different ratios of Ta2O5:PMMA were also investigated. The dielectric constant varied between 3.6 and 5.3 at 100 Hz, depending on the Ta2O5:PMMA ratio.

Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High-k Gate Dielectric Materials

Directory of Open Access Journals (Sweden)

Yu-Hsien Lin

2015-01-01

Full Text Available We investigated amorphous indium gallium zinc oxide (a-IGZO thin film transistors (TFTs using different high-k gate dielectric materials such as silicon nitride (Si3N4 and aluminum oxide (Al2O3 at low temperature process (<300°C and compared them with low temperature silicon dioxide (SiO2. The IGZO device with high-k gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, postannealing treatment is an essential process for completing the process. The chemical reaction of the high-k/IGZO interface due to heat formation in high-k/IGZO materials results in reliability issue. We also used the voltage stress for testing the reliability for the device with different high-k gate dielectric materials and explained the interface effect by charge band diagram.

Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High-k Gate Dielectric Materials

International Nuclear Information System (INIS)

Lin, Y. H.; Chou, J. C.

2015-01-01

We investigated amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFT_s) using different high-Κ gate dielectric materials such as silicon nitride (Si_3N_4) and aluminum oxide (Al_2O_3) at low temperature process (<300 degree) and compared them with low temperature silicon dioxide (SiO_2). The IGZO device with high-Κ gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, post annealing treatment is an essential process for completing the process. The chemical reaction of the high-κ/IGZO interface due to heat formation in high-Κ/IGZO materials results in reliability issue. We also used the voltage stress for testing the reliability for the device with different high-Κ gate dielectric materials and explained the interface effect by charge band diagram.

High mobility and low operating voltage ZnGaO and ZnGaLiO transistors with spin-coated Al2O3 as gate dielectric

International Nuclear Information System (INIS)

Xia, D X; Xu, J B

2010-01-01

Spin-coated alumina serving as a gate dielectric in thin film transistors shows interesting dielectric properties for low-voltage applications, despite a moderate capacitance. With Ga singly doped and Ga, Li co-doped ZnO as the active channel layers, typical mobilities of 4.7 cm 2 V -1 s -1 and 2.1 cm 2 V -1 s -1 are achieved, respectively. At a given gate bias, the operation current is much smaller than the previously reported values in low-voltage thin film transistors, primarily relying on the giant-capacitive dielectric. The reported devices combine advantages of high mobility, low power consumption, low cost and ease of fabrication. In addition to the transparent nature of both the dielectric and semiconducting active channels, the superior electrical properties of the devices may provide a new avenue for future transparent electronics. (fast track communication)

Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11 000 cm2/V·s

KAUST Repository

Smith, Casey; Qaisi, Ramy M.; Liu, Zhihong; Yu, Qingkai; Hussain, Muhammad Mustafa

2013-01-01

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11 000 cm 2/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low t ox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance. © 2013 American Chemical Society.

Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11 000 cm2/V·s

KAUST Repository

Smith, Casey

2013-07-23

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11 000 cm 2/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low t ox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance. © 2013 American Chemical Society.

Experimental and theoretical investigation of the effect of SiO2 content in gate dielectrics on work function shift induced by nanoscale capping layers

KAUST Repository

Caraveo-Frescas, J. A.; Wang, H.; Schwingenschlö gl, Udo; Alshareef, Husam N.

2012-01-01

The impact of SiO2 content in ultrathin gate dielectrics on the magnitude of the effective work function (EWF) shift induced by nanoscale capping layers has been investigated experimentally and theoretically. The magnitude of the effective work function shift for four different capping layers (AlN, Al2O3, La2O3, and Gd2O3) is measured as a function of SiO2 content in the gate dielectric. A nearly linear increase of this shift with SiO2 content is observed for all capping layers. The origin of this dependence is explained using density functional theory simulations.

Experimental and theoretical investigation of the effect of SiO2 content in gate dielectrics on work function shift induced by nanoscale capping layers

KAUST Repository

Caraveo-Frescas, J. A.

2012-09-10

The impact of SiO2 content in ultrathin gate dielectrics on the magnitude of the effective work function (EWF) shift induced by nanoscale capping layers has been investigated experimentally and theoretically. The magnitude of the effective work function shift for four different capping layers (AlN, Al2O3, La2O3, and Gd2O3) is measured as a function of SiO2 content in the gate dielectric. A nearly linear increase of this shift with SiO2 content is observed for all capping layers. The origin of this dependence is explained using density functional theory simulations.

Dielectric strength of SiO2 in a CMOS transistor structure

International Nuclear Information System (INIS)

Soden, J.M.

1979-01-01

The distribution of experimental dielectric strengths of SiO 2 gate dielectric in a CMOS transistor structure is shown to be composed of a primary, statistically-normal distribution of high dielectric strength and a secondary distribution spread through the lower dielectric strength region. The dielectric strength was not significantly affected by high level (1 x 10 6 RADS (Si)) gamma radiation or high temperature (200 0 C) stress. The primary distribution breakdowns occurred at topographical edges, mainly at the gate/field oxide interface, and the secondary distribution breakdowns occurred at random locations in the central region of the gate

Electrical characteristics of GdTiO{sub 3} gate dielectric for amorphous InGaZnO thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Her, Jim-Long [Division of Natural Science, Center for General Education, Chang Gung University, Taoyuan 333, Taiwan (China); Pan, Tung-Ming, E-mail: tmpan@mail.cgu.edu.tw [Department of Electronics Engineering, Chang Gung University, Taoyuan 333, Taiwan (China); Liu, Jiang-Hung; Wang, Hong-Jun; Chen, Ching-Hung [Department of Electronics Engineering, Chang Gung University, Taoyuan 333, Taiwan (China); Koyama, Keiichi [Graduate School of Science and Engineering, Kagoshima University, Kagoshima 890-0065 (Japan)

2014-10-31

In this article, we studied the structural properties and electrical characteristics of GdTiO{sub 3} gate dielectric for amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) applications. The a-IGZO TFT device featuring the GdTiO{sub 3} gate dielectric exhibited better electrical characteristics, including a small threshold voltage of 0.14 V, a large field-effect mobility of 32.3 cm{sup 2}/V-s, a high I{sub on}/I{sub off} current ratio of 4.2 × 10{sup 8}, and a low subthreshold swing of 213 mV/decade. Furthermore, the electrical instability of GdTiO{sub 3} a-IGZO TFTs was investigated under both positive gate-bias stress (PGBS) and negative gate-bias stress (NGBS) conditions. The electron charge trapping in the gate dielectric dominates the PGBS degradation, while the oxygen vacancies control the NGBS degradation. - Highlights: • Indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) • Structural and electrical properties of the GdTiO{sub 3} film were studied. • a-IGZO TFT featuring GdTi{sub x}O{sub y} dielectric exhibited better electrical characteristics. • TFT instability investigated under positive and negative gate-bias stress conditions.

Reliability assessment of ultra-thin HfO2 films deposited on silicon wafer

International Nuclear Information System (INIS)

Fu, Wei-En; Chang, Chia-Wei; Chang, Yong-Qing; Yao, Chih-Kai; Liao, Jiunn-Der

2012-01-01

Highlights: ► Nano-mechanical properties on annealed ultra-thin HfO 2 film are studied. ► By AFM analysis, hardness of the crystallized HfO 2 film significantly increases. ► By nano-indention, the film hardness increases with less contact stiffness. ► Quality assessment on the annealed ultra-thin films can thus be achieved. - Abstract: Ultra-thin hafnium dioxide (HfO 2 ) is used to replace silicon dioxide to meet the required transistor feature size in advanced semiconductor industry. The process integration compatibility and long-term reliability for the transistors depend on the mechanical performance of ultra-thin HfO 2 films. The criteria of reliability including wear resistance, thermal fatigue, and stress-driven failure rely on film adhesion significantly. The adhesion and variations in mechanical properties induced by thermal annealing of the ultra-thin HfO 2 films deposited on silicon wafers (HfO 2 /SiO 2 /Si) are not fully understood. In this work, the mechanical properties of an atomic layer deposited HfO 2 (nominal thickness ≈10 nm) on a silicon wafer were characterized by the diamond-coated tip of an atomic force microscope and compared with those of annealed samples. The results indicate that the annealing process leads to the formation of crystallized HfO 2 phases for the atomic layer deposited HfO 2 . The HfSi x O y complex formed at the interface between HfO 2 and SiO 2 /Si, where the thermal diffusion of Hf, Si, and O atoms occurred. The annealing process increases the surface hardness of crystallized HfO 2 film and therefore the resistance to nano-scratches. In addition, the annealing process significantly decreases the harmonic contact stiffness (or thereafter eliminate the stress at the interface) and increases the nano-hardness, as measured by vertically sensitive nano-indentation. Quality assessments on as-deposited and annealed HfO 2 films can be thereafter used to estimate the mechanical properties and adhesion of ultra-thin HfO 2

Pentacene thin-film transistors and inverters with plasma-enhanced atomic-layer-deposited Al2O3 gate dielectric

International Nuclear Information System (INIS)

Koo, Jae Bon; Lim, Jung Wook; Kim, Seong Hyun; Yun, Sun Jin; Ku, Chan Hoe; Lim, Sang Chul; Lee, Jung Hun

2007-01-01

The performances of pentacene thin-film transistor with plasma-enhanced atomic-layer-deposited (PEALD) 150 nm thick Al 2 O 3 dielectric are reported. Saturation mobility of 0.38 cm 2 /V s, threshold voltage of 1 V, subthreshold swing of 0.6 V/decade, and on/off current ratio of about 10 8 have been obtained. Both depletion and enhancement mode inverter have been realized with the change of treatment method of hexamethyldisilazane on PEALD Al 2 O 3 gate dielectric. Full swing depletion mode inverter has been demonstrated at input voltages ranging from 5 V to - 5 V at supply voltage of - 5 V

Effect of gate dielectrics on the performance of p-type Cu2O TFTs processed at room temperature

KAUST Repository

Al-Jawhari, Hala A.; Caraveo-Frescas, Jesus Alfonso

2013-01-01

/off ratio of around 44, threshold voltage equaling -0.62 V and a sub threshold swing of 1.64 V/dec. These values were obtained at a low operating voltage of -2V. The advantages of using STO as a gate dielectric relative to ATO are discussed. © (2014) Trans

Leakage current conduction mechanisms and electrical properties of atomic-layer-deposited HfO2/Ga2O3 MOS capacitors

Science.gov (United States)

Zhang, Hongpeng; Jia, Renxu; Lei, Yuan; Tang, Xiaoyan; Zhang, Yimen; Zhang, Yuming

2018-02-01

In this paper, current conduction mechanisms in HfO2/β-Ga2O3 metal-oxide-semiconductor (MOS) capacitors under positive and negative biases are investigated using the current-voltage (I-V) measurements conducted at temperatures from 298 K to 378 K. The Schottky emission is dominant under positively biased electric fields of 0.37-2.19 MV cm-1, and the extracted Schottky barrier height ranged from 0.88 eV to 0.91 eV at various temperatures. The Poole-Frenkel emission dominates under negatively biased fields of 1.92-4.83 MV cm-1, and the trap energy levels are from 0.71 eV to 0.77 eV at various temperatures. The conduction band offset (ΔE c) of HfO2/β-Ga2O3 is extracted to be 1.31  ±  0.05 eV via x-ray photoelectron spectroscopy, while a large negative sheet charge density of 1.04  ×  1013 cm-2 is induced at the oxide layer and/or HfO2/β-Ga2O3 interface. A low C-V hysteresis of 0.76 V, low interface state density (D it) close to 1  ×  1012 eV-1 cm-2, and low leakage current density of 2.38  ×  10-5 A cm-2 at a gate voltage of 7 V has been obtained, suggesting the great electrical properties of HfO2/β-Ga2O3 MOSCAP. According to the above analysis, ALD-HfO2 is an attractive candidate for high voltage β-Ga2O3 power devices.

Top-gate dielectric induced doping and scattering of charge carriers in epitaxial graphene

Science.gov (United States)

Puls, Conor P.; Staley, Neal E.; Moon, Jeong-Sun; Robinson, Joshua A.; Campbell, Paul M.; Tedesco, Joseph L.; Myers-Ward, Rachael L.; Eddy, Charles R.; Gaskill, D. Kurt; Liu, Ying

2011-07-01

We show that an e-gun deposited dielectric impose severe limits on epitaxial graphene-based device performance based on Raman spectroscopy and low-temperature transport measurements. Specifically, we show from studies of epitaxial graphene Hall bars covered by SiO2 that the measured carrier density is strongly inhomogenous and predominantly induced by charged impurities at the grapheme/dielectric interface that limit mobility via Coulomb interactions. Our work emphasizes that material integration of epitaxial graphene and a gate dielectric is the next major road block towards the realization of graphene-based electronics.

Carbon nanotube transistors with graphene oxide films as gate dielectrics

Institute of Scientific and Technical Information of China (English)

无

2010-01-01

Carbon nanomaterials,including the one-dimensional(1-D) carbon nanotube(CNT) and two-dimensional(2-D) graphene,are heralded as ideal candidates for next generation nanoelectronics.An essential component for the development of advanced nanoelectronics devices is processing-compatible oxide.Here,in analogy to the widespread use of silicon dioxide(SiO2) in silicon microelectronic industry,we report the proof-of-principle use of graphite oxide(GO) as a gate dielectrics for CNT field-effect transistor(FET) via a fast and simple solution-based processing in the ambient condition.The exceptional transistor characteristics,including low operation voltage(2 V),high carrier mobility(950 cm2/V-1 s-1),and the negligible gate hysteresis,suggest a potential route to the future all-carbon nanoelectronics.

Suspended HfO2 photonic crystal slab on III-nitride/Si platform

International Nuclear Information System (INIS)

Wang, Yongjin; Feng, Jiao; Cao, Ziping; Zhu, Hongbo

2014-01-01

We present here the fabrication of suspended hafnium oxide (HfO 2 ) photonic crystal slab on a III-nitride/Si platform. The calculations are performed to model the suspended HfO 2 photonic crystal slab. Aluminum nitride (AlN) film is employed as the sacrificial layer to form air gap. Photonic crystal patterns are defined by electron beam lithography and transferred into HfO 2 film, and suspended HfO 2 photonic crystal slab is achieved on a III-nitride/Si platform through wet-etching of AlN layer in the alkaline solution. The method is promising for the fabrication of suspended HfO 2 nanostructures incorporating into a III-nitride/Si platform, or acting as the template for epitaxial growth of III-nitride materials. (orig.)

Depletion-mode vertical Ga2O3 trench MOSFETs fabricated using Ga2O3 homoepitaxial films grown by halide vapor phase epitaxy

Science.gov (United States)

Sasaki, Kohei; Thieu, Quang Tu; Wakimoto, Daiki; Koishikawa, Yuki; Kuramata, Akito; Yamakoshi, Shigenobu

2017-12-01

We developed depletion-mode vertical Ga2O3 trench metal-oxide-semiconductor field-effect transistors by using n+ contact and n- drift layers. These epilayers were grown on an n+ (001) Ga2O3 single-crystal substrate by halide vapor phase epitaxy. Cu and HfO2 were used for the gate metal and dielectric film, respectively. The mesa width and gate length were approximately 2 and 1 µm, respectively. The devices showed good DC characteristics, with a specific on-resistance of 3.7 mΩ cm2 and clear current modulation. An on-off ratio of approximately 103 was obtained.

Influence of gate dielectric on the ambipolar characteristics of solution-processed organic field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Ribierre, J C; Ghosh, S; Takaishi, K; Muto, T; Aoyama, T, E-mail: jcribierre@ewha.ac.kr, E-mail: taoyama@riken.jp [Advanced Science Institute, RIKEN, 2-1 Hirosawa, Wako, Saitama 351-0198 (Japan)

2011-05-25

Solution-processed ambipolar organic field-effect transistors based on dicyanomethylene-substituted quinoidal quaterthiophene derivative [QQT(CN)4] are fabricated using various gate dielectric materials including cross-linked polyimide and poly-4-vinylphenol. Devices with spin-coated polymeric gate dielectric layers show a reduced hysteresis in their transfer characteristics. Among the insulating polymers examined in this study, a new fluorinated polymer with a low dielectric constant of 2.8 significantly improves both hole and electron field-effect mobilities of QQT(CN)4 thin films to values as high as 0.04 and 0.002 cm{sup 2} V{sup -1} s{sup -1}. These values are close to the best mobilities obtained in QQT(CN)4 devices fabricated on SiO{sub 2} treated with octadecyltrichlorosilane. The influence of the metal used for source/drain metal electrodes on the device performance is also investigated. Whereas best device performances are achieved with gold electrodes, more balanced electron and hole field-effect mobilities could be obtained using chromium.

Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

Science.gov (United States)

Jayanti, Srikant

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

OpenAIRE

Roeckerath, M.; Lopes, J. M. J.; Durgun Özben, E.; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D.G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of < 1 nA/cm(2). Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated ...

Influence of Gate Dielectrics, Electrodes and Channel Width on OFET Characteristics

International Nuclear Information System (INIS)

Liyana, V P; Stephania, A M; Shiju, K; Predeep, P

2015-01-01

Organic Field Effect Transistors (OFET) possess wide applications in large area electronics owing to their attractive features like easy fabrication process, light weight, flexibility, cost effectiveness etc. But instability, high operational voltages and low carrier mobility act as inhibitors to commercialization of OFETs and various approaches were tried on a regular basis so as to make it viable. In this work, Poly 3-hexylthiophene-2,5diyl (P3HT) based OFETs with bottom-contact top-gate configuration using Poly vinyl alcohol (PVA) and Poly (methyl methacrylate) (PMMA) as gate dielectrics, aluminium and copper as source-drain electrodes are investigated. An effort is made to compare the effect of these dielectric materials and electrodes on the performance of OFET. Also, an attempt has been made to optimize the channel width of the device. These devices are characterised with mobility (μ), threshold voltage (V T ), on-off ratio (I on /I off ) and their comparative analysis is reported. (paper)

Influence of Gate Dielectrics, Electrodes and Channel Width on OFET Characteristics

Science.gov (United States)

Liyana, V. P.; Stephania, A. M.; Shiju, K.; Predeep, P.

2015-06-01

Organic Field Effect Transistors (OFET) possess wide applications in large area electronics owing to their attractive features like easy fabrication process, light weight, flexibility, cost effectiveness etc. But instability, high operational voltages and low carrier mobility act as inhibitors to commercialization of OFETs and various approaches were tried on a regular basis so as to make it viable. In this work, Poly 3-hexylthiophene-2,5diyl (P3HT) based OFETs with bottom-contact top-gate configuration using Poly vinyl alcohol (PVA) and Poly (methyl methacrylate) (PMMA) as gate dielectrics, aluminium and copper as source-drain electrodes are investigated. An effort is made to compare the effect of these dielectric materials and electrodes on the performance of OFET. Also, an attempt has been made to optimize the channel width of the device. These devices are characterised with mobility (μ), threshold voltage (VT), on-off ratio (Ion/Ioff) and their comparative analysis is reported.

Nano-CMOS gate dielectric engineering

CERN Document Server

Wong, Hei

2011-01-01

According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance

Science.gov (United States)

Anand, Sunny; Sarin, R. K.

2017-02-01

In this paper, charge-plasma-based tunnel FET is proposed by employing dual material gate with hetero gate dielectric technique and it is named hetero-dielectric dual material gate doping-less TFET (HD_DMG_DLTFET). It is compared with conventional doping-less TFET (DLTFET) and dual material gate doping-less TFET (DMG_DLTFET) on the basis of analog and RF performance. The HD_DMG_DLTFET provides better ON state current ({I}\\text{ON}=94 μ \\text{A}/μ \\text{m}), {I}\\text{ON}/{I}\\text{OFF}(≈ 1.36× {10}13), \\text{point} (≈ 3\\text{mV}/\\text{dec}) and average subthreshold slope (\\text{AV}-\\text{SS}=40.40 \\text{mV}/\\text{dec}). The proposed device offers low total gate capacitance (C gg) along with higher drive current. However, with a better transconductance (g m) and cut-off frequency (f T), the HD_DMG_DLTFET can be a good candidate for RF circuitry. The early voltage (V EA) and output conductance (g d) are also moderate for the proposed device with comparison to other devices and therefore can be a candidate for analog devices. From all these simulation results and their study, it is observed that HD_DMG_DLTFET has improved analog/RF performance compared to DLTFET and DMG_DLTFET.

Plasma nitridation optimization for sub-15 A gate dielectrics

NARCIS (Netherlands)

Cubaynes, F.N; Schmitz, Jurriaan; van der Marel, C.; Snijders, J.H.M.; Veloso, A.; Rothschild, A.; Olsen, C.; Date, L.

The work investigates the impact of plasma nitridation process parameters upon the physical properties and upon the electrical performance of sub-15 A plasma nitrided gate dielectrics. The nitrogen distribution and chemical bonding of ultra-thin plasma nitrided films have been investigated using

Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Tari, Alireza, E-mail: atari@uwaterloo.ca; Lee, Czang-Ho; Wong, William S. [Department of Electrical and Computer Engineering, University of Waterloo, 200 University Avenue West, Waterloo, Ontario N2L 3G1 (Canada)

2015-07-13

Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer into the IGZO and resulted in higher resistivity films.

High carrier mobility of CoPc wires based field-effect transistors using bi-layer gate dielectric

Directory of Open Access Journals (Sweden)

Murali Gedda

2013-11-01

Full Text Available Polyvinyl alcohol (PVA and anodized Al2O3 layers were used as bi-layer gate for the fabrication of cobalt phthalocyanine (CoPc wire base field-effect transistors (OFETs. CoPc wires were grown on SiO2 surfaces by organic vapor phase deposition method. These devices exhibit a field-effect carrier mobility (μEF value of 1.11 cm2/Vs. The high carrier mobility for CoPc molecules is attributed to the better capacitive coupling between the channel of CoPc wires and the gate through organic-inorganic dielectric layer. Our measurements also demonstrated the way to determine the thicknesses of the dielectric layers for a better process condition of OFETs.

Formation of Al2O3-HfO2 Eutectic EBC Film on Silicon Carbide Substrate

Directory of Open Access Journals (Sweden)

Kyosuke Seya

2015-01-01

Full Text Available The formation mechanism of Al2O3-HfO2 eutectic structure, the preparation method, and the formation mechanism of the eutectic EBC layer on the silicon carbide substrate are summarized. Al2O3-HfO2 eutectic EBC film is prepared by optical zone melting method on the silicon carbide substrate. At high temperature, a small amount of silicon carbide decomposed into silicon and carbon. The components of Al2O3 and HfO2 in molten phase also react with the free carbon. The Al2O3 phase reacts with free carbon and vapor species of AlO phase is formed. The composition of the molten phase becomes HfO2 rich from the eutectic composition. HfO2 phase also reacts with the free carbon and HfC phase is formed on the silicon carbide substrate; then a high density intermediate layer is formed. The adhesion between the intermediate layer and the substrate is excellent by an anchor effect. When the solidification process finished before all of HfO2 phase is reduced to HfC phase, HfC-HfO2 functionally graded layer is formed on the silicon carbide substrate and the Al2O3-HfO2 eutectic structure grows from the top of the intermediate layer.

High performance top-gated indium–zinc–oxide thin film transistors with in-situ formed HfO{sub 2} gate insulator

Energy Technology Data Exchange (ETDEWEB)

Song, Yang, E-mail: yang_song@brown.edu [Department of Physics, Brown University, 182 Hope Street, Providence, RI 02912 (United States); Zaslavsky, A. [Department of Physics, Brown University, 182 Hope Street, Providence, RI 02912 (United States); School of Engineering, Brown University, 184 Hope Street, Providence, RI 02912 (United States); Paine, D.C. [School of Engineering, Brown University, 184 Hope Street, Providence, RI 02912 (United States)

2016-09-01

We report on top-gated indium–zinc–oxide (IZO) thin film transistors (TFTs) with an in-situ formed HfO{sub 2} gate dielectric insulator. Building on our previous demonstration of high-performance IZO TFTs with Al{sub 2}O{sub 3}/HfO{sub 2} gate dielectric, we now report on a one-step process, in which Hf is evaporated onto the 20 nm thick IZO channel, forming a partially oxidized HfO{sub x} layer, without any additional insulator in-between. After annealing in air at 300 °C, the in-situ reaction between partially oxidized Hf and IZO forms a high quality HfO{sub 2} gate insulator with a low interface trapped charge density N{sub TC} ~ 2.3 × 10{sup 11} cm{sup −2} and acceptably low gate leakage < 3 × 10{sup −7} A/cm{sup 2} at gate voltage V{sub G} = 1 V. The annealed TFTs with gate length L{sub G} = 50 μm have high mobility ~ 95 cm{sup 2}/V ∙ s (determined via the Y-function technique), high on/off ratio ~ 10{sup 7}, near-zero threshold voltage V{sub T} = − 0.02 V, and a subthreshold swing of 0.062 V/decade, near the theoretical limit. The on-current of our proof-of-concept TFTs is relatively low, but can be improved by reducing L{sub G}, indicating that high-performance top-gated HfO{sub 2}-isolated IZO TFTs can be fabricated using a single-step in-situ dielectric formation approach. - Highlights: • High-performance indium–zinc–oxide (IZO) thin film transistors (TFTs). • Single-step in-situ dielectric formation approach simplifies fabrication process. • During anneal, reaction between HfO{sub x} and IZO channel forms a high quality HfO{sub 2} layer. • Gate insulator HfO{sub 2} shows low interface trapped charge and small gate leakage. • TFTs have high mobility, near-zero threshold voltage, and a low subthreshold swing.

Interface Engineering and Gate Dielectric Engineering for High Performance Ge MOSFETs

Directory of Open Access Journals (Sweden)

Jiabao Sun

2015-01-01

Full Text Available In recent years, germanium has attracted intensive interests for its promising applications in the microelectronics industry. However, to achieve high performance Ge channel devices, several critical issues still have to be addressed. Amongst them, a high quality gate stack, that is, a low defect interface layer and a dielectric layer, is of crucial importance. In this work, we first review the existing methods of interface engineering and gate dielectric engineering and then in more detail we discuss and compare three promising approaches (i.e., plasma postoxidation, high pressure oxidation, and ozone postoxidation. It has been confirmed that these approaches all can significantly improve the overall performance of the metal-oxide-semiconductor field effect transistor (MOSFET device.

Low operating voltage n-channel organic field effect transistors using lithium fluoride/PMMA bilayer gate dielectric

Energy Technology Data Exchange (ETDEWEB)

Kumar, S.; Dhar, A., E-mail: adhar@phy.iitkgp.ernet.in

2015-10-15

Highlights: • Alternative to chemically crosslinking of PMMA to achieve low leakage in provided. • Effect of LiF in reducing gate leakage through the OFET device is studied. • Effect of gate leakage on transistor performance has been investigated. • Low voltage operable and low temperature processed n-channel OFETs were fabricated. - Abstract: We report low temperature processed, low voltage operable n-channel organic field effect transistors (OFETs) using N,N′-Dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C{sub 8}) organic semiconductor and poly(methylmethacrylate) (PMMA)/lithium fluoride (LiF) bilayer gate dielectric. We have studied the role of LiF buffer dielectric in effectively reducing the gate leakage through the device and thus obtaining superior performance in contrast to the single layer PMMA dielectric devices. The bilayer OFET devices had a low threshold voltage (V{sub t}) of the order of 5.3 V. The typical values of saturation electron mobility (μ{sub s}), on/off ratio and inverse sub-threshold slope (S) for the range of devices made were estimated to be 2.8 × 10{sup −3} cm{sup 2}/V s, 385, and 3.8 V/decade respectively. Our work thus provides a potential substitution for much complicated process of chemically crosslinking PMMA to achieve low leakage, high capacitance, and thus low operating voltage OFETs.

Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

Directory of Open Access Journals (Sweden)

H. Hussin

2014-01-01

Full Text Available We present a simulation study on negative bias temperature instability (NBTI induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2 and hafnium oxide (HfO2 layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2 are increased but is reduced by 11% when the SiO2 interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2 interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated.

Effect of interfacial SiO2- y layer and defect in HfO2- x film on flat-band voltage of HfO2- x /SiO2- y stacks for backside-illuminated CMOS image sensors

Science.gov (United States)

Na, Heedo; Lee, Jimin; Jeong, Juyoung; Kim, Taeho; Sohn, Hyunchul

2018-03-01

In this study, the effect of oxygen gas fraction during deposition of a hafnium oxide (HfO2- x ) film and the influence of the quality of the SiO2- y interlayer on the nature of flat-band voltage ( V fb) in TiN/HfO/SiO2- y /p-Si structures were investigated. X-ray photoemission spectroscopy analysis showed that the non-lattice oxygen peak, indicating an existing oxygen vacancy, increased as the oxygen gas fraction decreased during sputtering. From C- V and J- E analyses, the V fb behavior was significantly affected by the characteristics of the SiO2- y interlayer and the non-lattice oxygen fraction in the HfO2- x films. The HfO2- x /native SiO2- y stack presented a V fb of - 1.01 V for HfO2- x films with an oxygen gas fraction of 5% during sputtering. Additionally, the V fb of the HfO2- x /native SiO2- y stack could be controlled from - 1.01 to - 0.56 V by changing the deposition conditions of the HfO2- x film with the native SiO2- y interlayer. The findings of this study can be useful to fabricate charge-accumulating layers for backside-illuminated image sensor devices.

Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

Science.gov (United States)

Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

2018-01-01

Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

Device performance of in situ steam generated gate dielectric nitrided by remote plasma nitridation

International Nuclear Information System (INIS)

Al-Shareef, H. N.; Karamcheti, A.; Luo, T. Y.; Bersuker, G.; Brown, G. A.; Murto, R. W.; Jackson, M. D.; Huff, H. R.; Kraus, P.; Lopes, D.

2001-01-01

In situ steam generated (ISSG) oxides have recently attracted interest for use as gate dielectrics because of their demonstrated reliability improvement over oxides formed by dry oxidation. [G. Minor, G. Xing, H. S. Joo, E. Sanchez, Y. Yokota, C. Chen, D. Lopes, and A. Balakrishna, Electrochem. Soc. Symp. Proc. 99-10, 3 (1999); T. Y. Luo, H. N. Al-Shareef, G. A. Brown, M. Laughery, V. Watt, A. Karamcheti, M. D. Jackson, and H. R. Huff, Proc. SPIE 4181, 220 (2000).] We show in this letter that nitridation of ISSG oxide using a remote plasma decreases the gate leakage current of ISSG oxide by an order of magnitude without significantly degrading transistor performance. In particular, it is shown that the peak normalized transconductance of n-channel devices with an ISSG oxide gate dielectric decreases by only 4% and the normalized drive current by only 3% after remote plasma nitridation (RPN). In addition, it is shown that the reliability of the ISSG oxide exhibits only a small degradation after RPN. These observations suggest that the ISSG/RPN process holds promise for gate dielectric applications. [copyright] 2001 American Institute of Physics

SIMS study of oxygen diffusion in monoclinic HfO2

Science.gov (United States)

Mueller, Michael P.; De Souza, Roger A.

2018-01-01

The diffusion of oxygen in dense ceramics of monoclinic HfO2 was studied by means of (18O/16O) isotope exchange annealing and subsequent determination of isotope depth profiles by Secondary Ion Mass Spectrometry. Anneals were performed in the temperature range of 573 ≤T /K ≤ 973 at an oxygen partial pressure of p O2=200 mbar . All measured isotope profiles exhibited two features: the first feature, closer to the surface, was attributed mainly to slow oxygen diffusion in an impurity silicate phase; the second feature, deeper in the sample, was attributed to oxygen diffusion in bulk monoclinic HfO2 . The activation enthalpy of oxygen tracer diffusion in bulk HfO2 was found to be ΔHD∗≈0.5 eV .

Structural, morphological, optical and photoluminescence properties of HfO2 thin films

International Nuclear Information System (INIS)

Ma, C.Y.; Wang, W.J.; Wang, J.; Miao, C.Y.; Li, S.L.; Zhang, Q.Y.

2013-01-01

Nanocrystalline monoclinic HfO 2 films with an average crystal size of 4.2–14.8 nm were sputter deposited under controlled temperatures and their structural characteristics and optical and photoluminescence properties have been evaluated. Structural investigations indicate that monoclinic HfO 2 films grown at higher temperatures above 400 °C are highly oriented along the (− 111) direction. The lattice expansion increases with diminishing HfO 2 crystalline size below 6.8 nm while maximum lattice expansion occurs with highly oriented monoclinic HfO 2 of crystalline size about 14.8 nm. The analysis of atomic force microscopy shows that the film growth at 600 °C can be attributed to the surface-diffusion-dominated growth. The intensity of the shoulderlike band that initiates at ∼ 5.7 eV and saturates at 5.94 eV shows continued increase with increasing crystalline size, which is intrinsic to nanocrystalline monoclinic HfO 2 films. Optical band gap varies in the range 5.40 ± 0.03–5.60 ± 0.03 eV and is slightly decreased with the increase in crystalline size. The luminescence band at 4.0 eV of HfO 2 films grown at room temperature can be ascribed to the vibronic transition of excited OH · radical while the emission at 3.2–3.3 eV for the films grown at all temperatures was attributed to the radiative recombination at impurity and/or defect centers. - Highlights: • Nanocrystalline monoclinic HfO 2 films were sputter deposited. • Structural, optical and photoluminescence properties were studied. • To analyze the scaling behavior using the power spectral density • Optical and photoluminescence properties strongly depend on film growth temperature

Depth Profiling of La2O3 ∕ HfO2 Stacked Dielectrics for Nanoelectronic Device Applications

KAUST Repository

Alshareef, Husam N.

2011-01-03

Nanoscale La2O3 /HfO2 dielectric stacks have been studied using high resolution Rutherford backscattering spectrometry. The measured distance of the tail-end of the La signal from the dielectric/Si interface suggests that the origin of the threshold voltage shifts and the carrier mobility degradation may not be the same. Up to 20% drop in mobility and 500 mV shift in threshold voltage was observed as the La signal reached the Si substrate. Possible reasons for these changes are proposed, aided by depth profiling and bonding analysis. © 2011 The Electrochemical Society.

Biotransformation of 2,3,3,3-tetrafluoropropene (HFO-1234yf)

International Nuclear Information System (INIS)

Schuster, Paul; Bertermann, Ruediger; Snow, Timothy A.; Han Xing; Rusch, George M.; Jepson, Gary W.; Dekant, Wolfgang

2008-01-01

2,3,3,3-Tetrafluoropropene (HFO-1234yf) is a non-ozone-depleting fluorocarbon replacement with a low global warming potential which has been developed as refrigerant. The biotransformation of HFO-1234yf was investigated after inhalation exposure. Male Sprague-Dawley rats were exposed to air containing 2000, 10,000, or 50,000 ppm HFO-1234yf for 6 h and male B6C3F1 mice were exposed to 50,000 ppm HFO-1234yf for 3.5 h in a dynamic exposure chamber (n = 5/concentration). After the end of the exposure, animals were individually housed in metabolic cages and urines were collected at 6 or 12-hour intervals for 48 h. For metabolite identification, urine samples were analyzed by 1 H-coupled and decoupled 19 F-NMR and by LC/MS-MS or GC/MS. Metabolites were identified by 19 F-NMR chemical shifts, signal multiplicity, 1 H- 19 F coupling constants and by comparison with synthetic reference compounds. In all urine samples, the predominant metabolites were two diastereomers of N-acetyl-S-(3,3,3-trifluoro-2-hydroxy-propyl)-L-cysteine. In 19 F-NMR, the signal intensity of these metabolites represented more than 85% (50,000 ppm) of total 19 F related signals in the urine samples. Trifluoroacetic acid, 3,3,3-trifluorolactic acid, 3,3,3-trifluoro-1-hydroxyacetone, 3,3,3-trifluoroacetone and 3,3,3-trifluoro-1,2-dihydroxypropane were present as minor metabolites. Quantification of N-acetyl-S-(3,3,3-trifluoro-2-hydroxy-propyl)-L-cysteine by LC/MS-MS showed that most of this metabolite (90%) was excreted within 18 h after the end of exposure (t 1/2 app. 6 h). In rats, the recovery of N-acetyl-S-(3,3,3-trifluoro-2-hydroxy-propyl)-L-cysteine excreted within 48 h in urine was determined as 0.30 ± 0.03, 0.63 ± 0.16, and 2.43 ± 0.86 μmol at 2000, 10,000 and 50,000 ppm, respectively suggesting only a low extent (<< 1% of dose received) of biotransformation of HFO-1234yf. In mice, the recovery of this metabolite was 1.774 ± 0.4 μmol. Metabolites identified after in vitro incubations of HFO

Mechanistic Insight into the Stability of HfO2-Coated MoS2 Nanosheet Anodes for Sodium Ion Batteries

KAUST Repository

Ahmed, Bilal; Anjum, Dalaver H.; Hedhili, Mohamed N.; Alshareef, Husam N.

2015-01-01

It is demonstrated for the first time that surface passivation of 2D nanosheets of MoS2 by an ultrathin and uniform layer of HfO2 can significantly improve the cyclic performance of sodium ion batteries. After 50 charge/discharge cycles, bare MoS2 and HfO2 coated MoS2 electrodes deliver the specific capacity of 435 and 636 mAh g-1, respectively, at current density of 100 mA g-1. These results imply that batteries using HfO2 coated MoS2 anodes retain 91% of the initial capacity; in contrast, bare MoS2 anodes retain only 63%. Also, HfO2 coated MoS2 anodes show one of the highest reported capacity values for MoS2. Cyclic voltammetry and X-ray photoelectron spectroscopy results suggest that HfO2 does not take part in electrochemical reaction. The mechanism of capacity retention with HfO2 coating is explained by ex situ transmission electron microscope imaging and electrical impedance spectroscopy. It is illustrated that HfO2 acts as a passivation layer at the anode/electrolyte interface and prevents structural degradation during charge/discharge process. Moreover, the amorphous nature of HfO2 allows facile diffusion of Na ions. These results clearly show the potential of HfO2 coated MoS2 anodes, which performance is significantly higher than previous reports where bulk MoS2 or composites of MoS2 with carbonaceous materials are used. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Mechanistic Insight into the Stability of HfO2-Coated MoS2 Nanosheet Anodes for Sodium Ion Batteries

KAUST Repository

Ahmed, Bilal

2015-06-01

It is demonstrated for the first time that surface passivation of 2D nanosheets of MoS2 by an ultrathin and uniform layer of HfO2 can significantly improve the cyclic performance of sodium ion batteries. After 50 charge/discharge cycles, bare MoS2 and HfO2 coated MoS2 electrodes deliver the specific capacity of 435 and 636 mAh g-1, respectively, at current density of 100 mA g-1. These results imply that batteries using HfO2 coated MoS2 anodes retain 91% of the initial capacity; in contrast, bare MoS2 anodes retain only 63%. Also, HfO2 coated MoS2 anodes show one of the highest reported capacity values for MoS2. Cyclic voltammetry and X-ray photoelectron spectroscopy results suggest that HfO2 does not take part in electrochemical reaction. The mechanism of capacity retention with HfO2 coating is explained by ex situ transmission electron microscope imaging and electrical impedance spectroscopy. It is illustrated that HfO2 acts as a passivation layer at the anode/electrolyte interface and prevents structural degradation during charge/discharge process. Moreover, the amorphous nature of HfO2 allows facile diffusion of Na ions. These results clearly show the potential of HfO2 coated MoS2 anodes, which performance is significantly higher than previous reports where bulk MoS2 or composites of MoS2 with carbonaceous materials are used. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Tungsten trioxide as high-{kappa} gate dielectric for highly transparent and temperature-stable zinc-oxide-based thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Lorenz, Michael; Wenckstern, Holger von; Grundmann, Marius [Universitaet Leipzig, Fakultaet fuer Physik und Geowissenschaften, Institut fuer Experimentelle Physik II, Linnestr. 5, 04103 Leipzig (Germany)

2012-07-01

We demonstrate metal-insulator-semiconductor field-effect transistors with high-{kappa}, room-temperature deposited, highly transparent tungsten trioxide (WO{sub 3}) as gate dielectric. The channel material consists of a zinc oxide (ZnO) thin-film. The transmittance and resistivity of WO{sub 3} films was tuned in order to obtain a highly transparent and insulating WO{sub 3} dielectric. The devices were processed by standard photolithography using lift-off technique. On top of the WO{sub 3} dielectric a highly transparent and conductive oxide consisting of ZnO: Al 3% wt. was deposited. The gate structure of the devices exhibits an average transmittance in the visible spectral range of 86%. The on/off-current ratio is larger than 10{sup 8} with off- and gate leakage-currents below 3 x 10{sup -8} A/cm{sup 2}. Due to the high relative permittivity of {epsilon}{sub r} {approx} 70, a gate voltage sweep of only 2 V is necessary to turn the transistor on and off with a minimum subthreshold swing of 80 mV/decade. The channel mobility of the transistors equals the Hall-effect mobility with a value of 5 cm{sup 2}/Vs. It is furthermore shown, that the devices are stable up to operating temperatures of at least 150 C.

Sol–gel deposited ceria thin films as gate dielectric for CMOS ...

Indian Academy of Sciences (India)

Sol–gel deposited ceria thin films as gate dielectric for CMOS technology. ANIL G KHAIRNAR ... The semiconductor roadmap following Moore's law is responsible for ..... The financial support from University Grants Commi- ssion (UGC), New ...

Preparation and characterization of Ce-doped HfO2 nanoparticles

International Nuclear Information System (INIS)

Gálvez-Barboza, S.; González, L.A.; Puente-Urbina, B.A.; Saucedo-Salazar, E.M.; García-Cerda, L.A.

2015-01-01

Highlights: • Ce-doped HfO 2 nanoparticles were prepared by a modified solgel method. • Ce-doped HfO 2 nanoparticles have a semispherical shape with sizes between 6 and 11.5 nm. • The samples doped with 10% in weight of Ce directly crystallized in a cubic structure. • A quick, straightforward and effective route for the preparation of Ce-doped nanoparticles. - Abstract: A modified solgel method to synthesize Ce-doped HfO 2 nanoparticles was carried out using a precursor material prepared with cerium nitrate, hafnium chloride, citric acid and ethylene glycol. The obtained precursor material was calcined at 500 and 700 °C for 2 h in air. The influence of the concentration of Ce and the calcination temperature was studied to observe the structural and morphological changes of the obtained materials. For the characterization, X-ray diffraction (XRD), transmission electron microscopy (TEM) and Raman scattering (RS) were employed. The XRD patterns shown that the Ce-doped HfO 2 undergoes a structural transformation from monoclinic to cubic phase, which is significantly dependent on the Ce content and calcination temperature. TEM images have also confirmed the existence of semispherical nanoparticles with sizes between 6 and 11.5 nm

Temperature-dependent field-effect carrier mobility in organic thin-film transistors with a gate SiO2 dielectric modified by H2O2 treatment

Science.gov (United States)

Lin, Yow-Jon; Hung, Cheng-Chun

2018-02-01

The effect of the modification of a gate SiO2 dielectric using an H2O2 solution on the temperature-dependent behavior of carrier transport for pentacene-based organic thin-film transistors (OTFTs) is studied. H2O2 treatment leads to the formation of Si(-OH) x (i.e., the formation of a hydroxylated layer) on the SiO2 surface that serves to reduce the SiO2 capacitance and weaken the pentacene-SiO2 interaction, thus increasing the field-effect carrier mobility ( µ) in OTFTs. The temperature-dependent behavior of carrier transport is dominated by the multiple trapping model. Note that H2O2 treatment leads to a reduction in the activation energy. The increased value of µ is also attributed to the weakening of the interactions of the charge carriers with the SiO2 dielectric that serves to reduce the activation energy.

Effect of oxide charge trapping on x-ray photoelectron spectroscopy of HfO2/SiO2/Si structures

International Nuclear Information System (INIS)

Abe, Yasuhiro; Miyata, Noriyuki; Suzuki, Haruhiko; Kitamura, Koji; Igarashi, Satoru; Nohira, Hiroshi; Ikenaga, Eiji

2009-01-01

We examined the effects of interfacial SiO 2 layers and a surface metal layer on the photoelectron spectra of HfO 2 /SiO 2 /Si structures by hard X-ray photoemission spectroscopy with synchrotron radiation as well as conventional X-ray photoelectron spectroscopy (XPS). The Hf 4f and Hf 3d photoelectron peaks broadened and shifted toward a higher binding energy with increasing thickness of the interfacial SiO 2 layer, even though photoelectrons may have been emitted from the HfO 2 layer with the same chemical composition. Thinning the interfacial Si oxide layer to approximately one monolayer and depositing a metal layer on the HfO 2 surface suppressed these phenomena. The O 1s photoelectron spectra revealed marked differences between the metal- and nonmetal-deposited HfO 2 /SiO 2 /Si structures; HfO 2 and SiO 2 components in the O 1s photoelectron spectra for the metal-deposited structures were observed at reasonably separated binding energies, but those for the nonmetal-deposited structures were not separated clearly. From this behavior concerning the effects of interfacial SiO 2 and surface metal layers, we concluded that the Hf 4f, Hf 3d, and O 1s spectra measured from the HfO 2 /SiO 2 /Si structures did not reflect actual chemical bonding states. We consider that potential variations in the HfO 2 film owing to charge trapping strongly affect the measured photoelectron spectra. On the basis of angle-resolved XPS measurements, we propose that positive charges are trapped at the HfO 2 surface and negative charges are trapped inside the HfO 2 layer. (author)

Influence of the oxygen/argon ratio on the properties of sputtered hafnium oxide

International Nuclear Information System (INIS)

Pereira, L.; Barquinha, P.; Fortunato, E.; Martins, R.

2005-01-01

In this work we have focused our attention on the role of the gas mixture (O 2 /Ar) used during HfO 2 thin film processing by r.f. magnetron sputtering, to produce dielectrics with suitable characteristics to be used as gate dielectric. Increasing the O 2 /Ar ratio from 0 to 0.2, the films properties (optical gap, permittivity, resistivity and compactness) are improved. At these conditions, films with a band gap around 5 eV were produced, indicating a good stoichiometry. Also the flat band voltage has a reduction of almost three times indicating also a reduction of the same order on the fixed charge density at the semiconductor-insulator interface. The dielectric constant is around 16 which is very good, since the surface of the silicon where the HfO 2 films were deposited contains a SiO 2 layer of about 3 nm that gives an effective dielectric constant above 20, close to the HfO 2 stoichiometric value (∼25). Further increase on the O 2 /Ar ratio does not produce significant improvements

SnO2 anode surface passivation by atomic layer deposited HfO2 improves li-ion battery performance

KAUST Repository

Yesibolati, Nulati

2014-03-14

For the first time, it is demonstrated that nanoscale HfO2 surface passivation layers formed by atomic layer deposition (ALD) significantly improve the performance of Li ion batteries with SnO2-based anodes. Specifically, the measured battery capacity at a current density of 150 mAg -1 after 100 cycles is 548 and 853 mAhg-1 for the uncoated and HfO2-coated anodes, respectively. Material analysis reveals that the HfO2 layers are amorphous in nature and conformably coat the SnO2-based anodes. In addition, the analysis reveals that ALD HfO2 not only protects the SnO2-based anodes from irreversible reactions with the electrolyte and buffers its volume change, but also chemically interacts with the SnO2 anodes to increase battery capacity, despite the fact that HfO2 is itself electrochemically inactive. The amorphous nature of HfO2 is an important factor in explaining its behavior, as it still allows sufficient Li diffusion for an efficient anode lithiation/delithiation process to occur, leading to higher battery capacity. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Low voltage operation of IGZO thin film transistors enabled by ultrathin Al2O3 gate dielectric

Science.gov (United States)

Ma, Pengfei; Du, Lulu; Wang, Yiming; Jiang, Ran; Xin, Qian; Li, Yuxiang; Song, Aimin

2018-01-01

An ultrathin, 5 nm, Al2O3 film grown by atomic-layer deposition was used as a gate dielectric for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The Al2O3 layer showed a low surface roughness of 0.15 nm, a low leakage current, and a high breakdown voltage of 6 V. In particular, a very high gate capacitance of 720 nF/cm2 was achieved, making it possible for the a-IGZO TFTs to not only operate at a low voltage of 1 V but also exhibit desirable properties including a low threshold voltage of 0.3 V, a small subthreshold swing of 100 mV/decade, and a high on/off current ratio of 1.2 × 107. Furthermore, even under an ultralow operation voltage of 0.6 V, well-behaved transistor characteristics were still observed with an on/off ratio as high as 3 × 106. The electron transport through the Al2O3 layer has also been analyzed, indicating the Fowler-Nordheim tunneling mechanism.

Integration of atomic layer deposited high-k dielectrics on GaSb via hydrogen plasma exposure

Directory of Open Access Journals (Sweden)

Laura B. Ruppalt

2014-12-01

Full Text Available In this letter we report the efficacy of a hydrogen plasma pretreatment for integrating atomic layer deposited (ALD high-k dielectric stacks with device-quality p-type GaSb(001 epitaxial layers. Molecular beam eptiaxy-grown GaSb surfaces were subjected to a 30 minute H2/Ar plasma treatment and subsequently removed to air. High-k HfO2 and Al2O3/HfO2 bilayer insulating films were then deposited via ALD and samples were processed into standard metal-oxide-semiconductor (MOS capacitors. The quality of the semiconductor/dielectric interface was probed by current-voltage and variable-frequency admittance measurements. Measurement results indicate that the H2-plamsa pretreatment leads to a low density of interface states nearly independent of the deposited dielectric material, suggesting that pre-deposition H2-plasma exposure, coupled with ALD of high-k dielectrics, may provide an effective means for achieving high-quality GaSb MOS structures for advanced Sb-based digital and analog electronics.

A threshold-voltage model for small-scaled GaAs nMOSFET with stacked high-k gate dielectric

International Nuclear Information System (INIS)

Liu Chaowen; Xu Jingping; Liu Lu; Lu Hanhan; Huang Yuan

2016-01-01

A threshold-voltage model for a stacked high-k gate dielectric GaAs MOSFET is established by solving a two-dimensional Poisson's equation in channel and considering the short-channel, DIBL and quantum effects. The simulated results are in good agreement with the Silvaco TCAD data, confirming the correctness and validity of the model. Using the model, impacts of structural and physical parameters of the stack high-k gate dielectric on the threshold-voltage shift and the temperature characteristics of the threshold voltage are investigated. The results show that the stacked gate dielectric structure can effectively suppress the fringing-field and DIBL effects and improve the threshold and temperature characteristics, and on the other hand, the influence of temperature on the threshold voltage is overestimated if the quantum effect is ignored. (paper)

Self-diffusion of Er and Hf inpure and HfO2-doped polycrystalline Er2O3

International Nuclear Information System (INIS)

Scheidecker, R.W.

1979-01-01

Using a tracer technique, self-diffusion of Er and Hf was measured over the approximate temperature interval of 1600 to 1970 0 C in pure and HfO 2 -doped polycryatalline Er 2 O 3 . Up to about 10 m/o HfO 2 dopant level, the Er self-diffusion coefficients followed a relationship based on cation vacancies. Above 10 m/o HfO 2 , deviation from this relationship occurred, apparently due to clustering of cation vacancies and oxygen interstitials around the dopant hafnia ion. The activation energy for the self-diffusion of Er in pure Er 2 O 3 was 82.2 Kcal/mole and increased with the HfO 2 dopant level present. Self-diffusion of Hf was measured in pure Er 2 O 3 having two impurity levels, and a separation of the grain boundary. The volume diffusion of Hf showed both extrinsic and intrinsic behavior with the transition temperature increasing with the impurity level present in Er 2 O 3 . The activation energy for Hf volume diffusion in the intrinsic region was high, i.e. 235 -+ 9.5 Kcal/mole. The grain boundary diffusion was apparently extrinsic over the entire temperature interval Very low Hf self diffusion rates were found in both pure and HfO 2 doped Er 2 O 3 compositions. Despite a clustering effect, the HfO 2 dopant increased the Hf volume diffusion coefficients

Study of high-k gate dielectrics by means of positron annihilation

International Nuclear Information System (INIS)

Uedono, A.; Naito, T.; Otsuka, T.; Ito, K.; Shiraishi, K.; Yamabe, K.; Miyazaki, S.; Watanabe, H.; Umezawa, N.; Hamid, A.; Chikyow, T.; Ohdaira, T.; Suzuki, R.; Ishibashi, S.; Inumiya, S.; Kamiyama, S.; Akasaka, Y.; Nara, Y.; Yamada, K.

2007-01-01

High-dielectric constant (high-k) gate materials, such as HfSiO x and HfAlO x , fabricated by atomic-layer-deposition techniques were characterized using monoenergetic positron beams. Measurements of the Doppler broadening spectra of annihilation radiation and the lifetime spectra of positrons indicated that positrons annihilated from the trapped state by open volumes that exist intrinsically in amorphous structures of the films. The size distributions of the open volumes and the local atomic configurations around such volumes can be discussed using positron annihilation parameters, and they were found to correlate with the electrical properties of the films. We confirmed that the positron annihilation is useful technique to characterize the matrix structure of amorphous high-k materials, and can be used to determine process parameters for the fabrication of high-k gate dielectrics. (copyright 2007 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Use of water vapor for suppressing the growth of unstable low-κ interlayer in HfTiO gate-dielectric Ge metal-oxide-semiconductor capacitors with sub-nanometer capacitance equivalent thickness

International Nuclear Information System (INIS)

Xu, J.P.; Zou, X.; Lai, P.T.; Li, C.X.; Chan, C.L.

2009-01-01

Annealing of high-permittivity HfTiO gate dielectric on Ge substrate in different gases (N 2 , NH 3 , NO and N 2 O) with or without water vapor is investigated. Analysis by transmission electron microscopy indicates that the four wet anneals can greatly suppress the growth of a GeO x interlayer at the dielectric/Ge interface, and thus decrease interface states, oxide charges and gate leakage current. Moreover, compared with the wet N 2 anneal, the wet NH 3 , NO and N 2 O anneals decrease the equivalent permittivity of the gate dielectric due to the growth of a GeO x N y interlayer. Among the eight anneals, the wet N 2 anneal produces the best dielectric performance with an equivalent relative permittivity of 35, capacitance equivalent thickness of 0.81 nm, interface-state density of 6.4 x 10 11 eV -1 cm -2 and gate leakage current of 2.7 x 10 -4 A/cm 2 at V g = 1 V

Modeling on oxide dependent 2DEG sheet charge density and threshold voltage in AlGaN/GaN MOSHEMT

Science.gov (United States)

Panda, J.; Jena, K.; Swain, R.; Lenka, T. R.

2016-04-01

We have developed a physics based analytical model for the calculation of threshold voltage, two dimensional electron gas (2DEG) density and surface potential for AlGaN/GaN metal oxide semiconductor high electron mobility transistors (MOSHEMT). The developed model includes important parameters like polarization charge density at oxide/AlGaN and AlGaN/GaN interfaces, interfacial defect oxide charges and donor charges at the surface of the AlGaN barrier. The effects of two different gate oxides (Al2O3 and HfO2) are compared for the performance evaluation of the proposed MOSHEMT. The MOSHEMTs with Al2O3 dielectric have an advantage of significant increase in 2DEG up to 1.2 × 1013 cm-2 with an increase in oxide thickness up to 10 nm as compared to HfO2 dielectric MOSHEMT. The surface potential for HfO2 based device decreases from 2 to -1.6 eV within 10 nm of oxide thickness whereas for the Al2O3 based device a sharp transition of surface potential occurs from 2.8 to -8.3 eV. The variation in oxide thickness and gate metal work function of the proposed MOSHEMT shifts the threshold voltage from negative to positive realizing the enhanced mode operation. Further to validate the model, the device is simulated in Silvaco Technology Computer Aided Design (TCAD) showing good agreement with the proposed model results. The accuracy of the developed calculations of the proposed model can be used to develop a complete physics based 2DEG sheet charge density and threshold voltage model for GaN MOSHEMT devices for performance analysis.

Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for Advanced CMOS Devices

Directory of Open Access Journals (Sweden)

Masamichi Suzuki

2012-03-01

Full Text Available A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3 high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process.

AlN and Al oxy-nitride gate dielectrics for reliable gate stacks on Ge and InGaAs channels

Energy Technology Data Exchange (ETDEWEB)

Guo, Y.; Li, H.; Robertson, J. [Engineering Department, Cambridge University, Cambridge CB2 1PZ (United Kingdom)

2016-05-28

AlN and Al oxy-nitride dielectric layers are proposed instead of Al{sub 2}O{sub 3} as a component of the gate dielectric stacks on higher mobility channels in metal oxide field effect transistors to improve their positive bias stress instability reliability. It is calculated that the gap states of nitrogen vacancies in AlN lie further away in energy from the semiconductor band gap than those of oxygen vacancies in Al{sub 2}O{sub 3}, and thus AlN might be less susceptible to charge trapping and have a better reliability performance. The unfavourable defect energy level distribution in amorphous Al{sub 2}O{sub 3} is attributed to its larger coordination disorder compared to the more symmetrically bonded AlN. Al oxy-nitride is also predicted to have less tendency for charge trapping.

A threshold-voltage model for small-scaled GaAs nMOSFET with stacked high-k gate dielectric

Science.gov (United States)

Chaowen, Liu; Jingping, Xu; Lu, Liu; Hanhan, Lu; Yuan, Huang

2016-02-01

A threshold-voltage model for a stacked high-k gate dielectric GaAs MOSFET is established by solving a two-dimensional Poisson's equation in channel and considering the short-channel, DIBL and quantum effects. The simulated results are in good agreement with the Silvaco TCAD data, confirming the correctness and validity of the model. Using the model, impacts of structural and physical parameters of the stack high-k gate dielectric on the threshold-voltage shift and the temperature characteristics of the threshold voltage are investigated. The results show that the stacked gate dielectric structure can effectively suppress the fringing-field and DIBL effects and improve the threshold and temperature characteristics, and on the other hand, the influence of temperature on the threshold voltage is overestimated if the quantum effect is ignored. Project supported by the National Natural Science Foundation of China (No. 61176100).

Optical properties of a HfO2/Si stack with a trace amount of nitrogen incorporation

Science.gov (United States)

Ye, Li; Tingting, Jiang; Qingqing, Sun; Pengfei, Wang; Shijin, Ding; Wei, Zhang

2012-03-01

HfO2 films were deposited by atomic layer deposition through alternating pulsing of Hf[N(C2H5)(CH3)]4 and H2O2. A trace amount of nitrogen was incorporated into the HfO2 through ammonia annealing. The composition, the interface stability of the HfO2/Si stack and the optical properties of the annealed films were analyzed to investigate the property evolution of HfO2 during thermal treatment. With a nitrogen concentration increase from 1.41 to 7.45%, the bandgap of the films decreased from 5.82 to 4.94 eV.

Valence band variation in Si (110) nanowire induced by a covered insulator

International Nuclear Information System (INIS)

Hong-Hua, Xu; Xiao-Yan, Liu; Yu-Hui, He; Gang, Du; Ru-Qi, Han; Jin-Feng, Kang; Chun, Fan; Ai-Dong, Sun

2010-01-01

In this work, we investigate strain effects induced by the deposition of gate dielectrics on the valence band structures in Si (110) nanowire via the simulation of strain distribution and the calculation of a generalized 6×6k·p strained valence band. The nanowire is surrounded by the gate dielectric. Our simulation indicates that the strain of the amorphous SiO 2 insulator is negligible without considering temperature factors. On the other hand, the thermal residual strain in a nanowire with amorphous SiO 2 insulator which has negligible lattice misfit strain pushes the valence subbands upwards by chemical vapour deposition and downwards by thermal oxidation treatment. In contrast with the strain of the amorphous SiO 2 insulator, the strain of the HfO 2 gate insulator in Si (110) nanowire pushes the valence subbands upwards remarkably. The thermal residual strain by HfO 2 insulator contributes to the up-shifting tendency. Our simulation results for valence band shifting and warping in Si nanowires can provide useful guidance for further nanowire device design. (classical areas of phenomenology)

Difference in Thermal Degradation Behavior of ZrO2 and HfO2 Anodized Capacitors

Science.gov (United States)

Kamijyo, Masahiro; Onozuka, Tomotake; Yoshida, Naoto; Shinkai, Satoko; Sasaki, Katsutaka; Yamane, Misao; Abe, Yoshio

2004-09-01

Microcrystalline ZrO2 and HfO2 thin film capacitors were prepared by anodizing sputter-deposited Zr and Hf films. The thermal degradation behavior of both anodized capacitors was clarified by the measurement of their capacitance properties and Auger depth profiles before and after heat treatment in air. As a result, it is confirmed that the heat-resistance property of the HfO2 anodized capacitor is superior to that of the ZrO2 capacitor. In addition, it is revealed that the thermal degradation of the ZrO2 anodized capacitor is caused by the diffusion of Zr atoms from the underlying layer into the ZrO2 anodized layer, while that of the HfO2 anodized capacitor is caused by the diffusion of oxygen atoms from the anodized layer into the underlying Hf layer.

Al2O3 Passivation Effect in HfO2·Al2O3 Laminate Structures Grown on InP Substrates.

Science.gov (United States)

Kang, Hang-Kyu; Kang, Yu-Seon; Kim, Dae-Kyoung; Baik, Min; Song, Jin-Dong; An, Youngseo; Kim, Hyoungsub; Cho, Mann-Ho

2017-05-24

The passivation effect of an Al 2 O 3 layer on the electrical properties was investigated in HfO 2 -Al 2 O 3 laminate structures grown on indium phosphide (InP) substrate by atomic-layer deposition. The chemical state obtained using high-resolution X-ray photoelectron spectroscopy showed that interfacial reactions were dependent on the presence of the Al 2 O 3 passivation layer and its sequence in the HfO 2 -Al 2 O 3 laminate structures. Because of the interfacial reaction, the Al 2 O 3 /HfO 2 /Al 2 O 3 structure showed the best electrical characteristics. The top Al 2 O 3 layer suppressed the interdiffusion of oxidizing species into the HfO 2 films, whereas the bottom Al 2 O 3 layer blocked the outdiffusion of In and P atoms. As a result, the formation of In-O bonds was more effectively suppressed in the Al 2 O 3 /HfO 2 /Al 2 O 3 /InP structure than that in the HfO 2 -on-InP system. Moreover, conductance data revealed that the Al 2 O 3 layer on InP reduces the midgap traps to 2.6 × 10 12 eV -1 cm -2 (compared to that of HfO 2 /InP, that is, 5.4 × 10 12 eV -1 cm -2 ). The suppression of gap states caused by the outdiffusion of In atoms significantly controls the degradation of capacitors caused by leakage current through the stacked oxide layers.

Oxygen vacancy defect engineering using atomic layer deposited HfAlOx in multi-layered gate stack

Science.gov (United States)

Bhuyian, M. N.; Sengupta, R.; Vurikiti, P.; Misra, D.

2016-05-01

This work evaluates the defects in high quality atomic layer deposited (ALD) HfAlOx with extremely low Al (estimated by the high temperature current voltage measurement shows that the charged oxygen vacancies, V+/V2+, are the primary source of defects in these dielectrics. When Al is added in HfO2, the V+ type defects with a defect activation energy of Ea ˜ 0.2 eV modify to V2+ type to Ea ˜ 0.1 eV with reference to the Si conduction band. When devices were stressed in the gate injection mode for 1000 s, more V+ type defects are generated and Ea reverts back to ˜0.2 eV. Since Al has a less number of valence electrons than do Hf, the change in the co-ordination number due to Al incorporation seems to contribute to the defect level modifications. Additionally, the stress induced leakage current behavior observed at 20 °C and at 125 °C demonstrates that the addition of Al in HfO2 contributed to suppressed trap generation process. This further supports the defect engineering model as reduced flat-band voltage shifts were observed at 20 °C and at 125 °C.

Semi-transparent a-IGZO thin-film transistors with polymeric gate dielectric.

Science.gov (United States)

Hyung, Gun Woo; Wang, Jian-Xun; Li, Zhao-Hui; Koo, Ja-Ryong; Kwon, Sang Jik; Cho, Eou-Sik; Kim, Young Kwan

2013-06-01

We report the fabrication of semi-transparent a-IGZO-based thin-film transistors (TFTs) with crosslinked poly-4-vinylphenol (PVP) gate dielectric layers on PET substrate and thermally-evaporated Al/Ag/Al source and drain (S&D) electrodes, which showed a transmittance of 64% at a 500-nm wavelength and sheet resistance of 16.8 omega/square. The semi-transparent a-IGZO TFTs with a PVP layer exhibited decent saturation mobilities (maximum approximately 5.8 cm2Ns) and on/off current ratios of approximately 10(6).

Effects of H2 High-pressure Annealing on HfO2/Al2O3/In0.53Ga0.47As Capacitors: Chemical Composition and Electrical Characteristics

OpenAIRE

Choi, Sungho; An, Youngseo; Lee, Changmin; Song, Jeongkeun; Nguyen, Manh-Cuong; Byun, Young-Chul; Choi, Rino; McIntyre, Paul C.; Kim, Hyoungsub

2017-01-01

We studied the impact of H2 pressure during post-metallization annealing on the chemical composition of a HfO2/Al2O3 gate stack on a HCl wet-cleaned In0.53Ga0.47As substrate by comparing the forming gas annealing (at atmospheric pressure with a H2 partial pressure of 0.04?bar) and H2 high-pressure annealing (H2-HPA at 30?bar) methods. In addition, the effectiveness of H2-HPA on the passivation of the interface states was compared for both p- and n-type In0.53Ga0.47As substrates. The decomposi...

Use of water vapor for suppressing the growth of unstable low-{kappa} interlayer in HfTiO gate-dielectric Ge metal-oxide-semiconductor capacitors with sub-nanometer capacitance equivalent thickness

Energy Technology Data Exchange (ETDEWEB)

Xu, J.P. [Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan, 430074 (China); Zou, X. [School of Electromachine and Architecture Engineering, Jianghan University, Wuhan, 430056 (China); Lai, P.T. [Department of Electrical and Electronic Engineering, University of Hong Kong, Pokfulam Road (Hong Kong)], E-mail: laip@eee.hku.hk; Li, C.X.; Chan, C.L. [Department of Electrical and Electronic Engineering, University of Hong Kong, Pokfulam Road (Hong Kong)

2009-03-02

Annealing of high-permittivity HfTiO gate dielectric on Ge substrate in different gases (N{sub 2}, NH{sub 3}, NO and N{sub 2}O) with or without water vapor is investigated. Analysis by transmission electron microscopy indicates that the four wet anneals can greatly suppress the growth of a GeO{sub x} interlayer at the dielectric/Ge interface, and thus decrease interface states, oxide charges and gate leakage current. Moreover, compared with the wet N{sub 2} anneal, the wet NH{sub 3}, NO and N{sub 2}O anneals decrease the equivalent permittivity of the gate dielectric due to the growth of a GeO{sub x}N{sub y} interlayer. Among the eight anneals, the wet N{sub 2} anneal produces the best dielectric performance with an equivalent relative permittivity of 35, capacitance equivalent thickness of 0.81 nm, interface-state density of 6.4 x 10{sup 11} eV{sup -1} cm{sup -2} and gate leakage current of 2.7 x 10{sup -4} A/cm{sup 2} at V{sub g} = 1 V.

Bio Organic-Semiconductor Field-Effect Transistor (BioFET) Based on Deoxyribonucleic Acid (DNA) Gate Dielectric

Science.gov (United States)

2010-03-31

floating gate devices and metal-insulator-oxide-semiconductor (MIOS) devices. First attempts to use polarizable gate insulators in combination with...bulk of the semiconductor (ii) Due to the polarizable gate dielectric (iii) dipole polarization and (iv)electret effect due to mobile ions in the...characterization was carried out under an argon environment inside the glove box. An Agilent model E5273A with a two source-measurement unit instrument was

Thermally-driven H interaction with HfO2 films deposited on Ge(100) and Si(100)

Science.gov (United States)

Soares, G. V.; Feijó, T. O.; Baumvol, I. J. R.; Aguzzoli, C.; Krug, C.; Radtke, C.

2014-01-01

In the present work, we investigated the thermally-driven H incorporation in HfO2 films deposited on Si and Ge substrates. Two regimes for deuterium (D) uptake were identified, attributed to D bonded near the HfO2/substrate interface region (at 300 °C) and through the whole HfO2 layer (400-600 °C). Films deposited on Si presented higher D amounts for all investigated temperatures, as well as, a higher resistance for D desorption. Moreover, HfO2 films underwent structural changes during annealings, influencing D incorporation. The semiconductor substrate plays a key role in this process.

Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process

International Nuclear Information System (INIS)

Wang Yanrong; Yang Hong; Xu Hao; Luo Weichun; Qi Luwei; Zhang Shuxiang; Wang Wenwu; Zhu Huilong; Zhao Chao; Chen Dapeng; Ye Tianchun; Yan Jiang

2017-01-01

In the process of high- k films fabrication, a novel multi deposition multi annealing (MDMA) technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing (PDA) times. The equivalent oxide thickness (EOT) decreases when the annealing time(s) change from 1 to 2. Furthermore, the characteristics of SILC (stress-induced leakage current) for an ultra-thin SiO 2 /HfO 2 gate dielectric stack are studied systematically. The increase of the PDA time(s) from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes. (paper)

Nanomechanical study of amorphous and polycrystalline ALD HfO2 thin films

Science.gov (United States)

K. Tapily; J.E. Jakes; D. Gu; H. Baumgart; A.A. Elmustafa

2011-01-01

Thin films of hafnium oxide (HfO2) were deposited by atomic layer deposition (ALD). The structural properties of the deposited films were characterised by transmission electron microscopy (TEM) and X-ray diffraction (XRD). We investigated the effect of phase transformations induced by thermal treatments on the mechanical properties of ALD HfO

Pressure-induced phase transformation of HfO2

International Nuclear Information System (INIS)

Arashi, H.

1992-01-01

This paper reports on the pressure dependence of the Raman spectra of HfO 2 that was measured by a micro-Raman technique using a single-crystal specimen in the pressure range from 0 to 10 GPa at room temperature. The symmetry assignment of Raman bands of the monoclinic phase was experimentally accomplished from the polarization measurements for the single crystal. With increased pressure, a phase transformation for the monoclinic phase took place at 4.3 ± 0.3 GPa. Nineteen Raman bands were observed for the high-pressure phase. The spectral structure of the Raman bands for the high-pressure phase was similar with those reported previously for ZrO 2 . The space group for the high pressure phase of HfO 2 was determined as Pbcm, which was the same as that of the high-pressure phase for ZrO 2 on the basis of the number and the spectral structure of the Raman bands

Influence of phosphorous precursors on spectroscopic properties of Er3+-activated SiO2-HfO2-P2O5 planar waveguides

International Nuclear Information System (INIS)

Vasilchenko, I; Carpentiero, A; Chiappini, A; Chiasera, A; Ferrari, M; Vaccari, A; Lukowiak, A; Righini, G C; Vereshagin, V

2014-01-01

(70-x)SiO 2 -30HfO 2 -xP 2 O 5 (x= 5, 10 mol %) glass planar waveguides activated by 0.5 mol% Er 3 + ions were prepared by sol-gel route. Several phosphorous precursors have been investigated for the synthesis of a dielectric stable sol useful for the realization of planar waveguides. The waveguides were investigated by different diagnostic techniques. The optical properties such as refractive index, thickness, number of propagating modes and attenuation coefficient were measured at 632.8 and 543.5 nm by prism coupling technique. Transmission measurements were carried out in order to assess the transparency of the deposited films. Photoluminescence measurements and lifetime decay curves of the Er 3 + transition (4 I 13/2 → 4 I 15/2 ) were performed in order to investigate the role of P 2 O 5

Electrical behaviour of fully solution processed HfO2 (MOS) in presence of different light illumination

Science.gov (United States)

Mondal, Sandip

2018-04-01

This experiment demonstrates the electrical behaviors of fully solution processed HfO2(MOS) in presence of different optical illumination. The capacitance voltage measurement was performed at frequency of 100 kHz with a DC gate sweep voltage of ±5V (with additional AC voltage of 100mV) in presence of deep UV (wavelength of 365nm with power of 25W) as well as white light (20W). It is found that there is a large shift in flatband voltage of 120mV due presence of white light during the CV measurement. However there is negligible change in flatband voltage (30mV) has been observed due to illumination of deep UV light.

High-temperature x-ray diffraction study of HfTiO4-HfO2 solid solutions

International Nuclear Information System (INIS)

Carpenter, D.A.

1975-01-01

High-temperature x-ray diffraction techniques were used to determine the axial thermal expansion curves of HfTiO 4 -HfO 2 solid solutions as a function of composition. Data show increasing anisotropy with increasing HfO 2 content. An orthorhombic-to-monoclinic phase transformation was detected near room temperature for compositions near the high HfO 2 end of the orthorhombic phase field and for compositions within the two-phase region (HfTiO 4 solid solution plus HfO 2 solid solution). An orthorhombic-to-cubic phase transformation is indicated by data from oxygen-deficient materials at greater than 1873 0 K. (U.S.)

Thermal Conductivity and Water Vapor Stability of Ceramic HfO2-Based Coating Materials

Science.gov (United States)

Zhu, Dong-Ming; Fox, Dennis S.; Bansal, Narottam P.; Miller, Robert A.

2004-01-01

HfO2-Y2O3 and La2Zr2O7 are candidate thermal/environmental barrier coating materials for gas turbine ceramic matrix composite (CMC) combustor liner applications because of their relatively low thermal conductivity and high temperature capability. In this paper, thermal conductivity and high temperature phase stability of plasma-sprayed coatings and/or hot-pressed HfO2-5mol%Y2O3, HfO2-15mol%Y2O3 and La2Zr2O7 were evaluated at temperatures up to 1700 C using a steady-state laser heat-flux technique. Sintering behavior of the plasma-sprayed coatings was determined by monitoring the thermal conductivity increases during a 20-hour test period at various temperatures. Durability and failure mechanisms of the HfO2-Y2O3 and La2Zr2O7 coatings on mullite/SiC Hexoloy or CMC substrates were investigated at 1650 C under thermal gradient cyclic conditions. Coating design and testing issues for the 1650 C thermal/environmental barrier coating applications will also be discussed.

Label Free Detection of Biomolecules Using Charge-Plasma-Based Gate Underlap Dielectric Modulated Junctionless TFET

Science.gov (United States)

Wadhwa, Girish; Raj, Balwinder

2018-05-01

Nanoscale devices are emerging as a platform for detecting biomolecules. Various issues were observed during the fabrication process such as random dopant fluctuation and thermal budget. To reduce these issues charge-plasma-based concept is introduced. This paper proposes the implementation of charge-plasma-based gate underlap dielectric modulated junctionless tunnel field effect transistor (DM-JLTFET) for the revelation of biomolecule immobilized in the open cavity gate channel region. In this p+ source and n+ drain regions are introduced by employing different work function over the intrinsic silicon. Also dual material gate architecture is implemented to reduce short channel effect without abandoning any other device characteristic. The sensitivity of biosensor is studied for both the neutral and charge-neutral biomolecules. The effect of device parameters such as channel thickness, cavity length and cavity thickness on drain current have been analyzed through simulations. This paper investigates the performance of charge-plasma-based gate underlap DM-JLTFET for biomolecule sensing applications while varying dielectric constant, charge density at different biasing conditions.

AlGaN/GaN MISHEMTs with AlN gate dielectric grown by thermal ALD technique.

Science.gov (United States)

Liu, Xiao-Yong; Zhao, Sheng-Xun; Zhang, Lin-Qing; Huang, Hong-Fan; Shi, Jin-Shan; Zhang, Chun-Min; Lu, Hong-Liang; Wang, Peng-Fei; Zhang, David Wei

2015-01-01

Recently, AlN plasma-enhanced atomic layer deposition (ALD) passivation technique had been proposed and investigated for suppressing the dynamic on-resistance degradation behavior of high-electron-mobility transistors (HEMTs). In this paper, a novel gate dielectric and passivation technique for GaN-on-Si AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMTs) is presented. This technique features the AlN thin film grown by thermal ALD at 400°C without plasma enhancement. A 10.6-nm AlN thin film was grown upon the surface of the HEMT serving as the gate dielectric under the gate electrode and as the passivation layer in the access region at the same time. The MISHEMTs with thermal ALD AlN exhibit enhanced on/off ratio, reduced channel sheet resistance, reduction of gate leakage by three orders of magnitude at a bias of 4 V, reduced threshold voltage hysteresis of 60 mV, and suppressed current collapse degradation.

Gate dielectric strength dependent performance of CNT MOSFET and CNT TFET: A tight binding study

Directory of Open Access Journals (Sweden)

Md. Shamim Sarker

Full Text Available This paper presents a comparative study between CNT MOSFET and CNT TFET taking into account of different dielectric strength of gate oxide materials. Here we have studied the transfer characteristics, on/off current (ION/IOFF ratio and subthreshold slope of the device using Non Equilibrium Greens Function (NEGF formalism in tight binding frameworks. The results are obtained by solving the NEGF and Poisson’s equation self-consistently in NanoTCADViDES environment and found that the ON state performance of CNT MOSFET and CNT TFET have significant dependency on the dielectric strength of the gate oxide materials. The figure of merits of the devices also demonstrates that the CNT TFET is promising for high-speed and low-power logic applications. Keywords: CNT TFET, Subthreshold slop, Barrier width, Conduction band (C.B and Valance band (V.B, Oxide dielectric strength, Tight binding approach

Improved speed and data retention characteristics in flash memory using a stacked HfO2/Ta2O5 charge-trapping layer

International Nuclear Information System (INIS)

Zheng, Zhiwei; Huo, Zongliang; Zhang, Manhong; Zhu, Chenxin; Liu, Jing; Liu, Ming

2011-01-01

This paper reports the simultaneous improvements in erase speed and data retention characteristics in flash memory using a stacked HfO 2 /Ta 2 O 5 charge-trapping layer. In comparison to a memory capacitor with a single HfO 2 trapping layer, the erase speed of a memory capacitor with a stacked HfO 2 /Ta 2 O 5 charge-trapping layer is 100 times faster and its memory window is enlarged from 2.7 to 4.8 V for the same ±16 V sweeping voltage range. With the same initial window of ΔV FB = 4 V, the device with a stacked HfO 2 /Ta 2 O 5 charge-trapping layer has a 3.5 V extrapolated 10-year retention window, while the control device with a single HfO 2 trapping layer has only 2.5 V for the extrapolated 10-year window. The present results demonstrate that the device with the stacked HfO 2 /Ta 2 O 5 charge-trapping layer has a strong potential for future high-performance nonvolatile memory application

Low-Temperature Solution-Processed Gate Dielectrics for High-Performance Organic Thin Film Transistors

Directory of Open Access Journals (Sweden)

Jaekyun Kim

2015-10-01

Full Text Available A low-temperature solution-processed high-k gate dielectric layer for use in a high-performance solution-processed semiconducting polymer organic thin-film transistor (OTFT was demonstrated. Photochemical activation of sol-gel-derived AlOx films under 150 °C permitted the formation of a dense film with low leakage and relatively high dielectric-permittivity characteristics, which are almost comparable to the results yielded by the conventionally used vacuum deposition and high temperature annealing method. Octadecylphosphonic acid (ODPA self-assembled monolayer (SAM treatment of the AlOx was employed in order to realize high-performance (>0.4 cm2/Vs saturation mobility and low-operation-voltage (<5 V diketopyrrolopyrrole (DPP-based OTFTs on an ultra-thin polyimide film (3-μm thick. Thus, low-temperature photochemically-annealed solution-processed AlOx film with SAM layer is an attractive candidate as a dielectric-layer for use in high-performance organic TFTs operated at low voltages.

Wet thermal annealing effect on TaN/HfO2/Ge metal—oxide—semiconductor capacitors with and without a GeO2 passivation layer

International Nuclear Information System (INIS)

Liu Guan-Zhou; Li Cheng; Lu Chang-Bao; Tang Rui-Fan; Tang Meng-Rao; Wu Zheng; Yang Xu; Huang Wei; Lai Hong-Kai; Chen Song-Yan

2012-01-01

Wet thermal annealing effects on the properties of TaN/HfO 2 /Ge metal—oxide—semiconductor (MOS) structures with and without a GeO 2 passivation layer are investigated. The physical and the electrical properties are characterized by X-ray photoemission spectroscopy, high-resolution transmission electron microscopy, capacitance—voltage (C—V) and current—voltage characteristics. It is demonstrated that wet thermal annealing at relatively higher temperature such as 550 °C can lead to Ge incorporation in HfO 2 and the partial crystallization of HfO 2 , which should be responsible for the serious degradation of the electrical characteristics of the TaN/HfO 2 /Ge MOS capacitors. However, wet thermal annealing at 400 °C can decrease the GeO x interlayer thickness at the HfO 2 /Ge interface, resulting in a significant reduction of the interface states and a smaller effective oxide thickness, along with the introduction of a positive charge in the dielectrics due to the hydrolyzable property of GeO x in the wet ambient. The pre-growth of a thin GeO 2 passivation layer can effectively suppress the interface states and improve the C—V characteristics for the as-prepared HfO 2 gated Ge MOS capacitors, but it also dissembles the benefits of wet thermal annealing to a certain extent

Deep electron traps in HfO_2-based metal-oxide-semiconductor capacitors

International Nuclear Information System (INIS)

Salomone, L. Sambuco; Lipovetzky, J.; Carbonetto, S.H.; García Inza, M.A.; Redin, E.G.; Campabadal, F.

2016-01-01

Hafnium oxide (HfO_2) is currently considered to be a good candidate to take part as a component in charge-trapping nonvolatile memories. In this work, the electric field and time dependences of the electron trapping/detrapping processes are studied through a constant capacitance voltage transient technique on metal-oxide-semiconductor capacitors with atomic layer deposited HfO_2 as insulating layer. A tunneling-based model is proposed to reproduce the experimental results, obtaining fair agreement between experiments and simulations. From the fitting procedure, a band of defects is identified, located in the first 1.7 nm from the Si/HfO_2 interface at an energy level E_t = 1.59 eV below the HfO_2 conduction band edge with density N_t = 1.36 × 10"1"9 cm"−"3. A simplified analytical version of the model is proposed in order to ease the fitting procedure for the low applied voltage case considered in this work. - Highlights: • We characterized deep electron trapping/detrapping in HfO_2 structures. • We modeled the experimental results through a tunneling-based model. • We obtained an electron trap energy level of 1.59 eV below conduction band edge. • We obtained a spatial trap distribution extending 1.7 nm within the insulator. • A simplified tunneling front model is able to reproduce the experimental results.

Issues concerning the determination of solubility products of sparingly soluble crystalline solids. Solubility of HfO2(cr)

International Nuclear Information System (INIS)

Rai, Dhanpat; Kitamura, Akira; Rosso, Kevin M.; Sasaki, Takayuki; Kobayashi, Taishi

2016-01-01

Solubility studies were conducted with HfO 2 (cr) solid as a function HCl and ionic strength ranging from 2.0 to 0.004 mol kg -1 . These studies involved (1) using two different amounts of the solid phase, (2) acid washing the bulk solid phase, (3) preheating the solid phase to 1400 C, and (4) heating amorphous HfO 2 (am) suspensions to 90 C to ascertain whether the HfO 2 (am) converts to HfO 2 (cr) and to determine the solubility from the oversaturation direction. Based on the results of these treatments it is concluded that the HfO 2 (cr) contains a small fraction of less crystalline, but not amorphous, material [HfO 2 (lcr)] and this, rather than the HfO 2 (cr), is the solubility-controlling phase in the range of experimental variables investigated in this study. The solubility data are interpreted using both the Pitzer and SIT models and they provide log 10 K 0 values of -(59.75±0.35) and -(59.48±0.41), respectively, for the solubility product of HfO 2 (lcr)[HfO 2 (lcr) + 2H 2 O ↔ Hf 4+ + 4OH - ]. The log 10 of the solubility product of HfO 2 (cr) is estimated to be < -63. The observation of a small fraction of less crystalline higher solubility material is consistent with the general picture that mineral surfaces are often structurally and/or compositionally imperfect leading to a higher solubility than the bulk crystalline solid. This study stresses the urgent need, during interpretation of solubility data, of taking precautions to make certain that the observed solubility behavior for sparingly-soluble solids is assigned to the proper solid phase.

Black Phosphorus Based Field Effect Transistors with Simultaneously Achieved Near Ideal Subthreshold Swing and High Hole Mobility at Room Temperature.

Science.gov (United States)

Liu, Xinke; Ang, Kah-Wee; Yu, Wenjie; He, Jiazhu; Feng, Xuewei; Liu, Qiang; Jiang, He; Dan Tang; Wen, Jiao; Lu, Youming; Liu, Wenjun; Cao, Peijiang; Han, Shun; Wu, Jing; Liu, Wenjun; Wang, Xi; Zhu, Deliang; He, Zhubing

2016-04-22

Black phosphorus (BP) has emerged as a promising two-dimensional (2D) material for next generation transistor applications due to its superior carrier transport properties. Among other issues, achieving reduced subthreshold swing and enhanced hole mobility simultaneously remains a challenge which requires careful optimization of the BP/gate oxide interface. Here, we report the realization of high performance BP transistors integrated with HfO2 high-k gate dielectric using a low temperature CMOS process. The fabricated devices were shown to demonstrate a near ideal subthreshold swing (SS) of ~69 mV/dec and a room temperature hole mobility of exceeding >400 cm(2)/Vs. These figure-of-merits are benchmarked to be the best-of-its-kind, which outperform previously reported BP transistors realized on traditional SiO2 gate dielectric. X-ray photoelectron spectroscopy (XPS) analysis further reveals the evidence of a more chemically stable BP when formed on HfO2 high-k as opposed to SiO2, which gives rise to a better interface quality that accounts for the SS and hole mobility improvement. These results unveil the potential of black phosphorus as an emerging channel material for future nanoelectronic device applications.

Structure and properties of a model conductive filament/host oxide interface in HfO2-based ReRAM

Science.gov (United States)

Padilha, A. C. M.; McKenna, K. P.

2018-04-01

Resistive random-access memory (ReRAM) is a promising class of nonvolatile memory capable of storing information via its resistance state. In the case of hafnium oxide-based devices, experimental evidence shows that a conductive oxygen-deficient filament is formed and broken inside of the device by oxygen migration, leading to switching of its resistance state. However, little is known about the nature of this conductive phase, its interface with the host oxide, or the associated interdiffusion of oxygen, presenting a challenge to understanding the switching mechanism and device properties. To address these problems, we present atomic-scale first-principles simulations of a prototypical conductive phase (HfO), the electronic properties of its interface with HfO2, as well as stability with respect to oxygen diffusion across the interface. We show that the conduction-band offset between HfO and HfO2 is 1.3 eV, smaller than typical electrode-HfO2 band offsets, suggesting that positive charging and band bending should occur at the conductive filament-HfO2 interface. We also show that transfer of oxygen across the interface, from HfO2 into HfO, costs around 1.2 eV per atom and leads to a gradual opening of the HfO band gap, and hence disruption of the electrical conductivity. These results provide invaluable insights into understanding the switching mechanism for HfO2-based ReRAM.

Metallorganic chemical vapor deposition and atomic layer deposition approaches for the growth of hafnium-based thin films from dialkylamide precursors for advanced CMOS gate stack applications

Science.gov (United States)

Consiglio, Steven P.

To continue the rapid progress of the semiconductor industry as described by Moore's Law, the feasibility of new material systems for front end of the line (FEOL) process technologies needs to be investigated, since the currently employed polysilicon/SiO2-based transistor system is reaching its fundamental scaling limits. Revolutionary breakthroughs in complementary-metal-oxide-semiconductor (CMOS) technology were recently announced by Intel Corporation and International Business Machines Corporation (IBM), with both organizations revealing significant progress in the implementation of hafnium-based high-k dielectrics along with metal gates. This announcement was heralded by Gordon Moore as "...the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s." Accordingly, the study described herein focuses on the growth of Hf-based dielectrics and Hf-based metal gates using chemical vapor-based deposition methods, specifically metallorganic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). A family of Hf source complexes that has received much attention recently due to their desirable properties for implementation in wafer scale manufacturing is the Hf dialkylamide precursors. These precursors are room temperature liquids and possess sufficient volatility and desirable decomposition characteristics for both MOCVD and ALD processing. Another benefit of using these sources is the existence of chemically compatible Si dialkylamide sources as co-precursors for use in Hf silicate growth. The first part of this study investigates properties of MOCVD-deposited HfO2 and HfSixOy using dimethylamido Hf and Si precursor sources using a customized MOCVD reactor. The second part of this study involves a study of wet and dry surface pre-treatments for ALD growth of HfO2 using tetrakis(ethylmethylamido)hafnium in a wafer scale manufacturing environment. The third part of this study is an investigation of

The Performance Improvement of N2 Plasma Treatment on ZrO2 Gate Dielectric Thin-Film Transistors with Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition IGZO Channel.

Science.gov (United States)

Wu, Chien-Hung; Huang, Bo-Wen; Chang, Kow-Ming; Wang, Shui-Jinn; Lin, Jian-Hong; Hsu, Jui-Mei

2016-06-01

The aim of this paper is to illustrate the N2 plasma treatment for high-κ ZrO2 gate dielectric stack (30 nm) with indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs). Experimental results reveal that a suitable incorporation of nitrogen atoms could enhance the device performance by eliminating the oxygen vacancies and provide an amorphous surface with better surface roughness. With N2 plasma treated ZrO2 gate, IGZO channel is fabricated by atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) technique. The best performance of the AP-PECVD IGZO TFTs are obtained with 20 W-90 sec N2 plasma treatment with field-effect mobility (μ(FET)) of 22.5 cm2/V-s, subthreshold swing (SS) of 155 mV/dec, and on/off current ratio (I(on)/I(off)) of 1.49 x 10(7).

Effects of Y incorporation in TaON gate dielectric on electrical performance of GaAs metal-oxide-semiconductor capacitor

Energy Technology Data Exchange (ETDEWEB)

Liu, Li Ning; Choi, Hoi Wai; Lai, Pui To [Department of Electrical and Electronic Engineering, The University of Hong Kong (China); Xu, Jing Ping [School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan (China)

2016-09-15

In this study, GaAs metal-oxide-semiconductor (MOS) capacitors using Y-incorporated TaON as gate dielectric have been investigated. Experimental results show that the sample with a Y/(Y + Ta) atomic ratio of 27.6% exhibits the best device characteristics: high k value (22.9), low interfacestate density (9.0 x 10{sup 11} cm{sup -2} eV{sup -1}), small flatband voltage (1.05 V), small frequency dispersion and low gate leakage current (1.3 x 10{sup -5}A/cm{sup 2} at V{sub fb} + 1 V). These merits should be attributed to the complementary properties of Y{sub 2}O{sub 3} and Ta{sub 2}O{sub 5}:Y can effectively passivate the large amount of oxygen vacancies in Ta{sub 2}O{sub 5}, while the positively-charged oxygen vacancies in Ta{sub 2}O{sub 5} are capable of neutralizing the effects of the negative oxide charges in Y{sub 2}O{sub 3}. This work demonstrates that an appropriate doping of Y content in TaON gate dielectric can effectively improve the electrical performance for GaAs MOS devices. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Electrical transport of bottom-up grown single-crystal Si1-xGex nanowire

International Nuclear Information System (INIS)

Yang, W F; Lee, S J; Liang, G C; Whang, S J; Kwong, D L

2008-01-01

In this work, we fabricated an Si 1-x Ge x nanowire (NW) metal-oxide-semiconductor field-effect transistor (MOSFET) by using bottom-up grown single-crystal Si 1-x Ge x NWs integrated with HfO 2 gate dielectric, TaN/Ta gate electrode and Pd Schottky source/drain electrodes, and investigated the electrical transport properties of Si 1-x Ge x NWs. It is found that both undoped and phosphorus-doped Si 1-x Ge x NW MOSFETs exhibit p-MOS operation while enhanced performance of higher I on ∼100 nA and I on /I off ∼10 5 are achieved from phosphorus-doped Si 1-x Ge x NWs, which can be attributed to the reduction of the effective Schottky barrier height (SBH). Further improvement in gate control with a subthreshold slope of 142 mV dec -1 was obtained by reducing HfO 2 gate dielectric thickness. A comprehensive study on SBH between the Si 1-x Ge x NW channel and Pd source/drain shows that a doped Si 1-x Ge x NW has a lower effective SBH due to a thinner depletion width at the junction and the gate oxide thickness has negligible effect on effective SBH

Ternary rare-earth based alternative gate-dielectrics for future integration in MOSFETs

Energy Technology Data Exchange (ETDEWEB)

Schubert, Juergen; Lopes, Joao Marcelo; Durgun Oezben, Eylem; Luptak, Roman; Lenk, Steffi; Zander, Willi; Roeckerath, Martin [IBN 1-IT, Forschungszentrum Juelich, 52425 Juelich (Germany)

2009-07-01

The dielectric SiO{sub 2} has been the key to the tremendous improvements in Si-based metal-oxide-semiconductor (MOS) device performance over the past four decades. It has, however, reached its limit in terms of scaling since it exhibits a leakage current density higher than 1 A/cm{sup 2} and does not retain its intrinsic physical properties at thicknesses below 1.5 nm. In order to overcome these problems and keep Moore's law ongoing, the use of higher dielectric constant (k) gate oxides has been suggested. These high-k materials must satisfy numerous requirements such as the high k, low leakage currents, suitable band gap und offsets to silicon. Rare-earth based dielectrics are promising materials which fulfill these needs. We will review the properties of REScO{sub 3} (RE = La, Dy, Gd, Sm, Tb) and LaLuO{sub 3} thin films, grown with pulsed laser deposition, e-gun evaporation or molecular beam deposition, integrated in capacitors and transistors. A k > 20 for the REScO{sub 3} (RE = Dy, Gd) and around 30 for (RE = La, Sm, Tb) and LaLuO{sub 3} are obtained. Transistors prepared on SOI and sSOI show mobility values up to 380 cm{sup 2}/Vs on sSOI, which are comparable to such prepared with HfO{sub 2}.

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO₂ Gate Dielectrics by CF₄ Plasma Treatment.

Science.gov (United States)

Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

2018-05-17

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO₂ gate insulator and CF₄ plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO₂ gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm²/V∙s (without treatment) to 54.6 cm²/V∙s (with CF₄ plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO₂ gate dielectric has also been improved by the CF₄ plasma treatment. By applying the CF₄ plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device's immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF₄ plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO₂ gate dielectric, but also enhances the device's reliability.

Thermoluminescence in films of HfO2:Dy+3

International Nuclear Information System (INIS)

Ceron, P.; Rivera, T.; Guzman, J.; Montes, E.; Pelaez, A.; Rojas, B.; Guzman, D.; Azorin, J.; Paredes, L.

2014-08-01

In this work the thermoluminescence (TL) response of films of hafnium oxide polluted with dysprosium (HfO 2 :Dy +3 ) that were irradiated in the near UV (200 nm - 400 nm). The films were deposited by means of the ultrasonics spray pyrolysis technique on a glass substrate, using different deposit temperatures (300 grades C - 600 grades C). The best TL emission corresponded to the prepared film to 450 grades C that was exposed to a spectral irradiation of 80 μJ/(cm 2 -s) with a wave longitude of 240 nm. The TL response in function of the spectral irradiation was lineal in the studied interval (24 to 288 mJ/cm 2 ), several kinetic parameters were also calculated of the shine curve as depth of the trap (E), frequency factor (s) and order to the kinetics (b). The obtained results show that the films of HfO 2 :Dy +3 could be used as radiation monitor in the region of the near UV. (Author)

4f-5d hybridization in a high k dielectric

International Nuclear Information System (INIS)

Losovyj, Ya.B.; Tang, Jinke; Wang, Wendong; Hong Yuanjia; Palshin, Vadim; Tittsworth, Roland

2006-01-01

While intra-atomic f-d hybridization is expected, experimental confirmation of f-d hybridization in the photoemission final state leading to 4f band structure has been limited to 5f systems and compound systems with very shallow 4f levels. We demonstrate that core 4f states can contribute to the valence band structure in a wide band gap dielectric, in this case HfO 2 in the photoemission final state. In spite of the complications of sample charging, we find evidence of symmetry in the shallow 4f levels and wave vector dependent band dispersion, the latter consistent with the crystal structure of HfO 2

A novel approach for the improvement of electrostatic behaviour of physically doped TFET using plasma formation and shortening of gate electrode with hetero-gate dielectric

Science.gov (United States)

Soni, Deepak; Sharma, Dheeraj; Aslam, Mohd.; Yadav, Shivendra

2018-04-01

This article presents a new device configuration to enhance current drivability and suppress negative conduction (ambipolar conduction) with improved RF characteristics of physically doped TFET. Here, we used a new approach to get excellent electrical characteristics of hetero-dielectric short gate source electrode TFET (HD-SG SE-TFET) by depositing a metal electrode of 5.93 eV work function over the heavily doped source (P+) region. Deposition of metal electrode induces the plasma (thin layer) of holes under the Si/HfO2 interface due to work function difference of metal and semiconductor. Plasma layer of holes is advantageous to increase abruptness as well as decrease the tunneling barrier at source/channel junction for attaining higher tunneling rate of charge carriers (i.e., electrons), which turns into 86.66 times higher ON-state current compared with the conventional physically doped TFET (C-TFET). Along with metal electrode deposition, gate electrode is under-lapped for inducing asymmetrical concentration of charge carriers in the channel region, which is helpful for widening the tunneling barrier width at the drain/channel interface. Consequently, HD-SG SE-TFET shows suppression of ambipolar behavior with reduction in gate-to-drain capacitance which is beneficial for improvement in RF performance. Furthermore, the effectiveness of hetero-gate dielectric concept has been used for improving the RF performance. Furthermore, reliability of C-TFET and proposed structures has been confirmed in term of linearity.

Electrical properties of nano-resistors made from the Zr-doped HfO2 high-k dielectric film

Science.gov (United States)

Zhang, Shumao; Kuo, Yue

2018-03-01

Electrical properties of nano-sized resistors made from the breakdown of the metal-oxide-semiconductor capacitor composed of the amorphous high-k gate dielectric have been investigated under different stress voltages and temperatures. The effective resistance of nano-resistors in the device was estimated from the I-V curve in the high voltage range. It decreased with the increase of the number of resistors. The resistance showed complicated temperature dependence, i.e. it neither behaves like a conductor nor a semiconductor. In the low voltage operation range, the charge transfer was controlled by the Schottky barrier at the nano-resistor/Si interface. The barrier height decreased with the increase of stress voltage, which was probably caused by the change of the nano-resistor composition. Separately, it was observed that the barrier height was dependent on the temperature, which was probably due to the dynamic nano-resistor formation process and the inhomogeneous barrier height distribution. The unique electrical characteristics of this new type of nano-resistors are important for many electronic and optoelectronic applications.

Graphene-graphite oxide field-effect transistors.

Science.gov (United States)

Standley, Brian; Mendez, Anthony; Schmidgall, Emma; Bockrath, Marc

2012-03-14

Graphene's high mobility and two-dimensional nature make it an attractive material for field-effect transistors. Previous efforts in this area have used bulk gate dielectric materials such as SiO(2) or HfO(2). In contrast, we have studied the use of an ultrathin layered material, graphene's insulating analogue, graphite oxide. We have fabricated transistors comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. The graphite oxide layers show relatively minimal leakage at room temperature. The breakdown electric field of graphite oxide was found to be comparable to SiO(2), typically ~1-3 × 10(8) V/m, while its dielectric constant is slightly higher, κ ≈ 4.3. © 2012 American Chemical Society

Low-voltage organic thin film transistors (OTFTs) using crosslinked polyvinyl alcohol (PVA)/neodymium oxide (Nd2O3) bilayer gate dielectrics

Science.gov (United States)

Khound, Sagarika; Sarma, Ranjit

2018-01-01

We have reported here on the design, processing and dielectric properties of pentacene-based organic thin film transitors (OTFTs) with a bilayer gate dilectrics of crosslinked PVA/Nd2O3 which enables low-voltage organic thin film operations. The dielectric characteristics of PVA/Nd2O3 bilayer films are studied by capacitance-voltage ( C- V) and current-voltage ( I- V) curves in the metal-insulator-metal (MIM) structure. We have analysed the output electrical responses and transfer characteristics of the OTFT devices to determine their performance of OTFT parameters. The mobility of 0.94 cm2/Vs, the threshold voltage of - 2.8 V, the current on-off ratio of 6.2 × 105, the subthreshold slope of 0.61 V/decade are evaluated. Low leakage current of the device is observed from current density-electric field ( J- E) curve. The structure and the morphology of the device are studied using X-ray diffraction (XRD) and atomic force microscope (AFM), respectively. The study demonstrates an effective way to realize low-voltage, high-performance OTFTs at low cost.

Conduction Mechanism and Improved Endurance in HfO2-Based RRAM with Nitridation Treatment

Science.gov (United States)

Yuan, Fang-Yuan; Deng, Ning; Shih, Chih-Cheng; Tseng, Yi-Ting; Chang, Ting-Chang; Chang, Kuan-Chang; Wang, Ming-Hui; Chen, Wen-Chung; Zheng, Hao-Xuan; Wu, Huaqiang; Qian, He; Sze, Simon M.

2017-10-01

A nitridation treatment technology with a urea/ammonia complex nitrogen source improved resistive switching property in HfO2-based resistive random access memory (RRAM). The nitridation treatment produced a high performance and reliable device which results in superior endurance (more than 109 cycles) and a self-compliance effect. Thus, the current conduction mechanism changed due to defect passivation by nitrogen atoms in the HfO2 thin film. At a high resistance state (HRS), it transferred to Schottky emission from Poole-Frenkel in HfO2-based RRAM. At low resistance state (LRS), the current conduction mechanism was space charge limited current (SCLC) after the nitridation treatment, which suggests that the nitrogen atoms form Hf-N-Ox vacancy clusters (Vo +) which limit electron movement through the switching layer.

Customized binary and multi-level HfO2-x-based memristors tuned by oxidation conditions.

Science.gov (United States)

He, Weifan; Sun, Huajun; Zhou, Yaxiong; Lu, Ke; Xue, Kanhao; Miao, Xiangshui

2017-08-30

The memristor is a promising candidate for the next generation non-volatile memory, especially based on HfO 2-x , given its compatibility with advanced CMOS technologies. Although various resistive transitions were reported independently, customized binary and multi-level memristors in unified HfO 2-x material have not been studied. Here we report Pt/HfO 2-x /Ti memristors with double memristive modes, forming-free and low operation voltage, which were tuned by oxidation conditions of HfO 2-x films. As O/Hf ratios of HfO 2-x films increase, the forming voltages, SET voltages, and R off /R on windows increase regularly while their resistive transitions undergo from gradually to sharply in I/V sweep. Two memristors with typical resistive transitions were studied to customize binary and multi-level memristive modes, respectively. For binary mode, high-speed switching with 10 3 pulses (10 ns) and retention test at 85 °C (>10 4 s) were achieved. For multi-level mode, the 12-levels stable resistance states were confirmed by ongoing multi-window switching (ranging from 10 ns to 1 μs and completing 10 cycles of each pulse). Our customized binary and multi-level HfO 2-x -based memristors show high-speed switching, multi-level storage and excellent stability, which can be separately applied to logic computing and neuromorphic computing, further suitable for in-memory computing chip when deposition atmosphere may be fine-tuned.

Insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor devices with Al2O3 or AlTiO gate dielectrics

Science.gov (United States)

Le, Son Phuong; Nguyen, Duong Dai; Suzuki, Toshi-kazu

2018-01-01

We have investigated insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor (MIS) devices with Al2O3 or AlTiO (an alloy of Al2O3 and TiO2) gate dielectrics obtained by atomic layer deposition on AlGaN. Analyzing insulator-thickness dependences of threshold voltages for the MIS devices, we evaluated positive interface fixed charges, whose density at the AlTiO/AlGaN interface is significantly lower than that at the Al2O3/AlGaN interface. This and a higher dielectric constant of AlTiO lead to rather shallower threshold voltages for the AlTiO gate dielectric than for Al2O3. The lower interface fixed charge density also leads to the fact that the two-dimensional electron concentration is a decreasing function of the insulator thickness for AlTiO, whereas being an increasing function for Al2O3. Moreover, we discuss the relationship between the interface fixed charges and interface states. From the conductance method, it is shown that the interface state densities are very similar at the Al2O3/AlGaN and AlTiO/AlGaN interfaces. Therefore, we consider that the lower AlTiO/AlGaN interface fixed charge density is not owing to electrons trapped at deep interface states compensating the positive fixed charges and can be attributed to a lower density of oxygen-related interface donors.

Effect of annealing temperature on structural and electrical properties of high-κ YbTixOy gate dielectrics for InGaZnO thin film transistors

International Nuclear Information System (INIS)

Pan, Tung-Ming; Chen, Fa-Hsyang; Hung, Meng-Ning

2015-01-01

This paper describes the effect of annealing temperature on the structural properties and electrical characteristics of high–κ YbTi x O y gate dielectrics for indium–gallium–zinc–oxide (IGZO) thin-film transistors (TFTs). X-ray diffraction, x-ray photoelectron spectroscopy and atomic force microscopy were used to study the structural, chemical and morphological features, respectively, of these dielectric films annealed at 200, 300 and 400 °C. The YbTi x O y IGZO TFT that had been annealed at 400 °C exhibited better electrical characteristics, such as a small threshold voltage of 0.53 V, a large field-effect mobility of 19.1 cm 2 V −1 s −1 , a high I on /I off ratio of 2.8 × 10 7 , and a low subthreshold swing of 176 mV dec. −1 , relative to those of the systems that had been subjected to other annealing conditions. This result suggests that YbTi x O y dielectric possesses a higher dielectric constant as well as lower oxygen vacancies (or defects) in the film. In addition, the instability of YbTi x O y IGZO TFT was studied under positive gate-bias stress and negative gate-bias stress conditions. (paper)

Impedance Characterization of the Capacitive field-Effect pH-Sensor Based on a thin-Layer Hafnium Oxide Formed by Atomic Layer Deposition

Directory of Open Access Journals (Sweden)

Michael LEE

2014-05-01

Full Text Available As a sensing element, silicon dioxide (SiO2 has been applied within ion-sensitive field effect transistors (ISFET. However, a requirement of increasing pH-sensitivity and stability has observed an increased number of insulating materials that obtain high-k gate being applied as FETs. The increased high-k gate reduces the required metal oxide layer and, thus, the fabrication of thin hafnium oxide (HfO2 layers by atomic layer deposition (ALD has grown with interest in recent years. This metal oxide presents advantageous characteristics that can be beneficial for the advancements within miniaturization of complementary metal oxide semiconductor (CMOS technology. In this article, we describe a process for fabrication of HfO2 based on ALD by applying water (H2O as the oxygen precursor. As a first, electrochemical impedance spectroscopy (EIS measurements were performed with varying pH (2-10 to demonstrate the sensitivity of HfO2 as a potential pH sensing material. The Nyquist plot demonstrates a high clear shift of the polarization resistance (Rp between pH 6-10 (R2 = 0.9986, Y = 3,054X + 12,100. At acidic conditions (between pH 2-10, the Rp change was small due to the unmodified oxide gate (R2 = 0.9655, Y = 2,104X + 4,250. These preliminary results demonstrate the HfO2 substrate functioned within basic to neutral conditions and establishes a great potential for applying HfO2 as a dielectric material for future pH measuring FET sensors.

Defect states and charge trapping characteristics of HfO2 films for high performance nonvolatile memory applications

International Nuclear Information System (INIS)

Zhang, Y.; Shao, Y. Y.; Lu, X. B.; Zeng, M.; Zhang, Z.; Gao, X. S.; Zhang, X. J.; Liu, J.-M.; Dai, J. Y.

2014-01-01

In this work, we present significant charge trapping memory effects of the metal-hafnium oxide-SiO 2 -Si (MHOS) structure. The devices based on 800 °C annealed HfO 2 film exhibit a large memory window of ∼5.1 V under ±10 V sweeping voltages and excellent charge retention properties with only small charge loss of ∼2.6% after more than 10 4  s retention. The outstanding memory characteristics are attributed to the high density of deep defect states in HfO 2 films. We investigated the defect states in the HfO 2 films by photoluminescence and photoluminescence excitation measurements and found that the defect states distributed in deep energy levels ranging from 1.1 eV to 2.9 eV below the conduction band. Our work provides further insights for the charge trapping mechanisms of the HfO 2 based MHOS devices.

Thermal expansion studies on HfO2-Gd2O3 system

International Nuclear Information System (INIS)

Panneerselvam, G.; Antony, M.P.; Nagarajan, K.

2014-01-01

A series of solid solutions containing GdO 1.5 in HfO 2 , (Hf 1-y Gd y ) O 2 (y = 0.15, 0.2, 0.3, 0.41 and 0.505) were prepared by solid state method. Structural characterization and computation of lattice parameter was carried out using room temperature X-ray diffraction measurements

Fabrication and electrical characterization of a MOS memory device containing self-assembled metallic nanoparticles

Science.gov (United States)

Sargentis, Ch.; Giannakopoulos, K.; Travlos, A.; Tsamakis, D.

2007-04-01

Floating gate devices with nanoparticles embedded in dielectrics have recently attracted much attention due to the fact that these devices operate as non-volatile memories with high speed, high density and low power consumption. In this paper, memory devices containing gold (Au) nanoparticles have been fabricated using e-gun evaporation. The Au nanoparticles are deposited on a very thin SiO 2 layer and are then fully covered by a HfO 2 layer. The HfO 2 is a high- k dielectric and gives good scalability to the fabricated devices. We studied the effect of the deposition parameters to the size and the shape of the Au nanoparticles using capacitance-voltage and conductance-voltage measurements, we demonstrated that the fabricated device can indeed operate as a low-voltage memory device.

Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

International Nuclear Information System (INIS)

Ghosh, Bahniman; Mondal, Partha; Akram, M. W.; Bal, Punyasloka; Salimath, Akshay Kumar

2014-01-01

We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel. These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n–p–n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability. (semiconductor devices)

A complementary organic inverter of porphyrazine thin films: low-voltage operation using ionic liquid gate dielectrics.

Science.gov (United States)

Fujimoto, Takuya; Miyoshi, Yasuhito; Matsushita, Michio M; Awaga, Kunio

2011-05-28

We studied a complementary organic inverter consisting of a p-type semiconductor, metal-free phthalocyanine (H(2)Pc), and an n-type semiconductor, tetrakis(thiadiazole)porphyrazine (H(2)TTDPz), operated through the ionic-liquid gate dielectrics of N,N-diethyl-N-methyl(2-methoxyethyl)ammonium bis(trifluoromethylsulfonyl)imide (DEME-TFSI). This organic inverter exhibits high performance with a very low operation voltage below 1.0 V and a dynamic response up to 20 Hz. © The Royal Society of Chemistry 2011

Field-enhanced route to generating anti-Frenkel pairs in HfO2

Science.gov (United States)

Schie, Marcel; Menzel, Stephan; Robertson, John; Waser, Rainer; De Souza, Roger A.

2018-03-01

The generation of anti-Frenkel pairs (oxygen vacancies and oxygen interstitials) in monoclinic and cubic HfO2 under an applied electric field is examined. A thermodynamic model is used to derive an expression for the critical field strength required to generate an anti-Frenkel pair. The critical field strength of EaFcr˜101GVm-1 obtained for HfO2 exceeds substantially the field strengths routinely employed in the forming and switching operations of resistive switching HfO2 devices, suggesting that field-enhanced defect generation is negligible. Atomistic simulations with molecular static (MS) and molecular dynamic (MD) approaches support this finding. The MS calculations indicated a high formation energy of Δ EaF≈8 eV for the infinitely separated anti-Frenkel pair, and only a decrease to Δ EaF≈6 eV for the adjacent anti-Frenkel pair. The MD simulations showed no defect generation in either phase for E <3 GVm-1 , and only sporadic defect generation in the monoclinic phase (at E =3 GVm-1 ) with fast (trec<4 ps ) recombination. At even higher E but below EaFcr both monoclinic and cubic structures became unstable as a result of field-induced deformation of the ionic potential wells. Further MD investigations starting with preexisting anti-Frenkel pairs revealed recombination of all pairs within trec<1 ps , even for the case of neutral vacancies and charged interstitials, for which formally there is no electrostatic attraction between the defects. In conclusion, we find no physically reasonable route to generating point-defects in HfO2 by an applied field.

Phosphorus recovery from biogas slurry by ultrasound/H2O2 digestion coupled with HFO/biochar adsorption process.

Science.gov (United States)

He, Xuemeng; Zhang, Tao; Ren, Hongqiang; Li, Guoxue; Ding, Lili; Pawlowski, Lucjan

2017-02-01

Phosphorus (P) recovery from biogas slurry has recently attracted considerable interest. In this work, ultrasound/H 2 O 2 digestion coupled with ferric oxide hydrate/biochar (HFO/biochar) adsorption process was performed to promote P dissolution, release, and recovery from biogas slurry. The results showed that the optimal total phosphorus release efficiency was achieved at an inorganic phosphorus/total phosphorus ratio of 95.0% at pH 4, 1mL of added H 2 O 2 , and ultrasonication for 30min. The P adsorption by the HFO/biochar followed pseudo second-order kinetics and was mainly controlled by chemical processes. The Langmuir-Freundlich model matched the experimental data best for P adsorption by HFO/biochar at 298 and 308K, whereas the Freundlich model matched best at 318K. The maximum amount of P adsorbed was 220mg/g. The process was endothermic, spontaneous, and showed an increase in disorder at the solid-liquid interface. The saturated adsorbed HFO/biochar continually releases P and is most suitable for use in an alkaline environment. The amount of P released reached 29.1mg/g after five extractions. P mass balance calculation revealed that 11.3% of the total P can be made available. Copyright © 2016. Published by Elsevier Ltd.

Ferroelectric transistors with monolayer molybdenum disulfide and ultra-thin aluminum-doped hafnium oxide

Science.gov (United States)

Yap, Wui Chung; Jiang, Hao; Liu, Jialun; Xia, Qiangfei; Zhu, Wenjuan

2017-07-01

In this letter, we demonstrate ferroelectric memory devices with monolayer molybdenum disulfide (MoS2) as the channel material and aluminum (Al)-doped hafnium oxide (HfO2) as the ferroelectric gate dielectric. Metal-ferroelectric-metal capacitors with 16 nm thick Al-doped HfO2 are fabricated, and a remnant polarization of 3 μC/cm2 under a program/erase voltage of 5 V is observed. The capability of potential 10 years data retention was estimated using extrapolation of the experimental data. Ferroelectric transistors based on embedded ferroelectric HfO2 and MoS2 grown by chemical vapor deposition are fabricated. Clockwise hysteresis is observed at low program/erase voltages due to slow bulk traps located near the 2D/dielectric interface, while counterclockwise hysteresis is observed at high program/erase voltages due to ferroelectric polarization. In addition, the endurances of the devices are tested, and the effects associated with ferroelectric materials, such as the wake-up effect and polarization fatigue, are observed. Reliable writing/reading in MoS2/Al-doped HfO2 ferroelectric transistors over 2 × 104 cycles is achieved. This research can potentially lead to advances of two-dimensional (2D) materials in low-power logic and memory applications.

Mechanical properties of ultra-thin HfO2 films studied by nano scratches tests

International Nuclear Information System (INIS)

Fu, Wei-En; Chang, Yong-Qing; Chang, Chia-Wei; Yao, Chih-Kai; Liao, Jiunn-Der

2013-01-01

10-nm-thick atomic layer deposited HfO 2 films were characterized in terms of wear resistance and indentation hardness to investigate the thermal annealing induced impacts on mechanical properties. The wear resistance of ultra-thin films at low loads was characterized using nano-scratch tests with an atomic force microscope. The depth of the nano-scratches decreases with increasing annealing temperature, indicating that the hardness of the annealed films increases with the annealing temperatures. Surface nanoindentation was also performed to confirm the nanoscratch test results. The hardness variation of the annealed films is due to the generation of HfSi x O y induced by the thermal annealing. X-ray photoelectron spectroscopy measurements proved that the hardness of formed HfSi x O y with increasing annealing temperatures. The existence of HfSi x O y broadens the interface, and causes the increase of the interfacial layer thickness. As a result, the surface hardness increases with the increasing HfSi x O y induced by the thermal annealing. - Highlights: ► Mechanical properties of HfO 2 films were assessed by nano-scratch and indentation. ► Scratch depth of HfO 2 films decreased with the increase of annealing temperatures. ► Nano-hardness of HfO 2 films increased with the increase of annealing temperatures

Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

Science.gov (United States)

Choi, Woo Young; Lee, Hyun Kook

2016-01-01

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

High-Sensitivity, Highly Transparent, Gel-Gated MoS2 Phototransistor on Biodegradable Nanopaper

KAUST Repository

Zhang, Qing

2016-06-21

Transition metal dichalcogenides hold great promise for a variety of novel electrical, optical and mechanical devices and applications. Among them, molybdenum disulphide (MoS2) is gaining increasing attention as the gate dielectric and semiconductive channel for high-perfomance field effect transistors. Here we report on the first MoS2 phototransistor built on flexible, transparent and biodegradable substrate with electrolyte gate dielectric. We have carried out systematic studies on its electrical and optoelectronic properties. The MoS2 phototransistor exhibited excellent photo responsivity of ~1.5 kA/W, about two times higher compared to typical back-gated devices reported in previous studies. The device is highly transparent at the same time with an average optical transmittance of 82%. Successful fabrication of phototransistors on flexible cellulose nanopaper with excellent performance and transparency suggests that it is feasible to achieve an ecofriendly, biodegradable phototransistor with great photoresponsivity, broad spectral range and durable flexibility.

High-Sensitivity, Highly Transparent, Gel-Gated MoS2 Phototransistor on Biodegradable Nanopaper

KAUST Repository

Zhang, Qing; Bao, Wenzhong; Gong, Amy; Gong, Tao; Ma, Dakang; Wan, Jiayu; Dai, Jiaqi; Munday, J; He, Jr-Hau; Hu, Liangbing; Zhang, Daihua

2016-01-01

Transition metal dichalcogenides hold great promise for a variety of novel electrical, optical and mechanical devices and applications. Among them, molybdenum disulphide (MoS2) is gaining increasing attention as the gate dielectric and semiconductive channel for high-perfomance field effect transistors. Here we report on the first MoS2 phototransistor built on flexible, transparent and biodegradable substrate with electrolyte gate dielectric. We have carried out systematic studies on its electrical and optoelectronic properties. The MoS2 phototransistor exhibited excellent photo responsivity of ~1.5 kA/W, about two times higher compared to typical back-gated devices reported in previous studies. The device is highly transparent at the same time with an average optical transmittance of 82%. Successful fabrication of phototransistors on flexible cellulose nanopaper with excellent performance and transparency suggests that it is feasible to achieve an ecofriendly, biodegradable phototransistor with great photoresponsivity, broad spectral range and durable flexibility.

Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling

Directory of Open Access Journals (Sweden)

Noor Faizah Z.A.

2016-01-01

Full Text Available This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2 as dielectric and Tungsten Silicide (WSi2 and Titanium Silicide (TiSi2 as a metal gate for NMOS and PMOS respectively. The devices are fabricated virtually using ATHENA module and characterized its performance evaluation via ATLAS module; both in Virtual Wafer Fabrication (VWF of Silvaco TCAD Tools. The devices were then optimized through a process parameters variability using L9 Taguchi Method. There were four process parameter with two noise factor of different values were used to analyze the factor effect. The results show that the optimal value for both transistors are well within ITRS 2013 prediction where VTH and IOFF are 0.236737V and 6.995705nA/um for NMOS device and 0.248635 V and 5.26nA/um for PMOS device respectively.

Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance

Science.gov (United States)

Yadav, Dharmendra Singh; Verma, Abhishek; Sharma, Dheeraj; Tirkey, Sukeshni; Raad, Bhagwan Ram

2017-11-01

Tunnel-field-effect-transistor (TFET) has emerged as one of the most prominent devices to replace conventional MOSFET due to its ability to provide sub-threshold slope below 60 mV/decade (SS ≤ 60 mV/decade) and low leakage current. Despite this, TFETs suffer from ambipolar behavior, lower ON-state current, and poor RF performance. To address these issues, we have introduced drain and gate work function engineering with hetero gate dielectric for the first time in charge plasma based doping-less TFET (DL TFET). In this, the usage of dual work functionality over the drain region significantly reduces the ambipolar behavior of the device by varying the energy barrier at drain/channel interface. Whereas, the presence of dual work function at the gate terminal increases the ON-state current (ION). The combined effect of dual work function at the gate and drain electrode results in the increment of ON-state current (ION) and decrement of ambipolar conduction (Iambi) respectively. Furthermore, the incorporation of hetero gate dielectric along with dual work functionality at the drain and gate electrode provides an overall improvement in the performance of the device in terms of reduction in ambipolarity, threshold voltage and sub-threshold slope along with improved ON-state current and high frequency figures of merit.

Laser conditioning effect on HfO2/SiO2 film

International Nuclear Information System (INIS)

Wei Yaowei; Zhang Zhe; Liu Hao; Ouyang Sheng; Zheng Yi; Tang Gengyu; Chen Songlin; Ma Ping

2013-01-01

Laser conditioning is one of the important methods to improve the laser damage threshold of film optics. Firstly, a large aperture laser was used to irradiate the HfO 2 /SiO 2 reflectors, which were evaporated from hafnia and silica by e-beam. Secondly, a laser calorimeter was used to test the film absorption before and after laser irradiation. Focused ion beam (FIB) was few reported using on laser film, it was used to study the damage morphology and explore the cause of damage. The shooting of the partial ejection on nodule was obtained for the first time, which provided the basis for study the damage process. The results show that film absorption was decreased obviously after the laser irradiation, laser conditioning can raise the laser damage threshold by the 'cleaning mechanism'. For the HfO 2 /SiO 2 reflectors, laser conditioning was effective to eject the nodules on substrate. It resulted from the nodule residue not to affect the subsequent laser. In addition, laser conditioning was not effective to the nodule in the film, which might be from the material spatter in coating process. In this case, other method could be used to get rid of the nodules. (authors)

Study of dielectric property on ZrO2 and Al doped ZrO2 nanoparticles

International Nuclear Information System (INIS)

Catherine Siriya Pushpa, K.; Mangayarkarasi, K.; Ravichandran, A.T.; Xavier, A. Robert; Nagabushana, B.M.

2014-01-01

A solution combustion process was used to synthesize ZrO 2 and Al doped ZrO 2 nanoparticles by using Zirconium nitrate and aluminium nitrate as the oxidizer and glycine as fuel. The prepared samples were characterized by several techniques such as X-ray Diffraction (XRD), Scanning Electron Microscopy (SEM), UV-visible spectroscopy (UV-vis). The dielectric values of the pelletized samples were examined at room temperature as the function of frequency. XRD shows the structure of the prepared and doped samples. The SEM shows the surface morphology of the pure and doped ZrO 2 nanoparticles. The dielectric property enhances with increase of Al concentration, which is useful in dielectric gates. (author)

Advanced passivation techniques for Si solar cells with high-κ dielectric materials

International Nuclear Information System (INIS)

Geng, Huijuan; Lin, Tingjui; Letha, Ayra Jagadhamma; Hwang, Huey-Liang; Kyznetsov, Fedor A.; Smirnova, Tamara P.; Saraev, Andrey A.; Kaichev, Vasily V.

2014-01-01

Electronic recombination losses at the wafer surface significantly reduce the efficiency of Si solar cells. Surface passivation using a suitable thin dielectric layer can minimize the recombination losses. Herein, advanced passivation using simple materials (Al 2 O 3 , HfO 2 ) and their compounds H (Hf) A (Al) O deposited by atomic layer deposition (ALD) was investigated. The chemical composition of Hf and Al oxide films were determined by X-ray photoelectron spectroscopy (XPS). The XPS depth profiles exhibit continuous uniform dense layers. The ALD-Al 2 O 3 film has been found to provide negative fixed charge (−6.4 × 10 11  cm −2 ), whereas HfO 2 film provides positive fixed charge (3.2 × 10 12  cm −2 ). The effective lifetimes can be improved after oxygen gas annealing for 1 min. I-V characteristics of Si solar cells with high-κ dielectric materials as passivation layers indicate that the performance is significantly improved, and ALD-HfO 2 film would provide better passivation properties than that of the ALD-Al 2 O 3 film in this research work.

Design of Higher-k and More Stable Rare Earth Oxides as Gate Dielectrics for Advanced CMOS Devices

Directory of Open Access Journals (Sweden)

Yi Zhao

2012-08-01

Full Text Available High permittivity (k gate dielectric films are widely studied to substitute SiO₂ as gate oxides to suppress the unacceptable gate leakage current when the traditional SiO₂ gate oxide becomes ultrathin. For high-k gate oxides, several material properties are dominantly important. The first one, undoubtedly, is permittivity. It has been well studied by many groups in terms of how to obtain a higher permittivity for popular high-k oxides, like HfO₂ and La₂O₃. The second one is crystallization behavior. Although it’s still under the debate whether an amorphous film is definitely better than ploy-crystallized oxide film as a gate oxide upon considering the crystal boundaries induced leakage current, the crystallization behavior should be well understood for a high-k gate oxide because it could also, to some degree, determine the permittivity of the high-k oxide. Finally, some high-k gate oxides, especially rare earth oxides (like La₂O₃, are not stable in air and very hygroscopic, forming hydroxide. This topic has been well investigated in over the years and significant progresses have been achieved. In this paper, I will intensively review the most recent progresses of the experimental and theoretical studies for preparing higher-k and more stable, in terms of hygroscopic tolerance and crystallization behavior, Hf- and La-based ternary high-k gate oxides.

Silicon surface passivation using thin HfO2 films by atomic layer deposition

International Nuclear Information System (INIS)

Gope, Jhuma; Vandana; Batra, Neha; Panigrahi, Jagannath; Singh, Rajbir; Maurya, K.K.; Srivastava, Ritu; Singh, P.K.

2015-01-01

Graphical abstract: - Highlights: • HfO 2 films using thermal ALD are studied for silicon surface passivation. • As-deposited thin film (∼8 nm) shows better passivation with surface recombination velocity (SRV) <100 cm/s. • Annealing improves passivation quality with SRV ∼20 cm/s for ∼8 nm film. - Abstract: Hafnium oxide (HfO 2 ) is a potential material for equivalent oxide thickness (EOT) scaling in microelectronics; however, its surface passivation properties particularly on silicon are not well explored. This paper reports investigation on passivation properties of thermally deposited thin HfO 2 films by atomic layer deposition system (ALD) on silicon surface. As-deposited pristine film (∼8 nm) shows better passivation with <100 cm/s surface recombination velocity (SRV) vis-à-vis thicker films. Further improvement in passivation quality is achieved with annealing at 400 °C for 10 min where the SRV reduces to ∼20 cm/s. Conductance measurements show that the interface defect density (D it ) increases with film thickness whereas its value decreases after annealing. XRR data corroborate with the observations made by FTIR and SRV data.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure.

Science.gov (United States)

Chen, Szu-Hung; Liao, Wen-Shiang; Yang, Hsin-Chia; Wang, Shea-Jue; Liaw, Yue-Gie; Wang, Hao; Gu, Haoshuang; Wang, Mu-Chun

2012-08-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal-semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

Graphene/Pentacene Barristor with Ion-Gel Gate Dielectric: Flexible Ambipolar Transistor with High Mobility and On/Off Ratio.

Science.gov (United States)

Oh, Gwangtaek; Kim, Jin-Soo; Jeon, Ji Hoon; Won, EunA; Son, Jong Wan; Lee, Duk Hyun; Kim, Cheol Kyeom; Jang, Jingon; Lee, Takhee; Park, Bae Ho

2015-07-28

High-quality channel layer is required for next-generation flexible electronic devices. Graphene is a good candidate due to its high carrier mobility and unique ambipolar transport characteristics but typically shows a low on/off ratio caused by gapless band structure. Popularly investigated organic semiconductors, such as pentacene, suffer from poor carrier mobility. Here, we propose a graphene/pentacene channel layer with high-k ion-gel gate dielectric. The graphene/pentacene device shows both high on/off ratio and carrier mobility as well as excellent mechanical flexibility. Most importantly, it reveals ambipolar behaviors and related negative differential resistance, which are controlled by external bias. Therefore, our graphene/pentacene barristor with ion-gel gate dielectric can offer various flexible device applications with high performances.

High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric.

Science.gov (United States)

Fujii, Mami N; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

2015-12-18

The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices.

Investigation of high- k yttrium copper titanate thin films as alternative gate dielectrics

International Nuclear Information System (INIS)

Monteduro, Anna Grazia; Ameer, Zoobia; Rizzato, Silvia; Martino, Maurizio; Caricato, Anna Paola; Maruccio, Giuseppe; Tasco, Vittorianna; Lekshmi, Indira Chaitanya; Hazarika, Abhijit; Choudhury, Debraj; Sarma, D D

2016-01-01

Nearly amorphous high- k yttrium copper titanate thin films deposited by laser ablation were investigated in both metal–oxide–semiconductor (MOS) and metal–insulator–metal (MIM) junctions in order to assess the potentialities of this material as a gate oxide. The trend of dielectric parameters with film deposition shows a wide tunability for the dielectric constant and AC conductivity, with a remarkably high dielectric constant value of up to 95 for the thick films and conductivity as low as 6  ×  10 −10 S cm −1 for the thin films deposited at high oxygen pressure. The AC conductivity analysis points out a decrease in the conductivity, indicating the formation of a blocking interface layer, probably due to partial oxidation of the thin films during cool-down in an oxygen atmosphere. Topography and surface potential characterizations highlight differences in the thin film microstructure as a function of the deposition conditions; these differences seem to affect their electrical properties. (paper)

A thorough investigation of the progressive reset dynamics in HfO2-based resistive switching structures

International Nuclear Information System (INIS)

Lorenzi, P.; Rao, R.; Irrera, F.; Suñé, J.; Miranda, E.

2015-01-01

According to previous reports, filamentary electron transport in resistive switching HfO 2 -based metal-insulator-metal structures can be modeled using a diode-like conduction mechanism with a series resistance. Taking the appropriate limits, the model allows simulating the high (HRS) and low (LRS) resistance states of the devices in terms of exponential and linear current-voltage relationships, respectively. In this letter, we show that this simple equivalent circuit approach can be extended to represent the progressive reset transition between the LRS and HRS if a generalized logistic growth model for the pre-exponential diode current factor is considered. In this regard, it is demonstrated here that a Verhulst logistic model does not provide accurate results. The reset dynamics is interpreted as the sequential deactivation of multiple conduction channels spanning the dielectric film. Fitting results for the current-voltage characteristics indicate that the voltage sweep rate only affects the deactivation rate of the filaments without altering the main features of the switching dynamics

Enhancement of Endurance in HfO2-Based CBRAM Device by Introduction of a TaN Diffusion Blocking Layer

KAUST Repository

Chand, Umesh

2017-08-05

We propose a new method to improve resistive switching properties in HfO2 based CBRAM crossbar structure device by introducing a TaN thin diffusion blocking layer between the Cu top electrode and HfO2 switching layer. The Cu/TaN/HfO2/TiN device structure exhibits high resistance ratio of OFF/ON states without any degradation in switching during endurance test. The improvement in the endurance properties of the Cu/TaN/HfO2/TiN CBRAM device is thus attributed to the relatively low amount of Cu migration into HfO2 switching layer.

The Impact of Dielectric Material and Temperature on Dielectric Charging in RF MEMS Capacitive Switches

Science.gov (United States)

Papaioannou, George

The present work attempts to provide a better insight on the dielectric charging in RF-MEMS capacitive switches that constitutes a key issue limiting parameter of their commercialization. The dependence of the charging process on the nature of dielectric materials widely used in these devices, such as SiO2, Si3N4, AlN, Al2O3, Ta2O5, HfO2, which consist of covalent or ionic bonds and may exhibit piezoelectric properties is discussed taking into account the effect of deposition conditions and resulting material stoichiometry. Another key issue parameter that accelerates the charging and discharging processes by providing enough energy to trapped charges to be released and to dipoles to overcome potential barriers and randomize their orientation is the temperature will be investigated too. Finally, the effect of device structure will be also taken into account.

Investigation of various properties of HfO2-TiO2 thin film composites deposited by multi-magnetron sputtering system

Science.gov (United States)

Mazur, M.; Poniedziałek, A.; Kaczmarek, D.; Wojcieszak, D.; Domaradzki, J.; Gibson, D.

2017-11-01

In this work the properties of hafnium dioxide (HfO2), titanium dioxide (TiO2) and mixed HfO2-TiO2 thin films with various amount of titanium addition, deposited by magnetron sputtering were described. Structural, surface, optical and mechanical properties of deposited coatings were analyzed. Based on X-ray diffraction and Raman scattering measuremets it was observed that there was a significant influence of titanium concentration in mixed TiO2-HfO2 thin films on their microstructure. Increase of Ti content in prepared mixed oxides coatings caused, e.g. a decrease of average crystallite size and amorphisation of the coatings. As-deposited hafnia and titania thin films exhibited nanocrystalline structure of monoclinic phase and mixed anatase-rutile phase for HfO2 and TiO2 thin films, respectively. Atomic force microscopy investigations showed that the surface of deposited thin films was densely packed, crack-free and composed of visible grains. Surface roughness and the value of water contact angle decreased with the increase of Ti content in mixed oxides. Results of optical studies showed that all deposited thin films were well transparent in a visible light range. The effect of the change of material composition on the cut-off wavelength, refractive index and packing density was also investigated. Performed measurements of mechanical properties revealed that hardness and Young's elastic modulus of thin films were dependent on material composition. Hardness of thin films increased with an increase of Ti content in thin films, from 4.90 GPa to 13.7 GPa for HfO2 and TiO2, respectively. The results of the scratch resistance showed that thin films with proper material composition can be used as protective coatings in optical devices.

Characterization of luminescent samarium doped HfO2 coatings synthesized by spray pyrolysis technique

International Nuclear Information System (INIS)

Chacon-Roa, C; Guzman-Mendoza, J; Aguilar-Frutis, M; Garcia-Hipolito, M; Alvarez-Fragoso, O; Falcony, C

2008-01-01

Trivalent samarium (Sm 3+ ) doped hafnium oxide (HfO 2 ) films were deposited using the spray pyrolysis deposition technique. The films were deposited on Corning glass substrates at temperatures ranging from 300 to 550 deg. C using chlorides as raw materials. Films, mostly amorphous, were obtained when deposition temperatures were below 350 deg. C. However, for temperatures higher than 400 deg. C, the films became polycrystalline, presenting the HfO 2 monoclinic phase. Scanning electron microscopy of the films revealed a rough surface morphology with spherical particles. Also, electron energy dispersive analysis was performed on these films. The photoluminescence and cathodoluminescence characteristics of the HfO 2 : SmCl 3 films, measured at room temperature, exhibited four main bands centred at 570, 610, 652 and 716 nm, which are due to the well-known intra-4f transitions of the Sm 3+ ion. It was found that the overall emission intensity rose as the deposition temperature was increased. Furthermore, a concentration quenching of the luminescence intensity was also observed

Breakdown of coupling dielectrics for Si microstrip detectors

International Nuclear Information System (INIS)

Candelori, A.; Paccagnella, A.; Padova Univ.; Saglimbeni, G.

1999-01-01

Double-layer coupling dielectrics for AC-coupled Si microstrip detectors have been electrically characterized in order to determine their performance in a radiation-harsh environment, with a focus on the dielectric breakdown. Two different dielectric technologies have been investigated: SiO 2 /TEOS and SiO 2 /Si 3 N 4 . Dielectrics have been tested by using a negative gate voltage ramp of 0.2 MV/(cm·s). The metal/insulator/Si I-V characteristics show different behaviours depending on the technology. The extrapolated values of the breakdown field for unirradiated devices are significantly higher for SiO 2 /Si 3 N 4 dielectrics, but the data dispersion is lower for SiO 2 /TEOS devices. No significant variation of the breakdown field has been measured after a 10 Mrad (Si) γ irradiation for SiO 2 /Si 3 N 4 dielectrics. Finally, the SiO 2 /Si 3 N 4 DC conduction is enhanced if a positive gate voltage ramp is applied with respect to the negative one, due to the asymmetric conduction of the double-layer dielectric

Effects of trap density on drain current LFN and its model development for E-mode GaN MOS-HEMT

Science.gov (United States)

Panda, D. K.; Lenka, T. R.

2017-12-01

In this paper the drain current low-frequency noise (LFN) of E-mode GaN MOS-HEMT is investigated for different gate insulators such as SiO2, Al2O3/Ga2O3/GdO3, HfO2/SiO2, La2O3/SiO2 and HfO2 with different trap densities by IFM based TCAD simulation. In order to analyze this an analytical model of drain current low frequency noise is developed. The model is developed by considering 2DEG carrier fluctuations, mobility fluctuations and the effects of 2DEG charge carrier fluctuations on the mobility. In the study of different gate insulators it is observed that carrier fluctuation is the dominant low frequency noise source and the non-uniform exponential distribution is critical to explain LFN behavior, so the analytical model is developed by considering uniform distribution of trap density. The model is validated with available experimental data from literature. The effect of total number of traps and gate length scaling on this low frequency noise due to different gate dielectrics is also investigated.

Electrical characteristics of AlO sub x N sub y prepared by oxidation of sub-10-nm-thick AlN films for MOS gate dielectric applications

CERN Document Server

Jeon, S H; Kim, H S; Noh, D Y; Hwang, H S

2000-01-01

In this research, the feasibility of ultrathin AlO sub x N sub y prepared by oxidation of sub 100-A-thick AlN thin films for metal-oxide-semiconductor (MOS) gate dielectric applications was investigated. Oxidation of 51-A-and 98-A-thick as-deposited AlN at 800 .deg. C was used to form 72-A-and 130-A-thick AlO sub x N sub y , respectively. Based on the capacitance-voltage (C-V) measurements of the MOS capacitor, the dielectric constants of 72 A-thick and 130 A-thick Al-oxynitride were 5.15 and 7, respectively. The leakage current of Al-oxynitride at low field was almost the same as that of thermal SiO sub 2. based on the CV data, the interface state density of Al-oxynitride was relatively higher than that of SiO sub 2. Although process optimization is still necessary, the Al-oxynitride exhibits some possibility for future MOS gate dielectric applications.

Electrical characteristics of AlO{sub x}N{sub y} prepared by oxidation of sub-10-nm-thick AlN films for MOS gate dielectric applications

Energy Technology Data Exchange (ETDEWEB)

Jeon, Sang Hun; Jang, Hyeon Woo; Kim, Hyun Soo; Noh, Do Young; Hwang, Hyun Sang [Kwangju Institute of Science and Technology, Kwangju (Korea, Republic of)

2000-12-01

In this research, the feasibility of ultrathin AlO{sub x}N{sub y} prepared by oxidation of sub 100-A-thick AlN thin films for metal-oxide-semiconductor (MOS) gate dielectric applications was investigated. Oxidation of 51-A-and 98-A-thick as-deposited AlN at 800 .deg. C was used to form 72-A-and 130-A-thick AlO{sub x}N{sub y}, respectively. Based on the capacitance-voltage (C-V) measurements of the MOS capacitor, the dielectric constants of 72 A-thick and 130 A-thick Al-oxynitride were 5.15 and 7, respectively. The leakage current of Al-oxynitride at low field was almost the same as that of thermal SiO{sub 2}. based on the CV data, the interface state density of Al-oxynitride was relatively higher than that of SiO{sub 2}. Although process optimization is still necessary, the Al-oxynitride exhibits some possibility for future MOS gate dielectric applications.

Lowered operation voltage in Pt/SBi2Ta2O9/HfO2/Si ferroelectric-gate field-effect transistors by oxynitriding Si

International Nuclear Information System (INIS)

Horiuchi, Takeshi; Takahashi, Mitsue; Li, Qiu-Hong; Wang, Shouyu; Sakai, Shigeki

2010-01-01

Oxynitrided Si (SiON) surfaces show smaller subthreshold swings than do directly nitrided Si (SiN) surfaces when used in ferroelectric-gate field-effect transistors (FeFETs) having the following stacked-gate structure: Pt/SrBi 2 Ta 2 O 9 (SBT)/HfO 2 /Si. SiON/Si substrates for FeFETs were prepared by rapid thermal oxidation (RTO) in O 2 at 1000 °C and subsequent rapid thermal nitridation (RTN) in NH 3 at various temperatures in the range 950–1150 °C. The electrical properties of the Pt/SBT/HfO 2 /SiON/Si FeFET were compared with those of reference FETs, i.e. Pt/SBT/HfO 2 gate stacks formed on Si substrates subjected to various treatments: SiN x /Si formed by RTN, SiO 2 /Si formed by RTO and untreated Si. The Pt/SBT/HfO 2 /SiON/Si FeFET had a larger memory window than all the other reference FeFETs, particularly at low operation voltages when the RTN temperature was 1050 °C

The memory effect of a pentacene field-effect transistor with a polarizable gate dielectric

Science.gov (United States)

Unni, K. N. N.; de Bettignies, Remi; Dabos-Seignon, Sylvie; Nunzi, Jean-Michel

2004-06-01

The nonvolatile transistor memory element is an interesting topic in organic electronics. In this case a memory cell consists of only one device where the stored information is written as a gate insulator polarization by a gate voltage pulse and read by the channel conductance control with channel voltage pulse without destruction of the stored information. Therefore such transistor could be the base of non-volatile non-destructively readable computer memory of extremely high density. Also devices with polarizable gate dielectrics can function more effectively in certain circuits. The effective threshold voltage Vt can be brought very close to zero, for applications where the available gate voltage is limited. Resonant and adaptive circuits can be tuned insitu by polarizing the gates. Poly(vinylidene fluoride), PVDF and its copolymer with trifluoroethylene P(VDF-TrFE) are among the best known and most widely used ferroelectric polymers. In this manuscript, we report new results of an organic FET, fabricated with pentacene as the active material and P(VDF-TrFE) as the gate insulator. Application of a writing voltage of -50 V for short duration results in significant change in the threshold voltage and remarkable increase in the drain current. The memory effect is retained over a period of 20 hours.

Dielectric Modulated FET (DMFET)

Indian Academy of Sciences (India)

First page Back Continue Last page Graphics. Working Principle: Change in Dielectric constant due to immobilization of biomolecules in the nanogap cavity leads to change in effective gate capacitance and thus gate bias for FET. Working Principle: Change in Dielectric constant due to immobilization of biomolecules in the ...

Structural Evaluation of 5,5′-Bis(naphth-2-yl)-2,2′-bithiophene in Organic Field-Effect Transistors with n-Octadecyltrichlorosilane Coated SiO2 Gate Dielectric

DEFF Research Database (Denmark)

Lauritzen, Andreas E.; Torkkeli, Mika; Bikondoa, Oier

2018-01-01

We report on the structure and morphology of 5,5′-bis(naphth-2-yl)-2,2′-bithiophene (NaT2) films in bottom-contact organic field-effect transistors (OFETs) with octadecyltrichlorosilane (OTS) coated SiO2 gate dielectric, characterized by atomic force microscopy (AFM), grazing-incidence X......-ray diffraction (GIXRD), and electrical transport measurements. Three types of devices were investigated with the NaT2 thin-film deposited either on (1) pristine SiO2 (corresponding to higher surface energy, 47 mJ/m2) or on OTS deposited on SiO2 under (2) anhydrous or (3) humid conditions (corresponding to lower...... surface energies, 20–25 mJ/m2). NaT2 films grown on pristine SiO2 form nearly featureless three-dimensional islands. NaT2 films grown on OTS/SiO2 deposited under anhydrous conditions form staggered pyramid islands where the interlayer spacing corresponds to the size of the NaT2 unit cell. At the same time...

Vacancy-fluorine complexes and their impact on the properties of metal-oxide transistors with high-k gate dielectrics studied using monoenergetic positron beams

Science.gov (United States)

Uedono, A.; Inumiya, S.; Matsuki, T.; Aoyama, T.; Nara, Y.; Ishibashi, S.; Ohdaira, T.; Suzuki, R.; Miyazaki, S.; Yamada, K.

2007-09-01

Vacancy-fluorine complexes in metal-oxide semiconductors (MOS) with high-k gate dielectrics were studied using a positron annihilation technique. F+ ions were implanted into Si substrates before the deposition of gate dielectrics (HfSiON). The shift of threshold voltage (Vth) in MOS capacitors and an increase in Fermi level position below the HfSiON/Si interface were observed after F+ implantation. Doppler broadening spectra of the annihilation radiation and positron lifetimes were measured before and after HfSiON fabrication processes. From a comparison between Doppler broadening spectra and those obtained by first-principles calculation, the major defect species in Si substrates after annealing treatment (1050 °C, 5 s) was identified as vacancy-fluorine complexes (V3F2). The origin of the Vth shift in the MOS capacitors was attributed to V3F2 located in channel regions.

Al-, Y-, and La-doping effects favoring intrinsic and field induced ferroelectricity in HfO2: A first principles study

Science.gov (United States)

Materlik, Robin; Künneth, Christopher; Falkowski, Max; Mikolajick, Thomas; Kersch, Alfred

2018-04-01

III-valent dopants have shown to be most effective in stabilizing the ferroelectric, crystalline phase in atomic layer deposited, polycrystalline HfO2 thin films. On the other hand, such dopants are commonly used for tetragonal and cubic phase stabilization in ceramic HfO2. This difference in the impact has not been elucidated so far. The prospect is a suitable doping to produce ferroelectric HfO2 ceramics with a technological impact. In this paper, we investigate the impact of Al, Y, and La doping, which have experimentally proven to stabilize the ferroelectric Pca21 phase in HfO2, in a comprehensive first-principles study. Density functional theory calculations reveal the structure, formation energy, and total energy of various defects in HfO2. Most relevant are substitutional electronically compensated defects without oxygen vacancy, substitutional mixed compensated defects paired with a vacancy, and ionically compensated defect complexes containing two substitutional dopants paired with a vacancy. The ferroelectric phase is strongly favored with La and Y in the substitutional defect. The mixed compensated defect favors the ferroelectric phase as well, but the strongly favored cubic phase limits the concentration range for ferroelectricity. We conclude that a reduction of oxygen vacancies should significantly enhance this range in Y doped HfO2 thin films. With Al, the substitutional defect hardly favors the ferroelectric phase before the tetragonal phase becomes strongly favored with the increasing concentration. This could explain the observed field induced ferroelectricity in Al-doped HfO2. Further Al defects are investigated, but do not favor the f-phase such that the current explanation remains incomplete for Al doping. According to the simulation, doping alone shows clear trends, but is insufficient to replace the monoclinic phase as the ground state. To explain this fact, some other mechanism is needed.

The influence of thermal treatment on the phase development in HfO2-Al2O3 and ZrO2-Al2O3 systems

International Nuclear Information System (INIS)

Stefanic, G.; Music, S.; Trojko, R.

2005-01-01

Amorphous precursors of HfO 2 -AlO 1.5 and ZrO 2 -AlO 1.5 systems covering the whole concentration range were co-precipitated from aqueous solutions of the corresponding salts. The thermal behaviour of the amorphous precursors was examined by differential thermal analysis, X-ray powder diffraction (XRD), laser Raman spectroscopy and scanning electron microscopy. The crystallization temperature of both systems increased with increase in the AlO 1.5 content, from 530 to 940 deg. C in the HfO 2 -AlO 1.5 system, and from 405 to 915 deg. C in the ZrO 2 -AlO 1.5 system. The results of phase analysis indicate an extended capability for the incorporation of Al 3+ ions in the metastable HfO 2 - and ZrO 2 -type solid solutions obtained after crystallization of amorphous co-gels. Precise determination of lattice parameters, performed using whole-powder-pattern decomposition method, showed that the axial ratio c f /a f in the ZrO 2 - and HfO 2 -type solid solutions with 10 mol% or more of Al 3+ approach 1. The tetragonal symmetry of these samples, as determined by laser Raman spectroscopy, was attributed to the displacement of the oxygen sublattice from the ideal fluorite positions. It was found that the lattice parameters of the ZrO 2 -type solid solutions decreased with increasing Al 3+ content up to ∼10 mol%, whereas above 10 mol%, further increase of the Al 3+ content has very small influence on the unit-cell volume of both HfO 2 - and ZrO 2 -type solid solutions. The reason for such behaviour was discussed. The solubility of Hf 4+ and Zr 4+ ions in the aluminium oxides lattice appeared to be negligible

Electrical performance of multilayer MoS2 transistors on high-κ Al2O3 coated Si substrates

Directory of Open Access Journals (Sweden)

Tao Li

2015-05-01

Full Text Available The electrical performance of MoS2 can be engineered by introducing high-κ dielectrics, while the interactions between high-κ dielectrics and MoS2 need to be studied. In this study, multilayer MoS2 field-effect transistors (FETs with a back-gated configuration were fabricated on high-κ Al2O3 coated Si substrates. Compared with MoS2 FETs on SiO2, the field-effect mobility (μFE and subthreshold swing (SS were remarkably improved in MoS2/Al2O3/Si. The improved μFE was thought to result from the dielectric screening effect from high-κ Al2O3. When a HfO2 passivation layer was introduced on the top of MoS2/Al2O3/Si, the field-effect mobility was further enhanced, which was thought to be concerned with the decreased contact resistance between the metal and MoS2. Meanwhile, the interface trap density increased from 2.4×1012 eV−1cm−2 to 6.3×1012 eV−1cm−2. The increase of the off-state current and the negative shift of the threshold voltage may be related to the increase of interface traps.

Effect of the post-deposition annealing on electrical characteristics of MIS structures with HfO{sub 2}/SiO{sub 2} gate dielectric stacks

Energy Technology Data Exchange (ETDEWEB)

Taube, Andrzej [Institute of Electron Technology, Al. Lotnikow 32/46, 02-668 Warsaw (Poland); Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland); Mroczynski, Robert, E-mail: rmroczyn@elka.pw.edu.pl [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland); Korwin-Mikke, Katarzyna [Institute of Electron Technology, Al. Lotnikow 32/46, 02-668 Warsaw (Poland); Gieraltowska, Sylwia [Institute of Physics, Polish Academy of Sciences, Al. Lotnikow 32/46, 02-668 Warsaw (Poland); Szmidt, Jan [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland); Piotrowska, Anna [Institute of Electron Technology, Al. Lotnikow 32/46, 02-668 Warsaw (Poland)

2012-09-01

In this work, we report on effects of post-deposition annealing on electrical characteristics of metal-insulator-semiconductor (MIS) structures with HfO{sub 2}/SiO{sub 2} double gate dielectric stacks. Obtained results have shown the deterioration of electro-physical properties of MIS structures, e.g. higher interface traps density in the middle of silicon forbidden band (D{sub itmb}), as well as non-uniform distribution and decrease of breakdown voltage (U{sub br}) values, after annealing above 400 Degree-Sign C. Two potential hypothesis of such behavior were proposed: the formation of interfacial layer between hafnia and silicon dioxide and the increase of crystallinity of HfO{sub 2} due to the high temperature treatment. Furthermore, the analysis of conduction mechanisms in investigated stacks revealed Poole-Frenkel (P-F) tunneling at broad range of electric field intensity.

InAs/GaAs quantum-dot intermixing: comparison of various dielectric encapsulants

KAUST Repository

Alhashim, Hala H.

2015-10-16

We report on the impurity-free vacancy-disordering effect in InAs/GaAs quantum-dot (QD) laser structure based on seven dielectric capping layers. Compared to the typical SiO2 and Si3N4 films, HfO2 and SrTiO3 dielectric layers showed superior enhancement and suppression of intermixing up to 725°C, respectively. A QD peak ground-state differential blue shift of >175  nm (>148  meV) is obtained for HfO2 capped sample. Likewise, investigation of TiO2, Al2O3, and ZnO capping films showed unusual characteristics, such as intermixing-control caps at low annealing temperature (650°C) and interdiffusion-promoting caps at high temperatures (≥675°C). We qualitatively compared the degree of intermixing induced by these films by extracting the rate of intermixing and the temperature for ground-state and excited-state convergences. Based on our systematic characterization, we established reference intermixing processes based on seven different dielectric encapsulation materials. The tailored wavelength emission of ∼1060−1200  nm at room temperature and improved optical quality exhibited from intermixed QDs would serve as key materials for eventual realization of low-cost, compact, and agile lasers. Applications include solid-state laser pumping, optical communications, gas sensing, biomedical imaging, green–yellow–orange coherent light generation, as well as addressing photonic integration via area-selective, and postgrowth bandgap engineering.

Development and characterization of ultrathin hafnium titanates as high permittivity gate insulators

Science.gov (United States)

Li, Min

High permittivity or high-kappa materials are being developed for use as gate insulators for future ultrascaled metal oxide semiconductor field effect transistors (MOSFETs). Hafnium containing compounds are the leading candidates. Due to its moderate permittivity, however, it is difficult to achieve HfO2 gate structures with an EOT well below 1.0 nm. One approach to increase HfO2 permittivity is combining it with a very high-kappa material, such as TiO2. In this thesis, we systematically studied the electrical and physical characteristics of high-kappa hafnium titanates films as gate insulators. A series of HfxTi1-xO2 films with well-controlled composition were deposited using an MOCVD system. The physical properties of the films were analyzed using a variety of characterization techniques. X-ray micro diffraction indicates that the Ti-rich thin film is more immune to crystallization. TEM analysis showed that the thick stoichiometric HfTiO 4 film has an orthorhombic structure and large anisotropic grains. The C-V curves from the devices with the hafnium titanates films displayed relatively low hysteresis. In a certain composition range, the interfacial layer (IL) EOT and permittivity of HfxTi1-x O2 increases linearly with increasing Ti. The charge is negative for HfxTi1-xO2/IL and positive for Si/IL interface, and the magnitude increases as Hf increases. For ultra-thin films (less than 2 nm EOT), the leakage current increases with increasing HE Moreover, the Hf-rich sample has weaker temperature dependence of the current. In the MOSFET devices with the hafnium titanates films, normal transistor characteristics were observed, also electron mobility degradation. Next, we investigated the effects that different pre-deposition surface treatments, including HF dipping, NH3 surface nitridation, and HfO2 deposition, have on the electrical properties of hafnium titanates. Surface nitridation shows stronger effect than the thin HfO2 layer. The nitrided samples displayed a

Fabrication of Metal Nanoparticle Arrays in the ZrO2(Y, HfO2(Y, and GeOx Films by Magnetron Sputtering

Directory of Open Access Journals (Sweden)

Oleg Gorshkov

2017-01-01

Full Text Available The single sheet arrays of Au nanoparticles (NPs embedded into the ZrO2(Y, HfO2(Y, and GeOx (x≈2 films have been fabricated by the alternating deposition of the nanometer-thick dielectric and metal films using Magnetron Sputtering followed by annealing. The structure and optical properties of the NP arrays have been studied, subject to the fabrication technology parameters. The possibility of fabricating dense single sheet Au NP arrays in the matrices listed above with controlled NP sizes (within 1 to 3 nm and surface density has been demonstrated. A red shift of the plasmonic optical absorption peak in the optical transmission spectra of the nanocomposite films (in the wavelength band of 500 to 650 nm has been observed. The effect was attributed to the excitation of the collective surface plasmon-polaritons in the dense Au NP arrays. The nanocomposite films fabricated in the present study can find various applications in nanoelectronics (e.g., single electronics, nonvolatile memory devices, integrated optics, and plasmonics.

Effect of heat treatment on properties of HfO2 film deposited by ion-beam sputtering

Science.gov (United States)

Liu, Huasong; Jiang, Yugang; Wang, Lishuan; Li, Shida; Yang, Xiao; Jiang, Chenghui; Liu, Dandan; Ji, Yiqin; Zhang, Feng; Chen, Deying

2017-11-01

The effects of atmosphere heat treatment on optical, stress, and microstructure properties of an HfO2 film deposited by ion-beam sputtering were systematically researched. The relationships among annealing temperature and refractive index, extinction coefficient, physical thickness, forbidden-band width, tape trailer width, Urbach energy, crystal phase structure, and stress were assessed. The results showed that 400 °C is the transformation point, and the microstructure of the HfO2 film changed from an amorphous into mixed-phase structure. Multistage phonons appeared on the HfO2 film, and the trends of the refractive index, extinction coefficient, forbidden-band width change, and Urbach energy shifted from decrease to increase. With the elevation of the annealing temperature, the film thickness increased monotonously, the compressive stress gradually turned to tensile stress, and the transformation temperature point for the stress was between 200 °C and 300 °C. Therefore, the change in the stress is the primary cause for the shifts in thin-film thickness.

Properties of phases in HfO2-TiO2 system

International Nuclear Information System (INIS)

Red'ko, V.P.; Terekhovskij, P.B.; Majster, I.M.; Shevchenko, A.V.; Lopato, L.M.; Dvernyakova, A.A.

1990-01-01

A study was made on axial and linear coefficients of thermal expansion (CTE) of HfO 2 -TiO 2 system samples in concentration range of 25-50 mol% TiO 2 . Samples, containing 35 and 37 mol% TiO 2 , are characterized by the lowest values of linear CTE. Dispersion of the basic substances doesn't affect CTE value. Correlation with axial and linear CTE of samples in ZrO 2 -TiO 2 system was conducted. Presence of anisotropy of change of lattice parameters was supported for samples, containing 37.5 and 40 mol% TiO 2 . Polymorphous transformations for hafnium titanate were not revealed

Theoretical prediction of ion conductivity in solid state HfO2

Science.gov (United States)

Zhang, Wei; Chen, Wen-Zhou; Sun, Jiu-Yu; Jiang, Zhen-Yi

2013-01-01

A theoretical prediction of ion conductivity for solid state HfO2 is carried out in analogy to ZrO2 based on the density functional calculation. Geometric and electronic structures of pure bulks exhibit similarity for the two materials. Negative formation enthalpy and negative vacancy formation energy are found for YSH (yttria-stabilized hafnia) and YSZ (yttria-stabilized zirconia), suggesting the stability of both materials. Low activation energies (below 0.7 eV) of diffusion are found in both materials, and YSH's is a little higher than that of YSZ. In addition, for both HfO2 and ZrO2, the supercells with native oxygen vacancies are also studied. The so-called defect states are observed in the supercells with neutral and +1 charge native vacancy but not in the +2 charge one. It can give an explanation to the relatively lower activation energies of yttria-doped oxides and +2 charge vacancy supercells. A brief discussion is presented to explain the different YSH ion conductivities in the experiment and obtained by us, and we attribute this to the different ion vibrations at different temperatures.

Improved integration of ultra-thin high-k dielectrics in few-layer MoS2 FET by remote forming gas plasma pretreatment

Science.gov (United States)

Wang, Xiao; Zhang, Tian-Bao; Yang, Wen; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

2017-01-01

The effective and high-quality integration of high-k dielectrics on two-dimensional (2D) crystals is essential to the device structure engineering and performance improvement of field-effect transistor (FET) based on the 2D semiconductors. We report a 2D MoS2 transistor with ultra-thin Al2O3 top-gate dielectric (6.1 nm) and extremely low leakage current. Remote forming gas plasma pretreatment was carried out prior to the atomic layer deposition, providing nucleation sites with the physically adsorbed ions on the MoS2 surface. The top gate MoS2 FET exhibited excellent electrical performance, including high on/off current ratio over 109, subthreshold swing of 85 mV/decade and field-effect mobility of 45.03 cm2/V s. Top gate leakage current less than 0.08 pA/μm2 at 4 MV/cm has been obtained, which is the smallest compared with the reported top-gated MoS2 transistors. Such an optimized integration of high-k dielectric in 2D semiconductor FET with enhanced performance is very attractive, and it paves the way towards the realization of more advanced 2D nanoelectronic devices and integrated circuits.

Effect of Advanced Plasma Source bias voltage on properties of HfO2 films prepared by plasma ion assisted electron evaporation from metal hafnium

International Nuclear Information System (INIS)

Zhu, Meiping; Yi, Kui; Arhilger, Detlef; Qi, Hongji; Shao, Jianda

2013-01-01

HfO 2 films, using metal hafnium as starting material, are deposited by plasma-ion assisted electron evaporation with different Advanced Plasma Source (APS) bias voltages. The refractive index and extinction coefficient are calculated, the chemical state and composition, as well as the stress and aging behavior is investigated. Laser induced damage threshold (LIDT) and damage mechanism are also evaluated and discussed. Optical, structural, mechanical and laser induced damage properties of HfO 2 films are found to be sensitive to APS bias voltage. The film stress can be tuned by varying the APS bias voltage. Damage morphologies indicate the LIDT of the HfO 2 films at 1064 nm and 532 nm are dominated by the nodular-defect density in coatings, while the 355 nm LIDT is dominated by the film absorption. HfO 2 films with higher 1064 nm LIDT than samples evaporated from hafnia are achieved with bias voltage of 100 V. - Highlights: • HfO 2 films are evaporated with different Advanced Plasma Source (APS) bias voltages. • Properties of HfO 2 films are sensitive to APS bias voltage. • With a bias voltage of 100 V, HfO 2 coatings without any stress can be achieved. • Higher 1064 nm laser induced damage threshold is achieved at a bias voltage of 100 V

Oxygen vacancy effects in HfO2-based resistive switching memory: First principle study

Directory of Open Access Journals (Sweden)

Yuehua Dai

2016-08-01

Full Text Available The work investigated the shape and orientation of oxygen vacancy clusters in HfO2-base resistive random access memory (ReRAM by using the first-principle method based on the density functional theory. Firstly, the formation energy of different local Vo clusters was calculated in four established orientation systems. Then, the optimized orientation and charger conductor shape were identified by comparing the isosurface plots of partial charge density, formation energy, and the highest isosurface value of oxygen vacancy. The calculated results revealed that the [010] orientation was the optimal migration path of Vo, and the shape of system D4 was the best charge conductor in HfO2, which effectively influenced the SET voltage, formation voltage and the ON/OFF ratio of the device. Afterwards, the PDOS of Hf near Vo and total density of states of the system D4_010 were obtained, revealing the composition of charge conductor was oxygen vacancy instead of metal Hf. Furthermore, the migration barriers of the Vo hopping between neighboring unit cells were calculated along four different orientations. The motion was proved along [010] orientation. The optimal circulation path for Vo migration in the HfO2 super-cell was obtained.

Study of structure and antireflective properties of LaF3/HfO2/SiO2 and LaF3/HfO2/MgF2 trilayers for UV applications

Science.gov (United States)

Marszalek, K.; Jaglarz, J.; Sahraoui, B.; Winkowski, P.; Kanak, J.

2015-01-01

The aim of this paper is to study antireflective properties of the tree-layer systems LaF3/HfO2/SiO2 and LaF3/HfO2/MgF2 deposited on heated optical glass substrates. The films were evaporated by the use two deposition techniques. In first method oxide films were prepared by means of e-gun evaporation in vacuum of 5 × 10-5 mbar in the presence of oxygen. The second was used for the deposition of fluoride films. They were obtained by means of thermal source evaporation. Simulation of reflectance was performed for 1M2H1L (Quarter Wavelength Optical Thickness) film stack on an optical quartz glass with the refractive index n = 1.46. The layer thickness was optimized to achieve the lowest light scattering from glass surface covered with dioxide and fluoride films. The values of the interface roughness were determined through atomic force microscopy measurements. The essence of performed calculation was to find minimum reflectance of light in wide ultraviolet region. The spectral dispersion of the refractive index needed for calculations was determined from ellipsometric measurements using the spectroscopic ellipsometer M2000. Additionally, the total reflectance measurements in integrating sphere coupled with Perkin Elmer 900 spectrophotometer were performed. These investigations allowed to determine the influence of such film features like surface and interface roughness on light scattering.

Oligo- and polymeric FET devices: Thiophene-based active materials and their interaction with different gate dielectrics

International Nuclear Information System (INIS)

Porzio, W.; Destri, S.; Pasini, M.; Bolognesi, A.; Angiulli, A.; Di Gianvincenzo, P.; Natali, D.; Sampietro, M.; Caironi, M.; Fumagalli, L.; Ferrari, S.; Peron, E.; Perissinotti, F.

2006-01-01

Derivatives of both oligo- and polythiophene-based FET were recently considered for low cost electronic applications. In the device optimization, factors like redox reversibility of the molecule/polymer, electronic level compatibility with source/drain electrodes, packing closeness, and orientation versus the electrodes, can determine the overall performance. In addition, a gate insulator with a high dielectric constant, a low leakage current, and capability to promote ordering in the semiconductor is required to increase device performances and to lower the FET operating voltage. In this view, Al 2 O 3 appears a good candidate, although its widespread adoption is limited by the disorder that such oxide induces on the semiconductor with detrimental consequences on semiconductor electrical properties. In this contribution, an overview of recent results obtained on thiophene-derivative-based FET devices, fabricated by different growth techniques, and using both thermally grown SiO 2 and Al 2 O 3 from atomic layer deposition gate insulators will be reported and discussed with particular reference to organic solid state aggregation, morphology, and organic-inorganic interface

Effects of N{sub 2} and NH{sub 3} remote plasma nitridation on the structural and electrical characteristics of the HfO{sub 2} gate dielectrics

Energy Technology Data Exchange (ETDEWEB)

Park, K.-S., E-mail: kunsik@etri.re.kr [RFID/USN Research Department, Electronics and Telecommunications Research Institute, Daejeon 305-700 (Korea, Republic of); Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Daejeon 305-701 (Korea, Republic of); Baek, K.-H.; Kim, D.P.; Woo, J.-C.; Do, L.-M. [RFID/USN Research Department, Electronics and Telecommunications Research Institute, Daejeon 305-700 (Korea, Republic of); No, K.-S. [Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Daejeon 305-701 (Korea, Republic of)

2010-12-01

The remote plasma nitridation (RPN) of an HfO{sub 2} film using N{sub 2} and NH{sub 3} has been investigated comparatively. X-ray photoelectron spectroscopy and Auger electron spectroscopy analyses after post-deposition annealing (PDA) at 700 deg. C show that a large amount of nitrogen is present in the bulk film as well as in the interfacial layer for the HfO{sub 2} film nitrided with NH{sub 3}-RPN. It is also shown that the interfacial layer formed during RPN and PDA is a nitrogen-rich Hf-silicate. The C-V characteristics of an HfO{sub x}N{sub y} gate dielectric nitrided with NH{sub 3}-RPN have a smaller equivalent oxide thickness than that nitrided with N{sub 2}-RPN in spite of its thicker interfacial layer.

An “ohmic-first” self-terminating gate-recess technique for normally-off Al2O3/GaN MOSFET

Science.gov (United States)

Wang, Hongyue; Wang, Jinyan; Li, Mengjun; He, Yandong; Wang, Maojun; Yu, Min; Wu, Wengang; Zhou, Yang; Dai, Gang

2018-04-01

In this article, an ohmic-first AlGaN/GaN self-terminating gate-recess etching technique was demonstrated where ohmic contact formation is ahead of gate-recess-etching/gate-dielectric-deposition (GRE/GDD) process. The ohmic contact exhibits few degradations after the self-terminating gate-recess process. Besides, when comparing with that using the conventional fabrication process, the fabricated device using the ohmic-first fabrication process shows a better gate dielectric quality in terms of more than 3 orders lower forward gate leakage current, more than twice higher reverse breakdown voltage as well as better stability. Based on this proposed technique, the normally-off Al2O3/GaN MOSFET exhibits a threshold voltage (V th) of ˜1.8 V, a maximum drain current of ˜328 mA/mm, a forward gate leakage current of ˜10-6 A/mm and an off-state breakdown voltage of 218 V at room temperature. Meanwhile, high temperature characteristics of the device was also evaluated and small variations (˜7.6%) of the threshold voltage was confirmed up to 300 °C.

Crystal structure and band gap determination of HfO2 thin films

NARCIS (Netherlands)

Cheynet, M.C.; Pokrant, S.; Tichelaar, F.D.; Rouvière, J.L.

2007-01-01

Valence electron energy loss spectroscopy (VEELS) and high resolution transmission electron microscopy (HRTEM) are performed on three different HfO2 thin films grown on Si (001) by chemical vapor deposition (CVD) or atomic layer deposition (ALD). For each sample the band gap (Eg) is determined by

Enhanced PEC performance of nanoporous Si photoelectrodes by covering HfO2 and TiO2 passivation layers

Science.gov (United States)

Xing, Zhuo; Ren, Feng; Wu, Hengyi; Wu, Liang; Wang, Xuening; Wang, Jingli; Wan, Da; Zhang, Guozhen; Jiang, Changzhong

2017-03-01

Nanostructured Si as the high efficiency photoelectrode material is hard to keep stable in aqueous for water splitting. Capping a passivation layer on the surface of Si is an effective way of protecting from oxidation. However, it is still not clear in the different mechanisms and effects between insulating oxide materials and oxide semiconductor materials as passivation layers. Here, we compare the passivation effects, the photoelectrochemical (PEC) properties, and the corresponding mechanisms between the HfO2/nanoporous-Si and the TiO2/nanoporous-Si by I-V curves, Motte-schottky (MS) curves, and electrochemical impedance spectroscopy (EIS). Although the saturated photocurrent densities of the TiO2/nanoporous Si are lower than that of the HfO2/nanoporous Si, the former is more stable than the later.

Enhanced PEC performance of nanoporous Si photoelectrodes by covering HfO2 and TiO2 passivation layers.

Science.gov (United States)

Xing, Zhuo; Ren, Feng; Wu, Hengyi; Wu, Liang; Wang, Xuening; Wang, Jingli; Wan, Da; Zhang, Guozhen; Jiang, Changzhong

2017-03-02

Nanostructured Si as the high efficiency photoelectrode material is hard to keep stable in aqueous for water splitting. Capping a passivation layer on the surface of Si is an effective way of protecting from oxidation. However, it is still not clear in the different mechanisms and effects between insulating oxide materials and oxide semiconductor materials as passivation layers. Here, we compare the passivation effects, the photoelectrochemical (PEC) properties, and the corresponding mechanisms between the HfO 2 /nanoporous-Si and the TiO 2 /nanoporous-Si by I-V curves, Motte-schottky (MS) curves, and electrochemical impedance spectroscopy (EIS). Although the saturated photocurrent densities of the TiO 2 /nanoporous Si are lower than that of the HfO 2 /nanoporous Si, the former is more stable than the later.

Sodium beta-alumina thin films as gate dielectrics for AlGaN/GaN metal—insulator—semiconductor high-electron-mobility transistors

International Nuclear Information System (INIS)

Tian Ben-Lang; Chen Chao; Li Yan-Rong; Zhang Wan-Li; Liu Xing-Zhao

2012-01-01

Sodium beta-alumina (SBA) is deposited on AlGaN/GaN by using a co-deposition process with sodium and Al 2 O 3 as the precursors. The X-ray diffraction (XRD) spectrum reveals that the deposited thin film is amorphous. The binding energy and composition of the deposited thin film, obtained from the X-ray photoelectron spectroscopy (XPS) measurement, are consistent with those of SBA. The dielectric constant of the SBA thin film is about 50. Each of the capacitance—voltage characteristics obtained at five different frequencies shows a high-quality interface between SBA and AlGaN. The interface trap density of metal—insulator—semiconductor high-electron-mobility transistor (MISHEMT) is measured to be (3.5∼9.5)×10 10 cm −2 ·eV −1 by the conductance method. The fixed charge density of SBA dielectric is on the order of 2.7×10 12 cm −2 . Compared with the AlGaN/GaN metal—semiconductor heterostructure high-electron-mobility transistor (MESHEMT), the AlGaN/GaN MISHEMT usually has a threshold voltage that shifts negatively. However, the threshold voltage of the AlGaN/GaN MISHEMT using SBA as the gate dielectric shifts positively from −5.5 V to −3.5 V. From XPS results, the surface valence-band maximum (VBM-EF) of AlGaN is found to decrease from 2.56 eV to 2.25 eV after the SBA thin film deposition. The possible reasons why the threshold voltage of AlGaN/GaN MISHEMT with the SBA gate dielectric shifts positively are the influence of SBA on surface valence-band maximum (VBM-EF), the reduction of interface traps and the effects of sodium ions, and/or the fixed charges in SBA on the two-dimensional electron gas (2DEG). (condensed matter: structural, mechanical, and thermal properties)

High temperature X-ray diffraction studies on HfO2-Gd2O3 system

International Nuclear Information System (INIS)

Panneerselvam, G.; Antony, M.P.; Ananthasivan, K.; Joseph, M.

2016-01-01

High temperature X-ray diffraction (HTXRD) technique is an important experimental tool for measuring thermal expansion of materials of interest. A series of solid solutions containing GdO 1.5 in HfO 2 ,Hf 1-y Gd y )O 2 (y = 0.15, 0.2, 0.3, 0.41 and 0.505) were prepared by solid state method. Structural characterization and computation of lattice parameter was carried out by using room temperature X-ray diffraction measurements. The room temperature lattice parameter estimated for (Hf 1-y Gd y )O 2 (y=0.15, 0.2, 0.3, 0.41 and 0.505) are 0.51714 nm, 0.51929 nm, 0.52359nm, 0.52789nm and 0.53241 nm, respectively. Thermal expansion coefficients and percentage linear thermal expansion of the HfO 2 -Gd 2 O 3 solid solutions containing 20 and 41 mol% GdO 1.5 were determined using HTXRD in the temperature range 298 to 1673K. The mean linear thermal expansion coefficients of the solid solutions containing 20 and 41 mol. %Gd are 11.65 x 10 -6 K -1 and 12.07 x 10 -6 K -1 , respectively. (author)

Optimum source/drain overlap design for 16 nm high-k/metal gate MOSFETs

International Nuclear Information System (INIS)

Jang, Junyong; Lim, Towoo; Kim, Youngmin

2009-01-01

We explore a source/drain (S/D) design for a 16 nm MOSFET utilizing a replacement process for a high-k gate dielectric and metal gate electrode integration. Using TCAD simulation, a trade-off study between series resistance and overlap capacitance is carried out for a high-k dielectric surrounding gate structure, which results from the replacement process. An optimum S/D overlap to gate for the high-k surrounding gate structure is found to be different from the conventional gate structure, i.e. 0∼1 nm underlap is preferred for the surround high-k gate structure while 1∼2 nm overlap for the conventional gate one

Modeling and Implementation of HfO2-based Ferroelectric Tunnel Junctions

Science.gov (United States)

Pringle, Spencer Allen

HfO2-based ferroelectric tunnel junctions (FTJs) represent a unique opportunity as both a next-generation digital non-volatile memory and as synapse devices in braininspired logic systems, owing to their higher reliability compared to filamentary resistive random-access memory (ReRAM) and higher speed and lower power consumption compared to competing devices, including phase-change memory (PCM) and state-of-the-art FTJ. Ferroelectrics are often easier to deposit and have simpler material structure than films for magnetic tunnel junctions (MTJs). Ferroelectric HfO2 also enables complementary metal-oxide-semiconductor (CMOS) compatibility, since lead zirconate titanate (PZT) and BaTiO3-based FTJs often are not. No other groups have yet demonstrated a HfO2-based FTJ (to best of the author's knowledge) or applied it to a suitable system. For such devices to be useful, system designers require models based on both theoretical physical analysis and experimental results of fabricated devices in order to confidently design control systems. Both the CMOS circuitry and FTJs must then be designed in layout and fabricated on the same die. This work includes modeling of proposed device structures using a custom python script, which calculates theoretical potential barrier heights as a function of material properties and corresponding current densities (ranging from 8x103 to 3x10-2 A/cm 2 with RHRS/RLRS ranging from 5x105 to 6, depending on ferroelectric thickness). These equations were then combined with polynomial fits of experimental timing data and implemented in a Verilog-A behavioral analog model in Cadence Virtuoso. The author proposes tristate CMOS control systems, and circuits, for implementation of FTJ devices as digital memory and presents simulated performance. Finally, a process flow for fabrication of FTJ devices with CMOS is presented. This work has therefore enabled the fabrication of FTJ devices at RIT and the continued investigation of them as applied to any

Intermixing between HfO2 and GeO2 films deposited on Ge(001) and Si(001): Role of the substrate

International Nuclear Information System (INIS)

Soares, G. V.; Krug, C.; Miotti, L.; Bastos, K. P.; Lucovsky, G.; Baumvol, I. J. R.; Radtke, C.

2011-01-01

Thermally driven atomic transport in HfO 2 /GeO 2 /substrate structures on Ge(001) and Si(001) was investigated in N 2 ambient as function of annealing temperature and time. As-deposited stacks showed no detectable intermixing and no instabilities were observed on Si. On Ge, loss of O and Ge was detected in all annealed samples, presumably due to evolution of GeO from the GeO 2 /Ge interface. In addition, hafnium germanate is formed at 600 deg. C. Our data indicate that at 500 deg. C and above HfO 2 /GeO 2 stacks are stable only if isolated from the Ge substrate.

Thermal effects on the Raman phonon of few-layer phosphorene

International Nuclear Information System (INIS)

Ling, Zhi-Peng; Ang, Kah-Wee

2015-01-01

Two-dimensional phosphorene is a promising channel material for next generation transistor applications due to its superior carrier transport property. Here, we report the influence of thermal effects on the Raman phonon of few-layer phosphorene formed on hafnium-dioxide (HfO 2 ) high-k dielectric. When annealed at elevated temperatures (up to 200 °C), the phosphorene film was found to exhibit a blue shift in both the out-of-plane (A 1 g ) and in-plane (B 2g and A 2 g ) phonon modes as a result of compressive strain effect. This is attributed to the out-diffusion of hafnium (Hf) atoms from the underlying HfO 2 dielectric, which compresses the phosphorene in both the zigzag and armchair directions. With a further increase in thermal energy beyond 250 °C, strain relaxation within phosphorene eventually took place. When this happens, the phosphorene was unable to retain its intrinsic crystallinity prior to annealing, as evident from the broadening of full-width at half maximum of the Raman phonon. These results provide an important insight into the impact of thermal effects on the structural integrity of phosphorene when integrated with high-k gate dielectric

Physical and electrical characteristics of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with rare earth Er2O3 as a gate dielectric

International Nuclear Information System (INIS)

Lin, Ray-Ming; Chu, Fu-Chuan; Das, Atanu; Liao, Sheng-Yu; Chou, Shu-Tsun; Chang, Liann-Be

2013-01-01

In this study, the rare earth erbium oxide (Er 2 O 3 ) was deposited using an electron beam onto an AlGaN/GaN heterostructure to fabricate metal-oxide-semiconductor high-electron-mobility transistors (MOS–HEMTs) that exhibited device performance superior to that of a conventional HEMT. Under similar bias conditions, the gate leakage currents of these MOS–HEMT devices were four orders of magnitude lower than those of conventional Schottky gate HEMTs. The measured sub-threshold swing (SS) and the effective trap state density (N t ) of the MOS–HEMT were 125 mV/decade and 4.3 × 10 12 cm −2 , respectively. The dielectric constant of the Er 2 O 3 layer in this study was 14, as determined through capacitance–voltage measurements. In addition, the gate–source reverse breakdown voltage increased from –166 V for the conventional HEMT to –196 V for the Er 2 O 3 MOS–HEMT. - Highlights: ► GaN/AlGaN/Er 2 O 3 metal-oxide semiconductor high electron mobility transistor ► Physical and electrical characteristics are presented. ► Electron beam evaporated Er 2 O 3 with excellent surface roughness ► Device exhibits reduced gate leakage current and improved I ON /I OFF ratio

SnO2 anode surface passivation by atomic layer deposited HfO2 improves li-ion battery performance

KAUST Repository

Yesibolati, Nulati; Shahid, Muhammad; Chen, Wei; Hedhili, Mohamed N.; Reuter, Mark C.; Ross, Frances M.; Alshareef, Husam N.

2014-01-01

For the first time, it is demonstrated that nanoscale HfO2 surface passivation layers formed by atomic layer deposition (ALD) significantly improve the performance of Li ion batteries with SnO2-based anodes. Specifically, the measured battery

Effects of the gate dielectric on the subthreshold transport of carbon nanotube network transistors grown by using plasma-enhanced chemical vapor deposition

International Nuclear Information System (INIS)

Jeong, Seung Geun; Park, Wan Jun

2010-01-01

In this study, we investigated the subthreshold slope of random network carbon nanotube transistors with different geometries and passivations. Single-wall carbon nanotubes with lengths of 1-2 m were grown by using plasma-enhanced chemical vapor deposition to form the transistor channels. A critical channel length, where the subthreshold slope was saturated, of 7 μm was obtained. This was due to the percolational behavior of the nanotube random networks. With the dielectric passivation, the subthreshold slope was dramatically reduced from 9 V/decade to 0.9 V/decade by reducing interfacial trap sites, which then reduced the interface capacitance between the nanotube network and the gate dielectric.

Comparative analysis of the effects of tantalum doping and annealing on atomic layer deposited (Ta2O5)x(Al2O3)1−x as potential gate dielectrics for GaN/AlxGa1−xN/GaN high electron mobility transistors

International Nuclear Information System (INIS)

Partida-Manzanera, T.; Roberts, J. W.; Sedghi, N.; Potter, R. J.; Bhat, T. N.; Zhang, Z.; Tan, H. R.; Dolmanan, S. B.; Tripathy, S.

2016-01-01

This paper describes a method to optimally combine wide band gap Al 2 O 3 with high dielectric constant (high-κ) Ta 2 O 5 for gate dielectric applications. (Ta 2 O 5 ) x (Al 2 O 3 ) 1−x thin films deposited by thermal atomic layer deposition (ALD) on GaN-capped Al x Ga 1−x N/GaN high electron mobility transistor (HEMT) structures have been studied as a function of the Ta 2 O 5 molar fraction. X-ray photoelectron spectroscopy shows that the bandgap of the oxide films linearly decreases from 6.5 eV for pure Al 2 O 3 to 4.6 eV for pure Ta 2 O 5 . The dielectric constant calculated from capacitance-voltage measurements also increases linearly from 7.8 for Al 2 O 3 up to 25.6 for Ta 2 O 5 . The effect of post-deposition annealing in N 2 at 600 °C on the interfacial properties of undoped Al 2 O 3 and Ta-doped (Ta 2 O 5 ) 0.12 (Al 2 O 3 ) 0.88 films grown on GaN-HEMTs has been investigated. These conditions are analogous to the conditions used for source/drain contact formation in gate-first HEMT technology. A reduction of the Ga-O to Ga-N bond ratios at the oxide/HEMT interfaces is observed after annealing, which is attributed to a reduction of interstitial oxygen-related defects. As a result, the conduction band offsets (CBOs) of the Al 2 O 3 /GaN-HEMT and (Ta 2 O 5 ) 0.16 (Al 2 O 3 ) 0.84 /GaN-HEMT samples increased by ∼1.1 eV to 2.8 eV and 2.6 eV, respectively, which is advantageous for n-type HEMTs. The results demonstrate that ALD of Ta-doped Al 2 O 3 can be used to control the properties of the gate dielectric, allowing the κ-value to be increased, while still maintaining a sufficient CBO to the GaN-HEMT structure for low leakage currents

Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

KAUST Repository

Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Young, Chadwin D.; Bersuker, Gennadi; Hussain, Muhammad Mustafa

2015-01-01

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard

Tunable Mobility in Double-Gated MoTe2 Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites.

Science.gov (United States)

Ji, Hyunjin; Joo, Min-Kyu; Yi, Hojoon; Choi, Homin; Gul, Hamza Zad; Ghimire, Mohan Kumar; Lim, Seong Chu

2017-08-30

There is a general consensus that the carrier mobility in a field-effect transistor (FET) made of semiconducting transition-metal dichalcogenides (s-TMDs) is severely degraded by the trapping/detrapping and Coulomb scattering of carriers by ionic charges in the gate oxides. Using a double-gated (DG) MoTe 2 FET, we modulated and enhanced the carrier mobility by adjusting the top- and bottom-gate biases. The relevant mechanism for mobility tuning in this device was explored using static DC and low-frequency (LF) noise characterizations. In the investigations, LF-noise analysis revealed that for a strong back-gate bias the Coulomb scattering of carriers by ionized traps in the gate dielectrics is strongly screened by accumulation charges. This significantly reduces the electrostatic scattering of channel carriers by the interface trap sites, resulting in increased mobility. The reduction of the number of effective trap sites also depends on the gate bias, implying that owing to the gate bias, the carriers are shifted inside the channel. Thus, the number of active trap sites decreases as the carriers are repelled from the interface by the gate bias. The gate-controlled Coulomb-scattering parameter and the trap-site density provide new handles for improving the carrier mobility in TMDs, in a fundamentally different way from dielectric screening observed in previous studies.

Change in carrier type in high-k gate carbon nanotube field-effect transistors by interface fixed charges

International Nuclear Information System (INIS)

Moriyama, N; Ohno, Y; Kitamura, T; Kishimoto, S; Mizutani, T

2010-01-01

We study the phenomenon of change in carrier type in carbon nanotube field-effect transistors (CNFETs) caused by the atomic layer deposition (ALD) of a HfO 2 gate insulator. When a HfO 2 layer is deposited on a CNFET, the type of carrier changes from p-type to n-type. The so-obtained n-type device has good performance and stability in air. The conductivity of such a device with a channel length of 0.7 μm is 11% of the quantum conductance 4e 2 /h. The contact resistance for electron current is estimated to be 14 kΩ. The n-type conduction of this CNFET is maintained for more than 100 days. The change in carrier type is attributed to positive fixed charges introduced at the interface between the HfO 2 and SiO 2 layers. We also propose a novel technique to control the type of conduction by utilizing interface fixed charges; this technique is compatible with Si CMOS process technology.

Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process

International Nuclear Information System (INIS)

Wang Yan-Rong; Yang Hong; Xu Hao; Wang Xiao-Lei; Luo Wei-Chun; Qi Lu-Wei; Zhang Shu-Xiang; Wang Wen-Wu; Yan Jiang; Zhu Hui-Long; Zhao Chao; Chen Da-Peng; Ye Tian-Chun

2015-01-01

A multi-deposition multi-annealing technique (MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device’s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown (TDDB) characteristics of positive channel metal oxide semiconductor (PMOS) under different MDMA process conditions, including the deposition/annealing (D and A) cycles, the D and A time, and the total annealing time. The results show that the increases of the number of D and A cycles (from 1 to 2) and D and A time (from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail (TTF) at 63.2% increases by about several times. However, too many D and A cycles (such as 4 cycles) make the equivalent oxide thickness (EOT) increase by about 1 Å and the TTF of PMOS worsen. Moreover, different D and A times and numbers of D and A cycles induce different breakdown mechanisms. (paper)

Low-temperature fabrication of an HfO2 passivation layer for amorphous indium-gallium-zinc oxide thin film transistors using a solution process.

Science.gov (United States)

Hong, Seonghwan; Park, Sung Pyo; Kim, Yeong-Gyu; Kang, Byung Ha; Na, Jae Won; Kim, Hyun Jae

2017-11-24

We report low-temperature solution processing of hafnium oxide (HfO 2 ) passivation layers for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). At 150 °C, the hafnium chloride (HfCl 4 ) precursor readily hydrolyzed in deionized (DI) water and transformed into an HfO 2 film. The fabricated HfO 2 passivation layer prevented any interaction between the back surface of an a-IGZO TFT and ambient gas. Moreover, diffused Hf 4+ in the back-channel layer of the a-IGZO TFT reduced the oxygen vacancy, which is the origin of the electrical instability in a-IGZO TFTs. Consequently, the a-IGZO TFT with the HfO 2 passivation layer exhibited improved stability, showing a decrease in the threshold voltage shift from 4.83 to 1.68 V under a positive bias stress test conducted over 10,000 s.

Tunneling current in HfO2 and Hf0.5Zr0.5O2-based ferroelectric tunnel junction

Science.gov (United States)

Dong, Zhipeng; Cao, Xi; Wu, Tong; Guo, Jing

2018-03-01

Ferroelectric tunnel junctions (FTJs) have been intensively explored for future low power data storage and information processing applications. Among various ferroelectric (FE) materials studied, HfO2 and H0.5Zr0.5O2 (HZO) have the advantage of CMOS process compatibility. The validity of the simple effective mass approximation, for describing the tunneling process in these materials, is examined by computing the complex band structure from ab initio simulations. The results show that the simple effective mass approximation is insufficient to describe the tunneling current in HfO2 and HZO materials, and quantitative accurate descriptions of the complex band structures are indispensable for calculation of the tunneling current. A compact k . p Hamiltonian is parameterized to and validated by ab initio complex band structures, which provides a method for efficiently and accurately computing the tunneling current in HfO2 and HZO. The device characteristics of a metal/FE/metal structure and a metal/FE/semiconductor (M-F-S) structure are investigated by using the non-equilibrium Green's function formalism with the parameterized effective Hamiltonian. The result shows that the M-F-S structure offers a larger resistance window due to an extra barrier in the semiconductor region at off-state. A FTJ utilizing M-F-S structure is beneficial for memory design.

Dry etching of MgCaO gate dielectric and passivation layers on GaN

International Nuclear Information System (INIS)

Hlad, M.; Voss, L.; Gila, B.P.; Abernathy, C.R.; Pearton, S.J.; Ren, F.

2006-01-01

MgCaO films grown by rf plasma-assisted molecular beam epitaxy and capped with Sc 2 O 3 are promising candidates as surface passivation layers and gate dielectrics on GaN-based high electron mobility transistors (HEMTs) and metal-oxide semiconductor HEMTs (MOS-HEMTs), respectively. Two different plasma chemistries were examined for etching these thin films on GaN. Inductively coupled plasmas of CH 4 /H 2 /Ar produced etch rates only in the range 20-70 A/min, comparable to the Ar sputter rates under the same conditions. Similarly slow MgCaO etch rates (∼100 A/min) were obtained with Cl 2 /Ar discharges under the same conditions, but GaN showed rates almost an order of magnitude higher. The MgCaO removal rates are limited by the low volatilities of the respective etch products. The CH 4 /H 2 /Ar plasma chemistry produced a selectivity of around 2 for etching the MgCaO with respect to GaN

TaN interface properties and electric field cycling effects on ferroelectric Si-doped HfO2 thin films

International Nuclear Information System (INIS)

Lomenzo, Patrick D.; Nishida, Toshikazu; Takmeel, Qanit; Zhou, Chuanzhen; Fancher, Chris M.; Jones, Jacob L.; Lambers, Eric; Rudawski, Nicholas G.; Moghaddam, Saeed

2015-01-01

Ferroelectric HfO 2 -based thin films, which can exhibit ferroelectric properties down to sub-10 nm thicknesses, are a promising candidate for emerging high density memory technologies. As the ferroelectric thickness continues to shrink, the electrode-ferroelectric interface properties play an increasingly important role. We investigate the TaN interface properties on 10 nm thick Si-doped HfO 2 thin films fabricated in a TaN metal-ferroelectric-metal stack which exhibit highly asymmetric ferroelectric characteristics. To understand the asymmetric behavior of the ferroelectric characteristics of the Si-doped HfO 2 thin films, the chemical interface properties of sputtered TaN bottom and top electrodes are probed with x-ray photoelectron spectroscopy. Ta-O bonds at the bottom electrode interface and a significant presence of Hf-N bonds at both electrode interfaces are identified. It is shown that the chemical heterogeneity of the bottom and top electrode interfaces gives rise to an internal electric field, which causes the as-grown ferroelectric domains to preferentially polarize to screen positively charged oxygen vacancies aggregated at the oxidized bottom electrode interface. Electric field cycling is shown to reduce the internal electric field with a concomitant increase in remanent polarization and decrease in relative permittivity. Through an analysis of pulsed transient switching currents, back-switching is observed in Si-doped HfO 2 thin films with pinched hysteresis loops and is shown to be influenced by the internal electric field

Comparison of effective relative dielectric permittivities obtained by three independent ways for CeO2-Sm2O3 films prepared by EB-PVD (+IBAD) techniques

International Nuclear Information System (INIS)

Kundracik, F.; Neilinger, P.; Hartmanova, M.; Nadazdy, V.; Mansilla, C.

2011-01-01

Ceria, as material with relatively high dielectric permittivity, ε r , and ability to form films on the Si substrate, is a candidate for the gate dielectrics in the MOS devices. Doping with suitable e.g. trivalent rare earth oxides and suitable treatment after deposition (preparation) can improve their properties, e.g. ionic conductivity, dielectric permittivity and mechanical hardness. In this work, the dielectric properties of CeO 2 + Sm 2 O 3 films prepared by electron beam physical vapour deposition (EB-PVD) and some of them simultaneously also by the Ar + ionic beam assisted deposition (IBAD) techniques are analysed. (authors)

Mechanisms for plasma etching of HfO{sub 2} gate stacks with Si selectivity and photoresist trimming

Energy Technology Data Exchange (ETDEWEB)

Shoeb, Juline; Kushner, Mark J. [Department of Electrical and Computer Engineering, Iowa State University, Ames, Iowa 50011 (United States); Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109-2122 (United States)

2009-11-15

To minimize leakage currents resulting from the thinning of the insulator in the gate stack of field effect transistors, high-dielectric constant (high-k) metal oxides, and HfO{sub 2} in particular, are being implemented as a replacement for SiO{sub 2}. To speed the rate of processing, it is desirable to etch the gate stack (e.g., metal gate, antireflection layers, and dielectric) in a single process while having selectivity to the underlying Si. Plasma etching using Ar/BCl{sub 3}/Cl{sub 2} mixtures effectively etches HfO{sub 2} while having good selectivity to Si. In this article, results from integrated reactor and feature scale modeling of gate-stack etching in Ar/BCl{sub 3}/Cl{sub 2} plasmas, preceded by photoresist trimming in Ar/O{sub 2} plasmas, are discussed. It was found that BCl{sub n} species react with HfO{sub 2}, which under ion impact, form volatile etch products such as B{sub m}OCl{sub n} and HfCl{sub n}. Selectivity to Si is achieved by creating Si-B bonding as a precursor to the deposition of a BCl{sub n} polymer which slows the etch rate relative to HfO{sub 2}. The low ion energies required to achieve this selectivity then challenge one to obtain highly anisotropic profiles in the metal gate portion of the stack. Validation was performed with data from literature. The effect of bias voltage and key reactant probabilities on etch rate, selectivity, and profile are discussed.

Resistive switching characteristics of HfO2-based memory devices on flexible plastics.

Science.gov (United States)

Han, Yong; Cho, Kyoungah; Park, Sukhyung; Kim, Sangsig

2014-11-01

In this study, we examine the characteristics of HfO2-based resistive switching random access memory (ReRAM) devices on flexible plastics. The Pt/HfO2/Au ReRAM devices exhibit the unipolar resistive switching behaviors caused by the conducting filaments. From the Auger depth profiles of the HfO2 thin film, it is confirmed that the relatively lower oxygen content in the interface of the bottom electrode is responsible for the resistive switching by oxygen vacancies. And the unipolar resistive switching behaviors are analyzed from the C-V characteristics in which negative and positive capacitances are measured in the low-resistance state and the high-resistance state, respectively. The devices have a high on/off ratio of 10(4) and the excellent retention properties even after a continuous bending test of two thousand cycles. The correlation between the device size and the memory characteristics is investigated as well. A relatively smaller-sized device having a higher on/off ratio operates at a higher voltage than a relatively larger-sized device.

Effects of H2 High-pressure Annealing on HfO2/Al2O3/In0.53Ga0.47As Capacitors: Chemical Composition and Electrical Characteristics.

Science.gov (United States)

Choi, Sungho; An, Youngseo; Lee, Changmin; Song, Jeongkeun; Nguyen, Manh-Cuong; Byun, Young-Chul; Choi, Rino; McIntyre, Paul C; Kim, Hyoungsub

2017-08-29

We studied the impact of H 2 pressure during post-metallization annealing on the chemical composition of a HfO 2 /Al 2 O 3 gate stack on a HCl wet-cleaned In 0.53 Ga 0.47 As substrate by comparing the forming gas annealing (at atmospheric pressure with a H 2 partial pressure of 0.04 bar) and H 2 high-pressure annealing (H 2 -HPA at 30 bar) methods. In addition, the effectiveness of H 2 -HPA on the passivation of the interface states was compared for both p- and n-type In 0.53 Ga 0.47 As substrates. The decomposition of the interface oxide and the subsequent out-diffusion of In and Ga atoms toward the high-k film became more significant with increasing H 2 pressure. Moreover, the increase in the H 2 pressure significantly improved the capacitance‒voltage characteristics, and its effect was more pronounced on the p-type In 0.53 Ga 0.47 As substrate. However, the H 2 -HPA induced an increase in the leakage current, probably because of the out-diffusion and incorporation of In/Ga atoms within the high-k stack.

Impact of oxygen precursor flow on the forward bias behavior of MOCVD-Al2O3 dielectrics grown on GaN

Science.gov (United States)

Chan, Silvia H.; Bisi, Davide; Liu, Xiang; Yeluri, Ramya; Tahhan, Maher; Keller, Stacia; DenBaars, Steven P.; Meneghini, Matteo; Mishra, Umesh K.

2017-11-01

This paper investigates the effects of the oxygen precursor flow supplied during metalorganic chemical vapor deposition (MOCVD) of Al2O3 films on the forward bias behavior of Al2O3/GaN metal-oxide-semiconductor capacitors. The low oxygen flow (100 sccm) delivered during the in situ growth of Al2O3 on GaN resulted in films that exhibited a stable capacitance under forward stress, a lower density of stress-generated negative fixed charges, and a higher dielectric breakdown strength compared to Al2O3 films grown under high oxygen flow (480 sccm). The low oxygen grown Al2O3 dielectrics exhibited lower gate current transients in stress/recovery measurements, providing evidence of a reduced density of trap states near the GaN conduction band and an enhanced robustness under accumulated gate stress. This work reveals oxygen flow variance in MOCVD to be a strategy for controlling the dielectric properties and performance.

Formation and disruption of conductive filaments in a HfO2/TiN structure

International Nuclear Information System (INIS)

Brivio, S; Tallarida, G; Cianci, E; Spiga, S

2014-01-01

The process of the formation and disruption of nanometric conductive filaments in a HfO 2 /TiN structure is investigated by conductive atomic force microscopy. The preforming state evidences nonhomogeneous conduction at high fields through conductive paths, which are associated with pre-existing defects and develop into conductive filaments with a forming procedure. The disruption of the same filaments is demonstrated as well, according to a bipolar operation. In addition, the conductive tip of the microscopy is exploited to perform electrical operations on single conductive spots, which evidences that neighboring conductive filaments are not electrically independent. We propose a picture that describes the evolution of the shape of the conductive filaments in the processes of their formation and disruption, which involves the development of conductive branches from a common root; this root resides in the pre-existing defects that lay at the HfO 2 /TiN interface. (paper)

An EELS sub-nanometer investigation of the dielectric gate stack for the realization of InGaAs based MOSFET devices

International Nuclear Information System (INIS)

Longo, P; Paterson, G W; Craven, A J; Holland, M C; Thayne, I G

2010-01-01

In this paper, a subnanometer investigation of the Ga 2 O 3 /GdGaO dielectric gate stack deposited onto InGaAs is presented. Results regarding the influence of the growth conditions on the interface region from a chemical and morphological point of view are presented. The chemical information reported in this paper has been obtained using electron energy loss spectroscopy (EELS) that was carried out in a scanning transmission electron microscope ((S)TEM) showing both spatial and depth resolution.

Low temperature formation of higher-k cubic phase HfO2 by atomic layer deposition on GeOx/Ge structures fabricated by in-situ thermal oxidation

International Nuclear Information System (INIS)

Zhang, R.; Huang, P.-C.; Taoka, N.; Yokoyama, M.; Takenaka, M.; Takagi, S.

2016-01-01

We have demonstrated a low temperature formation (300 °C) of higher-k HfO 2 using atomic layer deposition (ALD) on an in-situ thermal oxidation GeO x interfacial layer. It is found that the cubic phase is dominant in the HfO 2 film with an epitaxial-like growth behavior. The maximum permittivity of 42 is obtained for an ALD HfO 2 film on a 1-nm-thick GeO x form by the in-situ thermal oxidation. It is suggested from physical analyses that the crystallization of cubic phase HfO 2 can be induced by the formation of six-fold crystalline GeO x structures in the underlying GeO x interfacial layer

Comparative study on nitridation and oxidation plasma interface treatment for AlGaN/GaN MIS-HEMTs with AlN gate dielectric

Science.gov (United States)

Zhu, Jie-Jie; Ma, Xiao-Hua; Hou, Bin; Chen, Li-Xiang; Zhu, Qing; Hao, Yue

2017-02-01

This paper demonstrated the comparative study on interface engineering of AlN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) by using plasma interface pre-treatment in various ambient gases. The 15 nm AlN gate dielectric grown by plasma-enhanced atomic layer deposition significantly suppressed the gate leakage current by about two orders of magnitude and increased the peak field-effect mobility by more than 50%. NH3/N2 nitridation plasma treatment (NPT) was used to remove the 3 nm poor-quality interfacial oxide layer and N2O/N2 oxidation plasma treatment (OPT) to improve the quality of interfacial layer, both resulting in improved dielectric/barrier interface quality, positive threshold voltage (V th) shift larger than 0.9 V, and negligible dispersion. In comparison, however, NPT led to further decrease in interface charges by 3.38 × 1012 cm-2 and an extra positive V th shift of 1.3 V. Analysis with fat field-effect transistors showed that NPT resulted in better sub-threshold characteristics and transconductance linearity for MIS-HEMTs compared with OPT. The comparative study suggested that direct removing the poor interfacial oxide layer by nitridation plasma was superior to improving the quality of interfacial layer by oxidation plasma for the interface engineering of GaN-based MIS-HEMTs.

Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging?

Directory of Open Access Journals (Sweden)

Takashi Ando

2012-03-01

Full Text Available Current status and challenges of aggressive equivalent-oxide-thickness (EOT scaling of high-κ gate dielectrics via higher-κ ( > 20 materials and interfacial layer (IL scavenging techniques are reviewed. La-based higher-κ materials show aggressive EOT scaling (0.5–0.8 nm, but with effective workfunction (EWF values suitable only for n-type field-effect-transistor (FET. Further exploration for p-type FET-compatible higher-κ materials is needed. Meanwhile, IL scavenging is a promising approach to extend Hf-based high-κ dielectrics to future nodes. Remote IL scavenging techniques enable EOT scaling below 0.5 nm. Mobility-EOT trends in the literature suggest that short-channel performance improvement is attainable with aggressive EOT scaling via IL scavenging or La-silicate formation. However, extreme IL scaling (e.g., zero-IL is accompanied by loss of EWF control and with severe penalty in reliability. Therefore, highly precise IL thickness control in an ultra-thin IL regime ( < 0.5 nm will be the key technology to satisfy both performance and reliability requirements for future CMOS devices.

In situ atomic layer nitridation on the top and down regions of the amorphous and crystalline high-K gate dielectrics

Energy Technology Data Exchange (ETDEWEB)

Tsai, Meng-Chen [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China); Lee, Min-Hung [Institute of Electro-Optical Science and Technology, National Taiwan Normal University, Taipei 11677, Taiwan (China); Kuo, Chin-Lung; Lin, Hsin-Chih [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China); Chen, Miin-Jang, E-mail: mjchen@ntu.edu.tw [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China)

2016-11-30

Highlights: • The structural and electrical characteristics of the ZrO{sub 2} high-K dielectrics, treated with the in situ atomic layer doping of nitrogen into the top and down regions (top and down nitridation, TN and DN, respectively), were investigated. • The amorphous DN sample has a lower leakage current density (J{sub g}) than the amorphous TN sample, attributed to the formation of SiO{sub x}N{sub y} in the interfacial layer (IL). • The crystalline TN sample exhibited a lower CET and a similar J{sub g} as compared with the crystalline DN sample, which can be ascribed to the suppression of IL regrowth. • The crystalline ZrO{sub 2} with in situ atomic layer doping of nitrogen into the top region exhibited superior scaling limit, electrical characteristics, and reliability. - Abstract: Amorphous and crystalline ZrO{sub 2} gate dielectrics treated with in situ atomic layer nitridation on the top and down regions (top and down nitridation, abbreviated as TN and DN) were investigated. In a comparison between the as-deposited amorphous DN and TN samples, the DN sample has a lower leakage current density (J{sub g}) of ∼7 × 10{sup −4} A/cm{sup 2} with a similar capacitance equivalent thickness (CET) of ∼1.53 nm, attributed to the formation of SiO{sub x}N{sub y} in the interfacial layer (IL). The post-metallization annealing (PMA) leads to the transformation of ZrO{sub 2} from the amorphous to the crystalline tetragonal/cubic phase, resulting in an increment of the dielectric constant. The PMA-treated TN sample exhibits a lower CET of 1.22 nm along with a similar J{sub g} of ∼1.4 × 10{sup −5} A/cm{sup 2} as compared with the PMA-treated DN sample, which can be ascribed to the suppression of IL regrowth. The result reveals that the nitrogen engineering in the top and down regions has a significant impact on the electrical characteristics of amorphous and crystalline ZrO{sub 2} gate dielectrics, and the nitrogen incorporation at the top of crystalline

Threshold-Voltage Shifts in Organic Transistors Due to Self-Assembled Monolayers at the Dielectric: Evidence for Electronic Coupling and Dipolar Effects.

Science.gov (United States)

Aghamohammadi, Mahdieh; Rödel, Reinhold; Zschieschang, Ute; Ocal, Carmen; Boschker, Hans; Weitz, R Thomas; Barrena, Esther; Klauk, Hagen

2015-10-21

The mechanisms behind the threshold-voltage shift in organic transistors due to functionalizing of the gate dielectric with self-assembled monolayers (SAMs) are still under debate. We address the mechanisms by which SAMs determine the threshold voltage, by analyzing whether the threshold voltage depends on the gate-dielectric capacitance. We have investigated transistors based on five oxide thicknesses and two SAMs with rather diverse chemical properties, using the benchmark organic semiconductor dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene. Unlike several previous studies, we have found that the dependence of the threshold voltage on the gate-dielectric capacitance is completely different for the two SAMs. In transistors with an alkyl SAM, the threshold voltage does not depend on the gate-dielectric capacitance and is determined mainly by the dipolar character of the SAM, whereas in transistors with a fluoroalkyl SAM the threshold voltages exhibit a linear dependence on the inverse of the gate-dielectric capacitance. Kelvin probe force microscopy measurements indicate this behavior is attributed to an electronic coupling between the fluoroalkyl SAM and the organic semiconductor.

Optical properties of the Al2O3/SiO2 and Al2O3/HfO2/SiO2 antireflective coatings

Science.gov (United States)

Marszałek, Konstanty; Winkowski, Paweł; Jaglarz, Janusz

2014-01-01

Investigations of bilayer and trilayer Al2O3/SiO2 and Al2O3/HfO2/SiO2 antireflective coatings are presented in this paper. The oxide films were deposited on a heated quartz glass by e-gun evaporation in a vacuum of 5 × 10-3 [Pa] in the presence of oxygen. Depositions were performed at three different temperatures of the substrates: 100 °C, 200 °C and 300 °C. The coatings were deposited onto optical quartz glass (Corning HPFS). The thickness and deposition rate were controlled with Inficon XTC/2 thickness measuring system. Deposition rate was equal to 0.6 nm/s for Al2O3, 0.6 nm - 0.8 nm/s for HfO2 and 0.6 nm/s for SiO2. Simulations leading to optimization of the thin film thickness and the experimental results of optical measurements, which were carried out during and after the deposition process, have been presented. The optical thickness values, obtained from the measurements performed during the deposition process were as follows: 78 nm/78 nm for Al2O3/SiO2 and 78 nm/156 nm/78 nm for Al2O3/HfO2/SiO2. The results were then checked by ellipsometric technique. Reflectance of the films depended on the substrate temperature during the deposition process. Starting from 240 nm to the beginning of visible region, the average reflectance of the trilayer system was below 1 % and for the bilayer, minima of the reflectance were equal to 1.6 %, 1.15 % and 0.8 % for deposition temperatures of 100 °C, 200 °C and 300 °C, respectively.

Versatile sputtering technology for Al2O3 gate insulators on graphene

Directory of Open Access Journals (Sweden)

Miriam Friedemann, Mirosław Woszczyna, André Müller, Stefan Wundrack, Thorsten Dziomba, Thomas Weimann and Franz J Ahlers

2012-01-01

Full Text Available We report a novel, sputtering-based fabrication method of Al2O3 gate insulators on graphene. Electrical performance of dual-gated mono- and bilayer exfoliated graphene devices is presented. Sputtered Al2O3 layers possess comparable quality to oxides obtained by atomic layer deposition with respect to a high relative dielectric constant of about 8, as well as low-hysteresis performance and high breakdown voltage. We observe a moderate carrier mobility of about 1000 cm2 V− 1 s−1 in monolayer graphene and 350 cm2 V− 1 s−1 in bilayer graphene, respectively. The mobility decrease can be attributed to the resonant scattering on atomic-scale defects, likely originating from the Al precursor layer evaporated prior to sputtering.

Design and Fabrication of Interdigital Nanocapacitors Coated with HfO2

Directory of Open Access Journals (Sweden)

Gabriel González

2015-01-01

Full Text Available In this article nickel interdigital capacitors were fabricated on top of silicon substrates. The capacitance of the interdigital capacitor was optimized by coating the electrodes with a 60 nm layer of HfO2. An analytical solution of the capacitance was compared to electromagnetic simulations using COMSOL and with experimental measurements. Results show that modeling interdigital capacitors using Finite Element Method software such as COMSOL is effective in the design and electrical characterization of these transducers.

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene-graphene composite layers for flexible thin film transistors with a polymer gate dielectric.

Science.gov (United States)

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-02-28

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene-graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene-graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm(2) V(-1) s(-1) and a threshold voltage of -0.7 V at V(gs) = -40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm(2) V(-1) s(-1) and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies.

Cleaning Challenges of High-κ/Metal Gate Structures

KAUST Repository

Hussain, Muhammad Mustafa; Shamiryan, Denis G.; Paraschiv, Vasile; Sano, Kenichi; Reinhardt, Karen A.

2010-01-01

High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.

Cleaning Challenges of High-κ/Metal Gate Structures

KAUST Repository

Hussain, Muhammad Mustafa

2010-12-20

High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.

Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

KAUST Repository

Ghoneim, Mohamed T.

2015-06-01

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard bulk mono-crystalline silicon substrate. A lifetime projection is extracted using statistical analysis of the ramping voltage (Vramp) breakdown and time dependent dielectric breakdown data. The obtained flexible MOSCAPs operational voltages satisfying the 10 years lifetime benchmark are compared to those of the control MOSCAPs, which are not peeled off from the silicon wafer. © 2014 IEEE.

SEMICONDUCTOR TECHNOLOGY: TaN wet etch for application in dual-metal-gate integration technology

Science.gov (United States)

Yongliang, Li; Qiuxia, Xu

2009-12-01

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and Jg-Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.

Interface trapping in (2 ¯ 01 ) β-Ga2O3 MOS capacitors with deposited dielectrics

Science.gov (United States)

Jayawardena, Asanka; Ramamurthy, Rahul P.; Ahyi, Ayayi C.; Morisette, Dallas; Dhar, Sarit

2018-05-01

The electrical properties of interfaces and the impact of post-deposition annealing have been investigated in gate oxides formed by low pressure chemical vapor deposition (LPCVD SiO2) and atomic layer deposition (Al2O3) on ( 2 ¯ 01 ) oriented n-type β-Ga2O3 single crystals. Capacitance-voltage based methods have been used to extract the interface state densities, including densities of slow `border' traps at the dielectric-Ga2O3 interfaces. It was observed that SiO2-β-Ga2O3 has a higher interface and border trap density than the Al2O3-β-Ga2O3. An increase in shallow interface states was also observed at the Al2O3-β-Ga2O3 interface after post-deposition annealing at higher temperature suggesting the high temperature annealing to be detrimental for Al2O3-Ga2O3 interfaces. Among the different dielectrics studied, LPCVD SiO2 was found to have the lowest dielectric leakage and the highest breakdown field, consistent with a higher conduction band-offset. These results are important for the processing of high performance β-Ga2O3 MOS devices as these factors will critically impact channel transport, threshold voltage stability, and device reliability.

Internal filament modulation in low-dielectric gap design for built-in selector-less resistive switching memory application

Science.gov (United States)

Chen, Ying-Chen; Lin, Chih-Yang; Huang, Hui-Chun; Kim, Sungjun; Fowler, Burt; Chang, Yao-Feng; Wu, Xiaohan; Xu, Gaobo; Chang, Ting-Chang; Lee, Jack C.