Grade Level and Gender Differences in a School-Based Reading Tutoring Program

Science.gov (United States)

Chang, Sau Hou

2011-01-01

The purpose of the present study is to investigate the grade level and gender differences in a school-based reading tutoring program. The treatment group included 10 first-grade and 12 second-grade struggling readers, and the control group included 41 first-grade and 63 second-grade nonstruggling readers. The tutors were teacher candidates in an…

Grade Level Differences in Factors of Self-Esteem

Science.gov (United States)

Kokenes, Barbara

1974-01-01

Investigated the construct validity of the Coopersmith Self Esteem Inventory, using approximately 1500 elementary school students. Also investigated grade level differences in preadolescent and adolescent children. (Author/ED)

Targeting multiple heterogeneous hardware platforms with OpenCL

Science.gov (United States)

Fox, Paul A.; Kozacik, Stephen T.; Humphrey, John R.; Paolini, Aaron; Kuller, Aryeh; Kelmelis, Eric J.

2014-06-01

The OpenCL API allows for the abstract expression of parallel, heterogeneous computing, but hardware implementations have substantial implementation differences. The abstractions provided by the OpenCL API are often insufficiently high-level to conceal differences in hardware architecture. Additionally, implementations often do not take advantage of potential performance gains from certain features due to hardware limitations and other factors. These factors make it challenging to produce code that is portable in practice, resulting in much OpenCL code being duplicated for each hardware platform being targeted. This duplication of effort offsets the principal advantage of OpenCL: portability. The use of certain coding practices can mitigate this problem, allowing a common code base to be adapted to perform well across a wide range of hardware platforms. To this end, we explore some general practices for producing performant code that are effective across platforms. Additionally, we explore some ways of modularizing code to enable optional optimizations that take advantage of hardware-specific characteristics. The minimum requirement for portability implies avoiding the use of OpenCL features that are optional, not widely implemented, poorly implemented, or missing in major implementations. Exposing multiple levels of parallelism allows hardware to take advantage of the types of parallelism it supports, from the task level down to explicit vector operations. Static optimizations and branch elimination in device code help the platform compiler to effectively optimize programs. Modularization of some code is important to allow operations to be chosen for performance on target hardware. Optional subroutines exploiting explicit memory locality allow for different memory hierarchies to be exploited for maximum performance. The C preprocessor and JIT compilation using the OpenCL runtime can be used to enable some of these techniques, as well as to factor in hardware

ATLAS level-1 calorimeter trigger hardware: initial timing and energy calibration

CERN Document Server

Childers, JT; The ATLAS collaboration

2010-01-01

The ATLAS Level-1 Calorimeter Trigger identifies high-pT objects in the Liquid Argon and Tile Calorimeters with a fixed latency of up to 2.4 microseconds using a hardware-based, pipelined system built with custom electronics. The Preprocessor Module conditions and digitizes about 7200 pre-summed analogue signals from the calorimeters at the LHC bunch-crossing frequency of 40 MHz, and performs bunch-crossing identification (BCID) and deposited energy measurement for each input signal. This information is passed to further processors for object classification and total energy calculation, and the results are used to make the Level-1 trigger decision for the ATLAS detector. The BCID and energy measurement in the trigger depend on precise timing adjustments to achieve correct sampling of the input signal peak. Test pulses from the calorimeters were analysed to derive the initial timing and energy calibration, and first data from the LHC restart in autumn 2009 and early 2010 were used for validation and further op...

Learning Machines Implemented on Non-Deterministic Hardware

OpenAIRE

Gupta, Suyog; Sindhwani, Vikas; Gopalakrishnan, Kailash

2014-01-01

This paper highlights new opportunities for designing large-scale machine learning systems as a consequence of blurring traditional boundaries that have allowed algorithm designers and application-level practitioners to stay -- for the most part -- oblivious to the details of the underlying hardware-level implementations. The hardware/software co-design methodology advocated here hinges on the deployment of compute-intensive machine learning kernels onto compute platforms that trade-off deter...

(Biased) Grading of Students’ Performance: Students’ Names, Performance Level, and Implicit Attitudes

Science.gov (United States)

Bonefeld, Meike; Dickhäuser, Oliver

2018-01-01

Biases in pre-service teachers’ evaluations of students’ performance may arise due to stereotypes (e.g., the assumption that students with a migrant background have lower potential). This study examines the effects of a migrant background, performance level, and implicit attitudes toward individuals with a migrant background on performance assessment (assigned grades and number of errors counted in a dictation). Pre-service teachers (N = 203) graded the performance of a student who appeared to have a migrant background statistically significantly worse than that of a student without a migrant background. The differences were more pronounced when the performance level was low and when the pre-service teachers held relatively positive implicit attitudes toward individuals with a migrant background. Interestingly, only performance level had an effect on the number of counted errors. Our results support the assumption that pre-service teachers exhibit bias when grading students with a migrant background in a third-grade level dictation assignment. PMID:29867618

(Biased Grading of Students’ Performance: Students’ Names, Performance Level, and Implicit Attitudes

Directory of Open Access Journals (Sweden)

Meike Bonefeld

2018-05-01

Full Text Available Biases in pre-service teachers’ evaluations of students’ performance may arise due to stereotypes (e.g., the assumption that students with a migrant background have lower potential. This study examines the effects of a migrant background, performance level, and implicit attitudes toward individuals with a migrant background on performance assessment (assigned grades and number of errors counted in a dictation. Pre-service teachers (N = 203 graded the performance of a student who appeared to have a migrant background statistically significantly worse than that of a student without a migrant background. The differences were more pronounced when the performance level was low and when the pre-service teachers held relatively positive implicit attitudes toward individuals with a migrant background. Interestingly, only performance level had an effect on the number of counted errors. Our results support the assumption that pre-service teachers exhibit bias when grading students with a migrant background in a third-grade level dictation assignment.

Expert System analysis of non-fuel assembly hardware and spent fuel disassembly hardware: Its generation and recommended disposal

International Nuclear Information System (INIS)

Williamson, D.A.

1991-01-01

Almost all of the effort being expended on radioactive waste disposal in the United States is being focused on the disposal of spent Nuclear Fuel, with little consideration for other areas that will have to be disposed of in the same facilities. one area of radioactive waste that has not been addressed adequately because it is considered a secondary part of the waste issue is the disposal of the various Non-Fuel Bearing Components of the reactor core. These hardware components fall somewhat arbitrarily into two categories: Non-Fuel Assembly (NFA) hardware and Spent Fuel Disassembly (SFD) hardware. This work provides a detailed examination of the generation and disposal of NFA hardware and SFD hardware by the nuclear utilities of the United States as it relates to the Civilian Radioactive Waste Management Program. All available sources of data on NFA and SFD hardware are analyzed with particular emphasis given to the Characteristics Data Base developed by Oak Ridge National Laboratory and the characterization work performed by Pacific Northwest Laboratories and Rochester Gas ampersand Electric. An Expert System developed as a portion of this work is used to assist in the prediction of quantities of NFA hardware and SFD hardware that will be generated by the United States' utilities. Finally, the hardware waste management practices of the United Kingdom, France, Germany, Sweden, and Japan are studied for possible application to the disposal of domestic hardware wastes. As a result of this work, a general classification scheme for NFA and SFD hardware was developed. Only NFA and SFD hardware constructed of zircaloy and experiencing a burnup of less than 70,000 MWD/MTIHM and PWR control rods constructed of stainless steel are considered Low-Level Waste. All other hardware is classified as Greater-ThanClass-C waste

Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System

DEFF Research Database (Denmark)

Grode, Jesper Nicolai Riis; Knudsen, Peter Voigt; Madsen, Jan

1998-01-01

as a designer's/design tool's aid to generate good hardware allocations for use in hardware/software partitioning. The algorithm has been implemented in a tool under the LYCOS system. The results show that the allocations produced by the algorithm come close to the best allocations obtained by exhaustive search.......This paper presents a novel hardware resource allocation technique for hardware/software partitioning. It allocates hardware resources to the hardware data-path using information such as data-dependencies between operations in the application, and profiling information. The algorithm is useful...

A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation

OpenAIRE

Lee , Jae-Gon; Chung , Moo-Kyoung; Ahn , Ki-Yong; Lee , Sang-Heon; Kyung , Chong-Min

2005-01-01

Submitted on behalf of EDAA (http://www.edaa.com/); International audience; This paper presents a scheme for efficient channel usage between simulator and accelerator where the accelerator models some RTL sub-blocks in the accelerator-based hardware/software co-simulation while the simulator runs transaction-level model of the remaining part of the whole chip being verified. With conventional simulation accelerator, evaluations of simulator and accelerator alternate at every valid simulation ...

ATLAS level-1 calorimeter trigger hardware: initial timing and energy calibration

International Nuclear Information System (INIS)

Childers, J T

2011-01-01

The ATLAS Level-1 Calorimeter Trigger identifies high-pT objects in the Liquid Argon and Tile Calorimeters with a fixed latency of up to 2.5μs using a hardware-based, pipelined system built with custom electronics. The Preprocessor Module conditions and digitizes about 7200 pre-summed analogue signals from the calorimeters at the LHC bunch-crossing frequency of 40 MHz, and performs bunch-crossing identification (BCID) and deposited energy measurement for each input signal. This information is passed to further processors for object classification and total energy calculation, and the results are used to make the Level-1 trigger decision for the ATLAS detector. The BCID and energy measurement in the trigger depend on precise timing adjustments to achieve correct sampling of the input signal peak. Test pulses from the calorimeters were analysed to derive the initial timing and energy calibration, and first data from the LHC restart in autumn 2009 and early 2010 were used for validation and further optimization. The results from these calibration measurements are presented.

Ortographic difficulties in writing at a basic grade level

Directory of Open Access Journals (Sweden)

Maria Cristina Rodrigues Azevedo Joly

2009-12-01

Full Text Available This study aimed to identify the performance in children’s writing at a basic grade level. A written test was applied to 546 grade 2 or 3 boys and girls (aged 7 to 13 in public and private schools from the State of São Paulo. The results showed that the grade 3 participants presented a better performance than the grade 2 participants even though both groups have achieved the same maximum and minimum scores. It was confirmed that participants had more difficulty with words containing compound syllables, while words with aggregated consonants and digraphs were associated with the highest rate of correct answers. Furthermore, students from private school revealed more competence in orthographic writing than those coming from public schools. As to gender differences, there were no significant differences in performance for compound and complex syllables items though for other words, girls had better scores.   Keywords: writing; academic achievement; evaluation.

Hardware for soft computing and soft computing for hardware

CERN Document Server

Nedjah, Nadia

2014-01-01

Single and Multi-Objective Evolutionary Computation (MOEA),  Genetic Algorithms (GAs), Artificial Neural Networks (ANNs), Fuzzy Controllers (FCs), Particle Swarm Optimization (PSO) and Ant colony Optimization (ACO) are becoming omnipresent in almost every intelligent system design. Unfortunately, the application of the majority of these techniques is complex and so requires a huge computational effort to yield useful and practical results. Therefore, dedicated hardware for evolutionary, neural and fuzzy computation is a key issue for designers. With the spread of reconfigurable hardware such as FPGAs, digital as well as analog hardware implementations of such computation become cost-effective. The idea behind this book is to offer a variety of hardware designs for soft computing techniques that can be embedded in any final product. Also, to introduce the successful application of soft computing technique to solve many hard problem encountered during the design of embedded hardware designs. Reconfigurable em...

Designing Secure Systems on Reconfigurable Hardware

OpenAIRE

Huffmire, Ted; Brotherton, Brett; Callegari, Nick; Valamehr, Jonathan; White, Jeff; Kastner, Ryan; Sherwood, Ted

2008-01-01

The extremely high cost of custom ASIC fabrication makes FPGAs an attractive alternative for deployment of custom hardware. Embedded systems based on reconfigurable hardware integrate many functions onto a single device. Since embedded designers often have no choice but to use soft IP cores obtained from third parties, the cores operate at different trust levels, resulting in mixed trust designs. The goal of this project is to evaluate recently proposed security primitives for reconfigurab...

Effects of multisensory resources on the achievement and science attitudes of seventh-grade suburban students taught science concepts on and above grade level

Science.gov (United States)

Roberts, Patrice Helen

This research was designed to determine the relationships among students' achievement scores on grade-level science content, on science content that was three years above-grade level, on attitudes toward instructional approaches, and learning-styles perceptual preferences when instructional approaches were multisensory versus traditional. The dependent variables for this investigation were scores on achievement posttests and scores on the attitude survey. The independent variables were the instructional strategy and students' perceptual preferences. The sample consisted of 74 educationally oriented seventh-grade students. The Learning Styles Inventory (LSI) (Dunn, Dunn, & Price, 1990) was administered to determine perceptual preferences. The control group was taught seventh-grade and tenth-grade science units using a traditional approach and the experimental group was instructed on the same units using multisensory instructional resources. The Semantic Differential Scale (SDS) (Pizzo, 1981) was administered to reveal attitudinal differences. The traditional unit included oral reading from the textbook, completing outlines, labeling diagrams, and correcting the outlines and diagrams as a class. The multisensory unit included five instructional stations established in different sections of the classroom to allow students to learn by: (a) manipulating Flip Chutes, (b) using Electroboards, (c) assembling Task Cards, (d) playing a kinesthetic Floor Game, and (e) reading an individual Programmed Learning Sequence. Audio tapes and scripts were provided at each location. Students circulated in groups of four from station to station. The data subjected to statistical analyses supported the use of a multisensory, rather than a traditional approach, for teaching science content that is above-grade level. T-tests revealed a positive and significant impact on achievement scores (p < 0.0007). No significance was detected on grade-level achievement nor on the perceptual

Reliable software for unreliable hardware a cross layer perspective

CERN Document Server

Rehman, Semeen; Henkel, Jörg

2016-01-01

This book describes novel software concepts to increase reliability under user-defined constraints. The authors’ approach bridges, for the first time, the reliability gap between hardware and software. Readers will learn how to achieve increased soft error resilience on unreliable hardware, while exploiting the inherent error masking characteristics and error (stemming from soft errors, aging, and process variations) mitigations potential at different software layers. · Provides a comprehensive overview of reliability modeling and optimization techniques at different hardware and software levels; · Describes novel optimization techniques for software cross-layer reliability, targeting unreliable hardware.

The Purdue Elementary Problem-Solving Inventory (PEPSI), Grade Level, and Socioeconomic Status: A Preliminary Study.

Science.gov (United States)

Cox, David W.

1985-01-01

The effects of grade level and socioeconomic status upon Purdue Elementary Problem-Solving Inventory (PEPSI) scores were investigated with 123 elementary students. It was concluded that the PEPSI is usable with most grade two through grade six pupils at both lower and middle socioeconomic levels, and has potential utility in teaching…

A leading-edge hardware family for diagnostics applications and low-level RF in CERN's ELENA ring

CERN Document Server

Angoletta, M E; Jaussi, M; Leiononen, P; Levens, T E; Molendijk, J C; Sanchez-Quesada, J; Simonin, J

2013-01-01

The CERN Extra Low ENergy Antiproton (ELENA) Ring is a new synchrotron that will be commissioned in 2016 to further decelerate the antiprotons transferred from the CERN’s Antiproton Decelerator (AD). The requirements for the acquisition and treatment of signals for longitudinal diagnostics are very demanding, owing to the revolution frequency swing as well as to the digital signal processing required. The requirements for the Low-Level Radio-Frequency (LLRF) system are very demanding as well, especially in terms of revolution frequency swing, dynamic range and low noise required by the cavity voltage control and digital signal processing to be performed. Both sets of requirements will be satisfied by using a leading-edge hardware family, developed to cover the LLRF needs of all synchrotrons in the Meyrin site; it will be first deployed in 2014 in the CERN’s PSB and in the medical machine MedAustron. This paper gives an overview of the main building blocks of the hardware family and of th...

Introduction to Hardware Security

Directory of Open Access Journals (Sweden)

Yier Jin

2015-10-01

Full Text Available Hardware security has become a hot topic recently with more and more researchers from related research domains joining this area. However, the understanding of hardware security is often mixed with cybersecurity and cryptography, especially cryptographic hardware. For the same reason, the research scope of hardware security has never been clearly defined. To help researchers who have recently joined in this area better understand the challenges and tasks within the hardware security domain and to help both academia and industry investigate countermeasures and solutions to solve hardware security problems, we will introduce the key concepts of hardware security as well as its relations to related research topics in this survey paper. Emerging hardware security topics will also be clearly depicted through which the future trend will be elaborated, making this survey paper a good reference for the continuing research efforts in this area.

Relationship of the Van Herick Grading System with Peripheral Iris Configuration and Level of Iris Insertion.

Science.gov (United States)

Khan, Faisal Aziz; Niazi, Shafaq Pervez Khan; Khan, Assad Zaman

2017-09-01

To determine the relationship of the van Herick angle grading system with the level of iris insertion and peripheral iris configuration. Observational study. Eye department, Combined Military Hospital, Malir Cantt., Karachi, from May to October 2015. Sixty-five eyes of 65 patients were recruited. Anterior chamber depth at the temporal limbus was measured as a fraction of corneal section thickness using van Herick technique and graded on the standard 4-point scale of the van Herick grading system. Gonioscopy of the temporal quadrant was performed with a Posner 4 mirror goniolens and both the true level of iris insertion and peripheral iris configuration were recorded on a 4-point scale so as to equate with the van Herick 4-point grading system. Spearman's rho test was applied to determine the relationship of the van Herick grading system with level of iris root insertion and peripheral iris configuration. Amoderate positive correlation between van Herick grade and peripheral iris configuration was found which was statistically significant (rs=0.42, p < 0.001). Astatistically significant and moderate positive correlation was also detected between van Herick grade and the level of iris insertion (rs=0.45, p < 0.001). The van Herick grade has a moderately positive relationship with the peripheral iris configuration and true level of iris insertion.

A hardware acceleration based on high-level synthesis approach for glucose-insulin analysis

Science.gov (United States)

Daud, Nur Atikah Mohd; Mahmud, Farhanahani; Jabbar, Muhamad Hairol

2017-01-01

In this paper, the research is focusing on Type 1 Diabetes Mellitus (T1DM). Since this disease requires a full attention on the blood glucose concentration with the help of insulin injection, it is important to have a tool that able to predict that level when consume a certain amount of carbohydrate during meal time. Therefore, to make it realizable, a Hovorka model which is aiming towards T1DM is chosen in this research. A high-level language is chosen that is C++ to construct the mathematical model of the Hovorka model. Later, this constructed code is converted into intellectual property (IP) which is also known as a hardware accelerator by using of high-level synthesis (HLS) approach which able to improve in terms of design and performance for glucose-insulin analysis tool later as will be explained further in this paper. This is the first step in this research before implementing the design into system-on-chip (SoC) to achieve a high-performance system for the glucose-insulin analysis tool.

Hardware-based tracking at trigger level for ATLAS: The Fast Tracker (FTK) Project

CERN Document Server

Gramling, Johanna; The ATLAS collaboration

2015-01-01

Physics collisions at 13 TeV are expected at the LHC with an average of 40-50 proton-proton collisions per bunch crossing. Tracking at trigger level is an essential tool to control the rate in high-pileup conditions while maintaining a good efficiency for relevant physics processes. The Fast TracKer (FTK) is an integral part of the trigger upgrade for the ATLAS detector. For every event passing the Level 1 trigger (at a maximum rate of 100 kHz) the FTK receives data from the 80 million channels of the silicon detectors, providing tracking information to the High Level Trigger in order to ensure a selection robust against pile-up. The FTK performs a hardware-based track reconstruction, using associative memory (AM) that is based on the use of a custom chip, designed to perform pattern matching at very high speed. It finds track candidates at low resolution (roads) that seed a full-resolution track fitting done by FPGAs. Narrow roads permit a fast track fitting but need many patterns stored in the AM to ensure ...

Student selection: are the school-leaving A-level grades in biology and chemistry important?

Science.gov (United States)

Green, A; Peters, T J; Webster, D J

1993-01-01

This study determined the relationships of grades in A-level biology and chemistry with examination success or failure during the medical course. By inspection of medical student records, A-level grades at entry to medical school and examination performance were obtained for 128 (91%) of the students who sat their final MBBCh examination at the University of Wales College of Medicine in June 1988. The majority, 92 (72%), completed their medical school careers with no professional examination failures; 15 failed examinations just in the period up to 2nd MB; 11 failed examinations in the clinical period only and 10 failed examinations in both periods. Whereas grade achieved in A-level chemistry was not associated with undergraduate examination performance, students with a grade A or B in A-level biology were less likely to have problems than the others (21% compared with 47%; the difference of 26% has a 95% confidence interval of 7% to 44%). Specifically, there appears to be a strong relationship between a low grade in biology and difficulties in the preclinical examinations. Moreover, for those who have difficulties at this stage, this association continues later in the course.

Remote hardware-reconfigurable robotic camera

Science.gov (United States)

Arias-Estrada, Miguel; Torres-Huitzil, Cesar; Maya-Rueda, Selene E.

2001-10-01

In this work, a camera with integrated image processing capabilities is discussed. The camera is based on an imager coupled to an FPGA device (Field Programmable Gate Array) which contains an architecture for real-time computer vision low-level processing. The architecture can be reprogrammed remotely for application specific purposes. The system is intended for rapid modification and adaptation for inspection and recognition applications, with the flexibility of hardware and software reprogrammability. FPGA reconfiguration allows the same ease of upgrade in hardware as a software upgrade process. The camera is composed of a digital imager coupled to an FPGA device, two memory banks, and a microcontroller. The microcontroller is used for communication tasks and FPGA programming. The system implements a software architecture to handle multiple FPGA architectures in the device, and the possibility to download a software/hardware object from the host computer into its internal context memory. System advantages are: small size, low power consumption, and a library of hardware/software functionalities that can be exchanged during run time. The system has been validated with an edge detection and a motion processing architecture, which will be presented in the paper. Applications targeted are in robotics, mobile robotics, and vision based quality control.

System-Level Testing of the Advanced Stirling Radioisotope Generator Engineering Hardware

Science.gov (United States)

Chan, Jack; Wiser, Jack; Brown, Greg; Florin, Dominic; Oriti, Salvatore M.

2014-01-01

To support future NASA deep space missions, a radioisotope power system utilizing Stirling power conversion technology was under development. This development effort was performed under the joint sponsorship of the Department of Energy and NASA, until its termination at the end of 2013 due to budget constraints. The higher conversion efficiency of the Stirling cycle compared with that of the Radioisotope Thermoelectric Generators (RTGs) used in previous missions (Viking, Pioneer, Voyager, Galileo, Ulysses, Cassini, Pluto New Horizons and Mars Science Laboratory) offers the advantage of a four-fold reduction in Pu-238 fuel, thereby extending its limited domestic supply. As part of closeout activities, system-level testing of flight-like Advanced Stirling Convertors (ASCs) with a flight-like ASC Controller Unit (ACU) was performed in February 2014. This hardware is the most representative of the flight design tested to date. The test fully demonstrates the following ACU and system functionality: system startup; ASC control and operation at nominal and worst-case operating conditions; power rectification; DC output power management throughout nominal and out-of-range host voltage levels; ACU fault management, and system command / telemetry via MIL-STD 1553 bus. This testing shows the viability of such a system for future deep space missions and bolsters confidence in the maturity of the flight design.

VEG-01: Veggie Hardware Verification Testing

Science.gov (United States)

Massa, Gioia; Newsham, Gary; Hummerick, Mary; Morrow, Robert; Wheeler, Raymond

2013-01-01

The Veggie plant/vegetable production system is scheduled to fly on ISS at the end of2013. Since much of the technology associated with Veggie has not been previously tested in microgravity, a hardware validation flight was initiated. This test will allow data to be collected about Veggie hardware functionality on ISS, allow crew interactions to be vetted for future improvements, validate the ability of the hardware to grow and sustain plants, and collect data that will be helpful to future Veggie investigators as they develop their payloads. Additionally, food safety data on the lettuce plants grown will be collected to help support the development of a pathway for the crew to safely consume produce grown on orbit. Significant background research has been performed on the Veggie plant growth system, with early tests focusing on the development of the rooting pillow concept, and the selection of fertilizer, rooting medium and plant species. More recent testing has been conducted to integrate the pillow concept into the Veggie hardware and to ensure that adequate water is provided throughout the growth cycle. Seed sanitation protocols have been established for flight, and hardware sanitation between experiments has been studied. Methods for shipping and storage of rooting pillows and the development of crew procedures and crew training videos for plant activities on-orbit have been established. Science verification testing was conducted and lettuce plants were successfully grown in prototype Veggie hardware, microbial samples were taken, plant were harvested, frozen, stored and later analyzed for microbial growth, nutrients, and A TP levels. An additional verification test, prior to the final payload verification testing, is desired to demonstrate similar growth in the flight hardware and also to test a second set of pillows containing zinnia seeds. Issues with root mat water supply are being resolved, with final testing and flight scheduled for later in 2013.

The Impact of School Environment and Grade Level on Student Delinquency: A Multilevel Modeling Approach

Science.gov (United States)

Lo, Celia C.; Kim, Young S.; Allen, Thomas M.; Allen, Andrea N.; Minugh, P. Allison; Lomuto, Nicoletta

2011-01-01

Effects on delinquency made by grade level, school type (based on grade levels accommodated), and prosocial school climate were assessed, controlling for individual-level risk and protective factors. Data were obtained from the Substance Abuse Services Division of Alabama's state mental health agency and analyzed via hierarchical linear modeling,…

Performance of Layers Fed Graded Levels of Blood –Rumen ...

African Journals Online (AJOL)

240 laying hens were fed graded levels of Blood-Rumen content mixture (BRCM) for a period of eight weeks. The study was designed to determine the level of BRCM that layers can tolerate in their diet. Feed intake by birds fed the control and 4% BRCM diets were comparable, but significantly higher (P<0.05) than those ...

Open Source Hardware for DIY Environmental Sensing

Science.gov (United States)

Aufdenkampe, A. K.; Hicks, S. D.; Damiano, S. G.; Montgomery, D. S.

2014-12-01

The Arduino open source electronics platform has been very popular within the DIY (Do It Yourself) community for several years, and it is now providing environmental science researchers with an inexpensive alternative to commercial data logging and transmission hardware. Here we present the designs for our latest series of custom Arduino-based dataloggers, which include wireless communication options like self-meshing radio networks and cellular phone modules. The main Arduino board uses a custom interface board to connect to various research-grade sensors to take readings of turbidity, dissolved oxygen, water depth and conductivity, soil moisture, solar radiation, and other parameters. Sensors with SDI-12 communications can be directly interfaced to the logger using our open Arduino-SDI-12 software library (https://github.com/StroudCenter/Arduino-SDI-12). Different deployment options are shown, like rugged enclosures to house the loggers and rigs for mounting the sensors in both fresh water and marine environments. After the data has been collected and transmitted by the logger, the data is received by a mySQL-PHP stack running on a web server that can be accessed from anywhere in the world. Once there, the data can be visualized on web pages or served though REST requests and Water One Flow (WOF) services. Since one of the main benefits of using open source hardware is the easy collaboration between users, we are introducing a new web platform for discussion and sharing of ideas and plans for hardware and software designs used with DIY environmental sensors and data loggers.

The importance of O – level grades in medical school admission: the ...

African Journals Online (AJOL)

grades in Physics, Chemistry, Biology and Mathematics. In the latter group, the JAMB scores and O' level grades were given equal weighting (50% of mark ... were given a written interview test and an oral interview. At the end of the exercise, 40 candidates were admitted. Eventually, 31 of this group and four out of the five ...

The CMS Trigger Supervisor: Control and Hardware Monitoring System of the CMS Level-1 Trigger at CERN

CERN Document Server

Ildefons Magrans de Abril

2008-01-01

The experiments CMS (Compact Muon Solenoid) and ATLAS (A Toroidal LHC ApparatuS) at the LargeHadron Collider (LHC) are the greatest exponents of the rising complexity in High Energy Physics (HEP) datahandling instrumentation. Tens of millions of readout channels, tens of thousands of hardware boards and thesame order of connections are figures of merit. However, the hardware volume is not the only complexitydimension, the unprecedented large number of research institutes and scientists that form the internationalcollaborations, and the long design, development, commissioning and operational phases are additional factorsthat must be taken into account.The Level-1 (L1) trigger decision loop is an excellent example of these difficulties. This system is based on apipelined logic destined to analyze without deadtime the data from each LHC bunch crossing occurring every25_ns, using special coarsely segmented trigger data from the detectors. The L1 trigger is responsible forreducing the rate of accepted crossings to...

Performance of growing Yankasa rams Fed graded levels of ...

African Journals Online (AJOL)

A feeding trial which lasted eight (8) weeks was carried out to determine the intake and nutrient digestibility by growing Yankasa rams fed graded levels of Tamarindus indica leaves. Twelve Yankasa rams with average liveweight of 17.40kg were randomly allocated to three treatments of four replicates in a Randomized ...

Hardware description languages

Science.gov (United States)

Tucker, Jerry H.

1994-01-01

Hardware description languages are special purpose programming languages. They are primarily used to specify the behavior of digital systems and are rapidly replacing traditional digital system design techniques. This is because they allow the designer to concentrate on how the system should operate rather than on implementation details. Hardware description languages allow a digital system to be described with a wide range of abstraction, and they support top down design techniques. A key feature of any hardware description language environment is its ability to simulate the modeled system. The two most important hardware description languages are Verilog and VHDL. Verilog has been the dominant language for the design of application specific integrated circuits (ASIC's). However, VHDL is rapidly gaining in popularity.

Memory Based Machine Intelligence Techniques in VLSI hardware

OpenAIRE

James, Alex Pappachen

2012-01-01

We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

Hardware-based Tracking at Trigger Level for ATLAS: The Fast TracKer (FTK) Project

CERN Document Server

Gramling, Johanna; The ATLAS collaboration

2015-01-01

Physics collisions at 13 TeV are expected at the LHC with an average of 40-50 proton-proton collisions per bunch crossing. Tracking at trigger level is an essential tool to control the rate in high-pileup conditions while maintaining a good efficiency for relevant physics processes. The Fast TracKer (FTK) is an integral part of the trigger upgrade for the ATLAS detector. For every event passing the Level 1 trigger (at a maximum rate of 100 kHz) the FTK receives data from the 80 million channels of the silicon detectors, providing tracking information to the High Level Trigger in order to ensure a selection robust against pile-up. The FTK performs a hardware- based track reconstruction, using associative memory (AM) that is based on the use of a custom chip, designed to perform pattern matching at very high speed. It finds track candidates at low resolution (roads) that seed a full-resolution track fitting done by FPGAs. Narrow roads permit a fast track fitting but need many patterns stored in the AM to ensure...

Hardware-based Tracking at Trigger Level for ATLAS the Fast TracKer (FTK) Project

CERN Document Server

INSPIRE-00245767

2015-01-01

Physics collisions at 13 TeV are expected at the LHC with an average of 40-50 proton-proton collisions per bunch crossing under nominal conditions. Tracking at trigger level is an essential tool to control the rate in high-pileup conditions while maintaining a good efficiency for relevant physics processes. The Fast TracKer is an integral part of the trigger upgrade for the ATLAS detector. For every event passing the Level-1 trigger (at a maximum rate of 100 kHz) the FTK receives data from all the channels of the silicon detectors, providing tracking information to the High Level Trigger in order to ensure a selection robust against pile-up. The FTK performs a hardware-based track reconstruction, using associative memory that is based on the use of a custom chip, designed to perform pattern matching at very high speed. It finds track candidates at low resolution (roads) that seed a full-resolution track fitting done by FPGAs. An overview of the FTK system with focus on the pattern matching procedure will be p...

Relationship between Legible Handwriting and Level of Success of Third Grade Students in Written Expression

Science.gov (United States)

Bayat, Seher; Küçükayar, Hasan

2016-01-01

This study aims to identify third-grade students' performance levels for written expression and handwriting and to find the relationship between these performances. The study is based on relational screening model. It is carried out with 110 third grade students. Students' levels of success in handwriting and in written expression are evaluated…

A Photometric Technique for Determining Fluid Concentration using Consumer-Grade Hardware

Science.gov (United States)

Leslie, F.; Ramachandran, N.

1999-01-01

In support of a separate study to produce an exponential concentration gradient in a magnetic fluid, a noninvasive technique for determining, species concentration from off-the-shelf hardware has been developed. The approach uses a backlighted fluid test cell photographed with a commercial digital camcorder. Because the light extinction coefficient is wavelength dependent, tests were conducted to determine the best filter color to use, although some guidance was also provided using an absorption spectrophotometer. With the appropriate filter in place, the provide attenuation of the light passing, through the test cell was captured by the camcorder. The digital image was analyzed for intensity using, software from Scion Image Corp. downloaded from the Internet. The analysis provides a two-dimensional array of concentration with an average error of 0.0095 ml/ml. This technique is superior to invasive techniques, which require extraction of a sample that disturbs the concentration distribution in the test cell. Refinements of this technique using a true monochromatic laser light Source are also discussed.

Hardware Demonstrator of a Level-1 Track Finding Algorithm with FPGAs for the Phase II CMS Experiment

CERN Document Server

AUTHOR|(CDS)2090481

2016-01-01

At the HL-LHC, proton bunches collide every 25\\,ns, producing an average of 140 pp interactions per bunch crossing. To operate in such an environment, the CMS experiment will need a Level-1 (L1) hardware trigger, able to identify interesting events within a latency of 12.5\\,$\\mu$s. This novel L1 trigger will make use of data coming from the silicon tracker to constrain the trigger rate. Goal of this new \\textit{track trigger} will be to build L1 tracks from the tracker information. The architecture that will be implemented in future to process tracker data is still under discussion. One possibility is to adopt a system entirely based on FPGA electronic. The proposed track finding algorithm is based on the Hough transform method. The algorithm has been tested using simulated pp collision data and it is currently being demonstrated in hardware, using the ``MP7'', which is a $\\mu$TCA board with a powerful FPGA capable of handling data rates approaching 1 Tb/s. Two different implementations of the Hough tran...

Foundations of hardware IP protection

CERN Document Server

Torres, Lionel

2017-01-01

This book provides a comprehensive and up-to-date guide to the design of security-hardened, hardware intellectual property (IP). Readers will learn how IP can be threatened, as well as protected, by using means such as hardware obfuscation/camouflaging, watermarking, fingerprinting (PUF), functional locking, remote activation, hidden transmission of data, hardware Trojan detection, protection against hardware Trojan, use of secure element, ultra-lightweight cryptography, and digital rights management. This book serves as a single-source reference to design space exploration of hardware security and IP protection. · Provides readers with a comprehensive overview of hardware intellectual property (IP) security, describing threat models and presenting means of protection, from integrated circuit layout to digital rights management of IP; · Enables readers to transpose techniques fundamental to digital rights management (DRM) to the realm of hardware IP security; · Introduce designers to the concept of salutar...

Open hardware for open science

CERN Multimedia

CERN Bulletin

2011-01-01

Inspired by the open source software movement, the Open Hardware Repository was created to enable hardware developers to share the results of their R&D activities. The recently published CERN Open Hardware Licence offers the legal framework to support this knowledge and technology exchange.   Two years ago, a group of electronics designers led by Javier Serrano, a CERN engineer, working in experimental physics laboratories created the Open Hardware Repository (OHR). This project was initiated in order to facilitate the exchange of hardware designs across the community in line with the ideals of “open science”. The main objectives include avoiding duplication of effort by sharing results across different teams that might be working on the same need. “For hardware developers, the advantages of open hardware are numerous. For example, it is a great learning tool for technologies some developers would not otherwise master, and it avoids unnecessary work if someone ha...

An Analysis of Grades, Class Level and Faculty Evaluation Scores in the United Arab Emirates

Science.gov (United States)

Waller, Lee

2016-01-01

This study examined the results of a student evaluation of faculty against the grades awarded and the level of the course for a higher education institution in the United Arab Emirates. The purpose of the study was to determine if the grades awarded in the course and/or level of the course impacted the evaluation scores awarded to the faculty…

Open Hardware Business Models

OpenAIRE

Edy Ferreira

2008-01-01

In the September issue of the Open Source Business Resource, Patrick McNamara, president of the Open Hardware Foundation, gave a comprehensive introduction to the concept of open hardware, including some insights about the potential benefits for both companies and users. In this article, we present the topic from a different perspective, providing a classification of market offers from companies that are making money with open hardware.

Integrated circuit authentication hardware Trojans and counterfeit detection

CERN Document Server

Tehranipoor, Mohammad; Zhang, Xuehui

2013-01-01

This book describes techniques to verify the authenticity of integrated circuits (ICs). It focuses on hardware Trojan detection and prevention and counterfeit detection and prevention. The authors discuss a variety of detection schemes and design methodologies for improving Trojan detection techniques, as well as various attempts at developing hardware Trojans in IP cores and ICs. While describing existing Trojan detection methods, the authors also analyze their effectiveness in disclosing various types of Trojans, and demonstrate several architecture-level solutions. 

Programming time-multiplexed reconfigurable hardware using a scalable neuromorphic compiler.

Science.gov (United States)

Minkovich, Kirill; Srinivasa, Narayan; Cruz-Albrecht, Jose M; Cho, Youngkwan; Nogin, Aleksey

2012-06-01

Scalability and connectivity are two key challenges in designing neuromorphic hardware that can match biological levels. In this paper, we describe a neuromorphic system architecture design that addresses an approach to meet these challenges using traditional complementary metal-oxide-semiconductor (CMOS) hardware. A key requirement in realizing such neural architectures in hardware is the ability to automatically configure the hardware to emulate any neural architecture or model. The focus for this paper is to describe the details of such a programmable front-end. This programmable front-end is composed of a neuromorphic compiler and a digital memory, and is designed based on the concept of synaptic time-multiplexing (STM). The neuromorphic compiler automatically translates any given neural architecture to hardware switch states and these states are stored in digital memory to enable desired neural architectures. STM enables our proposed architecture to address scalability and connectivity using traditional CMOS hardware. We describe the details of the proposed design and the programmable front-end, and provide examples to illustrate its capabilities. We also provide perspectives for future extensions and potential applications.

Students' Level of Boredom, Boredom Coping Strategies, Epistemic Curiosity, and Graded Performance

Science.gov (United States)

Eren, Altay; Coskun, Hamit

2016-01-01

The authors examined the relationships among students' levels of boredom, boredom coping strategies, epistemic curiosity, and graded performance regarding mathematics lessons, with the intention to explore the mediating roles of boredom coping strategies and epistemic curiosity in the relationship between the level of boredom and graded…

Open Hardware Business Models

Directory of Open Access Journals (Sweden)

Edy Ferreira

2008-04-01

Full Text Available In the September issue of the Open Source Business Resource, Patrick McNamara, president of the Open Hardware Foundation, gave a comprehensive introduction to the concept of open hardware, including some insights about the potential benefits for both companies and users. In this article, we present the topic from a different perspective, providing a classification of market offers from companies that are making money with open hardware.

Timing generator of scientific grade CCD camera and its implementation based on FPGA technology

Science.gov (United States)

Si, Guoliang; Li, Yunfei; Guo, Yongfei

2010-10-01

The Timing Generator's functions of Scientific Grade CCD Camera is briefly presented: it generates various kinds of impulse sequence for the TDI-CCD, video processor and imaging data output, acting as the synchronous coordinator for time in the CCD imaging unit. The IL-E2TDI-CCD sensor produced by DALSA Co.Ltd. use in the Scientific Grade CCD Camera. Driving schedules of IL-E2 TDI-CCD sensor has been examined in detail, the timing generator has been designed for Scientific Grade CCD Camera. FPGA is chosen as the hardware design platform, schedule generator is described with VHDL. The designed generator has been successfully fulfilled function simulation with EDA software and fitted into XC2VP20-FF1152 (a kind of FPGA products made by XILINX). The experiments indicate that the new method improves the integrated level of the system. The Scientific Grade CCD camera system's high reliability, stability and low power supply are achieved. At the same time, the period of design and experiment is sharply shorted.

Serum endocan levels before and after surgery on low-grade gliomas.

Science.gov (United States)

Tanriverdi, Taner; Kemerdere, Rahsan; Inal, Berrin B; Yuksel, Odhan; Emre, Humeyra O; Ahmedov, Merdin; Baran, Oguz; Ates, Seda

2017-01-01

Endocan has been shown to be a marker for several cancers and may show degree of malignancy. The aim of this study is to assess serum levels of endocan before and after surgery on low-grade gliomas (LGGs). Endocan was assayed by commercially available enzyme-linked immunosorbent assay (ELISA) kits in a total of 19 patients and 12 controls. Serial serum samples were obtained before and after surgery (1 st day, 1 st week, and 1 st month of surgery). Control samples were collected from cord blood during cesarean section. The results were compared with control brain tissues. Controls showed significantly lower serum endocan levels compared to before and after surgery ( P < 0.05). There is a trend of increase in mean serum levels from before surgery and during the very early period after surgery (during first week); however, in the first month, mean serum levels became lower. Endocan, a vital molecule for angiogenesis, is highly expressed before and after surgery in LGGs, but long-term data is needed. Furthermore, future studies should include high-grade gliomas to discuss whether endocan is associated with recurrence and response to treatment.

Advances in neuromorphic hardware exploiting emerging nanoscale devices

CERN Document Server

2017-01-01

This book covers all major aspects of cutting-edge research in the field of neuromorphic hardware engineering involving emerging nanoscale devices. Special emphasis is given to leading works in hybrid low-power CMOS-Nanodevice design. The book offers readers a bidirectional (top-down and bottom-up) perspective on designing efficient bio-inspired hardware. At the nanodevice level, it focuses on various flavors of emerging resistive memory (RRAM) technology. At the algorithm level, it addresses optimized implementations of supervised and stochastic learning paradigms such as: spike-time-dependent plasticity (STDP), long-term potentiation (LTP), long-term depression (LTD), extreme learning machines (ELM) and early adoptions of restricted Boltzmann machines (RBM) to name a few. The contributions discuss system-level power/energy/parasitic trade-offs, and complex real-world applications. The book is suited for both advanced researchers and students interested in the field.

Grade Level Differences in High School Students' Conceptions of and Motives for Learning Science

Science.gov (United States)

Wang, Ya-Ling; Tsai, Chin-Chung

2017-08-01

Students' conceptions of learning science and their relations with motive for learning may vary as the education level increases. This study aimed to compare the quantitative patterns in students' conceptions of learning science (COLS) and motives for learning science (MLS) across grade levels by adopting two survey instruments. A total of 768 high school students were surveyed in Taiwan, including 204 eighth graders, 262 tenth graders, and 302 12th graders. In the current research, memorizing, testing, and calculating and practicing were categorized as reproductive conceptions of learning science, while increase of knowledge, applying, understanding and seeing-in-a-new-way were regarded as constructivist conceptions. The results of multivariate analyses of variance (MANOVA) revealed that conceptions of learning science are more constructivist as education level increases. Both tenth graders and 12th graders endorsed understanding, seeing-in-a-new-way, and the constructivist COLS composite more strongly than the eighth graders did. In addition, the results of multigroup structural equation modeling (SEM) analysis indicated that the positive relations between testing and reproductive COLS were stronger as the grade level increased, while the negative relations between reproductive COLS and deep motive were tighter with the increase in grade level.

Teacher-to-Teacher Consultation: Facilitating Consistent and Effective Intervention across Grade Levels for Students with ADHD

Science.gov (United States)

Gormley, Matthew J.; Dupaul, George J.

2015-01-01

Teacher-to-teacher consultation (TTC) is an extension of standard behavioral consultation that seeks to transfer an established and effective intervention across a grade-level transition by including teachers from both grade levels as conjoint consultees at the beginning of the second school year. The purpose of the current study was to determine…

Computer organization and design the hardware/software interface

CERN Document Server

Hennessy, John L

1994-01-01

Computer Organization and Design: The Hardware/Software Interface presents the interaction between hardware and software at a variety of levels, which offers a framework for understanding the fundamentals of computing. This book focuses on the concepts that are the basis for computers.Organized into nine chapters, this book begins with an overview of the computer revolution. This text then explains the concepts and algorithms used in modern computer arithmetic. Other chapters consider the abstractions and concepts in memory hierarchies by starting with the simplest possible cache. This book di

Predictors of cultural capital on science academic achievement at the 8th grade level

Science.gov (United States)

Misner, Johnathan Scott

The purpose of the study was to determine if students' cultural capital is a significant predictor of 8th grade science achievement test scores in urban locales. Cultural capital refers to the knowledge used and gained by the dominant class, which allows social and economic mobility. Cultural capital variables include magazines at home and parental education level. Other variables analyzed include socioeconomic status (SES), gender, and English language learners (ELL). This non-experimental study analyzed the results of the 2011 Eighth Grade Science National Assessment of Educational Progress (NAEP). The researcher analyzed the data using a multivariate stepwise regression analysis. The researcher concluded that the addition of cultural capital factors significantly increased the predictive power of the model where magazines in home, gender, student classified as ELL, parental education level, and SES were the independent variables and science achievement was the dependent variable. For alpha=0.05, the overall test for the model produced a R2 value of 0.232; therefore the model predicted 23.2% of variance in science achievement results. Other major findings include: higher measures of home resources predicted higher 2011 NAEP eighth grade science achievement; males were predicted to have higher 2011 NAEP 8 th grade science achievement; classified ELL students were predicted to score lower on the NAEP eight grade science achievement; higher parent education predicted higher NAEP eighth grade science achievement; lower measures of SES predicted lower 2011 NAEP eighth grade science achievement. This study contributed to the research in this field by identifying cultural capital factors that have been found to have statistical significance on predicting eighth grade science achievement results, which can lead to strategies to help improve science academic achievement among underserved populations.

Performance comparison between ISCSI and other hardware and software solutions

CERN Document Server

Gug, M

2003-01-01

We report on our investigations on some technologies that can be used to build disk servers and networks of disk servers using commodity hardware and software solutions. It focuses on the performance that can be achieved by these systems and gives measured figures for different configurations. It is divided into two parts : iSCSI and other technologies and hardware and software RAID solutions. The first part studies different technologies that can be used by clients to access disk servers using a gigabit ethernet network. It covers block access technologies (iSCSI, hyperSCSI, ENBD). Experimental figures are given for different numbers of clients and servers. The second part compares a system based on 3ware hardware RAID controllers, a system using linux software RAID and IDE cards and a system mixing both hardware RAID and software RAID. Performance measurements for reading and writing are given for different RAID levels.

Hardware Demonstrator of a Level-1 Track Finding Algorithm with FPGAs for the Phase II CMS Experiment

International Nuclear Information System (INIS)

Cieri, D.

2016-01-01

At the HL-LHC, proton bunches collide every 25 ns, producing an average of 140 pp interactions per bunch crossing. To operate in such an environment, the CMS experiment will need a Level-1 (L1) hardware trigger, able to identify interesting events within a latency of 12.5 μs. This novel L1 trigger will make use of data coming from the silicon tracker to constrain the trigger rate . Goal of this new track trigger will be to build L1 tracks from the tracker information. The architecture that will be implemented in future to process tracker data is still under discussion. One possibility is to adopt a system entirely based on FPGA electronic. The proposed track finding algorithm is based on the Hough transform method. The algorithm has been tested using simulated pp collision data and it is currently being demonstrated in hardware, using the “MP7”, which is a μTCA board with a powerful FPGA capable of handling data rates approaching 1 Tb/s. Two different implementations of the Hough transform technique are currently under investigation: one utilizes a systolic array to represent the Hough space, while the other exploits a pipelined approach. (paper)

A Modular Framework for Modeling Hardware Elements in Distributed Engine Control Systems

Science.gov (United States)

Zinnecker, Alicia M.; Culley, Dennis E.; Aretskin-Hariton, Eliot D.

2015-01-01

Progress toward the implementation of distributed engine control in an aerospace application may be accelerated through the development of a hardware-in-the-loop (HIL) system for testing new control architectures and hardware outside of a physical test cell environment. One component required in an HIL simulation system is a high-fidelity model of the control platform: sensors, actuators, and the control law. The control system developed for the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k) provides a verifiable baseline for development of a model for simulating a distributed control architecture. This distributed controller model will contain enhanced hardware models, capturing the dynamics of the transducer and the effects of data processing, and a model of the controller network. A multilevel framework is presented that establishes three sets of interfaces in the control platform: communication with the engine (through sensors and actuators), communication between hardware and controller (over a network), and the physical connections within individual pieces of hardware. This introduces modularity at each level of the model, encouraging collaboration in the development and testing of various control schemes or hardware designs. At the hardware level, this modularity is leveraged through the creation of a SimulinkR library containing blocks for constructing smart transducer models complying with the IEEE 1451 specification. These hardware models were incorporated in a distributed version of the baseline C-MAPSS40k controller and simulations were run to compare the performance of the two models. The overall tracking ability differed only due to quantization effects in the feedback measurements in the distributed controller. Additionally, it was also found that the added complexity of the smart transducer models did not prevent real-time operation of the distributed controller model, a requirement of an HIL system.

A Scalable Approach for Hardware Semiformal Verification

OpenAIRE

Grimm, Tomas; Lettnin, Djones; Hübner, Michael

2018-01-01

The current verification flow of complex systems uses different engines synergistically: virtual prototyping, formal verification, simulation, emulation and FPGA prototyping. However, none is able to verify a complete architecture. Furthermore, hybrid approaches aiming at complete verification use techniques that lower the overall complexity by increasing the abstraction level. This work focuses on the verification of complex systems at the RT level to handle the hardware peculiarities. Our r...

Hardware controls for the STAR experiment at RHIC

International Nuclear Information System (INIS)

Reichhold, D.; Bieser, F.; Bordua, M.; Cherney, M.; Chrin, J.; Dunlop, J.C.; Ferguson, M.I.; Ghazikhanian, V.; Gross, J.; Harper, G.; Howe, M.; Jacobson, S.; Klein, S.R.; Kravtsov, P.; Lewis, S.; Lin, J.; Lionberger, C.; LoCurto, G.; McParland, C.; McShane, T.; Meier, J.; Sakrejda, I.; Sandler, Z.; Schambach, J.; Shi, Y.; Willson, R.; Yamamoto, E.; Zhang, W.

2003-01-01

The STAR detector sits in a high radiation area when operating normally; therefore it was necessary to develop a robust system to remotely control all hardware. The STAR hardware controls system monitors and controls approximately 14,000 parameters in the STAR detector. Voltages, currents, temperatures, and other parameters are monitored. Effort has been minimized by the adoption of experiment-wide standards and the use of pre-packaged software tools. The system is based on the Experimental Physics and Industrial Control System (EPICS) . VME processors communicate with subsystem-based sensors over a variety of field busses, with High-level Data Link Control (HDLC) being the most prevalent. Other features of the system include interfaces to accelerator and magnet control systems, a web-based archiver, and C++-based communication between STAR online, run control and hardware controls and their associated databases. The system has been designed for easy expansion as new detector elements are installed in STAR

Hardware Support for Embedded Java

DEFF Research Database (Denmark)

Schoeberl, Martin

2012-01-01

The general Java runtime environment is resource hungry and unfriendly for real-time systems. To reduce the resource consumption of Java in embedded systems, direct hardware support of the language is a valuable option. Furthermore, an implementation of the Java virtual machine in hardware enables...... worst-case execution time analysis of Java programs. This chapter gives an overview of current approaches to hardware support for embedded and real-time Java....

Effect of Graded Levels of Dates Dietary Fiber on Weight Gain ...

African Journals Online (AJOL)

Objective: The aim of the study was to evaluate the effect of graded levels of dates dietary fiber on diabetes mellitus induced by streptozotocin (STZ) in male Sprague-Dawley (SD) rats. Methodology: Rats were divided into eight groups, among which four groups (Groups 1-4) were normal and the other four groups were ...

HARDWARE TROJAN IDENTIFICATION AND DETECTION

OpenAIRE

Samer Moein; Fayez Gebali; T. Aaron Gulliver; Abdulrahman Alkandari

2017-01-01

ABSTRACT The majority of techniques developed to detect hardware trojans are based on specific attributes. Further, the ad hoc approaches employed to design methods for trojan detection are largely ineffective. Hardware trojans have a number of attributes which can be used to systematically develop detection techniques. Based on this concept, a detailed examination of current trojan detection techniques and the characteristics of existing hardware trojans is presented. This is used to dev...

Event-driven processing for hardware-efficient neural spike sorting

Science.gov (United States)

Liu, Yan; Pereira, João L.; Constandinou, Timothy G.

2018-02-01

Objective. The prospect of real-time and on-node spike sorting provides a genuine opportunity to push the envelope of large-scale integrated neural recording systems. In such systems the hardware resources, power requirements and data bandwidth increase linearly with channel count. Event-based (or data-driven) processing can provide here a new efficient means for hardware implementation that is completely activity dependant. In this work, we investigate using continuous-time level-crossing sampling for efficient data representation and subsequent spike processing. Approach. (1) We first compare signals (synthetic neural datasets) encoded with this technique against conventional sampling. (2) We then show how such a representation can be directly exploited by extracting simple time domain features from the bitstream to perform neural spike sorting. (3) The proposed method is implemented in a low power FPGA platform to demonstrate its hardware viability. Main results. It is observed that considerably lower data rates are achievable when using 7 bits or less to represent the signals, whilst maintaining the signal fidelity. Results obtained using both MATLAB and reconfigurable logic hardware (FPGA) indicate that feature extraction and spike sorting accuracies can be achieved with comparable or better accuracy than reference methods whilst also requiring relatively low hardware resources. Significance. By effectively exploiting continuous-time data representation, neural signal processing can be achieved in a completely event-driven manner, reducing both the required resources (memory, complexity) and computations (operations). This will see future large-scale neural systems integrating on-node processing in real-time hardware.

Internet-based hardware/software co-design framework for embedded 3D graphics applications

Directory of Open Access Journals (Sweden)

Wong Weng-Fai

2011-01-01

Full Text Available Abstract Advances in technology are making it possible to run three-dimensional (3D graphics applications on embedded and handheld devices. In this article, we propose a hardware/software co-design environment for 3D graphics application development that includes the 3D graphics software, OpenGL ES application programming interface (API, device driver, and 3D graphics hardware simulators. We developed a 3D graphics system-on-a-chip (SoC accelerator using transaction-level modeling (TLM. This gives software designers early access to the hardware even before it is ready. On the other hand, hardware designers also stand to gain from the more complex test benches made available in the software for verification. A unique aspect of our framework is that it allows hardware and software designers from geographically dispersed areas to cooperate and work on the same framework. Designs can be entered and executed from anywhere in the world without full access to the entire framework, which may include proprietary components. This results in controlled and secure transparency and reproducibility, granting leveled access to users of various roles.

Hunting for hardware changes in data centres

International Nuclear Information System (INIS)

Coelho dos Santos, M; Steers, I; Szebenyi, I; Xafi, A; Barring, O; Bonfillou, E

2012-01-01

With many servers and server parts the environment of warehouse sized data centres is increasingly complex. Server life-cycle management and hardware failures are responsible for frequent changes that need to be managed. To manage these changes better a project codenamed “hardware hound” focusing on hardware failure trending and hardware inventory has been started at CERN. By creating and using a hardware oriented data set - the inventory - with detailed information on servers and their parts as well as tracking changes to this inventory, the project aims at, for example, being able to discover trends in hardware failure rates.

Open-source hardware for medical devices.

Science.gov (United States)

Niezen, Gerrit; Eslambolchilar, Parisa; Thimbleby, Harold

2016-04-01

Open-source hardware is hardware whose design is made publicly available so anyone can study, modify, distribute, make and sell the design or the hardware based on that design. Some open-source hardware projects can potentially be used as active medical devices. The open-source approach offers a unique combination of advantages, including reducing costs and faster innovation. This article compares 10 of open-source healthcare projects in terms of how easy it is to obtain the required components and build the device.

Generation of embedded Hardware/Software from SystemC

OpenAIRE

Houzet , Dominique; Ouadjaout , Salim

2006-01-01

International audience; Designers increasingly rely on reusing intellectual property (IP) and on raising the level of abstraction to respect system-on-chip (SoC) market characteristics. However, most hardware and embedded software codes are recoded manually from system level. This recoding step often results in new coding errors that must be identified and debugged. Thus, shorter time-to-market requires automation of the system synthesis from high-level specifications. In this paper, we propo...

CBM maze-scores as indicators of reading level and growth for seventh-grade students

NARCIS (Netherlands)

Chung, S.; Espin, C.A.; Stevenson, C.E.

The technical adequacy of CBM maze-scores as indicators of reading level and growth for seventh-grade secondary-school students was examined. Participants were 452 Dutch students who completed weekly maze measures over a period of 23 weeks. Criterion measures were school level, dyslexia status,

An evaluation of Skylab habitability hardware

Science.gov (United States)

Stokes, J.

1974-01-01

For effective mission performance, participants in space missions lasting 30-60 days or longer must be provided with hardware to accommodate their personal needs. Such habitability hardware was provided on Skylab. Equipment defined as habitability hardware was that equipment composing the food system, water system, sleep system, waste management system, personal hygiene system, trash management system, and entertainment equipment. Equipment not specifically defined as habitability hardware but which served that function were the Wardroom window, the exercise equipment, and the intercom system, which was occasionally used for private communications. All Skylab habitability hardware generally functioned as intended for the three missions, and most items could be considered as adequate concepts for future flights of similar duration. Specific components were criticized for their shortcomings.

Digital Controller Development Methodology Based on Real-Time Simulations with LabVIEW FPGA Hardware-Software Toolset

Directory of Open Access Journals (Sweden)

Tommaso Caldognetto

2013-12-01

Full Text Available In this paper, we exemplify the use of NI Lab-VIEW FPGA as a rapid prototyping environment for digital controllers. In our power electronics laboratory, it has been successfully employed in the development, debugging, and test of different power converter controllers for microgrid applications.The paper shows how this high level programming language,together with its target hardware platforms, including CompactRIO and Single Board RIO systems, allows researchers and students to develop even complex applications in reasonable times. The availability of efficient drivers for the considered hardware platforms frees the users from the burden of low level programming. At the same time, the high level programming approach facilitates software re-utilization, allowing the laboratory know-how to steadily grow along time. Furthermore, it allows hardware-in-the-loop real-time simulation, that proved to be effective, and safe, in debugging even complex hardware and software co-designed controllers. To illustrate the effectiveness of these hardware-software toolsets and of the methodology based upon them, two case studies are

Is Hardware Removal Recommended after Ankle Fracture Repair?

Directory of Open Access Journals (Sweden)

Hong-Geun Jung

2016-01-01

Full Text Available The indications and clinical necessity for routine hardware removal after treating ankle or distal tibia fracture with open reduction and internal fixation are disputed even when hardware-related pain is insignificant. Thus, we determined the clinical effects of routine hardware removal irrespective of the degree of hardware-related pain, especially in the perspective of patients’ daily activities. This study was conducted on 80 consecutive cases (78 patients treated by surgery and hardware removal after bony union. There were 56 ankle and 24 distal tibia fractures. The hardware-related pain, ankle joint stiffness, discomfort on ambulation, and patient satisfaction were evaluated before and at least 6 months after hardware removal. Pain score before hardware removal was 3.4 (range 0 to 6 and decreased to 1.3 (range 0 to 6 after removal. 58 (72.5% patients experienced improved ankle stiffness and 65 (81.3% less discomfort while walking on uneven ground and 63 (80.8% patients were satisfied with hardware removal. These results suggest that routine hardware removal after ankle or distal tibia fracture could ameliorate hardware-related pain and improves daily activities and patient satisfaction even when the hardware-related pain is minimal.

Hierarchical Effects of School-, Classroom-, and Student-Level Factors on the Science Performance of Eighth-Grade Taiwanese Students

Science.gov (United States)

Tsai, Liang-Ting; Yang, Chih-Chien

2015-05-01

This study was conducted to understand the effect of student-, classroom-, and school-level factors on the science performance of 8th-grade Taiwanese students in the Trends in International Mathematics and Science Study (TIMSS) 2011 by using multilevel analysis. A total of 5,042 students from 153 classrooms of 150 schools participated in the TIMSS 2011 study, in which they were required to complete questionnaires. A 3-level multilevel analysis was used to assess the influence of factors at 3 levels on the science performance of 8th-grade Taiwanese students. The results showed that the provision of education resources at home, teachers' level of education, and school climate were the strongest predictor of science performance at the student, classroom, and school level, respectively. It was concluded that the science performance of 8th-grade Taiwanese students is driven largely by individual factors. Classroom-level factors accounted for a smaller proportion of the total variance in science performance than did school-level factors.

Door Hardware and Installations; Carpentry: 901894.

Science.gov (United States)

Dade County Public Schools, Miami, FL.

The curriculum guide outlines a course designed to provide instruction in the selection, preparation, and installation of hardware for door assemblies. The course is divided into five blocks of instruction (introduction to doors and hardware, door hardware, exterior doors and jambs, interior doors and jambs, and a quinmester post-test) totaling…

The Revised School Culture Elements Questionnaire: Gender and Grade Level Invariant?

Science.gov (United States)

DeVaney, Thomas A.; Adams, Nan B.; Hill-Winstead, Flo; Trahan, Mitzi P.

2012-01-01

The purpose of this research was to examine the psychometric properties of the RSCEQ with respect to invariance across gender and grade level, using a sample of 901 teachers from 44 schools in southeast Louisiana. Reliability estimates were consistent with previous research and ranged from 0.81 to 0.90 on the actual and 0.83 to 0.92 on the…

Smart Home Hardware-in-the-Loop Testing

Energy Technology Data Exchange (ETDEWEB)

Pratt, Annabelle

2017-07-12

This presentation provides a high-level overview of NREL's smart home hardware-in-the-loop testing. It was presented at the Fourth International Workshop on Grid Simulator Testing of Energy Systems and Wind Turbine Powertrains, held April 25-26, 2017, hosted by NREL and Clemson University at the Energy Systems Integration Facility in Golden, Colorado.

High exposure rate hardware ALARA plan

International Nuclear Information System (INIS)

Nellesen, A.L.

1996-10-01

This as low as reasonably achievable review provides a description of the engineering and administrative controls used to manage personnel exposure and to control contamination levels and airborne radioactivity concentrations. HERH waste is hardware found in the N-Fuel Storage Basin, which has a contact dose rate greater than 1 R/hr and used filters. This waste will be collected in the fuel baskets at various locations in the basins

Research and development of intelligent controller for high-grade sanitary ware

Science.gov (United States)

Bao, Kongjun; Shen, Qingping

2013-03-01

With the social and economic development and people's living standards improve, more and more emphasis on modern society, people improve the quality of family life, the use of intelligent controller applications in high-grade sanitary ware physiotherapy students. Analysis of high-grade sanitary ware physiotherapy common functions pointed out in the production and use of the possible risks, proposed implementation of the system hardware and matching, given the system software implementation process. High-grade sanitary ware physiotherapy intelligent controller not only to achieve elegant and beautiful, simple, physical therapy, water power, deodorant, multi-function, intelligent control, to meet the consumers, the high-end sanitary ware market, strong demand, Accelerate the enterprise product Upgrade and improve the competitiveness of enterprises.

Relationship of word- and sentence-level working memory to reading and writing in second, fourth, and sixth grade.

Science.gov (United States)

Berninger, Virginia W; Abbott, Robert D; Swanson, H Lee; Lovitt, Dan; Trivedi, Pam; Lin, Shin-Ju Cindy; Gould, Laura; Youngstrom, Marci; Shimada, Shirley; Amtmann, Dagmar

2010-04-01

The purpose of this study was to evaluate the contribution of working memory at the word and sentence levels of language to reading and writing outcomes. Measures of working memory at the word and sentence levels, reading and writing, were administered to 2nd (N = 122), 4th (N = 222), and 6th (N = 105) graders. Structural equation modeling was used to evaluate whether the 2 predictor working memory factors contributed unique variance beyond their shared covariance to each of 5 outcome factors: handwriting, spelling, composing, word reading, and reading comprehension. At each grade level, except for handwriting and composing in 6th grade, the word-level working memory factor contributed unique variance to each reading and writing outcome. The text-level working memory factor contributed unique variance to reading comprehension in 4th and 6th grade. The clinical significance of these findings for assessment and intervention is discussed.

From Open Source Software to Open Source Hardware

OpenAIRE

Viseur , Robert

2012-01-01

Part 2: Lightning Talks; International audience; The open source software principles progressively give rise to new initiatives for culture (free culture), data (open data) or hardware (open hardware). The open hardware is experiencing a significant growth but the business models and legal aspects are not well known. This paper is dedicated to the economics of open hardware. We define the open hardware concept and determine intellectual property tools we can apply to open hardware, with a str...

Career Aspirations of Adolescent Girls: Effects of Achievement Level, Grade, and Single-Sex School Environment.

Science.gov (United States)

Watson, Cary M.; Quatman, Teri; Edler, Erik

2002-01-01

Compared high achieving adolescent girls' ideal and real career aspirations to adolescent boys' aspirations, examining the influence of grade level, achievement level, and an all-girls school environment. At all achievement levels, girls were commensurate with boys in ideal and realistic career aspirations. High achieving girls exceeded the…

Fifth-Grade Turkish Elementary School Students' Listening and Reading Comprehension Levels with Regard to Text Types

Science.gov (United States)

Yildirim, Kasim; Yildiz, Mustafa; Ates, Seyit; Rasinski, Timothy

2010-01-01

The aim of this study was to examine fifth grade elementary school students' listening and reading comprehension levels with regard to text types. This study was conducted on 180 fifth grade elementary school students in Sincan-Ankara in the spring semester of the academic year 2008-2009. The comprehension test was administered to students. The…

SYNTHESIS OF INFORMATION SYSTEM FOR SMART HOUSE HARDWARE MANAGEMENT

Directory of Open Access Journals (Sweden)

Vikentyeva Olga Leonidovna

2017-10-01

Full Text Available Subject: smart house maintenance requires taking into account a number of factors: resource-saving, reduction of operational expenditures, safety enhancement, providing comfortable working and leisure conditions. Automation of the corresponding engineering systems of illumination, climate control, security as well as communication systems and networks via utilization of contemporary technologies (e.g., IoT - Internet of Things poses a significant challenge related to storage and processing of the overwhelmingly massive volume of data whose utilization extent is extremely low nowadays. Since a building’s lifespan is large enough and exceeds the lifespan of codes and standards that take into account the requirements of safety, comfort, energy saving, etc., it is necessary to consider management aspects in the context of rational use of large data at the stage of information modeling. Research objectives: increase the efficiency of managing the subsystems of smart buildings hardware on the basis of a web-based information system that has a flexible multi-level architecture with several control loops and an adaptation model. Materials and methods: since a smart house belongs to man-machine systems, the cybernetic approach is considered as the basic method for design and research of information management system. Instrumental research methods are represented by set-theoretical modelling, automata theory and architectural principles of organization of information management systems. Results: a flexible architecture of information system for management of smart house hardware subsystems has been synthesized. This architecture encompasses several levels: client level, application level and data level as well as three layers: presentation level, actuating device layer and analytics layer. The problem of growing volumes of information processed by realtime message controller is attended by employment of sensors and actuating mechanisms with configurable

A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems

Directory of Open Access Journals (Sweden)

Manuel Saldaña

2009-01-01

Full Text Available High-performance reconfigurable computers (HPRCs provide a mix of standard processors and FPGAs to collectively accelerate applications. This introduces new design challenges, such as the need for portable programming models across HPRCs and system-level verification tools. To address the need for cosimulating a complete heterogeneous application using both software and hardware in an HPRC, we have created a tool called the Message-passing Simulation Framework (MSF. We have used it to simulate and develop an interface enabling an MPI-based approach to exchange data between X86 processors and hardware engines inside FPGAs. The MSF can also be used as an application development tool that enables multiple FPGAs in simulation to exchange messages amongst themselves and with X86 processors. As an example, we simulate a LINPACK benchmark hardware core using an Intel-FSB-Xilinx-FPGA platform to quickly prototype the hardware, to test the communications. and to verify the benchmark results.

Content, format, gender and grade level differences in elementary students' ability to read science materials as measured by the cloze procedure

Science.gov (United States)

Williams, Richard L.; Yore, Larry D.

Present instructional trends in science indicate a need to reexamine a traditional concern in science education: the readability of science textbooks. An area of reading research not well documented is the effect of color, visuals, and page layout on readability of science materials. Using the cloze readability method, the present study explored the relationships between page format, grade level, sex, content, and elementary school students ability to read science material. Significant relationships were found between cloze scores and both grade level and content, and there was a significant interaction effect between grade and sex in favor of older males. No significant relationships could be attributed to page format and sex. In the area of science content, biological materials were most difficult in terms of readability followed by earth science and physical science. Grade level data indicated that grade five materials were more difficult for that level than either grade four or grade six materials were for students at each respective level. In eight of nine cases, the science text materials would be classified at or near the frustration level of readability. The implications for textbook writers and publishers are that science reading materials need to be produced with greater attention to readability and known design principles regarding visual supplements. The implication for teachers is that students need direct instruction in using visual materials to increase their learning from text material. Present visual materials appear to neither help nor hinder the student to gain information from text material.

Learning Achievement and the Efficiency of Learning the Concept of Vector Addition at Three Different Grade Levels

Science.gov (United States)

Gubrud, Allan R.; Novak, Joseph D.

1973-01-01

Empirical data relate to Bruner's and Ausubel's theories of learning concepts at different age levels. The concept of vector addition was taught to eighth, ninth, and tenth grade students. The concept was learned and retained by high ability ninth and all tenth grade students. (PS)

Hardware-accelerated autostereogram rendering for interactive 3D visualization

Science.gov (United States)

Petz, Christoph; Goldluecke, Bastian; Magnor, Marcus

2003-05-01

Single Image Random Dot Stereograms (SIRDS) are an attractive way of depicting three-dimensional objects using conventional display technology. Once trained in decoupling the eyes' convergence and focusing, autostereograms of this kind are able to convey the three-dimensional impression of a scene. We present in this work an algorithm that generates SIRDS at interactive frame rates on a conventional PC. The presented system allows rotating a 3D geometry model and observing the object from arbitrary positions in real-time. Subjective tests show that the perception of a moving or rotating 3D scene presents no problem: The gaze remains focused onto the object. In contrast to conventional SIRDS algorithms, we render multiple pixels in a single step using a texture-based approach, exploiting the parallel-processing architecture of modern graphics hardware. A vertex program determines the parallax for each vertex of the geometry model, and the graphics hardware's texture unit is used to render the dot pattern. No data has to be transferred between main memory and the graphics card for generating the autostereograms, leaving CPU capacity available for other tasks. Frame rates of 25 fps are attained at a resolution of 1024x512 pixels on a standard PC using a consumer-grade nVidia GeForce4 graphics card, demonstrating the real-time capability of the system.

ZEUS hardware control system

Science.gov (United States)

Loveless, R.; Erhard, P.; Ficenec, J.; Gather, K.; Heath, G.; Iacovacci, M.; Kehres, J.; Mobayyen, M.; Notz, D.; Orr, R.; Orr, R.; Sephton, A.; Stroili, R.; Tokushuku, K.; Vogel, W.; Whitmore, J.; Wiggers, L.

1989-12-01

The ZEUS collaboration is building a system to monitor, control and document the hardware of the ZEUS detector. This system is based on a network of VAX computers and microprocessors connected via ethernet. The database for the hardware values will be ADAMO tables; the ethernet connection will be DECNET, TCP/IP, or RPC. Most of the documentation will also be kept in ADAMO tables for easy access by users.

ZEUS hardware control system

International Nuclear Information System (INIS)

Loveless, R.; Erhard, P.; Ficenec, J.; Gather, K.; Heath, G.; Iacovacci, M.; Kehres, J.; Mobayyen, M.; Notz, D.; Orr, R.; Sephton, A.; Stroili, R.; Tokushuku, K.; Vogel, W.; Whitmore, J.; Wiggers, L.

1989-01-01

The ZEUS collaboration is building a system to monitor, control and document the hardware of the ZEUS detector. This system is based on a network of VAX computers and microprocessors connected via ethernet. The database for the hardware values will be ADAMO tables; the ethernet connection will be DECNET, TCP/IP, or RPC. Most of the documentation will also be kept in ADAMO tables for easy access by users. (orig.)

The LISA Pathfinder interferometry-hardware and system testing

Energy Technology Data Exchange (ETDEWEB)

Audley, H; Danzmann, K; MarIn, A Garcia; Heinzel, G; Monsky, A; Nofrarias, M; Steier, F; Bogenstahl, J [Albert-Einstein-Institut, Max-Planck-Institut fuer Gravitationsphysik und Universitaet Hannover, 30167 Hannover (Germany); Gerardi, D; Gerndt, R; Hechenblaikner, G; Johann, U; Luetzow-Wentzky, P; Wand, V [EADS Astrium GmbH, Friedrichshafen (Germany); Antonucci, F [Dipartimento di Fisica, Universita di Trento and INFN, Gruppo Collegato di Trento, 38050 Povo, Trento (Italy); Armano, M [European Space Astronomy Centre, European Space Agency, Villanueva de la Canada, 28692 Madrid (Spain); Auger, G; Binetruy, P [APC UMR7164, Universite Paris Diderot, Paris (France); Benedetti, M [Dipartimento di Ingegneria dei Materiali e Tecnologie Industriali, Universita di Trento and INFN, Gruppo Collegato di Trento, Mesiano, Trento (Italy); Boatella, C, E-mail: antonio.garcia@aei.mpg.de [CNES, DCT/AQ/EC, 18 Avenue Edouard Belin, 31401 Toulouse, Cedex 9 (France)

2011-05-07

Preparations for the LISA Pathfinder mission have reached an exciting stage. Tests of the engineering model (EM) of the optical metrology system have recently been completed at the Albert Einstein Institute, Hannover, and flight model tests are now underway. Significantly, they represent the first complete integration and testing of the space-qualified hardware and are the first tests on an optical system level. The results and test procedures of these campaigns will be utilized directly in the ground-based flight hardware tests, and subsequently during in-flight operations. In addition, they allow valuable testing of the data analysis methods using the MATLAB-based LTP data analysis toolbox. This paper presents an overview of the results from the EM test campaign that was successfully completed in December 2009.

CBM Maze-Scores as Indicators of Reading Level and Growth for Seventh-Grade Students

Science.gov (United States)

Chung, Siuman; Espin, Christine A.; Stevenson, Claire E.

2018-01-01

The technical adequacy of CBM maze-scores as indicators of reading level and growth for seventh-grade secondary-school students was examined. Participants were 452 Dutch students who completed weekly maze measures over a period of 23 weeks. Criterion measures were school level, dyslexia status, scores and growth on a standardized reading test.…

NDAS Hardware Translation Layer Development

Science.gov (United States)

Nazaretian, Ryan N.; Holladay, Wendy T.

2011-01-01

The NASA Data Acquisition System (NDAS) project is aimed to replace all DAS software for NASA s Rocket Testing Facilities. There must be a software-hardware translation layer so the software can properly talk to the hardware. Since the hardware from each test stand varies, drivers for each stand have to be made. These drivers will act more like plugins for the software. If the software is being used in E3, then the software should point to the E3 driver package. If the software is being used at B2, then the software should point to the B2 driver package. The driver packages should also be filled with hardware drivers that are universal to the DAS system. For example, since A1, A2, and B2 all use the Preston 8300AU signal conditioners, then the driver for those three stands should be the same and updated collectively.

Hardware standardization for embedded systems

International Nuclear Information System (INIS)

Sharma, M.K.; Kalra, Mohit; Patil, M.B.; Mohanty, Ashutos; Ganesh, G.; Biswas, B.B.

2010-01-01

Reactor Control Division (RCnD) has been one of the main designers of safety and safety related systems for power reactors. These systems have been built using in-house developed hardware. Since the present set of hardware was designed long ago, a need was felt to design a new family of hardware boards. A Working Group on Electronics Hardware Standardization (WG-EHS) was formed with an objective to develop a family of boards, which is general purpose enough to meet the requirements of the system designers/end users. RCnD undertook the responsibility of design, fabrication and testing of boards for embedded systems. VME and a proprietary I/O bus were selected as the two system buses. The boards have been designed based on present day technology and components. The intelligence of these boards has been implemented on FPGA/CPLD using VHDL. This paper outlines the various boards that have been developed with a brief description. (author)

Hardware for dynamic quantum computing.

Science.gov (United States)

Ryan, Colm A; Johnson, Blake R; Ristè, Diego; Donovan, Brian; Ohki, Thomas A

2017-10-01

We describe the hardware, gateware, and software developed at Raytheon BBN Technologies for dynamic quantum information processing experiments on superconducting qubits. In dynamic experiments, real-time qubit state information is fed back or fed forward within a fraction of the qubits' coherence time to dynamically change the implemented sequence. The hardware presented here covers both control and readout of superconducting qubits. For readout, we created a custom signal processing gateware and software stack on commercial hardware to convert pulses in a heterodyne receiver into qubit state assignments with minimal latency, alongside data taking capability. For control, we developed custom hardware with gateware and software for pulse sequencing and steering information distribution that is capable of arbitrary control flow in a fraction of superconducting qubit coherence times. Both readout and control platforms make extensive use of field programmable gate arrays to enable tailored qubit control systems in a reconfigurable fabric suitable for iterative development.

Hardware device binding and mutual authentication

Science.gov (United States)

Hamlet, Jason R; Pierson, Lyndon G

2014-03-04

Detection and deterrence of device tampering and subversion by substitution may be achieved by including a cryptographic unit within a computing device for binding multiple hardware devices and mutually authenticating the devices. The cryptographic unit includes a physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generates a binding PUF value. The cryptographic unit uses the binding PUF value during an enrollment phase and subsequent authentication phases. During a subsequent authentication phase, the cryptographic unit uses the binding PUF values of the multiple hardware devices to generate a challenge to send to the other device, and to verify a challenge received from the other device to mutually authenticate the hardware devices.

Secure coupling of hardware components

NARCIS (Netherlands)

Hoepman, J.H.; Joosten, H.J.M.; Knobbe, J.W.

2011-01-01

A method and a system for securing communication between at least a first and a second hardware components of a mobile device is described. The method includes establishing a first shared secret between the first and the second hardware components during an initialization of the mobile device and,

Does Grade Level Matter for the Assessment of Business Process Management Maturity?

Directory of Open Access Journals (Sweden)

Gabryelczyk Renata

2016-06-01

Full Text Available The purpose of this paper is to create and test the practical application of a business process management maturity assessment conducted at two different grade levels (management and professional level in an organization. The conceptual framework for this research includes creating a business process maturity indicator (BPMI for six process areas: strategy, documentation, optimization, implementation, execution, and controlling. The comparative analysis of the business process management maturity is performed using the BPMI on two cases: inside a single organization and the sector internally.

High pre-transplant soluble CD30 levels are predictive of the grade of rejection.

Science.gov (United States)

Rajakariar, Ravindra; Jivanji, Naina; Varagunam, Mira; Rafiq, Mohammad; Gupta, Arun; Sheaff, Michael; Sinnott, Paul; Yaqoob, M M

2005-08-01

In renal transplantation, serum soluble CD30 (sCD30) levels in graft recipients are associated with increased rejection and graft loss. We investigated whether pre-transplant sCD30 concentrations are predictive of the grade of rejection. Pre-transplant sera of 51 patients with tubulointerstitial rejection (TIR), 16 patients with vascular rejection (VR) and an age-matched control group of 41 patients with no rejection (NR) were analyzed for sCD30. The transplant biopsies were immunostained for C4d. The median sCD30 level was significantly elevated in the group with VR (248 Units (U)/mL, range: 92-802) when compared with TIR (103 U/mL, range: 36-309, psCD30 levels compared to NR. Based on C4d staining, a TH2 driven process, the median sCD30 levels were significantly raised in C4d+ patients compared with C4d- group (177 U/mL vs. 120 U/mL, psCD30 levels measured at time of transplantation correlate with the grade of rejection. High pre-transplant levels are associated with antibody-mediated rejection which carries a poorer prognosis. sCD30 could be another tool to assess immunological risk prior to transplantation and enable a patient centered approach to immunosuppression.

The Impact of Flight Hardware Scavenging on Space Logistics

Science.gov (United States)

Oeftering, Richard C.

2011-01-01

For a given fixed launch vehicle capacity the logistics payload delivered to the moon may be only roughly 20 percent of the payload delivered to the International Space Station (ISS). This is compounded by the much lower flight frequency to the moon and thus low availability of spares for maintenance. This implies that lunar hardware is much more scarce and more costly per kilogram than ISS and thus there is much more incentive to preserve hardware. The Constellation Lunar Surface System (LSS) program is considering ways of utilizing hardware scavenged from vehicles including the Altair lunar lander. In general, the hardware will have only had a matter of hours of operation yet there may be years of operational life remaining. By scavenging this hardware the program, in effect, is treating vehicle hardware as part of the payload. Flight hardware may provide logistics spares for system maintenance and reduce the overall logistics footprint. This hardware has a wide array of potential applications including expanding the power infrastructure, and exploiting in-situ resources. Scavenging can also be seen as a way of recovering the value of, literally, billions of dollars worth of hardware that would normally be discarded. Scavenging flight hardware adds operational complexity and steps must be taken to augment the crew s capability with robotics, capabilities embedded in flight hardware itself, and external processes. New embedded technologies are needed to make hardware more serviceable and scavengable. Process technologies are needed to extract hardware, evaluate hardware, reconfigure or repair hardware, and reintegrate it into new applications. This paper also illustrates how scavenging can be used to drive down the cost of the overall program by exploiting the intrinsic value of otherwise discarded flight hardware.

Hardware Commissioning of the LHC Quality Assurance, follow-up and storing of the test results

CERN Document Server

Barbero, E

2005-01-01

During the commissioning of the LHC technical systems [1] (the so-called Hardware Commissioning) a large number of test sequences and procedures will be applied to the different systems and components of the accelerator. All the information related to the coordination of the Hardware Commissioning will be structured and managed towards the final objective of integrating all the data produced in the Manufacturing and Test Folders (MTF) [2] at both equipment level (i.e. individual system tests) and commissioning level (i.e.Hardware Commissioning). The MTF for Hardware Commissioning will be mainly used to archive the results of the tests (i.e. status, parameters and waveforms) which will be used later as reference during the operation with beam. Also it is an indispensable tool for monitoring the progress of the different tests and ensuring the proper follow-up of the procedures described in the engineering specifications; in this way, the Quality Assurance process will be completed. This paper describes the spe...

Variation of Student Numerical and Figural Reasoning Approaches by Pattern Generalization Type, Strategy Use and Grade Level

Science.gov (United States)

El Mouhayar, Rabih; Jurdak, Murad

2016-01-01

This paper explored variation of student numerical and figural reasoning approaches across different pattern generalization types and across grade level. An instrument was designed for this purpose. The instrument was given to a sample of 1232 students from grades 4 to 11 from five schools in Lebanon. Analysis of data showed that the numerical…

ESCOLEX: a grade-level lexical database from European Portuguese elementary to middle school textbooks.

Science.gov (United States)

Soares, Ana Paula; Medeiros, José Carlos; Simões, Alberto; Machado, João; Costa, Ana; Iriarte, Álvaro; de Almeida, José João; Pinheiro, Ana P; Comesaña, Montserrat

2014-03-01

In this article, we introduce ESCOLEX, the first European Portuguese children's lexical database with grade-level-adjusted word frequency statistics. Computed from a 3.2-million-word corpus, ESCOLEX provides 48,381 word forms extracted from 171 elementary and middle school textbooks for 6- to 11-year-old children attending the first six grades in the Portuguese educational system. Like other children's grade-level databases (e.g., Carroll, Davies, & Richman, 1971; Corral, Ferrero, & Goikoetxea, Behavior Research Methods, 41, 1009-1017, 2009; Lété, Sprenger-Charolles, & Colé, Behavior Research Methods, Instruments, & Computers, 36, 156-166, 2004; Zeno, Ivens, Millard, Duvvuri, 1995), ESCOLEX provides four frequency indices for each grade: overall word frequency (F), index of dispersion across the selected textbooks (D), estimated frequency per million words (U), and standard frequency index (SFI). It also provides a new measure, contextual diversity (CD). In addition, the number of letters in the word and its part(s) of speech, number of syllables, syllable structure, and adult frequencies taken from P-PAL (a European Portuguese corpus-based lexical database; Soares, Comesaña, Iriarte, Almeida, Simões, Costa, …, Machado, 2010; Soares, Iriarte, Almeida, Simões, Costa, França, …, Comesaña, in press) are provided. ESCOLEX will be a useful tool both for researchers interested in language processing and development and for professionals in need of verbal materials adjusted to children's developmental stages. ESCOLEX can be downloaded along with this article or from http://p-pal.di.uminho.pt/about/databases .

The Relationship between Multiplication Fact Speed-Recall and Fluency and Higher Level Mathematics Learning with Eighth Grade Middle School Students

Science.gov (United States)

Curry, Steven James

2012-01-01

This quantitative study investigated relationships between higher level mathematics learning and multiplication fact fluency, multiplication fact speed-recall, and reading grade equivalency of eighth grade students in Algebra I and Pre-Algebra. Higher level mathematics learning was indicated by an average score of 80% or higher on first and second…

Optimizing memory-bound SYMV kernel on GPU hardware accelerators

KAUST Repository

Abdelfattah, Ahmad

2013-01-01

Hardware accelerators are becoming ubiquitous high performance scientific computing. They are capable of delivering an unprecedented level of concurrent execution contexts. High-level programming language extensions (e.g., CUDA), profiling tools (e.g., PAPI-CUDA, CUDA Profiler) are paramount to improve productivity, while effectively exploiting the underlying hardware. We present an optimized numerical kernel for computing the symmetric matrix-vector product on nVidia Fermi GPUs. Due to its inherent memory-bound nature, this kernel is very critical in the tridiagonalization of a symmetric dense matrix, which is a preprocessing step to calculate the eigenpairs. Using a novel design to address the irregular memory accesses by hiding latency and increasing bandwidth, our preliminary asymptotic results show 3.5x and 2.5x fold speedups over the similar CUBLAS 4.0 kernel, and 7-8% and 30% fold improvement over the Matrix Algebra on GPU and Multicore Architectures (MAGMA) library in single and double precision arithmetics, respectively. © 2013 Springer-Verlag.

Exploiting current-generation graphics hardware for synthetic-scene generation

Science.gov (United States)

Tanner, Michael A.; Keen, Wayne A.

2010-04-01

Increasing seeker frame rate and pixel count, as well as the demand for higher levels of scene fidelity, have driven scene generation software for hardware-in-the-loop (HWIL) and software-in-the-loop (SWIL) testing to higher levels of parallelization. Because modern PC graphics cards provide multiple computational cores (240 shader cores for a current NVIDIA Corporation GeForce and Quadro cards), implementation of phenomenology codes on graphics processing units (GPUs) offers significant potential for simultaneous enhancement of simulation frame rate and fidelity. To take advantage of this potential requires algorithm implementation that is structured to minimize data transfers between the central processing unit (CPU) and the GPU. In this paper, preliminary methodologies developed at the Kinetic Hardware In-The-Loop Simulator (KHILS) will be presented. Included in this paper will be various language tradeoffs between conventional shader programming, Compute Unified Device Architecture (CUDA) and Open Computing Language (OpenCL), including performance trades and possible pathways for future tool development.

Test Hardware Design for Flight-Like Operation of Advanced Stirling Convertors

Science.gov (United States)

Oriti, Salvatore M.

2012-01-01

NASA Glenn Research Center (GRC) has been supporting development of the Advanced Stirling Radioisotope Generator (ASRG) since 2006. A key element of the ASRG project is providing life, reliability, and performance testing of the Advanced Stirling Convertor (ASC). For this purpose, the Thermal Energy Conversion branch at GRC has been conducting extended operation of a multitude of free-piston Stirling convertors. The goal of this effort is to generate long-term performance data (tens of thousands of hours) simultaneously on multiple units to build a life and reliability database. The test hardware for operation of these convertors was designed to permit in-air investigative testing, such as performance mapping over a range of environmental conditions. With this, there was no requirement to accurately emulate the flight hardware. For the upcoming ASC-E3 units, the decision has been made to assemble the convertors into a flight-like configuration. This means the convertors will be arranged in the dual-opposed configuration in a housing that represents the fit, form, and thermal function of the ASRG. The goal of this effort is to enable system level tests that could not be performed with the traditional test hardware at GRC. This offers the opportunity to perform these system-level tests much earlier in the ASRG flight development, as they would normally not be performed until fabrication of the qualification unit. This paper discusses the requirements, process, and results of this flight-like hardware design activity.

Hardware Development Process for Human Research Facility Applications

Science.gov (United States)

Bauer, Liz

2000-01-01

The simple goal of the Human Research Facility (HRF) is to conduct human research experiments on the International Space Station (ISS) astronauts during long-duration missions. This is accomplished by providing integration and operation of the necessary hardware and software capabilities. A typical hardware development flow consists of five stages: functional inputs and requirements definition, market research, design life cycle through hardware delivery, crew training, and mission support. The purpose of this presentation is to guide the audience through the early hardware development process: requirement definition through selecting a development path. Specific HRF equipment is used to illustrate the hardware development paths. The source of hardware requirements is the science community and HRF program. The HRF Science Working Group, consisting of SCientists from various medical disciplines, defined a basic set of equipment with functional requirements. This established the performance requirements of the hardware. HRF program requirements focus on making the hardware safe and operational in a space environment. This includes structural, thermal, human factors, and material requirements. Science and HRF program requirements are defined in a hardware requirements document which includes verification methods. Once the hardware is fabricated, requirements are verified by inspection, test, analysis, or demonstration. All data is compiled and reviewed to certify the hardware for flight. Obviously, the basis for all hardware development activities is requirement definition. Full and complete requirement definition is ideal prior to initiating the hardware development. However, this is generally not the case, but the hardware team typically has functional inputs as a guide. The first step is for engineers to conduct market research based on the functional inputs provided by scientists. CommerCially available products are evaluated against the science requirements as

DIFFERENT LEVEL OF LEARNED-HELPLESSNESS AMONG HIGH SCHOOL STUDENTS WITH LOWER GRADE AND HIGHER GRADE IN SALATIGA INDONESIA

Directory of Open Access Journals (Sweden)

Berta Esti Ari Prasetya

2013-06-01

consisted of 190 of higher grade students and 127 of lower grade students. Mann-Whitney U was used to analyse the data, considering that the data were not normally distributed. This test result showed that there was a significant difference between high school students with higher grade and lower grade (the Mann-Whitney U coefficient of 10,644, with z value of -1795, p <0.05 (p = 0036, 1-tailed, with students of lower grade tend to be more prone to experience learned-helplessness. Additional results from their subjective perception on their achievement were also discussed and so were the implications of the study.

Correlation between the Physical Activity Level and Grade Point Averages of Faculty of Education Students

Science.gov (United States)

Imdat, Yarim

2014-01-01

The aim of the study is to find the correlation that exists between physical activity level and grade point averages of faculty of education students. The subjects consist of 359 (172 females and 187 males) under graduate students To determine the physical activity levels of the students in this research, International Physical Activity…

Can delayed time to referral to a tertiary level urologist with an abnormal PSA level affect subsequent Gleason grade in the opportunistically screened population?

LENUS (Irish Health Repository)

O'Kelly, Fardod

2013-09-01

There is growing conflict in the literature describing the effect of delayed treatment on outcomes following radical prostatectomy. There is also evidence to suggest progression of low-risk prostate cancer to develop higher grades and volumes of prostate cancer during active surveillance. It is unknown as to what affect a delay in referral of those men with abnormal screened-PSA levels have on subsequent Gleason grade.

Implementation of Hardware Accelerators on Zynq

DEFF Research Database (Denmark)

Toft, Jakob Kenn

of the ARM Cortex-9 processor featured on the Zynq SoC, with regard to execution time, power dissipation and energy consumption. The implementation of the hardware accelerators were successful. Use of the Monte Carlo processor resulted in a significant increase in performance. The Telco hardware accelerator......In the recent years it has become obvious that the performance of general purpose processors are having trouble meeting the requirements of high performance computing applications of today. This is partly due to the relatively high power consumption, compared to the performance, of general purpose...... processors, which has made hardware accelerators an essential part of several datacentres and the worlds fastest super-computers. In this work, two different hardware accelerators were implemented on a Xilinx Zynq SoC platform mounted on the ZedBoard platform. The two accelerators are based on two different...

Enteral nutrition increases interstitial brain glucose levels in poor-grade subarachnoid hemorrhage patients.

Science.gov (United States)

Kofler, Mario; Schiefecker, Alois J; Beer, Ronny; Gaasch, Maxime; Rhomberg, Paul; Stover, John; Pfausler, Bettina; Thomé, Claudius; Schmutzhard, Erich; Helbok, Raimund

2018-03-01

Low brain tissue glucose levels after acute brain injury are associated with poor outcome. Whether enteral nutrition (EN) reliably increases cerebral glucose levels remains unclear. In this retrospective analysis of prospectively collected observational data, we investigate the effect of EN on brain metabolism in 17 poor-grade subarachnoid hemorrhage (SAH) patients undergoing cerebral microdialysis (CMD) monitoring. CMD-values were obtained hourly. A nutritional intervention was defined as the clinical routine administration of EN without supplemental parenteral nutrition. Sixty-three interventions were analyzed. The mean amount of EN per intervention was 472.4 ± 10.7 kcal. CMD-glucose levels significantly increased from 1.59 ± 0.13 mmol/l at baseline to a maximum of 2.03 ± 0.2 mmol/l after 5 h (p  40) and the microdialysis probe location. The increase in CMD-glucose was directly dependent on the magnitude of increase of serum glucose levels (p = 0.007). No change in CMD-lactate, CMD-pyruvate, CMD-LPR, or CMD-glutamate (p > 0.4) was observed. Routine EN also increased CMD-glucose even if baseline concentrations were critically low ( < 0.7 mmol/l, neuroglucopenia; p < 0.001). These results may have treatment implications regarding glucose management of poor-grade aneurysmal SAH patients.

Computer hardware fault administration

Science.gov (United States)

Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

2010-09-14

Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

Nearest Neighborhood Grayscale Operator for Hardware-Efficient Microscale Texture Extraction

Directory of Open Access Journals (Sweden)

Andreas König

2007-01-01

Full Text Available First-stage feature computation and data rate reduction play a crucial role in an efficient visual information processing system. Hardware-based first stages usually win out where power consumption, dynamic range, and speed are the issue, but have severe limitations with regard to flexibility. In this paper, the local orientation coding (LOC, a nearest neighborhood grayscale operator, is investigated and enhanced for hardware implementation. The features produced by this operator are easy and fast to compute, compress the salient information contained in an image, and lend themselves naturally to various medium-to-high-level postprocessing methods such as texture segmentation, image decomposition, and feature tracking. An image sensor architecture based on the LOC has been elaborated, that combines high dynamic range (HDR image aquisition, feature computation, and inherent pixel-level ADC in the pixel cells. The mixed-signal design allows for simple readout as digital memory.

The FTK: A Hardware Track Finder for the ATLAS Trigger

CERN Document Server

Alison, J; Anderson, J; Andreani, A; Andreazza, A; Annovi, A; Antonelli, M; Atkinson, M; Auerbach, B; Baines, J; Barberio, E; Beccherle, R; Beretta, M; Biesuz, N V; Blair, R; Blazey, G; Bogdan, M; Boveia, A; Britzger, D; Bryant, P; Burghgrave, B; Calderini, G; Cavaliere, V; Cavasinni, V; Chakraborty, D; Chang, P; Cheng, Y; Cipriani, R; Citraro, S; Citterio, M; Crescioli, F; Dell'Orso, M; Donati, S; Dondero, P; Drake, G; Gadomski, S; Gatta, M; Gentsos, C; Giannetti, P; Giulini, M; Gkaitatzis, S; Howarth, J W; Iizawa, T; Kapliy, A; Kasten, M; Kim, Y K; Kimura, N; Klimkovich, T; Kordas, K; Korikawa, T; Krizka, K; Kubota, T; Lanza, A; Lasagni, F; Liberali, V; Li, H L; Love, J; Luciano, P; Luongo, C; Magalotti, D; Melachrinos, C; Meroni, C; Mitani, T; Negri, A; Neroutsos, P; Neubauer, M; Nikolaidis, S; Okumura, Y; Pandini, C; Penning, B; Petridou, C; Piendibene, M; Proudfoot, J; Rados, P; Roda, C; Rossi, E; Sakurai, Y; Sampsonidis, D; Sampsonidou, D; Schmitt, S; Schoening, A; Shochet, M; Shojaii, S; Soltveit, H; Sotiropoulou, C L; Stabile, A; Tang, F; Testa, M; Tompkins, L; Vercesi, V; Villa, M; Volpi, G; Webster, J; Wu, X; Yorita, K; Yurkewicz, A; Zeng, J C; Zhang, J

2014-01-01

The ATLAS experiment trigger system is designed to reduce the event rate, at the LHC design luminosity of 1034 cm-2 s-1, from the nominal bunch crossing rate of 40 MHz to less than 1 kHz for permanent storage. During Run 1, the LHC has performed exceptionally well, routinely exceeding the design luminosity. From 2015 the LHC is due to operate with higher still luminosities. This will place a significant load on the High Level Trigger system, both due to the need for more sophisticated algorithms to reject background, and from the larger data volumes that will need to be processed. The Fast TracKer is a hardware upgrade for Run 2, consisting of a custom electronics system that will operate at the full rate for Level-1 accepted events of 100 kHz and provide high quality tracks at the beginning of processing in the High Level Trigger. This will perform track reconstruction using hardware with massive parallelism using associative memories and FPGAs. The availability of the full tracking information will enable r...

Non-fuel bearing hardware melting technology

International Nuclear Information System (INIS)

Newman, D.F.

1993-01-01

Battelle has developed a portable hardware melter concept that would allow spent fuel rod consolidation operations at commercial nuclear power plants to provide significantly more storage space for other spent fuel assemblies in existing pool racks at lower cost. Using low pressure compaction, the non-fuel bearing hardware (NFBH) left over from the removal of spent fuel rods from the stainless steel end fittings and the Zircaloy guide tubes and grid spacers still occupies 1/3 to 2/5 of the volume of the consolidated fuel rod assemblies. Melting the non-fuel bearing hardware reduces its volume by a factor 4 from that achievable with low-pressure compaction. This paper describes: (1) the configuration and design features of Battelle's hardware melter system that permit its portability, (2) the system's throughput capacity, (3) the bases for capital and operating estimates, and (4) the status of NFBH melter demonstration to reduce technical risks for implementation of the concept. Since all NFBH handling and processing operations would be conducted at the reactor site, costs for shipping radioactive hardware to and from a stationary processing facility for volume reduction are avoided. Initial licensing, testing, and installation in the field would follow the successful pattern achieved with rod consolidation technology

A Practical Introduction to HardwareSoftware Codesign

CERN Document Server

Schaumont, Patrick R

2013-01-01

This textbook provides an introduction to embedded systems design, with emphasis on integration of custom hardware components with software. The key problem addressed in the book is the following: how can an embedded systems designer strike a balance between flexibility and efficiency? The book describes how combining hardware design with software design leads to a solution to this important computer engineering problem. The book covers four topics in hardware/software codesign: fundamentals, the design space of custom architectures, the hardware/software interface and application examples. The book comes with an associated design environment that helps the reader to perform experiments in hardware/software codesign. Each chapter also includes exercises and further reading suggestions. Improvements in this second edition include labs and examples using modern FPGA environments from Xilinx and Altera, which make the material applicable to a greater number of courses where these tools are already in use.  Mo...

Comparative Modal Analysis of Sieve Hardware Designs

Science.gov (United States)

Thompson, Nathaniel

2012-01-01

The CMTB Thwacker hardware operates as a testbed analogue for the Flight Thwacker and Sieve components of CHIMRA, a device on the Curiosity Rover. The sieve separates particles with a diameter smaller than 150 microns for delivery to onboard science instruments. The sieving behavior of the testbed hardware should be similar to the Flight hardware for the results to be meaningful. The elastodynamic behavior of both sieves was studied analytically using the Rayleigh Ritz method in conjunction with classical plate theory. Finite element models were used to determine the mode shapes of both designs, and comparisons between the natural frequencies and mode shapes were made. The analysis predicts that the performance of the CMTB Thwacker will closely resemble the performance of the Flight Thwacker within the expected steady state operating regime. Excitations of the testbed hardware that will mimic the flight hardware were recommended, as were those that will improve the efficiency of the sieving process.

A hardware fast tracker for the ATLAS trigger

Science.gov (United States)

Asbah, Nedaa

2016-09-01

The trigger system of the ATLAS experiment is designed to reduce the event rate from the LHC nominal bunch crossing at 40 MHz to about 1 kHz, at the design luminosity of 1034 cm-2 s-1. After a successful period of data taking from 2010 to early 2013, the LHC already started with much higher instantaneous luminosity. This will increase the load on High Level Trigger system, the second stage of the selection based on software algorithms. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals. The Fast TracKer (FTK) is part of the ATLAS trigger upgrade project. It is a hardware processor that will provide, at every Level-1 accepted event (100 kHz) and within 100 microseconds, full tracking information for tracks with momentum as low as 1 GeV. Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance. FTK exploits hardware technologies with massive parallelism, combining Associative Memory ASICs, FPGAs and high-speed communication links.

Commercial Grade Item (CGI) dedication - on complex electronic equipment

International Nuclear Information System (INIS)

Sohn, Kwang Young; Kim, Joong Han; Koo, In Soo; Lee, Sang Yong

2008-01-01

In future more complicated IT-based hardware and software is supposed to used in the safety-grade systems in nuclear power plants. Also there are the efforts to establish the criteria for CGI dedications in NRC and CEC dedication in other standard organizations. The highly complicated components, i.e. CEC should be dedication plans. Thus work to be done in later is to prepare the strategies, plans, guide and procedures that is more specific for CEC dedication

Physical Activity and Sedentary Behaviors of Urban Chinese Children: Grade Level Prevalence and Academic Burden Associations

Directory of Open Access Journals (Sweden)

Xihe Zhu

2017-01-01

Full Text Available The objectives of this study were (a to report grade level prevalence in physical activity and sedentary behaviors and (b to examine academic burden associations with these behaviors. School-aged children (n = 48,118 reported their physical activity, perception of physical activity sufficiency, factors for activity insufficiency, homework hours, and screen time in a typical week. Data were analyzed using general linear models and logistic regression models of Complex Samples. Prevalence results showed that children had lower physical activity and lower screen viewing time, but higher homework time during transition grades (6th, 9th, and 12th and high school years. Academic burden was cited as the primary reason for not having sufficient physical activity (76.6%. Compared to those citing academic burden, students who did not report academic burden were significantly more likely to meet physical activity guidelines (Odds Ratio (OR = 5.38, 95% CI = 4.74–6.11, but less likely to meet screen time guidelines (OR = 0.78, 95% CI = 0.72–0.84, controlling for body mass index, gender, and grade level. Additionally, children who reported academic burdens had significantly longer average daily homework time than those who did not (p<0.01. Policy makers should promote physical activity and help children find a balance between homework and physical activity time particularly among the educational transition grades.

Locating hardware faults in a parallel computer

Science.gov (United States)

Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

2010-04-13

Locating hardware faults in a parallel computer, including defining within a tree network of the parallel computer two or more sets of non-overlapping test levels of compute nodes of the network that together include all the data communications links of the network, each non-overlapping test level comprising two or more adjacent tiers of the tree; defining test cells within each non-overlapping test level, each test cell comprising a subtree of the tree including a subtree root compute node and all descendant compute nodes of the subtree root compute node within a non-overlapping test level; performing, separately on each set of non-overlapping test levels, an uplink test on all test cells in a set of non-overlapping test levels; and performing, separately from the uplink tests and separately on each set of non-overlapping test levels, a downlink test on all test cells in a set of non-overlapping test levels.

Change in the level of strength and endurance development of 5-6 grades pupils under cheerleading exercises influence

Directory of Open Access Journals (Sweden)

Tetyana Bala

2015-06-01

Full Text Available Purpose: determine the degree of change in the level of strength and endurance development of 5-6 grades pupils under cheerleading exercises influence. Material and Methods: theoretical analysis and generalization of scientific and methodical literature, pedagogical testing, pedagogical experiment and mathematical statistics methods. Results: parameters of strength and endurance development level are presented with their degree of change under cheerleading exercises influence for 5-6 grades pupils of secondary school. Conclusions: cheerleading exercises usage has positive influence on demonstrated strength and endurance degree of secondary school children by all investigated parameters.

The Prediction of Reading Levels between Second and Third Grade Limited English Proficient Students in a Bilingual Program

Science.gov (United States)

Moses, Britani Creel

2010-01-01

The purpose of this study was to predict the third grade English reading TAKS scores while considering the same students' native language, Spanish, reading level as assessed by a state-approved reading assessment, the Evaluacion del desarrollo de la lectura (EDL), from the end of the second grade year. In addition, this study was been designed to…

Synthetic hardware performance analysis in virtualized cloud environment for healthcare organization.

Science.gov (United States)

Tan, Chee-Heng; Teh, Ying-Wah

2013-08-01

The main obstacles in mass adoption of cloud computing for database operations in healthcare organization are the data security and privacy issues. In this paper, it is shown that IT services particularly in hardware performance evaluation in virtual machine can be accomplished effectively without IT personnel gaining access to actual data for diagnostic and remediation purposes. The proposed mechanisms utilized the hypothetical data from TPC-H benchmark, to achieve 2 objectives. First, the underlying hardware performance and consistency is monitored via a control system, which is constructed using TPC-H queries. Second, the mechanism to construct stress-testing scenario is envisaged in the host, using a single or combination of TPC-H queries, so that the resource threshold point can be verified, if the virtual machine is still capable of serving critical transactions at this constraining juncture. This threshold point uses server run queue size as input parameter, and it serves 2 purposes: It provides the boundary threshold to the control system, so that periodic learning of the synthetic data sets for performance evaluation does not reach the host's constraint level. Secondly, when the host undergoes hardware change, stress-testing scenarios are simulated in the host by loading up to this resource threshold level, for subsequent response time verification from real and critical transactions.

Transmission delays in hardware clock synchronization

Science.gov (United States)

Shin, Kang G.; Ramanathan, P.

1988-01-01

Various methods, both with software and hardware, have been proposed to synchronize a set of physical clocks in a system. Software methods are very flexible and economical but suffer an excessive time overhead, whereas hardware methods require no time overhead but are unable to handle transmission delays in clock signals. The effects of nonzero transmission delays in synchronization have been studied extensively in the communication area in the absence of malicious or Byzantine faults. The authors show that it is easy to incorporate the ideas from the communication area into the existing hardware clock synchronization algorithms to take into account the presence of both malicious faults and nonzero transmission delays.

Computer hardware description languages - A tutorial

Science.gov (United States)

Shiva, S. G.

1979-01-01

The paper introduces hardware description languages (HDL) as useful tools for hardware design and documentation. The capabilities and limitations of HDLs are discussed along with the guidelines needed in selecting an appropriate HDL. The directions for future work are provided and attention is given to the implementation of HDLs in microcomputers.

Support for NUMA hardware in HelenOS

OpenAIRE

Horký, Vojtěch

2011-01-01

The goal of this master thesis is to extend HelenOS operating system with the support for ccNUMA hardware. The text of the thesis contains a brief introduction to ccNUMA hardware, an overview of NUMA features and relevant features of HelenOS (memory management, scheduling, etc.). The thesis analyses various design decisions of the implementation of NUMA support -- introducing the hardware topology into the kernel data structures, propagating this information to user space, thread affinity to ...

The Stability of School Effectiveness Indices across Grade Levels and Subject Areas.

Science.gov (United States)

Mandeville, Garrett K.; Anderson, Lorin W.

1987-01-01

School effectiveness indices based on regressing achievement test scores onto earlier scores and a socioeconomic status measure were obtained for South Carolina students in grades one to four. Results were unstable across grades, and grade-to-grade correlations were more significant for mathematics achievement than for reading. (Author/GDC)

Fracture of fusion mass after hardware removal in patients with high sagittal imbalance.

Science.gov (United States)

Sedney, Cara L; Daffner, Scott D; Stefanko, Jared J; Abdelfattah, Hesham; Emery, Sanford E; France, John C

2016-04-01

As spinal fusions become more common and more complex, so do the sequelae of these procedures, some of which remain poorly understood. The authors report on a series of patients who underwent removal of hardware after CT-proven solid fusion, confirmed by intraoperative findings. These patients later developed a spontaneous fracture of the fusion mass that was not associated with trauma. A series of such patients has not previously been described in the literature. An unfunded, retrospective review of the surgical logs of 3 fellowship-trained spine surgeons yielded 7 patients who suffered a fracture of a fusion mass after hardware removal. Adult patients from the West Virginia University Department of Orthopaedics who underwent hardware removal in the setting of adjacent-segment disease (ASD), and subsequently experienced fracture of the fusion mass through the uninstrumented segment, were studied. The medical records and radiological studies of these patients were examined for patient demographics and comorbidities, initial indication for surgery, total number of surgeries, timeline of fracture occurrence, risk factors for fracture, as well as sagittal imbalance. All 7 patients underwent hardware removal in conjunction with an extension of fusion for ASD. All had CT-proven solid fusion of their previously fused segments, which was confirmed intraoperatively. All patients had previously undergone multiple operations for a variety of indications, 4 patients were smokers, and 3 patients had osteoporosis. Spontaneous fracture of the fusion mass occurred in all patients and was not due to trauma. These fractures occurred 4 months to 4 years after hardware removal. All patients had significant sagittal imbalance of 13-15 cm. The fracture level was L-5 in 6 of the 7 patients, which was the first uninstrumented level caudal to the newly placed hardware in all 6 of these patients. Six patients underwent surgery due to this fracture. The authors present a case series of 7

Reconfigurable Hardware for Compressing Hyperspectral Image Data

Science.gov (United States)

Aranki, Nazeeh; Namkung, Jeffrey; Villapando, Carlos; Kiely, Aaron; Klimesh, Matthew; Xie, Hua

2010-01-01

High-speed, low-power, reconfigurable electronic hardware has been developed to implement ICER-3D, an algorithm for compressing hyperspectral-image data. The algorithm and parts thereof have been the topics of several NASA Tech Briefs articles, including Context Modeler for Wavelet Compression of Hyperspectral Images (NPO-43239) and ICER-3D Hyperspectral Image Compression Software (NPO-43238), which appear elsewhere in this issue of NASA Tech Briefs. As described in more detail in those articles, the algorithm includes three main subalgorithms: one for computing wavelet transforms, one for context modeling, and one for entropy encoding. For the purpose of designing the hardware, these subalgorithms are treated as modules to be implemented efficiently in field-programmable gate arrays (FPGAs). The design takes advantage of industry- standard, commercially available FPGAs. The implementation targets the Xilinx Virtex II pro architecture, which has embedded PowerPC processor cores with flexible on-chip bus architecture. It incorporates an efficient parallel and pipelined architecture to compress the three-dimensional image data. The design provides for internal buffering to minimize intensive input/output operations while making efficient use of offchip memory. The design is scalable in that the subalgorithms are implemented as independent hardware modules that can be combined in parallel to increase throughput. The on-chip processor manages the overall operation of the compression system, including execution of the top-level control functions as well as scheduling, initiating, and monitoring processes. The design prototype has been demonstrated to be capable of compressing hyperspectral data at a rate of 4.5 megasamples per second at a conservative clock frequency of 50 MHz, with a potential for substantially greater throughput at a higher clock frequency. The power consumption of the prototype is less than 6.5 W. The reconfigurability (by means of reprogramming) of

Sterilization of space hardware.

Science.gov (United States)

Pflug, I. J.

1971-01-01

Discussion of various techniques of sterilization of space flight hardware using either destructive heating or the action of chemicals. Factors considered in the dry-heat destruction of microorganisms include the effects of microbial water content, temperature, the physicochemical properties of the microorganism and adjacent support, and nature of the surrounding gas atmosphere. Dry-heat destruction rates of microorganisms on the surface, between mated surface areas, or buried in the solid material of space vehicle hardware are reviewed, along with alternative dry-heat sterilization cycles, thermodynamic considerations, and considerations of final sterilization-process design. Discussed sterilization chemicals include ethylene oxide, formaldehyde, methyl bromide, dimethyl sulfoxide, peracetic acid, and beta-propiolactone.

Software for Managing Inventory of Flight Hardware

Science.gov (United States)

Salisbury, John; Savage, Scott; Thomas, Shirman

2003-01-01

The Flight Hardware Support Request System (FHSRS) is a computer program that relieves engineers at Marshall Space Flight Center (MSFC) of most of the non-engineering administrative burden of managing an inventory of flight hardware. The FHSRS can also be adapted to perform similar functions for other organizations. The FHSRS affords a combination of capabilities, including those formerly provided by three separate programs in purchasing, inventorying, and inspecting hardware. The FHSRS provides a Web-based interface with a server computer that supports a relational database of inventory; electronic routing of requests and approvals; and electronic documentation from initial request through implementation of quality criteria, acquisition, receipt, inspection, storage, and final issue of flight materials and components. The database lists both hardware acquired for current projects and residual hardware from previous projects. The increased visibility of residual flight components provided by the FHSRS has dramatically improved the re-utilization of materials in lieu of new procurements, resulting in a cost savings of over $1.7 million. The FHSRS includes subprograms for manipulating the data in the database, informing of the status of a request or an item of hardware, and searching the database on any physical or other technical characteristic of a component or material. The software structure forces normalization of the data to facilitate inquiries and searches for which users have entered mixed or inconsistent values.

Cognitive impairments in patients with low grade gliomas and high grade gliomas

Directory of Open Access Journals (Sweden)

Eliane C. Miotto

2011-08-01

Full Text Available OBJECTIVE: The relationship between brain tumors and cognitive deficits is well established in the literature. However, studies investigating the cognitive status in low and high-grade gliomas patients are scarce, particularly in patients with average or lower educational level. This study aimed at investigating the cognitive functioning in a sample of patients with low and high-grade gliomas before surgical intervention. METHOD: The low-grade (G1, n=19 and high-grade glioma (G2, n=8 patients underwent a detailed neuropsychological assessment of memory, executive functions, visuo-perceptive and visuo-spatial abilities, intellectual level and language. RESULTS: There was a significant impairment on verbal and visual episodic memory, executive functions including mental flexibility, nominal and categorical verbal fluency and speed of information processing in G2. G1 showed only specific deficits on verbal and visual memory recall, mental flexibility and processing speed. CONCLUSION: These findings demonstrated different levels of impairments in the executive and memory domains in patients with low and high grade gliomas.

Automation Hardware & Software for the STELLA Robotic Telescope

Science.gov (United States)

Weber, M.; Granzer, Th.; Strassmeier, K. G.

The STELLA telescope (a joint project of the AIP, Hamburger Sternwarte and the IAC) is to operate in fully robotic mode, with no human interaction necessary for regular operation. Thus, the hardware must be kept as simple as possible to avoid unnecessary failures, and the environmental conditions must be monitored accurately to protect the telescope in case of bad weather. All computers are standard PCs running Linux, and communication with specialized hardware is done via a RS232/RS485 bus system. The high level (java based) control software consists of independent modules to ease bug-tracking and to allow the system to be extended without changing existing modules. Any command cycle consists of three messages, the actual command sent from the central node to the operating device, an immediate acknowledge, and a final done message, both sent back from the receiving device to the central node. This reply-splitting allows a direct distinction between communication problems (no acknowledge message) and hardware problems (no or a delayed done message). To avoid bug-prone packing of all the sensor-analyzing software into a single package, each sensor-reading and interaction with other sensors is done within a self-contained thread. Weather-decision making is therefore totally decoupled from the core control software to avoid dead-locks in the core module.

LHCb: Hardware Data Injector

CERN Multimedia

Delord, V; Neufeld, N

2009-01-01

The LHCb High Level Trigger and Data Acquisition system selects about 2 kHz of events out of the 1 MHz of events, which have been selected previously by the first-level hardware trigger. The selected events are consolidated into files and then sent to permanent storage for subsequent analysis on the Grid. The goal of the upgrade of the LHCb readout is to lift the limitation to 1 MHz. This means speeding up the DAQ to 40 MHz. Such a DAQ system will certainly employ 10 Gigabit or technologies and might also need new networking protocols: a customized TCP or proprietary solutions. A test module is being presented, which integrates in the existing LHCb infrastructure. It is a 10-Gigabit traffic generator, flexible enough to generate LHCb's raw data packets using dummy data or simulated data. These data are seen as real data coming from sub-detectors by the DAQ. The implementation is based on an FPGA using 10 Gigabit Ethernet interface. This module is integrated in the experiment control system. The architecture, ...

Grade Inflation Marches On: Grade Increases from the 1990s to 2000s

Science.gov (United States)

Kostal, Jack W.; Kuncel, Nathan R.; Sackett, Paul R.

2016-01-01

Grade inflation threatens the integrity of college grades as indicators of academic achievement. In this study, we contribute to the literature on grade inflation by providing the first estimate of the size of grade increases at the student level between the mid-1990s and mid-2000s. By controlling for student characteristics and course-taking…

An elevated serum alkaline phosphatase level in hepatic metastases of grade 1 and 2 gastrointestinal neuroendocrine tumors is unusual and of prognostic value.

Science.gov (United States)

Andriantsoa, Maeva; Hoibian, Solene; Autret, Aurelie; Gilabert, Marine; Sarran, Anthony; Niccoli, Patricia; Raoul, Jean-Luc

2017-01-01

In our clinical practice we have observed that despite a high hepatic metastatic tumor burden, serum alkaline phosphatase (AP) levels are frequently normal in cases of metastatic neuroendocrine tumor (NET). We retrospectively reviewed the records of patients with grade 1 and 2 NETs with liver metastases but without bone metastases seen at our institution in 2013. In total, 49 patients were included (22 female), with a median age of 60 years (range: 28 to 84 years). The primary tumors were located in the duodenum/pancreas (n = 29), small bowel (n = 17) or colon/rectum (n = 3); 10 cases were grade 1 and 39 grade 2. Hepatic involvement was bulky, with more than 10 lesions in 23 patients and a tumor burden above 10% of the liver volume in 26 patients. Serum AP levels were elevated (≥ upper limit of normal (ULN)) in 16 patients. In multiparametric analysis, elevated serum AP levels were not associated with the primary site, grade, or number or volume of metastases. In multiparametric analysis, progression-free survival was only correlated with grade (p = 0.010) and AP level (p = 0.017). Serum AP levels are frequently normal in liver metastases from NET, even in the event of a major tumor burden, and the serum AP level can be of prognostic value.

Turkish students' perceptions of their biology learning environments: the effects of gender and grade level

NARCIS (Netherlands)

Telli, S.; Brok, den P.J.; Tekkaya, C.; Cakiroglu, J.

2009-01-01

This study investigates the effects of gender and grade level on Turkish secondary school students’ perceptions of their biology learning environment. A total of 1474 high school students completed the What is Happening in This Classroom (WIHIC) questionnaire. The WIHIC maps several important

Improvement of hardware basic testing : Identification and development of a scripted automation tool that will support hardware basic testing

OpenAIRE

Rask, Ulf; Mannestig, Pontus

2002-01-01

In the ever-increasing development pace, circuits and hardware are no exception. Hardware designs grow and circuits gets more complex at the same time as the market pressure lowers the expected time-to-market. In this rush, verification methods often lag behind. Hardware manufacturers must be aware of the importance of total verification if they want to avoid quality flaws and broken deadlines which in the long run will lead to delayed time-to-market, bad publicity and a decreasing market sha...

The Role of the A* Grade at a Level as a Predictor of University Performance in the United Kingdom

Science.gov (United States)

Vidal Rodeiro, Carmen; Zanini, Nadir

2015-01-01

In summer 2010, the A* grade at A level was awarded for the first time. This grade was introduced to help higher education institutions to differentiate between the highest achieving candidates and to promote and reward greater stretch and challenge. Exploring data from the Higher Education Statistics Service and making use of multilevel…

Tablet Computer Literacy Levels of the Physical Education and Sports Department Students

Directory of Open Access Journals (Sweden)

Gulten HERGUNER

2016-04-01

Full Text Available Education systems are being affected in parallel by newly emerging hardware and new developments    occurring in technology daily. Tablet usage especially is becoming ubiquitous in the teaching‐learning processes in recent years. Therefore, using the tablets effectively, managing them and having a high level of tablet literacy play an important role within the education system. This study aimed at determining the tablet literacy levels of students in the Physical Education and Sports Teaching department at Sakarya University in Turkey, and examining this data with regard to various variables. Some 276 students participated in the study. Findings of the study suggest that the sample has a high tablet literacy level. While no significant difference was found in the tablet literacy  by gender, the students in the 2nd grade are noted to have higher levels of tablet literacy compared to the students in 3rd and 4th grades and tablet owners are more tablet literate when compared to non‐owners. A significant but low level correlation was found between the tablet usage time and tablet literacy.  

Physical activity levels and motor skills of 5 th to 7 th grade students ...

African Journals Online (AJOL)

The physical activity (PA) and motor skill levels (MS) (flexibility, balance, speed, sit-up, hand grip strength, standing long jump) were determined for 5th to 7th grade students from central schools in Nigde Province, Turkey according to age and gender and to investigate the relationships. PAL was determined by means of ...

New Directions for Hardware-assisted Trusted Computing Policies (Position Paper)

Science.gov (United States)

Bratus, Sergey; Locasto, Michael E.; Ramaswamy, Ashwin; Smith, Sean W.

The basic technological building blocks of the TCG architecture seem to be stabilizing. As a result, we believe that the focus of the Trusted Computing (TC) discipline must naturally shift from the design and implementation of the hardware root of trust (and the subsequent trust chain) to the higher-level application policies. Such policies must build on these primitives to express new sets of security goals. We highlight the relationship between enforcing these types of policies and debugging, since both activities establish the link between expected and actual application behavior. We argue that this new class of policies better fits developers' mental models of expected application behaviors, and we suggest a hardware design direction for enabling the efficient interpretation of such policies.

A Hardware Fast Tracker for the ATLAS trigger

International Nuclear Information System (INIS)

Asbah, N.

2016-01-01

The trigger system of the ATLAS experiment is designed to reduce the event rate from the LHC nominal bunch crossing at 40 MHz to about 1 kHz, at the design luminosity of 10 34 cm -2 · s -1 . After a successful period of data taking from 2010 to early 2013, the LHC already started with much higher instantaneous luminosity. This will increase the load on High Level Trigger system, the second stage of the selection based on software algorithms. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals. The Fast TracKer (FTK) is part of the ATLAS trigger upgrade project. It is a hardware processor that will provide, at every Level-1 accepted event (100 kHz) and within 100 μs, full tracking information for tracks with momentum as low as 1 GeV. Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance. FTK exploits hardware technologies with massive parallelism, combining Associative Memory ASICs, FPGAs and high-speed communication links.

A hardware overview of the RHIC LLRF platform

International Nuclear Information System (INIS)

Hayes, T.; Smith, K.S.

2011-01-01

The RHIC Low Level RF (LLRF) platform is a flexible, modular system designed around a carrier board with six XMC daughter sites. The carrier board features a Xilinx FPGA with an embedded, hard core Power PC that is remotely reconfigurable. It serves as a front end computer (FEC) that interfaces with the RHIC control system. The carrier provides high speed serial data paths to each daughter site and between daughter sites as well as four generic external fiber optic links. It also distributes low noise clocks and serial data links to all daughter sites and monitors temperature, voltage and current. To date, two XMC cards have been designed: a four channel high speed ADC and a four channel high speed DAC. The new LLRF hardware was used to replace the old RHIC LLRF system for the 2009 run. For the 2010 run, the RHIC RF system operation was dramatically changed with the introduction of accelerating both beams in a new, common cavity instead of each ring having independent cavities. The flexibility of the new system was beneficial in allowing the low level system to be adapted to support this new configuration. This hardware was also used in 2009 to provide LLRF for the newly commissioned Electron Beam Ion Source.

Flight Hardware Packaging Design for Stringent EMC Radiated Emission Requirements

Science.gov (United States)

Lortz, Charlene L.; Huang, Chi-Chien N.; Ravich, Joshua A.; Steiner, Carl N.

2013-01-01

This packaging design approach can help heritage hardware meet a flight project's stringent EMC radiated emissions requirement. The approach requires only minor modifications to a hardware's chassis and mainly concentrates on its connector interfaces. The solution is to raise the surface area where the connector is mounted by a few millimeters using a pedestal, and then wrapping with conductive tape from the cable backshell down to the surface-mounted connector. This design approach has been applied to JPL flight project subsystems. The EMC radiated emissions requirements for flight projects can vary from benign to mission critical. If the project's EMC requirements are stringent, the best approach to meet EMC requirements would be to design an EMC control program for the project early on and implement EMC design techniques starting with the circuit board layout. This is the ideal scenario for hardware that is built from scratch. Implementation of EMC radiated emissions mitigation techniques can mature as the design progresses, with minimal impact to the design cycle. The real challenge exists for hardware that is planned to be flown following a built-to-print approach, in which heritage hardware from a past project with a different set of requirements is expected to perform satisfactorily for a new project. With acceptance of heritage, the design would already be established (circuit board layout and components have already been pre-determined), and hence any radiated emissions mitigation techniques would only be applicable at the packaging level. The key is to take a heritage design with its known radiated emissions spectrum and repackage, or modify its chassis design so that it would have a better chance of meeting the new project s radiated emissions requirements.

Static Scheduling of Periodic Hardware Tasks with Precedence and Deadline Constraints on Reconfigurable Hardware Devices

Directory of Open Access Journals (Sweden)

Ikbel Belaid

2011-01-01

Full Text Available Task graph scheduling for reconfigurable hardware devices can be defined as finding a schedule for a set of periodic tasks with precedence, dependence, and deadline constraints as well as their optimal allocations on the available heterogeneous hardware resources. This paper proposes a new methodology comprising three main stages. Using these three main stages, dynamic partial reconfiguration and mixed integer programming, pipelined scheduling and efficient placement are achieved and enable parallel computing of the task graph on the reconfigurable devices by optimizing placement/scheduling quality. Experiments on an application of heterogeneous hardware tasks demonstrate an improvement of resource utilization of 12.45% of the available reconfigurable resources corresponding to a resource gain of 17.3% compared to a static design. The configuration overhead is reduced to 2% of the total running time. Due to pipelined scheduling, the task graph spanning is minimized by 4% compared to sequential execution of the graph.

Anthropometric and Athletic Performance Combine Test Results Among Positions Within Grade Levels of High School-Aged American Football Players.

Science.gov (United States)

Leutzinger, Todd J; Gillen, Zachary M; Miramonti, Amelia M; McKay, Brianna D; Mendez, Alegra I; Cramer, Joel T

2018-05-01

Leutzinger, TJ, Gillen, ZM, Miramonti, AM, McKay, BD, Mendez, AI, and Cramer, JT. Anthropometric and athletic performance combine test results among positions within grade levels of high school-aged American football players. J Strength Cond Res 32(5): 1288-1296, 2018-The purpose of this study was to investigate differences among player positions at 3 grade levels in elite, collegiate-prospective American football players. Participants' data (n = 7,160) were analyzed for this study (mean height [Ht] ± SD = 178 ± 7 cm, mass [Bm] = 86 ± 19 kg). Data were obtained from 12 different high school American football recruiting combines hosted by Zybek Sports (Boulder, Colorado). Eight 2-way (9 × 3) mixed factorial analysis of variances {position (defensive back [DB], defensive end, defensive lineman, linebacker, offensive lineman [OL], quarterback, running back, tight end, and wide receiver [WR]) × grade (freshmen, sophomores, and juniors)} were used to test for differences among the mean test scores for each combine measure (Ht, Bm, 40-yard [40 yd] dash, proagility [PA] drill, L-cone [LC] drill, vertical jump [VJ], and broad jump [BJ]). There were position-related differences (p ≤ 0.05) for Ht, 40 yd dash, and BJ, within each grade level and for Bm, PA, LC, and VJ independent of grade level. Generally, the results showed that OL were the tallest, weighed the most, and exhibited the lowest performance scores among positions. Running backs were the shortest, whereas DBs and WRs weighed the least and exhibited the highest performance scores among positions. These results demonstrate the value of classifying high school-aged American football players according to their specific position rather than categorical groupings such as "line" vs. "skill" vs. "big skill" when evaluating anthropometric and athletic performance combine test results.

An elevated serum alkaline phosphatase level in hepatic metastases of grade 1 and 2 gastrointestinal neuroendocrine tumors is unusual and of prognostic value.

Directory of Open Access Journals (Sweden)

Maeva Andriantsoa

Full Text Available In our clinical practice we have observed that despite a high hepatic metastatic tumor burden, serum alkaline phosphatase (AP levels are frequently normal in cases of metastatic neuroendocrine tumor (NET.We retrospectively reviewed the records of patients with grade 1 and 2 NETs with liver metastases but without bone metastases seen at our institution in 2013. In total, 49 patients were included (22 female, with a median age of 60 years (range: 28 to 84 years. The primary tumors were located in the duodenum/pancreas (n = 29, small bowel (n = 17 or colon/rectum (n = 3; 10 cases were grade 1 and 39 grade 2. Hepatic involvement was bulky, with more than 10 lesions in 23 patients and a tumor burden above 10% of the liver volume in 26 patients.Serum AP levels were elevated (≥ upper limit of normal (ULN in 16 patients. In multiparametric analysis, elevated serum AP levels were not associated with the primary site, grade, or number or volume of metastases. In multiparametric analysis, progression-free survival was only correlated with grade (p = 0.010 and AP level (p = 0.017.Serum AP levels are frequently normal in liver metastases from NET, even in the event of a major tumor burden, and the serum AP level can be of prognostic value.

Greater-than-Class C low-level waste characterization. Appendix G: Evaluation of potential for greater-than-Class C classification of irradiated hardware generated by utility-operated reactors

International Nuclear Information System (INIS)

Cline, J.E.

1991-08-01

This study compiles and evaluates data from many sources to expand a base of data from which to estimate the activity concentrations and volumes of greater-than-Class C low-level waste that the Department of Energy will receive from the commercial power industry. Sources of these data include measurements of irradiated hardware made by or for the utilities that was classified for disposal in commercial burial sites, measurements of neutron flux in the appropriate regions of the reactor pressure vessel, analyses of elemental constituents of the particular structural material used for the components, and the activation analysis calculations done for hardware. Evaluations include results and assumptions in the activation analyses. Sections of this report and the appendices present interpretation of data and the classification definitions and requirements

Test Hardware Design for Flightlike Operation of Advanced Stirling Convertors (ASC-E3)

Science.gov (United States)

Oriti, Salvatore M.

2012-01-01

NASA Glenn Research Center (GRC) has been supporting development of the Advanced Stirling Radioisotope Generator (ASRG) since 2006. A key element of the ASRG project is providing life, reliability, and performance testing of the Advanced Stirling Convertor (ASC). For this purpose, the Thermal Energy Conversion branch at GRC has been conducting extended operation of a multitude of free-piston Stirling convertors. The goal of this effort is to generate long-term performance data (tens of thousands of hours) simultaneously on multiple units to build a life and reliability database. The test hardware for operation of these convertors was designed to permit in-air investigative testing, such as performance mapping over a range of environmental conditions. With this, there was no requirement to accurately emulate the flight hardware. For the upcoming ASC-E3 units, the decision has been made to assemble the convertors into a flight-like configuration. This means the convertors will be arranged in the dual-opposed configuration in a housing that represents the fit, form, and thermal function of the ASRG. The goal of this effort is to enable system level tests that could not be performed with the traditional test hardware at GRC. This offers the opportunity to perform these system-level tests much earlier in the ASRG flight development, as they would normally not be performed until fabrication of the qualification unit. This paper discusses the requirements, process, and results of this flight-like hardware design activity.

COMPUTER HARDWARE MARKING

CERN Multimedia

Groupe de protection des biens

2000-01-01

As part of the campaign to protect CERN property and for insurance reasons, all computer hardware belonging to the Organization must be marked with the words 'PROPRIETE CERN'.IT Division has recently introduced a new marking system that is both economical and easy to use. From now on all desktop hardware (PCs, Macintoshes, printers) issued by IT Division with a value equal to or exceeding 500 CHF will be marked using this new system.For equipment that is already installed but not yet marked, including UNIX workstations and X terminals, IT Division's Desktop Support Service offers the following services free of charge:Equipment-marking wherever the Service is called out to perform other work (please submit all work requests to the IT Helpdesk on 78888 or helpdesk@cern.ch; for unavoidable operational reasons, the Desktop Support Service will only respond to marking requests when these coincide with requests for other work such as repairs, system upgrades, etc.);Training of personnel designated by Division Leade...

Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm

Directory of Open Access Journals (Sweden)

O. Ahmed

2013-01-01

Full Text Available Packet classification is a ubiquitous and key building block for many critical network devices. However, it remains as one of the main bottlenecks faced when designing fast network devices. In this paper, we propose a novel Group Based Search packet classification Algorithm (GBSA that is scalable, fast, and efficient. GBSA consumes an average of 0.4 megabytes of memory for a 10 k rule set. The worst-case classification time per packet is 2 microseconds, and the preprocessing speed is 3 M rules/second based on an Xeon processor operating at 3.4 GHz. When compared with other state-of-the-art classification techniques, the results showed that GBSA outperforms the competition with respect to speed, memory usage, and processing time. Moreover, GBSA is amenable to implementation in hardware. Three different hardware implementations are also presented in this paper including an Application Specific Instruction Set Processor (ASIP implementation and two pure Register-Transfer Level (RTL implementations based on Impulse-C and Handel-C flows, respectively. Speedups achieved with these hardware accelerators ranged from 9x to 18x compared with a pure software implementation running on an Xeon processor.

GOSH! A roadmap for open-source science hardware

CERN Multimedia

Stefania Pandolfi

2016-01-01

The goal of the Gathering for Open Science Hardware (GOSH! 2016), held from 2 to 5 March 2016 at IdeaSquare, was to lay the foundations of the open-source hardware for science movement.   The participants in the GOSH! 2016 meeting gathered in IdeaSquare. (Image: GOSH Community) “Despite advances in technology, many scientific innovations are held back because of a lack of affordable and customisable hardware,” says François Grey, a professor at the University of Geneva and coordinator of Citizen Cyberlab – a partnership between CERN, the UN Institute for Training and Research and the University of Geneva – which co-organised the GOSH! 2016 workshop. “This scarcity of accessible science hardware is particularly obstructive for citizen science groups and humanitarian organisations that don’t have the same economic means as a well-funded institution.” Instead, open sourcing science hardware co...

Is a 4-bit synaptic weight resolution enough? - constraints on enabling spike-timing dependent plasticity in neuromorphic hardware.

Science.gov (United States)

Pfeil, Thomas; Potjans, Tobias C; Schrader, Sven; Potjans, Wiebke; Schemmel, Johannes; Diesmann, Markus; Meier, Karlheinz

2012-01-01

Large-scale neuromorphic hardware systems typically bear the trade-off between detail level and required chip resources. Especially when implementing spike-timing dependent plasticity, reduction in resources leads to limitations as compared to floating point precision. By design, a natural modification that saves resources would be reducing synaptic weight resolution. In this study, we give an estimate for the impact of synaptic weight discretization on different levels, ranging from random walks of individual weights to computer simulations of spiking neural networks. The FACETS wafer-scale hardware system offers a 4-bit resolution of synaptic weights, which is shown to be sufficient within the scope of our network benchmark. Our findings indicate that increasing the resolution may not even be useful in light of further restrictions of customized mixed-signal synapses. In addition, variations due to production imperfections are investigated and shown to be uncritical in the context of the presented study. Our results represent a general framework for setting up and configuring hardware-constrained synapses. We suggest how weight discretization could be considered for other backends dedicated to large-scale simulations. Thus, our proposition of a good hardware verification practice may rise synergy effects between hardware developers and neuroscientists.

Hardware Accelerated Simulated Radiography

International Nuclear Information System (INIS)

Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

2005-01-01

We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32 bit floating point texture capabilities to obtain validated solutions to the radiative transport equation for X-rays. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedra that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester. We show that the hardware accelerated solution is faster than the current technique used by scientists

FPGA-Based Flexible Hardware Architecture for Image Interest Point Detection

Directory of Open Access Journals (Sweden)

Ana Hernandez-Lopez

2015-07-01

Full Text Available An important challenge in computer vision is the implementation of fast and accurate feature detectors, as they are the basis for high-level image processing analysis and understanding. However, image feature detectors cannot be easily applied in embedded scenarios, mainly due to the fact that they are time consuming and require a significant amount of processing power. Although some feature detectors have been implemented in hardware, most implementations target a single detector under very specific constraints. This paper proposes a flexible hardware implementation approach for computing interest point extraction from grey-level images based on two different detectors, Harris and SUSAN, suitable for robotic applications. The design is based on parallel and configurable processing elements for window operators and a buffering strategy to support a coarse-grain pipeline scheme for operator sequencing. When targeted to a Virtex-6 FPGA, a throughput of 49.45 Mpixel/s (processing rate of 161 frames per second of VGA image resolution is achieved at a clock frequency of 50 MHz.

Fast Sparse Level Sets on Graphics Hardware

NARCIS (Netherlands)

Jalba, Andrei C.; Laan, Wladimir J. van der; Roerdink, Jos B.T.M.

The level-set method is one of the most popular techniques for capturing and tracking deformable interfaces. Although level sets have demonstrated great potential in visualization and computer graphics applications, such as surface editing and physically based modeling, their use for interactive

The effects of graded levels of calorie restriction: VI. Impact of short-term graded calorie restriction on transcriptomic responses of the hypothalamic hunger and circadian signaling pathways.

Science.gov (United States)

Derous, Davina; Mitchell, Sharon E; Green, Cara L; Chen, Luonan; Han, Jing-Dong J; Wang, Yingchun; Promislow, Daniel E L; Lusseau, David; Speakman, John R; Douglas, Alex

2016-04-01

Food intake and circadian rhythms are regulated by hypothalamic neuropeptides and circulating hormones, which could mediate the anti-ageing effect of calorie restriction (CR). We tested whether these two signaling pathways mediate CR by quantifying hypothalamic transcripts of male C57BL/6 mice exposed to graded levels of CR (10 % to 40 %) for 3 months. We found that the graded CR manipulation resulted in upregulation of core circadian rhythm genes, which correlated negatively with circulating levels of leptin, insulin-like growth factor 1 (IGF-1), insulin, and tumor necrosis factor alpha (TNF-α). In addition, key components in the hunger signaling pathway were expressed in a manner reflecting elevated hunger at greater levels of restriction, and which also correlated negatively with circulating levels of insulin, TNF-α, leptin and IGF-1. Lastly, phenotypes, such as food anticipatory activity and body temperature, were associated with expression levels of both hunger genes and core clock genes. Our results suggest modulation of the hunger and circadian signaling pathways in response to altered levels of circulating hormones, that are themselves downstream of morphological changes resulting from CR treatment, may be important elements in the response to CR, driving some of the key phenotypic outcomes.

Teachers' Motivating Methods to Support Thai Ninth Grade Students' Levels of Motivation and Learning in Mathematics Classrooms

Science.gov (United States)

Nenthien, Sansanee; Loima, Jyrki

2016-01-01

The aims of this qualitative research were to investigate the level of motivation and learning of ninth grade students in mathematics classrooms in Thailand and to reveal how the teachers supported students' levels of motivation and learning. The participants were 333 students and 12 teachers in 12 mathematics classrooms from four regions of…

Population-level associations between preschool vulnerability and grade-four basic skills.

Directory of Open Access Journals (Sweden)

Amedeo D'Angiulli

2009-11-01

Full Text Available This is a predictive validity study examining the extent to which developmental vulnerability at kindergarten entry (as measured by the Early Development Instrument, EDI is associated with children's basic skills in 4th grade (as measured by the Foundation Skills Assessment, FSA.Relative risk analysis was performed on a large database linking individual-level EDI ratings to the scores the same children obtained on a provincial assessment of academic skills (FSA--Foundation Skills Assessment four years later. We found that early vulnerability in kindergarten is associated with the basic skills that underlie populations of children's academic achievement in reading, writing and math, indicating that the Early Development Instrument permits to predict achievement-related skills four years in advance.The EDI can be used to predict children's educational trends at the population level and can help select early prevention and intervention programs targeting pre-school populations at minimum cost.

Hardware device to physical structure binding and authentication

Science.gov (United States)

Hamlet, Jason R.; Stein, David J.; Bauer, Todd M.

2013-08-20

Detection and deterrence of device tampering and subversion may be achieved by including a cryptographic fingerprint unit within a hardware device for authenticating a binding of the hardware device and a physical structure. The cryptographic fingerprint unit includes an internal physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generate an internal PUF value. Binding logic is coupled to receive the internal PUF value, as well as an external PUF value associated with the physical structure, and generates a binding PUF value, which represents the binding of the hardware device and the physical structure. The cryptographic fingerprint unit also includes a cryptographic unit that uses the binding PUF value to allow a challenger to authenticate the binding.

Raspberry Pi hardware projects 1

CERN Document Server

Robinson, Andrew

2013-01-01

Learn how to take full advantage of all of Raspberry Pi's amazing features and functions-and have a blast doing it! Congratulations on becoming a proud owner of a Raspberry Pi, the credit-card-sized computer! If you're ready to dive in and start finding out what this amazing little gizmo is really capable of, this ebook is for you. Taken from the forthcoming Raspberry Pi Projects, Raspberry Pi Hardware Projects 1 contains three cool hardware projects that let you have fun with the Raspberry Pi while developing your Raspberry Pi skills. The authors - PiFace inventor, Andrew Robinson and Rasp

A Hardware Abstraction Layer in Java

DEFF Research Database (Denmark)

Schoeberl, Martin; Korsholm, Stephan; Kalibera, Tomas

2011-01-01

Embedded systems use specialized hardware devices to interact with their environment, and since they have to be dependable, it is attractive to use a modern, type-safe programming language like Java to develop programs for them. Standard Java, as a platform-independent language, delegates access...... to devices, direct memory access, and interrupt handling to some underlying operating system or kernel, but in the embedded systems domain resources are scarce and a Java Virtual Machine (JVM) without an underlying middleware is an attractive architecture. The contribution of this article is a proposal...... for Java packages with hardware objects and interrupt handlers that interface to such a JVM. We provide implementations of the proposal directly in hardware, as extensions of standard interpreters, and finally with an operating system middleware. The latter solution is mainly seen as a migration path...

No differences in grades or level of satisfaction in a flipped classroom for neuroanatomy.

Science.gov (United States)

Whillier, Stephney; Lystad, Reidar Petter

2015-10-01

The intensive nature of a 5- or 6-week teaching block poses unique problems for adequate delivery of content. This study was designed to compare the delivery of a unit of undergraduate neuroanatomy in a short summer school period, as a traditionally taught unit, with a rendition given in the form of the "Flipped Classroom." The aim was to evaluate the effectiveness of the flipped classroom in the intensive mode classroom. The flipped classroom encompassed the same learning outcomes, but students were responsible for covering the content at home in preparation for tutorials that applied their acquired knowledge to higher levels of thinking. The main outcome measures were the final course grades and the level of satisfaction with the course. There were no significant differences between the 2 cohorts in final grades (p = .259), self-rated knowledge (p = .182), or overall satisfaction with the course (p = .892). This particular design of the flipped classroom did not add value to the intensive mode experience. It may be that this mode of delivery is ill suited to intensive classes for subjects that carry a lot of content. The use of the flipped classroom requires further research to fully evaluate its value.

Hardware-Accelerated Simulated Radiography

International Nuclear Information System (INIS)

Laney, D; Callahan, S; Max, N; Silva, C; Langer, S.; Frank, R

2005-01-01

We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32-bit floating point texture capabilities to obtain solutions to the radiative transport equation for X-rays. The hardware accelerated solutions are accurate enough to enable scientists to explore the experimental design space with greater efficiency than the methods currently in use. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedral meshes that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester

The results of STEM education methods in physics at the 11th grade level: Light and visual equipment lesson

Science.gov (United States)

Tungsombatsanti, A.; Ponkham, K.; Somtoa, T.

2018-01-01

This research aimed to: 1) To evaluate the efficiency of the process and the efficiency of the results (E1 / E2) of the innovative instructional lesson plan in the form of the STEM Education method in the field of physics of secondary students at the 10th grade level in physics class to determine the efficiency of the STEM based on criteria of the 70/70 standard level. 2) To study students' critical thinking skills of secondary students at the 11th grade level, and assessing skill in criteria 80 percentage 3) To compare learning achievements between students' pre-post testing after taught in STEM Education 4) To evaluate Student' Satisfaction after using STEM Education teaching by using mean compare to 5 points Likert Scale. The participant used were 40 students from grade 11 at Borabu School, Borabu District, Mahasarakham Province, semester 2, Academic year 2016. Tools used in this study consist of: 1) STEM Education plan about the force and laws of motion for grade 11 students of 1 schemes with total of 15 hours, 2) The test of critical think skills with essay type in amount of 30 items, 3) achievement test on Light and visual equipment with multiple-choice of 4 options of 30 items, 4) satisfaction learning with 5 Rating Scale of 16 items. The statistics used in data analysis were percentage, mean, standard deviation, and t-test (Dependent). The results showed that 1) The results of these findings revealed that the efficiency of the STEM based on criteria indicate that are higher than the standard level of the 70/70 at 71.51/75 2) Student has critical thinking scores that are higher than criteria 80 percentage as amount is 26 people. 3) Statistically significant of students' learning achievements to their later outcomes were differentiated between pretest and posttest at the .05 level, evidently. 4) The student' level of satisfaction toward the learning by using STEM Education plan was at a good level (X ¯ = 4.33, S.D = 0.64).

Hardware descriptions of the I and C systems for NPP

International Nuclear Information System (INIS)

Lee, Cheol Kwon; Oh, In Suk; Park, Joo Hyun; Kim, Dong Hoon; Han, Jae Bok; Shin, Jae Whal; Kim, Young Bak

2003-09-01

The hardware specifications for I and C Systems of SNPP(Standard Nuclear Power Plant) are reviewed in order to acquire the hardware requirement and specification of KNICS (Korea Nuclear Instrumentation and Control System). In the study, we investigated hardware requirements, hardware configuration, hardware specifications, man-machine hardware requirements, interface requirements with the other system, and data communication requirements that are applicable to SNP. We reviewed those things of control systems, protection systems, monitoring systems, information systems, and process instrumentation systems. Through the study, we described the requirements and specifications of digital systems focusing on a microprocessor and a communication interface, and repeated it for analog systems focusing on the manufacturing companies. It is expected that the experience acquired from this research will provide vital input for the development of the KNICS

Is a 4-bit synaptic weight resolution enough? - Constraints on enabling spike-timing dependent plasticity in neuromorphic hardware

Directory of Open Access Journals (Sweden)

Thomas ePfeil

2012-07-01

Full Text Available Large-scale neuromorphic hardware systems typically bear the trade-off be-tween detail level and required chip resources. Especially when implementingspike-timing-dependent plasticity, reduction in resources leads to limitations ascompared to floating point precision. By design, a natural modification that savesresources would be reducing synaptic weight resolution. In this study, we give anestimate for the impact of synaptic weight discretization on different levels, rangingfrom random walks of individual weights to computer simulations of spiking neuralnetworks. The FACETS wafer-scale hardware system offers a 4-bit resolution ofsynaptic weights, which is shown to be sufficient within the scope of our networkbenchmark. Our findings indicate that increasing the resolution may not even beuseful in light of further restrictions of customized mixed-signal synapses. In ad-dition, variations due to production imperfections are investigated and shown tobe uncritical in the context of the presented study. Our results represent a generalframework for setting up and configuring hardware-constrained synapses. We sug-gest how weight discretization could be considered for other backends dedicatedto large-scale simulations. Thus, our proposition of a good hardware verificationpractice may rise synergy effects between hardware developers and neuroscientists.

Software-Controlled Dynamically Swappable Hardware Design in Partially Reconfigurable Systems

Directory of Open Access Journals (Sweden)

Huang Chun-Hsian

2008-01-01

Full Text Available Abstract We propose two basic wrapper designs and an enhanced wrapper design for arbitrary digital hardware circuit designs such that they can be enhanced with the capability for dynamic swapping controlled by software. A hardware design with either of the proposed wrappers can thus be swapped out of the partially reconfigurable logic at runtime in some intermediate state of computation and then swapped in when required to continue from that state. The context data is saved to a buffer in the wrapper at interruptible states, and then the wrapper takes care of saving the hardware context to communication memory through a peripheral bus, and later restoring the hardware context after the design is swapped in. The overheads of the hardware standardization and the wrapper in terms of additional reconfigurable logic resources and the time for context switching are small and generally acceptable. With the capability for dynamic swapping, high priority hardware tasks can interrupt low-priority tasks in real-time embedded systems so that the utilization of hardware space per unit time is increased.

Sensitivity of anterior pituitary hormones to graded levels of psychological stress.

Science.gov (United States)

Armario, A; Lopez-Calderón, A; Jolin, T; Castellanos, J M

1986-08-04

The effect of graded levels of stressor intensity on anterior pituitary hormones was studied in adult male rats. Corticosterone, considered as a reflection of ACTH release, and prolactin responses showed a good correlation with the intensity of the stressors. On the contrary, neither LH, GH nor TSH release showed a parallelism with the intensity of the stressors in spite of the fact that they clearly responded to all the stimuli. It appears that the hormones of the anterior pituitary might be divided into two groups: those whose response is sensitive to the levels of emotional arousal elicited by stress, and those displaying a clear but stereotyped response during stress. However, other alternative explanations might exist to justify the present results. The neural mechanisms underlying the two types of response are at present unknown. These data indicate that only the pituitary-adrenal axis and prolactin have some potential utilities as quantitative indices of emotional arousal elicited by currently applied stressors in the rat.

Cooperative communications hardware, channel and PHY

CERN Document Server

Dohler, Mischa

2010-01-01

Facilitating Cooperation for Wireless Systems Cooperative Communications: Hardware, Channel & PHY focuses on issues pertaining to the PHY layer of wireless communication networks, offering a rigorous taxonomy of this dispersed field, along with a range of application scenarios for cooperative and distributed schemes, demonstrating how these techniques can be employed. The authors discuss hardware, complexity and power consumption issues, which are vital for understanding what can be realized at the PHY layer, showing how wireless channel models differ from more traditional

IDD Archival Hardware Architecture and Workflow

Energy Technology Data Exchange (ETDEWEB)

Mendonsa, D; Nekoogar, F; Martz, H

2008-10-09

This document describes the functionality of every component in the DHS/IDD archival and storage hardware system shown in Fig. 1. The document describes steps by step process of image data being received at LLNL then being processed and made available to authorized personnel and collaborators. Throughout this document references will be made to one of two figures, Fig. 1 describing the elements of the architecture and the Fig. 2 describing the workflow and how the project utilizes the available hardware.

Aspects of system modelling in Hardware/Software partitioning

DEFF Research Database (Denmark)

Knudsen, Peter Voigt; Madsen, Jan

1996-01-01

This paper addresses fundamental aspects of system modelling and partitioning algorithms in the area of Hardware/Software Codesign. Three basic system models for partitioning are presented and the consequences of partitioning according to each of these are analyzed. The analysis shows...... the importance of making a clear distinction between the model used for partitioning and the model used for evaluation It also illustrates the importance of having a realistic hardware model such that hardware sharing can be taken into account. Finally, the importance of integrating scheduling and allocation...

Functional modelling for integration of human-software-hardware in complex physical systems

International Nuclear Information System (INIS)

Modarres, M.

1996-01-01

A framework describing the properties of complex physical systems composed of human-software-hardware interactions in terms of their functions is described. It is argued that such a framework is domain-general, so that functional primitives present a language that is more general than most other modeling methods such as mathematical simulation. The characteristics and types of functional models are described. Examples of uses of the framework in modeling physical systems composed of human-software-hardware (hereby we refer to them as only physical systems) are presented. It is concluded that a function-centered model of a physical system provides a capability for generating a high-level simulation of the system for intelligent diagnostic, control or other similar applications

Hardware Acceleration of Adaptive Neural Algorithms.

Energy Technology Data Exchange (ETDEWEB)

James, Conrad D. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

2017-11-01

As tradit ional numerical computing has faced challenges, researchers have turned towards alternative computing approaches to reduce power - per - computation metrics and improve algorithm performance. Here, we describe an approach towards non - conventional computing that strengthens the connection between machine learning and neuroscience concepts. The Hardware Acceleration of Adaptive Neural Algorithms (HAANA) project ha s develop ed neural machine learning algorithms and hardware for applications in image processing and cybersecurity. While machine learning methods are effective at extracting relevant features from many types of data, the effectiveness of these algorithms degrades when subjected to real - world conditions. Our team has generated novel neural - inspired approa ches to improve the resiliency and adaptability of machine learning algorithms. In addition, we have also designed and fabricated hardware architectures and microelectronic devices specifically tuned towards the training and inference operations of neural - inspired algorithms. Finally, our multi - scale simulation framework allows us to assess the impact of microelectronic device properties on algorithm performance.

Hardware-efficient Implementation of Half-Band IIR Filter for Interpolation and Decimation

DEFF Research Database (Denmark)

Jørgensen, Ivan Harald Holger; Pracný, Peter; Bruun, Erik

2013-01-01

This brief deals with a simple heuristic method for the hardware optimization of a half-band infinite-impulse response (IIR) filter. The optimization method that is proposed here is intended for a quick design selection at the system level, without the need for computationally intensive calculati...

Full Wafer Redistribution and Wafer Embedding as Key Technologies for a Multi-Scale Neuromorphic Hardware Cluster

OpenAIRE

Zoschke, Kai; Güttler, Maurice; Böttcher, Lars; Grübl, Andreas; Husmann, Dan; Schemmel, Johannes; Meier, Karlheinz; Ehrmann, Oswin

2018-01-01

Together with the Kirchhoff-Institute for Physics(KIP) the Fraunhofer IZM has developed a full wafer redistribution and embedding technology as base for a large-scale neuromorphic hardware system. The paper will give an overview of the neuromorphic computing platform at the KIP and the associated hardware requirements which drove the described technological developments. In the first phase of the project standard redistribution technologies from wafer level packaging were adapted to enable a ...

Longitudinal Relationships of Levels of Language in Writing and between Writing and Reading in Grades 1 to 7

Science.gov (United States)

Abbott, Robert D.; Berninger, Virginia W.; Fayol, Michel

2010-01-01

Longitudinal structural equation modeling was used to evaluate longitudinal relationships across adjacent grade levels 1 to 7 for levels of language in writing (Model 1, subword letter writing, word spelling, and text composing) or writing and reading (Model 2, subword letter writing and word spelling and reading; Model 3, word spelling and…

Hardware/software virtualization for the reconfigurable multicore platform.

NARCIS (Netherlands)

Ferger, M.; Al Kadi, M.; Hübner, M.; Koedam, M.L.P.J.; Sinha, S.S.; Goossens, K.G.W.; Marchesan Almeida, Gabriel; Rodrigo Azambuja, J.; Becker, Juergen

2012-01-01

This paper presents the Flex Tiles approach for the virtualization of hardware and software for a reconfigurable multicore architecture. The approach enables the virtualization of a dynamic tile-based hardware architecture consisting of processing tiles connected via a network-on-chip and a

School and Child Level Predictors of Academic Success for African American Children in Third Grade: Implications for No Child Left behind

Science.gov (United States)

Graves, Scott

2011-01-01

The purpose of this study was to examine correlates of being at expected grade level in reading in the third grade. Participants for this study were a nationally representative sample of African American children from the Early Childhood Longitudinal Study (ECLS-K). Multilevel modeling was conducted to determine significant predictors of academic…

Grading A-Level Double Subject Mathematicians and the Implications for Selection.

Science.gov (United States)

Newbould, Charles A.

1981-01-01

Test data were used to compare the grading of two forms of double mathematics: pure and applied math, and regular and advanced math. Results confirm expectations that in the former system, the grading is comparable, and in the latter, it is not necessarily comparable. Implications for student admission are discussed. (MSE)

PERANCANGAN APLIKASI SISTEM PAKAR DIAGNOSA KERUSAKAN HARDWARE KOMPUTER METODE FORWARD CHAINING

Directory of Open Access Journals (Sweden)

Ali Akbar Rismayadi

2016-09-01

Full Text Available Abstract Damage to computer hardware, not a big disaster, because not all damage to computer hardware can not be repaired, nearly all computer users, whether public or institutions often suffer various kinds of damage that occurred in the computer hardware it has, and the damage can be caused by various factors that are basically as the user does not know the cause of what makes the computer hardware used damaged. Therefore, it is necessary to build an application that can help users to mendiganosa damage to computer hardware. So that everyone can diagnose the type of hardware damage his computer. Development of expert system diagnosis of damage to computer hardware uses forward chaining method by promoting alisisis descriptive of various damage data obtained from several experts and other sources of literature to reach a conclusion on the diagnosis of damage. As well as using the waterfall model as a model system development, starting from the analysis stage to stage software needs support. This application is built using a programming language tools Eclipse ADT as well as SQLite as its database. diagnosis expert system damage computer hardware is expected to be used as a tool to help find the causes of damage to computer hardware independently without the help of a computer technician.

Flight Hardware Virtualization for On-Board Science Data Processing

Data.gov (United States)

National Aeronautics and Space Administration — Utilize Hardware Virtualization technology to benefit on-board science data processing by investigating new real time embedded Hardware Virtualization solutions and...

Speed challenge: a case for hardware implementation in soft-computing

Science.gov (United States)

Daud, T.; Stoica, A.; Duong, T.; Keymeulen, D.; Zebulum, R.; Thomas, T.; Thakoor, A.

2000-01-01

For over a decade, JPL has been actively involved in soft computing research on theory, architecture, applications, and electronics hardware. The driving force in all our research activities, in addition to the potential enabling technology promise, has been creation of a niche that imparts orders of magnitude speed advantage by implementation in parallel processing hardware with algorithms made especially suitable for hardware implementation. We review our work on neural networks, fuzzy logic, and evolvable hardware with selected application examples requiring real time response capabilities.

The Interaction Effects of Gender and Grade Level on Secondary School Students' Attitude towards Learning Chemistry

Science.gov (United States)

Heng, Chua Kah; Karpudewan, Mageswary

2015-01-01

This quantitative study reports the effects of gender and grade level on secondary students' attitude towards chemistry lessons. For this purpose, the Attitude towards Chemistry Lessons Scale (ATCLS) was administered to 446 secondary school students between 16-19 years old. The ATCLS consists of four different subscales: liking for chemistry…

Computer hardware for radiologists: Part I

International Nuclear Information System (INIS)

Indrajit, IK; Alam, A

2010-01-01

Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU), the chipset, the random access memory (RAM), the memory modules, bus, storage drives, and ports. The personnel computer (PC) has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs). The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called “buses”. The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute “programs”. A Pentium ® 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM) is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration

Computer hardware for radiologists: Part I

Directory of Open Access Journals (Sweden)

Indrajit I

2010-01-01

Full Text Available Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM, Picture Archiving and Communication System (PACS, Radiology information system (RIS technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU, the chipset, the random access memory (RAM, the memory modules, bus, storage drives, and ports. The personnel computer (PC has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs. The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called "buses". The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute "programs". A Pentium® 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration.

{sup 18}F-FDG PET/CT evaluation of children and young adults with suspected spinal fusion hardware infection

Energy Technology Data Exchange (ETDEWEB)

Bagrosky, Brian M. [University of Colorado School of Medicine, Department of Pediatric Radiology, Children' s Hospital Colorado, 12123 E. 16th Ave., Box 125, Aurora, CO (United States); University of Colorado School of Medicine, Department of Radiology, Division of Nuclear Medicine, Aurora, CO (United States); Hayes, Kari L.; Fenton, Laura Z. [University of Colorado School of Medicine, Department of Pediatric Radiology, Children' s Hospital Colorado, 12123 E. 16th Ave., Box 125, Aurora, CO (United States); Koo, Phillip J. [University of Colorado School of Medicine, Department of Radiology, Division of Nuclear Medicine, Aurora, CO (United States)

2013-08-15

Evaluation of the child with spinal fusion hardware and concern for infection is challenging because of hardware artifact with standard imaging (CT and MRI) and difficult physical examination. Studies using {sup 18}F-FDG PET/CT combine the benefit of functional imaging with anatomical localization. To discuss a case series of children and young adults with spinal fusion hardware and clinical concern for hardware infection. These people underwent FDG PET/CT imaging to determine the site of infection. We performed a retrospective review of whole-body FDG PET/CT scans at a tertiary children's hospital from December 2009 to January 2012 in children and young adults with spinal hardware and suspected hardware infection. The PET/CT scan findings were correlated with pertinent clinical information including laboratory values of inflammatory markers, postoperative notes and pathology results to evaluate the diagnostic accuracy of FDG PET/CT. An exempt status for this retrospective review was approved by the Institution Review Board. Twenty-five FDG PET/CT scans were performed in 20 patients. Spinal fusion hardware infection was confirmed surgically and pathologically in six patients. The most common FDG PET/CT finding in patients with hardware infection was increased FDG uptake in the soft tissue and bone immediately adjacent to the posterior spinal fusion rods at multiple contiguous vertebral levels. Noninfectious hardware complications were diagnosed in ten patients and proved surgically in four. Alternative sources of infection were diagnosed by FDG PET/CT in seven patients (five with pneumonia, one with pyonephrosis and one with superficial wound infections). FDG PET/CT is helpful in evaluation of children and young adults with concern for spinal hardware infection. Noninfectious hardware complications and alternative sources of infection, including pneumonia and pyonephrosis, can be diagnosed. FDG PET/CT should be the first-line cross-sectional imaging study in

Infected hardware after surgical stabilization of rib fractures: Outcomes and management experience.

Science.gov (United States)

Thiels, Cornelius A; Aho, Johnathon M; Naik, Nimesh D; Zielinski, Martin D; Schiller, Henry J; Morris, David S; Kim, Brian D

2016-05-01

Surgical stabilization of rib fracture (SSRF) is increasingly used for treatment of rib fractures. There are few data on the incidence, risk factors, outcomes, and optimal management strategy for hardware infection in these patients. We aimed to develop and propose a management algorithm to help others treat this potentially morbid complication. We retrospectively searched a prospectively collected rib fracture database for the records of all patients who underwent SSRF from August 2009 through March 2014 at our institution. We then analyzed for the subsequent development of hardware infection among these patients. Standard descriptive analyses were performed. Among 122 patients who underwent SSRF, most (73%) were men; the mean (SD) age was 59.5 (16.4) years, and median (interquartile range [IQR]) Injury Severity Score was 17 (13-22). The median number of rib fractures was 7 (5-9) and 48% of the patients had flail chest. Mortality at 30 days was 0.8%. Five patients (4.1%) had a hardware infection on mean (SD) postoperative day 12.0 (6.6). Median Injury Severity Score (17 [range, 13-42]) and hospital length of stay (9 days [6-37 days]) in these patients were similar to the values for those without infection (17 days [range, 13-22 days] and 9 days [6-12 days], respectively). Patients with infection underwent a median (IQR) of 2 (range, 2-3) additional operations, which included wound debridement (n = 5), negative-pressure wound therapy (n = 3), and antibiotic beads (n = 4). Hardware was removed in 3 patients at 140, 190, and 192 days after index operation. Cultures grew only gram-positive organisms. No patients required reintervention after hardware removal, and all achieved bony union and were taking no narcotics or antibiotics at the latest follow-up. Although uncommon, hardware infection after SSRF carries considerable morbidity. With the use of an aggressive multimodal management strategy, however, bony union and favorable long-term outcomes can be achieved

Hardware malware

CERN Document Server

Krieg, Christian

2013-01-01

In our digital world, integrated circuits are present in nearly every moment of our daily life. Even when using the coffee machine in the morning, or driving our car to work, we interact with integrated circuits. The increasing spread of information technology in virtually all areas of life in the industrialized world offers a broad range of attack vectors. So far, mainly software-based attacks have been considered and investigated, while hardware-based attacks have attracted comparatively little interest. The design and production process of integrated circuits is mostly decentralized due to

Hardware Accelerated Sequence Alignment with Traceback

Directory of Open Access Journals (Sweden)

Scott Lloyd

2009-01-01

in a timely manner. Known methods to accelerate alignment on reconfigurable hardware only address sequence comparison, limit the sequence length, or exhibit memory and I/O bottlenecks. A space-efficient, global sequence alignment algorithm and architecture is presented that accelerates the forward scan and traceback in hardware without memory and I/O limitations. With 256 processing elements in FPGA technology, a performance gain over 300 times that of a desktop computer is demonstrated on sequence lengths of 16000. For greater performance, the architecture is scalable to more processing elements.

Hardware-in-the-Loop Testing

Data.gov (United States)

Federal Laboratory Consortium — RTC has a suite of Hardware-in-the Loop facilities that include three operational facilities that provide performance assessment and production acceptance testing of...

Student-Centred Teaching Strategies by Gender, Grade Level, and Teacher’s Self-Concept in Mexico

Directory of Open Access Journals (Sweden)

PEDRO SÁNCHEZ-ESCOBEDO

2018-05-01

Full Text Available This study examined the student-centred teaching strategies of Mexican teachers by gender, grade level, and self-concept as an instructor. A conventional sample of 573 teachers from diverse school settings in the state of Yucatan in Mexico responded to a paper and pencil questionnaire. Results indicated, in general, that teachers prioritized classroom management and independent learning activities, in contrast with teaching strategies emphasized by policies and teacher´s training programs in the country, such as cooperative learning, differentiation, or promoting critical thinking. There were some gender and grade level differences. In general, female teachers promoted more independent activities than males. As expected, primary school teachers were more concerned with using differentiation teaching strategies than secondary education teachers, considering the greatest variance in younger students. Teachers self-concept had differential effects. Whilst self-efficacy feelings had no influence in the use of specific student-centred teaching strategies, high self-esteem teachers used more student-centred teaching strategies. The importance of asking teachers what they did, and how they felt as teachers was argued in light of results. Future research avenues regarding self-concept and teaching strategies are posited.

Hardware Middleware for Person Tracking on Embedded Distributed Smart Cameras

Directory of Open Access Journals (Sweden)

Ali Akbar Zarezadeh

2012-01-01

Full Text Available Tracking individuals is a prominent application in such domains like surveillance or smart environments. This paper provides a development of a multiple camera setup with jointed view that observes moving persons in a site. It focuses on a geometry-based approach to establish correspondence among different views. The expensive computational parts of the tracker are hardware accelerated via a novel system-on-chip (SoC design. In conjunction with this vision application, a hardware object request broker (ORB middleware is presented as the underlying communication system. The hardware ORB provides a hardware/software architecture to achieve real-time intercommunication among multiple smart cameras. Via a probing mechanism, a performance analysis is performed to measure network latencies, that is, time traversing the TCP/IP stack, in both software and hardware ORB approaches on the same smart camera platform. The empirical results show that using the proposed hardware ORB as client and server in separate smart camera nodes will considerably reduce the network latency up to 100 times compared to the software ORB.

Open Hardware for CERN's accelerator control systems

International Nuclear Information System (INIS)

Bij, E van der; Serrano, J; Wlostowski, T; Cattin, M; Gousiou, E; Sanchez, P Alvarez; Boccardi, A; Voumard, N; Penacoba, G

2012-01-01

The accelerator control systems at CERN will be upgraded and many electronics modules such as analog and digital I/O, level converters and repeaters, serial links and timing modules are being redesigned. The new developments are based on the FPGA Mezzanine Card, PCI Express and VME64x standards while the Wishbone specification is used as a system on a chip bus. To attract partners, the projects are developed in an 'Open' fashion. Within this Open Hardware project new ways of working with industry are being evaluated and it has been proven that industry can be involved at all stages, from design to production and support.

Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification

OpenAIRE

Drzevitzky, Stephanie; Kastens, Uwe; Platzner, Marco

2010-01-01

Dynamically reconfigurable hardware combines hardware performance with software-like flexibility and finds increasing use in networked systems. The capability to load hardware modules at runtime provides these systems with an unparalleled degree of adaptivity but at the same time poses new challenges for security and safety. In this paper, we elaborate on the presentation of proof carrying hardware (PCH) as a novel approach to reconfigurable system security. PCH takes ...

The Effect of Project Based Learning on the Statistical Literacy Levels of Student 8th Grade

Science.gov (United States)

Koparan, Timur; Güven, Bülent

2014-01-01

This study examines the effect of project based learning on 8th grade students' statistical literacy levels. A performance test was developed for this aim. Quasi-experimental research model was used in this article. In this context, the statistics were taught with traditional method in the control group and it was taught using project based…

Testing Our Assumptions: The Role of First Course Grade and Course Level in Mathematics and English

Science.gov (United States)

Callahan, Janet; Belcheir, Marcia

2017-01-01

Methods that provide an early indicator of factors that affect student persistence are important to colleges and universities. This quantitative research focused on the role of level of entry mathematics and English and also on grades earned in those classes, as they relate to persistence after 1 year. The research showed that by far, the variable…

An environmental testing facility for Space Station Freedom power management and distribution hardware

Science.gov (United States)

Jackola, Arthur S.; Hartjen, Gary L.

1992-01-01

The plans for a new test facility, including new environmental test systems, which are presently under construction, and the major environmental Test Support Equipment (TSE) used therein are addressed. This all-new Rocketdyne facility will perform space simulation environmental tests on Power Management and Distribution (PMAD) hardware to Space Station Freedom (SSF) at the Engineering Model, Qualification Model, and Flight Model levels of fidelity. Testing will include Random Vibration in three axes - Thermal Vacuum, Thermal Cycling and Thermal Burn-in - as well as numerous electrical functional tests. The facility is designed to support a relatively high throughput of hardware under test, while maintaining the high standards required for a man-rated space program.

The VMTG Hardware Description

CERN Document Server

Puccio, B

1998-01-01

The document describes the hardware features of the CERN Master Timing Generator. This board is the common platform for the transmission of General Timing Machine required by the CERN accelerators. In addition, the paper shows the various jumper options to customise the card which is compliant to the VMEbus standard.

Dynamically-Loaded Hardware Libraries (HLL) Technology for Audio Applications

DEFF Research Database (Denmark)

Esposito, A.; Lomuscio, A.; Nunzio, L. Di

2016-01-01

In this work, we apply hardware acceleration to embedded systems running audio applications. We present a new framework, Dynamically-Loaded Hardware Libraries or HLL, to dynamically load hardware libraries on reconfigurable platforms (FPGAs). Provided a library of application-specific processors......, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. The proposed architecture provides excellent flexibility with respect to the different audio applications implemented, high quality audio, and an energy efficient solution....

Readmission after treatment of Grade 3 and 4 renal injuries at a Level I trauma center: Statewide assessment using the Comprehensive Hospital Abstract Reporting System.

Science.gov (United States)

Winters, Brian; Wessells, Hunter; Voelzke, Bryan B

2016-03-01

One criticism of the existing renal trauma research is the limited outpatient follow-up after index hospitalization. We assessed readmission rates following treatment for American Association for the Surgery of Trauma (AAST) Grade 3 and 4 renal injury using the Comprehensive Hospital Abstract Reporting System (CHARS). We evaluated all patients with AAST Grade 3 and 4 renal injuries admitted to Harborview Medical Center (HMC) between 1998 and 2010, the only Level 1 trauma center in Washington state. Grade 4 renal injuries were stratified by collecting system laceration (CSL) or segmental vascular injury. Data were abstracted from the CHARS database for readmissions to any Washington state hospital within 6 months of renal injury. Clinical variables, diagnoses, and procedures were queried based on DRG International Classification of Diseases-9th Rev. codes. A total of 477 Grade 3 and 159 Grade 4 renal injuries were initially treated at HMC. On admission, 111 patients required intervention: 75 (16%) of 477 Grade 3 and 36 (23%) of 159 Grade 4 injuries. Within 6 months of index hospitalization, 86 (18%) of 477 Grade 3 and 38 (24%) of 159 Grade 4 patients were readmitted to any Washington state hospital. Eighty percent of Grade 3 injuries and 66% of Grade 4 injuries returned to HMC compared with secondary hospitals (p = 0.08). At readmission, 19 (22%) of 86 Grade 3 and 16 (42%) of 38 Grade 4 injuries had a urologic diagnosis. Subsequent procedural intervention was required on readmission in 6 (7%) of 86 Grade 3 and 5 (13%) of 38 Grade 4 renal injuries (all CSL injuries). A subset of patients treated for Grade 3 and 4 renal trauma will be readmitted for further management. While urologic diagnoses and additional procedures may be low overall, readmission to outside hospitals may preclude accurate determination of renal trauma outcomes. Based on these data, patients with Grade 4 CSL injuries seem to be at the highest risk for readmission and to require a subsequent

Web-Compatible Graphics Visualization Framework for Online Instruction and Assessment of Hardware Concepts

Science.gov (United States)

Chandramouli, Magesh; Chittamuru, Siva-Teja

2016-01-01

This paper explains the design of a graphics-based virtual environment for instructing computer hardware concepts to students, especially those at the beginner level. Photorealistic visualizations and simulations are designed and programmed with interactive features allowing students to practice, explore, and test themselves on computer hardware…

Hardware Approach for Real Time Machine Stereo Vision

Directory of Open Access Journals (Sweden)

Michael Tornow

2006-02-01

Full Text Available Image processing is an effective tool for the analysis of optical sensor information for driver assistance systems and controlling of autonomous robots. Algorithms for image processing are often very complex and costly in terms of computation. In robotics and driver assistance systems, real-time processing is necessary. Signal processing algorithms must often be drastically modified so they can be implemented in the hardware. This task is especially difficult for continuous real-time processing at high speeds. This article describes a hardware-software co-design for a multi-object position sensor based on a stereophotogrammetric measuring method. In order to cover a large measuring area, an optimized algorithm based on an image pyramid is implemented in an FPGA as a parallel hardware solution for depth map calculation. Object recognition and tracking are then executed in real-time in a processor with help of software. For this task a statistical cluster method is used. Stabilization of the tracking is realized through use of a Kalman filter. Keywords: stereophotogrammetry, hardware-software co-design, FPGA, 3-d image analysis, real-time, clustering and tracking.

Hardware implementation of a GFSR pseudo-random number generator

Science.gov (United States)

Aiello, G. R.; Budinich, M.; Milotti, E.

1989-12-01

We describe the hardware implementation of a pseudo-random number generator of the "Generalized Feedback Shift Register" (GFSR) type. After brief theoretical considerations we describe two versions of the hardware, the tests done and the performances achieved.

Hardware Realization of Chaos Based Symmetric Image Encryption

KAUST Repository

Barakat, Mohamed L.

2012-06-01

This thesis presents a novel work on hardware realization of symmetric image encryption utilizing chaos based continuous systems as pseudo random number generators. Digital implementation of chaotic systems results in serious degradations in the dynamics of the system. Such defects are illuminated through a new technique of generalized post proceeding with very low hardware cost. The thesis further discusses two encryption algorithms designed and implemented as a block cipher and a stream cipher. The security of both systems is thoroughly analyzed and the performance is compared with other reported systems showing a superior results. Both systems are realized on Xilinx Vetrix-4 FPGA with a hardware and throughput performance surpassing known encryption systems.

Desenvolvimento de hardware reconfigurável de criptografia assimétrica

Directory of Open Access Journals (Sweden)

Otávio Souza Martins Gomes

2015-01-01

Full Text Available Este artigo apresenta o resultado parcial do desenvolvimento de uma interface de hardware reconfigurável para criptografia assimétrica que permite a troca segura de dados. Hardwares reconfiguráveis permitem o desenvolvimento deste tipo de dispositivo com segurança e flexibilidade e possibilitam a mudança de características no projeto com baixo custo e de forma rápida.Palavras-chave: Criptografia. Hardware. ElGamal. FPGA. Segurança. Development of an asymmetric cryptography reconfigurable harwadre ABSTRACTThis paper presents some conclusions and choices about the development of an asymmetric cryptography reconfigurable hardware interface to allow a safe data communication. Reconfigurable hardwares allows the development of this kind of device with safety and flexibility, and offer the possibility to change some features with low cost and in a fast way.Keywords: Cryptography. Hardware. ElGamal. FPGAs. Security.

MRI monitoring of focused ultrasound sonications near metallic hardware.

Science.gov (United States)

Weber, Hans; Ghanouni, Pejman; Pascal-Tenorio, Aurea; Pauly, Kim Butts; Hargreaves, Brian A

2018-07-01

To explore the temperature-induced signal change in two-dimensional multi-spectral imaging (2DMSI) for fast thermometry near metallic hardware to enable MR-guided focused ultrasound surgery (MRgFUS) in patients with implanted metallic hardware. 2DMSI was optimized for temperature sensitivity and applied to monitor focus ultrasound surgery (FUS) sonications near metallic hardware in phantoms and ex vivo porcine muscle tissue. Further, we evaluated its temperature sensitivity for in vivo muscle in patients without metallic hardware. In addition, we performed a comparison of temperature sensitivity between 2DMSI and conventional proton-resonance-frequency-shift (PRFS) thermometry at different distances from metal devices and different signal-to-noise ratios (SNR). 2DMSI thermometry enabled visualization of short ultrasound sonications near metallic hardware. Calibration using in vivo muscle yielded a constant temperature sensitivity for temperatures below 43 °C. For an off-resonance coverage of ± 6 kHz, we achieved a temperature sensitivity of 1.45%/K, resulting in a minimum detectable temperature change of ∼2.5 K for an SNR of 100 with a temporal resolution of 6 s per frame. The proposed 2DMSI thermometry has the potential to allow MR-guided FUS treatments of patients with metallic hardware and therefore expand its reach to a larger patient population. Magn Reson Med 80:259-271, 2018. © 2017 International Society for Magnetic Resonance in Medicine. © 2017 International Society for Magnetic Resonance in Medicine.

Trends in computer hardware and software.

Science.gov (United States)

Frankenfeld, F M

1993-04-01

Previously identified and current trends in the development of computer systems and in the use of computers for health care applications are reviewed. Trends identified in a 1982 article were increasing miniaturization and archival ability, increasing software costs, increasing software independence, user empowerment through new software technologies, shorter computer-system life cycles, and more rapid development and support of pharmaceutical services. Most of these trends continue today. Current trends in hardware and software include the increasing use of reduced instruction-set computing, migration to the UNIX operating system, the development of large software libraries, microprocessor-based smart terminals that allow remote validation of data, speech synthesis and recognition, application generators, fourth-generation languages, computer-aided software engineering, object-oriented technologies, and artificial intelligence. Current trends specific to pharmacy and hospitals are the withdrawal of vendors of hospital information systems from the pharmacy market, improved linkage of information systems within hospitals, and increased regulation by government. The computer industry and its products continue to undergo dynamic change. Software development continues to lag behind hardware, and its high cost is offsetting the savings provided by hardware.

CERN Neutrino Platform Hardware

CERN Document Server

Nelson, Kevin

2017-01-01

My summer research was broadly in CERN's neutrino platform hardware efforts. This project had two main components: detector assembly and data analysis work for ICARUS. Specifically, I worked on assembly for the ProtoDUNE project and monitored the safety of ICARUS as it was transported to Fermilab by analyzing the accelerometer data from its move.

Human Centered Hardware Modeling and Collaboration

Science.gov (United States)

Stambolian Damon; Lawrence, Brad; Stelges, Katrine; Henderson, Gena

2013-01-01

In order to collaborate engineering designs among NASA Centers and customers, to in clude hardware and human activities from multiple remote locations, live human-centered modeling and collaboration across several sites has been successfully facilitated by Kennedy Space Center. The focus of this paper includes innovative a pproaches to engineering design analyses and training, along with research being conducted to apply new technologies for tracking, immersing, and evaluating humans as well as rocket, vehic le, component, or faci lity hardware utilizing high resolution cameras, motion tracking, ergonomic analysis, biomedical monitoring, wor k instruction integration, head-mounted displays, and other innovative human-system integration modeling, simulation, and collaboration applications.

Analysis for Parallel Execution without Performing Hardware/Software Co-simulation

OpenAIRE

Muhammad Rashid

2014-01-01

Hardware/software co-simulation improves the performance of embedded applications by executing the applications on a virtual platform before the actual hardware is available in silicon. However, the virtual platform of the target architecture is often not available during early stages of the embedded design flow. Consequently, analysis for parallel execution without performing hardware/software co-simulation is required. This article presents an analysis methodology for parallel execution of ...

Sample Grade Level Benchmarks, Grades 5-8, Based on the 1998 Arkansas State Mathematics Framework.

Science.gov (United States)

Arkansas State Dept. of Education, Little Rock.

This document presents the application and use of mathematics learning proposed by the Arkansas curriculum frameworks for grades 5-8. The standards are presented in chart form and organized into five strands: (1) number sense, properties, and operations; (2) geometry and spatial sense; (3) measurement; (4) data analysis, statistics, and…

Software error masking effect on hardware faults

International Nuclear Information System (INIS)

Choi, Jong Gyun; Seong, Poong Hyun

1999-01-01

Based on the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL), in this work, a simulation model for fault injection is developed to estimate the dependability of the digital system in operational phase. We investigated the software masking effect on hardware faults through the single bit-flip and stuck-at-x fault injection into the internal registers of the processor and memory cells. The fault location reaches all registers and memory cells. Fault distribution over locations is randomly chosen based on a uniform probability distribution. Using this model, we have predicted the reliability and masking effect of an application software in a digital system-Interposing Logic System (ILS) in a nuclear power plant. We have considered four the software operational profiles. From the results it was found that the software masking effect on hardware faults should be properly considered for predicting the system dependability accurately in operation phase. It is because the masking effect was formed to have different values according to the operational profile

Instrument hardware and software upgrades at IPNS

International Nuclear Information System (INIS)

Worlton, Thomas; Hammonds, John; Mikkelson, D.; Mikkelson, Ruth; Porter, Rodney; Tao, Julian; Chatterjee, Alok

2006-01-01

IPNS is in the process of upgrading their time-of-flight neutron scattering instruments with improved hardware and software. The hardware upgrades include replacing old VAX Qbus and Multibus-based data acquisition systems with new systems based on VXI and VME. Hardware upgrades also include expanded detector banks and new detector electronics. Old VAX Fortran-based data acquisition and analysis software is being replaced with new software as part of the ISAW project. ISAW is written in Java for ease of development and portability, and is now used routinely for data visualization, reduction, and analysis on all upgraded instruments. ISAW provides the ability to process and visualize the data from thousands of detector pixels, each having thousands of time channels. These operations can be done interactively through a familiar graphical user interface or automatically through simple scripts. Scripts and operators provided by end users are automatically included in the ISAW menu structure, along with those distributed with ISAW, when the application is started

MFTF supervisory control and diagnostics system hardware

International Nuclear Information System (INIS)

Butner, D.N.

1979-01-01

The Supervisory Control and Diagnostics System (SCDS) for the Mirror Fusion Test Facility (MFTF) is a multiprocessor minicomputer system designed so that for most single-point failures, the hardware may be quickly reconfigured to provide continued operation of the experiment. The system is made up of nine Perkin-Elmer computers - a mixture of 8/32's and 7/32's. Each computer has ports on a shared memory system consisting of two independent shared memory modules. Each processor can signal other processors through hardware external to the shared memory. The system communicates with the Local Control and Instrumentation System, which consists of approximately 65 microprocessors. Each of the six system processors has facilities for communicating with a group of microprocessors; the groups consist of from four to 24 microprocessors. There are hardware switches so that if an SCDS processor communicating with a group of microprocessors fails, another SCDS processor takes over the communication

Flight Hardware Virtualization for On-Board Science Data Processing Project

Data.gov (United States)

National Aeronautics and Space Administration — Utilize Hardware Virtualization technology to benefit on-board science data processing by investigating new real time embedded Hardware Virtualization solutions and...

Compiling quantum circuits to realistic hardware architectures using temporal planners

Science.gov (United States)

Venturelli, Davide; Do, Minh; Rieffel, Eleanor; Frank, Jeremy

2018-04-01

To run quantum algorithms on emerging gate-model quantum hardware, quantum circuits must be compiled to take into account constraints on the hardware. For near-term hardware, with only limited means to mitigate decoherence, it is critical to minimize the duration of the circuit. We investigate the application of temporal planners to the problem of compiling quantum circuits to newly emerging quantum hardware. While our approach is general, we focus on compiling to superconducting hardware architectures with nearest neighbor constraints. Our initial experiments focus on compiling Quantum Alternating Operator Ansatz (QAOA) circuits whose high number of commuting gates allow great flexibility in the order in which the gates can be applied. That freedom makes it more challenging to find optimal compilations but also means there is a greater potential win from more optimized compilation than for less flexible circuits. We map this quantum circuit compilation problem to a temporal planning problem, and generated a test suite of compilation problems for QAOA circuits of various sizes to a realistic hardware architecture. We report compilation results from several state-of-the-art temporal planners on this test set. This early empirical evaluation demonstrates that temporal planning is a viable approach to quantum circuit compilation.

Fuel cell hardware-in-loop

Energy Technology Data Exchange (ETDEWEB)

Moore, R.M.; Randolf, G.; Virji, M. [University of Hawaii, Hawaii Natural Energy Institute (United States); Hauer, K.H. [Xcellvision (Germany)

2006-11-08

Hardware-in-loop (HiL) methodology is well established in the automotive industry. One typical application is the development and validation of control algorithms for drive systems by simulating the vehicle plus the vehicle environment in combination with specific control hardware as the HiL component. This paper introduces the use of a fuel cell HiL methodology for fuel cell and fuel cell system design and evaluation-where the fuel cell (or stack) is the unique HiL component that requires evaluation and development within the context of a fuel cell system designed for a specific application (e.g., a fuel cell vehicle) in a typical use pattern (e.g., a standard drive cycle). Initial experimental results are presented for the example of a fuel cell within a fuel cell vehicle simulation under a dynamic drive cycle. (author)

Flexible hardware design for RSA and Elliptic Curve Cryptosystems

NARCIS (Netherlands)

Batina, L.; Bruin - Muurling, G.; Örs, S.B.; Okamoto, T.

2004-01-01

This paper presents a scalable hardware implementation of both commonly used public key cryptosystems, RSA and Elliptic Curve Cryptosystem (ECC) on the same platform. The introduced hardware accelerator features a design which can be varied from very small (less than 20 Kgates) targeting wireless

Sharing open hardware through ROP, the robotic open platform

NARCIS (Netherlands)

Lunenburg, J.; Soetens, R.P.T.; Schoenmakers, F.; Metsemakers, P.M.G.; van de Molengraft, M.J.G.; Steinbuch, M.; Behnke, S.; Veloso, M.; Visser, A.; Xiong, R.

2014-01-01

The robot open source software community, in particular ROS, drastically boosted robotics research. However, a centralized place to exchange open hardware designs does not exist. Therefore we launched the Robotic Open Platform (ROP). A place to share and discuss open hardware designs. Among others

Sharing open hardware through ROP, the Robotic Open Platform

NARCIS (Netherlands)

Lunenburg, J.J.M.; Soetens, R.P.T.; Schoenmakers, Ferry; Metsemakers, P.M.G.; Molengraft, van de M.J.G.; Steinbuch, M.

2013-01-01

The robot open source software community, in particular ROS, drastically boosted robotics research. However, a centralized place to exchange open hardware designs does not exist. Therefore we launched the Robotic Open Platform (ROP). A place to share and discuss open hardware designs. Among others

Hardware Abstraction and Protocol Optimization for Coded Sensor Networks

DEFF Research Database (Denmark)

Nistor, Maricica; Roetter, Daniel Enrique Lucani; Barros, João

2015-01-01

The design of the communication protocols in wireless sensor networks (WSNs) often neglects several key characteristics of the sensor's hardware, while assuming that the number of transmitted bits is the dominating factor behind the system's energy consumption. A closer look at the hardware speci...

A critical appraisal of standard guidelines for grading levels of evidence.

Science.gov (United States)

Gugiu, P Cristian; Gugiu, Mihaiela Ristei

2010-09-01

Over the past 30 years, a general consensus has emerged within the medical community regarding the essential role served by grading guidelines in evaluating the quality of evidence produced by a medical research study. Specifically, consensus exists regarding the hierarchy of evidence, where randomized controlled trials (RCTs) are considered the ''gold standard'' followed by nonrandomized controlled trials (non-RCTs) and uncontrolled trials. As guidelines have become more sophisticated, processes have been developed for downgrading poorly conducted studies and upgrading strong studies. Lists of threats to internal validity have been disseminated, thereby assisting reviewers in grading studies. However, despite these many accomplishments, considerable issues remain unresolved with respect to how to evaluate the strength of evidence produced by flawed RCTs versus well-conducted non-RCTs. The purpose of this article is to evaluate existing evidence-based grading guidelines and to offer suggestions for how such guidelines may be improved.

Fast DRR splat rendering using common consumer graphics hardware

International Nuclear Information System (INIS)

Spoerk, Jakob; Bergmann, Helmar; Wanschitz, Felix; Dong, Shuo; Birkfellner, Wolfgang

2007-01-01

Digitally rendered radiographs (DRR) are a vital part of various medical image processing applications such as 2D/3D registration for patient pose determination in image-guided radiotherapy procedures. This paper presents a technique to accelerate DRR creation by using conventional graphics hardware for the rendering process. DRR computation itself is done by an efficient volume rendering method named wobbled splatting. For programming the graphics hardware, NVIDIAs C for Graphics (Cg) is used. The description of an algorithm used for rendering DRRs on the graphics hardware is presented, together with a benchmark comparing this technique to a CPU-based wobbled splatting program. Results show a reduction of rendering time by about 70%-90% depending on the amount of data. For instance, rendering a volume of 2x10 6 voxels is feasible at an update rate of 38 Hz compared to 6 Hz on a common Intel-based PC using the graphics processing unit (GPU) of a conventional graphics adapter. In addition, wobbled splatting using graphics hardware for DRR computation provides higher resolution DRRs with comparable image quality due to special processing characteristics of the GPU. We conclude that DRR generation on common graphics hardware using the freely available Cg environment is a major step toward 2D/3D registration in clinical routine

FPS-RAM: Fast Prefix Search RAM-Based Hardware for Forwarding Engine

Science.gov (United States)

Zaitsu, Kazuya; Yamamoto, Koji; Kuroda, Yasuto; Inoue, Kazunari; Ata, Shingo; Oka, Ikuo

Ternary content addressable memory (TCAM) is becoming very popular for designing high-throughput forwarding engines on routers. However, TCAM has potential problems in terms of hardware and power costs, which limits its ability to deploy large amounts of capacity in IP routers. In this paper, we propose new hardware architecture for fast forwarding engines, called fast prefix search RAM-based hardware (FPS-RAM). We designed FPS-RAM hardware with the intent of maintaining the same search performance and physical user interface as TCAM because our objective is to replace the TCAM in the market. Our RAM-based hardware architecture is completely different from that of TCAM and has dramatically reduced the costs and power consumption to 62% and 52%, respectively. We implemented FPS-RAM on an FPGA to examine its lookup operation.

Combining high productivity with high performance on commodity hardware

DEFF Research Database (Denmark)

Skovhede, Kenneth

-like compiler for translating CIL bytecode on the CELL-BE. I then introduce a bytecode converter that transforms simple loops in Java bytecode to GPGPU capable code. I then introduce the numeric library for the Common Intermediate Language, NumCIL. I can then utilizing the vector programming model from Num......CIL and map this to the Bohrium framework. The result is a complete system that gives the user a choice of high-level languages with no explicit parallelism, yet seamlessly performs efficient execution on a number of hardware setups....

Hardware and software status of QCDOC

International Nuclear Information System (INIS)

Boyle, P.A.; Chen, D.; Christ, N.H.; Clark, M.; Cohen, S.D.; Cristian, C.; Dong, Z.; Gara, A.; Joo, B.; Jung, C.; Kim, C.; Levkova, L.; Liao, X.; Liu, G.; Mawhinney, R.D.; Ohta, S.; Petrov, K.; Wettig, T.; Yamaguchi, A.

2004-01-01

QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of $1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation

Quantum neuromorphic hardware for quantum artificial intelligence

Science.gov (United States)

Prati, Enrico

2017-08-01

The development of machine learning methods based on deep learning boosted the field of artificial intelligence towards unprecedented achievements and application in several fields. Such prominent results were made in parallel with the first successful demonstrations of fault tolerant hardware for quantum information processing. To which extent deep learning can take advantage of the existence of a hardware based on qubits behaving as a universal quantum computer is an open question under investigation. Here I review the convergence between the two fields towards implementation of advanced quantum algorithms, including quantum deep learning.

Analysis of facility needs level in architecture studio for students’ studio grades

Science.gov (United States)

Lubis, A. S.; Hamid, B.; Pane, I. F.; Marpaung, B. O. Y.

2018-03-01

Architects must be able to play an active role and contribute to the realization of a sustainable environment. Architectural education has inherited many education research used qualitative and quantitative methods. The data were gathered by conducting (a) observation,(b) interviews, (c) documentation, (d) literature study, and (e) Questionnaire. The gathered data were analyzed qualitatively to find out what equipment needed in the learning process in the Architecture Studio, USU. Questionnaires and Ms. Excel were used for the quantitative analysis. The tabulation of quantitative data would be correlated with the students’ studio grades. The result of the research showed that equipment with the highest level of needs was (1) drawing table, (2) Special room for each student, (3) Internet Network, (4) Air Conditioning, (5) Sufficient lighting.

Introduction to co-simulation of software and hardware in embedded processor systems

Energy Technology Data Exchange (ETDEWEB)

Dreike, P.L.; McCoy, J.A.

1996-09-01

From the dawn of the first use of microprocessors and microcontrollers in embedded systems, the software has been blamed for products being late to market, This is due to software being developed after hardware is fabricated. During the past few years, the use of Hardware Description (or Design) Languages (HDLs) and digital simulation have advanced to a point where the concurrent development of software and hardware can be contemplated using simulation environments. This offers the potential of 50% or greater reductions in time-to-market for embedded systems. This paper is a tutorial on the technical issues that underlie software-hardware (swhw) co-simulation, and the current state of the art. We review the traditional sequential hardware-software design paradigm, and suggest a paradigm for concurrent design, which is supported by co-simulation of software and hardware. This is followed by sections on HDLs modeling and simulation;hardware assisted approaches to simulation; microprocessor modeling methods; brief descriptions of four commercial products for sw-hw co-simulation and a description of our own experiments to develop a co-simulation environment.

The LASS hardware processor

International Nuclear Information System (INIS)

Kunz, P.F.

1976-01-01

The problems of data analysis with hardware processors are reviewed and a description is given of a programmable processor. This processor, the 168/E, has been designed for use in the LASS multi-processor system; it has an execution speed comparable to the IBM 370/168 and uses the subset of IBM 370 instructions appropriate to the LASS analysis task. (Auth.)

RRFC hardware operation manual

International Nuclear Information System (INIS)

Abhold, M.E.; Hsue, S.T.; Menlove, H.O.; Walton, G.

1996-05-01

The Research Reactor Fuel Counter (RRFC) system was developed to assay the 235 U content in spent Material Test Reactor (MTR) type fuel elements underwater in a spent fuel pool. RRFC assays the 235 U content using active neutron coincidence counting and also incorporates an ion chamber for gross gamma-ray measurements. This manual describes RRFC hardware, including detectors, electronics, and performance characteristics

Removal of symptomatic craniofacial titanium hardware following craniotomy: Case series and review

Directory of Open Access Journals (Sweden)

Sheri K. Palejwala

2015-06-01

Full Text Available Titanium craniofacial hardware has become commonplace for reconstruction and bone flap fixation following craniotomy. Complications of titanium hardware include palpability, visibility, infection, exposure, pain, and hardware malfunction, which can necessitate hardware removal. We describe three patients who underwent craniofacial reconstruction following craniotomies for trauma with post-operative courses complicated by medically intractable facial pain. All three patients subsequently underwent removal of the symptomatic craniofacial titanium hardware and experienced rapid resolution of their painful parasthesias. Symptomatic plates were found in the region of the frontozygomatic suture or MacCarty keyhole, or in close proximity with the supraorbital nerve. Titanium plates, though relatively safe and low profile, can cause local nerve irritation or neuropathy. Surgeons should be cognizant of the potential complications of titanium craniofacial hardware and locations that are at higher risk for becoming symptomatic necessitating a second surgery for removal.

WE-DE-206-02: MRI Hardware - Magnet, Gradient, RF Coils

Energy Technology Data Exchange (ETDEWEB)

Kocharian, A. [Methodist Hospital (United States)

2016-06-15

Magnetic resonance imaging (MRI) has become an essential part of clinical imaging due to its ability to render high soft tissue contrast. Instead of ionizing radiation, MRI use strong magnetic field, radio frequency waves and field gradients to create diagnostic useful images. It can be used to image the anatomy and also functional and physiological activities within the human body. Knowledge of the basic physical principles underlying MRI acquisition is vitally important to successful image production and proper image interpretation. This lecture will give an overview of the spin physics, imaging principle of MRI, the hardware of the MRI scanner, and various pulse sequences and their applications. It aims to provide a conceptual foundation to understand the image formation process of a clinical MRI scanner. Learning Objectives: Understand the origin of the MR signal and contrast from the spin physics level. Understand the main hardware components of a MRI scanner and their purposes Understand steps for MR image formation including spatial encoding and image reconstruction Understand the main kinds of MR pulse sequences and their characteristics.

Hardware support for collecting performance counters directly to memory

Science.gov (United States)

Gara, Alan; Salapura, Valentina; Wisniewski, Robert W.

2012-09-25

Hardware support for collecting performance counters directly to memory, in one aspect, may include a plurality of performance counters operable to collect one or more counts of one or more selected activities. A first storage element may be operable to store an address of a memory location. A second storage element may be operable to store a value indicating whether the hardware should begin copying. A state machine may be operable to detect the value in the second storage element and trigger hardware copying of data in selected one or more of the plurality of performance counters to the memory location whose address is stored in the first storage element.

Why Open Source Hardware matters and why you should care

OpenAIRE

Gürkaynak, Frank K.

2017-01-01

Open source hardware is currently where open source software was about 30 years ago. The idea is well received by enthusiasts, there is interest and the open source hardware has gained visible momentum recently, with several well-known universities including UC Berkeley, Cambridge and ETH Zürich actively working on large projects involving open source hardware, attracting the attention of companies big and small. But it is still not quite there yet. In this talk, based on my experience on the...

Acceleration of Meshfree Radial Point Interpolation Method on Graphics Hardware

International Nuclear Information System (INIS)

Nakata, Susumu

2008-01-01

This article describes a parallel computational technique to accelerate radial point interpolation method (RPIM)-based meshfree method using graphics hardware. RPIM is one of the meshfree partial differential equation solvers that do not require the mesh structure of the analysis targets. In this paper, a technique for accelerating RPIM using graphics hardware is presented. In the method, the computation process is divided into small processes suitable for processing on the parallel architecture of the graphics hardware in a single instruction multiple data manner.

No-hardware-signature cybersecurity-crypto-module: a resilient cyber defense agent

Science.gov (United States)

Zaghloul, A. R. M.; Zaghloul, Y. A.

2014-06-01

We present an optical cybersecurity-crypto-module as a resilient cyber defense agent. It has no hardware signature since it is bitstream reconfigurable, where single hardware architecture functions as any selected device of all possible ones of the same number of inputs. For a two-input digital device, a 4-digit bitstream of 0s and 1s determines which device, of a total of 16 devices, the hardware performs as. Accordingly, the hardware itself is not physically reconfigured, but its performance is. Such a defense agent allows the attack to take place, rendering it harmless. On the other hand, if the system is already infected with malware sending out information, the defense agent allows the information to go out, rendering it meaningless. The hardware architecture is immune to side attacks since such an attack would reveal information on the attack itself and not on the hardware. This cyber defense agent can be used to secure a point-to-point, point-to-multipoint, a whole network, and/or a single entity in the cyberspace. Therefore, ensuring trust between cyber resources. It can provide secure communication in an insecure network. We provide the hardware design and explain how it works. Scalability of the design is briefly discussed. (Protected by United States Patents No.: US 8,004,734; US 8,325,404; and other National Patents worldwide.)

Communication Estimation for Hardware/Software Codesign

DEFF Research Database (Denmark)

Knudsen, Peter Voigt; Madsen, Jan

1998-01-01

This paper presents a general high level estimation model of communication throughput for the implementation of a given communication protocol. The model, which is part of a larger model that includes component price, software driver object code size and hardware driver area, is intended...... to be general enough to be able to capture the characteristics of a wide range of communication protocols and yet to be sufficiently detailed as to allow the designer or design tool to efficiently explore tradeoffs between throughput, bus widths, burst/non-burst transfers and data packing strategies. Thus...... it provides a basis for decision making with respect to communication protocols/components and communication driver design in the initial design space exploration phase of a co-synthesis process where a large number of possibilities must be examined and where fast estimators are therefore necessary. The fill...

Affix Meaning Knowledge in First Through Third Grade Students.

Science.gov (United States)

Apel, Kenn; Henbest, Victoria Suzanne

2016-04-01

We examined grade-level differences in 1st- through 3rd-grade students' performance on an experimenter-developed affix meaning task (AMT) and determined whether AMT performance explained unique variance in word-level reading and reading comprehension, beyond other known contributors to reading development. Forty students at each grade level completed an assessment battery that included measures of phonological awareness, receptive vocabulary, word-level reading, reading comprehension, and affix meaning knowledge. On the AMT, 1st-grade students were significantly less accurate than 2nd- and 3rd-grade students; there was no significant difference in performance between the 2nd- and 3rd-grade students. Regression analyses revealed that the AMT accounted for 8% unique variance of students' performance on word-level reading measures and 6% unique variance of students' performance on the reading comprehension measure, after age, phonological awareness, and receptive vocabulary were explained. These results provide initial information on the development of affix meaning knowledge via an explicit measure in 1st- through 3rd-grade students and demonstrate that affix meaning knowledge uniquely contributes to the development of reading abilities above other known literacy predictors. These findings provide empirical support for how students might use morphological problem solving to read unknown multimorphemic words successfully.

GRADE AS THE MOTIVATIONAL FACTOR IN LEARNING MATHEMATICS

Directory of Open Access Journals (Sweden)

Sead Rešić

2017-09-01

Full Text Available In this research the motivation for learning mathematics was tested,as well as the effect of grades on the motivation of primary school level students. On a sample of N=100 participants, primary school students, we conducted a survey, the results of which show that the participants are more motivated with extrinsic factors, then intrinsic factors for learning mathematics. Grades are the main factor that has the most influence on the motivation level of students for learning mathematics, because students need good grades for their further education. The results also show that punishment and rewards from parents for bad and good grades has no effect on the motivation level of students

TreeBASIS Feature Descriptor and Its Hardware Implementation

Directory of Open Access Journals (Sweden)

Spencer Fowers

2014-01-01

Full Text Available This paper presents a novel feature descriptor called TreeBASIS that provides improvements in descriptor size, computation time, matching speed, and accuracy. This new descriptor uses a binary vocabulary tree that is computed using basis dictionary images and a test set of feature region images. To facilitate real-time implementation, a feature region image is binary quantized and the resulting quantized vector is passed into the BASIS vocabulary tree. A Hamming distance is then computed between the feature region image and the effectively descriptive basis dictionary image at a node to determine the branch taken and the path the feature region image takes is saved as a descriptor. The TreeBASIS feature descriptor is an excellent candidate for hardware implementation because of its reduced descriptor size and the fact that descriptors can be created and features matched without the use of floating point operations. The TreeBASIS descriptor is more computationally and space efficient than other descriptors such as BASIS, SIFT, and SURF. Moreover, it can be computed entirely in hardware without the support of a CPU for additional software-based computations. Experimental results and a hardware implementation show that the TreeBASIS descriptor compares well with other descriptors for frame-to-frame homography computation while requiring fewer hardware resources.

Efficient Architecture for Spike Sorting in Reconfigurable Hardware

Science.gov (United States)

Hwang, Wen-Jyi; Lee, Wei-Hao; Lin, Shiow-Jyu; Lai, Sheng-Ying

2013-01-01

This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation. PMID:24189331

Efficient Architecture for Spike Sorting in Reconfigurable Hardware

Directory of Open Access Journals (Sweden)

Sheng-Ying Lai

2013-11-01

Full Text Available This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA and fuzzy C-means (FCM algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA. It is embedded in a System-on-Chip (SOC platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.

Parallel asynchronous hardware implementation of image processing algorithms

Science.gov (United States)

Coon, Darryl D.; Perera, A. G. U.

1990-01-01

Research is being carried out on hardware for a new approach to focal plane processing. The hardware involves silicon injection mode devices. These devices provide a natural basis for parallel asynchronous focal plane image preprocessing. The simplicity and novel properties of the devices would permit an independent analog processing channel to be dedicated to every pixel. A laminar architecture built from arrays of the devices would form a two-dimensional (2-D) array processor with a 2-D array of inputs located directly behind a focal plane detector array. A 2-D image data stream would propagate in neuron-like asynchronous pulse-coded form through the laminar processor. No multiplexing, digitization, or serial processing would occur in the preprocessing state. High performance is expected, based on pulse coding of input currents down to one picoampere with noise referred to input of about 10 femtoamperes. Linear pulse coding has been observed for input currents ranging up to seven orders of magnitude. Low power requirements suggest utility in space and in conjunction with very large arrays. Very low dark current and multispectral capability are possible because of hardware compatibility with the cryogenic environment of high performance detector arrays. The aforementioned hardware development effort is aimed at systems which would integrate image acquisition and image processing.

A Hybrid Hardware and Software Component Architecture for Embedded System Design

Science.gov (United States)

Marcondes, Hugo; Fröhlich, Antônio Augusto

Embedded systems are increasing in complexity, while several metrics such as time-to-market, reliability, safety and performance should be considered during the design of such systems. A component-based design which enables the migration of its components between hardware and software can cope to achieve such metrics. To enable that, we define hybrid hardware and software components as a development artifact that can be deployed by different combinations of hardware and software elements. In this paper, we present an architecture for developing such components in order to construct a repository of components that can migrate between the hardware and software domains to meet the design system requirements.

Space elevator systems level analysis

Energy Technology Data Exchange (ETDEWEB)

Laubscher, B. E. (Bryan E.)

2004-01-01

The Space Elevator (SE) represents a major paradigm shift in space access. It involves new, untried technologies in most of its subsystems. Thus the successful construction of the SE requires a significant amount of development, This in turn implies a high level of risk for the SE. This paper will present a systems level analysis of the SE by subdividing its components into their subsystems to determine their level of technological maturity. such a high-risk endeavor is to follow a disciplined approach to the challenges. A systems level analysis informs this process and is the guide to where resources should be applied in the development processes. It is an efficient path that, if followed, minimizes the overall risk of the system's development. systems level analysis is that the overall system is divided naturally into its subsystems, and those subsystems are further subdivided as appropriate for the analysis. By dealing with the complex system in layers, the parameter space of decisions is kept manageable. Moreover, A rational way to manage One key aspect of a resources are not expended capriciously; rather, resources are put toward the biggest challenges and most promising solutions. This overall graded approach is a proven road to success. The analysis includes topics such as nanotube technology, deployment scenario, power beaming technology, ground-based hardware and operations, ribbon maintenance and repair and climber technology.

Forecasting and recruitment in graded manpower systems

NARCIS (Netherlands)

van Nunen, J.A.E.E.; Wessels, J.

1977-01-01

In this paper a generalized Markov model is introduced to describe the dynamic behaviour of an individual employee in a graded Manpower system. Characteristics like the employee's grade, his educational level, his age and the time spent in his actual grade, can be incorporated in the Markov model.

BIOLOGICALLY INSPIRED HARDWARE CELL ARCHITECTURE

DEFF Research Database (Denmark)

2010-01-01

Disclosed is a system comprising: - a reconfigurable hardware platform; - a plurality of hardware units defined as cells adapted to be programmed to provide self-organization and self-maintenance of the system by means of implementing a program expressed in a programming language defined as DNA...... language, where each cell is adapted to communicate with one or more other cells in the system, and where the system further comprises a converter program adapted to convert keywords from the DNA language to a binary DNA code; where the self-organisation comprises that the DNA code is transmitted to one...... or more of the cells, and each of the one or more cells is adapted to determine its function in the system; where if a fault occurs in a first cell and the first cell ceases to perform its function, self-maintenance is performed by that the system transmits information to the cells that the first cell has...

Travel Software using GPU Hardware

CERN Document Server

Szalwinski, Chris M; Dimov, Veliko Atanasov; CERN. Geneva. ATS Department

2015-01-01

Travel is the main multi-particle tracking code being used at CERN for the beam dynamics calculations through hadron and ion linear accelerators. It uses two routines for the calculation of space charge forces, namely, rings of charges and point-to-point. This report presents the studies to improve the performance of Travel using GPU hardware. The studies showed that the performance of Travel with the point-to-point simulations of space-charge effects can be speeded up at least 72 times using current GPU hardware. Simple recompilation of the source code using an Intel compiler can improve performance at least 4 times without GPU support. The limited memory of the GPU is the bottleneck. Two algorithms were investigated on this point: repeated computation and tiling. The repeating computation algorithm is simpler and is the currently recommended solution. The tiling algorithm was more complicated and degraded performance. Both build and test instructions for the parallelized version of the software are inclu...

The principles of computer hardware

CERN Document Server

Clements, Alan

2000-01-01

Principles of Computer Hardware, now in its third edition, provides a first course in computer architecture or computer organization for undergraduates. The book covers the core topics of such a course, including Boolean algebra and logic design; number bases and binary arithmetic; the CPU; assembly language; memory systems; and input/output methods and devices. It then goes on to cover the related topics of computer peripherals such as printers; the hardware aspects of the operating system; and data communications, and hence provides a broader overview of the subject. Its readable, tutorial-based approach makes it an accessible introduction to the subject. The book has extensive in-depth coverage of two microprocessors, one of which (the 68000) is widely used in education. All chapters in the new edition have been updated. Major updates include: powerful software simulations of digital systems to accompany the chapters on digital design; a tutorial-based introduction to assembly language, including many exam...

Multi-User Hardware Solutions to Combustion Science ISS Research

Science.gov (United States)

Otero, Angel M.

2001-01-01

In response to the budget environment and to expand on the International Space Station (ISS) Fluids and Combustion Facility (FCF) Combustion Integrated Rack (CIR), common hardware approach, the NASA Combustion Science Program shifted focus in 1999 from single investigator PI (Principal Investigator)-specific hardware to multi-user 'Minifacilities'. These mini-facilities would take the CIR common hardware philosophy to the next level. The approach that was developed re-arranged all the investigations in the program into sub-fields of research. Then common requirements within these subfields were used to develop a common system that would then be complemented by a few PI-specific components. The sub-fields of research selected were droplet combustion, solids and fire safety, and gaseous fuels. From these research areas three mini-facilities have sprung: the Multi-user Droplet Combustion Apparatus (MDCA) for droplet research, Flow Enclosure for Novel Investigations in Combustion of Solids (FEANICS) for solids and fire safety, and the Multi-user Gaseous Fuels Apparatus (MGFA) for gaseous fuels. These mini-facilities will develop common Chamber Insert Assemblies (CIA) and diagnostics for the respective investigators complementing the capability provided by CIR. Presently there are four investigators for MDCA, six for FEANICS, and four for MGFA. The goal of these multi-user facilities is to drive the cost per PI down after the initial development investment is made. Each of these mini-facilities will become a fixture of future Combustion Science NASA Research Announcements (NRAs), enabling investigators to propose against an existing capability. Additionally, an investigation is provided the opportunity to enhance the existing capability to bridge the gap between the capability and their specific science requirements. This multi-user development approach will enable the Combustion Science Program to drive cost per investigation down while drastically reducing the time

Hardware and software for image acquisition in nuclear medicine

International Nuclear Information System (INIS)

Fideles, E.L.; Vilar, G.; Silva, H.S.

1992-01-01

A system for image acquisition and processing in nuclear medicine is presented, including the hardware and software referring to acquisition. The hardware is consisted of an analog-digital conversion card, developed in wire-wape. Its function is digitate the analogic signs provided by gamma camera. The acquisitions are made in list or frame mode. (C.G.C.)

The Hardware Topological Trigger of ATLAS: Commissioning and Operations

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00226165; The ATLAS collaboration

2018-01-01

The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system with an output rate of 100 kHz and decision latency smaller than 2.5 μs. It consists of a calorimeter trigger, muon trigger and a central trigger processor. To improve the physics potential reach in ATLAS, during the LHC shutdown after Run 1, the Level-1 trigger system was upgraded at hardware, firmware and software level. In particular, a new electronics sub-system was introduced in the real-time data processing path: the Topological Processor System (L1Topo). It consists of a single AdvancedCTA shelf equipped with two Level-1 topological processor blades. For individual blades, real-time information from calorimeter and muon Level-1 trigger systems, is processed by four individual state-of-the-art FPGAs. It needs to deal with a large input bandwidth of up to 6 Tb/s, optical connectivity and low processing latency on the real-time data path. The L1Topo firmware apply measurements of angles between jets and/or leptons and several...

Hardware Realization of Chaos-based Symmetric Video Encryption

KAUST Repository

Ibrahim, Mohamad A.

2013-05-01

This thesis reports original work on hardware realization of symmetric video encryption using chaos-based continuous systems as pseudo-random number generators. The thesis also presents some of the serious degradations caused by digitally implementing chaotic systems. Subsequently, some techniques to eliminate such defects, including the ultimately adopted scheme are listed and explained in detail. Moreover, the thesis describes original work on the design of an encryption system to encrypt MPEG-2 video streams. Information about the MPEG-2 standard that fits this design context is presented. Then, the security of the proposed system is exhaustively analyzed and the performance is compared with other reported systems, showing superiority in performance and security. The thesis focuses more on the hardware and the circuit aspect of the system’s design. The system is realized on Xilinx Vetrix-4 FPGA with hardware parameters and throughput performance surpassing conventional encryption systems.

Hardware and software constructs for a vibration analysis network

International Nuclear Information System (INIS)

Cook, S.A.; Crowe, R.D.; Toffer, H.

1985-01-01

Vibration level monitoring and analysis has been initiated at N Reactor, the dual purpose reactor operated at Hanford, Washington by UNC Nuclear Industries (UNC) for the Department of Energy (DOE). The machinery to be monitored was located in several buildings scattered over the plant site, necessitating an approach using satellite stations to collect, monitor and temporarily store data. The satellite stations are, in turn, linked to a centralized processing computer for further analysis. The advantages of a networked data analysis system are discussed in this paper along with the hardware and software required to implement such a system

The Relationship between Readability Level of Mississippi's Middle Schools' Websites and Seventh Grade Language Arts MCT2 Scores

Science.gov (United States)

Pickard, Anna Marlene Graves

2011-01-01

Today's educators face the unprecedented challenge of increasing achievement for all students. One response has been to increase and improve parent involvement and school-to-home communication through the use of school websites. The quantitative section of this study analyzed the readability grade level of the website as it relates to state test…

A Comparative Analysis of Multiple Intelligence Theory with Relationship to Gender and Grade Level in Selected Schools in Ghana

Science.gov (United States)

Oteng, Ellen N.

2012-01-01

This dissertation examined the relationships between Howard Gardner's Multiple Intelligence Theory and students' gender, age, grade level, and enrollment into a public or private school. The research determined students' dominant intelligences and investigated whether students' intelligences may be influenced by demographic variables such as…

Systematic development of industrial control systems using Software/Hardware Engineering

NARCIS (Netherlands)

Voeten, J.P.M.; van der Putten, P.H.A.; Stevens, M.P.J.; Milligan, P.; Corr, P.

1997-01-01

SHE (Software/Hardware Engineering) is a new object-oriented analysis, specification and design method for complex reactive hardware/software systems. SHE is based on the formal specification language POOSL and a design framework guiding analysis and design activities. This paper reports on the

CT image reconstruction system based on hardware implementation

International Nuclear Information System (INIS)

Silva, Hamilton P. da; Evseev, Ivan; Schelin, Hugo R.; Paschuk, Sergei A.; Milhoretto, Edney; Setti, Joao A.P.; Zibetti, Marcelo; Hormaza, Joel M.; Lopes, Ricardo T.

2009-01-01

Full text: The timing factor is very important for medical imaging systems, which can nowadays be synchronized by vital human signals, like heartbeats or breath. The use of hardware implemented devices in such a system has advantages considering the high speed of information treatment combined with arbitrary low cost on the market. This article refers to a hardware system which is based on electronic programmable logic called FPGA, model Cyclone II from ALTERA Corporation. The hardware was implemented on the UP3 ALTERA Kit. A partially connected neural network with unitary weights was programmed. The system was tested with 60 topographic projections, 100 points in each, of the Shepp and Logan phantom created by MATLAB. The main restriction was found to be the memory size available on the device: the dynamic range of reconstructed image was limited to 0 65535. Also, the normalization factor must be observed in order to do not saturate the image during the reconstruction and filtering process. The test shows a principal possibility to build CT image reconstruction systems for any reasonable amount of input data by arranging the parallel work of the hardware units like we have tested. However, further studies are necessary for better understanding of the error propagation from topographic projections to reconstructed image within the implemented method. (author)

Hardware Implementation Of Line Clipping A lgorithm By Using FPGA

Directory of Open Access Journals (Sweden)

Amar Dawod

2013-04-01

Full Text Available The computer graphics system performance is increasing faster than any other computing application. Algorithms for line clipping against convex polygons and lines have been studied for a long time and many research papers have been published so far. In spite of the latest graphical hardware development and significant increase of performance the clipping is still a bottleneck of any graphical system. So its implementation in hardware is essential for real time applications. In this paper clipping operation is discussed and a hardware implementation of the line clipping algorithm is presented and finally formulated and tested using Field Programmable Gate Arrays (FPGA. The designed hardware unit consists of two parts : the first is positional code generator unit and the second is the clipping unit. Finally it is worth mentioning that the  designed unit is capable of clipping (232524 line segments per second.       

Hardware based redundant multi-threading inside a GPU for improved reliability

Science.gov (United States)

Sridharan, Vilas; Gurumurthi, Sudhanva

2015-05-05

A system and method for verifying computation output using computer hardware are provided. Instances of computation are generated and processed on hardware-based processors. As instances of computation are processed, each instance of computation receives a load accessible to other instances of computation. Instances of output are generated by processing the instances of computation. The instances of output are verified against each other in a hardware based processor to ensure accuracy of the output.

Basics of spectroscopic instruments. Hardware of NMR spectrometer

International Nuclear Information System (INIS)

Sato, Hajime

2009-01-01

NMR is a powerful tool for structure analysis of small molecules, natural products, biological macromolecules, synthesized polymers, samples from material science and so on. Magnetic Resonance Imaging (MRI) is applicable to plants and animals Because most of NMR experiments can be done by an automation mode, one can forget hardware of NMR spectrometers. It would be good to understand features and performance of NMR spectrometers. Here I present hardware of a modern NMR spectrometer which is fully equipped with digital technology. (author)

A Hardware Lab Anywhere At Any Time

Directory of Open Access Journals (Sweden)

Tobias Schubert

2004-12-01

Full Text Available Scientific technical courses are an important component in any student's education. These courses are usually characterised by the fact that the students execute experiments in special laboratories. This leads to extremely high costs and a reduction in the maximum number of possible participants. From this traditional point of view, it doesn't seem possible to realise the concepts of a Virtual University in the context of sophisticated technical courses since the students must be "on the spot". In this paper we introduce the so-called Mobile Hardware Lab which makes student participation possible at any time and from any place. This lab nevertheless transfers a feeling of being present in a laboratory. This is accomplished with a special Learning Management System in combination with hardware components which correspond to a fully equipped laboratory workstation that are lent out to the students for the duration of the lab. The experiments are performed and solved at home, then handed in electronically. Judging and marking are also both performed electronically. Since 2003 the Mobile Hardware Lab is now offered in a completely web based form.

Motion compensation in digital subtraction angiography using graphics hardware.

Science.gov (United States)

Deuerling-Zheng, Yu; Lell, Michael; Galant, Adam; Hornegger, Joachim

2006-07-01

An inherent disadvantage of digital subtraction angiography (DSA) is its sensitivity to patient motion which causes artifacts in the subtraction images. These artifacts could often reduce the diagnostic value of this technique. Automated, fast and accurate motion compensation is therefore required. To cope with this requirement, we first examine a method explicitly designed to detect local motions in DSA. Then, we implement a motion compensation algorithm by means of block matching on modern graphics hardware. Both methods search for maximal local similarity by evaluating a histogram-based measure. In this context, we are the first who have mapped an optimizing search strategy on graphics hardware while paralleling block matching. Moreover, we provide an innovative method for creating histograms on graphics hardware with vertex texturing and frame buffer blending. It turns out that both methods can effectively correct the artifacts in most case, as the hardware implementation of block matching performs much faster: the displacements of two 1024 x 1024 images can be calculated at 3 frames/s with integer precision or 2 frames/s with sub-pixel precision. Preliminary clinical evaluation indicates that the computation with integer precision could already be sufficient.

Classification of Living Things. A Teacher's Manual for General Level Program Development. Grades 7 and 8. Science and Society Teaching Units. Informal Series/55.

Science.gov (United States)

Roberts, Douglas A.; And Others

This manual is one of a series designed to assist junior high school teachers in developing general level or non-academic science programs which focus on the relationship between science and society. Although designed primarily for grades 7 and 8, the content is also suitable for students in grade 6. The major portion of the manual consists of six…

Hardware packet pacing using a DMA in a parallel computer

Science.gov (United States)

Chen, Dong; Heidelberger, Phillip; Vranas, Pavlos

2013-08-13

Method and system for hardware packet pacing using a direct memory access controller in a parallel computer which, in one aspect, keeps track of a total number of bytes put on the network as a result of a remote get operation, using a hardware token counter.

The priority queue as an example of hardware/software codesign

DEFF Research Database (Denmark)

Høeg, Flemming; Mellergaard, Niels; Staunstrup, Jørgen

1994-01-01

The paper identifies a number of issues that are believed to be important for hardware/software codesign. The issues are illustrated by a small comprehensible example: a priority queue. Based on simulations of a real application, we suggest a combined hardware/software realization of the priority...

Commercial off-the-shelf software dedication process based on the commercial grade survey of supplier

International Nuclear Information System (INIS)

Kim, J. Y.; Lee, J. S.; Chon, S. W.; Lee, G. Y.; Park, J. K.

2000-01-01

Commercial Off-The-Shelf(COTS) software dedication process can apply to a combination of methods like the hardware commercial grade item dedication process. In general, these methods are : methods 1(special test and inspection), method 2(commercial grade survey of supplier), method 3(source verification), and method 4(acceptance supplier/item performance record). In this paper, the suggested procedure-oriented dedication process on the basis of method 2 for COTS software is consistent with EPRI/TR-106439 and NUREG/CR-6421 requirements. Additional tailoring policy based on code and standards related to COTS software may be also founded in the suggested commercial software dedication process. Suggested commercial software dedication process has been developed for a commercial I and C software dedication who performs COTS qualification according to the dedication procedure

Hardware characteristic and application

International Nuclear Information System (INIS)

Gu, Dong Hyeon

1990-03-01

The contents of this book are system board on memory, performance, system timer system click and specification, coprocessor such as programing interface and hardware interface, power supply on input and output, protection for DC output, Power Good signal, explanation on 84 keyboard and 101/102 keyboard,BIOS system, 80286 instruction set and 80287 coprocessor, characters, keystrokes and colors, communication and compatibility of IBM personal computer on application direction, multitasking and code for distinction of system.

Hardware architecture design of image restoration based on time-frequency domain computation

Science.gov (United States)

Wen, Bo; Zhang, Jing; Jiao, Zipeng

2013-10-01

The image restoration algorithms based on time-frequency domain computation is high maturity and applied widely in engineering. To solve the high-speed implementation of these algorithms, the TFDC hardware architecture is proposed. Firstly, the main module is designed, by analyzing the common processing and numerical calculation. Then, to improve the commonality, the iteration control module is planed for iterative algorithms. In addition, to reduce the computational cost and memory requirements, the necessary optimizations are suggested for the time-consuming module, which include two-dimensional FFT/IFFT and the plural calculation. Eventually, the TFDC hardware architecture is adopted for hardware design of real-time image restoration system. The result proves that, the TFDC hardware architecture and its optimizations can be applied to image restoration algorithms based on TFDC, with good algorithm commonality, hardware realizability and high efficiency.

Automating an EXAFS facility: hardware and software considerations

International Nuclear Information System (INIS)

Georgopoulos, P.; Sayers, D.E.; Bunker, B.; Elam, T.; Grote, W.A.

1981-01-01

The basic design considerations for computer hardware and software, applicable not only to laboratory EXAFS facilities, but also to synchrotron installations, are reviewed. Uniformity and standardization of both hardware configurations and program packages for data collection and analysis are heavily emphasized. Specific recommendations are made with respect to choice of computers, peripherals, and interfaces, and guidelines for the development of software packages are set forth. A description of two working computer-interfaced EXAFS facilities is presented which can serve as prototypes for future developments. 3 figures

Hardware-in-the-Loop Co-simulation of Distribution Grid for Demand Response

Energy Technology Data Exchange (ETDEWEB)

Rotger-Griful, Sergi; Chatzivasileiadis, Spyros; Jacobsen, Rune H.; Stewart, Emma M.; Domingo, Javier M.; Wetter, Michael

2016-06-20

In modern power systems, co-simulation is proposed as an enabler for analyzing the interactions between disparate systems. This paper introduces the co-simulation platform Virtual Grid Integration Laboratory (VirGIL) including Hardware-in-the-Loop testing, and demonstrates its potential to assess demand response strategies. VirGIL is based on a modular architecture using the Functional Mock-up Interface industrial standard to integrate new simulators. VirGIL combines state-of-the-art simulators in power systems, communications, buildings, and control. In this work, VirGIL is extended with a Hardware-in-the-Loop component to control the ventilation system of a real 12-story building in Denmark. VirGIL capabilities are illustrated in three scenarios: load following, primary reserves and load following aggregation. Experimental results show that the system can track one minute changing signals and it can provide primary reserves for up-regulation. Furthermore, the potential of aggregating several ventilation systems is evaluated considering the impact at distribution grid level and the communications protocol effect.

Fault Detection, Isolation and Recovery (FDIR) Portable Liquid Oxygen Hardware Demonstrator

Science.gov (United States)

Oostdyk, Rebecca L.; Perotti, Jose M.

2011-01-01

The Fault Detection, Isolation and Recovery (FDIR) hardware demonstration will highlight the effort being conducted by Constellation's Ground Operations (GO) to provide the Launch Control System (LCS) with system-level health management during vehicle processing and countdown activities. A proof-of-concept demonstration of the FDIR prototype established the capability of the software to provide real-time fault detection and isolation using generated Liquid Hydrogen data. The FDIR portable testbed unit (presented here) aims to enhance FDIR by providing a dynamic simulation of Constellation subsystems that feed the FDIR software live data based on Liquid Oxygen system properties. The LO2 cryogenic ground system has key properties that are analogous to the properties of an electronic circuit. The LO2 system is modeled using electrical components and an equivalent circuit is designed on a printed circuit board to simulate the live data. The portable testbed is also be equipped with data acquisition and communication hardware to relay the measurements to the FDIR application running on a PC. This portable testbed is an ideal capability to perform FDIR software testing, troubleshooting, training among others.

Linguistic Resources Used in Grade 8 Students' Submicro Level Explanations—Science Items from TIMSS 2007

Science.gov (United States)

Frändberg, Birgitta; Lincoln, Per; Wallin, Anita

2013-12-01

Explanations involving submicro levels of representation are central to science education, but known to be difficult for students in secondary school. This study examines students' written explanations of physical and chemical phenomena regarding matter and changes in matter, in a large-scale test. This is done in order to understand linguistic challenges in constructing submicro level explanations involving the particle model of matter. Drawing from systemic functional linguistics, the lexicogrammatics used in explanations for realising experiential meaning in student explanations were analysed. We used answers to two partly constructed response items from the Swedish part of Trends in International Mathematics and Science Studies 2007, grade 8, to sort out explanations referring to the particle model of matter. These answers (86 from 954) were analysed regarding choices of vocabulary and grammar to distinguish between macro and submicro level of representation. The results show that students use a wide variety of lexicogrammatical resources to realise what happens on both macro and submicro level of representation, with greater diversity of verbs on the submicro level of explanation. The results suggest an uncertainty about the distinction between macro and submicro level of explanation.

Commodity hardware and software summary

International Nuclear Information System (INIS)

Wolbers, S.

1997-04-01

A review is given of the talks and papers presented in the Commodity Hardware and Software Session at the CHEP97 conference. An examination of the trends leading to the consideration of PC's for HEP is given, and a status of the work that is being done at various HEP labs and Universities is given

A Fast Hardware Tracker for the ATLAS Trigger System

CERN Document Server

Kimura, N; The ATLAS collaboration

2012-01-01

Selecting interesting events with triggering is very challenging at the LHC due to the busy hadronic environment. Starting in 2014 the LHC will run with an energy of 13 or 14 TeV and instantaneous luminosities which could exceed 1034 interactions per cm2 and per second. The triggering in the ATLAS detector is realized using a three level trigger approach, in which the first level (Level-1) is hardware based and the second (Level-2) and third (EF) stag are realized using large computing farms. It is a crucial and non-trivial task for triggering to maintain a high efficiency for events of interest while suppressing effectively the very high rates of inclusive QCD process, which constitute mainly background. At the same time the trigger system has to be robust and provide sufficient operational margins to adapt to changes in the running environment. In the current design track reconstruction can be performed only in limited regions of interest at L2 and the CPU requirements may limit this even further at the hig...

Plutonium Finishing Plant (PFP) Criticality Alarm System Commercial Grade Item (CGI) Critical Characteristics

International Nuclear Information System (INIS)

WHITE, W.F.

1999-01-01

This document specifies the critical characteristics for Commercial Grade Items (CGI) procured for PFP's criticality alarm system as required by HNF-PRO-268 and HNF-PRO-1819. These are the minimum specifications that the equipment must meet in order to properly perform its safety function. There may be several manufacturers or models that meet the critical characteristics for any one item. PFP's Criticality Alarm System includes the nine criticality alarm system panels and their associated hardware. This includes all parts up to the first breaker in the electrical distribution system. Specific system boundaries and justifications are contained in HNF-SD-CP-SDD-003, ''Definition and Means of Maintaining the Criticality Detectors and Alarms Portion of the PFP Safety Envelope.'' The procurement requirements associated with the system necessitates procurement of some system equipment as Commercial Grade Items in accordance with HNF-PRO-268, ''Control of Purchased Items and Services.''

Contamination Control and Hardware Processing Solutions at Marshall Space Flight Center

Science.gov (United States)

Burns, DeWitt H.; Hampton, Tammy; Huey, LaQuieta; Mitchell, Mark; Norwood, Joey; Lowrey, Nikki

2012-01-01

The Contamination Control Team of Marshall Space Flight Center's Materials and Processes Laboratory supports many Programs/ Projects that design, manufacture, and test a wide range of hardware types that are sensitive to contamination and foreign object damage (FOD). Examples where contamination/FOD concerns arise include sensitive structural bondline failure, critical orifice blockage, seal leakage, and reactive fluid compatibility (liquid oxygen, hydrazine) as well as performance degradation of sensitive instruments or spacecraft surfaces such as optical elements and thermal control systems. During the design phase, determination of the sensitivity of a hardware system to different types or levels of contamination/FOD is essential. A contamination control and FOD control plan must then be developed and implemented through all phases of ground processing, and, sometimes, on-orbit use, recovery, and refurbishment. Implementation of proper controls prevents cost and schedule impacts due to hardware damage or rework and helps assure mission success. Current capabilities are being used to support recent and on-going activities for multiple Mission Directorates / Programs such as International Space Station (ISS), James Webb Space Telescope (JWST), Space Launch System (SLS) elements (tanks, engines, booster), etc. The team also advances Green Technology initiatives and addresses materials obsolescence issues for NASA and external customers, most notably in the area of solvent replacement (e.g. aqueous cleaners containing hexavalent chrome, ozone depleting chemicals (CFC s and HCFC's), suspect carcinogens). The team evaluates new surface cleanliness inspection and cleaning technologies (e.g. plasma cleaning), and maintains databases for processing support materials as well as outgassing and optical compatibility test results for spaceflight environments.

Surface moisture measurement system hardware acceptance test report

Energy Technology Data Exchange (ETDEWEB)

Ritter, G.A., Westinghouse Hanford

1996-05-28

This document summarizes the results of the hardware acceptance test for the Surface Moisture Measurement System (SMMS). This test verified that the mechanical and electrical features of the SMMS functioned as designed and that the unit is ready for field service. The bulk of hardware testing was performed at the 306E Facility in the 300 Area and the Fuels and Materials Examination Facility in the 400 Area. The SMMS was developed primarily in support of Tank Waste Remediation System (TWRS) Safety Programs for moisture measurement in organic and ferrocyanide watch list tanks.

Registration Patterns Under Two Different Grading Systems.

Science.gov (United States)

Remley, Audrey W.

In the early 1960's, Westminster College adopted a new grading system, with the traditional grade levels of A, B, C, D, and F converted to DN (Distinction), HP (High Pass), P (Pass), and NC (No Credit). NC replaced both D and F of the old system, and grade point averages were abolished, in an effort to encourage students to register in more…

Terrestrial Sources of X-Ray Radiation and Their Effects on NASA Flight Hardware

Science.gov (United States)

Kniffin, Scott

2016-01-01

X-rays are an energetic and penetrating form of ionizing electromagnetic radiation, which can degrade NASA flight hardware. The main concern posed by such radiation is degradation of active electronic devices and, in some cases, diodes. Non-electronic components are only damaged at doses that far exceed the point where any electronic device would be destroyed. For the purposes of this document, flight hardware can be taken to mean an entire instrument, the flight electronics within the instrument or the individual microelectronic devices in the flight electronics. This document will discuss and describe the ways in which NASA flight hardware might be exposed to x-rays, what is and isn't a concern, and how to tell the difference. First, we must understand what components in flight hardware may be vulnerable to degradation or failure as a result of being exposed to ionizing radiation, such as x-rays. As stated above, bulk materials (structural metals, plastics, etc.) are generally only affected by ionizing radiation at very high dose levels. Likewise, passive electronic components (e.g. resistors, capacitors, most diodes) are strongly resistant to exposure to x-rays, except at very high doses. The main concerns arise when active components, that is, components like discrete transistors and microelectronic devices, are exposed to ionizing radiation. Active components are designed to respond to minute changes in currents and voltages in the circuit. As such, it is not surprising that exposure to ionizing radiation, which creates ionized and therefore electrically active particles, may degrade the way the hardware performs. For the most part, the mechanism for this degradation is trapping of the charges generated by ionizing radiation by defects in dielectric materials in the hardware. As such, the degree of damage is a function of both the quantity of ionizing radiation exposure and the physical characteristics of the hardware itself. The metric that describes the

The role of the visual hardware system in rugby performance ...

African Journals Online (AJOL)

This study explores the importance of the 'hardware' factors of the visual system in the game of rugby. A group of professional and club rugby players were tested and the results compared. The results were also compared with the established norms for elite athletes. The findings indicate no significant difference in hardware ...

OER Approach for Specific Student Groups in Hardware-Based Courses

Science.gov (United States)

Ackovska, Nevena; Ristov, Sasko

2014-01-01

Hardware-based courses in computer science studies require much effort from both students and teachers. The most important part of students' learning is attending in person and actively working on laboratory exercises on hardware equipment. This paper deals with a specific group of students, those who are marginalized by not being able to…

49 CFR 238.105 - Train electronic hardware and software safety.

Science.gov (United States)

2010-10-01

... and software system safety as part of the pre-revenue service testing of the equipment. (d)(1... safely by initiating a full service brake application in the event of a hardware or software failure that... 49 Transportation 4 2010-10-01 2010-10-01 false Train electronic hardware and software safety. 238...

A Study of Light Level Effect on the Accuracy of Image Processing-based Tomato Grading

Science.gov (United States)

Prijatna, D.; Muhaemin, M.; Wulandari, R. P.; Herwanto, T.; Saukat, M.; Sugandi, W. K.

2018-05-01

Image processing method has been used in non-destructive tests of agricultural products. Compared to manual method, image processing method may produce more objective and consistent results. Image capturing box installed in currently used tomato grading machine (TEP-4) is equipped with four fluorescence lamps to illuminate the processed tomatoes. Since the performance of any lamp will decrease if its service time has exceeded its lifetime, it is predicted that this will affect tomato classification. The objective of this study was to determine the minimum light levels which affect classification accuracy. This study was conducted by varying light level from minimum and maximum on tomatoes in image capturing boxes and then investigates its effects on image characteristics. Research results showed that light intensity affects two variables which are important for classification, for example, area and color of captured image. Image processing program was able to determine correctly the weight and classification of tomatoes when light level was 30 lx to 140 lx.

EMMPRIN expression positively correlates with WHO grades of astrocytomas and meningiomas.

Science.gov (United States)

Tsai, Wen-Chiuan; Chen, Ying; Huang, Li-Chun; Lee, Herng-Sheng; Ma, Hsin-I; Huang, Shih-Ming; Sytwu, Huey-Kang; Hueng, Dueng-Yuan

2013-09-01

High-grade primary brain tumors possessed poor outcome due to invasiveness. Extracellular matrix metalloproteinase inducer (EMMPRIN) stimulates peri-tumoral fibroblasts to secrete matrix metalloproteinase and promote invasiveness. This study hypothesized that high-grade brain tumors overexpress EMMPRIN. Analyzing the public delinked database from the Gene Expression Omnibus profile, the results showed that the EMMPRIN mRNA level was higher in WHO grade IV (n = 81) than in grade III (n = 19, p EMMPRIN levels positively correlated with WHO grades for astrocytomas (p = 0.008) and meningiomas (p = 0.048). EMMPRIN mRNA levels in conventional glioma cell lines (n = 36) was not less than those in glioma primary culture cells (n = 27) and glioblastoma stem-like cells (n = 12). The GBM8401, U87MG, and LN229 human glioma cell lines also overexpressed EMMPRIN. Hematoxylin and eosin, IHC, and immunofluorescence staining of xenografts confirmed that high-grade brain tumors overexpressed EMMPRIN. Lastly, Kaplan-Meier analysis revealed poorer survival in WHO grade IV (n = 56) than in grade III astrocytomas (n = 21, by log-rank test; p = 0.0001, 95 % CI: 1.842-3.053). However, in high-grade astrocytomas, there was no difference in survival between high and low EMMPRIN mRNA levels. Thus, this study identified that high-grade brain tumors overexpress EMMPRIN, which positively correlates with WHO grades in human astrocytomas and meningiomas, and suggests that EMMPRIN may be a therapeutic target of brain tumor.

A Framework for Hardware-Accelerated Services Using Partially Reconfigurable SoCs

Directory of Open Access Journals (Sweden)

MACHIDON, O. M.

2016-05-01

Full Text Available The current trend towards ?Everything as a Service? fosters a new approach on reconfigurable hardware resources. This innovative, service-oriented approach has the potential of bringing a series of benefits for both reconfigurable and distributed computing fields by favoring a hardware-based acceleration of web services and increasing service performance. This paper proposes a framework for accelerating web services by offloading the compute-intensive tasks to reconfigurable System-on-Chip (SoC devices, as integrated IP (Intellectual Property cores. The framework provides a scalable, dynamic management of the tasks and hardware processing cores, based on dynamic partial reconfiguration of the SoC. We have enhanced security of the entire system by making use of the built-in detection features of the hardware device and also by implementing active counter-measures that protect the sensitive data.

Outline of a Hardware Reconfiguration Framework for Modular Industrial Mobile Manipulators

DEFF Research Database (Denmark)

Schou, Casper; Bøgh, Simon; Madsen, Ole

2014-01-01

This paper presents concepts and ideas of a hard- ware reconfiguration framework for modular industrial mobile manipulators. Mobile manipulators pose a highly flexible pro- duction resource due to their ability to autonomously navigate between workstations. However, due to this high flexibility new...... approaches to the operation of the robots are needed. Reconfig- uring the robot to a new task should be carried out by shop floor operators and, thus, be both quick and intuitive. Late research has already proposed a method for intuitive robot programming. However, this relies on a predetermined hardware...... configuration. Finding a single multi-purpose hardware configuration suited to all tasks is considered unrealistic. As a result, the need for reconfiguration of the hardware is inevitable. In this paper an outline of a framework for making hardware reconfiguration quick and intuitive is presented. Two main...

Optimized hardware design for the divertor remote handling control system

Energy Technology Data Exchange (ETDEWEB)

Saarinen, Hannu [Tampere University of Technology, Korkeakoulunkatu 6, 33720 Tampere (Finland)], E-mail: hannu.saarinen@tut.fi; Tiitinen, Juha; Aha, Liisa; Muhammad, Ali; Mattila, Jouni; Siuko, Mikko; Vilenius, Matti [Tampere University of Technology, Korkeakoulunkatu 6, 33720 Tampere (Finland); Jaervenpaeae, Jorma [VTT Systems Engineering, Tekniikankatu 1, 33720 Tampere (Finland); Irving, Mike; Damiani, Carlo; Semeraro, Luigi [Fusion for Energy, Josep Pla 2, Torres Diagonal Litoral B3, 08019 Barcelona (Spain)

2009-06-15

A key ITER maintenance activity is the exchange of the divertor cassettes. One of the major focuses of the EU Remote Handling (RH) programme has been the study and development of the remote handling equipment necessary for divertor exchange. The current major step in this programme involves the construction of a full scale physical test facility, namely DTP2 (Divertor Test Platform 2), in which to demonstrate and refine the RH equipment designs for ITER using prototypes. The major objective of the DTP2 project is the proof of concept studies of various RH devices, but is also important to define principles for standardizing control hardware and methods around the ITER maintenance equipment. This paper focuses on describing the control system hardware design optimization that is taking place at DTP2. Here there will be two RH movers, namely the Cassette Multifuctional Mover (CMM), Cassette Toroidal Mover (CTM) and assisting water hydraulic force feedback manipulators (WHMAN) located aboard each Mover. The idea here is to use common Real Time Operating Systems (RTOS), measurement and control IO-cards etc. for all maintenance devices and to standardize sensors and control components as much as possible. In this paper, new optimized DTP2 control system hardware design and some initial experimentation with the new DTP2 RH control system platform are presented. The proposed new approach is able to fulfil the functional requirements for both Mover and Manipulator control systems. Since the new control system hardware design has reduced architecture there are a number of benefits compared to the old approach. The simplified hardware solution enables the use of a single software development environment and a single communication protocol. This will result in easier maintainability of the software and hardware, less dependence on trained personnel, easier training of operators and hence reduced the development costs of ITER RH.

Security challenges and opportunities in adaptive and reconfigurable hardware

OpenAIRE

Costan, Victor Marius; Devadas, Srinivas

2011-01-01

We present a novel approach to building hardware support for providing strong security guarantees for computations running in the cloud (shared hardware in massive data centers), while maintaining the high performance and low cost that make cloud computing attractive in the first place. We propose augmenting regular cloud servers with a Trusted Computation Base (TCB) that can securely perform high-performance computations. Our TCB achieves cost savings by spreading functionality across two pa...

Review of Maxillofacial Hardware Complications and Indications for Salvage

OpenAIRE

Hernandez Rosa, Jonatan; Villanueva, Nathaniel L.; Sanati-Mehrizy, Paymon; Factor, Stephanie H.; Taub, Peter J.

2015-01-01

From 2002 to 2006, more than 117,000 facial fractures were recorded in the U.S. National Trauma Database. These fractures are commonly treated with open reduction and internal fixation. While in place, the hardware facilitates successful bony union. However, when postoperative complications occur, the plates may require removal before bony union. Indications for salvage versus removal of the maxillofacial hardware are not well defined. A literature review was performed to identify instances w...

Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware.

Science.gov (United States)

Rast, Alexander; Galluppi, Francesco; Davies, Sergio; Plana, Luis; Patterson, Cameron; Sharp, Thomas; Lester, David; Furber, Steve

2011-11-01

Dedicated hardware is becoming increasingly essential to simulate emerging very-large-scale neural models. Equally, however, it needs to be able to support multiple models of the neural dynamics, possibly operating simultaneously within the same system. This may be necessary either to simulate large models with heterogeneous neural types, or to simplify simulation and analysis of detailed, complex models in a large simulation by isolating the new model to a small subpopulation of a larger overall network. The SpiNNaker neuromimetic chip is a dedicated neural processor able to support such heterogeneous simulations. Implementing these models on-chip uses an integrated library-based tool chain incorporating the emerging PyNN interface that allows a modeller to input a high-level description and use an automated process to generate an on-chip simulation. Simulations using both LIF and Izhikevich models demonstrate the ability of the SpiNNaker system to generate and simulate heterogeneous networks on-chip, while illustrating, through the network-scale effects of wavefront synchronisation and burst gating, methods that can provide effective behavioural abstractions for large-scale hardware modelling. SpiNNaker's asynchronous virtual architecture permits greater scope for model exploration, with scalable levels of functional and temporal abstraction, than conventional (or neuromorphic) computing platforms. The complete system illustrates a potential path to understanding the neural model of computation, by building (and breaking) neural models at various scales, connecting the blocks, then comparing them against the biology: computational cognitive neuroscience. Copyright © 2011 Elsevier Ltd. All rights reserved.

Energy Efficiency Analysis of Antenna Selection Techniques in Massive MIMO-OFDM System with Hardware Impairments

Directory of Open Access Journals (Sweden)

Anuj Singal

2018-01-01

Full Text Available In massive multiple-input multiple-output (M-MIMO systems, a large number of antennas increase system complexity as well as the cost of hardware. In this paper, we propose an M-MIMO-OFDM model using per-subcarrier antenna selection and bulk antenna selection schemes to mitigate these problems. Also, we derive a new uplink and downlink energy efficiency (EE equation for the M-MIMO-OFDM system by taking into consideration the antenna selection schemes, power scaling factor (g=0.25,  0.5, and a range of hardware impairments {κBS, κUEϵ (0, 0.052, 0.12}. In addition, we investigate a trend of EE by varying various parameters like number of base station antennas (BSAs, SNR, level of hardware impairments, total circuit power consumption, power optimization, antenna selection schemes, and power scaling factor in the proposed M-MIMO-OFDM model. The simulation results thus obtained show that the EE increases with increase in the value of SNR. Also, it increases abruptly up to 100 number of BSA. However, the increase in the EE is not significant in the range of 125 to 400 number of BSA. Further, the bulk antenna selection technique has comparatively more EE than the per-subcarrier antenna selection. Moreover, EE gaps between antenna selection schemes decrease with increase in the value of hardware impairments and power scaling factor. However, as the hardware degradation effect increases, the EE of the bulk antenna selection scheme suffers more degradation as compared to the Per-subcarrier antenna selection scheme. It has also been observed that EE performance is inversely proportional to the total circuit power consumption (λ+γ and it increases with the power optimization.

Readability Levels of the 1975 Third Grade Macmillan Basal Readers.

Science.gov (United States)

McKinney, Ernestine Williams

1983-01-01

Analysis of third-grade books in the New Macmillan Reading Program reveals that the books exceeded the publisher's designation of readability and did not progress in difficulty from easy to more difficult. Findings suggest the need for more complete and reliable information from publishers concerning textbook readability. (FL)

Health Maintenance System (HMS) Hardware Research, Design, and Collaboration

Science.gov (United States)

Gonzalez, Stefanie M.

2010-01-01

The Space Life Sciences division (SLSD) concentrates on optimizing a crew member's health. Developments are translated into innovative engineering solutions, research growth, and community awareness. This internship incorporates all those areas by targeting various projects. The main project focuses on integrating clinical and biomedical engineering principles to design, develop, and test new medical kits scheduled for launch in the Spring of 2011. Additionally, items will be tagged with Radio Frequency Interference Devices (RFID) to keep track of the inventory. The tags will then be tested to optimize Radio Frequency feed and feed placement. Research growth will occur with ground based experiments designed to measure calcium encrusted deposits in the International Space Station (ISS). The tests will assess the urine calcium levels with Portable Clinical Blood Analyzer (PCBA) technology. If effective then a model for urine calcium will be developed and expanded to microgravity environments. To support collaboration amongst the subdivisions of SLSD the architecture of the Crew Healthcare Systems (CHeCS) SharePoint site has been redesigned for maximum efficiency. Community collaboration has also been established with the University of Southern California, Dept. of Aeronautical Engineering and the Food and Drug Administration (FDA). Hardware disbursements will transpire within these communities to support planetary surface exploration and to serve as an educational tool demonstrating how ground based medicine influenced the technological development of space hardware.

Test Program for Stirling Radioisotope Generator Hardware at NASA Glenn Research Center

Science.gov (United States)

Lewandowski, Edward J.; Bolotin, Gary S.; Oriti, Salvatore M.

2015-01-01

Stirling-based energy conversion technology has demonstrated the potential of high efficiency and low mass power systems for future space missions. This capability is beneficial, if not essential, to making certain deep space missions possible. Significant progress was made developing the Advanced Stirling Radioisotope Generator (ASRG), a 140-W radioisotope power system. A variety of flight-like hardware, including Stirling convertors, controllers, and housings, was designed and built under the ASRG flight development project. To support future Stirling-based power system development NASA has proposals that, if funded, will allow this hardware to go on test at the NASA Glenn Research Center. While future flight hardware may not be identical to the hardware developed under the ASRG flight development project, many components will likely be similar, and system architectures may have heritage to ASRG. Thus, the importance of testing the ASRG hardware to the development of future Stirling-based power systems cannot be understated. This proposed testing will include performance testing, extended operation to establish an extensive reliability database, and characterization testing to quantify subsystem and system performance and better understand system interfaces. This paper details this proposed test program for Stirling radioisotope generator hardware at NASA Glenn. It explains the rationale behind the proposed tests and how these tests will meet the stated objectives.

Graded levels of sugar syrup in broiler rations and its effect on growth performance and blood biochemical parameters

Directory of Open Access Journals (Sweden)

Ahmed S. Hussein

2016-09-01

Full Text Available Dietary energy for chickens normally includes cereal grains and fat. This innovative study investigated the effect of replacing part of the corn and fat in broiler chicken rations with graded levels of sugar syrup on growth performance and biochemical parameters. Experimental treatments consisted of feeding a corn-soy basal diet alone, or with graded levels of sugar syrup in increments of 5%, 10% and 15%. All starter diets were isonitrogenous and isocaloric. Body weight gain and efficiency of feed utilization of chicks fed the control diet alone were not significantly (P < 0.05 different from chicks fed diets supplemented with either 5% or 15% sugar syrup. Supplementation of sugar syrup to broiler diets had no significant effect on blood glucose, creatinine, total protein, or liver enzymes. Adding 5% sugar syrup to broiler rations significantly decreased blood cholesterol and triglycerides in chickens fed the sugar syrup diet compared with birds fed the control diet. In conclusion, the results shows sugar syrup can be used in poultry ration to replace part of the corn as a source of energy. These results allowed the authors to recommend the safe usage of sugar syrup in broiler rations.

Hardware and layout aspects affecting maintainability

International Nuclear Information System (INIS)

Jayaraman, V.N.; Surendar, Ch.

1977-01-01

It has been found from maintenance experience at the Rajasthan Atomic Power Station that proper hardware and instrumentation layout can reduce maintenance and down-time on the related equipment. The problems faced in this connection and how they were solved is narrated. (M.G.B.)

Building Correlators with Many-Core Hardware

NARCIS (Netherlands)

van Nieuwpoort, R.V.

2010-01-01

Radio telescopes typically consist of multiple receivers whose signals are cross-correlated to filter out noise. A recent trend is to correlate in software instead of custom-built hardware, taking advantage of the flexibility that software solutions offer. Examples include e-VLBI and LOFAR. However,

Acceptable contamination levels in solar grade silicon: From feedstock to solar cell

International Nuclear Information System (INIS)

Hofstetter, J.; Lelievre, J.F.; Canizo, C.; Luque, A. del

2009-01-01

Ultimately, alternative ways of silicon purification for photovoltaic applications are developed and applied. There is an ongoing debate about what are the acceptable contamination levels within the purified silicon feedstock to specify the material as solar grade silicon. Applying a simple model and making some additional assumptions, we calculate the acceptable contamination levels of different characteristic impurities for each fabrication step of a typical industrial mc-Si solar cell. The acceptable impurity concentrations within the finished solar cell are calculated for SRH recombination exclusively and under low injection conditions. It is assumed that during solar cell fabrication impurity concentrations are only altered by a gettering step. During the crystallization process, impurity segregation at the solid-liquid interface and at extended defects are taken into account. Finally, the initial contamination levels allowed within the feedstock are deduced. The acceptable concentration of iron in the finished solar cell is determined to be 9.7x10 -3 ppma whereas the concentration in the silicon feedstock can be as high as 12.5 ppma. In comparison, the titanium concentration admitted in the solar cell is calculated to be 2.7x10 -4 ppma and the allowed concentration of 2.2x10 -2 ppma in the feedstock is only two orders of magnitude higher. Finally, it is shown theoretically and experimentally that slow cooling rates can lead to a decrease of the interstitial Fe concentration and thus relax the purity requirements in the feedstock.

Test system design for Hardware-in-Loop evaluation of PEM fuel cells and auxiliaries

Energy Technology Data Exchange (ETDEWEB)

Randolf, Guenter; Moore, Robert M. [Hawaii Natural Energy Institute, University of Hawaii, Honolulu, HI (United States)

2006-07-14

In order to evaluate the dynamic behavior of proton exchange membrane (PEM) fuel cells and their auxiliaries, the dynamic capability of the test system must exceed the dynamics of the fastest component within the fuel cell or auxiliary component under test. This criterion is even more critical when a simulated component of the fuel cell system (e.g., the fuel cell stack) is replaced by hardware and Hardware-in-Loop (HiL) methodology is employed. This paper describes the design of a very fast dynamic test system for fuel cell transient research and HiL evaluation. The integration of the real time target (which runs the simulation), the test stand PC (that controls the operation of the test stand), and the programmable logic controller (PLC), for safety and low-level control tasks, into one single integrated unit is successfully completed. (author)

Hardware and software maintenance strategies for upgrading vintage computers

International Nuclear Information System (INIS)

Wang, B.C.; Buijs, W.J.; Banting, R.D.

1992-01-01

The paper focuses on the maintenance of the computer hardware and software for digital control computers (DCC). Specific design and problems related to various maintenance strategies are reviewed. A foundation was required for a reliable computer maintenance and upgrading program to provide operation of the DCC with high availability and reliability for 40 years. This involved a carefully planned and executed maintenance and upgrading program, involving complementary hardware and software strategies. The computer system was designed on a modular basis, with large sections easily replaceable, to facilitate maintenance and improve availability of the system. Advances in computer hardware have made it possible to replace DCC peripheral devices with reliable, inexpensive, and widely available components from PC-based systems (PC = personal computer). By providing a high speed link from the DCC to a PC, it is now possible to use many commercial software packages to process data from the plant. 1 fig

Open source hardware and software platform for robotics and artificial intelligence applications

Science.gov (United States)

Liang, S. Ng; Tan, K. O.; Lai Clement, T. H.; Ng, S. K.; Mohammed, A. H. Ali; Mailah, Musa; Azhar Yussof, Wan; Hamedon, Zamzuri; Yussof, Zulkifli

2016-02-01

Recent developments in open source hardware and software platforms (Android, Arduino, Linux, OpenCV etc.) have enabled rapid development of previously expensive and sophisticated system within a lower budget and flatter learning curves for developers. Using these platform, we designed and developed a Java-based 3D robotic simulation system, with graph database, which is integrated in online and offline modes with an Android-Arduino based rubbish picking remote control car. The combination of the open source hardware and software system created a flexible and expandable platform for further developments in the future, both in the software and hardware areas, in particular in combination with graph database for artificial intelligence, as well as more sophisticated hardware, such as legged or humanoid robots.

Open source hardware and software platform for robotics and artificial intelligence applications

International Nuclear Information System (INIS)

Liang, S Ng; Tan, K O; Clement, T H Lai; Ng, S K; Mohammed, A H Ali; Mailah, Musa; Yussof, Wan Azhar; Hamedon, Zamzuri; Yussof, Zulkifli

2016-01-01

Recent developments in open source hardware and software platforms (Android, Arduino, Linux, OpenCV etc.) have enabled rapid development of previously expensive and sophisticated system within a lower budget and flatter learning curves for developers. Using these platform, we designed and developed a Java-based 3D robotic simulation system, with graph database, which is integrated in online and offline modes with an Android-Arduino based rubbish picking remote control car. The combination of the open source hardware and software system created a flexible and expandable platform for further developments in the future, both in the software and hardware areas, in particular in combination with graph database for artificial intelligence, as well as more sophisticated hardware, such as legged or humanoid robots. (paper)

X-Window for process control in a mixed hardware environment

International Nuclear Information System (INIS)

Clausen, M.; Rehlich, K.

1992-01-01

X-Window is a common standard for display purposes on the current workstations. The possibility to create more than one window on a single screen enables the operators to gain more information about the process. Multiple windows from different control systems using mixed hardware is one of the problems this paper will describe. The experience shows that X-Window is a standard per definition, but not in any case. But it is an excellent tool to separate data-acquisition and display from each other over long distances using different types of hardware and software for communications and display. Our experience with X-Window displays for the cryogenic control system and the vacuum control system at HERA on DEC and SUN hardware will be described. (author)

Plutonium Protection System (PPS). Volume 2. Hardware description. Final report

International Nuclear Information System (INIS)

Miyoshi, D.S.

1979-05-01

The Plutonium Protection System (PPS) is an integrated safeguards system developed by Sandia Laboratories for the Department of Energy, Office of Safeguards and Security. The system is designed to demonstrate and test concepts for the improved safeguarding of plutonium. Volume 2 of the PPS final report describes the hardware elements of the system. The major areas containing hardware elements are the vault, where plutonium is stored, the packaging room, where plutonium is packaged into Container Modules, the Security Operations Center, which controls movement of personnel, the Material Accountability Center, which maintains the system data base, and the Material Operations Center, which monitors the operating procedures in the system. References are made to documents in which details of the hardware items can be found

Current trends in hardware and software for brain-computer interfaces (BCIs).

Science.gov (United States)

Brunner, P; Bianchi, L; Guger, C; Cincotti, F; Schalk, G

2011-04-01

A brain-computer interface (BCI) provides a non-muscular communication channel to people with and without disabilities. BCI devices consist of hardware and software. BCI hardware records signals from the brain, either invasively or non-invasively, using a series of device components. BCI software then translates these signals into device output commands and provides feedback. One may categorize different types of BCI applications into the following four categories: basic research, clinical/translational research, consumer products, and emerging applications. These four categories use BCI hardware and software, but have different sets of requirements. For example, while basic research needs to explore a wide range of system configurations, and thus requires a wide range of hardware and software capabilities, applications in the other three categories may be designed for relatively narrow purposes and thus may only need a very limited subset of capabilities. This paper summarizes technical aspects for each of these four categories of BCI applications. The results indicate that BCI technology is in transition from isolated demonstrations to systematic research and commercial development. This process requires several multidisciplinary efforts, including the development of better integrated and more robust BCI hardware and software, the definition of standardized interfaces, and the development of certification, dissemination and reimbursement procedures.

Current trends in hardware and software for brain-computer interfaces (BCIs)

Science.gov (United States)

Brunner, P.; Bianchi, L.; Guger, C.; Cincotti, F.; Schalk, G.

2011-04-01

A brain-computer interface (BCI) provides a non-muscular communication channel to people with and without disabilities. BCI devices consist of hardware and software. BCI hardware records signals from the brain, either invasively or non-invasively, using a series of device components. BCI software then translates these signals into device output commands and provides feedback. One may categorize different types of BCI applications into the following four categories: basic research, clinical/translational research, consumer products, and emerging applications. These four categories use BCI hardware and software, but have different sets of requirements. For example, while basic research needs to explore a wide range of system configurations, and thus requires a wide range of hardware and software capabilities, applications in the other three categories may be designed for relatively narrow purposes and thus may only need a very limited subset of capabilities. This paper summarizes technical aspects for each of these four categories of BCI applications. The results indicate that BCI technology is in transition from isolated demonstrations to systematic research and commercial development. This process requires several multidisciplinary efforts, including the development of better integrated and more robust BCI hardware and software, the definition of standardized interfaces, and the development of certification, dissemination and reimbursement procedures.

Tomographic image reconstruction and rendering with texture-mapping hardware

International Nuclear Information System (INIS)

Azevedo, S.G.; Cabral, B.K.; Foran, J.

1994-07-01

The image reconstruction problem, also known as the inverse Radon transform, for x-ray computed tomography (CT) is found in numerous applications in medicine and industry. The most common algorithm used in these cases is filtered backprojection (FBP), which, while a simple procedure, is time-consuming for large images on any type of computational engine. Specially-designed, dedicated parallel processors are commonly used in medical CT scanners, whose results are then passed to graphics workstation for rendering and analysis. However, a fast direct FBP algorithm can be implemented on modern texture-mapping hardware in current high-end workstation platforms. This is done by casting the FBP algorithm as an image warping operation with summing. Texture-mapping hardware, such as that on the Silicon Graphics Reality Engine (TM), shows around 600 times speedup of backprojection over a CPU-based implementation (a 100 Mhz R4400 in this case). This technique has the further advantages of flexibility and rapid programming. In addition, the same hardware can be used for both image reconstruction and for volumetric rendering. The techniques can also be used to accelerate iterative reconstruction algorithms. The hardware architecture also allows more complex operations than straight-ray backprojection if they are required, including fan-beam, cone-beam, and curved ray paths, with little or no speed penalties

Hardware realization of an SVM algorithm implemented in FPGAs

Science.gov (United States)

Wiśniewski, Remigiusz; Bazydło, Grzegorz; Szcześniak, Paweł

2017-08-01

The paper proposes a technique of hardware realization of a space vector modulation (SVM) of state function switching in matrix converter (MC), oriented on the implementation in a single field programmable gate array (FPGA). In MC the SVM method is based on the instantaneous space-vector representation of input currents and output voltages. The traditional computation algorithms usually involve digital signal processors (DSPs) which consumes the large number of power transistors (18 transistors and 18 independent PWM outputs) and "non-standard positions of control pulses" during the switching sequence. Recently, hardware implementations become popular since computed operations may be executed much faster and efficient due to nature of the digital devices (especially concurrency). In the paper, we propose a hardware algorithm of SVM computation. In opposite to the existing techniques, the presented solution applies COordinate Rotation DIgital Computer (CORDIC) method to solve the trigonometric operations. Furthermore, adequate arithmetic modules (that is, sub-devices) used for intermediate calculations, such as code converters or proper sectors selectors (for output voltages and input current) are presented in detail. The proposed technique has been implemented as a design described with the use of Verilog hardware description language. The preliminary results of logic implementation oriented on the Xilinx FPGA (particularly, low-cost device from Artix-7 family from Xilinx was used) are also presented.

Hardware Design Considerations for Edge-Accelerated Stereo Correspondence Algorithms

Directory of Open Access Journals (Sweden)

Christos Ttofis

2012-01-01

Full Text Available Stereo correspondence is a popular algorithm for the extraction of depth information from a pair of rectified 2D images. Hence, it has been used in many computer vision applications that require knowledge about depth. However, stereo correspondence is a computationally intensive algorithm and requires high-end hardware resources in order to achieve real-time processing speed in embedded computer vision systems. This paper presents an overview of the use of edge information as a means to accelerate hardware implementations of stereo correspondence algorithms. The presented approach restricts the stereo correspondence algorithm only to the edges of the input images rather than to all image points, thus resulting in a considerable reduction of the search space. The paper highlights the benefits of the edge-directed approach by applying it to two stereo correspondence algorithms: an SAD-based fixed-support algorithm and a more complex adaptive support weight algorithm. Furthermore, we present design considerations about the implementation of these algorithms on reconfigurable hardware and also discuss issues related to the memory structures needed, the amount of parallelism that can be exploited, the organization of the processing blocks, and so forth. The two architectures (fixed-support based versus adaptive-support weight based are compared in terms of processing speed, disparity map accuracy, and hardware overheads, when both are implemented on a Virtex-5 FPGA platform.

Introduction to Hardware Security and Trust

CERN Document Server

Wang, Cliff

2012-01-01

The emergence of a globalized, horizontal semiconductor business model raises a set of concerns involving the security and trust of the information systems on which modern society is increasingly reliant for mission-critical functionality. Hardware-oriented security and trust issues span a broad range including threats related to the malicious insertion of Trojan circuits designed, e.g.,to act as a ‘kill switch’ to disable a chip, to integrated circuit (IC) piracy,and to attacks designed to extract encryption keys and IP from a chip. This book provides the foundations for understanding hardware security and trust, which have become major concerns for national security over the past decade.  Coverage includes security and trust issues in all types of electronic devices and systems such as ASICs, COTS, FPGAs, microprocessors/DSPs, and embedded systems.  This serves as an invaluable reference to the state-of-the-art research that is of critical significance to the security of,and trust in, modern society�...

Utilizing IXP1200 hardware and software for packet filtering

OpenAIRE

Lindholm, Jeffery L.

2004-01-01

As network processors have advanced in speed and efficiency they have become more and more complex in both hardware and software configurations. Intel's IXP1200 is one of these new network processors that has been given to different universities worldwide to conduct research on. The goal of this thesis is to take the first step in starting that research by providing a stable system that can provide a reliable platform for further research. This thesis introduces the fundamental hardware of In...

The hardware control system for WEAVE at the William Herschel telescope

NARCIS (Netherlands)

Delgado Hernandez, Jose M.; Rodríguez-Ramos, Luis F.; Cano Infantes, Diego; Martin, Carlos; Bevil, Craige; Picó, Sergio; Dee, Kevin M.; Abrams, Don Carlos; Lewis, Ian J.; Pragt, Johan; Stuik, Remko; Tromp, Niels; Dalton, Gavin; L. Aguerri, J. Alfonso; Bonifacio, Piercarlo; Middleton, Kevin F.; Trager, Scott C.

This work describes the hardware control system of the Prime Focus Corrector (PFC) and the Spectrograph, two of the main parts of WEAVE, a multi-object fiber spectrograph for the WHT Telescope. The PFC and Spectrograph control system hardware is based on the Allen Bradley's Programmable Automation

A Fast Hardware Tracker for the ATLAS Trigger System

CERN Document Server

Neubauer, M; The ATLAS collaboration

2011-01-01

In hadron collider experiments, triggering the detector to store interesting events for offline analysis is a challenge due to the high rates and multiplicities of particles produced. The LHC will soon operate at a center-of-mass energy of 14 TeV and at high instantaneous luminosities of the order of $10^{34}$ to $10^{35}$ cm$^{-2}$ s$^{-1}$. A multi-level trigger strategy is used in ATLAS, with the first level (LVL1) implemented in hardware and the second and third levels (LVL2 and EF) implemented in a large computer farm. Maintaining high trigger efficiency for the physics we are most interested in while at the same time suppressing high rate physics from inclusive QCD processes is a difficult but important problem. It is essential that the trigger system be flexible and robust, with sufficient redundancy and operating margin. Providing high quality track reconstruction over the full ATLAS detector by the start of processing at LVL2 is an important element to achieve these needs. As the instantaneous lumino...

Establishing a novel modeling tool: a python-based interface for a neuromorphic hardware system.

Science.gov (United States)

Brüderle, Daniel; Müller, Eric; Davison, Andrew; Muller, Eilif; Schemmel, Johannes; Meier, Karlheinz

2009-01-01

Neuromorphic hardware systems provide new possibilities for the neuroscience modeling community. Due to the intrinsic parallelism of the micro-electronic emulation of neural computation, such models are highly scalable without a loss of speed. However, the communities of software simulator users and neuromorphic engineering in neuroscience are rather disjoint. We present a software concept that provides the possibility to establish such hardware devices as valuable modeling tools. It is based on the integration of the hardware interface into a simulator-independent language which allows for unified experiment descriptions that can be run on various simulation platforms without modification, implying experiment portability and a huge simplification of the quantitative comparison of hardware and simulator results. We introduce an accelerated neuromorphic hardware device and describe the implementation of the proposed concept for this system. An example setup and results acquired by utilizing both the hardware system and a software simulator are demonstrated.

An AES chip with DPA resistance using hardware-based random order execution

International Nuclear Information System (INIS)

Yu Bo; Li Xiangyu; Chen Cong; Sun Yihe; Wu Liji; Zhang Xiangmin

2012-01-01

This paper presents an AES (advanced encryption standard) chip that combats differential power analysis (DPA) side-channel attack through hardware-based random order execution. Both decryption and encryption procedures of an AES are implemented on the chip. A fine-grained dataflow architecture is proposed, which dynamically exploits intrinsic byte-level independence in the algorithm. A novel circuit called an HMF (Hold-Match-Fetch) unit is proposed for random control, which randomly sets execution orders for concurrent operations. The AES chip was manufactured in SMIC 0.18 μm technology. The average energy for encrypting one group of plain texts (128 bits secrete keys) is 19 nJ. The core area is 0.43 mm 2 . A sophisticated experimental setup was built to test the DPA resistance. Measurement-based experimental results show that one byte of a secret key cannot be disclosed from our chip under random mode after 64000 power traces were used in the DPA attack. Compared with the corresponding fixed order execution, the hardware based random order execution is improved by at least 21 times the DPA resistance. (semiconductor integrated circuits)

An AES chip with DPA resistance using hardware-based random order execution

Science.gov (United States)

Bo, Yu; Xiangyu, Li; Cong, Chen; Yihe, Sun; Liji, Wu; Xiangmin, Zhang

2012-06-01

This paper presents an AES (advanced encryption standard) chip that combats differential power analysis (DPA) side-channel attack through hardware-based random order execution. Both decryption and encryption procedures of an AES are implemented on the chip. A fine-grained dataflow architecture is proposed, which dynamically exploits intrinsic byte-level independence in the algorithm. A novel circuit called an HMF (Hold-Match-Fetch) unit is proposed for random control, which randomly sets execution orders for concurrent operations. The AES chip was manufactured in SMIC 0.18 μm technology. The average energy for encrypting one group of plain texts (128 bits secrete keys) is 19 nJ. The core area is 0.43 mm2. A sophisticated experimental setup was built to test the DPA resistance. Measurement-based experimental results show that one byte of a secret key cannot be disclosed from our chip under random mode after 64000 power traces were used in the DPA attack. Compared with the corresponding fixed order execution, the hardware based random order execution is improved by at least 21 times the DPA resistance.

FTK: the hardware Fast TracKer of the ATLAS experiment at CERN

CERN Document Server

Maznas, Ioannis; The ATLAS collaboration

2016-01-01

FTK: the hardware Fast TracKer of the ATLAS experiment at CERN In the ever increasing pile-up of the Large Hadron Collider environment, the trigger systems of the experiments have to be exceedingly sophisticated and fast at the same time, in order to select the relevant physics processes against the background processes. The Fast TracKer (FTK) is a track finding implementation at hardware level that is designed to deliver full-scan tracks with $p_{T}$ above 1 GeV to the ATLAS trigger system for every L1 accept (at a maximum rate of 100kHz). To accomplish this, FTK is a highly parallel system which is currently under installation in ATLAS. It will first provide the trigger system with tracks in the central region of the ATLAS detector, and next year it is expected to cover the whole detector. The system is based on pattern matching between hits coming from the silicon trackers of the ATLAS detector and 1 billion simulated patterns stored in specially designed ASIC chips (Associative memory – AM06). In a firs...

Hardware realization of a fast neural network algorithm for real-time tracking in HEP experiments

International Nuclear Information System (INIS)

Leimgruber, F.R.; Pavlopoulos, P.; Steinacher, M.; Tauscher, L.; Vlachos, S.; Wendler, H.

1995-01-01

A fast pattern recognition system for HEP experiments, based on artificial neural network algorithms (ANN), has been realized with standard electronics. The multiplicity and location of tracks in an event are determined in less than 75 ns. Hardware modules of this first level trigger were extensively tested for performance and reliability with data from the CPLEAR experiment. (orig.)

Sex and Grade Level Differences in Marijuana Use among Youth

Science.gov (United States)

King, Keith A.; Vidourek, Rebecca A.; Hoffman, Ashlee R.

2012-01-01

A total of 54,361 students in seventh through twelfth grades completed a survey examining the impact of perceived harm of marijuana use, ease of access in obtaining marijuana, and perceived parent/peer disapproval of marijuana use on youth involvement in annual and recent marijuana use. Results indicated that 1 in 6 (16%) students used marijuana…

Benchmarking Model Variants in Development of a Hardware-in-the-Loop Simulation System

Science.gov (United States)

Aretskin-Hariton, Eliot D.; Zinnecker, Alicia M.; Kratz, Jonathan L.; Culley, Dennis E.; Thomas, George L.

2016-01-01

Distributed engine control architecture presents a significant increase in complexity over traditional implementations when viewed from the perspective of system simulation and hardware design and test. Even if the overall function of the control scheme remains the same, the hardware implementation can have a significant effect on the overall system performance due to differences in the creation and flow of data between control elements. A Hardware-in-the-Loop (HIL) simulation system is under development at NASA Glenn Research Center that enables the exploration of these hardware dependent issues. The system is based on, but not limited to, the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k). This paper describes the step-by-step conversion from the self-contained baseline model to the hardware in the loop model, and the validation of each step. As the control model hardware fidelity was improved during HIL system development, benchmarking simulations were performed to verify that engine system performance characteristics remained the same. The results demonstrate the goal of the effort; the new HIL configurations have similar functionality and performance compared to the baseline C-MAPSS40k system.

Establishing a novel modeling tool: a python-based interface for a neuromorphic hardware system

Directory of Open Access Journals (Sweden)

Daniel Brüderle

2009-06-01

Full Text Available Neuromorphic hardware systems provide new possibilities for the neuroscience modeling community. Due to the intrinsic parallelism of the micro-electronic emulation of neural computation, such models are highly scalable without a loss of speed. However, the communities of software simulator users and neuromorphic engineering in neuroscience are rather disjoint. We present a software concept that provides the possibility to establish such hardware devices as valuable modeling tools. It is based on the integration of the hardware interface into a simulator-independent language which allows for unified experiment descriptions that can be run on various simulation platforms without modification, implying experiment portability and a huge simplification of the quantitative comparison of hardware and simulator results. We introduce an accelerated neuromorphic hardware device and describe the implementation of the proposed concept for this system. An example setup and results acquired by utilizing both the hardware system and a software simulator are demonstrated.

Enabling Open Hardware through FOSS tools

CERN Multimedia

CERN. Geneva

2016-01-01

Software developers often take open file formats and tools for granted. When you publish code on github, you do not ask yourself if somebody will be able to open it and modify it. We need the same freedom in the open hardware world, to make it truly accessible for everyone.

Integrated conception of hardware/software mixed systems used in nuclear instrumentation

International Nuclear Information System (INIS)

Dias, Ailton F.; Sorel, Yves; Akil, Mohamed

2002-01-01

Hardware/software codesign carries out the design of systems composed by a hardware portion, with specific components, and a software portion, with microprocessor based architecture. This paper describes the Algorithm Architecture Adequation (AAA) design methodology - originally oriented to programmable multicomponent architectures, its extension to reconfigurable circuits and its application to design and development of nuclear instrumentation systems composed by programmable and configurable circuits. AAA methodology uses an unified model to describe algorithm, architecture and implementation, based on graph theory. The great advantage of AAA methodology is the utilization of a same model from the specification to the implementation of hardware/software systems, reducing the complexity and design time. (author)

A Hardware Fast Tracker for the ATLAS trigger

CERN Document Server

Asbah, Nedaa; The ATLAS collaboration

2015-01-01

The trigger system of the ATLAS experiment is designed to reduce the event rate from the LHC nominal bunch crossing at 40 MHz to about 1 kHz, at the design luminosity of 10^{34} cm^{-2}s^{-1}. After a successful period of data taking from 2010 to early 2013, the LHC restarted with much higher instantaneous luminosity. This will increase the load on High Level Trigger system, the second stage of the selection based on software algorithms. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals. The Fast TracKer (FTK) is part of the ATLAS trigger upgrade project; it is a hardware processor that will provide, at every level-1 accepted event (100 kHz) and within 100 microseconds, full tracking information for tracks with momentum as low as 1 GeV. Providing fast extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondar...

Rapid prototyping of an automated video surveillance system: a hardware-software co-design approach

Science.gov (United States)

Ngo, Hau T.; Rakvic, Ryan N.; Broussard, Randy P.; Ives, Robert W.

2011-06-01

FPGA devices with embedded DSP and memory blocks, and high-speed interfaces are ideal for real-time video processing applications. In this work, a hardware-software co-design approach is proposed to effectively utilize FPGA features for a prototype of an automated video surveillance system. Time-critical steps of the video surveillance algorithm are designed and implemented in the FPGAs logic elements to maximize parallel processing. Other non timecritical tasks are achieved by executing a high level language program on an embedded Nios-II processor. Pre-tested and verified video and interface functions from a standard video framework are utilized to significantly reduce development and verification time. Custom and parallel processing modules are integrated into the video processing chain by Altera's Avalon Streaming video protocol. Other data control interfaces are achieved by connecting hardware controllers to a Nios-II processor using Altera's Avalon Memory Mapped protocol.

Calculator: A Hardware Design, Math and Software Programming Project Base Learning

Directory of Open Access Journals (Sweden)

F. Criado

2015-03-01

Full Text Available This paper presents the implementation by the students of a complex calculator in hardware. This project meets hardware design goals, and also highly motivates them to use competences learned in others subjects. The learning process, associated to System Design, is hard enough because the students have to deal with parallel execution, signal delay, synchronization … Then, to strengthen the knowledge of hardware design a methodology as project based learning (PBL is proposed. Moreover, it is also used to reinforce cross subjects like math and software programming. This methodology creates a course dynamics that is closer to a professional environment where they will work with software and mathematics to resolve the hardware design problems. The students design from zero the functionality of the calculator. They are who make the decisions about the math operations that it is able to resolve it, and also the operands format or how to introduce a complex equation into the calculator. This will increase the student intrinsic motivation. In addition, since the choices may have consequences on the reliability of the calculator, students are encouraged to program in software the decisions about how implement the selected mathematical algorithm. Although math and hardware design are two tough subjects for students, the perception that they get at the end of the course is quite positive.

Performance and system flexibility of the CDF Hardware Event Builder

Energy Technology Data Exchange (ETDEWEB)

Shaw, T.M.; Schurecht, K. (Fermi National Accelerator Lab., Batavia, IL (United States)); Sinervo, P. (Toronto Univ., ON (Canada). Dept. of Physics)

1991-11-01

The CDF Hardware Event Builder (1) is a flexible system which is built from a combination of three different 68020-based single width Fastbus modules. The system may contain as few as three boards or as many as fifteen, depending on the specific application. Functionally, the boards receive a command to read out the raw event data from a set of Fastbus based data buffers ( scanners''), reformat data and then write the data to a Level 3 trigger/processing farm which will decide to throw the event away or to write it to tape. The data acquisition system at CDF will utilize two nine board systems which will allow an event rate of up to 35 Hz into the Level 3 trigger. This paper will present detailed performance factors, system and individual board architecture, and possible system configurations.

Readability Levels of Dental Patient Education Brochures.

Science.gov (United States)

Boles, Catherine D; Liu, Ying; November-Rider, Debra

2016-02-01

The objective of this study was to evaluate dental patient education brochures produced since 2000 to determine if there is any change in the Flesch-Kincaid grade level readability. A convenience sample of 36 brochures was obtained for analysis of the readability of the patient education material on multiple dental topics. Readability was measured using the Flesch-Kincaid Grade Level through Microsoft Word. Pearson's correlation was used to describe the relationship among the factors of interest. Backward model selection of multiple linear regression model was used to investigate the relationship between Flesch-Kincaid Grade level and a set of predictors included in this study. A convenience sample (n=36) of dental education brochures produced from 2000 to 2014 showed a mean Flesch-Kincaid reading grade level of 9.15. Weak to moderate correlations existed between word count and grade level (r=0.40) and characters count and grade level (r=0.46); strong correlations were found between grade level and average words per sentence (r=0.70), average characters per word (r=0.85) and Flesch Reading Ease (r=-0.98). Only 1 brochure out of the sample met the recommended sixth grade reading level (Flesch-Kincaid Grade Level 5.7). Overall, the Flesch-Kincaid Grade Level of all brochures was significantly higher than the recommended sixth grade reading level (preadability of the brochures. However, the majority of the brochures analyzed are still testing above the recommended sixth grade reading level. Copyright © 2016 The American Dental Hygienists’ Association.

MORPION: a fast hardware processor for straight line finding in MWPC

International Nuclear Information System (INIS)

Mur, M.

1980-02-01

A fast hardware processor for straight line finding in MWPC has been built in Saclay and successfully operated in the NA3 experiment at CERN. We give the motivations to build this processor, and describe the hardware implementation of the line finding algorithm. Finally its use and performance in NA3 are described

Environmental Control System Software & Hardware Development

Science.gov (United States)

Vargas, Daniel Eduardo

2017-01-01

ECS hardware: (1) Provides controlled purge to SLS Rocket and Orion spacecraft. (2) Provide mission-focused engineering products and services. ECS software: (1) NASA requires Compact Unique Identifiers (CUIs); fixed-length identifier used to identify information items. (2) CUI structure; composed of nine semantic fields that aid the user in recognizing its purpose.

Development of Chemistry Triangle Oriented Module on Topic of Reaction Rate for Senior High School Level Grade XI Chemistry Learning.

Science.gov (United States)

Sari, D. R.; Hardeli; Bayharti

2018-04-01

This study aims to produce chemistry triangle oriented module on topic of reaction rate, and to reveal the validity and practicality level of the generated module. The type of research used is EducationalDesign Research (EDR) with development model is Plompmodel. This model consists of three phases, which are preliminary research, prototyping phase, and assessment phase. The instrument used in this research is questionnaire validity and practicality. The data of the research were analyzed by using Kappa Cohen formula. The chemistry triangle oriented module validation sheet was given to 5 validators consisting of 3 chemistry lecturers and 2 high school chemistry teachers, while the practicality sheet was given to 2 chemistry teachers, 6 students of SMAN 10 Padang grade XII MIA 5 on the small groupevaluation and 25 students of SMAN 10 Padang grade XII MIA 6 on the field test. Based on the questionnaire validity analysis, the validity level of the module is very high with the value of kappa moment 0.87. The level of practicality based on teacher questionnaire response is very high category with a kappa moment value 0.96. Based on the questionnaire of student responses on small group evaluation, the level of practicality is very high category with a kappa moment 0.81, and the practicality is very high category with kappa moment value 0.83 based on questionnaire of student response on field test.

Total knee arthroplasty using patient-specific blocks after prior femoral fracture without hardware removal

Directory of Open Access Journals (Sweden)

Raju Vaishya

2018-01-01

Full Text Available Background: The options to perform total knee arthroplasty (TKA with retained hardware in femur are mainly – removal of hardware, use of extramedullary guide, or computer-assisted surgery. Patient-specific blocks (PSBs have been introduced with many potential advantages, but their use in retained hardware has not been adequately explored. The purpose of the present study was to outline and assess the usefulness of the PSBs in performing TKA in patients with retained femoral hardware. Materials and Materials and Methods: Nine patients with retained femoral hardware underwent TKA using PSBs. All the surgeries were performed by the same surgeon using same implants. Nine cases (7 males and 2 females out of total of 120 primary TKA had retained hardware. The average age of the patients was 60.55 years. The retained hardware were 6 patients with nails, 2 with plates and one patient had screws. Out of the nine cases, only one patient needed removal of a screw which was hindering placement of pin for the PSB. Results: All the patients had significant improvement in their Knee Society Score (KSS which improved from 47.0 to postoperative KSS of 86.77 (P < 0.00. The mechanical axis was significantly improved (P < 0.03 after surgery. No patient required blood transfusion and the average tourniquet time was 41 min. Conclusion: TKA using PSBs is useful and can be used in patients with retained hardware with good functional and radiological outcome.

High Performance Motion-Planner Architecture for Hardware-In-the-Loop System Based on Position-Based-Admittance-Control

Directory of Open Access Journals (Sweden)

Francesco La Mura

2018-02-01

Full Text Available This article focuses on a Hardware-In-the-Loop application developed from the advanced energy field project LIFES50+. The aim is to replicate, inside a wind gallery test facility, the combined effect of aerodynamic and hydrodynamic loads on a floating wind turbine model for offshore energy production, using a force controlled robotic device, emulating floating substructure’s behaviour. In addition to well known real-time Hardware-In-the-Loop (HIL issues, the particular application presented has stringent safety requirements of the HIL equipment and difficult to predict operating conditions, so that extra computational efforts have to be spent running specific safety algorithms and achieving desired performance. To meet project requirements, a high performance software architecture based on Position-Based-Admittance-Control (PBAC is presented, combining low level motion interpolation techniques, efficient motion planning, based on buffer management and Time-base control, and advanced high level safety algorithms, implemented in a rapid real-time control architecture.

Event management for large scale event-driven digital hardware spiking neural networks.

Science.gov (United States)

Caron, Louis-Charles; D'Haene, Michiel; Mailhot, Frédéric; Schrauwen, Benjamin; Rouat, Jean

2013-09-01

The interest in brain-like computation has led to the design of a plethora of innovative neuromorphic systems. Individually, spiking neural networks (SNNs), event-driven simulation and digital hardware neuromorphic systems get a lot of attention. Despite the popularity of event-driven SNNs in software, very few digital hardware architectures are found. This is because existing hardware solutions for event management scale badly with the number of events. This paper introduces the structured heap queue, a pipelined digital hardware data structure, and demonstrates its suitability for event management. The structured heap queue scales gracefully with the number of events, allowing the efficient implementation of large scale digital hardware event-driven SNNs. The scaling is linear for memory, logarithmic for logic resources and constant for processing time. The use of the structured heap queue is demonstrated on a field-programmable gate array (FPGA) with an image segmentation experiment and a SNN of 65,536 neurons and 513,184 synapses. Events can be processed at the rate of 1 every 7 clock cycles and a 406×158 pixel image is segmented in 200 ms. Copyright © 2013 Elsevier Ltd. All rights reserved.

MAS: Malware Analysis System Based on Hardware-Assisted Virtualization Technology

Science.gov (United States)

Kim, Taehyoung; Kim, Inhyuk; Min, Changwoo; Eom, Young Ik

There are many analysis techniques in order to analyze malicious codes. However, recently malicious codes often evade detection using stealthy obfuscation techniques, and attack computing systems. We propose an enhanced dynamic binary instrumentation using hardware-assisted virtualization technology. As a machine-level analyzer, our system can be isolated from almost the whole threats of malware, and provides single step analysis environment. Proposed system also supports rapid system call analysis environment. We implement our malware analysis system (referred as MAS) on the KVM hypervisor with Intel VT-x virtualization support. Our experiments with benchmarks show that the proposed system provides efficient analysis environment with low overhead.

The hardware track finder processor in CMS at CERN

International Nuclear Information System (INIS)

Kluge, A.

1997-07-01

The work covers the design of the Track Finder Processor in the high energy experiment CMS at CERN/Geneva. The task of this processor is to identify muons and to measure their transverse momentum. The Track Finder makes it possible to determine the physical relevance of each high energetic collision and to forward only interesting data to the data analysis units. Data of more than two hundred thousand detector cells are used to determine the location of muons and to measure their transverse momentum. Each 25 ns a new data set is generated. Measurement of location and transverse momentum of the muons can be terminated within 350 ns by using an ASIC. The classical method in high energy physics experiments is to employ a pattern comparison method. The predefined patterns are compared to the found patterns. The high number of data channels and the complex requirements to the spatial detector resolution do not permit to employ a pattern comparison method. A so called track following algorithm was designed, which is able to assemble complete tracks through the whole detector starting from single track segments. Instead of storing a high number of track patterns the problem is brought back to the algorithm level. Comprehensive simulations, employing the hardware simulation language VHDL, were conducted in order to optimize the algorithm and its hardware implementation. A FPGA (field program able gate array)-prototype was designed. A feasibility study to implement the track finder processor employing ASICs was conducted. (author)

Hardware-assisted software clock synchronization for homogeneous distributed systems

Science.gov (United States)

Ramanathan, P.; Kandlur, Dilip D.; Shin, Kang G.

1990-01-01

A clock synchronization scheme that strikes a balance between hardware and software solutions is proposed. The proposed is a software algorithm that uses minimal additional hardware to achieve reasonably tight synchronization. Unlike other software solutions, the guaranteed worst-case skews can be made insensitive to the maximum variation of message transit delay in the system. The scheme is particularly suitable for large partially connected distributed systems with topologies that support simple point-to-point broadcast algorithms. Examples of such topologies include the hypercube and the mesh interconnection structures.

Hardware availability calculations and results of the IFMIF accelerator facility

International Nuclear Information System (INIS)

Bargalló, Enric; Arroyo, Jose Manuel; Abal, Javier; Beauvais, Pierre-Yves; Gobin, Raphael; Orsini, Fabienne; Weber, Moisés; Podadera, Ivan; Grespan, Francesco; Fagotti, Enrico; De Blas, Alfredo; Dies, Javier; Tapia, Carlos; Mollá, Joaquín; Ibarra, Ángel

2014-01-01

Highlights: • IFMIF accelerator facility hardware availability analyses methodology is described. • Results of the individual hardware availability analyses are shown for the reference design. • Accelerator design improvements are proposed for each system. • Availability results are evaluated and compared with the requirements. - Abstract: Hardware availability calculations have been done individually for each system of the deuteron accelerators of the International Fusion Materials Irradiation Facility (IFMIF). The principal goal of these analyses is to estimate the availability of the systems, compare it with the challenging IFMIF requirements and find new paths to improve availability performances. Major unavailability contributors are highlighted and possible design changes are proposed in order to achieve the hardware availability requirements established for each system. In this paper, such possible improvements are implemented in fault tree models and the availability results are evaluated. The parallel activity on the design and construction of the linear IFMIF prototype accelerator (LIPAc) provides detailed design information for the RAMI (reliability, availability, maintainability and inspectability) analyses and allows finding out the improvements that the final accelerator could have. Because of the R and D behavior of the LIPAc, RAMI improvements could be the major differences between the prototype and the IFMIF accelerator design

Hardware availability calculations and results of the IFMIF accelerator facility

Energy Technology Data Exchange (ETDEWEB)

Bargalló, Enric, E-mail: enric.bargallo-font@upc.edu [Fusion Energy Engineering Laboratory (FEEL), Technical University of Catalonia (UPC), Barcelona (Spain); Arroyo, Jose Manuel [Laboratorio Nacional de Fusión por Confinamiento Magnético – CIEMAT, Madrid (Spain); Abal, Javier [Fusion Energy Engineering Laboratory (FEEL), Technical University of Catalonia (UPC), Barcelona (Spain); Beauvais, Pierre-Yves; Gobin, Raphael; Orsini, Fabienne [Commissariat à l’Energie Atomique, Saclay (France); Weber, Moisés; Podadera, Ivan [Laboratorio Nacional de Fusión por Confinamiento Magnético – CIEMAT, Madrid (Spain); Grespan, Francesco; Fagotti, Enrico [Istituto Nazionale di Fisica Nucleare, Legnaro (Italy); De Blas, Alfredo; Dies, Javier; Tapia, Carlos [Fusion Energy Engineering Laboratory (FEEL), Technical University of Catalonia (UPC), Barcelona (Spain); Mollá, Joaquín; Ibarra, Ángel [Laboratorio Nacional de Fusión por Confinamiento Magnético – CIEMAT, Madrid (Spain)

2014-10-15

Highlights: • IFMIF accelerator facility hardware availability analyses methodology is described. • Results of the individual hardware availability analyses are shown for the reference design. • Accelerator design improvements are proposed for each system. • Availability results are evaluated and compared with the requirements. - Abstract: Hardware availability calculations have been done individually for each system of the deuteron accelerators of the International Fusion Materials Irradiation Facility (IFMIF). The principal goal of these analyses is to estimate the availability of the systems, compare it with the challenging IFMIF requirements and find new paths to improve availability performances. Major unavailability contributors are highlighted and possible design changes are proposed in order to achieve the hardware availability requirements established for each system. In this paper, such possible improvements are implemented in fault tree models and the availability results are evaluated. The parallel activity on the design and construction of the linear IFMIF prototype accelerator (LIPAc) provides detailed design information for the RAMI (reliability, availability, maintainability and inspectability) analyses and allows finding out the improvements that the final accelerator could have. Because of the R and D behavior of the LIPAc, RAMI improvements could be the major differences between the prototype and the IFMIF accelerator design.

Advanced hardware design for error correcting codes

CERN Document Server

Coussy, Philippe

2015-01-01

This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. • Examines how to optimize the architecture of hardware design for error correcting codes; • Presents error correction codes from theory to optimized architecture for the current and the next generation standards; • Provides coverage of industrial user needs advanced error correcting techniques.

Implementation of the ALICE HLT hardware cluster finder algorithm in Vivado HLS

Energy Technology Data Exchange (ETDEWEB)

Gruell, Frederik; Engel, Heiko; Kebschull, Udo [Infrastructure and Computer Systems in Data Processing, Goethe University Frankfurt (Germany); Collaboration: ALICE-Collaboration

2016-07-01

The FastClusterFinder algorithm running in the ALICE High-Level Trigger (HLT) read-out boards extracts clusters from raw data from the Time Projection Chamber (TPC) detector and forwards them to the HLT data processing framework for tracking, event reconstruction and compression. It serves as an early stage of feature extraction in the FPGA of the board. Past and current implementations are written in VHDL on reconfigurable hardware for high throughput and low latency. We examine Vivado HLS, a high-level language that promises an increased developer productivity, as an alternative. The implementation of the application is compared to descriptions in VHDL and MaxJ in terms of productivity, resource usage and maximum clock frequency.

A comparison of hardware description languages. [describing digital systems structure and behavior to a computer

Science.gov (United States)

Shiva, S. G.

1978-01-01

Several high level languages which evolved over the past few years for describing and simulating the structure and behavior of digital systems, on digital computers are assessed. The characteristics of the four prominent languages (CDL, DDL, AHPL, ISP) are summarized. A criterion for selecting a suitable hardware description language for use in an automatic integrated circuit design environment is provided.

Computer hardware for radiologists: Part 2

International Nuclear Information System (INIS)

Indrajit, IK; Alam, A

2010-01-01

Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU), chipset, random access memory (RAM), and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. “Storage drive” is a term describing a “memory” hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. “Drive interfaces” connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular “input/output devices” used commonly with computers are the printer, monitor, mouse, and keyboard. The “bus” is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated) ISA bus. “Ports” are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the ‘ever increasing’ digital future

Computer hardware for radiologists: Part 2

Directory of Open Access Journals (Sweden)

Indrajit I

2010-01-01

Full Text Available Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU, chipset, random access memory (RAM, and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. "Storage drive" is a term describing a "memory" hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. "Drive interfaces" connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular "input/output devices" used commonly with computers are the printer, monitor, mouse, and keyboard. The "bus" is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated ISA bus. "Ports" are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the ′ever increasing′ digital future.

HwPMI: An Extensible Performance Monitoring Infrastructure for Improving Hardware Design and Productivity on FPGAs

Directory of Open Access Journals (Sweden)

Andrew G. Schmidt

2012-01-01

Full Text Available Designing hardware cores for FPGAs can quickly become a complicated task, difficult even for experienced engineers. With the addition of more sophisticated development tools and maturing high-level language-to-gates techniques, designs can be rapidly assembled; however, when the design is evaluated on the FPGA, the performance may not be what was expected. Therefore, an engineer may need to augment the design to include performance monitors to better understand the bottlenecks in the system or to aid in the debugging of the design. Unfortunately, identifying what to monitor and adding the infrastructure to retrieve the monitored data can be a challenging and time-consuming task. Our work alleviates this effort. We present the Hardware Performance Monitoring Infrastructure (HwPMI, which includes a collection of software tools and hardware cores that can be used to profile the current design, recommend and insert performance monitors directly into the HDL or netlist, and retrieve the monitored data with minimal invasiveness to the design. Three applications are used to demonstrate and evaluate HwPMI’s capabilities. The results are highly encouraging as the infrastructure adds numerous capabilities while requiring minimal effort by the designer and low resource overhead to the existing design.

Hardwares e sistemas multiagente: um estudo sobre arquiteturas híbridas

Directory of Open Access Journals (Sweden)

Rafhael Rodrigues Cunha

2015-05-01

Full Text Available Este artigo apresenta três estudos de caso sobre a aplicabilidade de arquiteturas de hardware reconfiguráveis, como FPGA, voltadas à utilização em sistemas multiagentes. Feita uma análise visando à elucidação dos resultados e das contribuições que os estudos proporcionaram aos autores, observa-se que o desenvolvimento de sistemas inteligentes depende cada vez mais de uma programação que explore o hardware ao máximo. Esse desfecho torna o uso de hardwares reconfiguráveis o mais aconselhável quando problemas computacionais complexos demandam respostas rápidas e eficientes, como nos casos estudados.

Accelerator Technology: Injection and Extraction Related Hardware: Kickers and Septa

CERN Document Server

Barnes, M J; Mertens, V

2013-01-01

This document is part of Subvolume C 'Accelerators and Colliders' of Volume 21 'Elementary Particles' of Landolt-Börnstein - Group I 'Elementary Particles, Nuclei and Atoms'. It contains the the Section '8.7 Injection and Extraction Related Hardware: Kickers and Septa' of the Chapter '8 Accelerator Technology' with the content: 8.7 Injection and Extraction Related Hardware: Kickers and Septa 8.7.1 Fast Pulsed Systems (Kickers) 8.7.2 Electrostatic and Magnetic Septa

Testing Microgravity Flight Hardware Concepts on the NASA KC-135

Science.gov (United States)

Motil, Susan M.; Harrivel, Angela R.; Zimmerli, Gregory A.

2001-01-01

This paper provides an overview of utilizing the NASA KC-135 Reduced Gravity Aircraft for the Foam Optics and Mechanics (FOAM) microgravity flight project. The FOAM science requirements are summarized, and the KC-135 test-rig used to test hardware concepts designed to meet the requirements are described. Preliminary results regarding foam dispensing, foam/surface slip tests, and dynamic light scattering data are discussed in support of the flight hardware development for the FOAM experiment.

Hardware control system using modular software under RSX-11D

International Nuclear Information System (INIS)

Kittell, R.S.; Helland, J.A.

1978-01-01

A modular software system used to control extensive hardware is described. The development, operation, and experience with this software are discussed. Included are the methods employed to implement this system while taking advantage of the Real-Time features of RSX-11D. Comparisons are made between this system and an earlier nonmodular system. The controlled hardware includes magnet power supplies, stepping motors, DVM's, and multiplexors, and is interfaced through CAMAC. 4 figures

ARM assembly language with hardware experiments

CERN Document Server

Elahi, Ata

2015-01-01

This book provides a hands-on approach to learning ARM assembly language with the use of a TI microcontroller. The book starts with an introduction to computer architecture and then discusses number systems and digital logic. The text covers ARM Assembly Language, ARM Cortex Architecture and its components, and Hardware Experiments using TILM3S1968. Written for those interested in learning embedded programming using an ARM Microcontroller. ·         Introduces number systems and signal transmission methods   ·         Reviews logic gates, registers, multiplexers, decoders and memory   ·         Provides an overview and examples of ARM instruction set   ·         Uses using Keil development tools for writing and debugging ARM assembly language Programs   ·         Hardware experiments using a Mbed NXP LPC1768 microcontroller; including General Purpose Input/Output (GPIO) configuration, real time clock configuration, binary input to 7-segment display, creating ...

Fast image processing on parallel hardware

International Nuclear Information System (INIS)

Bittner, U.

1988-01-01

Current digital imaging modalities in the medical field incorporate parallel hardware which is heavily used in the stage of image formation like the CT/MR image reconstruction or in the DSA real time subtraction. In order to image post-processing as efficient as image acquisition, new software approaches have to be found which take full advantage of the parallel hardware architecture. This paper describes the implementation of two-dimensional median filter which can serve as an example for the development of such an algorithm. The algorithm is analyzed by viewing it as a complete parallel sort of the k pixel values in the chosen window which leads to a generalization to rank order operators and other closely related filters reported in literature. A section about the theoretical base of the algorithm gives hints for how to characterize operations suitable for implementations on pipeline processors and the way to find the appropriate algorithms. Finally some results that computation time and usefulness of medial filtering in radiographic imaging are given

Open Hardware For CERN's Accelerator Control Systems

CERN Document Server

van der Bij, E; Ayass, M; Boccardi, A; Cattin, M; Gil Soriano, C; Gousiou, E; Iglesias Gonsálvez, S; Penacoba Fernandez, G; Serrano, J; Voumard, N; Wlostowski, T

2011-01-01

The accelerator control systems at CERN will be renovated and many electronics modules will be redesigned as the modules they will replace cannot be bought anymore or use obsolete components. The modules used in the control systems are diverse: analog and digital I/O, level converters and repeaters, serial links and timing modules. Overall around 120 modules are supported that are used in systems such as beam instrumentation, cryogenics and power converters. Only a small percentage of the currently used modules are commercially available, while most of them had been specifically designed at CERN. The new developments are based on VITA and PCI-SIG standards such as FMC (FPGA Mezzanine Card), PCI Express and VME64x using transition modules. As system-on-chip interconnect, the public domain Wishbone specification is used. For the renovation, it is considered imperative to have for each board access to the full hardware design and its firmware so that problems could quickly be resolved by CERN engineers or its ...

The Association of Plasminogen Activator Inhibitor Type 1 (PAI-1) Level and PAI-1 4G/5G Gene Polymorphism with the Formation and the Grade of Endometrial Cancer.

Science.gov (United States)

Yıldırım, Malik Ejder; Karakuş, Savas; Kurtulgan, Hande Küçük; Kılıçgün, Hasan; Erşan, Serpil; Bakır, Sevtap

2017-08-01

Plasminogen activator inhibitor type 1 (PAI-1) is a serine protease inhibitor (Serpine 1), and it inhibits both tissue plasminogen activator and urokinase plasminogen activator which are important in fibrinolysis. We aimed to find whether there is a possible association between PAI-1 level, PAI-1 4G/5G polymorphism, and endometrial cancer. PAI-1 levels in peripheral blood were determined in 82 patients with endometrial carcinoma and 76 female healthy controls using an enzyme-linked immunoassay (ELISA). Then, the genomic DNA was extracted and screened by reverse hybridization procedure (Strip assay) to detect PAI 1 4G/5G polymorphism. The levels of PAI-1 in the patients were higher statistically in comparison to controls (P 5G polymorphism was quite different between patients and controls (P = 0.008), and 4G allelic frequency was significantly higher in the patients of endometrial cancer than in controls (P = 0.026). We found significant difference between Grade 1 and Grade 2+3 patients in terms of the PAI-1 levels (P = 0.047). There was no association between PAI-1 4G/5G polymorphism and the grades of endometrial cancer (P = 0.993). Our data suggest that the level of PAI-1 and PAI-1 4G/5G gene polymorphism are effective in the formation of endometrial cancer. PAI-1 levels are also associated with the grades of endometrial cancer.

Secure Hardware Performance Analysis in Virtualized Cloud Environment

Directory of Open Access Journals (Sweden)

Chee-Heng Tan

2013-01-01

Full Text Available The main obstacle in mass adoption of cloud computing for database operations is the data security issue. In this paper, it is shown that IT services particularly in hardware performance evaluation in virtual machine can be accomplished effectively without IT personnel gaining access to real data for diagnostic and remediation purposes. The proposed mechanisms utilized TPC-H benchmark to achieve 2 objectives. First, the underlying hardware performance and consistency is supervised via a control system, which is constructed using a combination of TPC-H queries, linear regression, and machine learning techniques. Second, linear programming techniques are employed to provide input to the algorithms that construct stress-testing scenarios in the virtual machine, using the combination of TPC-H queries. These stress-testing scenarios serve 2 purposes. They provide the boundary resource threshold verification to the first control system, so that periodic training of the synthetic data sets for performance evaluation is not constrained by hardware inadequacy, particularly when the resources in the virtual machine are scaled up or down which results in the change of the utilization threshold. Secondly, they provide a platform for response time verification on critical transactions, so that the expected Quality of Service (QoS from these transactions is assured.

Programming languages and compiler design for realistic quantum hardware

Science.gov (United States)

Chong, Frederic T.; Franklin, Diana; Martonosi, Margaret

2017-09-01

Quantum computing sits at an important inflection point. For years, high-level algorithms for quantum computers have shown considerable promise, and recent advances in quantum device fabrication offer hope of utility. A gap still exists, however, between the hardware size and reliability requirements of quantum computing algorithms and the physical machines foreseen within the next ten years. To bridge this gap, quantum computers require appropriate software to translate and optimize applications (toolflows) and abstraction layers. Given the stringent resource constraints in quantum computing, information passed between layers of software and implementations will differ markedly from in classical computing. Quantum toolflows must expose more physical details between layers, so the challenge is to find abstractions that expose key details while hiding enough complexity.

Programming languages and compiler design for realistic quantum hardware.

Science.gov (United States)

Chong, Frederic T; Franklin, Diana; Martonosi, Margaret

2017-09-13

Quantum computing sits at an important inflection point. For years, high-level algorithms for quantum computers have shown considerable promise, and recent advances in quantum device fabrication offer hope of utility. A gap still exists, however, between the hardware size and reliability requirements of quantum computing algorithms and the physical machines foreseen within the next ten years. To bridge this gap, quantum computers require appropriate software to translate and optimize applications (toolflows) and abstraction layers. Given the stringent resource constraints in quantum computing, information passed between layers of software and implementations will differ markedly from in classical computing. Quantum toolflows must expose more physical details between layers, so the challenge is to find abstractions that expose key details while hiding enough complexity.

2D neural hardware versus 3D biological ones

Energy Technology Data Exchange (ETDEWEB)

Beiu, V.

1998-12-31

This paper will present important limitations of hardware neural nets as opposed to biological neural nets (i.e. the real ones). The author starts by discussing neural structures and their biological inspirations, while mentioning the simplifications leading to artificial neural nets. Going further, the focus will be on hardware constraints. The author will present recent results for three different alternatives of implementing neural networks: digital, threshold gate, and analog, while the area and the delay will be related to neurons' fan-in and weights' precision. Based on all of these, it will be shown why hardware implementations cannot cope with their biological inspiration with respect to their power of computation: the mapping onto silicon lacking the third dimension of biological nets. This translates into reduced fan-in, and leads to reduced precision. The main conclusion is that one is faced with the following alternatives: (1) try to cope with the limitations imposed by silicon, by speeding up the computation of the elementary silicon neurons; (2) investigate solutions which would allow one to use the third dimension, e.g. using optical interconnections.

Performance/price estimates for cortex-scale hardware: a design space exploration.

Science.gov (United States)

Zaveri, Mazad S; Hammerstrom, Dan

2011-04-01

In this paper, we revisit the concept of virtualization. Virtualization is useful for understanding and investigating the performance/price and other trade-offs related to the hardware design space. Moreover, it is perhaps the most important aspect of a hardware design space exploration. Such a design space exploration is a necessary part of the study of hardware architectures for large-scale computational models for intelligent computing, including AI, Bayesian, bio-inspired and neural models. A methodical exploration is needed to identify potentially interesting regions in the design space, and to assess the relative performance/price points of these implementations. As an example, in this paper we investigate the performance/price of (digital and mixed-signal) CMOS and hypothetical CMOL (nanogrid) technology based hardware implementations of human cortex-scale spiking neural systems. Through this analysis, and the resulting performance/price points, we demonstrate, in general, the importance of virtualization, and of doing these kinds of design space explorations. The specific results suggest that hybrid nanotechnology such as CMOL is a promising candidate to implement very large-scale spiking neural systems, providing a more efficient utilization of the density and storage benefits of emerging nano-scale technologies. In general, we believe that the study of such hypothetical designs/architectures will guide the neuromorphic hardware community towards building large-scale systems, and help guide research trends in intelligent computing, and computer engineering. Copyright © 2010 Elsevier Ltd. All rights reserved.

LISA Pathfinder: hardware tests and their input to the mission

Science.gov (United States)

Audley, Heather

The Laser Interferometer Space Antenna (LISA) is a joint ESA-NASA mission for the first space-borne gravitational wave detector. LISA aims to detect sources in the 0.1mHz to 1Hz range, which include supermassive black holes and galactic binary stars. Core technologies required for the LISA mission, including drag-free test mass control, picometre interferometry and micro-Newton thrusters, cannot be tested on-ground. Therefore, a precursor satellite, LISA Pathfinder, has been developed as a technology demonstration mission. The preparations for the LISA Pathfinder mission have reached an exciting stage. Tests of the engineering model of the optical metrology system have recently been completed at the Albert Einstein Institute, Hannover, and flight model tests are now underway. Significantly, they represent the first complete integration and testing of the space-qualified hardware and are the first tests on system level. The results and test procedures of these campaigns will be utilised directly in the ground-based flight hardware tests, and subsequently within in-flight operations. In addition, they allow valuable testing of the data analysis methods using the MatLab based LTP data analysis toolbox. This contribution presents an overview of the test campaigns calibration, control and perfor-mance results, focusing on the implications for the Experimental Master Plan which provides the basis for the in-flight operations and procedures.

A photovoltaic source I/U model suitable for hardware in the loop application

Directory of Open Access Journals (Sweden)

Stala Robert

2017-12-01

Full Text Available This paper presents a novel, low-complexity method of simulating PV source characteristics suitable for real-time modeling and hardware implementation. The application of the suitable model of the PV source as well as the model of all the PV system components in a real-time hardware gives a safe, fast and low cost method of testing PV systems. The paper demonstrates the concept of the PV array model and the hardware implementation in FPGAs of the system which combines two PV arrays. The obtained results confirm that the proposed model is of low complexity and can be suitable for hardware in the loop (HIL tests of the complex PV system control, with various arrays operating under different conditions.

Establishing Proficiency Levels for the Delaware Student Testing Program in Science and Social Studies, Grades 4 & 6. Report and Recommendations to the Delaware State Board of Education.

Science.gov (United States)

Delaware State Dept. of Education, Dover. Assessment and Accountability Branch.

This document contains the results of a standard setting conducted in January 2002 on the Delaware Student Testing Program (DSTP) Science and Social Studies tests at grades 4 and 6. Each standard setting process entailed convening four groups, one for each grade level and content area, and each group met for 2 days. At the standard setting judges…

Clinical and molecular features of high-grade osteosarcoma

NARCIS (Netherlands)

Anninga, Jakob Klaas

2013-01-01

It can be concluded from this thesis that high-grade osteosarcoma is at clinical, pathological and molecular level a heterogeneous disease. To treat high-grade osteosarcoma, neo-adjuvant chemotherapy should be combined with radical surgery, irrespective the localization. There are only 4 effective

[Low level auditory skills compared to writing skills in school children attending third and fourth grade: evidence for the rapid auditory processing deficit theory?].

Science.gov (United States)

Ptok, M; Meisen, R

2008-01-01

The rapid auditory processing defi-cit theory holds that impaired reading/writing skills are not caused exclusively by a cognitive deficit specific to representation and processing of speech sounds but arise due to sensory, mainly auditory, deficits. To further explore this theory we compared different measures of auditory low level skills to writing skills in school children. prospective study. School children attending third and fourth grade. just noticeable differences for intensity and frequency (JNDI, JNDF), gap detection (GD) monaural and binaural temporal order judgement (TOJb and TOJm); grade in writing, language and mathematics. correlation analysis. No relevant correlation was found between any auditory low level processing variable and writing skills. These data do not support the rapid auditory processing deficit theory.

A Comparison of the Capability of Sensitivity Level 3 and Sensitivity Level 4 Fluorescent Penetrants to Detect Fatigue Cracks in Aluminum

Science.gov (United States)

Parker, Bradford, H.

2009-01-01

Historically both sensitivity level 3 and sensitivity level 4 fluorescent penetrants have been used to perform NASA Standard Level inspections of aerospace hardware. In April 2008, NASA-STD-5009 established a requirement that only sensitivity level 4 penetrants were acceptable for inspections of NASA hardware. Having NASA contractors change existing processes or perform demonstration tests to certify sensitivity level 3 penetrants posed a potentially huge cost to the Agency. This study was conducted to directly compare the probability of detection sensitivity level 3 and level 4 penetrants using both Method A and Method D inspection processes. The study results strongly support the conclusion that sensitivity level 3 penetrants are acceptable for NASA Standard Level inspections

Hardware detection and parameter tuning method for speed control system of PMSM

Science.gov (United States)

Song, Zhengqiang; Yang, Huiling

2018-03-01

In this paper, the development of permanent magnet synchronous motor AC speed control system is taken as an example, aiming to expound the principle and parameter setting method of the system hardware, and puts forward the method of using software or hardware to eliminate the problem.

Grading standards, prepared by the Configuration Management Office

International Nuclear Information System (INIS)

Cort, G.; Donahue, S.; Frank, J.; Perkins, B.; Wrye, J.

1994-01-01

This report describes the grading methodology used by the organization to determine the required levels of configuration management for all controlled elements that are part of the nuclear facility and its operation. The goal is to have a flexible grading system that accurately reflects the overall operational environment. The grading methodology should identify which items, processes, and information should be incorporated into facility baselines as controlled elements; and specify the level of formality that should be applied to activities that employ or impact these controlled elements. Evaluation categories include the following: radiological damage to workers; toxicological damage to workers; industrial safety; environmental damage; property damage; facility availability; cost effect; reputation; and commitments

Robustness of spiking Deep Belief Networks to noise and reduced bit precision of neuro-inspired hardware platforms.

Science.gov (United States)

Stromatias, Evangelos; Neil, Daniel; Pfeiffer, Michael; Galluppi, Francesco; Furber, Steve B; Liu, Shih-Chii

2015-01-01

Increasingly large deep learning architectures, such as Deep Belief Networks (DBNs) are the focus of current machine learning research and achieve state-of-the-art results in different domains. However, both training and execution of large-scale Deep Networks require vast computing resources, leading to high power requirements and communication overheads. The on-going work on design and construction of spike-based hardware platforms offers an alternative for running deep neural networks with significantly lower power consumption, but has to overcome hardware limitations in terms of noise and limited weight precision, as well as noise inherent in the sensor signal. This article investigates how such hardware constraints impact the performance of spiking neural network implementations of DBNs. In particular, the influence of limited bit precision during execution and training, and the impact of silicon mismatch in the synaptic weight parameters of custom hybrid VLSI implementations is studied. Furthermore, the network performance of spiking DBNs is characterized with regard to noise in the spiking input signal. Our results demonstrate that spiking DBNs can tolerate very low levels of hardware bit precision down to almost two bits, and show that their performance can be improved by at least 30% through an adapted training mechanism that takes the bit precision of the target platform into account. Spiking DBNs thus present an important use-case for large-scale hybrid analog-digital or digital neuromorphic platforms such as SpiNNaker, which can execute large but precision-constrained deep networks in real time.

Design of hardware accelerators for demanding applications.

NARCIS (Netherlands)

Jozwiak, L.; Jan, Y.

2010-01-01

This paper focuses on mastering the architecture development of hardware accelerators. It presents the results of our analysis of the main issues that have to be addressed when designing accelerators for modern demanding applications, when using as an example the accelerator design for LDPC decoding

Introduction to 6800/6802 microprocessor systems hardware, software and experimentation

CERN Document Server

Simpson, Robert J

1987-01-01

Introduction to 6800/6802 Microprocessor Systems: Hardware, Software and Experimentation introduces the reader to the features, characteristics, operation, and applications of the 6800/6802 microprocessor and associated family of devices. Many worked examples are included to illustrate the theoretical and practical aspects of the 6800/6802 microprocessor.Comprised of six chapters, this book begins by presenting several aspects of digital systems before introducing the concepts of fetching and execution of a microprocessor instruction. Details and descriptions of hardware elements (MPU, RAM, RO

CAMAC high energy physics electronics hardware

International Nuclear Information System (INIS)

Kolpakov, I.F.

1977-01-01

CAMAC hardware for high energy physics large spectrometers and control systems is reviewed as is the development of CAMAC modules at the High Energy Laboratory, JINR (Dubna). The total number of crates used at the Laboratory is 179. The number of CAMAC modules of 120 different types exceeds 1700. The principles of organization and the structure of developed CAMAC systems are described. (author)

Secondary Schools Curriculum Guide, Mathematics, Grades 10-12, Levels 87-112.

Science.gov (United States)

Rogers, Arnold R., Ed.; And Others

Behavioral objectives for geometry, algebra, computer mathematics, trigonometry, analytic geometry, calculus, and probability are specified for grades 10 through 12. General objectives are stated for major areas under each topic and are followed by a list of specific objectives for that area. This work was prepared under an ESEA Title III…

Hardware Realization of Chaos Based Symmetric Image Encryption

KAUST Repository

Barakat, Mohamed L.

2012-01-01

This thesis presents a novel work on hardware realization of symmetric image encryption utilizing chaos based continuous systems as pseudo random number generators. Digital implementation of chaotic systems results in serious degradations

Design of a Hardware Track Finder (Fast Tracker) for the ATLAS Trigger

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00010976; Albicocco, P.; Alison, J.; Ancu, L.S.; Anderson, J.; Andari, N.; Andreani, A.; Andreazza, A.; Annovi, A.; Antonelli, M.; Asbah, N.; Atkinson, M.; Baines, J.; Barberio, E.; Beccherle, R.; Beretta, M.; Bertolucci, F.; Biesuz, N.V.; Blair, R.; Bogdan, M.; Boveia, A.; Britzger, D.; Bryant, P.; Burghgrave, B.; Calderini, G.; Camplani, A.; Cavasinni, V.; Chakraborty, D.; Chang, P.; Cheng, Y.; Citraro, S.; Citterio, M.; Crescioli, F.; Dawe, N.; Dell'Orso, M.; Donati, S.; Dondero, P.; Drake, G.; Gadomski, S.; Gatta, M.; Gentsos, C.; Giannetti, P.; Gkaitatzis, S.; Gramling, J.; Howarth, J.W.; Iizawa, T.; Ilic, N.; Jiang, Z.; Kaji, T.; Kasten, M.; Kawaguchi, Y.; Kim, Y.K.; Kimura, N.; Klimkovich, T.; Kolb, M.; Kordas, K.; Krizka, K.; Kubota, T.; Lanza, A.; Li, H.L.; Liberali, V.; Lisovyi, M.; Liu, L.; Love, J.; Luciano, P.; Luongo, C.; Magalotti, D.; Maznas, I.; Meroni, C.; Mitani, T.; Nasimi, H.; Negri, A.; Neroutsos, P.; Neubauer, M.; Nikolaidis, S.; Okumura, Y.; Pandini, C.; Petridou, C.; Piendibene, M.; Proudfoot, J.; Rados, P.; Roda, C.; Rossi, E.; Sakurai, Y.; Sampsonidis, D.; Saxon, J.; Schmitt, S.; Schoening, A.; Shochet, M.; Shojaii, S.; Soltveit, H.; Sotiropoulou, C.L.; Stabile, A.; Swiatlowski, M.; Tang, F.; Taylor, P.T.; Testa, M.; Tompkins, L.; Vercesi, V.; Volpi, G.; Wang, R.; Watari, R.; Webster, J.; Wu, X.; Yorita, K.; Yurkewicz, A.; Zeng, J.C.; Zhang, J.; Zou, R.

2016-01-01

The use of tracking information at the trigger level in the LHC Run II period is crucial for the trigger an data acquisition (TDAQ) system and will be even more so as contemporary collisions that occur at every bunch crossing will increase in Run III. The Fast TracKer (FTK) is part of the ATLAS trigger upgrade project; it is a hardware processor that will provide every Level-1 accepted event (100 kHz) and within 100$\\mu$s, full tracking information for tracks with momentum as low as 1 GeV. Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance.

Asymmetric Hardware Distortions in Receive Diversity Systems: Outage Performance Analysis

KAUST Repository

Javed, Sidrah; Amin, Osama; Ikki, Salama S.; Alouini, Mohamed-Slim

2017-01-01

This paper studies the impact of asymmetric hardware distortion (HWD) on the performance of receive diversity systems using linear and switched combining receivers. The asymmetric attribute of the proposed model motivates the employment of improper Gaussian signaling (IGS) scheme rather than the traditional proper Gaussian signaling (PGS) scheme. The achievable rate performance is analyzed for the ideal and non-ideal hardware scenarios using PGS and IGS transmission schemes for different combining receivers. In addition, the IGS statistical characteristics are optimized to maximize the achievable rate performance. Moreover, the outage probability performance of the receive diversity systems is analyzed yielding closed form expressions for both PGS and IGS based transmission schemes. HWD systems that employ IGS is proven to efficiently combat the self interference caused by the HWD. Furthermore, the obtained analytic expressions are validated through Monte-Carlo simulations. Eventually, non-ideal hardware transceivers degradation and IGS scheme acquired compensation are quantified through suitable numerical results.

Reconfigurable Signal Processing and Hardware Architecture for Broadband Wireless Communications

Directory of Open Access Journals (Sweden)

Liang Ying-Chang

2005-01-01

Full Text Available This paper proposes a broadband wireless transceiver which can be reconfigured to any type of cyclic-prefix (CP -based communication systems, including orthogonal frequency-division multiplexing (OFDM, single-carrier cyclic-prefix (SCCP system, multicarrier (MC code-division multiple access (MC-CDMA, MC direct-sequence CDMA (MC-DS-CDMA, CP-based CDMA (CP-CDMA, and CP-based direct-sequence CDMA (CP-DS-CDMA. A hardware platform is proposed and the reusable common blocks in such a transceiver are identified. The emphasis is on the equalizer design for mobile receivers. It is found that after block despreading operation, MC-DS-CDMA and CP-DS-CDMA have the same equalization blocks as OFDM and SCCP systems, respectively, therefore hardware and software sharing is possible for these systems. An attempt has also been made to map the functional reconfigurable transceiver onto the proposed hardware platform. The different functional entities which will be required to perform the reconfiguration and realize the transceiver are explained.

Asymmetric Hardware Distortions in Receive Diversity Systems: Outage Performance Analysis

KAUST Repository

Javed, Sidrah

2017-02-22

This paper studies the impact of asymmetric hardware distortion (HWD) on the performance of receive diversity systems using linear and switched combining receivers. The asymmetric attribute of the proposed model motivates the employment of improper Gaussian signaling (IGS) scheme rather than the traditional proper Gaussian signaling (PGS) scheme. The achievable rate performance is analyzed for the ideal and non-ideal hardware scenarios using PGS and IGS transmission schemes for different combining receivers. In addition, the IGS statistical characteristics are optimized to maximize the achievable rate performance. Moreover, the outage probability performance of the receive diversity systems is analyzed yielding closed form expressions for both PGS and IGS based transmission schemes. HWD systems that employ IGS is proven to efficiently combat the self interference caused by the HWD. Furthermore, the obtained analytic expressions are validated through Monte-Carlo simulations. Eventually, non-ideal hardware transceivers degradation and IGS scheme acquired compensation are quantified through suitable numerical results.

Qualification of software and hardware

International Nuclear Information System (INIS)

Gossner, S.; Schueller, H.; Gloee, G.

1987-01-01

The qualification of on-line process control equipment is subdivided into three areas: 1) materials and structural elements; 2) on-line process-control components and devices; 3) electrical systems (reactor protection and confinement system). Microprocessor-aided process-control equipment are difficult to verify for failure-free function owing to the complexity of the functional structures of the hardware and to the variety of the software feasible for microprocessors. Hence, qualification will make great demands on the inspecting expert. (DG) [de

Rupture hardware minimization in pressurized water reactor piping

International Nuclear Information System (INIS)

Mukherjee, S.K.; Ski, J.J.; Chexal, V.; Norris, D.M.; Goldstein, N.A.; Beaudoin, B.F.; Quinones, D.F.; Server, W.L.

1989-01-01

For much of the high-energy piping in light reactor systems, fracture mechanics calculations can be used to assure pipe failure resistance, thus allowing the elimination of excessive rupture restraint hardware both inside and outside containment. These calculations use the concept of leak-before-break (LBB) and include part-through-wall flaw fatigue crack propagation, through-wall flaw detectable leakage, and through-wall flaw stability analyses. Performing these analyses not only reduces initial construction, future maintenance, and radiation exposure costs, but also improves the overall safety and integrity of the plant since much more is known about the piping and its capabilities than would be the case had the analyses not been performed. This paper presents the LBB methodology applied a Beaver Valley Power Station- Unit 2 (BVPS-2); the application for two specific lines, one inside containment (stainless steel) and the other outside containment (ferrutic steel), is shown in a generic sense using a simple parametric matrix. The overall results for BVPS-2 indicate that pipe rupture hardware is not necessary for stainless steel lines inside containment greater than or equal to 6-in. (152-mm) nominal pipe size that have passed a screening criteria designed to eliminate potential problem systems (such as the feedwater system). Similarly, some ferritic steel line as small as 3-in. (76-mm) diameter (outside containment) can qualify for pipe rupture hardware elemination

7 CFR 810.2204 - Grades and grade requirements for wheat.

Science.gov (United States)

2010-01-01

... 7 Agriculture 7 2010-01-01 2010-01-01 false Grades and grade requirements for wheat. 810.2204... OFFICIAL UNITED STATES STANDARDS FOR GRAIN United States Standards for Wheat Principles Governing the Application of Standards § 810.2204 Grades and grade requirements for wheat. (a) Grades and grade requirements...

Multi-loop PWR modeling and hardware-in-the-loop testing using ACSL

International Nuclear Information System (INIS)

Thomas, V.M.; Heibel, M.D.; Catullo, W.J.

1989-01-01

Westinghouse has developed an Advanced Digital Feedwater Control System (ADFCS) which is aimed at reducing feedwater related reactor trips through improved control performance for pressurized water reactor (PWR) power plants. To support control system setpoint studies and functional design efforts for the ADFCS, an ACSL based model of the nuclear steam supply system (NSSS) of a Westinghouse (PWR) was generated. Use of this plant model has been extended from system design to system testing through integration of the model into a Hardware-in-Loop test environment for the ADFCS. This integration includes appropriate interfacing between a Gould SEL 32/87 computer, upon which the plant model executes in real time, and the Westinghouse Distributed Processing family (WDPF) test hardware. A development program has been undertaken to expand the existing ACSL model to include capability to explicitly model multiple plant loops, steam generators, and corresponding feedwater systems. Furthermore, the program expands the ADFCS Hardware-in-Loop testing to include the multi-loop plant model. This paper provides an overview of the testing approach utilized for the ADFCS with focus on the role of Hardware-in-Loop testing. Background on the plant model, methodology and test environment is also provided. Finally, an overview is presented of the program to expand the model and associated Hardware-in-Loop test environment to handle multiple loops

Hardware architecture for projective model calculation and false match refining using random sample consensus algorithm

Science.gov (United States)

Azimi, Ehsan; Behrad, Alireza; Ghaznavi-Ghoushchi, Mohammad Bagher; Shanbehzadeh, Jamshid

2016-11-01

The projective model is an important mapping function for the calculation of global transformation between two images. However, its hardware implementation is challenging because of a large number of coefficients with different required precisions for fixed point representation. A VLSI hardware architecture is proposed for the calculation of a global projective model between input and reference images and refining false matches using random sample consensus (RANSAC) algorithm. To make the hardware implementation feasible, it is proved that the calculation of the projective model can be divided into four submodels comprising two translations, an affine model and a simpler projective mapping. This approach makes the hardware implementation feasible and considerably reduces the required number of bits for fixed point representation of model coefficients and intermediate variables. The proposed hardware architecture for the calculation of a global projective model using the RANSAC algorithm was implemented using Verilog hardware description language and the functionality of the design was validated through several experiments. The proposed architecture was synthesized by using an application-specific integrated circuit digital design flow utilizing 180-nm CMOS technology as well as a Virtex-6 field programmable gate array. Experimental results confirm the efficiency of the proposed hardware architecture in comparison with software implementation.

A Cost-Effective Approach to Hardware-in-the-Loop Simulation

DEFF Research Database (Denmark)

Pedersen, Mikkel Melters; Hansen, M. R.; Ballebye, M.

2012-01-01

This paper presents an approach for developing cost effective hardware-in-the- loop (HIL) simulation platforms for the use in controller software test and development. The approach is aimed at the many smaller manufacturers of e.g. mobile hydraulic machinery, which often do not have very advanced...... testing facilities at their disposal. A case study is presented where a HIL simulation platform is developed for the controller of a truck mounted loader crane. The total expenses in hardware and software is less than 10.000$....

Electrical, electronics, and digital hardware essentials for scientists and engineers

CERN Document Server

Lipiansky, Ed

2012-01-01

A practical guide for solving real-world circuit board problems Electrical, Electronics, and Digital Hardware Essentials for Scientists and Engineers arms engineers with the tools they need to test, evaluate, and solve circuit board problems. It explores a wide range of circuit analysis topics, supplementing the material with detailed circuit examples and extensive illustrations. The pros and cons of various methods of analysis, fundamental applications of electronic hardware, and issues in logic design are also thoroughly examined. The author draws on more than tw

Carbonate fuel cell endurance: Hardware corrosion and electrolyte management status

Energy Technology Data Exchange (ETDEWEB)

Yuh, C.; Johnsen, R.; Farooque, M.; Maru, H.

1993-01-01

Endurance tests of carbonate fuel cell stacks (up to 10,000 hours) have shown that hardware corrosion and electrolyte losses can be reasonably controlled by proper material selection and cell design. Corrosion of stainless steel current collector hardware, nickel clad bipolar plate and aluminized wet seal show rates within acceptable limits. Electrolyte loss rate to current collector surface has been minimized by reducing exposed current collector surface area. Electrolyte evaporation loss appears tolerable. Electrolyte redistribution has been restrained by proper design of manifold seals.

Carbonate fuel cell endurance: Hardware corrosion and electrolyte management status

Energy Technology Data Exchange (ETDEWEB)

Yuh, C.; Johnsen, R.; Farooque, M.; Maru, H.

1993-05-01

Endurance tests of carbonate fuel cell stacks (up to 10,000 hours) have shown that hardware corrosion and electrolyte losses can be reasonably controlled by proper material selection and cell design. Corrosion of stainless steel current collector hardware, nickel clad bipolar plate and aluminized wet seal show rates within acceptable limits. Electrolyte loss rate to current collector surface has been minimized by reducing exposed current collector surface area. Electrolyte evaporation loss appears tolerable. Electrolyte redistribution has been restrained by proper design of manifold seals.

The management of moderation of school based assessment at Grade 12 level in the Gauteng province

OpenAIRE

2012-01-01

D.Phil. In 2000, the incumbent Minister of Education, Professor Kader Asmal, mandated the inclusion of school based assessment (SBA) as a component of Senior Certificate (Grade 12) assessment across all examining bodies in the country. Prior to this, the Senior Certificate (Grade 12) examination was a “once off” terminal examination at the end of twelve years of schooling. The rationale for the inclusion of SBA as a component of the Senior Certificate (Grade 12) was to remove the focus fro...

Summary of multi-core hardware and programming model investigations

Energy Technology Data Exchange (ETDEWEB)

Kelly, Suzanne Marie; Pedretti, Kevin Thomas Tauke; Levenhagen, Michael J.

2008-05-01

This report summarizes our investigations into multi-core processors and programming models for parallel scientific applications. The motivation for this study was to better understand the landscape of multi-core hardware, future trends, and the implications on system software for capability supercomputers. The results of this study are being used as input into the design of a new open-source light-weight kernel operating system being targeted at future capability supercomputers made up of multi-core processors. A goal of this effort is to create an agile system that is able to adapt to and efficiently support whatever multi-core hardware and programming models gain acceptance by the community.

Hardware Realization of Chaos-based Symmetric Video Encryption

KAUST Repository

Ibrahim, Mohamad A.

2013-01-01

This thesis reports original work on hardware realization of symmetric video encryption using chaos-based continuous systems as pseudo-random number generators. The thesis also presents some of the serious degradations caused by digitally

Control/interlock/display system for EBT-P using commercially-available hardware and firmware

International Nuclear Information System (INIS)

Schmitt, R.J.

1983-01-01

For the EBT-P project, alternative commercially-available hardware, software and firmware have been employed for control, interlock and data display functions. This paper describes the criteria and rationale used to select that commercial equipment and discusses the important features of the equipment chosen, especially programmable controllers. Additional discussion is centered on interface problems which are encountered upon attempts to integrate equipment from several vendors. Some solutions to these problems are discussed. Details of software and hardware performance during tests are presented. The extent to which the EBT-P hardware and software configuration addresses and resolves various issues is discussed. Several areas have been uncovered in which relatively slight improvements/modifications of commercial programmable controller firmware would significantly improve the capability of this type of hardware in fusion control applications. These improvements are discussed in detail

A better norm-referenced grading using the standard deviation criterion.

Science.gov (United States)

Chan, Wing-shing

2014-01-01

The commonly used norm-referenced grading assigns grades to rank-ordered students in fixed percentiles. It has the disadvantage of ignoring the actual distance of scores among students. A simple norm-referenced grading via standard deviation is suggested for routine educational grading. The number of standard deviation of a student's score from the class mean was used as the common yardstick to measure achievement level. Cumulative probability of a normal distribution was referenced to help decide the amount of students included within a grade. RESULTS of the foremost 12 students from a medical examination were used for illustrating this grading method. Grading by standard deviation seemed to produce better cutoffs in allocating an appropriate grade to students more according to their differential achievements and had less chance in creating arbitrary cutoffs in between two similarly scored students than grading by fixed percentile. Grading by standard deviation has more advantages and is more flexible than grading by fixed percentile for norm-referenced grading.

Digital Hardware Design Teaching: An Alternative Approach

Science.gov (United States)

Benkrid, Khaled; Clayton, Thomas

2012-01-01

This article presents the design and implementation of a complete review of undergraduate digital hardware design teaching in the School of Engineering at the University of Edinburgh. Four guiding principles have been used in this exercise: learning-outcome driven teaching, deep learning, affordability, and flexibility. This has identified…

A Fast Hardware Tracker for the ATLAS Trigger System

CERN Document Server

Kimura, N; The ATLAS collaboration

2012-01-01

Selecting interesting events with triggering is very challenging at the LHC due to the busy hadronic environment. Starting in 2014 the LHC will run with an energy of 14TeV and instantaneous luminosities which could exceed 10^34 interactions per cm^2 and per second. The triggering in the ATLAS detector is realized using a three level trigger approach, in which the first level (L1) is hardware based and the second (L2) and third (EF) stag are realized using large computing farms. It is a crucial and non-trivial task for triggering to maintain a high efficiency for events of interest while suppressing effectively the very high rates of inclusive QCD process, which constitute mainly background. At the same time the trigger system has to be robust and provide sufficient operational margins to adapt to changes in the running environment. In the current design track reconstruction can be performed only in limited regions of interest at L2 and the CPU requirements may limit this even further at the highest instantane...

Linguistic Feature Development Across Grades and Genre in Elementary Writing.

Science.gov (United States)

Hall-Mills, Shannon; Apel, Kenn

2015-07-01

As children develop skills in writing across academic contexts, clinicians and educators need to have a fundamental understanding of typical writing development as well as valid and reliable assessment methods. The purpose of this study was to examine the progression of linguistic elements in school-age children's narrative and expository writing development. Narrative and expository writing samples produced by 89 children in Grades 2 through 4 were analyzed at the microstructure and macrostructure levels. Measures of receptive vocabulary, word-level reading, and reading comprehension were obtained. Exploratory factor analyses revealed 4 microstructure factors (e.g., productivity, grammatical complexity, grammatical accuracy, and lexical density) and 1 macrostructure factor (e.g., a combination of organization, text structure, and cohesion). Multivariate analyses of covariance with reading comprehension as a covariate showed that productivity and macrostructure were sensitive to grade-level and genre differences and that expository grammatical complexity was sensitive to grade-level differences. Findings are discussed in light of grade-level standards for narrative and expository writing and current practices in writing assessment. Multiple suggestions are offered for clinical and educational implications, and specific directions are provided for future research.

Development of a hardware-in-loop attitude control simulator for a CubeSat satellite

Science.gov (United States)

Tapsawat, Wittawat; Sangpet, Teerawat; Kuntanapreeda, Suwat

2018-01-01

Attitude control is an important part in satellite on-orbit operation. It greatly affects the performance of satellites. Testing of an attitude determination and control subsystem (ADCS) is very challenging since it might require attitude dynamics and space environment in the orbit. This paper develops a low-cost hardware-in-loop (HIL) simulator for testing an ADCS of a CubeSat satellite. The simulator consists of a numerical simulation part, a hardware part, and a HIL interface hardware unit. The numerical simulation part includes orbital dynamics, attitude dynamics and Earth’s magnetic field. The hardware part is the real ADCS board of the satellite. The simulation part outputs satellite’s angular velocity and geomagnetic field information to the HIL interface hardware. Then, based on this information, the HIL interface hardware generates I2C signals mimicking the signals of the on-board rate-gyros and magnetometers and consequently outputs the signals to the ADCS board. The ADCS board reads the rate-gyro and magnetometer signals, calculates control signals, and drives the attitude actuators which are three magnetic torquers (MTQs). The responses of the MTQs sensed by a separated magnetometer are feedback to the numerical simulation part completing the HIL simulation loop. Experimental studies are conducted to demonstrate the feasibility and effectiveness of the simulator.

The NIDS Cluster: Scalable, Stateful Network Intrusion Detection on Commodity Hardware

Energy Technology Data Exchange (ETDEWEB)

Tierney, Brian L; Vallentin, Matthias; Sommer, Robin; Lee, Jason; Leres, Craig; Paxson, Vern; Tierney, Brian

2007-09-19

In this work we present a NIDS cluster as a scalable solution for realizing high-performance, stateful network intrusion detection on commodity hardware. The design addresses three challenges: (i) distributing traffic evenly across an extensible set of analysis nodes in a fashion that minimizes the communication required for coordination, (ii) adapting the NIDS's operation to support coordinating its low-level analysis rather than just aggregating alerts; and (iii) validating that the cluster produces sound results. Prototypes of our NIDS cluster now operate at the Lawrence Berkeley National Laboratory and the University of California at Berkeley. In both environments the clusters greatly enhance the power of the network security monitoring.

Direct behavior rating as a school-based behavior screener for elementary and middle grades.

Science.gov (United States)

Chafouleas, Sandra M; Kilgus, Stephen P; Jaffery, Rose; Riley-Tillman, T Chris; Welsh, Megan; Christ, Theodore J

2013-06-01

The purpose of this study was to investigate how Direct Behavior Rating Single Item Scales (DBR-SIS) involving targets of academically engaged, disruptive, and respectful behaviors function in school-based screening assessment. Participants included 831 students in kindergarten through eighth grades who attended schools in the northeastern United States. Teachers provided behavior ratings for a sample of students in their classrooms on the DBR-SIS, the Behavioral and Emotional Screening System (Kamphaus & Reynolds, 2007), and the Student Risk Screening Scale (Drummond, 1994). Given variations in rating procedures to accommodate scheduling differences across grades, analysis was conducted separately for elementary school and middle school grade levels. Results suggested that the recommended cut scores, the combination of behavior targets, and the resulting conditional probability indices varied depending on grade level grouping (lower elementary, upper elementary, middle). For example, for the lower elementary grade level grouping, a combination of disruptive behavior (cut score=2) and academically engaged behavior (cut score=8) was considered to offer the best balance among indices of diagnostic accuracy, whereas a cut score of 1 for disruptive behavior and 8 for academically engaged behavior were recommended for the upper elementary school grade level grouping and cut scores of 1 and 9, respectively, were suggested for middle school grade level grouping. Generally, DBR-SIS cut scores considered optimal for screening using single or combined targets including academically engaged behavior and disruptive behavior by offering a reasonable balance of indices for sensitivity (.51-.90), specificity (.47-.83), negative predictive power (.94-.98), and positive predictive power (.14-.41). The single target of respectful behavior performed poorly across all grade level groups, and performance of DBR-SIS targets was relatively better in the elementary school than middle

Laser-controlled land grading for farmland drainage in the Red River Valley: an economic evaluation

International Nuclear Information System (INIS)

Edwardson, S.; Watt, D.; Disrud, L.

1988-01-01

A study was conducted in the Red River Valley to evaluate the benefits of laser land grading for drainage. Graded fields were compared with ungraded fields to measure changes in crop yields due to better drainage on the graded fields. Cut-and-fill areas were studied in graded fields to evaluate the effect of grading on nutrient levels and crop uniformity. Potential cut-and-fill areas on an ungraded field were also studied for yield uniformity and nutrient levels and compared with the graded field. Crop maturity and yield were more uniform on graded fields (0.05 level of significance) than on ungraded fields. Aerial photographs indicated graded fields had more uniform drainage and, consequently, more uniform crop maturity at harvest. A method is presented for determining the economic feasibility of land grading based upon the percentage of land lost to drown out, the value of the crop, and the cost of grading. The economic analysis indicates that land grading on the areas studied resulted in an 8-year payback and a positive investment return for a longer period of time. (author)

Raman spectroscopy for grading of live osteosarcoma cells.

Science.gov (United States)

Chiang, Yi-Hung; Wu, Stewart H; Kuo, Yi-Chun; Chen, How-Foo; Chiou, Arthur; Lee, Oscar K

2015-04-18

Osteosarcoma is the most common primary malignant bone tumor, and the grading of osteosarcoma cells relies on traditional histopathology and molecular biology methods, which require RNA extraction, protein isolation and immunohistological staining. All these methods require cell isolation, lysis or fixation, which is time-consuming and requires certain amount of tumor specimen. In this study, we report the use of Raman spectroscopy for grading of malignant osteosarcoma cells. We demonstrate that, based on the detection of differential production of mineral species, Raman spectroscopy can be used as a live cell analyzer to accurately assess the grades of osteosarcoma cells by evaluating their mineralization levels. Mineralization level was assessed by measuring amount of hydroxyapatite (HA), which is highly expressed in mature osteoblasts, but not in poorly differentiated osteosarcoma cell or mesenchymal stem cells, the putative cell-of-origin of osteosarcoma. We found that under Raman spectroscopy, the level of HA production was high in MG-63 cells, which are low-grade. Moreover, hydroxyapatite production was low in high-grade osteosarcoma cells such as 143B and SaOS2 cells (p Raman spectroscopy for the measurement of HA production by the protocol reported in this study may serve as a useful tool to rapidly and accurately assess the degree of malignancy in osteosarcoma cells in a label-free manner. Such application may shorten the period of pathological diagnosis and may benefit patients who are inflicted with osteosarcoma.

Evaluating the scalability of HEP software and multi-core hardware

CERN Document Server

Jarp, S; Leduc, J; Nowak, A

2011-01-01

As researchers have reached the practical limits of processor performance improvements by frequency scaling, it is clear that the future of computing lies in the effective utilization of parallel and multi-core architectures. Since this significant change in computing is well underway, it is vital for HEP programmers to understand the scalability of their software on modern hardware and the opportunities for potential improvements. This work aims to quantify the benefit of new mainstream architectures to the HEP community through practical benchmarking on recent hardware solutions, including the usage of parallelized HEP applications.

Water system hardware and management rehabilitation: Qualitative evidence from Ghana, Kenya, and Zambia.

Science.gov (United States)

Klug, Tori; Shields, Katherine F; Cronk, Ryan; Kelly, Emma; Behnke, Nikki; Lee, Kristen; Bartram, Jamie

2017-05-01

Sufficient, safe, continuously available drinking water is important for human health and development, yet one in three handpumps in sub-Saharan Africa are non-functional at any given time. Community management, coupled with access to external technical expertise and spare parts, is a widely promoted model for rural water supply management. However, there is limited evidence describing how community management can address common hardware and management failures of rural water systems in sub-Saharan Africa. We identified hardware and management rehabilitation pathways using qualitative data from 267 interviews and 57 focus group discussions in Ghana, Kenya, and Zambia. Study participants were water committee members, community members, and local leaders in 18 communities (six in each study country) with water systems managed by a water committee and supported by World Vision (WV), an international non-governmental organization (NGO). Government, WV or private sector employees engaged in supporting the water systems were also interviewed. Inductive analysis was used to allow for pathways to emerge from the data, based on the perspectives and experiences of study participants. Four hardware rehabilitation pathways were identified, based on the types of support used in rehabilitation. Types of support were differentiated as community or external. External support includes financial and/or technical support from government or WV employees. Community actor understanding of who to contact when a hardware breakdown occurs and easy access to technical experts were consistent reasons for rapid rehabilitation for all hardware rehabilitation pathways. Three management rehabilitation pathways were identified. All require the involvement of community leaders and were best carried out when the action was participatory. The rehabilitation pathways show how available resources can be leveraged to restore hardware breakdowns and management failures for rural water systems in sub

Trainable hardware for dynamical computing using error backpropagation through physical media.

Science.gov (United States)

Hermans, Michiel; Burm, Michaël; Van Vaerenbergh, Thomas; Dambre, Joni; Bienstman, Peter

2015-03-24

Neural networks are currently implemented on digital Von Neumann machines, which do not fully leverage their intrinsic parallelism. We demonstrate how to use a novel class of reconfigurable dynamical systems for analogue information processing, mitigating this problem. Our generic hardware platform for dynamic, analogue computing consists of a reciprocal linear dynamical system with nonlinear feedback. Thanks to reciprocity, a ubiquitous property of many physical phenomena like the propagation of light and sound, the error backpropagation-a crucial step for tuning such systems towards a specific task-can happen in hardware. This can potentially speed up the optimization process significantly, offering important benefits for the scalability of neuro-inspired hardware. In this paper, we show, using one experimentally validated and one conceptual example, that such systems may provide a straightforward mechanism for constructing highly scalable, fully dynamical analogue computers.

High–Level Control System for Biomimetic Autonomous Under-water Vehicle

Directory of Open Access Journals (Sweden)

Praczyk Tomasz

2017-01-01

Full Text Available Usually, a rough software architecture designed for a robot can be can be shortly presented in the form of layers. The lowest layer is responsible for direct control of the hardware, i.e. engines, energy system, sensors, navigation devices, etc. A next layer is a low–level control which knows how to use the hardware in order to achieve a desired state of the robot, e.g. to stay on a desired course. And the last layer, the layer which is the nearest to the human–operator, is a high–level control which decides how to use the low–level control and sometimes also individual pieces of the hardware to achieve predefined objectives. The paper describes architecture, tasks and operation of the high–level control system (HLCS designed for Biomimetic Autonomous Underwater Vehicle (BAUV.

FPGA-Based Efficient Hardware/Software Co-Design for Industrial Systems with Consideration of Output Selection

Science.gov (United States)

Deliparaschos, Kyriakos M.; Michail, Konstantinos; Zolotas, Argyrios C.; Tzafestas, Spyros G.

2016-05-01

This work presents a field programmable gate array (FPGA)-based embedded software platform coupled with a software-based plant, forming a hardware-in-the-loop (HIL) that is used to validate a systematic sensor selection framework. The systematic sensor selection framework combines multi-objective optimization, linear-quadratic-Gaussian (LQG)-type control, and the nonlinear model of a maglev suspension. A robustness analysis of the closed-loop is followed (prior to implementation) supporting the appropriateness of the solution under parametric variation. The analysis also shows that quantization is robust under different controller gains. While the LQG controller is implemented on an FPGA, the physical process is realized in a high-level system modeling environment. FPGA technology enables rapid evaluation of the algorithms and test designs under realistic scenarios avoiding heavy time penalty associated with hardware description language (HDL) simulators. The HIL technique facilitates significant speed-up in the required execution time when compared to its software-based counterpart model.

Levels of some molecular and biochemical tumor markers in Egyptian patients with different grades and stages of bladder cancer

International Nuclear Information System (INIS)

Abd-elgoad, E.I.; Elkashef, H.S.; Hanfy, A.; El-maghraby, T.

2003-01-01

This study enrolled 64 patients with bladder cancer disease, 54 of them treated by surgery and 10 by radiotherapy. The patients were classified according to their clinical data that include infection with bilharziasis, grade, stage and type of tumor. The present study included determination of telomerase activity in tissue and urine using molecular methods and the levels of nuclear matrix protein 22 (NMP22) and fibronectin in urine. The applied tumor markers showed significant differences in malignant patients compared to control. The same picture was noticed in case of patients received radiotherapy but less pronounced. The results revealed that there is significant correlation between the three tumor markers and the grade of tumor, while NMP22 and fibronectin correlated with stage. Moreover, fibronectin only have significant correlation with the infection with the bilharziasis. The results indicated that determination of telomerase, fibronectin and NMP22 can give clear idea about the development of malignancy and may help in the prediction of cancer recurrence

48 CFR 1812.7000 - Prohibition on guaranteed customer bases for new commercial space hardware or services.

Science.gov (United States)

2010-10-01

... customer bases for new commercial space hardware or services. 1812.7000 Section 1812.7000 Federal... PLANNING ACQUISITION OF COMMERCIAL ITEMS Commercial Space Hardware or Services 1812.7000 Prohibition on guaranteed customer bases for new commercial space hardware or services. Public Law 102-139, title III...

Robustness of spiking Deep Belief Networks to noise and reduced bit precision of neuro-inspired hardware platforms

Directory of Open Access Journals (Sweden)

Evangelos eStromatias

2015-07-01

Full Text Available Increasingly large deep learning architectures, such as Deep Belief Networks (DBNs are the focus of current machine learning research and achieve state-of-the-art results in different domains. However, both training and execution of large-scale Deep Networks requires vast computing resources, leading to high power requirements and communication overheads. The on-going work on design and construction of spike-based hardware platforms offers an alternative for running deep neural networks with significantly lower power consumption, but has to overcome hardware limitations in terms of noise and limited weight precision, as well as noise inherent in the sensor signal. This article investigates how such hardware constraints impact the performance of spiking neural network implementations of DBNs. In particular, the influence of limited bit precision during execution and training, and the impact of silicon mismatch in the synaptic weight parameters of custom hybrid VLSI implementations is studied. Furthermore, the network performance of spiking DBNs is characterized with regard to noise in the spiking input signal. Our results demonstrate that spiking DBNs can tolerate very low levels of hardware bit precision down to almost 2 bits, and shows that their performance can be improved by at least 30% through an adapted training mechanism that takes the bit precision of the target platform into account. Spiking DBNs thus present an important use-case for large-scale hybrid analog-digital or digital neuromorphic platforms such as SpiNNaker, which can execute large but precision-constrained deep networks in real time.

Growth in spaceflight hardware results in alterations to the transcriptome and proteome

Science.gov (United States)

Basu, Proma; Kruse, Colin P. S.; Luesse, Darron R.; Wyatt, Sarah E.

2017-11-01

The Biological Research in Canisters (BRIC) hardware has been used to house many biology experiments on both the Space Transport System (STS, commonly known as the space shuttle) and the International Space Station (ISS). However, microscopic examination of Arabidopsis seedlings by Johnson et al. (2015) indicated the hardware itself may affect cell morphology. The experiment herein was designed to assess the effects of the BRIC-Petri Dish Fixation Units (BRIC-PDFU) hardware on the transcriptome and proteome of Arabidopsis seedlings. To our knowledge, this is the first transcriptomic and proteomic comparison of Arabidopsis seedlings grown with and without hardware. Arabidopsis thaliana wild-type Columbia (Col-0) seeds were sterilized and bulk plated on forty-four 60 mm Petri plates, of which 22 were integrated into the BRIC-PDFU hardware and 22 were maintained in closed containers at Ohio University. Seedlings were grown for approximately 3 days, fixed with RNAlater® and stored at -80 °C prior to RNA and protein extraction, with proteins separated into membrane and soluble fractions prior to analysis. The RNAseq analysis identified 1651 differentially expressed genes; MS/MS analysis identified 598 soluble and 589 membrane proteins differentially abundant both at p < .05. Fold enrichment analysis of gene ontology terms related to differentially expressed transcripts and proteins highlighted a variety of stress responses. Some of these genes and proteins have been previously identified in spaceflight experiments, indicating that these genes and proteins may be perturbed by both conditions.

The effect of various grading scales on student grade point averages.

Science.gov (United States)

Barnes, Kelli D; Buring, Shauna M

2012-04-10

To investigate changes in and the impact of grading scales from 2005 to 2010 and explore pharmacy faculty and student perceptions of whole-letter and plus/minus grading scales on cumulative grade point averages (GPAs) in required courses. Grading scales used in 2010 at the University of Cincinnati College of Pharmacy were retrospectively identified and compared to those used in 2005. Mean GPA was calculated using a whole-letter grading scale and a plus/minus grading scale to determine the impact of scales on GPA. Faculty members and students were surveyed regarding their perceptions of plus/minus grading. Nine unique grading scales were used throughout the curriculum, including plus/minus (64%) and whole-letter (21%) grading scales. From 2005 to 2010 there was transition from use of predominantly whole-letter scales to plus/minus grading scales. The type of grading scale used did not affect the mean cumulative GPA. Students preferred use of a plus-only grading scale while faculty members preferred use of a plus/minus grading scale. The transition from whole-letter grading to plus/minus grading in courses from 2005 to 2010 reflects pharmacy faculty members' perception that plus/minus grading allows for better differentiation between students' performances.

MRI differentiation of low-grade from high-grade appendicular chondrosarcoma

International Nuclear Information System (INIS)

Douis, Hassan; Singh, Leanne; Saifuddin, Asif

2014-01-01

To identify magnetic resonance imaging (MRI) features which differentiate low-grade chondral lesions (atypical cartilaginous tumours/grade 1 chondrosarcoma) from high-grade chondrosarcomas (grade 2, grade 3 and dedifferentiated chondrosarcoma) of the major long bones. We identified all patients treated for central atypical cartilaginous tumours and central chondrosarcoma of major long bones (humerus, femur, tibia) over a 13-year period. The MRI studies were assessed for the following features: bone marrow oedema, soft tissue oedema, bone expansion, cortical thickening, cortical destruction, active periostitis, soft tissue mass and tumour length. The MRI-features were compared with the histopathological tumour grading using univariate, multivariate logistic regression and receiver operating characteristic curve (ROC) analyses. One hundred and seventy-nine tumours were included in this retrospective study. There were 28 atypical cartilaginous tumours, 79 grade 1 chondrosarcomas, 36 grade 2 chondrosarcomas, 13 grade 3 chondrosarcomas and 23 dedifferentiated chondrosarcomas. Multivariate analysis demonstrated that bone expansion (P = 0.001), active periostitis (P = 0.001), soft tissue mass (P < 0.001) and tumour length (P < 0.001) were statistically significant differentiating factors between low-grade and high-grade chondral lesions with an area under the ROC curve of 0.956. On MRI, bone expansion, active periostitis, soft tissue mass and tumour length can reliably differentiate high-grade chondrosarcomas from low-grade chondral lesions of the major long bones. (orig.)

MRI differentiation of low-grade from high-grade appendicular chondrosarcoma

Energy Technology Data Exchange (ETDEWEB)

Douis, Hassan; Singh, Leanne; Saifuddin, Asif [The Royal National Orthopaedic Hospital NHS Trust, Department of Radiology, Stanmore, Middlesex (United Kingdom)

2014-01-15

To identify magnetic resonance imaging (MRI) features which differentiate low-grade chondral lesions (atypical cartilaginous tumours/grade 1 chondrosarcoma) from high-grade chondrosarcomas (grade 2, grade 3 and dedifferentiated chondrosarcoma) of the major long bones. We identified all patients treated for central atypical cartilaginous tumours and central chondrosarcoma of major long bones (humerus, femur, tibia) over a 13-year period. The MRI studies were assessed for the following features: bone marrow oedema, soft tissue oedema, bone expansion, cortical thickening, cortical destruction, active periostitis, soft tissue mass and tumour length. The MRI-features were compared with the histopathological tumour grading using univariate, multivariate logistic regression and receiver operating characteristic curve (ROC) analyses. One hundred and seventy-nine tumours were included in this retrospective study. There were 28 atypical cartilaginous tumours, 79 grade 1 chondrosarcomas, 36 grade 2 chondrosarcomas, 13 grade 3 chondrosarcomas and 23 dedifferentiated chondrosarcomas. Multivariate analysis demonstrated that bone expansion (P = 0.001), active periostitis (P = 0.001), soft tissue mass (P < 0.001) and tumour length (P < 0.001) were statistically significant differentiating factors between low-grade and high-grade chondral lesions with an area under the ROC curve of 0.956. On MRI, bone expansion, active periostitis, soft tissue mass and tumour length can reliably differentiate high-grade chondrosarcomas from low-grade chondral lesions of the major long bones. (orig.)

Particle Transport Simulation on Heterogeneous Hardware

CERN Multimedia

CERN. Geneva

2014-01-01

CPUs and GPGPUs. About the speaker Vladimir Koylazov is CTO and founder of Chaos Software and one of the original developers of the V-Ray raytracing software. Passionate about 3D graphics and programming, Vlado is the driving force behind Chaos Group's software solutions. He participated in the implementation of algorithms for accurate light simulations and support for different hardware platforms, including CPU and GPGPU, as well as distributed calculat...

Hardware-in-the-Loop Simulation for the Automatic Power Control System of Research Reactors

International Nuclear Information System (INIS)

Fikry, R.M.; Shehata, S.A.; Elaraby, S.M.; Mahmoud, M.I.; Elbardini, M.M.

2009-01-01

Designing and testing digital control system for any nuclear research reactor can be costly and time consuming. In this paper, a rapid, low-cost proto typing and testing procedure for digital controller design is proposed using the concept of Hardware-In- The-Loop (HIL). Some of the control loop components are real hardware components and thc others are simulated. First, the whole system is modeled and tested by Real- Time Simulation (RTS) using conventional simulation techniques such as MATLAB / SIMULINK. Second the Hardware-in-the-Ioop simulation is tested using Real-Time Windows Target in MATLAB and Visual C++. The control parts are included as hardware components which are the reactor control rod and its drivers. Two kinds of controllers are studied, Proportional derivative (PD) and Fuzzy controller, An experimental setup for the hardware used in HIL concept for the control of the nuclear research reactor has been realized. Experimental results are obtained and compared with the simulation results. The experimental results indicate the validation of HIL method in this domain

7 CFR 810.404 - Grades and grade requirements for corn.

Science.gov (United States)

2010-01-01

... 7 Agriculture 7 2010-01-01 2010-01-01 false Grades and grade requirements for corn. 810.404... OFFICIAL UNITED STATES STANDARDS FOR GRAIN United States Standards for Corn Principles Governing the Application of Standards § 810.404 Grades and grade requirements for corn. Grade Minimum test weight per...

Hardware accuracy counters for application precision and quality feedback

Science.gov (United States)

de Paula Rosa Piga, Leonardo; Majumdar, Abhinandan; Paul, Indrani; Huang, Wei; Arora, Manish; Greathouse, Joseph L.

2018-06-05

Methods, devices, and systems for capturing an accuracy of an instruction executing on a processor. An instruction may be executed on the processor, and the accuracy of the instruction may be captured using a hardware counter circuit. The accuracy of the instruction may be captured by analyzing bits of at least one value of the instruction to determine a minimum or maximum precision datatype for representing the field, and determining whether to adjust a value of the hardware counter circuit accordingly. The representation may be output to a debugger or logfile for use by a developer, or may be output to a runtime or virtual machine to automatically adjust instruction precision or gating of portions of the processor datapath.

Fast and Reliable Mouse Picking Using Graphics Hardware

Directory of Open Access Journals (Sweden)

Hanli Zhao

2009-01-01

Full Text Available Mouse picking is the most commonly used intuitive operation to interact with 3D scenes in a variety of 3D graphics applications. High performance for such operation is necessary in order to provide users with fast responses. This paper proposes a fast and reliable mouse picking algorithm using graphics hardware for 3D triangular scenes. Our approach uses a multi-layer rendering algorithm to perform the picking operation in linear time complexity. The objectspace based ray-triangle intersection test is implemented in a highly parallelized geometry shader. After applying the hardware-supported occlusion queries, only a small number of objects (or sub-objects are rendered in subsequent layers, which accelerates the picking efficiency. Experimental results demonstrate the high performance of our novel approach. Due to its simplicity, our algorithm can be easily integrated into existing real-time rendering systems.

Web tools to monitor and debug DAQ hardware

International Nuclear Information System (INIS)

Desavouret, Eugene; Nogiec, Jerzy M.

2003-01-01

A web-based toolkit to monitor and diagnose data acquisition hardware has been developed. It allows for remote testing, monitoring, and control of VxWorks data acquisition computers and associated instrumentation using the HTTP protocol and a web browser. This solution provides concurrent and platform independent access, supplementary to the standard single-user rlogin mechanism. The toolkit is based on a specialized web server, and allows remote access and execution of select system commands and tasks, execution of test procedures, and provides remote monitoring of computer system resources and connected hardware. Various DAQ components such as multiplexers, digital I/O boards, analog to digital converters, or current sources can be accessed and diagnosed remotely in a uniform and well-organized manner. Additionally, the toolkit application supports user authentication and is able to enforce specified access restrictions

A Hardware Framework for on-Chip FPGA Acceleration

DEFF Research Database (Denmark)

Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

2016-01-01

In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accele......In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA......-based accelerator. Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism....

Dynamic modelling and hardware-in-the-loop testing of PEMFC

Energy Technology Data Exchange (ETDEWEB)

Vath, Andreas; Soehn, Matthias; Nicoloso, Norbert; Hartkopf, Thomas [Technische Universitaet Darmstadt/Institut fuer Elektrische Energie wand lung, Landgraf-Georg-Str. 4, D-64283 Darmstadt (Germany); Lemes, Zijad; Maencher, Hubert [MAGNUM Automatisierungstechnik GmbH, Bunsenstr. 22, D-64293 Darmstadt (Germany)

2006-07-03

Modelling and hardware-in-the-loop (HIL) testing of fuel cell components and entire systems open new ways for the design and advance development of FCs. In this work proton exchange membrane fuel cells (PEMFC) are dynamically modelled within MATLAB-Simulink at various operation conditions in order to establish a comprehensive description of their dynamic behaviour as well as to explore the modelling facility as a diagnostic tool. Set-up of a hardware-in-the-loop (HIL) system enables real time interaction between the selected hardware and the model. The transport of hydrogen, nitrogen, oxygen, water vapour and liquid water in the gas diffusion and catalyst layers of the stack are incorporated into the model according to their physical and electrochemical characteristics. Other processes investigated include, e.g., the membrane resistance as a function of the water content during fast load changes. Cells are modelled three-dimensionally and dynamically. In case of system simulations a one-dimensional model is preferred to reduce computation time. The model has been verified by experiments with a water-cooled stack. (author)

Wireless Energy Harvesting Two-Way Relay Networks with Hardware Impairments.

Science.gov (United States)

Peng, Chunling; Li, Fangwei; Liu, Huaping

2017-11-13

This paper considers a wireless energy harvesting two-way relay (TWR) network where the relay has energy-harvesting abilities and the effects of practical hardware impairments are taken into consideration. In particular, power splitting (PS) receiver is adopted at relay to harvests the power it needs for relaying the information between the source nodes from the signals transmitted by the source nodes, and hardware impairments is assumed suffered by each node. We analyze the effect of hardware impairments [-20]on both decode-and-forward (DF) relaying and amplify-and-forward (AF) relaying networks. By utilizing the obtained new expressions of signal-to-noise-plus-distortion ratios, the exact analytical expressions of the achievable sum rate and ergodic capacities for both DF and AF relaying protocols are derived. Additionally, the optimal power splitting (OPS) ratio that maximizes the instantaneous achievable sum rate is formulated and solved for both protocols. The performances of DF and AF protocols are evaluated via numerical results, which also show the effects of various network parameters on the system performance and on the OPS ratio design.

Hardware implementation of on -chip learning using re configurable FPGAS

International Nuclear Information System (INIS)

Kelash, H.M.; Sorour, H.S; Mahmoud, I.I.; Zaki, M; Haggag, S.S.

2009-01-01

The multilayer perceptron (MLP) is a neural network model that is being widely applied in the solving of diverse problems. A supervised training is necessary before the use of the neural network.A highly popular learning algorithm called back-propagation is used to train this neural network model. Once trained, the MLP can be used to solve classification problems. An interesting method to increase the performance of the model is by using hardware implementations. The hardware can do the arithmetical operations much faster than software. In this paper, a design and implementation of the sequential mode (stochastic mode) of backpropagation algorithm with on-chip learning using field programmable gate arrays (FPGA) is presented, a pipelined adaptation of the on-line back propagation algorithm (BP) is shown.The hardware implementation of forward stage, backward stage and update weight of backpropagation algorithm is also presented. This implementation is based on a SIMD parallel architecture of the forward propagation the diagnosis of the multi-purpose research reactor of Egypt accidents is used to test the proposed system

Evaluation of accelerated iterative x-ray CT image reconstruction using floating point graphics hardware

International Nuclear Information System (INIS)

Kole, J S; Beekman, F J

2006-01-01

Statistical reconstruction methods offer possibilities to improve image quality as compared with analytical methods, but current reconstruction times prohibit routine application in clinical and micro-CT. In particular, for cone-beam x-ray CT, the use of graphics hardware has been proposed to accelerate the forward and back-projection operations, in order to reduce reconstruction times. In the past, wide application of this texture hardware mapping approach was hampered owing to limited intrinsic accuracy. Recently, however, floating point precision has become available in the latest generation commodity graphics cards. In this paper, we utilize this feature to construct a graphics hardware accelerated version of the ordered subset convex reconstruction algorithm. The aims of this paper are (i) to study the impact of using graphics hardware acceleration for statistical reconstruction on the reconstructed image accuracy and (ii) to measure the speed increase one can obtain by using graphics hardware acceleration. We compare the unaccelerated algorithm with the graphics hardware accelerated version, and for the latter we consider two different interpolation techniques. A simulation study of a micro-CT scanner with a mathematical phantom shows that at almost preserved reconstructed image accuracy, speed-ups of a factor 40 to 222 can be achieved, compared with the unaccelerated algorithm, and depending on the phantom and detector sizes. Reconstruction from physical phantom data reconfirms the usability of the accelerated algorithm for practical cases

A CU-Level Rate and Distortion Estimation Scheme for RDO of Hardware-Friendly HEVC Encoders Using Low-Complexity Integer DCTs.

Science.gov (United States)

Lee, Bumshik; Kim, Munchurl

2016-08-01

In this paper, a low complexity coding unit (CU)-level rate and distortion estimation scheme is proposed for High Efficiency Video Coding (HEVC) hardware-friendly implementation where a Walsh-Hadamard transform (WHT)-based low-complexity integer discrete cosine transform (DCT) is employed for distortion estimation. Since HEVC adopts quadtree structures of coding blocks with hierarchical coding depths, it becomes more difficult to estimate accurate rate and distortion values without actually performing transform, quantization, inverse transform, de-quantization, and entropy coding. Furthermore, DCT for rate-distortion optimization (RDO) is computationally high, because it requires a number of multiplication and addition operations for various transform block sizes of 4-, 8-, 16-, and 32-orders and requires recursive computations to decide the optimal depths of CU or transform unit. Therefore, full RDO-based encoding is highly complex, especially for low-power implementation of HEVC encoders. In this paper, a rate and distortion estimation scheme is proposed in CU levels based on a low-complexity integer DCT that can be computed in terms of WHT whose coefficients are produced in prediction stages. For rate and distortion estimation in CU levels, two orthogonal matrices of 4×4 and 8×8 , which are applied to WHT that are newly designed in a butterfly structure only with addition and shift operations. By applying the integer DCT based on the WHT and newly designed transforms in each CU block, the texture rate can precisely be estimated after quantization using the number of non-zero quantized coefficients and the distortion can also be precisely estimated in transform domain without de-quantization and inverse transform required. In addition, a non-texture rate estimation is proposed by using a pseudoentropy code to obtain accurate total rate estimates. The proposed rate and the distortion estimation scheme can effectively be used for HW-friendly implementation of

Hardware-in-the-loop (HIL) nuclear power plant training simulation platform design and validation

Energy Technology Data Exchange (ETDEWEB)

Rankin, D.J. [Univ. of Western Ontario, Control and Instrumentation (CIES) Research Group, Dept. of Electrical and Computer Engineering, London, Ontario (Canada)

2008-07-01

The design, development and validation of a hardware-in- the-loop (HIL) simulation platform are presented. An Invensys Triconex Tricon v9 safety PLC is interfaced to a nuclear power plant (NPP) simulation suite, replicating the operation of Darlington NPP. Communication between the simulator and external hardware is supported by a National Instruments (NI) data acquisition system (DAQ) and a customized virtual instrument (VI). Event timings within the control loop are thoroughly investigated and an acceptable method for HIL platform communication is developed. A sample application (primary shutdown system (SDS1)) is implemented and evaluated. SDS1 evaluation is performed with focus on steam generator (SG) level low trip scenarios. For this purpose, a design basis accident (DBA) associated with SDS1 regulatory standards is applied to the HIL simulation environment and compared with simulated expected plant operation. Further, the role of the Tricon v9 system within the HIL loop is investigated to establish a basis for the future integration of the entire SDS1 control logic. (author)

A preferential design approach for energy-efficient and robust implantable neural signal processing hardware.

Science.gov (United States)

Narasimhan, Seetharam; Chiel, Hillel J; Bhunia, Swarup

2009-01-01

For implantable neural interface applications, it is important to compress data and analyze spike patterns across multiple channels in real time. Such a computational task for online neural data processing requires an innovative circuit-architecture level design approach for low-power, robust and area-efficient hardware implementation. Conventional microprocessor or Digital Signal Processing (DSP) chips would dissipate too much power and are too large in size for an implantable system. In this paper, we propose a novel hardware design approach, referred to as "Preferential Design" that exploits the nature of the neural signal processing algorithm to achieve a low-voltage, robust and area-efficient implementation using nanoscale process technology. The basic idea is to isolate the critical components with respect to system performance and design them more conservatively compared to the noncritical ones. This allows aggressive voltage scaling for low power operation while ensuring robustness and area efficiency. We have applied the proposed approach to a neural signal processing algorithm using the Discrete Wavelet Transform (DWT) and observed significant improvement in power and robustness over conventional design.

High-level synthesis for reduction of WCET in real-time systems

DEFF Research Database (Denmark)

Kristensen, Andreas Toftegaard; Pezzarossa, Luca; Sparsø, Jens

2017-01-01

. Compared to executing the high-level language code on a processor, HLS can be used to create hardware that accelerates critical parts of the code. When discussing performance in the context or real-time systems, it is the worst-case execution time (WCET) of a task that matters. WCET obviously benefits from...... hardware acceleration, but it may also benefit from a tighter bound on the WCET. This paper explores the use of and integration of accelerators generated using HLS into a time-predictable processor intended for real-time systems. The high-level design tool, Vivado HLS, is used to generate hardware...

Foraminal syringomyelia: suggestion for a grading system.

Science.gov (United States)

Versari, P P; D'Aliberti, G; Talamonti, G; Collice, M

1993-01-01

The standard treatment of foraminal syringomyelia includes foramen magnum decompression and duraplasty. Improvement or stabilization of the disease are achieved in most of cases. However, at least one third of patients are reported to receive little or no benefit. In this paper we retrospectively reviewed a series of 40 consecutive foramen magnum decompressions in order to identify the possible pre-operative outcome predictors. Based on clinical evolution, neurological impairment and radiological features, a scale of severity was fixed and retrospectively tested. A pre-operative score was obtained for each patient and was correlated with the surgical results. Then a four level grading system was derived. All grade I and grade II patients achieved good results (improvement or stabilization), whereas grade III patients showed intermediate behaviour and grade IV invariably worsened. On this basis, surgical results of foramen magnum decompression might be further improved provided that a careful pre-operative selection is made.

High-performance reconfigurable hardware architecture for restricted Boltzmann machines.

Science.gov (United States)

Ly, Daniel Le; Chow, Paul

2010-11-01

Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications has been limited. A primary cause for this lack of adoption is that neural networks are usually implemented as software running on general-purpose processors. Hence, a hardware implementation that can exploit the inherent parallelism in neural networks is desired. This paper investigates how the restricted Boltzmann machine (RBM), which is a popular type of neural network, can be mapped to a high-performance hardware architecture on field-programmable gate array (FPGA) platforms. The proposed modular framework is designed to reduce the time complexity of the computations through heavily customized hardware engines. A method to partition large RBMs into smaller congruent components is also presented, allowing the distribution of one RBM across multiple FPGA resources. The framework is tested on a platform of four Xilinx Virtex II-Pro XC2VP70 FPGAs running at 100 MHz through a variety of different configurations. The maximum performance was obtained by instantiating an RBM of 256 × 256 nodes distributed across four FPGAs, which resulted in a computational speed of 3.13 billion connection-updates-per-second and a speedup of 145-fold over an optimized C program running on a 2.8-GHz Intel processor.

Hardware demonstration of high-speed networks for satellite applications.

Energy Technology Data Exchange (ETDEWEB)

Donaldson, Jonathon W.; Lee, David S.

2008-09-01

This report documents the implementation results of a hardware demonstration utilizing the Serial RapidIO{trademark} and SpaceWire protocols that was funded by Sandia National Laboratories (SNL's) Laboratory Directed Research and Development (LDRD) office. This demonstration was one of the activities in the Modeling and Design of High-Speed Networks for Satellite Applications LDRD. This effort has demonstrated the transport of application layer packets across both RapidIO and SpaceWire networks to a common downlink destination using small topologies comprised of commercial-off-the-shelf and custom devices. The RapidFET and NEX-SRIO debug and verification tools were instrumental in the successful implementation of the RapidIO hardware demonstration. The SpaceWire hardware demonstration successfully demonstrated the transfer and routing of application data packets between multiple nodes and also was able reprogram remote nodes using configuration bitfiles transmitted over the network, a key feature proposed in node-based architectures (NBAs). Although a much larger network (at least 18 to 27 nodes) would be required to fully verify the design for use in a real-world application, this demonstration has shown that both RapidIO and SpaceWire are capable of routing application packets across a network to a common downlink node, illustrating their potential use in real-world NBAs.

Autonomous target tracking of UAVs based on low-power neural network hardware

Science.gov (United States)

Yang, Wei; Jin, Zhanpeng; Thiem, Clare; Wysocki, Bryant; Shen, Dan; Chen, Genshe

2014-05-01

Detecting and identifying targets in unmanned aerial vehicle (UAV) images and videos have been challenging problems due to various types of image distortion. Moreover, the significantly high processing overhead of existing image/video processing techniques and the limited computing resources available on UAVs force most of the processing tasks to be performed by the ground control station (GCS) in an off-line manner. In order to achieve fast and autonomous target identification on UAVs, it is thus imperative to investigate novel processing paradigms that can fulfill the real-time processing requirements, while fitting the size, weight, and power (SWaP) constrained environment. In this paper, we present a new autonomous target identification approach on UAVs, leveraging the emerging neuromorphic hardware which is capable of massively parallel pattern recognition processing and demands only a limited level of power consumption. A proof-of-concept prototype was developed based on a micro-UAV platform (Parrot AR Drone) and the CogniMemTMneural network chip, for processing the video data acquired from a UAV camera on the y. The aim of this study was to demonstrate the feasibility and potential of incorporating emerging neuromorphic hardware into next-generation UAVs and their superior performance and power advantages towards the real-time, autonomous target tracking.

[Reproducibility of Fuhrman nuclear grade: advantages of a two-grade system].

Science.gov (United States)

Letourneux, Hervé; Lindner, Véronique; Lang, Hervé; Massfelder, Thierry; Meyer, Nicolas; Saussine, Christian; Jacqmin, Didier

2006-06-01

The Fuhrman nuclear grade is the reference histoprognostic grading system routinely used all over the world for renal cell carcinoma. Studies measuring the inter-observer and intra-observer concordance of Fuhrman grade show poor results in terms of reproducibility and repeatability. These variations are due to a certain degree of subjectivity of the pathologist in application of the definition of tumour grade, particularly nuclear grade. Elements able to account for this subjectivity in renal cell carcinoma are identified from a review of the literature. To improve the reliability of nuclear grade, the territory occupied by the highest grade must be specified and the grades should probably be combined. At the present time, regrouping of grade 1 and 2 tumours as low grade and grade 3 and 4 tumours as high grade would achieve better reproducibility, while preserving the prognostic: value for overall survival. The development of new treatment modalities and their use in adjuvant situations will imply the use of reliable histoprognostic factors to specify, indications.

A Framework for Dynamically-Loaded Hardware Library (HLL) in FPGA Acceleration

DEFF Research Database (Denmark)

Cardarilli, Gian Carlo; Di Carlo, Leonardo; Nannarelli, Alberto

2016-01-01

Hardware acceleration is often used to address the need for speed and computing power in embedded systems. FPGAs always represented a good solution for HW acceleration and, recently, new SoC platforms extended the flexibility of the FPGAs by combining on a single chip both high-performance CPUs...... and FPGA fabric. The aim of this work is the implementation of hardware accelerators for these new SoCs. The innovative feature of these accelerators is the on-the-fly reconfiguration of the hardware to dynamically adapt the accelerator’s functionalities to the current CPU workload. The realization...... of the accelerators preliminarily requires also the profiling of both the SW (ARM CPU + NEON Units) and HW (FPGA) performance, an evaluation of the partial reconfiguration times and the development of an applicationspecific IP-cores library. This paper focuses on the profiling aspect of both the SW and HW...

Efficient Hardware Implementation For Fingerprint Image Enhancement Using Anisotropic Gaussian Filter.

Science.gov (United States)

Khan, Tariq Mahmood; Bailey, Donald G; Khan, Mohammad A U; Kong, Yinan

2017-05-01

A real-time image filtering technique is proposed which could result in faster implementation for fingerprint image enhancement. One major hurdle associated with fingerprint filtering techniques is the expensive nature of their hardware implementations. To circumvent this, a modified anisotropic Gaussian filter is efficiently adopted in hardware by decomposing the filter into two orthogonal Gaussians and an oriented line Gaussian. An architecture is developed for dynamically controlling the orientation of the line Gaussian filter. To further improve the performance of the filter, the input image is homogenized by a local image normalization. In the proposed structure, for a middle-range reconfigurable FPGA, both parallel compute-intensive and real-time demands were achieved. We manage to efficiently speed up the image-processing time and improve the resource utilization of the FPGA. Test results show an improved speed for its hardware architecture while maintaining reasonable enhancement benchmarks.

IDEAS and App Development Internship in Hardware and Software Design

Science.gov (United States)

Alrayes, Rabab D.

2016-01-01

In this report, I will discuss the tasks and projects I have completed while working as an electrical engineering intern during the spring semester of 2016 at NASA Kennedy Space Center. In the field of software development, I completed tasks for the G-O Caching Mobile App and the Asbestos Management Information System (AMIS) Web App. The G-O Caching Mobile App was written in HTML, CSS, and JavaScript on the Cordova framework, while the AMIS Web App is written in HTML, CSS, JavaScript, and C# on the AngularJS framework. My goals and objectives on these two projects were to produce an app with an eye-catching and intuitive User Interface (UI), which will attract more employees to participate; to produce a fully-tested, fully functional app which supports workforce engagement and exploration; to produce a fully-tested, fully functional web app that assists technicians working in asbestos management. I also worked in hardware development on the Integrated Display and Environmental Awareness System (IDEAS) wearable technology project. My tasks on this project were focused in PCB design and camera integration. My goals and objectives for this project were to successfully integrate fully functioning custom hardware extenders on the wearable technology headset to minimize the size of hardware on the smart glasses headset for maximum user comfort; to successfully integrate fully functioning camera onto the headset. By the end of this semester, I was able to successfully develop four extender boards to minimize hardware on the headset, and assisted in integrating a fully-functioning camera into the system.

Ammonia levels and the severity of hepatic encephalopathy

International Nuclear Information System (INIS)

Qureshi, M.O.; Khokhar, N.; Shafqat, F.

2014-01-01

Objective: To evaluate the correlation between ammonia levels with the severity of HE in patients coming to the tertiary care hospital with liver cirrhosis and hepatic encephalopathy (HE). Study Design: Descriptive, analytical study. Place and Duration of Study: Shifa International Hospital, Islamabad, from January 2011 to February 2012. Methodology: A total of 135 patients with liver cirrhosis and HE had serum ammonia levels measured on admission. The diagnosis of HE was based on clinical criteria, and its severity was graded according to the West Haven Criteria for grading of mental status. Ammonia levels were correlated with the severity of HE using Spearman rank correlation. Results: Out of 20 patients with normal ammonia levels, 13 (65%) were in HE I-II, 6 (30%) were in grade-III, while 1 (5%) patient was in grade-IV HE. Out of 45 patients with mild hyperammonemia, 27 (60%) were in grade I-II, 12 (26%) were in grade-III and 6 (13%) were in grade-IV HE. Out of 34 patients with moderate hyperammonemia, 9 (26%) were in grade I-II, 18 (53%) were in grade-III, and 7 (20%) were in grade-IV HE. Out of 36 patients with severe hyperammonemia, 31 (86%) patients were in grade-IV HE (p < 0.001). Conclusion: Ammonia levels correlated with the severity of hepatic encephalopathy. Greater the ammonia level, severe is the grade of hepatic encephalopathy. (author)

Upper Elementary Grades Bear the Brunt of Accountability

Science.gov (United States)

Anderson, Lorin W.

2009-01-01

Upper elementary teachers won't be surprised to learn that in every state, students enrolled in grades 3 through 8 bear the brunt of educational accountability. All states test all students at these grade levels in English/language arts and mathematics. Furthermore, an increasing number of states are testing students at selected elementary and…

Using MaxCompiler for High Level Synthesis of Trigger Algorithms

CERN Document Server

Summers, Sioni Paris; Sanders, P.

2017-01-01

Firmware for FPGA trigger applications at the CMS experiment is conventionally written using hardware description languages such as Verilog and VHDL. MaxCompiler is an alternative, Java based, tool for developing FPGA applications which uses a higher level of abstraction from the hardware than a hardware description language. An implementation of the jet and energy sum algorithms for the CMS Level-1 calorimeter trigger has been written using MaxCompiler to benchmark against the VHDL implementation in terms of accuracy, latency, resource usage, and code size. A Kalman Filter track fitting algorithm has been developed using MaxCompiler for a proposed CMS Level-1 track trigger for the High-Luminosity LHC upgrade. The design achieves a low resource usage, and has a latency of 187.5 ns per iteration.

Round Girls in Square Computers: Feminist Perspectives on the Aesthetics of Computer Hardware.

Science.gov (United States)

Carr-Chellman, Alison A.; Marra, Rose M.; Roberts, Shari L.

2002-01-01

Considers issues related to computer hardware, aesthetics, and gender. Explores how gender has influenced the design of computer hardware and how these gender-driven aesthetics may have worked to maintain, extend, or alter gender distinctions, roles, and stereotypes; discusses masculine media representations; and presents an alternative model.…

Contamination Examples and Lessons from Low Earth Orbit Experiments and Operational Hardware

Science.gov (United States)

Pippin, Gary; Finckenor, Miria M.

2009-01-01

Flight experiments flown on the Space Shuttle, the International Space Station, Mir, Skylab, and free flyers such as the Long Duration Exposure Facility, the European Retrievable Carrier, and the EFFU, provide multiple opportunities for the investigation of molecular contamination effects. Retrieved hardware from the Solar Maximum Mission satellite, Mir, and the Hubble Space Telescope has also provided the means gaining insight into contamination processes. Images from the above mentioned hardware show contamination effects due to materials processing, hardware storage, pre-flight cleaning, as well as on-orbit events such as outgassing, mechanical failure of hardware in close proximity, impacts from man-made debris, and changes due to natural environment factors.. Contamination effects include significant changes to thermal and electrical properties of thermal control surfaces, optics, and power systems. Data from several flights has been used to develop a rudimentary estimate of asymptotic values for absorptance changes due to long-term solar exposure (4000-6000 Equivalent Sun Hours) of silicone-based molecular contamination deposits of varying thickness. Recommendations and suggestions for processing changes and constraints based on the on-orbit observed results will be presented.

SEnviro: A Sensorized Platform Proposal Using Open Hardware and Open Standards

Directory of Open Access Journals (Sweden)

Sergio Trilles

2015-03-01

Full Text Available The need for constant monitoring of environmental conditions has produced an increase in the development of wireless sensor networks (WSN. The drive towards smart cities has produced the need for smart sensors to be able to monitor what is happening in our cities. This, combined with the decrease in hardware component prices and the increase in the popularity of open hardware, has favored the deployment of sensor networks based on open hardware. The new trends in Internet Protocol (IP communication between sensor nodes allow sensor access via the Internet, turning them into smart objects (Internet of Things and Web of Things. Currently, WSNs provide data in different formats. There is a lack of communication protocol standardization, which turns into interoperability issues when connecting different sensor networks or even when connecting different sensor nodes within the same network. This work presents a sensorized platform proposal that adheres to the principles of the Internet of Things and theWeb of Things. Wireless sensor nodes were built using open hardware solutions, and communications rely on the HTTP/IP Internet protocols. The Open Geospatial Consortium (OGC SensorThings API candidate standard was used as a neutral format to avoid interoperability issues. An environmental WSN developed following the proposed architecture was built as a proof of concept. Details on how to build each node and a study regarding energy concerns are presented.

SEnviro: a sensorized platform proposal using open hardware and open standards.

Science.gov (United States)

Trilles, Sergio; Luján, Alejandro; Belmonte, Óscar; Montoliu, Raúl; Torres-Sospedra, Joaquín; Huerta, Joaquín

2015-03-06

The need for constant monitoring of environmental conditions has produced an increase in the development of wireless sensor networks (WSN). The drive towards smart cities has produced the need for smart sensors to be able to monitor what is happening in our cities. This, combined with the decrease in hardware component prices and the increase in the popularity of open hardware, has favored the deployment of sensor networks based on open hardware. The new trends in Internet Protocol (IP) communication between sensor nodes allow sensor access via the Internet, turning them into smart objects (Internet of Things and Web of Things). Currently, WSNs provide data in different formats. There is a lack of communication protocol standardization, which turns into interoperability issues when connecting different sensor networks or even when connecting different sensor nodes within the same network. This work presents a sensorized platform proposal that adheres to the principles of the Internet of Things and theWeb of Things. Wireless sensor nodes were built using open hardware solutions, and communications rely on the HTTP/IP Internet protocols. The Open Geospatial Consortium (OGC) SensorThings API candidate standard was used as a neutral format to avoid interoperability issues. An environmental WSN developed following the proposed architecture was built as a proof of concept. Details on how to build each node and a study regarding energy concerns are presented.

Exploring How Second Grade Elementary Teachers Translate Their Nature of Science Views into Classroom Practice After a Graduate Level Nature of Science Course

Science.gov (United States)

Deniz, Hasan; Adibelli, Elif

2015-12-01

The main purpose of this study was to explore the factors mediating the translation of second grade teachers' nature of science (NOS) views into classroom practice after completing a graduate level NOS course. Four second grade in-service elementary teachers comprised the sample of this study. Data were collected from several sources during the course of this study. The primary data sources were (a) assessment of the elementary teachers' NOS views before and after the graduate level NOS course using the Views of Nature of Science Questionnaire Version B (VNOS-B) (Lederman et al., 2002) coupled with interviews, and (b) a classroom observation and videotaped recording of the elementary teachers' best NOS lessons coupled with interview. We identified three distinct but related factors that mediated the translation of NOS views into classroom practice: the teachers' perspectives about the developmental appropriateness of the NOS aspect, the teachers' selection of target NOS aspects, and the relative importance placed by teachers on each NOS aspect.

Optimization Strategies for Hardware-Based Cofactorization

Science.gov (United States)

Loebenberger, Daniel; Putzka, Jens

We use the specific structure of the inputs to the cofactorization step in the general number field sieve (GNFS) in order to optimize the runtime for the cofactorization step on a hardware cluster. An optimal distribution of bitlength-specific ECM modules is proposed and compared to existing ones. With our optimizations we obtain a speedup between 17% and 33% of the cofactorization step of the GNFS when compared to the runtime of an unoptimized cluster.

Hardware Design of a Smart Meter

OpenAIRE

Ganiyu A. Ajenikoko; Anthony A. Olaomi

2014-01-01

Smart meters are electronic measurement devices used by utilities to communicate information for billing customers and operating their electric systems. This paper presents the hardware design of a smart meter. Sensing and circuit protection circuits are included in the design of the smart meter in which resistors are naturally a fundamental part of the electronic design. Smart meters provides a route for energy savings, real-time pricing, automated data collection and elimina...

Communication and synchronization aspects of a mixed hardware control and data acquisition system

International Nuclear Information System (INIS)

Schmidt, V.; Flor, G.; Luchetta, A.; Manduchi, G.; Piacentini, I.E.; Vitturi, S.; Hemming, O.N.

1989-01-01

The paper deals with some specific aspects of the control and data acquisition system of the RFX nuclear fusion experiment, at present under construction in Padova, Italy. This system is built around a local area network which connects programmable controllers, minicomputers with CAMAC front-end, and personal computers as operator consoles. These three types of nodes use compatible software which contain a set of low level routines according to levels one to four of the ISO OSI recommendations. The paper describes in detail how the overall system synchronization is achieved. Another aspect described in the paper is the proposed solution for the precision timing and waveform generation (which uses commercial CAMAC hardware) and its integration with the overall system synchronization

The relation of serum PSA and Gleason's grade in patients with prostacic carcinoma

Directory of Open Access Journals (Sweden)

Živković Slađana

2003-01-01

Full Text Available The prostatic adenocarcinoma is one of the most frequent malignant tumors of men over 50 years of age. It is distinguished by agressive clinical course and heterogeneous multifocal hystomorphologic changes. PSA is the most reliable serum marker in diagnostics and observation of prostatic carcinoma and gleason's system of tumor-diferentiation grading is generally accepted way of determining the hystologic grade. Gleason's system is correlated with serum levels of PSA and with biological behaviour of the tumor. We presented 40 patients with verified ACP in whom the level of serum PSA, gleason's grade and score were compared. Highly significant correlation was found between serum level of PSA and the differentation grade of the tumor - Gleason's grade and score. Combination of PSA parameters and Gleason's score enables correct estimation of tumor's behaviour and correct therapeutic protocole.

The Texas Solution to the Nation's Disposal Needs for Irradiated Hardware - 13337

International Nuclear Information System (INIS)

Britten, Jay M.

2013-01-01

The closure of the disposal facility in Barnwell, South Carolina, to out-of-compact states in 2008 left commercial nuclear power plants without a disposal option for Class B and C irradiated hardware. In 2012, Waste Control Specialists LLC (WCS) opened a highly engineered facility specifically designed and built for the disposal of Class B and C waste. The WCS facility is the first Interstate Compact low-level radioactive waste disposal facility to be licensed and operated under the Low-level Waste Policy Act of 1980, as amended in 1985. Due to design requirements of a modern Low Level Radioactive Waste (LLRW) facility, traditional methods for disposal were not achievable at the WCS site. Earlier methods primarily utilized the As Low as Reasonably Achievable (ALARA) concept of distance to accomplish worker safety. The WCS method required the use of all three ALARA concepts of time, distance, and shielding to ensure the safe disposal of this highly hazardous waste stream. (authors)

Suggested Curriculum Guidelines for an Effective Bilingual Program. 1972-1973. Destrezas Comunicativas del Idioma Espanol. Spanish Language Skills. Second Grade, Level 2.

Science.gov (United States)

Artesia Public Schools, NM.

This volume contains suggested curriculum guidelines for an effective bilingual program, with specific focus on Spanish language skills for the second grade level. The philosophy of the program views bilingual education as a vehicle and pedagogical tool to be used to better prepare all children to function in society. The point of departure for…

Suggested Curriculum Guidelines for an Effective Bilingual Program, 1972-1973. Destrezas Comunicativas del Idioma Espanol. Spanish Language Skills. Third Grade, Level 3.

Science.gov (United States)

Artesia Public Schools, NM.

This volume contains suggested curriculum guidelines for an effective bilingual program, with specific focus on Spanish language skills for the third grade level. The philosophy of the program views bilingual education as a vehicle and pedagogical tool to be used to better prepare all children to function in society. The point of departure for…

An interactive audio-visual installation using ubiquitous hardware and web-based software deployment

Directory of Open Access Journals (Sweden)

Tiago Fernandes Tavares

2015-05-01

Full Text Available This paper describes an interactive audio-visual musical installation, namely MOTUS, that aims at being deployed using low-cost hardware and software. This was achieved by writing the software as a web application and using only hardware pieces that are built-in most modern personal computers. This scenario implies in specific technical restrictions, which leads to solutions combining both technical and artistic aspects of the installation. The resulting system is versatile and can be freely used from any computer with Internet access. Spontaneous feedback from the audience has shown that the provided experience is interesting and engaging, regardless of the use of minimal hardware.

Ultrasound gel minimizes third body debris with partial hardware removal in joint arthroplasty

Directory of Open Access Journals (Sweden)

Aidan C. McGrory

2017-03-01

Full Text Available Hundreds of thousands of revision surgeries for hip, knee, and shoulder joint arthroplasties are now performed worldwide annually. Partial removal of hardware during some types of revision surgeries may create significant amounts of third body metal, polymer, or bone cement debris. Retained debris may lead to a variety of negative health effects including damage to the joint replacement. We describe a novel technique for the better containment and easier removal of third body debris during partial hardware removal. We demonstrate hardware removal on a hip joint model in the presence and absence of water-soluble gel to depict the reduction in metal debris volume and area of spread.

Solar cooling in the hardware-in-the-loop test; Solare Kuehlung im Hardware-in-the-Loop-Test

Energy Technology Data Exchange (ETDEWEB)

Lohmann, Sandra; Radosavljevic, Rada; Goebel, Johannes; Gottschald, Jonas; Adam, Mario [Fachhochschule Duesseldorf (Germany). Erneuerbare Energien und Energieeffizienz E2

2012-07-01

The first part of the BMBF-funded research project 'Solar cooling in the hardware-in-the-loop test' (SoCool HIL) deals with the simulation of a solar refrigeration system using the simulation environment Matlab / Simulink with the toolboxes Stateflow and Carnot. Dynamic annual simulations and DoE supported parameter variations were used to select meaningful system configurations, control strategies and dimensioning of components. The second part of this project deals with hardware-in-the-loop tests using the 17.5 kW absorption chiller of the company Yazaki Europe Limited (Hertfordshire, United Kingdom). For this, the chiller is operated on a test bench in order to emulate the behavior of other system components (solar circuit with heat storage, recooling, buildings and cooling distribution / transfer). The chiller is controlled by a simulation of the system using MATLAB / Simulink / Carnot. Based on the knowledge on the real dynamic performance of the chiller the simulation model of the chiller can then be validated. Further tests are used to optimize the control of the chiller to the current cooling load. In addition, some changes in system configurations (for example cold backup) are tested with the real machine. The results of these tests and the findings on the dynamic performance of the chiller are presented.

Interfacing Hardware Accelerators to a Time-Division Multiplexing Network-on-Chip

DEFF Research Database (Denmark)

Pezzarossa, Luca; Sørensen, Rasmus Bo; Schoeberl, Martin

2015-01-01

This paper addresses the integration of stateless hardware accelerators into time-predictable multi-core platforms based on time-division multiplexing networks-on-chip. Stateless hardware accelerators, like floating-point units, are typically attached as co-processors to individual processors in ...... implementation. The design evaluation is carried out using the open source T-CREST multi-core platform implemented on an Altera Cyclone IV FPGA. The size of the proposed design, including a floating-point accelerator, is about two-thirds of a processor....

Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system

Science.gov (United States)

Ammendola, R.; Biagioni, A.; Frezza, O.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Paolucci, P. S.; Pastorelli, E.; Rossetti, D.; Simula, F.; Tosoratto, L.; Vicini, P.

2015-12-01

In the attempt to develop an interconnection architecture optimized for hybrid HPC systems dedicated to scientific computing, we designed APEnet+, a point-to-point, low-latency and high-performance network controller supporting 6 fully bidirectional off-board links over a 3D torus topology. The first release of APEnet+ (named V4) was a board based on a 40 nm Altera FPGA, integrating 6 channels at 34 Gbps of raw bandwidth per direction and a PCIe Gen2 x8 host interface. It has been the first-of-its-kind device to implement an RDMA protocol to directly read/write data from/to Fermi and Kepler NVIDIA GPUs using NVIDIA peer-to-peer and GPUDirect RDMA protocols, obtaining real zero-copy GPU-to-GPU transfers over the network. The latest generation of APEnet+ systems (now named V5) implements a PCIe Gen3 x8 host interface on a 28 nm Altera Stratix V FPGA, with multi-standard fast transceivers (up to 14.4 Gbps) and an increased amount of configurable internal resources and hardware IP cores to support main interconnection standard protocols. Herein we present the APEnet+ V5 architecture, the status of its hardware and its system software design. Both its Linux Device Driver and the low-level libraries have been redeveloped to support the PCIe Gen3 protocol, introducing optimizations and solutions based on hardware/software co-design.

Hardware Descriptive Languages: An Efficient Approach to Device ...

African Journals Online (AJOL)

Contemporarily, owing to astronomical advancements in the very large scale integration (VLSI) market segments, hardware engineers are now focusing on how to develop their new digital system designs in programmable languages like very high speed integrated circuit hardwaredescription language (VHDL) and Verilog ...

Another way of doing RSA cryptography in hardware

NARCIS (Netherlands)

Batina, L.; Bruin - Muurling, G.; Honary, B.

2001-01-01

In this paper we describe an efficient and secure hardware implementation of the RSA cryptosystem. Modular exponentiation is based on Montgomery’s method without any modular reduction achieving the optimal bound. The presented systolic array architecture is scalable in severalparameters which makes

Hardware-Oblivious Parallelism for In-Memory Column-Stores

NARCIS (Netherlands)

M. Heimel; M. Saecker; H. Pirk (Holger); S. Manegold (Stefan); V. Markl

2013-01-01

htmlabstractThe multi-core architectures of today’s computer systems make parallelism a necessity for performance critical applications. Writing such applications in a generic, hardware-oblivious manner is a challenging problem: Current database systems thus rely on labor-intensive and error-prone

Generalized Distance Transforms and Skeletons in Graphics Hardware

NARCIS (Netherlands)

Strzodka, R.; Telea, A.

2004-01-01

We present a framework for computing generalized distance transforms and skeletons of two-dimensional objects using graphics hardware. Our method is based on the concept of footprint splatting. Combining different splats produces weighted distance transforms for different metrics, as well as the

34 CFR 464.42 - What limit applies to purchasing computer hardware and software?

Science.gov (United States)

2010-07-01

... software? 464.42 Section 464.42 Education Regulations of the Offices of the Department of Education... computer hardware and software? Not more than ten percent of funds received under any grant under this part may be used to purchase computer hardware or software. (Authority: 20 U.S.C. 1208aa(f)) ...

A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture

Directory of Open Access Journals (Sweden)

Sungho Kang

1996-01-01

Full Text Available In order to reduce cost and to achieve high speed a new hardware accelerator for fault simulation has been designed. The architecture of the new accelerator is based on a reconfigurabl mesh type processing element (PE array. Circuit elements at the same topological level are simulated concurrently, as in a pipelined process. A new parallel simulation algorithm expands all of the gates to two input gates in order to limit the number of faults to two at each gate, so that the faults can be distributed uniformly throughout the PE array. The PE array reconfiguration operation provides a simulation speed advantage by maximizing the use of each PE cell.

Computer organization and design the hardware/software interface

CERN Document Server

Patterson, David A

2013-01-01

The 5th edition of Computer Organization and Design moves forward into the post-PC era with new examples, exercises, and material highlighting the emergence of mobile computing and the cloud. This generational change is emphasized and explored with updated content featuring tablet computers, cloud infrastructure, and the ARM (mobile computing devices) and x86 (cloud computing) architectures. Because an understanding of modern hardware is essential to achieving good performance and energy efficiency, this edition adds a new concrete example, "Going Faster," used throughout the text to demonstrate extremely effective optimization techniques. Also new to this edition is discussion of the "Eight Great Ideas" of computer architecture. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, computer arithmetic, pipelining, memory hierarchies and I/O. Optimization techniques featured throughout the text. It covers parallelism in depth with...

Co-verification of hardware and software for ARM SoC design

CERN Document Server

Andrews, Jason

2004-01-01

Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing. This is the first book to apply this verification technique to the rapidly growing field of embedded systems-on-a-chip(SoC). As traditional embedded system design evolves into single-chip design, embedded engineers must be armed with the necessary information to make educated decisions about which tools and methodology to deploy. SoC verification requires a mix of expertise from the disciplines of microprocessor and computer architecture, logic design and simulation, and C and Assembly language embedded software. Until now, the relevant information on how it all fits together has not been available. Andrews, a recognized expert, provides in-depth information about how co-verification really works, how to be successful using it, and pitfalls to avoid. H...

Hardwood log grades and lumber grade yields for factory lumber logs

Science.gov (United States)

Leland F. Hanks; Glenn L. Gammon; Robert L. Brisbin; Everette D. Rast

1980-01-01

The USDA Forest Service Standard Grades for Hardwood Factory Lumber Logs are described, and lumber grade yields for 16 species and 2 species groups are presented by log grade and log diameter. The grades enable foresters, log buyers, and log sellers to select and grade those log suitable for conversion into standard factory grade lumber. By using the apropriate lumber...

Technological Studies at Thomas Edison Middle School. Grades 6-7-8.