A Gateway MultiSite recombination cloning toolkit.

Directory of Open Access Journals (Sweden)

Lena K Petersen

Full Text Available The generation of DNA constructs is often a rate-limiting step in conducting biological experiments. Recombination cloning of single DNA fragments using the Gateway system provided an advance over traditional restriction enzyme cloning due to increases in efficiency and reliability. Here we introduce a series of entry clones and a destination vector for use in two, three, and four fragment Gateway MultiSite recombination cloning whose advantages include increased flexibility and versatility. In contrast to Gateway single-fragment cloning approaches where variations are typically incorporated into model system-specific destination vectors, our Gateway MultiSite cloning strategy incorporates variations in easily generated entry clones that are model system-independent. In particular, we present entry clones containing insertions of GAL4, QF, UAS, QUAS, eGFP, and mCherry, among others, and demonstrate their in vivo functionality in Drosophila by using them to generate expression clones including GAL4 and QF drivers for various trp ion channel family members, UAS and QUAS excitatory and inhibitory light-gated ion channels, and QUAS red and green fluorescent synaptic vesicle markers. We thus establish a starter toolkit of modular Gateway MultiSite entry clones potentially adaptable to any model system. An inventory of entry clones and destination vectors for Gateway MultiSite cloning has also been established (www.gatewaymultisite.org.

Multi-Gateway-Based Energy Holes Avoidance Routing Protocol for WSN

Directory of Open Access Journals (Sweden)

Rohini Sharma

2016-04-01

Full Text Available In wireless sensor networks (WSNs, efficient energy conservation is required to prolong the lifetime of the network. In this work, we have given emphasis on balanced energy consumption and energy holes avoidance. This paper proposes a multi-gateway-based approach to reduce the transmission distance between the sender and the sink node. The area to be monitored is divided into regions and gateway nodes are deployed at optimal positions. We have designed a transmission scheme, in which sensors in the sink region communicate directly to the sink, sensors in the gateway region communicate directly to the gateway, and sensors in the cluster region transmit their data directly to their respective cluster head which transmits data to the gateway in its region. If the distance between a cluster head and the sink is less than the distance between the cluster head and the gateway node, the cluster head transmits data to the sink instead of the gateway node. We have compared the proposed protocol with Low-Energy Adaptive Clustering Hierarchy (LEACH, Gateway Based Energy Aware Multi-Hop Routing (M-GEAR, and Gateway Based Stable Election Protocol (GSEP protocols. The protocol performs better than other protocols in terms of throughput, stability period, lifetime, residual energy, and the packet transmitted to the sink.

Subject Gateway Sites and Search Engine Ranking.

Science.gov (United States)

Thelwall, Mike

2002-01-01

Discusses subject gateway sites and commercial search engines for the Web and presents an explanation of Google's PageRank algorithm. The principle question addressed is the conditions under which a gateway site will increase the likelihood that a target page is found in search engines. (LRW)

A Smart Home Gateway Platform for Data Collection and Awareness

OpenAIRE

Wang, Pan; Ye, Feng; Chen, Xuejiao

2018-01-01

Smart homes have attracted much attention due to the expanding of Internet-of-Things (IoT) and smart devices. In this paper, we propose a smart gateway platform for data collection and awareness in smart home networks. A smart gateway will replace the traditional network gateway to connect the home network and the Internet. A smart home network supports different types of smart devices, such as in home IoT devices, smart phones, smart electric appliances, etc. A traditional network gateway is...

Performance Evaluation of a Multipurpose Bare PC Gateway

DEFF Research Database (Denmark)

Tsetse, Anthony; Appiah-Kubi, Patrick; Loukili, Alae

2015-01-01

. Different solutions (6to4 tunneling, IVI translation, NAT64, DNS64 etc.), have being proposed but these are all standalone systems. In this paper we discuss the design,implementation and performance evaluation of a multipurpose Bare PC Gateway which incorporates Network Address translation (NAT), 6to4...... results indicate a relatively better performance (18%-45%) of the Bare PC gateway compared to a Linux gateway (running the functionalities as standalone systems). We believe the proposed solution could easily scale to wide area networks and also provide a cost efficient solution...

SEDAC information gateway plan V(1)

Science.gov (United States)

Chen, Robert S. (Compiler)

1995-01-01

This annual update of the Information Gateway Plan incorporates changes recommended by the Socioeconomic Data and Applications Center (SEDAC) User Working Group (UWG) and reflects comments and suggestions from users, collaborators, and the Contracting Officer Technical Representative (COTR). The Information Gateway Plan is a concise and specific plan that outlines SEDAC activities and services in support of the earth and social sciences and other user communities. The SEDAC Information Gateway effort is a primary means by which the Earth Observing System Data and Information System (EOSDIS) can link meaningfully with a broad range of social science data sources and users in ways that lead to tangible benefits to the American people. The SEDAC Information Gateway provides interdisciplinary access to socioeconomic and physical science data and information resources held by SEDAC and numerous other institutions and networks around the world. The Plan describes the areas of research of earth scientists and socioeconomic scientists where interchange of data and information is most needed. It sets guidelines for the continued development of SEDAC's directory of social science datasets and establishes priorities for efforts to make data held by SEDAC or accessible through SEDAC available to the user community. The Plan also describes the means by which the SEDAC user community can access information products specified by the SEDAC Data and Applications Development Plan (DADP). Among other major activities, SEDAC will continue to enhance and operate a directory capability, interoperable with the Global Change Master Directory, that provides the socioeconomic community with information about earth science products and the earth science research community with information about socioeconomic data. The Information Gateway also serves as a unique and powerful access pathway for a wide range of users and potential users of socioeconomic and earth science data, including

Neutron Science TeraGrid Gateway

International Nuclear Information System (INIS)

Lynch, Vickie E.; Chen, Meili; Cobb, John W.; Kohl, James Arthur; Miller, Stephen D.; Speirs, David A.; Vazhkudai, Sudharshan S.

2010-01-01

The unique contributions of the Neutron Science TeraGrid Gateway (NSTG) are the connection of national user facility instrument data sources to the integrated cyberinfrastructure of the National Science FoundationTeraGrid and the development of a neutron science gateway that allows neutron scientists to use TeraGrid resources to analyze their data, including comparison of experiment with simulation. The NSTG is working in close collaboration with the Spallation Neutron Source (SNS) at Oak Ridge as their principal facility partner. The SNS is a next-generation neutron source. It has completed construction at a cost of $1.4 billion and is ramping up operations. The SNS will provide an order of magnitude greater flux than any previous facility in the world and will be available to all of the nation's scientists, independent of funding source, on a peer-reviewed merit basis. With this new capability, the neutron science community is facing orders of magnitude larger data sets and is at a critical point for data analysis and simulation. There is a recognized need for new ways to manage and analyze data to optimize both beam time and scientific output. The TeraGrid is providing new capabilities in the gateway for simulations using McStas and a fitting service on distributed TeraGrid resources to improved turnaround. NSTG staff are also exploring replicating experimental data in archival storage. As part of the SNS partnership, the NSTG provides access to gateway support, cyberinfrastructure outreach, community development, and user support for the neutron science community. This community includes not only SNS staff and users but extends to all the major worldwide neutron scattering centers.

A gateway to the Gulf

International Nuclear Information System (INIS)

Crawford, A.P.

1992-01-01

One day in February 1991, a man strolling along a bucolic stretch of rural real estate in Alabama heard the call of what he later discovered to be a red-cockaded woodpecker. A rare event, this would ordinarily have been a pleasant surprise. When officials at the Federal Energy Regulatory Commission (FERC) in Washington, D.C., got word of the red's siting, they took notice. And when Dan Mitchell and Jamie Craddock at United Gas Pipe Line Co. in Houston found out, they just shook their heads --- again. The red-cockaded woodpecker is but one of the uniquely named, federally protected species native to South Alabama that Mitchell and Craddock had to constantly concern themselves with as they attempted to ensure the environmental and regulatory compliance of United's recently completed 28-mile Gateway gas pipeline near gas-rich Mobile Bay. Until May 1, when United put Gateway into service, it had taken more than six years to plan and construct the most environmentally correct route for the pipeline. This paper discusses the largest portion of Gateway's route which is piney forest or agricultural land with the wetlands area prevalent in the southern end of the route

Global Document Delivery, User Studies, and Service Evaluation: The Gateway Experience

Science.gov (United States)

Miller, Rush; Xu, Hong; Zou, Xiuying

2008-01-01

This study examines user and service data from 2002-2006 at the East Asian Gateway Service for Chinese and Korean Academic Journal Publications (Gateway Service), the University of Pittsburgh. Descriptive statistical analysis reveals that the Gateway Service has been consistently playing the leading role in global document delivery service as well…

Mentoring the Next Generation of Science Gateway Developers and Users

Science.gov (United States)

Hayden, L. B.; Jackson-Ward, F.

2016-12-01

The Science Gateway Institute (SGW-I) for the Democratization and Acceleration of Science was a SI2-SSE Collaborative Research conceptualization award funded by NSF in 2012. From 2012 through 2015, we engaged interested members of the science and engineering community in a planning process for a Science Gateway Community Institute (SGCI). Science Gateways provide Web interfaces to some of the most sophisticated cyberinfrastructure resources. They interact with remotely executing science applications on supercomputers, they connect to remote scientific data collections, instruments and sensor streams, and support large collaborations. Gateways allow scientists to concentrate on the most challenging science problems while underlying components such as computing architectures and interfaces to data collection changes. The goal of our institute was to provide coordinating activities across the National Science Foundation, eventually providing services more broadly to projects funded by other agencies. SGW-I has succeeded in identifying two underrepresented communities of future gateway designers and users. The Association of Computer and Information Science/Engineering Departments at Minority Institutions (ADMI) was identified as a source of future gateway designers. The National Organization for the Professional Advancement of Black Chemists and Chemical Engineers (NOBCChE) was identified as a community of future science gateway users. SGW-I efforts to engage NOBCChE and ADMI faculty and students in SGW-I are now woven into the workforce development component of SGCI. SGCI (ScienceGateways.org ) is a collaboration of six universities, led by San Diego Supercomputer Center. The workforce development component is led by Elizabeth City State University (ECSU). ECSU efforts focus is on: Produce a model of engagement; Integration of research into education; and Mentoring of students while aggressively addressing diversity. This paper documents the outcome of the SGW

Construction of gateway-compatible yeast two-hybrid vectors for ...

African Journals Online (AJOL)

USER

2010-03-01

Mar 1, 2010 ... vectors pBTM116GW and pVP16GW by introducing the gateway cassette ... Key words: Yeast two-hybrid, gateway cloning technology, protein interaction. .... cycling parameters were as follows: an initial denaturation step at.

Remote Sensing Information Gateway

Science.gov (United States)

Remote Sensing Information Gateway, a tool that allows scientists, researchers and decision makers to access a variety of multi-terabyte, environmental datasets and to subset the data and obtain only needed variables, greatly improving the download time.

Data-intensive science gateway for rock physicists and volcanologists.

Science.gov (United States)

Filgueira, Rosa; Atkinson, Malcom; Bell, Andrew; Main, Ian; Boon, Steve; Meredith, Philp; Kilburn, Christopher

2014-05-01

Scientists have always shared data and mathematical models of the phenomena they study. Rock physics and Volcanology, as well as other solid-Earth sciences, have increasingly used Internet communications and computational renditions of their models for this purpose over the last two decades. Here we consider how to organise rock physics and volcanology data to open up opportunities for sharing and comparing both experiment data from experiments, observations and model runs and analytic interpretations of these data. Our hypothesis is that if we facilitate productive information sharing across those communities by using a new science gateway, it will benefit the science. The proposed science gateway should make the first steps for making existing research practices easier and facilitate new research. It will achieve this by supporting three major functions: 1) sharing data from laboratories and observatories, experimental facilities and models; 2) sharing models of rock fracture and methods for analysing experimental data; and 3) supporting recurrent operational tasks, such as data collection and model application in real time. We report initial work in two projects (NERC EFFORT and NERC CREEP-2) and experience with an early web-accessible protytpe called EFFORT gateway, where we are implementing such information sharing services for those projects. 1. Sharing data: In EFFORT gateway, we are working on several facilities for sharing data: *Upload data: We have designed and developed a new adaptive data transfer java tool called FAST (Flexible Automated Streaming Transfer) to upload experimental data and metadata periodically from laboratories to our repository. *Visualisation: As data are deposited in the repository, a visualisation of the accumulated data is made available for display in the Web portal. *Metadata and catalogues: The gateway uses a repository to hold all the data and a catalogue to hold all the corresponding metadata. 2. Sharing models and methods

A data-centric neuroscience gateway: design, implementation, and experiences

NARCIS (Netherlands)

Shahand, Shayan; Benabdelkader, Ammar; Jaghoori, Mohammad Mahdi; al Mourabit, Mostapha; Huguet, Jordi; Caan, Matthan W. A.; van Kampen, Antoine H. C.; Olabarriaga, Silvia D.

2015-01-01

Science gateways provide UIs and high-level services to access and manage applications and data collections on distributed resources. They facilitate users to perform data analysis on distributed computing infrastructures without getting involved into the technical details. The e-BioInfra Gateway is

Alcohol as a Gateway Drug: A Study of US 12th Graders

Science.gov (United States)

Kirby, Tristan; Barry, Adam E.

2012-01-01

Background: The Gateway Drug Theory suggests that licit drugs, such as tobacco and alcohol, serve as a "gateway" toward the use of other, illicit drugs. However, there remains some discrepancy regarding which drug--alcohol, tobacco, or even marijuana--serves as the initial "gateway" drug subsequently leading to the use of…

The Einstein Genome Gateway using WASP - a high throughput multi-layered life sciences portal for XSEDE.

Science.gov (United States)

Golden, Aaron; McLellan, Andrew S; Dubin, Robert A; Jing, Qiang; O Broin, Pilib; Moskowitz, David; Zhang, Zhengdong; Suzuki, Masako; Hargitai, Joseph; Calder, R Brent; Greally, John M

2012-01-01

Massively-parallel sequencing (MPS) technologies and their diverse applications in genomics and epigenomics research have yielded enormous new insights into the physiology and pathophysiology of the human genome. The biggest hurdle remains the magnitude and diversity of the datasets generated, compromising our ability to manage, organize, process and ultimately analyse data. The Wiki-based Automated Sequence Processor (WASP), developed at the Albert Einstein College of Medicine (hereafter Einstein), uniquely manages to tightly couple the sequencing platform, the sequencing assay, sample metadata and the automated workflows deployed on a heterogeneous high performance computing cluster infrastructure that yield sequenced, quality-controlled and 'mapped' sequence data, all within the one operating environment accessible by a web-based GUI interface. WASP at Einstein processes 4-6 TB of data per week and since its production cycle commenced it has processed ~ 1 PB of data overall and has revolutionized user interactivity with these new genomic technologies, who remain blissfully unaware of the data storage, management and most importantly processing services they request. The abstraction of such computational complexity for the user in effect makes WASP an ideal middleware solution, and an appropriate basis for the development of a grid-enabled resource - the Einstein Genome Gateway - as part of the Extreme Science and Engineering Discovery Environment (XSEDE) program. In this paper we discuss the existing WASP system, its proposed middleware role, and its planned interaction with XSEDE to form the Einstein Genome Gateway.

Design of smart home gateway based on Wi-Fi and ZigBee

Science.gov (United States)

Li, Yang

2018-04-01

With the increasing demand for home lifestyle, the traditional smart home products have been unable to meet the needs of users. Aim at the complex wiring, high cost and difficult operation problems of traditional smart home system, this paper designs a home gateway for smart home system based on Wi-Fi and ZigBee. This paper first gives a smart home system architecture base on cloud server, Wi-Fi and ZigBee. This architecture enables users to access the smart home system remotely from Internet through the cloud server or through Wi-Fi at home. It also offers the flexibility and low cost of ZigBee wireless networking for home equipment. This paper analyzes the functional requirements of the home gateway, and designs a modular hardware architecture based on the RT5350 wireless gateway module and the CC2530 ZigBee coordinator module. Also designs the software of the home gateway, including the gateway master program and the ZigBee coordinator program. Finally, the smart home system and home gateway are tested in two kinds of network environments, internal network and external network. The test results show that the designed home gateway can meet the requirements, support remote and local access, support multi-user, support information security technology, and can timely report equipment status information.

Convergence of Residential Gateway technology: analysis of evolutionary paths

NARCIS (Netherlands)

Hartog, den F.T.H.; Balm, M.; Jong, de C.M.; Kwaaitaal, J.J.B.

2004-01-01

A new OSI (Open Systems Interconnection)-based model is described that can be used for the classification of residential gateways (RG). It is applied to analyze current gateway solutions and to draw evolutionary paths for the mid-to-long term. It is concluded that set-top boxes and broadband modems

Construction of gateway-compatible yeast two-hybrid vectors for ...

African Journals Online (AJOL)

Yeast two-hybrid system combined with the gateway technology will greatly facilitate the cloning of interested DNA fragment into yeast two-hybrid vectors and therefore increase the efficiency of yeast two-hybrid analysis. In this study, we constructed a pair of Gateway-compatible yeast two-hybrid vectors pBTM116GW and ...

Array processor architecture

Science.gov (United States)

Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

1983-01-01

A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

Green Secure Processors: Towards Power-Efficient Secure Processor Design

Science.gov (United States)

Chhabra, Siddhartha; Solihin, Yan

With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the software stack of a system, hardware attacks have become equally likely. Researchers have proposed Secure Processor Architectures which utilize hardware mechanisms for memory encryption and integrity verification to protect the confidentiality and integrity of data and computation, even from sophisticated hardware attacks. While there have been many works addressing performance and other system level issues in secure processor design, power issues have largely been ignored. In this paper, we first analyze the sources of power (energy) increase in different secure processor architectures. We then present a power analysis of various secure processor architectures in terms of their increase in power consumption over a base system with no protection and then provide recommendations for designs that offer the best balance between performance and power without compromising security. We extend our study to the embedded domain as well. We also outline the design of a novel hybrid cryptographic engine that can be used to minimize the power consumption for a secure processor. We believe that if secure processors are to be adopted in future systems (general purpose or embedded), it is critically important that power issues are considered in addition to performance and other system level issues. To the best of our knowledge, this is the first work to examine the power implications of providing hardware mechanisms for security.

Probabilistic programmable quantum processors

International Nuclear Information System (INIS)

Buzek, V.; Ziman, M.; Hillery, M.

2004-01-01

We analyze how to improve performance of probabilistic programmable quantum processors. We show how the probability of success of the probabilistic processor can be enhanced by using the processor in loops. In addition, we show that an arbitrary SU(2) transformations of qubits can be encoded in program state of a universal programmable probabilistic quantum processor. The probability of success of this processor can be enhanced by a systematic correction of errors via conditional loops. Finally, we show that all our results can be generalized also for qudits. (Abstract Copyright [2004], Wiley Periodicals, Inc.)

Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

OpenAIRE

Abdul Kareem PARCHUR; Ram Asaray SINGH

2012-01-01

High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310). The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many ke...

The LASS hardware processor

International Nuclear Information System (INIS)

Kunz, P.F.

1976-01-01

The problems of data analysis with hardware processors are reviewed and a description is given of a programmable processor. This processor, the 168/E, has been designed for use in the LASS multi-processor system; it has an execution speed comparable to the IBM 370/168 and uses the subset of IBM 370 instructions appropriate to the LASS analysis task. (Auth.)

Formal Semantics and Implementation of BPMN 2.0 Inclusive Gateways

Science.gov (United States)

Christiansen, David Raymond; Carbone, Marco; Hildebrandt, Thomas

We present the first direct formalization of the semantics of inclusive gateways as described in the Business Process Modeling Notation (BPMN) 2.0 Beta 1 specification. The formal semantics is given for a minimal subset of BPMN 2.0 containing just the inclusive and exclusive gateways and the start and stop events. By focusing on this subset we achieve a simple graph model that highlights the particular non-local features of the inclusive gateway semantics. We sketch two ways of implementing the semantics using algorithms based on incrementally updated data structures and also discuss distributed communication-based implementations of the two algorithms.

Deep Space Gateway Science Opportunities

Science.gov (United States)

Quincy, C. D.; Charles, J. B.; Hamill, Doris; Sidney, S. C.

2018-01-01

The NASA Life Sciences Research Capabilities Team (LSRCT) has been discussing deep space research needs for the last two years. NASA's programs conducting life sciences studies - the Human Research Program, Space Biology, Astrobiology, and Planetary Protection - see the Deep Space Gateway (DSG) as affording enormous opportunities to investigate biological organisms in a unique environment that cannot be replicated in Earth-based laboratories or on Low Earth Orbit science platforms. These investigations may provide in many cases the definitive answers to risks associated with exploration and living outside Earth's protective magnetic field. Unlike Low Earth Orbit or terrestrial locations, the Gateway location will be subjected to the true deep space spectrum and influence of both galactic cosmic and solar particle radiation and thus presents an opportunity to investigate their long-term exposure effects. The question of how a community of biological organisms change over time within the harsh environment of space flight outside of the magnetic field protection can be investigated. The biological response to the absence of Earth's geomagnetic field can be studied for the first time. Will organisms change in new and unique ways under these new conditions? This may be specifically true on investigations of microbial communities. The Gateway provides a platform for microbiology experiments both inside, to improve understanding of interactions between microbes and human habitats, and outside, to improve understanding of microbe-hardware interactions exposed to the space environment.

The Neutron Science TeraGrid Gateway, a TeraGrid Science Gateway to Support the Spallation Neutron Source

International Nuclear Information System (INIS)

Cobb, John W.; Geist, Al; Kohl, James Arthur; Miller, Stephen D; Peterson, Peter F.; Pike, Gregory; Reuter, Michael A; Swain, William; Vazhkudai, Sudharshan S.; Vijayakumar, Nithya N.

2006-01-01

The National Science Foundation's (NSF's) Extensible Terascale Facility (ETF), or TeraGrid (1) is entering its operational phase. An ETF science gateway effort is the Neutron Science TeraGrid Gateway (NSTG.) The Oak Ridge National Laboratory (ORNL) resource provider effort (ORNL-RP) during construction and now in operations is bridging a large scale experimental community and the TeraGrid as a large-scale national cyberinfrastructure. Of particular emphasis is collaboration with the Spallation Neutron Source (SNS) at ORNL. The U.S. Department of Energy's (DOE's) SNS (2) at ORNL will be commissioned in spring of 2006 as the world's brightest source of neutrons. Neutron science users can run experiments, generate datasets, perform data reduction, analysis, visualize results; collaborate with remotes users; and archive long term data in repositories with curation services. The ORNL-RP and the SNS data analysis group have spent 18 months developing and exploring user requirements, including the creation of prototypical services such as facility portal, data, and application execution services. We describe results from these efforts and discuss implications for science gateway creation. Finally, we show incorporation into implementation planning for the NSTG and SNS architectures. The plan is for a primarily portal-based user interaction supported by a service oriented architecture for functional implementation

Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

Directory of Open Access Journals (Sweden)

Abdul Kareem PARCHUR

2012-08-01

Full Text Available High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310. The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many key application areas in modern generation. The scaling of performance in two major series of Intel Xeon processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310 has been analyzed using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. The results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.

Simulation of a parallel processor on a serial processor: The neutron diffusion equation

International Nuclear Information System (INIS)

Honeck, H.C.

1981-01-01

Parallel processors could provide the nuclear industry with very high computing power at a very moderate cost. Will we be able to make effective use of this power. This paper explores the use of a very simple parallel processor for solving the neutron diffusion equation to predict power distributions in a nuclear reactor. We first describe a simple parallel processor and estimate its theoretical performance based on the current hardware technology. Next, we show how the parallel processor could be used to solve the neutron diffusion equation. We then present the results of some simulations of a parallel processor run on a serial processor and measure some of the expected inefficiencies. Finally we extrapolate the results to estimate how actual design codes would perform. We find that the standard numerical methods for solving the neutron diffusion equation are still applicable when used on a parallel processor. However, some simple modifications to these methods will be necessary if we are to achieve the full power of these new computers. (orig.) [de

Center for Integrated Nanotechnologies (CINT) - Gateway

Data.gov (United States)

Federal Laboratory Consortium — The CINT Gateway to Los Alamos Facility, located at Los Alamos National Laboratory in the center of the Materials Science Complex, brings together materials science...

An Authentication Gateway for Integrated Grid and Cloud Access

International Nuclear Information System (INIS)

Ciaschini, V; Salomoni, D

2011-01-01

The WNoDeS architecture, providing distributed, integrated access to both Cloud and Grid resources through virtualization technologies, makes use of an Authentication Gateway to support diverse authentication mechanisms. Three main use cases are foreseen, covering access via X.509 digital certificates, federated services like Shibboleth or Kerberos, and credit-based access. In this paper, we describe the structure of the WNoDeS authentication gateway.

The Gateway to Cosmic Dawn: A Low Frequency Radio Telescope for the Deep Space Gateway

Science.gov (United States)

Tauscher, K.; Burns, J. O.; Monsalve, R.; Rapetti, D.

2018-02-01

We suggest that, with a suitable antenna and receiver, the Deep Space Gateway can be used to measure the highly redshifted, global 21-cm signal from neutral hydrogen, a spectral imprint of the history of the universe onto cosmic background radiation.

Environmental Dataset Gateway (EDG) REST Interface

Data.gov (United States)

U.S. Environmental Protection Agency — Use the Environmental Dataset Gateway (EDG) to find and access EPA's environmental resources. Many options are available for easily reusing EDG content in other...

Deep Space Gateway "Recycler" Mission

Science.gov (United States)

Graham, L.; Fries, M.; Hamilton, J.; Landis, R.; John, K.; O'Hara, W.

2018-02-01

Use of the Deep Space Gateway provides a hub for a reusable planetary sample return vehicle for missions to gather star dust as well as samples from various parts of the solar system including main belt asteroids, near-Earth asteroids, and Mars moon.

Expansion of the gateway multisite recombination cloning toolkit.

Science.gov (United States)

Shearin, Harold K; Dvarishkis, Alisa R; Kozeluh, Craig D; Stowers, R Steven

2013-01-01

Precise manipulation of transgene expression in genetic model organisms has led to advances in understanding fundamental mechanisms of development, physiology, and genetic disease. Transgene construction is, however, a precondition of transgene expression, and often limits the rate of experimental progress. Here we report an expansion of the modular Gateway MultiSite recombination-cloning platform for high efficiency transgene assembly. The expansion includes two additional destination vectors and entry clones for the LexA binary transcription system, among others. These new tools enhance the expression levels possible with Gateway MultiSite generated transgenes and make possible the generation of LexA drivers and reporters with Gateway MultiSite cloning. In vivo data from transgenic Drosophila functionally validating each novel component are presented and include neuronal LexA drivers, LexAop2 red and green fluorescent synaptic vesicle reporters, TDC2 and TRH LexA, GAL4, and QF drivers, and LexAop2, UAS, and QUAS channelrhodopsin2 T159C reporters.

Functional unit for a processor

NARCIS (Netherlands)

Rohani, A.; Kerkhoff, Hans G.

2013-01-01

The invention relates to a functional unit for a processor, such as a Very Large Instruction Word Processor. The invention further relates to a processor comprising at least one such functional unit. The invention further relates to a functional unit and processor capable of mitigating the effect of

Communication-Gateway Software For NETEX, DECnet, And TCP/IP

Science.gov (United States)

Keith, B.; Ferry, D.; Fendler, E.

1990-01-01

Communications gateway software, GATEWAY, provides process-to-process communication between remote applications programs in different protocol domains. Communicating peer processes may be resident on any paired combination of NETEX, DECnet, or TCP/IP hosts. Provides necessary mapping from one protocol to another and facilitates practical intermachine communications in cost-effective manner by eliminating need to standardize on single protocol or to implement multiple protocols in host computers. Written in Ada.

Adaptive signal processor

Energy Technology Data Exchange (ETDEWEB)

Walz, H.V.

1980-07-01

An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 ..mu..sec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed.

Adaptive signal processor

International Nuclear Information System (INIS)

Walz, H.V.

1980-07-01

An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 μsec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed

Multithreading in vector processors

Science.gov (United States)

Evangelinos, Constantinos; Kim, Changhoan; Nair, Ravi

2018-01-16

In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

A Smart Gateway Architecture for Improving Efficiency of Home Network Applications

Directory of Open Access Journals (Sweden)

Fei Ding

2016-01-01

Full Text Available A smart home gateway plays an important role in the Internet of Things (IoT system that takes responsibility for the connection between the network layer and the ubiquitous sensor network (USN layer. Even though the home network application is developing rapidly, researches on the home gateway based open development architecture are less. This makes it difficult to extend the home network to support new applications, share service, and interoperate with other home network systems. An integrated access gateway (IAGW is proposed in this paper which upward connects with the operator machine-to-machine platform (M2M P/F. In this home network scheme, the gateway provides standard interfaces for supporting various applications in home environments, ranging from on-site configuration to node and service access. In addition, communication management ability is also provided by M2M P/F. A testbed of a simple home network application system that includes the IAGW prototype is created to test its user interaction capabilities. Experimental results show that the proposed gateway provides significant flexibility for users to configure and deploy a home automation network; it can be applied to other monitoring areas and simultaneously supports a multi-ubiquitous sensor network.

Dual-core Itanium Processor

CERN Multimedia

2006-01-01

Intel’s first dual-core Itanium processor, code-named "Montecito" is a major release of Intel's Itanium 2 Processor Family, which implements the Intel Itanium architecture on a dual-core processor with two cores per die (integrated circuit). Itanium 2 is much more powerful than its predecessor. It has lower power consumption and thermal dissipation.

3081/E processor

International Nuclear Information System (INIS)

Kunz, P.F.; Gravina, M.; Oxoby, G.

1984-04-01

The 3081/E project was formed to prepare a much improved IBM mainframe emulator for the future. Its design is based on a large amount of experience in using the 168/E processor to increase available CPU power in both online and offline environments. The processor will be at least equal to the execution speed of a 370/168 and up to 1.5 times faster for heavy floating point code. A single processor will thus be at least four times more powerful than the VAX 11/780, and five processors on a system would equal at least the performance of the IBM 3081K. With its large memory space and simple but flexible high speed interface, the 3081/E is well suited for the online and offline needs of high energy physics in the future

GATEWAY Report Brief: SSL Demonstration: Long-Term Evaluation of Indoor Field Performance

Energy Technology Data Exchange (ETDEWEB)

None, None

2017-02-28

Report brief summarizing a GATEWAY program evaluation of the long-term performance characteristics (chromaticity change, maintained illuminance, and operations and maintenance) of LED lighting systems in four field installations previously documented in separate DOE GATEWAY reports.

Integrated fuel processor development

International Nuclear Information System (INIS)

Ahmed, S.; Pereira, C.; Lee, S. H. D.; Krumpelt, M.

2001-01-01

The Department of Energy's Office of Advanced Automotive Technologies has been supporting the development of fuel-flexible fuel processors at Argonne National Laboratory. These fuel processors will enable fuel cell vehicles to operate on fuels available through the existing infrastructure. The constraints of on-board space and weight require that these fuel processors be designed to be compact and lightweight, while meeting the performance targets for efficiency and gas quality needed for the fuel cell. This paper discusses the performance of a prototype fuel processor that has been designed and fabricated to operate with liquid fuels, such as gasoline, ethanol, methanol, etc. Rated for a capacity of 10 kWe (one-fifth of that needed for a car), the prototype fuel processor integrates the unit operations (vaporization, heat exchange, etc.) and processes (reforming, water-gas shift, preferential oxidation reactions, etc.) necessary to produce the hydrogen-rich gas (reformate) that will fuel the polymer electrolyte fuel cell stacks. The fuel processor work is being complemented by analytical and fundamental research. With the ultimate objective of meeting on-board fuel processor goals, these studies include: modeling fuel cell systems to identify design and operating features; evaluating alternative fuel processing options; and developing appropriate catalysts and materials. Issues and outstanding challenges that need to be overcome in order to develop practical, on-board devices are discussed

XDS-I Gateway Development for HIE Connectivity with Legacy PACS at Gil Hospital.

Science.gov (United States)

Simalango, Mikael Fernandus; Kim, Youngchul; Seo, Young Tae; Choi, Young Hwan; Cho, Yong Kyun

2013-12-01

The ability to support healthcare document sharing is imperative in a health information exchange (HIE). Sharing imaging documents or images, however, can be challenging, especially when they are stored in a picture archiving and communication system (PACS) archive that does not support document sharing via standard HIE protocols. This research proposes a standard-compliant imaging gateway that enables connectivity between a legacy PACS and the entire HIE. Investigation of the PACS solutions used at Gil Hospital was conducted. An imaging gateway application was then developed using a Java technology stack. Imaging document sharing capability enabled by the gateway was tested by integrating it into Gil Hospital's order communication system and its HIE infrastructure. The gateway can acquire radiology images from a PACS storage system, provide and register the images to Gil Hospital's HIE for document sharing purposes, and make the images retrievable by a cross-enterprise document sharing document viewer. Development of an imaging gateway that mediates communication between a PACS and an HIE can be considered a viable option when the PACS does not support the standard protocol for cross-enterprise document sharing for imaging. Furthermore, the availability of common HIE standards expedites the development and integration of the imaging gateway with an HIE.

Region & Gateway Mapping

OpenAIRE

Schröter, Derik

2007-01-01

State-of-the-art robot mapping approaches are capable of acquiring impressively accurate 2D and 3D models of their environments. To the best of our knowledge, few of them represent structure or acquire models of task-relevant objects. In this work, a new approach to mapping of indoor environments is presented, in which the environment structure in terms of regions and gateways is automatically extracted, while the robot explores. Objects, both in 2D and 3D, are modeled explicitly in those map...

High-performance parallel interface to synchronous optical network gateway

Science.gov (United States)

St. John, Wallace B.; DuBois, David H.

1998-08-11

A digital system provides sending and receiving gateways for HIPPI interfaces. Electronic logic circuitry formats data signals and overhead signals in a data frame that is suitable for transmission over a connecting fiber optic link. Multiplexers route the data and overhead signals to a framer module. The framer module allocates the data and overhead signals to a plurality of 9-byte words that are arranged in a selected protocol. The formatted words are stored in a storage register for output through the gateway.

The use and effectiveness of the eLib subject gateways: a preliminary investigation

OpenAIRE

Mackie, M.; Burton, P.F.

1999-01-01

Internet subject gateways were set up under the Electronic Libraries Programme (eLib) in order to address some of the problems of searching the Internet which have been identified by information professionals, i.e. locating relevant, good quality information. This preliminary study examines the extent to which academics in two universities use three eLib subject gateways (EEVL, OMNI and SOSIG). The results are generally encouraging for the eLib programme, but it is necessary for the gateways ...

A Remote Health Monitoring System for the Elderly Based on Smart Home Gateway

OpenAIRE

Guan, Kai; Shao, Minggang; Wu, Shuicai

2017-01-01

This paper proposed a remote health monitoring system for the elderly based on smart home gateway. The proposed system consists of three parts: the smart clothing, the smart home gateway, and the health care server. The smart clothing collects the elderly's electrocardiogram (ECG) and motion signals. The home gateway is used for data transmission. The health care server provides services of data storage and user information management; it is constructed on the Windows-Apache-MySQL-PHP (WAMP) ...

The Gateway Reflex, a Novel Neuro-Immune Interaction for the Regulation of Regional Vessels

Directory of Open Access Journals (Sweden)

Yuki Tanaka

2017-10-01

Full Text Available The gateway reflex is a new phenomenon that explains how immune cells bypass the blood–brain barrier to infiltrate the central nervous system (CNS and trigger neuroinflammation. To date, four examples of gateway reflexes have been discovered, each described by the stimulus that evokes the reflex. Gravity, electricity, pain, and stress have all been found to create gateways at specific regions of the CNS. The gateway reflex, the most recently discovered of the four, has also been shown to upset the homeostasis of organs in the periphery through its action on the CNS. These reflexes provide novel therapeutic targets for the control of local neuroinflammation and organ function. Each gateway reflex is activated by different neural activations and induces inflmammation at different regions in the CNS. Therefore, it is theoretically possible to manipulate each independently, providing a novel therapeutic strategy to control local neuroinflammation and peripheral organ homeostasis.

A Remote Health Monitoring System for the Elderly Based on Smart Home Gateway

Directory of Open Access Journals (Sweden)

Kai Guan

2017-01-01

Full Text Available This paper proposed a remote health monitoring system for the elderly based on smart home gateway. The proposed system consists of three parts: the smart clothing, the smart home gateway, and the health care server. The smart clothing collects the elderly’s electrocardiogram (ECG and motion signals. The home gateway is used for data transmission. The health care server provides services of data storage and user information management; it is constructed on the Windows-Apache-MySQL-PHP (WAMP platform and is tested on the Ali Cloud platform. To resolve the issues of data overload and network congestion of the home gateway, an ECG compression algorithm is applied. System demonstration shows that the ECG signals and motion signals of the elderly can be monitored. Evaluation of the compression algorithm shows that it has a high compression ratio and low distortion and consumes little time, which is suitable for home gateways. The proposed system has good scalability, and it is simple to operate. It has the potential to provide long-term and continuous home health monitoring services for the elderly.

A Remote Health Monitoring System for the Elderly Based on Smart Home Gateway.

Science.gov (United States)

Guan, Kai; Shao, Minggang; Wu, Shuicai

2017-01-01

This paper proposed a remote health monitoring system for the elderly based on smart home gateway. The proposed system consists of three parts: the smart clothing, the smart home gateway, and the health care server. The smart clothing collects the elderly's electrocardiogram (ECG) and motion signals. The home gateway is used for data transmission. The health care server provides services of data storage and user information management; it is constructed on the Windows-Apache-MySQL-PHP (WAMP) platform and is tested on the Ali Cloud platform. To resolve the issues of data overload and network congestion of the home gateway, an ECG compression algorithm is applied. System demonstration shows that the ECG signals and motion signals of the elderly can be monitored. Evaluation of the compression algorithm shows that it has a high compression ratio and low distortion and consumes little time, which is suitable for home gateways. The proposed system has good scalability, and it is simple to operate. It has the potential to provide long-term and continuous home health monitoring services for the elderly.

A Remote Health Monitoring System for the Elderly Based on Smart Home Gateway

Science.gov (United States)

Shao, Minggang

2017-01-01

This paper proposed a remote health monitoring system for the elderly based on smart home gateway. The proposed system consists of three parts: the smart clothing, the smart home gateway, and the health care server. The smart clothing collects the elderly's electrocardiogram (ECG) and motion signals. The home gateway is used for data transmission. The health care server provides services of data storage and user information management; it is constructed on the Windows-Apache-MySQL-PHP (WAMP) platform and is tested on the Ali Cloud platform. To resolve the issues of data overload and network congestion of the home gateway, an ECG compression algorithm is applied. System demonstration shows that the ECG signals and motion signals of the elderly can be monitored. Evaluation of the compression algorithm shows that it has a high compression ratio and low distortion and consumes little time, which is suitable for home gateways. The proposed system has good scalability, and it is simple to operate. It has the potential to provide long-term and continuous home health monitoring services for the elderly. PMID:29204258

Performance evaluation of throughput computing workloads using multi-core processors and graphics processors

Science.gov (United States)

Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.

2017-11-01

Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.

GATEWAY Demonstrations: Long-Term Evaluation of SSL Field Performance in Select Interior Projects

Energy Technology Data Exchange (ETDEWEB)

Davis, Tess E. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Davis, Robert G. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Wilkerson, Andrea M. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

2017-02-28

The GATEWAY program evaluated the long-term performance characteristics (chromaticity change, maintained illuminance, and operations and maintenance) of LED lighting systems in four field installations previously documented in separate DOE GATEWAY reports.

The Molen Polymorphic Media Processor

NARCIS (Netherlands)

Kuzmanov, G.K.

2004-01-01

In this dissertation, we address high performance media processing based on a tightly coupled co-processor architectural paradigm. More specifically, we introduce a reconfigurable media augmentation of a general purpose processor and implement it into a fully operational processor prototype. The

Environmental Dataset Gateway (EDG) CS-W Interface

Data.gov (United States)

U.S. Environmental Protection Agency — Use the Environmental Dataset Gateway (EDG) to find and access EPA's environmental resources. Many options are available for easily reusing EDG content in other...

Design of an MSAT-X mobile transceiver and related base and gateway stations

Science.gov (United States)

Fang, Russell J. F.; Bhaskar, Udaya; Hemmati, Farhad; Mackenthun, Kenneth M.; Shenoy, Ajit

This paper summarizes the results of a design study of the mobile transceiver, base station, and gateway station for NASA's proposed Mobile Satellite Experiment (MSAT-X). Major ground segment system design issues such as frequency stability control, modulation method, linear predictive coding vocoder algorithm, and error control technique are addressed. The modular and flexible transceiver design is described in detail, including the core, RF/IF, modem, vocoder, forward error correction codec, amplitude-companded single sideband, and input/output modules, as well as the flexible interface. Designs for a three-carrier base station and a 10-carrier gateway station are also discussed, including the interface with the controllers and with the public-switched telephone networks at the gateway station. Functional specifications are given for the transceiver, the base station, and the gateway station.

Design of an MSAT-X mobile transceiver and related base and gateway stations

Science.gov (United States)

Fang, Russell J. F.; Bhaskar, Udaya; Hemmati, Farhad; Mackenthun, Kenneth M.; Shenoy, Ajit

1987-01-01

This paper summarizes the results of a design study of the mobile transceiver, base station, and gateway station for NASA's proposed Mobile Satellite Experiment (MSAT-X). Major ground segment system design issues such as frequency stability control, modulation method, linear predictive coding vocoder algorithm, and error control technique are addressed. The modular and flexible transceiver design is described in detail, including the core, RF/IF, modem, vocoder, forward error correction codec, amplitude-companded single sideband, and input/output modules, as well as the flexible interface. Designs for a three-carrier base station and a 10-carrier gateway station are also discussed, including the interface with the controllers and with the public-switched telephone networks at the gateway station. Functional specifications are given for the transceiver, the base station, and the gateway station.

Reflections on science gateways sustainability through the business model canvas: case study of a neuroscience gateway

NARCIS (Netherlands)

Shahand, S.; van Duffelen, J.; Olabarriaga, S. D.

2015-01-01

The sustainability of science gateways has been a topic of active discussion because they have been created and supported in the context of temporary research and infrastructure projects. As successful projects come to an end, it is necessary to find (new) models to secure continuous exploitation of

Access control mechanism of wireless gateway based on open flow

Science.gov (United States)

Peng, Rong; Ding, Lei

2017-08-01

In order to realize the access control of wireless gateway and improve the access control of wireless gateway devices, an access control mechanism of SDN architecture which is based on Open vSwitch is proposed. The mechanism utilizes the features of the controller--centralized control and programmable. Controller send access control flow table based on the business logic. Open vSwitch helps achieve a specific access control strategy based on the flow table.

Smart Meter (Gateways). Attacks and implementation of a cost effective security solution; Smart Meter (Gateways). Angriffe und Umsetzung einer kostenguenstigen Sicherheitsloesung

Energy Technology Data Exchange (ETDEWEB)

Krauss, Christoph [Fraunhofer Research Institution AISEC, Garching (Germany); Sigl, Georg [Technische Univ. Muenchen (Germany); Stumpf, Frederic

2012-07-01

Smart Meter (Gateways) are a central component of future Smart Grids and their secure operation must be ensured. In this paper, we first present several attacks on actual smart meter and gateway systems. Next, we describe a possible security solution which meets the requirements of the protection profile specified by the German Federal Office for Information Security (BIS) as far as possible with current available technology and includes additional security mechanisms. To realize a cost-efficient solution, we use off-the-shelf hardware for the mandatory Hardware Security Module (HSM) in form of a Trusted Platform Module (TPM). Finally, we give a brief overview on alternative approaches. (orig.)

JPP: A Java Pre-Processor

OpenAIRE

Kiniry, Joseph R.; Cheong, Elaine

1998-01-01

The Java Pre-Processor, or JPP for short, is a parsing pre-processor for the Java programming language. Unlike its namesake (the C/C++ Pre-Processor, cpp), JPP provides functionality above and beyond simple textual substitution. JPP's capabilities include code beautification, code standard conformance checking, class and interface specification and testing, and documentation generation.

Producing chopped firewood with firewood processors

International Nuclear Information System (INIS)

Kaerhae, K.; Jouhiaho, A.

2009-01-01

The TTS Institute's research and development project studied both the productivity of new, chopped firewood processors (cross-cutting and splitting machines) suitable for professional and independent small-scale production, and the costs of the chopped firewood produced. Seven chopped firewood processors were tested in the research, six of which were sawing processors and one shearing processor. The chopping work was carried out using wood feeding racks and a wood lifter. The work was also carried out without any feeding appliances. Altogether 132.5 solid m 3 of wood were chopped in the time studies. The firewood processor used had the most significant impact on chopping work productivity. In addition to the firewood processor, the stem mid-diameter, the length of the raw material, and of the firewood were also found to affect productivity. The wood feeding systems also affected productivity. If there is a feeding rack and hydraulic grapple loader available for use in chopping firewood, then it is worth using the wood feeding rack. A wood lifter is only worth using with the largest stems (over 20 cm mid-diameter) if a feeding rack cannot be used. When producing chopped firewood from small-diameter wood, i.e. with a mid-diameter less than 10 cm, the costs of chopping work were over 10 EUR solid m -3 with sawing firewood processors. The shearing firewood processor with a guillotine blade achieved a cost level of 5 EUR solid m -3 when the mid-diameter of the chopped stem was 10 cm. In addition to the raw material, the cost-efficient chopping work also requires several hundred annual operating hours with a firewood processor, which is difficult for individual firewood entrepreneurs to achieve. The operating hours of firewood processors can be increased to the required level by the joint use of the processors by a number of firewood entrepreneurs. (author)

Design and implementation of Skype USB user gateway software

Science.gov (United States)

Qi, Yang

2017-08-01

With the widespread application of VoIP, the client with private protocol becomes more and more popular. Skype is one of the representatives. How to connect Skype with PSTN just by Skype client has gradually become hot. This paper design and implement the software based on a kind of USB User Gateway. With the software Skype user can freely communicate with PSTN phone. FSM is designed as the core of the software, and Skype control is separated by the USB Gateway control. In this way, the communication becomes more flexible and efficient. In the actual user testing, the software obtains good results.

Design of a multimedia gateway for mobile devices

Science.gov (United States)

Hens, Raf; Goeminne, Nico; Van Hoecke, Sofie; Verdickt, Tom; Bouve, Thomas; Gielen, Frank; Demeester, Piet

2005-03-01

Although mobile users are currently offered a lot more capabilities on their mobile devices, they still experience some limitations. They can surf the Internet, read their e-mail and receive MMS messages, but they have limited processing power, storage capacity and bandwidth and are limited in their access to peripherals (e.g. printers). We have designed and implemented a multimedia gateway for mobile devices that reduces these limitations. It gives the mobile devices transparent access to high capacity devices connected to the gateway, which is built around a central, modularly extensible server that can run on any PC or home gateway. It manages two sets of modules: one set offering the actual services and another set handling the IP-based wireless interaction with the client applications on the mobile devices. These modules can be added and removed dynamically, offering new services on the fly. Currently services for storage, printing, domotics and playing music are provided. Others can easily be added later on. This paper discusses the architecture and development, the management of modules, the actual services and their benefits. Besides a proprietary implementation, it also looks into OSGi and how both platforms compare to each other, concerning design, architecture, ease of development, functionality, ...

Pengembangan SMS Gateway Layanan Informasi Akademik di STMIK GI MDP

Directory of Open Access Journals (Sweden)

Fransiska Prihatini Sihotang

2017-08-01

Full Text Available Information technology can be utilized in education such as e-Learning and Academic Information System. STMIK GI MDP has applied information technology that provides ease for the dissemination of academic information to students. However, the parents of the students have not obtained the academic information of their children due to the lack of internet-related knowledge. Therefore, this study aims to create a service that is able to convey information to parents directly with SMS Gateway service. This research begins with the collection of user needs through observation techniques and interviews to academic staff and parents. Then performed the required feature analysis. Then the design of SMS Gateway application that will be embedded in existing academic applications and coding system. Gammu is used as a link between applications with mobile phones. The result of this research is the application of SMS Gateway service that can give the student academic information to the parents.

Optical Associative Processors For Visual Perception"

Science.gov (United States)

Casasent, David; Telfer, Brian

1988-05-01

We consider various associative processor modifications required to allow these systems to be used for visual perception, scene analysis, and object recognition. For these applications, decisions on the class of the objects present in the input image are required and thus heteroassociative memories are necessary (rather than the autoassociative memories that have been given most attention). We analyze the performance of both associative processors and note that there is considerable difference between heteroassociative and autoassociative memories. We describe associative processors suitable for realizing functions such as: distortion invariance (using linear discriminant function memory synthesis techniques), noise and image processing performance (using autoassociative memories in cascade with with a heteroassociative processor and with a finite number of autoassociative memory iterations employed), shift invariance (achieved through the use of associative processors operating on feature space data), and the analysis of multiple objects in high noise (which is achieved using associative processing of the output from symbolic correlators). We detail and provide initial demonstrations of the use of associative processors operating on iconic, feature space and symbolic data, as well as adaptive associative processors.

AMD's 64-bit Opteron processor

CERN Multimedia

CERN. Geneva

2003-01-01

This talk concentrates on issues that relate to obtaining peak performance from the Opteron processor. Compiler options, memory layout, MPI issues in multi-processor configurations and the use of a NUMA kernel will be covered. A discussion of recent benchmarking projects and results will also be included.BiographiesDavid RichDavid directs AMD's efforts in high performance computing and also in the use of Opteron processors...

Composable processor virtualization for embedded systems

NARCIS (Netherlands)

Molnos, A.M.; Milutinovic, A.; She, D.; Goossens, K.G.W.

2010-01-01

Processor virtualization divides a physical processor's time among a set of virual machines, enabling efficient hardware utilization, application security and allowing co-existence of different operating systems on the same processor. Through initially intended for the server domain, virtualization

Middle Miocene paleoenvironmental crises in Central Eurasia caused by changes in marine gateway configuration

Science.gov (United States)

Palcu, D. V.; Golovina, L. A.; Vernyhorova, Y. V.; Popov, S. V.; Krijgsman, W.

2017-11-01

Marine gateways prove to be important factors for changes in the ecology and biochemistry of marginal seas. Changes in gateway configuration played a dominant role in the Middle Miocene paleogeographic evolution of the Paratethys Sea that covered Central Eurasia. Here, we focus on the connection between the Central (CP) and Eastern Paratethys (EP) to understand the paleoenvironmental changes caused by the evolution of this marine gateway. We first construct an integrated magneto-biostratigraphic framework for the late Langhian-Serravallian (Chokrakian-Karaganian-Konkian-Volhynian) sedimentary record of the eastern domain, which allows a correlation to the well-dated successions west of the gateway. The magneto-biostratigraphic results from the Zelensky-Panagia section on the Black Sea coast of Russia show that the Chokrakian/Karaganian boundary has an age of 13.8 Ma, the Karaganian/Konkian boundary is dated at 13.4 Ma, and the Konkian/Volhynian boundary at 12.65 Ma. We identify three major phases on gateway functioning that are reflected in specific environmental changes. During the Karaganian, the EP turned into a lake-sea that supplied a unidirectional flow of low-salinity waters to the west, where the CP sea experienced its Badenian Salinity Crisis. This configuration is remarkably similar to the Mediterranean during its Messinian Salinity Crisis. The second phase is marked by a marine transgression from the west, reinstalling open-marine conditions in the CP and causing marine incursions in the EP during the Konkian. The Volhynian is characterized by a new gateway configuration that allows exchange between CP and EP, creating unified conditions all over the Paratethys. We hypothesize that a density driven pumping mechanism is triggered by the increase in connectivity at the Konkian/Volhynian boundary, which simultaneously caused major paleoenvironmental changes at both sides of the gateway and led to the Badenian-Sarmatian extinction event in the CP.

Deterministic chaos in the processor load

International Nuclear Information System (INIS)

Halbiniak, Zbigniew; Jozwiak, Ireneusz J.

2007-01-01

In this article we present the results of research whose purpose was to identify the phenomenon of deterministic chaos in the processor load. We analysed the time series of the processor load during efficiency tests of database software. Our research was done on a Sparc Alpha processor working on the UNIX Sun Solaris 5.7 operating system. The conducted analyses proved the presence of the deterministic chaos phenomenon in the processor load in this particular case

Advanced distributed simulation technology: Digital Voice Gateway Reference Guide

Science.gov (United States)

Vanhook, Dan; Stadler, Ed

1994-01-01

The Digital Voice Gateway (referred to as the 'DVG' in this document) transmits and receives four full duplex encoded speech channels over the Ethernet. The information in this document applies only to DVG's running firmware of the version listed on the title page. This document, previously named Digital Voice Gateway Reference Guide, BBN Systems and Technologies Corporation, Cambridge, MA 02138, was revised for revision 2.00. This new revision changes the network protocol used by the DVG, to comply with the SINCGARS radio simulation (For SIMNET 6.6.1). Because of the extensive changes to revision 2.00 a separate document was created rather than supplying change pages.

Dust Measurements Onboard the Deep Space Gateway

Science.gov (United States)

Horanyi, M.; Kempf, S.; Malaspina, D.; Poppe, A.; Srama, R.; Sternovsky, Z.; Szalay, J.

2018-02-01

A dust instrument onboard the Deep Space Gateway will revolutionize our understanding of the dust environment at 1 AU, help our understanding of the evolution of the solar system, and improve dust hazard models for the safety of crewed and robotic missions.

BASSET: Scalable Gateway Finder in Large Graphs

Energy Technology Data Exchange (ETDEWEB)

Tong, H; Papadimitriou, S; Faloutsos, C; Yu, P S; Eliassi-Rad, T

2010-11-03

Given a social network, who is the best person to introduce you to, say, Chris Ferguson, the poker champion? Or, given a network of people and skills, who is the best person to help you learn about, say, wavelets? The goal is to find a small group of 'gateways': persons who are close enough to us, as well as close enough to the target (person, or skill) or, in other words, are crucial in connecting us to the target. The main contributions are the following: (a) we show how to formulate this problem precisely; (b) we show that it is sub-modular and thus it can be solved near-optimally; (c) we give fast, scalable algorithms to find such gateways. Experiments on real data sets validate the effectiveness and efficiency of the proposed methods, achieving up to 6,000,000x speedup.

A Smart Gateway Architecture for Improving Efficiency of Home Network Applications

OpenAIRE

Ding, Fei; Song, Aiguo; Tong, En; Li, Jianqing

2016-01-01

A smart home gateway plays an important role in the Internet of Things (IoT) system that takes responsibility for the connection between the network layer and the ubiquitous sensor network (USN) layer. Even though the home network application is developing rapidly, researches on the home gateway based open development architecture are less. This makes it difficult to extend the home network to support new applications, share service, and interoperate with other home network systems. An integr...

Neurovision processor for designing intelligent sensors

Science.gov (United States)

Gupta, Madan M.; Knopf, George K.

1992-03-01

A programmable multi-task neuro-vision processor, called the Positive-Negative (PN) neural processor, is proposed as a plausible hardware mechanism for constructing robust multi-task vision sensors. The computational operations performed by the PN neural processor are loosely based on the neural activity fields exhibited by certain nervous tissue layers situated in the brain. The neuro-vision processor can be programmed to generate diverse dynamic behavior that may be used for spatio-temporal stabilization (STS), short-term visual memory (STVM), spatio-temporal filtering (STF) and pulse frequency modulation (PFM). A multi- functional vision sensor that performs a variety of information processing operations on time- varying two-dimensional sensory images can be constructed from a parallel and hierarchical structure of numerous individually programmed PN neural processors.

VIRTUS: a multi-processor system in FASTBUS

International Nuclear Information System (INIS)

Ellett, J.; Jackson, R.; Ritter, R.; Schlein, P.; Yaeger, D.; Zweizig, J.

1986-01-01

VIRTUS is a system of parallel MC68000-based processors interconnected by FASTBUS that is used either on-line as an intelligent trigger component or off-line for full event processing. Each processor receives the complete set of data from one event. The host computer, a VAX 11/780, down-line loads all software to the processors, controls and monitors the functioning of all processors, and writes processed data to tape. Instructions, programs, and data are transferred among the processors and the host in the form of fixed format, variable length data blocks. (Auth.)

Eocene cooling linked to early flow across the Tasmanian Gateway.

Science.gov (United States)

Bijl, Peter K; Bendle, James A P; Bohaty, Steven M; Pross, Jörg; Schouten, Stefan; Tauxe, Lisa; Stickley, Catherine E; McKay, Robert M; Röhl, Ursula; Olney, Matthew; Sluijs, Appy; Escutia, Carlota; Brinkhuis, Henk

2013-06-11

The warmest global temperatures of the past 85 million years occurred during a prolonged greenhouse episode known as the Early Eocene Climatic Optimum (52-50 Ma). The Early Eocene Climatic Optimum terminated with a long-term cooling trend that culminated in continental-scale glaciation of Antarctica from 34 Ma onward. Whereas early studies attributed the Eocene transition from greenhouse to icehouse climates to the tectonic opening of Southern Ocean gateways, more recent investigations invoked a dominant role of declining atmospheric greenhouse gas concentrations (e.g., CO2). However, the scarcity of field data has prevented empirical evaluation of these hypotheses. We present marine microfossil and organic geochemical records spanning the early-to-middle Eocene transition from the Wilkes Land Margin, East Antarctica. Dinoflagellate biogeography and sea surface temperature paleothermometry reveal that the earliest throughflow of a westbound Antarctic Counter Current began ~49-50 Ma through a southern opening of the Tasmanian Gateway. This early opening occurs in conjunction with the simultaneous onset of regional surface water and continental cooling (2-4 °C), evidenced by biomarker- and pollen-based paleothermometry. We interpret that the westbound flowing current flow across the Tasmanian Gateway resulted in cooling of Antarctic surface waters and coasts, which was conveyed to global intermediate waters through invigorated deep convection in southern high latitudes. Although atmospheric CO2 forcing alone would provide a more uniform middle Eocene cooling, the opening of the Tasmanian Gateway better explains Southern Ocean surface water and global deep ocean cooling in the apparent absence of (sub-) equatorial cooling.

A lock circuit for a multi-core processor

DEFF Research Database (Denmark)

2015-01-01

An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores...... that are enqueued in the queue register. Furthermore, the integrated circuit comprises a current register and a selector circuit configured to select a processor core and identify that processor core by a value in the current register. A selected processor core is a prioritized processor core among the cores...... configured with an integrated circuit; and a silicon die configured with an integrated circuit....

RESTful M2M Gateway for Remote Wireless Monitoring for District Central Heating Networks

Directory of Open Access Journals (Sweden)

Bo Cheng

2014-11-01

Full Text Available In recent years, the increased interest in energy conservation and environmental protection, combined with the development of modern communication and computer technology, has resulted in the replacement of distributed heating by central heating in urban areas. This paper proposes a Representational State Transfer (REST Machine-to-Machine (M2M gateway for wireless remote monitoring for a district central heating network. In particular, we focus on the resource-oriented RESTful M2M gateway architecture, and present an uniform devices abstraction approach based on Open Service Gateway Initiative (OSGi technology, and implement the resource mapping mechanism between resource address mapping mechanism between RESTful resources and the physical sensor devices, and present the buffer queue combined with polling method to implement the data scheduling and Quality of Service (QoS guarantee, and also give the RESTful M2M gateway open service Application Programming Interface (API set. The performance has been measured and analyzed. Finally, the conclusions and future work are presented.

Sistem Informasi Penjualan dan Pemesanan Layanan Berbasis Web dan SMS Gateway di Petshop "PetZone"

Directory of Open Access Journals (Sweden)

Siska Fadhilah Wati

2013-09-01

Full Text Available Dewasa ini teknologi informasi sangat membantu dalam dunia bisnis. Kemudahan yang ditawarkan akan menjaring lebih banyak konsumen. Namun, perusahan tingkat menengah seperti PetZone saat ini masih jarang yang menawarkan kemudahan berbelanja atau pemesanan layanan secara online. Oleh karena itu diperlukan sebuah sistem berbasis web di perusahaan PetZone yang dapat memudahkan pemilik dan karyawan dalam apenjualan, pelayanan, dan pemasaran, serta memudahkan pelanggan dalam jual-beli barang dan jasa. Atas dasar masalah tersebut dibangun Sistem Informasi Penjualan dan Pemesanan Layanan Berbasis Web dan SMS Gateway untuk menunjang proses bisnis yang ada. Sistem informasi dibangun menggunakan bahasa pemrograman PHP framework Codeigniter, javascript untuk tampilan yang dinamis, dan database MySQL. Proses pembuatan dan pengembangan Sistem Informasi Penjualan ini menggunakan metode air terjun. Metode air terjun meliputi kebutuhan pengguna, analisis, rancangan, implementasi dan pengujian. Pemodelan Sistem Informasi yang dibangun menggunakan metode berorientasi objek UML (Unified Modeling Language yang terdiri dari Use case  diagram, Class diagram dan Sequence diagram. Hasil pengujian Sistem Informasi Penjualan dan Pemesanan Layanan Berbasis Web dan SMS Gateway menunjukkan bahwa semua fitur yang terdapat baik dalam sistem informasi maupun SMS gateway dapat bekerja dengan baikdengan ratusan sample data, dan server SMS gateway dapat memproses lebih dari satu SMS secara bersamaan. Dalam perkembangan ke depannya nanti, Sistem Informasi Penjualan dan Pemesanan Layanan Berbasis Web dan SMS Gateway masih dapat dikembangkan lagi dengan menambah fitur-fitur pada SMS gateway sehingga lebih memudahkan konsumen.

Sensitometric control of roentgen film processors

International Nuclear Information System (INIS)

Forsberg, H.; Karolinska Sjukhuset, Stockholm

1987-01-01

Monitoring of film processors performance is essential since image quality, patient dose and costs are influenced by the performance. A system for sensitometric constancy control of film processors and their associated components is described. Experience with the system for 3 years is given when implemented on 17 film processors. Modern high quality film processors have a stability that makes a test frequency of once a week sufficient to maintain adequate image quality. The test system is so sensitive that corrective actions almost invariably have been taken before any technical problem degraded the image quality to a visible degree. (orig.)

A Standard-Based and Context-Aware Architecture for Personal Healthcare Smart Gateways.

Science.gov (United States)

Santos, Danilo F S; Gorgônio, Kyller C; Perkusich, Angelo; Almeida, Hyggo O

2016-10-01

The rising availability of Personal Health Devices (PHDs) capable of Personal Network Area (PAN) communication and the desire of keeping a high quality of life are the ingredients of the Connected Health vision. In parallel, a growing number of personal and portable devices, like smartphones and tablet computers, are becoming capable of taking the role of health gateway, that is, a data collector for the sensor PHDs. However, as the number of PHDs increase, the number of other peripherals connected in PAN also increases. Therefore, PHDs are now competing for medium access with other devices, decreasing the Quality of Service (QoS) of health applications in the PAN. In this article we present a reference architecture to prioritize PHD connections based on their state and requirements, creating a healthcare Smart Gateway. Healthcare context information is extracted by observing the traffic through the gateway. A standard-based approach was used to identify health traffic based on ISO/IEEE 11073 family of standards. A reference implementation was developed showing the relevance of the problem and how the proposed architecture can assist in the prioritization. The reference Smart Gateway solution was integrated with a Connected Health System for the Internet of Things, validating its use in a real case scenario.

Special purpose processors for high energy physics applications

International Nuclear Information System (INIS)

Verkerk, C.

1978-01-01

The review on the subject of hardware processors from very fast decision logic for the split field magnet facility at CERN, to a point-finding processor used to relieve the data-acquisition minicomputer from the task of monitoring the SPS experiment is given. Block diagrams of decision making processor, point-finding processor, complanarity and opening angle processor and programmable track selector module are presented and discussed. The applications of fully programmable but slower processor on the one hand, and very fast and programmable decision logic on the other hand are given in this review

The Central Trigger Processor (CTP)

CERN Multimedia

Franchini, Matteo

2016-01-01

The Central Trigger Processor (CTP) receives trigger information from the calorimeter and muon trigger processors, as well as from other sources of trigger. It makes the Level-1 decision (L1A) based on a trigger menu.

Very Long Instruction Word Processors

Indian Academy of Sciences (India)

Pentium Processor have modified the processor architecture to exploit parallelism in a program. .... The type of operation itself is encoded using 14 bits. .... text of designing simple architectures with low power consump- tion and execute x86 ...

The virtual library: Coming of age

Science.gov (United States)

Hunter, Judy F.; Cotter, Gladys A.

1994-01-01

With the high speed networking capabilities, multiple media options, and massive amounts of information that exist in electronic format today, the concept of a 'virtual' library or 'library without walls' is becoming viable. In virtual library environment, the information processed goes beyond the traditional definition of documents to include the results of scientific and technical research and development (reports, software, data) recorded in any format or media: electronic, audio, video, or scanned images. Network access to information must include tools to help locate information sources and navigate the networks to connect to the sources, as well as methods to extract the relevant information. Graphical User Interfaces (GUI's) that are intuitive and navigational tools such as Intelligent Gateway Processors (IGP) will provide users with seamless and transparent use of high speed networks to access, organize, and manage information. Traditional libraries will become points of electronic access to information on multiple medias. The emphasis will be towards unique collections of information at each library rather than entire collections at every library. It is no longer a question of whether there is enough information available; it is more a question of how to manage the vast volumes of information. The future equation will involve being able to organize knowledge, manage information, and provide access at the point of origin.

Software Defined Radio (SDR) Overlay Node Gateway, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — This proposal details a novel mobile data transceiver solution that supports standalone wireless sensors and concurrently acts as a gateway between multiple sensor...

Experimental testing of the noise-canceling processor.

Science.gov (United States)

Collins, Michael D; Baer, Ralph N; Simpson, Harry J

2011-09-01

Signal-processing techniques for localizing an acoustic source buried in noise are tested in a tank experiment. Noise is generated using a discrete source, a bubble generator, and a sprinkler. The experiment has essential elements of a realistic scenario in matched-field processing, including complex source and noise time series in a waveguide with water, sediment, and multipath propagation. The noise-canceling processor is found to outperform the Bartlett processor and provide the correct source range for signal-to-noise ratios below -10 dB. The multivalued Bartlett processor is found to outperform the Bartlett processor but not the noise-canceling processor. © 2011 Acoustical Society of America

WorldWideScience.org: the global science gateway.

Science.gov (United States)

Fitzpatrick, Roberta Bronson

2009-10-01

WorldWideScience.org is a Web-based global gateway connecting users to both national and international scientific databases and portals. This column will provide background information on the resource as well as introduce basic searching practices for users.

GATEWAY Report Brief: OLED Lighting in the Offices of Aurora Lighting Design, Inc.

Energy Technology Data Exchange (ETDEWEB)

None, None

2016-05-31

Summary of a GATEWAY report evaluation at the offices of Aurora Lighting Design, Inc., in Grayslake, IL, where the GATEWAY program conducted its first investigation involving OLED lighting. The project experienced several challenges, but also highlighted a number of promising attributes – which indicate that with continued improvements in efficacy, longevity, size, and flexibility, OLEDs could provide a new tool for creative and effective lighting.

Development of a highly reliable CRT processor

International Nuclear Information System (INIS)

Shimizu, Tomoya; Saiki, Akira; Hirai, Kenji; Jota, Masayoshi; Fujii, Mikiya

1996-01-01

Although CRT processors have been employed by the main control board to reduce the operator's workload during monitoring, the control systems are still operated by hardware switches. For further advancement, direct controller operation through a display device is expected. A CRT processor providing direct controller operation must be as reliable as the hardware switches are. The authors are developing a new type of highly reliable CRT processor that enables direct controller operations. In this paper, we discuss the design principles behind a highly reliable CRT processor. The principles are defined by studies of software reliability and of the functional reliability of the monitoring and operation systems. The functional configuration of an advanced CRT processor is also addressed. (author)

Computer Generated Inputs for NMIS Processor Verification

International Nuclear Information System (INIS)

J. A. Mullens; J. E. Breeding; J. A. McEvers; R. W. Wysor; L. G. Chiang; J. R. Lenarduzzi; J. T. Mihalczo; J. K. Mattingly

2001-01-01

Proper operation of the Nuclear Identification Materials System (NMIS) processor can be verified using computer-generated inputs [BIST (Built-In-Self-Test)] at the digital inputs. Preselected sequences of input pulses to all channels with known correlation functions are compared to the output of the processor. These types of verifications have been utilized in NMIS type correlation processors at the Oak Ridge National Laboratory since 1984. The use of this test confirmed a malfunction in a NMIS processor at the All-Russian Scientific Research Institute of Experimental Physics (VNIIEF) in 1998. The NMIS processor boards were returned to the U.S. for repair and subsequently used in NMIS passive and active measurements with Pu at VNIIEF in 1999

3081//sub E/ processor

International Nuclear Information System (INIS)

Kunz, P.F.; Gravina, M.; Oxoby, G.; Trang, Q.; Fucci, A.; Jacobs, D.; Martin, B.; Storr, K.

1983-03-01

Since the introduction of the 168//sub E/, emulating processors have been successful over an amazingly wide range of applications. This paper will describe a second generation processor, the 3081//sub E/. This new processor, which is being developed as a collaboration between SLAC and CERN, goes beyond just fixing the obvious faults of the 168//sub E/. Not only will the 3081//sub E/ have much more memory space, incorporate many more IBM instructions, and have much more memory space, incorporate many more IBM instructions, and have full double precision floating point arithmetic, but it will also have faster execution times and be much simpler to build, debug, and maintain. The simple interface and reasonable cost of the 168//sub E/ will be maintained for the 3081//sub E/

Multimode power processor

Science.gov (United States)

O'Sullivan, George A.; O'Sullivan, Joseph A.

1999-01-01

In one embodiment, a power processor which operates in three modes: an inverter mode wherein power is delivered from a battery to an AC power grid or load; a battery charger mode wherein the battery is charged by a generator; and a parallel mode wherein the generator supplies power to the AC power grid or load in parallel with the battery. In the parallel mode, the system adapts to arbitrary non-linear loads. The power processor may operate on a per-phase basis wherein the load may be synthetically transferred from one phase to another by way of a bumpless transfer which causes no interruption of power to the load when transferring energy sources. Voltage transients and frequency transients delivered to the load when switching between the generator and battery sources are minimized, thereby providing an uninterruptible power supply. The power processor may be used as part of a hybrid electrical power source system which may contain, in one embodiment, a photovoltaic array, diesel engine, and battery power sources.

PixonVision real-time video processor

Science.gov (United States)

Puetter, R. C.; Hier, R. G.

2007-09-01

PixonImaging LLC and DigiVision, Inc. have developed a real-time video processor, the PixonVision PV-200, based on the patented Pixon method for image deblurring and denoising, and DigiVision's spatially adaptive contrast enhancement processor, the DV1000. The PV-200 can process NTSC and PAL video in real time with a latency of 1 field (1/60 th of a second), remove the effects of aerosol scattering from haze, mist, smoke, and dust, improve spatial resolution by up to 2x, decrease noise by up to 6x, and increase local contrast by up to 8x. A newer version of the processor, the PV-300, is now in prototype form and can handle high definition video. Both the PV-200 and PV-300 are FPGA-based processors, which could be spun into ASICs if desired. Obvious applications of these processors include applications in the DOD (tanks, aircraft, and ships), homeland security, intelligence, surveillance, and law enforcement. If developed into an ASIC, these processors will be suitable for a variety of portable applications, including gun sights, night vision goggles, binoculars, and guided munitions. This paper presents a variety of examples of PV-200 processing, including examples appropriate to border security, battlefield applications, port security, and surveillance from unmanned aerial vehicles.

ATLAS TDAQ application gateway upgrade during LS1

CERN Document Server

KOROL, A; The ATLAS collaboration; BOGDANCHIKOV, A; BRASOLIN, F; CONTESCU, A C; DUBROV, S; HAFEEZ, M; LEE, C J; SCANNICCHIO, D A; TWOMEY, M; VORONKOV, A; ZAYTSEV, A

2014-01-01

The ATLAS Gateway service is implemented with a set of dedicated computer nodes to provide a fine-grained access control between CERN General Public Network (GPN) and ATLAS Technical Control Network (ATCN). ATCN connects the ATLAS online farm used for ATLAS Operations and data taking, including the ATLAS TDAQ (Trigger and Data Aquisition) and DCS (Detector Control System) nodes. In particular, it provides restricted access to the web services (proxy), general login sessions (via SSH and RDP protocols), NAT and mail relay from ATCN. At the Operating System level the implementation is based on virtualization technologies. Here we report on the Gateway upgrade during Long Shutdown 1 (LS1) period: it includes the transition to the last production release of the CERN Linux distribution (SLC6), the migration to the centralized configuration management system (based on Puppet) and the redesign of the internal system architecture.

Processors and systems (picture processing)

Energy Technology Data Exchange (ETDEWEB)

Gemmar, P

1983-01-01

Automatic picture processing requires high performance computers and high transmission capacities in the processor units. The author examines the possibilities of operating processors in parallel in order to accelerate the processing of pictures. He therefore discusses a number of available processors and systems for picture processing and illustrates their capacities for special types of picture processing. He stresses the fact that the amount of storage required for picture processing is exceptionally high. The author concludes that it is as yet difficult to decide whether very large groups of simple processors or highly complex multiprocessor systems will provide the best solution. Both methods will be aided by the development of VLSI. New solutions have already been offered (systolic arrays and 3-d processing structures) but they also are subject to losses caused by inherently parallel algorithms. Greater efforts must be made to produce suitable software for multiprocessor systems. Some possibilities for future picture processing systems are discussed. 33 references.

Special processor for in-core control systems

International Nuclear Information System (INIS)

Golovanov, M.N.; Duma, V.R.; Levin, G.L.; Mel'nikov, A.V.; Polikanin, A.V.; Filatov, V.P.

1978-01-01

The BUTs-20 special processor is discussed, designed to control the units of the in-core control equipment which are incorporated into the VECTOR communication channel, and to provide preliminary data processing prior to computer calculations. A set of instructions and flowsheet of the processor, organization of its communication with memories and other units of the system are given. The processor components: a control unit and an arithmetic logical unit are discussed. It is noted that the special processor permits more effective utilization of the computer time

Enabling South-Africa: development of an intelligent gateway

CSIR Research Space (South Africa)

Evans, ED

1993-08-01

Full Text Available are catered for on all host protocols. The resulting gateway is operated on a sound business footing for the benefit of end-users and expert searchers in Southern Africa. The development of the system and the business are described in the paper....

Gateway to Careers. Postsecondary VSO Hones Workplace Skills.

Science.gov (United States)

Vernezze, Michael; Henkel, Marjorie

1993-01-01

The Gateway Marketing and Management Association is a local chapter of Delta Epsilon Chi, the postsecondary affiliate of Distributive Education Clubs of America. This vocational student organization provides leadership training and marketing skill development to prepare students for competition at state and national levels. (JOW)

System Design for Telecommunication Gateways

CERN Document Server

Bachmutsky, Alexander

2010-01-01

System Design for Telecommunication Gateways provides a thorough review of designing telecommunication network equipment based on the latest hardware designs and software methods available on the market. Focusing on high-end efficient designs that challenge all aspects of the system architecture, this book helps readers to understand a broader view of the system design, analyze all its most critical components, and select the parts that best fit a particular application. In many cases new technology trends, potential future developments, system flexibility and capability extensions are outline

The home gateway used in FTTH which can implement triple play

Science.gov (United States)

Ji, Wei; Yang, Hongliang; Liu, Yang; Liu, Yonghui; Cui, Wei

2008-11-01

The paper proposes the design of Home Gateway used in FTTH. On the customer's side, the Home Gateway finishes the optical signal receiving, provides three kinds of interfaces for the video, voice data, and attains the integration of the three services. PAS6301 chip achieves the control of voice, video and data services. Especially on the aspect of the video services, the HG system combines the advantages of IPTV and the DVB to offer a platform for receiving two signals. Users can use ordinary TV to receive both digital TV programs encoded by MPEG-2 and IPTV programs encoded by H.264.

Functional Verification of Enhanced RISC Processor

OpenAIRE

SHANKER NILANGI; SOWMYA L

2013-01-01

This paper presents design and verification of a 32-bit enhanced RISC processor core having floating point computations integrated within the core, has been designed to reduce the cost and complexity. The designed 3 stage pipelined 32-bit RISC processor is based on the ARM7 processor architecture with single precision floating point multiplier, floating point adder/subtractor for floating point operations and 32 x 32 booths multiplier added to the integer core of ARM7. The binary representati...

Effect of processor temperature on film dosimetry

International Nuclear Information System (INIS)

Srivastava, Shiv P.; Das, Indra J.

2012-01-01

Optical density (OD) of a radiographic film plays an important role in radiation dosimetry, which depends on various parameters, including beam energy, depth, field size, film batch, dose, dose rate, air film interface, postexposure processing time, and temperature of the processor. Most of these parameters have been studied for Kodak XV and extended dose range (EDR) films used in radiation oncology. There is very limited information on processor temperature, which is investigated in this study. Multiple XV and EDR films were exposed in the reference condition (d max. , 10 × 10 cm 2 , 100 cm) to a given dose. An automatic film processor (X-Omat 5000) was used for processing films. The temperature of the processor was adjusted manually with increasing temperature. At each temperature, a set of films was processed to evaluate OD at a given dose. For both films, OD is a linear function of processor temperature in the range of 29.4–40.6°C (85–105°F) for various dose ranges. The changes in processor temperature are directly related to the dose by a quadratic function. A simple linear equation is provided for the changes in OD vs. processor temperature, which could be used for correcting dose in radiation dosimetry when film is used.

SET: Session Layer-Assisted Efficient TCP Management Architecture for 6LoWPAN with Multiple Gateways

Directory of Open Access Journals (Sweden)

Akbar AliHammad

2010-01-01

Full Text Available 6LoWPAN (IPv6 based Low-Power Personal Area Network is a protocol specification that facilitates communication of IPv6 packets on top of IEEE 802.15.4 so that Internet and wireless sensor networks can be inter-connected. This interconnection is especially required in commercial and enterprise applications of sensor networks where reliable and timely data transfers such as multiple code updates are needed from Internet nodes to sensor nodes. For this type of inbound traffic which is mostly bulk, TCP as transport layer protocol is essential, resulting in end-to-end TCP session through a default gateway. In this scenario, a single gateway tends to become the bottleneck because of non-uniform connectivity to all the sensor nodes besides being vulnerable to buffer overflow. We propose SET; a management architecture for multiple split-TCP sessions across a number of serving gateways. SET implements striping and multiple TCP session management through a shim at session layer. Through analytical modeling and ns2 simulations, we show that our proposed architecture optimizes communication for ingress bulk data transfer while providing associated load balancing services. We conclude that multiple split-TCP sessions managed in parallel across a number of gateways result in reduced latency for bulk data transfer and provide robustness against gateway failures.

Bank switched memory interface for an image processor

International Nuclear Information System (INIS)

Barron, M.; Downward, J.

1980-09-01

A commercially available image processor is interfaced to a PDP-11/45 through an 8K window of memory addresses. When the image processor was not in use it was desired to be able to use the 8K address space as real memory. The standard method of accomplishing this would have been to use UNIBUS switches to switch in either the physical 8K bank of memory or the image processor memory. This method has the disadvantage of being rather expensive. As a simple alternative, a device was built to selectively enable or disable either an 8K bank of memory or the image processor memory. To enable the image processor under program control, GEN is contracted in size, the memory is disabled, a device partition for the image processor is created above GEN, and the image processor memory is enabled. The process is reversed to restore memory to GEN. The hardware to enable/disable the image and computer memories is controlled using spare bits from a DR-11K output register. The image processor and physical memory can be switched in or out on line with no adverse affects on the system's operation

Starshade Assembly Enabled by the Deep Space Gateway Architecture

Science.gov (United States)

Grunsfeld, J. M.; Siegler, N.; Mukherjee, R.

2018-02-01

A starshade is a large external coronagraph which will allow the direct imaging and analysis of planets around nearby stars. We present how the Deep Space Gateway would enable the robotic/astronaut construction of a starshade.

VON WISPR Family Processors: Volume 1

National Research Council Canada - National Science Library

Wagstaff, Ronald

1997-01-01

...) and the background noise they are embedded in. Processors utilizing those fluctuations such as the von WISPR Family Processors discussed herein, are methods or algorithms that preferentially attenuate the fluctuating signals and noise...

Many - body simulations using an array processor

International Nuclear Information System (INIS)

Rapaport, D.C.

1985-01-01

Simulations of microscopic models of water and polypeptides using molecular dynamics and Monte Carlo techniques have been carried out with the aid of an FPS array processor. The computational techniques are discussed, with emphasis on the development and optimization of the software to take account of the special features of the processor. The computing requirements of these simulations exceed what could be reasonably carried out on a normal 'scientific' computer. While the FPS processor is highly suited to the kinds of models described, several other computationally intensive problems in statistical mechanics are outlined for which alternative processor architectures are more appropriate

Multi-processor network implementations in Multibus II and VME

International Nuclear Information System (INIS)

Briegel, C.

1992-01-01

ACNET (Fermilab Accelerator Controls Network), a proprietary network protocol, is implemented in a multi-processor configuration for both Multibus II and VME. The implementations are contrasted by the bus protocol and software design goals. The Multibus II implementation provides for multiple processors running a duplicate set of tasks on each processor. For a network connected task, messages are distributed by a network round-robin scheduler. Further, messages can be stopped, continued, or re-routed for each task by user-callable commands. The VME implementation provides for multiple processors running one task across all processors. The process can either be fixed to a particular processor or dynamically allocated to an available processor depending on the scheduling algorithm of the multi-processing operating system. (author)

All gates lead to smoking: the 'gateway theory', e-cigarettes and the remaking of nicotine.

Science.gov (United States)

Bell, Kirsten; Keane, Helen

2014-10-01

The idea that drug use in 'softer' forms leads to 'harder' drug use lies at the heart of the gateway theory, one of the most influential models of drug use of the twentieth century. Although hotly contested, the notion of the 'gateway drug' continues to rear its head in discussions of drug use--most recently in the context of electronic cigarettes. Based on a critical reading of a range of texts, including scholarly literature and media reports, we explore the history and gestation of the gateway theory, highlighting the ways in which intersections between academic, media and popular accounts actively produced the concept. Arguing that the theory has been critical in maintaining the distinction between 'soft' and 'hard' drugs, we turn to its distinctive iteration in the context of debates about e-cigarettes. We show that the notion of the 'gateway' has been transformed from a descriptive to a predictive model, one in which nicotine is constituted as simultaneously 'soft' and 'hard'--as both relatively innocuous and incontrovertibly harmful. Copyright © 2014 Elsevier Ltd. All rights reserved.

Network Gateway Technology: The Issue of Redundancy towards ...

African Journals Online (AJOL)

Everyone connected to the Internet is concerned about two basic things: the availability of network services and the speed of the network. Network gateway redundancy technology falls within these categories and happens to be one of the newest technologies which only few companies, such as mobile companies and ...

Competitive Swarm Optimizer Based Gateway Deployment Algorithm in Cyber-Physical Systems.

Science.gov (United States)

Huang, Shuqiang; Tao, Ming

2017-01-22

Wireless sensor network topology optimization is a highly important issue, and topology control through node selection can improve the efficiency of data forwarding, while saving energy and prolonging lifetime of the network. To address the problem of connecting a wireless sensor network to the Internet in cyber-physical systems, here we propose a geometric gateway deployment based on a competitive swarm optimizer algorithm. The particle swarm optimization (PSO) algorithm has a continuous search feature in the solution space, which makes it suitable for finding the geometric center of gateway deployment; however, its search mechanism is limited to the individual optimum (pbest) and the population optimum (gbest); thus, it easily falls into local optima. In order to improve the particle search mechanism and enhance the search efficiency of the algorithm, we introduce a new competitive swarm optimizer (CSO) algorithm. The CSO search algorithm is based on an inter-particle competition mechanism and can effectively avoid trapping of the population falling into a local optimum. With the improvement of an adaptive opposition-based search and its ability to dynamically parameter adjustments, this algorithm can maintain the diversity of the entire swarm to solve geometric K -center gateway deployment problems. The simulation results show that this CSO algorithm has a good global explorative ability as well as convergence speed and can improve the network quality of service (QoS) level of cyber-physical systems by obtaining a minimum network coverage radius. We also find that the CSO algorithm is more stable, robust and effective in solving the problem of geometric gateway deployment as compared to the PSO or Kmedoids algorithms.

Competitive Swarm Optimizer Based Gateway Deployment Algorithm in Cyber-Physical Systems

Directory of Open Access Journals (Sweden)

Shuqiang Huang

2017-01-01

Full Text Available Wireless sensor network topology optimization is a highly important issue, and topology control through node selection can improve the efficiency of data forwarding, while saving energy and prolonging lifetime of the network. To address the problem of connecting a wireless sensor network to the Internet in cyber-physical systems, here we propose a geometric gateway deployment based on a competitive swarm optimizer algorithm. The particle swarm optimization (PSO algorithm has a continuous search feature in the solution space, which makes it suitable for finding the geometric center of gateway deployment; however, its search mechanism is limited to the individual optimum (pbest and the population optimum (gbest; thus, it easily falls into local optima. In order to improve the particle search mechanism and enhance the search efficiency of the algorithm, we introduce a new competitive swarm optimizer (CSO algorithm. The CSO search algorithm is based on an inter-particle competition mechanism and can effectively avoid trapping of the population falling into a local optimum. With the improvement of an adaptive opposition-based search and its ability to dynamically parameter adjustments, this algorithm can maintain the diversity of the entire swarm to solve geometric K-center gateway deployment problems. The simulation results show that this CSO algorithm has a good global explorative ability as well as convergence speed and can improve the network quality of service (QoS level of cyber-physical systems by obtaining a minimum network coverage radius. We also find that the CSO algorithm is more stable, robust and effective in solving the problem of geometric gateway deployment as compared to the PSO or Kmedoids algorithms.

Competitive Swarm Optimizer Based Gateway Deployment Algorithm in Cyber-Physical Systems

Science.gov (United States)

Huang, Shuqiang; Tao, Ming

2017-01-01

Wireless sensor network topology optimization is a highly important issue, and topology control through node selection can improve the efficiency of data forwarding, while saving energy and prolonging lifetime of the network. To address the problem of connecting a wireless sensor network to the Internet in cyber-physical systems, here we propose a geometric gateway deployment based on a competitive swarm optimizer algorithm. The particle swarm optimization (PSO) algorithm has a continuous search feature in the solution space, which makes it suitable for finding the geometric center of gateway deployment; however, its search mechanism is limited to the individual optimum (pbest) and the population optimum (gbest); thus, it easily falls into local optima. In order to improve the particle search mechanism and enhance the search efficiency of the algorithm, we introduce a new competitive swarm optimizer (CSO) algorithm. The CSO search algorithm is based on an inter-particle competition mechanism and can effectively avoid trapping of the population falling into a local optimum. With the improvement of an adaptive opposition-based search and its ability to dynamically parameter adjustments, this algorithm can maintain the diversity of the entire swarm to solve geometric K-center gateway deployment problems. The simulation results show that this CSO algorithm has a good global explorative ability as well as convergence speed and can improve the network quality of service (QoS) level of cyber-physical systems by obtaining a minimum network coverage radius. We also find that the CSO algorithm is more stable, robust and effective in solving the problem of geometric gateway deployment as compared to the PSO or Kmedoids algorithms. PMID:28117735

Working research codes into fluid dynamics education: a science gateway approach

Science.gov (United States)

Mason, Lachlan; Hetherington, James; O'Reilly, Martin; Yong, May; Jersakova, Radka; Grieve, Stuart; Perez-Suarez, David; Klapaukh, Roman; Craster, Richard V.; Matar, Omar K.

2017-11-01

Research codes are effective for illustrating complex concepts in educational fluid dynamics courses, compared to textbook examples, an interactive three-dimensional visualisation can bring a problem to life! Various barriers, however, prevent the adoption of research codes in teaching: codes are typically created for highly-specific `once-off' calculations and, as such, have no user interface and a steep learning curve. Moreover, a code may require access to high-performance computing resources that are not readily available in the classroom. This project allows academics to rapidly work research codes into their teaching via a minimalist `science gateway' framework. The gateway is a simple, yet flexible, web interface allowing students to construct and run simulations, as well as view and share their output. Behind the scenes, the common operations of job configuration, submission, monitoring and post-processing are customisable at the level of shell scripting. In this talk, we demonstrate the creation of an example teaching gateway connected to the Code BLUE fluid dynamics software. Student simulations can be run via a third-party cloud computing provider or a local high-performance cluster. EPSRC, UK, MEMPHIS program Grant (EP/K003976/1), RAEng Research Chair (OKM).

Evaluation of the Intel Sandy Bridge-EP server processor

CERN Document Server

Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

2012-01-01

In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing an 8-core “Sandy Bridge-EP” processor with Intel’s previous microarchitecture, the “Westmere-EP”. The Intel marketing names for these processors are “Xeon E5-2600 processor series” and “Xeon 5600 processor series”, respectively. Both processors are produced in a 32nm process, and both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores ...

Array processors based on Gaussian fraction-free method

Energy Technology Data Exchange (ETDEWEB)

Peng, S; Sedukhin, S [Aizu Univ., Aizuwakamatsu, Fukushima (Japan); Sedukhin, I

1998-03-01

The design of algorithmic array processors for solving linear systems of equations using fraction-free Gaussian elimination method is presented. The design is based on a formal approach which constructs a family of planar array processors systematically. These array processors are synthesized and analyzed. It is shown that some array processors are optimal in the framework of linear allocation of computations and in terms of number of processing elements and computing time. (author)

Mumbai harbour, India: Gateway for introduction of marine organisms

Digital Repository Service at National Institute of Oceanography (India)

Gaonkar, C.; Sawant, S.S.; Anil, A; Venkat, K.; Harkantra, S.N.

Ships have been identified as one of the important vectors in the translocation of organisms from one bioregion to another leading to bioinvasion. In this context, harbours serve as a gateway for the introduction of alien species. Surveys were...

Efficient preparation of shuffled DNA libraries through recombination (Gateway) cloning.

Science.gov (United States)

Lehtonen, Soili I; Taskinen, Barbara; Ojala, Elina; Kukkurainen, Sampo; Rahikainen, Rolle; Riihimäki, Tiina A; Laitinen, Olli H; Kulomaa, Markku S; Hytönen, Vesa P

2015-01-01

Efficient and robust subcloning is essential for the construction of high-diversity DNA libraries in the field of directed evolution. We have developed a more efficient method for the subcloning of DNA-shuffled libraries by employing recombination cloning (Gateway). The Gateway cloning procedure was performed directly after the gene reassembly reaction, without additional purification and amplification steps, thus simplifying the conventional DNA shuffling protocols. Recombination-based cloning, directly from the heterologous reassembly reaction, conserved the high quality of the library and reduced the time required for the library construction. The described method is generally compatible for the construction of DNA-shuffled gene libraries. © The Author 2014. Published by Oxford University Press. All rights reserved. For Permissions, please e-mail: journals.permissions@oup.com.

Multiple Embedded Processors for Fault-Tolerant Computing

Science.gov (United States)

Bolotin, Gary; Watson, Robert; Katanyoutanant, Sunant; Burke, Gary; Wang, Mandy

2005-01-01

A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.

Online track processor for the CDF upgrade

International Nuclear Information System (INIS)

Thomson, E. J.

2002-01-01

A trigger track processor, called the eXtremely Fast Tracker (XFT), has been designed for the CDF upgrade. This processor identifies high transverse momentum (> 1.5 GeV/c) charged particles in the new central outer tracking chamber for CDF II. The XFT design is highly parallel to handle the input rate of 183 Gbits/s and output rate of 44 Gbits/s. The processor is pipelined and reports the result for a new event every 132 ns. The processor uses three stages: hit classification, segment finding, and segment linking. The pattern recognition algorithms for the three stages are implemented in programmable logic devices (PLDs) which allow in-situ modification of the algorithm at any time. The PLDs reside on three different types of modules. The complete system has been installed and commissioned at CDF II. An overview of the track processor and performance in CDF Run II are presented

Effective connectivity gateways to the Theory of Mind network in processing communicative intention.

Science.gov (United States)

Tettamanti, Marco; Vaghi, Matilde M; Bara, Bruno G; Cappa, Stefano F; Enrici, Ivan; Adenzato, Mauro

2017-07-15

An Intention Processing Network (IPN), involving the medial prefrontal cortex, precuneus, bilateral posterior superior temporal sulcus, and temporoparietal junctions, plays a fundamental role in comprehending intentions underlying action goals. In a previous fMRI study, we showed that, depending on the linguistic or extralinguistic (gestural) modality used to convey the intention, the IPN is complemented by activation of additional brain areas, reflecting distinct modality-specific input gateways to the IPN. These areas involve, for the linguistic modality, the left inferior frontal gyrus (LIFG), and for the extralinguistic modality, the right inferior frontal gyrus (RIFG). Here, we tested the modality-specific gateway hypothesis, by using DCM to measure inter-regional functional integration dynamics between the IPN and LIFG/RIFG gateways. We found strong evidence of a well-defined effective connectivity architecture mediating the functional integration between the IPN and the inferior frontal cortices. The connectivity dynamics indicate a modality-specific propagation of stimulus information from LIFG to IPN for the linguistic modality, and from RIFG to IPN for the extralinguistic modality. Thus, we suggest a functional model in which the modality-specific gateways mediate the structural and semantic decoding of the stimuli, and allow for the modality-specific communicative information to be integrated in Theory of Mind inferences elaborated through the IPN. Copyright © 2017 Elsevier Inc. All rights reserved.

Design Principles for Synthesizable Processor Cores

DEFF Research Database (Denmark)

Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven

2012-01-01

As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput...

Data register and processor for multiwire chambers

International Nuclear Information System (INIS)

Karpukhin, V.V.

1985-01-01

A data register and a processor for data receiving and processing from drift chambers of a device for investigating relativistic positroniums are described. The data are delivered to the register input in the form of the Grey 8 bit code, memorized and transformed to a position code. The register information is delivered to the KAMAK trunk and to the front panel plug. The processor selects particle tracks in a horizontal plane of the facility. ΔY maximum coordinate divergence and minimum point quantity on the track are set from the processor front panel. Processor solution time is 16 μs maximum quantity of simultaneously analyzed coordinates is 16

A Life-Course Perspective on the "Gateway Hypothesis"

Science.gov (United States)

Van Gundy, Karen; Rebellon, Cesar J.

2010-01-01

Drawing on stress and life-course perspectives and using panel data from 1,286 south Florida young adults, we assess three critical questions regarding the role of marijuana in the "gateway hypothesis." First, does teen marijuana use independently (causally) affect subsequent use of more dangerous substances? Second, if so, does that…

Network Gateway Technology: The Issue of Redundancy towards ...

African Journals Online (AJOL)

The Internet has provided advancement in the areas of network and networking facilities. Everyone connected to the Internet is concerned about two basic things: the availability of network services and the speed of the network. Network gateway redundancy technology falls within these categories and happens to be one of ...

Advances in Planetary Protection at the Deep Space Gateway

Science.gov (United States)

Spry, J. A.; Siegel, B.; Race, M.; Rummel, J. D.; Pugel, D. E.; Groen, F. J.; Kminek, G.; Conley, C. A.; Carosso, N. J.

2018-02-01

Planetary protection knowledge gaps that can be addressed by science performed at the Deep Space Gateway in the areas of human health and performance, space biology, and planetary sciences that enable future exploration in deep space, at Mars, and other targets.

Development methods for VLSI-processors

International Nuclear Information System (INIS)

Horninger, K.; Sandweg, G.

1982-01-01

The aim of this project, which was originally planed for 3 years, was the development of modern system and circuit concepts, for VLSI-processors having a 32 bit wide data path. The result of this first years work is the concept of a general purpose processor. This processor is not only logically but also physically (on the chip) divided into four functional units: a microprogrammable instruction unit, an execution unit in slice technique, a fully associative cache memory and an I/O unit. For the ALU of the execution unit circuits in PLA and slice techniques have been realized. On the basis of regularity, area consumption and achievable performance the slice technique has been prefered. The designs utilize selftesting circuitry. (orig.) [de

The performance of an LSI-11/23 with a SKYMNK-Q array processor as a high speed front end processor

International Nuclear Information System (INIS)

Clark, D.L.

1983-01-01

The NSRL has recently installed a VAX-11/750 based data acquisition system which is networked to two LSI-11/23 satellite processors. Each of the LSI's are connected to CAMAC branch drivers. The LSI's have small array processors installed for use in preprocessing data. The objective is to provide an easy to use high speed processor that will relieve the VAX of some of the real-time data analysis tasks. The basic operation of the array processor and some of the results of performance tests are described

Embedded Processor Laboratory

Data.gov (United States)

Federal Laboratory Consortium — The Embedded Processor Laboratory provides the means to design, develop, fabricate, and test embedded computers for missile guidance electronics systems in support...

Multi-Core Processor Memory Contention Benchmark Analysis Case Study

Science.gov (United States)

Simon, Tyler; McGalliard, James

2009-01-01

Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

Architectural design and analysis of a programmable image processor

International Nuclear Information System (INIS)

Siyal, M.Y.; Chowdhry, B.S.; Rajput, A.Q.K.

2003-01-01

In this paper we present an architectural design and analysis of a programmable image processor, nicknamed Snake. The processor was designed with a high degree of parallelism to speed up a range of image processing operations. Data parallelism found in array processors has been included into the architecture of the proposed processor. The implementation of commonly used image processing algorithms and their performance evaluation are also discussed. The performance of Snake is also compared with other types of processor architectures. (author)

Analytical Bounds on the Threads in IXP1200 Network Processor

OpenAIRE

Ramakrishna, STGS; Jamadagni, HS

2003-01-01

Increasing link speeds have placed enormous burden on the processing requirements and the processors are expected to carry out a variety of tasks. Network Processors (NP) [1] [2] is the blanket name given to the processors, which are traded for flexibility and performance. Network Processors are offered by a number of vendors; to take the main burden of processing requirement of network related operations from the conventional processors. The Network Processors cover a spectrum of design trad...

Experimental evaluation of BZ-GW (BACnet-ZigBee smart grid gateway) for demand response in buildings

International Nuclear Information System (INIS)

Hong, Seung Ho; Kim, Se Hwan; Kim, Gi Myung; Kim, Hyung Lae

2014-01-01

The SG (smart grid) is a modernized and a future-oriented electric grid that deals with the whole energy chain, from generation to consumer. Among the SG applications, DR (demand response) is an important control mechanism to manage the electricity consumption of the customer in response to supply conditions. In buildings, DR is managed through installed communication networks which support DR applications. BACnet is an international standard communication protocol for building automation and control systems. BACnet uses ZigBee as a wireless communication protocol. Both BACnet and ZigBee have their own DR applications. In this study, we developed a BACnet-ZigBee gateway that maps the DR application of BACnet to that of ZigBee and vice versa. In addition, we developed an experimental facility to demonstrate how the BACnet-ZigBee gateway can be implemented for DR applications in buildings. We also measured the communication delay to verify that the BZ-GW (BACnet-ZigBee smart grid gateway) developed here satisfies the requirements of real-time DR service in buildings. - Highlights: • Developed a gateway that maps the DR application of BACnet to that of ZigBee. • Verified satisfaction for real-time requirement using experimental facility. • The gateway and other device will play a infrastructure role in buildings. • The implementation method could become a reference model for future similar

Theater gateway closure: a strategic level barricade

Science.gov (United States)

logistical planners at the strategic level can anticipate or mitigate the effects of a theater gateway closure on military operations. Through two...that at the strategic level the effects are based on the economic and diplomatic elements of the national power, affecting proportionally sustainment...Finally, logistical planners at the strategic level need to have a vast and ample knowledge and understanding of the operational environment to

A UNIX-based prototype biomedical virtual image processor

International Nuclear Information System (INIS)

Fahy, J.B.; Kim, Y.

1987-01-01

The authors have developed a multiprocess virtual image processor for the IBM PC/AT, in order to maximize image processing software portability for biomedical applications. An interprocess communication scheme, based on two-way metacode exchange, has been developed and verified for this purpose. Application programs call a device-independent image processing library, which transfers commands over a shared data bridge to one or more Autonomous Virtual Image Processors (AVIP). Each AVIP runs as a separate process in the UNIX operating system, and implements the device-independent functions on the image processor to which it corresponds. Application programs can control multiple image processors at a time, change the image processor configuration used at any time, and are completely portable among image processors for which an AVIP has been implemented. Run-time speeds have been found to be acceptable for higher level functions, although rather slow for lower level functions, owing to the overhead associated with sending commands and data over the shared data bridge

The communication processor of TUMULT-64

NARCIS (Netherlands)

Smit, Gerardus Johannes Maria; Jansen, P.G.

1988-01-01

Tumult (Twente University MULTi-processor system) is a modular extendible multi-processor system designed and implemented at the Twente University of Technology in co-operation with Oce Nederland B.V. and the Dr. Neher Laboratories (Dutch PTT). Characteristics of the hardware are: MIMD type,

High-Speed General Purpose Genetic Algorithm Processor.

Science.gov (United States)

Hoseini Alinodehi, Seyed Pourya; Moshfe, Sajjad; Saber Zaeimian, Masoumeh; Khoei, Abdollah; Hadidi, Khairollah

2016-07-01

In this paper, an ultrafast steady-state genetic algorithm processor (GAP) is presented. Due to the heavy computational load of genetic algorithms (GAs), they usually take a long time to find optimum solutions. Hardware implementation is a significant approach to overcome the problem by speeding up the GAs procedure. Hence, we designed a digital CMOS implementation of GA in [Formula: see text] process. The proposed processor is not bounded to a specific application. Indeed, it is a general-purpose processor, which is capable of performing optimization in any possible application. Utilizing speed-boosting techniques, such as pipeline scheme, parallel coarse-grained processing, parallel fitness computation, parallel selection of parents, dual-population scheme, and support for pipelined fitness computation, the proposed processor significantly reduces the processing time. Furthermore, by relying on a built-in discard operator the proposed hardware may be used in constrained problems that are very common in control applications. In the proposed design, a large search space is achievable through the bit string length extension of individuals in the genetic population by connecting the 32-bit GAPs. In addition, the proposed processor supports parallel processing, in which the GAs procedure can be run on several connected processors simultaneously.

Accuracies Of Optical Processors For Adaptive Optics

Science.gov (United States)

Downie, John D.; Goodman, Joseph W.

1992-01-01

Paper presents analysis of accuracies and requirements concerning accuracies of optical linear-algebra processors (OLAP's) in adaptive-optics imaging systems. Much faster than digital electronic processor and eliminate some residual distortion. Question whether errors introduced by analog processing of OLAP overcome advantage of greater speed. Paper addresses issue by presenting estimate of accuracy required in general OLAP that yields smaller average residual aberration of wave front than digital electronic processor computing at given speed.

Making CSB + -Trees Processor Conscious

DEFF Research Database (Denmark)

Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

2005-01-01

of the CSB+-tree. We argue that it is necessary to consider a larger group of parameters in order to adapt CSB+-tree to processor architectures as different as Pentium and Itanium. We identify this group of parameters and study how it impacts the performance of CSB+-tree on Itanium 2. Finally, we propose......Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performance...... a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager....

Lipsi: Probably the Smallest Processor in the World

DEFF Research Database (Denmark)

Schoeberl, Martin

2018-01-01

While research on high-performance processors is important, it is also interesting to explore processor architectures at the other end of the spectrum: tiny processor cores for auxiliary functions. While it is common to implement small circuits for such functions, such as a serial port, in dedica...... at a minimal cost....

Recommending the heterogeneous cluster type multi-processor system computing

International Nuclear Information System (INIS)

Iijima, Nobukazu

2010-01-01

Real-time reactor simulator had been developed by reusing the equipment of the Musashi reactor and its performance improvement became indispensable for research tools to increase sampling rate with introduction of arithmetic units using multi-Digital Signal Processor(DSP) system (cluster). In order to realize the heterogeneous cluster type multi-processor system computing, combination of two kinds of Control Processor (CP) s, Cluster Control Processor (CCP) and System Control Processor (SCP), were proposed with Large System Control Processor (LSCP) for hierarchical cluster if needed. Faster computing performance of this system was well evaluated by simulation results for simultaneous execution of plural jobs and also pipeline processing between clusters, which showed the system led to effective use of existing system and enhancement of the cost performance. (T. Tanaka)

First level trigger processor for the ZEUS calorimeter

International Nuclear Information System (INIS)

Dawson, J.W.; Talaga, R.L.; Burr, G.W.; Laird, R.J.; Smith, W.; Lackey, J.

1990-01-01

This paper discusses the design of the first level trigger processor for the ZEUS calorimeter. This processor accepts data from the 13,000 photomultipliers of the calorimeter which is topologically divided into 16 regions, and after regional preprocessing, performs logical and numerical operations which cross regional boundaries. Because the crossing period at the HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100K ECL, Advanced CMOS discrete devices, and programmable gate arrays, and operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flows into the processor at a rate of 5.2GB/s, and processed data flows from the processor to the Global First-Level Trigger at a rate of 700MB/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor. 2 refs., 3 figs

First-level trigger processor for the ZEUS calorimeter

International Nuclear Information System (INIS)

Dawson, J.W.; Talaga, R.L.; Burr, G.W.; Laird, R.J.; Smith, W.; Lackey, J.

1990-01-01

The design of the first-level trigger processor for the Zeus calorimeter is discussed. This processor accepts data from the 13,000 photomultipliers of the calorimeter, which is topologically divided into 16 regions, and after regional preprocessing performs logical and numerical operations that cross regional boundaries. Because the crossing period at the HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100K emitter-coupled logic (ECL), advanced CMOS discrete devices and programmable gate arrays, and operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flows into the processor at a rate of 5.2 Gbyte/s, and processed data flows from the processor to the global first-level trigger at a rate of 70 Mbyte/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor

A digital retina-like low-level vision processor.

Science.gov (United States)

Mertoguno, S; Bourbakis, N G

2003-01-01

This correspondence presents the basic design and the simulation of a low level multilayer vision processor that emulates to some degree the functional behavior of a human retina. This retina-like multilayer processor is the lower part of an autonomous self-organized vision system, called Kydon, that could be used on visually impaired people with a damaged visual cerebral cortex. The Kydon vision system, however, is not presented in this paper. The retina-like processor consists of four major layers, where each of them is an array processor based on hexagonal, autonomous processing elements that perform a certain set of low level vision tasks, such as smoothing and light adaptation, edge detection, segmentation, line recognition and region-graph generation. At each layer, the array processor is a 2D array of k/spl times/m hexagonal identical autonomous cells that simultaneously execute certain low level vision tasks. Thus, the hardware design and the simulation at the transistor level of the processing elements (PEs) of the retina-like processor and its simulated functionality with illustrative examples are provided in this paper.

Median and Morphological Specialized Processors for a Real-Time Image Data Processing

Directory of Open Access Journals (Sweden)

Kazimierz Wiatr

2002-01-01

Full Text Available This paper presents the considerations on selecting a multiprocessor MISD architecture for fast implementation of the vision image processing. Using the author′s earlier experience with real-time systems, implementing of specialized hardware processors based on the programmable FPGA systems has been proposed in the pipeline architecture. In particular, the following processors are presented: median filter and morphological processor. The structure of a universal reconfigurable processor developed has been proposed as well. Experimental results are presented as delays on LCA level implementation for median filter, morphological processor, convolution processor, look-up-table processor, logic processor and histogram processor. These times compare with delays in general purpose processor and DSP processor.

Java Processor Optimized for RTSJ

Directory of Open Access Journals (Sweden)

Tu Shiliang

2007-01-01

Full Text Available Due to the preeminent work of the real-time specification for Java (RTSJ, Java is increasingly expected to become the leading programming language in real-time systems. To provide a Java platform suitable for real-time applications, a Java processor which can execute Java bytecode is directly proposed in this paper. It provides efficient support in hardware for some mechanisms specified in the RTSJ and offers a simpler programming model through ameliorating the scoped memory of the RTSJ. The worst case execution time (WCET of the bytecodes implemented in this processor is predictable by employing the optimization method proposed in our previous work, in which all the processing interfering predictability is handled before bytecode execution. Further advantage of this method is to make the implementation of the processor simpler and suited to a low-cost FPGA chip.

Data collection from FASTBUS to a DEC UNIBUS processor through the UNIBUS-Processor Interface

International Nuclear Information System (INIS)

Larwill, M.; Barsotti, E.; Lesny, D.; Pordes, R.

1983-01-01

This paper describes the use of the UNIBUS Processor Interface, an interface between FASTBUS and the Digital Equipment Corporation UNIBUS. The UPI was developed by Fermilab and the University of Illinois. Details of the use of this interface in a high energy physics experiment at Fermilab are given. The paper includes a discussion of the operation of the UPI on the UNIBUS of a VAX-11, and plans for using the UPI to perform data acquisition from FASTBUS to a VAX-11 Processor

New development for low energy electron beam processor

International Nuclear Information System (INIS)

Takei, Taro; Goto, Hitoshi; Oizumi, Matsutoshi; Hirakawa, Tetsuya; Ochi, Masafumi

2003-01-01

Newly developed low-energy electron beam (EB) processors that have unique designs and configurations compared to conventional ones enable electron-beam treatment of small three-dimensional objects, such as grain-like agricultural products and small plastic parts. As the EB processor can irradiate the products from the whole angles, the uniform EB treatment can be achieved at one time regardless the complex shapes of the product. Here presented are two new EB processors: the first system has cylindrical process zone, which allows three-dimensional objects to be irradiated with one-pass treatment. The second is a tube-type small EB processor, achieving not only its compactor design, but also higher beam extraction efficiency and flexible installation of the irradiation heads. The basic design of each processor and potential applications with them will be presented in this paper. (author)

A data base processor semantics specification package

Science.gov (United States)

Fishwick, P. A.

1983-01-01

A Semantics Specification Package (DBPSSP) for the Intel Data Base Processor (DBP) is defined. DBPSSP serves as a collection of cross assembly tools that allow the analyst to assemble request blocks on the host computer for passage to the DBP. The assembly tools discussed in this report may be effectively used in conjunction with a DBP compatible data communications protocol to form a query processor, precompiler, or file management system for the database processor. The source modules representing the components of DBPSSP are fully commented and included.

Globe hosts launch of new processor

CERN Multimedia

2006-01-01

Launch of the quadecore processor chip at the Globe. On 14 November, in a series of major media events around the world, the chip-maker Intel launched its new 'quadcore' processor. For the regions of Europe, the Middle East and Africa, the day-long launch event took place in CERN's Globe of Science and Innovation, with over 30 journalists in attendance, coming from as far away as Johannesburg and Dubai. CERN was a significant choice for the event: the first tests of this new generation of processor in Europe had been made at CERN over the preceding months, as part of CERN openlab, a research partnership with leading IT companies such as Intel, HP and Oracle. The event also provided the opportunity for the journalists to visit ATLAS and the CERN Computer Centre. The strategy of putting multiple processor cores on the same chip, which has been pursued by Intel and other chip-makers in the last few years, represents an important departure from the more traditional improvements in the sheer speed of such chips. ...

XL-100S microprogrammable processor

International Nuclear Information System (INIS)

Gorbunov, N.V.; Guzik, Z.; Sutulin, V.A.; Forytski, A.

1983-01-01

The XL-100S microprogrammable processor providing the multiprocessor operation mode in the XL system crate is described. The processor meets the EUR 6500 CAMAC standards, address up to 4 Mbyte memory, and interacts with 7 CAMAC branchas. Eight external requests initiate operations preset by a sequence of microcommands in a memory of the capacity up to 64 kwords of 32-Git. The microprocessor architecture allows one to emulate commands of the majority of mini- or micro-computers, including floating point operations. The XL-100S processor may be used in various branches of experimental physics: for physical experiment apparatus control, fast selection of useful physical events, organization of the of input/output operations, organization of direct assess to memory included, etc. The Am2900 microprocessor set is used as an elementary base. The device is made in the form of a single width CAMAC module

Acoustooptic linear algebra processors - Architectures, algorithms, and applications

Science.gov (United States)

Casasent, D.

1984-01-01

Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

Simulation of a processor switching circuit with APLSV

International Nuclear Information System (INIS)

Dilcher, H.

1979-01-01

The report describes the simulation of a processor switching circuit with APL. Furthermore an APL function is represented to simulate a processor in an assembly like language. Both together serve as a tool for studying processor properties. By means of the programming function it is also possible to program other simulated processors. The processor is to be used in the processing of data in real time analysis that occur in high energy physics experiments. The data are already offered to the computer in digitalized form. A typical data rate is at 10 KB/ sec. The data are structured in blocks. The particular blocks are 1 KB wide and are independent from each other. Aprocessor has to decide, whether the block data belong to an event that is part of the backround noise and can therefore be forgotten, or whether the data should be saved for a later evaluation. (orig./WB) [de

Accuracy Limitations in Optical Linear Algebra Processors

Science.gov (United States)

Batsell, Stephen Gordon

1990-01-01

One of the limiting factors in applying optical linear algebra processors (OLAPs) to real-world problems has been the poor achievable accuracy of these processors. Little previous research has been done on determining noise sources from a systems perspective which would include noise generated in the multiplication and addition operations, noise from spatial variations across arrays, and from crosstalk. In this dissertation, we propose a second-order statistical model for an OLAP which incorporates all these system noise sources. We now apply this knowledge to determining upper and lower bounds on the achievable accuracy. This is accomplished by first translating the standard definition of accuracy used in electronic digital processors to analog optical processors. We then employ our second-order statistical model. Having determined a general accuracy equation, we consider limiting cases such as for ideal and noisy components. From the ideal case, we find the fundamental limitations on improving analog processor accuracy. From the noisy case, we determine the practical limitations based on both device and system noise sources. These bounds allow system trade-offs to be made both in the choice of architecture and in individual components in such a way as to maximize the accuracy of the processor. Finally, by determining the fundamental limitations, we show the system engineer when the accuracy desired can be achieved from hardware or architecture improvements and when it must come from signal pre-processing and/or post-processing techniques.

The Heidelberg POLYP - a flexible and fault-tolerant poly-processor

International Nuclear Information System (INIS)

Maenner, R.; Deluigi, B.

1981-01-01

The Heidelberg poly-processor system POLYP is described. It is intended to be used in nuclear physics for reprocessing of experimental data, in high energy physics as second-stage trigger processor, and generally in other applications requiring high-computing power. The POLYP system consists of any number of I/O-processors, processor modules (eventually of different types), global memory segments, and a host processor. All modules (up to several hundred) are connected by a multiple common-data-bus system; all processors, additionally, by a multiple sync bus system for processor/task-scheduling. All hard- and software is designed to be decentralized and free of bottle-necks. Most hardware-faults like single-bit errors in memory or multi-bit errors during transfers are automatically corrected. Defective modules, buses, etc., can be removed with only a graceful degradation of the system-throughput. (orig.)

Rancang Bangun Sistem Pemesanan Tiket Bus Kupang-Atambua Berbasis SMS Gateway

Directory of Open Access Journals (Sweden)

Emerensiana Ngaga

2016-11-01

Full Text Available Bus merupakan alat transportasi yang paling banyak digunakan masyarakat karena harga yang murah dan masih terjangkau untuk masyarakat kalangan ekonomi menengah ke bawah.  Umumnya pemesanan tiket bus dilakukan dengan mendatangi langsung tempat penjualan tiket bus atau dengan cara menelepon ke kantor agen. Proses pemesanan seperti ini  memiliki kekurangan dimana pegawai kerepotan dalam mencatat dan seringkali terjadi kesalahan dalam mencatat pemesanan tiket. Sedangkan untuk waktu pemesanan, umumnya calon penumpang melakukan pemesanan tiket, satu atau dua hari sebelum keberangkatan dan ada juga yang tidak sempat memesan tiket beberapa hari sebelumnya dan melakukan pembelian tiket pada hari keberangkatan sehingga sering kali tidak mendapatkan tiket. Penelitian ini bertujuan merancang bangun sistem pemesanan tiket bus berbasis SMS Gateway yang memberikan kemudahan layanan pemesanan tiket bus bagi masyarakat secara jarak jauh serta kemudahan mengetahui informasi penjadwalan bus dengan cepat. Aplikasi dibangun menggunakan metode Unified Process, dengan bahasa pemrograman Java NetBeansIDE 7.3.1, MySQL sebagai database dan Gammu sebagai software untuk membantu pembangunan aplikasi SMS Gateway. Hasil dari penelitian ini adalah sebuah sistem pemesanan tiket bus yang memberikan alternatif baru proses pemesanan tiket bus secara baik tanpa ada permasalahan jarak dan waktu. Selain itu masyarakat juga dapat mengetahui informasi jadwal bus, harga tiket dan juga informasi bila terjadi perubahan jadwal keberangkatan bus.   Kata kunci— Bus, Tiket, SMS Gateway, Unified Process

Science gateways for distributed computing infrastructures development framework and exploitation by scientific user communities

CERN Document Server

Kacsuk, Péter

2014-01-01

The book describes the science gateway building technology developed in the SCI-BUS European project and its adoption and customization method, by which user communities, such as biologists, chemists, and astrophysicists, can build customized, domain-specific science gateways. Many aspects of the core technology are explained in detail, including its workflow capability, job submission mechanism to various grids and clouds, and its data transfer mechanisms among several distributed infrastructures. The book will be useful for scientific researchers and IT professionals engaged in the develop

A dedicated line-processor as used at the SHF

International Nuclear Information System (INIS)

Bevan, A.V.; Hatley, R.W.; Price, D.R.; Rankin, P.

1985-01-01

A hardwired trigger processor was used at the SLAC Hybrid Facility to find evidence for charged tracks originating from the fiducial volume of a 40'' rapidcycling bubble chamber. Straight-line projections of these tracks in the plane perpendicular to the applied magnetic field were searched for using data from three sets of proportional wire chambers (PWC). This information was made directly available to the processor by means of a special digitizing card. The results memory of the processor simulated read-only memory in a 168/E processor and was accessible by it. The 168/E controlled the issuing of a trigger command to the bubble chamber flash tubes. The same design of digitizer card used by the line processor was incorporated into the 168/E, again as read only memory, which allowed it access to the raw data for continual monitoring of trigger integrity. The design logic of the trigger processor was verified by running real PWC data through a FORTRAN simulation of the hardware. This enabled the debugging to become highly automated since a step by step, computer controlled comparison of processor registers to simulation predictions could be made

RANCANGAN PROTOTYPE ALAT PEMANTAU JUMLAH PENGUNJUNG MINIMARKET BERBASIS SMS GATEWAY

Directory of Open Access Journals (Sweden)

Suleman Suleman

2016-03-01

Full Text Available Abstract - Has designed and implemented the monitoring system, the number of visitors to the minimart based sms gateway using microcontroller ATMega8. If the first minimarket (glass was opened, then automatically limit switch 1 on the first door is depressed, so that would indicate to the microcontroller to give orders to the wavecom modem convert to the owner. The second condition, namely if the minimarket is closed then automatically limit switch 2 is depressed, it will then indicate to the microcontroller to give orders to the wavecom modem for sending sms to the owner. The design of this system using the method of architecture that consists of several stages, namely, (1 analysis of needs, (2, (3 design, Implementation arrangements, Testing tools (4, (5 test procedure and (6 Making Tools. The hardware consists of a limit switch, infrared, ATMega8 microcontroller as a minimum system controller circuit controller inputs and outputs, the output display circuit using IC MAX 232 wavecom modem that is linked to. The software is written with BASCOM-AVR Keyword : Design Of Prototype Tools Monitor The Number Of Visitors To The Minimarket, SMS Gateway Abstrak - Telah dirancang dan implementasikan sistem pemantau jumlah pengunjung minimarket berbasis sms gateway menggunakan mikrokontroler ATMega8. Jika pintu minimarket pertama (kaca dibuka, maka secara otomatis limit switch 1 yang terdapat pada pintu pertama tertekan, sehingga akan mengindikasikan kepada mikrokontroler untuk memberikan perintah kepada modem wavecom untuk menggirimkan sms kepada owner. Keadaan kedua yaitu jika pintu minimarket ditutup maka secara otomatis limit switch 2 tertekan, kemudian akan mengindikasikan kepada mikrokontroler untuk memberikan perintah kepada modem wavecom untuk mengirimkan sms kepada owner. Perancangan sistem ini menggunakan metode rancang bangun yang terdiri beberapa tahap yaitu, (1 Analisis kebutuhan, (2 Perancangan, (3 Implementasi rangkaian, (4 Pengujian alat

Embedded processor extensions for image processing

Science.gov (United States)

Thevenin, Mathieu; Paindavoine, Michel; Letellier, Laurent; Heyrman, Barthélémy

2008-04-01

The advent of camera phones marks a new phase in embedded camera sales. By late 2009, the total number of camera phones will exceed that of both conventional and digital cameras shipped since the invention of photography. Use in mobile phones of applications like visiophony, matrix code readers and biometrics requires a high degree of component flexibility that image processors (IPs) have not, to date, been able to provide. For all these reasons, programmable processor solutions have become essential. This paper presents several techniques geared to speeding up image processors. It demonstrates that a gain of twice is possible for the complete image acquisition chain and the enhancement pipeline downstream of the video sensor. Such results confirm the potential of these computing systems for supporting future applications.

Gateway to the Syriac Saints: A Database Project

Directory of Open Access Journals (Sweden)

Jeanne-Nicole Mellon Saint-Laurent

2016-04-01

Full Text Available This article describes The Gateway to the Syriac Saints, a database project developed by the Syriac Reference Portal (www.syriaca.org. It is a research tool for the study of Syriac saints and hagiographic texts. The Gateway to the Syriac Saints is a two-volume database: 1 Qadishe and 2 Bibliotheca Hagiographica Syriaca Electronica (BHSE. Hagiography, the lives of the saints, is a multiform genre. It contains elements of myth, history, biblical exegesis, romance, and theology. The production of saints’ lives blossomed in late antiquity alongside the growth of the cult of the saints. Scholars have attended to hagiographic traditions in Greek and Latin, but many scholars have yet to discover the richness of Syriac hagiographic literature: the stories, homilies, and hymns on the saints that Christians of the Middle East told and preserved. It is our hope that our database will give scholars and students increased access to these traditions to generate new scholarship. The first volume, Qadishe or “saints” in Syriac, is a digital catalogue of saints or holy persons venerated in the Syriac tradition. Some saints are native to the Syriac-speaking milieu, whereas others come from other linguistic or cultural traditions. Through the translation of their hagiographies and the diffusion of saints’ cults in the late antique world, saints were adopted, “imported,” and appropriated into Syriac religious memory. The second volume, the BHSE, focuses on Syriac hagiographic texts. The BHSE contains the titles of over 1000 Syriac stories, hymns, and homilies on saints. It also includes authors’ or hagiographers’ names, the first and last lines of the texts (in Syriac, English, and French, bibliographic information, and the names of the manuscripts containing these hagiographic works. We have also listed modern and ancient translations of these works. All of the data in the Gateway to the Syriac Saints has been encoded in TEI, and it is fully

Sojourn time tails in processor-sharing systems

NARCIS (Netherlands)

Egorova, R.R.

2009-01-01

The processor-sharing discipline was originally introduced as a modeling abstraction for the design and performance analysis of the processing unit of a computer system. Under the processor-sharing discipline, all active tasks are assumed to be processed simultaneously, receiving an equal share of

An interactive parallel processor for data analysis

International Nuclear Information System (INIS)

Mong, J.; Logan, D.; Maples, C.; Rathbun, W.; Weaver, D.

1984-01-01

A parallel array of eight minicomputers has been assembled in an attempt to deal with kiloparameter data events. By exporting computer system functions to a separate processor, the authors have been able to achieve computer amplification linearly proportional to the number of executing processors

Optical Array Processor: Laboratory Results

Science.gov (United States)

Casasent, David; Jackson, James; Vaerewyck, Gerard

1987-01-01

A Space Integrating (SI) Optical Linear Algebra Processor (OLAP) is described and laboratory results on its performance in several practical engineering problems are presented. The applications include its use in the solution of a nonlinear matrix equation for optimal control and a parabolic Partial Differential Equation (PDE), the transient diffusion equation with two spatial variables. Frequency-multiplexed, analog and high accuracy non-base-two data encoding are used and discussed. A multi-processor OLAP architecture is described and partitioning and data flow issues are addressed.

Multiprocessor Real-Time Scheduling with Hierarchical Processor Affinities

OpenAIRE

Bonifaci , Vincenzo; Brandenburg , Björn; D'Angelo , Gianlorenzo; Marchetti-Spaccamela , Alberto

2016-01-01

International audience; Many multiprocessor real-time operating systems offer the possibility to restrict the migrations of any task to a specified subset of processors by setting affinity masks. A notion of " strong arbitrary processor affinity scheduling " (strong APA scheduling) has been proposed; this notion avoids schedulability losses due to overly simple implementations of processor affinities. Due to potential overheads, strong APA has not been implemented so far in a real-time operat...

Hardware trigger processor for the MDT system

CERN Document Server

AUTHOR|(SzGeCERN)757787; The ATLAS collaboration; Hazen, Eric; Butler, John; Black, Kevin; Gastler, Daniel Edward; Ntekas, Konstantinos; Taffard, Anyes; Martinez Outschoorn, Verena; Ishino, Masaya; Okumura, Yasuyuki

2017-01-01

We are developing a low-latency hardware trigger processor for the Monitored Drift Tube system in the Muon spectrometer. The processor will fit candidate Muon tracks in the drift tubes in real time, improving significantly the momentum resolution provided by the dedicated trigger chambers. We present a novel pure-FPGA implementation of a Legendre transform segment finder, an associative-memory alternative implementation, an ARM (Zynq) processor-based track fitter, and compact ATCA carrier board architecture. The ATCA architecture is designed to allow a modular, staged approach to deployment of the system and exploration of alternative technologies.

A MultiSite GatewayTM vector set for the functional analysis of genes in the model Saccharomyces cerevisiae

Directory of Open Access Journals (Sweden)

Nagels Durand Astrid

2012-09-01

Full Text Available Abstract Background Recombinatorial cloning using the GatewayTM technology has been the method of choice for high-throughput omics projects, resulting in the availability of entire ORFeomes in GatewayTM compatible vectors. The MultiSite GatewayTM system allows combining multiple genetic fragments such as promoter, ORF and epitope tag in one single reaction. To date, this technology has not been accessible in the yeast Saccharomyces cerevisiae, one of the most widely used experimental systems in molecular biology, due to the lack of appropriate destination vectors. Results Here, we present a set of three-fragment MultiSite GatewayTM destination vectors that have been developed for gene expression in S. cerevisiae and that allow the assembly of any promoter, open reading frame, epitope tag arrangement in combination with any of four auxotrophic markers and three distinct replication mechanisms. As an example of its applicability, we used yeast three-hybrid to provide evidence for the assembly of a ternary complex of plant proteins involved in jasmonate signalling and consisting of the JAZ, NINJA and TOPLESS proteins. Conclusion Our vectors make MultiSite GatewayTM cloning accessible in S. cerevisiae and implement a fast and versatile cloning method for the high-throughput functional analysis of (heterologous proteins in one of the most widely used model organisms for molecular biology research.

Ripensare le “Piattaforme Logistiche”: il Caso del Gateway dell’Alto Adriatico Rethinking “Logistics Platforms”: the case of the North Adriatic Gateway

Directory of Open Access Journals (Sweden)

Marco Dean

2011-11-01

Full Text Available

Nel presente paper si intende sostenere la necessità di un nuovo approccio alla pianificazione delle infrastrutture nazionali ed alla programmazione dei grandi assi multimodali, in modo da focalizzarsi maggiormente su quelle infrastrutture e quei territori che, in quanto posizionati lungo le principali direttrici di traffico europee, potrebbero caratterizzarsi, in tempi non “biblici”, come gateway europee in territorio italiano.

Si sostiene che diversi strumenti programmatori che si sono alternati nell’ultimo decennio in Italia non hanno saputo individuare quei pochi veri hub portuali ed interportuali in grado di garantire effettivamente l’accesso ai grandi network internazionali e generare benefici economici già nel breve-medio termine, preferendo adottare, invece, visioni proiettate su scenari futuri, largamente incerti o mutevoli. E’ il caso del Friuli Venezia Giulia, inquadrato nella Piattaforma Logistica del Nord-Est, dove strategie infrastrutturali, logistiche ed industriali incardinate su un ipotetico Corridoio V, anziché sull’esistente (ma non ancora riconosciuto nelle mappe europee corridoio Adriatico-Baltico, hanno finito per trascurare fondamentali infrastrutture esistenti (ferrovia Pontebbana, Interporto di Cervignano e zone industriali.

Il caso analizzato suggerisce l’ipotesi che il riaggancio del nostro paese all’intera rete europea dei trasporti e della logistica possa essere rappresentato, non tanto dal Corridoio V, quanto dagli assi che si sviluppano lungo la direttrice nord-sud (Corridoi 24, 1 ed Adriatico-Baltico e che connettono i potenziali gateway europei del Mediterraneo settentrionale (Alto Adriatico e Alto Tirreno alle aree più produttive d’Europa

The objective of this paper is to explore more realistic and sustainable territorial and logistics strategies (see Fabbro, Mesolella, 2010 in order to reconnect the Italian infrastructural system to

Towards a Process Algebra for Shared Processors

DEFF Research Database (Denmark)

Buchholtz, Mikael; Andersen, Jacob; Løvengreen, Hans Henrik

2002-01-01

We present initial work on a timed process algebra that models sharing of processor resources allowing preemption at arbitrary points in time. This enables us to model both the functional and the timely behaviour of concurrent processes executed on a single processor. We give a refinement relation...

High-speed packet filtering utilizing stream processors

Science.gov (United States)

Hummel, Richard J.; Fulp, Errin W.

2009-04-01

Parallel firewalls offer a scalable architecture for the next generation of high-speed networks. While these parallel systems can be implemented using multiple firewalls, the latest generation of stream processors can provide similar benefits with a significantly reduced latency due to locality. This paper describes how the Cell Broadband Engine (CBE), a popular stream processor, can be used as a high-speed packet filter. Results show the CBE can potentially process packets arriving at a rate of 1 Gbps with a latency less than 82 μ-seconds. Performance depends on how well the packet filtering process is translated to the unique stream processor architecture. For example the method used for transmitting data and control messages among the pseudo-independent processor cores has a significant impact on performance. Experimental results will also show the current limitations of a CBE operating system when used to process packets. Possible solutions to these issues will be discussed.

Fast processor for dilepton triggers

International Nuclear Information System (INIS)

Katsanevas, S.; Kostarakis, P.; Baltrusaitis, R.

1983-01-01

We describe a fast trigger processor, developed for and used in Fermilab experiment E-537, for selecting high-mass dimuon events produced by negative pions and anti-protons. The processor finds candidate tracks by matching hit information received from drift chambers and scintillation counters, and determines their momenta. Invariant masses are calculated for all possible pairs of tracks and an event is accepted if any invariant mass is greater than some preselectable minimum mass. The whole process, accomplished within 5 to 10 microseconds, achieves up to a ten-fold reduction in trigger rate

Exploration of Near-Earth Objects from the Deep Space Gateway

Science.gov (United States)

Dunham, D. W.; Stakkestad, K.; Vedder, P.; McAdams, J.; Horsewood, J.; Genova, A. L.

2018-02-01

The paper will show how clever use of orbital dynamics can lower delta-V costs to enable scientifically interesting missions. The high-energy Deep Space Gateway orbits can be used to reach NEOs, a trans node for crews, or to deploy small sats. Examples are given.

Design of RISC Processor Using VHDL and Cadence

Science.gov (United States)

Moslehpour, Saeid; Puliroju, Chandrasekhar; Abu-Aisheh, Akram

The project deals about development of a basic RISC processor. The processor is designed with basic architecture consisting of internal modules like clock generator, memory, program counter, instruction register, accumulator, arithmetic and logic unit and decoder. This processor is mainly used for simple general purpose like arithmetic operations and which can be further developed for general purpose processor by increasing the size of the instruction register. The processor is designed in VHDL by using Xilinx 8.1i version. The present project also serves as an application of the knowledge gained from past studies of the PSPICE program. The study will show how PSPICE can be used to simplify massive complex circuits designed in VHDL Synthesis. The purpose of the project is to explore the designed RISC model piece by piece, examine and understand the Input/ Output pins, and to show how the VHDL synthesis code can be converted to a simplified PSPICE model. The project will also serve as a collection of various research materials about the pieces of the circuit.

A Planetary Defense Gateway for Smart Discovery of relevant Information for Decision Support

Science.gov (United States)

Bambacus, Myra; Yang, Chaowei Phil; Leung, Ronald Y.; Barbee, Brent; Nuth, Joseph A.; Seery, Bernard; Jiang, Yongyao; Qin, Han; Li, Yun; Yu, Manzhu;

Wetlands & Deepwater Habitats - MO 2012 East West Gateway Wetland Restoration Rank (GDB)

Data.gov (United States)

NSGIC State | GIS Inventory — Over the past five years, the East-West Gateway Council of Governments has facilitated creation of data layers to enhance conservation and transportation planning in...

Real time processor for array speckle interferometry

Science.gov (United States)

Chin, Gordon; Florez, Jose; Borelli, Renan; Fong, Wai; Miko, Joseph; Trujillo, Carlos

1989-02-01

The authors are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element two-dimensional complex FFT (fast Fourier transform) and average the power spectrum, all within the 25 ms coherence time for speckles at near-IR (infrared) wavelength. The processor will be a compact unit controlled by a PC with real-time display and data storage capability. This will provide the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with offline methods. The image acquisition and processing, design criteria, and processor architecture are described.

Vector and parallel processors in computational science

International Nuclear Information System (INIS)

Duff, I.S.; Reid, J.K.

1985-01-01

These proceedings contain the articles presented at the named conference. These concern hardware and software for vector and parallel processors, numerical methods and algorithms for the computation on such processors, as well as applications of such methods to different fields of physics and related sciences. See hints under the relevant topics. (HSI)

SCORPION II persistent surveillance system with universal gateway

Science.gov (United States)

Coster, Michael; Chambers, Jonathan; Brunck, Albert

2009-05-01

This paper addresses improvements and benefits derived from the next generation Northrop Grumman SCORPION II family of persistent surveillance and target recognition systems produced by the Xetron campus in Cincinnati, Ohio. SCORPION II reduces the size, weight, and cost of all SCORPION components in a flexible, field programmable system that is easier to conceal, backward compatible, and enables integration of over forty Unattended Ground Sensor (UGS) and camera types from a variety of manufacturers, with a modular approach to supporting multiple Line of Sight (LOS) and Beyond Line of Sight (BLOS) communications interfaces. Since 1998 Northrop Grumman has been integrating best in class sensors with its proven universal modular Gateway to provide encrypted data exfiltration to Common Operational Picture (COP) systems and remote sensor command and control. In addition to being fed to COP systems, SCORPION and SCORPION II data can be directly processed using a common sensor status graphical user interface (GUI) that allows for viewing and analysis of images and sensor data from up to seven hundred SCORPION system Gateways on single or multiple displays. This GUI enables a large amount of sensor data and imagery to be used for actionable intelligence as well as remote sensor command and control by a minimum number of analysts.

Design on intelligent gateway technique in home network

Science.gov (United States)

Hu, Zhonggong; Feng, Xiancheng

2008-12-01

Based on digitization, multimedia, mobility, wide band, real-time interaction and so on,family networks, because can provide diverse and personalized synthesis service in information, correspondence work, entertainment, education and health care and so on, are more and more paid attention by the market. The family network product development has become the focus of the related industry. In this paper,the concept of the family network and the overall reference model of the family network are introduced firstly.Then the core techniques and the correspondence standard related with the family network are proposed.The key analysis is made for the function of family gateway, the function module of the software,the key technologies to client side software architecture and the trend of development of the family network entertainment seeing and hearing service and so on. Product present situation of the family gateway and the future trend of development, application solution of the digital family service are introduced. The development of the family network product bringing about the digital family network industry is introduced finally.It causes the development of software industries,such as communication industry,electrical appliances industry, computer and game and so on.It also causes the development of estate industry.

Tackling the complexity of residential gateways in an unbundling value chain

NARCIS (Netherlands)

Hartog, F.T.H. den; Baken, N.H.G.; Keyson, D.V.; Kwaaitaal, J.J.B.; Snijders, W.A.M.

2004-01-01

Various crucial multi-disciplinary issues have been investigated concerning residential gateway (RG) technology applicable in an unbundled telecommunications value chain. We find that the Calculating-with-Concepts method can be used to construct an unambiguous frame of reference for digital rights

Lyceum: A Multi-Protocol Digital Library Gateway

Science.gov (United States)

Maa, Ming-Hokng; Nelson, Michael L.; Esler, Sandra L.

1997-01-01

Lyceum is a prototype scalable query gateway that provides a logically central interface to multi-protocol and physically distributed, digital libraries of scientific and technical information. Lyceum processes queries to multiple syntactically distinct search engines used by various distributed information servers from a single logically central interface without modification of the remote search engines. A working prototype (http://www.larc.nasa.gov/lyceum/) demonstrates the capabilities, potentials, and advantages of this type of meta-search engine by providing access to over 50 servers covering over 20 disciplines.

Evolution of a C2 protocol gateway

CSIR Research Space (South Africa)

Duvenhage, A

2008-06-01

Full Text Available real-time or slower than real-time, depending on the type of link and the data source: The gateway normally reads logged raw protocol data much faster than real-time; a simulation could also start running slower than real-time if it requires too... inherent support for logging and playback of the raw protocol data. From a software architecture perspective, each link has a corresponding link component that is responsible for opening and closing the connection, as well as reading and writing...

MPC Related Computational Capabilities of ARMv7A Processors

DEFF Research Database (Denmark)

Frison, Gianluca; Jørgensen, John Bagterp

2015-01-01

In recent years, the mass market of mobile devices has pushed the demand for increasingly fast but cheap processors. ARM, the world leader in this sector, has developed the Cortex-A series of processors with focus on computationally intensive applications. If properly programmed, these processors...... are powerful enough to solve the complex optimization problems arising in MPC in real-time, while keeping the traditional low-cost and low-power consumption. This makes these processors ideal candidates for use in embedded MPC. In this paper, we investigate the floating-point capabilities of Cortex A7, A9...... and A15 and show how to exploit the unique features of each processor to obtain the best performance, in the context of a novel implementation method for the linear-algebra routines used in MPC solvers. This method adapts high-performance computing techniques to the needs of embedded MPC. In particular...

Air-Lubricated Thermal Processor For Dry Silver Film

Science.gov (United States)

Siryj, B. W.

1980-09-01

Since dry silver film is processed by heat, it may be viewed on a light table only seconds after exposure. On the other hand, wet films require both bulky chemicals and substantial time before an image can be analyzed. Processing of dry silver film, although simple in concept, is not so simple when reduced to practice. The main concern is the effect of film temperature gradients on uniformity of optical film density. RCA has developed two thermal processors, different in implementation but based on the same philosophy. Pressurized air is directed to both sides of the film to support the film and to conduct the heat to the film. Porous graphite is used as the medium through which heat and air are introduced. The initial thermal processor was designed to process 9.5-inch-wide film moving at speeds ranging from 0.0034 to 0.008 inch per second. The processor configuration was curved to match the plane generated by the laser recording beam. The second thermal processor was configured to process 5-inch-wide film moving at a continuously variable rate ranging from 0.15 to 3.5 inches per second. Due to field flattening optics used in this laser recorder, the required film processing area was plane. In addition, this processor was sectioned in the direction of film motion, giving the processor the capability of varying both temperature and effective processing area.

Logistic Fuel Processor Development

National Research Council Canada - National Science Library

Salavani, Reza

2004-01-01

The Air Base Technologies Division of the Air Force Research Laboratory has developed a logistic fuel processor that removes the sulfur content of the fuel and in the process converts logistic fuel...

A Gateway((R)) -compatible bacterial adenylate cyclase-based two-hybrid system

Czech Academy of Sciences Publication Activity Database

Ouellette, S. P.; Gauliard, E.; Antošová, Zuzana; Ladant, D.

2014-01-01

Roč. 6, č. 3 (2014), s. 259-267 ISSN 1758-2229 Institutional support: RVO:67985823 Keywords : bacterial two-hybrid system * protein–protein interactions * cell division * Gateway((R))(GW) cloning system Subject RIV: EE - Microbiology, Virology Impact factor: 3.293, year: 2014

Real time monitoring of electron processors

International Nuclear Information System (INIS)

Nablo, S.V.; Kneeland, D.R.; McLaughlin, W.L.

1995-01-01

A real time radiation monitor (RTRM) has been developed for monitoring the dose rate (current density) of electron beam processors. The system provides continuous monitoring of processor output, electron beam uniformity, and an independent measure of operating voltage or electron energy. In view of the device's ability to replace labor-intensive dosimetry in verification of machine performance on a real-time basis, its application to providing archival performance data for in-line processing is discussed. (author)

Fast track trigger processor for the OPAL detector at LEP

Energy Technology Data Exchange (ETDEWEB)

Carter, A A; Carter, J R; Ward, D R; Heuer, R D; Jaroslawski, S; Wagner, A

1986-09-20

A fast hardware track trigger processor being built for the OPAL experiment is described. The processor will analyse data from the central drift chambers of OPAL to determine whether any tracks come from the interaction region, and thereby eliminate background events. The processor will find tracks over a large angular range, vertical strokecos thetavertical stroke < or approx. 0.95. The design of the processor is described, together with a brief account of its hardware implementation for OPAL. The results of feasibility studies are also presented.

Multi-processor data acquisition and monitoring systems for particle physics

International Nuclear Information System (INIS)

White, V.; Burch, B.; Eng, K.; Heinicke, P.; Pyatetsky, M.; Ritchie, D.

1983-01-01

A high speed distributed processing system, using PDP-11 and VAX processors, is being developed at Fermilab. The acquisition of data is done using one or more PDP-11s. Additional processors are connected to provide either data logging or extra data analysis capabilities. Within this framework, functional interchangeability of PDP-11 and VAX processors and of the PDP-11 operating systems, RT-11 and RSX-11M, has been maintained. Inter-processor connections have been implemented in a general way using the 5 megabit DR11-W hardware currently selected for the purpose. Using this approach the authors have been able to make use of several existing data acquisition and analysis packages, such as RT/MULTI, in a multi-processor system

Rapid prototyping and evaluation of programmable SIMD SDR processors in LISA

Science.gov (United States)

Chen, Ting; Liu, Hengzhu; Zhang, Botao; Liu, Dongpei

2013-03-01

With the development of international wireless communication standards, there is an increase in computational requirement for baseband signal processors. Time-to-market pressure makes it impossible to completely redesign new processors for the evolving standards. Due to its high flexibility and low power, software defined radio (SDR) digital signal processors have been proposed as promising technology to replace traditional ASIC and FPGA fashions. In addition, there are large numbers of parallel data processed in computation-intensive functions, which fosters the development of single instruction multiple data (SIMD) architecture in SDR platform. So a new way must be found to prototype the SDR processors efficiently. In this paper we present a bit-and-cycle accurate model of programmable SIMD SDR processors in a machine description language LISA. LISA is a language for instruction set architecture which can gain rapid model at architectural level. In order to evaluate the availability of our proposed processor, three common baseband functions, FFT, FIR digital filter and matrix multiplication have been mapped on the SDR platform. Analytical results showed that the SDR processor achieved the maximum of 47.1% performance boost relative to the opponent processor.

Optical backplane interconnect switch for data processors and computers

Science.gov (United States)

Hendricks, Herbert D.; Benz, Harry F.; Hammer, Jacob M.

1989-01-01

An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

Improving interoperability through gateways and cots technologies

CSIR Research Space (South Africa)

Smith, C

2013-01-01

Full Text Available simultaneously, reducing dramatically the time to deploy of the nodes. 4.2 Success History In [7] [8] it’s shown how an out-of-the-box Android smartphone can be used as an information gateway hosting JTRS SCA based public safety waveforms: AM, FM and APCO-P25... and the smartphone. Thus, the entire SCA stack, including the CRC’s Core Framework [8] and the OIS’s CORBA middleware [9] was installed in the Android smartphone. The three SCA compliant waveforms were installed also in the phone. It’s worth to mention...

Accelerating molecular dynamic simulation on the cell processor and Playstation 3.

Science.gov (United States)

Luttmann, Edgar; Ensign, Daniel L; Vaidyanathan, Vishal; Houston, Mike; Rimon, Noam; Øland, Jeppe; Jayachandran, Guha; Friedrichs, Mark; Pande, Vijay S

2009-01-30

Implementation of molecular dynamics (MD) calculations on novel architectures will vastly increase its power to calculate the physical properties of complex systems. Herein, we detail algorithmic advances developed to accelerate MD simulations on the Cell processor, a commodity processor found in PlayStation 3 (PS3). In particular, we discuss issues regarding memory access versus computation and the types of calculations which are best suited for streaming processors such as the Cell, focusing on implicit solvation models. We conclude with a comparison of improved performance on the PS3's Cell processor over more traditional processors. (c) 2008 Wiley Periodicals, Inc.

Fast digital processor for event selection according to particle number difference

International Nuclear Information System (INIS)

Basiladze, S.G.; Gus'kov, B.N.; Li Van Sun; Maksimov, A.N.; Parfenov, A.N.

1978-01-01

A fast digital processor for a magnetic spectrometer is described. It is used in experimental searches for charmed particles. The basic purpose of the processor is discriminating events in the difference of numbers of particles passing through two proportional chambers (PC). The processor consists of three units for detecting signals with PC, and a binary coder. The number of inputs of the processor is 32 for the first PC and 64 for the second. The difference in the number of particles discriminated is from 0 to 8. The resolution time is 180 ns. The processor is built in the CAMAC standard

Logistic Fuel Processor Development

National Research Council Canada - National Science Library

Salavani, Reza

2004-01-01

... to light gases then steam reform the light gases into hydrogen rich stream. This report documents the efforts in developing a fuel processor capable of providing hydrogen to a 3kW fuel cell stack...

Control over surrounding rocks deformation of soft floor and whole-coal gateways with trapezoidal supports

Energy Technology Data Exchange (ETDEWEB)

Zhai, X.; Li, D.; Shao, Q.; Sun, Y. [Henan Polytechnic University, Jaozuo (China). Dept. of Resource and Material Engineering

2005-06-01

The coal seams of Guengcun Coal mine of Yima Coal Group Co. Ltd. are prone to spontaneous combustion. Fully mechanized longwall mining with sublevel caving is used as the mining method. Based on the characteristics of the gateways of the 1301 coal face and of the roof coal seams, the natural equilibrium arch theory was used to design the parameters of 11 mine-type metal supports. Then, in-situ supporting experiments were carried out. The results indicate that under the action of virgin rock stress, the width of broken rocks zone of surrounding rocks is 1.7-2.0 m in the return heading and 1.1-1.3 m in the outgoing headway and their surrounding rocks belong to the IV-type soft rock and the III-type common surrounding rock respectively. Therefore, under the movable abutment pressure, the gateway deformation is serious. At the same time, the accumulated water on gateway floor must be drained in time. These measures were taken in the 1302 and 1304 coal faces in Gengcun colliery, and satisfactory results have been obtained. 8 refs., 3 figs.

Coal comprehensive utilization is the gateway for Shanxi Province

International Nuclear Information System (INIS)

Ma, L.; Gui, G.

1997-01-01

Shanxi Province is abundant in coal reserve. Taiyuan Coal Gasification Corporation is a large sized union enterprise engaged in comprehensive use of coal in Shanxi province, and significant economic, social, environmental benefits have been brought forth with it. This leads people to believe that coal comprehensive utilization is the gateway for Shanxi Province in the fields of improvement of environment and development of economy

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

Science.gov (United States)

Barr, David R. W.; Dudek, Piotr

2009-12-01

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

Directory of Open Access Journals (Sweden)

David R. W. Barr

2009-01-01

Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

Adolescents and Young Adults' Perceptions of Electronic Cigarettes as a Gateway to Smoking: A Qualitative Study in Switzerland

Science.gov (United States)

Akre, Christina; Suris, Joan-Carles

2017-01-01

Electronic cigarettes (ECs) acting as a gateway to smoking traditional cigarettes (TCs) is a growing public health concern of EC use among youths. To gather the opinions and perceptions of adolescents and young adults (AYAs) on whether and how EC can act as a gateway to smoking TC among youths. A qualitative method included 42 AYAs. Participants…

A plasmid toolkit for cloning chimeric cDNAs encoding customized fusion proteins into any Gateway destination expression vector

Science.gov (United States)

2013-01-01

Background Valuable clone collections encoding the complete ORFeomes for some model organisms have been constructed following the completion of their genome sequencing projects. These libraries are based on Gateway cloning technology, which facilitates the study of protein function by simplifying the subcloning of open reading frames (ORF) into any suitable destination vector. The expression of proteins of interest as fusions with functional modules is a frequent approach in their initial functional characterization. A limited number of Gateway destination expression vectors allow the construction of fusion proteins from ORFeome-derived sequences, but they are restricted to the possibilities offered by their inbuilt functional modules and their pre-defined model organism-specificity. Thus, the availability of cloning systems that overcome these limitations would be highly advantageous. Results We present a versatile cloning toolkit for constructing fully-customizable three-part fusion proteins based on the MultiSite Gateway cloning system. The fusion protein components are encoded in the three plasmids integral to the kit. These can recombine with any purposely-engineered destination vector that uses a heterologous promoter external to the Gateway cassette, leading to the in-frame cloning of an ORF of interest flanked by two functional modules. In contrast to previous systems, a third part becomes available for peptide-encoding as it no longer needs to contain a promoter, resulting in an increased number of possible fusion combinations. We have constructed the kit’s component plasmids and demonstrate its functionality by providing proof-of-principle data on the expression of prototype fluorescent fusions in transiently-transfected cells. Conclusions We have developed a toolkit for creating fusion proteins with customized N- and C-term modules from Gateway entry clones encoding ORFs of interest. Importantly, our method allows entry clones obtained from ORFeome

Control structures for high speed processors

Science.gov (United States)

Maki, G. K.; Mankin, R.; Owsley, P. A.; Kim, G. M.

1982-01-01

A special processor was designed to function as a Reed Solomon decoder with throughput data rate in the Mhz range. This data rate is significantly greater than is possible with conventional digital architectures. To achieve this rate, the processor design includes sequential, pipelined, distributed, and parallel processing. The processor was designed using a high level language register transfer language. The RTL can be used to describe how the different processes are implemented by the hardware. One problem of special interest was the development of dependent processes which are analogous to software subroutines. For greater flexibility, the RTL control structure was implemented in ROM. The special purpose hardware required approximately 1000 SSI and MSI components. The data rate throughput is 2.5 megabits/second. This data rate is achieved through the use of pipelined and distributed processing. This data rate can be compared with 800 kilobits/second in a recently proposed very large scale integration design of a Reed Solomon encoder.

Summary report and strategy recommendations for EU citizen science gateway for biodiversity data

Directory of Open Access Journals (Sweden)

Veljo Runnel

2016-12-01

Full Text Available Citizen science is an approach of public participation in scientific research which has gained significant momentum in recent years. This is particularly evident in biology and environmental sciences where input from citizen scientists has greatly increased the number of publicly available observation data. However, there are still challenges in effective networking, data sharing and securing data quality. EU BON project has analyzed the citizen science landscape in Europe with regards to biodiversity research and proposes several policy recommendations. One of the recommendations is a Pan-European citizen science gateway for biodiversity data with dedicated tools for data collection and management. The prototypes of the gateway components are part of the EU BON biodiversity portal and described in current report.

Accuracy requirements of optical linear algebra processors in adaptive optics imaging systems

Science.gov (United States)

Downie, John D.; Goodman, Joseph W.

1989-10-01

The accuracy requirements of optical processors in adaptive optics systems are determined by estimating the required accuracy in a general optical linear algebra processor (OLAP) that results in a smaller average residual aberration than that achieved with a conventional electronic digital processor with some specific computation speed. Special attention is given to an error analysis of a general OLAP with regard to the residual aberration that is created in an adaptive mirror system by the inaccuracies of the processor, and to the effect of computational speed of an electronic processor on the correction. Results are presented on the ability of an OLAP to compete with a digital processor in various situations.

Remote Agriculture Automation using Wireless Link and IoT Gateway Infrastructure

DEFF Research Database (Denmark)

Nakutis, Z.; Deksnys, V.; Jaurusevicius, I.

2015-01-01

processing and control algorithms that produce control stimulus are executed in the gateway. This approach features the advantage of convenient possibilities to change control rules from Cloud services (installing or configuring process controller) without updating firmware of remote sensors...... benefit from the proposed architecture are identified....

Communications Relay and Human-Assisted Sample Return from the Deep Space Gateway

Science.gov (United States)

Cichan, T.; Hopkins, J. B.; Bierhaus, B.; Murrow, D. W.

2018-02-01

The Deep Space Gateway can enable or enhance exploration of the lunar surface through two capabilities: 1. communications relay, opening up access to the lunar farside, and 2. sample return, enhancing the ability to return large sample masses.

High performance graphics processors for medical imaging applications

International Nuclear Information System (INIS)

Goldwasser, S.M.; Reynolds, R.A.; Talton, D.A.; Walsh, E.S.

1989-01-01

This paper describes a family of high- performance graphics processors with special hardware for interactive visualization of 3D human anatomy. The basic architecture expands to multiple parallel processors, each processor using pipelined arithmetic and logical units for high-speed rendering of Computed Tomography (CT), Magnetic Resonance (MR) and Positron Emission Tomography (PET) data. User-selectable display alternatives include multiple 2D axial slices, reformatted images in sagittal or coronal planes and shaded 3D views. Special facilities support applications requiring color-coded display of multiple datasets (such as radiation therapy planning), or dynamic replay of time- varying volumetric data (such as cine-CT or gated MR studies of the beating heart). The current implementation is a single processor system which generates reformatted images in true real time (30 frames per second), and shaded 3D views in a few seconds per frame. It accepts full scale medical datasets in their native formats, so that minimal preprocessing delay exists between data acquisition and display

Evaluation of the Intel Westmere-EP server processor

CERN Document Server

Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

2010-01-01

In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing the 6-core “Westmere-EP” processor with Intel’s previous generation of the same microarchitecture, the “Nehalem-EP”. The former is produced in a new 32nm process, the latter in 45nm. Both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores via Simultaneous Multi-Threading (SMT), the cache sizes available, the memory configuration installed, as well...

Keystone Business Models for Network Security Processors

OpenAIRE

Arthur Low; Steven Muegge

2013-01-01

Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor...

Development of level 2 processor for the readout of TMC

International Nuclear Information System (INIS)

Arai, Y.; Ikeno, M.; Murata, T.; Sudo, F.; Emura, T.

1995-01-01

We have developed a prototype 8-bit processor for the level 2 data processing for the Time Memory Cell (TMC). The first prototype processor successfully runs with 18 MHz clock. The operation of same clock frequency as TMC (30 MHz) will be easily achieved with simple modifications. Although the processor is very primitive one but shows its powerful performance and flexibility. To realize the compact TMC/L2P (Level 2 Processor) system, it is better to include the microcode memory within the chip. Encoding logic of the microcode must be included to reduce the microcode memory in this case. (J.P.N.)

Research and implementation of intelligent gateway driver layer based on Linux bus

Directory of Open Access Journals (Sweden)

ZHANG Jian

2016-10-01

Full Text Available Currently,in the field of smart home,there is no relevant organization that yet has proposed an unified protocol standard.It increases the complexity and limitations of heterogeneous gateway software framework design that different vendor′s devices have different communication mode and protocol standards.In this paper,a serial of interfaces are provided by Linux kernel,and a virtual bus is registered under Linux.The physical device drivers are able to connect to the virtual bus.The detailed designs of the communication protocol are placed in the underlying adapters,making the integration of heterogeneous networks more natural.At the same time,designing the intelligent gateway system driver layer based on Linux bus can let the application layer be more unified and clear logical.And it also let the hardware access network become more convenient and distinct.

A Practical Evaluation of a High-Security Energy-Efficient Gateway for IoT Fog Computing Applications.

Science.gov (United States)

Suárez-Albela, Manuel; Fernández-Caramés, Tiago M; Fraga-Lamas, Paula; Castedo, Luis

2017-08-29

Fog computing extends cloud computing to the edge of a network enabling new Internet of Things (IoT) applications and services, which may involve critical data that require privacy and security. In an IoT fog computing system, three elements can be distinguished: IoT nodes that collect data, the cloud, and interconnected IoT gateways that exchange messages with the IoT nodes and with the cloud. This article focuses on securing IoT gateways, which are assumed to be constrained in terms of computational resources, but that are able to offload some processing from the cloud and to reduce the latency in the responses to the IoT nodes. However, it is usually taken for granted that IoT gateways have direct access to the electrical grid, which is not always the case: in mission-critical applications like natural disaster relief or environmental monitoring, it is common to deploy IoT nodes and gateways in large areas where electricity comes from solar or wind energy that charge the batteries that power every device. In this article, how to secure IoT gateway communications while minimizing power consumption is analyzed. The throughput and power consumption of Rivest-Shamir-Adleman (RSA) and Elliptic Curve Cryptography (ECC) are considered, since they are really popular, but have not been thoroughly analyzed when applied to IoT scenarios. Moreover, the most widespread Transport Layer Security (TLS) cipher suites use RSA as the main public key-exchange algorithm, but the key sizes needed are not practical for most IoT devices and cannot be scaled to high security levels. In contrast, ECC represents a much lighter and scalable alternative. Thus, RSA and ECC are compared for equivalent security levels, and power consumption and data throughput are measured using a testbed of IoT gateways. The measurements obtained indicate that, in the specific fog computing scenario proposed, ECC is clearly a much better alternative than RSA, obtaining energy consumption reductions of up to

A Practical Evaluation of a High-Security Energy-Efficient Gateway for IoT Fog Computing Applications

Science.gov (United States)

Castedo, Luis

2017-01-01

Fog computing extends cloud computing to the edge of a network enabling new Internet of Things (IoT) applications and services, which may involve critical data that require privacy and security. In an IoT fog computing system, three elements can be distinguished: IoT nodes that collect data, the cloud, and interconnected IoT gateways that exchange messages with the IoT nodes and with the cloud. This article focuses on securing IoT gateways, which are assumed to be constrained in terms of computational resources, but that are able to offload some processing from the cloud and to reduce the latency in the responses to the IoT nodes. However, it is usually taken for granted that IoT gateways have direct access to the electrical grid, which is not always the case: in mission-critical applications like natural disaster relief or environmental monitoring, it is common to deploy IoT nodes and gateways in large areas where electricity comes from solar or wind energy that charge the batteries that power every device. In this article, how to secure IoT gateway communications while minimizing power consumption is analyzed. The throughput and power consumption of Rivest–Shamir–Adleman (RSA) and Elliptic Curve Cryptography (ECC) are considered, since they are really popular, but have not been thoroughly analyzed when applied to IoT scenarios. Moreover, the most widespread Transport Layer Security (TLS) cipher suites use RSA as the main public key-exchange algorithm, but the key sizes needed are not practical for most IoT devices and cannot be scaled to high security levels. In contrast, ECC represents a much lighter and scalable alternative. Thus, RSA and ECC are compared for equivalent security levels, and power consumption and data throughput are measured using a testbed of IoT gateways. The measurements obtained indicate that, in the specific fog computing scenario proposed, ECC is clearly a much better alternative than RSA, obtaining energy consumption reductions of up

Review of trigger and on-line processors at SLAC

International Nuclear Information System (INIS)

Lankford, A.J.

1984-07-01

The role of trigger and on-line processors in reducing data rates to manageable proportions in e + e - physics experiments is defined not by high physics or background rates, but by the large event sizes of the general-purpose detectors employed. The rate of e + e - annihilation is low, and backgrounds are not high; yet the number of physics processes which can be studied is vast and varied. This paper begins by briefly describing the role of trigger processors in the e + e - context. The usual flow of the trigger decision process is illustrated with selected examples of SLAC trigger processing. The features are mentioned of triggering at the SLC and the trigger processing plans of the two SLC detectors: The Mark II and the SLD. The most common on-line processors at SLAC, the BADC, the SLAC Scanner Processor, the SLAC FASTBUS Controller, and the VAX CAMAC Channel, are discussed. Uses of the 168/E, 3081/E, and FASTBUS VAX processors are mentioned. The manner in which these processors are interfaced and the function they serve on line is described. Finally, the accelerator control system for the SLC is outlined. This paper is a survey in nature, and hence, relies heavily upon references to previous publications for detailed description of work mentioned here. 27 references, 9 figures, 1 table

Suppression of Longitudinal Coupled-Bunch Instabilities at the KEK-PF

International Nuclear Information System (INIS)

Obina, T.; Tobiyama, M.; Honda, T.; Tadano, M.; Flanagan, J.W.; Mitsuhashi, T.; Cheng, W.X.; Fox, J.D.; Teytelman, D.

2012-01-01

A bunch-by-bunch feedback system has been developed to suppress longitudinal coupled-bunch instabilities at the KEK-PF. A longitudinal kicker based on a DAFNE-type overdamped cavity has been designed and installed in the ring, and a general purpose signal processor, called iGp, has been developed by the collaboration of the KEK, SLAC, and INFN-LNF. The entire feedback loop has been closed by the end of June 2007, and the feedback system has successfully suppressed the longitudinal dipole-mode instabilities up to 430 mA.

FY1995 study of design methodology and environment of high-performance processor architectures; 1995 nendo koseino processor architecture sekkeiho to sekkei kankyo no kenkyu

Energy Technology Data Exchange (ETDEWEB)

NONE

1997-03-01

The aim of our project is to develop high-performance processor architectures for both general purpose and application-specific purpose. We also plan to develop basic softwares, such as compliers, and various design aid tools for those architectures. We are particularly interested in performance evaluation at architecture design phase, design optimization, automatic generation of compliers from processor designs, and architecture design methodologies combined with circuit layout. We have investigated both microprocessor architectures and design methodologies / environments for the processors. Our goal is to establish design technologies for high-performance, low-power, low-cost and highly-reliable systems in system-on-silicon era. We have proposed PPRAM architecture for high-performance system using DRAM and logic mixture technology, Softcore processor architecture for special purpose processors in embedded systems, and Power-Pro architecture for low power systems. We also developed design methodologies and design environments for the above architectures as well as a new method for design verification of microprocessors. (NEDO)

Prioritizing Active Learning: An Exploration of Gateway Courses in Political Science

Science.gov (United States)

Archer, Candace C.; Miller, Melissa K.

2011-01-01

Prior research in political science and other disciplines demonstrates the pedagogical and practical benefits of active learning. Less is known, however, about the extent to which active learning is used in political science classrooms. This study assesses the prioritization of active learning in "gateway" political science courses, paying…

Global Lunar Topography from the Deep Space Gateway for Science and Exploration

Science.gov (United States)

Archinal, B.; Gaddis, L.; Kirk, R.; Edmundson, K.; Stone, T.; Portree, D.; Keszthelyi, L.

2018-02-01

The Deep Space Gateway, in low lunar orbit, could be used to achieve a long standing goal of lunar science, collecting stereo images in two months to make a complete, uniform, high resolution, known accuracy, global topographic model of the Moon.

Software-defined reconfigurable microwave photonics processor.

Science.gov (United States)

Pérez, Daniel; Gasulla, Ivana; Capmany, José

2015-06-01

We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic and RF parts. We demonstrate the model versatility by applying it to several relevant application examples.

GATEWAY Demonstrations: LED System Performance in a Trial Installation--Two Years Later, Yuma Border Patrol, Yuma, Arizona

Energy Technology Data Exchange (ETDEWEB)

Wilkerson, Andrea M. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Sullivan, Gregory P. [Efficiency Solutions, Inc., Richland, WA (United States); Davis, Robert G. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

2016-04-01

Along the Yuma Sector Border Patrol Area in Yuma, Arizona, the GATEWAY program conducted a trial demonstration in which the incumbent quartz metal halide area lighting was replaced with LED at three pole locations at the Yuma Sector Border Patrol Area in Yuma, Arizona. The retrofit was documented to better understand LED technology performance in high-temperature environments. This report follows the GATEWAY Yuma Phase 1.1 Report and reflects LED system results documented two years after the demonstration began.

Designing a dataflow processor using CλaSH

NARCIS (Netherlands)

Niedermeier, A.; Wester, Rinse; Wester, Rinse; Rovers, K.C.; Baaij, C.P.R.; Kuper, Jan; Smit, Gerardus Johannes Maria

2010-01-01

In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code.

Gateways and Water Mass Mixing in the Late Cretaceous North Atlantic

Science.gov (United States)

Asgharian Rostami, M.; Martin, E. E.; MacLeod, K. G.; Poulsen, C. J.; Vande Guchte, A.; Haynes, S.

2017-12-01

Regions of intermediate/deep water formation and water-mass mixing in the North Atlantic are poorly defined for the Late Cretaceous, a time of gateway evolution and cooler conditions following the Mid Cretaceous greenhouse. Improved proxy data combined with modeling efforts are required to effectively evaluate the relationship between CO2, paleogeography, and circulation during this cooler interval. We analyzed and compiled latest Cretaceous (79 - 66 Ma) ɛNd and δ13C records from seven bathyal (paleodepths 0.2 - 2 km) and eight abyssal (paleodepths > 2 km) sites in the North Atlantic. Data suggest local downwelling of Northern Component Water (NCW; ɛNd -9.5 and δ13C 1.7 ‰) is the primary source of intermediate/deep water masses in the basin. As this water flows southward and ages, δ13C values decrease and ɛNd values increase; however, additional chemical changes at several sites require mixing with contributions from several additional water masses. Lower ɛNd ( -10) and higher δ13C ( 1.9 ‰) values in the deep NW part of the basin indicate proximal contributions from a region draining old continental crust, potentially representing deep convection following opening of the Labrador Sea. In the deep NE Iberian Basin, higher ɛNd ( -7) and lower δ13C ( 0.8 ‰) during the Campanian suggest mixing with a Tethyan source (ɛNd -7 and δ13C 0.1 ‰) whose importance decreased with restriction of that gateway in the Maastrichtian. Data from bathyal sites suggest additional mixing. In the SE Cape Verde region, observed ɛNd variations from -10 in the Campanian to -13 and -12 in the early and late Maastrichtian, respectively, may record variations in output rates of Tethyan and/or NCW sources and Demerara Bottom Water (ɛNd -16), a proposed warm saline intermediate water mass formed in shallow, equatorial seas. Pacific inflow through the Caribbean gateway impacts intermediate sites at Blake Nose (ɛNd values -8), particularly the shallowest site during the late

Researching, building a soft-processor and Ethernet interface circuit using EDK

International Nuclear Information System (INIS)

Tuong Thi Thu Huong; Pham Ngoc Tuan; Truong Van Dat, Dang Lanh; Chau Thi Nhu Quynh

2014-01-01

The processor is an indispensable component in the measurement and automatic control systems. This report describes the fabrication of a soft-processor (32-bits, on-chip block RAM 64K, 50M clock, internal and peripheral bus) for receiving, sending and processing of data Ethernet packets. This processor is fabricated using the XPS component from EDK (Xilinx) software toolkit. After that, it is configured on the FPGA named Spartan XC3S500E circuit. A firmware of a processor for controlling the interface between processor and Ethernet port is written in C language and can play a role of a HOST (station) which has its own IP to connect to Ethernet network. Besides, there are some needed parts as follows: an Ethernet interfacing controller chip, a suitable cable providing a speed up to 100 Mbs and an application program running under Window XP environment written in LabView to communicate with soft-processor. (author)

A high-accuracy optical linear algebra processor for finite element applications

Science.gov (United States)

Casasent, D.; Taylor, B. K.

1984-01-01

Optical linear processors are computationally efficient computers for solving matrix-matrix and matrix-vector oriented problems. Optical system errors limit their dynamic range to 30-40 dB, which limits their accuray to 9-12 bits. Large problems, such as the finite element problem in structural mechanics (with tens or hundreds of thousands of variables) which can exploit the speed of optical processors, require the 32 bit accuracy obtainable from digital machines. To obtain this required 32 bit accuracy with an optical processor, the data can be digitally encoded, thereby reducing the dynamic range requirements of the optical system (i.e., decreasing the effect of optical errors on the data) while providing increased accuracy. This report describes a new digitally encoded optical linear algebra processor architecture for solving finite element and banded matrix-vector problems. A linear static plate bending case study is described which quantities the processor requirements. Multiplication by digital convolution is explained, and the digitally encoded optical processor architecture is advanced.

Tobacco, the Common Enemy and a Gateway Drug: Policy Implications

Science.gov (United States)

Torabi, Mohammad R.; Jun, Mi Kyung; Nowicke, Carole; Seitz de Martinez, Barbara; Gassman, Ruth

2010-01-01

For the four leading causes of death in the United States (heart disease, cancer, stroke and chronic respiratory disease), tobacco use is a common risk factor. Tobacco use is responsible for almost 450,000 deaths per year and impacts the health of every member of our society. Tobacco is a gateway drug for substance abuse. That role is critical to…

“Puerto Rico: gateway to landscape” from an ecological perspective

Science.gov (United States)

Grizelle Gonzalez

2015-01-01

The exhibit Puerto Rico: Gateway to Landscape proposes to explore various ways in which citizens approach the landscape, or construct it – inside and outside the city – and considers city planning, the creation of parks and natural reserves, and their interpretation. From a perspective of citizen involvement, this thematic scaffolding related to landscape and the...

Low voltage 80 KV to 125 KV electron processors

International Nuclear Information System (INIS)

Lauppi, U.V.

1999-01-01

The classic electron beam technology made use of accelerating energies in the voltage range of 300 to 800 kV. The first EB processors - built for the curing of coatings - operated at 300 kV. The products to be treated were thicker than a simple layer of coating with thicknesses up to 100g and more. It was only in the beginning of the 1970's that industrial EB processors with accelerating voltages below 300 kV appeared on the market. Our company developed the first commercial electron accelerator without a beam scanner. The new EB machine featured a linear cathode, emitting a shower or 'curtain' of electrons over the full width of the product. These units were much smaller than anv previous EB processors and dedicated to the curing of coatings and other thin layers. ESI's first EB units operated with accelerating voltages between 150 and 200 kV. In 1993 ESI announced the introduction of a new generation of Electrocure. EB processors operating at 120 kV, and in 1998, at the RadTech North America '98 Conference in Chicago, the introduction of an 80 kV electron beam processor under the designation Microbeam LV

A fast track trigger processor for the OPAL detector at LEP

International Nuclear Information System (INIS)

Carter, A.A.; Jaroslawski, S.; Wagner, A.

1986-01-01

A fast hardware track trigger processor being built for the OPAL experiment is described. The processor will analyse data from the central drift chambers of OPAL to determine whether any tracks come from the interaction region, and thereby eliminate background events. The processor will find tracks over a large angular range, vertical strokecos thetavertical stroke < or approx. 0.95. The design of the processor is described, together with a brief account of its hardware implementation for OPAL. The results of feasibility studies are also presented. (orig.)

Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers

Science.gov (United States)

Tomkins, James L [Albuquerque, NM; Camp, William J [Albuquerque, NM

2009-03-17

A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

Satellite on-board real-time SAR processor prototype

Science.gov (United States)

Bergeron, Alain; Doucet, Michel; Harnisch, Bernd; Suess, Martin; Marchese, Linda; Bourqui, Pascal; Desnoyers, Nicholas; Legros, Mathieu; Guillot, Ludovic; Mercier, Luc; Châteauneuf, François

2017-11-01

A Compact Real-Time Optronic SAR Processor has been successfully developed and tested up to a Technology Readiness Level of 4 (TRL4), the breadboard validation in a laboratory environment. SAR, or Synthetic Aperture Radar, is an active system allowing day and night imaging independent of the cloud coverage of the planet. The SAR raw data is a set of complex data for range and azimuth, which cannot be compressed. Specifically, for planetary missions and unmanned aerial vehicle (UAV) systems with limited communication data rates this is a clear disadvantage. SAR images are typically processed electronically applying dedicated Fourier transformations. This, however, can also be performed optically in real-time. Originally the first SAR images were optically processed. The optical Fourier processor architecture provides inherent parallel computing capabilities allowing real-time SAR data processing and thus the ability for compression and strongly reduced communication bandwidth requirements for the satellite. SAR signal return data are in general complex data. Both amplitude and phase must be combined optically in the SAR processor for each range and azimuth pixel. Amplitude and phase are generated by dedicated spatial light modulators and superimposed by an optical relay set-up. The spatial light modulators display the full complex raw data information over a two-dimensional format, one for the azimuth and one for the range. Since the entire signal history is displayed at once, the processor operates in parallel yielding real-time performances, i.e. without resulting bottleneck. Processing of both azimuth and range information is performed in a single pass. This paper focuses on the onboard capabilities of the compact optical SAR processor prototype that allows in-orbit processing of SAR images. Examples of processed ENVISAT ASAR images are presented. Various SAR processor parameters such as processing capabilities, image quality (point target analysis), weight and

Particle simulation on a distributed memory highly parallel processor

International Nuclear Information System (INIS)

Sato, Hiroyuki; Ikesaka, Morio

1990-01-01

This paper describes parallel molecular dynamics simulation of atoms governed by local force interaction. The space in the model is divided into cubic subspaces and mapped to the processor array of the CAP-256, a distributed memory, highly parallel processor developed at Fujitsu Labs. We developed a new technique to avoid redundant calculation of forces between atoms in different processors. Experiments showed the communication overhead was less than 5%, and the idle time due to load imbalance was less than 11% for two model problems which contain 11,532 and 46,128 argon atoms. From the software simulation, the CAP-II which is under development is estimated to be about 45 times faster than CAP-256 and will be able to run the same problem about 40 times faster than Fujitsu's M-380 mainframe when 256 processors are used. (author)

Code compression for VLIW embedded processors

Science.gov (United States)

Piccinelli, Emiliano; Sannino, Roberto

2004-04-01

The implementation of processors for embedded systems implies various issues: main constraints are cost, power dissipation and die area. On the other side, new terminals perform functions that require more computational flexibility and effort. Long code streams must be loaded into memories, which are expensive and power consuming, to run on DSPs or CPUs. To overcome this issue, the "SlimCode" proprietary algorithm presented in this paper (patent pending technology) can reduce the dimensions of the program memory. It can run offline and work directly on the binary code the compiler generates, by compressing it and creating a new binary file, about 40% smaller than the original one, to be loaded into the program memory of the processor. The decompression unit will be a small ASIC, placed between the Memory Controller and the System bus of the processor, keeping unchanged the internal CPU architecture: this implies that the methodology is completely transparent to the core. We present comparisons versus the state-of-the-art IBM Codepack algorithm, along with its architectural implementation into the ST200 VLIW family core.

Recursive Matrix Inverse Update On An Optical Processor

Science.gov (United States)

Casasent, David P.; Baranoski, Edward J.

1988-02-01

A high accuracy optical linear algebraic processor (OLAP) using the digital multiplication by analog convolution (DMAC) algorithm is described for use in an efficient matrix inverse update algorithm with speed and accuracy advantages. The solution of the parameters in the algorithm are addressed and the advantages of optical over digital linear algebraic processors are advanced.

Santarém: Gateway City of Historic Frontiers of Western Pará

Directory of Open Access Journals (Sweden)

Scott William Hoefle

2013-07-01

Full Text Available This article treats the historical role of Santarém as a gateway city of multiplefrontiers of the middle valley of the Amazon and valley of the Tapajós Rivers. Over the centuries the city has controlled a hinterland that underwent a number of economic surges, from collecting natural spices, herbs and fruit of the forest in the beginning of the Portuguese colonization to agro-industry today. Located midway between Belém and Manaus, and historically subordinated to these cities, Santarém today has become a regional center for administrative, commercial, cultural and specialized services. The economic surges and socio-environmental transformations are interpreted according to the global cities network model of Peter Taylor, adapted to the Amazon with the concept of gateway cities from the literature on historical frontiers of the world. 

Evaluation of the Intel Nehalem-EX server processor

CERN Document Server

Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

2010-01-01

In this paper we report on a set of benchmark results recently obtained by the CERN openlab by comparing the 4-socket, 32-core Intel Xeon X7560 server with the previous generation 4-socket server, based on the Xeon X7460 processor. The Xeon X7560 processor represents a major change in many respects, especially the memory sub-system, so it was important to make multiple comparisons. In most benchmarks the two 4-socket servers were compared. It should be underlined that both servers represent the “top of the line” in terms of frequency. However, in some cases, it was important to compare systems that integrated the latest processor features, such as QPI links, Symmetric multithreading and over-clocking via Turbo mode, and in such situations the X7560 server was compared to a dual socket L5520 based system with an identical frequency of 2.26 GHz. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following ...

Graphical user interface for TOUGH/TOUGH2 - development of database, pre-processor, and post-processor

Energy Technology Data Exchange (ETDEWEB)

Sato, Tatsuya; Okabe, Takashi; Osato, Kazumi [Geothermal Energy Research and Development Co., Ltd., Tokyo (Japan)

1995-03-01

One of the advantages of the TOUGH/TOUGH2 (Pruess, 1987 and 1991) is the modeling using {open_quotes}free shape{close_quotes} polygonal blocks. However, the treatment of three-dimensional information, particularly for TOUGH/TOUGH2 is not easy because of the {open_quotes}free shape{close_quotes} polygonal blocks. Therefore, we have developed a database named {open_quotes}GEOBASE{close_quotes} and a pre/post-processor named {open_quotes}GEOGRAPH{close_quotes} for TOUGH/TOUGH2 on engineering work station (EWS). {open_quotes}GEOGRAPH{close_quotes} is based on the ORACLE{sup *1} relational database manager system to access data sets of surface exploration (geology, geophysics, geochemistry, etc.), drilling (well trajectory, geological column, logging, etc.), well testing (production test, injection test, interference test, tracer test, etc.) and production/injection history.{open_quotes}GEOGRAPH{close_quotes} consists of {open_quotes}Pre-processor{close_quotes} that can construct the three-dimensional free shape reservoir modeling by mouse operation on X-window and {open_quotes}Post-processor{close_quotes} that can display several kinds of two/three-dimensional maps and X-Y plots to compile data on {open_quotes}GEOBASE{close_quotes} and result of TOUGH/TOUGH2 calculation. This paper shows concept of the systems and examples of utilization.

IKT-Gateway as a bridge between dual-purpose power plant and smart grid; IKT-Gateway als Bruecke zwischen BHKW und Smart Grid

Energy Technology Data Exchange (ETDEWEB)

Neumann, Joerg [SSV Software Systems GmbH, Hannover (Germany). Bereich Vertrieb und Marketing

2012-07-15

The way to a smart grid leads via the interconnection of distributed energy producers and consumers. Within the total network, energy producers and consumers have to communicate meaningfully with each other. This is a great performance for a reliable and performant long-distance service. In the case of 2G Energietechnik AG (Heek, Federal Republic of Germany), SSV Software Systems GmbH (Hannover, Federal Republic of Germany) has met this challenge with an ICT-based gateway solution mastered.

Access for Internet of Things using Smartphone as a Gateway utilizing LTE and WiFi

DEFF Research Database (Denmark)

Mathur, Prateek; Nielsen, Rasmus Hjorth; Prasad, Neeli R.

2016-01-01

Communicating the Internet of Things (IoT) data relying on Long-Term Evolution (LTE) and WiFi has been been presented in the relevant literature. However, this necessitates devices to have LTE/WiFi capability of their own, that has limitations in the form of power consumption, and radio access...... the data to the Internet. In this paper we present a system model wherein the smartphone functions as a gateway for the IoT devices operating on NFC, ZigBee and Bluetooth. The smartphone functioning as a gateway for transferring IoT data. The system modelled in the form of a Markov Chain based...

Europe in global maritime flows: Gateways, forelands, and subnetworks

OpenAIRE

Ducruet , César; Joly , Olivier; Le Cam , Marine

2014-01-01

The position of Europe in maritime flows is demonstrated by the connections of its port gateways with the rest of the world. Such connections vary from one port to another in terms of traffic concentration and geographic coverage, dependent on multiple factors including origin-destination time and cost factors, shipper and ocean carrier decisions, and the size, quality, and specialization of local port infrastructures. A key research challenge is therefore to unravel the relationships between...

PENERAPAN CUSTOMER RELATIONSHIP MANAGEMENT (CRM BERBASIS SMS GATEWAY PADA ONLINE SHOP TOKOFARAH

Directory of Open Access Journals (Sweden)

Arfiani Nur Khusna

2016-01-01

Full Text Available SMS applications has become a promising business opportunities in the consumer and industrial markets in the world. One part that can not be separated from the SMS business is the role of an SMS Gateway, a system used by service providers to send and receive SMS automatically. Online shop tokofarah an online web business venture engaged in the production and sales of baby clothes and children. The problems that exist in the online shop tokofarah is the absence of communication between the customer and tokofarah thus reduced customer loyalty, customers are unaware of the latest promos and discounts, so the application of CRM (Customer Relationship Management is very necessary to help communication. Alternative solutions in addition to implementing CRM also develop and implement SMS technology as a service via SMS Gateway online. Where customers can easily find information on the latest promos and discounts, customers can simply type a certain key word and send it to a specific number that has been provided, the store can also inform customers about the latest promos and products through SMS brodcast. In this study, using Gammu as tools liaison between the device with a computer modem. Making the program using the programming language PHP as an interface, a database maker MySQL tools. The results of the implementation of the concept of SMS Gateway technology is that it can provide convenience for online customers shop tokofarah in knowing the promo and the latest product information and can order via SMS.

Biomass is beginning to threaten the wood-processors

International Nuclear Information System (INIS)

Beer, G.; Sobinkovic, B.

2004-01-01

In this issue an exploitation of biomass in Slovak Republic is analysed. Some new projects of constructing of the stoke-holds for biomass processing are published. The grants for biomass are ascending the prices of wood raw material, which is thus becoming less accessible for the wood-processors. An excessive wood export threatens the domestic processors

Reconfigurable signal processor designs for advanced digital array radar systems

Science.gov (United States)

Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

2017-05-01

The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

Parallel processor for fast event analysis

International Nuclear Information System (INIS)

Hensley, D.C.

1983-01-01

Current maximum data rates from the Spin Spectrometer of approx. 5000 events/s (up to 1.3 MBytes/s) and minimum analysis requiring at least 3000 operations/event require a CPU cycle time near 70 ns. In order to achieve an effective cycle time of 70 ns, a parallel processing device is proposed where up to 4 independent processors will be implemented in parallel. The individual processors are designed around the Am2910 Microsequencer, the AM29116 μP, and the Am29517 Multiplier. Satellite histogramming in a mass memory system will be managed by a commercial 16-bit μP system

Asymmetrical floating point array processors, their application to exploration and exploitation

Energy Technology Data Exchange (ETDEWEB)

Geriepy, B L

1983-01-01

An asymmetrical floating point array processor is a special-purpose scientific computer which operates under asymmetrical control of a host computer. Although an array processor can receive fixed point input and produce fixed point output, its primary mode of operation is floating point. The first generation of array processors was oriented towards time series information. The next generation of array processors has proved much more versatile and their applicability ranges from petroleum reservoir simulation to speech syntheses. Array processors are becoming commonplace in mining, the primary usage being construction of grids-by usual methods or by kriging. The Australian mining community is among the world's leaders in regard to computer-assisted exploration and exploitation systems. Part of this leadership role must be providing guidance to computer vendors in regard to current and future requirements.

On the effective parallel programming of multi-core processors

NARCIS (Netherlands)

Varbanescu, A.L.

2010-01-01

Multi-core processors are considered now the only feasible alternative to the large single-core processors which have become limited by technological aspects such as power consumption and heat dissipation. However, due to their inherent parallel structure and their diversity, multi-cores are

PreciseMail anti-spam gateway allows users more control over spam definitions; unwanted email is eliminated with no false positives

CERN Multimedia

ten Bruggencate, J

2003-01-01

"PreciseMail Anti-Spam Gateway uses a combination of proven heuristic (rules-based) and artificial intelligence technologies that eliminates unwanted spam e-mail at an Internet gateway without filtering critical e-mail messages. Its highly effective filtering engine identifies spam and allows multiple levels of tuning and customization to meet each user's personal e-mail spam filtering requirements" (1 page).

The UA1 upgrade calorimeter trigger processor

International Nuclear Information System (INIS)

Bains, N.; Baird, S.A.; Biddulph, P.

1990-01-01

The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no deadtime. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (author)

The UA1 upgrade calorimeter trigger processor

International Nuclear Information System (INIS)

Bains, M.; Charleton, D.; Ellis, N.; Garvey, J.; Gregory, J.; Jimack, M.P.; Jovanovic, P.; Kenyon, I.R.; Baird, S.A.; Campbell, D.; Cawthraw, M.; Coughlan, J.; Flynn, P.; Galagedera, S.; Grayer, G.; Halsall, R.; Shah, T.P.; Stephens, R.; Biddulph, P.; Eisenhandler, E.; Fensome, I.F.; Landon, M.; Robinson, D.; Oliver, J.; Sumorok, K.

1990-01-01

The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no dead time. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (orig.)

Benchmarking NWP Kernels on Multi- and Many-core Processors

Science.gov (United States)

Michalakes, J.; Vachharajani, M.

2008-12-01

Increased computing power for weather, climate, and atmospheric science has provided direct benefits for defense, agriculture, the economy, the environment, and public welfare and convenience. Today, very large clusters with many thousands of processors are allowing scientists to move forward with simulations of unprecedented size. But time-critical applications such as real-time forecasting or climate prediction need strong scaling: faster nodes and processors, not more of them. Moreover, the need for good cost- performance has never been greater, both in terms of performance per watt and per dollar. For these reasons, the new generations of multi- and many-core processors being mass produced for commercial IT and "graphical computing" (video games) are being scrutinized for their ability to exploit the abundant fine- grain parallelism in atmospheric models. We present results of our work to date identifying key computational kernels within the dynamics and physics of a large community NWP model, the Weather Research and Forecast (WRF) model. We benchmark and optimize these kernels on several different multi- and many-core processors. The goals are to (1) characterize and model performance of the kernels in terms of computational intensity, data parallelism, memory bandwidth pressure, memory footprint, etc. (2) enumerate and classify effective strategies for coding and optimizing for these new processors, (3) assess difficulties and opportunities for tool or higher-level language support, and (4) establish a continuing set of kernel benchmarks that can be used to measure and compare effectiveness of current and future designs of multi- and many-core processors for weather and climate applications.

Processors for wavelet analysis and synthesis: NIFS and TI-C80 MVP

Science.gov (United States)

Brooks, Geoffrey W.

1996-03-01

Two processors are considered for image quadrature mirror filtering (QMF). The neuromorphic infrared focal-plane sensor (NIFS) is an existing prototype analog processor offering high speed spatio-temporal Gaussian filtering, which could be used for the QMF low- pass function, and difference of Gaussian filtering, which could be used for the QMF high- pass function. Although not designed specifically for wavelet analysis, the biologically- inspired system accomplishes the most computationally intensive part of QMF processing. The Texas Instruments (TI) TMS320C80 Multimedia Video Processor (MVP) is a 32-bit RISC master processor with four advanced digital signal processors (DSPs) on a single chip. Algorithm partitioning, memory management and other issues are considered for optimal performance. This paper presents these considerations with simulated results leading to processor implementation of high-speed QMF analysis and synthesis.

The VERCE Science Gateway: Enabling User Friendly HPC Seismic Wave Simulations.

Science.gov (United States)

Casarotti, E.; Spinuso, A.; Matser, J.; Leong, S. H.; Magnoni, F.; Krause, A.; Garcia, C. R.; Muraleedharan, V.; Krischer, L.; Anthes, C.

2014-12-01

The EU-funded project VERCE (Virtual Earthquake and seismology Research Community in Europe) aims to deploy technologies which satisfy the HPC and data-intensive requirements of modern seismology.As a result of VERCE official collaboration with the EU project SCI-BUS, access to computational resources, like local clusters and international infrastructures (EGI and PRACE), is made homogeneous and integrated within a dedicated science gateway based on the gUSE framework. In this presentation we give a detailed overview on the progress achieved with the developments of the VERCE Science Gateway, according to a use-case driven implementation strategy. More specifically, we show how the computational technologies and data services have been integrated within a tool for Seismic Forward Modelling, whose objective is to offer the possibility to performsimulations of seismic waves as a service to the seismological community.We will introduce the interactive components of the OGC map based web interface and how it supports the user with setting up the simulation. We will go through the selection of input data, which are either fetched from federated seismological web services, adopting community standards, or provided by the users themselves by accessing their own document data store. The HPC scientific codes can be selected from a number of waveform simulators, currently available to the seismological community as batch tools or with limited configuration capabilities in their interactive online versions.The results will be staged out via a secure GridFTP transfer to a VERCE data layer managed by iRODS. The provenance information of the simulation will be automatically cataloged by the data layer via NoSQL techonologies.Finally, we will show the example of how the visualisation output of the gateway could be enhanced by the connection with immersive projection technology at the Virtual Reality and Visualisation Centre of Leibniz Supercomputing Centre (LRZ).

ACP/R3000 processors in data acquisition systems

International Nuclear Information System (INIS)

Deppe, J.; Areti, H.; Atac, R.

1989-02-01

We describe ACP/R3000 processor based data acquisition systems for high energy physics. This VME bus compatible processor board, with a computational power equivalent to 15 VAX 11/780s or better, contains 8 Mb of memory for event buffering and has a high speed secondary bus that allows data gathering from front end electronics. 2 refs., 3 figs

GA103: A microprogrammable processor for online filtering

International Nuclear Information System (INIS)

Calzas, A.; Danon, G.; Bouquet, B.

1981-01-01

GA 103 is a 16 bit microprogrammable processor which emulates the PDP 11 instruction set. It is based on the Am 2900 slices. It allows user-implemented microinstructions and addition of hardwired processors. It will perform on-line filtering tasks in the NA 14 experiment at CERN, based on the reconstruction of transverse momentum of photons detected in a lead glass calorimeter. (orig.)

European Film Gateway projekt EFG1914 / Ivi Tomingas

Index Scriptorium Estoniae

Tomingas, Ivi

2015-01-01

Saja aasta möödumise puhul Esimesest maailmasõjast kutsus Euroopa Komisjon ellu European Film Gateway projekti EFG 1914. Avalikkusele on nüüd kättesaadav 660 tundi digiteeritud filme ja 5500 plakatit, fotot ja dokumenti. Nendega saab tutvuda aadressidel http://project.efg1914.eu ja http://www.europeanfilmgateway.eu/content/efg1914-project. Rahvusarhiivist on portaali lisatud kaks tundi Johannes Pääsukese ülesvõetud etnograafilist materjali, Pathé ringvaade nr. 17 (sõjategevus 1917) ja Theodor Lutsu film "Noored kotkad" (1927) ning Karl Akeli ja Johann Ostrati fotosid

Integrating QoS and security functions in an IP-VPN gateway

Science.gov (United States)

Fan, Kuo-Pao; Chang, Shu-Hsin; Lin, Kuan-Ming; Pen, Mau-Jy

2001-10-01

IP-based Virtual Private Network becomes more and more popular. It can not only reduce the enterprise communication cost but also increase the revenue of the service provider. The common IP-VPN application types include Intranet VPN, Extranet VPN, and remote access VPN. For the large IP-VPN market, some vendors develop dedicated IP-VPN devices; while some vendors add the VPN functions into their existing network equipment such as router, access gateway, etc. The functions in the IP-VPN device include security, QoS, and management. The common security functions supported are IPSec (IP Security), IKE (Internet Key Exchange), and Firewall. The QoS functions include bandwidth control and packet scheduling. In the management component, policy-based network management is under standardization in IETF. In this paper, we discuss issues on how to integrate the QoS and security functions in an IP-VPN Gateway. We propose three approaches to do this. They are (1) perform Qos first (2) perform IPSec first and (3) reserve fixed bandwidth for IPSec. We also compare the advantages and disadvantages of the three proposed approaches.

Real-time trajectory optimization on parallel processors

Science.gov (United States)

Psiaki, Mark L.

1993-01-01

A parallel algorithm has been developed for rapidly solving trajectory optimization problems. The goal of the work has been to develop an algorithm that is suitable to do real-time, on-line optimal guidance through repeated solution of a trajectory optimization problem. The algorithm has been developed on an INTEL iPSC/860 message passing parallel processor. It uses a zero-order-hold discretization of a continuous-time problem and solves the resulting nonlinear programming problem using a custom-designed augmented Lagrangian nonlinear programming algorithm. The algorithm achieves parallelism of function, derivative, and search direction calculations through the principle of domain decomposition applied along the time axis. It has been encoded and tested on 3 example problems, the Goddard problem, the acceleration-limited, planar minimum-time to the origin problem, and a National Aerospace Plane minimum-fuel ascent guidance problem. Execution times as fast as 118 sec of wall clock time have been achieved for a 128-stage Goddard problem solved on 32 processors. A 32-stage minimum-time problem has been solved in 151 sec on 32 processors. A 32-stage National Aerospace Plane problem required 2 hours when solved on 32 processors. A speed-up factor of 7.2 has been achieved by using 32-nodes instead of 1-node to solve a 64-stage Goddard problem.

The ATLAS Level-1 Central Trigger Processor (CTP)

CERN Document Server

Spiwoks, Ralf; Ellis, Nick; Farthouat, P; Gällnö, P; Haller, J; Krasznahorkay, A; Maeno, T; Pauly, T; Pessoa-Lima, H; Resurreccion-Arcas, I; Schuler, G; De Seixas, J M; Torga-Teixeira, R; Wengler, T

2005-01-01

The ATLAS Level-1 Central Trigger Processor (CTP) combines information from calorimeter and muon trigger processors and makes the final Level-1 Accept (L1A) decision on the basis of lists of selection criteria (trigger menus). In addition to the event-selection decision, the CTP also provides trigger summary information to the Level-2 trigger and the data acquisition system. It further provides accumulated and bunch-by-bunch scaler data for monitoring of the trigger, detector and beam conditions. The CTP is presented and results are shown from tests with the calorimeter adn muon trigger processors connected to detectors in a particle beam, as well as from stand-alone full-system tests in the laboratory which were used to validate the CTP.

A Processor-Sharing Scheduling Strategy for NFV Nodes

Directory of Open Access Journals (Sweden)

Giuseppe Faraci

2016-01-01

Full Text Available The introduction of the two paradigms SDN and NFV to “softwarize” the current Internet is making management and resource allocation two key challenges in the evolution towards the Future Internet. In this context, this paper proposes Network-Aware Round Robin (NARR, a processor-sharing strategy, to reduce delays in traversing SDN/NFV nodes. The application of NARR alleviates the job of the Orchestrator by automatically working at the intranode level, dynamically assigning the processor slices to the virtual network functions (VNFs according to the state of the queues associated with the output links of the network interface cards (NICs. An extensive simulation set is presented to show the improvements achieved with respect to two more processor-sharing strategies chosen as reference.

Processor farming method for multi-scale analysis of masonry structures

Science.gov (United States)

Krejčí, Tomáš; Koudelka, Tomáš

2017-07-01

This paper describes a processor farming method for a coupled heat and moisture transport in masonry using a two-level approach. The motivation for the two-level description comes from difficulties connected with masonry structures, where the size of stone blocks is much larger than the size of mortar layers and very fine finite element mesh has to be used. The two-level approach is suitable for parallel computing because nearly all computations can be performed independently with little synchronization. This approach is called processor farming. The master processor is dealing with the macro-scale level - the structure and the slave processors are dealing with a homogenization procedure on the meso-scale level which is represented by an appropriate representative volume element.

[Improving speech comprehension using a new cochlear implant speech processor].

Science.gov (United States)

Müller-Deile, J; Kortmann, T; Hoppe, U; Hessel, H; Morsnowski, A

2009-06-01

The aim of this multicenter clinical field study was to assess the benefits of the new Freedom 24 sound processor for cochlear implant (CI) users implanted with the Nucleus 24 cochlear implant system. The study included 48 postlingually profoundly deaf experienced CI users who demonstrated speech comprehension performance with their current speech processor on the Oldenburg sentence test (OLSA) in quiet conditions of at least 80% correct scores and who were able to perform adaptive speech threshold testing using the OLSA in noisy conditions. Following baseline measures of speech comprehension performance with their current speech processor, subjects were upgraded to the Freedom 24 speech processor. After a take-home trial period of at least 2 weeks, subject performance was evaluated by measuring the speech reception threshold with the Freiburg multisyllabic word test and speech intelligibility with the Freiburg monosyllabic word test at 50 dB and 70 dB in the sound field. The results demonstrated highly significant benefits for speech comprehension with the new speech processor. Significant benefits for speech comprehension were also demonstrated with the new speech processor when tested in competing background noise.In contrast, use of the Abbreviated Profile of Hearing Aid Benefit (APHAB) did not prove to be a suitably sensitive assessment tool for comparative subjective self-assessment of hearing benefits with each processor. Use of the preprocessing algorithm known as adaptive dynamic range optimization (ADRO) in the Freedom 24 led to additional improvements over the standard upgrade map for speech comprehension in quiet and showed equivalent performance in noise. Through use of the preprocessing beam-forming algorithm BEAM, subjects demonstrated a highly significant improved signal-to-noise ratio for speech comprehension thresholds (i.e., signal-to-noise ratio for 50% speech comprehension scores) when tested with an adaptive procedure using the Oldenburg

Flexible gateway constructs for functional analyses of genes in plant pathogenic fungi

NARCIS (Netherlands)

Mehrabi, Rahim; Mirzadi Gohari, Amir; Silva, da Gilvan Ferreira; Steinberg, Gero; Kema, Gert H.J.; Wit, de Pierre J.G.M.

2015-01-01

Genetic manipulation of fungi requires quick, low-cost, efficient, high-throughput and molecular tools. In this paper, we report 22 entry constructs as new molecular tools based on the Gateway technology facilitating rapid construction of binary vectors that can be used for functional analysis of

Virtual Experiments on the Neutron Science TeraGrid Gateway

International Nuclear Information System (INIS)

Lynch, Vickie E; Cobb, John W; Farhi, Emmanuel N; Miller, Stephen D; Taylor, M

2008-01-01

The TeraGrid's outreach effort to the neutron science community is creating an environment that is encouraging the exploration of advanced cyberinfrastructure being incorporated into facility operations in a way that leverages facility operations to multiply the scientific output of its users, including many NSF supported scientists in many disciplines. The Neutron Science TeraGrid Gateway serves as an exploratory incubator for several TeraGrid projects. Virtual neutron scattering experiments from one exploratory project will be highlighted

A case study of the Secure Anonymous Information Linkage (SAIL) Gateway: A privacy-protecting remote access system for health-related research and evaluation☆

Science.gov (United States)

Jones, Kerina H.; Ford, David V.; Jones, Chris; Dsilva, Rohan; Thompson, Simon; Brooks, Caroline J.; Heaven, Martin L.; Thayer, Daniel S.; McNerney, Cynthia L.; Lyons, Ronan A.

2014-01-01

With the current expansion of data linkage research, the challenge is to find the balance between preserving the privacy of person-level data whilst making these data accessible for use to their full potential. We describe a privacy-protecting safe haven and secure remote access system, referred to as the Secure Anonymised Information Linkage (SAIL) Gateway. The Gateway provides data users with a familiar Windows interface and their usual toolsets to access approved anonymously-linked datasets for research and evaluation. We outline the principles and operating model of the Gateway, the features provided to users within the secure environment, and how we are approaching the challenges of making data safely accessible to increasing numbers of research users. The Gateway represents a powerful analytical environment and has been designed to be scalable and adaptable to meet the needs of the rapidly growing data linkage community. PMID:24440148

Hardware processor for tracking particles in an alternating-gradient synchrotron

International Nuclear Information System (INIS)

Johnson, M.; Avilez, C.

1987-01-01

We discuss the design and performance of special-purpose processors for tracking particles through an alternating-gradient synchrotron. We present block diagram designs for two hardware processors. Both processors use algorithms based on the 'kick' approximation, i.e., transport matrices are used for dipoles and quadrupoles, and the thin-lens approximation is used for all higher multipoles. The faster processor makes extensive use of memory look-up tables for evaluating functions. For the case of magnets with multipoles up to pole 30 and using one kick per magnet, this processor can track 19 particles through an accelerator at a rate that is only 220 times slower than the time it takes real particles to travel around the machine. For a model consisting of only thin lenses, it is only 150 times slower than real particles. An additional factor of 2 can be obtained with chips now becoming available. The number of magnets in the accelerator is limited only by the amount of memory available for storing magnet parameters. (author) 20 refs., 7 figs., 2 tabs

High-speed special-purpose processor for event selection by number of direct tracks

International Nuclear Information System (INIS)

Kalinnikov, V.A.; Krastev, V.R.; Chudakov, E.A.

1986-01-01

A processor which uses data on events from five detector planes is described. To increase economy and speed in parallel processing, the processor converts the input data to superposition code and recognizes tracks by a generated search mask. The resolving time of the processor is ≤300 nsec. The processor is CAMAC-compatible and uses ECL integrated circuits

Multibus-based parallel processor for simulation

Science.gov (United States)

Ogrady, E. P.; Wang, C.-H.

1983-01-01

A Multibus-based parallel processor simulation system is described. The system is intended to serve as a vehicle for gaining hands-on experience, testing system and application software, and evaluating parallel processor performance during development of a larger system based on the horizontal/vertical-bus interprocessor communication mechanism. The prototype system consists of up to seven Intel iSBC 86/12A single-board computers which serve as processing elements, a multiple transmission controller (MTC) designed to support system operation, and an Intel Model 225 Microcomputer Development System which serves as the user interface and input/output processor. All components are interconnected by a Multibus/IEEE 796 bus. An important characteristic of the system is that it provides a mechanism for a processing element to broadcast data to other selected processing elements. This parallel transfer capability is provided through the design of the MTC and a minor modification to the iSBC 86/12A board. The operation of the MTC, the basic hardware-level operation of the system, and pertinent details about the iSBC 86/12A and the Multibus are described.

Monitoring the performance of off-site processors

International Nuclear Information System (INIS)

Miller, C.C.

1995-01-01

Commercial nuclear power plants have been able to utilize the latest technologies and achieve large volume reduction by obtaining off-site waste processor services. Although the use of such services reduce the burden of waste processing it also reduces the utility's control over the process. Monitoring the performance of off-site processors is important so that the utility is cognizant of the waste disposition for required regulatory reporting. In addition to obtaining data for Reg Guide 1.21 reporting, Performance monitoring is important to determine which vendor and which services to utilize. Off-site processor services were initially offered for the decontamination of metallic waste. Since that time the list of services has expanded to include supercompaction, survey for release, incineration and metal melting. The number of vendors offering off-site services has increased and the services they offer vary. processing rates vary between vendors and have different charge bases. Determining which vendor to use for what service can be complicated and confusing

Characterization of Outer Space Radiation Induced Changes in Extremophiles Utilizing Deep Space Gateway Opportunities

Science.gov (United States)

Venkateswaran, K.; Wang, C.; Smith, D.; Mason, C.; Landry, K.; Rettberg, P.

2018-02-01

Extremophilic microbial survival, adaptation, biological functions, and molecular mechanisms associated with outer space radiation can be tested by exposing them onto Deep Space Gateway hardware (inside/outside) using microbiology and molecular biology techniques.

Marine gateway vs. fluvial stream within the Balkans from 6 to 5Ma

NARCIS (Netherlands)

Suc, Jean Pierre; Popescu, Speranta Maria; Do Couto, Damien; Clauzon, Georges; Rubino, Jean Loup; Melinte-Dobrinescu, Mihaela Carmen; Quillévéré, Frédéric; Brun, Jean Pierre; Dumurdžanov, Nikola; Zagorchev, Ivan; Lesić, Vesna; Tomić, Dragana; Sokoutis, Dimitrios; Meyer, Bertrand; Macaleţ, Rodica; Rifelj, Helena

Since the discovery of calcareous nannofossils, dinoflagellate cysts and planktonic foraminifers in deposits from the Dacic Basin, intensive research has been performed in order to evidence which gateway this microplankton used to connect Paratethys and the Mediterranean prior and after the

Digital Signal Processor System for AC Power Drivers

Directory of Open Access Journals (Sweden)

Ovidiu Neamtu

2009-10-01

Full Text Available DSP (Digital Signal Processor is the bestsolution for motor control systems to make possible thedevelopment of advanced motor drive systems. The motorcontrol processor calculates the required motor windingvoltage magnitude and frequency to operate the motor atthe desired speed. A PWM (Pulse Width Modulationcircuit controls the on and off duty cycle of the powerinverter switches to vary the magnitude of the motorvoltages.

Early experience with the cochlear ESPrit ear-level speech processor in children.

Science.gov (United States)

Totten, C; Cope, Y; McCormick, B

2000-12-01

The ESPrit ear-level speech processor has recently become available in the United Kingdom for use with the Nucleus CI24M multichannel cochlear implant. We report on the use of this ear-level processor with 6 children, ages 8 to 15 years. In this study, all patients were initially fitted with the SPrint body-worn processor, this being a prerequisite for programming the ESPrit. Five of the children were fitted successfully with the ESPrit and are using their devices consistently. The results show that patient experience with the ESPrit has been favorable, although there have been some device and programming difficulties. Aided threshold measures show that the ESPrit processor performs at least as well as the SPrint processor, with a trend toward improved aided thresholds for the ESPrit processor compared with the SPrint processor. Further study of the functional benefit of both of these devices may confirm these potential gains. The ESPrit device currently has a disadvantage for children in that it does not support FM radio hearing aid use. Finally, caution is advised in the fitting of the ESPrit in very young children or inexperienced listeners, because of difficulties in monitoring device function.

Survey of cochlear implant user satisfaction with the Neptune™ waterproof sound processor

Directory of Open Access Journals (Sweden)

Jeroen J. Briaire

2016-04-01

Full Text Available A multi-center self-assessment survey was conducted to evaluate patient satisfaction with the Advanced Bionics Neptune™ waterproof sound processor used with the AquaMic™ totally submersible microphone. Subjective satisfaction with the different Neptune™ wearing options, comfort, ease of use, sound quality and use of the processor in a range of active and water related situations were assessed for 23 adults and 73 children, using an online and paper based questionnaire. Upgraded subjects compared their previous processor to the Neptune™. The Neptune™ was most popular for use in general sports and in the pool. Subjects were satisfied with the sound quality of the sound processor outside and under water and following submersion. Seventyeight percent of subjects rated waterproofness as being very useful and 83% of the newly implanted subjects selected waterproofness as one of the reasons why they chose the Neptune™ processor. Providing a waterproof sound processor is considered by cochlear implant recipients to be useful and important and is a factor in their processor choice. Subjects reported that they were satisfied with the Neptune™ sound quality, ease of use and different wearing options.

A word processor optimized for preparing journal articles and student papers.

Science.gov (United States)

Wolach, A H; McHale, M A

2001-11-01

A new Windows-based word processor for preparing journal articles and student papers is described. In addition to standard features found in word processors, the present word processor provides specific help in preparing manuscripts. Clicking on "Reference Help (APA Form)" in the "File" menu provides a detailed help system for entering the references in a journal article. Clicking on "Examples and Explanations of APA Form" provides a help system with examples of the various sections of a review article, journal article that has one experiment, or journal article that has two or more experiments. The word processor can automatically place the manuscript page header and page number at the top of each page using the form required by APA and Psychonomic Society journals. The "APA Form" submenu of the "Help" menu provides detailed information about how the word processor is optimized for preparing articles and papers.

Extended performance electric propulsion power processor design study. Volume 2: Technical summary

Science.gov (United States)

Biess, J. J.; Inouye, L. Y.; Schoenfeld, A. D.

1977-01-01

Electric propulsion power processor technology has processed during the past decade to the point that it is considered ready for application. Several power processor design concepts were evaluated and compared. Emphasis was placed on a 30 cm ion thruster power processor with a beam power rating supply of 2.2KW to 10KW for the main propulsion power stage. Extension in power processor performance were defined and were designed in sufficient detail to determine efficiency, component weight, part count, reliability and thermal control. A detail design was performed on a microprocessor as the thyristor power processor controller. A reliability analysis was performed to evaluate the effect of the control electronics redesign. Preliminary electrical design, mechanical design and thermal analysis were performed on a 6KW power transformer for the beam supply. Bi-Mod mechanical, structural and thermal control configurations were evaluated for the power processor and preliminary estimates of mechanical weight were determined.

First Results of an “Artificial Retina” Processor Prototype

International Nuclear Information System (INIS)

Cenci, Riccardo; Bedeschi, Franco; Marino, Pietro; Morello, Michael J.; Ninci, Daniele; Piucci, Alessio; Punzi, Giovanni; Ristori, Luciano; Spinella, Franco; Stracka, Simone; Tonelli, Diego; Walsh, John

2016-01-01

We report on the performance of a specialized processor capable of reconstructing charged particle tracks in a realistic LHC silicon tracker detector, at the same speed of the readout and with sub-microsecond latency. The processor is based on an innovative pattern-recognition algorithm, called “artificial retina algorithm”, inspired from the vision system of mammals. A prototype of the processor has been designed, simulated, and implemented on Tel62 boards equipped with high-bandwidth Altera Stratix III FPGA devices. The prototype is the first step towards a real-time track reconstruction device aimed at processing complex events of high-luminosity LHC experiments at 40 MHz crossing rate

A case study of the Secure Anonymous Information Linkage (SAIL) Gateway: a privacy-protecting remote access system for health-related research and evaluation.

Science.gov (United States)

Jones, Kerina H; Ford, David V; Jones, Chris; Dsilva, Rohan; Thompson, Simon; Brooks, Caroline J; Heaven, Martin L; Thayer, Daniel S; McNerney, Cynthia L; Lyons, Ronan A

2014-08-01

With the current expansion of data linkage research, the challenge is to find the balance between preserving the privacy of person-level data whilst making these data accessible for use to their full potential. We describe a privacy-protecting safe haven and secure remote access system, referred to as the Secure Anonymised Information Linkage (SAIL) Gateway. The Gateway provides data users with a familiar Windows interface and their usual toolsets to access approved anonymously-linked datasets for research and evaluation. We outline the principles and operating model of the Gateway, the features provided to users within the secure environment, and how we are approaching the challenges of making data safely accessible to increasing numbers of research users. The Gateway represents a powerful analytical environment and has been designed to be scalable and adaptable to meet the needs of the rapidly growing data linkage community. Copyright © 2014 The Aurthors. Published by Elsevier Inc. All rights reserved.

Nonlinear Wave Simulation on the Xeon Phi Knights Landing Processor

Science.gov (United States)

Hristov, Ivan; Goranov, Goran; Hristova, Radoslava

2018-02-01

We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named "Ivy Bridge-EP") in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named "Knights Landing" (KNL). The results show 2 times better performance on KNL processor.

M7--a high speed digital processor for second level trigger selections

International Nuclear Information System (INIS)

Droege, T.F.; Gaines, I.; Turner, K.J.

1978-01-01

A digital processor is described which reconstructs mass and momentum as a second-level trigger selection. The processor is a five-address, microprogramed, pipelined, ECL machine with simultaneous memory access to four operands which load two parallel multipliers and an ALU. Source data modules are extensions of the processor

A gateway for phylogenetic analysis powered by grid computing featuring GARLI 2.0.

Science.gov (United States)

Bazinet, Adam L; Zwickl, Derrick J; Cummings, Michael P

2014-09-01

We introduce molecularevolution.org, a publicly available gateway for high-throughput, maximum-likelihood phylogenetic analysis powered by grid computing. The gateway features a garli 2.0 web service that enables a user to quickly and easily submit thousands of maximum likelihood tree searches or bootstrap searches that are executed in parallel on distributed computing resources. The garli web service allows one to easily specify partitioned substitution models using a graphical interface, and it performs sophisticated post-processing of phylogenetic results. Although the garli web service has been used by the research community for over three years, here we formally announce the availability of the service, describe its capabilities, highlight new features and recent improvements, and provide details about how the grid system efficiently delivers high-quality phylogenetic results. © The Author(s) 2014. Published by Oxford University Press, on behalf of the Society of Systematic Biologists.

Social class culture cycles: how three gateway contexts shape selves and fuel inequality.

Science.gov (United States)

Stephens, Nicole M; Markus, Hazel Rose; Phillips, L Taylor

2014-01-01

America's unprecedented levels of inequality have far-reaching negative consequences for society as a whole. Although differential access to resources contributes to inequality, the current review illuminates how ongoing participation in different social class contexts also gives rise to culture-specific selves and patterns of thinking, feeling, and acting. We integrate a growing body of interdisciplinary research to reveal how social class culture cycles operate over the course of the lifespan and through critical gateway contexts, including homes, schools, and workplaces. We first document how each of these contexts socializes social class cultural differences. Then, we demonstrate how these gateway institutions, which could provide access to upward social mobility, are structured according to middle-class ways of being a self and thus can fuel and perpetuate inequality. We conclude with a discussion of intervention opportunities that can reduce inequality by taking into account the contextual responsiveness of the self.

Flooding and subsidence in the Thames Gateway: impact on insurance loss potential

Science.gov (United States)

Royse, Katherine; Horn, Diane; Eldridge, Jillian; Barker, Karen

2010-05-01

In the UK, household buildings insurance generally covers loss and damage to the insured property from a range of natural and human perils, including windstorm, flood, subsidence, theft, accidental fire and winter freeze. Consequently, insurers require a reasoned view on the likely scale of losses that they may face to assist in strategic planning, reinsurance structuring, regulatory returns and general risk management. The UK summer 2007 flood events not only provided a clear indication of the scale of potential losses that the industry could face from an individual event, with £3 billion in claims, but also identified a need for insurers and reinsurers to better understand how events may correlate in time and space, and how to most effectively use the computational models of extreme events that are commonly applied to reflect these correlations. In addition to the potential for temporal clustering of events such as windstorms and floods, there is a possibility that seemingly uncorrelated natural perils, such as floods and subsidence, may impact an insurer's portfolio. Where aggregations of large numbers of new properties are planned, such as in the Thames Gateway, consideration of the potential future risk of aggregate losses due to the combination of perils such as subsidence and flood is increasingly important within the insurance company's strategic risk management process. Whilst perils such as subsidence and flooding are generally considered independent within risk modelling, the potential for one event to influence the magnitude and likelihood of the other should be taken into account when determining risk level. In addition, the impact of correlated, but distinctive, loss causing events on particular property types may be significant, particularly if a specific property is designed to protect against one peril but is potentially susceptible to another. We suggest that flood events can lead to increased subsidence risk due to the weight of additional water

Gateways: Expanding knowledge through broader participation

Directory of Open Access Journals (Sweden)

Phil Nyden

2008-09-01

Full Text Available This new journal, Gateways: International Journal of Community Research and Engagement, responds to a growing global movement of university-collaborative research initiatives. It also strives to fill a gap created by the sparse number of journals which publish outcomes of community-engaged research and work concerning community engagement. We seek articles based on research that is the result of actively engaged research-practitioner collaborative projects, has the potential of informing community-based activities or develops understanding of community engagement. Combining different knowledge bases that have traditionally been separated into academic and non-academic worlds can dramatically increase information flowing to scholars, community leaders and activists seeking to improve the quality of life in local communities around the world. We also wish to encourage work that contributes to the scholarship of engagement.

GateWay Community College Water Resources Program Partnerships: An Opportunity for Program Success and Collaboration

Science.gov (United States)

Castaneda, M.

2012-12-01

GateWay Community College Water Resources Technologies (WRT) Program offers Certificate of Completions and Associate Degrees on Hydrologic Studies, Water Treatment and Wastewater Treatment. The program has been in existence since 1998 and has gone through several updates to meet the demand for professionals in those areas. The program includes theoretical and practical hands-on training in the monitoring of water quality and quantity as well as in water and industrial wastewater treatment. The WRT program offers online, face-to-face, and hybrid courses to address different student's needs for training. The program only Full-time faculty is supported by 15 adjunct- faculty professionals. Adjunct faculty is usually hired from a wide variety of professional people already working in the industry that have shown interest on teaching. Adjunct faculty also provide free tutoring to the WRT students when they are not teaching courses. The college Learning Center provides funding to support these tutoring activities. The program has an active Advisory Committee that provides guidance and recommends program changes to meet their training needs. This Advisory Committee is made of professionals from different federal, state, county agencies, and municipalities, private industry and consulting companies in the area. The Advisory Committee meets every year to provide feedback to GateWay on curriculum changes and commit to potential internship opportunities for the WRT students. Those internships (or voluntary work) are paid directly by the municipalities or agencies or can be paid by the GateWay WRT program. These internship jobs provides with an opportunity to actively promote the WRT program throughout the valley. The GateWay WRT program considers the Advisory Committee an essential component for the program success: the committee supports the program in recommending and acquiring the latest field equipment needed for the hands-on training. One of the main WRT program

Discussion paper for a highly parallel array processor-based machine

International Nuclear Information System (INIS)

Hagstrom, R.; Bolotin, G.; Dawson, J.

1984-01-01

The architectural plant for a quickly realizable implementation of a highly parallel special-purpose computer system with peak performance in the range of 6 billion floating point operations per second is discussed. The architecture is suitable to Lattice Gauge theoretical computations of fundamental physics interest and may be applicable to a range of other problems which deal with numerically intensive computational problems. The plan is quickly realizable because it employs a maximum of commercially available hardware subsystems and because the architecture is software-transparent to the individual processors, allowing straightforward re-use of whatever commercially available operating-systems and support software that is suitable to run on the commercially-produced processors. A tiny prototype instrument, designed along this architecture has already operated. A few elementary examples of programs which can run efficiently are presented. The large machine which the authors would propose to build would be based upon a highly competent array-processor, the ST-100 Array Processor, and specific design possibilities are discussed. The first step toward realizing this plan practically is to install a single ST-100 to allow algorithm development to proceed while a demonstration unit is built using two of the ST-100 Array Processors

SSC 254 Screen-Based Word Processors: Production Tests. The Lanier Word Processor.

Science.gov (United States)

Moyer, Ruth A.

Designed for use in Trident Technical College's Secretarial Lab, this series of 12 production tests focuses on the use of the Lanier Word Processor for a variety of tasks. In tests 1 and 2, students are required to type and print out letters. Tests 3 through 8 require students to reformat a text; make corrections on a letter; divide and combine…

GATEWAY Report Brief: Tunable-White Lighting at the ACC Care Center

Energy Technology Data Exchange (ETDEWEB)

None, None

2016-09-30

Summary of a GATEWAY program report that documented the performance of tunable-white LED lighting systems installed in several spaces within the ACC Care Center, a senior-care facility in Sacramento, CA. The project results included energy savings and improved lighting quality, as well as other possible health-related benefits that may have been attributable, at least in part, to the lighting changes.

Performance of Artificial Intelligence Workloads on the Intel Core 2 Duo Series Desktop Processors

OpenAIRE

Abdul Kareem PARCHUR; Kuppangari Krishna RAO; Fazal NOORBASHA; Ram Asaray SINGH

2010-01-01

As the processor architecture becomes more advanced, Intel introduced its Intel Core 2 Duo series processors. Performance impact on Intel Core 2 Duo processors are analyzed using SPEC CPU INT 2006 performance numbers. This paper studied the behavior of Artificial Intelligence (AI) benchmarks on Intel Core 2 Duo series processors. Moreover, we estimated the task completion time (TCT) @1 GHz, @2 GHz and @3 GHz Intel Core 2 Duo series processors frequency. Our results show the performance scalab...

Nonlinear Wave Simulation on the Xeon Phi Knights Landing Processor

Directory of Open Access Journals (Sweden)

Hristov Ivan

2018-01-01

Full Text Available We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named “Ivy Bridge-EP” in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named “Knights Landing” (KNL. The results show 2 times better performance on KNL processor.

HTGR core seismic analysis using an array processor

International Nuclear Information System (INIS)

Shatoff, H.; Charman, C.M.

1983-01-01

A Floating Point Systems array processor performs nonlinear dynamic analysis of the high-temperature gas-cooled reactor (HTGR) core with significant time and cost savings. The graphite HTGR core consists of approximately 8000 blocks of various shapes which are subject to motion and impact during a seismic event. Two-dimensional computer programs (CRUNCH2D, MCOCO) can perform explicit step-by-step dynamic analyses of up to 600 blocks for time-history motions. However, use of two-dimensional codes was limited by the large cost and run times required. Three-dimensional analysis of the entire core, or even a large part of it, had been considered totally impractical. Because of the needs of the HTGR core seismic program, a Floating Point Systems array processor was used to enhance computer performance of the two-dimensional core seismic computer programs, MCOCO and CRUNCH2D. This effort began by converting the computational algorithms used in the codes to a form which takes maximum advantage of the parallel and pipeline processors offered by the architecture of the Floating Point Systems array processor. The subsequent conversion of the vectorized FORTRAN coding to the array processor required a significant programming effort to make the system work on the General Atomic (GA) UNIVAC 1100/82 host. These efforts were quite rewarding, however, since the cost of running the codes has been reduced approximately 50-fold and the time threefold. The core seismic analysis with large two-dimensional models has now become routine and extension to three-dimensional analysis is feasible. These codes simulate the one-fifth-scale full-array HTGR core model. This paper compares the analysis with the test results for sine-sweep motion

A single chip pulse processor for nuclear spectroscopy

International Nuclear Information System (INIS)

Hilsenrath, F.; Bakke, J.C.; Voss, H.D.

1985-01-01

A high performance digital pulse processor, integrated into a single gate array microcircuit, has been developed for spaceflight applications. The new approach takes advantage of the latest CMOS high speed A/D flash converters and low-power gated logic arrays. The pulse processor measures pulse height, pulse area and the required timing information (e.g. multi detector coincidence and pulse pile-up detection). The pulse processor features high throughput rate (e.g. 0.5 Mhz for 2 usec gausssian pulses) and improved differential linearity (e.g. + or - 0.2 LSB for a + or - 1 LSB A/D). Because of the parallel digital architecture of the device, the interface is microprocessor bus compatible. A satellite flight application of this module is presented for use in the X-ray imager and high energy particle spectrometers of the PEM experiment on the Upper Atmospheric Research Satellite

The hardware track finder processor in CMS at CERN

CERN Document Server

Kluge, A

1997-01-01

The work covers the design of the Track Finder Processor in the high energy experiment CMS (Compact Muon Solenoid, planned for 2005) at CERN/Geneva. The task of this processor is to identify muons and measure their transverse momentum. The track finder processor makes it possible to determine the physical relevance of each high energetic collision and to forward only interesting data to the data an alysis units. Data of more than two hundred thousand detector cells are used to determine the location of muons and measure their transverse momentum. Each 25 ns a new data set is generated. Measurem ent of location and transverse momentum of the muons can be terminated within 350 ns by using an ASIC (Application Specific Integrated Circuit). A pipeline architecture processes new data sets with th e required data rate of 40 MHz to ensure dead time free operation. In the framework of this study specifications and the overall concept of the track finder processor were worked out in detail. Simul ations were performed...

The BUG BITBUS Universal Gateway

International Nuclear Information System (INIS)

Nawrocki, G.

1996-01-01

The BITBUS Universal Gateway (BUG) provides a unique, cost effective solution to many different computer interface problems. Each BUG node, utilizing ''on board'' intelligence, has the ability to provide a communication link between BITBUS protocol and other computer-signal interfaces. Among them, IEEE-488, RS232, and raw analog and binary signal 1/0. BITBUS is a multidrop, multinode link with the ability to communicate over great distances. By using this method of signal transfer, along with the communication conversion ability of the BUG, one could accomplish such things as the ability to run IEEE-488 instruments over great distances, extend a multidrop links to RS232 instruments, and provide a convenient interface point for remote analog and binary 1/0 signals, all on one homogeneous network. The BUG not only provides this through the wired ''twisted pair'' standard of BITBUS, but extends the ability to fiber optic communications for signal transfer over extreme distances and through electrically ''noisy'' environments

Enabling Global Lunar Sample Return and Life-Detection Studies Using a Deep-Space Gateway

Science.gov (United States)

Cohen, B. A.; Eigenbrode, J. A.; Young, K. E.; Bleacher, J. E.; Trainer, M. E.

2018-02-01

The Deep Space Gateway could uniquely enable a lunar robotic sampling campaign that would provide incredible science return as well as feed forward to Mars and Europa by testing instrument sterility and ability to distinguish biogenic signals.

UA1 upgrade first-level calorimeter trigger processor

International Nuclear Information System (INIS)

Bains, N.; Charlton, D.; Ellis, N.; Garvey, J.; Gregory, J.; Jimack, M.P.; Jovanovic, P.; Kenyon, I.R.; Baird, S.A.; Campbell, D.; Cawthraw, M.; Coughlan, J.; Flynn, P.; Galagedera, S.; Grayer, G.; Halsall, R.; Shah, T.P.; Stephens, R.; Eisenhandler, E.; Fensome, I.; Landon, M.

1989-01-01

A new first-level trigger processor has been built for the UA1 experiment on the Cern SppS Collider. The processor exploits the fine granularity of the new UA1 uranium-TMP calorimeter to improve the selectivity of the trigger. The new electron trigger has improved hadron jet rejection, achieved by requiring low energy deposition around the electromagnetic cluster. A missing transverse energy trigger and a total energy trigger have also been implemented. (orig.)

Application of the Computer Capacity to the Analysis of Processors Evolution

OpenAIRE

Ryabko, Boris; Rakitskiy, Anton

2017-01-01

The notion of computer capacity was proposed in 2012, and this quantity has been estimated for computers of different kinds. In this paper we show that, when designing new processors, the manufacturers change the parameters that affect the computer capacity. This allows us to predict the values of parameters of future processors. As the main example we use Intel processors, due to the accessibility of detailed description of all their technical characteristics.

Optimal processor for malfunction detection in operating nuclear reactor

International Nuclear Information System (INIS)

Ciftcioglu, O.

1990-01-01

An optimal processor for diagnosing operational transients in a nuclear reactor is described. Basic design of the processor involves real-time processing of noise signal obtained from a particular in core sensor and the optimality is based on minimum alarm failure in contrast to minimum false alarm criterion from the safe and reliable plant operation viewpoint

An updated program-controlled analog processor, model AP-006, for semiconductor detector spectrometers

International Nuclear Information System (INIS)

Shkola, N.F.; Shevchenko, Yu.A.

1989-01-01

An analog processor, model AP-006, is reported. The processor is a development of a series of spectrometric units based on a shaper of the type 'DL dif +TVS+gated ideal integrator'. Structural and circuits design features are described. The results of testing the processor in a setup with a Si(Li) detecting unit over an input count-rate range of up to 5x10 5 cps are presented. Processor applications are illustrated. (orig.)

Intelligent trigger processor for the crystal box

International Nuclear Information System (INIS)

Sanders, G.H.; Butler, H.S.; Cooper, M.D.

1981-01-01

A large solid angle modular NaI(Tl) detector with 432 phototubes and 88 trigger scintillators is being used to search simultaneously for three lepton flavor changing decays of muon. A beam of up to 10 6 muons stopping per second with a 6% duty factor would yield up to 1000 triggers per second from random triple coincidences. A reduction of the trigger rate to 10 Hz is required from a hardwired primary trigger processor described in this paper. Further reduction to < 1 Hz is achieved by a microprocessor based secondary trigger processor. The primary trigger hardware imposes voter coincidence logic, stringent timing requirements, and a non-adjacency requirement in the trigger scintillators defined by hardwired circuits. Sophisticated geometric requirements are imposed by a PROM-based matrix logic, and energy and vector-momentum cuts are imposed by a hardwired processor using LSI flash ADC's and digital arithmetic loci. The secondary trigger employs four satellite microprocessors to do a sparse data scan, multiplex the data acquisition channels and apply additional event filtering

40 CFR 80.840 - What requirements apply to transmix processors?

Science.gov (United States)

2010-07-01

... PROGRAMS (CONTINUED) REGULATION OF FUELS AND FUEL ADDITIVES Gasoline Toxics Gasoline Toxics Performance Requirements § 80.840 What requirements apply to transmix processors? Any transmix processor who produces gasoline or gasoline blendstock from transmix, or recovers gasoline or gasoline blendstock from transmix...

The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

CERN Document Server

Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

2015-01-01

The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed on purpose to execute pattern matching with a high degree of parallelism. It finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. We report on the performance of the intermedia...

The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

CERN Document Server

Andreani, A; The ATLAS collaboration; Beccherle, R; Beretta, M; Cipriani, R; Citraro, S; Citterio, M; Colombo, A; Crescioli, F; Dimas, D; Donati, S; Giannetti, P; Kordas, K; Lanza, A; Liberali, V; Luciano, P; Magalotti, D; Neroutsos, P; Nikolaidis, S; Piendibene, M; Sakellariou, A; Shojaii, S; Sotiropoulou, C-L; Stabile, A

2014-01-01

The Associative Memory (AM) system of the FTK processor has been designed to perform pattern matching using the hit information of the ATLAS silicon tracker. The AM is the heart of the FTK and it finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside the FTK, multiple designs and tests have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of the AM chip, an ASIC designed and optimized to perform pattern matching, and two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. Special relevance will be given to the AMchip design that includes two custom cells optimized for low consumption. We repo...

The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

CERN Document Server

Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

2015-01-01

The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed to execute pattern matching with a high degree of parallelism. The AM system finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 828 2 Gbit/s serial links for a total in/out bandwidth of 56 Gb/s. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. ...

Safe and Efficient Support for Embeded Multi-Processors in ADA

Science.gov (United States)

Ruiz, Jose F.

2010-08-01

New software demands increasing processing power, and multi-processor platforms are spreading as the answer to achieve the required performance. Embedded real-time systems are also subject to this trend, but in the case of real-time mission-critical systems, the properties of reliability, predictability and analyzability are also paramount. The Ada 2005 language defined a subset of its tasking model, the Ravenscar profile, that provides the basis for the implementation of deterministic and time analyzable applications on top of a streamlined run-time system. This Ravenscar tasking profile, originally designed for single processors, has proven remarkably useful for modelling verifiable real-time single-processor systems. This paper proposes a simple extension to the Ravenscar profile to support multi-processor systems using a fully partitioned approach. The implementation of this scheme is simple, and it can be used to develop applications amenable to schedulability analysis.

A programmable systolic trigger processor for FERA bus data

International Nuclear Information System (INIS)

Appelquist, G.; Hovander, B.; Sellden, B.; Bohm, C.

1992-09-01

A generic CAMAC based trigger processor module for fast processing of large amounts of ADC data, has been designed. This module has been realised using complex programmable gate arrays (LCAs from XILINX). The gate arrays have been connected to memories and multipliers in such a way that different gate array configurations can cover a wide range of module applications. Using this module, it is possible to construct complex trigger processors. The module uses both the fast ECL FERA bus and the CAMAC bus for inputs and outputs. The latter, however, is primarily used for set-up and control but may also be used for data output. Large numbers of ADCs can be served by a hierarchical arrangement of trigger processor modules, processing ADC data with pipe-line arithmetics producing the final result at the apex of the pyramid. The trigger decision will be transmitted to the data acquisition system via a logic signal while numeric results may be extracted by the CAMAC controller. The trigger processor was originally developed for the proposed neutral particle search experiment at CERN, NUMASS. There it was designed to serve as a second level trigger processor. It was required to correct all ADC raw data for efficiency and pedestal, calculate the total calorimeter energy, obtain the optimal time of flight data and calculate the particle mass. A suitable mass cut would then deliver the trigger decision. More complex triggers were also considered. (au)

Endoscopic treatment of multilocular walled-off pancreatic necrosis with the multiple transluminal gateway technique.

Science.gov (United States)

Jagielski, Mateusz; Smoczyński, Marian; Adrych, Krystian

2017-06-01

The development of minimally invasive techniques allowed access to the necrotic cavity through transperitoneal, retroperitoneal, transmural and transpapillary routes. The choice of access to walled-off pancreatic necrosis (WOPN) should depend not only on the spread of necrosis, but also on the experience of the clinical center. Herein we describe treatment of a patient with multilocular symptomatic walled-off pancreatic necrosis using minimally invasive techniques. The single transmural access (single transluminal gateway technique - SGT) to the necrotic collection of the patient was ineffective. The second gastrocystostomy was performed using the same minimally invasive technique as an extra way of access to the necrosis (multiple transluminal gateway technique - MTGT). In the described case the performance of the new technique consisting in endoscopic multiplexing transmural access (MTGT) was effective enough and led to complete recovery of the patient.

Perceived Connections between Anti-Social Gateway Behaviors and School Bullying and Culture

Science.gov (United States)

Grell, Brett Stanley; Meyer, Richard C.

2016-01-01

The purpose of this study was to examine and compare opinions of 8th and 9th grade teachers and students regarding the prevalence of anti-social/gateway behaviors in their classrooms, the perceived connection between these behaviors and more traditional forms of bullying, and the potential impact of school-wide anti-bullying programs specifically…

7 CFR 1215.14 - Processor.

Science.gov (United States)

2010-01-01

... 7 Agriculture 10 2010-01-01 2010-01-01 false Processor. 1215.14 Section 1215.14 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (MARKETING AGREEMENTS... CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14...

Performance of Artificial Intelligence Workloads on the Intel Core 2 Duo Series Desktop Processors

Directory of Open Access Journals (Sweden)

Abdul Kareem PARCHUR

2010-12-01

Full Text Available As the processor architecture becomes more advanced, Intel introduced its Intel Core 2 Duo series processors. Performance impact on Intel Core 2 Duo processors are analyzed using SPEC CPU INT 2006 performance numbers. This paper studied the behavior of Artificial Intelligence (AI benchmarks on Intel Core 2 Duo series processors. Moreover, we estimated the task completion time (TCT @1 GHz, @2 GHz and @3 GHz Intel Core 2 Duo series processors frequency. Our results show the performance scalability in Intel Core 2 Duo series processors. Even though AI benchmarks have similar execution time, they have dissimilar characteristics which are identified using principal component analysis and dendogram. As the processor frequency increased from 1.8 GHz to 3.167 GHz the execution time is decreased by ~370 sec for AI workloads. In the case of Physics/Quantum Computing programs it was ~940 sec.

Lunar Heat Flux Measurements Enabled by a Microwave Radiometer Aboard the Deep Space Gateway

Science.gov (United States)

Siegler, M.; Ruf, C.; Putzig, N.; Morgan, G.; Hayne, P.; Paige, D.; Nagihara, S.; Weber, R.

2018-02-01

We would like to present a concept to use the Deep Space Gateway as a platform for constraining the geothermal heat production, surface, and near-surface rocks, and dielectric properties of the Moon from orbit with passive microwave radiometery.

Basic and Applied Algal Life Support System Research on Board the Deep Space Gateway

Science.gov (United States)

Niederwieser, T.; Zea, L.; Anthony, J.; Stodieck, L.

2018-02-01

We study the effect of long-term preservation methods on DNA damage of algal cultures for BLSS applications. In a secondary step, the Deep Space Gateway serves as a technology demonstration platform for algal photobioreactors in intermittently occupied habitats.

CernVM Online and Cloud Gateway: a uniform interface for CernVM contextualization and deployment

International Nuclear Information System (INIS)

Lestaris, G; Charalampidis, I; Berzano, D; Blomer, J; Buncic, P; Ganis, G; Meusel, R

2014-01-01

In a virtualized environment, contextualization is the process of configuring a VM instance for the needs of various deployment use cases. Contextualization in CernVM can be done by passing a handwritten context to the user data field of cloud APIs, when running CernVM on the cloud, or by using CernVM web interface when running the VM locally. CernVM Online is a publicly accessible web interface that unifies these two procedures. A user is able to define, store and share CernVM contexts using CernVM Online and then apply them either in a cloud by using CernVM Cloud Gateway or on a local VM with the single-step pairing mechanism. CernVM Cloud Gateway is a distributed system that provides a single interface to use multiple and different clouds (by location or type, private or public). Cloud gateway has been so far integrated with OpenNebula, CloudStack and EC2 tools interfaces. A user, with access to a number of clouds, can run CernVM cloud agents that will communicate with these clouds using their interfaces, and then use one single interface to deploy and scale CernVM clusters. CernVM clusters are defined in CernVM Online and consist of a set of CernVM instances that are contextualized and can communicate with each other.

Photonics and Fiber Optics Processor Lab

Data.gov (United States)

Federal Laboratory Consortium — The Photonics and Fiber Optics Processor Lab develops, tests and evaluates high speed fiber optic network components as well as network protocols. In addition, this...

E-DECIDER Decision Support Gateway For Earthquake Disaster Response

Science.gov (United States)

Glasscoe, M. T.; Stough, T. M.; Parker, J. W.; Burl, M. C.; Donnellan, A.; Blom, R. G.; Pierce, M. E.; Wang, J.; Ma, Y.; Rundle, J. B.; Yoder, M. R.

2013-12-01

Earthquake Data Enhanced Cyber-Infrastructure for Disaster Evaluation and Response (E-DECIDER) is a NASA-funded project developing capabilities for decision-making utilizing remote sensing data and modeling software in order to provide decision support for earthquake disaster management and response. E-DECIDER incorporates earthquake forecasting methodology and geophysical modeling tools developed through NASA's QuakeSim project in order to produce standards-compliant map data products to aid in decision-making following an earthquake. Remote sensing and geodetic data, in conjunction with modeling and forecasting tools, help provide both long-term planning information for disaster management decision makers as well as short-term information following earthquake events (i.e. identifying areas where the greatest deformation and damage has occurred and emergency services may need to be focused). E-DECIDER utilizes a service-based GIS model for its cyber-infrastructure in order to produce standards-compliant products for different user types with multiple service protocols (such as KML, WMS, WFS, and WCS). The goal is to make complex GIS processing and domain-specific analysis tools more accessible to general users through software services as well as provide system sustainability through infrastructure services. The system comprises several components, which include: a GeoServer for thematic mapping and data distribution, a geospatial database for storage and spatial analysis, web service APIs, including simple-to-use REST APIs for complex GIS functionalities, and geoprocessing tools including python scripts to produce standards-compliant data products. These are then served to the E-DECIDER decision support gateway (http://e-decider.org), the E-DECIDER mobile interface, and to the Department of Homeland Security decision support middleware UICDS (Unified Incident Command and Decision Support). The E-DECIDER decision support gateway features a web interface that

Slowdown in the $M/M/1$ discriminatory processor-sharing queue

NARCIS (Netherlands)

Cheung, S.K.; Kim, Bara; Kim, Jeongsim

2008-01-01

We consider a queue with multiple K job classes, Poisson arrivals, and exponentially distributed required service times in which a single processor serves according to the discriminatory processor-sharing (DPS) discipline. For this queue, we obtain the first and second moments of the slowdown, which

Online Fastbus processor for LEP

International Nuclear Information System (INIS)

Mueller, H.

1986-01-01

The author describes the online computing aspects of Fastbus systems using a processor module which has been developed at CERN and is now available commercially. These General Purpose Master/Slaves (GPMS) are based on 68000/10 (or optionally 68020/68881) processors. Applications include use as event-filters (DELPHI), supervisory controllers, Fastbus stand-alone diagnostic tools, and multiprocessor array components. The direct mapping of single, 32-bit assembly instructions to execute Fastbus protocols makes the use of a GPM both simple and flexible. Loosely coupled processing in Fastbus networks is possible between GPM's as they support access semaphores and use a two port memory as I/O buffer for Fastbus. Both master and slave-ports support block transfers up to 20 Mbytes/s. The CERN standard Fastbus software and the MoniCa symbolic debugging monitor are available on the GPM with real time, multiprocessing support. (Auth.)

Invasive tightly coupled processor arrays

CERN Document Server

LARI, VAHID

2016-01-01

This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desire...

A Modular Pipelined Processor for High Resolution Gamma-Ray Spectroscopy

Science.gov (United States)

Veiga, Alejandro; Grunfeld, Christian

2016-02-01

The design of a digital signal processor for gamma-ray applications is presented in which a single ADC input can simultaneously provide temporal and energy characterization of gamma radiation for a wide range of applications. Applying pipelining techniques, the processor is able to manage and synchronize very large volumes of streamed real-time data. Its modular user interface provides a flexible environment for experimental design. The processor can fit in a medium-sized FPGA device operating at ADC sampling frequency, providing an efficient solution for multi-channel applications. Two experiments are presented in order to characterize its temporal and energy resolution.

A survey of Tumult, a real-time multi-processor system

International Nuclear Information System (INIS)

Jansen, P.G.

1986-01-01

Tumult (Twente University MULTi processor system) is the name of an ongoing project aiming at the design and implementation of a modular extendible multiprocessor system. All memory is distributed and processors communicate in parallel via a fast and reliable local switching network instead of a shared bus. A distributed real-time operating system is being designed and implemented, consisting of a multi-tasking subsystem per processor. Processes can communicate via a message passing mechanism. Communication links and processes are dynamically created and disposed by the application. In this article a brief description of the system is given; communication aspects are emphasized. (Auth.)

Reaction-diffusion path planning in a hybrid chemical and cellular-automaton processor

International Nuclear Information System (INIS)

Adamatzky, Andrew; Lacy Costello, Benjamin de

2003-01-01

To find the shortest collision-free path in a room containing obstacles we designed a chemical processor and coupled it with a cellular-automaton processor. In the chemical processor obstacles are represented by sites of high concentration of potassium iodide and a planar substrate is saturated with palladium chloride. Potassium iodide diffuses into the substrate and reacts with palladium chloride. A dark coloured precipitate of palladium iodide is formed almost everywhere except sites where two or more diffusion wavefronts collide. The less coloured sites are situated at the furthest distance from obstacles. Thus, the chemical processor develops a repulsive field, generated by obstacles. A snapshot of the chemical processor is inputted to a cellular automaton. The automaton behaves like a discrete excitable media; also, every cell of the automaton is supplied with a pointer that shows an origin of the cell's excitation. The excitation spreads along the cells corresponding to precipitate depleted sites of the chemical processor. When the destination-site is excited, waves travel on the lattice and update the orientations of the pointers. Thus, the automaton constructs a spanning tree, made of pointers, that guides a traveler towards the destination point. Thus, the automaton medium generates an attractive field and combination of this attractive field with the repulsive field, generated by the chemical processor, provides us with a solution of the collision-free path problem

A VAX-FPS Loosely-Coupled Array of Processors

International Nuclear Information System (INIS)

Grosdidier, G.

1987-03-01

The main features of a VAX-FPS Loosely-Coupled Array of Processors (LCAP) set-up and the implementation of a High Energy Physics tracking program for off-line purposes will be described. This LCAP consists of a VAX 11/750 host and two FPS 64 bit attached processors. Before analyzing the performances of this LCAP, its characteristics will be outlined, especially from a user's point of vue, and will be briefly compared to those of the IBM-FPS LCAP

Reducing Competitive Cache Misses in Modern Processor Architectures

OpenAIRE

Prisagjanec, Milcho; Mitrevski, Pece

2017-01-01

The increasing number of threads inside the cores of a multicore processor, and competitive access to the shared cache memory, become the main reasons for an increased number of competitive cache misses and performance decline. Inevitably, the development of modern processor architectures leads to an increased number of cache misses. In this paper, we make an attempt to implement a technique for decreasing the number of competitive cache misses in the first level of cache memory. This tec...

16-Bit RISC Processor Design for Convolution Application

OpenAIRE

Anand Nandakumar Shardul

2013-01-01

In this project, we propose a 16-bit non-pipelined RISC processor, which is used for signal processing applications. The processor consists of the blocks, namely, program counter, clock control unit, ALU, IDU and registers. Advantageous architectural modifications have been made in the incremented circuit used in program counter and carry select adder unit of the ALU in the RISC CPU core. Furthermore, a high speed and low power modified modifies multiplier has been designed and introduced in ...

Modal Processor Effects Inspired by Hammond Tonewheel Organs

Directory of Open Access Journals (Sweden)

Kurt James Werner

2016-06-01

Full Text Available In this design study, we introduce a novel class of digital audio effects that extend the recently introduced modal processor approach to artificial reverberation and effects processing. These pitch and distortion processing effects mimic the design and sonics of a classic additive-synthesis-based electromechanical musical instrument, the Hammond tonewheel organ. As a reverb effect, the modal processor simulates a room response as the sum of resonant filter responses. This architecture provides precise, interactive control over the frequency, damping, and complex amplitude of each mode. Into this framework, we introduce two types of processing effects: pitch effects inspired by the Hammond organ’s equal tempered “tonewheels”, “drawbar” tone controls, vibrato/chorus circuit, and distortion effects inspired by the pseudo-sinusoidal shape of its tonewheels and electromagnetic pickup distortion. The result is an effects processor that imprints the Hammond organ’s sonics onto any audio input.

Safety-critical Java on a time-predictable processor

DEFF Research Database (Denmark)

Korsholm, Stephan E.; Schoeberl, Martin; Puffitsch, Wolfgang

2015-01-01

For real-time systems the whole execution stack needs to be time-predictable and analyzable for the worst-case execution time (WCET). This paper presents a time-predictable platform for safety-critical Java. The platform consists of (1) the Patmos processor, which is a time-predictable processor......; (2) a C compiler for Patmos with support for WCET analysis; (3) the HVM, which is a Java-to-C compiler; (4) the HVM-SCJ implementation which supports SCJ Level 0, 1, and 2 (for both single and multicore platforms); and (5) a WCET analysis tool. We show that real-time Java programs translated to C...... and compiled to a Patmos binary can be analyzed by the AbsInt aiT WCET analysis tool. To the best of our knowledge the presented system is the second WCET analyzable real-time Java system; and the first one on top of a RISC processor....

Stepping motor control processor reference manual. Volume I

International Nuclear Information System (INIS)

Holloway, F.W.; VanArsdall, P.J.; Suski, G.J.; Gant, R.G.; Rash, M.

1980-01-01

This manual is intended to serve several purposes. The first goal is to describe the capabilities and operation of the SMC processor package from an operator or user point of view. Secondly, the manual will describe in some detail the basic hardware elements and how they can be used effectively to implement a step motor control system. Practical information on the use, installation and checkout of the hardware set is presented in the following sections along with programming suggestions. Available related system software is described in this manual for reference and as an aid in understanding the system architecture. Section two presents an overview and operations manual of the SMC processor describing its composition and functional capabilities. Section three contains hardware descriptions in some detail for the LLL-designed hardware used in the SMC processor. Basic theory of operation and important features are explained

The Interface Between Redundant Processor Modules Of Safety Grade PLC Using Mass Storage DPRAM

International Nuclear Information System (INIS)

Hwang, Sung Jae; Song, Seong Hwan; No, Young Hun; Yun, Dong Hwa; Park, Gang Min; Kim, Min Gyu; Choi, Kyung Chul; Lee, Ui Taek

2010-01-01

Processor module of safety grade PLC (hereinafter called as POSAFE-Q) developed by POSCO ICT provides high reliability and safety. However, POSAFEQ would have suffered a malfunction when we think taking place of abnormal operation by exceptional environmental. POSAFE-Q would not able to conduct its function normally in such case. To prevent these situations, the necessity of redundant processor module has been raised. Therefore, redundant processor module, NCPU-2Q, has been developed which has not only functions of single processor module with high reliability and safety but also functions of redundant processor

The performances of coffee processors and coffee market in the Republic of Serbia

Directory of Open Access Journals (Sweden)

Nuševa Daniela

2017-01-01

Full Text Available The main aim of this paper is to investigate the performances of coffee processors and coffee market in Serbia based on the market concentration analysis, profitability analysis, and profitability determinants analysis. The research was based on the sample of 40 observations of coffee processing companies divided into two groups: large and small coffee processors. The results indicate that two large coffee processors have dominant market share. Even though the Serbian coffee market is an oligopolistic, profitability analysis indicates that small coffee processors have a significant better profitability ratio than large coffee processors. Furthermore, results show that profitability ratio is positively related to the inventory turnover and negatively related to the market share.

Hardware Synchronization for Embedded Multi-Core Processors

DEFF Research Database (Denmark)

Stoif, Christian; Schoeberl, Martin; Liccardi, Benito

2011-01-01

Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers should look with respect to the strict requirements in the field. We present the step from one to multiple cores in this paper, establi......Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers should look with respect to the strict requirements in the field. We present the step from one to multiple cores in this paper...

The microelectronic and photonic test bed RISC processor and DRAM memory stack experiments

International Nuclear Information System (INIS)

Clark, K.A.; Meehan, T.J.

1999-01-01

This paper reports on the on-orbit data obtained from the MPTB RISC Processor Experiment, containing three Integrated Device Technologies R3081 processors. During operations, nine SEUs were observed in the processors, and four SEUs were observed in the memory and/or support circuitry. (authors)

Digital image processing software system using an array processor

International Nuclear Information System (INIS)

Sherwood, R.J.; Portnoff, M.R.; Journeay, C.H.; Twogood, R.E.

1981-01-01

A versatile array processor-based system for general-purpose image processing was developed. At the heart of this system is an extensive, flexible software package that incorporates the array processor for effective interactive image processing. The software system is described in detail, and its application to a diverse set of applications at LLNL is briefly discussed. 4 figures, 1 table

Embedded Processor Based Automatic Temperature Control of VLSI Chips

Directory of Open Access Journals (Sweden)

Narasimha Murthy Yayavaram

2009-01-01

Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

GATEWAY Demonstrations: OLED Lighting in the Offices of Aurora Lighting Design, Inc.

Energy Technology Data Exchange (ETDEWEB)

Miller, Naomi J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

2016-03-31

At the offices of Aurora Lighting Design, Inc., in Grayslake, IL, the GATEWAY program conducted its first investigation involving OLED lighting. The project experienced several challenges, but also highlighted a number of promising attributes – which indicate that with continued improvements in efficacy, longevity, size, and flexibility, OLEDs could provide a new tool for creative and effective lighting.

Factors Affecting Student Academic Success in Gateway Courses at Northern Arizona University

Science.gov (United States)

Benford, Russell; Gess-Newsome, Julie

2006-01-01

Students in gateway business, math, and science courses at Northern Arizona University receive non-passing grades (grades of D, F, and W) at high rates. To identify possible trends in demographic groups that receive DFWs and to investigate why students receive DFWs in these courses, a student survey was administered to 719 students in 7 gateway…

gFEX, the ATLAS Calorimeter Level-1 Real Time Processor

CERN Document Server

AUTHOR|(SzGeCERN)759889; The ATLAS collaboration; Begel, Michael; Chen, Hucheng; Lanni, Francesco; Takai, Helio; Wu, Weihao

2016-01-01

The global feature extractor (gFEX) is a component of the Level-1 Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Vertex Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 276 optical fibers with the data transferred at the 40 MHz Large Hadron Collider (LHC) clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor Field-Programmable Gate Array (FPGAs), monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA ...

gFEX, the ATLAS Calorimeter Level 1 Real Time Processor

CERN Document Server

Tang, Shaochun; The ATLAS collaboration

2015-01-01

The global feature extractor (gFEX) is a component of the Level-1Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 264 optical fibers with the data transferred at the 40 MHz LHC clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor FPGAs, monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA has been designed for testing and verification. The performance ...

Scientific programming on massively parallel processor CP-PACS

International Nuclear Information System (INIS)

Boku, Taisuke

1998-01-01

The massively parallel processor CP-PACS takes various problems of calculation physics as the object, and it has been designed so that its architecture has been devised to do various numerical processings. In this report, the outline of the CP-PACS and the example of programming in the Kernel CG benchmark in NAS Parallel Benchmarks, version 1, are shown, and the pseudo vector processing mechanism and the parallel processing tuning of scientific and technical computation utilizing the three-dimensional hyper crossbar net, which are two great features of the architecture of the CP-PACS are described. As for the CP-PACS, the PUs based on RISC processor and added with pseudo vector processor are used. Pseudo vector processing is realized as the loop processing by scalar command. The features of the connection net of PUs are explained. The algorithm of the NPB version 1 Kernel CG is shown. The part that takes the time for processing most in the main loop is the product of matrix and vector (matvec), and the parallel processing of the matvec is explained. The time for the computation by the CPU is determined. As the evaluation of the performance, the evaluation of the time for execution, the short vector processing of pseudo vector processor based on slide window, and the comparison with other parallel computers are reported. (K.I.)

Investigation of Large Scale Cortical Models on Clustered Multi-Core Processors

Science.gov (United States)

2013-02-01

Playstation 3 with 6 available SPU cores outperforms the Intel Xeon processor (with 4 cores) by about 1.9 times for the HTM model and by 2.4 times...runtime breakdowns of the HTM and Dean models respectively on the Cell processor (on the Playstation 3) and the Intel Xeon processor ( 4 thread...YOUR FORM TO THE ABOVE ORGANIZATION. 1. REPORT DATE (DD-MM-YYYY) 2. REPORT TYPE 3. DATES COVERED (From - To) 4 . TITLE AND SUBTITLE 5a. CONTRACT NUMBER

Automation of ORIGEN2 calculations for the transuranic waste baseline inventory database using a pre-processor and a post-processor

International Nuclear Information System (INIS)

Liscum-Powell, J.

1997-06-01

The purpose of the work described in this report was to automate ORIGEN2 calculations for the Waste Isolation Pilot Plant (WIPP) Transuranic Waste Baseline Inventory Database (WTWBID); this was done by developing a pre-processor to generate ORIGEN2 input files from WWBID inventory files and a post-processor to remove excess information from the ORIGEN2 output files. The calculations performed with ORIGEN2 estimate the radioactive decay and buildup of various radionuclides in the waste streams identified in the WTWBID. The resulting radionuclide inventories are needed for performance assessment calculations for the WIPP site. The work resulted in the development of PreORG, which requires interaction with the user to generate ORIGEN2 input files on a site-by-site basis, and PostORG, which processes ORIGEN2 output into more manageable files. Both programs are written in the FORTRAN 77 computer language. After running PreORG, the user will run ORIGEN2 to generate the desired data; upon completion of ORIGEN2 calculations, the user can run PostORG to process the output to make it more manageable. All the programs run on a 386 PC or higher with a math co-processor or a computer platform running under VMS operating system. The pre- and post-processors for ORIGEN2 were generated for use with Rev. 1 data of the WTWBID and can also be used with Rev. 2 and 3 data of the TWBID (Transuranic Waste Baseline Inventory Database)

A design of a computer complex including vector processors

International Nuclear Information System (INIS)

Asai, Kiyoshi

1982-12-01

We, members of the Computing Center, Japan Atomic Energy Research Institute have been engaged for these six years in the research of adaptability of vector processing to large-scale nuclear codes. The research has been done in collaboration with researchers and engineers of JAERI and a computer manufacturer. In this research, forty large-scale nuclear codes were investigated from the viewpoint of vectorization. Among them, twenty-six codes were actually vectorized and executed. As the results of the investigation, it is now estimated that about seventy percents of nuclear codes and seventy percents of our total amount of CPU time of JAERI are highly vectorizable. Based on the data obtained by the investigation, (1)currently vectorizable CPU time, (2)necessary number of vector processors, (3)necessary manpower for vectorization of nuclear codes, (4)computing speed, memory size, number of parallel 1/0 paths, size and speed of 1/0 buffer of vector processor suitable for our applications, (5)necessary software and operational policy for use of vector processors are discussed, and finally (6)a computer complex including vector processors is presented in this report. (author)

Parallel computation for distributed parameter system-from vector processors to Adena computer

Energy Technology Data Exchange (ETDEWEB)

Nogi, T

1983-04-01

Research on advanced parallel hardware and software architectures for very high-speed computation deserves and needs more support and attention to fulfil its promise. Novel architectures for parallel processing are being made ready. Architectures for parallel processing can be roughly divided into two groups. One is a vector processor in which a single central processing unit involves multiple vector-arithmetic registers. The other is a processor array in which slave processors are connected to a host processor to perform parallel computation. In this review, the concept and data structure of the Adena (alternating-direction edition nexus array) architecture, which is conformable to distributed-parameter simulation algorithms, are described. 5 references.

Digital control card based on digital signal processor

International Nuclear Information System (INIS)

Hou Shigang; Yin Zhiguo; Xia Le

2008-01-01

A digital control card based on digital signal processor was developed. Two Freescale DSP-56303 processors were utilized to achieve 3 channels proportional- integral-differential regulations. The card offers high flexibility for 100 MeV cyclotron RF system development. It was used as feedback controller in low level radio frequency control prototype, with the feedback gain parameters continuously adjustable. By using high precision analog to digital converter with 500 kHz sampling rate, a regulation bandwidth of 20 kHz was achieved. (authors)

Treecode with a Special-Purpose Processor

Science.gov (United States)

Makino, Junichiro

1991-08-01

We describe an implementation of the modified Barnes-Hut tree algorithm for a gravitational N-body calculation on a GRAPE (GRAvity PipE) backend processor. GRAPE is a special-purpose computer for N-body calculations. It receives the positions and masses of particles from a host computer and then calculates the gravitational force at each coordinate specified by the host. To use this GRAPE processor with the hierarchical tree algorithm, the host computer must maintain a list of all nodes that exert force on a particle. If we create this list for each particle of the system at each timestep, the number of floating-point operations on the host and that on GRAPE would become comparable, and the increased speed obtained by using GRAPE would be small. In our modified algorithm, we create a list of nodes for many particles. Thus, the amount of the work required of the host is significantly reduced. This algorithm was originally developed by Barnes in order to vectorize the force calculation on a Cyber 205. With this algorithm, the computing time of the force calculation becomes comparable to that of the tree construction, if the GRAPE backend processor is sufficiently fast. The obtained speed-up factor is 30 to 50 for a RISC-based host computer and GRAPE-1A with a peak speed of 240 Mflops.

Token-Aware Completion Functions for Elastic Processor Verification

Directory of Open Access Journals (Sweden)

Sudarshan K. Srinivasan

2009-01-01

Full Text Available We develop a formal verification procedure to check that elastic pipelined processor designs correctly implement their instruction set architecture (ISA specifications. The notion of correctness we use is based on refinement. Refinement proofs are based on refinement maps, which—in the context of this problem—are functions that map elastic processor states to states of the ISA specification model. Data flow in elastic architectures is complicated by the insertion of any number of buffers in any place in the design, making it hard to construct refinement maps for elastic systems in a systematic manner. We introduce token-aware completion functions, which incorporate a mechanism to track the flow of data in elastic pipelines, as a highly automated and systematic approach to construct refinement maps. We demonstrate the efficiency of the overall verification procedure based on token-aware completion functions using six elastic pipelined processor models based on the DLX architecture.

A light hydrocarbon fuel processor producing high-purity hydrogen

Science.gov (United States)

Löffler, Daniel G.; Taylor, Kyle; Mason, Dylan

This paper discusses the design process and presents performance data for a dual fuel (natural gas and LPG) fuel processor for PEM fuel cells delivering between 2 and 8 kW electric power in stationary applications. The fuel processor resulted from a series of design compromises made to address different design constraints. First, the product quality was selected; then, the unit operations needed to achieve that product quality were chosen from the pool of available technologies. Next, the specific equipment needed for each unit operation was selected. Finally, the unit operations were thermally integrated to achieve high thermal efficiency. Early in the design process, it was decided that the fuel processor would deliver high-purity hydrogen. Hydrogen can be separated from other gases by pressure-driven processes based on either selective adsorption or permeation. The pressure requirement made steam reforming (SR) the preferred reforming technology because it does not require compression of combustion air; therefore, steam reforming is more efficient in a high-pressure fuel processor than alternative technologies like autothermal reforming (ATR) or partial oxidation (POX), where the combustion occurs at the pressure of the process stream. A low-temperature pre-reformer reactor is needed upstream of a steam reformer to suppress coke formation; yet, low temperatures facilitate the formation of metal sulfides that deactivate the catalyst. For this reason, a desulfurization unit is needed upstream of the pre-reformer. Hydrogen separation was implemented using a palladium alloy membrane. Packed beds were chosen for the pre-reformer and reformer reactors primarily because of their low cost, relatively simple operation and low maintenance. Commercial, off-the-shelf balance of plant (BOP) components (pumps, valves, and heat exchangers) were used to integrate the unit operations. The fuel processor delivers up to 100 slm hydrogen >99.9% pure with <1 ppm CO, <3 ppm CO 2. The

Soft-core dataflow processor architecture optimised for radar signal processing: Article

CSIR Research Space (South Africa)

Broich, R

2014-10-01

Full Text Available Current radar signal processors lack either performance or flexibility. Custom soft-core processors exhibit potential in high-performance signal processing applications, yet remain relatively unexplored in research literature. In this paper, we use...

GATEWAY Demonstrations: OLED Lighting in the Offices of DeJoy, Knauf & Blood, LLP

Energy Technology Data Exchange (ETDEWEB)

Miller, Naomi J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

2017-07-24

At the offices of the accounting firm of DeJoy, Knauf & Blood, LLP in Rochester, NY, the GATEWAY program evaluated a new lighting system that incorporates a number of different OLED luminaires. Evaluation of the OLED products included efficacy performance, field measurements of panel color, flicker measurements, and staff feedback.

Merged ozone profiles from four MIPAS processors

Science.gov (United States)

Laeng, Alexandra; von Clarmann, Thomas; Stiller, Gabriele; Dinelli, Bianca Maria; Dudhia, Anu; Raspollini, Piera; Glatthor, Norbert; Grabowski, Udo; Sofieva, Viktoria; Froidevaux, Lucien; Walker, Kaley A.; Zehner, Claus

2017-04-01

The Michelson Interferometer for Passive Atmospheric Sounding (MIPAS) was an infrared (IR) limb emission spectrometer on the Envisat platform. Currently, there are four MIPAS ozone data products, including the operational Level-2 ozone product processed at ESA, with the scientific prototype processor being operated at IFAC Florence, and three independent research products developed by the Istituto di Fisica Applicata Nello Carrara (ISAC-CNR)/University of Bologna, Oxford University, and the Karlsruhe Institute of Technology-Institute of Meteorology and Climate Research/Instituto de Astrofísica de Andalucía (KIT-IMK/IAA). Here we present a dataset of ozone vertical profiles obtained by merging ozone retrievals from four independent Level-2 MIPAS processors. We also discuss the advantages and the shortcomings of this merged product. As the four processors retrieve ozone in different parts of the spectra (microwindows), the source measurements can be considered as nearly independent with respect to measurement noise. Hence, the information content of the merged product is greater and the precision is better than those of any parent (source) dataset. The merging is performed on a profile per profile basis. Parent ozone profiles are weighted based on the corresponding error covariance matrices; the error correlations between different profile levels are taken into account. The intercorrelations between the processors' errors are evaluated statistically and are used in the merging. The height range of the merged product is 20-55 km, and error covariance matrices are provided as diagnostics. Validation of the merged dataset is performed by comparison with ozone profiles from ACE-FTS (Atmospheric Chemistry Experiment-Fourier Transform Spectrometer) and MLS (Microwave Limb Sounder). Even though the merging is not supposed to remove the biases of the parent datasets, around the ozone volume mixing ratio peak the merged product is found to have a smaller (up to 0.1 ppmv

Keystone Business Models for Network Security Processors

Directory of Open Access Journals (Sweden)

Arthur Low

2013-07-01

Full Text Available Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor” models nor the silicon intellectual-property licensing (“IP-licensing” models allow small technology companies to successfully compete. This article describes an alternative approach that produces an ongoing stream of novel network security processors for niche markets through continuous innovation by both large and small companies. This approach, referred to here as the "business ecosystem model for network security processors", includes a flexible and reconfigurable technology platform, a “keystone” business model for the company that maintains the platform architecture, and an extended ecosystem of companies that both contribute and share in the value created by innovation. New opportunities for business model innovation by participating companies are made possible by the ecosystem model. This ecosystem model builds on: i the lessons learned from the experience of the first author as a senior integrated circuit architect for providers of public-key cryptography solutions and as the owner of a semiconductor startup, and ii the latest scholarly research on technology entrepreneurship, business models, platforms, and business ecosystems. This article will be of interest to all technology entrepreneurs, but it will be of particular interest to owners of small companies that provide security solutions and to specialized security professionals seeking to launch their own companies.

European Film Gateway projekt EFG 1914 Esimesest maailmasõjast / Ivi Tomingas

Index Scriptorium Estoniae

Tomingas, Ivi

2014-01-01

Saja aasta möödumise puhul Esimesest maailmasõjast kutsus Euroopa Komisjon ellu European Film Gateway projekti EFG 1914. Projekti tulemusena on avalikkusele kättesaadav 660 tundi digiteeritud filme ja 5500 plakatit, fotot ja dokumenti. Nendega saab tutvuda aadressidel http://project.efg1914.eu ja http://www.europeanfilmgateway.eu/content/efg1914-project. Tekstile lisatud väike valik Eesti arhiivides leiduvast 2230-st projektiteemalisest fotost

Demonstration of two-qubit algorithms with a superconducting quantum processor.

Science.gov (United States)

DiCarlo, L; Chow, J M; Gambetta, J M; Bishop, Lev S; Johnson, B R; Schuster, D I; Majer, J; Blais, A; Frunzio, L; Girvin, S M; Schoelkopf, R J

2009-07-09

Quantum computers, which harness the superposition and entanglement of physical states, could outperform their classical counterparts in solving problems with technological impact-such as factoring large numbers and searching databases. A quantum processor executes algorithms by applying a programmable sequence of gates to an initialized register of qubits, which coherently evolves into a final state containing the result of the computation. Building a quantum processor is challenging because of the need to meet simultaneously requirements that are in conflict: state preparation, long coherence times, universal gate operations and qubit readout. Processors based on a few qubits have been demonstrated using nuclear magnetic resonance, cold ion trap and optical systems, but a solid-state realization has remained an outstanding challenge. Here we demonstrate a two-qubit superconducting processor and the implementation of the Grover search and Deutsch-Jozsa quantum algorithms. We use a two-qubit interaction, tunable in strength by two orders of magnitude on nanosecond timescales, which is mediated by a cavity bus in a circuit quantum electrodynamics architecture. This interaction allows the generation of highly entangled states with concurrence up to 94 per cent. Although this processor constitutes an important step in quantum computing with integrated circuits, continuing efforts to increase qubit coherence times, gate performance and register size will be required to fulfil the promise of a scalable technology.

Advanced Avionics and Processor Systems for a Flexible Space Exploration Architecture

Science.gov (United States)

Keys, Andrew S.; Adams, James H.; Smith, Leigh M.; Johnson, Michael A.; Cressler, John D.

2010-01-01

The Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to develop advanced avionic and processor technologies anticipated to be used by NASA s currently evolving space exploration architectures. The AAPS project is a part of the Exploration Technology Development Program, which funds an entire suite of technologies that are aimed at enabling NASA s ability to explore beyond low earth orbit. NASA s Marshall Space Flight Center (MSFC) manages the AAPS project. AAPS uses a broad-scoped approach to developing avionic and processor systems. Investment areas include advanced electronic designs and technologies capable of providing environmental hardness, reconfigurable computing techniques, software tools for radiation effects assessment, and radiation environment modeling tools. Near-term emphasis within the multiple AAPS tasks focuses on developing prototype components using semiconductor processes and materials (such as Silicon-Germanium (SiGe)) to enhance a device s tolerance to radiation events and low temperature environments. As the SiGe technology will culminate in a delivered prototype this fiscal year, the project emphasis shifts its focus to developing low-power, high efficiency total processor hardening techniques. In addition to processor development, the project endeavors to demonstrate techniques applicable to reconfigurable computing and partially reconfigurable Field Programmable Gate Arrays (FPGAs). This capability enables avionic architectures the ability to develop FPGA-based, radiation tolerant processor boards that can serve in multiple physical locations throughout the spacecraft and perform multiple functions during the course of the mission. The individual tasks that comprise AAPS are diverse, yet united in the common endeavor to develop electronics capable of operating within the harsh environment of space. Specifically, the AAPS tasks for

OLYMPUS system and development of its pre-processor

International Nuclear Information System (INIS)

Okamoto, Masao; Takeda, Tatsuoki; Tanaka, Masatoshi; Asai, Kiyoshi; Nakano, Koh.

1977-08-01

The OLYMPUS SYSTEM developed by K. V. Roverts et al. was converted and introduced in computer system FACOM 230/75 of the JAERI Computing Center. A pre-processor was also developed for the OLYMPUS SYSTEM. The OLYMPUS SYSTEM is very useful for development, standardization and exchange of programs in thermonuclear fusion research and plasma physics. The pre-processor developed by the present authors is not only essential for the JAERI OLYMPUS SYSTEM, but also useful in manipulation, creation and correction of program files. (auth.)

A fast processor for di-lepton triggers

CERN Document Server

Kostarakis, P; Barsotti, E; Conetti, S; Cox, B; Enagonio, J; Haldeman, M; Haynes, W; Katsanevas, S; Kerns, C; Lebrun, P; Smith, H; Soszyniski, T; Stoffel, J; Treptow, K; Turkot, F; Wagner, R

1981-01-01

As a new application of the Fermilab ECL-CAMAC logic modules a fast trigger processor was developed for Fermilab experiment E-537, aiming to measure the higher mass di-muon production by antiprotons. The processor matches the hit information received from drift chambers and scintillation counters, to find candidate muon tracks and determine their directions and momenta. The tracks are then paired to compute an invariant mass: when the computed mass falls within the desired range, the event is accepted. The process is accomplished in times of 5 to 10 microseconds, while achieving a trigger rate reduction of up to a factor of ten. (5 refs).

Time Manager Software for a Flight Processor

Science.gov (United States)

Zoerne, Roger

2012-01-01

Data analysis is a process of inspecting, cleaning, transforming, and modeling data to highlight useful information and suggest conclusions. Accurate timestamps and a timeline of vehicle events are needed to analyze flight data. By moving the timekeeping to the flight processor, there is no longer a need for a redundant time source. If each flight processor is initially synchronized to GPS, they can freewheel and maintain a fairly accurate time throughout the flight with no additional GPS time messages received. How ever, additional GPS time messages will ensure an even greater accuracy. When a timestamp is required, a gettime function is called that immediately reads the time-base register.

Bulk-memory processor for data acquisition

International Nuclear Information System (INIS)

Nelson, R.O.; McMillan, D.E.; Sunier, J.W.; Meier, M.; Poore, R.V.

1981-01-01

To meet the diverse needs and data rate requirements at the Van de Graaff and Weapons Neutron Research (WNR) facilities, a bulk memory system has been implemented which includes a fast and flexible processor. This bulk memory processor (BMP) utilizes bit slice and microcode techniques and features a 24 bit wide internal architecture allowing direct addressing of up to 16 megawords of memory and histogramming up to 16 million counts per channel without overflow. The BMP is interfaced to the MOSTEK MK 8000 bulk memory system and to the standard MODCOMP computer I/O bus. Coding for the BMP both at the microcode level and with macro instructions is supported. The generalized data acquisition system has been extended to support the BMP in a manner transparent to the user

RISC Processors and High Performance Computing

Science.gov (United States)

Bailey, David H.; Saini, Subhash; Craw, James M. (Technical Monitor)

1995-01-01

This tutorial will discuss the top five RISC microprocessors and the parallel systems in which they are used. It will provide a unique cross-machine comparison not available elsewhere. The effective performance of these processors will be compared by citing standard benchmarks in the context of real applications. The latest NAS Parallel Benchmarks, both absolute performance and performance per dollar, will be listed. The next generation of the NPB will be described. The tutorial will conclude with a discussion of future directions in the field. Technology Transfer Considerations: All of these computer systems are commercially available internationally. Information about these processors is available in the public domain, mostly from the vendors themselves. The NAS Parallel Benchmarks and their results have been previously approved numerous times for public release, beginning back in 1991.

Reduced power processor requirements for the 30-cm diameter HG ion thruster

Science.gov (United States)

Rawlin, V. K.

1979-01-01

The characteristics of power processors strongly impact the overall performance and cost of electric propulsion systems. A program was initiated to evaluate simplifications of the thruster-power processor interface requirements. The power processor requirements are mission dependent with major differences arising for those missions which require a nearly constant thruster operating point (typical of geocentric and some inbound planetary missions) and those requiring operation over a large range of input power (such as outbound planetary missions). This paper describes the results of tests which have indicated that as many as seven of the twelve power supplies may be eliminated from the present Functional Model Power Processor used with 30-cm diameter Hg ion thrusters.

Optical gateway for intelligent buildings: a new open-up window to the optical fibre sensors market?

Science.gov (United States)

Fernandez-Valdivielso, Carlos; Matias, Ignacio R.; Arregui, Francisco J.; Bariain, Candido; Lopez-Amo, Manuel

2004-06-01

This paper presents the first optical fiber sensor gateway for integrating these special measurement devices in Home Automation Systems, concretely in those buildings that use the KNX European Intelligent Buildings Standard.

Sensitometric Control of Automatic Processors in a Hospital Center : Retrospective Study

International Nuclear Information System (INIS)

Lobato Busto, R.; Pombar Camean, M.

1992-01-01

This paper analyses the results obtained between February (1990) and July (1991) of the sensitometric control of the seven automatic processors which are in Hospital General de Galicia-Clinico Universitario (Santiago de Compostela). The deviations with regard to the reference values of each processor, permitting the precocious detection of disturbances before being revealed by the image, were analysed. In this analysis, it was achieved that the days in which the automatic processors were out of standing only varied between 2.3% and 5% from the checked days. (author)

Rational calculation accuracy in acousto-optical matrix-vector processor

Science.gov (United States)

Oparin, V. V.; Tigin, Dmitry V.

1994-01-01

The high speed of parallel computations for a comparatively small-size processor and acceptable power consumption makes the usage of acousto-optic matrix-vector multiplier (AOMVM) attractive for processing of large amounts of information in real time. The limited accuracy of computations is an essential disadvantage of such a processor. The reduced accuracy requirements allow for considerable simplification of the AOMVM architecture and the reduction of the demands on its components.

Post-silicon and runtime verification for modern processors

CERN Document Server

Wagner, Ilya

2010-01-01

The purpose of this book is to survey the state of the art and evolving directions in post-silicon and runtime verification. The authors start by giving an overview of the state of the art in verification, particularly current post-silicon methodologies in use in the industry, both for the domain of processor pipeline design and for memory subsystems. They then dive into the presentation of several new post-silicon verification solutions aimed at boosting the verification coverage of modern processors, dedicating several chapters to this topic. The presentation of runtime verification solution

Ring-array processor distribution topology for optical interconnects

Science.gov (United States)

Li, Yao; Ha, Berlin; Wang, Ting; Wang, Sunyu; Katz, A.; Lu, X. J.; Kanterakis, E.

1992-01-01

The existing linear and rectangular processor distribution topologies for optical interconnects, although promising in many respects, cannot solve problems such as clock skews, the lack of supporting elements for efficient optical implementation, etc. The use of a ring-array processor distribution topology, however, can overcome these problems. Here, a study of the ring-array topology is conducted with an aim of implementing various fast clock rate, high-performance, compact optical networks for digital electronic multiprocessor computers. Practical design issues are addressed. Some proof-of-principle experimental results are included.

Reconfigurable lattice mesh designs for programmable photonic processors.

Science.gov (United States)

Pérez, Daniel; Gasulla, Ivana; Capmany, José; Soref, Richard A

2016-05-30

We propose and analyse two novel mesh design geometries for the implementation of tunable optical cores in programmable photonic processors. These geometries are the hexagonal and the triangular lattice. They are compared here to a previously proposed square mesh topology in terms of a series of figures of merit that account for metrics that are relevant to on-chip integration of the mesh. We find that that the hexagonal mesh is the most suitable option of the three considered for the implementation of the reconfigurable optical core in the programmable processor.

Interactive high-resolution isosurface ray casting on multicore processors.

Science.gov (United States)

Wang, Qin; JaJa, Joseph

2008-01-01

We present a new method for the interactive rendering of isosurfaces using ray casting on multi-core processors. This method consists of a combination of an object-order traversal that coarsely identifies possible candidate 3D data blocks for each small set of contiguous pixels, and an isosurface ray casting strategy tailored for the resulting limited-size lists of candidate 3D data blocks. While static screen partitioning is widely used in the literature, our scheme performs dynamic allocation of groups of ray casting tasks to ensure almost equal loads among the different threads running on multi-cores while maintaining spatial locality. We also make careful use of memory management environment commonly present in multi-core processors. We test our system on a two-processor Clovertown platform, each consisting of a Quad-Core 1.86-GHz Intel Xeon Processor, for a number of widely different benchmarks. The detailed experimental results show that our system is efficient and scalable, and achieves high cache performance and excellent load balancing, resulting in an overall performance that is superior to any of the previous algorithms. In fact, we achieve an interactive isosurface rendering on a 1024(2) screen for all the datasets tested up to the maximum size of the main memory of our platform.

77 FR 124 - Biological Processors of Alabama; Decatur, Morgan County, AL; Notice of Settlement

Science.gov (United States)

2012-01-03

... ENVIRONMENTAL PROTECTION AGENCY [FRL-9612-9] Biological Processors of Alabama; Decatur, Morgan... reimbursement of past response costs concerning the Biological Processors of Alabama Superfund Site located in... Ms. Paula V. Painter. Submit your comments by Site name Biological Processors of Alabama Superfund...

Analisa Link Balancing dan Failover 2 Provider Menggunakan Border Gateway Protocol (BGP Pada Router Cisco 7606s

Directory of Open Access Journals (Sweden)

Darmawan Darmawan

2017-12-01

Full Text Available Sistem link balancing dan failover merupakan salah satu cara yang dapat digunakan untuk membagi beban traffic dari client pada beberapa koneksi internet, dapat sebagai backup/failover ketika salah satu koneksi internet mengalami gangguan. Pada perancangan sistem ini digunakan 4 buah router, yaitu terdiri dari satu router cisco 7606s yang berfungsi sebagai main gateway yang mengatur sistem failover dan link balancing menuju ke 2 buah router mikrotik RB951G 2HND sebagai jalur kedua ISP dan router mikrotik CCR1036-12G-4S sebagai gateway dari FTP server. Tiap router tersebut memiliki Autonomus System Number yang berbeda yang saling berkomunikasi menggunakan routing Border Gateway Protocol (BGP. Dari hasil pengujian penggunaan link balancing dengan besar bandwidth 10 mb/s, didapatkan throughput 794 KB/s, sedangkan yang tidak menggunakan link balancing dengan bandwidth sebesar 20 mb/s, didapatkan nilai throughput hanya 136 KB/s. Penggunaan link balancing dapat memanfaatkan besar bandwidth yang ada dan meningkatkan throughput, dibandingkan tidak menggunkan link balancing. Pada pengujian delay, menggunakan link balancing hanya delay 1.24 ms, sedangkan tidak menggunakan metode link balancing mencapai 8.19 ms. Nilai latency didapatkan 12 ms untuk menggunakan link balancing sedangkan tidak menggunkan metode link balancing mencapai 1896 ms.

On the Behavior of ECN/RED Gateways Under a Large Number of TCP Flows: Limit Theorems

National Research Council Canada - National Science Library

Tinnakornsrisuphap, Peerapol; Makowski, Armand M

2005-01-01

.... As the number of competing flows becomes large, the asymptotic queue behavior at the gateway can be described by a simple recursion and the throughput behavior of individual TCP flows becomes asymptotically independent...

“Gateway hypothesis” and early drug use: Additional findings from tracking a population-based sample of adolescents to adulthood

Directory of Open Access Journals (Sweden)

Stephen Nkansah-Amankra

2016-12-01

Full Text Available To evaluate the consistency of the relationship between early drug use in adolescence and illegal drug use in adulthood as proposed in the “gateway theory” and to determine whether pre-existing depressive symptoms modifies this relationship. We used contractual data from the National Longitudinal Study of Adolescent to Adult health data spanning a 14 year period. We assessed the relationship between gateway drugs at baseline (age 11–20 years and drug use in adulthood using generalized estimating equation (GEE regression models. Gateways drugs used in early adolescence were significantly associated with marijuana use, illegal drugs and cocaine in older adolescence, but over time these relationships were not consistent in adulthood. Changes in the pattern of psychoactive drug use were important predictors of drug use in adulthood. A history of higher depressive symptoms was associated with higher frequencies of psychoactive drug use over time. Users of mental health services in adolescence were less likely to use drugs in older adolescence and in adulthood. Relationships between early drug use and later drug use in adulthood cannot be solely explained by the gateway hypothesis. Collectively, adolescent drug prevention and treatment programs should apply theory-based and evidence-proven multisectoral intervention strategies rather than providing a brief counseling on individual's behaviors. This evidence should include understanding that changes in behavior should involve broader analyses of the underlying social context for drug use and in particular the role of the community social norms in driving a group's behaviors.

Physician Acceptance of Gateway to Care at Irwin Army Community Hospital

Science.gov (United States)

1992-07-27

frontier cavalry post once commanded by General George Armstrong Custer. Today it is the home of almost 20,000 soldiers of the Big Red One, First Infantry...especially important for the future. Physicians, as key "players" in healthcare organizations, are also key to the success of Gateway to Care. Kotler and...research (3rd ed.). New York: Holt. Physician Acceptance 32 Kotler , P., & Clarke, R. (1987). Marketing for health care organizations. Englewood Cliffs

HAPS Gateway Link in the 5850-7075 MHz and Coexistence with Fixed Satellite Service

Directory of Open Access Journals (Sweden)

M. Ahmed

2013-09-01

Full Text Available Gateway link is essential to connect HAPS platform to terrestrial based networks. This crucial link is incorporated in HAPS fixed service spectrum allocation in considerably high frequencies, renders the link for more attenuations by atmospheric gases, and rain effects, especially when the regional climate is not favorable. However, under the agenda item 1.20 of World Radio Conference-2012 (WRC-12 new HAPS allocation in the 5850-7075 MHz band is proposed. Although, spectrum features are incomparably reliable, on the contrary, Fixed Satellite Service (FSS uplink transmissions will have signal levels much higher than those in HAPS systems and have the potential for causing interference at the HAPS gateway receiver. In this article a key aspect of co-channel interference phenomena is investigated to facilitate optimum frequency sharing in the band in question. By proposing mitigation techniques and statistical method this generic prediction model enhances the capability of the HAPS spectrum sharing and provides flexibility in spectrum planning for different fixed services.

A PICKSC Science Gateway for enabling the common plasma physicist to run kinetic software

Science.gov (United States)

Hu, Q.; Winjum, B. J.; Zonca, A.; Youn, C.; Tsung, F. S.; Mori, W. B.

2017-10-01

Computer simulations offer tremendous opportunities for studying plasmas, ranging from simulations for students that illuminate fundamental educational concepts to research-level simulations that advance scientific knowledge. Nevertheless, there is a significant hurdle to using simulation tools. Users must navigate codes and software libraries, determine how to wrangle output into meaningful plots, and oftentimes confront a significant cyberinfrastructure with powerful computational resources. Science gateways offer a Web-based environment to run simulations without needing to learn or manage the underlying software and computing cyberinfrastructure. We discuss our progress on creating a Science Gateway for the Particle-in-Cell and Kinetic Simulation Software Center that enables users to easily run and analyze kinetic simulations with our software. We envision that this technology could benefit a wide range of plasma physicists, both in the use of our simulation tools as well as in its adaptation for running other plasma simulation software. Supported by NSF under Grant ACI-1339893 and by the UCLA Institute for Digital Research and Education.

Monte Carlo photon transport on shared memory and distributed memory parallel processors

International Nuclear Information System (INIS)

Martin, W.R.; Wan, T.C.; Abdel-Rahman, T.S.; Mudge, T.N.; Miura, K.

1987-01-01

Parallelized Monte Carlo algorithms for analyzing photon transport in an inertially confined fusion (ICF) plasma are considered. Algorithms were developed for shared memory (vector and scalar) and distributed memory (scalar) parallel processors. The shared memory algorithm was implemented on the IBM 3090/400, and timing results are presented for dedicated runs with two, three, and four processors. Two alternative distributed memory algorithms (replication and dispatching) were implemented on a hypercube parallel processor (1 through 64 nodes). The replication algorithm yields essentially full efficiency for all cube sizes; with the 64-node configuration, the absolute performance is nearly the same as with the CRAY X-MP. The dispatching algorithm also yields efficiencies above 80% in a large simulation for the 64-processor configuration

Time Dependent Hartree Fock Equation: Gateway to Nonequilibrium Plasmas

International Nuclear Information System (INIS)

Dufty, James W.

2007-01-01

This is the Final Technical Report for DE-FG02-2ER54677 award 'Time Dependent Hartree Fock Equation - Gateway to Nonequilibrium Plasmas'. Research has focused on the nonequilibrium dynamics of electrons in the presence of ions, both via basic quantum theory and via semi-classical molecular dynamics (MD) simulation. In addition, fundamental notions of dissipative dynamics have been explored for models of grains and dust, and for scalar fields (temperature) in turbulent edge plasmas. The specific topics addressed were Quantum Kinetic Theory for Metallic Clusters, Semi-classical MD Simulation of Plasmas , and Effects of Dissipative Dynamics.

Very Long Instruction Word Processors

Indian Academy of Sciences (India)

Explicitly Parallel Instruction Computing (EPIC) is an instruction processing paradigm that has been in the spot- light due to its adoption by the next generation of Intel. Processors starting with the IA-64. The EPIC processing paradigm is an evolution of the Very Long Instruction. Word (VLIW) paradigm. This article gives an ...

User manual Dieka PreProcessor

NARCIS (Netherlands)

Valkering, Kasper

2000-01-01

This is the user manual belonging to the Dieka-PreProcessor. This application was written by Wenhua Cao and revised and expanded by Kasper Valkering. The aim of this preproccesor is to be able to draw and mesh extrusion dies in ProEngineer, and do the FE-calculation in Dieka. The preprocessor makes

Evaluation of the Intel Westmere-EX server processor

CERN Document Server

Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

2011-01-01

One year after the arrival of the Intel Xeon 7500 systems (“Nehalem-EX”), CERN openlab is presenting a set of benchmark results obtained when running on the new Xeon E7-4870 Processors, representing the “Westmere-EX” family. A modern 4-socket, 40-core system is confronted with the previous generation of expandable (“EX”) platforms, represented by a 4-socket, 32-core Intel Xeon X7560 based system – both being “top of the line” systems. Benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores via Symmetric MultiThreading (SMT), the cache sizes available, the configured memory topology, as well as the power configuration if throughput per watt is to be measured. As in previous activities, we have tried to do a good job of comparing like with like. In a “top of the line” comparison based on the HEPSPEC06 benchmark, the “We...

3081/E processor and its on-line use

International Nuclear Information System (INIS)

Rankin, P.; Bricaud, B.; Gravina, M.

1985-05-01

The 3081/E is a second generation emulator of a mainframe IBM. One of it's applications will be to form part of the data acquisition system of the upgraded Mark II detector for data taking at the SLAC linear collider. Since the processor does not have direct connections to I/O devices a FASTBUS interface will be provided to allow communication with both SLAC Scanner Processors (which are responsible for the accumulation of data at a crate level) and the experiment's VAX 8600 mainframe. The 3081/E's will supply a significant amount of on-line computing power to the experiment (a single 3081/E is equivalent to 4 to 5 VAX 11/780's). A major advantage of the 3081/E is that program development can be done on an IBM mainframe (such as the one used for off-line analysis) which gives the programmer access to a full range of debugging tools. The processor's performance can be continually monitored by comparison of the results obtained using it to those given when the same program is run on an IBM computer. 9 refs

Linking Gateway Technical College with Workforce Development: The SC Johnson-A Family Company Story.

Science.gov (United States)

Knudson, Edward

2004-01-01

Seven years ago, SC Johnson--A Family Company approached Gateway Technical College with a need to further strengthen their incumbent workforce's technical training and education. Retirements, brain drain, and competition for technical expertise were the forces driving SC Johnson to develop a comprehensive, flexible, and timely workplace education…

Los Angeles-Gateway Freight Advanced Traveler Information System : final system design and architecture for FRATIS prototype.

Science.gov (United States)

2013-05-01

This Final Architecture and Design report has been prepared to describe the structure and design of all the system : components for the LA-Gateway FRATIS Demonstration Project. More specifically, this document provides: : Detailed descriptions of...

GATEWAY Demonstrations: Trial Demonstration of Area Lighting Retrofit, Yuma Border Patrol, Yuma, Arizona

Energy Technology Data Exchange (ETDEWEB)

Wilkerson, A. M. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); McCullough, J. J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

2014-12-31

Along the Yuma Sector Border Patrol Area in Yuma, Arizona, the GATEWAY program conducted a trial demonstration in which the incumbent quartz metal halide area lighting was replaced with LED at three pole locations at the Yuma Sector Border Patrol Area in Yuma, Arizona. The retrofit was documented to better understand LED technology performance in high-temperature environments.

An intercomparison of Canadian external dosimetry processors for radiation protection

International Nuclear Information System (INIS)

1989-10-01

The five Canadian external dosimetry processors have participated in a two-stage intercomparison. The first stage involved dosimeters to known radiation fields under controlled laboratory conditions. The second stage involved exposing dosimeters to radiation fields in power reactor working environments. The results for each stage indicated the dose reported by each processor relative to an independently determined dose and relative to the others. The results of the intercomparisons confirm the original supposition: namely that the average differences in reported dose among five processors are much less than the uncertainty limits recommended by the ICRP. This report provides a description of the experimental methods as well as a discussion of the results for each stage. The report also includes a set of recommendations

A high-speed analog neural processor

NARCIS (Netherlands)

Masa, P.; Masa, Peter; Hoen, Klaas; Hoen, Klaas; Wallinga, Hans

1994-01-01

Targeted at high-energy physics research applications, our special-purpose analog neural processor can classify up to 70 dimensional vectors within 50 nanoseconds. The decision-making process of the implemented feedforward neural network enables this type of computation to tolerate weight

Processor farming in two-level analysis of historical bridge

Science.gov (United States)

Krejčí, T.; Kruis, J.; Koudelka, T.; Šejnoha, M.

2017-11-01

This contribution presents a processor farming method in connection with a multi-scale analysis. In this method, each macro-scopic integration point or each finite element is connected with a certain meso-scopic problem represented by an appropriate representative volume element (RVE). The solution of a meso-scale problem provides then effective parameters needed on the macro-scale. Such an analysis is suitable for parallel computing because the meso-scale problems can be distributed among many processors. The application of the processor farming method to a real world masonry structure is illustrated by an analysis of Charles bridge in Prague. The three-dimensional numerical model simulates the coupled heat and moisture transfer of one half of arch No. 3. and it is a part of a complex hygro-thermo-mechanical analysis which has been developed to determine the influence of climatic loading on the current state of the bridge.

Array processors: an introduction to their architecture, software, and applications in nuclear medicine

International Nuclear Information System (INIS)

King, M.A.; Doherty, P.W.; Rosenberg, R.J.; Cool, S.L.

1983-01-01

Array processors are ''number crunchers'' that dramatically enhance the processing power of nuclear medicine computer systems for applicatons dealing with the repetitive operations involved in digital image processing of large segments of data. The general architecture and the programming of array processors are introduced, along with some applications of array processors to the reconstruction of emission tomographic images, digital image enhancement, and functional image formation

Direct Characterization of Comets and Asteroids via Cosmic Dust Analysis from the Deep Space Gateway

Science.gov (United States)

Fries, M.; Fisher, K.

2018-02-01

The Deep Space Gateway can allow direct analysis of dust from over a dozen comets, using an instrument similar to the successful Cassini Dust Analyzer (CDA). Long-term measurements are preferred. Compositions of over a dozen asteroids and comets can be obtained.

Accessibility: global gateway to health literacy.

Science.gov (United States)

Perlow, Ellen

2010-01-01

Health literacy, cited as essential to achieving Healthy People 2010's goals to "increase quality and years of healthy life" and to "eliminate health disparities," is defined by Healthy People as "the degree to which individuals have the capacity to obtain, process, and understand basic health information and services needed to make appropriate health decisions." Accessibility, by definition, the aforementioned "capacity to obtain," thus is health literacy's primary prerequisite. Accessibility's designation as the global gateway to health literacy is predicated also on life's realities: global aging and climate change, war and terrorism, and life-extending medical and technological advances. People with diverse access needs are health professionals' raison d'être. However, accessibility, consummately cross-cultural and universal, is virtually absent as a topic of health promotion and practice research and scholarly discussion of health literacy and equity. A call to action to place accessibility in its rightful premier position on the profession's agenda is issued.

Service interoperability through advanced media gateways

CERN Document Server

van der Meer, S

2000-01-01

The convergence of telecommunications systems and the Internet causes a variety of concepts for service integration. The focus of the recent research studies and the work of several standardization bodies lies mostly on the interworking of services and the universal service access from end-user systems including both fixed and wireless terminals. All approaches are driven by the concept of providing several technologies to users by keeping the peculiarity of each service alive. But, developments should not only concentrate on media adaptation between VoIP and PSTN, but also consider the adaptation among completely different types of applications as for example E- mail, facsimile, or voice. Unified messaging, which is an already accepted service on the market, provides solutions for conversions of different application protocols into each other. The functionality of converting one medium into another is implemented here in so-called media gateways. This paper provides an overview of the current developments in...

Smart home design for electronic devices monitoring based wireless gateway network using cisco packet tracer

Science.gov (United States)

Sihombing, Oloan; Zendrato, Niskarto; Laia, Yonata; Nababan, Marlince; Sitanggang, Delima; Purba, Windania; Batubara, Diarmansyah; Aisyah, Siti; Indra, Evta; Siregar, Saut

2018-04-01

In the era of technological development today, the technology has become the need for the life of today's society. One is needed to create a smart home in turning on and off electronic devices via smartphone. So far in turning off and turning the home electronic device is done by pressing the switch or remote button, so in control of electronic device control less effective. The home smart design is done by simulation concept by testing system, network configuration, and wireless home gateway computer network equipment required by a smart home network on cisco packet tracer using Internet Thing (IoT) control. In testing the IoT home network wireless network gateway system, multiple electronic devices can be controlled and monitored via smartphone based on predefined configuration conditions. With the Smart Ho me can potentially increase energy efficiency, decrease energy usage costs, control electronics and change the role of residents.

The Danish real-time SAR processor: first results

DEFF Research Database (Denmark)

Dall, Jørgen; Jørgensen, Jørn Hjelm; Netterstrøm, Anders

1993-01-01

A real-time processor (RTP) for the Danish airborne Synthetic Aperture Radar (SAR) has been designed and constructed at the Electromagnetics Institute. The implementation was completed in mid 1992, and since then the RTP has been operated successfully on several test and demonstration flights....... The processor is capable of focusing the entire swath of the raw SAR data into full resolution, and depending on the choice made by the on-board operator, either a high resolution one-look zoom image or a spatially multilooked overview image is displayed. After a brief design review, the paper addresses various...

Wavelength-encoded OCDMA system using opto-VLSI processors.

Science.gov (United States)

Aljada, Muhsen; Alameh, Kamal

2007-07-01

We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

Wavelength-encoded OCDMA system using opto-VLSI processors

Science.gov (United States)

Aljada, Muhsen; Alameh, Kamal

2007-07-01

We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

Evaluating the Effectiveness of IP Hopping via an Address Routing Gateway

Science.gov (United States)

2013-03-01

supportable? How does latency affect this? • Is ARG stable when presented with corrupt, malformed , and/or replayed packets? Each question is tested in a...is the heart of ARG. It maintains the state of the gateways (e.g., keys, hop intervals, times) it knows about and transfers packets to and from the...4. Is ARG stable when presented with corrupt, malformed , or replayed packets? It is hypothesized that ARG correctly classifies 99% of traffic it

Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures

Science.gov (United States)

Manolakos, Elias S.

2015-01-01

Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub. PMID:26605332

Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures.

Science.gov (United States)

Sharma, Anuj; Manolakos, Elias S

2015-01-01

Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub.

A Squandered Resource: The Divestment of Mexican Parental Involvement in a New Gateway State

Science.gov (United States)

Petrone, Eleanor

2016-01-01

Parental involvement plays an important role in the academic success of children. Schools in new gateway states where there has not been a longstanding tradition of immigration often lack the cultural knowledge and linguistic resources necessary to serve immigrant youth and their families effectively. By examining the experiences of Mexican…

ARM Processor Based Embedded System for Remote Data Acquisition

OpenAIRE

Raj Kumar Tiwari; Santosh Kumar Agrahari

2014-01-01

The embedded systems are widely used for the data acquisition. The data acquired may be used for monitoring various activity of the system or it can be used to control the parts of the system. Accessing various signals with remote location has greater advantage for multisite operation or unmanned systems. The remote data acquisition used in this paper is based on ARM processor. The Cortex M3 processor used in this system has in-built Ethernet controller which facilitate to acquire the remote ...

Application of Advanced Multi-Core Processor Technologies to Oceanographic Research

Science.gov (United States)

2013-09-30

1 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. Application of Advanced Multi-Core Processor Technologies...STM32 NXP LPC series No Proprietary Microchip PIC32/DSPIC No > 500 mW; < 5 W ARM Cortex TI OMAP TI Sitara Broadcom BCM2835 Varies FPGA...state-of-the-art information processing architectures. OBJECTIVES Next-generation processor architectures (multi-core, multi-threaded) hold the

Hardware processors for pattern recognition tasks in experiments with wire chambers

International Nuclear Information System (INIS)

Verkerk, C.

1975-01-01

Hardware processors for pattern recognition tasks in experiments with multiwire proportional chambers or drift chambers are described. They vary from simple ones used for deciding in real time if particle trajectories are straight to complex ones for recognition of curved tracks. Schematics and block-diagrams of different processors are shown

Pre-Assessment and Peer Tutoring as Measures to Improve Performance in Gateway General Chemistry Classes

Science.gov (United States)

Allenbaugh, R. J.; Herrera, K. M.

2014-01-01

Determining student readiness for gateway chemistry courses and providing underprepared students effective remediation are important as student bodies are growing increasingly diverse in their precollege preparation. The effectiveness of the ACT Mathematics Test and the Whimbey Analytical Skills Inventory (WASI) in predicting student success in…

Thermal Dissipation Efficiency in a Micro-Processor Using Carbon Nanotubes Based Composite

Science.gov (United States)

Thang, Bui Hung; Van Quang, Cao; Nghia, Van Trong; Hong, Phan Ngoc; Van Chuc, Nguyen; Tam, Ngo Thi Thanh; Quang, Le Dinh; Khang, Dao Duc; Khoi, Phan Hong; Minh, Phan Ngoc

2009-09-01

Modern electronic and optoelectronic devices such as μ-processor, light emitting diode, semiconductor laser issued a challenge in the thermal dissipation problem. Finding an effective way for thermal dissipation therefore becomes a very important issue. It is known that carbon nanotubes (CNTs) is one of the most valuable materials with high thermal conductivity (2000 W/m.K compared to thermal conductivity of Ag 419 W/m.K). This suggested an approach in applying the CNTs as an essential component for thermal dissipation media to improve the performance of computer processor and other high power electronic devices. In this work multi walled carbon nanotubes (MWCNTs) based composites were utilized as the thermal dissipation media in a micro processor of a personal computer. The MWCNTs of different concentrations were added into polyaniline, commercial silicon thermal paste and commercial silver thermal paste by mechanical methods. A personal computer with configuration: Intel Pentium IV 3.066 GHz, 512 MB of RAM and Windows XP Service Pack 2 Operating System was employed. The thermal dissipation efficiency of the system was evaluated by directly measure the temperature of the μ-processor during the operation of the computer in different CPU speeds. The measured results showed that the CNTs based composite could reduce the temperature of the u-processor more than 5° C, and the time for increasing the temperature of the μ-processor was three times longer than that when using commercial thermal paste.

Video frame processor

International Nuclear Information System (INIS)

Joshi, V.M.; Agashe, Alok; Bairi, B.R.

1993-01-01

This report provides technical description regarding the Video Frame Processor (VFP) developed at Bhabha Atomic Research Centre. The instrument provides capture of video images available in CCIR format. Two memory planes each with a capacity of 512 x 512 x 8 bit data enable storage of two video image frames. The stored image can be processed on-line and on-line image subtraction can also be carried out for image comparisons. The VFP is a PC Add-on board and is I/O mapped within the host IBM PC/AT compatible computer. (author). 9 refs., 4 figs., 19 photographs

Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

International Nuclear Information System (INIS)

Kretzschmar, U.; Gomez-Cornejo, J.; Astarloa, A.; Bidarte, U.; Ser, J. Del

2016-01-01

The expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion. - Highlights: • Four different synchronization methods for faulty processors are proposed. • The methods balance between synchronization speed and hardware overhead. • They can be applied to TMR-protected reconfigurable FPGA designs. • The proposed schemes are implemented and tested in real hardware.

Simulation of Particulate Flows Multi-Processor Machines with Distributed Memory

Energy Technology Data Exchange (ETDEWEB)

Uhlmann, M.

2004-07-01

We presented a method for the parallelization of an immersed boundary algorithm for particulate flows using the MPI standard of communication. The treatment of the fluid phase used the domain decomposition technique over a Cartesian processor grid. The solution of the Helmholtz problem is approximately factorized an relies upon apparel tri-diagonal solver the Poisson problem is solved by means of a parallel multi-grid technique similar to MUDPACK. for the solid phase we employ a master-slaves technique where one processor handles all the particles contained in its Eulerian fluid sub-domain and zero or more neighbor processors collaborate in the computation of particle-related quantities whenever a particle position over laps the boundary of a sub-domain. the parallel efficiency for some preliminary computations is presented. (Author) 9 refs.

MORPION: a fast hardware processor for straight line finding in MWPC

International Nuclear Information System (INIS)

Mur, M.

1980-02-01

A fast hardware processor for straight line finding in MWPC has been built in Saclay and successfully operated in the NA3 experiment at CERN. We give the motivations to build this processor, and describe the hardware implementation of the line finding algorithm. Finally its use and performance in NA3 are described

The MIM web gateway to IP multicast e-meetings

Science.gov (United States)

Parviainen, Roland; Parnes, Peter

2003-12-01

As video conferencing and e-meeting systems are used more and more on the Internet and in businesses it becomes increasingly important to be able to participate from any computer at any location. Often this is impossible, since these systems requires often special software that are not available everywhere or impossible to install for administrative reasons. Many locations also lack the necessary network infrastructure such as IP multicast. This paper presents a WWW gateway system that enables users to participate using only a standard web browser. The design and architecture of the system are described and performance tests that show the scalability of the system are also presented.

Graphics processor efficiency for realization of rapid tabular computations

International Nuclear Information System (INIS)

Dudnik, V.A.; Kudryavtsev, V.I.; Us, S.A.; Shestakov, M.V.

2016-01-01

Capabilities of graphics processing units (GPU) and central processing units (CPU) have been investigated for realization of fast-calculation algorithms with the use of tabulated functions. The realization of tabulated functions is exemplified by the GPU/CPU architecture-based processors. Comparison is made between the operating efficiencies of GPU and CPU, employed for tabular calculations at different conditions of use. Recommendations are formulated for the use of graphical and central processors to speed up scientific and engineering computations through the use of tabulated functions

FASTBUS Standard Routines implementation for Fermilab embedded processor boards

International Nuclear Information System (INIS)

Pangburn, J.; Patrick, J.; Kent, S.; Oleynik, G.; Pordes, R.; Votava, M.; Heyes, G.; Watson, W.A. III

1992-10-01

In collaboration with CEBAF, Fermilab's Online Support Department and the CDF experiment have produced a new implementation of the IEEE FASTBUS Standard Routines for two embedded processor FASTBUS boards: the Fermilab Smart Crate Controller (FSCC) and the FASTBUS Readout Controller (FRC). Features of this implementation include: portability (to other embedded processor boards), remote source-level debugging, high speed, optional generation of very high-speed code for readout applications, and built-in Sun RPC support for execution of FASTBUS transactions and lists over the network

Statistical analysis of quality control of automatic processor

International Nuclear Information System (INIS)

Niu Yantao; Zhao Lei; Zhang Wei; Yan Shulin

2002-01-01

Objective: To strengthen the scientific management of automatic processor and promote QC, based on analyzing QC management chart for automatic processor by statistical method, evaluating and interpreting the data and trend of the chart. Method: Speed, contrast, minimum density of step wedge of film strip were measured everyday and recorded on the QC chart. Mean (x-bar), standard deviation (s) and range (R) were calculated. The data and the working trend were evaluated and interpreted for management decisions. Results: Using relative frequency distribution curve constructed by measured data, the authors can judge whether it is a symmetric bell-shaped curve or not. If not, it indicates a few extremes overstepping control limits possibly are pulling the curve to the left or right. If it is a normal distribution, standard deviation (s) is observed. When x-bar +- 2s lies in upper and lower control limits of relative performance indexes, it indicates the processor works in stable status in this period. Conclusion: Guided by statistical method, QC work becomes more scientific and quantified. The authors can deepen understanding and application of the trend chart, and improve the quality management to a new step

Broadband set-top box using MAP-CA processor

Science.gov (United States)

Bush, John E.; Lee, Woobin; Basoglu, Chris

2001-12-01

Advances in broadband access are expected to exert a profound impact in our everyday life. It will be the key to the digital convergence of communication, computer and consumer equipment. A common thread that facilitates this convergence comprises digital media and Internet. To address this market, Equator Technologies, Inc., is developing the Dolphin broadband set-top box reference platform using its MAP-CA Broadband Signal ProcessorT chip. The Dolphin reference platform is a universal media platform for display and presentation of digital contents on end-user entertainment systems. The objective of the Dolphin reference platform is to provide a complete set-top box system based on the MAP-CA processor. It includes all the necessary hardware and software components for the emerging broadcast and the broadband digital media market based on IP protocols. Such reference design requires a broadband Internet access and high-performance digital signal processing. By using the MAP-CA processor, the Dolphin reference platform is completely programmable, allowing various codecs to be implemented in software, such as MPEG-2, MPEG-4, H.263 and proprietary codecs. The software implementation also enables field upgrades to keep pace with evolving technology and industry demands.

High-Performance Linear Algebra Processor using FPGA

National Research Council Canada - National Science Library

Johnson, J

2004-01-01

With recent advances in FPGA (Field Programmable Gate Array) technology it is now feasible to use these devices to build special purpose processors for floating point intensive applications that arise in scientific computing...

Use of a track and vertex processor in a fixed-target charm experiment

International Nuclear Information System (INIS)

Schub, M.H.; Carey, T.A.; Hsiung, Y.B.; Kaplan, D.M.; Lee, C.; Miller, G.; Sa, J.; Teng, P.K.

1996-01-01

We have constructed and operated a high-speed parallel-pipelined track and vertex processor and used it to trigger data acquisition in a high-rate charm and beauty experiment at Fermilab. The processor uses information from hodoscopes and wire chambers to reconstruct tracks in the bend view of a magnetic spectrometer, and uses these tracks to find the corresponding tracks in a set of silicon-strip detectors. The processor then forms vertices and triggers the experiment if at least one vertex is downstream of the target. Under typical charm running conditions, with an interaction rate of ∼5 MHz, the processor rejects 80-90% of lower-level triggers while maintaining efficiency of ∼70% for two-prong D-meson decays. (orig.)

Simplifying cochlear implant speech processor fitting

NARCIS (Netherlands)

Willeboer, C.

2008-01-01

Conventional fittings of the speech processor of a cochlear implant (CI) rely to a large extent on the implant recipient's subjective responses. For each of the 22 intracochlear electrodes the recipient has to indicate the threshold level (T-level) and comfortable loudness level (C-level) while

A prediction method for job runtimes on shared processors: Survey, statistical analysis and new avenues

NARCIS (Netherlands)

Dobber, A.M.; van der Mei, R.D.; Koole, G.M.

2007-01-01

Grid computing is an emerging technology by which huge numbers of processors over the world create a global source of processing power. Their collaboration makes it possible to perform computations that are too extensive to perform on a single processor. On a grid, processors may connect and

Design of Processors with Reconfigurable Microarchitecture

Directory of Open Access Journals (Sweden)

Andrey Mokhov

2014-01-01

Full Text Available Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor.

Coordinated Energy Management in Heterogeneous Processors

Directory of Open Access Journals (Sweden)

Indrani Paul

2014-01-01

Full Text Available This paper examines energy management in a heterogeneous processor consisting of an integrated CPU–GPU for high-performance computing (HPC applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating energy management across distinct core types – a new and less understood problem. We examine the intra-node CPU–GPU frequency sensitivity of HPC applications on tightly coupled CPU–GPU architectures as the first step in understanding power and performance optimization for a heterogeneous multi-node HPC system. The insights from this analysis form the basis of a coordinated energy management scheme, called DynaCo, for integrated CPU–GPU architectures. We implement DynaCo on a modern heterogeneous processor and compare its performance to a state-of-the-art power- and performance-management algorithm. DynaCo improves measured average energy-delay squared (ED2 product by up to 30% with less than 2% average performance loss across several exascale and other HPC workloads.

A Bayesian sequential processor approach to spectroscopic portal system decisions

Energy Technology Data Exchange (ETDEWEB)

Sale, K; Candy, J; Breitfeller, E; Guidry, B; Manatt, D; Gosnell, T; Chambers, D

2007-07-31

The development of faster more reliable techniques to detect radioactive contraband in a portal type scenario is an extremely important problem especially in this era of constant terrorist threats. Towards this goal the development of a model-based, Bayesian sequential data processor for the detection problem is discussed. In the sequential processor each datum (detector energy deposit and pulse arrival time) is used to update the posterior probability distribution over the space of model parameters. The nature of the sequential processor approach is that a detection is produced as soon as it is statistically justified by the data rather than waiting for a fixed counting interval before any analysis is performed. In this paper the Bayesian model-based approach, physics and signal processing models and decision functions are discussed along with the first results of our research.

Parallelising a molecular dynamics algorithm on a multi-processor workstation

Science.gov (United States)

Müller-Plathe, Florian

1990-12-01

The Verlet neighbour-list algorithm is parallelised for a multi-processor Hewlett-Packard/Apollo DN10000 workstation. The implementation makes use of memory shared between the processors. It is a genuine master-slave approach by which most of the computational tasks are kept in the master process and the slaves are only called to do part of the nonbonded forces calculation. The implementation features elements of both fine-grain and coarse-grain parallelism. Apart from three calls to library routines, two of which are standard UNIX calls, and two machine-specific language extensions, the whole code is written in standard Fortran 77. Hence, it may be expected that this parallelisation concept can be transfered in parts or as a whole to other multi-processor shared-memory computers. The parallel code is routinely used in production work.

Real time processor for array speckle interferometry

International Nuclear Information System (INIS)

Chin, G.; Florez, J.; Borelli, R.; Fong, W.; Miko, J.; Trujillo, C.

1989-01-01

With the construction of several new large aperture telescopes and the development of large format array detectors in the near IR, the ability to obtain diffraction limited seeing via IR array speckle interferometry offers a powerful tool. We are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element 2D complex FFT, and to average the power spectrum all within the 25 msec coherence time for speckles at near IR wavelength. The processor is a compact unit controlled by a PC with real time display and data storage capability. It provides the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with off-line methods

ASE-BAN, a Wireless Body Area Network Testbed

DEFF Research Database (Denmark)

Madsen, Jens Kargaard; Karstoft, Henrik; Toftegaard, Thomas Skjødeberg

2010-01-01

/actuators attached to the body and a host server application. The gateway uses the BlackFin BF533 processor from Analog Devices, and uses Bluetooth for wireless communication. Two types of sensors are attached to the network: an electro-cardio-gram sensor and an oximeter sensor. The testbed has been successfully...

UNIBUS processor interface for a FASTBUS data acquisition system

International Nuclear Information System (INIS)

Larwill, M.; Lagerlund, T.D.; Barsotti, E.; Taff, L.M.; Franzen, J.

1981-01-01

Current work on a FASTBUS data acquisition system at Fermilab is described. The system will consist of three pieces of FASTBUS hardware: a UNIBUS processor interface (UPI), a dual-ported bulk memory, and a FASTBUS ''event builder'' (i.e., data acquisition processor). Primary efforts have been on specifying and constructing a UPI. The present specification includes capability for all basic FASTBUS operations, including list processing of consecutive FASTBUS operations. Some possible FASTBUS data acquisition system architectures employing the UPI are discussed along with some detailed specifications of the UPI itself

The UA1 trigger processor

International Nuclear Information System (INIS)

Grayer, G.H.

1981-01-01

Experiment UA1 is a large multi-purpose spectrometer at the CERN proton-antiproton collider, scheduled for late 1981. The principal trigger is formed on the basis of the energy deposition in calorimeters. A trigger decision taken in under 2.4 microseconds can avoid dead time losses due to the bunched nature of the beam. To achieve this we have built fast 8-bit charge to digital converters followed by two identical digital processors tailored to the experiment. The outputs of groups of the 2440 photomultipliers in the calorimeters are summed to form a total of 288 input channels to the ADCs. A look-up table in RAM is used to convert the digitised photomultiplier signals to energy in one processor, combinations of input channels, and also counts the number of clusters with electromagnetic or hadronic energy above pre-determined levels. Up to twelve combinations of these conditions, together with external information, may be combined in coincidence or in veto to form the final trigger. Provision has been made for testing using simulated data in an off-line mode, and sampling real data when on-line. (orig.)

Alternative Water Processor Test Development

Science.gov (United States)

Pickering, Karen D.; Mitchell, Julie; Vega, Leticia; Adam, Niklas; Flynn, Michael; Wjee (er. Rau); Lunn, Griffin; Jackson, Andrew

2012-01-01

The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrogen and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

The NC3Rs gateway: Accelerating scientific discoveries with new 3Rs models and technologies.

Science.gov (United States)

Percie du Sert, Nathalie; Robinson, Vicky

2018-01-01

This editorial introduces the NC3Rs gateway, which publishes articles and reviews on new models and technologies emerging from NC3Rs-funded research. The aim is to raise awareness about these approaches, increase confidence in their capability, and provide sufficient information to facilitate their uptake by others.

Suboptimal processor for anomaly detection for system surveillance and diagnosis

Energy Technology Data Exchange (ETDEWEB)

Ciftcioglu, Oe.; Hoogenboom, J.E.; Dam, H. van

1989-06-01

Anomaly detection for nuclear reactor surveillance and diagnosis is described. The residual noise obtained as a result of autoregressive (AR) modelling is essential to obtain high sensitivity for anomaly detection. By means of the method of hypothesis testing a suboptimal anomaly detection processor is devised for system surveillance and diagnosis. Experiments are carried out to investigate the performance of the processor, which is in particular of interest for on-line and real-time applications.

A Trade Study of Two Membrane-Aerated Biological Water Processors

Science.gov (United States)

Allada, Ram; Lange, Kevin; Vega. Leticia; Roberts, Michael S.; Jackson, Andrew; Anderson, Molly; Pickering, Karen

2011-01-01

Biologically based systems are under evaluation as primary water processors for next generation life support systems due to their low power requirements and their inherent regenerative nature. This paper will summarize the results of two recent studies involving membrane aerated biological water processors and present results of a trade study comparing the two systems with regards to waste stream composition, nutrient loading and system design. Results of optimal configurations will be presented.

The Gateway Paper--financing health in Pakistan and its linkage with health reforms.

Science.gov (United States)

Nishtar, Sania

2006-12-01

Pakistan currently principally uses three modes of financing health--taxation, out of pocket payments and donor contributions of which the latter is the least significant in terms of size. Less than 3.6% of the employees are covered under the social security scheme and there is a limited social protection mechanism, which collectively serves the health needs of 3.4% of the population. The main issues in health financing include low spending, lack of attention to alternate sources of financing and issues with fund mobilization and utilization. With respect to the first, health reforms proposed as part of the Gateway Paper make a strong case for promoting the reallocation of tax-based revenues and developing sustainable alternatives to low levels of public spending on health. With respect to alternative sources of health financing, the Gateway Paper lays stress on exploring policy options for private health insurance, broadening the base of Employees Social Security, creating a Federal Employees Social Security Programme, developing social health insurance within the framework of a broad-based social protection strategy, which scopes beyond the formally employed sector, establishing a widely inclusive safety net for the poor; mainstreaming philanthropic grants as a major source of health financing; developing a conducive tax configuration; generating greater corporate support for social sector causes within the framework of the concept of Corporate Social Responsibility and developing cost-sharing programmes, albeit with safeguards. The Gateway Paper regards efficient fund utilization a priority and lays stress on striking a balance between minimizing costs, controlling costs and using resources more efficiently and equitably--in other words, getting the best value for the money, on the one hand, and increasing the pool of available resources, on the other. Specific interventions such as the promotion of transparent financial administration, budgeting and cost

Space and frequency-multiplexed optical linear algebra processor - Fabrication and initial tests

Science.gov (United States)

Casasent, D.; Jackson, J.

1986-01-01

A new optical linear algebra processor architecture is described. Space and frequency-multiplexing are used to accommodate bipolar and complex-valued data. A fabricated laboratory version of this processor is described, the electronic support system used is discussed, and initial test data obtained on it are presented.

Automotive Fuel Processor Development and Demonstration with Fuel Cell Systems

Energy Technology Data Exchange (ETDEWEB)

Nuvera Fuel Cells

2005-04-15

The potential for fuel cell systems to improve energy efficiency and reduce emissions over conventional power systems has generated significant interest in fuel cell technologies. While fuel cells are being investigated for use in many applications such as stationary power generation and small portable devices, transportation applications present some unique challenges for fuel cell technology. Due to their lower operating temperature and non-brittle materials, most transportation work is focusing on fuel cells using proton exchange membrane (PEM) technology. Since PEM fuel cells are fueled by hydrogen, major obstacles to their widespread use are the lack of an available hydrogen fueling infrastructure and hydrogen's relatively low energy storage density, which leads to a much lower driving range than conventional vehicles. One potential solution to the hydrogen infrastructure and storage density issues is to convert a conventional fuel such as gasoline into hydrogen onboard the vehicle using a fuel processor. Figure 2 shows that gasoline stores roughly 7 times more energy per volume than pressurized hydrogen gas at 700 bar and 4 times more than liquid hydrogen. If integrated properly, the fuel processor/fuel cell system would also be more efficient than traditional engines and would give a fuel economy benefit while hydrogen storage and distribution issues are being investigated. Widespread implementation of fuel processor/fuel cell systems requires improvements in several aspects of the technology, including size, startup time, transient response time, and cost. In addition, the ability to operate on a number of hydrocarbon fuels that are available through the existing infrastructure is a key enabler for commercializing these systems. In this program, Nuvera Fuel Cells collaborated with the Department of Energy (DOE) to develop efficient, low-emission, multi-fuel processors for transportation applications. Nuvera's focus was on (1) developing fuel

MIRATE: MIps RATional dEsign Science Gateway.

Science.gov (United States)

Busato, Mirko; Distefano, Rosario; Bates, Ferdia; Karim, Kal; Bossi, Alessandra Maria; López Vilariño, José Manuel; Piletsky, Sergey; Bombieri, Nicola; Giorgetti, Alejandro

2018-06-13

Molecularly imprinted polymers (MIPs) are high affinity robust synthetic receptors, which can be optimally synthesized and manufactured more economically than their biological equivalents (i.e. antibody). In MIPs production, rational design based on molecular modeling is a commonly employed technique. This mostly aids in (i) virtual screening of functional monomers (FMs), (ii) optimization of monomer-template ratio, and (iii) selectivity analysis. We present MIRATE, an integrated science gateway for the intelligent design of MIPs. By combining and adapting multiple state-of-the-art bioinformatics tools into automated and innovative pipelines, MIRATE guides the user through the entire process of MIPs' design. The platform allows the user to fully customize each stage involved in the MIPs' design, with the main goal to support the synthesis in the wet-laboratory. MIRATE is freely accessible with no login requirement at http://mirate.di.univr.it/. All major browsers are supported.

The Square Kilometre Array Science Data Processor. Preliminary compute platform design

International Nuclear Information System (INIS)

Broekema, P.C.; Nieuwpoort, R.V. van; Bal, H.E.

2015-01-01

The Square Kilometre Array is a next-generation radio-telescope, to be built in South Africa and Western Australia. It is currently in its detailed design phase, with procurement and construction scheduled to start in 2017. The SKA Science Data Processor is the high-performance computing element of the instrument, responsible for producing science-ready data. This is a major IT project, with the Science Data Processor expected to challenge the computing state-of-the art even in 2020. In this paper we introduce the preliminary Science Data Processor design and the principles that guide the design process, as well as the constraints to the design. We introduce a highly scalable and flexible system architecture capable of handling the SDP workload

An enhanced Ada run-time system for real-time embedded processors

Science.gov (United States)

Sims, J. T.

1991-01-01

An enhanced Ada run-time system has been developed to support real-time embedded processor applications. The primary focus of this development effort has been on the tasking system and the memory management facilities of the run-time system. The tasking system has been extended to support efficient and precise periodic task execution as required for control applications. Event-driven task execution providing a means of task-asynchronous control and communication among Ada tasks is supported in this system. Inter-task control is even provided among tasks distributed on separate physical processors. The memory management system has been enhanced to provide object allocation and protected access support for memory shared between disjoint processors, each of which is executing a distinct Ada program.

From the Adam Smith Institute to the Zapatistas: An Internet Gateway to all Development Knowledge.

Science.gov (United States)

Wilks, Alex

2002-01-01

Examines the World Bank Internet initiative, the Development Gateway. Describes the importance of the Bank as a knowledge bank and the threats posed by the Internet to its near monopoly of development thinking. Argues that the initiative reveals biases and misunderstandings in the World Bank's approach to knowledge for development. (CAJ)

High speed vision processor with reconfigurable processing element array based on full-custom distributed memory

Science.gov (United States)

Chen, Zhe; Yang, Jie; Shi, Cong; Qin, Qi; Liu, Liyuan; Wu, Nanjian

2016-04-01

In this paper, a hybrid vision processor based on a compact full-custom distributed memory for near-sensor high-speed image processing is proposed. The proposed processor consists of a reconfigurable processing element (PE) array, a row processor (RP) array, and a dual-core microprocessor. The PE array includes two-dimensional processing elements with a compact full-custom distributed memory. It supports real-time reconfiguration between the PE array and the self-organized map (SOM) neural network. The vision processor is fabricated using a 0.18 µm CMOS technology. The circuit area of the distributed memory is reduced markedly into 1/3 of that of the conventional memory so that the circuit area of the vision processor is reduced by 44.2%. Experimental results demonstrate that the proposed design achieves correct functions.

Initial explorations of ARM processors for scientific computing

International Nuclear Information System (INIS)

Abdurachmanov, David; Elmer, Peter; Eulisse, Giulio; Muzaffar, Shahzad

2014-01-01

Power efficiency is becoming an ever more important metric for both high performance and high throughput computing. Over the course of next decade it is expected that flops/watt will be a major driver for the evolution of computer architecture. Servers with large numbers of ARM processors, already ubiquitous in mobile computing, are a promising alternative to traditional x86-64 computing. We present the results of our initial investigations into the use of ARM processors for scientific computing applications. In particular we report the results from our work with a current generation ARMv7 development board to explore ARM-specific issues regarding the software development environment, operating system, performance benchmarks and issues for porting High Energy Physics software

SPP: A data base processor data communications protocol

Science.gov (United States)

Fishwick, P. A.

1983-01-01

The design and implementation of a data communications protocol for the Intel Data Base Processor (DBP) is defined. The protocol is termed SPP (Service Port Protocol) since it enables data transfer between the host computer and the DBP service port. The protocol implementation is extensible in that it is explicitly layered and the protocol functionality is hierarchically organized. Extensive trace and performance capabilities have been supplied with the protocol software to permit optional efficient monitoring of the data transfer between the host and the Intel data base processor. Machine independence was considered to be an important attribute during the design and implementation of SPP. The protocol source is fully commented and is included in Appendix A of this report.

Techniques for optimizing inerting in electron processors

International Nuclear Information System (INIS)

Rangwalla, I.J.; Korn, D.J.; Nablo, S.V.

1993-01-01

The design of an ''inert gas'' distribution system in an electron processor must satisfy a number of requirements. The first of these is the elimination or control of beam produced ozone and NO x which can be transported from the process zone by the product into the work area. Since the tolerable levels for O 3 in occupied areas around the processor are 3 in the beam heated process zone, or exhausting and dilution of the gas at the processor exit. The second requirement of the inerting system is to provide a suitable environment for completing efficient, free radical initiated addition polymerization. The competition between radical loss through de-excitation and that from O 2 quenching must be understood. This group has used gas chromatographic analysis of electron cured coatings to study the trade-offs of delivered dose, dose rate and O 2 concentrations in the process zone to determine the tolerable ranges of parameter excursions for production quality control purposes. These techniques are described for an ink coating system on paperboard, where a broad range of process parameters have been studied (D, D radical, O 2 ). It is then shown how the technique is used to optimize the use of higher purity (10-100 ppm O 2 ) nitrogen gas for inerting, in combination with lower purity (2-20,000 ppm O 2 ) non-cryogenically produced gas, as from a membrane or pressure swing adsorption generators. (author)

An Innovative Gateway for Indoor Positioning

Directory of Open Access Journals (Sweden)

Marias Giannis F

2006-01-01

Full Text Available Enabling the pervasive paradigm requires the incorporation of location information. Retrieving location data has been a field of ongoing research for both the outdoor and indoor wireless systems. The results in the cellular scenario are already mature and location architectures have been standardized. Recent research is ongoing for indoor-positioning mechanisms, resulting in implementations that vary. A platform that enables the deployment of location-based services in heterogeneous indoor and WLAN-based communication systems will address difficulties in cooperating with different positioning systems. For that purpose, we have designed a novel entity, called Gateway WLAN Location Center (GWLC, which hides the heterogeneous functions of the indoor positioning architectures, incorporating a unified framework for retrieving location data of users and objects. The GWLC platform has been designed to meet objectives such as modularity, scalability, as well as portability, and to facilitate open interfaces. In this contribution, we elaborate on the design principles and the functionality of GWLC. We also provide performance results, obtained through real experiments.

A discussion of tools and techniques for distributed processor based control systems using CAMAC

International Nuclear Information System (INIS)

Tippie, J.W.; Scandora, A.E.

1985-01-01

This paper describes and analyzes various distributed processor architectures using commercially available CAMAC components. The general orientation is toward distributed control systems using Digital Equipment Corporation LSI11 processors in a CAMAC environment. The paper describes in detail software tools available to simplify the development of applications software and to provide a high-level runtime environment both at the host and the remote processors. Discussion focuses on techniques for downloading of operating systems from a large host and applications tasks written in high-level languages. It also discusses software tools which enable tasks in the remote processors to exchange messages and data with tasks in the host in a simple and elegant way

Expert System Constant False Alarm Rate (CFAR) Processor

National Research Council Canada - National Science Library

Wicks, Michael C

2006-01-01

An artificial intelligence system improves radar signal processor performance by increasing target probability of detection and reducing probability of false alarm in a severe radar clutter environment...

Recombinational Cloning Using Gateway and In-Fusion Cloning Schemes

Science.gov (United States)

Throop, Andrea L.; LaBaer, Joshua

2015-01-01

The comprehensive study of protein structure and function, or proteomics, depends on the obtainability of full-length cDNAs in species-specific expression vectors and subsequent functional analysis of the expressed protein. Recombinational cloning is a universal cloning technique based on site-specific recombination that is independent of the insert DNA sequence of interest, which differentiates this method from the classical restriction enzyme-based cloning methods. Recombinational cloning enables rapid and efficient parallel transfer of DNA inserts into multiple expression systems. This unit summarizes strategies for generating expression-ready clones using the most popular recombinational cloning technologies, including the commercially available Gateway® (Life Technologies) and In-Fusion® (Clontech) cloning technologies. PMID:25827088

Choosing processor array configuration by performance modeling for a highly parallel linear algebra algorithm

International Nuclear Information System (INIS)

Littlefield, R.J.; Maschhoff, K.J.

1991-04-01

Many linear algebra algorithms utilize an array of processors across which matrices are distributed. Given a particular matrix size and a maximum number of processors, what configuration of processors, i.e., what size and shape array, will execute the fastest? The answer to this question depends on tradeoffs between load balancing, communication startup and transfer costs, and computational overhead. In this paper we analyze in detail one algorithm: the blocked factored Jacobi method for solving dense eigensystems. A performance model is developed to predict execution time as a function of the processor array and matrix sizes, plus the basic computation and communication speeds of the underlying computer system. In experiments on a large hypercube (up to 512 processors), this model has been found to be highly accurate (mean error ∼ 2%) over a wide range of matrix sizes (10 x 10 through 200 x 200) and processor counts (1 to 512). The model reveals, and direct experiment confirms, that the tradeoffs mentioned above can be surprisingly complex and counterintuitive. We propose decision procedures based directly on the performance model to choose configurations for fastest execution. The model-based decision procedures are compared to a heuristic strategy and shown to be significantly better. 7 refs., 8 figs., 1 tab

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors.

Science.gov (United States)

Cheung, Kit; Schultz, Simon R; Luk, Wayne

2015-01-01

NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation.

Beeldverwerking met de Micron Automatic Processor

OpenAIRE

Goyens, Frank

2017-01-01

Deze thesis is een onderzoek naar toepassingen binnen beeldverwerking op de Micron Automata Processor hardware. De hardware wordt vergeleken met populaire hedendaagse hardware. Ook bevat dit onderzoek nuttige informatie en strategieën voor het ontwikkelen van nieuwe toepassingen. Bevindingen in dit onderzoek omvatten proof of concept algoritmes en een praktische toepassing.

Compact gasoline fuel processor for passenger vehicle APU

Science.gov (United States)

Severin, Christopher; Pischinger, Stefan; Ogrzewalla, Jürgen

Due to the increasing demand for electrical power in today's passenger vehicles, and with the requirements regarding fuel consumption and environmental sustainability tightening, a fuel cell-based auxiliary power unit (APU) becomes a promising alternative to the conventional generation of electrical energy via internal combustion engine, generator and battery. It is obvious that the on-board stored fuel has to be used for the fuel cell system, thus, gasoline or diesel has to be reformed on board. This makes the auxiliary power unit a complex integrated system of stack, air supply, fuel processor, electrics as well as heat and water management. Aside from proving the technical feasibility of such a system, the development has to address three major barriers:start-up time, costs, and size/weight of the systems. In this paper a packaging concept for an auxiliary power unit is presented. The main emphasis is placed on the fuel processor, as good packaging of this large subsystem has the strongest impact on overall size. The fuel processor system consists of an autothermal reformer in combination with water-gas shift and selective oxidation stages, based on adiabatic reactors with inter-cooling. The configuration was realized in a laboratory set-up and experimentally investigated. The results gained from this confirm a general suitability for mobile applications. A start-up time of 30 min was measured, while a potential reduction to 10 min seems feasible. An overall fuel processor efficiency of about 77% was measured. On the basis of the know-how gained by the experimental investigation of the laboratory set-up a packaging concept was developed. Using state-of-the-art catalyst and heat exchanger technology, the volumes of these components are fixed. However, the overall volume is higher mainly due to mixing zones and flow ducts, which do not contribute to the chemical or thermal function of the system. Thus, the concept developed mainly focuses on minimization of those

Architecture-Aware Optimization of an HEVC decoder on Asymmetric Multicore Processors

OpenAIRE

Rodríguez-Sánchez, Rafael; Quintana-Ortí, Enrique S.

2016-01-01

Low-power asymmetric multicore processors (AMPs) attract considerable attention due to their appealing performance-power ratio for energy-constrained environments. However, these processors pose a significant programming challenge due to the integration of cores with different performance capabilities, asking for an asymmetry-aware scheduling solution that carefully distributes the workload. The recent HEVC standard, which offers several high-level parallelization strategies, is an important ...

Using of opportunities of graphic processors for acceleration of scientific and technical calculations

International Nuclear Information System (INIS)

Dudnik, V.A.; Kudryavtsev, V.I.; Sereda, T.M.; Us, S.A.; Shestakov, M.V.

2009-01-01

The new opportunities of modern graphic processors (GPU) for acceleration of the scientific and technical calculations with the help of paralleling of a calculating task between the central processor and GPU are described. The description of using the technology NVIDIA CUDA for connection of parallel computing opportunities of GPU within the programme of the some intensive mathematical tasks is resulted. The examples of comparison of parameters of productivity in the process of these tasks' calculation without application of GPU and with use of opportunities NVIDIA CUDA for graphic processor GeForce 8800 are resulted

Run-time Adaptable VLIW Processors : Resources, Performance, Power Consumption, and Reliability Trade-offs

NARCIS (Netherlands)

Anjam, F.

2013-01-01

In this dissertation, we propose to combine programmability with reconfigurability by implementing an adaptable programmable VLIW processor in a reconfigurable hardware. The approach allows applications to be developed at high-level (C language level), while at the same time, the processor

Trigger and decision processors

International Nuclear Information System (INIS)

Franke, G.

1980-11-01

In recent years there have been many attempts in high energy physics to make trigger and decision processes faster and more sophisticated. This became necessary due to a permanent increase of the number of sensitive detector elements in wire chambers and calorimeters, and in fact it was possible because of the fast developments in integrated circuits technique. In this paper the present situation will be reviewed. The discussion will be mainly focussed upon event filtering by pure software methods and - rather hardware related - microprogrammable processors as well as random access memory triggers. (orig.)

Optical Finite Element Processor

Science.gov (United States)

Casasent, David; Taylor, Bradley K.

1986-01-01

A new high-accuracy optical linear algebra processor (OLAP) with many advantageous features is described. It achieves floating point accuracy, handles bipolar data by sign-magnitude representation, performs LU decomposition using only one channel, easily partitions and considers data flow. A new application (finite element (FE) structural analysis) for OLAPs is introduced and the results of a case study presented. Error sources in encoded OLAPs are addressed for the first time. Their modeling and simulation are discussed and quantitative data are presented. Dominant error sources and the effects of composite error sources are analyzed.

Performance evaluation of integrated fuel processor for residential PEMFCs application

International Nuclear Information System (INIS)

Yu Taek Seo; Dong Joo Seo; Young-Seog Seo; Hyun-Seog Roh; Wang Lai Yoon; Jin Hyeok Jeong

2006-01-01

KIER has been developing the natural gas fuel processor to produce hydrogen rich gas for residential PEMFCs system. To realize a compact and high efficiency, the unit processes of steam reforming, water gas shift, and preferential oxidation are chemically and physically integrated in a package. Current fuel processor designed for 1 kW class PEMFCs shows thermal efficiency of 78% as a HHV basis with methane conversion of 90% at rated load operation. CO concentration below 10 ppm in the produced gas is achieved with preferential oxidation unit using Pt and Ru based catalyst under the condition of [O 2 ]/[CO]=2.0. The partial load operation have been carried out to test the performance of fuel processor from 40% to 80% load, showing stable methane conversion and CO concentration below 10 ppm. The durability test for the daily start-stop and 8 hr operation procedure is under investigation and shows no deterioration of its performance after 40 start-stop cycles. (authors)

Space Biology Model Organism Research on the Deep Space Gateway to Pioneer Discovery and Advance Human Space Exploration

Science.gov (United States)

Sato, K. Y.; Tomko, D. L.; Levine, H. G.; Quincy, C. D.; Rayl, N. A.; Sowa, M. B.; Taylor, E. M.; Sun, S. C.; Kundrot, C. E.

2018-02-01

Model organisms are foundational for conducting physiological and systems biology research to define how life responds to the deep space environment. The organisms, areas of research, and Deep Space Gateway capabilities needed will be presented.

Radiation Tolerant Software Defined Video Processor, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — MaXentric's is proposing a radiation tolerant Software Define Video Processor, codenamed SDVP, for the problem of advanced motion imaging in the space environment....

The Usage of Informational Gateways for Data Exchange between Personal Data Systems of Different Classes

Directory of Open Access Journals (Sweden)

E. I. Goncharov

2010-03-01

Full Text Available When personal data exchange between informational systems takes place, one must guarantee the systems are not integrating but just interacting. This task can not be accomplished by using traditional tools such as firewalls, cryptography and so on. To solve the problem we suggest deploying of informational gateway in personal data exchange process.

The Divine Dreams of a Sample of South African Children: The Gateway to Their Spirituality

Science.gov (United States)

Potgieter, Ferdinand J.; van der Walt, Johannes L.; Wolhuter, Charl C.

2009-01-01

As part of a research project on religion, spirituality and education, the authors attended to the role that children's divine dreams could play in religious education (RE). They contend that such dreams can indeed be used by RE teachers as the gateway to understanding the spirituality of their learners. They defend their claim by firstly…

The fast tracker processor for hadronic collider triggers

CERN Document Server

Annovi, A; Bardi, A; Carosi, R; Dell'Orso, Mauro; D'Onofrio, M; Giannetti, P; Iannaccone, G; Morsani, F; Pietri, M; Varotto, G

2000-01-01

Perspective for precise and fast track reconstruction in future hadronic collider experiments are addressed. We discuss the feasibility of a pipelined highly parallelized processor dedicated to the implementation of a very fast algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points (patterns) for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at a rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution traces with transverse momentum above few GeV and search secondary vertexes within typical level-2 times. 15 Refs.

Digital implementation of the preloaded filter pulse processor

International Nuclear Information System (INIS)

Westphal, G.P.; Cadek, G.R.; Keroe, N.; Sauter, TH.; Thorwartl, P.C.

1995-01-01

Adapting it's processing time to the respective pulse intervals, the Preloaded Filter (PLF) pulse processor offers optimum resolution together with highest possible throughput rates. The PLF algorithm could be formulated in a recursive manner which made possible it's implementation by means of a large field-programmable gate array, as a fast, pipe-lined digital processor with 10 MHz maximum throughput rate. While pre-filter digitization by an ADC with 12 bit resolution and 10M Hz sampling rate resulted in a poorer resolution than that of an analog filter, a digital PLF based on an ADC with 14 bit resolution and 10 MHz sampling rate, surpassed high-quality analog filters in resolution, throughput rate and long-term stability. (author) 6 refs.; 7 figs

Biological Water Processor and Forward Osmosis Secondary Treatment

Science.gov (United States)

Shull, Sarah; Meyer, Caitlin

2014-01-01

The goal of the Biological Water Processor (BWP) is to remove 90% organic carbon and 75% ammonium from an exploration-based wastewater stream for four crew members. The innovative design saves on space, power and consumables as compared to the ISS Urine Processor Assembly (UPA) by utilizing microbes in a biofilm. The attached-growth system utilizes simultaneous nitrification and denitrification to mineralize organic carbon and ammonium to carbon dioxide and nitrogen gas, which can be scrubbed in a cabin air revitalization system. The BWP uses a four-crew wastewater comprised of urine and humidity condensate, as on the ISS, but also includes hygiene (shower, shave, hand washing and oral hygiene) and laundry. The BWP team donates 58L per day of this wastewater processed in Building 7.

PENERAPAN CUSTOMER RELATIONSHIP MANAGEMENT (CRM) BERBASIS SMS GATEWAY PADA ONLINE SHOP TOKOFARAH

OpenAIRE

Arfiani Nur Khusna

2016-01-01

SMS applications has become a promising business opportunities in the consumer and industrial markets in the world. One part that can not be separated from the SMS business is the role of an SMS Gateway, a system used by service providers to send and receive SMS automatically. Online shop tokofarah an online web business venture engaged in the production and sales of baby clothes and children. The problems that exist in the online shop tokofarah is the absence of communication between the cus...

Dual shear plate power processor packaging design. [for Solar Electric Propulsion spacecraft

Science.gov (United States)

Franzon, A. O.; Fredrickson, C. D.; Ross, R. G.

1975-01-01

The use of solar electric propulsion (SEP) for spacecraft primary propulsion imposes an extreme range of operational and environmental design requirements associated with the diversity of missions for which solar electric primary propulsion is advantageous. One SEP element which is particularly sensitive to these environmental extremes is the power processor unit (PPU) which powers and controls the electric ion thruster. An improved power processor thermal-mechanical packaging approach, referred to as dual shear plate packaging, has been designed to accommodate these different requirements with minimum change to the power processor design. Details of this packaging design are presented together with test results obtained from thermal-vacuum and structural-vibration tests conducted with prototype hardware.

Parallel processor programs in the Federal Government

Science.gov (United States)

Schneck, P. B.; Austin, D.; Squires, S. L.; Lehmann, J.; Mizell, D.; Wallgren, K.

1985-01-01

In 1982, a report dealing with the nation's research needs in high-speed computing called for increased access to supercomputing resources for the research community, research in computational mathematics, and increased research in the technology base needed for the next generation of supercomputers. Since that time a number of programs addressing future generations of computers, particularly parallel processors, have been started by U.S. government agencies. The present paper provides a description of the largest government programs in parallel processing. Established in fiscal year 1985 by the Institute for Defense Analyses for the National Security Agency, the Supercomputing Research Center will pursue research to advance the state of the art in supercomputing. Attention is also given to the DOE applied mathematical sciences research program, the NYU Ultracomputer project, the DARPA multiprocessor system architectures program, NSF research on multiprocessor systems, ONR activities in parallel computing, and NASA parallel processor projects.

Nonlinear Wave Simulation on the Xeon Phi Knights Landing Processor

OpenAIRE

Hristov Ivan; Goranov Goran; Hristova Radoslava

2018-01-01

We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named “Ivy Bridge-EP”) in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named “Knights Landing” (KNL). The results show 2 times better per...

Global synchronization of parallel processors using clock pulse width modulation

Science.gov (United States)

Chen, Dong; Ellavsky, Matthew R.; Franke, Ross L.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Jeanson, Mark J.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Littrell, Daniel; Ohmacht, Martin; Reed, Don D.; Schenck, Brandon E.; Swetz, Richard A.

2013-04-02

A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

Pathway Processor 2.0: a web resource for pathway-based analysis of high-throughput data.

Science.gov (United States)

Beltrame, Luca; Bianco, Luca; Fontana, Paolo; Cavalieri, Duccio

2013-07-15

Pathway Processor 2.0 is a web application designed to analyze high-throughput datasets, including but not limited to microarray and next-generation sequencing, using a pathway centric logic. In addition to well-established methods such as the Fisher's test and impact analysis, Pathway Processor 2.0 offers innovative methods that convert gene expression into pathway expression, leading to the identification of differentially regulated pathways in a dataset of choice. Pathway Processor 2.0 is available as a web service at http://compbiotoolbox.fmach.it/pathwayProcessor/. Sample datasets to test the functionality can be used directly from the application. duccio.cavalieri@fmach.it Supplementary data are available at Bioinformatics online.

Space Station Water Processor Process Pump

Science.gov (United States)

Parker, David

1995-01-01

This report presents the results of the development program conducted under contract NAS8-38250-12 related to the International Space Station (ISS) Water Processor (WP) Process Pump. The results of the Process Pumps evaluation conducted on this program indicates that further development is required in order to achieve the performance and life requirements for the ISSWP.

Response of Mediterranean circulation to Miocene shoaling and closure of the Indian Gateway : A model study

NARCIS (Netherlands)

De La Vara, Alba; Meijer, Paul

2016-01-01

In this regional ocean model study, we explore the effect of the Early to Middle Miocene shoaling and closure of the Indian Gateway on Mediterranean circulation and its exchange with the adjacent oceans. For this we use the regional ocean circulation model "sbPOM" and a collection of bathymetries

78 FR 79707 - Notice of Public Meeting, Gateway West Project Subcommittee of the Boise District Resource...

Science.gov (United States)

2013-12-31

... Resource Advisory Council on matters of planning and management of the Gateway West Project (sections 8 and... Interior, through the BLM, on a variety of planning and management issues associated with public land... a telecommunications device for the deaf (TDD) may call the Federal Information Relay Service (FIRS...

Modcomp MAX IV System Processors reference guide

Energy Technology Data Exchange (ETDEWEB)

Cummings, J.

1990-10-01

A user almost always faces a big problem when having to learn to use a new computer system. The information necessary to use the system is often scattered throughout many different manuals. The user also faces the problem of extracting the information really needed from each manual. Very few computer vendors supply a single Users Guide or even a manual to help the new user locate the necessary manuals. Modcomp is no exception to this, Modcomp MAX IV requires that the user be familiar with the system file usage which adds to the problem. At General Atomics there is an ever increasing need for new users to learn how to use the Modcomp computers. This paper was written to provide a condensed Users Reference Guide'' for Modcomp computer users. This manual should be of value not only to new users but any users that are not Modcomp computer systems experts. This Users Reference Guide'' is intended to provided the basic information for the use of the various Modcomp System Processors necessary to, create, compile, link-edit, and catalog a program. Only the information necessary to provide the user with a basic understanding of the Systems Processors is included. This document provides enough information for the majority of programmers to use the Modcomp computers without having to refer to any other manuals. A lot of emphasis has been placed on the file description and usage for each of the System Processors. This allows the user to understand how Modcomp MAX IV does things rather than just learning the system commands.

A pre- and post-processor for the ICOOL muon transport code

International Nuclear Information System (INIS)

Fawley, W.M.

2001-01-01

ICOOL[1] is a Fortran77 macroparticle transport code widely used by researchers to study the front end of a neutrino factory/muon collider[2]. In part due to the desire that ICOOL be usable over multiple computer platforms and operating systems, the code uses simple text files for input/output services. This choice together with user-driven requests for greater and greater choice of lattice element type and configuration has led to ICOOL input decks becoming rather difficult to compose and modify easily. Moreover, the lack of a standard graphical post-processor has prevented many ICOOL users from extracting all but the most simple results from the output files. Here I present two attempts to improve this situation: First, a simple but quite general graphical pre-processor (NIME) written in the Tcl/TK[3] to permit users to write and maintain ASCII-formatted input files by use of simple macro definitions and expansions. Second, an interactive post-processor written in Fortran90 and NCAR graphics, which allows users to define, extract, and then examine the behavior of various particle subsets. In this paper I show some examples of use of both the pre- and post-processor for a standard ICOOL run

Making the black box signal processor transparent explains the contradictions in x-ray spectroscopy

International Nuclear Information System (INIS)

Papp, T.; Maxwell, J.A.; Papp, A.T.

2008-01-01

Full text: There are significant differences in the experimental data needed in the analysis of x-ray spectra, and many of the results contradict basic conservation laws and simple arithmetic. We have identified that the main source of the unexplainable results is rooted in the signal processing electronics. We have developed a line of fully digital signal processors that have yielded improved resolution, line shape, tailing and pile up recognition. The signal processor is a time variant, non-paralyzable signal processor. The signal processor accounts for and registers all events, sorting them into two spectra, one spectrum for the desirable or accepted events, and one spectrum for the rejected events. Although the information on the rejected events is always necessary, we recently realized its additional benefits in high rate, (10 5 -10 6 cps) analytical measurements. Having all information available we were surprised to see how different conclusions and level of understandings are possible in detector characterization, detector efficiency, spectrum evaluation methodology, and that it explains many of the contradictions. We will demonstrate how the Coster-Kronig transition measurements often do not even comply with arithmetic, and why is it difficult to interpret the spectra with other processors. It will be presented that for different spectra in origin, like radioisotope measurements, x-ray fluorescence, and particle induced x-ray emission, the primary signal from the preamplifier is so different, that the signal processor is facing very different challenges, and different metrological approaches are necessary in data processing. This data processing methodology cannot be established on the partial and fractional information offered by other approaches. However, the maximum information utilization approach offered by our processor's rejected spectrum supplements the accepted spectrum to allow the development of straight forward and accurate metrology. All the

Tinuso: A processor architecture for a multi-core hardware simulation platform

DEFF Research Database (Denmark)

Schleuniger, Pascal; Karlsson, Sven

2010-01-01

Multi-core systems have the potential to improve performance, energy and cost properties of embedded systems but also require new design methods and tools to take advantage of the new architectures. Due to the limited accuracy and performance of pure software simulators, we are working on a cycle...... accurate hardware simulation platform. We have developed the Tinuso processor architecture for this platform. Tinuso is a processor architecture optimized for FPGA implementation. The instruction set makes use of predicated instructions and supports C/C++ and assembly language programming. It is designed...... to be easy extendable to maintain the exibility required for the research on multi-core systems. Tinuso contains a co-processor interface to connect to a network interface. This interface allow for communication over an on-chip network. A clock frequency estimation study on a deeply pipelined Tinuso...

PERFORMANCE EVALUATION OF OR1200 PROCESSOR WITH EVOLUTIONARY PARALLEL HPRC USING GEP

Directory of Open Access Journals (Sweden)

R. Maheswari

2012-04-01

Full Text Available In this fast computing era, most of the embedded system requires more computing power to complete the complex function/ task at the lesser amount of time. One way to achieve this is by boosting up the processor performance which allows processor core to run faster. This paper presents a novel technique of increasing the performance by parallel HPRC (High Performance Reconfigurable Computing in the CPU/DSP (Digital Signal Processor unit of OR1200 (Open Reduced Instruction Set Computer (RISC 1200 using Gene Expression Programming (GEP an evolutionary programming model. OR1200 is a soft-core RISC processor of the Intellectual Property cores that can efficiently run any modern operating system. In the manufacturing process of OR1200 a parallel HPRC is placed internally in the Integer Execution Pipeline unit of the CPU/DSP core to increase the performance. The GEP Parallel HPRC is activated /deactivated by triggering the signals i HPRC_Gene_Start ii HPRC_Gene_End. A Verilog HDL(Hardware Description language functional code for Gene Expression Programming parallel HPRC is developed and synthesised using XILINX ISE in the former part of the work and a CoreMark processor core benchmark is used to test the performance of the OR1200 soft core in the later part of the work. The result of the implementation ensures the overall speed-up increased to 20.59% by GEP based parallel HPRC in the execution unit of OR1200.

Bounds on achievable accuracy in analog optical linear-algebra processors

Science.gov (United States)

Batsell, Stephen G.; Walkup, John F.; Krile, Thomas F.

1990-07-01

Upper arid lower bounds on the number of bits of accuracy achievable are determined by applying a seconth-ortler statistical model to the linear algebra processor. The use of bounds was found necessary due to the strong signal-dependence of the noise at the output of the optical linear algebra processor (OLAP). 1 1. ACCURACY BOUNDS One of the limiting factors in applying OLAPs to real world problems has been the poor achievable accuracy of these processors. Little previous research has been done on determining noise sources from a systems perspective which would include noise generated in the multiplication ard addition operations spatial variations across arrays and crosstalk. We have previously examined these noise sources and determined a general model for the output noise mean and variance. The model demonstrates a strony signaldependency in the noise at the output of the processor which has been confirmed by our experiments. 1 We define accuracy similar to its definition for an analog signal input to an analog-to-digital (ND) converter. The number of bits of accuracy achievable is related to the log (base 2) of the number of separable levels at the P/D converter output. The number of separable levels is fouri by dividing the dynamic range by m times the standard deviation of the signal a. 2 Here m determines the error rate in the P/D conversion. The dynamic range can be expressed as the

Parallel Processor for 3D Recovery from Optical Flow

Directory of Open Access Journals (Sweden)

Jose Hugo Barron-Zambrano

2009-01-01

Full Text Available 3D recovery from motion has received a major effort in computer vision systems in the recent years. The main problem lies in the number of operations and memory accesses to be performed by the majority of the existing techniques when translated to hardware or software implementations. This paper proposes a parallel processor for 3D recovery from optical flow. Its main feature is the maximum reuse of data and the low number of clock cycles to calculate the optical flow, along with the precision with which 3D recovery is achieved. The results of the proposed architecture as well as those from processor synthesis are presented.

Cassava processors' awareness of occupational and environmental ...

African Journals Online (AJOL)

A larger percentage (74.5%) of the respondents indicated that the Agricultural Development Programme (ADP) is their source of information. The result also showed that processor's awareness of occupational hazards associated with the different stages of cassava processing vary because their involvement in these stages

The application of charge-coupled device processors in automatic-control systems

Science.gov (United States)

Mcvey, E. S.; Parrish, E. A., Jr.

1977-01-01

The application of charge-coupled device (CCD) processors to automatic-control systems is suggested. CCD processors are a new form of semiconductor component with the unique ability to process sampled signals on an analog basis. Specific implementations of controllers are suggested for linear time-invariant, time-varying, and nonlinear systems. Typical processing time should be only a few microseconds. This form of technology may become competitive with microprocessors and minicomputers in addition to supplementing them.