WorldWideScience

Sample records for gate metal layer

  1. Feasibility study of using thin aluminum nitride film as a buffer layer for dual metal gate process

    International Nuclear Information System (INIS)

    Park, Chang Seo; Cho, Byung Jin; Balasubramanian, N.; Kwong, Dim-Lee

    2004-01-01

    We evaluated the feasibility of using an ultra thin aluminum nitride (AlN) buffer layer for dual metal gates CMOS process. Since the buffer layer should not affect the thickness of gate dielectric, it should be removed or consumed during subsequent process. In this work, it was shown that a thin AlN dielectric layer would be reacted with initial gate metals and would be consumed during subsequent annealing, resulting in no increase of equivalent oxide thickness (EOT). The reaction of AlN layer with tantalum (Ta) and hafnium (Hf) during subsequent annealing, which was confirmed with X-ray photoelectron spectroscopy (XPS) analysis, shifted the flat-band voltage of AlN buffered MOS capacitors. No contribution to equivalent oxide thickness (EOT) was also an indication showing the full consumption of AIN, which was confirmed with TEM analysis. The work functions of gate metals were modulated through the reaction, suggesting that the consumption of AlN resulted in new thin metal alloys. Finally, it was found that the barrier heights of the new alloys were consistent with their work functions

  2. Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

    Energy Technology Data Exchange (ETDEWEB)

    Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A., E-mail: steven.vitale@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

    2015-07-28

    Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

  3. Simulation of dual-gate SOI MOSFET with different dielectric layers

    Science.gov (United States)

    Yadav, Jyoti; Chaudhary, R.; Mukhiya, R.; Sharma, R.; Khanna, V. K.

    2016-04-01

    The paper presents the process design and simulation of silicon-on-insulator (SOI)-based dual-gate metal oxide field-effect transistor (DG-MOSFET) stacked with different dielectric layers on the top of gate oxide. A detailed 2D process simulation of SOI-MOSFETs and its electrical characterization has been done using SILVACO® TCAD tool. A variation in transconductance was observed with different dielectric layers, AlN-gate MOSFET having the highest tranconductance value as compared to other three dielectric layers (SiO2, Si3N4 and Al2O3).

  4. Chemical gating of epitaxial graphene through ultrathin oxide layers.

    Science.gov (United States)

    Larciprete, Rosanna; Lacovig, Paolo; Orlando, Fabrizio; Dalmiglio, Matteo; Omiciuolo, Luca; Baraldi, Alessandro; Lizzit, Silvano

    2015-08-07

    We achieved a controllable chemical gating of epitaxial graphene grown on metal substrates by exploiting the electrostatic polarization of ultrathin SiO2 layers synthesized below it. Intercalated oxygen diffusing through the SiO2 layer modifies the metal-oxide work function and hole dopes graphene. The graphene/oxide/metal heterostructure behaves as a gated plane capacitor with the in situ grown SiO2 layer acting as a homogeneous dielectric spacer, whose high capacity allows the Fermi level of graphene to be shifted by a few hundreds of meV when the oxygen coverage at the metal substrate is of the order of 0.5 monolayers. The hole doping can be finely tuned by controlling the amount of interfacial oxygen, as well as by adjusting the thickness of the oxide layer. After complete thermal desorption of oxygen the intrinsic doping of SiO2 supported graphene is evaluated in the absence of contaminants and adventitious adsorbates. The demonstration that the charge state of graphene can be changed by chemically modifying the buried oxide/metal interface hints at the possibility of tuning the level and sign of doping by the use of other intercalants capable of diffusing through the ultrathin porous dielectric and reach the interface with the metal.

  5. Electroresistance effect in gold thin film induced by ionic-liquid-gated electric double layer

    International Nuclear Information System (INIS)

    Nakayama, Hiroyasu; Ohtani, Takashi; Fujikawa, Yasunori; Ando, Kazuya; Saitoh, Eiji; Ye, Jianting; Iwasa, Yoshihiro

    2012-01-01

    Electroresistance effect was detected in a metallic thin film using ionic-liquid-gated electric-double-layer transistors (EDLTs). We observed reversible modulation of the electric resistance of a Au thin film. In this system, we found that an electric double layer works as a nanogap capacitor with 27 (-25) MV cm -1 of electric field by applying only 1.7 V of positive (negative) gate voltage. The experimental results indicate that the ionic-liquid-gated EDLT technique can be used for controlling the surface electronic states on metallic systems. (author)

  6. Cleaning Challenges of High-κ/Metal Gate Structures

    KAUST Repository

    Hussain, Muhammad Mustafa; Shamiryan, Denis G.; Paraschiv, Vasile; Sano, Kenichi; Reinhardt, Karen A.

    2010-01-01

    High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.

  7. Cleaning Challenges of High-κ/Metal Gate Structures

    KAUST Repository

    Hussain, Muhammad Mustafa

    2010-12-20

    High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.

  8. Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics

    KAUST Repository

    Alshareef, Husam N.

    2010-11-19

    Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.

  9. Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics

    KAUST Repository

    Alshareef, Husam N.; Caraveo-Frescas, J. A.; Cha, D. K.

    2010-01-01

    Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.

  10. Microstructure and chemical analysis of Hf-based high-k dielectric layers in metal-insulator-metal capacitors

    Energy Technology Data Exchange (ETDEWEB)

    Thangadurai, P. [Department of Materials Engineering, Technion - Israel Institute of Technology, Haifa 32000 (Israel); Mikhelashvili, V.; Eisenstein, G. [Department of Electrical Engineering, Technion - Israel Institute of Technology, Haifa 32000 (Israel); Kaplan, W.D., E-mail: kaplan@tx.technion.ac.i [Department of Materials Engineering, Technion - Israel Institute of Technology, Haifa 32000 (Israel)

    2010-05-31

    The microstructure and chemistry of the high-k gate dielectric significantly influences the performance of metal-insulator-metal (MIM) and metal-oxide-semiconductor devices. In particular, the local structure, chemistry, and inter-layer mixing are important phenomena to be understood. In the present study, high resolution and analytical transmission electron microscopy are combined to study the local structure, morphology, and chemistry in MIM capacitors containing a Hf-based high-k dielectric. The gate dielectric, bottom and gate electrodes were deposited on p-type Si(100) wafers by electron beam evaporation. Four chemically distinguishable sub-layers were identified within the dielectric stack. One is an unintentionally formed 4.0 nm thick interfacial layer of Ta{sub 2}O{sub 5} at the interface between the Ta electrode and the dielectric. The other three layers are based on HfN{sub x}O{sub y} and HfTiO{sub y}, and intermixing between the nearby sub-layers including deposited SiO{sub 2}. Hf-rich clusters were found in the HfN{sub x}O{sub y} layer adjacent to the Ta{sub 2}O{sub 5} layer.

  11. Electroresistance Effect in Gold Thin Film Induced by Ionic-Liquid-Gated Electric Double Layer

    NARCIS (Netherlands)

    Nakayama, Hiroyasu; Ye, Jianting; Ohtani, Takashi; Fujikawa, Yasunori; Ando, Kazuya; Iwasa, Yoshihiro; Saitoh, Eiji

    Electroresistance effect was detected in a metallic thin film using ionic-liquid-gated electric-double-layer transistors (EDLTs). We observed reversible modulation of the electric resistance of a Au thin film. In this system, we found that an electric double layer works as a nanogap capacitor with

  12. Backside versus frontside advanced chemical analysis of high-k/metal gate stacks

    Energy Technology Data Exchange (ETDEWEB)

    Martinez, E., E-mail: eugenie.martinez@cea.fr [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Saidi, B. [STMicroelectronics, 850 rue Jean Monnet, 38926 Rousset Cedex, Crolles (France); Veillerot, M. [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Caubet, P. [STMicroelectronics, 850 rue Jean Monnet, 38926 Rousset Cedex, Crolles (France); Fabbri, J-M. [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Piallat, F. [STMicroelectronics, 850 rue Jean Monnet, 38926 Rousset Cedex, Crolles (France); Gassilloud, R. [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Schamm-Chardon, S. [CEMES-CNRS et Université de Toulouse, 29 rue Jeanne Marvig, 31055 Toulouse (France)

    2015-08-15

    Highlights: • The backside approach is a promising solution for advanced chemical characterization of future MOSFETs. • Frontside ToF-SIMS and Auger depth profiles are affected by cumulative mixing effects and thus not relevant for analyzing ultra-thin layers. • Higher in-depth resolution is possible in the backside approach for Auger and ToF-SIMS depth profiling. • Backside depth profiling allows revealing ultra-thin layers and elemental in-depth redistribution inside high-k/metal gate stacks. • Backside XPS allows preserving the full metal gate, thus enabling the analysis of real technological samples. - Abstract: Downscaling of transistors beyond the 14 nm technological node requires the implementation of new architectures and materials. Advanced characterization methods are needed to gain information about the chemical composition of buried layers and interfaces. An effective approach based on backside analysis is presented here. X-ray photoelectron spectroscopy, Auger depth profiling and time-of-flight secondary ions mass spectrometry are combined to investigate inter-diffusion phenomena. To highlight improvements related to the backside method, backside and frontside analyses are compared. Critical information regarding nitrogen, oxygen and aluminium redistribution inside the gate stacks is obtained only in the backside configuration.

  13. Silicon dioxide with a silicon interfacial layer as an insulating gate for highly stable indium phosphide metal-insulator-semiconductor field effect transistors

    Science.gov (United States)

    Kapoor, V. J.; Shokrani, M.

    1991-01-01

    A novel gate insulator consisting of silicon dioxide (SiO2) with a thin silicon (Si) interfacial layer has been investigated for high-power microwave indium phosphide (InP) metal-insulator-semiconductor field effect transistors (MISFETs). The role of the silicon interfacial layer on the chemical nature of the SiO2/Si/InP interface was studied by high-resolution X-ray photoelectron spectroscopy. The results indicated that the silicon interfacial layer reacted with the native oxide at the InP surface, thus producing silicon dioxide, while reducing the native oxide which has been shown to be responsible for the instabilities in InP MISFETs. While a 1.2-V hysteresis was present in the capacitance-voltage (C-V) curve of the MIS capacitors with silicon dioxide, less than 0.1 V hysteresis was observed in the C-V curve of the capacitors with the silicon interfacial layer incorporated in the insulator. InP MISFETs fabricated with the silicon dioxide in combination with the silicon interfacial layer exhibited excellent stability with drain current drift of less than 3 percent in 10,000 sec, as compared to 15-18 percent drift in 10,000 sec for devices without the silicon interfacial layer. High-power microwave InP MISFETs with Si/SiO2 gate insulators resulted in an output power density of 1.75 W/mm gate width at 9.7 GHz, with an associated power gain of 2.5 dB and 24 percent power added efficiency.

  14. Analysis of chemical bond states and electrical properties of stacked AlON/HfO{sub 2} gate oxides formed by using a layer-by-layer technique

    Energy Technology Data Exchange (ETDEWEB)

    Choi, Wonjoon; Lee, Jonghyun; Yang, Jungyup; Kim, Chaeok; Hong, Jinpyo; Nahm, Tschanguh; Byun, Byungsub; Kim, Moseok [Hanyang University, Seoul (Korea, Republic of)

    2006-06-15

    Stacked AlON/HfO{sub 2} thin films for gate oxides in metal-oxide-semiconductor devices are successfully prepared on Si substrates by utilizing a layer-by-layer technique integrated with an off-axis RF remote plasma sputtering process at room temperature. This off-axis structure is designed to improve the uniformity and the quality of gate oxide films. Also, a layer-by-layer technique is used to control the interface layer between the gate oxide and the Si substrate. The electrical properties of our stacked films are characterized by using capacitance versus voltage and leakage current versus voltage measurements. The stacked AlON/HfO{sub 2} gate oxide exhibits a low leakage current of about 10{sup -6} A/cm{sup 2} and a high dielectric constant value of 14.26 by effectively suppressing the interface layer between gate oxide and Si substrate. In addition, the chemical bond states and the optimum thickness of each AlON and HfO{sub 2} thin film are analyzed using X-ray photoemission spectroscopy and transmission electron microscopy measurement.

  15. Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices.

    Science.gov (United States)

    Black, Jennifer M; Come, Jeremy; Bi, Sheng; Zhu, Mengyang; Zhao, Wei; Wong, Anthony T; Noh, Joo Hyon; Pudasaini, Pushpa R; Zhang, Pengfei; Okatan, Mahmut Baris; Dai, Sheng; Kalinin, Sergei V; Rack, Philip D; Ward, Thomas Zac; Feng, Guang; Balke, Nina

    2017-11-22

    Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal-insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment and theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.

  16. Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure.

    Directory of Open Access Journals (Sweden)

    Z N Khan

    Full Text Available Metal Oxide Semiconductor (MOS capacitors (MOSCAP have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer, time-temperature cycle and sequence are key parameters influencing the device's output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application.

  17. Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs

    Science.gov (United States)

    Dentoni Litta, E.; Hellström, P.-E.; Östling, M.

    2015-06-01

    High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.

  18. Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

    Science.gov (United States)

    Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

    2013-06-01

    In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

  19. Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers.

    Science.gov (United States)

    Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

    2017-01-01

    Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

  20. SEMICONDUCTOR TECHNOLOGY: TaN wet etch for application in dual-metal-gate integration technology

    Science.gov (United States)

    Yongliang, Li; Qiuxia, Xu

    2009-12-01

    Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and Jg-Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.

  1. Ultra-fine metal gate operated graphene optical intensity modulator

    Science.gov (United States)

    Kou, Rai; Hori, Yosuke; Tsuchizawa, Tai; Warabi, Kaori; Kobayashi, Yuzuki; Harada, Yuichi; Hibino, Hiroki; Yamamoto, Tsuyoshi; Nakajima, Hirochika; Yamada, Koji

    2016-12-01

    A graphene based top-gate optical modulator on a standard silicon photonic platform is proposed for the future optical telecommunication networks. On the basis of the device simulation, we proposed that an electro-absorption light modulation can be realized by an ultra-narrow metal top-gate electrode (width less than 400 nm) directly located on the top of a silicon wire waveguide. The designed structure also provides excellent features such as carrier doping and waveguide-planarization free fabrication processes. In terms of the fabrication, we established transferring of a CVD-grown mono-layer graphene sheet onto a CMOS compatible silicon photonic sample followed by a 25-nm thick ALD-grown Al2O3 deposition and Source-Gate-Drain electrodes formation. In addition, a pair of low-loss spot-size converter for the input and output area is integrated for the efficient light source coupling. The maximum modulation depth of over 30% (1.2 dB) is observed at a device length of 50 μm, and a metal width of 300 nm. The influence of the initial Fermi energy obtained by experiment on the modulation performance is discussed with simulation results.

  2. Channel mobility degradation and charge trapping in high-k/metal gate NMOSFETs

    International Nuclear Information System (INIS)

    Mathew, Shajan; Bera, L.K.; Balasubramanian, N.; Joo, M.S.; Cho, B.J.

    2004-01-01

    NMOSFETs with Metalo-Organic Chemical Vapor Deposited (MOCVD) HfAlO gate dielectric and TiN metal gate have been fabricated. Channel electron mobility was measured using the split-CV method and compared with SiO 2 devices. All high-k devices showed lower mobility compared with SiO 2 reference devices. High-k MOSFETs exhibited significant charge trapping and threshold instability. Threshold voltage recovery with time was studied on devices with oxide/nitride interfacial layer between high-k film and silicon substrate

  3. Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

    Energy Technology Data Exchange (ETDEWEB)

    Inaba, Masafumi, E-mail: inaba-ma@ruri.waseda.jp; Muta, Tsubasa; Kobayashi, Mikinori; Saito, Toshiki; Shibata, Masanobu; Matsumura, Daisuke; Kudo, Takuya; Hiraiwa, Atsushi [Graduate School of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kawarada, Hiroshi [Graduate School of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kagami Memorial Laboratory for Materials Science and Technology, Waseda University, 2-8-26 Nishiwaseda, Shinjuku, Tokyo 169-0051 (Japan)

    2016-07-18

    The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al{sub 2}O{sub 3}. Using Al{sub 2}O{sub 3} as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulation by the gate and pinch off.

  4. Metal-Insulator-Metal Single Electron Transistors with Tunnel Barriers Prepared by Atomic Layer Deposition

    Directory of Open Access Journals (Sweden)

    Golnaz Karbasian

    2017-03-01

    Full Text Available Single electron transistors are nanoscale electron devices that require thin, high-quality tunnel barriers to operate and have potential applications in sensing, metrology and beyond-CMOS computing schemes. Given that atomic layer deposition is used to form CMOS gate stacks with low trap densities and excellent thickness control, it is well-suited as a technique to form a variety of tunnel barriers. This work is a review of our recent research on atomic layer deposition and post-fabrication treatments to fabricate metallic single electron transistors with a variety of metals and dielectrics.

  5. Anomalous positive flatband voltage shifts in metal gate stacks containing rare-earth oxide capping layers

    KAUST Repository

    Caraveo-Frescas, J. A.

    2012-03-09

    It is shown that the well-known negative flatband voltage (VFB) shift, induced by rare-earth oxide capping in metal gate stacks, can be completely reversed in the absence of the silicon overlayer. Using TaN metal gates and Gd2O3-doped dielectric, we measure a ∼350 mV negative shift with the Si overlayer present and a ∼110 mV positive shift with the Si overlayer removed. This effect is correlated to a positive change in the average electrostatic potential at the TaN/dielectric interface which originates from an interfacial dipole. The dipole is created by the replacement of interfacial oxygen atoms in the HfO2 lattice with nitrogen atoms from TaN.

  6. Gate-first integration of tunable work function metal gates of different thicknesses into high-k metal gates CMOS FinFETs for multi- VTh engineering

    KAUST Repository

    Hussain, Muhammad Mustafa; Smith, Casey Eben; Harris, Harlan Rusty; Young, Chadwin; Tseng, Hsinghuang; Jammy, Rajarao

    2010-01-01

    Gate-first integration of tunable work function metal gates of different thicknesses (320 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ∼ 40 mV/V), nearly symmetric VTh, low T inv(∼ 1.4 nm), and high Ion(∼780μAμm) for N/PMOS without any intentional strain enhancement. © 2006 IEEE.

  7. Gate-first integration of tunable work function metal gates of different thicknesses into high-k metal gates CMOS FinFETs for multi- VTh engineering

    KAUST Repository

    Hussain, Muhammad Mustafa

    2010-03-01

    Gate-first integration of tunable work function metal gates of different thicknesses (320 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ∼ 40 mV/V), nearly symmetric VTh, low T inv(∼ 1.4 nm), and high Ion(∼780μAμm) for N/PMOS without any intentional strain enhancement. © 2006 IEEE.

  8. Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

    Science.gov (United States)

    Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J

    2016-06-09

    Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

  9. Interface engineering and reliability characteristics of hafnium dioxide with poly silicon gate and dual metal (ruthenium-tantalum alloy, ruthenium) gate electrode for beyond 65 nm technology

    Science.gov (United States)

    Kim, Young-Hee

    Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is

  10. Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors.

    Science.gov (United States)

    Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

    2016-12-01

    In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade(-1) and 3.62 × 10(11) eV(-1) cm(-2), respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

  11. Thickness engineering of atomic layer deposited Al2O3 films to suppress interfacial reaction and diffusion of Ni/Au gate metal in AlGaN/GaN HEMTs up to 600 °C in air

    Science.gov (United States)

    Suria, Ateeq J.; Yalamarthy, Ananth Saran; Heuser, Thomas A.; Bruefach, Alexandra; Chapin, Caitlin A.; So, Hongyun; Senesky, Debbie G.

    2017-06-01

    In this paper, we describe the use of 50 nm atomic layer deposited (ALD) Al2O3 to suppress the interfacial reaction and inter-diffusion between the gate metal and semiconductor interface, to extend the operation limit up to 600 °C in air. Suppression of diffusion is verified through Auger electron spectroscopy (AES) depth profiling and X-ray diffraction (XRD) and is further supported with electrical characterization. An ALD Al2O3 thin film (10 nm and 50 nm), which functions as a dielectric layer, was inserted between the gate metal (Ni/Au) and heterostructure-based semiconductor material (AlGaN/GaN) to form a metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). This extended the 50 nm ALD Al2O3 MIS-HEMT (50-MIS) current-voltage (Ids-Vds) and gate leakage (Ig,leakage) characteristics up to 600 °C. Both, the 10 nm ALD Al2O3 MIS-HEMT (10-MIS) and HEMT, failed above 350 °C, as evidenced by a sudden increase of approximately 50 times and 5.3 × 106 times in Ig,leakage, respectively. AES on the HEMT revealed the formation of a Ni-Au alloy and Ni present in the active region. Additionally, XRD showed existence of metal gallides in the HEMT. The 50-MIS enables the operation of AlGaN/GaN based electronics in oxidizing high-temperature environments, by suppressing interfacial reaction and inter-diffusion of the gate metal with the semiconductor.

  12. Memory characteristics of an MOS capacitor structure with double-layer semiconductor and metal heterogeneous nanocrystals

    International Nuclear Information System (INIS)

    Ni Henan; Wu Liangcai; Song Zhitang; Hui Chun

    2009-01-01

    An MOS (metal oxide semiconductor) capacitor structure with double-layer heterogeneous nanocrystals consisting of semiconductor and metal embedded in a gate oxide for nonvolatile memory applications has been fabricated and characterized. By combining vacuum electron-beam co-evaporated Si nanocrystals and self-assembled Ni nanocrystals in a SiO 2 matrix, an MOS capacitor with double-layer heterogeneous nanocrystals can have larger charge storage capacity and improved retention characteristics compared to one with single-layer nanocrystals. The upper metal nanocrystals as an additional charge trap layer enable the direct tunneling mechanism to enhance the flat voltage shift and prolong the retention time. (semiconductor devices)

  13. Piezophototronic Effect in Single-Atomic-Layer MoS 2 for Strain-Gated Flexible Optoelectronics

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Wenzhuo [School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta GA 30332-0245 USA; Wang, Lei [Department of Electrical Engineering, Columbia University, New York NY 10027 USA; Yu, Ruomeng [School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta GA 30332-0245 USA; Liu, Yuanyue [National Renewable Energy Laboratory (NREL), Golden CO 80401 USA; Wei, Su-Huai [National Renewable Energy Laboratory (NREL), Golden CO 80401 USA; Hone, James [Department of Mechanical Engineering, Columbia University, New York NY 10027 USA; Wang, Zhong Lin [School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta GA 30332-0245 USA; Beijing Institute of Nanoenergy and Nanosystems, Chinese Academy of Sciences, 100083 Beijing China

    2016-08-03

    Strain-gated flexible optoelectronics are reported based on monolayer MoS2. Utilizing the piezoelectric polarization created at metal-MoS2 interface to modulate the separation/transport of photogenerated carriers, the piezophototronic effect is applied to implement atomic-layer-thick phototransistor. Coupling between piezoelectricity and photogenerated carriers may enable the development of novel optoelectronics.

  14. Effects of a metallic front gate on the temperature-dependent electronic property of pentacene films

    Energy Technology Data Exchange (ETDEWEB)

    Lin, Yow-Jon, E-mail: rzr2390@yahoo.com.tw [Institute of Photonics, National Changhua University of Education, Changhua 500, Taiwan (China); Tsao, Hou-Yen [Institute of Photonics, National Changhua University of Education, Changhua 500, Taiwan (China); Liu, Day-Shan [Graduate Institute of Electro-Optical and Materials Science, National Formosa University, Huwei 632, Taiwan (China)

    2014-11-14

    The effect of a metallic front gate on the temperature-dependent electronic property of pentacene films was investigated in this study. The carrier mobility exhibits strong temperature dependence, implying the dominance of tunneling (hopping) at low (high) temperatures. The room-temperature mobility was drastically increased by capping an In (Au) layer on the pentacene front surface. However, the carrier concentration is not affected. An increase in the phonon energy occurs for In-capped or Au-capped pentacene samples, which corresponds to the abrupt transition to the nonlocal electron–phonon coupling. The enhanced mobility by capping a metal layer is attributed to a change in the electron–phonon coupling. - Highlights: • For the metal-capped and uncapped pentacene films, the mobility was researched. • The mobility was dramatically increased by capping an In (Au) layer. • The induced strain by capping a metal layer is found. • The strain may lead to the electron–phonon coupling variation. • The enhanced mobility is attributed to the weakened electron–phonon coupling.

  15. Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

    Science.gov (United States)

    An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

    2016-11-01

    Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

  16. Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology

    International Nuclear Information System (INIS)

    Weng, W.T.; Lin, H.C.; Huang, T.Y.; Lee, Y.J.; Lin, H.C.

    2009-01-01

    This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO 2 /poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

  17. All-metallic electrically gated 2H-TaSe2 thin-film switches and logic circuits

    International Nuclear Information System (INIS)

    Renteria, J.; Jiang, C.; Yan, Z.; Samnakay, R.; Goli, P.; Pope, T. R.; Salguero, T. T.; Wickramaratne, D.; Lake, R. K.; Khitun, A. G.; Balandin, A. A.

    2014-01-01

    We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe 2 were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe 2 –Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials

  18. All-metallic electrically gated 2H-TaSe2 thin-film switches and logic circuits

    Science.gov (United States)

    Renteria, J.; Samnakay, R.; Jiang, C.; Pope, T. R.; Goli, P.; Yan, Z.; Wickramaratne, D.; Salguero, T. T.; Khitun, A. G.; Lake, R. K.; Balandin, A. A.

    2014-01-01

    We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe2 were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe2-Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials.

  19. Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

    Directory of Open Access Journals (Sweden)

    Paul C. McIntyre

    2012-07-01

    Full Text Available The literature on polar Gallium Nitride (GaN surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

  20. Fabrication and independent control of patterned polymer gate for a few-layer WSe{sub 2} field-effect transistor

    Energy Technology Data Exchange (ETDEWEB)

    Hong, Sung Ju; Park, Min; Kang, Hojin; Park, Yung Woo, E-mail: ywpark@snu.ac.kr [Department of Physics and Astronomy, Seoul National University, Seoul 151-747 (Korea, Republic of); Lee, Minwoo; Jeong, Dae Hong [Department of Chemistry Education, Seoul National University, Seoul 151-742 (Korea, Republic of)

    2016-08-15

    We report the fabrication of a patterned polymer electrolyte for a two-dimensional (2D) semiconductor, few-layer tungsten diselenide (WSe{sub 2}) field-effect transistor (FET). We expose an electron-beam in a desirable region to form the patterned structure. The WSe{sub 2} FET acts as a p-type semiconductor in both bare and polymer-covered devices. We observe a highly efficient gating effect in the polymer-patterned device with independent gate control. The patterned polymer gate operates successfully in a molybdenum disulfide (MoS{sub 2}) FET, indicating the potential for general applications to 2D semiconductors. The results of this study can contribute to large-scale integration and better flexibility in transition metal dichalcogenide (TMD)-based electronics.

  1. Controlling the layer localization of gapless states in bilayer graphene with a gate voltage

    Science.gov (United States)

    Jaskólski, W.; Pelc, M.; Bryant, Garnett W.; Chico, Leonor; Ayuela, A.

    2018-04-01

    Experiments in gated bilayer graphene with stacking domain walls present topological gapless states protected by no-valley mixing. Here we research these states under gate voltages using atomistic models, which allow us to elucidate their origin. We find that the gate potential controls the layer localization of the two states, which switches non-trivially between layers depending on the applied gate voltage magnitude. We also show how these bilayer gapless states arise from bands of single-layer graphene by analyzing the formation of carbon bonds between layers. Based on this analysis we provide a model Hamiltonian with analytical solutions, which explains the layer localization as a function of the ratio between the applied potential and interlayer hopping. Our results open a route for the manipulation of gapless states in electronic devices, analogous to the proposed writing and reading memories in topological insulators.

  2. All-metallic electrically gated 2H-TaSe{sub 2} thin-film switches and logic circuits

    Energy Technology Data Exchange (ETDEWEB)

    Renteria, J.; Jiang, C.; Yan, Z. [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Samnakay, R.; Goli, P. [Materials Science and Engineering Program, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Pope, T. R.; Salguero, T. T. [Department of Chemistry, University of Georgia, Athens, Georgia 30602 (United States); Wickramaratne, D.; Lake, R. K. [Laboratory for Terascale and Terahertz Electronics, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Khitun, A. G. [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Materials Science and Engineering Program, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Balandin, A. A., E-mail: balandin@ee.ucr.edu [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Department of Chemistry, University of Georgia, Athens, Georgia 30602 (United States)

    2014-01-21

    We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe{sub 2} were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe{sub 2}–Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials.

  3. Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high- k metal gate NMOSFET with kMC TDDB simulations

    International Nuclear Information System (INIS)

    Xu Hao; Yang Hong; Luo Wei-Chun; Xu Ye-Feng; Wang Yan-Rong; Tang Bo; Wang Wen-Wu; Qi Lu-Wei; Li Jun-Feng; Yan Jiang; Zhu Hui-Long; Zhao Chao; Chen Da-Peng; Ye Tian-Chun

    2016-01-01

    The thickness effect of the TiN capping layer on the time dependent dielectric breakdown (TDDB) characteristic of ultra-thin EOT high- k metal gate NMOSFET is investigated in this paper. Based on experimental results, it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer. From the charge pumping measurement and secondary ion mass spectroscopy (SIMS) analysis, it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density. In addition, the influences of interface and bulk trap density ratio N it / N ot are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo (kMC) method. The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses. (paper)

  4. Novel Dry-Type Glucose Sensor Based on a Metal-Oxide-Semiconductor Capacitor Structure with Horseradish Peroxidase + Glucose Oxidase Catalyzing Layer

    Science.gov (United States)

    Lin, Jing-Jenn; Wu, You-Lin; Hsu, Po-Yen

    2007-10-01

    In this paper, we present a novel dry-type glucose sensor based on a metal-oxide-semiconductor capacitor (MOSC) structure using SiO2 as a gate dielectric in conjunction with a horseradish peroxidase (HRP) + glucose oxidase (GOD) catalyzing layer. The tested glucose solution was dropped directly onto the window opened on the SiO2 layer, with a coating of HRP + GOD catalyzing layer on top of the gate dielectric. From the capacitance-voltage (C-V) characteristics of the sensor, we found that the glucose solution can induce an inversion layer on the silicon surface causing a gate leakage current flowing along the SiO2 surface. The gate current changes Δ I before and after the drop of glucose solution exhibits a near-linear relationship with increasing glucose concentration. The Δ I sensitivity is about 1.76 nA cm-2 M-1, and the current is quite stable 20 min after the drop of the glucose solution is tested.

  5. Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

    Science.gov (United States)

    Jayanti, Srikant

    Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG

  6. Gate-controlled metal-insulator transition in the LaAlO{sub 3}/SrTiO{sub 3} system with sub-critical LaAlO{sub 3} thickness

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Joon Sung; Lee, Seung Ran; Chang, Jung-Won; Noh, Hyunho; Baasandorj, Lkhagvasuren; Shim, Seung-Bo; Kim, Jinhee [Korea Research Institute of Standards and Science, Daejeon 305-600 (Korea, Republic of); Seung, Sang Keun; Shin, Hyun Sup; Song, Jonghyun [Department of Physics, Chungnam National University, Daejeon 305-764 (Korea, Republic of)

    2012-12-15

    We studied the electrical conduction in the LaAlO{sub 3}/SrTiO{sub 3} (LAO/STO) interface electron system with a sub-critical LAO layer thickness of {proportional_to}3.5 unit cells (uc). It was found that the true dividing point between metallic and insulating behaviour without gating lies near the LAO thickness of 3.5 uc. Our marginally metallic 3.5 uc sample showed a sharp transition to insulating state at temperatures which strongly depended on the applied negative back-gate voltage. The superior gate-controllability of the sample was attributed to its sheet carrier density which was an order of magnitude lower than those of conducting LAO/STO samples with 4 uc or more of LAO layers. (copyright 2012 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  7. Work Function Tuning in Sub-20nm Titanium Nitride (TiN) Metal Gate: Mechanism and Engineering

    KAUST Repository

    Hasan, Mehdi

    2011-07-01

    Scaling of transistors (the building blocks of modern information age) provides faster computation at the expense of excessive power dissipation. Thus to address these challenges, high-k/metal gate stack has been introduced in commercially available microprocessors from 2007. Since then titanium nitride (TiN) metal gate’s work function (Wf) tunability with its thickness (thickness increases, work function increases) is a well known phenomenon. Many hypotheses have been made over the years which include but not limited to: trap charge and metal gate nucleation, nitrogen concentration, microstructure agglomeration and global stress, metal oxide formation, and interfacial oxide thickness. However, clear contradictions exist in these assumptions. Also, nearly all these reports skipped a comprehensive approach to explain this complex paradigm. Therefore, in this work we first show a comprehensive physical investigation using transmission electron microcopy/electron energy loss spectroscopy (TEM/EELS), x-ray diffraction (XRD), x-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS) to show replacement of oxygen by nitrogen in the metal/dielectric interface, formation of TiONx, reduction of Ti/N concentration and grain size increment happen with TiN thickness increment and thus may increase the work function. Then, using these finding, we experimentally show 100meV of work function modulation in 10nm TiN Metal-oxide-semiconductor capacitor by using low temperature oxygen annealing. A low thermal budget flow (replicating gate-last) shows similar work function boost up. Also, a work function modulation of 250meV has been possible using oxygen annealing and applying no thermal budget. On the other hand, etch-back of TiN layer can decrease the work function. Thus this study quantifies role of various factors in TiN work function tuning; it also reproduces the thickness varied TiN work function modulation in single thickness TiN thus reducing the

  8. Atomic-Layer-Deposited SnO2 as Gate Electrode for Indium-Free Transparent Electronics

    KAUST Repository

    Alshammari, Fwzah Hamud

    2017-08-04

    Atomic-layer-deposited SnO2 is used as a gate electrode to replace indium tin oxide (ITO) in thin-film transistors and circuits for the first time. The SnO2 films deposited at 200 °C show low electrical resistivity of ≈3.1 × 10−3 Ω cm with ≈93% transparency in most of the visible range of the electromagnetic spectrum. Thin-film transistors fabricated with SnO2 gates show excellent transistor properties including saturation mobility of 15.3 cm2 V−1 s−1, a low subthreshold swing of ≈130 mV dec−1, a high on/off ratio of ≈109, and an excellent electrical stability under constant-voltage stressing conditions to the gate terminal. Moreover, the SnO2-gated thin-film transistors show excellent electrical characteristics when used in electronic circuits such as negative channel metal oxide semiconductor (NMOS) inverters and ring oscillators. The NMOS inverters exhibit a low propagation stage delay of ≈150 ns with high DC voltage gain of ≈382. A high oscillation frequency of ≈303 kHz is obtained from the output sinusoidal signal of the 11-stage NMOS inverter-based ring oscillators. These results show that SnO2 can effectively replace ITO in transparent electronics and sensor applications.

  9. Design and Optimization of 22 nm Gate Length High-k/Metal gate NMOS Transistor

    International Nuclear Information System (INIS)

    Afifah Maheran A H; Menon P S; Shaari, S; Elgomati, H A; Salehuddin, F; Ahmad, I

    2013-01-01

    In this paper, we invented the optimization experiment design of a 22 nm gate length NMOS device which uses a combination of high-k material and metal as the gate which was numerically developed using an industrial-based simulator. The high-k material is Titanium dioxide (TiO 2 ), while the metal gate is Tungsten Silicide (WSi x ). The design is optimized using the L9 Taguchi method to get the optimum parameter design. There are four process parameters and two noise parameters which were varied for analyzing the effect on the threshold voltage (V th ). The objective of this experiment is to minimize the variance of V th where Taguchi's nominal-the-best signal-to-noise ratio (S/N Ratio) was used. The best settings of the process parameters were determined using Analysis of Mean (ANOM) and analysis of variance (ANOVA) to reduce the variability of V th . The results show that the V th values have least variance and the mean value can be adjusted to 0.306V ±0.027 for the NMOS device which is in line with projections by the ITRS specifications.

  10. Influence of ultra-thin TiN thickness (1.4 nm and 2.4 nm) on positive bias temperature instability (PBTI) of high-k/metal gate nMOSFETs with gate-last process

    International Nuclear Information System (INIS)

    Qi Lu-Wei; Yang Hong; Ren Shang-Qing; Xu Ye-Feng; Luo Wei-Chun; Xu Hao; Wang Yan-Rong; Tang Bo; Wang Wen-Wu; Yan Jiang; Zhu Hui-Long; Zhao Chao; Chen Da-Peng; Ye Tian-Chun

    2015-01-01

    The positive bias temperature instability (PBTI) degradations of high-k/metal gate (HK/MG) nMOSFETs with thin TiN capping layers (1.4 nm and 2.4 nm) are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI (90 °C, 125 °C, 160 °C) are studied and activation energy (E a ) values (0.13 eV and 0.15 eV) are extracted. Although the equivalent oxide thickness (EOT) values of two TiN thickness values are almost similar (0.85 nm and 0.87 nm), the 2.4-nm TiN one (thicker TiN capping layer) shows better PBTI reliability (13.41% at 0.9 V, 90 °C, 1000 s). This is due to the better interfacial layer/high-k (IL/HK) interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer. (paper)

  11. Characterization, integration and reliability of HfO2 and LaLuO3 high-κ/metal gate stacks for CMOS applications

    International Nuclear Information System (INIS)

    Nichau, Alexander

    2013-01-01

    The continued downscaling of MOSFET dimensions requires an equivalent oxide thickness (EOT) of the gate stack below 1 nm. An EOT below 1.4 nm is hereby enabled by the use of high-κ/metal gate stacks. LaLuO 3 and HfO 2 are investigated as two different high-κ oxides on silicon in conjunction with TiN as the metal electrode. LaLuO 3 and its temperature-dependent silicate formation are characterized by hard X-ray photoemission spectroscopy (HAXPES). The effective attenuation length of LaLuO 3 is determined between 7 and 13 keV to enable future interface and diffusion studies. In a first investigation of LaLuO 3 on germanium, germanate formation is shown. LaLuO 3 is further integrated in a high-temperature MOSFET process flow with varying thermal treatment. The devices feature drive currents up to 70μA/μm at 1μm gate length. Several optimization steps are presented. The effective device mobility is related to silicate formation and thermal budget. At high temperature the silicate formation leads to mobility degradation due to La-rich silicate formation. The integration of LaLuO 3 in high-T processes delicately connects with the optimization of the TiN metal electrode. Hereby, stoichiometric TiN yields the best results in terms of thermal stability with respect to Si-capping and high-κ oxide. Different approaches are presented for a further EOT reduction with LaLuO 3 and HfO 2 . Thereby the thermodynamic and kinetic predictions are employed to estimate the behavior on the nanoscale. Based on thermodynamics, excess oxygen in the gate stack, especially in oxidized metal electrodes, is identified to prevent EOT scaling below 1.2 nm. The equivalent oxide thickness of HfO 2 gate stacks is scalable below 1 nm by the use of thinned interfacial SiO 2 . The prevention of oxygen incorporation into the metal electrode by Si-capping maintains the EOT after high temperature annealing. Redox systems are employed within the gate electrode to decrease the EOT of HfO 2 gate stacks

  12. Study of the tunnelling initiated leakage current through the carbon nanotube embedded gate oxide in metal oxide semiconductor structures

    International Nuclear Information System (INIS)

    Chakraborty, Gargi; Sarkar, C K; Lu, X B; Dai, J Y

    2008-01-01

    The tunnelling currents through the gate dielectric partly embedded with semiconducting single-wall carbon nanotubes in a silicon metal-oxide-semiconductor (MOS) structure have been investigated. The application of the gate voltage to such an MOS device results in the band bending at the interface of the partly embedded oxide dielectric and the surface of the silicon, initiating tunnelling through the gate oxide responsible for the gate leakage current whenever the thickness of the oxide is scaled. A model for silicon MOS structures, where carbon nanotubes are confined in a narrow layer embedded in the gate dielectric, is proposed to investigate the direct and the Fowler-Nordheim (FN) tunnelling currents of such systems. The idea of embedding such elements in the gate oxide is to assess the possibility for charge storage for memory device applications. Comparing the FN tunnelling onset voltage between the pure gate oxide and the gate oxide embedded with carbon nanotubes, it is found that the onset voltage decreases with the introduction of the nanotubes. The direct tunnelling current has also been studied at very low gate bias, for the thin oxide MOS structure which plays an important role in scaling down the MOS transistors. The FN tunnelling current has also been studied with varying nanotube diameter

  13. Lg = 100 nm In0.7Ga0.3As quantum well metal-oxide semiconductor field-effect transistors with atomic layer deposited beryllium oxide as interfacial layer

    International Nuclear Information System (INIS)

    Koh, D.; Kwon, H. M.; Kim, T.-W.; Veksler, D.; Gilmer, D.; Kirsch, P. D.; Kim, D.-H.; Hudnall, Todd W.; Bielawski, Christopher W.; Maszara, W.; Banerjee, S. K.

    2014-01-01

    In this study, we have fabricated nanometer-scale channel length quantum-well (QW) metal-oxide-semiconductor field effect transistors (MOSFETs) incorporating beryllium oxide (BeO) as an interfacial layer. BeO has high thermal stability, excellent electrical insulating characteristics, and a large band-gap, which make it an attractive candidate for use as a gate dielectric in making MOSFETs. BeO can also act as a good diffusion barrier to oxygen owing to its small atomic bonding length. In this work, we have fabricated In 0.53 Ga 0.47 As MOS capacitors with BeO and Al 2 O 3 and compared their electrical characteristics. As interface passivation layer, BeO/HfO 2 bilayer gate stack presented effective oxide thickness less 1 nm. Furthermore, we have demonstrated In 0.7 Ga 0.3 As QW MOSFETs with a BeO/HfO 2 dielectric, showing a sub-threshold slope of 100 mV/dec, and a transconductance (g m,max ) of 1.1 mS/μm, while displaying low values of gate leakage current. These results highlight the potential of atomic layer deposited BeO for use as a gate dielectric or interface passivation layer for III–V MOSFETs at the 7 nm technology node and/or beyond

  14. Characteristics of dual-gate thin-film transistors for applications in digital radiology

    International Nuclear Information System (INIS)

    Waechter, D.; Huang, Z.; Zhao, W.; Blevis, I.; Rowlands, J.A.

    1996-01-01

    A large-area flat-panel detector for digital radiology is being developed. The detector uses an array of dual-gate thin-film transistors (TFTs) to read out X-ray-generated charge produced in an amorphous selenium (a-Se) layer. The TFTs use CdSe as the semiconductor and use the bottom gate for row selection. The top gate can be divided into a 'deliberate' gate, covering most of the channel length, and small 'parasitic' gates that consist of: overlap of source or drain metal over the top-gate oxide; and gap regions in the metal that are covered only by the a-Se. In this paper we present the properties of dual-gate TFTs and examine the effect of both the deliberate and parasitic gates on the detector operation. Various options for controlling the top-gate potential are analyzed and discussed. (author)

  15. Optimum source/drain overlap design for 16 nm high-k/metal gate MOSFETs

    International Nuclear Information System (INIS)

    Jang, Junyong; Lim, Towoo; Kim, Youngmin

    2009-01-01

    We explore a source/drain (S/D) design for a 16 nm MOSFET utilizing a replacement process for a high-k gate dielectric and metal gate electrode integration. Using TCAD simulation, a trade-off study between series resistance and overlap capacitance is carried out for a high-k dielectric surrounding gate structure, which results from the replacement process. An optimum S/D overlap to gate for the high-k surrounding gate structure is found to be different from the conventional gate structure, i.e. 0∼1 nm underlap is preferred for the surround high-k gate structure while 1∼2 nm overlap for the conventional gate one

  16. Electrical and materials properties of AlN/ HfO{sub 2} high-k stack with a metal gate

    Energy Technology Data Exchange (ETDEWEB)

    Reid, Kimberly G. [Tokyo Electron U.S., 14338 FM 1826, Austin, TX 78737 (United States)], E-mail: kim@ireid.com; Dip, Anthony [Tokyo Electron U.S., 2400 Grove Blvd., Austin, TX 78747 (United States)], E-mail: anthony.dip@us.tel.com; Sasaki, Sadao [Tokyo Electron U.S. (United States)], E-mail: Sadao.sasaki@us.tel.com; Triyoso, Dina [Freescale Semiconductor Inc., 3501 Ed Bluestein Blvd, Austin, TX 78721 (United States)], E-mail: Dina.Triyoso@freescale.com; Samavedam, Sri [Freescale Semiconductor Inc., 3501 Ed Bluestein Blvd, Austin, TX 78721 (United States)], E-mail: Sri.Samavedam@freescale.com; Gilmer, David [SEMATECH 2706 Montopolis Drive, Austin, TX 78741 (United States)], E-mail: David.Gilmer@sematech.org; Gondran, Carolyn F.H. [Process Characterization Laboratory, ATDF/SEMATECH, 2706 Montopolis Drive, Austin, Texas 78741 (United States)], E-mail: Carolyn.Gondran@atdf.com

    2009-02-27

    In this study, aluminum nitride (AlN) was grown by molecular layer deposition on HfO{sub 2} that had been deposited on 200 mm Si (100) substrates. The AlN was grown on HfO{sub 2} using sequential exposures of trimethyl-aluminum and ammonia (NH{sub 3}) in a batch vertical furnace. Excellent thickness uniformity on test wafers from the top of the furnace to the bottom of the furnace (across the furnace load) was obtained. The equivalent oxide thickness was 16.5-18.8 A for the AlN/HfO{sub 2} stack on patterned device wafers with a molybdenum oxynitride metal gate with leakage current densities from low 10{sup -5} to mid 10{sup -6} A/cm{sup 2} at threshold voltage minus one volt. There was no change in the work function with the AlN cap on HfO{sub 2} with the MoN metal gate, even with a 1000 deg. C anneal.

  17. Fermi level pinning in metal/Al{sub 2}O{sub 3}/InGaAs gate stack after post metallization annealing

    Energy Technology Data Exchange (ETDEWEB)

    Winter, R.; Krylov, I.; Cytermann, C.; Eizenberg, M. [Department of Materials Science and Engineering, Technion—Israel Institute of Technology, Haifa 32000 (Israel); Tang, K.; Ahn, J.; McIntyre, P. C. [Department of Materials Science and Engineering, Stanford University, Stanford, California 94305 (United States)

    2015-08-07

    The effect of post metal deposition annealing on the effective work function in metal/Al{sub 2}O{sub 3}/InGaAs gate stacks was investigated. The effective work functions of different metal gates (Al, Au, and Pt) were measured. Flat band voltage shifts for these and other metals studied suggest that their Fermi levels become pinned after the post-metallization vacuum annealing. Moreover, there is a difference between the measured effective work functions of Al and Pt, and the reported vacuum work function of these metals after annealing. We propose that this phenomenon is caused by charging of indium and gallium induced traps at the annealed metal/Al{sub 2}O{sub 3} interface.

  18. Simulation study of 14-nm-gate III-V trigate field effect transistor devices with In1−xGaxAs channel capping layer

    Directory of Open Access Journals (Sweden)

    Cheng-Hao Huang

    2015-06-01

    Full Text Available In this work, we study characteristics of 14-nm-gate InGaAs-based trigate MOSFET (metal-oxide-semiconductor field effect transistor devices with a channel capping layer. The impacts of thickness and gallium (Ga concentration of the channel capping layer on the device characteristic are firstly simulated and optimized by using three-dimensional quantum-mechanically corrected device simulation. Devices with In1−xGaxAs/In0.53Ga0.47As channels have the large driving current owing to small energy band gap and low alloy scattering at the channel surface. By simultaneously considering various physical and switching properties, a 4-nm-thick In0.68Ga0.32As channel capping layer can be adopted for advanced applications. Under the optimized channel parameters, we further examine the effects of channel fin angle and the work-function fluctuation (WKF resulting from nano-sized metal grains of NiSi gate on the characteristic degradation and variability. To maintain the device characteristics and achieve the minimal variation induced by WKF, the physical findings of this study indicate a critical channel fin angle of 85o is needed for the device with an averaged grain size of NiSi below 4x4 nm2.

  19. High-Mobility 6,13-Bis(triisopropylsilylethynyl) Pentacene Transistors Using Solution-Processed Polysilsesquioxane Gate Dielectric Layers.

    Science.gov (United States)

    Matsuda, Yu; Nakahara, Yoshio; Michiura, Daisuke; Uno, Kazuyuki; Tanaka, Ichiro

    2016-04-01

    Polysilsesquioxane (PSQ) is a low-temperature curable polymer that is compatible with low-cost plastic substrates. We cured PSQ gate dielectric layers by irradiation with ultraviolet light at ~60 °C, and used them for 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) thin film transistors (TFTs). The fabricated TFTs have shown the maximum and average hole mobility of 1.3 and 0.78 ± 0.3 cm2V-1s-1, which are comparable to those of the previously reported transistors using single-crystalline TIPS-pentacene micro-ribbons for their active layers and thermally oxidized SiO2 for their gate dielectric layers. Itis therefore demonstrated that PSQ is a promising polymer gate dielectric material for low-cost organic TFTs.

  20. SO-limited mobility in a germanium inversion channel with non-ideal metal gate

    International Nuclear Information System (INIS)

    Shah, Raheel; De Souza, M.M.

    2008-01-01

    Germanium is an attractive candidate for ultra fast CMOS technology due to its potential for doubling electron mobility and quadrupling hole mobility in comparison to silicon. To maintain the requirements of the International Technology Roadmap for Semiconductors (ITRS), high-κ insulators and metal gates will be required in conjunction with Ge technology. Key issues which will have to be addressed in achieving Ge technology are: trap free insulators, assessment of appropriate crystallographic orientations and the selection of gate metals for the best mobility. In this work mobilities are evaluated for Ge-nMOSFET with two metal gates (Al and TiN) and high-κ (HfO 2 ) insulator. Scattering with bulk phonons, surface roughness and high-κ phonons are taken into account. It is predicted that Al as the gate material on Ge {100} substrate performs 50% better than Ge {111} orientation at a sheet concentration of 1 x 10 13 cm -2 . Surface roughness is likely to be the most damaging mobility degradation mechanism at high fields for Ge {111}

  1. Effect of a gate buffer layer on the performance of a 4H-SiC Schottky barrier field-effect transistor

    International Nuclear Information System (INIS)

    Zhang Xianjun; Yang Yintang; Chai Changchun; Duan Baoxing; Song Kun; Chen Bin

    2012-01-01

    A lower doped layer is inserted between the gate and channel layer and its effect on the performance of a 4H-SiC Schottky barrier field-effect transistor (MESFET) is investigated. The dependences of the drain current and small signal parameters on this inserted gate-buffer layer are obtained by solving one-dimensional (1-D) and two-dimensional (2-D) Poisson's equations. The drain current and small signal parameters of the 4H-SiC MESFET with a gate-buffer layer thickness of 0.15 μm are calculated and the breakdown characteristics are simulated. The results show that the current is increased by increasing the thickness of the gate-buffer layer; the breakdown voltage is 160 V, compared with 125 V for the conventional 4H-SiC MESFET; the cutoff frequency is 27 GHz, which is higher than 20 GHz of the conventional structure due to the lower doped gate-buffer layer. (semiconductor devices)

  2. GeO{sub x} interfacial layer scavenging remotely induced by metal electrode in metal/HfO{sub 2}/GeO{sub x}/Ge capacitors

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Taehoon; Jung, Yong Chan; Seong, Sejong; Ahn, Jinho, E-mail: jhahn@hanyang.ac.kr [Department of Materials Science and Engineering, Hanyang University, Seoul 04763 (Korea, Republic of); Lee, Sung Bo [Department of Materials Science and Engineering and Research Institute of Advanced Materials (RIAM), Seoul National University, Seoul 08826 (Korea, Republic of); Park, In-Sung, E-mail: parkis77@hanyang.ac.kr [Department of Materials Science and Engineering, Hanyang University, Seoul 04763 (Korea, Republic of); Institute of Nano Science and Technology, Hanyang University, Seoul 04763 (Korea, Republic of)

    2016-07-11

    The metal gate electrodes of Ni, W, and Pt have been investigated for their scavenging effect: a reduction of the GeO{sub x} interfacial layer (IL) between HfO{sub 2} dielectric and Ge substrate in metal/HfO{sub 2}/GeO{sub x}/Ge capacitors. All the capacitors were fabricated using the same process except for the material used in the metal electrodes. Capacitance-voltage measurements, scanning transmission electron microscopy, and electron energy loss spectroscopy were conducted to confirm the scavenging of GeO{sub x} IL. Interestingly, these metals are observed to remotely scavenge the interfacial layer, reducing its thickness in the order of Ni, W, and then Pt. The capacitance equivalent thickness of these capacitors with Ni, W, and Pt electrodes are evaluated to be 2.7 nm, 3.0 nm, and 3.5 nm, and each final remnant physical thickness of GeO{sub x} IL layer is 1.1 nm 1.4 nm, and 1.9 nm, respectively. It is suggested that the scavenging effect induced by the metal electrodes is related to the concentration of oxygen vacancies generated by oxidation reaction at the metal/HfO{sub 2} interface.

  3. The Aharonov-Bohm effect in a side-gated graphene ring

    International Nuclear Information System (INIS)

    Huefner, Magdalena; Molitor, Francoise; Jacobsen, Arnhild; Pioda, Alessandro; Stampfer, Christoph; Ensslin, Klaus; Ihn, Thomas

    2010-01-01

    We investigate the magnetoresistance of a side-gated ring structure etched out of single-layer graphene. We observe Aharonov-Bohm oscillations with about 5% visibility. We are able to change the relative phases of the wave functions in the interfering paths and induce phase jumps of π in the Aharonov-Bohm oscillations by changing the voltage applied to the side gate or the back gate. The observed data can be interpreted within existing models for 'dirty metals'.

  4. A refractory metal gate approach for micronic CMOS technology

    International Nuclear Information System (INIS)

    Lubowiecki, V.; Ledys, J.L.; Plossu, C.; Balland, B.

    1987-01-01

    In the future, devices scaling down, integration density and performance improvements are going to bring a number of conventional circuit design and process techniques to their fundamental limits. To avoid any severe limitations in MOS ULSI (Ultra Large Scale Integration) technologies, interconnection materials and schemes are required to emerge, in order to face the Megabits memory field. Among those, the gate approach will obviously take a keyrole, when the operating speed of ULSI chips will reach the practical upper limits imposed by parasitic resistances and capacitances which stem from the circuit interconnect wiring. Even if fairly suitable for MOS process, doped polycrystalline silicon is being gradually replaced by refractory metal silicide or polycide structures, which match better with low resistivity requirements. However, as we approach the submicronic IC's, higher conductivity materials will be paid more and more attention. Recently, works have been devoted and published on refractory metal gate technologies. Molybdenum or tungsten, deposited either by CVD or PVD methods, are currently reported even if some drawbacks in their process integration still remain. This paper is willing to present such an approach based on tungsten (more reliable than Molybdenum deposited by LPCVD (giving more conductive and more stable films than PVD). Deposition process will be first described. Then CMOS process flow will allow us to focus on specific refractory metal gate issues. Finally, electrical and physical properties will be assessed, which will demonstrate the feasibility of such a technology as well as the compatibility of the tungsten with most of the usual techniques

  5. Scanning gate microscopy on graphene: charge inhomogeneity and extrinsic doping

    International Nuclear Information System (INIS)

    Jalilian, Romaneh; Tian Jifa; Chen, Yong P; Jauregui, Luis A; Lopez, Gabriel; Roecker, Caleb; Jovanovic, Igor; Yazdanpanah, Mehdi M; Cohn, Robert W

    2011-01-01

    We have performed scanning gate microscopy (SGM) on graphene field effect transistors (GFET) using a biased metallic nanowire coated with a dielectric layer as a contact mode tip and local top gate. Electrical transport through graphene at various back gate voltages is monitored as a function of tip voltage and tip position. Near the Dirac point, the response of graphene resistance to the tip voltage shows significant variation with tip position, and SGM imaging displays mesoscopic domains of electron-doped and hole-doped regions. Our measurements reveal substantial spatial fluctuation in the carrier density in graphene due to extrinsic local doping from sources such as metal contacts, graphene edges, structural defects and resist residues. Our scanning gate measurements also demonstrate graphene's excellent capability to sense the local electric field and charges.

  6. GaN MOSHEMT employing HfO2 as a gate dielectric with partially etched barrier

    Science.gov (United States)

    Han, Kefeng; Zhu, Lin

    2017-09-01

    In order to suppress the gate leakage current of a GaN high electron mobility transistor (GaN HEMT), a GaN metal-oxide-semiconductor high electron mobility transistor (MOSHEMT) is proposed, in which a metal-oxide-semiconductor gate with high-dielectric-constant HfO2 as an insulating dielectric is employed to replace the traditional GaN HEMT Schottky gate. A 0.5 μm gate length GaN MOSHEMT was fabricated based on the proposed structure, the {{{Al}}}0.28{{{Ga}}}0.72{{N}} barrier layer is partially etched to produce a higher transconductance without deteriorating the transport characteristics of the two-dimensional electron gas in the channel, the gate dielectric is HfO2 deposited by atomic layer deposition. Current-voltage characteristics and radio frequency characteristics are obtained after device preparation, the maximum current density of the device is 900 mA mm-1, the source-drain breakdown voltage is 75 V, gate current is significantly suppressed and the forward gate voltage swing range is about ten times higher than traditional GaN HEMTs, the GaN MOSHEMT also demonstrates radio frequency characteristics comparable to traditional GaN HEMTs with the same gate length.

  7. Characterization, integration and reliability of HfO{sub 2} and LaLuO{sub 3} high-κ/metal gate stacks for CMOS applications

    Energy Technology Data Exchange (ETDEWEB)

    Nichau, Alexander

    2013-07-15

    The continued downscaling of MOSFET dimensions requires an equivalent oxide thickness (EOT) of the gate stack below 1 nm. An EOT below 1.4 nm is hereby enabled by the use of high-κ/metal gate stacks. LaLuO{sub 3} and HfO{sub 2} are investigated as two different high-κ oxides on silicon in conjunction with TiN as the metal electrode. LaLuO{sub 3} and its temperature-dependent silicate formation are characterized by hard X-ray photoemission spectroscopy (HAXPES). The effective attenuation length of LaLuO{sub 3} is determined between 7 and 13 keV to enable future interface and diffusion studies. In a first investigation of LaLuO{sub 3} on germanium, germanate formation is shown. LaLuO{sub 3} is further integrated in a high-temperature MOSFET process flow with varying thermal treatment. The devices feature drive currents up to 70μA/μm at 1μm gate length. Several optimization steps are presented. The effective device mobility is related to silicate formation and thermal budget. At high temperature the silicate formation leads to mobility degradation due to La-rich silicate formation. The integration of LaLuO{sub 3} in high-T processes delicately connects with the optimization of the TiN metal electrode. Hereby, stoichiometric TiN yields the best results in terms of thermal stability with respect to Si-capping and high-κ oxide. Different approaches are presented for a further EOT reduction with LaLuO{sub 3} and HfO{sub 2}. Thereby the thermodynamic and kinetic predictions are employed to estimate the behavior on the nanoscale. Based on thermodynamics, excess oxygen in the gate stack, especially in oxidized metal electrodes, is identified to prevent EOT scaling below 1.2 nm. The equivalent oxide thickness of HfO{sub 2} gate stacks is scalable below 1 nm by the use of thinned interfacial SiO{sub 2}. The prevention of oxygen incorporation into the metal electrode by Si-capping maintains the EOT after high temperature annealing. Redox systems are employed within the

  8. CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

    Science.gov (United States)

    Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

    2018-04-01

    Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

  9. A novel approach for the improvement of electrostatic behaviour of physically doped TFET using plasma formation and shortening of gate electrode with hetero-gate dielectric

    Science.gov (United States)

    Soni, Deepak; Sharma, Dheeraj; Aslam, Mohd.; Yadav, Shivendra

    2018-04-01

    This article presents a new device configuration to enhance current drivability and suppress negative conduction (ambipolar conduction) with improved RF characteristics of physically doped TFET. Here, we used a new approach to get excellent electrical characteristics of hetero-dielectric short gate source electrode TFET (HD-SG SE-TFET) by depositing a metal electrode of 5.93 eV work function over the heavily doped source (P+) region. Deposition of metal electrode induces the plasma (thin layer) of holes under the Si/HfO2 interface due to work function difference of metal and semiconductor. Plasma layer of holes is advantageous to increase abruptness as well as decrease the tunneling barrier at source/channel junction for attaining higher tunneling rate of charge carriers (i.e., electrons), which turns into 86.66 times higher ON-state current compared with the conventional physically doped TFET (C-TFET). Along with metal electrode deposition, gate electrode is under-lapped for inducing asymmetrical concentration of charge carriers in the channel region, which is helpful for widening the tunneling barrier width at the drain/channel interface. Consequently, HD-SG SE-TFET shows suppression of ambipolar behavior with reduction in gate-to-drain capacitance which is beneficial for improvement in RF performance. Furthermore, the effectiveness of hetero-gate dielectric concept has been used for improving the RF performance. Furthermore, reliability of C-TFET and proposed structures has been confirmed in term of linearity.

  10. Gated field-emitter cathodes for high-power microwave applications

    International Nuclear Information System (INIS)

    Barasch, E.F.; Demroff, H.P.; Elliott, T.S.; Kasprowicz, T.B.; Lee, B.; Mazumdar, T.; McIntyre, P.M.; Pang, Y.; Smith, D.D.; Trost, H.J.

    1992-01-01

    Gated field-emitter cathodes have been fabricated on silicon wafers. Two fabrication approaches have been employed: a knife-edge array and a porous silicon structure. The knife-edge array consists of a pattern of knife-edges, sharpened to ∼200 A radius, configured with an insulated metal gate structure at a gap of ∼500 A. The porous silicon cathode consists of an insulating porous layer, containing pores of ∼50 A diameter, densely spaced in the native silicon, biased for field emission by a thin gate metallization on the surface. Emission current density of 20 A/cm 2 has been obtained with only 10 V bias. Fabrication processes and test results are presented. (Author) 4 figs., tab., 12 refs

  11. Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate

    International Nuclear Information System (INIS)

    Liu, Hsi-Wen; Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Chang, Ting-Chang; Chen, Ching-En; Tseng, Tseung-Yuen; Lin, Chien-Yu; Cheng, Osbert; Huang, Cheng-Tung; Ye, Yi-Han

    2016-01-01

    This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

  12. Demonstration of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with silicon-oxy-nitride as the gate insulator

    International Nuclear Information System (INIS)

    Balachander, K.; Arulkumaran, S.; Egawa, T.; Sano, Y.; Baskar, K.

    2005-01-01

    AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs) were fabricated with plasma enhanced chemical vapor deposited silicon oxy-nitride (SiON) as an insulating layer. The compositions of SiON thin films were confirmed using X-ray photoelectron spectroscopy. The fabricated MOSHEMTs exhibited a very high saturation current density of 1.1 A/mm coupled with high positive operational gate voltage up to +7 V. The MOSHEMTs also exhibited four orders of low gate leakage current and high forward-on voltage when compared with the conventional HEMTs. The drain current collapse using gate pulse measurements showed only a negligible difference in the saturation current density revealing the drastic improvement in passivation of the surface states due to the high quality of dielectric thin films deposited. Thus, based on the improved direct-current operation, SiON can be considered to be a potential gate oxide comparable with other dielectric insulators

  13. Intelligent layered nanoflare: ``lab-on-a-nanoparticle'' for multiple DNA logic gate operations and efficient intracellular delivery

    Science.gov (United States)

    Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

    2014-07-01

    DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of

  14. Flexible FETs using ultrathin Si microwires embedded in solution processed dielectric and metal layers

    Science.gov (United States)

    Khan, S.; Yogeswaran, N.; Taube, W.; Lorenzelli, L.; Dahiya, R.

    2015-12-01

    This work presents a novel manufacturing route for obtaining high performance bendable field effect transistors (FET) by embedding silicon (Si) microwires (2.5 μm thick) in layers of solution-processed dielectric and metallic layers. The objective of this study is to explore heterogeneous integration of Si with polymers and to exploit the benefits of both microelectronics and printing technologies. Arrays of Si microwires are developed on silicon on insulator (SOI) wafers and transfer printed to polyimide (PI) substrate through a polydimethylsiloxane (PDMS) carrier stamp. Following the transfer printing of Si microwires, two different processing steps were developed to obtain top gate top contact and back gate top contact FETs. Electrical characterizations indicate devices having mobility as high as 117.5 cm2 V-1 s-1. The fabricated devices were also modeled using SILVACO Atlas. Simulation results show a trend in the electrical response similar to that of experimental results. In addition, a cyclic test was performed to demonstrate the reliability and mechanical robustness of the Si μ-wires on flexible substrates.

  15. Flexible FETs using ultrathin Si microwires embedded in solution processed dielectric and metal layers

    International Nuclear Information System (INIS)

    Khan, S; Yogeswaran, N; Lorenzelli, L; Taube, W; Dahiya, R

    2015-01-01

    This work presents a novel manufacturing route for obtaining high performance bendable field effect transistors (FET) by embedding silicon (Si) microwires (2.5 μm thick) in layers of solution-processed dielectric and metallic layers. The objective of this study is to explore heterogeneous integration of Si with polymers and to exploit the benefits of both microelectronics and printing technologies. Arrays of Si microwires are developed on silicon on insulator (SOI) wafers and transfer printed to polyimide (PI) substrate through a polydimethylsiloxane (PDMS) carrier stamp. Following the transfer printing of Si microwires, two different processing steps were developed to obtain top gate top contact and back gate top contact FETs. Electrical characterizations indicate devices having mobility as high as 117.5 cm 2 V −1 s −1 . The fabricated devices were also modeled using SILVACO Atlas. Simulation results show a trend in the electrical response similar to that of experimental results. In addition, a cyclic test was performed to demonstrate the reliability and mechanical robustness of the Si μ-wires on flexible substrates. (paper)

  16. Gate metal dependent electrical characteristics of AlGaN/GaN HEMTs

    International Nuclear Information System (INIS)

    Koo, Sang-Mo; Kang, Min-Seok

    2014-01-01

    Highlights: • We investigated transfer characteristics of AlGaN/GaN high electron mobility transistors. • We demonstrate the effect of the barrier height of Schottky gate metals. • The conduction mechanisms examine by comparing the experimental results with numerical simulations. • 2-DEG concentration depends on the barrier height of Schottky gate metals. - Abstract: We investigated transfer characteristics of AlGaN/GaN high electron mobility transistors (HEMTs) and the effect of the barrier height of Schottky gate metals. It is found that the threshold voltage of the HEMT structures with the Ni Schottky contact shows a positive shift compared to that of the Ti Schottky contacts (ΔV th = 2.9 V). The maximum saturation current of the HEMT structures with the Ti Schottky contact (∼1.4 × 10 7 A/cm 2 ) is found to be ∼2.5 times higher than that of the Ni Schottky contact (2.9 × 10 7 A/cm 2 ). The conduction mechanisms have been examined by comparing the experimental results with numerical simulations, which confirm that the increased barrier height is mainly attributed to the reduction of 2-DEG concentration

  17. Gate metal dependent electrical characteristics of AlGaN/GaN HEMTs

    Energy Technology Data Exchange (ETDEWEB)

    Koo, Sang-Mo, E-mail: smkoo@kw.ac.kr; Kang, Min-Seok, E-mail: hyde0220@gmail.com

    2014-10-15

    Highlights: • We investigated transfer characteristics of AlGaN/GaN high electron mobility transistors. • We demonstrate the effect of the barrier height of Schottky gate metals. • The conduction mechanisms examine by comparing the experimental results with numerical simulations. • 2-DEG concentration depends on the barrier height of Schottky gate metals. - Abstract: We investigated transfer characteristics of AlGaN/GaN high electron mobility transistors (HEMTs) and the effect of the barrier height of Schottky gate metals. It is found that the threshold voltage of the HEMT structures with the Ni Schottky contact shows a positive shift compared to that of the Ti Schottky contacts (ΔV{sub th} = 2.9 V). The maximum saturation current of the HEMT structures with the Ti Schottky contact (∼1.4 × 10{sup 7} A/cm{sup 2}) is found to be ∼2.5 times higher than that of the Ni Schottky contact (2.9 × 10{sup 7} A/cm{sup 2}). The conduction mechanisms have been examined by comparing the experimental results with numerical simulations, which confirm that the increased barrier height is mainly attributed to the reduction of 2-DEG concentration.

  18. High carrier mobility of CoPc wires based field-effect transistors using bi-layer gate dielectric

    Directory of Open Access Journals (Sweden)

    Murali Gedda

    2013-11-01

    Full Text Available Polyvinyl alcohol (PVA and anodized Al2O3 layers were used as bi-layer gate for the fabrication of cobalt phthalocyanine (CoPc wire base field-effect transistors (OFETs. CoPc wires were grown on SiO2 surfaces by organic vapor phase deposition method. These devices exhibit a field-effect carrier mobility (μEF value of 1.11 cm2/Vs. The high carrier mobility for CoPc molecules is attributed to the better capacitive coupling between the channel of CoPc wires and the gate through organic-inorganic dielectric layer. Our measurements also demonstrated the way to determine the thicknesses of the dielectric layers for a better process condition of OFETs.

  19. Comprehensive study and design of scaled metal/high-k/Ge gate stacks with ultrathin aluminum oxide interlayers

    Energy Technology Data Exchange (ETDEWEB)

    Asahara, Ryohei; Hideshima, Iori; Oka, Hiroshi; Minoura, Yuya; Hosoi, Takuji, E-mail: hosoi@mls.eng.osaka-u.ac.jp; Shimura, Takayoshi; Watanabe, Heiji [Graduate School of Engineering, Osaka University, 2-1 Yamadaoka, Suita, Osaka 565-0871 (Japan); Ogawa, Shingo [Graduate School of Engineering, Osaka University, 2-1 Yamadaoka, Suita, Osaka 565-0871 (Japan); Toray Research Center Inc., 3-3-7 Sonoyama, Otsu, Shiga 520-8567 (Japan); Yoshigoe, Akitaka; Teraoka, Yuden [Japan Atomic Energy Agency, 1-1-1 Kouto, Sayo-cho, Sayo-gun, Hyogo 679-5148 (Japan)

    2015-06-08

    Advanced metal/high-k/Ge gate stacks with a sub-nm equivalent oxide thickness (EOT) and improved interface properties were demonstrated by controlling interface reactions using ultrathin aluminum oxide (AlO{sub x}) interlayers. A step-by-step in situ procedure by deposition of AlO{sub x} and hafnium oxide (HfO{sub x}) layers on Ge and subsequent plasma oxidation was conducted to fabricate Pt/HfO{sub 2}/AlO{sub x}/GeO{sub x}/Ge stacked structures. Comprehensive study by means of physical and electrical characterizations revealed distinct impacts of AlO{sub x} interlayers, plasma oxidation, and metal electrodes serving as capping layers on EOT scaling, improved interface quality, and thermal stability of the stacks. Aggressive EOT scaling down to 0.56 nm and very low interface state density of 2.4 × 10{sup 11 }cm{sup −2}eV{sup −1} with a sub-nm EOT and sufficient thermal stability were achieved by systematic process optimization.

  20. Integration issues of high-k and metal gate into conventional CMOS technology

    International Nuclear Information System (INIS)

    Song, S.C.; Zhang, Z.; Huffman, C.; Bae, S.H.; Sim, J.H.; Kirsch, P.; Majhi, P.; Moumen, N.; Lee, B.H.

    2006-01-01

    Issues surrounding the integration of Hf-based high-k dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate stack process as well as optimization of other CMOS process steps enables robust CMOSFETs with a wide process latitude. HfO 2 of a 2 nm physical thickness shows complete suppression of transient charge trapping resulting from a significant reduction in film volume as well as kinetically suppressed crystallization. Metal thickness is also critical when optimizing physical stress effects and minimizing dopant diffusion. A high temperature anneal after source and drain implantation in a conventional CMOSFET process reduces the interface state density and improves electron mobility

  1. Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

    Energy Technology Data Exchange (ETDEWEB)

    Chun, Minkyu; Um, Jae Gwang; Park, Min Sang; Chowdhury, Md Delwar Hossain; Jang, Jin, E-mail: jjang@khu.ac.kr [Advanced Display Research Center and Department of Information Display, Kyung Hee University, Seoul 02447 (Korea, Republic of)

    2016-07-15

    We report the abnormal behavior of the threshold voltage (V{sub TH}) shift under positive bias Temperature stress (PBTS) and negative bias temperature stress (NBTS) at top/bottom gate in dual gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). It is found that the PBTS at top gate shows negative transfer shift and NBTS shows positive transfer shift for both top and bottom gate sweep. The shift of bottom/top gate sweep is dominated by top gate bias (V{sub TG}), while bottom gate bias (V{sub BG}) is less effect than V{sub TG}. The X-ray photoelectron spectroscopy (XPS) depth profile provides the evidence of In metal diffusion to the top SiO{sub 2}/a-IGZO and also the existence of large amount of In{sup +} under positive top gate bias around top interfaces, thus negative transfer shift is observed. On the other hand, the formation of OH{sup −} at top interfaces under the stress of negative top gate bias shows negative transfer shift. The domination of V{sub TG} both on bottom/top gate sweep after PBTS/NBTS is obviously occurred due to thin active layer.

  2. Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

    Science.gov (United States)

    Wang, Wei; Han, Jinhua; Ying, Jun; Xiang, Lanyi; Xie, Wenfa

    2014-09-01

    Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm2/V s. The unidirectional shift of turn-on voltage (Von) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (VP/VE) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered molecule orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm2/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the VP/VE of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional Von shift. As a result, an enlarged memory window of 28.6 V at the VP/VE of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.

  3. Combining a multi deposition multi annealing technique with a scavenging (Ti) to improve the high-k/metal gate stack performance for a gate-last process

    International Nuclear Information System (INIS)

    Zhang ShuXiang; Yang Hong; Tang Bo; Tang Zhaoyun; Xu Yefeng; Xu Jing; Yan Jiang

    2014-01-01

    ALD HfO 2 films fabricated by a novel multi deposition multi annealing (MDMA) technique are investigated, we have included samples both with and without a Ti scavenging layer. As compared to the reference gate stack treated by conventional one-time deposition and annealing (D and A), devices receiving MDMA show a significant reduction in leakage current. Meanwhile, EOT growth is effectively controlled by the Ti scavenging layer. This improvement strongly correlates with the cycle number of D and A (while keeping the total annealing time and total dielectrics thickness the same). Transmission electron microscope and energy-dispersive X-ray spectroscopy analysis suggests that oxygen incorporation into both the high-k film and the interfacial layer is likely to be responsible for the improvement of the device. This novel MDMA is promising for the development of gate stack technology in a gate last integration scheme. (semiconductor technology)

  4. Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

    KAUST Repository

    Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Young, Chadwin D.; Bersuker, Gennadi; Hussain, Muhammad Mustafa

    2015-01-01

    We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard

  5. Low-leakage-current AlGaN/GaN HEMTs on Si substrates with partially Mg-doped GaN buffer layer by metal organic chemical vapor deposition

    International Nuclear Information System (INIS)

    Li Ming; Wang Yong; Wong Kai-Ming; Lau Kei-May

    2014-01-01

    High-performance low-leakage-current AlGaN/GaN high electron mobility transistors (HEMTs) on silicon (111) substrates grown by metal organic chemical vapor deposition (MOCVD) with a novel partially Magnesium (Mg)-doped GaN buffer scheme have been fabricated successfully. The growth and DC results were compared between Mg-doped GaN buffer layer and a unintentionally one. A 1-μm gate-length transistor with Mg-doped buffer layer exhibited an OFF-state drain leakage current of 8.3 × 10 −8 A/mm, to our best knowledge, which is the lowest value reported for MOCVD-grown AlGaN/GaN HEMTs on Si featuring the same dimension and structure. The RF characteristics of 0.25-μm gate length T-shaped gate HEMTs were also investigated

  6. TiN/Al2O3/ZnO gate stack engineering for top-gate thin film transistors by combination of post oxidation and annealing

    Science.gov (United States)

    Kato, Kimihiko; Matsui, Hiroaki; Tabata, Hitoshi; Takenaka, Mitsuru; Takagi, Shinichi

    2018-04-01

    Control of fabrication processes for a gate stack structure with a ZnO thin channel layer and an Al2O3 gate insulator has been examined for enhancing the performance of a top-gate ZnO thin film transistor (TFT). The Al2O3/ZnO interface and the ZnO layer are defective just after the Al2O3 layer formation by atomic layer deposition. Post treatments such as plasma oxidation, annealing after the Al2O3 deposition, and gate metal formation (PMA) are promising to improve the interfacial and channel layer qualities drastically. Post-plasma oxidation effectively reduces the interfacial defect density and eliminates Fermi level pinning at the Al2O3/ZnO interface, which is essential for improving the cut-off of the drain current of TFTs. A thermal effect of post-Al2O3 deposition annealing at 350 °C can improve the crystalline quality of the ZnO layer, enhancing the mobility. On the other hand, impacts of post-Al2O3 deposition annealing and PMA need to be optimized because the annealing can also accompany the increase in the shallow-level defect density and the resulting electron concentration, in addition to the reduction in the deep-level defect density. The development of the interfacial control technique has realized the excellent TFT performance with a large ON/OFF ratio, steep subthreshold characteristics, and high field-effect mobility.

  7. Coulomb Oscillations in a Gate-Controlled Few-Layer Graphene Quantum Dot.

    Science.gov (United States)

    Song, Yipu; Xiong, Haonan; Jiang, Wentao; Zhang, Hongyi; Xue, Xiao; Ma, Cheng; Ma, Yulin; Sun, Luyan; Wang, Haiyan; Duan, Luming

    2016-10-12

    Graphene quantum dots could be an ideal host for spin qubits and thus have been extensively investigated based on graphene nanoribbons and etched nanostructures; however, edge and substrate-induced disorders severely limit device functionality. Here, we report the confinement of quantum dots in few-layer graphene with tunable barriers, defined by local strain and electrostatic gating. Transport measurements unambiguously reveal that confinement barriers are formed by inducing a band gap via the electrostatic gating together with local strain induced constriction. Numerical simulations according to the local top-gate geometry confirm the band gap opening by a perpendicular electric field. We investigate the magnetic field dependence of the energy-level spectra in these graphene quantum dots. Experimental results reveal a complex evolution of Coulomb oscillations with the magnetic field, featuring kinks at level crossings. The simulation of energy spectrum shows that the kink features and the magnetic field dependence are consistent with experimental observations, implying the hybridized nature of energy-level spectrum of these graphene quantum dots.

  8. Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

    International Nuclear Information System (INIS)

    Wang, Wei; Han, Jinhua; Ying, Jun; Xiang, Lanyi; Xie, Wenfa

    2014-01-01

    Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm 2 /V s. The unidirectional shift of turn-on voltage (V on ) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (V P /V E ) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered molecule orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm 2 /V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the V P /V E of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional V on shift. As a result, an enlarged memory window of 28.6 V at the V P /V E of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.

  9. Memory Effect of Metal-Oxide-Silicon Capacitors with Self-Assembly Double-Layer Au Nanocrystals Embedded in Atomic-Layer-Deposited HfO2 Dielectric

    International Nuclear Information System (INIS)

    Yue, Huang; Hong-Yan, Gou; Qing-Qing, Sun; Shi-Jin, Ding; Wei, Zhang; Shi-Li, Zhang

    2009-01-01

    We report the chemical self-assembly growth of Au nanocrystals on atomic-layer-deposited HfO 2 films aminosilanized by (3-Aminopropyl)-trimethoxysilane aforehand for memory applications. The resulting Au nanocrystals show a density of about 4 × 10 11 cm −2 and a diameter range of 5–8nm. The metal-oxide-silicon capacitor with double-layer Au nanocrystals embedded in HfO 2 dielectric exhibits a large C – V hysteresis window of 11.9V for ±11 V gate voltage sweeps at 1 MHz, a flat-band voltage shift of 1.5 V after the electrical stress under 7 V for 1 ms, a leakage current density of 2.9 × 10 −8 A/cm −2 at 9 V and room temperature. Compared to single-layer Au nanocrystals, the double-layer Au nanocrystals increase the hysteresis window significantly, and the underlying mechanism is thus discussed

  10. Direct protein detection with a nano-interdigitated array gate MOSFET.

    Science.gov (United States)

    Tang, Xiaohui; Jonas, Alain M; Nysten, Bernard; Demoustier-Champagne, Sophie; Blondeau, Franoise; Prévot, Pierre-Paul; Pampin, Rémi; Godfroid, Edmond; Iñiguez, Benjamin; Colinge, Jean-Pierre; Raskin, Jean-Pierre; Flandre, Denis; Bayot, Vincent

    2009-08-15

    A new protein sensor is demonstrated by replacing the gate of a metal oxide semiconductor field effect transistor (MOSFET) with a nano-interdigitated array (nIDA). The sensor is able to detect the binding reaction of a typical antibody Ixodes ricinus immunosuppressor (anti-Iris) protein at a concentration lower than 1 ng/ml. The sensor exhibits a high selectivity and reproducible specific detection. We provide a simple model that describes the behavior of the sensor and explains the origin of its high sensitivity. The simulated and experimental results indicate that the drain current of nIDA-gate MOSFET sensor is significantly increased with the successive binding of the thiol layer, Iris and anti-Iris protein layers. It is found that the sensor detection limit can be improved by well optimizing the geometrical parameters of nIDA-gate MOSFET. This nanobiosensor, with real-time and label-free capabilities, can easily be used for the detection of other proteins, DNA, virus and cancer markers. Moreover, an on-chip associated electronics nearby the sensor can be integrated since its fabrication is compatible with complementary metal oxide semiconductor (CMOS) technology.

  11. Channel length scaling and the impact of metal gate work function ...

    Indian Academy of Sciences (India)

    As the channel length is reduced from one transistor generation to the next, ... As CMOS technology continues to scale, metal gate electrodes need to be intro .... in the z-direction, q is the electron charge, h is the Planck's constant, Ψ(x, z) is the.

  12. Chemical vapor deposited monolayer MoS2 top-gate MOSFET with atomic-layer-deposited ZrO2 as gate dielectric

    Science.gov (United States)

    Hu, Yaoqiao; Jiang, Huaxing; Lau, Kei May; Li, Qiang

    2018-04-01

    For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec-1, and a field-effect electron mobility of 12.1 cm2 V-1 s-1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm-1 at V DS = 5 V. The gate leakage current is below 10-2 A cm-2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm-1 is obtained. Gate hysteresis and frequency-dependent capacitance-voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ˜3 × 1012 cm-2 eV-1.

  13. Resin infusion of layered metal/composite hybrid and resulting metal/composite hybrid laminate

    Science.gov (United States)

    Cano, Roberto J. (Inventor); Grimsley, Brian W. (Inventor); Weiser, Erik S. (Inventor); Jensen, Brian J. (Inventor)

    2009-01-01

    A method of fabricating a metal/composite hybrid laminate is provided. One or more layered arrangements are stacked on a solid base to form a layered structure. Each layered arrangement is defined by a fibrous material and a perforated metal sheet. A resin in its liquid state is introduced along a portion of the layered structure while a differential pressure is applied across the laminate structure until the resin permeates the fibrous material of each layered arrangement and fills perforations in each perforated metal sheet. The resin is cured thereby yielding a metal/composite hybrid laminate.

  14. The impact of non-uniform channel layer growth on device characteristics in state of the Art Si/SiGe/Si p-metal oxide semiconductor field effect transistors

    International Nuclear Information System (INIS)

    Chang, A.C.K.; Ross, I.M.; Norris, D.J.; Cullis, A.G.; Tang, Y.T.; Cerrina, C.; Evans, A.G.R.

    2006-01-01

    In this study we have highlighted the effect of non-uniform channel layer growth by the direct correlation of the microstructure and electrical characteristics in state-of-the-art pseudomorphic Si/SiGe p-channel metal oxide semiconductor field effect transistor devices fabricated on Si. Two nominally identical sets of devices from adjacent locations of the same wafer were found to have radically different distributions in gate threshold voltages. Due to the close proximity and narrow gate length of the devices, focused ion beam milling was used to prepare a number of thin cross-sections from each of the two regions for subsequent analysis using transmission electron microscopy. It was found that devices from the region giving a very narrow range of gate threshold voltages exhibited a uniform microstructure in general agreement with the intended growth parameters. However, in the second region, which showed a large spread in the gate threshold voltages, profound anomalies in the microstructure were observed. These anomalies consisted of fluctuations in the quality and thickness of the SiGe strained layers. The non-uniform growth of the strained SiGe layer clearly accounted for the poorly controlled threshold voltages of these devices. The results emphasize the importance of good layer growth uniformity to ensure optimum device yield

  15. Single-electron-occupation metal-oxide-semiconductor quantum dots formed from efficient poly-silicon gate layout

    Energy Technology Data Exchange (ETDEWEB)

    Carroll, Malcolm S.; rochette, sophie; Rudolph, Martin; Roy, A. -M.; Curry, Matthew Jon; Ten Eyck, Gregory A.; Manginell, Ronald P.; Wendt, Joel R.; Pluym, Tammy; Carr, Stephen M; Ward, Daniel Robert; Lilly, Michael; pioro-ladriere, michel

    2017-07-01

    We introduce a silicon metal-oxide-semiconductor quantum dot structure that achieves dot-reservoir tunnel coupling control without a dedicated barrier gate. The elementary structure consists of two accumulation gates separated spatially by a gap, one gate accumulating a reservoir and the other a quantum dot. Control of the tunnel rate between the dot and the reservoir across the gap is demonstrated in the single electron regime by varying the reservoir accumulation gate voltage while compensating with the dot accumulation gate voltage. The method is then applied to a quantum dot connected in series to source and drain reservoirs, enabling transport down to the single electron regime. Finally, tuning of the valley splitting with the dot accumulation gate voltage is observed. This split accumulation gate structure creates silicon quantum dots of similar characteristics to other realizations but with less electrodes, in a single gate stack subtractive fabrication process that is fully compatible with silicon foundry manufacturing.

  16. Flexible semi-transparent silicon (100) fabric with high-k/metal gate devices

    KAUST Repository

    Rojas, Jhonathan Prieto

    2013-01-07

    Can we build a flexible and transparent truly high performance computer? High-k/metal gate stack based metal-oxide-semiconductor capacitor devices are monolithically fabricated on industry\\'s most widely used low-cost bulk single-crystalline silicon (100) wafers and then released as continuous, mechanically flexible, optically semi-transparent and high thermal budget compatible silicon fabric with devices. This is the first ever demonstration with this set of materials which allows full degree of freedom to fabricate nanoelectronics devices using state-of-the-art CMOS compatible processes and then to utilize them in an unprecedented way for wide deployment over nearly any kind of shape and architecture surfaces. Electrical characterization shows uncompromising performance of post release devices. Mechanical characterization shows extra-ordinary flexibility (minimum bending radius of 1 cm) making this generic process attractive to extend the horizon of flexible electronics for truly high performance computers. Schematic and photograph of flexible high-k/metal gate MOSCAPs showing high flexibility and C-V plot showing uncompromised performance. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  17. Temperature-Dependent Physical and Memory Characteristics of Atomic-Layer-Deposited RuOx Metal Nanocrystal Capacitors

    Directory of Open Access Journals (Sweden)

    S. Maikap

    2011-01-01

    Full Text Available Physical and memory characteristics of the atomic-layer-deposited RuOx metal nanocrystal capacitors in an n-Si/SiO2/HfO2/RuOx/Al2O3/Pt structure with different postdeposition annealing temperatures from 850–1000°C have been investigated. The RuOx metal nanocrystals with an average diameter of 7 nm and a highdensity of 0.7 × 1012/cm2 are observed by high-resolution transmission electron microscopy after a postdeposition annealing temperature at 1000°C. The density of RuOx nanocrystal is decreased (slightly by increasing the annealing temperatures, due to agglomeration of multiple nanocrystals. The RuO3 nanocrystals and Hf-silicate layer at the SiO2/HfO2 interface are confirmed by X-ray photoelectron spectroscopy. For post-deposition annealing temperature of 1000°C, the memory capacitors with a small equivalent oxide thickness of ~9 nm possess a large hysteresis memory window of >5 V at a small sweeping gate voltage of ±5 V. A promising memory window under a small sweeping gate voltage of ~3 V is also observed due to charge trapping in the RuOx metal nanocrystals. The program/erase mechanism is modified Fowler-Nordheim (F-N tunneling of the electrons and holes from Si substrate. The electrons and holes are trapped in the RuOx nanocrystals. Excellent program/erase endurance of 106 cycles and a large memory window of 4.3 V with a small charge loss of ~23% at 85°C are observed after 10 years of data retention time, due to the deep-level traps in the RuOx nanocrystals. The memory structure is very promising for future nanoscale nonvolatile memory applications.

  18. Dry etching of MgCaO gate dielectric and passivation layers on GaN

    International Nuclear Information System (INIS)

    Hlad, M.; Voss, L.; Gila, B.P.; Abernathy, C.R.; Pearton, S.J.; Ren, F.

    2006-01-01

    MgCaO films grown by rf plasma-assisted molecular beam epitaxy and capped with Sc 2 O 3 are promising candidates as surface passivation layers and gate dielectrics on GaN-based high electron mobility transistors (HEMTs) and metal-oxide semiconductor HEMTs (MOS-HEMTs), respectively. Two different plasma chemistries were examined for etching these thin films on GaN. Inductively coupled plasmas of CH 4 /H 2 /Ar produced etch rates only in the range 20-70 A/min, comparable to the Ar sputter rates under the same conditions. Similarly slow MgCaO etch rates (∼100 A/min) were obtained with Cl 2 /Ar discharges under the same conditions, but GaN showed rates almost an order of magnitude higher. The MgCaO removal rates are limited by the low volatilities of the respective etch products. The CH 4 /H 2 /Ar plasma chemistry produced a selectivity of around 2 for etching the MgCaO with respect to GaN

  19. P-6 : Impact of buffer layers on the self-aligned top-gate a-IGZO TFT characteristics

    NARCIS (Netherlands)

    Nag, M.; en de rest

    2015-01-01

    In this work we present the impact of buffer layers deposited by various techniques such as plasma enhanced chemical deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD) techniques on self-aligned (SA) top gate amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) TFT

  20. Impact of metal-ion contaminated silica particles on gate oxide integrity

    NARCIS (Netherlands)

    Rink, Ingrid; Wali, F.; Knotter, D.M.

    2009-01-01

    The impact of metal-ion contamination (present on wafer surface before oxidation) on gate oxide integrity (GOI) is well known in literature, which is not the case for clean silica particles [1, 2]. However, it is known that particles present in ultra-pure water (UPW) decrease the random yield in

  1. Metal-oxide-semiconductor devices based on epitaxial germanium-carbon layers grown directly on silicon substrates by ultra-high-vacuum chemical vapor deposition

    Science.gov (United States)

    Kelly, David Quest

    After the integrated circuit was invented in 1959, complementary metal-oxide-semiconductor (CMOS) technology soon became the mainstay of the semiconductor industry. Silicon-based CMOS has dominated logic technologies for decades. During this time, chip performance has grown at an exponential rate at the cost of higher power consumption and increased process complexity. The performance gains have been made possible through scaling down circuit dimensions by improvements in lithography capabilities. Since scaling cannot continue forever, researchers have vigorously pursued new ways of improving the performance of metal-oxide-semiconductor field-effect transistors (MOSFETs) without having to shrink gate lengths and reduce the gate insulator thickness. Strained silicon, with its ability to boost transistor current by improving the channel mobility, is one of the methods that has already found its way into production. Although not yet in production, high-kappa dielectrics have also drawn wide interest in industry since they allow for the reduction of the electrical oxide thickness of the gate stack without having to reduce the physical thickness of the dielectric. Further out on the horizon is the incorporation of high-mobility materials such as germanium (Ge), silicon-germanium (Si1-xGe x), and the III-V semiconductors. Among the high-mobility materials, Ge has drawn the most attention because it has been shown to be compatible with high-kappa dielectrics and to produce high drive currents compared to Si. Among the most difficult challenges for integrating Ge on Si is finding a suitable method for reducing the number of crystal defects. The use of strain-relaxed Si1- xGex buffers has proven successful for reducing the threading dislocation density in Ge epitaxial layers, but questions remain as to the viability of this method in terms of cost and process complexity. This dissertation presents research on thin germanium-carbon (Ge 1-yCy layers on Si for the fabrication

  2. Metallorganic chemical vapor deposition and atomic layer deposition approaches for the growth of hafnium-based thin films from dialkylamide precursors for advanced CMOS gate stack applications

    Science.gov (United States)

    Consiglio, Steven P.

    To continue the rapid progress of the semiconductor industry as described by Moore's Law, the feasibility of new material systems for front end of the line (FEOL) process technologies needs to be investigated, since the currently employed polysilicon/SiO2-based transistor system is reaching its fundamental scaling limits. Revolutionary breakthroughs in complementary-metal-oxide-semiconductor (CMOS) technology were recently announced by Intel Corporation and International Business Machines Corporation (IBM), with both organizations revealing significant progress in the implementation of hafnium-based high-k dielectrics along with metal gates. This announcement was heralded by Gordon Moore as "...the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s." Accordingly, the study described herein focuses on the growth of Hf-based dielectrics and Hf-based metal gates using chemical vapor-based deposition methods, specifically metallorganic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). A family of Hf source complexes that has received much attention recently due to their desirable properties for implementation in wafer scale manufacturing is the Hf dialkylamide precursors. These precursors are room temperature liquids and possess sufficient volatility and desirable decomposition characteristics for both MOCVD and ALD processing. Another benefit of using these sources is the existence of chemically compatible Si dialkylamide sources as co-precursors for use in Hf silicate growth. The first part of this study investigates properties of MOCVD-deposited HfO2 and HfSixOy using dimethylamido Hf and Si precursor sources using a customized MOCVD reactor. The second part of this study involves a study of wet and dry surface pre-treatments for ALD growth of HfO2 using tetrakis(ethylmethylamido)hafnium in a wafer scale manufacturing environment. The third part of this study is an investigation of

  3. Electrical and materials properties of ZrO2 gate dielectrics grown by atomic layer chemical vapor deposition

    Science.gov (United States)

    Perkins, Charles M.; Triplett, Baylor B.; McIntyre, Paul C.; Saraswat, Krishna C.; Haukka, Suvi; Tuominen, Marko

    2001-04-01

    Structural and electrical properties of gate stack structures containing ZrO2 dielectrics were investigated. The ZrO2 films were deposited by atomic layer chemical vapor deposition (ALCVD) after different substrate preparations. The structure, composition, and interfacial characteristics of these gate stacks were examined using cross-sectional transmission electron microscopy and x-ray photoelectron spectroscopy. The ZrO2 films were polycrystalline with either a cubic or tetragonal crystal structure. An amorphous interfacial layer with a moderate dielectric constant formed between the ZrO2 layer and the substrate during ALCVD growth on chemical oxide-terminated silicon. Gate stacks with a measured equivalent oxide thickness (EOT) of 1.3 nm showed leakage values of 10-5 A/cm2 at a bias of -1 V from flatband, which is significantly less than that seen with SiO2 dielectrics of similar EOT. A hysteresis of 8-10 mV was seen for ±2 V sweeps while a midgap interface state density (Dit) of ˜3×1011 states/cm eV was determined from comparisons of measured and ideal capacitance curves.

  4. Channel length scaling and the impact of metal gate work function ...

    Indian Academy of Sciences (India)

    Further- more, quantum effects on the performance of DG-MOSFETs are addressed and discussed. We also study the influence of metal gate work function on the performance of nanoscale MOSFETs. We use a self-consistent Poisson–Schrödinger solver in two dimensions over the entire device. A good agreement with ...

  5. Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

    Directory of Open Access Journals (Sweden)

    Gaspar Casados-Cruz

    2010-11-01

    Full Text Available Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane.

  6. Interface Engineering and Gate Dielectric Engineering for High Performance Ge MOSFETs

    Directory of Open Access Journals (Sweden)

    Jiabao Sun

    2015-01-01

    Full Text Available In recent years, germanium has attracted intensive interests for its promising applications in the microelectronics industry. However, to achieve high performance Ge channel devices, several critical issues still have to be addressed. Amongst them, a high quality gate stack, that is, a low defect interface layer and a dielectric layer, is of crucial importance. In this work, we first review the existing methods of interface engineering and gate dielectric engineering and then in more detail we discuss and compare three promising approaches (i.e., plasma postoxidation, high pressure oxidation, and ozone postoxidation. It has been confirmed that these approaches all can significantly improve the overall performance of the metal-oxide-semiconductor field effect transistor (MOSFET device.

  7. Low temperature (100 °C) atomic layer deposited-ZrO2 for recessed gate GaN HEMTs on Si

    Science.gov (United States)

    Byun, Young-Chul; Lee, Jae-Gil; Meng, Xin; Lee, Joy S.; Lucero, Antonio T.; Kim, Si Joon; Young, Chadwin D.; Kim, Moon J.; Kim, Jiyoung

    2017-08-01

    In this paper, the effect of atomic layer deposited ZrO2 gate dielectrics, deposited at low temperature (100 °C), on the characteristics of recessed-gate High Electron Mobility Transistors (HEMTs) on Al0.25Ga0.75N/GaN/Si is investigated and compared with the characteristics of those with ZrO2 films deposited at typical atomic layer deposited (ALD) process temperatures (250 °C). Negligible hysteresis (ΔVth 4 V), and low interfacial state density (Dit = 3.69 × 1011 eV-1 cm-2) were observed on recessed gate HEMTs with ˜5 nm ALD-ZrO2 films grown at 100 °C. The excellent properties of recessed gate HEMTs are due to the absence of an interfacial layer and an amorphous phase of the film. An interfacial layer between 250 °C-ZrO2 and GaN is observed via high-resolution transmission electron microscopy and X-ray photoelectron spectroscopy. However, 100 °C-ZrO2 and GaN shows no significant interfacial layer formation. Moreover, while 100 °C-ZrO2 films maintain an amorphous phase on either substrate (GaN and Si), 250 °C-ZrO2 films exhibit a polycrystalline-phase when deposited on GaN and an amorphous phase when deposited on Si. Contrary to popular belief, the low-temperature ALD process for ZrO2 results in excellent HEMT performance.

  8. Magnetic phase transition induced by electrostatic gating in two-dimensional square metal-organic frameworks

    Science.gov (United States)

    Wang, Yun-Peng; Li, Xiang-Guo; Liu, Shuang-Long; Fry, James N.; Cheng, Hai-Ping

    2018-03-01

    We investigate theoretically magnetism and magnetic phase transitions induced by electrostatic gating of two-dimensional square metal-organic framework compounds. We find that electrostatic gating can induce phase transitions between homogeneous ferromagnetic and various spin-textured antiferromagnetic states. Electronic structure and Wannier function analysis can reveal hybridizations between transition-metal d orbitals and conjugated π orbitals in the organic framework. Mn-containing compounds exhibit a strong d -π hybridization that leads to partially occupied spin-minority bands, in contrast to compounds containing transition-metal ions other than Mn, for which electronic structure around the Fermi energy is only slightly spin split due to weak d -π hybridization and the magnetic interaction is of the Ruderman-Kittel-Kasuya-Yosida type. We use a ferromagnetic Kondo lattice model to understand the phase transition in Mn-containing compounds in terms of carrier density and illuminate the complexity and the potential to control two-dimensional magnetization.

  9. Molecular-beam-deposited yttrium-oxide dielectrics in aluminum-gated metal - oxide - semiconductor field-effect transistors: Effective electron mobility

    International Nuclear Information System (INIS)

    Ragnarsson, L.-A degree.; Guha, S.; Copel, M.; Cartier, E.; Bojarczuk, N. A.; Karasinski, J.

    2001-01-01

    We report on high effective mobilities in yttrium-oxide-based n-channel metal - oxide - semiconductor field-effect transistors (MOSFETs) with aluminum gates. The yttrium oxide was grown in ultrahigh vacuum using a reactive atomic-beam-deposition system. Medium-energy ion-scattering studies indicate an oxide with an approximate composition of Y 2 O 3 on top of a thin layer of interfacial SiO 2 . The thickness of this interfacial oxide as well as the effective mobility are found to be dependent on the postgrowth anneal conditions. Optimum conditions result in mobilities approaching that of SiO 2 -based MOSFETs at higher fields with peak mobilities at approximately 210 cm 2 /Vs. [copyright] 2001 American Institute of Physics

  10. Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

    Science.gov (United States)

    Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

    2009-08-01

    This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

  11. Controlling the interface charge density in GaN-based metal-oxide-semiconductor heterostructures by plasma oxidation of metal layers

    International Nuclear Information System (INIS)

    Hahn, Herwig; Kalisch, Holger; Vescan, Andrei; Pécz, Béla; Kovács, András; Heuken, Michael

    2015-01-01

    In recent years, investigating and engineering the oxide-semiconductor interface in GaN-based devices has come into focus. This has been driven by a large effort to increase the gate robustness and to obtain enhancement mode transistors. Since it has been shown that deep interface states act as fixed interface charge in the typical transistor operating regime, it appears desirable to intentionally incorporate negative interface charge, and thus, to allow for a positive shift in threshold voltage of transistors to realise enhancement mode behaviour. A rather new approach to obtain such negative charge is the plasma-oxidation of thin metal layers. In this study, we present transmission electron microscopy and energy dispersive X-ray spectroscopy analysis as well as electrical data for Al-, Ti-, and Zr-based thin oxide films on a GaN-based heterostructure. It is shown that the plasma-oxidised layers have a polycrystalline morphology. An interfacial amorphous oxide layer is only detectable in the case of Zr. In addition, all films exhibit net negative charge with varying densities. The Zr layer is providing a negative interface charge density of more than 1 × 10 13  cm –2 allowing to considerably shift the threshold voltage to more positive values

  12. Effect of oxygen on tuning the TiNx metal gate work function on LaLuO3

    International Nuclear Information System (INIS)

    Mitrovic, I.Z.; Przewlocki, H.M.; Piskorski, K.; Simutis, G.; Dhanak, V.R.; Sedghi, N.; Hall, S.

    2012-01-01

    This paper presents experimental evidence on effective work function tuning due to the presence of oxygen at the TiNx/LaLuO 3 interface. Two complementary techniques, internal photoemission and X-ray photoelectron spectroscopy, show good agreement on the position of the metal gate Fermi level to conduction (2.79 ± 0.25 eV) and valence (2.65 ± 0.08 eV) band edge for TiNx/bulk LaLuO 3 gate stacks. The chemical shifts of Ti2p and N1s core levels and different degree in ionicity of TiNx metal gates correlate with the observed valence band offset shifts. The results have significance for setting the band edge work function and resulting low threshold voltage for ultimately scaled LaLuO 3 -based p-metal oxide semiconductor field effect transistor devices. - Highlights: ► The conduction band offset measured by internal photoemission. ► The valence band offset (VBO) measured by X-ray photoelectron spectroscopy. ► Different degree in ionicity of TiNx correlates with the VBO shifts. ► The effective work function of the gate stacks varies from 4.6 to 5.2 eV. ► Oxygen at the TiNx/LaLuO 3 interface increases effective work function.

  13. Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

    Directory of Open Access Journals (Sweden)

    Minkyu Chun

    2015-05-01

    Full Text Available We investigated the effects of top gate voltage (VTG and temperature (in the range of 25 to 70 oC on dual-gate (DG back-channel-etched (BCE amorphous-indium-gallium-zinc-oxide (a-IGZO thin film transistors (TFTs characteristics. The increment of VTG from -20V to +20V, decreases the threshold voltage (VTH from 19.6V to 3.8V and increases the electron density to 8.8 x 1018cm−3. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on VTG. At VTG of 20V, the mobility decreases from 19.1 to 15.4 cm2/V ⋅ s with increasing temperature, showing a metallic conduction. On the other hand, at VTG of - 20V, the mobility increases from 6.4 to 7.5cm2/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.

  14. Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks

    International Nuclear Information System (INIS)

    Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Liu, Xi-Wen; Chang, Ting-Chang; Chen, Ching-En; Ho, Szu-Han; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Lu, Ching-Sen

    2014-01-01

    This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO 2 interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks.

  15. Optimization of multi-layered metallic shield

    International Nuclear Information System (INIS)

    Ben-Dor, G.; Dubinsky, A.; Elperin, T.

    2011-01-01

    Research highlights: → We investigated the problem of optimization of a multi-layered metallic shield. → The maximum ballistic limit velocity is a criterion of optimization. → The sequence of materials and the thicknesses of layers in the shield are varied. → The general problem is reduced to the problem of Geometric Programming. → Analytical solutions are obtained for two- and three-layered shields. - Abstract: We investigate the problem of optimization of multi-layered metallic shield whereby the goal is to determine the sequence of materials and the thicknesses of the layers that provide the maximum ballistic limit velocity of the shield. Optimization is performed under the following constraints: fixed areal density of the shield, the upper bound on the total thickness of the shield and the bounds on the thicknesses of the plates manufactured from every material. The problem is reduced to the problem of Geometric Programming which can be solved numerically using known methods. For the most interesting in practice cases of two-layered and three-layered shields the solution is obtained in the explicit analytical form.

  16. Simultaneous control of thermoelectric properties in p- and n-type materials by electric double-layer gating: New design for thermoelectric device

    Science.gov (United States)

    Takayanagi, Ryohei; Fujii, Takenori; Asamitsu, Atsushi

    2015-05-01

    We report a novel design of a thermoelectric device that can control the thermoelectric properties of p- and n-type materials simultaneously by electric double-layer gating. Here, p-type Cu2O and n-type ZnO were used as the positive and negative electrodes of the electric double-layer capacitor structure. When a gate voltage was applied between the two electrodes, holes and electrons accumulated on the surfaces of Cu2O and ZnO, respectively. The thermopower was measured by applying a thermal gradient along the accumulated layer on the electrodes. We demonstrate here that the accumulated layers worked as a p-n pair of the thermoelectric device.

  17. Characterization of 0.18- μm gate length AlGaN/GaN HEMTs on SiC fabricated using two-step gate recessing

    Science.gov (United States)

    Yoon, Hyung Sup; Min, Byoung-Gue; Lee, Jong Min; Kang, Dong Min; Ahn, Ho Kyun; Cho, Kyu-Jun; Do, Jae-Won; Shin, Min Jeong; Jung, Hyun-Wook; Kim, Sung Il; Kim, Hae Cheon; Lim, Jong Won

    2017-09-01

    We fabricated a 0.18- μm gate-length AlGaN/GaN high electron mobility transistor (HEMT) on SiC substrate fabricated by using two-step gate recessing which was composed of inductively coupled plasma (ICP) dry etching with a gas mixture of BCl3/Cl2 and wet chemical etching using the oxygen plasma treatment and HCl-based cleaning. The two-step gate recessing process exhibited an etch depth of 4.5 nm for the AlGaN layer and the clean surface of AlGaN layer at the AlGaN/gate metal contact region for the AlGaN/GaN HEMT structure. The recessed 0.18 μm × 200 μm AlGaN/GaN HEMT devices showed good DC characteristics, having a good Schottky diode ideality factor of 1.25, an extrinsic transconductance ( g m ) of 345 mS/mm, and a threshold voltage ( V th ) of -2.03 V. The recessed HEMT devices exhibited high RF performance, having a cut-off frequency ( f T ) of 48 GHz and a maximum oscillation frequency ( f max ) of 130 GHz. These devices also showed minimum noise figure of 0.83 dB and associated gain of 12.2 dB at 10 GHz.

  18. Modulation of the effective work function of a TiN metal gate for NMOS requisition with Al incorporation

    International Nuclear Information System (INIS)

    Han Kai; Ma Xueli; Yang Hong; Wang Wenwu

    2013-01-01

    The effect of Al incorporation on the effective work function (EWF) of TiN metal gate was systematically investigated. Metal—oxide—semiconductor (MOS) capacitors with W/TiN/Al/TiN gate stacks were used to fulfill this purpose. Different thickness ratios of Al to TiN and different post metal annealing (PMA) conditions were employed. Significant shift of work function towards to Si conduction band was observed, which was suitable for NMOS and the magnitude of shift depends on the processing conditions. (semiconductor technology)

  19. Lithium ion intercalation in thin crystals of hexagonal TaSe2 gated by a polymer electrolyte

    Science.gov (United States)

    Wu, Yueshen; Lian, Hailong; He, Jiaming; Liu, Jinyu; Wang, Shun; Xing, Hui; Mao, Zhiqiang; Liu, Ying

    2018-01-01

    Ionic liquid gating has been used to modify the properties of layered transition metal dichalcogenides (TMDCs), including two-dimensional (2D) crystals of TMDCs used extensively recently in the device work, which has led to observations of properties not seen in the bulk. The main effect comes from the electrostatic gating due to the strong electric field at the interface. In addition, ionic liquid gating also leads to ion intercalation when the ion size of the gate electrolyte is small compared to the interlayer spacing of TMDCs. However, the microscopic processes of ion intercalation have rarely been explored in layered TMDCs. Here, we employed a technique combining photolithography device fabrication and electrical transport measurements on the thin crystals of hexagonal TaSe2 using multiple channel devices gated by a polymer electrolyte LiClO4/Polyethylene oxide (PEO). The gate voltage and time dependent source-drain resistances of these thin crystals were used to obtain information on the intercalation process, the effect of ion intercalation, and the correlation between the ion occupation of allowed interstitial sites and the device characteristics. We found a gate voltage controlled modulation of the charge density waves and a scattering rate of charge carriers. Our work suggests that ion intercalation can be a useful tool for layered materials engineering and 2D crystal device design.

  20. Effect of layered manufacturing techniques, alloy powders, and layer thickness on metal-ceramic bond strength.

    Science.gov (United States)

    Ekren, Orhun; Ozkomur, Ahmet; Ucar, Yurdanur

    2018-03-01

    Direct metal laser sintering (DMLS) and direct metal laser melting (DMLM) have become popular for fabricating the metal frameworks of metal-ceramic restorations. How the type of layered manufacturing device, layer thickness, and alloy powder may affect the bond strength of ceramic to metal substructure is unclear. The purpose of this in vitro study was to evaluate the bond strength of dental porcelain to metal frameworks fabricated using different layered manufacturing techniques (DMLS and DMLM), Co-Cr alloy powders, and layer thicknesses and to evaluate whether a correlation exists between the bond strength and the number of ceramic remnants on the metal surface. A total of 75 bar-shaped metal specimens (n=15) were fabricated using either DMLS or DMLM. The powder alloys used were Keramit NP-S and EOS-Cobalt-Chrome SP-2 with layer thicknesses of 20 μm and 30 μm. After ceramic application, the metal-ceramic bond strength was evaluated with a 3-point-bend test. Three-way ANOVA followed by the Tukey honest significance difference test were used for statistical analysis (α=.05). De-bonding surface microstructure was observed with scanning electron microscopy. Energy dispersive spectroscopy analysis was conducted to evaluate the correlation between ceramic remnants on the metal surface and bond strength values. The mean bond strength value of DMLS was significantly higher than that of DMLM. While no statistically significant difference was found between layer thicknesses, alloy powders closely affected bond strength. Statistical comparisons revealed that the highest bond strength could be achieved with DMLS-Cobalt-Chrome SP2-20μm, and the lowest bond strength was observed in DMLS-Keramit NP-S-20μm (P≤.05). No correlation was found between porcelain remnants on the metal surface and bond strength values. The layered manufacturing device and the alloy powders evaluated in the current study closely affected the bond strength of dental porcelain to a metal framework

  1. N-channel thin-film transistors based on 1,4,5,8-naphthalene tetracarboxylic dianhydride with ultrathin polymer gate buffer layer

    International Nuclear Information System (INIS)

    Tanida, Shinji; Noda, Kei; Kawabata, Hiroshi; Matsushige, Kazumi

    2009-01-01

    N-channel operation of thin-film transistors based on 1,4,5,8-naphthalene tetracarboxylic dianhydride (NTCDA) with a 9-nm-thick poly(methyl methacrylate) (PMMA) gate buffer layer was examined. The uniform coverage of the ultrathin PMMA layer on an SiO 2 gate insulator, verified by X-ray reflectivity measurement, caused the increase of electron field-effect mobility because of the suppression of electron traps existing on the SiO 2 surface. In addition, air stability for n-channel operation of the NTCDA transistor was also improved by the PMMA layer which possibly prevented the adsorption of ambient water molecules onto the SiO 2 surface.

  2. Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

    Energy Technology Data Exchange (ETDEWEB)

    Chun, Minkyu; Chowdhury, Md Delwar Hossain; Jang, Jin, E-mail: jjang@khu.ac.kr [Advanced Display Research Center and Department of Information Display, Kyung Hee University, Seoul 130-701 (Korea, Republic of)

    2015-05-15

    We investigated the effects of top gate voltage (V{sub TG}) and temperature (in the range of 25 to 70 {sup o}C) on dual-gate (DG) back-channel-etched (BCE) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) characteristics. The increment of V{sub TG} from -20V to +20V, decreases the threshold voltage (V{sub TH}) from 19.6V to 3.8V and increases the electron density to 8.8 x 10{sup 18}cm{sup −3}. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on V{sub TG}. At V{sub TG} of 20V, the mobility decreases from 19.1 to 15.4 cm{sup 2}/V ⋅ s with increasing temperature, showing a metallic conduction. On the other hand, at V{sub TG} of - 20V, the mobility increases from 6.4 to 7.5cm{sup 2}/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.

  3. C-V analysis at variable frequency of MOS structures with different gates, containing Hf-Doped Ta2O5

    International Nuclear Information System (INIS)

    Stojanovska-Georgievska, L.; Novkovski, N.; Atanassova, E.

    2012-01-01

    The quality of the interface between the insulating layer and the Si substrate in contemporary submicron MOS technology is a critical issue for device functioning. It is characterized through the electrically active defect centers, known as interface states. Their response to the frequency is discussed here, by analyzing capacitance-voltage and conductance-voltage curves. The C-V method is preferred in many cases, since it offers easy measurement, and it is applied to extract information about interface traps and fixed oxide charge, at different frequencies. This technique, related with frequency dependent G-V measurements, can be very useful in characterizing charge trapped in the dielectric and at the interface with Si. By extracting the value of frequency dependent flat band voltage, we have obtained the fixed oxide charges at flat band condition. A comparison between the results obtained by two different methods is made. The samples that are studied are metal-insulator-semiconductor (MIS) structures that include high-k dielectric as insulating layer (Hf doped Ta 2 O 5 ), with thickness of 8 nm, with different metal used as gate electrode. Here the influence of the top electrode on the generation and behavior of the traps in the oxide layer is discussed. The results show that the value of metal work function of the gate material is an issue that should be considered very carefully, especially in the case of high work function metal gates, when generation of extra positive charge than in the case of other metals is observed. (Author)

  4. Laser modification of macroscopic properties of metal surface layer

    Science.gov (United States)

    Kostrubiec, Franciszek

    1995-03-01

    Surface laser treatment of metals comprises a number of diversified technological operations out of which the following can be considered the most common: oxidation and rendering surfaces amorphous, surface hardening of steel, modification of selected physical properties of metal surface layers. In the paper basic results of laser treatment of a group of metals used as base materials for electric contacts have been presented. The aim of the study was to test the usability of laser treatment from the viewpoint of requirements imposed on materials for electric contacts. The results presented in the paper refer to two different surface treatment technologies: (1) modification of infusible metal surface layer: tungsten and molybdenum through laser fusing of their surface layer and its crystallization, and (2) modification of surface layer properties of other metals through laser doping of their surface layer with foreign elements. In the paper a number of results of experimental investigations obtained by the team under the author's supervision are presented.

  5. Proximity Effect in Gate Fabrication Using Photolithography Technique

    Directory of Open Access Journals (Sweden)

    Joanna Prazmowska

    2017-01-01

    Full Text Available In the paper the technological factors influencing test structure gate length were described. The influence of test structure gate placement (Schottky metallization between ohmic contacts, on mesa and on GaN surface was analyzed and discussed. Moreover, various distances between ohmic contacts paths were tested. Except for experimental investigations, simulations using finite elements method in COMSOL were performed for the same structure. The modelling results revealed crucial impact of a gap beyond the mask on the electric field distribution in photoresist layer. The smallest value of relative error of test finger lengths was observed for finger parts placed between ohmic paths on mesas. It was explained by thicker lift-off double layer between ohmic paths and the smallest Y-gap compared to test fingers placed on mesa and outside of it. Simulation did not bring an explanation of larger values of relative error for smaller distance between ohmic paths.

  6. Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

    Science.gov (United States)

    Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

    2008-11-01

    In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

  7. A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

    International Nuclear Information System (INIS)

    Luo Xiao-Rong; Hu Gang-Yi; Zhang Zheng-Yuan; Luo Yin-Chun; Fan Ye; Wang Xiao-Wei; Fan Yuan-Hang; Cai Jin-Yong; Wang Pei; Zhou Kun

    2013-01-01

    A low specific on-resistance (R on,sp ) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates, which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R on,sp of 4.151 mΩ·cm 2 (V GS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  8. Gate Engineering in SOI LDMOS for Device Reliability

    Directory of Open Access Journals (Sweden)

    Aanand

    2016-01-01

    Full Text Available A linearly graded doping drift region with step gate structure, used for improvement of reduced surface field (RESURF SOI LDMOS transistor performance has been simulated with 0.35µm technology in this paper. The proposed device has one poly gate and double metal gate arranged in a stepped manner, from channel to drift region. The first gate uses n+ poly (near source where as other two gates of aluminium. The first gate with thin gate oxide has good control over the channel charge. The third gate with thick gate oxide at drift region reduce gate to drain capacitance. The arrangement of second and third gates in a stepped manner in drift region spreads the electric field uniformly. Using two dimensional device simulations, the proposed SOI LDMOS is compared with conventional structure and the extended metal structure. We demonstrate that the proposed device exhibits significant enhancement in linearity, breakdown voltage, on-resistance and HCI. Double metal gate reduces the impact ionization area which helps to improve the Hot Carrier Injection effect..

  9. Polysulfide intercalated layered double hydroxides for metal capture applications

    Energy Technology Data Exchange (ETDEWEB)

    Kanatzidis, Mercouri G.; Ma, Shulan

    2017-04-04

    Polysulfide intercalated layered double hydroxides and methods for their use in vapor and liquid-phase metal capture applications are provided. The layered double hydroxides comprise a plurality of positively charged host layers of mixed metal hydroxides separated by interlayer spaces. Polysulfide anions are intercalated in the interlayer spaces.

  10. Investigating degradation behavior of hole-trapping effect under static and dynamic gate-bias stress in a dual gate a-InGaZnO thin film transistor with etch stop layer

    Energy Technology Data Exchange (ETDEWEB)

    Liao, Po-Yung [Department of Physics, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang3708@gmail.com [Department of Physics, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan (China); Hsieh, Tien-Yu [Department of Physics, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Tsai, Ming-Yen; Chen, Bo-Wei; Chu, Ann-Kuo [Department of Photonics, National Sun Yat-Sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Chou, Cheng-Hsu; Chang, Jung-Fang [Product Technology Center, Chimei Innolux Corp., Tainan 741, Taiwan (China)

    2016-03-31

    The degree of degradation between the amorphous-indium–gallium–zinc oxide (a-IGZO) thin film transistor (TFT) using the top-gate only or bottom-gate only is compared. Under negative gate bias illumination stress (NBIS), the threshold voltage (V{sub T}) after bottom-gate NBIS monotonically shifts in the negative direction, whereas top-gate NBIS operation exhibits on-state current increases without V{sub T} shift. Such anomalous degradation behavior of NBIS under top-gate operation is due to hole-trapping in the etch stop layer above the central portion of the channel. These phenomena can be ascribed to the screening of the electric field by redundant source/drain electrodes. In addition, the device degradation of dual gate a-IGZO TFT stressed with different top gate pulse waveforms is investigated. It is observed that the degradation is dependent on the frequency of the top gate pulses. The V{sub T} shift increases with decreasing frequency, indicating the hole mobility of IGZO is low. - Highlights: • Static and dynamic gate bias stresses are imposed on dual gate InGaZnO TFTs. • Top-gate NBIS operation exhibits on-state current increases without VT shift. • The degradation behavior of top-gate NBIS is due to hole-trapping in the ESL. • The degradation is dependent on the frequency of the top gate pulses. • The V{sub T} shift increases with decreasing frequency of the top gate pulses.

  11. Investigating degradation behavior of hole-trapping effect under static and dynamic gate-bias stress in a dual gate a-InGaZnO thin film transistor with etch stop layer

    International Nuclear Information System (INIS)

    Liao, Po-Yung; Chang, Ting-Chang; Hsieh, Tien-Yu; Tsai, Ming-Yen; Chen, Bo-Wei; Chu, Ann-Kuo; Chou, Cheng-Hsu; Chang, Jung-Fang

    2016-01-01

    The degree of degradation between the amorphous-indium–gallium–zinc oxide (a-IGZO) thin film transistor (TFT) using the top-gate only or bottom-gate only is compared. Under negative gate bias illumination stress (NBIS), the threshold voltage (V T ) after bottom-gate NBIS monotonically shifts in the negative direction, whereas top-gate NBIS operation exhibits on-state current increases without V T shift. Such anomalous degradation behavior of NBIS under top-gate operation is due to hole-trapping in the etch stop layer above the central portion of the channel. These phenomena can be ascribed to the screening of the electric field by redundant source/drain electrodes. In addition, the device degradation of dual gate a-IGZO TFT stressed with different top gate pulse waveforms is investigated. It is observed that the degradation is dependent on the frequency of the top gate pulses. The V T shift increases with decreasing frequency, indicating the hole mobility of IGZO is low. - Highlights: • Static and dynamic gate bias stresses are imposed on dual gate InGaZnO TFTs. • Top-gate NBIS operation exhibits on-state current increases without VT shift. • The degradation behavior of top-gate NBIS is due to hole-trapping in the ESL. • The degradation is dependent on the frequency of the top gate pulses. • The V T shift increases with decreasing frequency of the top gate pulses.

  12. Determination of accurate metal silicide layer thickness by RBS

    International Nuclear Information System (INIS)

    Kirchhoff, J.F.; Baumann, S.M.; Evans, C.; Ward, I.; Coveney, P.

    1995-01-01

    Rutherford Backscattering Spectrometry (RBS) is a proven useful analytical tool for determining compositional information of a wide variety of materials. One of the most widely utilized applications of RBS is the study of the composition of metal silicides (MSi x ), also referred to as polycides. A key quantity obtained from an analysis of a metal silicide is the ratio of silicon to metal (Si/M). Although compositional information is very reliable in these applications, determination of metal silicide layer thickness by RBS techniques can differ from true layer thicknesses by more than 40%. The cause of these differences lies in how the densities utilized in the RBS analysis are calculated. The standard RBS analysis software packages calculate layer densities by assuming each element's bulk densities weighted by the fractional atomic presence. This calculation causes large thickness discrepancies in metal silicide thicknesses because most films form into crystal structures with distinct densities. Assuming a constant layer density for a full spectrum of Si/M values for metal silicide samples improves layer thickness determination but ignores the underlying physics of the films. We will present results of RBS determination of the thickness various metal silicide films with a range of Si/M values using a physically accurate model for the calculation of layer densities. The thicknesses are compared to scanning electron microscopy (SEM) cross-section micrographs. We have also developed supporting software that incorporates these calculations into routine analyses. (orig.)

  13. Intermodulation Linearity in High-k/Metal Gate 28 nm RF CMOS Transistors

    Directory of Open Access Journals (Sweden)

    Zhen Li

    2015-09-01

    Full Text Available This paper presents experimental characterization, simulation, and Volterra series based analysis of intermodulation linearity on a high-k/metal gate 28 nm RF CMOS technology. A figure-of-merit is proposed to account for both VGS and VDS nonlinearity, and extracted from frequency dependence of measured IIP3. Implications to biasing current and voltage optimization for linearity are discussed.

  14. Atomic-Layer-Deposited SnO2 as Gate Electrode for Indium-Free Transparent Electronics

    KAUST Repository

    Alshammari, Fwzah Hamud; Hota, Mrinal Kanti; Wang, Zhenwei; Aljawhari, Hala; Alshareef, Husam N.

    2017-01-01

    Atomic-layer-deposited SnO2 is used as a gate electrode to replace indium tin oxide (ITO) in thin-film transistors and circuits for the first time. The SnO2 films deposited at 200 °C show low electrical resistivity of ≈3.1 × 10−3 Ω cm with ≈93

  15. Physical and electrical characteristics of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with rare earth Er2O3 as a gate dielectric

    International Nuclear Information System (INIS)

    Lin, Ray-Ming; Chu, Fu-Chuan; Das, Atanu; Liao, Sheng-Yu; Chou, Shu-Tsun; Chang, Liann-Be

    2013-01-01

    In this study, the rare earth erbium oxide (Er 2 O 3 ) was deposited using an electron beam onto an AlGaN/GaN heterostructure to fabricate metal-oxide-semiconductor high-electron-mobility transistors (MOS–HEMTs) that exhibited device performance superior to that of a conventional HEMT. Under similar bias conditions, the gate leakage currents of these MOS–HEMT devices were four orders of magnitude lower than those of conventional Schottky gate HEMTs. The measured sub-threshold swing (SS) and the effective trap state density (N t ) of the MOS–HEMT were 125 mV/decade and 4.3 × 10 12 cm −2 , respectively. The dielectric constant of the Er 2 O 3 layer in this study was 14, as determined through capacitance–voltage measurements. In addition, the gate–source reverse breakdown voltage increased from –166 V for the conventional HEMT to –196 V for the Er 2 O 3 MOS–HEMT. - Highlights: ► GaN/AlGaN/Er 2 O 3 metal-oxide semiconductor high electron mobility transistor ► Physical and electrical characteristics are presented. ► Electron beam evaporated Er 2 O 3 with excellent surface roughness ► Device exhibits reduced gate leakage current and improved I ON /I OFF ratio

  16. AlGaN/GaN MISHEMTs with AlN gate dielectric grown by thermal ALD technique.

    Science.gov (United States)

    Liu, Xiao-Yong; Zhao, Sheng-Xun; Zhang, Lin-Qing; Huang, Hong-Fan; Shi, Jin-Shan; Zhang, Chun-Min; Lu, Hong-Liang; Wang, Peng-Fei; Zhang, David Wei

    2015-01-01

    Recently, AlN plasma-enhanced atomic layer deposition (ALD) passivation technique had been proposed and investigated for suppressing the dynamic on-resistance degradation behavior of high-electron-mobility transistors (HEMTs). In this paper, a novel gate dielectric and passivation technique for GaN-on-Si AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMTs) is presented. This technique features the AlN thin film grown by thermal ALD at 400°C without plasma enhancement. A 10.6-nm AlN thin film was grown upon the surface of the HEMT serving as the gate dielectric under the gate electrode and as the passivation layer in the access region at the same time. The MISHEMTs with thermal ALD AlN exhibit enhanced on/off ratio, reduced channel sheet resistance, reduction of gate leakage by three orders of magnitude at a bias of 4 V, reduced threshold voltage hysteresis of 60 mV, and suppressed current collapse degradation.

  17. Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

    International Nuclear Information System (INIS)

    Besleaga, C.; Stan, G.E.; Pintilie, I.; Barquinha, P.; Fortunato, E.; Martins, R.

    2016-01-01

    Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

  18. Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

    Energy Technology Data Exchange (ETDEWEB)

    Besleaga, C.; Stan, G.E.; Pintilie, I. [National Institute of Materials Physics, 405A Atomistilor, 077125 Magurele-Ilfov (Romania); Barquinha, P.; Fortunato, E. [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal); Martins, R., E-mail: rm@uninova.pt [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal)

    2016-08-30

    Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

  19. Low band-to-band tunnelling and gate tunnelling current in novel nanoscale double-gate architecture: simulations and investigation

    International Nuclear Information System (INIS)

    Datta, Deepanjan; Ganguly, Samiran; Dasgupta, S

    2007-01-01

    Large band-to-band tunnelling (BTBT) and gate leakage current can limit scalability of nanoscale devices. In this paper, we have proposed a novel nanoscale parallel connected heteromaterial double gate (PCHEM-DG) architecture with triple metal gate which significantly suppress BTBT leakage, making it efficient for low power design in the sub-10 nm regime. We have also proposed a triple gate device with p + poly-n + poly-p + poly gate which has substantially low gate leakage over symmetric DG MOSFET. Simulations are performed using a 2D Poisson-Schroedinger simulator and verified with a 2D device simulator ATLAS. We conclude that, due to intrinsic body doping, negligible gate leakage, suppressed BTBT over symmetric DG devices, metal gate (MG) PCHEM-DG MOSFET is efficient for low power circuit design in the nanometre regime

  20. Continuous adjustment of threshold voltage in carbon nanotube field-effect transistors through gate engineering

    Science.gov (United States)

    Zhong, Donglai; Zhao, Chenyi; Liu, Lijun; Zhang, Zhiyong; Peng, Lian-Mao

    2018-04-01

    In this letter, we report a gate engineering method to adjust threshold voltage of carbon nanotube (CNT) based field-effect transistors (FETs) continuously in a wide range, which makes the application of CNT FETs especially in digital integrated circuits (ICs) easier. Top-gated FETs are fabricated using solution-processed CNT network films with stacking Pd and Sc films as gate electrodes. By decreasing the thickness of the lower layer metal (Pd) from 20 nm to zero, the effective work function of the gate decreases, thus tuning the threshold voltage (Vt) of CNT FETs from -1.0 V to 0.2 V. The continuous adjustment of threshold voltage through gate engineering lays a solid foundation for multi-threshold technology in CNT based ICs, which then can simultaneously provide high performance and low power circuit modules on one chip.

  1. All-solution-processed bottom-gate organic thin-film transistor with improved subthreshold behaviour using functionalized pentacene active layer

    International Nuclear Information System (INIS)

    Kim, Jinwoo; Jeong, Jaewook; Cho, Hyun Duk; Lee, Changhee; Hong, Yongtaek; Kim, Seul Ong; Kwon, Soon-Ki

    2009-01-01

    We report organic thin-film transistors (OTFTs) made by simple solution processes in an ambient air environment. Inkjet-printed silver electrodes were used for bottom-gate and bottom-contacted source/drain electrodes. A spin-coated cross-linked poly(4-vinylphenol) (PVP) and a spin-coated 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) were used as a gate dielectric layer and an active layer, respectively. A high-boiling-point solvent was used for TIPS-pentacene and the resulting film showed stem-like morphology. X-ray diffraction (XRD) measurement showed the spin-coated active layer was well crystallized, showing the (0 0 1) plane. The reasonable mobility, on/off ratio and threshold voltage of the fabricated device, which are comparable to those of the previously reported TIPS-pentacene OTFT with gold electrodes, show that the printed silver electrodes worked successfully as gate and source/drain electrodes. Furthermore, the device showed a subthreshold slope of 0.61 V/dec in the linear region (V DS = -5 V), which is the lowest value for spin-coated TIPS-pentacene TFT ever reported, and much lower than that of the thermally evaporated pentacene OTFTs. It is thought that the surface energy of the PVP dielectric layer is well matched with that of a well-ordered TIPS-pentacene (0 0 1) surface when a high-boiling-point solvent and a low-temperature drying process are used, thereby making good interface properties, and showing higher performances than those for pentacene TFT with the same structure.

  2. Capacitance-voltage characteristics of MOS capacitors with Ge nanocrystals embedded in ZrO2 gate material

    International Nuclear Information System (INIS)

    Lee, Hye-Ryoung; Choi, Samjong; Cho, Kyoungah; Kim, Sangsig

    2007-01-01

    Capacitance versus voltage (C-V) curves of Ge-nanocrystals (NCs)-embedded metal-oxide-semiconductor (MOS) capacitors are characterized in this work. Ge NCs were formed in 20-nm thick ZrO 2 gate layers by ion implantation and subsequent annealing procedures. The formation of the Ge NCs in the ZrO 2 gate layers was confirmed by high-resolution transmission electron microscopy and energy dispersive spectroscopy. The C-V curves obtained from a representative MOS capacitor embedded with the Ge NCs exhibit a 3 V memory window as bias voltage varied from 9 to - 9 V and then back to the initial positive voltage, whereas MOS capacitors without Ge NCs show negligible memory windows at the same voltage range. This indicates the presence of charge storages in the Ge NCs. The counterclockwise hysteresis observed from the C-V curves implies that electrons are trapped in Ge NCs presented inside the ZrO 2 gate layer. And our experimental results obtained from capacitance versus time measurements show good retention characteristics of Ge-NCs-embedded MOS capacitors with ZrO 2 gate material for the application of NFGM

  3. Impedance Characterization of the Capacitive field-Effect pH-Sensor Based on a thin-Layer Hafnium Oxide Formed by Atomic Layer Deposition

    Directory of Open Access Journals (Sweden)

    Michael LEE

    2014-05-01

    Full Text Available As a sensing element, silicon dioxide (SiO2 has been applied within ion-sensitive field effect transistors (ISFET. However, a requirement of increasing pH-sensitivity and stability has observed an increased number of insulating materials that obtain high-k gate being applied as FETs. The increased high-k gate reduces the required metal oxide layer and, thus, the fabrication of thin hafnium oxide (HfO2 layers by atomic layer deposition (ALD has grown with interest in recent years. This metal oxide presents advantageous characteristics that can be beneficial for the advancements within miniaturization of complementary metal oxide semiconductor (CMOS technology. In this article, we describe a process for fabrication of HfO2 based on ALD by applying water (H2O as the oxygen precursor. As a first, electrochemical impedance spectroscopy (EIS measurements were performed with varying pH (2-10 to demonstrate the sensitivity of HfO2 as a potential pH sensing material. The Nyquist plot demonstrates a high clear shift of the polarization resistance (Rp between pH 6-10 (R2 = 0.9986, Y = 3,054X + 12,100. At acidic conditions (between pH 2-10, the Rp change was small due to the unmodified oxide gate (R2 = 0.9655, Y = 2,104X + 4,250. These preliminary results demonstrate the HfO2 substrate functioned within basic to neutral conditions and establishes a great potential for applying HfO2 as a dielectric material for future pH measuring FET sensors.

  4. Progress in MOSFET double-layer metalization

    Science.gov (United States)

    Gassaway, J. D.; Trotter, J. D.; Wade, T. E.

    1980-01-01

    Report describes one-year research effort in VLSL fabrication. Four activities are described: theoretical study of two-dimensional diffusion in SOS (silicon-on-sapphire); setup of sputtering system, furnaces, and photolithography equipment; experiments on double layer metal; and investigation of two-dimensional modeling of MOSFET's (metal-oxide-semiconductor field-effect transistors).

  5. Low band-to-band tunnelling and gate tunnelling current in novel nanoscale double-gate architecture: simulations and investigation

    Energy Technology Data Exchange (ETDEWEB)

    Datta, Deepanjan [Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47906 (United States); Ganguly, Samiran [Department of Electronics Engineering, Indian School of Mines, Dhanbad-826004 (India); Dasgupta, S [Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee-247667 (India)

    2007-05-30

    Large band-to-band tunnelling (BTBT) and gate leakage current can limit scalability of nanoscale devices. In this paper, we have proposed a novel nanoscale parallel connected heteromaterial double gate (PCHEM-DG) architecture with triple metal gate which significantly suppress BTBT leakage, making it efficient for low power design in the sub-10 nm regime. We have also proposed a triple gate device with p{sup +} poly-n{sup +} poly-p{sup +} poly gate which has substantially low gate leakage over symmetric DG MOSFET. Simulations are performed using a 2D Poisson-Schroedinger simulator and verified with a 2D device simulator ATLAS. We conclude that, due to intrinsic body doping, negligible gate leakage, suppressed BTBT over symmetric DG devices, metal gate (MG) PCHEM-DG MOSFET is efficient for low power circuit design in the nanometre regime.

  6. HfO2 as gate dielectric on Ge: Interfaces and deposition techniques

    International Nuclear Information System (INIS)

    Caymax, M.; Van Elshocht, S.; Houssa, M.; Delabie, A.; Conard, T.; Meuris, M.; Heyns, M.M.; Dimoulas, A.; Spiga, S.; Fanciulli, M.; Seo, J.W.; Goncharova, L.V.

    2006-01-01

    To fabricate MOS gate stacks on Ge, one can choose from a multitude of metal oxides as dielectric material which can be deposited by many chemical or physical vapor deposition techniques. As a few typical examples, we will discuss here the results from atomic layer deposition (ALD), metal organic CVD (MOCVD) and molecular beam deposition (MBD) using HfO 2 /Ge as materials model system. It appears that a completely interface layer free HfO 2 /Ge combination can be made in MBD, but this results in very bad capacitors. The same bad result we find if HfGe y (Hf germanides) are formed like in the case of MOCVD on HF-dipped Ge. A GeO x interfacial layer appears to be indispensable (if no other passivating materials are applied), but the composition of this interfacial layer (as determined by XPS, TOFSIMS and MEIS) is determining for the C/V quality. On the other hand, the presence of Ge in the HfO 2 layer is not the most important factor that can be responsible for poor C/V, although it can still induce bumps in C/V curves, especially in the form of germanates (Hf-O-Ge). We find that most of these interfacial GeO x layers are in fact sub-oxides, and that this could be (part of) the explanation for the high interfacial state densities. In conclusion, we find that the Ge surface preparation is determining for the gate stack quality, but it needs to be adapted to the specific deposition technique

  7. First-principles simulations of Graphene/Transition-metal-Dichalcogenides/Graphene Field-Effect Transistor

    Science.gov (United States)

    Li, Xiangguo; Wang, Yun-Peng; Zhang, X.-G.; Cheng, Hai-Ping

    A prototype field-effect transistor (FET) with fascinating properties can be made by assembling graphene and two-dimensional insulating crystals into three-dimensional stacks with atomic layer precision. Transition metal dichalcogenides (TMDCs) such as WS2, MoS2 are good candidates for the atomically thin barrier between two layers of graphene in the vertical FET due to their sizable bandgaps. We investigate the electronic properties of the Graphene/TMDCs/Graphene sandwich structure using first-principles method. We find that the effective tunnel barrier height of the TMDC layers in contact with the graphene electrodes has a layer dependence and can be modulated by a gate voltage. Consequently a very high ON/OFF ratio can be achieved with appropriate number of TMDC layers and a suitable range of the gate voltage. The spin-orbit coupling in TMDC layers is also layer dependent but unaffected by the gate voltage. These properties can be important in future nanoelectronic device designs. DOE/BES-DE-FG02-02ER45995; NERSC.

  8. Respiration Gates Sensory Input Responses in the Mitral Cell Layer of the Olfactory Bulb

    Science.gov (United States)

    Short, Shaina M.; Morse, Thomas M.; McTavish, Thomas S.; Shepherd, Gordon M.; Verhagen, Justus V.

    2016-01-01

    Respiration plays an essential role in odor processing. Even in the absence of odors, oscillating excitatory and inhibitory activity in the olfactory bulb synchronizes with respiration, commonly resulting in a burst of action potentials in mammalian mitral/tufted cells (MTCs) during the transition from inhalation to exhalation. This excitation is followed by inhibition that quiets MTC activity in both the glomerular and granule cell layers. Odor processing is hypothesized to be modulated by and may even rely on respiration-mediated activity, yet exactly how respiration influences sensory processing by MTCs is still not well understood. By using optogenetics to stimulate discrete sensory inputs in vivo, it was possible to temporally vary the stimulus to occur at unique phases of each respiration. Single unit recordings obtained from the mitral cell layer were used to map spatiotemporal patterns of glomerular evoked responses that were unique to stimulations occurring during periods of inhalation or exhalation. Sensory evoked activity in MTCs was gated to periods outside phasic respiratory mediated firing, causing net shifts in MTC activity across the cycle. In contrast, odor evoked inhibitory responses appear to be permitted throughout the respiratory cycle. Computational models were used to further explore mechanisms of inhibition that can be activated by respiratory activity and influence MTC responses. In silico results indicate that both periglomerular and granule cell inhibition can be activated by respiration to internally gate sensory responses in the olfactory bulb. Both the respiration rate and strength of lateral connectivity influenced inhibitory mechanisms that gate sensory evoked responses. PMID:28005923

  9. Material parameters from frequency dispersion simulation of floating gate memory with Ge nanocrystals in HfO2

    Science.gov (United States)

    Palade, C.; Lepadatu, A. M.; Slav, A.; Lazanu, S.; Teodorescu, V. S.; Stoica, T.; Ciurea, M. L.

    2018-01-01

    Trilayer memory capacitors with Ge nanocrystals (NCs) floating gate in HfO2 were obtained by magnetron sputtering deposition on p-type Si substrate followed by rapid thermal annealing at relatively low temperature of 600 °C. The frequency dispersion of capacitance and resistance was measured in accumulation regime of Al/HfO2 gate oxide/Ge NCs in HfO2 floating gate/HfO2 tunnel oxide/SiOx/p-Si/Al memory capacitors. For simulation of the frequency dispersion a complex circuit model was used considering an equivalent parallel RC circuit for each layer of the trilayer structure. A series resistance due to metallic contacts and Si substrate was necessary to be included in the model. A very good fit to the experimental data was obtained and the parameters of each layer in the memory capacitor, i.e. capacitances and resistances were determined and in turn the intrinsic material parameters, i.e. dielectric constants and resistivities of layers were evaluated. The results are very important for the study and optimization of the hysteresis behaviour of floating gate memories based on NCs embedded in oxide.

  10. Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt

    KAUST Repository

    Hinkle, Christopher L.; Galatage, Rohit V.; Chapman, Richard A.; Vogel, Eric M.; Alshareef, Husam N.; Freeman, Clive M.; Wimmer, Erich; Niimi, Hiroaki; Li-Fatou, Andrei V.; Shaw, Judy B.; Chambers, James J.

    2010-01-01

    In this contribution, NMOS and PMOS band edge effective work function (EWF) and correspondingly low Vt are demonstrated using standard fab materials and processes in a gate-last scheme. For NMOS, the use of an Al cladding layer results in Vt = 0.08 V consistent with NMOS EWF = 4.15 eV. Migration of the Al cladding into the TiN and a relatively low oxygen concentration near the TiN/HfO2 interface are responsible for the low EWF. For PMOS, employing a W cladding layer along with a post-TiN anneal in an oxidizing ambient results in elevated oxygen concentration near the TiN/HfO2 interface and Vt = -0.20 V consistent with a PMOS EWF = 5.05 eV. First-principles calculations indicate N atoms displaced from the TiN during the oxidizing anneal form dipoles at the TiN/HfO2 interface that play a critical role in determining the PMOS EWF. © 2010 IEEE.

  11. Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt

    KAUST Repository

    Hinkle, Christopher L.

    2010-06-01

    In this contribution, NMOS and PMOS band edge effective work function (EWF) and correspondingly low Vt are demonstrated using standard fab materials and processes in a gate-last scheme. For NMOS, the use of an Al cladding layer results in Vt = 0.08 V consistent with NMOS EWF = 4.15 eV. Migration of the Al cladding into the TiN and a relatively low oxygen concentration near the TiN/HfO2 interface are responsible for the low EWF. For PMOS, employing a W cladding layer along with a post-TiN anneal in an oxidizing ambient results in elevated oxygen concentration near the TiN/HfO2 interface and Vt = -0.20 V consistent with a PMOS EWF = 5.05 eV. First-principles calculations indicate N atoms displaced from the TiN during the oxidizing anneal form dipoles at the TiN/HfO2 interface that play a critical role in determining the PMOS EWF. © 2010 IEEE.

  12. Analytical modeling and simulation of subthreshold behavior in nanoscale dual material gate AlGaN/GaN HEMT

    Science.gov (United States)

    Kumar, Sona P.; Agrawal, Anju; Chaujar, Rishu; Gupta, Mridula; Gupta, R. S.

    2008-07-01

    A two-dimensional (2-D) analytical model for a Dual Material Gate (DMG) AlGaN/GaN High Electron Mobility Transistor (HEMT) has been developed to demonstrate the unique attributes of this device structure in suppressing short channel effects (SCEs). The model accurately predicts the channel potential, electric field variation along the channel, and sub-threshold drain current, taking into account the effect of lengths of the two gate metals, their work functions, barrier layer thicknesses, and applied drain biases. It is seen that the SCEs and hot carrier effects in DMG AlGaN/GaN HEMT are suppressed due to the work function difference of the two metal gates, thereby screening the drain potential variations by the gate near the drain. Besides, a more uniform electric field along the channel leads to improved carrier transport efficiency. The accuracy of the results obtained from our analytical model has been verified using ATLAS device simulations.

  13. ZnO buffer layer for metal films on silicon substrates

    Science.gov (United States)

    Ihlefeld, Jon

    2014-09-16

    Dramatic improvements in metallization integrity and electroceramic thin film performance can be achieved by the use of the ZnO buffer layer to minimize interfacial energy between metallization and adhesion layers. In particular, the invention provides a substrate metallization method utilizing a ZnO adhesion layer that has a high work of adhesion, which in turn enables processing under thermal budgets typically reserved for more exotic ceramic, single-crystal, or metal foil substrates. Embodiments of the present invention can be used in a broad range of applications beyond ferroelectric capacitors, including microelectromechanical systems, micro-printed heaters and sensors, and electrochemical energy storage, where integrity of metallized silicon to high temperatures is necessary.

  14. Metal-phthalocyanine ordered layers on Au(110): Metal-dependent adsorption energy

    Energy Technology Data Exchange (ETDEWEB)

    Massimi, Lorenzo, E-mail: lorenzo.massimi@uniroma1.it; Angelucci, Marco; Gargiani, Pierluigi; Betti, Maria Grazia [Dipartimento di Fisica, Università di Roma La “Sapienza,” 00185 Roma (Italy); Montoro, Silvia [IFIS Litoral, CONICET-UNL, Laboratorio de Fisica de Superficies e Interfaces, Güemes 3450, Santa Fe (Argentina); Mariani, Carlo, E-mail: carlo.mariani@uniroma1.it [Dipartimento di Fisica, CNISM, Università di Roma La “Sapienza,” 00185 Roma (Italy)

    2014-06-28

    Iron-phthalocyanine and cobalt-phthalocyanine chains, assembled along the Au(110)-(1×2) reconstructed channels, present a strong interaction with the Au metallic states, via the central metal ion. X-ray photoemission spectroscopy from the metal-2p core-levels and valence band high-resolution ultraviolet photoelectron spectroscopy bring to light signatures of the interaction of the metal-phthalocyanine single-layer with gold. The charge transfer from Au to the molecule causes the emerging of a metal-2p core level component at lower binding energy with respect to that measured in the molecular thin films, while the core-levels associated to the organic macrocycle (C and N 1s) are less influenced by the adsorption, and the macrocycles stabilize the interaction, inducing a strong interface dipole. Temperature Programmed Desorption experiments and photoemission as a function of temperature allow to estimate the adsorption energy for the thin-films, mainly due to the molecule-molecule van der Waals interaction, while the FePc and CoPc single-layers remain adsorbed on the Au surface up to at least 820 K.

  15. 100-nm gate lithography for double-gate transistors

    Science.gov (United States)

    Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

    2001-09-01

    The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

  16. Single attosecond pulse generation by using plasmon-driven double optical gating technology in crossed metal nanostructures

    Science.gov (United States)

    Feng, Liqiang; Liu, Katheryn

    2018-05-01

    An effective method to obtain the single attosecond pulses (SAPs) by using the multi-cycle plasmon-driven double optical gating (DOG) technology in the specifically designed metal nanostructures has been proposed and investigated. It is found that with the introduction of the crossed metal nanostructures along the driven and the gating polarization directions, not only the harmonic cutoff can be extended, but also the efficient high-order harmonic generation (HHG) at the very highest orders occurs only at one side of the region inside the nanostructure. As a result, a 93 eV supercontinuum with the near stable phase can be found. Further, by properly introducing an ultraviolet (UV) pulse into the driven laser polarization direction (which is defined as the DOG), the harmonic yield can be enhanced by two orders of magnitude in comparison with the singe polarization gating (PG) technology. However, as the polarized angle or the ellipticity of the UV pulse increase, the enhancement of the harmonic yield is slightly reduced. Finally, by superposing the selected harmonics from the DOG scheme, a 30 as SAP with intensity enhancement of two orders of magnitude can be obtained.

  17. Impacts of zinc layer and pouring method on interface performance for Al-22Si/ZL104 bi-metal

    Directory of Open Access Journals (Sweden)

    Jun-feng Zhao

    2017-01-01

    Full Text Available Bi-metal material consisting of spray-formed Al-22Si and ZL104 is a suitable candidate for applications in internal combustion engines. This research investigated the effects of surface treatment and appropriate gating system on the microstructures and mechanical properties in evaluating the optimal strategy for producing high quality bi-metal materials. The bi-metal materials were prepared using ZL104 gravity casting by different pouring types around the spray-formed Al-22Si with varied surface treatments. The wettability between Al-22Si and ZL104 was significantly improved when Zn coating was used to remove the natural oxide layer. This research also obtained the improved interfacial microstructures and interfacial bonding strength for materials when applying the appropriate pouring method. The hardness profiles of Al-22Si/ZL104 bi-metal were consistent with the observed microstructures. The average tensile strength of the bi-metal material with zinc coating is ~42.3 MPa, which is much higher than that with oxide film at ~10 MPa. The process presented is a promising and effective approach for developing materials in the automotive industry.

  18. Gate-Defined Quantum Confinement in InSe-based van der Waals Heterostructures.

    Science.gov (United States)

    Hamer, Matthew J; Tóvári, Endre; Zhu, Mengjian; Thompson, Michael Dermot; Mayorov, Alexander S; Prance, Jonathan; Lee, Yongjin; Haley, Richard; Kudrynskyi, Zakhar R; Patanè, Amalia; Terry, Daniel; Kovalyuk, Zakhar D; Ensslin, Klaus; Kretinin, Andrey V; Geim, Andre K; Gorbachev, Roman Vladislavovich

    2018-05-15

    Indium selenide, a post-transition metal chalcogenide, is a novel two-dimensional (2D) semiconductor with interesting electronic properties. Its tunable band gap and high electron mobility have already attracted considerable research interest. Here we demonstrate strong quantum confinement and manipulation of single electrons in devices made from few-layer crystals of InSe using electrostatic gating. We report on gate-controlled quantum dots in the Coulomb blockade regime as well as one-dimensional quantization in point contacts, revealing multiple plateaus. The work represents an important milestone in the development of quality devices based on 2D materials and makes InSe a prime candidate for relevant electronic and optoelectronic applications.

  19. Water-gel for gating graphene transistors.

    Science.gov (United States)

    Kim, Beom Joon; Um, Soong Ho; Song, Woo Chul; Kim, Yong Ho; Kang, Moon Sung; Cho, Jeong Ho

    2014-05-14

    Water, the primary electrolyte in biology, attracts significant interest as an electrolyte-type dielectric material for transistors compatible with biological systems. Unfortunately, the fluidic nature and low ionic conductivity of water prevents its practical usage in such applications. Here, we describe the development of a solid state, megahertz-operating, water-based gate dielectric system for operating graphene transistors. The new electrolyte systems were prepared by dissolving metal-substituted DNA polyelectrolytes into water. The addition of these biocompatible polyelectrolytes induced hydrogelation to provide solid-state integrity to the system. They also enhanced the ionic conductivities of the electrolytes, which in turn led to the quick formation of an electric double layer at the graphene/electrolyte interface that is beneficial for modulating currents in graphene transistors at high frequencies. At the optimized conditions, the Na-DNA water-gel-gated flexible transistors and inverters were operated at frequencies above 1 MHz and 100 kHz, respectively.

  20. Impact of metal nano layer thickness on tunneling oxide and memory performance of core-shell iridium-oxide nanocrystals

    Energy Technology Data Exchange (ETDEWEB)

    Banerjee, W.; Maikap, S. [Thin Film Nano Tech. Lab., Department of Electronic Engineering, Chang Gung University, Tao-Yuan, Taiwan 333, Taiwan (China); Tien, T.-C. [Material Research Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan 310, Taiwan (China); Li, W.-C.; Yang, J.-R. [Department of Materials Science and Engineering, National Taiwan University, Taipei 106, Taiwan (China)

    2011-10-01

    The impact of iridium-oxide (IrO{sub x}) nano layer thickness on the tunneling oxide and memory performance of IrO{sub x} metal nanocrystals in an n-Si/SiO{sub 2}/Al{sub 2}O{sub 3}/IrO{sub x}/Al{sub 2}O{sub 3}/IrO{sub x} structure has been investigated. A thinner (1.5 nm) IrO{sub x} nano layer has shown better memory performance than that of a thicker one (2.5 nm). Core-shell IrO{sub x} nanocrystals with a small average diameter of 2.4 nm and a high density of {approx}2 x 10{sup 12}/cm{sup 2} have been observed by scanning transmission electron microscopy. The IrO{sub x} nanocrystals are confirmed by x-ray photoelectron spectroscopy. A large memory window of 3.0 V at a sweeping gate voltage of {+-}5 V and 7.2 V at a sweeping gate voltage of {+-} 8 V has been observed for the 1.5 nm-thick IrO{sub x} nano layer memory capacitors with a small equivalent oxide thickness of 8 nm. The electrons and holes are trapped in the core and annular regions of the IrO{sub x} nanocrystals, respectively, which is explained by Gibbs free energy. High electron and hole-trapping densities are found to be 1.5 x 10{sup 13}/cm{sup 2} and 2 x 10{sup 13}/cm{sup 2}, respectively, due to the small size and high-density of IrO{sub x} nanocrystals. Excellent program/erase endurance of >10{sup 6} cycles and good retention of 10{sup 4} s with a good memory window of >1.2 V under a small operation voltage of {+-} 5 V are obtained. A large memory size of >10 Tbit/sq. in. can be designed by using the IrO{sub x} nanocrystals. This study is not only important for the IrO{sub x} nanocrystal charge-trapping memory investigation but it will also help to design future metal nanocrystal flash memory.

  1. Impact of metal nano layer thickness on tunneling oxide and memory performance of core-shell iridium-oxide nanocrystals

    International Nuclear Information System (INIS)

    Banerjee, W.; Maikap, S.; Tien, T.-C.; Li, W.-C.; Yang, J.-R.

    2011-01-01

    The impact of iridium-oxide (IrO x ) nano layer thickness on the tunneling oxide and memory performance of IrO x metal nanocrystals in an n-Si/SiO 2 /Al 2 O 3 /IrO x /Al 2 O 3 /IrO x structure has been investigated. A thinner (1.5 nm) IrO x nano layer has shown better memory performance than that of a thicker one (2.5 nm). Core-shell IrO x nanocrystals with a small average diameter of 2.4 nm and a high density of ∼2 x 10 12 /cm 2 have been observed by scanning transmission electron microscopy. The IrO x nanocrystals are confirmed by x-ray photoelectron spectroscopy. A large memory window of 3.0 V at a sweeping gate voltage of ±5 V and 7.2 V at a sweeping gate voltage of ± 8 V has been observed for the 1.5 nm-thick IrO x nano layer memory capacitors with a small equivalent oxide thickness of 8 nm. The electrons and holes are trapped in the core and annular regions of the IrO x nanocrystals, respectively, which is explained by Gibbs free energy. High electron and hole-trapping densities are found to be 1.5 x 10 13 /cm 2 and 2 x 10 13 /cm 2 , respectively, due to the small size and high-density of IrO x nanocrystals. Excellent program/erase endurance of >10 6 cycles and good retention of 10 4 s with a good memory window of >1.2 V under a small operation voltage of ± 5 V are obtained. A large memory size of >10 Tbit/sq. in. can be designed by using the IrO x nanocrystals. This study is not only important for the IrO x nanocrystal charge-trapping memory investigation but it will also help to design future metal nanocrystal flash memory.

  2. Rare earth zirconium oxide buffer layers on metal substrates

    Science.gov (United States)

    Williams, Robert K.; Paranthaman, Mariappan; Chirayil, Thomas G.; Lee, Dominic F.; Goyal, Amit; Feenstra, Roeland

    2001-01-01

    A laminate article comprises a substrate and a biaxially textured (RE.sub.x A.sub.(1-x)).sub.2 O.sub.2-(x/2) buffer layer over the substrate, wherein 0layer can be deposited using sol-gel or metal-organic decomposition. The laminate article can include a layer of YBCO over the (RE.sub.x A.sub.(1-x)).sub.2 O.sub.2-(x/2) buffer layer. A layer of CeO.sub.2 between the YBCO layer and the (RE.sub.x A.sub.(1-x)).sub.2 O.sub.2-(x/2) buffer layer can also be include. Further included can be a layer of YSZ between the CeO.sub.2 layer and the (RE.sub.x A.sub.(1-x)).sub.2 O.sub.2-(x/2) buffer layer. The substrate can be a biaxially textured metal, such as nickel. A method of forming the laminate article is also disclosed.

  3. Control of interlayer physics in 2H transition metal dichalcogenides

    Science.gov (United States)

    Wang, Kuang-Chung; Stanev, Teodor K.; Valencia, Daniel; Charles, James; Henning, Alex; Sangwan, Vinod K.; Lahiri, Aritra; Mejia, Daniel; Sarangapani, Prasad; Povolotskyi, Michael; Afzalian, Aryan; Maassen, Jesse; Klimeck, Gerhard; Hersam, Mark C.; Lauhon, Lincoln J.; Stern, Nathaniel P.; Kubis, Tillmann

    2017-12-01

    It is assessed in detail both experimentally and theoretically how the interlayer coupling of transition metal dichalcogenides controls the electronic properties of the respective devices. Gated transition metal dichalcogenide structures show electrons and holes to either localize in individual monolayers, or delocalize beyond multiple layers—depending on the balance between spin-orbit interaction and interlayer hopping. This balance depends on the layer thickness, momentum space symmetry points, and applied gate fields. The design range of this balance, the effective Fermi levels, and all relevant effective masses is analyzed in great detail. A good quantitative agreement of predictions and measurements of the quantum confined Stark effect in gated MoS2 systems unveils intralayer excitons as the major source for the observed photoluminescence.

  4. Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

    Science.gov (United States)

    Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

    2018-04-01

    In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

  5. Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

    KAUST Repository

    Ghoneim, Mohamed T.

    2015-06-01

    We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard bulk mono-crystalline silicon substrate. A lifetime projection is extracted using statistical analysis of the ramping voltage (Vramp) breakdown and time dependent dielectric breakdown data. The obtained flexible MOSCAPs operational voltages satisfying the 10 years lifetime benchmark are compared to those of the control MOSCAPs, which are not peeled off from the silicon wafer. © 2014 IEEE.

  6. Polymer thin film as coating layer to prevent corrosion of metal/metal oxide film

    Science.gov (United States)

    Sarkar, Suman; Kundu, Sarathi

    2018-04-01

    Thin film of polymer is used as coating layer and the corrosion of metal/metal oxide layer is studied with the variation of the thickness of the coating layer. The thin layer of polystyrene is fabricated using spin coating method on copper oxide (CuO) film which is deposited on glass substrate using DC magnetron sputtering technique. Thickness of the polystyrene and the CuO layers are determined using X-ray reflectivity (XRR) technique. CuO thin films coated with the polystyrene layer are exposed to acetic acid (2.5 v/v% aqueous CH3COOH solution) environments and are subsequently analyzed using UV-Vis spectroscopy and atomic force microscopy (AFM). Surface morphology of the film before and after interaction with the acidic environment is determined using AFM. Results obtained from the XRR and UV-Vis spectroscopy confirm that the thin film of polystyrene acts as an anticorrosion coating layer and the strength of the coating depends upon the polymer layer thickness at a constant acid concentration.

  7. High performance high-κ/metal gate complementary metal oxide semiconductor circuit element on flexible silicon

    KAUST Repository

    Sevilla, Galo T.

    2016-02-29

    Thinned silicon based complementary metal oxide semiconductor(CMOS)electronics can be physically flexible. To overcome challenges of limited thinning and damaging of devices originated from back grinding process, we show sequential reactive ion etching of silicon with the assistance from soft polymeric materials to efficiently achieve thinned (40 μm) and flexible (1.5 cm bending radius) silicon based functional CMOSinverters with high-κ/metal gate transistors. Notable advances through this study shows large area of silicon thinning with pre-fabricated high performance elements with ultra-large-scale-integration density (using 90 nm node technology) and then dicing of such large and thinned (seemingly fragile) pieces into smaller pieces using excimer laser. The impact of various mechanical bending and bending cycles show undeterred high performance of flexible siliconCMOSinverters. Future work will include transfer of diced silicon chips to destination site, interconnects, and packaging to obtain fully flexible electronic systems in CMOS compatible way.

  8. Quantum ballistic analysis of transition metal dichalcogenides based double gate junctionless field effect transistor and its application in nano-biosensor

    Science.gov (United States)

    Shadman, Abir; Rahman, Ehsanur; Khosru, Quazi D. M.

    2017-11-01

    To reduce the thermal budget and the short channel effects in state of the art CMOS technology, Junctionless field effect transistor (JLFET) has been proposed in the literature. Numerous experimental, modeling, and simulation based works have been done on this new FET with bulk materials for various geometries until now. On the other hand, the two-dimensional layered material is considered as an alternative to current Si technology because of its ultra-thin body and high mobility. Very recently few simulation based works have been done on monolayer molybdenum disulfide based JLFET mainly to show the advantage of JLFET over conventional FET. However, no comprehensive simulation-based work has been done for double gate JLFET keeping in mind the prominent transition metal dichalcogenides (TMDC) to the authors' best knowledge. In this work, we have studied quantum ballistic drain current-gate voltage characteristics of such FETs within non-equilibrium Green's function (NEGF) framework. Our simulation results reveal that all these TMDC materials are viable options for implementing state of the art Junctionless MOSFET with emphasis on their performance at short gate lengths. Besides evaluating the prospect of TMDC materials in the digital logic application, the performance of Junctionless Double Gate trilayer TMDC heterostructure FET for the label-free electrical detection of biomolecules in dry environment has been investigated for the first time to the authors' best knowledge. The impact of charge neutral biomolecules on the electrical characteristics of the biosensor has been analyzed under dry environment situation. Our study shows that these materials could provide high sensitivity in the sub-threshold region as a channel material in nano-biosensor, a trend demonstrated by silicon on insulator FET sensor in the literature. Thus, going by the trend of replacing silicon with these novel materials in device level, TMDC heterostructure could be a viable alternative to

  9. Paraffin wax passivation layer improvements in electrical characteristics of bottom gate amorphous indium–gallium–zinc oxide thin-film transistors

    International Nuclear Information System (INIS)

    Chang, Geng-Wei; Chang, Ting-Chang; Syu, Yong-En; Tsai, Tsung-Ming; Chang, Kuan-Chang; Tu, Chun-Hao; Jian, Fu-Yen; Hung, Ya-Chi; Tai, Ya-Hsiang

    2011-01-01

    In this research, paraffin wax is employed as the passivation layer of the bottom gate amorphous indium–gallium–zinc oxide thin-film transistors (a-IGZO TFTs), and it is formed by sol–gel process in the atmosphere. The high yield and low cost passivation layer of sol–gel process technology has attracted much attention for current flat-panel-display manufacturing. Comparing with passivation-free a-IGZO TFTs, passivated devices exhibit a superior stability against positive gate bias stress in different ambient gas, demonstrating that paraffin wax shows gas-resisting characteristics for a-IGZO TFTs application. Furthermore, light-induced stretch-out phenomenon for paraffin wax passivated device is suppressed. This superior stability of the passivated device was attributed to the reduced total density of states (DOS) including the interfacial and semiconductor bulk trap densities.

  10. P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

    Science.gov (United States)

    Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

    2018-04-01

    In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

  11. Alkali metal and alkali metal hydroxide intercalates of the layered transition metal disulfides

    International Nuclear Information System (INIS)

    Kanzaki, Y.; Konuma, M.; Matsumoto, O.

    1981-01-01

    The intercalation reaction of some layered transition metal disulfides with alkali metals, alkali metal hydroxides, and tetraalkylammonium hydroxides were investigated. The alkali metal intercalates were prepared in the respective metal-hexamethylphosphoric triamide solutions in vaccuo, and the hydroxide intercalates in aqueous hydroxide solutions. According to the intercalation reaction, the c-lattice parameter was increased, and the increase indicated the expansion of the interlayer distance. In the case of alkali metal intercalates, the expansion of the interlayer distance increased continuously, corresponding to the atomic radius of the alkali metal. On the other hand, the hydroxide intercalates showed discrete expansion corresponding to the effective ionic radius of the intercalated cation. All intercalates of TaS 2 amd NbS 2 were superconductors. The expansion of the interlayer distance tended to increase the superconducting transition temperature in the intercalates of TaS 2 and vice versa in those of NbS 2 . (orig.)

  12. Experimental and theoretical investigation of the effect of SiO2 content in gate dielectrics on work function shift induced by nanoscale capping layers

    KAUST Repository

    Caraveo-Frescas, J. A.; Wang, H.; Schwingenschlö gl, Udo; Alshareef, Husam N.

    2012-01-01

    The impact of SiO2 content in ultrathin gate dielectrics on the magnitude of the effective work function (EWF) shift induced by nanoscale capping layers has been investigated experimentally and theoretically. The magnitude of the effective work function shift for four different capping layers (AlN, Al2O3, La2O3, and Gd2O3) is measured as a function of SiO2 content in the gate dielectric. A nearly linear increase of this shift with SiO2 content is observed for all capping layers. The origin of this dependence is explained using density functional theory simulations.

  13. Experimental and theoretical investigation of the effect of SiO2 content in gate dielectrics on work function shift induced by nanoscale capping layers

    KAUST Repository

    Caraveo-Frescas, J. A.

    2012-09-10

    The impact of SiO2 content in ultrathin gate dielectrics on the magnitude of the effective work function (EWF) shift induced by nanoscale capping layers has been investigated experimentally and theoretically. The magnitude of the effective work function shift for four different capping layers (AlN, Al2O3, La2O3, and Gd2O3) is measured as a function of SiO2 content in the gate dielectric. A nearly linear increase of this shift with SiO2 content is observed for all capping layers. The origin of this dependence is explained using density functional theory simulations.

  14. A high performance gate drive for large gate turn off thyristors

    Energy Technology Data Exchange (ETDEWEB)

    Szilagyi, C.P.

    1993-01-01

    Past approaches to gate turn-off (GTO) gating are application oriented, inefficient and dissipate power even when inactive. They allow the gate to avalanch, and do not reduce GTO turn-on and turn-off losses. A new approach is proposed which will allow modular construction and adaptability to large GTOs in the 50 amp to 2000 amp range. The proposed gate driver can be used in large voltage source and current source inverters and other power converters. The approach consists of a power metal-oxide-silicon field effect transistor (MOSFET) technology gating unit, with associated logic and supervisory circuits and an isolated flyback converter as the dc power source for the gating unit. The gate driver formed by the gating unit and the flyback converter is designed for 4000 V isolation. Control and supervisory signals are exchanged between the gate driver and the remote control system via fiber optics. The gating unit has programmable front-porch current amplitude and pulse-width, programmable closed-loop controlled back-porch current, and a turn-off switch capable of supplying negative gate current at demand as a function of peak controllable forward anode current. The GTO turn-on, turn-off and gate avalanch losses are reduced to a minimum. The gate driver itself has minimum operating losses. Analysis, design and practical realization are reported. 19 refs., 54 figs., 1 tab.

  15. Metal-oxide assisted surface treatment of polyimide gate insulators for high-performance organic thin-film transistors.

    Science.gov (United States)

    Kim, Sohee; Ha, Taewook; Yoo, Sungmi; Ka, Jae-Won; Kim, Jinsoo; Won, Jong Chan; Choi, Dong Hoon; Jang, Kwang-Suk; Kim, Yun Ho

    2017-06-14

    We developed a facile method for treating polyimide-based organic gate insulator (OGI) surfaces with self-assembled monolayers (SAMs) by introducing metal-oxide interlayers, called the metal-oxide assisted SAM treatment (MAST). To create sites for surface modification with SAM materials on polyimide-based OGI (KPI) surfaces, the metal-oxide interlayer, here amorphous alumina (α-Al 2 O 3 ), was deposited on the KPI gate insulator using spin-coating via a rapid sol-gel reaction, providing an excellent template for the formation of a high-quality SAM with phosphonic acid anchor groups. The SAM of octadecylphosphonic acid (ODPA) was successfully treated by spin-coating onto the α-Al 2 O 3 -deposited KPI film. After the surface treatment by ODPA/α-Al 2 O 3 , the surface energy of the KPI thin film was remarkably decreased and the molecular compatibility of the film with an organic semiconductor (OSC), 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-C 10 ), was increased. Ph-BTBT-C 10 molecules were uniformly deposited on the treated gate insulator surface and grown with high crystallinity, as confirmed by atomic force microscopy (AFM) and X-ray diffraction (XRD) analysis. The mobility of Ph-BTBT-C 10 thin-film transistors (TFTs) was approximately doubled, from 0.56 ± 0.05 cm 2 V -1 s -1 to 1.26 ± 0.06 cm 2 V -1 s -1 , after the surface treatment. The surface treatment of α-Al 2 O 3 and ODPA significantly decreased the threshold voltage from -21.2 V to -8.3 V by reducing the trap sites in the OGI and improving the interfacial properties with the OSC. We suggest that the MAST method for OGIs can be applied to various OGI materials lacking reactive sites using SAMs. It may provide a new platform for the surface treatment of OGIs, similar to that of conventional SiO 2 gate insulators.

  16. Work Function Tuning in Sub-20nm Titanium Nitride (TiN) Metal Gate: Mechanism and Engineering

    KAUST Repository

    Hasan, Mehdi

    2011-01-01

    thermal budget flow (replicating gate-last) shows similar work function boost up. Also, a work function modulation of 250meV has been possible using oxygen annealing and applying no thermal budget. On the other hand, etch-back of TiN layer can decrease

  17. In situ atomic layer nitridation on the top and down regions of the amorphous and crystalline high-K gate dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Tsai, Meng-Chen [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China); Lee, Min-Hung [Institute of Electro-Optical Science and Technology, National Taiwan Normal University, Taipei 11677, Taiwan (China); Kuo, Chin-Lung; Lin, Hsin-Chih [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China); Chen, Miin-Jang, E-mail: mjchen@ntu.edu.tw [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China)

    2016-11-30

    Highlights: • The structural and electrical characteristics of the ZrO{sub 2} high-K dielectrics, treated with the in situ atomic layer doping of nitrogen into the top and down regions (top and down nitridation, TN and DN, respectively), were investigated. • The amorphous DN sample has a lower leakage current density (J{sub g}) than the amorphous TN sample, attributed to the formation of SiO{sub x}N{sub y} in the interfacial layer (IL). • The crystalline TN sample exhibited a lower CET and a similar J{sub g} as compared with the crystalline DN sample, which can be ascribed to the suppression of IL regrowth. • The crystalline ZrO{sub 2} with in situ atomic layer doping of nitrogen into the top region exhibited superior scaling limit, electrical characteristics, and reliability. - Abstract: Amorphous and crystalline ZrO{sub 2} gate dielectrics treated with in situ atomic layer nitridation on the top and down regions (top and down nitridation, abbreviated as TN and DN) were investigated. In a comparison between the as-deposited amorphous DN and TN samples, the DN sample has a lower leakage current density (J{sub g}) of ∼7 × 10{sup −4} A/cm{sup 2} with a similar capacitance equivalent thickness (CET) of ∼1.53 nm, attributed to the formation of SiO{sub x}N{sub y} in the interfacial layer (IL). The post-metallization annealing (PMA) leads to the transformation of ZrO{sub 2} from the amorphous to the crystalline tetragonal/cubic phase, resulting in an increment of the dielectric constant. The PMA-treated TN sample exhibits a lower CET of 1.22 nm along with a similar J{sub g} of ∼1.4 × 10{sup −5} A/cm{sup 2} as compared with the PMA-treated DN sample, which can be ascribed to the suppression of IL regrowth. The result reveals that the nitrogen engineering in the top and down regions has a significant impact on the electrical characteristics of amorphous and crystalline ZrO{sub 2} gate dielectrics, and the nitrogen incorporation at the top of crystalline

  18. Transferred metal electrode films for large-area electronic devices

    International Nuclear Information System (INIS)

    Yang, Jin-Guo; Kam, Fong-Yu; Chua, Lay-Lay

    2014-01-01

    The evaporation of metal-film gate electrodes for top-gate organic field-effect transistors (OFETs) limits the minimum thickness of the polymer gate dielectric to typically more than 300 nm due to deep hot metal atom penetration and damage of the dielectric. We show here that the self-release layer transfer method recently developed for high-quality graphene transfer is also capable of giving high-quality metal thin-film transfers to produce high-performance capacitors and OFETs with superior dielectric breakdown strength even for ultrathin polymer dielectric films. Dielectric breakdown strengths up to 5–6 MV cm −1 have been obtained for 50-nm thin films of polystyrene and a cyclic olefin copolymer TOPAS ® (Zeon). High-quality OFETs with sub-10 V operational voltages have been obtained this way using conventional polymer dielectrics and a high-mobility polymer semiconductor poly[2,5-bis(3-tetradecylthiophene-2-yl)thieno[3,2-b]thiophene-2,5-diyl]. The transferred metal films can make reliable contacts without damaging ultrathin polymer films, self-assembled monolayers and graphene, which is not otherwise possible from evaporated or sputtered metal films

  19. Surface plasmons based terahertz modulator consisting of silicon-air-metal-dielectric-metal layers

    Science.gov (United States)

    Wang, Wei; Yang, Dongxiao; Qian, Zhenhai

    2018-05-01

    An optically controlled modulator of the terahertz wave, which is composed of a metal-dielectric-metal structure etched with circular loop arrays on both the metal layers and a photoexcited silicon wafer separated by an air layer, is proposed. Simulation results based on experimentally measured complex permittivities predict that modification of complex permittivity of the silicon wafer through excitation laser leads to a significant tuning of transmission characteristics of the modulator, forming the modulation depths of 59.62% and 96.64% based on localized surface plasmon peak and propagating surface plasmon peak, respectively. The influences of the complex permittivity of the silicon wafer and the thicknesses of both the air layer and the silicon wafer are numerically studied for better understanding the modulation mechanism. This study proposes a feasible methodology to design an optically controlled terahertz modulator with large modulation depth, high speed and suitable insertion loss, which is useful for terahertz applications in the future.

  20. Maximizing the value of gate capacitance in field-effect devices using an organic interface layer

    Science.gov (United States)

    Kwok, H. L.

    2015-12-01

    Past research has confirmed the existence of negative capacitance in organics such as tris (8-Hydroxyquinoline) Aluminum (Alq3). This work explored using such an organic interface layer to enhance the channel voltage in the field-effect transistor (FET) thereby lowering the sub-threshold swing. In particular, if the values of the positive and negative gate capacitances are approximately equal, the composite negative capacitance will increase by orders of magnitude. One concern is the upper frequency limit (∼100 Hz) over which negative capacitance has been observed. Nonetheless, this frequency limit can be raised to kHz when the organic layer is subjected to a DC bias.

  1. A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

    Science.gov (United States)

    Priya, Anjali; Mishra, Ram Awadh

    2016-04-01

    In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.

  2. Tuning the magnetoresistance of ultrathin WTe2 sheets by electrostatic gating.

    Science.gov (United States)

    Na, Junhong; Hoyer, Alexander; Schoop, Leslie; Weber, Daniel; Lotsch, Bettina V; Burghard, Marko; Kern, Klaus

    2016-11-10

    The semimetallic, two-dimensional layered transition metal dichalcogenide WTe 2 has raised considerable interest due to its huge, non-saturating magnetoresistance. While for the origin of this effect, a close-to-ideal balance of electrons and holes has been put forward, the carrier concentration dependence of the magnetoresistance remains to be clarified. Here, we present a detailed study of the magnetotransport behaviour of ultrathin, mechanically exfoliated WTe 2 sheets as a function of electrostatic back gating. The carrier concentration and mobility, determined using the two band model and analysis of the Shubnikov-de Haas oscillations, indicate enhanced surface scattering for the thinnest sheets. By the back gate action, the magnetoresistance could be tuned by up to ∼100% for a ∼13 nm-thick WTe 2 sheet.

  3. Short-Term Synaptic Plasticity Regulation in Solution-Gated Indium-Gallium-Zinc-Oxide Electric-Double-Layer Transistors.

    Science.gov (United States)

    Wan, Chang Jin; Liu, Yang Hui; Zhu, Li Qiang; Feng, Ping; Shi, Yi; Wan, Qing

    2016-04-20

    In the biological nervous system, synaptic plasticity regulation is based on the modulation of ionic fluxes, and such regulation was regarded as the fundamental mechanism underlying memory and learning. Inspired by such biological strategies, indium-gallium-zinc-oxide (IGZO) electric-double-layer (EDL) transistors gated by aqueous solutions were proposed for synaptic behavior emulations. Short-term synaptic plasticity, such as paired-pulse facilitation, high-pass filtering, and orientation tuning, was experimentally emulated in these EDL transistors. Most importantly, we found that such short-term synaptic plasticity can be effectively regulated by alcohol (ethyl alcohol) and salt (potassium chloride) additives. Our results suggest that solution gated oxide-based EDL transistors could act as the platforms for short-term synaptic plasticity emulation.

  4. Gate-voltage control of equal-spin Andreev reflection in half-metal/semiconductor/superconductor junctions

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Xiuqiang, E-mail: xianqiangzhe@126.com [National Laboratory of Solid State Microstructures and Department of Physics, Nanjing University, Nanjing 210093 (China); Meng, Hao, E-mail: menghao1982@shu.edu.cn [School of Physics and Telecommunication Engineering, Shanxi University of Technology, Hanzhong 723001 (China)

    2016-04-22

    With the Blonder–Tinkham–Klapwijk (BTK) approach, we investigate conductance spectrum in Ferromagnet/Semiconductor/Superconductor (FM/Sm/SC) double tunnel junctions where strong Rashba spin–orbit interaction (RSOI) is taken into account in semiconductors. For the half-metal limit, we find that the in-gap conductance becomes finite except at zero voltage when inserting a ferromagnetic insulator (FI) at the Sm/SC interface, which means that the appearance of a long-range triplet states in the half-metal. This is because of the emergence of the unconventional equal-spin Andreev reflection (ESAR). When the FI locates at the FM/Sm interface, however, we find the vanishing in-gap conductance due to the absence of the ESAR. Moreover, the non-zero in-gap conductance shows a nonmonotonic dependence on RSOI which can be controlled by applying an external gate voltage. Our results can be used to generate and manipulate the long-range spin triplet correlation in the nascent field of superconducting spintronics. - Highlights: • We study the equal-spin Andreev reflection in half-metal/semiconductor/superconductor (HM/Sm/SC) junctions. • The equal-spin Andreev reflection appearance when inserting a ferromagnetic insulator at the Sm/SC interface. • The finite in-gap conductance is attributed to the emergence of the equal-spin Andreev reflection. • The finite in-gap conductance shows a nonmonotonic dependence on Rashba spin–orbit interaction. • The finite in-gap conductance can be controlled by applying an external gate voltage.

  5. Photon-gated spin transistor

    OpenAIRE

    Li, Fan; Song, Cheng; Cui, Bin; Peng, Jingjing; Gu, Youdi; Wang, Guangyue; Pan, Feng

    2017-01-01

    Spin-polarized field-effect transistor (spin-FET), where a dielectric layer is generally employed for the electrical gating as the traditional FET, stands out as a seminal spintronic device under the miniaturization trend of electronics. It would be fundamentally transformative if optical gating was used for spin-FET. We report a new type of spin-polarized field-effect transistor (spin-FET) with optical gating, which is fabricated by partial exposure of the (La,Sr)MnO3 channel to light-emitti...

  6. Optical XOR gate

    Science.gov (United States)

    Vawter, G. Allen

    2013-11-12

    An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  7. Top-gate pentacene-based organic field-effect transistor with amorphous rubrene gate insulator

    Science.gov (United States)

    Hiroki, Mizuha; Maeda, Yasutaka; Ohmi, Shun-ichiro

    2018-02-01

    The scaling of organic field-effect transistors (OFETs) is necessary for high-density integration and for this, OFETs with a top-gate configuration are required. There have been several reports of damageless lithography processes for organic semiconductor or insulator layers. However, it is still difficult to fabricate scaled OFETs with a top-gate configuration. In this study, the lift-off process and the device characteristics of the OFETs with a top-gate configuration utilizing an amorphous (α) rubrene gate insulator were investigated. We have confirmed that α-rubrene shows an insulating property, and its extracted linear mobility was 2.5 × 10-2 cm2/(V·s). The gate length and width were 10 and 60 µm, respectively. From these results, the OFET with a top-gate configuration utilizing an α-rubrene gate insulator is promising for the high-density integration of scaled OFETs.

  8. Photolithographically Patterned TiO2 Films for Electrolyte-Gated Transistors.

    Science.gov (United States)

    Valitova, Irina; Kumar, Prajwal; Meng, Xiang; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

    2016-06-15

    Metal oxides constitute a class of materials whose properties cover the entire range from insulators to semiconductors to metals. Most metal oxides are abundant and accessible at moderate cost. Metal oxides are widely investigated as channel materials in transistors, including electrolyte-gated transistors, where the charge carrier density can be modulated by orders of magnitude upon application of relatively low electrical bias (2 V). Electrolyte gating offers the opportunity to envisage new applications in flexible and printed electronics as well as to improve our current understanding of fundamental processes in electronic materials, e.g. insulator/metal transitions. In this work, we employ photolithographically patterned TiO2 films as channels for electrolyte-gated transistors. TiO2 stands out for its biocompatibility and wide use in sensing, electrochromics, photovoltaics and photocatalysis. We fabricated TiO2 electrolyte-gated transistors using an original unconventional parylene-based patterning technique. By using a combination of electrochemical and charge carrier transport measurements we demonstrated that patterning improves the performance of electrolyte-gated TiO2 transistors with respect to their unpatterned counterparts. Patterned electrolyte-gated (EG) TiO2 transistors show threshold voltages of about 0.9 V, ON/OFF ratios as high as 1 × 10(5), and electron mobility above 1 cm(2)/(V s).

  9. Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process

    International Nuclear Information System (INIS)

    Wang Yan-Rong; Yang Hong; Xu Hao; Wang Xiao-Lei; Luo Wei-Chun; Qi Lu-Wei; Zhang Shu-Xiang; Wang Wen-Wu; Yan Jiang; Zhu Hui-Long; Zhao Chao; Chen Da-Peng; Ye Tian-Chun

    2015-01-01

    A multi-deposition multi-annealing technique (MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device’s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown (TDDB) characteristics of positive channel metal oxide semiconductor (PMOS) under different MDMA process conditions, including the deposition/annealing (D and A) cycles, the D and A time, and the total annealing time. The results show that the increases of the number of D and A cycles (from 1 to 2) and D and A time (from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail (TTF) at 63.2% increases by about several times. However, too many D and A cycles (such as 4 cycles) make the equivalent oxide thickness (EOT) increase by about 1 Å and the TTF of PMOS worsen. Moreover, different D and A times and numbers of D and A cycles induce different breakdown mechanisms. (paper)

  10. Methanogens predominate in natural corrosion protective layers on metal sheet piles.

    NARCIS (Netherlands)

    Kip, Nardy; Jansen, S.; Leite, M.F.A.; De Hollander, M.; Afanasyev, M.; Kuramae, E.E.; van Veen, J.A.

    2017-01-01

    Microorganisms are able to cause, but also to inhibit or protect against corrosion. Corrosion inhibition by microbial processes may be due to the formation of mineral deposition layers on metal objects. Such deposition layers have been found in archaeological studies on ancient metal objects, buried

  11. Spray coating of self-aligning passivation layer for metal grid lines

    NARCIS (Netherlands)

    Vuorinen, T.; Janka, M.; Rubingh, J.E.J.M.; Tuukkanen, S.; Groen, P.; Lupo, D.

    2014-01-01

    In applications such as organic light emitting diodes (OLEDs) or photovoltaic cells a homogenous voltage distribution in the large anode layer needs to be ensured by including a metal grid with a transparent conductor layer. To ensure sufficient conductivity, relatively thick metal lines are used,

  12. Ambipolar field-effect transistors by few-layer InSe with asymmetry contact metals

    Directory of Open Access Journals (Sweden)

    Chang-Yu Lin

    2017-07-01

    Full Text Available Group IIIA−VIA layered semiconductors (MX, where M = Ga and In, X = S, Se, and Te have attracted tremendous interest for their anisotropic optical, electronic, and mechanical properties. In this study, we demonstrated that metal and InSe junctions can lead to carrier behaviors in few-layered InSe FETs. These results indicate that the polarity of few-layered InSe FETs can be determined by using metals with different work functions. We adopted FET S/D metal contacts with asymmetric work functions to reduce the Schottky barriers of electrons and holes, and discovered that few-layered InSe FETs with carefully selected metal contacts can achieve ambipolar behaviors. These results indicate that group IIIA−VIA layered semiconductor FETs with asymmetry contact metals have great potential for applications in photovoltaic devices, optical sensors, and CMOS inverter circuits.

  13. Nonlinear optical properties of ultrathin metal layers

    DEFF Research Database (Denmark)

    Lysenko, Oleg

    2016-01-01

    This thesis presents experimental and theoretical studies of nonlinear propagation of ultrashort long-range surface plasmon polaritons in gold strip waveguides. The strip plasmonic waveguides are fabricated in house, and contain a gold layer, adhesion layers, and silicon dioxide cladding. The opt......This thesis presents experimental and theoretical studies of nonlinear propagation of ultrashort long-range surface plasmon polaritons in gold strip waveguides. The strip plasmonic waveguides are fabricated in house, and contain a gold layer, adhesion layers, and silicon dioxide cladding......-order nonlinear susceptibility of the plasmonic mode in the gold strip waveguides significantly depends on the metal layer thickness and laser pulse duration. This dependence is explained in detail in terms of the free-electron temporal dynamics in gold. The third-order nonlinear susceptibility of the gold layer...

  14. Mechanisms for plasma etching of HfO{sub 2} gate stacks with Si selectivity and photoresist trimming

    Energy Technology Data Exchange (ETDEWEB)

    Shoeb, Juline; Kushner, Mark J. [Department of Electrical and Computer Engineering, Iowa State University, Ames, Iowa 50011 (United States); Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109-2122 (United States)

    2009-11-15

    To minimize leakage currents resulting from the thinning of the insulator in the gate stack of field effect transistors, high-dielectric constant (high-k) metal oxides, and HfO{sub 2} in particular, are being implemented as a replacement for SiO{sub 2}. To speed the rate of processing, it is desirable to etch the gate stack (e.g., metal gate, antireflection layers, and dielectric) in a single process while having selectivity to the underlying Si. Plasma etching using Ar/BCl{sub 3}/Cl{sub 2} mixtures effectively etches HfO{sub 2} while having good selectivity to Si. In this article, results from integrated reactor and feature scale modeling of gate-stack etching in Ar/BCl{sub 3}/Cl{sub 2} plasmas, preceded by photoresist trimming in Ar/O{sub 2} plasmas, are discussed. It was found that BCl{sub n} species react with HfO{sub 2}, which under ion impact, form volatile etch products such as B{sub m}OCl{sub n} and HfCl{sub n}. Selectivity to Si is achieved by creating Si-B bonding as a precursor to the deposition of a BCl{sub n} polymer which slows the etch rate relative to HfO{sub 2}. The low ion energies required to achieve this selectivity then challenge one to obtain highly anisotropic profiles in the metal gate portion of the stack. Validation was performed with data from literature. The effect of bias voltage and key reactant probabilities on etch rate, selectivity, and profile are discussed.

  15. Inorganic-Organic Coating via Molecular Layer Deposition Enables Long Life Sodium Metal Anode.

    Science.gov (United States)

    Zhao, Yang; Goncharova, Lyudmila V; Zhang, Qian; Kaghazchi, Payam; Sun, Qian; Lushington, Andrew; Wang, Biqiong; Li, Ruying; Sun, Xueliang

    2017-09-13

    Metallic Na anode is considered as a promising alternative candidate for Na ion batteries (NIBs) and Na metal batteries (NMBs) due to its high specific capacity, and low potential. However, the unstable solid electrolyte interphase layer caused by serious corrosion and reaction in electrolyte will lead to big challenges, including dendrite growth, low Coulombic efficiency and even safety issues. In this paper, we first demonstrate the inorganic-organic coating via advanced molecular layer deposition (alucone) as a protective layer for metallic Na anode. By protecting Na anode with controllable alucone layer, the dendrites and mossy Na formation have been effectively suppressed and the lifetime has been significantly improved. Moreover, the molecular layer deposition alucone coating shows better performances than the atomic layer deposition Al 2 O 3 coating. The novel design of molecular layer deposition protected Na metal anode may bring in new opportunities to the realization of the next-generation high energy-density NIBs and NMBs.

  16. Thermal stability of atomic layer deposited WCxNy electrodes for metal oxide semiconductor devices

    Science.gov (United States)

    Zonensain, Oren; Fadida, Sivan; Fisher, Ilanit; Gao, Juwen; Danek, Michal; Eizenberg, Moshe

    2018-01-01

    This study is a thorough investigation of the chemical, structural, and electrical stability of W based organo-metallic films, grown by atomic layer deposition, for future use as gate electrodes in advanced metal oxide semiconductor structures. In an earlier work, we have shown that high effective work-function (4.7 eV) was produced by nitrogen enriched films (WCxNy) dominated by W-N chemical bonding, and low effective work-function (4.2 eV) was produced by hydrogen plasma resulting in WCx films dominated by W-C chemical bonding. In the current work, we observe, using x-ray diffraction analysis, phase transformation of the tungsten carbide and tungsten nitride phases after 900 °C annealing to the cubic tungsten phase. Nitrogen diffusion is also observed and is analyzed with time-of-flight secondary ion mass spectroscopy. After this 900 °C anneal, WCxNy effective work function tunability is lost and effective work-function values of 4.7-4.8 eV are measured, similar to stable effective work function values measured for PVD TiN up to 900 °C anneal. All the observed changes after annealing are discussed and correlated to the observed change in the effective work function.

  17. ABOUT THE WAYS OF THE SYSTEM ANALYSIS OF METAL MOVEMENT IN GATING SYSTEMS BASED ON THE NUMERICAL SOLUTIONS OF NAVIER-STOKES EQUATIONS

    Directory of Open Access Journals (Sweden)

    S. G. Lizouzov

    2014-01-01

    Full Text Available Numerical modeling of distribution of the fields of speeds projections on axes X, Y, Z in gating system with the casting “Case of conical pair” for various temporal values is carried out. Numerical criteria for assessment of metal movement through the feeders having various spatial location relative to the gating system are offered. Dynamics of change of the offered criteria on the basis of integral average value of the speed component on axes X, Y, Z in the gating systems at the outlet from feeder is calculated.

  18. Fabrication of metal organic framework materials using a layer-by-layer spin coating approach

    KAUST Repository

    Eddaoudi, Mohamed; Shekhah, Osama

    2016-01-01

    Embodiments describe a method of depositing an MOF, including depositing a metal solution onto a substrate, spinning the substrate sufficient to spread the metal solution, depositing an organic ligand solution onto the substrate and spinning the substrate sufficient to spread the organic ligand solution and form a MOF layer.

  19. Fabrication of metal organic framework materials using a layer-by-layer spin coating approach

    KAUST Repository

    Eddaoudi, Mohamed

    2016-03-17

    Embodiments describe a method of depositing an MOF, including depositing a metal solution onto a substrate, spinning the substrate sufficient to spread the metal solution, depositing an organic ligand solution onto the substrate and spinning the substrate sufficient to spread the organic ligand solution and form a MOF layer.

  20. Ion exchange of alkaline metals on the thin-layer zinc ferrocyanide

    International Nuclear Information System (INIS)

    Betenekov, N.D.; Buklanov, G.V.; Ipatova, E.G.; Korotkin, Yu.S.

    1991-01-01

    Basic regularities of interphase distribution in the system of thin-layer sorbent on the basis of mixed zinc ferrocyanide (FZ)-alkaline metal solution (Na, K, Rb, Cs, Fr) in the column chromatography made are studied. It is established that interphase distribution of microgram amounts of alkaline metals in the systems thin-layer FZ-NH 4 NO 3 electrolyte solutions is of ion-exchange character and subjected to of law effective mass. It is shown that FZ thin-layer material is applicable for effective chromatographic separation of alkaline metal trace amounts. An approach to the choice of a conditions of separate elution of Na, K, Rb, Cs, Fr in the column chromatography mode

  1. Nonvolatile memory characteristics in metal-oxide-semiconductors containing metal nanoparticles fabricated by using a unique laser irradiation method

    International Nuclear Information System (INIS)

    Yang, JungYup; Yoon, KapSoo; Kim, JuHyung; Choi, WonJun; Do, YoungHo; Kim, ChaeOk; Hong, JinPyo

    2006-01-01

    Metal-oxide-semiconductor (MOS) capacitors with metal nanoparticles (Co NP) were successfully fabricated by utilizing an external laser exposure technique for application of non-volatile memories. Images of high-resolution transmission electron microscopy reveal that the spherically shaped Co NP are clearly embedded in the gate oxide layer. Capacitance-voltage measurements exhibit typical charging and discharging effects with a large flat-band shift. The effects of the tunnel oxide thickness and the different tunnel materials are analyzed using capacitance-voltage and retention characteristics. In addition, the memory characteristics of the NP embedded in a high-permittivity material are investigated because the thickness of conventionally available SiO 2 gates is approaching the quantum tunneling limit as devices are scaled down. Finally, the suitability of NP memory devices for nonvolatile memory applications is also discussed. The present results suggest that our unique laser exposure technique holds promise for the NP formation as floating gate elements in nonvolatile NP memories and that the quality of the tunnel oxide is very important for enhancing the retention properties of nonvolatile memory.

  2. Ductility prediction of substrate-supported metal layers based on rate-independent crystal plasticity theory

    Directory of Open Access Journals (Sweden)

    Akpama Holanyo K.

    2016-01-01

    Full Text Available In this paper, both the bifurcation theory and the initial imperfection approach are used to predict localized necking in substrate-supported metal layers. The self-consistent scale-transition scheme is used to derive the mechanical behavior of a representative volume element of the metal layer from the behavior of its microscopic constituents (the single crystals. The mechanical behavior of the elastomer substrate follows the neo-Hookean hyperelastic model. The adherence between the two layers is assumed to be perfect. Through numerical results, it is shown that the limit strains predicted by the initial imperfection approach tend towards the bifurcation predictions when the size of the geometric imperfection in the metal layer vanishes. Also, it is shown that the addition of an elastomer layer to a metal layer enhances ductility.

  3. Medium band gap polymer based solution-processed high-κ composite gate dielectrics for ambipolar OFET

    Science.gov (United States)

    Canımkurbey, Betül; Unay, Hande; Çakırlar, Çiğdem; Büyükköse, Serkan; Çırpan, Ali; Berber, Savas; Altürk Parlak, Elif

    2018-03-01

    The authors present a novel ambipolar organic filed-effect transistors (OFETs) composed of a hybrid dielectric thin film of Ta2O5:PMMA nanocomposite material, and solution processed poly(selenophene, benzotriazole and dialkoxy substituted [1,2-b:4, 5-b‧] dithiophene (P-SBTBDT)-based organic semiconducting material as the active layer of the device. We find that the Ta2O5:PMMA insulator shows n-type conduction character, and its combination with the p-type P-SBTBDT organic semiconductor leads to an ambipolar OFET device. Top-gated OFETs were fabricated on glass substrate consisting of interdigitated ITO electrodes. P-SBTBDT-based material was spin coated on the interdigitated ITO electrodes. Subsequently, a solution processed Ta2O5:PMMA nanocomposite material was spin coated, thereby creating the gate dielectric layer. Finally, as a gate metal, an aluminum layer was deposited by thermal evaporation. The fabricated OFETs exhibited an ambipolar performance with good air-stability, high field-induced current and relatively high electron and hole mobilities although Ta2O5:PMMA nanocomposite films have slightly higher leakage current compared to the pure Ta2O5 films. Dielectric properties of the devices with different ratios of Ta2O5:PMMA were also investigated. The dielectric constant varied between 3.6 and 5.3 at 100 Hz, depending on the Ta2O5:PMMA ratio.

  4. An analytical threshold voltage model for a short-channel dual-metal-gate (DMG) recessed-source/drain (Re-S/D) SOI MOSFET

    Science.gov (United States)

    Saramekala, G. K.; Santra, Abirmoya; Dubey, Sarvesh; Jit, Satyabrata; Tiwari, Pramod Kumar

    2013-08-01

    In this paper, an analytical short-channel threshold voltage model is presented for a dual-metal-gate (DMG) fully depleted recessed source/drain (Re-S/D) SOI MOSFET. For the first time, the advantages of recessed source/drain (Re-S/D) and of dual-metal-gate structure are incorporated simultaneously in a fully depleted SOI MOSFET. The analytical surface potential model at Si-channel/SiO2 interface and Si-channel/buried-oxide (BOX) interface have been developed by solving the 2-D Poisson’s equation in the channel region with appropriate boundary conditions assuming parabolic potential profile in the transverse direction of the channel. Thereupon, a threshold voltage model is derived from the minimum surface potential in the channel. The developed model is analyzed extensively for a variety of device parameters like the oxide and silicon channel thicknesses, thickness of source/drain extension in the BOX, control and screen gate length ratio. The validity of the present 2D analytical model is verified with ATLAS™, a 2D device simulator from SILVACO Inc.

  5. High permittivity materials for oxide gate stack in Ge-based metal oxide semiconductor capacitors

    Energy Technology Data Exchange (ETDEWEB)

    Molle, Alessandro, E-mail: alessandro.molle@mdm.infm.i [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Baldovino, Silvia [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano Bicocca, Milano (Italy); Spiga, Sabina [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Fanciulli, Marco [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano Bicocca, Milano (Italy)

    2010-01-01

    In the effort to ultimately shrink the size of logic devices towards a post-Si era, the integration of Ge as alternative channel material for high-speed p-MOSFET devices and the concomitant coupling with high permittivity dielectrics (high-k) as gate oxides is currently a key-challenge in microelectronics. However, the Ge option still suffers from a number of unresolved drawbacks and open issues mainly related to the thermodynamic and electrical compatibility of Ge substrates with high-k gate stack. Strictly speaking, two main concerns can be emphasized. On one side is the dilemma on which chemical/physical passivation is more suitable to minimize the unavoidable presence of electrically active defects at the oxide/semiconductor interface. On the other side, overcoming the SiO{sub 2} gate stack opens the route to a number of potentially outperforming high-k oxides. Two deposition approaches were here separately adopted to investigate the high-k oxide growth on Ge substrates, the molecular beam deposition (MBD) of Gd{sub 2}O{sub 3} and the atomic layer deposition (ALD) of HfO{sub 2}. In the MBD framework epitaxial and amorphous Gd{sub 2}O{sub 3} films were grown onto GeO{sub 2}-passivated Ge substrates. In this case, Ge passivation was achieved by exploiting the Ge{sup 4+} bonding state in GeO{sub 2} ultra-thin interface layers intentionally deposited in between Ge and the high-k oxide by means of atomic oxygen exposure to Ge. The composition of the interface layer has been characterized as a function of the oxidation temperature and evidence of Ge dangling bonds at the GeO{sub 2}/Ge interface has been reported. Finally, the electrical response of MOS capacitors incorporating Gd{sub 2}O{sub 3} and GeO{sub 2}-passivated Ge substrates has been checked by capacitance-voltage measurements. On the other hand, the structural and electrical properties of HfO{sub 2} films grown by ALD on Ge by using different oxygen precursors, i.e. H{sub 2}O, Hf(O{sup t}Bu){sub 2}(mmp

  6. Optical properties of metallic multi-layer films

    International Nuclear Information System (INIS)

    Dimmich, R.

    1991-09-01

    Optical properties of multi-layer films consisting of alternating layers of two different metals are studied on the basis of the Maxwell equations and the Boltzmann transport theory. The influence of free-electron scattering at the film external surface and at the interfaces is taken into account and considered as a function of the electromagnetic field frequency and the structure modulation wavelength. Derived formulas for optical coefficients are valid at low frequencies, where the skin effect is nearly classical, as well as in the near-infrared, visible and ultraviolet spectral ranges, where the skin effect has the anomalous nature. It is shown that the obtained results are apparently dependent on the values of the scattering parameters. What is more, the oscillatory nature of analyzed spectra is observed, where the two oscillation periods may appear on certain conditions. The oscillations result from the electron surface and interface scattering and their amplitudes and periods depend on the boundary conditions for free-electron scattering. Finally, the application of the interference phenomenon in dielectric layers is proposed to obtain the enhancement of the non distinct details which can appear in optical spectra of metallic films. (author). 31 refs, 6 figs

  7. Influence of gate dielectric on the ambipolar characteristics of solution-processed organic field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Ribierre, J C; Ghosh, S; Takaishi, K; Muto, T; Aoyama, T, E-mail: jcribierre@ewha.ac.kr, E-mail: taoyama@riken.jp [Advanced Science Institute, RIKEN, 2-1 Hirosawa, Wako, Saitama 351-0198 (Japan)

    2011-05-25

    Solution-processed ambipolar organic field-effect transistors based on dicyanomethylene-substituted quinoidal quaterthiophene derivative [QQT(CN)4] are fabricated using various gate dielectric materials including cross-linked polyimide and poly-4-vinylphenol. Devices with spin-coated polymeric gate dielectric layers show a reduced hysteresis in their transfer characteristics. Among the insulating polymers examined in this study, a new fluorinated polymer with a low dielectric constant of 2.8 significantly improves both hole and electron field-effect mobilities of QQT(CN)4 thin films to values as high as 0.04 and 0.002 cm{sup 2} V{sup -1} s{sup -1}. These values are close to the best mobilities obtained in QQT(CN)4 devices fabricated on SiO{sub 2} treated with octadecyltrichlorosilane. The influence of the metal used for source/drain metal electrodes on the device performance is also investigated. Whereas best device performances are achieved with gold electrodes, more balanced electron and hole field-effect mobilities could be obtained using chromium.

  8. Leakage current suppression with a combination of planarized gate and overlap/off-set structure in metal-induced laterally crystallized polycrystalline-silicon thin-film transistors

    Science.gov (United States)

    Chae, Hee Jae; Seok, Ki Hwan; Lee, Sol Kyu; Joo, Seung Ki

    2018-04-01

    A novel inverted staggered metal-induced laterally crystallized (MILC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with a combination of a planarized gate and an overlap/off-set at the source-gate/drain-gate structure were fabricated and characterized. While the MILC process is advantageous for fabricating inverted staggered poly-Si TFTs, MILC TFTs reveal higher leakage current than TFTs crystallized by other processes due to their high trap density of Ni contamination. Due to this drawback, the planarized gate and overlap/off-set structure were applied to inverted staggered MILC TFTs. The proposed device shows drastic suppression of leakage current and pinning phenomenon by reducing the lateral electric field and the space-charge limited current from the gate to the drain.

  9. Influence of implantation energy on the electrical properties of ultrathin gate oxides grown on nitrogen implanted Si substrates

    International Nuclear Information System (INIS)

    Kapetanakis, E.; Skarlatos, D.; Tsamis, C.; Normand, P.; Tsoukalas, D.

    2003-01-01

    Metal-oxide-semiconductor tunnel diodes with gate oxides, in the range of 2.5-3.5 nm, grown either on 25 or 3 keV nitrogen-implanted Si substrates at (0.3 or 1) x10 15 cm -2 dose, respectively, are investigated. The dependence of N 2 + ion implant energy on the electrical quality of the growing oxide layers is studied through capacitance, equivalent parallel conductance, and gate current measurements. Superior electrical characteristics in terms of interface state trap density, leakage current, and breakdown fields are found for oxides obtained through 3 keV nitrogen implants. These findings together with the full absence of any extended defect in the silicon substrate make the low-energy nitrogen implantation technique an attractive option for reproducible low-cost growth of nanometer-thick gate oxides

  10. Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

    KAUST Repository

    Rojas, Jhonathan Prieto

    2013-02-12

    In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry\\'s most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

  11. Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

    KAUST Repository

    Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa; Sevilla, Galo T.

    2013-01-01

    In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry's most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

  12. Poly(4-vinylphenol) gate insulator with cross-linking using a rapid low-power microwave induction heating scheme for organic thin-film-transistors

    Science.gov (United States)

    Fan, Ching-Lin; Shang, Ming-Chi; Hsia, Mao-Yuan; Wang, Shea-Jue; Huang, Bohr-Ran; Lee, Win-Der

    2016-03-01

    A Microwave-Induction Heating (MIH) scheme is proposed for the poly(4-vinylphenol) (PVP) gate insulator cross-linking process to replace the traditional oven heating cross-linking process. The cross-linking time is significantly decreased from 1 h to 5 min by heating the metal below the PVP layer using microwave irradiation. The necessary microwave power was substantially reduced to about 50 W by decreasing the chamber pressure. The MIH scheme is a good candidate to replace traditional thermal heating for cross-linking of PVP as the gate insulator for organic thin-film-transistors.

  13. Single-Layer Limit of Metallic Indium Overlayers on Si(111).

    Science.gov (United States)

    Park, Jae Whan; Kang, Myung Ho

    2016-09-09

    Density-functional calculations are used to identify one-atom-thick metallic In phases grown on the Si(111) surface, which have long been sought in quest of the ultimate two-dimensional (2D) limit of metallic properties. We predict two metastable single-layer In phases, one sqrt[7]×sqrt[3] phase with a coverage of 1.4 monolayer (ML; here 1 ML refers to one In atom per top Si atom) and the other sqrt[7]×sqrt[7] phase with 1.43 ML, which indeed agree with experimental evidences. Both phases reveal quasi-1D arrangements of protruded In atoms, leading to 2D-metallic but anisotropic band structures and Fermi surfaces. This directional feature contrasts with the free-electron-like In-overlayer properties that are known to persist up to the double-layer thickness, implying that the ultimate 2D limit of In overlayers may have been achieved in previous studies of double-layer In phases.

  14. Low-power logic computing realized in a single electric-double-layer MoS2 transistor gated with polymer electrolyte

    Science.gov (United States)

    Guo, Junjie; Xie, Dingdong; Yang, Bingchu; Jiang, Jie

    2018-06-01

    Due to its mechanical flexibility, large bandgap and carrier mobility, atomically thin molybdenum disulphide (MoS2) has attracted widespread attention. However, it still lacks a facile route to fabricate a low-power high-performance logic gates/circuits before it gets the real application. Herein, we reported a facile and environment-friendly method to establish the low-power logic function in a single MoS2 field-effect transistor (FET) configuration gated with a polymer electrolyte. Such low-power and high-performance MoS2 FET can be implemented by using water-soluble polyvinyl alcohol (PVA) polymer as proton-conducting electric-double-layer (EDL) dielectric layer. It exhibited an ultra-low voltage (1.5 V) and a good performance with a high current on/off ratio (Ion/off) of 1 × 105, a large electron mobility (μ) of 47.5 cm2/V s, and a small subthreshold swing (S) of 0.26 V/dec, respectively. The inverter can be realized by using such a single MoS2 EDL FET with a gain of ∼4 at the operation voltage of only ∼1 V. Most importantly, the neuronal AND logic computing can be also demonstrated by using such a double-lateral-gate single MoS2 EDL transistor. These results show an effective step for future applications of 2D MoS2 FETs for integrated electronic engineering and low-energy environment-friendly green electronics.

  15. Influence of metal induced crystallization parameters on the performance of polycrystalline silicon thin film transistors

    International Nuclear Information System (INIS)

    Pereira, L.; Barquinha, P.; Fortunato, E.; Martins, R.

    2005-01-01

    In this work, metal induced crystallization using nickel was employed to obtain polycrystalline silicon by crystallization of amorphous films for thin film transistor applications. The devices were produced through only one lithographic process with a bottom gate configuration using a new gate dielectric consisting of a multi-layer of aluminum oxide/titanium oxide produced by atomic layer deposition. The best results were obtained for TFTs with the active layer of poly-Si crystallized for 20 h at 500 deg. C using a nickel layer of 0.5 nm where the effective mobility is 45.5 cm 2 V -1 s -1 . The threshold voltage, the on/off current ratio and the sub-threshold voltage are, respectively, 11.9 V, 5.55x10 4 and 2.49 V/dec

  16. Strain rate effects on localized necking in substrate-supported metal layers

    OpenAIRE

    BEN BETTAIEB, Mohamed; ABED-MERAIM, Farid

    2017-01-01

    Due to their good mechanical and technological performances, thin substrate-supported metal layers are increasingly used as functional components in flexible electronic devices. Consequently, the prediction of necking, and the associated limit strains, for such components is of major academic and industrial importance. The current contribution aims to numerically investigate the respective and combined effects of strain rate sensitivity of the metal layer and the addition of an elastomer l...

  17. Asymmetric polymeric membranes containing a metal-rich dense layer with a controlled thickness and method of making same

    KAUST Repository

    Peinemann, Klaus-Viktor; Villalobos, Vazquez De La Parra Luis Francisco

    2016-01-01

    A structure, and methods of making the structure are provided in which the structure can include: a membrane having a first layer and a second layer, the first layer comprising polymer chains formed with coordination complexes with metal ions, and the second layer consisting of a porous support layer formed of polymer chains substantially, if not completely, lacking the presence of metal ions. The structure can be an asymmetric polymeric membrane containing a metal-rich layer as the first layer. In various embodiments the first layer can be a metal-rich dense layer. The first layer can include pores. The polymer chains of the first layer can be closely packed. The second layer can include a plurality of macro voids and can have an absence of the metal ions of the first layer.

  18. Asymmetric polymeric membranes containing a metal-rich dense layer with a controlled thickness and method of making same

    KAUST Repository

    Peinemann, Klaus-Viktor

    2016-01-21

    A structure, and methods of making the structure are provided in which the structure can include: a membrane having a first layer and a second layer, the first layer comprising polymer chains formed with coordination complexes with metal ions, and the second layer consisting of a porous support layer formed of polymer chains substantially, if not completely, lacking the presence of metal ions. The structure can be an asymmetric polymeric membrane containing a metal-rich layer as the first layer. In various embodiments the first layer can be a metal-rich dense layer. The first layer can include pores. The polymer chains of the first layer can be closely packed. The second layer can include a plurality of macro voids and can have an absence of the metal ions of the first layer.

  19. Metallization of ion beam synthesized Si/3C-SiC/Si layer systems by high-dose implantation of transition metal ions

    International Nuclear Information System (INIS)

    Lindner, J.K.N.; Wenzel, S.; Stritzker, B.

    2001-01-01

    The formation of metal silicide layers contacting an ion beam synthesized buried 3C-SiC layer in silicon by means of high-dose titanium and molybdenum implantations is reported. Two different strategies to form such contact layers are explored. The titanium implantation aims to convert the Si top layer of an epitaxial Si/SiC/Si layer sequence into TiSi 2 , while Mo implantations were performed directly into the SiC layer after selectively etching off all capping layers. Textured and high-temperature stable C54-TiSi 2 layers with small additions of more metal-rich silicides are obtained in the case of the Ti implantations. Mo implantations result in the formation of the high-temperature phase β-MoSi 2 , which also grows textured on the substrate. The formation of cavities in the silicon substrate at the lower SiC/Si interface due to the Si consumption by the growing silicide phase is observed in both cases. It probably constitutes a problem, occurring whenever thin SiC films on silicon have to be contacted by silicide forming metals independent of the deposition technique used. It is shown that this problem can be solved with ion beam synthesized contact layers by proper adjustment of the metal ion dose

  20. Comparative study of the synthesis of layered transition metal molybdates

    International Nuclear Information System (INIS)

    Mitchell, S.; Gomez-Aviles, A.; Gardner, C.; Jones, W.

    2010-01-01

    Mixed metal oxides (MMOs) prepared by the mild thermal decomposition of layered double hydroxides (LDHs) differ in their reactivity on exposure to aqueous molybdate containing solutions. In this study, we investigate the reactivity of some T-Al containing MMOs (T=Co, Ni, Cu or Zn) towards the formation of layered transition metal molybdates (LTMs) possessing the general formula AT 2 (OH)(MoO 4 ) 2 .H 2 O, where A=NH 4 + , Na + or K + . The phase selectivity of the reaction was studied with respect to the source of molybdate, the ratio of T to Mo and the reaction pH. LTMs were obtained on reaction of Cu-Al and Zn-Al containing MMOs with aqueous solutions of ammonium heptamolybdate. Rehydration of these oxides in the presence of sodium or potassium molybdate yielded a rehydrated LDH phase as the only crystalline product. The LTM products obtained by the rehydration of MMO precursors were compared with LTMs prepared by direct precipitation from the metal salts in order to study the influence of preparative route on their chemical and physical properties. Differences were noted in the composition, morphology and thermal properties of the resulting products. - Graphical abstract: Mixed metal oxides (MMOs) derived from layered double hydroxide precursors differ in their reactivity on exposure to aqueous molybdate containing solutions. We investigate the influence of the molybdate source, the rehydration pH and the ratio of T/Mo on the reactivity of some T-Al containing MMOs (T=Co, Ni, Cu or Zn) towards the formation of layered transition metal molybdates of general formula AT 2 (OH)(MoO 4 ) 2 .H 2 O (where A + =NH 4 + , K + or Na + ).

  1. Application of the photomodulated reflectance technique to the monitoring of metal layers

    Energy Technology Data Exchange (ETDEWEB)

    Dobos, Gabor; Lenk, Sandor; Ujhelyi, Ferenc; Szita, Zsofia; Kocsanyi, Laszlo [Department of Atomic Physics, Budapest University of Technology and Economics, Budafoki ut 8, 1111 Budapest (Hungary); Somogyi, Andras [Semilab Corporation, Prielle Kornelia ut 2, 1117 Budapest (Hungary)

    2011-09-15

    Photomodulated reflectance (PMR) measurement techniques are currently used for the monitoring of ultra-shallow junctions. This paper discusses the possibility of applying them to the characterisation of metal layers. A finite element method based computer model has been created to study the dependence of the PMR signal on different sample parameters. We present the results of these simulations and show that the method can be used to establish the thickness of a metal layer (if the material is known) and it can also provide information about the metal/semiconductor interface. This information might be used to characterise the barrier seed layer beneath the metal, by a non-contact and non-destructive way. Simulation results are also supported by actual measurements on test samples. (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  2. Volatile and Nonvolatile Characteristics of Asymmetric Dual-Gate Thyristor RAM with Vertical Structure.

    Science.gov (United States)

    Kim, Hyun-Min; Kwon, Dae Woong; Kim, Sihyun; Lee, Kitae; Lee, Junil; Park, Euyhwan; Lee, Ryoongbin; Kim, Hyungjin; Kim, Sangwan; Park, Byung-Gook

    2018-09-01

    In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (107) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.

  3. Direct Structural Identification of Gas Induced Gate-Opening Coupled with Commensurate Adsorption in a Microporous Metal-Organic Framework.

    Science.gov (United States)

    Banerjee, Debasis; Wang, Hao; Plonka, Anna M; Emge, Thomas J; Parise, John B; Li, Jing

    2016-08-08

    Gate-opening is a unique and interesting phenomenon commonly observed in flexible porous frameworks, where the pore characteristics and/or crystal structures change in response to external stimuli such as adding or removing guest molecules. For gate-opening that is induced by gas adsorption, the pore-opening pressure often varies for different adsorbate molecules and, thus, can be applied to selectively separate a gas mixture. The detailed understanding of this phenomenon is of fundamental importance to the design of industrially applicable gas-selective sorbents, which remains under investigated due to the lack of direct structural evidence for such systems. We report a mechanistic study of gas-induced gate-opening process of a microporous metal-organic framework, [Mn(ina)2 ] (ina=isonicotinate) associated with commensurate adsorption, by a combination of several analytical techniques including single crystal X-ray diffraction, in situ powder X-ray diffraction coupled with differential scanning calorimetry (XRD-DSC), and gas adsorption-desorption methods. Our study reveals that the pronounced and reversible gate opening/closing phenomena observed in [Mn(ina)2 ] are coupled with a structural transition that involves rotation of the organic linker molecules as a result of interaction of the framework with adsorbed gas molecules including carbon dioxide and propane. The onset pressure to open the gate correlates with the extent of such interaction. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  4. Solution processed metal oxide thin film hole transport layers for high performance organic solar cells

    Science.gov (United States)

    Steirer, K. Xerxes; Berry, Joseph J.; Chesin, Jordan P.; Lloyd, Matthew T.; Widjonarko, Nicodemus Edwin; Miedaner, Alexander; Curtis, Calvin J.; Ginley, David S.; Olson, Dana C.

    2017-01-10

    A method for the application of solution processed metal oxide hole transport layers in organic photovoltaic devices and related organic electronics devices is disclosed. The metal oxide may be derived from a metal-organic precursor enabling solution processing of an amorphous, p-type metal oxide. An organic photovoltaic device having solution processed, metal oxide, thin-film hole transport layer.

  5. Alleviation of fermi-level pinning effect at metal/germanium interface by the insertion of graphene layers

    International Nuclear Information System (INIS)

    Baek, Seung-heon Chris; Seo, Yu-Jin; Oh, Joong Gun; Albert Park, Min Gyu; Bong, Jae Hoon; Yoon, Seong Jun; Lee, Seok-Hee; Seo, Minsu; Park, Seung-young; Park, Byong-Guk

    2014-01-01

    In this paper, we report the alleviation of the Fermi-level pinning on metal/n-germanium (Ge) contact by the insertion of multiple layers of single-layer graphene (SLG) at the metal/n-Ge interface. A decrease in the Schottky barrier height with an increase in the number of inserted SLG layers was observed, which supports the contention that Fermi-level pinning at metal/n-Ge contact originates from the metal-induced gap states at the metal/n-Ge interface. The modulation of Schottky barrier height by varying the number of inserted SLG layers (m) can bring about the use of Ge as the next-generation complementary metal-oxide-semiconductor material. Furthermore, the inserted SLG layers can be used as the tunnel barrier for spin injection into Ge substrate for spin-based transistors.

  6. Formation of strain-induced quantum dots in gated semiconductor nanostructures

    Directory of Open Access Journals (Sweden)

    Ted Thorbeck

    2015-08-01

    Full Text Available A long-standing mystery in the field of semiconductor quantum dots (QDs is: Why are there so many unintentional dots (also known as disorder dots which are neither expected nor controllable. It is typically assumed that these unintentional dots are due to charged defects, however the frequency and predictability of the location of the unintentional QDs suggests there might be additional mechanisms causing the unintentional QDs besides charged defects. We show that the typical strains in a semiconductor nanostructure from metal gates are large enough to create strain-induced quantum dots. We simulate a commonly used QD device architecture, metal gates on bulk silicon, and show the formation of strain-induced QDs. The strain-induced QD can be eliminated by replacing the metal gates with poly-silicon gates. Thus strain can be as important as electrostatics to QD device operation operation.

  7. Melt layer behavior of metal targets irradiatead by powerful plasma streams

    International Nuclear Information System (INIS)

    Bandura, A.N.; Byrka, O.V.; Chebotarev, V.V.; Garkusha, I.E.; Makhlaj, V.A.; Solyakov, D.G.; Tereshin, V.I.; Wuerz, H.

    2002-01-01

    In this paper melt layer erosion of metal targets under pulsed high-heat loads is studied. Experiments with steel, copper, aluminum and titanium samples were carried out in two plasma accelerator devices with different time durations of the heat load. The surfaces of the resolidified melt layers show a considerable roughness with microcraters and ridge like relief on the surface. For each material the mass loss was determined. Melt layer erosion by melt motion was clearly identified. However it is masked by boiling, bubble expansion and bubble collapse and by formation of a Kelvin-Helmholtz instability. The experimental results can be used for validation of numerical codes which model melt layer erosion of metallic armour materials in off-normal events, in tokamaks

  8. Melt layer behavior of metal targets irradiatead by powerful plasma streams

    Energy Technology Data Exchange (ETDEWEB)

    Bandura, A.N.; Byrka, O.V.; Chebotarev, V.V.; Garkusha, I.E. E-mail: garkusha@ipp.kharkov.ua; Makhlaj, V.A.; Solyakov, D.G.; Tereshin, V.I.; Wuerz, H

    2002-12-01

    In this paper melt layer erosion of metal targets under pulsed high-heat loads is studied. Experiments with steel, copper, aluminum and titanium samples were carried out in two plasma accelerator devices with different time durations of the heat load. The surfaces of the resolidified melt layers show a considerable roughness with microcraters and ridge like relief on the surface. For each material the mass loss was determined. Melt layer erosion by melt motion was clearly identified. However it is masked by boiling, bubble expansion and bubble collapse and by formation of a Kelvin-Helmholtz instability. The experimental results can be used for validation of numerical codes which model melt layer erosion of metallic armour materials in off-normal events, in tokamaks.

  9. Effect of ZnO channel thickness on the device behaviour of nonvolatile memory thin film transistors with double-layered gate insulators of Al2O3 and ferroelectric polymer

    International Nuclear Information System (INIS)

    Yoon, Sung-Min; Yang, Shin-Hyuk; Ko Park, Sang-Hee; Jung, Soon-Won; Cho, Doo-Hee; Byun, Chun-Won; Kang, Seung-Youl; Hwang, Chi-Sun; Yu, Byoung-Gon

    2009-01-01

    Poly(vinylidene fluoride trifluoroethylene) and ZnO were employed for nonvolatile memory thin film transistors as ferroelectric gate insulator and oxide semiconducting channel layers, respectively. It was proposed that the thickness of the ZnO layer be carefully controlled for realizing the lower programming voltage, because the serially connected capacitor by the formation of a fully depleted ZnO channel had a critical effect on the off programming voltage. The fabricated memory transistor with Al/P(VDF-TrFE) (80 nm)/Al 2 O 3 (4 nm)/ZnO (5 nm) exhibits encouraging behaviour such as a memory window of 3.8 V at the gate voltage of -10 to 12 V, and 10 7 on/off ratio, and a gate leakage current of 10 -11 A.

  10. Diverse and tunable electronic structures of single-layer metal phosphorus trichalcogenides for photocatalytic water splitting

    International Nuclear Information System (INIS)

    Liu, Jian; Li, Xi-Bo; Wang, Da; Liu, Li-Min; Lau, Woon-Ming; Peng, Ping

    2014-01-01

    The family of bulk metal phosphorus trichalcogenides (APX 3 , A = M II , M 0.5 I M 0.5 III ; X = S, Se; M I , M II , and M III represent Group-I, Group-II, and Group-III metals, respectively) has attracted great attentions because such materials not only own magnetic and ferroelectric properties, but also exhibit excellent properties in hydrogen storage and lithium battery because of the layered structures. Many layered materials have been exfoliated into two-dimensional (2D) materials, and they show distinct electronic properties compared with their bulks. Here we present a systematical study of single-layer metal phosphorus trichalcogenides by density functional theory calculations. The results show that the single layer metal phosphorus trichalcogenides have very low formation energies, which indicates that the exfoliation of single layer APX 3 should not be difficult. The family of single layer metal phosphorus trichalcogenides exhibits a large range of band gaps from 1.77 to 3.94 eV, and the electronic structures are greatly affected by the metal or the chalcogenide atoms. The calculated band edges of metal phosphorus trichalcogenides further reveal that single-layer ZnPSe 3 , CdPSe 3 , Ag 0.5 Sc 0.5 PSe 3 , and Ag 0.5 In 0.5 PX 3 (X = S and Se) have both suitable band gaps for visible-light driving and sufficient over-potentials for water splitting. More fascinatingly, single-layer Ag 0.5 Sc 0.5 PSe 3 is a direct band gap semiconductor, and the calculated optical absorption further convinces that such materials own outstanding properties for light absorption. Such results demonstrate that the single layer metal phosphorus trichalcogenides own high stability, versatile electronic properties, and high optical absorption, thus such materials have great chances to be high efficient photocatalysts for water-splitting

  11. Investigation of Ultraviolet Light Curable Polysilsesquioxane Gate Dielectric Layers for Pentacene Thin Film Transistors.

    Science.gov (United States)

    Shibao, Hideto; Nakahara, Yoshio; Uno, Kazuyuki; Tanaka, Ichiro

    2016-04-01

    Polysilsesquioxane (PSQ) comprising 3-methacryloxypropyl groups was investigated as an ultraviolet (UV)-light curable gate dielectric-material for pentacene thin film transistors (TFTs). The surface of UV-light cured PSQ films was smoother than that of thermally cured ones, and the pentacene layers deposited on the UV-Iight cured PSQ films consisted of larger grains. However, carrier mobility of the TFTs using the UV-light cured PSQ films was lower than that of the TFTs using the thermally cured ones. It was shown that the cross-linker molecules, which were only added to the UV-light cured PSQ films, worked as a major mobility-limiting factor for the TFTs.

  12. Nanogranular SiO{sub 2} proton gated silicon layer transistor mimicking biological synapses

    Energy Technology Data Exchange (ETDEWEB)

    Liu, M. J.; Huang, G. S., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Guo, Q. L.; Tian, Z. A.; Li, G. J.; Mei, Y. F. [Department of Materials Science, Fudan University, Shanghai 200433 (China); Feng, P., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Shao, F.; Wan, Q. [School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)

    2016-06-20

    Silicon on insulator (SOI)-based transistors gated by nanogranular SiO{sub 2} proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

  13. Considerably improved photovoltaic performance of carbon nanotube-based solar cells using metal oxide layers

    Science.gov (United States)

    Wang, Feijiu; Kozawa, Daichi; Miyauchi, Yuhei; Hiraoka, Kazushi; Mouri, Shinichiro; Ohno, Yutaka; Matsuda, Kazunari

    2015-02-01

    Carbon nanotube-based solar cells have been extensively studied from the perspective of potential application. Here we demonstrated a significant improvement of the carbon nanotube solar cells by the use of metal oxide layers for efficient carrier transport. The metal oxides also serve as an antireflection layer and an efficient carrier dopant, leading to a reduction in the loss of the incident solar light and an increase in the photocurrent, respectively. As a consequence, the photovoltaic performance of both p-single-walled carbon nanotube (SWNT)/n-Si and n-SWNT/p-Si heterojunction solar cells using MoOx and ZnO layers is improved, resulting in very high photovoltaic conversion efficiencies of 17.0 and 4.0%, respectively. These findings regarding the use of metal oxides as multifunctional layers suggest that metal oxide layers could improve the performance of various electronic devices based on carbon nanotubes.

  14. Considerably improved photovoltaic performance of carbon nanotube-based solar cells using metal oxide layers.

    Science.gov (United States)

    Wang, Feijiu; Kozawa, Daichi; Miyauchi, Yuhei; Hiraoka, Kazushi; Mouri, Shinichiro; Ohno, Yutaka; Matsuda, Kazunari

    2015-02-18

    Carbon nanotube-based solar cells have been extensively studied from the perspective of potential application. Here we demonstrated a significant improvement of the carbon nanotube solar cells by the use of metal oxide layers for efficient carrier transport. The metal oxides also serve as an antireflection layer and an efficient carrier dopant, leading to a reduction in the loss of the incident solar light and an increase in the photocurrent, respectively. As a consequence, the photovoltaic performance of both p-single-walled carbon nanotube (SWNT)/n-Si and n-SWNT/p-Si heterojunction solar cells using MoOx and ZnO layers is improved, resulting in very high photovoltaic conversion efficiencies of 17.0 and 4.0%, respectively. These findings regarding the use of metal oxides as multifunctional layers suggest that metal oxide layers could improve the performance of various electronic devices based on carbon nanotubes.

  15. Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

    Science.gov (United States)

    Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

    2015-12-01

    A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

  16. Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

    Science.gov (United States)

    Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

    2015-12-17

    A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

  17. Optical transparency of graphene layers grown on metal surfaces

    International Nuclear Information System (INIS)

    Rut’kov, E. V.; Lavrovskaya, N. P.; Sheshenya, E. S.; Gall, N. R.

    2017-01-01

    It is shown that, in contradiction with the fundamental results obtained for free graphene, graphene films grown on the Rh(111) surface to thicknesses from one to ~(12–15) single layers do not absorb visible electromagnetic radiation emitted from the surface and influence neither the brightness nor true temperature of the sample. At larger thicknesses, such absorption occurs. This effect is observed for the surfaces of other metals, specifically, Pt(111), Re(1010), and Ni(111) and, thus, can be considered as being universal. It is thought that the effect is due to changes in the electronic properties of thin graphene layers because of electron transfer between graphene and the metal substrate.

  18. Optical transparency of graphene layers grown on metal surfaces

    Energy Technology Data Exchange (ETDEWEB)

    Rut’kov, E. V. [Russian Academy of Sciences, Ioffe Physical–Technical Institute (Russian Federation); Lavrovskaya, N. P. [State University of Aerospace Instrumentation (Russian Federation); Sheshenya, E. S., E-mail: sheshenayket@gmail.ru; Gall, N. R. [Russian Academy of Sciences, Ioffe Physical–Technical Institute (Russian Federation)

    2017-04-15

    It is shown that, in contradiction with the fundamental results obtained for free graphene, graphene films grown on the Rh(111) surface to thicknesses from one to ~(12–15) single layers do not absorb visible electromagnetic radiation emitted from the surface and influence neither the brightness nor true temperature of the sample. At larger thicknesses, such absorption occurs. This effect is observed for the surfaces of other metals, specifically, Pt(111), Re(1010), and Ni(111) and, thus, can be considered as being universal. It is thought that the effect is due to changes in the electronic properties of thin graphene layers because of electron transfer between graphene and the metal substrate.

  19. Solar Cycle Response and Long-Term Trends in the Mesospheric Metal Layers

    Science.gov (United States)

    Dawkins, E. C. M.; Plane, J. M. C.; Chipperfield, M.; Feng, W.; Marsh, D. R.; Hoffner, J.; Janches, D.

    2016-01-01

    The meteoric metal layers (Na, Fe, and K) which form as a result of the ablation of incoming meteors act as unique tracers for chemical and dynamical processes that occur within the upper mesosphere lower thermosphere region. In this work, we examine whether these metal layers are sensitive Fe indicators of decadal long-term changes within the upper atmosphere. Output from a whole-atmosphere climate model is used to assess the response of the Na, K, and Fe layers across a 50 year period (1955-2005). At short timescales, the K layer has previously been shown to exhibit a very different seasonal behavior compared to the other metals. Here we show that this unusual behavior is also exhibited at longer time scales (both the 11 year solar cycle and 50 year periods), where K displays a much more pronounced response to atmospheric temperature changes than either Na or Fe. The contrasting solar cycle behavior of the K and Na layers predicted by the model is confirmed using satellite and lidar observations for the period 2004-2013.

  20. Dual metal gate tunneling field effect transistors based on MOSFETs: A 2-D analytical approach

    Science.gov (United States)

    Ramezani, Zeinab; Orouji, Ali A.

    2018-01-01

    A novel 2-D analytical drain current model of novel Dual Metal Gate Tunnel Field Effect Transistors Based on MOSFETs (DMG-TFET) is presented in this paper. The proposed Tunneling FET is extracted from a MOSFET structure by employing an additional electrode in the source region with an appropriate work function to induce holes in the N+ source region and hence makes it as a P+ source region. The electric field is derived which is utilized to extract the expression of the drain current by analytically integrating the band to band tunneling generation rate in the tunneling region based on the potential profile by solving the Poisson's equation. Through this model, the effects of the thin film thickness and gate voltage on the potential, the electric field, and the effects of the thin film thickness on the tunneling current can be studied. To validate our present model we use SILVACO ATLAS device simulator and the analytical results have been compared with it and found a good agreement.

  1. Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

    Science.gov (United States)

    Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

    2018-01-01

    Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

  2. High-κ gate dielectrics: Current status and materials properties considerations

    Science.gov (United States)

    Wilk, G. D.; Wallace, R. M.; Anthony, J. M.

    2001-05-01

    Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward successful integration into the expected processing conditions for future CMOS technologies, especially due to their tendency to form at interfaces with Si (e.g. silicates). These pseudobinary systems also thereby enable the use of other high-κ materials by serving as an interfacial high-κ layer. While work is ongoing, much research is still required, as it is clear that any material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

  3. Impacts of recessed gate and fluoride-based plasma treatment approaches toward normally-off AlGaN/GaN HEMT.

    Science.gov (United States)

    Heo, Jun-Woo; Kim, Young-Jin; Kim, Hyun-Seok

    2014-12-01

    We report two approaches to fabricating high performance normally-off AIGaN/GaN high-electron mobility transistors (HEMTs). The fabrication techniques employed were based on recessed-metal-insulator-semiconductor (MIS) gate and recessed fluoride-based plasma treatment. They were selectively applied to the area under the gate electrode to deplete the two-dimensional electron gas (2-DEG) density. We found that the recessed gate structure was effective in shifting the threshold voltage by controlling the etching depth of gate region to reduce the AIGaN layer thickness to less than 8 nm. Likewise, the CF4 plasma treatment effectively incorporated negatively charged fluorine ions into the thin AIGaN barrier so that the threshold voltage shifted to higher positive values. In addition to the increased threshold voltage, experimental results showed a maximum drain current and a maximum transconductance of 315 mA/mm and 100 mS/mm, respectively, for the recessed-MIS gate HEMT, and 340 mA/mm and 330 mS/mm, respectively, for the fluoride-based plasma treated HEMT.

  4. Improvement of corrosion resistance of transparent conductive multilayer coating consisting of silver layers and transparent metal oxide layers

    International Nuclear Information System (INIS)

    Koike, Katsuhiko; Yamazaki, Fumiharu; Okamura, Tomoyuki; Fukuda, Shin

    2007-01-01

    An optical filter for plasma display panel (PDP) requires an electromagnetic shield with very high ability. The authors investigated a transparent conductive multilayer coating consisting of silver (Ag) layers and transparent metal oxide layers. The durability of the multilayer sputter coating, including the silver layer, is very sensitive to the surrounding atmosphere. For example, after an exposure test they found discolored points on the multilayer sputter coatings, possibly caused by migration of silver atoms in the silver layers. In their investigation, they modified the top surface of the multilayer sputter coatings with transition metals to improve the corrosion resistance of the multilayer coating. Specifically, they deposited transition metals 0.5-2 nm thick on the top surface of the multilayer coatings by sputtering. They chose indium tin oxide (ITO) as the transparent metal oxide. They applied the multilayer sputter coatings of seven layers to a polyethylene terephthalate (PET) film substrate. A cross-sectional structure of the film with the multilayer coatings is PET film/ITO/Ag/ITO/Ag/ITO/Ag/ITO. They evaluated the corrosion resistance of the films by a salt-water immersion test. In the test, they immersed the film with multilayer coatings into salt water, and then evaluated the appearance, transmittance, and electrical resistance of the multilayer coatings. They investigated several transition metals as the modifying material, and found that titanium and tantalum drastically improved the resistance of the multilayer coatings to the salt-water exposure without a significant decline in transmittance. They also investigated the relation between elapsed time after deposition of the modifying materials and resistance to the salt water. Furthermore, they investigated the effects of a heat treatment and an oxide plasma treatment on resistance to the salt water

  5. Bubble gate for in-plane flow control.

    Science.gov (United States)

    Oskooei, Ali; Abolhasani, Milad; Günther, Axel

    2013-07-07

    We introduce a miniature gate valve as a readily implementable strategy for actively controlling the flow of liquids on-chip, within a footprint of less than one square millimetre. Bubble gates provide for simple, consistent and scalable control of liquid flow in microchannel networks, are compatible with different bulk microfabrication processes and substrate materials, and require neither electrodes nor moving parts. A bubble gate consists of two microchannel sections: a liquid-filled channel and a gas channel that intercepts the liquid channel to form a T-junction. The open or closed state of a bubble gate is determined by selecting between two distinct gas pressure levels: the lower level corresponds to the "open" state while the higher level corresponds to the "closed" state. During closure, a gas bubble penetrates from the gas channel into the liquid, flanked by a column of equidistantly spaced micropillars on each side, until the flow of liquid is completely obstructed. We fabricated bubble gates using single-layer soft lithographic and bulk silicon micromachining procedures and evaluated their performance with a combination of theory and experimentation. We assessed the dynamic behaviour during more than 300 open-and-close cycles and report the operating pressure envelope for different bubble gate configurations and for the working fluids: de-ionized water, ethanol and a biological buffer. We obtained excellent agreement between the experimentally determined bubble gate operational envelope and a theoretical prediction based on static wetting behaviour. We report case studies that serve to illustrate the utility of bubble gates for liquid sampling in single and multi-layer microfluidic devices. Scalability of our strategy was demonstrated by simultaneously addressing 128 bubble gates.

  6. A transparent electrochromic metal-insulator switching device with three-terminal transistor geometry

    Science.gov (United States)

    Katase, Takayoshi; Onozato, Takaki; Hirono, Misako; Mizuno, Taku; Ohta, Hiromichi

    2016-05-01

    Proton and hydroxyl ion play an essential role for tuning functionality of oxides because their electronic state can be controlled by modifying oxygen off-stoichiometry and/or protonation. Tungsten trioxide (WO3), a well-known electrochromic (EC) material for smart window, is a wide bandgap insulator, whereas it becomes a metallic conductor HxWO3 by protonation. Although one can utilize electrochromism together with metal-insulator (MI) switching for one device, such EC-MI switching cannot be utilized in current EC devices because of their two-terminal structure with parallel-plate configuration. Here we demonstrate a transparent EC-MI switchable device with three-terminal TFT-type structure using amorphous (a-) WO3 channel layer, which was fabricated on glass substrate at room temperature. We used water-infiltrated nano-porous glass, CAN (calcium aluminate with nano-pores), as a liquid-leakage-free solid gate insulator. At virgin state, the device was fully transparent in the visible-light region. For positive gate voltage, the active channel became dark blue, and electrical resistivity of the a-WO3 layer drastically decreased with protonation. For negative gate voltage, deprotonation occurred and the active channel returned to transparent insulator. Good cycleability of the present transparent EC-MI switching device would have potential for the development of advanced smart windows.

  7. Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

    International Nuclear Information System (INIS)

    Han, Jinhua; Wang, Wei; Ying, Jun; Xie, Wenfa

    2014-01-01

    An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized

  8. Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

    Energy Technology Data Exchange (ETDEWEB)

    Han, Jinhua; Wang, Wei, E-mail: wwei99@jlu.edu.cn; Ying, Jun; Xie, Wenfa [State Key Laboratory on Integrated Optoelectronics, College of Electronic Science and Engineering, Jilin University, 2699 Qianjin Street, Changchun 130012 (China)

    2014-01-06

    An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized.

  9. Wear resistance of layers hard faced by the high-alloyed filler metal

    OpenAIRE

    Dušan Arsić; Vukić Lazić; Ruzica R. Nikolic; Milan Mutavdžić; Srbislav Aleksandrović; Milan Djordjević

    2016-01-01

    The objective of this work was to determine the wear resistance of layers hard faced by the high-alloyed filler metal, with or without the austenite inter-layer, on parts that operate at different sliding speeds in conditions without lubrication. The samples were hard faced with the filler metal E 10-UM-60-C with high content of C, Cr and W. Used filler metal belongs into group of alloys aimed for reparatory hard facing of parts damaged by abrasive and erosive wear and it is characterized by ...

  10. ANTIREFLECTION MULTILAYER COATINGS WITH THIN METAL LAYERS

    Directory of Open Access Journals (Sweden)

    L. A. Gubanova

    2016-03-01

    Full Text Available The design of anti-reflective coatings for metal surfaces of Al, Ti, N,i Cr is proposed. The coatings have the form of alternating layers of dielectric/metal/dielectric with the number of cells up to15. The method of calculation of such coatings is proposed. We have calculated the coatings of the type [HfO2/Cr/HfO2]15, [ZrO2/Ti/Al2O3]15, [ZrO2/Cr/ZrO2]15. It is shown that the proposed interference coatings provide reduction of the residual reflectance of the metal several times (from 3.5 to 6.0 in a wide spectral range (300-1000 nm. The proposed coatings can be recommended as anti-reflective coatings for energy saving solar systems and batteries, and photovoltaic cells.

  11. Characterization of a Common-Gate Amplifier Using Ferroelectric Transistors

    Science.gov (United States)

    Hunt, Mitchell; Sayyah, Rana; MacLeod, Todd C.; Ho, Fat D.

    2011-01-01

    In this paper, the empirical data collected through experiments performed using a FeFET in the common-gate amplifier circuit is presented. The FeFET common-gate amplifier was characterized by varying all parameters in the circuit, such as load resistance, biasing of the transistor, and input voltages. Due to the polarization of the ferroelectric layer, the particular behavior of the FeFET common-gate amplifier presents interesting results. Furthermore, the differences between a FeFET common-gate amplifier and a MOSFET common-gate amplifier are examined.

  12. Gate-tunable gigantic lattice deformation in VO2

    International Nuclear Information System (INIS)

    Okuyama, D.; Hatano, T.; Nakano, M.; Takeshita, S.; Ohsumi, H.; Tardif, S.; Shibuya, K.; Yumoto, H.; Koyama, T.; Ohashi, H.; Takata, M.; Kawasaki, M.; Tokura, Y.; Iwasa, Y.; Arima, T.

    2014-01-01

    We examined the impact of electric field on crystal lattice of vanadium dioxide (VO 2 ) in a field-effect transistor geometry by in-situ synchrotron x-ray diffraction measurements. Whereas the c-axis lattice parameter of VO 2 decreases through the thermally induced insulator-to-metal phase transition, the gate-induced metallization was found to result in a significant increase of the c-axis length by almost 1% from that of the thermally stabilized insulating state. We also found that this gate-induced gigantic lattice deformation occurs even at the thermally stabilized metallic state, enabling dynamic control of c-axis lattice parameter by more than 1% at room temperature

  13. Controlled fabrication of Si nanocrystal delta-layers in thin SiO2 layers by plasma immersion ion implantation for nonvolatile memories

    International Nuclear Information System (INIS)

    Bonafos, C.; Ben-Assayag, G.; Groenen, J.; Carrada, M.; Spiegel, Y.; Torregrosa, F.; Normand, P.; Dimitrakis, P.; Kapetanakis, E.; Sahu, B. S.; Slaoui, A.

    2013-01-01

    Plasma Immersion Ion Implantation (PIII) is a promising alternative to beam line implantation to produce a single layer of nanocrystals (NCs) in the gate insulator of metal-oxide semiconductor devices. We report herein the fabrication of two-dimensional Si-NCs arrays in thin SiO 2 films using PIII and rapid thermal annealing. The effect of plasma and implantation conditions on the structural properties of the NC layers is examined by transmission electron microscopy. A fine tuning of the NCs characteristics is possible by optimizing the oxide thickness, implantation energy, and dose. Electrical characterization revealed that the PIII-produced-Si NC structures are appealing for nonvolatile memories

  14. Poly(4-vinylphenol gate insulator with cross-linking using a rapid low-power microwave induction heating scheme for organic thin-film-transistors

    Directory of Open Access Journals (Sweden)

    Ching-Lin Fan

    2016-03-01

    Full Text Available A Microwave-Induction Heating (MIH scheme is proposed for the poly(4-vinylphenol (PVP gate insulator cross-linking process to replace the traditional oven heating cross-linking process. The cross-linking time is significantly decreased from 1 h to 5 min by heating the metal below the PVP layer using microwave irradiation. The necessary microwave power was substantially reduced to about 50 W by decreasing the chamber pressure. The MIH scheme is a good candidate to replace traditional thermal heating for cross-linking of PVP as the gate insulator for organic thin-film-transistors.

  15. Hydration forces and liquid-like layer on the ice/metal interface

    International Nuclear Information System (INIS)

    Daikhin, Leonid; Tsionsky, Vladimir

    2007-01-01

    A model to describe the phenomenon of the liquid-like layer is proposed. It is based on the theory of the hydration forces proposed by Gruen and Marcelja (1983 J. Chem. Soc. Faraday Trans. II 79 225), taking into account the influence of ions on the free energy of water. The model was applied to experimental data obtained with the quartz-crystal microbalance, in a study of the liquid-like layer between metal and frozen aqueous electrolytes and between metal and ice

  16. Amplifying genetic logic gates.

    Science.gov (United States)

    Bonnet, Jerome; Yin, Peter; Ortiz, Monica E; Subsoontorn, Pakpoom; Endy, Drew

    2013-05-03

    Organisms must process information encoded via developmental and environmental signals to survive and reproduce. Researchers have also engineered synthetic genetic logic to realize simpler, independent control of biological processes. We developed a three-terminal device architecture, termed the transcriptor, that uses bacteriophage serine integrases to control the flow of RNA polymerase along DNA. Integrase-mediated inversion or deletion of DNA encoding transcription terminators or a promoter modulates transcription rates. We realized permanent amplifying AND, NAND, OR, XOR, NOR, and XNOR gates actuated across common control signal ranges and sequential logic supporting autonomous cell-cell communication of DNA encoding distinct logic-gate states. The single-layer digital logic architecture developed here enables engineering of amplifying logic gates to control transcription rates within and across diverse organisms.

  17. Analyzing Single-Event Gate Ruptures In Power MOSFET's

    Science.gov (United States)

    Zoutendyk, John A.

    1993-01-01

    Susceptibilities of power metal-oxide/semiconductor field-effect transistors (MOSFET's) to single-event gate ruptures analyzed by exposing devices to beams of energetic bromine ions while applying appropriate bias voltages to source, gate, and drain terminals and measuring current flowing into or out of each terminal.

  18. MATERIAL DEPENDENCE OF TEMPERATURE DISTRIBUTION IN MULTI-LAYER MULTI-METAL COOKWARE

    Directory of Open Access Journals (Sweden)

    MOHAMMADREZA SEDIGH

    2017-09-01

    Full Text Available Laminated structure is becoming more popular in cookware markets; however, there seems to be a lack of enough scientific studies to evaluate its pros and cons, and to show that how it functions. A numerical model using a finite element method with temperature-dependent material properties has been performed to investigate material and layer dependence of temperature distribution in multi-layer multi-metal plate exposed to irregular heating. Behavior of two parameters including mean temperature value and uniformity on the inner surface of plate under variations of thermal properties and geometrical conditions have been studied. The results indicate that conductive metals used as first layer in bi-layer plates have better thermal performance than those used in the second layer. In addition, since cookware manufacturers increasingly prefer to use all-clad aluminium plate, recently, this structure is analysed in the present study as well. The results show all-clad copper and aluminum plate possesses lower temperature gradient compared with single layer aluminum and all-clad aluminum core plates.

  19. Fringing field effects in negative capacitance field-effect transistors with a ferroelectric gate insulator

    Science.gov (United States)

    Hattori, Junichi; Fukuda, Koichi; Ikegami, Tsutomu; Ota, Hiroyuki; Migita, Shinji; Asai, Hidehiro; Toriumi, Akira

    2018-04-01

    We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal-oxide-semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.

  20. Surface layers in the 4A group metals with implanted silicon ions

    International Nuclear Information System (INIS)

    Kovneristyj, Yu.K.; Vavilova, V.V.; Krasnopevtsev, V.V.; Galkin, L.N.; Kudyshev, A.N.; Klechkovskaya, V.V.

    1987-01-01

    A study was made on the change of structure and phase composition of fine near the surface layers of 4A group metals (Hf, Zr, Ti) during ion Si implantation and successive thermal annealing at elevated temperatures. Implantation of Si + ions with 30 or 16 keV energy in Ti, Zr and Hf at room temperature results to amorphization of metal surface layer. The surface hafnium and titanium layer with implanted Si atoms due to interaction with residual atmosphere of oxygen turns during annealing at 870 K to amorphous solid solution of HfO 2m or TiO 2 with Si, preventing further metal oxidation; layers of amorphous alloy are characterized by thermal stability up to 1270 K. Oxidation of the surface amorphous layer in residual oxygen atmosphere and its crystallization in ZrO 2 take place in result of Zr annealing with implanted Si ions at temperature not exceeding 870 K. Similar phenomena are observed in the case of hafnium with implanted oxygen ions or small dose of silicon ions. Thermal stability of amorphous layers produced during ion implantation of Si in Ti, Zr and Hf corresponds to scale resistance of monolithic alloys in Ti-Si, Zr-Si and Hf-Si systems

  1. Metal ion-specific thermal stability of bacterial S-Layers

    Energy Technology Data Exchange (ETDEWEB)

    Drobot, Bjoern; Raff, Johannes [Helmholtz-Zentrum Dresden-Rossendorf e.V., Dresden (Germany). Div. Biogeochemistry; Fahmy, Karim [Helmholtz-Zentrum Dresden-Rossendorf e.V., Dresden (Germany). Div. Biophysics

    2016-07-01

    Many bacteria are covered by a surface layer (S-layer), i.e., a para-crystalline two-dimensional array of proteins which control cell shape, act as molecular sieves and have potential applications as radionuclide-binding material for bioremediation of polluted areas. Knowledge and control of the metal-dependent stability of the purified proteins is required for their technical application. Here, we have explored by differential scanning calorimetry the thermal stability of the S-layer protein slp-B53 from Lysinibacillus sphaericus, a Gram-positive bacterium isolated from a uranium mining waste pile [1].

  2. Characterization of Transition Metal Carbide Layers Synthesized by Thermo-reactive Diffusion Processes

    DEFF Research Database (Denmark)

    Laursen, Mads Brink; Fernandes, Frederico Augusto Pires; Christiansen, Thomas Lundin

    2015-01-01

    . In this study halide-activated pack cementation techniques were used on tool steel Vanadis 6 and martensitic stainless steel AISI 420 in order to produce hard layers of titanium carbide (TiC), vanadium carbide (V8C7) and chromium carbides (Cr23C6 and Cr7C3). Surface layers were characterized by scanning......Hard wear resistant surface layers of transition metal carbides can be produced by thermo-reactive diffusion processes where interstitial elements from a steel substrate together with external sources of transition metals (Ti, V, Cr etc.) form hard carbide and/or nitride layers at the steel surface...... electron microscopy, X-ray diffraction and Vickers hardness testing. The study shows that porosityfree, homogenous and very hard surface layers can be produced by thermo-reactive diffusion processes. The carbon availability of the substrate influences thickness of obtained layers, as Vanadis 6 tool steel...

  3. Controlled fabrication of Si nanocrystal delta-layers in thin SiO{sub 2} layers by plasma immersion ion implantation for nonvolatile memories

    Energy Technology Data Exchange (ETDEWEB)

    Bonafos, C.; Ben-Assayag, G.; Groenen, J.; Carrada, M. [CEMES-CNRS and Université de Toulouse, 29 rue J. Marvig, 31055 Toulouse Cedex 04 (France); Spiegel, Y.; Torregrosa, F. [IBS, Rue G Imbert Prolongée, ZI Peynier-Rousset, 13790 Peynier (France); Normand, P.; Dimitrakis, P.; Kapetanakis, E. [NCSRD, Terma Patriarchou Gregoriou, 15310 Aghia Paraskevi (Greece); Sahu, B. S.; Slaoui, A. [ICube, 23 Rue du Loess, 67037 Strasbourg Cedex 2 (France)

    2013-12-16

    Plasma Immersion Ion Implantation (PIII) is a promising alternative to beam line implantation to produce a single layer of nanocrystals (NCs) in the gate insulator of metal-oxide semiconductor devices. We report herein the fabrication of two-dimensional Si-NCs arrays in thin SiO{sub 2} films using PIII and rapid thermal annealing. The effect of plasma and implantation conditions on the structural properties of the NC layers is examined by transmission electron microscopy. A fine tuning of the NCs characteristics is possible by optimizing the oxide thickness, implantation energy, and dose. Electrical characterization revealed that the PIII-produced-Si NC structures are appealing for nonvolatile memories.

  4. High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

    Science.gov (United States)

    Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

    2018-05-01

    The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

  5. High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

    Science.gov (United States)

    Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

    2018-02-01

    The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

  6. Plasmonically sensitized metal-oxide electron extraction layers for organic solar cells.

    Science.gov (United States)

    Trost, S; Becker, T; Zilberberg, K; Behrendt, A; Polywka, A; Heiderhoff, R; Görrn, P; Riedl, T

    2015-01-16

    ZnO and TiOx are commonly used as electron extraction layers (EELs) in organic solar cells (OSCs). A general phenomenon of OSCs incorporating these metal-oxides is the requirement to illuminate the devices with UV light in order to improve device characteristics. This may cause severe problems if UV to VIS down-conversion is applied or if the UV spectral range (λ work, silver nanoparticles (AgNP) are used to plasmonically sensitize metal-oxide based EELs in the vicinity (1-20 nm) of the metal-oxide/organic interface. We evidence that plasmonically sensitized metal-oxide layers facilitate electron extraction and afford well-behaved highly efficient OSCs, even without the typical requirement of UV exposure. It is shown that in the plasmonically sensitized metal-oxides the illumination with visible light lowers the WF due to desorption of previously ionosorbed oxygen, in analogy to the process found in neat metal oxides upon UV exposure, only. As underlying mechanism the transfer of hot holes from the metal to the oxide upon illumination with hν < Eg is verified. The general applicability of this concept to most common metal-oxides (e.g. TiOx and ZnO) in combination with different photoactive organic materials is demonstrated.

  7. Fabrication of metallic nanomasks by transfer of self-organized nanodot patterns from semiconductor material into thin metallic layers

    International Nuclear Information System (INIS)

    Bobek, T.; Kurz, H.

    2007-01-01

    The basic understanding of the formation of highly regular nanostructures during ion erosion of amorphous GaSb layers is revised. The essential physical parameters for the formation of the highly regular dot pattern are discussed. Numerical modelling based on the stabilized isotropic Kuramoto-Sivashinsky equation is presented and discussed. The experimental part of this contribution presents the successful pattern transfer into metallic buried thin layers as well as into Silicon underlayers. The critical conditions for this transfer technique are discussed. Application potential of using this self-organization scheme for the generation of highly regular patterns in ferromagnetic metal layers as well as in crystalline silicon is estimated

  8. Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium–gallium–zinc oxide gate stack

    Science.gov (United States)

    Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

    2018-07-01

    We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium–gallium–zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>104). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

  9. Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium-gallium-zinc oxide gate stack.

    Science.gov (United States)

    Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

    2018-07-20

    We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium-gallium-zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>10 4 ). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

  10. Ultra-low power thin film transistors with gate oxide formed by nitric acid oxidation method

    International Nuclear Information System (INIS)

    Kobayashi, H.; Kim, W. B.; Matsumoto, T.

    2011-01-01

    We have developed a low temperature fabrication method of SiO 2 /Si structure by use of nitric acid, i.e., nitric acid oxidation of Si (NAOS) method, and applied it to thin film transistors (TFT). A silicon dioxide (SiO 2 ) layer formed by the NAOS method at room temperature possesses 1.8 nm thickness, and its leakage current density is as low as that of thermally grown SiO 2 layer with the same thickness formed at ∼900 deg C. The fabricated TFTs possess an ultra-thin NAOS SiO 2 /CVD SiO 2 stack gate dielectric structure. The ultrathin NAOS SiO 2 layer effectively blocks a gate leakage current, and thus, the thickness of the gate oxide layer can be decreased from 80 to 20 nm. The thin gate oxide layer enables to decrease the operation voltage to 2 V (cf. the conventional operation voltage of TFTs with 80 nm gate oxide: 12 V) because of the low threshold voltages, i.e., -0.5 V for P-ch TFTs and 0.5 V for N-ch TFTs, and thus the consumed power decreases to 1/36 of that of the conventional TFTs. The drain current increases rapidly with the gate voltage, and the sub-threshold voltage is ∼80 mV/dec. The low sub-threshold swing is attributable to the thin gate oxide thickness and low interface state density of the NAOS SiO 2 layer. (authors)

  11. Plasma Deposited SiO2 for Planar Self-Aligned Gate Metal-Insulator-Semiconductor Field Effect Transistors on Semi-Insulating InP

    Science.gov (United States)

    Tabory, Charles N.; Young, Paul G.; Smith, Edwyn D.; Alterovitz, Samuel A.

    1994-01-01

    Metal-insulator-semiconductor (MIS) field effect transistors were fabricated on InP substrates using a planar self-aligned gate process. A 700-1000 A gate insulator of Si02 doped with phosphorus was deposited by a direct plasma enhanced chemical vapor deposition at 400 mTorr, 275 C, 5 W, and power density of 8.5 MW/sq cm. High frequency capacitance-voltage measurements were taken on MIS capacitors which have been subjected to a 700 C anneal and an interface state density of lxl0(exp 11)/eV/cq cm was found. Current-voltage measurements of the capacitors show a breakdown voltage of 107 V/cm and a insulator resistivity of 10(exp 14) omega cm. Transistors were fabricated on semi-insulating InP using a standard planar self-aligned gate process in which the gate insulator was subjected to an ion implantation activation anneal of 700 C. MIS field effect transistors gave a maximum extrinsic transconductance of 23 mS/mm for a gate length of 3 microns. The drain current drift saturated at 87.5% of the initial current, while reaching to within 1% of the saturated value after only 1x10(exp 3). This is the first reported viable planar InP self-aligned gate transistor process reported to date.

  12. Layer-by-layer modification of thin-film metal-semiconductor multilayers with ultrashort laser pulses

    Science.gov (United States)

    Romashevskiy, S. A.; Tsygankov, P. A.; Ashitkov, S. I.; Agranat, M. B.

    2018-05-01

    The surface modifications in a multilayer thin-film structure (50-nm alternating layers of Si and Al) induced by a single Gaussian-shaped femtosecond laser pulse (350 fs, 1028 nm) in the air are investigated by means of atomic-force microscopy (AFM), scanning electron microscopy (SEM), and optical microscopy (OM). Depending on the laser fluence, various modifications of nanometer-scale metal and semiconductor layers, including localized formation of silicon/aluminum nanofoams and layer-by-layer removal, are found. While the nanofoams with cell sizes in the range of tens to hundreds of nanometers are produced only in the two top layers, layer-by-layer removal is observed for the four top layers under single pulse irradiation. The 50-nm films of the multilayer structure are found to be separated at their interfaces, resulting in a selective removal of several top layers (up to 4) in the form of step-like (concentric) craters. The observed phenomenon is associated with a thermo-mechanical ablation mechanism that results in splitting off at film-film interface, where the adhesion force is less than the bulk strength of the used materials, revealing linear dependence of threshold fluences on the film thickness.

  13. Design and implementation of an efficient single layer five input majority voter gate in quantum-dot cellular automata.

    Science.gov (United States)

    Bahar, Ali Newaz; Waheed, Sajjad

    2016-01-01

    The fundamental logical element of a quantum-dot cellular automata (QCA) circuit is majority voter gate (MV). The efficiency of a QCA circuit is depends on the efficiency of the MV. This paper presents an efficient single layer five-input majority voter gate (MV5). The structure of proposed MV5 is very simple and easy to implement in any logical circuit. This proposed MV5 reduce number of cells and use conventional QCA cells. However, using MV5 a multilayer 1-bit full-adder (FA) is designed. The functional accuracy of the proposed MV5 and FA are confirmed by QCADesigner a well-known QCA layout design and verification tools. Furthermore, the power dissipation of proposed circuits are estimated, which shows that those circuits dissipate extremely small amount of energy and suitable for reversible computing. The simulation outcomes demonstrate the superiority of the proposed circuit.

  14. Layered Metal Nanoparticle Structures on Electrodes for Sensing, Switchable Controlled Uptake/Release, and Photo-electrochemical Applications.

    Science.gov (United States)

    Tel-Vered, Ran; Kahn, Jason S; Willner, Itamar

    2016-01-06

    Layered metal nanoparticle (NP) assemblies provide highly porous and conductive composites of unique electrical and optical (plasmonic) properties. Two methods to construct layered metal NP matrices are described, and these include the layer-by-layer deposition of NPs, or the electropolymerization of monolayer-functionalized NPs, specifically thioaniline-modified metal NPs. The layered NP composites are used as sensing matrices through the use of electrochemistry or surface plasmon resonance (SPR) as transduction signals. The crosslinking of the metal NP composites with molecular receptors, or the imprinting of molecular recognition sites into the electropolymerized NP matrices lead to selective and chiroselective sensing interfaces. Furthermore, the electrosynthesis of redox-active, imprinted, bis-aniline bridged Au NP composites yields electrochemically triggered "sponges" for the switchable uptake and release of electron-acceptor substrates, and results in conductive surfaces of electrochemically controlled wettability. Also, photosensitizer-relay-crosslinked Au NP composites, or electrochemically polymerized layered semiconductor quantum dot/metal NP matrices on electrodes, are demonstrated as functional nanostructures for photoelectrochemical applications. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  15. Studies of proximity-effect and tunneling in YBCO/metal layered films

    Energy Technology Data Exchange (ETDEWEB)

    Greene, L.H.; Barner, J.B.; Feldmann, W.L.; Farrow, L.A.; Miceli, P.F.; Ramesh, R.; Wilkens, B.J.; Bagley, B.G.; Tarascon, J.M.; Wernick, J.H. (Bellcore, Red Bank, NJ (USA)); Giroud, M. (CRTBT-CNRS, Grenoble (France)); Rowell, J.M. (Conductus, Sunnyvale, CA (USA))

    1989-12-01

    The short coherence length of the high-Tc superconductors, coupled with their tendency to form non-superconducting surface layers, accounts for the difficulty in achieving good tunnel junctions. A proximity layer of a longer coherence length normal metal (N) is expected to ''draw out'' Cooper pairs. Our goal is to fabricate reproducible, planar tunnel junctions of SNIS layered structures for proximity tunneling spectroscopy. Such structures of YBCO/N/I/Pb and SNS structures of YBCO/N/Pb indicate that the normal metal produces a low resistance contact to the YBCO surface with a supercurrent observed in the SNS. The insulating barrier in the SNIS is reproducible, insulating and continuous: A sharp Pb gap and phonons from the counter-electrode are routinely observed. (orig.).

  16. Studies of proximity-effect and tunneling in YBCO/metal layered films

    International Nuclear Information System (INIS)

    Greene, L.H.; Barner, J.B.; Feldmann, W.L.; Farrow, L.A.; Miceli, P.F.; Ramesh, R.; Wilkens, B.J.; Bagley, B.G.; Tarascon, J.M.; Wernick, J.H.; Giroud, M.; Rowell, J.M.

    1989-01-01

    The short coherence length of the high-T c superconductors, coupled with their tendency to form non-superconducting surface layers, accounts for the difficulty in achieving good tunnel junctions. A proximity layer of a longer coherence length normal metal (N) is expected to draw out Cooper pairs. The authors' goal is to fabricate reproducible, planar tunnel junctions of SNIS layered structures for proximity tunneling spectroscopy. They discuss how such structures of YBCO/N/I/Pb and SNS structures of YBCO/N/Pb indicate that the normal metal produces a low resistance contact to the YBCO surface with a supercurrent observed in the SNS. The insulating barrier in the SNIS is reproducible, insulating and continuous: A sharp Pb gap and phonons from the counter-electrode are routinely observed

  17. Analysis of gate underlap channel double gate MOS transistor for electrical detection of bio-molecules

    Science.gov (United States)

    Ajay; Narang, Rakhi; Saxena, Manoj; Gupta, Mridula

    2015-12-01

    In this paper, an analytical model for gate drain underlap channel Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG-MOSFET) for label free electrical detection of biomolecules has been proposed. The conformal mapping technique has been used to derive the expressions for surface potential, lateral electric field, energy bands (i.e. conduction and valence band) and threshold voltage (Vth). Subsequently a full drain current model to analyze the sensitivity of the biosensor has been developed. The shift in the threshold voltage and drain current (after the biomolecules interaction with the gate underlap channel region of the MOS transistor) has been used as a sensing metric. All the characteristic trends have been verified through ATLAS (SILVACO) device simulation results.

  18. Heavy-ion-induced, gate-rupture in power MOSFETs

    International Nuclear Information System (INIS)

    Fischer, T.A.

    1987-01-01

    A new, heavy-ion-induced, burnout mechanism has been experimentally observed in power metal-oxide-semiconductor field-effect transistors (MOSFETs). This mechanism occurs when a heavy, charged particle passes through the gate oxide region of n- or p-channel devices having sufficient gate-to-source or gate-to-drain bias. The gate-rupture leads to significant permanent degradation of the device. A proposed failure mechanism is discussed and experimentally verified. In addition, the absolute immunity of p-channel devices to heavy-ion-induced, semiconductor burnout is demonstrated and discussed along with new, non-destructive, burnout testing methods

  19. Atomic layer deposition to prevent metal transfer from implants: An X-ray fluorescence study

    Energy Technology Data Exchange (ETDEWEB)

    Bilo, Fabjola [INSTM and Chemistry for Technologies Laboratory, University of Brescia, via Branze, 38, 25123 Brescia (Italy); Borgese, Laura, E-mail: laura.borgese@unibs.itl [INSTM and Chemistry for Technologies Laboratory, University of Brescia, via Branze, 38, 25123 Brescia (Italy); Prost, Josef; Rauwolf, Mirjam; Turyanskaya, Anna; Wobrauschek, Peter; Kregsamer, Peter; Streli, Christina [Atominstitut, TU Wien, Stadionallee 2, 1020 Vienna (Austria); Pazzaglia, Ugo [Dipartimento Specialità Medico Chirurgiche Sc. Radiol. e Sanità Pubblica, University of Brescia, v.le Europa, 11, 25121 Brescia (Italy); Depero, Laura E. [INSTM and Chemistry for Technologies Laboratory, University of Brescia, via Branze, 38, 25123 Brescia (Italy)

    2015-12-30

    Highlights: • Co and Cr migrate from bare alloy implant to the surrounding tissue showing a cluster distribution. • Co and Cr migrate from the TiO{sub 2} coated implant to the surrounding tissue showing a decreasing gradient distribution from the alloy surface. • TiO{sub 2} coating layers obtained by ALD on Co–Cr alloy show a barrier effect for the migration of metals. • The thicker the TiO{sub 2} layer deposited by ALD, the lower the metal migration. • The migration of metals from bare alloy toward the surrounding tissue increases with time. This effect is not detected in the coated samples. - Abstract: We show that Atomic Layer Deposition is a suitable coating technique to prevent metal diffusion from medical implants. The metal distribution in animal bone tissue with inserted bare and coated Co–Cr alloys was evaluated by means of micro X-ray fluorescence mapping. In the uncoated implant, the migration of Co and Cr particles from the bare alloy in the biological tissues is observed just after one month and the number of particles significantly increases after two months. In contrast, no metal diffusion was detected in the implant coated with TiO{sub 2}. Instead, a gradient distribution of the metals was found, from the alloy surface going into the tissue. No significant change was detected after two months of aging. As expected, the thicker is the TiO{sub 2} layer, the lower is the metal migration.

  20. Scan direction induced charging dynamics and the application for detection of gate to S/D shorts in logic devices

    Science.gov (United States)

    Lei, Ming; Tian, Qing; Wu, Kevin; Zhao, Yan

    2016-03-01

    Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

  1. Gate modulation of proton transport in a nanopore.

    Science.gov (United States)

    Mei, Lanju; Yeh, Li-Hsien; Qian, Shizhi

    2016-03-14

    Proton transport in confined spaces plays a crucial role in many biological processes as well as in modern technological applications, such as fuel cells. To achieve active control of proton conductance, we investigate for the first time the gate modulation of proton transport in a pH-regulated nanopore by a multi-ion model. The model takes into account surface protonation/deprotonation reactions, surface curvature, electroosmotic flow, Stern layer, and electric double layer overlap. The proposed model is validated by good agreement with the existing experimental data on nanopore conductance with and without a gate voltage. The results show that the modulation of proton transport in a nanopore depends on the concentration of the background salt and solution pH. Without background salt, the gated nanopore exhibits an interesting ambipolar conductance behavior when pH is close to the isoelectric point of the dielectric pore material, and the net ionic and proton conductance can be actively regulated with a gate voltage as low as 1 V. The higher the background salt concentration, the lower is the performance of the gate control on the proton transport.

  2. Surface metal standards produced by ion implantation through a removable layer

    International Nuclear Information System (INIS)

    Schueler, B.W.; Granger, C.N.; McCaig, L.; McKinley, J.M.; Metz, J.; Mowat, I.; Reich, D.F.; Smith, S.; Stevie, F.A.; Yang, M.H.

    2003-01-01

    Surface metal concentration standards were produced by ion implantation and investigated for their suitability to calibrate surface metal measurements by secondary ion mass spectrometry (SIMS). Single isotope implants were made through a 100 nm oxide layer on silicon. The implant energies were chosen to place the peak of the implanted species at a depth of 100 nm. Subsequent removal of the oxide layer was used to expose the implant peak and to produce controlled surface metal concentrations. Surface metal concentration measurements by time-of-flight SIMS (TOF-SIMS) with an analysis depth of 1 nm agreed with the expected surface concentrations of the implant standards with a relative mean standard deviation of 20%. Since the TOF-SIMS relative sensitivity factors (RSFs) were originally derived from surface metal measurements of surface contaminated silicon wafers, the agreement implies that the implant standards can be used to measure RSF values. The homogeneity of the surface metal concentration was typically <10%. The dopant dose remaining in silicon after oxide removal was measured using the surface-SIMS protocol. The measured implant dose agreed with the expected dose with a mean relative standard deviation of 25%

  3. Structure and nano-mechanical characteristics of surface oxide layers on a metallic glass.

    Science.gov (United States)

    Caron, A; Qin, C L; Gu, L; González, S; Shluger, A; Fecht, H-J; Louzguine-Luzgin, D V; Inoue, A

    2011-03-04

    Owing to their low elastic moduli, high specific strength and excellent processing characteristics in the undercooled liquid state, metallic glasses are promising materials for applications in micromechanical systems. With miniaturization of metallic mechanical components down to the micrometer scale, the importance of a native oxide layer on a glass surface is increasing. In this work we use TEM and XPS to characterize the structure and properties of the native oxide layer grown on Ni(62)Nb(38) metallic glass and their evolution after annealing in air. The thickness of the oxide layer almost doubled after annealing. In both cases the oxide layer is amorphous and consists predominantly of Nb oxide. We investigate the friction behavior at low loads and in ambient conditions (i.e. at T = 295 K and 60% air humidity) of both as-cast and annealed samples by friction force microscopy. After annealing the friction coefficient is found to have significantly increased. We attribute this effect to the increase of the mechanical stability of the oxide layer upon annealing.

  4. Memory characteristics of Au nanocrystals embedded in metal-oxide-semiconductor structure by using atomic-layer-deposited Al2O3 as control oxide

    International Nuclear Information System (INIS)

    Wang, C.-C.; Chiou, Y.-K.; Chang, C.-H.; Tseng, J.-Y.; Wu, L.-J.; Chen, C.-Y.; Wu, T.-B.

    2007-01-01

    The nonvolatile memory characteristics of metal-oxide-semiconductor (MOS) structures containing Au nanocrystals in the Al 2 O 3 /SiO 2 matrix were studied. In this work, we have demonstrated that the use of Al 2 O 3 as control oxide prepared by atomic-layer-deposition enhances the erase speed of the MOS capacitors. A giant capacitance-voltage hysteresis loop and a very short erase time which is lower than 1 ms can be obtained. Compared with the conventional floating-gate electrically erasable programmable read-only memories, the erase speed was promoted drastically. In addition, very low leakage current and large turn-around voltage resulting from electrons or holes stored in the Au nanocrystals were found in the current-voltage relation of the MOS capacitors

  5. Structural variations in layered alkaline earth metal cyclohexyl ...

    Indian Academy of Sciences (India)

    Administrator

    because of the entrance of the guest molecules between the layers, there will be a change in the interlayer distance (Alberti 1978). Although M(IV) organo-phos- phonates are well documented, the chemistry of M(II) organophosphonates especially the alkaline earth metal organophosphonates has been explored marginally ...

  6. The effect of gate length on SOI-MOSFETS operation | Baedi ...

    African Journals Online (AJOL)

    The effect of gate length on the operation of silicon-on-insulator (SOI) MOSFET structure with a layer of buried silicon oxide added to isolate the device body has been simulated. Three transistors with gate lengths of 100, 200 and 500 nm were simulated. Simulations showed that with a fixed channel length, when the gate ...

  7. Gate-tunable gigantic lattice deformation in VO{sub 2}

    Energy Technology Data Exchange (ETDEWEB)

    Okuyama, D., E-mail: okuyama@riken.jp, E-mail: nakano@imr.tohoku.ac.jp, E-mail: iwasa@ap.t.u-tokyo.ac.jp; Hatano, T. [RIKEN Center for Emergent Matter Science (CEMS), Wako 351-0198 (Japan); Nakano, M., E-mail: okuyama@riken.jp, E-mail: nakano@imr.tohoku.ac.jp, E-mail: iwasa@ap.t.u-tokyo.ac.jp [RIKEN Center for Emergent Matter Science (CEMS), Wako 351-0198 (Japan); Institute for Materials Research, Tohoku University, Sendai 980-8577 (Japan); Takeshita, S.; Ohsumi, H.; Tardif, S. [RIKEN SPring-8 Center, Hyogo 679-5148 (Japan); Shibuya, K. [National Institute of Advanced Industrial Science and Technology, Tsukuba 305-8562 (Japan); Yumoto, H.; Koyama, T.; Ohashi, H. [Japan Synchrotron Radiation Research Institute, SPring-8, Hyogo 679-5198 (Japan); Takata, M. [RIKEN SPring-8 Center, Hyogo 679-5148 (Japan); Japan Synchrotron Radiation Research Institute, SPring-8, Hyogo 679-5198 (Japan); Kawasaki, M.; Tokura, Y.; Iwasa, Y., E-mail: okuyama@riken.jp, E-mail: nakano@imr.tohoku.ac.jp, E-mail: iwasa@ap.t.u-tokyo.ac.jp [RIKEN Center for Emergent Matter Science (CEMS), Wako 351-0198 (Japan); Quantum-Phase Electronics Center and Department of Applied Physics, University of Tokyo, Tokyo 113-8656 (Japan); Arima, T. [RIKEN Center for Emergent Matter Science (CEMS), Wako 351-0198 (Japan); RIKEN SPring-8 Center, Hyogo 679-5148 (Japan); Department of Advanced Materials Science, University of Tokyo, Kashiwa 277-8561 (Japan)

    2014-01-13

    We examined the impact of electric field on crystal lattice of vanadium dioxide (VO{sub 2}) in a field-effect transistor geometry by in-situ synchrotron x-ray diffraction measurements. Whereas the c-axis lattice parameter of VO{sub 2} decreases through the thermally induced insulator-to-metal phase transition, the gate-induced metallization was found to result in a significant increase of the c-axis length by almost 1% from that of the thermally stabilized insulating state. We also found that this gate-induced gigantic lattice deformation occurs even at the thermally stabilized metallic state, enabling dynamic control of c-axis lattice parameter by more than 1% at room temperature.

  8. Multi-layer thin-film electrolytes for metal supported solid oxide fuel cells

    Science.gov (United States)

    Haydn, Markus; Ortner, Kai; Franco, Thomas; Uhlenbruck, Sven; Menzler, Norbert H.; Stöver, Detlev; Bräuer, Günter; Venskutonis, Andreas; Sigl, Lorenz S.; Buchkremer, Hans-Peter; Vaßen, Robert

    2014-06-01

    A key to the development of metal-supported solid oxide fuel cells (MSCs) is the manufacturing of gas-tight thin-film electrolytes, which separate the cathode from the anode. This paper focuses the electrolyte manufacturing on the basis of 8YSZ (8 mol.-% Y2O3 stabilized ZrO2). The electrolyte layers are applied by a physical vapor deposition (PVD) gas flow sputtering (GFS) process. The gas-tightness of the electrolyte is significantly improved when sequential oxidic and metallic thin-film multi-layers are deposited, which interrupt the columnar grain structure of single-layer electrolytes. Such electrolytes with two or eight oxide/metal layers and a total thickness of about 4 μm obtain leakage rates of less than 3 × 10-4 hPa dm3 s-1 cm-2 (Δp: 100 hPa) at room temperature and therefore fulfill the gas tightness requirements. They are also highly tolerant with respect to surface flaws and particulate impurities which can be present on the graded anode underground. MSC cell tests with double-layer and multilayer electrolytes feature high power densities more than 1.4 W cm-2 at 850 °C and underline the high potential of MSC cells.

  9. Enhancement mode GaN-based multiple-submicron channel array gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors

    Science.gov (United States)

    Lee, Ching-Ting; Wang, Chun-Chi

    2018-04-01

    To study the function of channel width in multiple-submicron channel array, we fabricated the enhancement mode GaN-based gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with a channel width of 450 nm and 195 nm, respectively. In view of the enhanced gate controllability in a narrower fin-channel structure, the transconductance was improved from 115 mS/mm to 151 mS/mm, the unit gain cutoff frequency was improved from 6.2 GHz to 6.8 GHz, and the maximum oscillation frequency was improved from 12.1 GHz to 13.1 GHz of the devices with a channel width of 195 nm, compared with the devices with a channel width of 450 nm.

  10. Band Offsets and Interfacial Properties of HfAlO Gate Dielectric Grown on InP by Atomic Layer Deposition.

    Science.gov (United States)

    Yang, Lifeng; Wang, Tao; Zou, Ying; Lu, Hong-Liang

    2017-12-01

    X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy have been used to determine interfacial properties of HfO 2 and HfAlO gate dielectrics grown on InP by atomic layer deposition. An undesirable interfacial InP x O y layer is easily formed at the HfO 2 /InP interface, which can severely degrade the electrical performance. However, an abrupt interface can be achieved when the growth of the HfAlO dielectric on InP starts with an ultrathin Al 2 O 3 layer. The valence and conduction band offsets for HfAlO/InP heterojunctions have been determined to be 1.87 ± 0.1 and 2.83 ± 0.1 eV, respectively. These advantages make HfAlO a potential dielectric for InP MOSFETs.

  11. Ion transport by gating voltage to nanopores produced via metal-assisted chemical etching method

    Science.gov (United States)

    Van Toan, Nguyen; Inomata, Naoki; Toda, Masaya; Ono, Takahito

    2018-05-01

    In this work, we report a simple and low-cost way to create nanopores that can be employed for various applications in nanofluidics. Nano sized Ag particles in the range from 1 to 20 nm are formed on a silicon substrate with a de-wetting method. Then the silicon nanopores with an approximate 15 nm average diameter and 200 μm height are successfully produced by the metal-assisted chemical etching method. In addition, electrically driven ion transport in the nanopores is demonstrated for nanofluidic applications. Ion transport through the nanopores is observed and could be controlled by an application of a gating voltage to the nanopores.

  12. Large-area few-layer MoS 2 deposited by sputtering

    KAUST Repository

    Huang, Jyun-Hong

    2016-06-06

    Direct magnetron sputtering of transition metal dichalcogenide targets is proposed as a new approach for depositing large-area two-dimensional layered materials. Bilayer to few-layer MoS2 deposited by magnetron sputtering followed by post-deposition annealing shows superior area scalability over 20 cm(2) and layer-by-layer controllability. High crystallinity of layered MoS2 was confirmed by Raman, photo-luminescence, and transmission electron microscopy analysis. The sputtering temperature and annealing ambience were found to play an important role in the film quality. The top-gate field-effect transistor by using the layered MoS2 channel shows typical n-type characteristics with a current on/off ratio of approximately 10(4). The relatively low mobility is attributed to the small grain size of 0.1-1 mu m with a trap charge density in grain boundaries of the order of 10(13) cm(-2).

  13. Selective and low temperature transition metal intercalation in layered tellurides

    Science.gov (United States)

    Yajima, Takeshi; Koshiko, Masaki; Zhang, Yaoqing; Oguchi, Tamio; Yu, Wen; Kato, Daichi; Kobayashi, Yoji; Orikasa, Yuki; Yamamoto, Takafumi; Uchimoto, Yoshiharu; Green, Mark A.; Kageyama, Hiroshi

    2016-01-01

    Layered materials embrace rich intercalation reactions to accommodate high concentrations of foreign species within their structures, and find many applications spanning from energy storage, ion exchange to secondary batteries. Light alkali metals are generally most easily intercalated due to their light mass, high charge/volume ratio and in many cases strong reducing properties. An evolving area of materials chemistry, however, is to capture metals selectively, which is of technological and environmental significance but rather unexplored. Here we show that the layered telluride T2PTe2 (T=Ti, Zr) displays exclusive insertion of transition metals (for example, Cd, Zn) as opposed to alkali cations, with tetrahedral coordination preference to tellurium. Interestingly, the intercalation reactions proceed in solid state and at surprisingly low temperatures (for example, 80 °C for cadmium in Ti2PTe2). The current method of controlling selectivity provides opportunities in the search for new materials for various applications that used to be possible only in a liquid. PMID:27966540

  14. Control of electronic properties of 2D carbides (MXenes) by manipulating their transition metal layers

    KAUST Repository

    Anasori, Babak

    2016-02-24

    In this study, a transition from metallic to semiconducting-like behavior has been demonstrated in two-dimensional (2D) transition metal carbides by replacing titanium with molybdenum in the outer transition metal (M) layers of M3C2 and M4C3 MXenes. The MXene structure consists of n + 1 layers of near-close packed M layers with C or N occupying the octahedral site between them in an [MX]nM arrangement. Recently, two new families of ordered 2D double transition metal carbides MXenes were discovered, M′2M′′C2 and M′2M′′2C3 – where M′ and M′′ are two different early transition metals, such as Mo, Cr, Ta, Nb, V, and Ti. The M′ atoms only occupy the outer layers and the M′′ atoms fill the middle layers. In other words, M′ atomic layers sandwich the middle M′′–C layers. Using X-ray atomic pair distribution function (PDF) analysis on Mo2TiC2 and Mo2Ti2C3 MXenes, we present the first quantitative analysis of structures of these novel materials and experimentally confirm that Mo atoms are in the outer layers of the [MC]nM structures. The electronic properties of these Mo-containing MXenes are compared with their Ti3C2 counterparts, and are found to be no longer metallic-like conductors; instead the resistance increases mildly with decreasing temperatures. Density functional theory (DFT) calculations suggest that OH terminated Mo–Ti MXenes are semiconductors with narrow band gaps. Measurements of the temperature dependencies of conductivities and magnetoresistances have confirmed that Mo2TiC2Tx exhibits semiconductor-like transport behavior, while Ti3C2Tx is a metal. This finding opens new avenues for the control of the electronic and optical applications of MXenes and for exploring new applications, in which semiconducting properties are required.

  15. Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene-graphene composite layers for flexible thin film transistors with a polymer gate dielectric.

    Science.gov (United States)

    Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

    2014-02-28

    Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene-graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene-graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm(2) V(-1) s(-1) and a threshold voltage of -0.7 V at V(gs) = -40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm(2) V(-1) s(-1) and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies.

  16. Large current modulation and tunneling magnetoresistance change by a side-gate electric field in a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor.

    Science.gov (United States)

    Kanaki, Toshiki; Yamasaki, Hiroki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

    2018-05-08

    A vertical spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) is a promising low-power device for the post scaling era. Here, using a ferromagnetic-semiconductor GaMnAs-based vertical spin MOSFET with a GaAs channel layer, we demonstrate a large drain-source current I DS modulation by a gate-source voltage V GS with a modulation ratio up to 130%, which is the largest value that has ever been reported for vertical spin field-effect transistors thus far. We find that the electric field effect on indirect tunneling via defect states in the GaAs channel layer is responsible for the large I DS modulation. This device shows a tunneling magnetoresistance (TMR) ratio up to ~7%, which is larger than that of the planar-type spin MOSFETs, indicating that I DS can be controlled by the magnetization configuration. Furthermore, we find that the TMR ratio can be modulated by V GS . This result mainly originates from the electric field modulation of the magnetic anisotropy of the GaMnAs ferromagnetic electrodes as well as the potential modulation of the nonmagnetic semiconductor GaAs channel layer. Our findings provide important progress towards high-performance vertical spin MOSFETs.

  17. An analytical gate tunneling current model for MOSFETs

    Energy Technology Data Exchange (ETDEWEB)

    Kazerouni, Iman Abaspur, E-mail: imanabaspur@gmail.com; Hosseini, Seyed Ebrahim [Sabzevar Tarbiat Moallem University, Electrical and Computer Department (Iran, Islamic Republic of)

    2012-03-15

    Gate tunneling current of MOSFETs is an important factor in modeling ultra small devices. In this paper, gate tunneling in present-generation MOSFETs is studied. In the proposed model, we calculate the electron wave function at the semiconductor-oxide interface and inversion charge by treating the inversion layer as a potential well, including some simplifying assumptions. Then we compute the gate tunneling current using the calculated wave function. The proposed model results have an excellent agreement with experimental results in the literature.

  18. Synthesis and Characterization of the 2-Dimensional Transition Metal Dichalcogenides

    Science.gov (United States)

    Browning, Robert

    In the last 50 years, the semiconductor industry has been scaling the silicon transistor to achieve faster devices, lower power consumption, and improve device performance. Transistor gate dimensions have become so small that short channel effects and gate leakage have become a significant problem. To address these issues, performance enhancement techniques such as strained silicon are used to improve mobility, while new high-k gate dielectric materials replace silicon oxide to reduce gate leakage. At some point the fundamental limit of silicon will be reached and the semiconductor industry will need to find an alternate solution. The advent of graphene led to the discovery of other layered materials such as the transition metal dichalcogenides. These materials have a layered structure similar to graphene and therefore possess some of the same qualities, but unlike graphene, these materials possess sizeable bandgaps between 1-2 eV making them useful for digital electronic applications. Since initially discovered, most of the research on these films has been from mechanically exfoliated flakes, which are easily produced due to the weak van der Waals force binding the layers together. For these materials to be considered for use in mainstream semiconductor technology, methods need to be explored to grow these films uniformly over a large area. In this research, atomic layer deposition (ALD) was employed as the growth technique used to produce large area uniform thin films of several different transition metal dichalcogenides. By optimizing the ALD growth parameters, it is possible to grow high quality films a few to several monolayers thick over a large area with good uniformity. This has been demonstrated and verified using several physical analytical tests such as Raman spectroscopy, photoluminescence, x-ray photoelectron spectroscopy, x-ray diffraction, transmission electron spectroscopy, and scanning electron microscopy, which show that these films possess the

  19. A self-aligned gate definition process with submicron gaps

    NARCIS (Netherlands)

    Warmerdam, L.F.P.; Aarnink, Antonius A.I.; Holleman, J.; Wallinga, Hans

    1989-01-01

    A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and smaller are fabricated. The spacing is realized by an edge-etch technique, combined with anisotropic plasma etching of the single poly-silicon layer. Straight gaps with minor width variation are

  20. Study of strength of Dsub(y)150 gate valve case, manufactured by centrifugal casting

    International Nuclear Information System (INIS)

    Umanskaya, L.G.; Semenov, P.V.; Tinyakov, V.G.; Babkina, R.I.; Khatuntsev, Eh.V.

    1982-01-01

    A process for manufacturing centrifugal-cast gate valve body is developed. Structural strength of such items, homogeneity, ductile and strength properties over the cross section as well as the metal susceptibility to embrittlement have been investigated. Three cast gate valve bodies have been taken: one - of 20GSL steel - for hydraulic testing, and two - of 15Kh1MFL steel - for investigation into the metal properties across the valve thickness. The strength properties of the centrifugal-cast gate valve body of 15Kh1M1FL steel are stated to meet the specifications. The gate valve metal ductility (delta and PSI) is twice as high as that of a sand-cast valve. The microstructure, strength and ductility are uniform both over wall thickness and over different body cross sections

  1. Quantum design rules for single molecule logic gates.

    Science.gov (United States)

    Renaud, N; Hliwa, M; Joachim, C

    2011-08-28

    Recent publications have demonstrated how to implement a NOR logic gate with a single molecule using its interaction with two surface atoms as logical inputs [W. Soe et al., ACS Nano, 2011, 5, 1436]. We demonstrate here how this NOR logic gate belongs to the general family of quantum logic gates where the Boolean truth table results from a full control of the quantum trajectory of the electron transfer process through the molecule by very local and classical inputs practiced on the molecule. A new molecule OR gate is proposed for the logical inputs to be also single metal atoms, one per logical input.

  2. Hydrogen permeation resistant layers for liquid metal reactors

    International Nuclear Information System (INIS)

    McGuire, J.C.

    1980-03-01

    Reviewing the literature in the tritium diffusion field one can readily see a wide divergence in results for both the response of permeation rate to pressure, and the effect of oxide layers on total permeation rates. The basic mechanism of protective oxide layers is discussed. Two coatings which are less hydrogen permeable than the best naturally occurring oxide are described. The work described is part of an HEDL-ANL cooperative research program on Tritium Permeation in Liquid Metal Cooled Reactors. This includes permeation work on hydrogen, deuterium, and tritium with the hydrogen-deuterium research leading to the developments presented

  3. Adder design using a 5-input majority gate in a novel “multilayer gate design paradigm” for quantum dot cellular automata circuits

    International Nuclear Information System (INIS)

    Kumar, Rohit; Ghosh, Bahniman; Gupta, Shoubhik

    2015-01-01

    This paper proposes a novel design paradigm for circuits designed in quantum dot cellular automata (QCA) technology. Previously reported QCA circuits in the literature have generally been designed in a single layer which is the main logical block in which the inverter and majority gate are on the base layer, except for the parts where multilayer wire crossing was used. In this paper the concept of multilayer wire crossing has been extended to design logic gates in multilayers. Using a 5-input majority gate in a multilayer, a 1-bit and 2-bit adder have been designed in the proposed multilayer gate design paradigm. A comparison has been made with some adders reported previously in the literature and it has been shown that circuits designed in the proposed design paradigm are much more efficient in terms of area, the requirement of QCA cells in the design and the input–output delay of the circuit. Over all, the availability of one additional spatial dimension makes the design process much more flexible and there is scope for the customizability of logic gate designs to make the circuit compact. (paper)

  4. Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

    International Nuclear Information System (INIS)

    Takano, H.; Hosogi, K.; Kato, T.

    1995-01-01

    A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier with an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs

  5. Atomic layer deposition of HfO{sub 2} for integration into three-dimensional metal-insulator-metal devices

    Energy Technology Data Exchange (ETDEWEB)

    Assaud, Loic [Aix Marseille Univ, CNRS, CINAM, Marseille (France); ICMMO-ERIEE, Universite Paris-Sud / Universite Paris-Saclay, CNRS, Orsay (France); Pitzschel, Kristina; Barr, Maissa K.S.; Petit, Matthieu; Hanbuecken, Margrit; Santinacci, Lionel [Aix Marseille Univ, CNRS, CINAM, Marseille (France); Monier, Guillaume [Universite Clermont Auvergne, Universite Blaise Pascal, CNRS, Institut Pascal, Clermont-Ferrand (France)

    2017-12-15

    HfO{sub 2} nanotubes have been fabricated via a template-assisted deposition process for further use in three-dimensional metal-insulator-metal (MIM) devices. HfO{sub 2} thin layers were grown by Atomic Layer Deposition (ALD) in anodic alumina membranes (AAM). The ALD was carried out using tetrakis(ethylmethylamino)hafnium and water as Hf and O sources, respectively. Long exposure durations to the precursors have been used to maximize the penetration depth of the HfO{sub 2} layer within the AAM and the effect of the process temperature was investigated. The morphology, the chemical composition, and the crystal structure were studied as a function of the deposition parameters using transmission and scanning electron microscopies, X-ray photoelectron spectroscopy, and X-ray diffraction, respectively. As expected, the HfO{sub 2} layers grown at low-temperature (T = 150 C) were amorphous, while for a higher temperature (T = 250 C), polycrystalline films were observed. The electrical characterizations have shown better insulating properties for the layers grown at low temperature. Finally, TiN/HfO{sub 2}/TiN multilayers were grown in an AAM as proof-of-concept for three-dimensional MIM nanostructures. (orig.)

  6. Energy loss from internal reflection off metal layers on glass

    Science.gov (United States)

    McDowell, M. W.; Bezuidenhout, D. F.; Klee, H. W.; Theron, E.

    1983-12-01

    The reflection characteristics of metal layers are considered for the situation where the electromagnetic radiation is incident from the glass side. Theoretical and measured reflectance values are presented which indicate that for some metals the reflection has a strong dependence on the refractive index of the incident medium. Some examples are given of recent cases where the above results were an important consideration in the choice of the metallic reflecting material. These results indicate that aluminium should not be automatically considered the best choice for the visible region nor gold for the infra-red.

  7. High performance top-gated indium–zinc–oxide thin film transistors with in-situ formed HfO{sub 2} gate insulator

    Energy Technology Data Exchange (ETDEWEB)

    Song, Yang, E-mail: yang_song@brown.edu [Department of Physics, Brown University, 182 Hope Street, Providence, RI 02912 (United States); Zaslavsky, A. [Department of Physics, Brown University, 182 Hope Street, Providence, RI 02912 (United States); School of Engineering, Brown University, 184 Hope Street, Providence, RI 02912 (United States); Paine, D.C. [School of Engineering, Brown University, 184 Hope Street, Providence, RI 02912 (United States)

    2016-09-01

    We report on top-gated indium–zinc–oxide (IZO) thin film transistors (TFTs) with an in-situ formed HfO{sub 2} gate dielectric insulator. Building on our previous demonstration of high-performance IZO TFTs with Al{sub 2}O{sub 3}/HfO{sub 2} gate dielectric, we now report on a one-step process, in which Hf is evaporated onto the 20 nm thick IZO channel, forming a partially oxidized HfO{sub x} layer, without any additional insulator in-between. After annealing in air at 300 °C, the in-situ reaction between partially oxidized Hf and IZO forms a high quality HfO{sub 2} gate insulator with a low interface trapped charge density N{sub TC} ~ 2.3 × 10{sup 11} cm{sup −2} and acceptably low gate leakage < 3 × 10{sup −7} A/cm{sup 2} at gate voltage V{sub G} = 1 V. The annealed TFTs with gate length L{sub G} = 50 μm have high mobility ~ 95 cm{sup 2}/V ∙ s (determined via the Y-function technique), high on/off ratio ~ 10{sup 7}, near-zero threshold voltage V{sub T} = − 0.02 V, and a subthreshold swing of 0.062 V/decade, near the theoretical limit. The on-current of our proof-of-concept TFTs is relatively low, but can be improved by reducing L{sub G}, indicating that high-performance top-gated HfO{sub 2}-isolated IZO TFTs can be fabricated using a single-step in-situ dielectric formation approach. - Highlights: • High-performance indium–zinc–oxide (IZO) thin film transistors (TFTs). • Single-step in-situ dielectric formation approach simplifies fabrication process. • During anneal, reaction between HfO{sub x} and IZO channel forms a high quality HfO{sub 2} layer. • Gate insulator HfO{sub 2} shows low interface trapped charge and small gate leakage. • TFTs have high mobility, near-zero threshold voltage, and a low subthreshold swing.

  8. AlN and Al oxy-nitride gate dielectrics for reliable gate stacks on Ge and InGaAs channels

    Energy Technology Data Exchange (ETDEWEB)

    Guo, Y.; Li, H.; Robertson, J. [Engineering Department, Cambridge University, Cambridge CB2 1PZ (United Kingdom)

    2016-05-28

    AlN and Al oxy-nitride dielectric layers are proposed instead of Al{sub 2}O{sub 3} as a component of the gate dielectric stacks on higher mobility channels in metal oxide field effect transistors to improve their positive bias stress instability reliability. It is calculated that the gap states of nitrogen vacancies in AlN lie further away in energy from the semiconductor band gap than those of oxygen vacancies in Al{sub 2}O{sub 3}, and thus AlN might be less susceptible to charge trapping and have a better reliability performance. The unfavourable defect energy level distribution in amorphous Al{sub 2}O{sub 3} is attributed to its larger coordination disorder compared to the more symmetrically bonded AlN. Al oxy-nitride is also predicted to have less tendency for charge trapping.

  9. Nonlocal laser annealing to improve thermal contacts between multi-layer graphene and metals

    International Nuclear Information System (INIS)

    Ermakov, Victor A; Alaferdov, Andrei V; Vaz, Alfredo R; Moshkalev, Stanislav A; Baranov, Alexander V

    2013-01-01

    The accuracy of thermal conductivity measurements by the micro-Raman technique for suspended multi-layer graphene flakes has been shown to depend critically on the quality of the thermal contacts between the flakes and the metal electrodes used as the heat sink. The quality of the contacts can be improved by nonlocal laser annealing at increased power. The improvement of the thermal contacts to initially rough metal electrodes is attributed to local melting of the metal surface under laser heating, and increased area of real metal–graphene contact. Improvement of the thermal contacts between multi-layer graphene and a silicon oxide surface was also observed, with more efficient heat transfer from graphene as compared with the graphene–metal case. (paper)

  10. Production of metal fullerene surface layer from various media in the process of steel carbonization

    Directory of Open Access Journals (Sweden)

    KUZEEV Iskander Rustemovich

    2018-04-01

    Full Text Available Studies devoted to production of metal fullerene layer in steels when introducing carbon from organic and inorganic media were performed. Barium carbonate was used as an inorganic medium and petroleum pitch was used as an organic medium. In order to generate the required amount of fullerenes in the process of steel samples carbonization, optimal temperature mode was found. The higher temperature, absorption and cohesive effects become less important and polymeric carbon structures destruction processes become more important. On the bottom the temperature is limited by petroleum pitch softening temperature and its transition to low-viscous state in order to enhance molecular mobility and improve the possibility of their diffusion to metal surface. Identification of fullerenes in the surface modified layer was carried out following the methods of IR-Fourier spectrometry and high-performance liquid chromatography. It was found out that nanocarbon structures, formed during carbonization in barium carbonate and petroleum pitch mediums, possess different morphology. In the process of metal carbonization from carbonates medium, the main role in fullerenes synthesis is belonged to catalytic effect of surface with generation of endohedral derivatives in the surface layer; but in the process of carbonization from pitch medium fullerenes are formed during crystallization of the latter and crystallization centers are of fullerene type. Based on theoretical data and dataof spectral and chromatographic analysis, optimal conditions of metal fullerene layer formation in barium carbonate and petroleum pitch mediums were determined. Low cohesion of layer, modified in barium carbonate medium, with metal basis was discovered. That was caused by limited carbon diffusion in the volume of α-Fe. According to the detected mechanism of fullerenes formation on steel surface in gaseous medium, fullerenes are formed on catalytic centers – ferrum atoms, forming thin metal

  11. Properties of InGaAs/GaAs metal-oxide-semiconductor heterostructure field-effect transistors modified by surface treatment

    Energy Technology Data Exchange (ETDEWEB)

    Gregušová, D., E-mail: Dagmar.Gregusova@savba.sk [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Gucmann, F.; Kúdela, R. [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Mičušík, M. [Polymer Institute of Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84541 (Slovakia); Stoklas, R.; Válik, L. [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Greguš, J. [Faculty of Mathematics, Physics and Informatics, Comenius University, Mlynská dolina, Bratislava SK-84248 (Slovakia); Blaho, M. [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Kordoš, P. [Institute of Electronics and Photonics, Faculty of Electrical Engineering and Information Technology STU, Ilkovičova 3, Bratislava SK-81219 (Slovakia)

    2017-02-15

    Highlights: • AlGaAs/InGaAs/GaAs-based metal oxide semiconductor transistors-MOSHFET. • Thin Al-layer deposited in-situ and oxidize in air – gate insulator. • MOSHFET vs HFET transistor properties, density of traps evaluated. - Abstract: GaAs-based heterostructures exhibit excellent carrier transport properties, mainly the high carrier velocity. An AlGaAs-GaAs heterostructure field-effect transistor (HFET) with an InGaAs channel was prepared using metal-organic chemical vapor deposition (MOVPE). An AlOx layer was formed on the AlGaAs barrier layer by the air-assisted oxidation of a thin Al layer deposited in-situ in an MOVPE reactor immediately after AlGaAs/InGaAs growth. The HFETs and MOSHFETs exhibited a very low trap state density in the order of 10{sup 11} cm{sup −2} eV{sup −1}. Capacitance measurement yielded no significant difference between the HFET and MOSHFET structures. The formation of an AlOx layer modified the surface by partially eliminating surface states that arise from Ga-and As-based native oxides. The presence of an AlOx layer reflected in a reduced gate leakage current, which was evidenced by the two-terminal transistor measurement. Presented preparation procedure and device properties show great potential of AlGaAs/InGaAs-based MOSHFETs.

  12. Thermal Rayleigh-Marangoni convection in a three-layer liquid-metal-battery model

    Science.gov (United States)

    Köllner, Thomas; Boeck, Thomas; Schumacher, Jörg

    2017-05-01

    The combined effects of buoyancy-driven Rayleigh-Bénard convection (RC) and surface tension-driven Marangoni convection (MC) are studied in a triple-layer configuration which serves as a simplified model for a liquid metal battery (LMB). The three-layer model consists of a liquid metal alloy cathode, a molten salt separation layer, and a liquid metal anode at the top. Convection is triggered by the temperature gradient between the hot electrolyte and the colder electrodes, which is a consequence of the release of resistive heat during operation. We present a linear stability analysis of the state of pure thermal conduction in combination with three-dimensional direct numerical simulations of the nonlinear turbulent evolution on the basis of a pseudospectral method. Five different modes of convection are identified in the configuration, which are partly coupled to each other: RC in the upper electrode, RC with internal heating in the molten salt layer, and MC at both interfaces between molten salt and electrode as well as anticonvection in the middle layer and lower electrode. The linear stability analysis confirms that the additional Marangoni effect in the present setup increases the growth rates of the linearly unstable modes, i.e., Marangoni and Rayleigh-Bénard instability act together in the molten salt layer. The critical Grashof and Marangoni numbers decrease with increasing middle layer thickness. The calculated thresholds for the onset of convection are found for realistic current densities of laboratory-sized LMBs. The global turbulent heat transfer follows scaling predictions for internally heated RC. The global turbulent momentum transfer is comparable with turbulent convection in the classical Rayleigh-Bénard case. In summary, our studies show that incorporating Marangoni effects generates smaller flow structures, alters the velocity magnitudes, and enhances the turbulent heat transfer across the triple-layer configuration.

  13. Gate length variation effect on performance of gate-first self-aligned In₀.₅₃Ga₀.₄₇As MOSFET.

    Science.gov (United States)

    Mohd Razip Wee, Mohd F; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y

    2013-01-01

    A multi-gate n-type In₀.₅₃Ga₀.₄₇As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm(2)/Vs are achieved for the gate length and width of 0.2 µm and 30 µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10(-8) A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared.

  14. Gate Length Variation Effect on Performance of Gate-First Self-Aligned In0.53Ga0.47As MOSFET

    Science.gov (United States)

    Mohd Razip Wee, Mohd F.; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y.

    2013-01-01

    A multi-gate n-type In0.53Ga0.47As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm2/Vs are achieved for the gate length and width of 0.2 µm and 30µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10−8 A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared. PMID:24367548

  15. UN2−x layer formed on uranium metal by glow plasma nitriding

    International Nuclear Information System (INIS)

    Long, Zhong; Hu, Yin; Chen, Lin; Luo, Lizhu; Liu, Kezhao; Lai, Xinchun

    2015-01-01

    Highlights: • We used a very simple method to prepare nitride layer on uranium metal surface. • This modified layer is nitrogen-rich nitride, which should be written as UN 2−x . • TEM images show the nitride layer is composed of nano-sized grains. • XPS analysis indicates there is uranium with abnormal low valence in the nitride. - Abstract: Glow plasma nitriding is a simple and economical surface treatment method, and this technology was used to prepare nitride layer on the surface of uranium metal with thickness of several microns. The composition and structure of the nitride layer were analyzed by AES and XRD, indicating that this modified layer is nitrogen-rich uranium nitride, which should be written as UN 2−x . TEM images show the nitride layer is composed of nano-sized grains, with compact structure. And XPS analysis indicates there is uranium with abnormal low valence existing in the nitride. After the treated uranium storage in air for a long time, oxygen just entered the surface several nanometers, showing the nitride layer has excellent oxidation resistance. The mechanism of nitride layer formation and low valence uranium appearance is discussed

  16. Valley polarization in magnetically doped single-layer transition-metal dichalcogenides

    KAUST Repository

    Cheng, Yingchun; Zhang, Q. Y.; Schwingenschlö gl, Udo

    2014-01-01

    We demonstrate that valley polarization can be induced and controlled in semiconducting single-layer transition-metal dichalcogenides by magnetic doping, which is important for spintronics, valleytronics, and photonics devices. As an example, we

  17. Post-assembly transformations of porphyrin-containing metal-organic framework (MOF) films fabricated via automated layer-by-layer coordination

    KAUST Repository

    So, Monica; Beyzavi, M. Hassan; Sawhney, Rohan; Shekhah, Osama; Eddaoudi, Mohamed; Al-Juaid, Salih Salem; Hupp, Joseph T.; Farha, Omar K.

    2015-01-01

    Herein, we demonstrate the robustness of layer-by-layer (LbL)-assembled, pillared-paddlewheel-type MOF films toward conversion to new or modified MOFs via solvent-assisted linker exchange (SALE) and post-assembly linker metalation. Further, we show that LbL synthesis can afford MOFs that have proven inaccessible through other de novo strategies.

  18. ZnO nanowire-based nano-floating gate memory with Pt nanocrystals embedded in Al2O3 gate oxides

    International Nuclear Information System (INIS)

    Yeom, Donghyuk; Kang, Jeongmin; Lee, Myoungwon; Jang, Jaewon; Yun, Junggwon; Jeong, Dong-Young; Yoon, Changjoon; Koo, Jamin; Kim, Sangsig

    2008-01-01

    The memory characteristics of ZnO nanowire-based nano-floating gate memory (NFGM) with Pt nanocrystals acting as the floating gate nodes were investigated in this work. Pt nanocrystals were embedded between Al 2 O 3 tunneling and control oxide layers deposited on ZnO nanowire channels. For a representative ZnO nanowire-based NFGM with embedded Pt nanocrystals, a threshold voltage shift of 3.8 V was observed in its drain current versus gate voltage (I DS -V GS ) measurements for a double sweep of the gate voltage, revealing that the deep effective potential wells built into the nanocrystals provide our NFGM with a large charge storage capacity. Details of the charge storage effect observed in this memory device are discussed in this paper

  19. Electrical characteristics of vapor deposited amorphous MoS2 two-terminal structures and back gate thin film transistors with Al, Au, Cu and Ni-Au contacts

    International Nuclear Information System (INIS)

    Kouvatsos, Dimitrios N.; Papadimitropoulos, Georgios; Spiliotis, Thanassis; Vasilopoulou, Maria; Davazoglou, Dimitrios; Barreca, Davide; Gasparotto, Alberto

    2015-01-01

    Amorphous molybdenum sulphide (a-MoS 2 ) thin films were deposited at near room temperature on oxidized silicon substrates and were electrically characterized with the use of two-terminal structures and of back-gated thin film transistors utilizing the substrate silicon as gate. Current-voltage characteristics were extracted for various metals used as pads, showing significant current variations attributable to different metal-sulphide interface properties and contact resistances, while the effect of a forming gas anneal was determined. With the use of heavily doped silicon substrates and aluminum backside deposition, thin film transistor (TFT) structures with the a-MoS 2 film as active layer were fabricated and characterized. Transfer characteristics showing a gate field effect, despite a leakage often present, were extracted for these devices, indicating that high mobility devices can be fabricated. SEM and EDXA measurements were also performed in an attempt to clarify issues related to material properties and fabrication procedures, so as to achieve a reliable and optimized a-MoS 2 TFT fabrication process. (copyright 2015 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  20. Gate-modulated conductance of few-layer WSe2 field-effect transistors in the subgap regime: Schottky barrier transistor and subgap impurity states

    International Nuclear Information System (INIS)

    Wang, Junjie; Feng, Simin; Rhodes, Daniel; Balicas, Luis; Nguyen, Minh An T.; Watanabe, K.; Taniguchi, T.; Mallouk, Thomas E.; Terrones, Mauricio; Zhu, J.

    2015-01-01

    Two key subjects stand out in the pursuit of semiconductor research: material quality and contact technology. The fledging field of atomically thin transition metal dichalcogenides (TMDCs) faces a number of challenges in both efforts. This work attempts to establish a connection between the two by examining the gate-dependent conductance of few-layer (1-5L) WSe 2 field effect devices. Measurements and modeling of the subgap regime reveal Schottky barrier transistor behavior. We show that transmission through the contact barrier is dominated by thermionic field emission (TFE) at room temperature, despite the lack of intentional doping. The TFE process arises due to a large number of subgap impurity states, the presence of which also leads to high mobility edge carrier densities. The density of states of such impurity states is self-consistently determined to be approximately 1–2 × 10 13 /cm 2 /eV in our devices. We demonstrate that substrate is unlikely to be a major source of the impurity states and suspect that lattice defects within the material itself are primarily responsible. Our experiments provide key information to advance the quality and understanding of TMDC materials and electrical devices

  1. Copper Benzenetricarboxylate Metal-Organic Framework Nucleation Mechanisms on Metal Oxide Powders and Thin Films formed by Atomic Layer Deposition.

    Science.gov (United States)

    Lemaire, Paul C; Zhao, Junjie; Williams, Philip S; Walls, Howard J; Shepherd, Sarah D; Losego, Mark D; Peterson, Gregory W; Parsons, Gregory N

    2016-04-13

    Chemically functional microporous metal-organic framework (MOF) crystals are attractive for filtration and gas storage applications, and recent results show that they can be immobilized on high surface area substrates, such as fiber mats. However, fundamental knowledge is still lacking regarding initial key reaction steps in thin film MOF nucleation and growth. We find that thin inorganic nucleation layers formed by atomic layer deposition (ALD) can promote solvothermal growth of copper benzenetricarboxylate MOF (Cu-BTC) on various substrate surfaces. The nature of the ALD material affects the MOF nucleation time, crystal size and morphology, and the resulting MOF surface area per unit mass. To understand MOF nucleation mechanisms, we investigate detailed Cu-BTC MOF nucleation behavior on metal oxide powders and Al2O3, ZnO, and TiO2 layers formed by ALD on polypropylene substrates. Studying both combined and sequential MOF reactant exposure conditions, we find that during solvothermal synthesis ALD metal oxides can react with the MOF metal precursor to form double hydroxy salts that can further convert to Cu-BTC MOF. The acidic organic linker can also etch or react with the surface to form MOF from an oxide metal source, which can also function as a nucleation agent for Cu-BTC in the mixed solvothermal solution. We discuss the implications of these results for better controlled thin film MOF nucleation and growth.

  2. Large scale metal-free synthesis of graphene on sapphire and transfer-free device fabrication.

    Science.gov (United States)

    Song, Hyun Jae; Son, Minhyeok; Park, Chibeom; Lim, Hyunseob; Levendorf, Mark P; Tsen, Adam W; Park, Jiwoong; Choi, Hee Cheul

    2012-05-21

    Metal catalyst-free growth of large scale single layer graphene film on a sapphire substrate by a chemical vapor deposition (CVD) process at 950 °C is demonstrated. A top-gated graphene field effect transistor (FET) device is successfully fabricated without any transfer process. The detailed growth process is investigated by the atomic force microscopy (AFM) studies.

  3. Influence of carbon monoxide to the surface layer of uranium metal and its oxides

    International Nuclear Information System (INIS)

    Wang Xiaoling; Fu Yibei; Xie Renshou; Huang Ruiliang

    1996-09-01

    The surface structures of uranium metal and triuranium octaoxide (U 3 O 8 ) and the influence of carbon monoxide to the surface layers have been studied by X-ray photoelectron spectroscopy (XPS). After exposure to carbon monoxide, contents of oxygen in the surface oxides of uranium metal and U 3 O 8 are decreased and O/U ratios decrease 7.2%, 8.0% respectively. The investigation indicated the surface layers of uranium metal and its oxides were forbidden to further oxidation in the atmosphere of carbon monoxide. (11 refs., 9 figs., 2 tabs.)

  4. Electron emission from a double-layer metal under femtosecond laser irradiation

    Energy Technology Data Exchange (ETDEWEB)

    Li, Shuchang; Li, Suyu; Jiang, Yuanfei; Chen, Anmin, E-mail: amchen@jlu.edu.cn; Ding, Dajun; Jin, Mingxing, E-mail: mxjin@jlu.edu.cn

    2015-01-01

    In this paper we theoretically investigate electron emission during femtosecond laser ablation of single-layer metal (copper) and double-layer structures. The double-layer structure is composed of a surface layer (copper) and a substrate layer (gold or chromium). The calculated results indicate that the double-layer structure brings a change to the electron emission from the copper surface. Compared with the ablation of a single-layer, a double-layer structure may be helpful to decrease the relaxation time of the electron temperature, and optimize the electron emission by diminishing the tailing phenomenon under the same absorbed laser fluence. With the increase of the absorbed laser fluence, the effect of optimization becomes significant. This study provides a way to optimize the electron emission which can be beneficial to generate laser induced ultrafast electron pulse sources.

  5. Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

    Science.gov (United States)

    Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

    2018-06-01

    The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

  6. The gate oxide integrity of CVD tungsten polycide

    International Nuclear Information System (INIS)

    Wu, N.W.; Su, W.D.; Chang, S.W.; Tseng, M.F.

    1988-01-01

    CVD tungsten polycide has been demonstrated as a good gate material in recent very large scale integration (VLSI) technology. CVD tungsten silicide offers advantages of low resistivity, high temperature stability and good step coverage. On the other hand, the polysilicon underlayer preserves most characteristics of the polysilicon gate and acts as a stress buffer layer to absorb part of the thermal stress origin from the large thermal expansion coefficient of tungsten silicide. Nevertheless, the gate oxide of CVD tungsten polycide is less stable or reliable than that of polysilicon gate. In this paper, the gate oxide integrity of CVD tungsten polycide with various thickness combinations and different thermal processes have been analyzed by several electrical measurements including breakdown yield, breakdown fluence, room temperature TDDB, I-V characteristics, electron traps and interface state density

  7. Diffusion barrier performance of novel Ti/TaN double layers for Cu metallization

    International Nuclear Information System (INIS)

    Zhou, Y.M.; He, M.Z.; Xie, Z.

    2014-01-01

    Highlights: • Novel Ti/TaN double layers offering good stability as a barrier against Cu metallization have been made achievable by annealing in vacuum. • The Ti/TaN double layers improved the adhesion with Cu thin films and showed good diffusion barrier between Cu and SiO 2 /Si up to the annealing condition. • The failure mechanism of Ti/TaN bi-layer is similar with the Cu/TaN/Si metallization system in which Cu atoms diffuse through the grain boundary of barrier and react with silicon to form Cu 3 Si. - Abstract: Novel Ti/TaN double layers offering good stability as a barrier against Cu metallization have been made achievable by annealing in vacuum better than 1 × 10 −3 Pa. Ti/TaN double layers were formed on SiO 2 /Si substrates by DC magnetron sputtering and then the properties of Cu/Ti/TaN/SiO 2 /Si film stacks were studied. It was found that the Ti/TaN double layers provide good diffusion barrier between Cu and SiO 2 /Si up to 750 °C for 30 min. The XRD, Auger and EDS results show that the Cu–Si compounds like Cu 3 Si were formed by Cu diffusion through Ti/TaN barrier for the 800 °C annealed samples. It seems that the improved diffusion barrier property of Cu/Ti/TaN/SiO 2 /Si stack is due to the diffusion of nitrogen along the grain boundaries in Ti layer, which would decrease the defects in Ti film and block the diffusion path for Cu diffusion with increasing annealing temperature. The failure mechanism of Ti/TaN bi-layer is similar to the Cu/TaN/Si metallization system in which Cu atoms diffuse through the grain boundary of barrier and react with silicon to form Cu 3 Si

  8. Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene–graphene composite layers for flexible thin film transistors with a polymer gate dielectric

    International Nuclear Information System (INIS)

    Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

    2014-01-01

    Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene–graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene–graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm 2  V −1  s −1 and a threshold voltage of −0.7 V at V gs = −40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm 2  V −1  s −1 and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies. (paper)

  9. Analytical modelling of a thin liquid metal layer submitted to an ac magnetic field

    Energy Technology Data Exchange (ETDEWEB)

    Hinaje, M [Groupe de Recherche en Electrotechnique et Electronique de Nancy, 2 avenue de la Foret de Haye, 54516 Vandoeuvre-les-Nancy (France); Vinsard, G [Laboratoire d' Energetique et de Mecanique Theorique et Appliquee, 2 avenue de la Foret de Haye, 54516 Vandoeuvre-les-Nancy (France); Dufour, S [Laboratoire d' Energetique et de Mecanique Theorique et Appliquee, 2 avenue de la Foret de Haye, 54516 Vandoeuvre-les-Nancy (France)

    2006-07-07

    A cylindrical thin liquid metal layer is submitted to a uniform ac magnetic field. When the intensity of the electromagnetic field exceeds a critical value, an opening in the liquid is shaped from outside to inside. At a given intensity of the electromagnetic field, this opening is in a frozen state, that is, the liquid metal layer reaches a new equilibrium shape. In this paper, we show that this equilibrium corresponds to a minimum of the total energy of the system. This total energy is equal to the sum of the magnetic energy and the mechanical energy. The magnetic energy is computed by assuming that the induced eddy current flowing through the liquid metal layer is concentrated in the cross-section S{sub c} equal to the product of the skin depth and the thickness of the layer. This assumption leads us to study an equivalent electrical circuit. The mechanical energy is composed of the potential energy and the surface energy.

  10. Analytical modelling of a thin liquid metal layer submitted to an ac magnetic field

    International Nuclear Information System (INIS)

    Hinaje, M; Vinsard, G; Dufour, S

    2006-01-01

    A cylindrical thin liquid metal layer is submitted to a uniform ac magnetic field. When the intensity of the electromagnetic field exceeds a critical value, an opening in the liquid is shaped from outside to inside. At a given intensity of the electromagnetic field, this opening is in a frozen state, that is, the liquid metal layer reaches a new equilibrium shape. In this paper, we show that this equilibrium corresponds to a minimum of the total energy of the system. This total energy is equal to the sum of the magnetic energy and the mechanical energy. The magnetic energy is computed by assuming that the induced eddy current flowing through the liquid metal layer is concentrated in the cross-section S c equal to the product of the skin depth and the thickness of the layer. This assumption leads us to study an equivalent electrical circuit. The mechanical energy is composed of the potential energy and the surface energy

  11. Graphene layer encapsulated metal nanoparticles as a new type of non-precious metal catalysts for oxygen reduction

    DEFF Research Database (Denmark)

    Hu, Yang; Zhong, Lijie; Jensen, Jens Oluf

    2016-01-01

    Cheap and efficient non-precious metal catalysts for oxygen reduction have been a focus of research in the field of low-temperature fuel cells. This review is devoted to a brief summary of the recent work on a new type of catalysts, i.e., the graphene layer encapsulated metal nanoparticles....... The discussion is focused on the synthesis, structure, mechanism, performance, and further research....

  12. Experimental study of conjugate heat transfer from liquid metal layer cooled by overlying freon

    International Nuclear Information System (INIS)

    Cho, J.S.; Suh, K.Y.; Chung, C.H.; Park, R.J.; Kim, S.B.

    2001-01-01

    Steady-state and transient experiments were performed for the heat transfer from the liquid metal pool with overlying Freon (R113) coolant in the process of boiling. The simulant molten pool material is tin (Sn) with the melting temperature of 232 Celsius degrees. The metal pool is heated from the bottom surface and the coolant is injected onto the molten metal pool. Tests were conducted under the condition of the bottom surface heating in the test section and the forced convection of the R113 coolant being injected onto the molten metal pool. The bottom heating condition was varied from 8 kW to 14 kW. The temperature distributions of the metal layer and coolant were obtained in the steady-state experiment. The boiling mechanism of the R113 coolant was changed from the nucleate boiling to film boiling in the transient experiment. The critical heat flux (CHF) phenomenon was observed during the transition from the nucleate boiling to the film boiling. Also, the Nusselt (Nu) number and the Rayleigh (Ra) number in the molten metal pool region were obtained as functions of time. Analysis was done for the relationship between the heat flux and the temperature difference between the metal layer surface and the boiling coolant. In this experiment, the heat transfer is achieved with accompanying solidification in the molten metal pool by the boiling R113 coolant there above. The present test results of the natural convection heat transfer on the molten metal pool are higher than those of the liquid metal natural convection heat transfer without coolant boiling. It can be interpreted that the heat transfer rate is enhanced by the overlying boiling coolant having the high heat removal rate. Analysis of the relationship between the heat flux and the difference between the metal layer surface temperature and the coolant bulk boiling temperature revealed that the CHF occurs when the temperature difference reaches a neighborhood of 50 Celsius degrees. Also, if the temperature

  13. The attenuation of temperature oscillations in passing through liquid metal boundary layers

    International Nuclear Information System (INIS)

    Lawn, C.J.

    1975-08-01

    One aspect of predicting the endurance of components subject to thermal fatigue in liquid metal cooled reactors is the extent to which oscillations in fluid temperature are transmitted to metal surfaces, such as the above-core structure. The first geometry considered is that of a solid plate in contact with a layer of stagnant fluid, in which temperature oscillations are imposed at a given distance from the plate. Transmission through a laminar boundary layer developing over the plate surface is then considered. An approximate calculation based on the slug-flow analysis of Sucec (1975) is developed. (U.K.)

  14. Dynamic partitioning of nanoparticulate metal species between gel layers and aqueous media

    NARCIS (Netherlands)

    Veeken, van der P.L.R.

    2010-01-01

    This thesis deals with several aspects of the use of Diffusive Gradient in Thin film (DGT) and Diffusive Equilibriation in Thin film (DET) in dynamic metal speciation analysis. It has a clear focus on the properties of the diffusive gel layer, and their possible impact on metal speciation

  15. Analytical models for the 2DEG concentration and gate leakage current in AlGaN/GaN HEMTs

    Science.gov (United States)

    Ahmed, Nadim; Dutta, Aloke K.

    2017-06-01

    In this paper, we present a completely analytical model for the 2DEG concentration in AlGaN/GaN HEMTs as a function of gate bias, considering the donor-like trap states present at the metal/AlGaN interface to be the primary source of 2DEG carriers. To the best of our knowledge, this is a completely new contribution of this work. The electric field in the AlGaN layer is calculated using this model, which is further used to model the gate leakage current under reverse bias. We have modified the existing TTT (Thermionic Trap-Assisted Tunneling) current model, taking into account the effect of both metal/AlGaN interface traps as well as AlGaN bulk traps. The gate current under forward bias is also modeled using the existing thermionic emission model, approximating it by its Taylor series expansion. To take into account the effect of non-zero drain-source bias (VDS), an empirical fitting parameter is introduced in order to model the channel voltage in terms of VDS. The results of our models have been compared with the experimental data reported in the literature for three different devices, and the match is found to be excellent for both forward and reverse bias as well as for zero and non-zero VDS.

  16. Organic-inorganic perovskites containing trivalent metal halide layers: the templating influence of the organic cation layer.

    Science.gov (United States)

    Mitzi, D B

    2000-12-25

    Thin sheetlike crystals of the metal-deficient perovskites (H2AEQT)M2/3I4 [M = Bi or Sb; AEQT = 5,5"'-bis-(aminoethyl)-2,2':5',2'':5'',2'''-quaterthiophene] were formed from slowly cooled ethylene glycol/2-butanol solutions containing the bismuth(III) or antimony(III) iodide and AEQT.2HI salts. Each structure was refined in a monoclinic (C2/m) subcell, with the lattice parameters a = 39.712(13) A, b = 5.976(2) A, c = 6.043(2) A, beta = 92.238(5) degrees, and Z = 2 for M = Bi and a = 39.439(7) A, b = 5.952(1) A, c = 6.031(1) A, beta = 92.245(3) degrees, and Z = 2 for M = Sb. The trivalent metal cations locally adopt a distorted octahedral coordination, with M-I bond lengths ranging from 3.046(1) to 3.218(3) A (3.114 A average) for M = Bi and 3.012(1) to 3.153(2) A (3.073 A average) for M = Sb. The new organic-inorganic hybrids are the first members of a metal-deficient perovskite family consisting of (Mn+)2/nV(n-2)/nX4(2-) sheets, where V represents a vacancy (generally left out of the formula) and the metal cation valence, n, is greater than 2. The organic layers in the AEQT-based organic-inorganic hybrids feature edge-to-face aromatic interactions among the rigid, rodlike quaterthiophene moieties, which may help to stabilize the unusual metal-deficient layered structures.

  17. Prediction of transmittance spectra for transparent composite electrodes with ultra-thin metal layers

    Energy Technology Data Exchange (ETDEWEB)

    Zhao, Zhao; Alford, T. L., E-mail: TA@asu.edu [School for Engineering of Matter, Transport, and Energy, Arizona State University, Tempe, Arizona 85287 (United States); Khorasani, Arash Elhami [ON Semiconductor Corp., Phoenix, Arizona 85005 (United States); Theodore, N. D. [CHD-Fab, Freescale Semiconductor Inc., Tempe, Arizona 85224 (United States); Dhar, A. [Intel Corp., 2501 NW 229th Ave, Hillsboro, Oregon 97124 (United States)

    2015-11-28

    Recent interest in indium-free transparent composite-electrodes (TCEs) has motivated theoretical and experimental efforts to better understand and enhance their electrical and optical properties. Various tools have been developed to calculate the optical transmittance of multilayer thin-film structures based on the transfer-matrix method. However, the factors that affect the accuracy of these calculations have not been investigated very much. In this study, two sets of TCEs, TiO{sub 2}/Au/TiO{sub 2} and TiO{sub 2}/Ag/TiO{sub 2}, were fabricated to study the factors that affect the accuracy of transmittance predictions. We found that the predicted transmittance can deviate significantly from measured transmittance for TCEs that have ultra-thin plasmonic metal layers. The ultrathin metal layer in the TCE is typically discontinuous. When light interacts with the metallic islands in this discontinuous layer, localized surface plasmons are generated. This causes extra light absorption, which then leads to the actual transmittance being lower than the predicted transmittance.

  18. Monolayer field effect transistor as a probe of electronic defects in organic semiconducting layers at organic/inorganic hetero-junction interface

    International Nuclear Information System (INIS)

    Park, Byoungnam

    2016-01-01

    The origin of a large negative threshold voltage observed in monolayer (ML) field effect transistors (FETs) is explored using in-situ electrical measurements through confining the thickness of an active layer to the accumulation layer thickness. Using ML pentacene FETs combined with gated multiple-terminal devices and atomic force microscopy, the effect of electronic and structural evolution of a ML pentacene film on the threshold voltage in an FET, proportional to the density of deep traps, was probed, revealing that a large negative threshold voltage found in ML FETs results from the pentacene/SiO_2 and pentacene/metal interfaces. More importantly, the origin of the threshold voltage difference between ML and thick FETs is addressed through a model in which the effective charge transport layer is transitioned from the pentacene layer interfacing with the SiO_2 gate dielectric to the upper layers with pentacene thickness increasing evidenced by pentacene coverage dependent threshold voltage measurements. - Highlights: • The origin of a large negative threshold voltage in accumulation layer is revealed. • Electronic localized states at the nanometer scale are separately probed from the bulk. • The second monolayer becomes the effective charge transport layer governing threshold voltage.

  19. Role of nanorods insertion layer in ZnO-based electrochemical metallization memory cell

    Science.gov (United States)

    Mangasa Simanjuntak, Firman; Singh, Pragya; Chandrasekaran, Sridhar; Juanda Lumbantoruan, Franky; Yang, Chih-Chieh; Huang, Chu-Jie; Lin, Chun-Chieh; Tseng, Tseung-Yuen

    2017-12-01

    An engineering nanorod array in a ZnO-based electrochemical metallization device for nonvolatile memory applications was investigated. A hydrothermally synthesized nanorod layer was inserted into a Cu/ZnO/ITO device structure. Another device was fabricated without nanorods for comparison, and this device demonstrated a diode-like behavior with no switching behavior at a low current compliance (CC). The switching became clear only when the CC was increased to 75 mA. The insertion of a nanorods layer induced switching characteristics at a low operation current and improve the endurance and retention performances. The morphology of the nanorods may control the switching characteristics. A forming-free electrochemical metallization memory device having long switching cycles (>104 cycles) with a sufficient memory window (103 times) for data storage application, good switching stability and sufficient retention was successfully fabricated by adjusting the morphology and defect concentration of the inserted nanorod layer. The nanorod layer not only contributed to inducing resistive switching characteristics but also acted as both a switching layer and a cation diffusion control layer.

  20. Superconductivity in Layered Organic Metals

    Directory of Open Access Journals (Sweden)

    Jochen Wosnitza

    2012-04-01

    Full Text Available In this short review, I will give an overview on the current understanding of the superconductivity in quasi-two-dimensional organic metals. Thereby, I will focus on charge-transfer salts based on bis(ethylenedithiotetrathiafulvalene (BEDT-TTF or ET for short. In these materials, strong electronic correlations are clearly evident, resulting in unique phase diagrams. The layered crystallographic structure leads to highly anisotropic electronic as well as superconducting properties. The corresponding very high orbital critical field for in-plane magnetic-field alignment allows for the occurrence of the Fulde–Ferrell– Larkin–Ovchinnikov state as evidenced by thermodynamic measurements. The experimental picture on the nature of the superconducting state is still controversial with evidence both for unconventional as well as for BCS-like superconductivity.

  1. Oxygen vacancy defect engineering using atomic layer deposited HfAlOx in multi-layered gate stack

    Science.gov (United States)

    Bhuyian, M. N.; Sengupta, R.; Vurikiti, P.; Misra, D.

    2016-05-01

    This work evaluates the defects in high quality atomic layer deposited (ALD) HfAlOx with extremely low Al (estimated by the high temperature current voltage measurement shows that the charged oxygen vacancies, V+/V2+, are the primary source of defects in these dielectrics. When Al is added in HfO2, the V+ type defects with a defect activation energy of Ea ˜ 0.2 eV modify to V2+ type to Ea ˜ 0.1 eV with reference to the Si conduction band. When devices were stressed in the gate injection mode for 1000 s, more V+ type defects are generated and Ea reverts back to ˜0.2 eV. Since Al has a less number of valence electrons than do Hf, the change in the co-ordination number due to Al incorporation seems to contribute to the defect level modifications. Additionally, the stress induced leakage current behavior observed at 20 °C and at 125 °C demonstrates that the addition of Al in HfO2 contributed to suppressed trap generation process. This further supports the defect engineering model as reduced flat-band voltage shifts were observed at 20 °C and at 125 °C.

  2. Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

    Science.gov (United States)

    Kumar, Manoj; Pratap, Yogesh; Haldar, Subhasis; Gupta, Mridula; Gupta, R. S.

    2017-12-01

    In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported, to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions. This novel structure offers low barrier height at the source and offers high ON-state current. The I ON/I OFF of ISE-CGAA-SB-MOSFET increases by 1177 times and offers steeper subthreshold slope (~60 mV/decade). However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate, dual metal gate, single metal gate with ISE, and dual metal gate with ISE has been presented. The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design. The numerical simulation is performed using the ATLAS-3D device simulator.

  3. FTIR spectroscopy structural analysis of the interaction between Lactobacillus kefir S-layers and metal ions

    Science.gov (United States)

    Gerbino, E.; Mobili, P.; Tymczyszyn, E.; Fausto, R.; Gómez-Zavaglia, A.

    2011-02-01

    FTIR spectroscopy was used to structurally characterize the interaction of S-layer proteins extracted from two strains of Lactobacillus kefir (the aggregating CIDCA 8348 and the non-aggregating JCM 5818) with metal ions (Cd +2, Zn +2, Pb +2 and Ni +2). The infrared spectra indicate that the metal/protein interaction occurs mainly through the carboxylate groups of the side chains of Asp and Glut residues, with some contribution of the NH groups belonging to the peptide backbone. The frequency separation between the νCOO - anti-symmetric and symmetric stretching vibrations in the spectra of the S-layers in presence of the metal ions was found to be ca. 190 cm -1 for S-layer CIDCA 8348 and ca. 170 cm -1 for JCM 5818, denoting an unidentate coordination in both cases. Changes in the secondary structures of the S-layers induced by the interaction with the metal ions were also noticed: a general trend to increase the amount of β-sheet structures and to reduce the amount of α-helices was observed. These changes allow the proteins to adjust their structure to the presence of the metal ions at minimum energy expense, and accordingly, these adjustments were found to be more important for the bigger ions.

  4. Gate-last TiN/HfO2 band edge effective work functions using low-temperature anneals and selective cladding to control interface composition

    KAUST Repository

    Hinkle, C. L.; Galatage, R. V.; Chapman, R. A.; Vogel, E. M.; Alshareef, Husam N.; Freeman, C.; Christensen, M.; Wimmer, E.; Niimi, H.; Li-Fatou, A.; Shaw, J. B.; Chambers, J. J.

    2012-01-01

    Silicon N-metal-oxide-semiconductor (NMOS) and P-metal-oxide-semiconductor (PMOS) band edge effective work functions and the correspondingly low threshold voltages (Vt) are demonstrated using standard fab materials and processes in a gate-last scheme employing low-temperature anneals and selective cladding layers. Al diffusion from the cladding to the TiN/HfO2interface during forming gas anneal together with low O concentration in the TiN enables low NMOS Vt. The use of non-migrating W cladding along with experimentally detected N-induced dipoles, produced by increased oxygen in the TiN, facilitates low PMOS Vt.

  5. Gate-last TiN/HfO2 band edge effective work functions using low-temperature anneals and selective cladding to control interface composition

    KAUST Repository

    Hinkle, C. L.

    2012-04-09

    Silicon N-metal-oxide-semiconductor (NMOS) and P-metal-oxide-semiconductor (PMOS) band edge effective work functions and the correspondingly low threshold voltages (Vt) are demonstrated using standard fab materials and processes in a gate-last scheme employing low-temperature anneals and selective cladding layers. Al diffusion from the cladding to the TiN/HfO2interface during forming gas anneal together with low O concentration in the TiN enables low NMOS Vt. The use of non-migrating W cladding along with experimentally detected N-induced dipoles, produced by increased oxygen in the TiN, facilitates low PMOS Vt.

  6. Metallic layer-by-layer photonic crystals for linearly-polarized thermal emission and thermophotovoltaic device including same

    Science.gov (United States)

    Lee, Jae-Hwang; Ho, Kai-Ming; Constant, Kristen P.

    2016-07-26

    Metallic thermal emitters consisting of two layers of differently structured nickel gratings on a homogeneous nickel layer are fabricated by soft lithography and studied for polarized thermal radiation. A thermal emitter in combination with a sub-wavelength grating shows a high extinction ratio, with a maximum value close to 5, in a wide mid-infrared range from 3.2 to 7.8 .mu.m, as well as high emissivity up to 0.65 at a wavelength of 3.7 .mu.m. All measurements show good agreement with theoretical predictions. Numerical simulations reveal that a high electric field exists within the localized air space surrounded by the gratings and the intensified electric-field is only observed for the polarizations perpendicular to the top sub-wavelength grating. This result suggests how the emissivity of a metal can be selectively enhanced at a certain range of wavelengths for a given polarization.

  7. Solvothermal synthesis of gallium-indium-zinc-oxide nanoparticles for electrolyte-gated transistors.

    Science.gov (United States)

    Santos, Lídia; Nunes, Daniela; Calmeiro, Tomás; Branquinho, Rita; Salgueiro, Daniela; Barquinha, Pedro; Pereira, Luís; Martins, Rodrigo; Fortunato, Elvira

    2015-01-14

    Solution-processed field-effect transistors are strategic building blocks when considering low-cost sustainable flexible electronics. Nevertheless, some challenges (e.g., processing temperature, reliability, reproducibility in large areas, and cost effectiveness) are requirements that must be surpassed in order to achieve high-performance transistors. The present work reports electrolyte-gated transistors using as channel layer gallium-indium-zinc-oxide nanoparticles produced by solvothermal synthesis combined with a solid-state electrolyte based on aqueous dispersions of vinyl acetate stabilized with cellulose derivatives, acrylic acid ester in styrene and lithium perchlorate. The devices fabricated using this approach display a ION/IOFF up to 1 × 10(6), threshold voltage (VTh) of 0.3-1.9 V, and mobility up to 1 cm(2)/(V s), as a function of gallium-indium-zinc-oxide ink formulation and two different annealing temperatures. These results validates the usage of electrolyte-gated transistors as a viable and promising alternative for nanoparticle based semiconductor devices as the electrolyte improves the interface and promotes a more efficient step coverage of the channel layer, reducing the operating voltage when compared with conventional dielectrics gating. Moreover, it is shown that by controlling the applied gate potential, the operation mechanism of the electrolyte-gated transistors can be modified from electric double layer to electrochemical doping.

  8. Study of the interface stability of the metal (Mo, Ni, Pd/HfO2/AlN/InGaAs MOS devices

    Directory of Open Access Journals (Sweden)

    Huy Binh Do

    2017-08-01

    Full Text Available The degeneration of the metal/HfO2 interfaces for Mo, Ni, and Pd gate metals was studied in this paper. An unstable PdOx interfacial layer formed at the Pd/HfO2 interface, inducing the oxygen segregation for the Pd/HfO2/InGaAs metal oxide capacitor (MOSCAP. The low dissociation energy for the Pd-O bond was the reason for oxygen segregation. The PdOx layer contains O2− and OH− ions which are mobile during thermal annealing and electrical stress test. The phenomenon was not observed for the (Mo, Ni/HfO2/InGaAs MOSCAPs. The results provide the guidance for choosing the proper metal electrode for the InGaAs based MOSFET.

  9. Gate-modulated conductance of few-layer WSe{sub 2} field-effect transistors in the subgap regime: Schottky barrier transistor and subgap impurity states

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Junjie; Feng, Simin [Department of Physics, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Rhodes, Daniel; Balicas, Luis [National High Magnetic Field Lab, Florida State University, Tallahassee, Florida 32310 (United States); Nguyen, Minh An T. [Department of Chemistry, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Watanabe, K.; Taniguchi, T. [National Institute for Materials Science, 1-1 Namiki, Tsukuba 305-0044 (Japan); Mallouk, Thomas E. [Department of Physics, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Department of Chemistry, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Department of Biochemistry and Molecular Biology, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Terrones, Mauricio [Department of Physics, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Department of Chemistry, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Department of Materials Science and Engineering, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Center for 2-Dimensional and Layered Materials, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Zhu, J., E-mail: jzhu@phys.psu.edu [Department of Physics, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Center for 2-Dimensional and Layered Materials, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States)

    2015-04-13

    Two key subjects stand out in the pursuit of semiconductor research: material quality and contact technology. The fledging field of atomically thin transition metal dichalcogenides (TMDCs) faces a number of challenges in both efforts. This work attempts to establish a connection between the two by examining the gate-dependent conductance of few-layer (1-5L) WSe{sub 2} field effect devices. Measurements and modeling of the subgap regime reveal Schottky barrier transistor behavior. We show that transmission through the contact barrier is dominated by thermionic field emission (TFE) at room temperature, despite the lack of intentional doping. The TFE process arises due to a large number of subgap impurity states, the presence of which also leads to high mobility edge carrier densities. The density of states of such impurity states is self-consistently determined to be approximately 1–2 × 10{sup 13}/cm{sup 2}/eV in our devices. We demonstrate that substrate is unlikely to be a major source of the impurity states and suspect that lattice defects within the material itself are primarily responsible. Our experiments provide key information to advance the quality and understanding of TMDC materials and electrical devices.

  10. Phosphorus oxide gate dielectric for black phosphorus field effect transistors

    Science.gov (United States)

    Dickerson, W.; Tayari, V.; Fakih, I.; Korinek, A.; Caporali, M.; Serrano-Ruiz, M.; Peruzzini, M.; Heun, S.; Botton, G. A.; Szkopek, T.

    2018-04-01

    The environmental stability of the layered semiconductor black phosphorus (bP) remains a challenge. Passivation of the bP surface with phosphorus oxide, POx, grown by a reactive ion etch with oxygen plasma is known to improve photoluminescence efficiency of exfoliated bP flakes. We apply phosphorus oxide passivation in the fabrication of bP field effect transistors using a gate stack consisting of a POx layer grown by reactive ion etching followed by atomic layer deposition of Al2O3. We observe room temperature top-gate mobilities of 115 cm2 V-1 s-1 in ambient conditions, which we attribute to the low defect density of the bP/POx interface.

  11. Issues involved in the atomic layer deposition of metals

    Science.gov (United States)

    Grubbs, Robert Kimes

    Auger Electron Spectroscopy (AES) was used to study the nucleation and growth of tungsten on aluminum oxide surfaces. Tungsten metal was deposited using Atomic Layer Deposition (ALD) techniques. ALD uses sequential surface reactions to deposit material with atomic layer control. W ALD is performed using sequential exposures of WF6 and Si2H6. The step-wise nature of W ALD allows nucleation studies to be performed by analyzing the W surface concentration after each ALD reaction. Nucleation and growth regions can be identified by quantifying the AES signal intensities from both the W surface and the Al2O3 substrate. W nucleation occurred in 3 ALD reaction cycles. The AES results yielded a nucleation rate of 1.0 A/ALD cycle and a growth rate of ≈3 A/ALD cycle. AES studies also explored the nucleation and growth of Al2O3 on W. Al2O3 nucleated in 1 ALD cycle giving a nucleation rate of 3.5 A/ALD cycle and a subsequent growth rate of 1.0 A/ALD cycle. Mass spectrometry was then used to study the ALD reaction chemistry of tungsten deposition. Because of the step-wise nature of the W ALD chemistry, each W ALD reaction could be studied independently. The gaseous mass products were identified from both the WF6 and Si2H6 reactions. H2, HF and SiF4 mass products were observed for the WF6 reaction. The Si2H6 reaction displayed a room temperature reaction and a 200°C reaction. Products from the room temperature Si2H6 reaction were H2 and SiF3H. The reaction at 200°C yielded only H2 as a reaction product. H2 desorption from the surface contributes to the 200°C Si2H6 reaction. AES was used to confirm that the gas phase reaction products are correlated with a change in the surface species. Atomic hydrogen reduction of metal halides and oganometallic compounds provides another method for depositing metals with atomic layer control. The quantity of atomic hydrogen necessary to perform this chemistry is critical to the metal ALD process. A thermocouple probe was constructed to

  12. Double layer resist process scheme for metal lift-off with application in inductive heating of microstructures

    DEFF Research Database (Denmark)

    Ouattara, Lassana; Knutzen, Michael; Keller, Stephan Urs

    2010-01-01

    We present a new method to define metal electrodes on top of high-aspect-ratio microstructures using standard photolithography equipment and a single chromium mask. A lift-off resist (LOR) layer is implemented in an SU-8 photolithography process to selectively remove metal at the end of the proce......We present a new method to define metal electrodes on top of high-aspect-ratio microstructures using standard photolithography equipment and a single chromium mask. A lift-off resist (LOR) layer is implemented in an SU-8 photolithography process to selectively remove metal at the end...

  13. Photoluminescence emission from Alq3 organic layer in metal–Alq3–metal plasmonic structure

    Energy Technology Data Exchange (ETDEWEB)

    Huang, Bohr-Ran; Liao, Chung-Chi [Graduate Institute of Electro-Optical Engineering and Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei 106, Taiwan (China); Fan, Wan-Ting [Institute of Electro-Optical Engineering and Department of Electronic Engineering, Chang Gung University, Tao-Yuan 333, Taiwan (China); Wu, Jin-Han; Chen, Cheng-Chang; Lin, Yi-Ping; Li, Jung-Yu; Chen, Shih-Pu [Green Energy and Environment Research Laboratories, Industrial Technology Research Institute (ITRI), 195, Sec. 4, Chung-Hsin Road, Chutung 310, Taiwan (China); Ke, Wen-Cheng [Department of Mechanical Engineering, Yuan Ze University, Tao-Yuan 320, Taiwan (China); Chen, Nai-Chuan, E-mail: ncchen001@mail.cgu.edu.tw [Institute of Electro-Optical Engineering and Department of Electronic Engineering, Chang Gung University, Tao-Yuan 333, Taiwan (China)

    2014-06-01

    The emission properties of an organic layer embedded in a metal–organic–metal (MOM) structure were investigated. A partially radiative odd-SPW as well as a non-radiative even-SPW modes are supported by hybridization of the SPW modes on the opposite organic/metal interface in the structure. Because of the competition by this radiative SPW, the population of excitons that recombine to form non-radiative SPW should be reduced. This may account for why the photoluminescence intensity of the MOM sample is higher than that of an organic–metal sample even though the MOM sample has an additional metal layer that should intuitively act as a filter.

  14. Comparative study of the synthesis of layered transition metal molybdates

    Science.gov (United States)

    Mitchell, S.; Gómez-Avilés, A.; Gardner, C.; Jones, W.

    2010-01-01

    Mixed metal oxides (MMOs) prepared by the mild thermal decomposition of layered double hydroxides (LDHs) differ in their reactivity on exposure to aqueous molybdate containing solutions. In this study, we investigate the reactivity of some T-Al containing MMOs ( T=Co, Ni, Cu or Zn) towards the formation of layered transition metal molybdates (LTMs) possessing the general formula AT2(OH)(MoO 4) 2·H 2O, where A=NH 4+, Na + or K +. The phase selectivity of the reaction was studied with respect to the source of molybdate, the ratio of T to Mo and the reaction pH. LTMs were obtained on reaction of Cu-Al and Zn-Al containing MMOs with aqueous solutions of ammonium heptamolybdate. Rehydration of these oxides in the presence of sodium or potassium molybdate yielded a rehydrated LDH phase as the only crystalline product. The LTM products obtained by the rehydration of MMO precursors were compared with LTMs prepared by direct precipitation from the metal salts in order to study the influence of preparative route on their chemical and physical properties. Differences were noted in the composition, morphology and thermal properties of the resulting products.

  15. Near interface traps in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

    Energy Technology Data Exchange (ETDEWEB)

    Fiorenza, Patrick; La Magna, Antonino; Vivona, Marilena; Roccaforte, Fabrizio [Consiglio Nazionale delle Ricerche-Istituto per la Microelettronica e Microsistemi (CNR-IMM), Strada VIII 5, Zona Industriale 95121 Catania (Italy)

    2016-07-04

    This letter reports on the impact of gate oxide trapping states on the conduction mechanisms in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs). The phenomena were studied by gate current transient measurements, performed on n-channel MOSFETs operated in “gate-controlled-diode” configuration. The measurements revealed an anomalous non-steady conduction under negative bias (V{sub G} > |20 V|) through the SiO{sub 2}/4H-SiC interface. The phenomenon was explained by the coexistence of a electron variable range hopping and a hole Fowler-Nordheim (FN) tunnelling. A semi-empirical modified FN model with a time-depended electric field is used to estimate the near interface traps in the gate oxide (N{sub trap} ∼ 2 × 10{sup 11} cm{sup −2}).

  16. Highly Stable Operation of Lithium Metal Batteries Enabled by the Formation of a Transient High Concentration Electrolyte Layer

    Energy Technology Data Exchange (ETDEWEB)

    Zheng, Jianming; Yan, Pengfei; Mei, Donghai; Engelhard, Mark H.; Cartmell, Samuel S.; Polzin, Bryant; Wang, Chong M.; Zhang, Jiguang; Xu, Wu

    2016-02-08

    Lithium (Li) metal has been extensively investigated as an anode for rechargeable battery applications due to its ultrahigh specific capacity and the lowest redox potential. However, significant challenges including dendrite growth and low Coulombic efficiency are still hindering the practical applications of rechargeable Li metal batteries. Here, we demonstrate that long-term cycling of Li metal batteries can be realized by the formation of a transient high concentration electrolyte layer near the surface of Li metal anode during high rate discharge process. The highly concentrated Li+ ions in this transient layer will immediately solvate with the available solvent molecules and facilitate the formation of a stable and flexible SEI layer composed of a poly(ethylene carbonate) framework integrated with other organic/inorganic lithium salts. This SEI layer largely suppresses the corrosion of Li metal anode by free organic solvents and enables the long-term operation of Li metal batteries. The fundamental findings in this work provide a new direction for the development and operation of Li metal batteries that could be operated at high current densities for a wide range of applications.

  17. Exchange coupling in metallic multilayers with a top FeRh layer

    Energy Technology Data Exchange (ETDEWEB)

    Yamada, S., E-mail: yamada@ee.es.osaka-u.ac.jp; Kanashima, T.; Hamaya, K., E-mail: hamaya@ee.es.osaka-u.ac.jp [Graduate School of Engineering Science, Osaka University, Toyonaka 560-8531 (Japan); Tanikawa, K. [Department of Electronics, Kyushu University, 744 Motooka, Fukuoka 819-0395 (Japan); Hirayama, J. [Graduate School of Engineering Science, Osaka University, Toyonaka 560-8531 (Japan); Department of Electronics, Kyushu University, 744 Motooka, Fukuoka 819-0395 (Japan); Taniyama, T. [Materials and Structures Laboratory, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama 226-8503 (Japan)

    2016-05-15

    We study magnetic properties of metallic multilayers with FeRh/ferromagnet interfaces grown by low-temperature molecular beam epitaxy. Room-temperature coercivity of the ferromagnetic layers is significantly enhanced after the growth of FeRh, proving the existence of the exchange coupling between the antiferromagnetic FeRh layer and the ferromagnetic layer. However, exchange bias is not clearly observed probably due to the presence of disordered structures, which result from the lattice strain at the FeRh/ferromagnet interfaces due to the lattice mismatch. We infer that the lattice matched interface between FeRh and ferromagnetic layers is a key parameter for controlling magnetic switching fields in such multilayer systems.

  18. Behaviour of ceramic and metallic layers in a H2O-H2S

    International Nuclear Information System (INIS)

    Furtuna, I.; Mihailescu, M.; Deaconu, M.; Dinu, A.; Cotolan, V; Nedelcu, L.; Titescu, Gh.

    1996-01-01

    In the installations for heavy water production there exist zones where the action of aggressive working conditions combined with a severe variable hydrodynamical regime lead to the destruction of the pyrite protecting layer. An alternating solution for the protection of these zones is to cover them with ceramic or metallic layers. This work presents the results of the preliminary tests on G28-52 steel samples, covered with ceramic and metallic layers, in the working environment (H 2 O-H 2 S) of the heavy water production installations and in severe hydrodynamical conditions. On the basis of the results obtained in the experiments and from the examination of the microstructure of the layers prior and after testing, a phenomenological model was developed to explain the behaviour of the deposed layers. On the basis of this model the conditions that the layers must satisfy have been deduced to improve their behaviour in the working environment

  19. Theoretical bases on thermal stability of layered metallic systems

    International Nuclear Information System (INIS)

    Kadyrzhanov, K.K.; Rusakov, V.S.; Turkebaev, T.Eh.; Zhankadamova, A.M.; Ensebaeva, M.Z.

    2003-01-01

    The paper is dedicated to implementation of the theoretical bases for layered metallic systems thermal stabilization. The theory is based on the stabilization mechanism expense of the intermediate two-phase field formation. As parameters of calculated model are coefficients of mutual diffusion and inclusions sizes of generated phases in two-phase fields. The stabilization time dependence for beryllium-iron (Be (1.1 μm)-Fe(5.5 μm)) layered system from iron and beryllium diffusion coefficients, and inclusions sizes is shown as an example. Conclusion about possible mechanisms change at transition from microscopic consideration to the nano-crystal physics level is given

  20. Adsorption of metal adatoms on single-layer phosphorene.

    Science.gov (United States)

    Kulish, Vadym V; Malyi, Oleksandr I; Persson, Clas; Wu, Ping

    2015-01-14

    Single- or few-layer phosphorene is a novel two-dimensional direct-bandgap nanomaterial. Based on first-principles calculations, we present a systematic study on the binding energy, geometry, magnetic moment and electronic structure of 20 different adatoms adsorbed on phosphorene. The adatoms cover a wide range of valences, including s and p valence metals, 3d transition metals, noble metals, semiconductors, hydrogen and oxygen. We find that adsorbed adatoms produce a rich diversity of structural, electronic and magnetic properties. Our work demonstrates that phosphorene forms strong bonds with all studied adatoms while still preserving its structural integrity. The adsorption energies of adatoms on phosphorene are more than twice higher than on graphene, while the largest distortions of phosphorene are only ∼0.1-0.2 Å. The charge carrier type in phosphorene can be widely tuned by adatom adsorption. The unique combination of high reactivity with good structural stability is very promising for potential applications of phosphorene.

  1. Diamond logic inverter with enhancement-mode metal-insulator-semiconductor field effect transistor

    Energy Technology Data Exchange (ETDEWEB)

    Liu, J. W., E-mail: liu.jiangwei@nims.go.jp [International Center for Young Scientists (ICYS), National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Liao, M. Y.; Imura, M. [Optical and Electronic Materials Unit, NIMS, 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Watanabe, E.; Oosato, H. [Nanofabrication Platform, NIMS, 1-2-1 Sengen, Tsukuba, Ibaraki 305-0047 (Japan); Koide, Y., E-mail: koide.yasuo@nims.go.jp [Optical and Electronic Materials Unit, NIMS, 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Nanofabrication Platform, NIMS, 1-2-1 Sengen, Tsukuba, Ibaraki 305-0047 (Japan); Center of Materials Research for Low Carbon Emission, NIMS, 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan)

    2014-08-25

    A diamond logic inverter is demonstrated using an enhancement-mode hydrogenated-diamond metal-insulator-semiconductor field effect transistor (MISFET) coupled with a load resistor. The gate insulator has a bilayer structure of a sputtering-deposited LaAlO{sub 3} layer and a thin atomic-layer-deposited Al{sub 2}O{sub 3} buffer layer. The source-drain current maximum, extrinsic transconductance, and threshold voltage of the MISFET are measured to be −40.7 mA·mm{sup −1}, 13.2 ± 0.1 mS·mm{sup −1}, and −3.1 ± 0.1 V, respectively. The logic inverters show distinct inversion (NOT-gate) characteristics for input voltages ranging from 4.0 to −10.0 V. With increasing the load resistance, the gain of the logic inverter increases from 5.6 to as large as 19.4. The pulse response against the high and low input voltages shows the inversion response with the low and high output voltages.

  2. UN{sub 2−x} layer formed on uranium metal by glow plasma nitriding

    Energy Technology Data Exchange (ETDEWEB)

    Long, Zhong [China Academy of Engineering Physics, P.O. Box 919-71, Mianyang 621907 (China); Hu, Yin [Science and Technology on Surface Physics and Chemistry Laboratory, P.O. Box 718-35, Mianyang 621907 (China); Chen, Lin [China Academy of Engineering Physics, P.O. Box 919-71, Mianyang 621907 (China); Luo, Lizhu [Science and Technology on Surface Physics and Chemistry Laboratory, P.O. Box 718-35, Mianyang 621907 (China); Liu, Kezhao, E-mail: liukz@hotmail.com [Science and Technology on Surface Physics and Chemistry Laboratory, P.O. Box 718-35, Mianyang 621907 (China); Lai, Xinchun, E-mail: lai319@yahoo.com [Science and Technology on Surface Physics and Chemistry Laboratory, P.O. Box 718-35, Mianyang 621907 (China)

    2015-01-25

    Highlights: • We used a very simple method to prepare nitride layer on uranium metal surface. • This modified layer is nitrogen-rich nitride, which should be written as UN{sub 2−x}. • TEM images show the nitride layer is composed of nano-sized grains. • XPS analysis indicates there is uranium with abnormal low valence in the nitride. - Abstract: Glow plasma nitriding is a simple and economical surface treatment method, and this technology was used to prepare nitride layer on the surface of uranium metal with thickness of several microns. The composition and structure of the nitride layer were analyzed by AES and XRD, indicating that this modified layer is nitrogen-rich uranium nitride, which should be written as UN{sub 2−x}. TEM images show the nitride layer is composed of nano-sized grains, with compact structure. And XPS analysis indicates there is uranium with abnormal low valence existing in the nitride. After the treated uranium storage in air for a long time, oxygen just entered the surface several nanometers, showing the nitride layer has excellent oxidation resistance. The mechanism of nitride layer formation and low valence uranium appearance is discussed.

  3. Self-aligned metallization on organic semiconductor through 3D dual-layer thermal nanoimprint

    International Nuclear Information System (INIS)

    Jung, Y; Cheng, X

    2014-01-01

    High-resolution patterning of metal structures on organic semiconductors is important to the realization of high-performance organic transistors for organic integrated circuit applications. The traditional shadow mask technique has a limited resolution, precluding sub-micron metal structures on organic semiconductors. Thus organic transistors cannot benefit from scaling into the deep sub-micron region to improve their dc and ac performances. In this work, we report an efficient multiple-level metallization on poly (3-hexylthiophene) (P3HT) with a deep sub-micron lateral gap. By using a 3D nanoimprint mold in a dual-layer thermal nanoimprint process, we achieved self-aligned two-level metallization on P3HT. The 3D dual-layer thermal nanoimprint enables the first metal patterns to have suspending side-wings that can clearly define a distance from the second metal patterns. Isotropic and anisotropic side-wing structures can be fabricated through two different schemes. The process based on isotropic side-wings achieves a lateral-gap in the order of 100 nm (scheme 1). A gap of 60 nm can be achieved from the process with anisotropic side-wings (scheme 2). Because of the capability of nanoscale metal patterning on organic semiconductors with high overlay accuracy, this self-aligned metallization technique can be utilized to fabricate high-performance organic metal semiconductor field-effect transistor. (paper)

  4. Micro-EDXRF surface analyses of a bronze spear head: Lead content in metal and corrosion layers

    International Nuclear Information System (INIS)

    Figueiredo, E.; Valerio, P.; Araujo, M.F.; Senna-Martinez, J.C.

    2007-01-01

    A bronze spear head from Central Portugal dated to Late Bronze Age has been analyzed by non-destructive micro-EDXRF in the metal surface and corrosion layers. The artifact had previously been analyzed using a conventional EDXRF spectrometer having a larger incident beam. The quantification of the micro-EDXRF analyses showed that lead content in corrosion layers can reach values up to four times higher than the content determined in the metal surface. Results obtained with the higher energy incident beam from the EDXRF equipment, although referring mainly to the corrosion layers, seem to suffer some influence from the surface composition of the metallic alloy

  5. Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors

    Science.gov (United States)

    Fan, Ching-Lin; Shang, Ming-Chi; Wang, Shea-Jue; Hsia, Mao-Yuan; Lee, Win-Der; Huang, Bohr-Ran

    2017-01-01

    In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W). PMID:28773101

  6. Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol for the Gate Insulator of Pentacene-Based Thin-Film Transistors

    Directory of Open Access Journals (Sweden)

    Ching-Lin Fan

    2017-07-01

    Full Text Available In this study, a proposed Microwave-Induction Heating (MIH scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO metal below the Poly(4-vinylphenol (PVP film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min and low-power microwave-irradiation (50 W.

  7. Anomalous degradation behaviors under illuminated gate bias stress in a-Si:H thin film transistor

    International Nuclear Information System (INIS)

    Tsai, Ming-Yen; Chang, Ting-Chang; Chu, Ann-Kuo; Hsieh, Tien-Yu; Lin, Kun-Yao; Wu, Yi-Chun; Huang, Shih-Feng; Chiang, Cheng-Lung; Chen, Po-Lin; Lai, Tzu-Chieh; Lo, Chang-Cheng; Lien, Alan

    2014-01-01

    This study investigates the impact of gate bias stress with and without light illumination in a-Si:H thin film transistors. It has been observed that the I–V curve shifts toward the positive direction after negative and positive gate bias stress due to interface state creation at the gate dielectric. However, this study found that threshold voltages shift negatively and that the transconductance curve maxima are anomalously degraded under illuminated positive gate bias stress. In addition, threshold voltages shift positively under illuminated negative gate bias stress. These degradation behaviors can be ascribed to charge trapping in the passivation layer dominating degradation instability and are verified by a double gate a-Si:H device. - Highlights: • There is abnormal V T shift induced by illuminated gate bias stress in a-Si:H thin film transistors. • Electron–hole pair is generated via trap-assisted photoexcitation. • Abnormal transconductance hump is induced by the leakage current from back channel. • Charge trapping in the passivation layer is likely due to the fact that a constant voltage has been applied to the top gate

  8. High dose, heavy ion implantation into metals: the use of sacrificial surface layers to enhance retention

    International Nuclear Information System (INIS)

    Clapham, L.

    1994-01-01

    While of considerable interest for the production of metallic alloys, high dose, heavy ion implantation is highly problematical, since the process is limited by sputtering effects. Sputtering is less significant, however, for light target materials, such as C and Al. This paper summarizes studies involving the use of light materials (such as C and Al) which act as slowly sputtering ''sacrificial layers'' when deposited on metallic targets prior to heavy ion implantation. The use of C and Al sacrificial coatings has enabled implanted ion retentions of 100% to be obtained in a number of ion-metal target systems, where the retentions in uncoated samples were as low as 20%. Ion implantation invariably leads to mixing at the sacrificial layer-metal target interface. This mixing may be detrimental in certain systems, so it is useful to be able to minimize or remove this mixed region. To achieve this, a number of techniques have been investigated: (1) removal of the mixed region in the latter stages of the implant; (2) using a barrier layer or chemical effects to minimize mixing at the sacrificial layer-metal interface; (3) choosing a sacrificial layer material which forms a mixed region which has desirable properties. The results of these investigations, for a number of different ion-target systems, are outlined in this paper. (orig.)

  9. Extended Solution Gate OFET-based Biosensor for Label-free Glial Fibrillary Acidic Protein Detection with Polyethylene Glycol-Containing Bioreceptor Layer.

    Science.gov (United States)

    Song, Jian; Dailey, Jennifer; Li, Hui; Jang, Hyun-June; Zhang, Pengfei; Wang, Jeff Tza-Huei; Everett, Allen D; Katz, Howard E

    2017-05-25

    A novel organic field effect transistor (OFET) -based biosensor is described for label-free glial fibrillary acidic protein (GFAP) detection. We report the first use of an extended solution gate structure where the sensing area and the organic semiconductor are separated, and a reference electrode is not needed. Different molecular weight polyethylene glycols (PEGs) are mixed into the bio-receptor layer to help extend the Debye screening length. The drain current change was significantly increased with the help of higher molecular weight PEGs, as they are known to reduce the dielectric constant. We also investigated the sensing performance under different gate voltage (V g ). The sensitivity increased after we decreased V g from -5 V to -2 V, because the lower V g is much closer to the OFET threshold voltage and the influence of attached negatively charged proteins become more apparent. Finally, the selectivity experiments toward different interferents were performed. The stability and selectivity are promising for clinical applications.

  10. Side-gate modulation effects on high-quality BN-Graphene-BN nanoribbon capacitors

    International Nuclear Information System (INIS)

    Wang, Yang; Chen, Xiaolong; Ye, Weiguang; Wu, Zefei; Han, Yu; Han, Tianyi; He, Yuheng; Cai, Yuan; Wang, Ning

    2014-01-01

    High-quality BN-Graphene-BN nanoribbon capacitors with double side-gates of graphene have been experimentally realized. The double side-gates can effectively modulate the electronic properties of graphene nanoribbon capacitors. By applying anti-symmetric side-gate voltages, we observed significant upward shifting and flattening of the V-shaped capacitance curve near the charge neutrality point. Symmetric side-gate voltages, however, only resulted in tilted upward shifting along the opposite direction of applied gate voltages. These modulation effects followed the behavior of graphene nanoribbons predicted theoretically for metallic side-gate modulation. The negative quantum capacitance phenomenon predicted by numerical simulations for graphene nanoribbons modulated by graphene side-gates was not observed, possibly due to the weakened interactions between the graphene nanoribbon and side-gate electrodes caused by the Ga + beam etching process

  11. Using white noise to gate organic transistors for dynamic monitoring of cultured cell layers.

    Science.gov (United States)

    Rivnay, Jonathan; Leleux, Pierre; Hama, Adel; Ramuz, Marc; Huerta, Miriam; Malliaras, George G; Owens, Roisin M

    2015-06-26

    Impedance sensing of biological systems allows for monitoring of cell and tissue properties, including cell-substrate attachment, layer confluence, and the "tightness" of an epithelial tissue. These properties are critical for electrical detection of tissue health and viability in applications such as toxicological screening. Organic transistors based on conducting polymers offer a promising route to efficiently transduce ionic currents to attain high quality impedance spectra, but collection of complete impedance spectra can be time consuming (minutes). By applying uniform white noise at the gate of an organic electrochemical transistor (OECT), and measuring the resulting current noise, we are able to dynamically monitor the impedance and thus integrity of cultured epithelial monolayers. We show that noise sourcing can be used to track rapid monolayer disruption due to compounds which interfere with dynamic polymerization events crucial for maintaining cytoskeletal integrity, and to resolve sub-second alterations to the monolayer integrity.

  12. Comparative study on nitridation and oxidation plasma interface treatment for AlGaN/GaN MIS-HEMTs with AlN gate dielectric

    Science.gov (United States)

    Zhu, Jie-Jie; Ma, Xiao-Hua; Hou, Bin; Chen, Li-Xiang; Zhu, Qing; Hao, Yue

    2017-02-01

    This paper demonstrated the comparative study on interface engineering of AlN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) by using plasma interface pre-treatment in various ambient gases. The 15 nm AlN gate dielectric grown by plasma-enhanced atomic layer deposition significantly suppressed the gate leakage current by about two orders of magnitude and increased the peak field-effect mobility by more than 50%. NH3/N2 nitridation plasma treatment (NPT) was used to remove the 3 nm poor-quality interfacial oxide layer and N2O/N2 oxidation plasma treatment (OPT) to improve the quality of interfacial layer, both resulting in improved dielectric/barrier interface quality, positive threshold voltage (V th) shift larger than 0.9 V, and negligible dispersion. In comparison, however, NPT led to further decrease in interface charges by 3.38 × 1012 cm-2 and an extra positive V th shift of 1.3 V. Analysis with fat field-effect transistors showed that NPT resulted in better sub-threshold characteristics and transconductance linearity for MIS-HEMTs compared with OPT. The comparative study suggested that direct removing the poor interfacial oxide layer by nitridation plasma was superior to improving the quality of interfacial layer by oxidation plasma for the interface engineering of GaN-based MIS-HEMTs.

  13. Ballistic transport of graphene pnp junctions with embedded local gates

    International Nuclear Information System (INIS)

    Nam, Seung-Geol; Ki, Dong-Keun; Kim, Youngwook; Kim, Jun Sung; Lee, Hu-Jong; Park, Jong Wan

    2011-01-01

    We fabricated graphene pnp devices, by embedding pre-defined local gates in an oxidized surface layer of a silicon substrate. With neither deposition of dielectric material on the graphene nor electron-beam irradiation, we obtained high-quality graphene pnp devices without degradation of the carrier mobility even in the local-gate region. The corresponding increased mean free path leads to the observation of ballistic and phase-coherent transport across a local gate 130 nm wide, which is about an order of magnitude wider than reported previously. Furthermore, in our scheme, we demonstrated independent control of the carrier density in the local-gate region, with a conductance map very much distinct from those of top-gated devices. This was caused by the electric field arising from the global back gate being strongly screened by the embedded local gate. Our scheme allows the realization of ideal multipolar graphene junctions with ballistic carrier transport.

  14. Design technology co-optimization for 14/10nm metal1 double patterning layer

    Science.gov (United States)

    Duan, Yingli; Su, Xiaojing; Chen, Ying; Su, Yajuan; Shao, Feng; Zhang, Recco; Lei, Junjiang; Wei, Yayi

    2016-03-01

    Design and technology co-optimization (DTCO) can satisfy the needs of the design, generate robust design rule, and avoid unfriendly patterns at the early stage of design to ensure a high level of manufacturability of the product by the technical capability of the present process. The DTCO methodology in this paper includes design rule translation, layout analysis, model validation, hotspots classification and design rule optimization mainly. The correlation of the DTCO and double patterning (DPT) can optimize the related design rule and generate friendlier layout which meets the requirement of the 14/10nm technology node. The experiment demonstrates the methodology of DPT-compliant DTCO which is applied to a metal1 layer from the 14/10nm node. The DTCO workflow proposed in our job is an efficient solution for optimizing the design rules for 14/10 nm tech node Metal1 layer. And the paper also discussed and did the verification about how to tune the design rule of the U-shape and L-shape structures in a DPT-aware metal layer.

  15. Effects of Y incorporation in TaON gate dielectric on electrical performance of GaAs metal-oxide-semiconductor capacitor

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Li Ning; Choi, Hoi Wai; Lai, Pui To [Department of Electrical and Electronic Engineering, The University of Hong Kong (China); Xu, Jing Ping [School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan (China)

    2016-09-15

    In this study, GaAs metal-oxide-semiconductor (MOS) capacitors using Y-incorporated TaON as gate dielectric have been investigated. Experimental results show that the sample with a Y/(Y + Ta) atomic ratio of 27.6% exhibits the best device characteristics: high k value (22.9), low interfacestate density (9.0 x 10{sup 11} cm{sup -2} eV{sup -1}), small flatband voltage (1.05 V), small frequency dispersion and low gate leakage current (1.3 x 10{sup -5}A/cm{sup 2} at V{sub fb} + 1 V). These merits should be attributed to the complementary properties of Y{sub 2}O{sub 3} and Ta{sub 2}O{sub 5}:Y can effectively passivate the large amount of oxygen vacancies in Ta{sub 2}O{sub 5}, while the positively-charged oxygen vacancies in Ta{sub 2}O{sub 5} are capable of neutralizing the effects of the negative oxide charges in Y{sub 2}O{sub 3}. This work demonstrates that an appropriate doping of Y content in TaON gate dielectric can effectively improve the electrical performance for GaAs MOS devices. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  16. Implementation of a funnel-and-gate remediation system

    International Nuclear Information System (INIS)

    O'Brien, K.; Keyes, G.; Sherman, N.

    1997-01-01

    A funnel-and-gate trademark system incorporating activated carbon was deemed the most attractive remediation method for an active lumber mill in the western United States. Petroleum hydrocarbons, chlorinated solvents, pentachlorophenol, and tetrachlorophenol were detected in on-site groundwater samples. The shallow aquifer consists of a heterogeneous mixture of marine deposits and artificial fill, underlain by low-permeability siltstones and mudstone. In the funnel-and-gate trademark system, a low-permeability cutoff wall was installed to funnel groundwater flow to a smaller area (a open-quotes gateclose quotes) where a passive below-grade treatment system treats the plume as it flows through the gate. Groundwater flow modeling focused on the inhomogeneities of the aquifer and the spatial relationship between gate(s) and barrier walls. The gate design incorporates several factors, including contaminant concentration, flow rate, and time between carbon changeouts. To minimize back pressure and maximize residence time, each gate was designed using 1.25-meter (4-foot) diameter corrugated metal pipe filled with a 1.25-meter (4-foot) thick bed of activated carbon. The configuration will allow water to flow through the treatment gates without pumps. The installed system is 190 meters (625 feet) long and treats approximately 76 L/min (20 gpm) during the winter months

  17. Infrared-transmittance tunable metal-insulator conversion device with thin-film-transistor-type structure on a glass substrate

    Directory of Open Access Journals (Sweden)

    Takayoshi Katase

    2017-05-01

    Full Text Available Infrared (IR transmittance tunable metal-insulator conversion was demonstrated on a glass substrate by using thermochromic vanadium dioxide (VO2 as the active layer in a three-terminal thin-film-transistor-type device with water-infiltrated glass as the gate insulator. Alternative positive/negative gate-voltage applications induce the reversible protonation/deprotonation of a VO2 channel, and two-orders of magnitude modulation of sheet-resistance and 49% modulation of IR-transmittance were simultaneously demonstrated at room temperature by the metal-insulator phase conversion of VO2 in a non-volatile manner. The present device is operable by the room-temperature protonation in an all-solid-state structure, and thus it will provide a new gateway to future energy-saving technology as an advanced smart window.

  18. Bimodal gate-dielectric deposition for improved performance of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

    International Nuclear Information System (INIS)

    Pang Liang; Kim, Kyekyoon

    2012-01-01

    A bimodal deposition scheme combining radiofrequency magnetron sputtering and plasma enhanced chemical vapour deposition (PECVD) is proposed as a means for improving the performance of GaN-based metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs). High-density sputtered-SiO 2 is utilized to reduce the gate leakage current and enhance the breakdown voltage while low-density PECVD-SiO 2 is employed to buffer the sputtering damage and further increase the drain current by engineering the stress-induced-polarization. Thus-fabricated MOSHEMT exhibited a low leakage current of 4.21 × 10 -9 A mm -1 and high breakdown voltage of 634 V for a gate-drain distance of 6 µm, demonstrating the promise of bimodal-SiO 2 deposition scheme for the development of GaN-based MOSHEMTs for high-power application. (paper)

  19. Neutron scattering investigation of layer-bending modes in alkali-metal--graphite intercalation compounds

    International Nuclear Information System (INIS)

    Zabel, H.; Kamitakahara, W.A.; Nicklow, R.M.

    1982-01-01

    Phonon dispersion curves for low-frequency transverse modes propagating in the basal plane have been measured in the alkali-metal--graphite intercalation compounds KC 8 , CsC 8 , KC 24 , and RbC 24 by means of neutron spectroscopy. The acoustic branches show an almost quadratic dispersion relation at small q, characteristic of strongly layered materials. The optical branches of stage-1 compounds can be classified as either graphitelike branches showing dispersion, or as almost dispersionless alkali-metal-like modes. Macroscopic shear constants C 44 and layer-bending moduli have been obtained for the intercalation compounds by analyzing the data in terms of a simple semicontinuum model. In stage-2 compounds, a dramatic softening of the shear constant by about a factor of 8 compared with pure graphite has been observed. Low-temperature results on KC 24 indicate the opening of a frequency gap near the alkali-metal Brillouin-zone boundary, possibly due to the formation of the alkali-metal superstructure

  20. Influence of gate recess on the electronic characteristics of β-Ga2O3 MOSFETs

    Science.gov (United States)

    Lv, Yuanjie; Mo, Jianghui; Song, Xubo; He, Zezhao; Wang, Yuangang; Tan, Xin; Zhou, Xingye; Gu, Guodong; Guo, Hongyu; Feng, Zhihong

    2018-05-01

    Gallium oxide (Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with gate recess depths of 110 nm and 220 nm, respectively. The gate recess was formed by dry plasma etching with Cr metal as the mask. The fabricated devices with a 25-nm HfO2 gate dielectric both showed a low off-state drain current of about 1.8 × 10-10 A/mm. The effects of recess depth on the electronic characteristics of Ga2O3 MOSFETs were investigated. Upon increasing the recess depth from 110 nm to 220 nm, the saturated drain current decreased from 20.7 mA/mm to 2.6 mA/mm, while the threshold voltage moved increased to +3 V. Moreover, the breakdown voltage increased from 122 V to 190 V. This is mainly because the inverted-trapezoidal gate played the role of a gate-field plate, which suppressed the peak electric field close to the gate.

  1. Thin-layer chromatography of ternary complexes of group-IIIA metals with 2-thenoyltrifluoroacetone and 2,2'-bipyridyl on cellulose layer

    Energy Technology Data Exchange (ETDEWEB)

    Chao, H E; Saitoh, K; Suzuki, N [Tohoku Univ., Sendai (Japan). Faculty of Science

    1980-11-11

    Normal phase thin-layer chromatographic behaviour of several ternary complexes of group-IIIA metals with 2-thenoyltrifluoroacetone (TTA) and 2,2'bipyridyl (bpy) has been investigated on cellulose layer. The ternary complexes of lanthanide metals show higher mutual separability than the complexes with TTA alone. Mutual separation of TTA complexes with La(III), Ce(III), Eu(III) or Y(III), Sc(III), Th(IV), and U(VI) has been successfully achieved by two-dimensional TLC, primarily with carbon tetrachloride-benzene (75:25) containing 0.02M TTA, and secondary with carbon tetrachloride-hexane (35:65) containing both 0.02M TTA and 0.02M bpy.

  2. Dynamic monitoring of transmembrane potential changes: a study of ion channels using an electrical double layer-gated FET biosensor.

    Science.gov (United States)

    Pulikkathodi, Anil Kumar; Sarangadharan, Indu; Chen, Yi-Hong; Lee, Geng-Yen; Chyi, Jen-Inn; Lee, Gwo-Bin; Wang, Yu-Lin

    2018-03-27

    In this research, we have designed, fabricated and characterized an electrical double layer (EDL)-gated AlGaN/GaN high electron mobility transistor (HEMT) biosensor array to study the transmembrane potential changes of cells. The sensor array platform is designed to detect and count circulating tumor cells (CTCs) of colorectal cancer (CRC) and investigate cellular bioelectric signals. Using the EDL FET biosensor platform, cellular responses can be studied in physiological salt concentrations, thereby eliminating complex automation. Upon investigation, we discovered that our sensor response follows the transmembrane potential changes of captured cells. Our whole cell sensor platform can be used to monitor the dynamic changes in the membrane potential of cells. The effects of continuously changing electrolyte ion concentrations and ion channel blocking using cadmium are investigated. This methodology has the potential to be used as an electrophysiological probe for studying ion channel gating and the interaction of biomolecules in cells. The sensor can also be a point-of-care diagnostic tool for rapid screening of diseases.

  3. In situ ceramic layer growth on coated fuel particles dispersed in a zirconium metal matrix

    Science.gov (United States)

    Terrani, K. A.; Silva, C. M.; Kiggans, J. O.; Cai, Z.; Shin, D.; Snead, L. L.

    2013-06-01

    The extent and nature of the chemical interaction between the outermost coating layer of coated fuel particles embedded in zirconium metal during fabrication of metal matrix microencapsulated fuels were examined. Various particles with outermost coating layers of pyrocarbon, SiC, and ZrC have been investigated in this study. ZrC-Zr interaction was the least substantial, while the PyC-Zr reaction can be exploited to produce a ZrC layer at the interface in an in situ manner. The thickness of the ZrC layer in the latter case can be controlled by adjusting the time and temperature during processing. The kinetics of ZrC layer growth is significantly faster from what is predicted using literature carbon diffusivity data in ZrC. SiC-Zr interaction is more complex and results in formation of various chemical phases in a layered aggregate morphology at the interface.

  4. Effects of electrolyte gating on photoluminescence spectra of large-area WSe2monolayer films

    KAUST Repository

    Matsuki, Keiichiro; Pu, Jiang; Kozawa, Daichi; Matsuda, Kazunari; Li, Lain-Jong; Takenobu, Taishi

    2016-01-01

    We fabricated electric double-layer transistors comprising large-area WSe2 monolayers and investigated the effects of electrolyte gating on their photoluminescence (PL) spectra. Using the efficient gating effects of electric double layers, we succeeded in the application of a large electric field (>107Vcm%1) and the accumulation of high carrier density (>1013cm%2). As a result, we observed PL spectra based on both positively and negatively charged excitons and their gate-voltage-dependent redshifts, suggesting the effects of both an electric field and charge accumulation. © 2016 The Japan Society of Applied Physics.

  5. Effects of electrolyte gating on photoluminescence spectra of large-area WSe2monolayer films

    KAUST Repository

    Matsuki, Keiichiro

    2016-05-24

    We fabricated electric double-layer transistors comprising large-area WSe2 monolayers and investigated the effects of electrolyte gating on their photoluminescence (PL) spectra. Using the efficient gating effects of electric double layers, we succeeded in the application of a large electric field (>107Vcm%1) and the accumulation of high carrier density (>1013cm%2). As a result, we observed PL spectra based on both positively and negatively charged excitons and their gate-voltage-dependent redshifts, suggesting the effects of both an electric field and charge accumulation. © 2016 The Japan Society of Applied Physics.

  6. Exact matrix treatment of statistical mechanical lattice model of adsorption induced gate opening in metal-organic frameworks

    International Nuclear Information System (INIS)

    Dunne, Lawrence J; Manos, George

    2015-01-01

    Here we present a statistical mechanical lattice model which is exactly solvable using a matrix method and allows treatment of adsorption induced gate opening structural transformations of metal-organic frameworks which are nanoporous materials with exceptional adsorption properties. Modelling of these structural changes presents a serious theoretical challenge when the solid and gas species are treated in an even handed way. This exactly solvable model complements other simulation based approaches. The methodology presented here highlights the competition between the potential for adsorption and the energy required for structural transition as a driving force for the features in the adsorption isotherms. (paper)

  7. Changes of electrical conductivity of the metal surface layer by the laser alloying with foreign elements

    Science.gov (United States)

    Kostrubiec, Franciszek; Pawlak, Ryszard; Raczynski, Tomasz; Walczak, Maria

    1994-09-01

    Laser treatment of the surface of materials is of major importance for many fields technology. One of the latest and most significant methods of this treatment is laser alloying consisting of introducing foreign atoms into the metal surface layer during the reaction of laser radiation with the surface. This opens up vast possibilities for the modification of properties of such a layer (obtaining layers of increased microhardness, increased resistance to electroerosion in an electric arc, etc.). Conductivity of the material is a very important parameter in case of conductive materials used for electrical contacts. The paper presents the results of studies on change in electrical conductivity of the surface layer of metals alloyed with a laser. A comparative analysis of conductivity of base metal surface layers prior to and following laser treatment has been performed. Depending on the base metal and the alloying element, optical treatment parameters allowing a required change in the surface layer conductivity have been selected. A very important property of the contact material is its resistance to plastic strain. It affects the real value of contact surface coming into contact and, along with the material conductivity, determines contact resistance and the amount of heat generated in place of contact. These quantities are directly related to the initiation and the course of an arc discharge, hence they also affect resistance to electroerosion. The parameter that reflects plastic properties with loads concentrated on a small surface, as is the case with a reciprocal contact force of two real surfaces with their irregularities being in contact, is microhardness. In the paper, the results of investigations into microhardness of modified surface layers compared with base metal microhardness have been presented.

  8. ZnO nanowire-based nano-floating gate memory with Pt nanocrystals embedded in Al{sub 2}O{sub 3} gate oxides

    Energy Technology Data Exchange (ETDEWEB)

    Yeom, Donghyuk; Kang, Jeongmin; Lee, Myoungwon; Jang, Jaewon; Yun, Junggwon; Jeong, Dong-Young; Yoon, Changjoon; Koo, Jamin; Kim, Sangsig [Department of Electrical Engineering and Institute for Nano Science, Korea University, Seoul 136-701 (Korea, Republic of)], E-mail: sangsig@korea.ac.kr

    2008-10-01

    The memory characteristics of ZnO nanowire-based nano-floating gate memory (NFGM) with Pt nanocrystals acting as the floating gate nodes were investigated in this work. Pt nanocrystals were embedded between Al{sub 2}O{sub 3} tunneling and control oxide layers deposited on ZnO nanowire channels. For a representative ZnO nanowire-based NFGM with embedded Pt nanocrystals, a threshold voltage shift of 3.8 V was observed in its drain current versus gate voltage (I{sub DS}-V{sub GS}) measurements for a double sweep of the gate voltage, revealing that the deep effective potential wells built into the nanocrystals provide our NFGM with a large charge storage capacity. Details of the charge storage effect observed in this memory device are discussed in this paper.

  9. Nucleation and Early Stages of Layer-by-Layer Growth of Metal Organic Frameworks on Surfaces

    Science.gov (United States)

    2015-01-01

    High resolution atomic force microscopy (AFM) is used to resolve the evolution of crystallites of a metal organic framework (HKUST-1) grown on Au(111) using a liquid-phase layer-by-layer methodology. The nucleation and faceting of individual crystallites is followed by repeatedly imaging the same submicron region after each cycle of growth and we find that the growing surface is terminated by {111} facets leading to the formation of pyramidal nanostructures for [100] oriented crystallites, and triangular [111] islands with typical lateral dimensions of tens of nanometres. AFM images reveal that crystallites can grow by 5–10 layers in each cycle. The growth rate depends on crystallographic orientation and the morphology of the gold substrate, and we demonstrate that under these conditions the growth is nanocrystalline with a morphology determined by the minimum energy surface. PMID:26709359

  10. Study on the influence of carbon monoxide to the surface oxide layer of uranium metal

    International Nuclear Information System (INIS)

    Wang Xiaolin; Duan Rongliang; Fu Yibei; Xie Renshou; Zuo Changming; Zhao Chunpei; Chen Hong

    1997-01-01

    The influence of carbon monoxide to the surface oxide layer of uranium metal has been studied by X-ray photoelectron spectroscopy (XPS) and gas chromatography (GC). Carbon monoxide adsorption on the oxide layer resulted in U4f peak shifting to the lower binding energy. The content of oxygen in the oxide is decreased and the atomic ratio (O/U) is decreased by 7.2%. The amount of carbon dioxide in the atmosphere after the surface reaction is increased by 11.0%. The investigation indicates that the surface layer can prevent the further oxidation uranium metal in the atmosphere of carbon monoxide

  11. First-principles simulations of the leakage current in metal-oxide-semiconductor structures caused by oxygen vacancies in HfO2 high-K gate dielectric

    International Nuclear Information System (INIS)

    Mao, L.F.; Wang, Z.O.

    2008-01-01

    HfO 2 high-K gate dielectric has been used as a new gate dielectric in metal-oxide-semiconductor structures. First-principles simulations are used to study the effects of oxygen vacancies on the tunneling current through the oxide. A level which is nearly 1.25 eV from the bottom of the conduction band is introduced into the bandgap due to the oxygen vacancies. The tunneling current calculations show that the tunneling currents through the gate oxide with different defect density possess the typical characteristic of stress-induced leakage current. Further analysis shows that the location of oxygen vacancies will have a marked effect on the tunneling current. The largest increase in the tunneling current caused by oxygen vacancies comes about at the middle oxide field when defects are located at the middle of the oxide. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  12. High performance Ω-gated Ge nanowire MOSFET with quasi-metallic source/drain contacts.

    Science.gov (United States)

    Burchhart, T; Zeiner, C; Hyun, Y J; Lugstein, A; Hochleitner, G; Bertagnolli, E

    2010-10-29

    Ge nanowires (NWs) about 2 µm long and 35 nm in diameter are grown heteroepitaxially on Si(111) substrates in a hot wall low-pressure chemical vapor deposition (LP-CVD) system using Au as a catalyst and GeH(4) as precursor. Individual NWs are contacted to Cu pads via e-beam lithography, thermal evaporation and lift-off techniques. Self-aligned and atomically sharp quasi-metallic copper-germanide source/drain contacts are achieved by a thermal activated phase formation process. The Cu(3)Ge segments emerge from the Cu contact pads through axial diffusion of Cu which was controlled in situ by SEM, thus the active channel length of the MOSFET is adjusted without any restrictions from a lithographic process. Finally the conductivity of the channel is enhanced by Ga(+) implantation leading to a high performance Ω-gated Ge-NW MOSFET with saturation currents of a few microamperes.

  13. Design, fabrication, and evaluation of charge-coupled devices with aluminum-anodized-aluminum gates

    Science.gov (United States)

    Gassaway, J. D.; Causey, W. H., Jr.

    1977-01-01

    A 4-phase, 49 1/2 bit CCD shift register was designed and fabricated using two levels of aluminum metallization with anodic Al2O3 insulation separating the layers. Test circuitry was also designed and constructed. A numerical analysis of an MOS-RC transmission line was made and results are given to characterize performance for various conductivities. The electrical design of the CCD included a low-noise dual-gate input and a balanced floating diffusion output circuit. Metallization was accomplished both by low voltage DC sputtering and thermal evaporation. The audization was according to published procedures using a buffered tartaric acid bath. Approximately 20 wafers were processed with 50 complete chips per wafer. All devices failed by shorting between the metal levels at some point. Experimental procedures eliminated temperature effects from sintering and drying, anodic oxide thickness, edge effects, photoresist stripping procedures, and metallization techniques as the primary causes of failure. It was believed from a study of SEM images that protuberances (hillocks) grow up from the first level metal through the oxide either causing a direct short or producing a weak, highly stressed insulation point which fails at low voltage. The cause of these hillocks is unknown; however, they have been observed to grow during temperature excursions to 470 C.

  14. Photovoltaic and photothermoelectric effect in a double-gated WSe2 device.

    Science.gov (United States)

    Groenendijk, Dirk J; Buscema, Michele; Steele, Gary A; Michaelis de Vasconcellos, Steffen; Bratschitsch, Rudolf; van der Zant, Herre S J; Castellanos-Gomez, Andres

    2014-10-08

    Tungsten diselenide (WSe2), a semiconducting transition metal dichalcogenide (TMDC), shows great potential as active material in optoelectronic devices due to its ambipolarity and direct bandgap in its single-layer form. Recently, different groups have exploited the ambipolarity of WSe2 to realize electrically tunable PN junctions, demonstrating its potential for digital electronics and solar cell applications. In this Letter, we focus on the different photocurrent generation mechanisms in a double-gated WSe2 device by measuring the photocurrent (and photovoltage) as the local gate voltages are varied independently in combination with above- and below-bandgap illumination. This enables us to distinguish between two main photocurrent generation mechanisms, the photovoltaic and photothermoelectric effect. We find that the dominant mechanism depends on the defined gate configuration. In the PN and NP configurations, photocurrent is mainly generated by the photovoltaic effect and the device displays a maximum responsivity of 0.70 mA/W at 532 nm illumination and rise and fall times close to 10 ms. Photocurrent generated by the photothermoelectric effect emerges in the PP configuration and is a factor of 2 larger than the current generated by the photovoltaic effect (in PN and NP configurations). This demonstrates that the photothermoelectric effect can play a significant role in devices based on WSe2 where a region of strong optical absorption, caused by, for example, an asymmetry in flake thickness or optical absorption of the electrodes, generates a sizable thermal gradient upon illumination.

  15. Transfer-free graphene synthesis on sapphire by catalyst metal agglomeration technique and demonstration of top-gate field-effect transistors

    International Nuclear Information System (INIS)

    Miyoshi, Makoto; Arima, Yukinori; Kubo, Toshiharu; Egawa, Takashi; Mizuno, Masaya; Soga, Tetsuo

    2015-01-01

    Transfer-free graphene synthesis was performed on sapphire substrates by using the catalyst metal agglomeration technique, and the graphene film quality was compared to that synthesized on sputtered SiO 2 /Si substrates. Raman scattering measurements indicated that the graphene film on sapphire has better structural qualities than that on sputtered SiO 2 /Si substrates. The cross-sectional transmission microscopic study also revealed that the film flatness was drastically improved by using sapphire substrates instead of sputtered SiO 2 /Si substrates. These quality improvements seemed to be due the chemical and thermal stabilities of sapphire. Top-gate field-effect transistors were fabricated using the graphene films on sapphire, and it was confirmed that their drain current can be modulated with applied gate voltages. The maximum field-effect mobilities were estimated to be 720 cm 2 /V s for electrons and 880 cm 2 /V s for holes, respectively

  16. Transfer-free graphene synthesis on sapphire by catalyst metal agglomeration technique and demonstration of top-gate field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Miyoshi, Makoto, E-mail: miyoshi.makoto@nitech.ac.jp; Arima, Yukinori; Kubo, Toshiharu; Egawa, Takashi [Research Center for Nano Device and Advanced Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan); Mizuno, Masaya [Research Center for Nano Device and Advanced Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan); Department of Frontier Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan); Soga, Tetsuo [Department of Frontier Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan)

    2015-08-17

    Transfer-free graphene synthesis was performed on sapphire substrates by using the catalyst metal agglomeration technique, and the graphene film quality was compared to that synthesized on sputtered SiO{sub 2}/Si substrates. Raman scattering measurements indicated that the graphene film on sapphire has better structural qualities than that on sputtered SiO{sub 2}/Si substrates. The cross-sectional transmission microscopic study also revealed that the film flatness was drastically improved by using sapphire substrates instead of sputtered SiO{sub 2}/Si substrates. These quality improvements seemed to be due the chemical and thermal stabilities of sapphire. Top-gate field-effect transistors were fabricated using the graphene films on sapphire, and it was confirmed that their drain current can be modulated with applied gate voltages. The maximum field-effect mobilities were estimated to be 720 cm{sup 2}/V s for electrons and 880 cm{sup 2}/V s for holes, respectively.

  17. Melt layer macroscopic erosion of tungsten and other metals under plasma heat loads simulating ITER off-normal events

    International Nuclear Information System (INIS)

    Garkusha, I.E.; Bandura, A.N.; Byrka, O.V.; Kulik, N.V.; Landman, I.; Wuerz, H.

    2002-01-01

    This paper is focused on experimental analysis of metal layer erosion and droplet splashing of tungsten and other metals under heat loads typical for ITER FEAT off-normal events,such as disruptions and VDE's. Plasma pressure gradient action on melt layer results in erosion crater formation with mountains of displaced material at the crater edge. It is shown that macroscopic motion of melt layer and surface cracking are the main factors responsible for tungsten damage. Weight loss measurements of all exposed materials demonstrate inessential contribution of evaporation process to metals erosion

  18. Monolayer field effect transistor as a probe of electronic defects in organic semiconducting layers at organic/inorganic hetero-junction interface

    Energy Technology Data Exchange (ETDEWEB)

    Park, Byoungnam, E-mail: metalpbn@hongik.ac.kr

    2016-01-01

    The origin of a large negative threshold voltage observed in monolayer (ML) field effect transistors (FETs) is explored using in-situ electrical measurements through confining the thickness of an active layer to the accumulation layer thickness. Using ML pentacene FETs combined with gated multiple-terminal devices and atomic force microscopy, the effect of electronic and structural evolution of a ML pentacene film on the threshold voltage in an FET, proportional to the density of deep traps, was probed, revealing that a large negative threshold voltage found in ML FETs results from the pentacene/SiO{sub 2} and pentacene/metal interfaces. More importantly, the origin of the threshold voltage difference between ML and thick FETs is addressed through a model in which the effective charge transport layer is transitioned from the pentacene layer interfacing with the SiO{sub 2} gate dielectric to the upper layers with pentacene thickness increasing evidenced by pentacene coverage dependent threshold voltage measurements. - Highlights: • The origin of a large negative threshold voltage in accumulation layer is revealed. • Electronic localized states at the nanometer scale are separately probed from the bulk. • The second monolayer becomes the effective charge transport layer governing threshold voltage.

  19. Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging?

    Directory of Open Access Journals (Sweden)

    Takashi Ando

    2012-03-01

    Full Text Available Current status and challenges of aggressive equivalent-oxide-thickness (EOT scaling of high-κ gate dielectrics via higher-κ ( > 20 materials and interfacial layer (IL scavenging techniques are reviewed. La-based higher-κ materials show aggressive EOT scaling (0.5–0.8 nm, but with effective workfunction (EWF values suitable only for n-type field-effect-transistor (FET. Further exploration for p-type FET-compatible higher-κ materials is needed. Meanwhile, IL scavenging is a promising approach to extend Hf-based high-κ dielectrics to future nodes. Remote IL scavenging techniques enable EOT scaling below 0.5 nm. Mobility-EOT trends in the literature suggest that short-channel performance improvement is attainable with aggressive EOT scaling via IL scavenging or La-silicate formation. However, extreme IL scaling (e.g., zero-IL is accompanied by loss of EWF control and with severe penalty in reliability. Therefore, highly precise IL thickness control in an ultra-thin IL regime ( < 0.5 nm will be the key technology to satisfy both performance and reliability requirements for future CMOS devices.

  20. Pentacene thin-film transistors and inverters with plasma-enhanced atomic-layer-deposited Al2O3 gate dielectric

    International Nuclear Information System (INIS)

    Koo, Jae Bon; Lim, Jung Wook; Kim, Seong Hyun; Yun, Sun Jin; Ku, Chan Hoe; Lim, Sang Chul; Lee, Jung Hun

    2007-01-01

    The performances of pentacene thin-film transistor with plasma-enhanced atomic-layer-deposited (PEALD) 150 nm thick Al 2 O 3 dielectric are reported. Saturation mobility of 0.38 cm 2 /V s, threshold voltage of 1 V, subthreshold swing of 0.6 V/decade, and on/off current ratio of about 10 8 have been obtained. Both depletion and enhancement mode inverter have been realized with the change of treatment method of hexamethyldisilazane on PEALD Al 2 O 3 gate dielectric. Full swing depletion mode inverter has been demonstrated at input voltages ranging from 5 V to - 5 V at supply voltage of - 5 V

  1. Formation of nanocrystalline surface layers in various metallic materials by near surface severe plastic deformation

    Directory of Open Access Journals (Sweden)

    Masahide Sato, Nobuhiro Tsuji, Yoritoshi Minamino and Yuichiro Koizumi

    2004-01-01

    Full Text Available The surface of the various kinds of metallic materials sheets were severely deformed by wire-brushing at ambient temperature to achieve nanocrystalline surface layer. The surface layers of the metallic materials developed by the near surface severe plastic deformation (NS-SPD were characterized by means of TEM. Nearly equiaxed nanocrystals with grain sizes ranging from 30 to 200 nm were observed in the near surface regions of all the severely scratched metallic materials, which are Ti-added ultra-low carbon interstitial free steel, austenitic stainless steel (SUS304, 99.99 wt.%Al, commercial purity aluminum (A1050 and A1100, Al–Mg alloy (A5083, Al-4 wt.%Cu alloy, OFHC-Cu (C1020, Cu–Zn alloy (C2600 and Pb-1.5%Sn alloy. In case of the 1050-H24 aluminum, the depth of the surface nanocrystalline layer was about 15 μm. It was clarified that wire-brushing is an effective way of NS-SPD, and surface nanocrystallization can be easily achieved in most of metallic materials.

  2. Metal Surface Modification for Obtaining Nano- and Sub-Nanostructured Protective Layers

    OpenAIRE

    Ledovskykh, Volodymyr; Vyshnevska, Yuliya; Brazhnyk, Igor; Levchenko, Sergiy

    2017-01-01

    Regularities of the phase protective layer formation in multicomponent systems involving inhibitors with different mechanism of protective action have been investigated. It was shown that optimization of the composition of the inhibition mixture allows to obtain higher protective efficiency owing to improved microstructure of the phase layer. It was found that mechanism of the film formation in the presence of NaNO2-PHMG is due to deposition of slightly soluble PHMG-Fe complexes on the metal ...

  3. Gate protective device for SOS array

    Science.gov (United States)

    Meyer, J. E., Jr.; Scott, J. H.

    1972-01-01

    Protective gate device consisting of alternating heavily doped n(+) and p(+) diffusions eliminates breakdown voltages in silicon oxide on sapphire arrays caused by electrostatic discharge from person or equipment. Diffusions are easily produced during normal double epitaxial processing. Devices with nine layers had 27-volt breakdown.

  4. General access to metal oxide (Metal = Mn, Co, Ni) double-layer nanospheres for application in lithium ion batteries and supercapacitors

    International Nuclear Information System (INIS)

    Xia, Yuan; Wang, Gang; Zhang, Xing; Wang, Beibei; Wang, Hui

    2016-01-01

    Highlights: • A series of metal oxide double layer nanospheres were prepared. • The obtained materials show excellent performances in lithium ion batteries and supercapacitors. • The unique structure of double layers is beneficial for superior electrochemical performances. - Abstract: In this work, a series of metal oxide double-layer nanospheres (DLNs), such as Mn 2 O 3 , Co 3 O 4 , NiO, NiCo 2 O 4 , and MnCo 2 O 4 have been successfully synthesized through a general template method. The layers of nanospheres were assembled by different nanostructure units and the removing of the SiO 2 template formed a void of several ten nanometers between the double layers, resulting large specific surface areas for them. The energy storage performances of the as-prepared double-layer nanospheres were further investigated in lithium ion battery and supercapacitor systems. Based on their unique nanostructures, the double-layer nanospheres exhibit excellent electrochemical performance with long cycle stability and high specific capacities or capacitances. The best of these, DLNs-NiCo 2 O 4 can deliver a reversible capacity of 1107 mAh g −1 at 0.25C after 200 cycles in lithium ion battery system, and shows a capacitance of 1088 F g −1 with capacitance loss of less than 3% at 5 A g −1 after 5000 cycles in supercapacitors.

  5. Transistor memory devices with large memory windows, using multi-stacking of densely packed, hydrophobic charge trapping metal nanoparticle array

    International Nuclear Information System (INIS)

    Cho, Ikjun; Cho, Jinhan; Kim, Beom Joon; Cho, Jeong Ho; Ryu, Sook Won

    2014-01-01

    Organic field-effect transistor (OFET) memories have rapidly evolved from low-cost and flexible electronics with relatively low-memory capacities to memory devices that require high-capacity memory such as smart memory cards or solid-state hard drives. Here, we report the high-capacity OFET memories based on the multilayer stacking of densely packed hydrophobic metal NP layers in place of the traditional transistor memory systems based on a single charge trapping layer. We demonstrated that the memory performances of devices could be significantly enhanced by controlling the adsorption isotherm behavior, multilayer stacking structure and hydrophobicity of the metal NPs. For this study, tetraoctylammonium (TOA)-stabilized Au nanoparticles (TOA-Au NPs ) were consecutively layer-by-layer (LbL) assembled with an amine-functionalized poly(amidoamine) dendrimer (PAD). The formed (PAD/TOA-Au NP ) n films were used as a multilayer stacked charge trapping layer at the interface between the tunneling dielectric layer and the SiO 2 gate dielectric layer. For a single Au NP layer (i.e. PAD/TOA-Au NP ) 1 ) with a number density of 1.82 × 10 12 cm −2 , the memory window of the OFET memory device was measured to be approximately 97 V. The multilayer stacked OFET memory devices prepared with four Au NP layers exhibited excellent programmable memory properties (i.e. a large memory window (ΔV th ) exceeding 145 V, a fast switching speed (1 μs), a high program/erase (P/E) current ratio (greater than 10 6 ) and good electrical reliability) during writing and erasing over a relatively short time scale under an operation voltage of 100 V applied at the gate. (paper)

  6. Thin film complementary metal oxide semiconductor (CMOS) device using a single-step deposition of the channel layer

    KAUST Repository

    Nayak, Pradipta K.

    2014-04-14

    We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n-and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications.

  7. Temperature dependence of trapping effects in metal gates/Al2O3/InGaAs stacks

    Science.gov (United States)

    Palumbo, F.; Pazos, S.; Aguirre, F.; Winter, R.; Krylov, I.; Eizenberg, M.

    2017-06-01

    The influence of the temperature on Metal Gate/Al2O3/n-InGaAs stacks has been studied by means of capacitance-voltage (C-V) hysteresis and flat band voltage as function of both negative and positive stress fields. It was found that the de-trapping effect decreases at low-temperature, indicating that the de-trapping of trapped electrons from oxide traps may be performed via Al2O3/InGaAs interface defects. The dependence of the C-V hysteresis on the stress field at different temperatures in our InGaAs stacks can be explained in terms of the defect spatial distribution. An oxide defect distribution can be found very close to the metal gate/Al2O3 interface. On the other side, the Al2O3/InGaAs interface presents defects distributed from the interface into the bulk of the oxide, showing the influence of InGaAs on Al2O3 in terms of the spatial defect distribution. At the present, he is a research staff of the National Council of Science and Technology (CONICET), working in the National Commission of Atomic Energy (CNEA) in Buenos Aires, Argentina, well embedded within international research collaboration. Since 2008, he is Professor at the National Technological University (UTN) in Buenos Aires, Argentina. Dr. Palumbo has received research fellowships from: Marie Curie Fellowship within the 7th European Community Framework Programme, Abdus Salam International Centre for Theoretical Physics (ICTP) Italy, National Council of Science and Technology (CONICET) Argentina, and Consiglio Nazionale delle Ricerche (CNR) Italy. He is also a frequent scientific visitor of academic institutions as IMM-CNR-Italy, Minatec Grenoble-France, the Autonomous University of Barcelona-Spain, and the Israel Institute of Technology-Technion. He has authored and co-authored more than 50 papers in international conferences and journals.

  8. Layer-by-Layer Method for the Synthesis and Growth of Surface Mounted Metal-Organic Frameworks (SURMOFs

    Directory of Open Access Journals (Sweden)

    Osama Shekhah

    2010-02-01

    Full Text Available A layer-by-layer method has been developed for the synthesis of metal-organic frameworks (MOFs and their deposition on functionalized organic surfaces. The approach is based on the sequential immersion of functionalized organic surfaces into solutions of the building blocks of the MOF, i.e., the organic ligand and the inorganic unit. The synthesis and growth of different types of MOFs on substrates with different functionalization, like COOH, OH and pyridine terminated surfaces, were studied and characterized with different surface characterization techniques. A controlled and highly oriented growth of very homogenous films was obtained using this method. The layer-by-layer method offered also the possibility to study the kinetics of film formation in more detail using surface plasmon resonance and quartz crystal microbalance. In addition, this method demonstrates the potential to synthesize new classes of MOFs not accessible by conventional methods. Finally, the controlled growth of MOF thin films is important for many applications like chemical sensors, membranes and related electrodes.

  9. Photodetection in p–n junctions formed by electrolyte-gated transistors of two-dimensional crystals

    KAUST Repository

    Kozawa, Daichi

    2016-11-16

    Transition metal dichalcogenide monolayers have attracted much attention due to their strong light absorption and excellent electronic properties. These advantages make this type of two-dimensional crystal a promising one for optoelectronic device applications. In the case of photoelectric conversion devices such as photodetectors and photovoltaic cells, p–n junctions are one of the most important devices. Here, we demonstrate photodetection with WSe2 monolayer films. We prepare the electrolyte-gated ambipolar transistors and electrostatic p–n junctions are formed by the electrolyte-gating technique at 270 K. These p-n junctions are cooled down to fix the ion motion (and p-n junctions) and we observed the reasonable photocurrent spectra without the external bias, indicating the formation of p-n junctions. Very interestingly, two-terminal devices exhibit higher photoresponsivity than that of three-terminal ones, suggesting the formation of highly balanced anion and cation layers. The maximum photoresponsivity reaches 5 mA/W in resonance with the first excitonic peak. Our technique provides important evidence for optoelectronics in atomically thin crystals.

  10. Photodetection in p–n junctions formed by electrolyte-gated transistors of two-dimensional crystals

    KAUST Repository

    Kozawa, Daichi; Pu, Jiang; Shimizu, Ryo; Kimura, Shota; Chiu, Ming-Hui; Matsuki, Keiichiro; Wada, Yoshifumi; Sakanoue, Tomo; Iwasa, Yoshihiro; Li, Lain-Jong; Takenobu, Taishi

    2016-01-01

    Transition metal dichalcogenide monolayers have attracted much attention due to their strong light absorption and excellent electronic properties. These advantages make this type of two-dimensional crystal a promising one for optoelectronic device applications. In the case of photoelectric conversion devices such as photodetectors and photovoltaic cells, p–n junctions are one of the most important devices. Here, we demonstrate photodetection with WSe2 monolayer films. We prepare the electrolyte-gated ambipolar transistors and electrostatic p–n junctions are formed by the electrolyte-gating technique at 270 K. These p-n junctions are cooled down to fix the ion motion (and p-n junctions) and we observed the reasonable photocurrent spectra without the external bias, indicating the formation of p-n junctions. Very interestingly, two-terminal devices exhibit higher photoresponsivity than that of three-terminal ones, suggesting the formation of highly balanced anion and cation layers. The maximum photoresponsivity reaches 5 mA/W in resonance with the first excitonic peak. Our technique provides important evidence for optoelectronics in atomically thin crystals.

  11. Spectra of magnetoplasma polaritons in a semiconductor layer on a metallic substrate

    International Nuclear Information System (INIS)

    Beletsekii, N.N.; Gasan, E.A.; Yakovenko, V.M.

    1988-01-01

    The dispersion properties of volume and surface magnetoplasma polaritons in a three-layer metal-semiconductor-insulator structure are studied. It is predicted that surface magnetoplasma polaritons propagating on the two boundaries of the semiconductor layer interact resonantly. It is shown that for a certain direction of propagation the dispersion curves of surface and volume magnetoplasma polaritons contain sections with negative dispersion. Nonreciprocal propagation of volume magnetoplasma polaritons has been observed. Losses in the semiconductor layer split the starting spectral lines into dispersion curves of two types, corresponding to forward and backward waves

  12. Near-thermal limit gating in heavily doped III-V semiconductor nanowires using polymer electrolytes

    Science.gov (United States)

    Ullah, A. R.; Carrad, D. J.; Krogstrup, P.; Nygârd, J.; Micolich, A. P.

    2018-02-01

    Doping is a common route to reducing nanowire transistor on-resistance but it has limits. A high doping level gives significant loss in gate performance and ultimately complete gate failure. We show that electrolyte gating remains effective even when the Be doping in our GaAs nanowires is so high that traditional metal-oxide gates fail. In this regime we obtain a combination of subthreshold swing and contact resistance that surpasses the best existing p -type nanowire metal-oxide semiconductor field-effect transistors (MOSFETs). Our subthreshold swing of 75 mV/dec is within 25 % of the room-temperature thermal limit and comparable with n -InP and n -GaAs nanowire MOSFETs. Our results open a new path to extending the performance and application of nanowire transistors, and motivate further work on improved solid electrolytes for nanoscale device applications.

  13. Decrease in effective electron mobility in the channel of a metal-oxide-semiconductor transistor as the gate length is decreased

    International Nuclear Information System (INIS)

    Frantsuzov, A. A.; Boyarkina, N. I.; Popov, V. P.

    2008-01-01

    Effective electron mobility μ eff in channels of metal-oxide-semiconductor transistors with a gate length L in the range of 3.8 to 0.34 μm was measured; the transistors were formed on wafers of the silicon-oninsulator type. It was found that μ eff decreases as L is decreased. It is shown that this decrease can be accounted for by the effect of series resistances of the source and drain only if it is assumed that there is a rapid increase in these resistances as the gate voltage is decreased. This assumption is difficult to substantiate. A more realistic model is suggested; this model accounts for the observed decrease in μ eff as L is decreased. The model implies that zones with a mobility lower than that in the middle part of the channel originate at the edges of the gate. An analysis shows that, in this case, the plot of the dependence of 1/μ eff on 1/L should be linear, which is exactly what is observed experimentally. The use of this plot makes it possible to determine both the electron mobility μ 0 in the middle part of the channel and the quantity A that characterizes the zones with lowered mobility at the gate’s edges.

  14. Scaling the Serialization of MOSFETs by Magnetically Coupling Their Gate Electrodes

    DEFF Research Database (Denmark)

    Dimopoulos, Emmanouil; Munk-Nielsen, Stig

    2013-01-01

    More than twenty years of thorough research on the serialization of power semiconductor switches, like the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) or the Insulated Gate Bipolar Transistor (IGBT), have resulted into several different stacking concepts; all aiming towards...... the establishment of a high-efficient, high-voltage, fast-switching device. Among the prevailing stacking approaches lies the gate balancing core technique, which, in its initial form, demonstrated very good performance in strings of high-power IGBT modules, by magnetically coupling their gate electrodes. Recently...

  15. Anomalous Temperature Dependence in Metal-Black Phosphorus Contact.

    Science.gov (United States)

    Li, Xuefei; Grassi, Roberto; Li, Sichao; Li, Tiaoyang; Xiong, Xiong; Low, Tony; Wu, Yanqing

    2018-01-10

    Metal-semiconductor contact has been the performance limiting problem for electronic devices and also dictates the scaling potential for future generation devices based on novel channel materials. Two-dimensional semiconductors beyond graphene, particularly few layer black phosphorus, have attracted much attention due to their exceptional electronic properties such as anisotropy and high mobility. However, due to its ultrathin body nature, few layer black phosphorus-metal contact behaves differently than conventional Schottky barrier (SB) junctions, and the mechanisms of its carrier transport across such a barrier remain elusive. In this work, we examine the transport characteristic of metal-black phosphorus contact under varying temperature. We elucidated the origin of apparent negative SB heights extracted from classical thermionic emission model and also the phenomenon of metal-insulator transition observed in the current-temperature transistor characteristic. In essence, we found that the SB height can be modulated by the back-gate voltage, which beyond a certain critical point becomes so low that the injected carrier can no longer be described by the conventional thermionic emission theory. The transition from transport dominated by a Maxwell-Boltzmann distribution for the high energy tail states, to that of a Fermi distribution by low energy Fermi sea electrons, is the physical origin of the observed metal-insulator transition. We identified two distinctive tunneling limited transport regimes in the contact: vertical and longitudinal tunneling.

  16. CMOS Active-Pixel Image Sensor With Simple Floating Gates

    Science.gov (United States)

    Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

    1996-01-01

    Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

  17. The relevance of electrostatics for scanning-gate microscopy

    International Nuclear Information System (INIS)

    Schnez, S; Guettinger, J; Stampfer, C; Ensslin, K; Ihn, T

    2011-01-01

    Scanning-probe techniques have been developed to extract local information from a given physical system. In particular, conductance maps obtained by means of scanning-gate microscopy (SGM), where a conducting tip of an atomic-force microscope is used as a local and movable gate, seem to present an intuitive picture of the underlying physical processes. Here, we argue that the interpretation of such images is complex and not very intuitive under certain circumstances: scanning a graphene quantum dot (QD) in the Coulomb-blockaded regime, we observe an apparent shift of features in scanning-gate images as a function of gate voltages, which cannot be a real shift of the physical system. Furthermore, we demonstrate the appearance of more than one set of Coulomb rings arising from the graphene QD. We attribute these effects to screening between the metallic tip and the gates. Our results are relevant for SGM on any kind of nanostructure, but are of particular importance for nanostructures that are not covered with a dielectric, e.g. graphene or carbon nanotube structures.

  18. Plated copper front side metallization on printed seed-layers for silicon solar cells

    OpenAIRE

    Kraft, Achim

    2015-01-01

    A novel copper front side metallization architecture for silicon solar cells based on a fine printed silver seed-layer, plated with nickel, copper and silver, is investigated. The work focuses on the printing of fine seed-layers with low silver consumption, the corrosion of the printed seed-layers by the interaction with electrolyte solutions and the encapsulation material on module level and on the long term stability of the cells due to copper migration. The investigation of the correlation...

  19. Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

    International Nuclear Information System (INIS)

    Wan, Chang Jin; Wan, Qing; Zhu, Li Qiang; Wan, Xiang; Shi, Yi

    2016-01-01

    The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors

  20. Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

    Energy Technology Data Exchange (ETDEWEB)

    Wan, Chang Jin; Wan, Qing, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn [School of Electronic Science & Engineering, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China); Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Zhu, Li Qiang [Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Wan, Xiang; Shi, Yi, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn [School of Electronic Science & Engineering, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)

    2016-01-25

    The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors.

  1. Removal of contaminated asphalt layers by using heat generating powder metallic systems

    International Nuclear Information System (INIS)

    Barinov, A.S.; Karlina, O.K.; Ojovan, M.I.

    1996-01-01

    Heat generating systems on the base of powder metallic fuel were used for the removal of contaminated asphalt layers. Decontamination of spots which had complex geometric form was performed. Asphalt layers with deep contamination were removed essentially all radionuclides being retained in asphalt residue. Only a small part (1 - 2 %) of radionuclides could pass to combustion slag. No radionuclides were detected in aerosol-gas phase during decontamination process

  2. High performance organic field-effect transistors with ultra-thin HfO2 gate insulator deposited directly onto the organic semiconductor

    International Nuclear Information System (INIS)

    Ono, S.; Häusermann, R.; Chiba, D.; Shimamura, K.; Ono, T.; Batlogg, B.

    2014-01-01

    We have produced stable organic field-effect transistors (OFETs) with an ultra-thin HfO 2 gate insulator deposited directly on top of rubrene single crystals by atomic layer deposition (ALD). We find that ALD is a gentle deposition process to grow thin films without damaging rubrene single crystals, as results these devices have a negligibly small threshold voltage and are very stable against gate-bias-stress, and the mobility exceeds 1 cm 2 /V s. Moreover, the devices show very little degradation even when kept in air for more than 2 months. These results demonstrate thin HfO 2 layers deposited by ALD to be well suited as high capacitance gate dielectrics in OFETs operating at small gate voltage. In addition, the dielectric layer acts as an effective passivation layer to protect the organic semiconductor

  3. Sliding wear resistance of metal matrix composite layers prepared by high power laser

    NARCIS (Netherlands)

    Ocelik, Vaclav; Matthews, D; de Hosson, Jeff

    2005-01-01

    Two laser surface engineering techniques, Laser Cladding and Laser Melt Injection (LMI), were used to prepare three different metal matrix composite layers with a thickness of about 1 mm and approximately 25-30% volume fraction of ceramic particles. SiC/Al-8Si, WC/Ti-6Al-4V and TiB2/Ti-6Al-4V layers

  4. Selective porous gates made from colloidal silica nanoparticles

    Directory of Open Access Journals (Sweden)

    Roberto Nisticò

    2015-11-01

    Full Text Available Highly selective porous films were prepared by spin-coating deposition of colloidal silica nanoparticles on an appropriate macroporous substrate. Silica nanoparticles very homogenous in size were obtained by sol–gel reaction of a metal oxide silica precursor, tetraethyl orthosilicate (TEOS, and using polystyrene-block-poly(ethylene oxide (PS-b-PEO copolymers as soft-templating agents. Nanoparticles synthesis was carried out in a mixed solvent system. After spin-coating onto a macroporous silicon nitride support, silica nanoparticles were calcined under controlled conditions. An organized nanoporous layer was obtained characterized by a depth filter-like structure with internal porosity due to interparticle voids. Permeability and size-selectivity were studied by monitoring the diffusion of probe molecules under standard conditions and under the application of an external stimulus (i.e., electric field. Promising results were obtained, suggesting possible applications of these nanoporous films as selective gates for controlled transport of chemical species in solution.

  5. Advanced metal lift-off process using electron-beam flood exposure of single-layer photoresist

    Science.gov (United States)

    Minter, Jason P.; Ross, Matthew F.; Livesay, William R.; Wong, Selmer S.; Narcy, Mark E.; Marlowe, Trey

    1999-06-01

    In the manufacture of many types of integrated circuit and thin film devices, it is desirable to use a lift-of process for the metallization step to avoid manufacturing problems encountered when creating metal interconnect structures using plasma etch. These problems include both metal adhesion and plasma etch difficulties. Key to the success of the lift-off process is the creation of a retrograde or undercut profile in the photoresists before the metal deposition step. Until now, lift-off processing has relied on costly multi-layer photoresists schemes, image reversal, and non-repeatable photoresist processes to obtain the desired lift-off profiles in patterned photoresist. This paper present a simple, repeatable process for creating robust, user-defined lift-off profiles in single layer photoresist using a non-thermal electron beam flood exposure. For this investigation, lift-off profiles created using electron beam flood exposure of many popular photoresists were evaluated. Results of lift-off profiles created in positive tone AZ7209 and ip3250 are presented here.

  6. Interfacial and Electrical Properties of Ge MOS Capacitor by ZrLaON Passivation Layer and Fluorine Incorporation

    Science.gov (United States)

    Huang, Yong; Xu, Jing-Ping; Liu, Lu; Cheng, Zhi-Xiang; Lai, Pui-To; Tang, Wing-Man

    2017-09-01

    Ge Metal-Oxide-Semiconductor (MOS) capacitor with HfTiON/ZrLaON stacked gate dielectric and fluorine-plasma treatment is fabricated, and its interfacial and electrical properties are compared with its counterparts without the ZrLaON passivation layer or the fluorine-plasma treatment. Experimental results show that the sample exhibits excellent performances: low interface-state density (3.7×1011 cm-2eV-1), small flatband voltage (0.21 V), good capacitance-voltage behavior, small frequency dispersion and low gate leakage current (4.41×10-5 A/cm2 at Vg = Vfb + 1V). These should be attributed to the suppressed growth of unstable Ge oxides on the Ge surface during gate-dielectric annealing by the ZrLaON interlayer and fluorine incorporation, thus greatly reducing the defective states at/near the ZrLaON/Ge interface and improving the electrical properties of the device.

  7. C-V characterization of Schottky- and MIS-gate SiGe/Si HEMT structures

    International Nuclear Information System (INIS)

    Onojima, Norio; Kasamatsu, Akihumi; Hirose, Nobumitsu; Mimura, Takashi; Matsui, Toshiaki

    2008-01-01

    Electrical properties of Schottky- and metal-insulator-semiconductor (MIS)-gate SiGe/Si high electron mobility transistors (HEMTs) were investigated with capacitance-voltage (C-V) measurements. The MIS-gate HEMT structure was fabricated using a SiN gate insulator formed by catalytic chemical vapor deposition (Cat-CVD). The Cat-CVD SiN thin film (5 nm) was found to be an effective gate insulator with good gate controllability and dielectric properties. We previously investigated device characteristics of sub-100-nm-gate-length Schottky- and MIS-gate HEMTs, and reported that the MIS-gate device had larger maximum drain current density and transconductance (g m ) than the Schottky-gate device. The radio frequency (RF) measurement of the MIS-gate device, however, showed a relatively lower current gain cutoff frequency f T compared with that of the Schottky-gate device. In this study, C-V characterization of the MIS-gate HEMT structure demonstrated that two electron transport channels existed, one at the SiGe/Si buried channel and the other at the SiN/Si surface channel

  8. C-V characterization of Schottky- and MIS-gate SiGe/Si HEMT structures

    Energy Technology Data Exchange (ETDEWEB)

    Onojima, Norio [National Institute of Information and Communications Technology (NICT), Koganei, Tokyo 184-8795 (Japan)], E-mail: nonojima@nict.go.jp; Kasamatsu, Akihumi; Hirose, Nobumitsu [National Institute of Information and Communications Technology (NICT), Koganei, Tokyo 184-8795 (Japan); Mimura, Takashi [National Institute of Information and Communications Technology (NICT), Koganei, Tokyo 184-8795 (Japan); Fujitsu Laboratories Ltd., Atsugi, Kanagawa 243-0197 (Japan); Matsui, Toshiaki [National Institute of Information and Communications Technology (NICT), Koganei, Tokyo 184-8795 (Japan)

    2008-07-30

    Electrical properties of Schottky- and metal-insulator-semiconductor (MIS)-gate SiGe/Si high electron mobility transistors (HEMTs) were investigated with capacitance-voltage (C-V) measurements. The MIS-gate HEMT structure was fabricated using a SiN gate insulator formed by catalytic chemical vapor deposition (Cat-CVD). The Cat-CVD SiN thin film (5 nm) was found to be an effective gate insulator with good gate controllability and dielectric properties. We previously investigated device characteristics of sub-100-nm-gate-length Schottky- and MIS-gate HEMTs, and reported that the MIS-gate device had larger maximum drain current density and transconductance (g{sub m}) than the Schottky-gate device. The radio frequency (RF) measurement of the MIS-gate device, however, showed a relatively lower current gain cutoff frequency f{sub T} compared with that of the Schottky-gate device. In this study, C-V characterization of the MIS-gate HEMT structure demonstrated that two electron transport channels existed, one at the SiGe/Si buried channel and the other at the SiN/Si surface channel.

  9. Growth of micrometric oxide layers to explore laser decontamination of metallic surfaces

    Directory of Open Access Journals (Sweden)

    Carvalho Luisa

    2017-01-01

    Full Text Available The nuclear industry produces a wide range of radioactive waste in terms of hazard level, contaminants and material. For metallic equipment like steam generators, the radioactivity is mainly located in the oxide surface. In order to study and develop safe techniques for dismantling and for decontamination, it is important to have access to oxide layers with a representative distribution of non-radioactive contaminants. In this paper we propose a method for the creation of oxide layers on stainless steel 304L with europium (Eu as contaminant. This technique consists in spraying an Eu-solution on stainless steel samples. The specimens are firstly treated with a pulsed nanosecond laser after which the steel samples are placed in a 873 K furnace for various durations in order to grow an oxide layer. The oxide structure and in-depth distribution of Eu in the oxide layer were analyzed by scanning electron microscopy coupled to an energy-dispersive X-ray microanalyzer, as well as by glow discharge optical emission or mass spectrometry. The oxide layers were grown to thicknesses in the range of 200 nm–4.5 μm depending on the laser treatment parameters and the heating duration. These contaminated oxides had a ‘duplex structure’ with a mean concentration of the order of 6 × 1016 atoms/cm2 (15 μg/cm2 of europium in the volume of the oxide layer. It appears that europium implementation prevented the oxide growth in the furnace. Nevertheless, the presence of the contamination had no impact on the thickness of the oxide layers obtained by preliminary laser treatment. These oxide layers were used to study the decontamination of metallic surfaces such as stainless steel 304L using a nanosecond pulsed laser.

  10. Heat-resistant organic molecular layer as a joint interface for metal reduction on plastics surfaces

    International Nuclear Information System (INIS)

    Sang, Jing; Aisawa, Sumio; Hirahara, Hidetoshi; Kudo, Takahiro; Mori, Kunio

    2016-01-01

    Graphical abstract: - Highlights: • In situ adsorption behaviors of TES on PA6 surface were clarified by QCM. • Highest adsorption of TES on PA6 was obtained in pH 3 and 0.1 M solution. • Molecular layers of TES with uniform structures were prepared on PA6 surface. • TES layer improved PA6 local heat resistance from 150 °C to 230 °C. • TES molecular layer successfully reduced Ag ion to Ag"0. - Abstract: Heat-resistant organic molecular layers have been fabricated by triazine-based silane coupling agent for metal reduction on plastic surfaces using adsorption method. These molecular layers were used as an interfacial layer between polyamide (PA6) and metal solution to reduce Ag"+ ion to Ag"0. The interfacial behaviors of triazine molecular layer at the interfaces between PA6 and Ag solution were investigated using quartz crystal microbalance (QCM). The kinetics of molecular adsorption on PA6 was investigated by using triazine-based silane coupling agent solutions at different pH and concentration. X-ray photoelectron spectroscopy (XPS), atomic force microscope (AFM), and local nano thermal analysis were employed to characterize the surfaces and interfaces. The nano thermal analysis results show that molecular layers of triazine-based silane coupling agent greatly improved heat resistance of PA6 resin from 170 °C up to 230 °C. This research developed an in-depth insight for molecular behaviors of triazine-based silane coupling agent at the PA6 and Ag solution interfaces and should be of significant value for interfacial research between plastics and metal solution in plating industry.

  11. Heat-resistant organic molecular layer as a joint interface for metal reduction on plastics surfaces

    Energy Technology Data Exchange (ETDEWEB)

    Sang, Jing [Department of Frontier Materials and Function Engineering, Graduate School of Engineering, Iwate University, 4-3-5 Ueda, Morioka 020-8551 (Japan); Aisawa, Sumio, E-mail: aisawa@iwate-u.ac.jp [Department of Frontier Materials and Function Engineering, Graduate School of Engineering, Iwate University, 4-3-5 Ueda, Morioka 020-8551 (Japan); Hirahara, Hidetoshi [Department of Frontier Materials and Function Engineering, Graduate School of Engineering, Iwate University, 4-3-5 Ueda, Morioka 020-8551 (Japan); Kudo, Takahiro [Sulfur Chemical Institute, 210, Collabo MIU, 4-3-5, Ueda, Morioka 020-0066 (Japan); Mori, Kunio [Department of Frontier Materials and Function Engineering, Graduate School of Engineering, Iwate University, 4-3-5 Ueda, Morioka 020-8551 (Japan); Sulfur Chemical Institute, 210, Collabo MIU, 4-3-5, Ueda, Morioka 020-0066 (Japan)

    2016-04-15

    Graphical abstract: - Highlights: • In situ adsorption behaviors of TES on PA6 surface were clarified by QCM. • Highest adsorption of TES on PA6 was obtained in pH 3 and 0.1 M solution. • Molecular layers of TES with uniform structures were prepared on PA6 surface. • TES layer improved PA6 local heat resistance from 150 °C to 230 °C. • TES molecular layer successfully reduced Ag ion to Ag{sup 0}. - Abstract: Heat-resistant organic molecular layers have been fabricated by triazine-based silane coupling agent for metal reduction on plastic surfaces using adsorption method. These molecular layers were used as an interfacial layer between polyamide (PA6) and metal solution to reduce Ag{sup +} ion to Ag{sup 0}. The interfacial behaviors of triazine molecular layer at the interfaces between PA6 and Ag solution were investigated using quartz crystal microbalance (QCM). The kinetics of molecular adsorption on PA6 was investigated by using triazine-based silane coupling agent solutions at different pH and concentration. X-ray photoelectron spectroscopy (XPS), atomic force microscope (AFM), and local nano thermal analysis were employed to characterize the surfaces and interfaces. The nano thermal analysis results show that molecular layers of triazine-based silane coupling agent greatly improved heat resistance of PA6 resin from 170 °C up to 230 °C. This research developed an in-depth insight for molecular behaviors of triazine-based silane coupling agent at the PA6 and Ag solution interfaces and should be of significant value for interfacial research between plastics and metal solution in plating industry.

  12. Sol-gel deposition of buffer layers on biaxially textured metal substances

    Science.gov (United States)

    Shoup, Shara S.; Paranthamam, Mariappan; Beach, David B.; Kroeger, Donald M.; Goyal, Amit

    2000-01-01

    A method is disclosed for forming a biaxially textured buffer layer on a biaxially oriented metal substrate by using a sol-gel coating technique followed by pyrolyzing/annealing in a reducing atmosphere. This method is advantageous for providing substrates for depositing electronically active materials thereon.

  13. Synthesizing new types of ultrathin 2D metal oxide nanosheets via half-successive ion layer adsorption and reaction

    Science.gov (United States)

    Gao, Linjie; Li, Yaguang; Xiao, Mu; Wang, Shufang; Fu, Guangsheng; Wang, Lianzhou

    2017-06-01

    Two-dimensional (2D) metal oxide nanosheets have demonstrated their great potential in a broad range of applications. The existing synthesis strategies are mainly preparing 2D nanosheets from layered and specific transition metal oxides. How to prepare the other types of metal oxides as ultrathin 2D nanosheets remains unsolved, especially for metal oxides containing alkali, alkaline earth metal, and multiple metal elements. Herein, we developed a half-successive ion layer adsorption and reaction (SILAR) method, which could synthesize those types of metal oxides as ultrathin 2D nanosheets. The synthesized 2D metal oxides nanosheets are within 1 nm level thickness and 500 m2 · g-1 level surface area. This method allows us to develop many new types of ultrathin 2D metal oxides nanosheets that have never been prepared before.

  14. Photo-modulation of the spin Hall conductivity of mono-layer transition metal dichalcogenides

    Energy Technology Data Exchange (ETDEWEB)

    Sengupta, Parijat; Bellotti, Enrico [Department of Electrical and Computer Engineering, Boston University, Boston, MA 02215 (United States)

    2016-05-23

    We report on a possible optical tuning of the spin Hall conductivity in mono-layer transition metal dichalcogenides. Light beams of frequencies much higher than the energy scale of the system (the off-resonant condition) do not excite electrons but rearrange the band structure. The rearrangement is quantitatively established using the Floquet formalism. For such a system of mono-layer transition metal dichalcogenides, the spin Hall conductivity (calculated with the Kubo expression in presence of disorder) exhibits a drop at higher frequencies and lower intensities. Finally, we compare the spin Hall conductivity of the higher spin-orbit coupled WSe{sub 2} to MoS{sub 2}; the spin Hall conductivity of WSe{sub 2} was found to be larger.

  15. Silver doped metal layers for medical applications

    International Nuclear Information System (INIS)

    Kocourek, T; Jelínek, M; Mikšovský, J; Jurek, K; Weiserová, M

    2014-01-01

    Biological, physical and mechanical properties of silver-doped layers of titanium alloy Ti6Al4V and 316L steel prepared by pulsed laser deposition were studied. Metallic silver-doped coatings could be a new route for antibacterial protection in medicine. Thin films of silver and silver-doped materials were synthesized using KrF excimer laser deposition. The materials were ablated from two targets, which were composed either from titanium alloy with silver segments or from steel with silver segments. The concentration of silver ranged from 1.54 at% to 4.32 at% for steel and from 3.04 at% to 13.05 at% for titanium alloy. The layer properties such as silver content, structure, adhesion, surface wettability, and antibacterial efficacy (evaluated by Escherichia coli and Bacillus subtilis bacteria) were measured. Film adhesion was studied using scratch test. The antibacterial efficacy changed with silver doping up to 99.9 %. Our investigation was focused on minimum Ag concentration needed to reach high antibacterial efficiency, high film adhesion, and hardness.

  16. Silver-doped metal layers for medical applications

    International Nuclear Information System (INIS)

    Kocourek, T; Jelínek, M; Mikšovský, J; Jurek, K; Weiserová, M

    2014-01-01

    Biological, physical and mechanical properties of silver-doped layers of titanium alloy Ti6Al4V and 316 L steel prepared by pulsed laser deposition were studied. Metallic silver-doped coatings could be a new route for antibacterial protection in medicine. Thin films of silver and silver-doped materials were synthesized using KrF excimer laser deposition. The materials were ablated from two targets, which were composed either from titanium alloy with silver segments or from steel with silver segments. The concentration of silver ranged from 1.54 to 4.32 at% for steel and from 3.04 to 13.05 at% for titanium alloy. The layer properties such as silver content, structure, adhesion, surface wettability, and antibacterial efficiency (evaluated by Escherichia coli and Bacillus subtilis bacteria) were measured. Film adhesion was studied using a scratch test. The antibacterial efficiency changed with silver doping up to 99.9 %. Our investigation was focused on the minimum Ag concentration needed to reach high antibacterial efficiency, high film adhesion, and hardness. (paper)

  17. Insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor devices with Al2O3 or AlTiO gate dielectrics

    Science.gov (United States)

    Le, Son Phuong; Nguyen, Duong Dai; Suzuki, Toshi-kazu

    2018-01-01

    We have investigated insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor (MIS) devices with Al2O3 or AlTiO (an alloy of Al2O3 and TiO2) gate dielectrics obtained by atomic layer deposition on AlGaN. Analyzing insulator-thickness dependences of threshold voltages for the MIS devices, we evaluated positive interface fixed charges, whose density at the AlTiO/AlGaN interface is significantly lower than that at the Al2O3/AlGaN interface. This and a higher dielectric constant of AlTiO lead to rather shallower threshold voltages for the AlTiO gate dielectric than for Al2O3. The lower interface fixed charge density also leads to the fact that the two-dimensional electron concentration is a decreasing function of the insulator thickness for AlTiO, whereas being an increasing function for Al2O3. Moreover, we discuss the relationship between the interface fixed charges and interface states. From the conductance method, it is shown that the interface state densities are very similar at the Al2O3/AlGaN and AlTiO/AlGaN interfaces. Therefore, we consider that the lower AlTiO/AlGaN interface fixed charge density is not owing to electrons trapped at deep interface states compensating the positive fixed charges and can be attributed to a lower density of oxygen-related interface donors.

  18. Gate-bias and temperature dependence of charge transport in dinaphtho[2,3-b:2‧,3‧-d]thiophene thin-film transistors with MoO3/Au electrodes

    Science.gov (United States)

    Shaari, Safizan; Naka, Shigeki; Okada, Hiroyuki

    2018-04-01

    We investigated the gate-bias and temperature dependence of the voltage-current (V-I) characteristics of dinaphtho[2,3-b:2‧,3‧-d]thiophene with MoO3/Au electrodes. The insertion of the MoO3 layer significantly improved the device performance. The temperature dependent V-I characteristics were evaluated and could be well fitted by the Schottky thermionic emission model with barrier height under forward- and reverse-biased regimes in the ranges of 33-57 and 49-73 meV, respectively. However, at a gate voltage of 0 V, at which a small activation energy was obtained, we needed to consider another conduction mechanism at the grain boundary. From the obtained results, we concluded that two possible conduction mechanisms governed the charge injection at the metal electrode-organic semiconductor interface: the Schottky thermionic emission model and the conduction model in the organic thin-film layer and grain boundary.

  19. Characteristics and infl uence factors of mold fi lling process in permanent mold with a slot gating system

    Directory of Open Access Journals (Sweden)

    Chen Changjun

    2009-11-01

    Full Text Available The main problems caused by improper gating are entrained aluminum oxide fi lms and entrapped gas. In this study, the slot gating system is employed to improve mold fi lling behavior and therefore, to improve the quality of aluminum castings produced in permanent molds. An equipment as well as operation procedures for real-time X-ray radiography of molten aluminum fl owing into permanent molds have been developed. Graphite molds transparent to X-rays are utilized which make it possible to observe the fl ow pattern through a number of vertically oriented gating systems. The investigation discovers that there are many infl uencing factors on the mold fi lling process. This paper focuses its research on some of the factors, such as the dimensions of the vertical riser and slot thickness, as well as roughness of the coating layer. The results indicate that molten metal can smoothly fi ll into casting cavity with a proper slot gating system. A bigger vertical riser, proper slot thickness and rougher coating can provide not only a better mold fi lling pattern, but also hot melt into the top of the cavity. A proper temperature gradient is obtainable, higher at the bottom and lower at the top of the casting cavity, which is in favor of feeding during casting solidifi cation.

  20. Fabrication of Polymer Solar Cells Using Aqueous Processing for All Layers Including the Metal Back Electrode

    DEFF Research Database (Denmark)

    Søndergaard, Roar; Helgesen, Martin; Jørgensen, Mikkel

    2011-01-01

    The challenges of printing all layers in polymer solar cells from aqueous solution are met by design of inks for the electron-, hole-, active-, and metallic back electrode-layers. The conversion of each layer to an insoluble state after printing enables multilayer formation from the same solvent...

  1. AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor with Polarized P(VDF-TrFE) Ferroelectric Polymer Gating

    Science.gov (United States)

    Liu, Xinke; Lu, Youming; Yu, Wenjie; Wu, Jing; He, Jiazhu; Tang, Dan; Liu, Zhihong; Somasuntharam, Pannirselvam; Zhu, Deliang; Liu, Wenjun; Cao, Peijiang; Han, Sun; Chen, Shaojun; Seow Tan, Leng

    2015-01-01

    Effect of a polarized P(VDF-TrFE) ferroelectric polymer gating on AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) was investigated. The P(VDF-TrFE) gating in the source/drain access regions of AlGaN/GaN MOS-HEMTs was positively polarized (i.e., partially positively charged hydrogen were aligned to the AlGaN surface) by an applied electric field, resulting in a shift-down of the conduction band at the AlGaN/GaN interface. This increases the 2-dimensional electron gas (2-DEG) density in the source/drain access region of the AlGaN/GaN heterostructure, and thereby reduces the source/drain series resistance. Detailed material characterization of the P(VDF-TrFE) ferroelectric film was also carried out using the atomic force microscopy (AFM), X-ray Diffraction (XRD), and ferroelectric hysteresis loop measurement. PMID:26364872

  2. Optical absorption in silicon layers in the presence of charge inversion/accumulation or ion implantation

    International Nuclear Information System (INIS)

    Alloatti, L.; Lauermann, M.; Koos, C.; Freude, W.; Sürgers, C.; Leuthold, J.

    2013-01-01

    We determine the optical losses in gate-induced charge accumulation/inversion layers at a Si/SiO 2 interface. Comparison between gate-induced charge layers and ion-implanted thin silicon films having an identical sheet resistance shows that optical losses can be significantly lower for gate-induced layers. For a given sheet resistance, holes produce higher optical loss than electrons. Measurements have been performed at λ = 1550 nm

  3. A flexible ligand-based wavy layered metal-organic framework for lithium-ion storage.

    Science.gov (United States)

    An, Tiance; Wang, Yuhang; Tang, Jing; Wang, Yang; Zhang, Lijuan; Zheng, Gengfeng

    2015-05-01

    A substantial challenge for direct utilization of metal-organic frameworks (MOFs) as lithium-ion battery anodes is to maintain the rigid MOF structure during lithiation/delithiation cycles. In this work, we developed a flexible, wavy layered nickel-based MOF (C20H24Cl2N8Ni, designated as Ni-Me4bpz) by a solvothermal approach of 3,3',5,5'-tetramethyl-4,4'-bipyrazole (H2Me4bpz) with nickel(II) chloride hexahydrate. The obtained MOF materials (Ni-Me4bpz) with metal azolate coordination mode provide 2-dimensional layered structure for Li(+) intercalation/extraction, and the H2Me4bpz ligands allow for flexible rotation feature and structural stability. Lithium-ion battery anodes made of the Ni-Me4bpz material demonstrate excellent specific capacity and cycling performance, and the crystal structure is well preserved after the electrochemical tests, suggesting the potential of developing flexible layered MOFs for efficient and stable electrochemical storage. Copyright © 2015 Elsevier Inc. All rights reserved.

  4. Layer-by-Layer Motif Architectures: Programmed Electrochemical Syntheses of Multilayer Mesoporous Metallic Films with Uniformly Sized Pores.

    Science.gov (United States)

    Jiang, Bo; Li, Cuiling; Qian, Huayu; Hossain, Md Shahriar A; Malgras, Victor; Yamauchi, Yusuke

    2017-06-26

    Although multilayer films have been extensively reported, most compositions have been limited to non-catalytically active materials (e.g. polymers, proteins, lipids, or nucleic acids). Herein, we report the preparation of binder-free multilayer metallic mesoporous films with sufficient accessibility for high electrocatalytic activity by using a programmed electrochemical strategy. By precisely tuning the deposition potential and duration, multilayer mesoporous architectures consisting of alternating mesoporous Pd layers and mesoporous PdPt layers with controlled layer thicknesses can be synthesized within a single electrolyte, containing polymeric micelles as soft templates. This novel architecture, combining the advantages of bimetallic alloys, multilayer architectures, and mesoporous structures, exhibits high electrocatalytic activity for both the methanol oxidation reaction (MOR) and the ethanol oxidation reaction (EOR). © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

  5. Electrically Tunable and Negative Schottky Barriers in Multi-layered Graphene/MoS2 Heterostructured Transistors

    Science.gov (United States)

    Qiu, Dongri; Kim, Eun Kyu

    2015-09-01

    We fabricated multi-layered graphene/MoS2 heterostructured devices by positioning mechanically exfoliated bulk graphite and single-crystalline 2H-MoS2 onto Au metal pads on a SiO2/Si substrate via a contamination-free dry transfer technique. We also studied the electrical transport properties of Au/MoS2 junction devices for systematic comparison. A previous work has demonstrated the existence of a positive Schottky barrier height (SBH) in the metal/MoS2 system. However, analysis of the SBH indicates that the contacts of the multi-layered graphene/MoS2 have tunable negative barriers in the range of 300 to -46 meV as a function of gate voltage. It is hypothesized that this tunable SBH is responsible for the modulation of the work function of the thick graphene in these devices. Despite the large number of graphene layers, it is possible to form ohmic contacts, which will provide new opportunities for the engineering of highly efficient contacts in flexible electronics and photonics.

  6. Electrically Tunable and Negative Schottky Barriers in Multi-layered Graphene/MoS2 Heterostructured Transistors.

    Science.gov (United States)

    Qiu, Dongri; Kim, Eun Kyu

    2015-09-03

    We fabricated multi-layered graphene/MoS2 heterostructured devices by positioning mechanically exfoliated bulk graphite and single-crystalline 2H-MoS2 onto Au metal pads on a SiO2/Si substrate via a contamination-free dry transfer technique. We also studied the electrical transport properties of Au/MoS2 junction devices for systematic comparison. A previous work has demonstrated the existence of a positive Schottky barrier height (SBH) in the metal/MoS2 system. However, analysis of the SBH indicates that the contacts of the multi-layered graphene/MoS2 have tunable negative barriers in the range of 300 to -46 meV as a function of gate voltage. It is hypothesized that this tunable SBH is responsible for the modulation of the work function of the thick graphene in these devices. Despite the large number of graphene layers, it is possible to form ohmic contacts, which will provide new opportunities for the engineering of highly efficient contacts in flexible electronics and photonics.

  7. Low dielectric constant-based organic field-effect transistors and metal-insulator-semiconductor capacitors

    Science.gov (United States)

    Ukah, Ndubuisi Benjamin

    This thesis describes a study of PFB and pentacene-based organic field-effect transistors (OFET) and metal-insulator-semiconductor (MIS) capacitors with low dielectric constant (k) poly(methyl methacrylate) (PMMA), poly(4-vinyl phenol) (PVP) and cross-linked PVP (c-PVP) gate dielectrics. A physical method -- matrix assisted pulsed laser evaporation (MAPLE) -- of fabricating all-polymer field-effect transistors and MIS capacitors that circumvents inherent polymer dissolution and solvent-selectivity problems, is demonstrated. Pentacene-based OFETs incorporating PMMA and PVP gate dielectrics usually have high operating voltages related to the thickness of the dielectric layer. Reduced PMMA layer thickness (≤ 70 nm) was obtained by dissolving the PMMA in propylene carbonate (PC). The resulting pentacene-based transistors exhibited very low operating voltage (below -3 V), minimal hysteresis in their transfer characteristics, and decent electrical performance. Also low voltage (within -2 V) operation using thin (≤ 80 nm) low-k and hydrophilic PVP and c-PVP dielectric layers obtained via dissolution in high dipole moment and high-k solvents -- PC and dimethyl sulfoxide (DMSO), is demonstrated to be a robust means of achieving improved electrical characteristics and high operational stability in OFETs incorporating PVP and c-PVP dielectrics.

  8. Computational investigation of the effects of barrier layers on the permeation of hydrogen through metals

    International Nuclear Information System (INIS)

    Perkins, W.G.

    1975-01-01

    Results of a computational investigation of the permeation behavior of oxide-coated metal membranes are presented. A steady-state permeation model was developed which promises to be useful in evaluation of oxide layers on metals as hydrogen permeation barriers. The pressure and thickness dependence of steady state permeation through oxide-coated metal membranes is described using plots of logarithmic functions. (U.S.)

  9. Gate-tunable coherent transport in Se-capped Bi{sub 2}Se{sub 3} grown on amorphous SiO{sub 2}/Si

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Y. H.; Chong, C. W., E-mail: cheongwei2000@yahoo.com, E-mail: jcahuang@mail.ncku.edu.tw, E-mail: smhuang@mail.nsysu.edu.tw; Huang, S. Y. [Department of Physics, National Cheng Kung University, Tainan 70101, Taiwan (China); Jheng, J. L.; Huang, S. M., E-mail: cheongwei2000@yahoo.com, E-mail: jcahuang@mail.ncku.edu.tw, E-mail: smhuang@mail.nsysu.edu.tw [Department of Physics, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan (China); Huang, J. C. A., E-mail: cheongwei2000@yahoo.com, E-mail: jcahuang@mail.ncku.edu.tw, E-mail: smhuang@mail.nsysu.edu.tw [Department of Physics, National Cheng Kung University, Tainan 70101, Taiwan (China); Advanced Optoelectronic Technology Center (AOTC), National Cheng Kung University, Tainan 70101, Taiwan (China); Taiwan Consortium of Emergent Crystalline Materials (TCECM), Ministry of Science and Technology, Taipei 10622, Taiwan (China); Li, Z.; Qiu, H. [School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei, Anhui 230009 (China); Marchenkov, V. V. [M.N. Miheev Institute of Metal Physics, Ekaterinburg 620137 (Russian Federation)

    2015-07-06

    A topological insulator (TI) is an exotic material that has a bulk insulating gap and metallic surface states with unique spin-momentum locking characteristics. Despite its various important applications, large scale integration of TI into MOSFET technologies and its coherent transport study are still rarely explored. Here, we report the growth of high quality Bi{sub 2}Se{sub 3} thin film on amorphous SiO{sub 2}/Si substrate using MBE. By controlling the thickness of the film at ∼7 nm and capping the as grown film in situ with a 2 nm-thick Se layer, largest electrostatic field effect is obtained and the resistance is changed by almost 300%. More importantly, pronounced gate-tunable weak antilocalization (WAL) is observed, which refers to modulation of α from ∼−0.55 to ∼−0.2 by applying a back gate voltage. The analysis herein suggests that the significant gate-tunable WAL is attributable to the transition from weak disorder into intermediate disorder regime when the Fermi level is shifted downward by increasing the negative back gate voltage. Our findings may pave the ways towards the development of TI-based MOSFET and are promising for the applications of electric-field controlled spintronic and magnetic device.

  10. Development of membrane filters with nanostructured porous layer by coating of metal nanoparticles sintered onto a micro-filter

    International Nuclear Information System (INIS)

    Park, Seok Joo; Park, Young Ok; Lee, Dong Geun; Ryu, Jeong In

    2008-01-01

    The membrane filter adhered with nanostructured porous layer was made by heat treatment after deposition of nanoparticle-agglomerates sintered in aerosol phase onto a conventional micron-fibrous metal filter as a substrate filter. The Sintered-Nanoparticle-Agglomerates-coated NanoStructured porous layer Membrane Filter (SNA-NSMF), whose the filtration performance was improved compared with the conventional metal membrane filters, was developed by adhesion of nanoparticle-agglomerates of dendrite structure sintered onto the micron-fibrous metal filter. The size of nanoparticle-agglomerates of dendrite structure decreased with increasing the sintering temperature because nanoparticle-agglomerates shrank. When shrinking nanoparticle-agglomerates were deposited and treated with heat onto the conventional micron-fibrous metal filter, pore size of nanostructured porous layer decreased. Therefore, pressure drops of SNA-NSMFs increased from 0.3 to 0.516 KPa and filtration efficiencies remarkably increased from 95.612 to 99.9993%

  11. Terahertz modulation based on surface plasmon resonance by self-gated graphene

    Science.gov (United States)

    Qian, Zhenhai; Yang, Dongxiao; Wang, Wei

    2018-05-01

    We theoretically and numerically investigate the extraordinary optical transmission through a terahertz metamaterial composed of metallic ring aperture arrays. The physical mechanism of different transmission peaks is elucidated to be magnetic polaritons or propagation surface plasmons with the help of surface current and electromagnetic field distributions at respective resonance frequencies. Then, we propose a high performance terahertz modulator based on the unique PSP resonance and combined with the metallic ring aperture arrays and a self-gated parallel-plate graphene capacitor. Because, to date, few researches have exhibited gate-controlled graphene modulation in terahertz region with low insertion losses, high modulation depth and low control voltage at room temperature. Here, we propose a 96% amplitude modulation with 0.7 dB insertion losses and ∼5.5 V gate voltage. Besides, we further study the absorption spectra of the modulator. When the transmission of modulator is very low, a 91% absorption can be achieved for avoiding damaging the source devices.

  12. Growth of micrometric oxide layers to explore laser decontamination of metallic surfaces

    OpenAIRE

    Carvalho Luisa; Pacquentin Wilfried; Tabarant Michel; Maskrot Hicham; Semerok Alexandre

    2017-01-01

    The nuclear industry produces a wide range of radioactive waste in terms of hazard level, contaminants and material. For metallic equipment like steam generators, the radioactivity is mainly located in the oxide surface. In order to study and develop safe techniques for dismantling and for decontamination, it is important to have access to oxide layers with a representative distribution of non-radioactive contaminants. In this paper we propose a method for the creation of oxide layers on stai...

  13. Role of Oxygen in Ionic Liquid Gating on Two-Dimensional Cr2Ge2Te6: A Non-oxide Material.

    Science.gov (United States)

    Chen, Yangyang; Xing, Wenyu; Wang, Xirui; Shen, Bowen; Yuan, Wei; Su, Tang; Ma, Yang; Yao, Yunyan; Zhong, Jiangnan; Yun, Yu; Xie, X C; Jia, Shuang; Han, Wei

    2018-01-10

    Ionic liquid gating can markedly modulate a material's carrier density so as to induce metallization, superconductivity, and quantum phase transitions. One of the main issues is whether the mechanism of ionic liquid gating is an electrostatic field effect or an electrochemical effect, especially for oxide materials. Recent observation of the suppression of the ionic liquid gate-induced metallization in the presence of oxygen for oxide materials suggests the electrochemical effect. However, in more general scenarios, the role of oxygen in the ionic liquid gating effect is still unclear. Here, we perform ionic liquid gating experiments on a non-oxide material: two-dimensional ferromagnetic Cr 2 Ge 2 Te 6 . Our results demonstrate that despite the large increase of the gate leakage current in the presence of oxygen, the oxygen does not affect the ionic liquid gating effect on  the channel resistance of Cr 2 Ge 2 Te 6 devices (ionic liquid gating is more effective on the modulation of the channel resistances compared to the back gating across the 300 nm thick SiO 2 .

  14. A split accumulation gate architecture for silicon MOS quantum dots

    Science.gov (United States)

    Rochette, Sophie; Rudolph, Martin; Roy, Anne-Marie; Curry, Matthew; Ten Eyck, Gregory; Dominguez, Jason; Manginell, Ronald; Pluym, Tammy; King Gamble, John; Lilly, Michael; Bureau-Oxton, Chloé; Carroll, Malcolm S.; Pioro-Ladrière, Michel

    We investigate tunnel barrier modulation without barrier electrodes in a split accumulation gate architecture for silicon metal-oxide-semiconductor quantum dots (QD). The layout consists of two independent accumulation gates, one gate forming a reservoir and the other the QD. The devices are fabricated with a foundry-compatible, etched, poly-silicon gate stack. We demonstrate 4 orders of magnitude of tunnel-rate control between the QD and the reservoir by modulating the reservoir gate voltage. Last electron charging energies of app. 10 meV and tuning of the ST splitting in the range 100-200 ueV are observed in two different split gate layouts and labs. This work was performed, in part, at the Center for Integrated Nanotechnologies, an Office of Science User Facility operated for the U.S. Department of Energy (DOE) Office of Science. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.

  15. Gas-controlled dynamic vacuum insulation with gas gate

    Science.gov (United States)

    Benson, D.K.; Potter, T.F.

    1994-06-07

    Disclosed is a dynamic vacuum insulation comprising sidewalls enclosing an evacuated chamber and gas control means for releasing hydrogen gas into a chamber to increase gas molecule conduction of heat across the chamber and retrieving hydrogen gas from the chamber. The gas control means includes a metal hydride that absorbs and retains hydrogen gas at cooler temperatures and releases hydrogen gas at hotter temperatures; a hydride heating means for selectively heating the metal hydride to temperatures high enough to release hydrogen gas from the metal hydride; and gate means positioned between the metal hydride and the chamber for selectively allowing hydrogen to flow or not to flow between said metal hydride and said chamber. 25 figs.

  16. Solid-gate control of insulator to 2D metal transition at SrTiO3 surface

    Science.gov (United States)

    Schulman, Alejandro; Stoliar, Pablo; Kitoh, Ai; Rozenberg, Marcelo; Inoue, Isao H.

    As miniaturization of the semiconductor transistor approaches its limit, semiconductor industries are facing a major challenge to extend information processing beyond what can be attainable by conventional Si-based transistors. Innovative combinations of new materials and new processing platforms are desired. Recent discovery of the 2D electron gas (2DEG) at the surface of SrTiO3 (STO) and its electrostatic control, have carried it to the top of promising materials to be utilized in innovative devices. We report an electrostatic control of the carrier density of the 2DEG formed at the channel of bilayer-gated STO field-effect devices. By applying a gate electric field at room temperature, its highly insulating channel exhibits a transition to metallic one. This transition is accompanied by non-monotonic voltage-gain transfer characteristic with both negative and positive slope regions and unexpected enhancement of the sheet carrier density. We will introduce a numerical model to rationalize the observed features in terms of the established physics of field-effect transistors and the physics of percolation. Furthermore, we have found a clear signature of a Kondo effect that arises due to the interaction between the dilute 2DEG and localized Ti 3d orbitals originated by oxygen vacancies near the channel. On leave from CIC nanoGUNE, Spain.

  17. AlN metal-semiconductor field-effect transistors using Si-ion implantation

    Science.gov (United States)

    Okumura, Hironori; Suihkonen, Sami; Lemettinen, Jori; Uedono, Akira; Zhang, Yuhao; Piedra, Daniel; Palacios, Tomás

    2018-04-01

    We report on the electrical characterization of Si-ion implanted AlN layers and the first demonstration of metal-semiconductor field-effect transistors (MESFETs) with an ion-implanted AlN channel. The ion-implanted AlN layers with Si dose of 5 × 1014 cm-2 exhibit n-type characteristics after thermal annealing at 1230 °C. The ion-implanted AlN MESFETs provide good drain current saturation and stable pinch-off operation even at 250 °C. The off-state breakdown voltage is 2370 V for drain-to-gate spacing of 25 µm. These results show the great potential of AlN-channel transistors for high-temperature and high-power applications.

  18. Metal droplet erosion and shielding plasma layer under plasma flows typical of transient processes in tokamaks

    Energy Technology Data Exchange (ETDEWEB)

    Martynenko, Yu. V., E-mail: Martynenko-YV@nrcki.ru [National Research Nuclear University “MEPhI” (Russian Federation)

    2017-03-15

    It is shown that the shielding plasma layer and metal droplet erosion in tokamaks are closely interrelated, because shielding plasma forms from the evaporated metal droplets, while droplet erosion is caused by the shielding plasma flow over the melted metal surface. Analysis of experimental data and theoretical models of these processes is presented.

  19. Single-layer dispersions of transition metal dichalcogenides in the synthesis of intercalation compounds

    International Nuclear Information System (INIS)

    Golub, Alexander S; Zubavichus, Yan V; Slovokhotov, Yurii L; Novikov, Yurii N

    2003-01-01

    Chemical methods for the exfoliation of transition metal dichalcogenides in a liquid medium to give single-layer dispersions containing quasi-two-dimensional layers of these compounds are surveyed. Data on the structure of dispersions and their use in the synthesis of various types of heterolayered intercalation compounds are discussed and described systematically. Structural features, the electronic structure and the physicochemical properties of the resulting intercalation compounds are considered. The potential of this method of synthesis is compared with that of traditional solid-state methods for the intercalation of layered crystals.

  20. Analytical charge control model for AlGaN/GaN MIS-HFETs including an undepleted barrier layer

    Energy Technology Data Exchange (ETDEWEB)

    Shenghui, Lu; Jiangfeng, Du; Qian, Luo; Qi, Yu; Wei, Zhou; Jianxin, Xia; Mohua, Yang, E-mail: lushenghui@sohu.co [State key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054 (China)

    2010-09-15

    An analytical charge control model considering the insulator/AlGaN interface charge and undepleted Al-GaN barrier layer is presented for AlGaN/GaN metal-insulator-semiconductor heterostructure field effect transistors (MIS-HFETs) over the entire operation range of gate voltage. The whole process of charge control is analyzed in detail and partitioned into four regions: I-full depletion, II-partial depletion, III-neutral region and IV-electron accumulation at the insulator/AlGaN interface. The results show that two-dimensional electron gas (2DEG) saturates at the boundary of region II/III and the gate voltage should not exceed the 2DEG saturation voltage in order to keep the channel in control. In addition, the span of region II accounts for about 50% of the range of gate voltage before 2DEG saturates. The good agreement of the calculated transfer characteristic with the measured data confirms the validity of the proposed model. (semiconductor devices)

  1. High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure.

    Science.gov (United States)

    Chen, Szu-Hung; Liao, Wen-Shiang; Yang, Hsin-Chia; Wang, Shea-Jue; Liaw, Yue-Gie; Wang, Hao; Gu, Haoshuang; Wang, Mu-Chun

    2012-08-01

    A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal-semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

  2. Performance of organic field effect transistors with high-k gate oxide after application of consecutive bias stress

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Sunwoo; Choi, Changhwan; Lee, Kilbock [Department of Materials Science and Engineering, Hanyang University, Seoul, 133-791 (Korea, Republic of); Cho, Joong Hwee [Department of Embedded Systems Engineering,University of Incheon, Incheon 406-722 (Korea, Republic of); Ko, Ki-Young [Korea Institute of Patent Information, Seoul, 146-8 (Korea, Republic of); Ahn, Jinho, E-mail: jhahn@hanyang.ac.kr [Department of Materials Science and Engineering, Hanyang University, Seoul, 133-791 (Korea, Republic of)

    2012-10-30

    We report the effect of consecutive electrical stress on the performance of organic field effect transistors (OFETs). Sputtered aluminum oxide (Al{sub 2}O{sub 3}) and hafnium oxide (HfO{sub 2}) were used as gate oxide layers. After the electrical stress, the threshold voltage, which strongly depends on bulk defects, was remarkably shifted to the negative direction, while the other performance characteristics of OFETs such as on-current, transconductance and mobility, which are sensitive to interface defects, were slightly decreased. This result implies that the defects in the bulk layer are significantly affected compared to the defects in the interface layer. Thus, it is important to control the defects in the pentacene bulk layer in order to maintain the good reliabilities of pentacene devices. Those defects in HfO{sub 2} gate oxide devices were larger compared to those in Al{sub 2}O{sub 3} gate oxide devices.

  3. Gating techniques for ultrasonic thickness testing using flaw detectors

    Energy Technology Data Exchange (ETDEWEB)

    Holloway, P., E-mail: paul@hollowayndt.com [Holloway NDT & Engineering Inc., Georgetown, Ontario (Canada)

    2016-05-15

    The purpose of this article is to provide guidance on settings and methods, in particular the careful use of gating, to ensure accuracy of thickness testing on corroded steel and other metallic components. Specific applications include boiler tubes, tank floors, piping and vessels where the testing is performed from the OD or top surfaces, inspecting for metal loss due to corrosion on the opposite side. (author)

  4. Wear resistance of layers hard faced by the high-alloyed filler metal

    Directory of Open Access Journals (Sweden)

    Dušan Arsić

    2016-10-01

    Full Text Available The objective of this work was to determine the wear resistance of layers hard faced by the high-alloyed filler metal, with or without the austenite inter-layer, on parts that operate at different sliding speeds in conditions without lubrication. The samples were hard faced with the filler metal E 10-UM-60-C with high content of C, Cr and W. Used filler metal belongs into group of alloys aimed for reparatory hard facing of parts damaged by abrasive and erosive wear and it is characterized by high hardness and wear resistance. In experiments, the sliding speed and the normal loading were varied and the wear scar was monitored, based on which the volume of the worn material was calculated analytically. The contact duration time was monitored over the sliding path of 300 mm. The most intensive wear was established for the loading force of 100 N and the sliding speed of 1 m.s-1, though the significant wear was also noticed in conditions of the small loading and speed of 0.25 m.s-1, which was even greater that at larger speeds.

  5. Synthesis, characterization and application of two-dimensional layered metal hydroxides for environmental remediation purposes

    Science.gov (United States)

    Machingauta, Cleopas

    Two-dimensional layered nano composites, which include layered double hydroxides (LDHs), hydroxy double salts (HDSs) and layered hydroxide salts (LHSs) are able to intercalate different molecular species within their gallery space. These materials have a tunable structural composition which has made them applicable as fire retardants, adsorbents, catalysts, catalyst support materials, and ion exchangers. Thermal treatment of these materials results in destruction of the layers and formation of mixed metal oxides (MMOs) and spinels. MMOs have the ability to adsorb anions from solution and may also regenerate layered structures through a phenomenon known as memory effect. Zinc-nickel hydroxy nitrate was used for the uptake of a series of halogenated acetates (HAs). HAs are pollutants introduced into water systems as by-products of water chlorination and pesticide degradation; their sequestration from water is thus crucial. Optimization of layered materials for controlled uptake requires an understanding of their ion-exchange kinetics and thermodynamics. Exchange kinetics of these anions was monitored using ex-situ PXRD, UV-vis, HPLC and FTIR. It was revealed that exchange rates and uptake efficiencies are related to electronic spatial extents and the charge on carboxyl-oxygen atoms. In addition, acetate and nitrate-based HDSs were used to explore how altering the hydroxide layer affects uptake of acetate/nitrate ions. Changing the metal identities affects the interaction of the anions with the layers. From FTIR, we observed that nitrates coordinate in a D3h and Cs/C 2v symmetry; the nitrates in D3h symmetry were easily exchangeable. Interlayer hydrogen bonding was also revealed to be dependent on metal identity. Substituting divalent cations with trivalent cations produces materials with a higher charge density than HDSs and LHSs. A comparison of the uptake efficiency of zinc-aluminum, zinc-gallium and zinc-nickel hydroxy nitrates was performed using trichloroacetic

  6. Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

    Science.gov (United States)

    Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

    2016-01-01

    Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

  7. Unified analytical threshold voltage model for non-uniformly doped dual metal gate fully depleted silicon-on-insulator MOSFETs

    Science.gov (United States)

    Rao, Rathnamala; Katti, Guruprasad; Havaldar, Dnyanesh S.; DasGupta, Nandita; DasGupta, Amitava

    2009-03-01

    The paper describes the unified analytical threshold voltage model for non-uniformly doped, dual metal gate (DMG) fully depleted silicon-on-insulator (FDSOI) MOSFETs based on the solution of 2D Poisson's equation. 2D Poisson's equation is solved analytically for appropriate boundary conditions using separation of variables technique. The solution is then extended to obtain the threshold voltage of the FDSOI MOSFET. The model is able to handle any kind of non-uniform doping, viz. vertical, lateral as well as laterally asymetric channel (LAC) profile in the SOI film in addition to the DMG structure. The analytical results are validated with the numerical simulations using the device simulator MEDICI.

  8. Piezo-phototronic Boolean logic and computation using photon and strain dual-gated nanowire transistors.

    Science.gov (United States)

    Yu, Ruomeng; Wu, Wenzhuo; Pan, Caofeng; Wang, Zhaona; Ding, Yong; Wang, Zhong Lin

    2015-02-04

    Using polarization charges created at the metal-cadmium sulfide interface under strain to gate/modulate electrical transport and optoelectronic processes of charge carriers, the piezo-phototronic effect is applied to process mechanical and optical stimuli into electronic controlling signals. The cascade nanowire networks are demonstrated for achieving logic gates, binary computations, and gated D latches to store information carried by these stimuli. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  9. Selective-area growth and controlled substrate coupling of transition metal dichalcogenides

    Science.gov (United States)

    Bersch, Brian M.; Eichfeld, Sarah M.; Lin, Yu-Chuan; Zhang, Kehao; Bhimanapati, Ganesh R.; Piasecki, Aleksander F.; Labella, Michael, III; Robinson, Joshua A.

    2017-06-01

    Developing a means for true bottom-up, selective-area growth of two-dimensional (2D) materials on device-ready substrates will enable synthesis in regions only where they are needed. Here, we demonstrate seed-free, site-specific nucleation of transition metal dichalcogenides (TMDs) with precise control over lateral growth by utilizing an ultra-thin polymeric surface functionalization capable of precluding nucleation and growth. This polymer functional layer (PFL) is derived from conventional photoresists and lithographic processing, and is compatible with multiple growth techniques, precursors (metal organics, solid-source) and TMDs. Additionally, we demonstrate that the substrate can play a major role in TMD transport properties. With proper TMD/substrate decoupling, top-gated field-effect transistors (FETs) fabricated with selectively-grown monolayer MoS2 channels are competitive with current reported MoS2 FETs. The work presented here demonstrates that substrate surface engineering is key to realizing precisely located and geometrically-defined 2D layers via unseeded chemical vapor deposition techniques.

  10. Atomic layer-deposited Al–HfO{sub 2}/SiO{sub 2} bi-layers towards 3D charge trapping non-volatile memory

    Energy Technology Data Exchange (ETDEWEB)

    Congedo, Gabriele, E-mail: gabriele.congedo@mdm.imm.cnr.it; Wiemer, Claudia; Lamperti, Alessio; Cianci, Elena; Molle, Alessandro; Volpe, Flavio G.; Spiga, Sabina, E-mail: sabina.spiga@mdm.imm.cnr

    2013-04-30

    A metal/oxide/high-κ dielectric/oxide/silicon (MOHOS) planar charge trapping memory capacitor including SiO{sub 2} as tunnel oxide, Al–HfO{sub 2} as charge trapping layer, SiO{sub 2} as blocking oxide and TaN metal gate was fabricated and characterized as test vehicle in the view of integration into 3D cells. The thin charge trapping layer and blocking oxide were grown by atomic layer deposition, the technique of choice for the implementation of these stacks into 3D structures. The oxide stack shows a good thermal stability for annealing temperature of 900 °C in N{sub 2}, as required for standard complementary metal–oxide–semiconductor processes. MOHOS capacitors can be efficiently programmed and erased under the applied voltages of ± 20 V to ± 12 V. When compared to a benchmark structure including thin Si{sub 3}N{sub 4} as charge trapping layer, the MOHOS cell shows comparable program characteristics, with the further advantage of the equivalent oxide thickness scalability due to the high dielectric constant (κ) value of 32, and an excellent retention even for strong testing conditions. Our results proved that high-κ based oxide structures grown by atomic layer deposition can be of interest for the integration into three dimensionally stacked charge trapping devices. - Highlights: ► Charge trapping device with Al–HfO{sub 2} storage layer is fabricated and characterized. ► Al–HfO{sub 2} and SiO{sub 2} blocking oxides are deposited by atomic layer deposition. ► The oxide stack shows a good thermal stability after annealing at 900 °C. ► The device can be efficiently programmed/erased and retention is excellent. ► The oxide stack could be used for 3D-stacked Flash non-volatile memories.

  11. Microtransfer printing of metal ink patterns onto plastic substrates utilizing an adhesion-controlled polymeric donor layer

    International Nuclear Information System (INIS)

    Park, Ji-Sub; Choi, Jun-Chan; Park, Min-Kyu; Bae, Jeong Min; Bae, Jin-Hyuk; Kim, Hak-Rin

    2016-01-01

    We propose a method for transfer-printed electrode patterns onto flexible/plastic substrates, specifically intended for metal ink that requires a high sintering temperature. Typically, metal-ink-based electrodes cannot be picked up for microtransfer printing because the adhesion between the electrodes and the donor substrate greatly increases after the sintering process due to the binding materials. We introduced a polymeric donor layer between the printed electrodes and the donor substrate and effectively reduced the adhesion between the Ag pattern and the polymeric donor layer by controlling the interfacial contact area. After completing a wet-etching process for the polymeric donor layer, we obtained Ag patterns supported on the fine polymeric anchor structures; the Ag patterns could be picked up onto the stamp surface even after the sintering process by utilizing the viscoelastic properties of the elastomeric stamp with a pick-up velocity control. The proposed method enables highly conductive metal-ink-based electrode patterns to be applied on thermally weak plastic substrates via an all-solution process. Metal electrodes transferred onto a film showed superior electrical and mechanical stability under the bending stress test required for use in printed flexible electronics. (paper)

  12. Metal Surface Modification for Obtaining Nano- and Sub-Nanostructured Protective Layers

    Science.gov (United States)

    Ledovskykh, Volodymyr; Vyshnevska, Yuliya; Brazhnyk, Igor; Levchenko, Sergiy

    2017-03-01

    Regularities of the phase protective layer formation in multicomponent systems involving inhibitors with different mechanism of protective action have been investigated. It was shown that optimization of the composition of the inhibition mixture allows to obtain higher protective efficiency owing to improved microstructure of the phase layer. It was found that mechanism of the film formation in the presence of NaNO2-PHMG is due to deposition of slightly soluble PHMG-Fe complexes on the metal surface. On the basis of the proposed mechanism, the advanced surface engineering methods for obtaining nanoscaled and sub-nanostructured functional coatings may be developed.

  13. Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

    International Nuclear Information System (INIS)

    Ghosh, Bahniman; Mondal, Partha; Akram, M. W.; Bal, Punyasloka; Salimath, Akshay Kumar

    2014-01-01

    We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel. These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n–p–n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability. (semiconductor devices)

  14. Influence of the Surface Layer on the Electrochemical Deposition of Metals and Semiconductors into Mesoporous Silicon

    Energy Technology Data Exchange (ETDEWEB)

    Chubenko, E. B., E-mail: eugene.chubenko@gmail.com; Redko, S. V.; Sherstnyov, A. I.; Petrovich, V. A.; Kotov, D. A.; Bondarenko, V. P. [Belarusian State University of Information and RadioElectronics (Belarus)

    2016-03-15

    The influence of the surface layer on the process of the electrochemical deposition of metals and semiconductors into porous silicon is studied. It is shown that the surface layer differs in structure and electrical characteristics from the host porous silicon bulk. It is established that a decrease in the conductivity of silicon crystallites that form the surface layer of porous silicon has a positive effect on the process of the filling of porous silicon with metals and semiconductors. This is demonstrated by the example of nickel and zinc oxide. The effect can be used for the formation of nanocomposite materials on the basis of porous silicon and nanostructures with a high aspect ratio.

  15. Influence of the Surface Layer on the Electrochemical Deposition of Metals and Semiconductors into Mesoporous Silicon

    International Nuclear Information System (INIS)

    Chubenko, E. B.; Redko, S. V.; Sherstnyov, A. I.; Petrovich, V. A.; Kotov, D. A.; Bondarenko, V. P.

    2016-01-01

    The influence of the surface layer on the process of the electrochemical deposition of metals and semiconductors into porous silicon is studied. It is shown that the surface layer differs in structure and electrical characteristics from the host porous silicon bulk. It is established that a decrease in the conductivity of silicon crystallites that form the surface layer of porous silicon has a positive effect on the process of the filling of porous silicon with metals and semiconductors. This is demonstrated by the example of nickel and zinc oxide. The effect can be used for the formation of nanocomposite materials on the basis of porous silicon and nanostructures with a high aspect ratio.

  16. A gate enhanced power U-shaped MOSFET integrated with a Schottky rectifier

    International Nuclear Information System (INIS)

    Wang Ying; Jiao Wen-Li; Hu Hai-Fan; Liu Yun-Tao; Cao Fei

    2012-01-01

    An accumulation gate enhanced power U-shaped metal-oxide-semiconductor field-effect-transistor (UMOSFET) integrated with a Schottky rectifier is proposed. In this device, a Schottky rectifier is integrated into each cell of the accumulation gate enhanced power UMOSFET. Specific on-resistances of 7.7 mΩ·mm 2 and 6.5 mΩ·mm 2 for the gate bias voltages of 5 V and 10 V are achieved, respectively, and the breakdown voltage is 61 V. The numerical simulation shows a 25% reduction in the reverse recovery time and about three orders of magnitude reduction in the leakage current as compared with the accumulation gate enhanced power UMOSFET. (condensed matter: structural, mechanical, and thermal properties)

  17. Chemically-modified graphene sheets as an active layer for eco-friendly metal electroplating on plastic substrates

    International Nuclear Information System (INIS)

    Oh, Joon-Suk; Hwang, Taeseon; Nam, Gi-Yong; Hong, Jung-Pyo; Bae, Ah-Hyun; Son, Sang-Ik; Lee, Geun-Ho; Sung, Hak kyung; Choi, Hyouk Ryeol; Koo, Ja Choon; Nam, Jae-Do

    2012-01-01

    Eco-friendly nickel (Ni) electroplating was carried out on a plastic substrate using chemically modified graphene sheets as an active and conductive layer to initiate electroplating without using conventional pre-treatment or electroless metal-seeding processes. A graphene oxide (GO) solution was self-assembled on a polyethylene terephthalate (PET) film followed by evaporation to give GO layers (thickness around 6.5 μm) on PET (GO/PET) film. Then, the GO/PET film was chemically and thermally reduced to convert the GO layers to reduced graphene oxide (RGO) layers on the PET substrate. The RGO-coated PET (RGO/PET) film showed the sheet resistance of 100 Ω per square. On RGO/PET film, Ni electroplating was conducted under the constant-current condition and the entire surface of the PET film was completely metalized with Ni without any voids.

  18. Bio Organic-Semiconductor Field-Effect Transistor (BioFET) Based on Deoxyribonucleic Acid (DNA) Gate Dielectric

    Science.gov (United States)

    2010-03-31

    floating gate devices and metal-insulator-oxide-semiconductor (MIOS) devices. First attempts to use polarizable gate insulators in combination with...bulk of the semiconductor (ii) Due to the polarizable gate dielectric (iii) dipole polarization and (iv)electret effect due to mobile ions in the...characterization was carried out under an argon environment inside the glove box. An Agilent model E5273A with a two source-measurement unit instrument was

  19. Polycrystalline diamond RF MOSFET with MoO3 gate dielectric

    Directory of Open Access Journals (Sweden)

    Zeyang Ren

    2017-12-01

    Full Text Available We report the radio frequency characteristics of the diamond metal-oxide-semiconductor field effect transistor with MoO3 gate dielectric for the first time. The device with 2-μm gate length was fabricated on high quality polycrystalline diamond. The maximum drain current of 150 mA/mm at VGS = -5 V and the maximum transconductance of 27 mS/mm were achieved. The extrinsic cutoff frequency of 1.2 GHz and the maximum oscillation frequency of 1.9 GHz have been measured. The moderate frequency characteristics are attributed to the moderate transconductance limited by the series resistance along the channel. We expect that the frequency characteristics of the device can be improved by increasing the magnitude of gm, or fundamentally decreasing the gate-controlled channel resistance and series resistance along the channel, and down-scaling the gate length.

  20. Study on effective MOSFET channel length extracted from gate capacitance

    Science.gov (United States)

    Tsuji, Katsuhiro; Terada, Kazuo; Fujisaka, Hisato

    2018-01-01

    The effective channel length (L GCM) of metal-oxide-semiconductor field-effect transistors (MOSFETs) is extracted from the gate capacitances of actual-size MOSFETs, which are measured by charge-injection-induced-error-free charge-based capacitance measurement (CIEF CBCM). To accurately evaluate the capacitances between the gate and the channel of test MOSFETs, the parasitic capacitances are removed by using test MOSFETs having various channel sizes and a source/drain reference device. A strong linear relationship between the gate-channel capacitance and the design channel length is obtained, from which L GCM is extracted. It is found that L GCM is slightly less than the effective channel length (L CRM) extracted from the measured MOSFET drain current. The reason for this is discussed, and it is found that the capacitance between the gate electrode and the source and drain regions affects this extraction.

  1. Global transport and localized layering of metallic ions in the upper atmospherer

    Directory of Open Access Journals (Sweden)

    L. N. Carter

    1999-02-01

    Full Text Available A numerical model has been developed which is capable of simulating all phases of the life cycle of metallic ions, and results are described and interpreted herein for the typical case of Fe+ ions. This cycle begins with the initial deposition of metallics through meteor ablation and sputtering, followed by conversion of neutral Fe atoms to ions through photoionization and charge exchange with ambient ions. Global transport arising from daytime electric fields and poleward/ downward di.usion along geomagnetic field lines, localized transport and layer formation through de- scending convergent nulls in the thermospheric wind field, and finally annihilation by chemical neutralization and compound formation are treated. The model thus sheds new light on the interdependencies of the physical and chemical processes a.ecting atmospheric metallics. Model output analysis confirms the dominant role of both global and local transport to the ion's life cycle, showing that upward forcing from the equatorial electric field is critical to global movement, and that diurnal and semidiurnal tidal winds are responsible for the forma- tion of dense ion layers in the 90±250 km height region. It is demonstrated that the assumed combination of sources, chemical sinks, and transport mechanisms actually produces F-region densities and E-region layer densities similar to those observed. The model also shows that zonal and meridional winds and electric fields each play distinct roles in local transport, whereas the ion distribution is relatively insensitive to reasonable variations in meteoric deposition and chemical reaction rates.Key words. Ionosphere (ion chemistry and composition; ionosphere-atmosphere interactions.

  2. Versatile sputtering technology for Al2O3 gate insulators on graphene

    Directory of Open Access Journals (Sweden)

    Miriam Friedemann, Mirosław Woszczyna, André Müller, Stefan Wundrack, Thorsten Dziomba, Thomas Weimann and Franz J Ahlers

    2012-01-01

    Full Text Available We report a novel, sputtering-based fabrication method of Al2O3 gate insulators on graphene. Electrical performance of dual-gated mono- and bilayer exfoliated graphene devices is presented. Sputtered Al2O3 layers possess comparable quality to oxides obtained by atomic layer deposition with respect to a high relative dielectric constant of about 8, as well as low-hysteresis performance and high breakdown voltage. We observe a moderate carrier mobility of about 1000 cm2 V− 1 s−1 in monolayer graphene and 350 cm2 V− 1 s−1 in bilayer graphene, respectively. The mobility decrease can be attributed to the resonant scattering on atomic-scale defects, likely originating from the Al precursor layer evaporated prior to sputtering.

  3. Stable Low-Voltage Operation Top-Gate Organic Field-Effect Transistors on Cellulose Nanocrystal Substrates

    Science.gov (United States)

    Cheng-Yin Wang; Canek Fuentes-Hernandez; Jen-Chieh Liu; Amir Dindar; Sangmoo Choi; Jeffrey P. Youngblood; Robert J. Moon; Bernard Kippelen

    2015-01-01

    We report on the performance and the characterization of top-gate organic field-effect transistors (OFETs), comprising a bilayer gate dielectric of CYTOP/ Al2O3 and a solution-processed semiconductor layer made of a blend of TIPS-pentacene:PTAA, fabricated on recyclable cellulose nanocrystal−glycerol (CNC/glycerol...

  4. Determination of stable shapes of a thin liquid metal layer using a boundary integral method

    Energy Technology Data Exchange (ETDEWEB)

    Hinaje, M [Groupe de Recherche en Electrotechnique et Electronique de Nancy, 2 avenue de la Foret de Haye, 54516 Vandoeuvre-les-Nancy (France); Vinsard, G [Laboratoire d' Energetique et de Mecanique Theorique et Appliquee, 2 avenue de la Foret de Haye, 54516 Vandoeuvre-les-Nancy (France); Dufour, S [Groupe de Recherche en Electrotechnique et Electronique de Nancy, 2 avenue de la Foret de Haye, 54516 Vandoeuvre-les-Nancy (France)

    2006-03-21

    This paper deals with a thin liquid metal layer submitted to an ac magnetic field. Experimentally, we have noticed that even if the system (inductor+liquid metal) is axisymmetric, when an ac magnetic field is applied the symmetry is broken. The observed deformations of the liquid metal are in three dimensions. Therefore, our aim is to investigate this deformation using a numerical method as boundary element method in three dimensions.

  5. Determination of stable shapes of a thin liquid metal layer using a boundary integral method

    International Nuclear Information System (INIS)

    Hinaje, M; Vinsard, G; Dufour, S

    2006-01-01

    This paper deals with a thin liquid metal layer submitted to an ac magnetic field. Experimentally, we have noticed that even if the system (inductor+liquid metal) is axisymmetric, when an ac magnetic field is applied the symmetry is broken. The observed deformations of the liquid metal are in three dimensions. Therefore, our aim is to investigate this deformation using a numerical method as boundary element method in three dimensions

  6. Simulations of thermal Rayleigh-Marangoni convection in a three-layer liquid-metal-battery model

    Science.gov (United States)

    Köllner, Thomas; Boeck, Thomas; Schumacher, Jörg

    2017-11-01

    Operating a liquid-metal battery produces Ohmic losses in the electrolyte layer that separates both metal electrodes. As a consequence, temperature gradients establish which potentially cause thermal convection since density and interfacial tension depend on the local temperature. In our numerical investigations, we considered three plane, immiscible layers governed by the Navier-Stokes-Boussinesq equations held at a constant temperature of 500°C at the bottom and top. A homogeneous current is applied that leads to a preferential heating of the mid electrolyte layer. We chose a typical material combination of Li separated by LiCl-KCl (a molten salt) from Pb-Bi for which we analyzed the linear stability of pure thermal conduction and performed three-dimensional direct-numerical simulations by a pseudospectral method probing different: electrolyte layer heights, overall heights, and current densities. Four instability mechanisms are identified, which are partly coupled to each other: buoyant convection in the upper electrode, buoyant convection in the molten salt layer, and Marangoni convection at both interfaces between molten salt and electrode. The global turbulent heat transfer follows scaling predictions for internally heated buoyant convection. Financial support by the Deutsche Forschungsgemeinschaft under Grant No. KO 5515/1-1 is gratefully acknowledged.

  7. Modeling Electrolytically Top-Gated Graphene

    Directory of Open Access Journals (Sweden)

    Mišković ZL

    2010-01-01

    Full Text Available Abstract We investigate doping of a single-layer graphene in the presence of electrolytic top gating. The interfacial phenomenon is modeled using a modified Poisson–Boltzmann equation for an aqueous solution of simple salt. We demonstrate both the sensitivity of graphene’s doping levels to the salt concentration and the importance of quantum capacitance that arises due to the smallness of the Debye screening length in the electrolyte.

  8. Effect of nanocomposite gate-dielectric properties on pentacene microstructure and field-effect transistor characteristics.

    Science.gov (United States)

    Lee, Wen-Hsi; Wang, Chun-Chieh

    2010-02-01

    In this study, the effect of surface energy and roughness of the nanocomposite gate dielectric on pentacene morphology and electrical properties of pentacene OTFT are reported. Nanoparticles TiO2 were added in the polyimide matrix to form a nanocomposite which has a significantly different surface characteristic from polyimide, leading to a discrepancy in the structural properties of pentacene growth. A growth mode of pentacene deposited on the nanocomposite is proposed to explain successfully the effect of surface properties of nanocomposite gate dielectric such as surface energy and roughness on the pentacene morphology and electrical properties of OTFT. To obtain the lower surface energy and smoother surface of nanocomposite gate dielectric that is responsible for the desired crystalline, microstructure of pentacene and electrical properties of device, a bottom contact OTFT-pentacene deposited on the double-layer nanocomposite gate dielectric consisting of top smoothing layer of the neat polyimide and bottom layer of (PI+ nano-TiO2 particles) nanocomposite has been successfully demonstrated to exhibit very promising performance including high current on to off ratio of about 6 x 10(5), threshold voltage of -10 V and moderately high filed mobility of 0.15 cm2V(-1)s(-1).

  9. Plasmons in spatially separated double-layer graphene nanoribbons

    International Nuclear Information System (INIS)

    Bagheri, Mehran; Bahrami, Mousa

    2014-01-01

    Motivated by innovative progresses in designing multi-layer graphene nanostructured materials in the laboratory, we theoretically investigate the Dirac plasmon modes of a spatially separated double-layer graphene nanoribbon system, made up of a vertically offset armchair and metallic graphene nanoribbon pair. We find striking features of the collective excitations in this novel Coulomb correlated system, where both nanoribbons are supposed to be either intrinsic (undoped/ungated) or extrinsic (doped/gated). In the former, it is shown the low-energy acoustical and the high-energy optical plasmon modes are tunable only by the inter-ribbon charge separation. In the later, the aforementioned plasmon branches are modified by the added doping factor. As a result, our model could be useful to examine the existence of a linear Landau-undamped low-energy acoustical plasmon mode tuned via the inter-ribbon charge separation as well as doping. This study might also be utilized for devising novel quantum optical waveguides based on the Coulomb coupled graphene nanoribbons

  10. Gate-tunable gigantic changes in lattice parameters and optical properties in VO2

    Science.gov (United States)

    Nakano, Masaki; Okuyama, Daisuke; Shibuya, Keisuke; Ogawa, Naoki; Hatano, Takafumi; Kawasaki, Masashi; Arima, Taka-Hisa; Iwasa, Yoshihiro; Tokura, Yoshinori

    2014-03-01

    The field-effect transistor provides an electrical switching function of current flowing through a channel surface by external gate voltage (VG). We recently reported that an electric-double-layer transistor (EDLT) based on vanadium dioxide (VO2) enables electrical switching of the metal-insulator phase transition, where the low-temperature insulating state can be completely switched to the metallic state by application of VG. Here we demonstrate that VO2-EDLT enables electrical switching of lattice parameters and optical properties as well as electrical current. We performed in-situ x-ray diffraction and optical transmission spectroscopy measurements, and found that the c-axis length and the infrared transmittance of VO2 can be significantly modulated by more than 1% and 40%, respectively, by application of VG. We emphasize that these distinguished features originate from the electric-field induced bulk phase transition available with VO2-EDLT. This work was supported by the Japan Society for the Promotion of Science (JSPS) through its ``Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program).''

  11. Investigation of Selective Laser Melting Surface Alloyed Aluminium Metal Matrix Dispersive Reinforced Layers

    Science.gov (United States)

    Kamburov, V. V.; Dimitrova, R. B.; Kandeva, M. K.; Sofronov, Y. P.

    2018-01-01

    The aim of the paper is to investigate the improvement of mechanical properties and in particular wear resistance of laser surface alloyed dispersive reinforced thin layers produced by selective laser melting (SLM) technology. The wear resistance investigation of aluminium matrix composite layers in the conditions of dry friction surface with abrasive particles and nanoindentation tests were carried out. The process parameters (as scan speed) and their impact on the wear resistant layers have been evaluated. The alloyed layers containing metalized SiC particles were studied by Optical and Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray microanalysis (EDX). The obtained experimental results of the laser alloyed thin layers show significant development of their wear resistance and nanohardness due to the incorporated reinforced phase of electroless nickel coated SiC particles.

  12. Micro-layers of polystyrene film preventing metal oxidation: implications in cultural heritage conservation

    Science.gov (United States)

    Giambi, Francesca; Carretti, Emiliano; Dei, Luigi; Baglioni, Piero

    2014-12-01

    Protection of surfaces directly exposed to the detrimental action of degradative agents (i.e. oxygen, air pollutants and bacteria) is one of the most important challenges in the field of conservation of works of art. Metallic objects are subjected to specific surface corrosion phenomena that, over the years, make mandatory the research of innovative materials that should avoid the direct contact between the metal surface and the weathering agents. In this paper, the set-up, characterisation and application of a new reversible material for preserving metal artefacts are reported. Micro-layers constituted of low-adhesive polystyrene (PS) films obtained from recycling waste packaging materials made of expanded PS were studied. The morphology and thickness of PS films were characterised by optical, atomic force and scanning electron microscopy (SEM). A further check on thickness was carried out by means of visible spectrophotometry doping the films with a hydrophobic dye. Thermal properties of the PS micro-layers were studied by means of differential scanning calorimetry coupled with optical microscopy. Permeability of the PS films to water vapour was also determined. The potential of the low-adhesive PS films, that enabled an easy removal in case of film deterioration, for preventing metal oxidation was investigated on brass specimens by simulating standard artificial corrosion programmes. Morphological and chemical (coupling the energy-dispersive X-rays spectrometry to SEM measurements) analyses carried out on these metal samples showed promising results in terms of surface protection against corrosion.

  13. Investigation of porosity and fractal properties of the sintered metal and semiconductor layers in the MDS capacitor structure

    Directory of Open Access Journals (Sweden)

    Skatkov Leonid

    2012-01-01

    Full Text Available MDS capacitor (metal - dielectric - semiconductor is a structure in which metal plate is represented by compact bulk-porous pellets of niobium sintered powder, and semiconductor plate - by pyrolytic layer of MnO2. In the present paper we report the results of investigation of microporosity of sintered Nb and pyrolytic MnO2 and also the fractal properties of semiconductor layer.

  14. Initial multi-parameter detection of atmospheric metal layers by Beijing Na–K lidar

    International Nuclear Information System (INIS)

    Jiao, Jing; Yang, Guotao; Wang, Jihong; Cheng, Xuewu; Du, Lifang; Wang, Zelong; Gong, Wei

    2017-01-01

    Beijing Na–K lidar has been started running in 2010. This lidar has two laser beams: one dye laser emits a 589-nm laser beam for Na layer detection; the other dye laser emits a 770-nm laser beam for K layer detection. Under similar conditions, the echo signal of K layer is only about 2 orders of magnitude smaller than that of Na layer. This lidar has a sufficient Signal Noise Ratio (SNR). The structure and details of potassium layer can be effectively distinguished from a single original echo. Several examples of co-observation of density of Na and K layer showed some different results with previous studies. This lidar not only can supplement the lack of Na and K layer observation at this latitude region, but also provide evidence for the atmospheric sciences and space environment monitoring. - Highlights: • Full-band dual-beam lidar at 40°N. • Detecting sodium and potassium layer simultaneously. • Providing a supplement to the study of atmospheric metal layers and evidence for atmospheric sciences and space and atmospheric sciences and space environment monitoring.

  15. Few-Layer Nanoplates of Bi 2 Se 3 and Bi 2 Te 3 with Highly Tunable Chemical Potential

    KAUST Repository

    Kong, Desheng

    2010-06-09

    A topological insulator (TI) represents an unconventional quantum phase of matter with insulating bulk band gap and metallic surface states. Recent theoretical calculations and photoemission spectroscopy measurements show that group V-VI materials Bi2Se3, Bi2Te3, and Sb2Te3 are TIs with a single Dirac cone on the surface. These materials have anisotropic, layered structures, in which five atomic layers are covalently bonded to form a quintuple layer, and quintuple layers interact weakly through van der Waals interaction to form the crystal. A few quintuple layers of these materials are predicted to exhibit interesting surface properties. Different from our previous nanoribbon study, here we report the synthesis and characterizations of ultrathin Bi2Te3 and Bi2Se3 nanoplates with thickness down to 3 nm (3 quintuple layers), via catalyst-free vapor-solid (VS) growth mechanism. Optical images reveal thickness-dependent color and contrast for nanoplates grown on oxidized silicon (300 nm SiO2/Si). As a new member of TI nanomaterials, ultrathin TI nanoplates have an extremely large surface-to-volume ratio and can be electrically gated more effectively than the bulk form, potentially enhancing surface state effects in transport measurements. Low-temperature transport measurements of a single nanoplate device, with a high-k dielectric top gate, show decrease in carrier concentration by several times and large tuning of chemical potential. © 2010 American Chemical Society.

  16. Coulomb oscillations in three-layer graphene nanostructures

    International Nuclear Information System (INIS)

    Guettinger, J; Stampfer, C; Molitor, F; Graf, D; Ihn, T; Ensslin, K

    2008-01-01

    We present transport measurements on a tunable three-layer graphene single electron transistor (SET). The device consists of an etched three-layer graphene flake with two narrow constrictions separating the island from source and drain contacts. Three lateral graphene gates are used to electrostatically tune the device. An individual three-layer graphene constriction has been investigated separately showing a transport gap near the charge neutrality point. The graphene tunneling barriers show a strongly nonmonotonic coupling as a function of gate voltage indicating the presence of localized states in the constrictions. We show Coulomb oscillations and Coulomb diamond measurements proving the functionality of the graphene SET. A charging energy of ∼0.6 meV is extracted.

  17. Tunable Electrical and Optical Characteristics in Monolayer Graphene and Few-Layer MoS2 Heterostructure Devices.

    Science.gov (United States)

    Rathi, Servin; Lee, Inyeal; Lim, Dongsuk; Wang, Jianwei; Ochiai, Yuichi; Aoki, Nobuyuki; Watanabe, Kenji; Taniguchi, Takashi; Lee, Gwan-Hyoung; Yu, Young-Jun; Kim, Philip; Kim, Gil-Ho

    2015-08-12

    Lateral and vertical two-dimensional heterostructure devices, in particular graphene-MoS2, have attracted profound interest as they offer additional functionalities over normal two-dimensional devices. Here, we have carried out electrical and optical characterization of graphene-MoS2 heterostructure. The few-layer MoS2 devices with metal electrode at one end and monolayer graphene electrode at the other end show nonlinearity in drain current with drain voltage sweep due to asymmetrical Schottky barrier height at the contacts and can be modulated with an external gate field. The doping effect of MoS2 on graphene was observed as double Dirac points in the transfer characteristics of the graphene field-effect transistor (FET) with a few-layer MoS2 overlapping the middle part of the channel, whereas the underlapping of graphene have negligible effect on MoS2 FET characteristics, which showed typical n-type behavior. The heterostructure also exhibits a strongest optical response for 520 nm wavelength, which decreases with higher wavelengths. Another distinct feature observed in the heterostructure is the peak in the photocurrent around zero gate voltage. This peak is distinguished from conventional MoS2 FETs, which show a continuous increase in photocurrent with back-gate voltage. These results offer significant insight and further enhance the understanding of the graphene-MoS2 heterostructure.

  18. Processing and performance of organic insulators as a gate layer in ...

    Indian Academy of Sciences (India)

    Abstract. Fabrication of organic thin film transistor (OTFT) on flexible substrates is a challenge, because of its low softening temperature, high roughness and flexible nature. Although several organic dielectrics have been used as gate insulator, it is difficult to choose one in absence of a comparative study covering ...

  19. Multiphase layered oxide growth on pure metals. I. General formulation

    International Nuclear Information System (INIS)

    Fromhold, A.T. Jr.

    1982-01-01

    A general formulation for the simultaneous growth of any number of layered planar oxide phases on a pure metal under diffusion-controlled conditions has been developed. Four individual situations have been developed in detail, namely, situations in which the predominant mode of ion transport is by cation interstitials, cation vacancies, anion interstitials, or anion vacancies. The generalized formulation enables the determination of quasi-steady-state growth kinetics following step function changes in the experimental conditions such as ambient oxygen pressure or temperature. Numerical evaluation of the coupled growth equations for the individual phases is required to deduce the general predictions of the theory. In the limit of two-layer growth by cation interstitial diffusion, the present formulation reproduces the earlier results of Fromhold and Sato

  20. Electron transport in a double quantum ring: Evidence of an AND gate

    International Nuclear Information System (INIS)

    Maiti, Santanu K.

    2009-01-01

    We explore AND gate response in a double quantum ring where each ring is threaded by a magnetic flux φ. The double quantum ring is attached symmetrically to two semi-infinite one-dimensional metallic electrodes and two gate voltages, namely, V a and V b , are applied, respectively, in the lower arms of the two rings which are treated as two inputs of the AND gate. The system is described in the tight-binding framework and the calculations are done using the Green's function formalism. Here we numerically compute the conductance-energy and current-voltage characteristics as functions of the ring-to-electrode coupling strengths, magnetic flux and gate voltages. Our study suggests that, for a typical value of the magnetic flux φ=φ 0 /2 (φ 0 =ch/e, the elementary flux-quantum) a high output current (1) (in the logical sense) appears only if both the two inputs to the gate are high (1), while if neither or only one input to the gate is high (1), a low output current (0) results. It clearly demonstrates the AND gate behavior and this aspect may be utilized in designing an electronic logic gate.