Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process

International Nuclear Information System (INIS)

Wang Yanrong; Yang Hong; Xu Hao; Luo Weichun; Qi Luwei; Zhang Shuxiang; Wang Wenwu; Zhu Huilong; Zhao Chao; Chen Dapeng; Ye Tianchun; Yan Jiang

2017-01-01

In the process of high- k films fabrication, a novel multi deposition multi annealing (MDMA) technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing (PDA) times. The equivalent oxide thickness (EOT) decreases when the annealing time(s) change from 1 to 2. Furthermore, the characteristics of SILC (stress-induced leakage current) for an ultra-thin SiO 2 /HfO 2 gate dielectric stack are studied systematically. The increase of the PDA time(s) from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes. (paper)

First-principles simulations of the leakage current in metal-oxide-semiconductor structures caused by oxygen vacancies in HfO2 high-K gate dielectric

International Nuclear Information System (INIS)

Mao, L.F.; Wang, Z.O.

2008-01-01

HfO 2 high-K gate dielectric has been used as a new gate dielectric in metal-oxide-semiconductor structures. First-principles simulations are used to study the effects of oxygen vacancies on the tunneling current through the oxide. A level which is nearly 1.25 eV from the bottom of the conduction band is introduced into the bandgap due to the oxygen vacancies. The tunneling current calculations show that the tunneling currents through the gate oxide with different defect density possess the typical characteristic of stress-induced leakage current. Further analysis shows that the location of oxygen vacancies will have a marked effect on the tunneling current. The largest increase in the tunneling current caused by oxygen vacancies comes about at the middle oxide field when defects are located at the middle of the oxide. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Modelling of Leakage Current Through Double Dielectric Gate Stack in Metal Oxide Semiconductor Capacitor

International Nuclear Information System (INIS)

Fatimah A Noor; Mikrajuddin Abdullah; Sukirno; Khairurrijal

2008-01-01

In this paper, we have derived analytical expression of leakage current through double barriers in Metal Oxide Semiconductor (MOS) capacitor. Initially, electron transmittance through the MOS capacitor was derived by including the coupling between the transverse and longitudinal energies. The transmittance was then employed to obtain leakage current through the double barrier. In this model, we observed the effect of electron velocity due to the coupling effect and the oxide thickness to the leakage current. The calculated results showed that the leakage current decreases as the electron velocity increases. (author)

A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies

Directory of Open Access Journals (Sweden)

A. Schmitz

2005-01-01

Full Text Available Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors' field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (VGS=0. Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. We propose a Self-Biasing Virtual Rails (SBVR - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability.

Analysis of reverse gate leakage mechanism of AlGaN/GaN HEMTs with N2 plasma surface treatment

Science.gov (United States)

Liu, Hui; Zhang, Zongjing; Luo, Weijun

2018-06-01

The mechanism of reverse gate leakage current of AlGaN/GaN HEMTs with two different surface treatment methods are studied by using C-V, temperature dependent I-V and theoretical analysis. At the lower reverse bias region (VR >- 3.5 V), the dominant leakage current mechanism of the device with N2 plasma surface treatment is the Poole-Frenkel emission current (PF), and Trap-Assisted Tunneling current (TAT) is the principal leakage current of the device which treated by HCl:H2O solution. At the higher reverse bias region (VR current of the device with N2 plasma surface treatment is one order of magnitude smaller than the device which treated by HCl:H2O solution. This is due to the recovery of Ga-N bond in N2 plasma surface treatment together with the reduction of the shallow traps in post-gate annealing (PGA) process. The measured results agree well with the theoretical calculations and demonstrate N2 plasma surface treatment can reduce the reverse leakage current of the AlGaN/GaN HEMTs.

Analytical models for the 2DEG concentration and gate leakage current in AlGaN/GaN HEMTs

Science.gov (United States)

Ahmed, Nadim; Dutta, Aloke K.

2017-06-01

In this paper, we present a completely analytical model for the 2DEG concentration in AlGaN/GaN HEMTs as a function of gate bias, considering the donor-like trap states present at the metal/AlGaN interface to be the primary source of 2DEG carriers. To the best of our knowledge, this is a completely new contribution of this work. The electric field in the AlGaN layer is calculated using this model, which is further used to model the gate leakage current under reverse bias. We have modified the existing TTT (Thermionic Trap-Assisted Tunneling) current model, taking into account the effect of both metal/AlGaN interface traps as well as AlGaN bulk traps. The gate current under forward bias is also modeled using the existing thermionic emission model, approximating it by its Taylor series expansion. To take into account the effect of non-zero drain-source bias (VDS), an empirical fitting parameter is introduced in order to model the channel voltage in terms of VDS. The results of our models have been compared with the experimental data reported in the literature for three different devices, and the match is found to be excellent for both forward and reverse bias as well as for zero and non-zero VDS.

Investigation of surface related leakage current in AlGaN/GaN High Electron Mobility Transistors

Energy Technology Data Exchange (ETDEWEB)

Kaushik, J.K., E-mail: janeshkaushik@sspl.drdo.in [Solid State Physics Laboratory, Delhi 110054 (India); Balakrishnan, V.R.; Mongia, D.; Kumar, U.; Dayal, S. [Solid State Physics Laboratory, Delhi 110054 (India); Panwar, B.S. [Indian Institute of Technology Delhi, Hauz Khas, New Delhi 110016 (India); Muralidharan, R. [Indian Institute of Science, Bengaluru, Karnataka 560012 (India)

2016-08-01

This paper reports the study of surface-related mechanisms to explain the high reverse leakage current observed in the in-house fabricated Si{sub 3}N{sub 4} passivated AlGaN/GaN High Electron Mobility Transistors. We propose that the Si{sub 3}N{sub 4}/AlGaN interface in the un-gated regions provides an additional leakage path between the gate and source/drain and may constitute a large component of reverse current. This surface related leakage component of current exhibits both temperature and electric field dependence and its Arrhenius behavior has been experimentally verified using Conductance Deep Level Transient Spectroscopy and temperature dependent reverse leakage current measurements. A thin interfacial amorphous semiconductor layer formed due to inter diffusion at Si{sub 3}N{sub 4}/AlGaN interface has been presumed as the source for this surface related leakage. We, therefore, conclude that optimum Si{sub 3}N{sub 4} deposition conditions and careful surface preparation prior to passivation can limit the extent of surface leakage and can thus vastly improve the device performance. - Highlights: • Enhanced leakage in AlGaN/GaN High Electron Mobility Transistors after passivation • Experimental evidence of the presence of extrinsic traps at Si{sub 3}N{sub 4}/AlGaN interface • Electron hopping in shallower extended defects and band tail traps at the interface. • Reduction in current collapse due to the virtual gate inhibition by this conduction • However, limitation on the operating voltages due to decrease in breakdown voltage.

Band to Band Tunneling (BBT) Induced Leakage Current Enhancement in Irradiated Fully Depleted SOI Devices

Science.gov (United States)

Adell, Phillipe C.; Barnaby, H. J.; Schrimpf, R. D.; Vermeire, B.

2007-01-01

We propose a model, validated with simulations, describing how band-to-band tunneling (BBT) affects the leakage current degradation in some irradiated fully-depleted SOI devices. The dependence of drain current on gate voltage, including the apparent transition to a high current regime is explained.

Analyzing the effect of gate dielectric on the leakage currents

Directory of Open Access Journals (Sweden)

Sakshi

2016-01-01

Full Text Available An analytical threshold voltage model for MOSFETs has been developed using different gate dielectric oxides by using MATLAB software. This paper explains the dependency of threshold voltage on the dielectric material. The variation in the subthreshold currents with the change in the threshold voltage sue to the change of dielectric material has also been studied.

Pulse sequences for suppressing leakage in single-qubit gate operations

Science.gov (United States)

Ghosh, Joydip; Coppersmith, S. N.; Friesen, Mark

2017-06-01

Many realizations of solid-state qubits involve couplings to leakage states lying outside the computational subspace, posing a threat to high-fidelity quantum gate operations. Mitigating leakage errors is especially challenging when the coupling strength is unknown, e.g., when it is caused by noise. Here we show that simple pulse sequences can be used to strongly suppress leakage errors for a qubit embedded in a three-level system. As an example, we apply our scheme to the recently proposed charge quadrupole (CQ) qubit for quantum dots. These results provide a solution to a key challenge for fault-tolerant quantum computing with solid-state elements.

A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

Directory of Open Access Journals (Sweden)

Xiaohui Fan

2014-01-01

Full Text Available With the scaling of technology process, leakage power becomes an increasing portion of total power. Power gating technology is an effective method to suppress the leakage power in VLSI design. When the power gating technique is applied in sequential circuits, such as flip-flops and latches, the data retention is necessary to store the circuit states. A low leakage autonomous data retention flip-flop (ADR-FF is proposed in this paper. Two high-Vth transistors are utilized to reduce the leakage power consumption in the sleep mode. The data retention cell is composed of a pair of always powered cross-coupled inverters in the slave latch. No extra control signals and complex operations are needed for controlling the data retention and restoration. The data retention flip-flops are simulated with NCSU 45 nm technology. The postlayout simulation results show that the leakage power of the ADR-FF reduces 51.39% compared with the Mutoh-FF. The active power of the ADR-FF is almost equal to other data retention flip-flops. The average state mode transition time of ADR-FF decreases 55.98%, 51.35%, and 21.07% as compared with Mutoh-FF, Balloon-FF, and Memory-TG-FF, respectively. Furthermore, the area overhead of ADR-FF is smaller than other data retention flip-flops.

Low dislocation density InAlN/AlN/GaN heterostructures grown on GaN substrates and the effects on gate leakage characteristics

Energy Technology Data Exchange (ETDEWEB)

Kotani, Junji, E-mail: kotani.junji-01@jp.fujitsu.com; Yamada, Atsushi; Ishiguro, Tetsuro; Tomabechi, Shuichi; Nakamura, Norikazu [Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi, Kanagawa 243-0197 (Japan)

2016-04-11

This paper reports on the electrical characterization of Ni/Au Schottky diodes fabricated on InAlN high-electron-mobility transistor (HEMT) structures grown on low dislocation density free-standing GaN substrates. InAlN HEMT structures were grown on sapphire and GaN substrates by metal-organic vapor phase epitaxy, and the effects of threading dislocation density on the leakage characteristics of Ni/Au Schottky diodes were investigated. Threading dislocation densities were determined to be 1.8 × 10{sup 4 }cm{sup −2} and 1.2 × 10{sup 9 }cm{sup −2} by the cathodoluminescence measurement for the HEMT structures grown on GaN and sapphire substrates, respectively. Leakage characteristics of Ni/Au Schottky diodes were compared between the two samples, and a reduction of the leakage current of about three to four orders of magnitude was observed in the forward bias region. For the high reverse bias region, however, no significant improvement was confirmed. We believe that the leakage current in the low bias region is governed by a dislocation-related Frenkel–Poole emission, and the leakage current in the high reverse bias region originates from field emission due to the large internal electric field in the InAlN barrier layer. Our results demonstrated that the reduction of dislocation density is effective in reducing leakage current in the low bias region. At the same time, it was also revealed that another approach will be needed, for instance, band modulation by impurity doping and insertion of insulating layers beneath the gate electrodes for a substantial reduction of the gate leakage current.

Total dose effects on the shallow-trench isolation leakage current characteristics in a 0.35microm SiGe BiCMOS technology

International Nuclear Information System (INIS)

Niu, G.; Mathew, S.J.; Banerjee, G.; Cressler, J.D.; Clark, S.D.; Palmer, M.J.; Subbanna, S.

1999-01-01

The effects of gamma irradiation on the Shallow-Trench Isolation (STI) leakage currents in a SiGe BiCMOS technology are investigated for the first time, and shown to be strongly dependent on the irradiation gate bias and operating substrate bias. A positive irradiation gate bias significantly enhances the STI leakage, suggesting a strong field assisted nature of the charge buildup process in the STI. Numerical simulations also suggest the existence of fixed positive charges deep in the bulk along the STI/Si interface. A negative substrate bias, however, effectively suppresses the STI leakage, and can be used to eliminate the leakage produced by the charges deep in the bulk under irradiation

Enhanced ground bounce noise reduction in a low-leakage CMOS multiplier

Science.gov (United States)

Verma, Bipin Kumar; Akashe, Shyam; Sharma, Sanjay

2015-09-01

In this paper, various parameters are used to reduce leakage power, leakage current and noise margin of circuits to enhance their performance. A multiplier is proposed with low-leakage current and low ground bounce noise for the microprocessor, digital signal processors (DSP) and graphics engines. The ground bounce noise problem appears when a conventional power-gating circuit transits from sleep-to-active mode. This paper discusses a reduction in leakage current in the stacking power-gating technique by three modes - sleep, active and sleep-to-active. The simulation results are performed on a 4 × 4 carry-save multiplier for leakage current, active power, leakage power and ground bounce noise, and comparison made for different nanoscales. Ground bounce noise is limited to 90%. The leakage current of the circuit is decimated up to 80% and the active power is reduced to 31%. We performed simulations using cadence virtuoso 180 and 45 nm at room temperature at various supply voltages.

Ultrathin silicon dioxide layers with a low leakage current density formed by chemical oxidation of Si

Science.gov (United States)

Asuha,; Kobayashi, Takuya; Maida, Osamu; Inoue, Morio; Takahashi, Masao; Todokoro, Yoshihiro; Kobayashi, Hikaru

2002-10-01

Chemical oxidation of Si by use of azeotrope of nitric acid and water can form 1.4-nm-thick silicon dioxide layers with a leakage current density as low as those of thermally grown SiO2 layers. The capacitance-voltage (C-V) curves for these ultrathin chemical SiO2 layers have been measured due to the low leakage current density. The leakage current density is further decreased to approx1/5 (cf. 0.4 A/cm2 at the forward gate bias of 1 V) by post-metallization annealing at 200 degC in hydrogen. Photoelectron spectroscopy and C-V measurements show that this decrease results from (i) increase in the energy discontinuity at the Si/SiO2 interface, and (ii) elimination of Si/SiO2 interface states and SiO2 gap states.

Compensated readout for high-density MOS-gated memristor crossbar array

KAUST Repository

Zidan, Mohammed A.

2015-01-01

Leakage current is one of the main challenges facing high-density MOS-gated memristor arrays. In this study, we show that leakage current ruins the memory readout process for high-density arrays, and analyze the tradeoff between the array density and its power consumption. We propose a novel readout technique and its underlying circuitry, which is able to compensate for the transistor leakage-current effect in the high-density gated memristor array.

Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

International Nuclear Information System (INIS)

Jiang Zhi; Zhuang Yi-Qi; Li Cong; Wang Ping; Liu Yu-Qi

2016-01-01

Trap-assisted tunneling (TAT) has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor (TFET). In this paper, we assess subthreshold performance of double gate TFET (DG-TFET) through a band-to-band tunneling (BTBT) model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile (D it ) and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current. (paper)

Low-leakage-current AlGaN/GaN HEMTs on Si substrates with partially Mg-doped GaN buffer layer by metal organic chemical vapor deposition

International Nuclear Information System (INIS)

Li Ming; Wang Yong; Wong Kai-Ming; Lau Kei-May

2014-01-01

High-performance low-leakage-current AlGaN/GaN high electron mobility transistors (HEMTs) on silicon (111) substrates grown by metal organic chemical vapor deposition (MOCVD) with a novel partially Magnesium (Mg)-doped GaN buffer scheme have been fabricated successfully. The growth and DC results were compared between Mg-doped GaN buffer layer and a unintentionally one. A 1-μm gate-length transistor with Mg-doped buffer layer exhibited an OFF-state drain leakage current of 8.3 × 10 −8 A/mm, to our best knowledge, which is the lowest value reported for MOCVD-grown AlGaN/GaN HEMTs on Si featuring the same dimension and structure. The RF characteristics of 0.25-μm gate length T-shaped gate HEMTs were also investigated

Improving off-state leakage characteristics for high voltage AlGaN/GaN-HFETs on Si substrates

Science.gov (United States)

Moon, Sung-Woon; Twynam, John; Lee, Jongsub; Seo, Deokwon; Jung, Sungdal; Choi, Hong Goo; Shim, Heejae; Yim, Jeong Soon; Roh, Sungwon D.

2014-06-01

We present a reliable process and design technique for realizing high voltage AlGaN/GaN hetero-junction field effect transistors (HFETs) on Si substrates with very low and stable off-state leakage current characteristics. In this work, we have investigated the effects of the surface passivation layer, prepared by low pressure chemical vapor deposition (LPCVD) of silicon nitride (SiNx), and gate bus isolation design on the off-state leakage characteristics of metal-oxide-semiconductor (MOS) gate structure-based GaN HFETs. The surface passivated devices with gate bus isolation fully surrounding the source and drain regions showed extremely low off-state leakage currents of less than 20 nA/mm at 600 V, with very small variation. These techniques were successfully applied to high-current devices with 80-mm gate width, yielding excellent off-state leakage characteristics within a drain voltage range 0-700 V.

Failure analysis of leakage current in plastic encapsulated packages

International Nuclear Information System (INIS)

Hu, S.J.; Cheang, F.T.

1989-12-01

Plastic encapsulated packages exhibit high leakage current after a few hundred hours steam pressure pot test. The present study investigates two possible sources of leakage current, the mold compound and the lead frame tape used for taping the lead frame fingers. The results of the study indicate that the leakage current is independent of the frame and is not caused by the mold compound. The data further indicates that it is the ionic contents and acrylic-based adhesive layer of the lead frame tapes which cause the leakage current. To eliminate the leakage current, lead frame tape with low ionic contents and non acrylic-based adhesive should be used. (author). 1 fig., 2 tabs, 3 graphs

Conduction mechanism of leakage current due to the traps in ZrO2 thin film

Science.gov (United States)

Seo, Yohan; Lee, Sangyouk; An, Ilsin; Song, Chulgi; Jeong, Heejun

2009-11-01

In this work, a metal-oxide-semiconductor capacitor with zirconium oxide (ZrO2) gate dielectric was fabricated by an atomic layer deposition (ALD) technique and the leakage current characteristics under negative bias were studied. From the result of current-voltage curves there are two possible conduction mechanisms to explain the leakage current in the ZrO2 thin film. The dominant mechanism is the space charge limited conduction in the high-electric field region (1.5-5.0 MV cm-1) while the trap-assisted tunneling due to the existence of traps is prevailed in the low-electric field region (0.8-1.5 MV cm-1). Conduction caused by the trap-assisted tunneling is found from the experimental results of a weak temperature dependence of current, and the trap barrier height is obtained. The space charge limited conduction is evidenced, for different temperatures, by Child's law dependence of current density versus voltage. Child's law dependence can be explained by considering a single discrete trapping level and we can obtain the activation energy of 0.22 eV.

Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

Science.gov (United States)

Zhi, Jiang; Yi-Qi, Zhuang; Cong, Li; Ping, Wang; Yu-Qi, Liu

2016-02-01

Trap-assisted tunneling (TAT) has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor (TFET). In this paper, we assess subthreshold performance of double gate TFET (DG-TFET) through a band-to-band tunneling (BTBT) model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile (Dit) and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current. Project supported by the National Natural Science Foundation of China (Grant Nos. 61574109 and 61204092).

Conduction mechanism of leakage current due to the traps in ZrO2 thin film

International Nuclear Information System (INIS)

Seo, Yohan; Lee, Sangyouk; An, Ilsin; Jeong, Heejun; Song, Chulgi

2009-01-01

In this work, a metal-oxide-semiconductor capacitor with zirconium oxide (ZrO 2 ) gate dielectric was fabricated by an atomic layer deposition (ALD) technique and the leakage current characteristics under negative bias were studied. From the result of current–voltage curves there are two possible conduction mechanisms to explain the leakage current in the ZrO 2 thin film. The dominant mechanism is the space charge limited conduction in the high-electric field region (1.5–5.0 MV cm −1 ) while the trap-assisted tunneling due to the existence of traps is prevailed in the low-electric field region (0.8–1.5 MV cm −1 ). Conduction caused by the trap-assisted tunneling is found from the experimental results of a weak temperature dependence of current, and the trap barrier height is obtained. The space charge limited conduction is evidenced, for different temperatures, by Child's law dependence of current density versus voltage. Child's law dependence can be explained by considering a single discrete trapping level and we can obtain the activation energy of 0.22 eV

Low field leakage current on ultra-thin gate oxides after ion or electron beam irradiations; Courant de fuite aux champs faibles d'oxydes ultra-minces apres irradiations avec des faisceaux d'ions et d'electrons

Energy Technology Data Exchange (ETDEWEB)

Ceschia, M.; Paccagnella, A.; Sandrin, S. [Universita di Padova, Dipt. di Elettronica e Informatica, Padova (Italy); Paccagnella, A. [Istituto Nazionale per la Fisica della Materia, INFM, Unita di Padova (Italy); Ghidini, G. [ST-Microelectronics, Agrate Brianza (Italy); Wyss, J. [Universita di Padova, Dipt. di Fisica, Padova (Italy)

1999-07-01

In contemporary CMOS 0.25-{mu}m technologies, the MOS gate oxide (thickness {approx_equal} 5 nm) shows a low-field leakage current after radiation stresses, i.e. the radiation induced leakage current (RILC). RILC is generally attributed to a trap assisted tunneling (TAT) of electrons through neutral oxide traps generated by radiation stress. RILC has been investigated on ultra-thin oxides irradiated with 158 MeV {sup 28}Si ions or 8 MeV electrons. 3 main results are worth being quoted: 1) ion or electron beam irradiation can produce RILC with similar characteristics. Even the dose dependence of RILC is similar in the 2 cases, despite the large LET difference (about a factor of 10{sup +4}), 2) RILC is not a constant as a function of time, it tends to decrease when an oxide field (few MV/cm) is applied for (tens of) thousands seconds. On the other hand, RILC stays constant in devices kept at low bias, and 3) if a pulsed gate voltage is applied during irradiation, RILC is reduced with respect to the zero-field case. (A.C.)

Free energy dissipation of the spontaneous gating of a single voltage-gated potassium channel.

Science.gov (United States)

Wang, Jia-Zeng; Wang, Rui-Zhen

2018-02-01

Potassium channels mainly contribute to the resting potential and re-polarizations, with the potassium electrochemical gradient being maintained by the pump Na + /K + -ATPase. In this paper, we construct a stochastic model mimicking the kinetics of a potassium channel, which integrates temporal evolving of the membrane voltage and the spontaneous gating of the channel. Its stationary probability density functions (PDFs) are found to be singular at the boundaries, which result from the fact that the evolving rates of voltage are greater than the gating rates of the channel. We apply PDFs to calculate the power dissipations of the potassium current, the leakage, and the gating currents. On a physical perspective, the essential role of the system is the K + -battery charging the leakage (L-)battery. A part of power will inevitably be dissipated among the process. So, the efficiency of energy transference is calculated.

Free energy dissipation of the spontaneous gating of a single voltage-gated potassium channel

Science.gov (United States)

Wang, Jia-Zeng; Wang, Rui-Zhen

2018-02-01

Potassium channels mainly contribute to the resting potential and re-polarizations, with the potassium electrochemical gradient being maintained by the pump Na+/K+-ATPase. In this paper, we construct a stochastic model mimicking the kinetics of a potassium channel, which integrates temporal evolving of the membrane voltage and the spontaneous gating of the channel. Its stationary probability density functions (PDFs) are found to be singular at the boundaries, which result from the fact that the evolving rates of voltage are greater than the gating rates of the channel. We apply PDFs to calculate the power dissipations of the potassium current, the leakage, and the gating currents. On a physical perspective, the essential role of the system is the K+-battery charging the leakage (L-)battery. A part of power will inevitably be dissipated among the process. So, the efficiency of energy transference is calculated.

Study of surface leakage current of AlGaN/GaN high electron mobility transistors

International Nuclear Information System (INIS)

Chen, YongHe; Zhang, Kai; Cao, MengYi; Zhao, ShengLei; Zhang, JinCheng; Hao, Yue; Ma, XiaoHua

2014-01-01

Temperature-dependent surface current measurements were performed to analyze the mechanism of surface conductance of AlGaN/GaN channel high-electron-mobility transistors by utilizing process-optimized double gate structures. Different temperatures and electric field dependence have been found in surface current measurements. At low electric field, the mechanism of surface conductance is considered to be two-dimensional variable range hopping. At elevated electric field, the Frenkel–Poole trap assisted emission governs the main surface electrons transportation. The extracted energy barrier height of electrons emitting from trapped state near Fermi energy level into a threading dislocations-related continuum state is 0.38 eV. SiN passivation reduces the surface leakage current by two order of magnitude and nearly 4 orders of magnitude at low and high electric fields, respectively. SiN also suppresses the Frenkel–Poole conductance at high temperature by improving the surface states of AlGaN/GaN. A surface treatment process has been introduced to further suppress the surface leakage current at high temperature and high field, which results in a decrease in surface current of almost 3 orders of magnitude at 476 K

Mechanism of leakage of ion-implantation isolated AlGaN/GaN MIS-high electron mobility transistors on Si substrate

Science.gov (United States)

Zhang, Zhili; Song, Liang; Li, Weiyi; Fu, Kai; Yu, Guohao; Zhang, Xiaodong; Fan, Yaming; Deng, Xuguang; Li, Shuiming; Sun, Shichuang; Li, Xiajun; Yuan, Jie; Sun, Qian; Dong, Zhihua; Cai, Yong; Zhang, Baoshun

2017-08-01

In this paper, we systematically investigated the leakage mechanism of the ion-implantation isolated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) on Si substrate. By means of combined DC tests at different temperatures and electric field dependence, we demonstrated the following original results: (1) It is proved that gate leakage is the main contribution to OFF-state leakage of ion-implantation isolated AlGaN/GaN MIS-HEMTs, and the gate leakage path is a series connection of the gate dielectric Si3N4 and Si3N4-GaN interface. (2) The dominant mechanisms of the leakage current through LPCVD-Si3N4 gate dielectric and Si3N4-GaN interface are identified to be Frenkel-Poole emission and two-dimensional variable range hopping (2D-VRH), respectively. (3) A certain temperature annealing could reduce the density of the interface state that produced by ion implantation, and consequently suppress the interface leakage transport, which results in a decrease in OFF-state leakage current of ion-implantation isolated AlGaN/GaN MIS-HEMTs.

Current transport mechanisms in mercury cadmium telluride diode

Energy Technology Data Exchange (ETDEWEB)

Gopal, Vishnu, E-mail: vishnu-46@yahoo.com, E-mail: wdhu@mail.sitp.ac.cn [Institute of Defence Scientists and Technologists, CFEES Complex, Brig. S. K. Majumdar Marg, Delhi 110054 (India); Li, Qing; He, Jiale; Hu, Weida, E-mail: vishnu-46@yahoo.com, E-mail: wdhu@mail.sitp.ac.cn [National Lab for Infrared Physics, Shanghai Institute of Technical Physics, Chinese Academy of Sciences, Shanghai 200083 (China); He, Kai; Lin, Chun [Key Laboratory of Infrared Imaging Materials and Detectors, Shanghai Institute of Technical Physics, Chinese Academy of Sciences, Shanghai 200083 (China)

2016-08-28

This paper reports the results of modelling of the current-voltage characteristics (I-V) of a planar mid-wave Mercury Cadmium Telluride photodiode in a gate controlled diode experiment. It is reported that the diode exhibits nearly ideal I-V characteristics under the optimum surface potential leading to the minimal surface leakage current. Deviations from the optimum surface potential lead to non ideal I–V characteristics, indicating a strong relationship between the ideality factor of the diode with its surface leakage current. Diode's I–V characteristics have been modelled over a range of gate voltages from −9 V to −2 V. This range of gate voltages includes accumulation, flat band, and depletion and inversion conditions below the gate structure of the diode. It is shown that the I–V characteristics of the diode can be very well described by (i) thermal diffusion current, (ii) ohmic shunt current, (iii) photo-current due to background illumination, and (iv) excess current that grows by the process of avalanche multiplication in the gate voltage range from −3 V to −5 V that corresponds to the optimum surface potential. Outside the optimum gate voltage range, the origin of the excess current of the diode is associated with its high surface leakage currents. It is reported that the ohmic shunt current model applies to small surface leakage currents. The higher surface leakage currents exhibit a nonlinear shunt behaviour. It is also shown that the observed zero-bias dynamic resistance of the diode over the entire gate voltage range is the sum of ohmic shunt resistance and estimated zero-bias dynamic resistance of the diode from its thermal saturation current.

Insulator Contamination Forecasting Based on Fractal Analysis of Leakage Current

Directory of Open Access Journals (Sweden)

Bing Luo

2012-07-01

Full Text Available In this paper, an artificial pollution test is carried out to study the leakage current of porcelain insulators. Fractal theory is adopted to extract the characteristics hidden in leakage current waveforms. Fractal dimensions of the leakage current for the security, forecast and danger zones are analyzed under four types of degrees of contamination. The mean value and the standard deviation of the fractal dimension in the forecast zone are calculated to characterize the differences. The analysis reveals large differences in the fractal dimension of leakage current under different contamination discharge stages and degrees. The experimental and calculation results suggest that the fractal dimension of a leakage current waveform can be used as a new indicator of the discharge process and contamination degree of insulators. The results provide new methods and valid indicators for forecasting contamination flashovers.

Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

Energy Technology Data Exchange (ETDEWEB)

Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A., E-mail: steven.vitale@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

2015-07-28

Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

Gate current for p+-poly PMOS devices under gate injection conditions

NARCIS (Netherlands)

Hof, A.J.; Holleman, J.; Woerlee, P.H.

2001-01-01

In current CMOS processing both n+-poly and p+-poly gates are used. The I-V –relationship and reliability of n+-poly devices are widely studied and well understood. Gate currents and reliability for p+-poly PMOS devices under gate injection conditions are not well understood. In this paper, the

Leakage current characteristics of the multiple metal alloy nanodot memory

International Nuclear Information System (INIS)

Lee, Gae Hun; Lee, Jung Min; Yang, Hyung Jun; Song, Yun Heub; Bea, Ji Chel; Tanaka, Tetsu

2010-01-01

The leakage current characteristics of a multiple metal alloy nanodot device for a nonvolatile random access memory using FePt materials are investigated. Several annealing conditions are evaluated and optimized to suppress the leakage current and to better the memory characterisctics. This work confirmed that the annealing condition of 700 .deg. C in a high vacuum ambience (under 1 x 10 -5 Pa) simultaneously provided good cell characteristics from a high dot density of over 1 x 10 13 /cm 2 and a low leakage current. In addition, a smaller nanodot diameter was found to give a lower leakage current for the multiple nanodot memory. Finally, for the proposed annealing condition, the quadruple FePt multiple nanodot memory with a 2-nm dot diameter provided good leakage current characteristics, showing a threshold voltage shift of under 5% at an initial retention stage of 1000 sec.

Effects of combined gate and ohmic recess on GaN HEMTs

Directory of Open Access Journals (Sweden)

Sunil Kumar

2016-09-01

Full Text Available AlGaN/GaN, because of their superior material properties, are most suitable semiconductor material for High Electron Mobility Transistors (HEMTs. In this work we investigated the hidden physics behind these materials and studied the effect of recess technology in AlGaN/GaN HEMTs. The device under investigation is simulated for different recess depth using Silvaco-Atlas TCAD. Recess technology improves the performance of AlGaN/GaN HEMTs. We considered three kinds of recess technology gate, ohmic and combination of gate and ohmic. Gate recess improves transconductance gm but it reduces the drain current Id of the device under investigation. Ohmic recess improves the transconductance gm but it introduces leakage current Ig in the device. In order to use AlGaN/GaN for high voltage operation, both the transconductance and the drain current should be reasonably high which is obtained by combining both gate and ohmic recess technologies. A good balance in transconductance and drain current is achieved by combining both gate and ohmic recess technologies without any leakage current.

Defect generation and activation processes in HfO{sub 2} thin films: Contributions to stress-induced leakage currents

Energy Technology Data Exchange (ETDEWEB)

Oettking, Rolf; Leitsmann, Roman; Lazarevic, Florian; Plaenitz, Philipp [AQcomputare, Business Unit MATcalc, Chemnitz (Germany); Kupke, Steve; Roll, Guntrade; Slesazeck, Stefan [NaMLab gGmbH, Dresden (Germany); Nadimi, Ebrahim [AQcomputare, Business Unit MATcalc, Chemnitz (Germany); K.N. Toosi University of Technology, Faculty of Electrical Engineering, Tehran (Iran, Islamic Republic of); Trentzsch, Martin [Globalfoundries Dresden, Dresden (Germany); Mikolajick, Thomas [Technische Universitaet Dresden, Fakultaet Elektrotechnik und Informationstechnik, Institut fuer Halbleiter- und Mikrosystemtechnik, Dresden (Germany)

2015-03-01

An important source of degradation in thin dielectric material layers is the generation and migration of oxygen vacancies. We investigated the formation of Frenkel pairs (FPs) in HfO{sub 2} as the first structural step for the creation of new defects as well as the migration of preexisting and newly built oxygen vacancies by nudged elastic band (NEB) calculations and stress induced leakage current (SILC) experiments. The analysis indicates, that for neutral systems no stable intimate FPs are built, whereas for the charge states q = ± 2 FPs are formed at threefold and at fourfold coordinated oxygen lattice sites. Their generation and annihilation rate are in equilibrium according to the Boltzmann statistics. Distant FPs (stable defects) are unlikely to build due to high formation energies and therefore cannot be accounted for the measured gate leakage current increase of nMOSFETs under constant voltage stress. The negatively charged oxygen vacancies were found to be very immobile in contrast to positively charged V{sub 0}'s with a low migration barrier that coincides well with the experimentally obtained activation energy. We show that rather the activation of preexisting defects and migration towards the interface than the defect generation are the cause for the gate oxide degradation. (copyright 2015 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Degradation of ultra-thin gate oxide LDD NMOSFET under GIDL stress

International Nuclear Information System (INIS)

Hu Shigang; Hao Yue; Cao Yanrong; Ma Xiaohua; Wu Xiaofeng; Chen Chi; Zhou Qingjun

2009-01-01

The degradation of device under GIDL (gate-induced drain leakage current) stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides. Experimental result shows that the degradation of device parameters depends more strongly on V d than on V g . The characteristics of the GIDL current are used to analyze the damage generated during the stress. It is clearly found that the change of GIDL current before and after stress can be divided into two stages. The trapping of holes in the oxide is dominant in the first stage, but that of electrons in the oxide is dominant in the second stage. It is due to the common effects of edge direct tunneling and band-to-band tunneling. SILC (stress induced leakage current) in the NMOSFET decreases with increasing stress time under GIDL stress. The degradation characteristic of SILC also shows saturating time dependence. SILC is strongly dependent on the measured gate voltage. The higher the measured gate voltage, the less serious the degradation of the gate current. A likely mechanism is presented to explain the origin of SILC during GIDL stress.

Low voltage stress-induced leakage current and traps in ultrathin oxide (1.2 2.5 nm) after constant voltage stresses

Science.gov (United States)

Petit, C.; Zander, D.

2007-10-01

It has been shown that the low voltage gate current in ultrathin oxide metal-oxide-semiconductor devices is very sensitive to electrical stresses. Therefore, it can be used as a reliability monitor when the oxide thickness becomes too small for traditional electrical measurements to be used. In this work, we present a study on n-MOSCAP devices at negative gate bias in the direct tunneling (DT) regime. If the low voltage stress-induced leakage current (LVSILC) depends strongly on the low sense voltages, it also depends strongly on the stress voltage magnitude. We show that two LVSILC peaks appear as a function of the sense voltage in the LVSILC region and that their magnitude, one compared to the other, depends strongly on the stress voltage magnitude. One is larger than the other at low stress voltage and smaller at high stress voltage. From our experimental results, different conduction mechanisms are analyzed. To explain LVSILC variations, we propose a model of the conduction through the ultrathin gate oxide based on two distinctly different trap-assisted tunneling mechanisms: inelastic of gate electron (INE) and trap-assisted electron (ETAT).

Leakage current analysis of single-phase transformer-less grid-connected PV inverters

DEFF Research Database (Denmark)

Ma, Lin; Kerekes, Tamas; Teodorescu, Remus

2016-01-01

Transformer-less string PV inverter is getting more and more widely utilized due to its higher efficiency, smaller volume and weight. However, without the galvanic isolation, the leakage current limitation and operation safety became the key issues of transformer-less inverters. This paper...... simplifies the leakage current generation circuit model and presents a leakage current estimation method both in real time and frequency domain. It shows that the leakage current is related to the circuit stray parameters, output filter and common mode voltage. Furthermore, with the proposed analysis method......, the leakage current generation of H-bridge with different modulation methods and HERIC inverter are discussed individually. At last, the presented method has been verified via simulation....

Transformerless photovoltaic inverters with leakage current and pulsating power elimination

DEFF Research Database (Denmark)

Tang, Yi; Yao, Wenli; Wang, H.

2015-01-01

This paper presents a transformerless inverter topology, which is capable of simultaneously solving leakage current and pulsating power issues in grid-connected photovoltaic (PV) systems. Without adding any additional components to the system, the leakage current caused by the PV......-to-ground parasitic capacitance can be bypassed by introducing a common mode (CM) conducting path to the inverter. The resulting ground leakage current is therefore well controlled to be below the regulation limit. Moreover, the proposed inverter can also eliminate the well-known double line frequency pulsating power....... The mechanism of leakage current suppression and the closed-loop control of pulsating power decoupling are discussed in the paper in details. A 500 W prototype was also built and tested in the laboratory, and both simulation and experimental results are finally presented to show the excellent performance...

A new on-line leakage current monitoring system of ZnO surge arresters

International Nuclear Information System (INIS)

Lee, Bok-Hee; Kang, Sung-Man

2005-01-01

This paper presents a new on-line leakage current monitoring system of zinc oxide (ZnO) surge arresters. To effectively diagnose the deterioration of ZnO surge arresters, a new algorithm and on-line leakage current detection device, which uses the time-delay addition method, for discriminating the resistive and capacitive currents was developed to use in the aging test and durability evaluation for ZnO arrester blocks. A computer-based measurement system of the resistive leakage current, the on-line monitoring device can detect accurately the leakage currents flowing through ZnO surge arresters for power frequency ac applied voltages. The proposed on-line leakage current monitoring device of ZnO surge arresters is more highly sensitive and gives more linear response than the existing devices using the detection method of the third harmonic leakage currents. Therefore, the proposed leakage current monitoring device can be useful for predicting the defects and performance deterioration of ZnO surge arresters in power system applications

Insulation Resistance and Leakage Currents in Low-Voltage Ceramic Capacitors with Cracks

Science.gov (United States)

Teverovsky, Alexander A.

2016-01-01

Measurement of insulation resistance (IR) in multilayer ceramic capacitors (MLCCs) is considered a screening technique that ensures the dielectric is defect-free. This work analyzes the effectiveness of this technique for revealing cracks in ceramic capacitors. It is shown that absorption currents prevail over the intrinsic leakage currents during standard IR measurements at room temperature. Absorption currents, and consequently IR, have a weak temperature dependence, increase linearly with voltage (before saturation), and are not sensitive to the presence of mechanical defects. In contrary, intrinsic leakage currents increase super-linearly with voltage and exponentially with temperature (activation energy is in the range from 0.6 eV to 1.1 eV). Leakage currents associated with the presence of cracks have a weaker dependence on temperature and voltage compared to the intrinsic leakage currents. For this reason, intrinsic leakage currents prevail at high temperatures and voltages, thus masking the presence of defects.

Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

International Nuclear Information System (INIS)

Ghosh, Bahniman; Mondal, Partha; Akram, M. W.; Bal, Punyasloka; Salimath, Akshay Kumar

2014-01-01

We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel. These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n–p–n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability. (semiconductor devices)

Parametrization of the radiation induced leakage current increase of NMOS transistors

International Nuclear Information System (INIS)

Backhaus, M.

2017-01-01

The increase of the leakage current of NMOS transistors during exposure to ionizing radiation is known and well studied. Radiation hardness by design techniques have been developed to mitigate this effect and have been successfully used. More recent developments in smaller feature size technologies do not make use of these techniques due to their drawbacks in terms of logic density and requirement of dedicated libraries. During operation the resulting increase of the supply current is a serious challenge and needs to be considered during the system design. A simple parametrization of the leakage current of NMOS transistors as a function of total ionizing dose is presented. The parametrization uses a transistor transfer characteristics of the parasitic transistor along the shallow trench isolation to describe the leakage current of the nominal transistor. Together with a parametrization of the number of positive charges trapped in the silicon dioxide and number of activated interface traps in the silicon to silicon dioxide interface the leakage current results as a function of the exposure time to ionizing radiation. This function is fitted to data of the leakage current of single transistors as well as to data of the supply current of full ASICs.

Modeling of Dual Gate Material Hetero-dielectric Strained PNPN TFET for Improved ON Current

Science.gov (United States)

Kumari, Tripty; Saha, Priyanka; Dash, Dinesh Kumar; Sarkar, Subir Kumar

2018-01-01

The tunnel field effect transistor (TFET) is considered to be a promising alternative device for future low-power VLSI circuits due to its steep subthreshold slope, low leakage current and its efficient performance at low supply voltage. However, the main challenging issue associated with realizing TFET for wide scale applications is its low ON current. To overcome this, a dual gate material with the concept of dielectric engineering has been incorporated into conventional TFET structure to tune the tunneling width at source-channel interface allowing significant flow of carriers. In addition to this, N+ pocket is implanted at source-channel junction of the proposed structure and the effect of strain is added for exploring the performance of the model in nanoscale regime. All these added features upgrade the device characteristics leading to higher ON current, low leakage and low threshold voltage. The present work derives the surface potential, electric field expression and drain current by solving 2D Poisson's equation at different boundary conditions. A comparative analysis of proposed model with conventional TFET has been done to establish the superiority of the proposed structure. All analytical results have been compared with the results obtained in SILVACO ATLAS device simulator to establish the accuracy of the derived analytical model.

Comparative studies of AlGaN/GaN MOS-HEMTs with stacked gate dielectrics by the mixed thin film growth method

International Nuclear Information System (INIS)

Chou, Bo-Yi; Hsu, Wei-Chou; Liu, Han-Yin; Ho, Chiu-Sheng; Lee, Ching-Sung

2013-01-01

This paper reports Al 0.27 Ga 0.73 N/GaN metal–oxide–semiconductor high electron mobility transistors (MOS-HEMTs) with stacked Al 2 O 3 /HfO 2 gate dielectrics by using hydrogen peroxideoxidation/sputtering techniques. The Al 2 O 3 employed as a gate dielectric and surface passivation layer effectively suppresses the gate leakage current, improves RF drain current collapse and exhibits good thermal stability. Moreover, by stacking the good insulating high-k HfO 2 dielectric further suppresses the gate leakage, enhances the dielectric breakdown field and power-added efficiency, and decreases the equivalent oxide thickness. The present MOS-HEMT design has demonstrated superior improvements of 10.1% (16.4%) in the maximum drain–source current (I DS,max ), 11.4% (22.5%) in the gate voltage swing and 12.5%/14.4% (21.9%/22.3%) in the two-terminal gate–drain breakdown/turn-on voltages (BV GD /V ON ), and the present design also demonstrates the lowest gate leakage current and best thermal stability characteristics as compared to two reference MOS-HEMTs with a single Al 2 O 3 /(HfO 2 ) dielectric layer of the same physical thickness. (invited paper)

RF capacitance-voltage characterization of MOSFETs with high-leakage dielectric

NARCIS (Netherlands)

Schmitz, Jurriaan; Cubaynes, F.N; Cubaynes, F.N.; Havens, R.J.; de Kort, R.; Scholten, A.J.; Tiemeijer, L.F.

2003-01-01

We present a MOS Capacitance-Voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm/sup 2/. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter

Gate-Driven Pure Spin Current in Graphene

Science.gov (United States)

Lin, Xiaoyang; Su, Li; Si, Zhizhong; Zhang, Youguang; Bournel, Arnaud; Zhang, Yue; Klein, Jacques-Olivier; Fert, Albert; Zhao, Weisheng

2017-09-01

The manipulation of spin current is a promising solution for low-power devices beyond CMOS. However, conventional methods, such as spin-transfer torque or spin-orbit torque for magnetic tunnel junctions, suffer from large power consumption due to frequent spin-charge conversions. An important challenge is, thus, to realize long-distance transport of pure spin current, together with efficient manipulation. Here, the mechanism of gate-driven pure spin current in graphene is presented. Such a mechanism relies on the electrical gating of carrier-density-dependent conductivity and spin-diffusion length in graphene. The gate-driven feature is adopted to realize the pure spin-current demultiplexing operation, which enables gate-controllable distribution of the pure spin current into graphene branches. Compared with the Elliott-Yafet spin-relaxation mechanism, the D'yakonov-Perel spin-relaxation mechanism results in more appreciable demultiplexing performance. The feature of the pure spin-current demultiplexing operation will allow a number of logic functions to be cascaded without spin-charge conversions and open a route for future ultra-low-power devices.

Simulation of leakage current measurement on medical devices using helmholtz coil configuration with different current flow

Science.gov (United States)

Sutanto, E.; Chandra, F.; Dinata, R.

2017-05-01

Leakage current measurement which can follow IEC standard for medical device is one of many challenges to be answered. The IEC 60601-1 has defined that the limit for a leakage current for Medical Device can be as low as 10 µA and as high as 500 µA, depending on which type of contact (applied part) connected to the patient. Most people are using ELCB (Earth-leakage circuit breaker) for safety purpose as this is the most common and available safety device in market. One type of ELCB devices is RCD (Residual Current Device) and this RCD type can measure the leakage current directly. This work will show the possibility on how Helmholtz Coil Configuration can be made to be like the RCD. The possibility is explored by comparing the magnetic field formula from each device, then it proceeds with a simulation using software EJS (Easy Java Simulation). The simulation will make sure the concept of magnetic field current cancellation follows the RCD concept. Finally, the possibility of increasing the measurement’s sensitivity is also analyzed. The sensitivity is needed to see the possibility on reaching the minimum leakage current limit defined by IEC, 0.01mA.

Simulation of leakage current measurement on medical devices using helmholtz coil configuration with different current flow

International Nuclear Information System (INIS)

Sutanto, E; Chandra, F; Dinata, R

2017-01-01

Leakage current measurement which can follow IEC standard for medical device is one of many challenges to be answered. The IEC 60601-1 has defined that the limit for a leakage current for Medical Device can be as low as 10 µA and as high as 500 µA, depending on which type of contact (applied part) connected to the patient. Most people are using ELCB (Earth-leakage circuit breaker) for safety purpose as this is the most common and available safety device in market. One type of ELCB devices is RCD (Residual Current Device) and this RCD type can measure the leakage current directly. This work will show the possibility on how Helmholtz Coil Configuration can be made to be like the RCD. The possibility is explored by comparing the magnetic field formula from each device, then it proceeds with a simulation using software EJS (Easy Java Simulation). The simulation will make sure the concept of magnetic field current cancellation follows the RCD concept. Finally, the possibility of increasing the measurement’s sensitivity is also analyzed. The sensitivity is needed to see the possibility on reaching the minimum leakage current limit defined by IEC, 0.01mA. (paper)

Leakage Current Elimination of Four-Leg Inverter for Transformerless Three-Phase PV Systems

DEFF Research Database (Denmark)

Guo, Xiaoqiang; He, Ran; Jian, Jiamin

2016-01-01

Eliminating the leakage current is one of the most important issues for transformerless three phase photovoltaic (PV) systems. In this paper, the leakage current elimination of a three-phase four-leg PV inverter is investigated. With the common mode loop model established, the generation mechanism...... of the leakage current is clearly identified. Different typical carrier-based modulation methods and their corresponding common mode voltages are discussed. A new modulation strategy with Boolean logic function is proposed to achieve the constant common mode voltage for the leakage current reduction. Finally...

Highly Reliable Transformerless Photovoltaic Inverters With Leakage Current and Pulsating Power Elimination

DEFF Research Database (Denmark)

Tang, Yi; Yao, Wenli; Loh, Poh Chiang

2016-01-01

This paper presents a transformerless inverter topology, which is capable of simultaneously solving leakage current and pulsating power issues in grid-connected photovoltaic (PV) systems. Without adding any additional components to the system, the leakage current caused by the PV-to-ground parasi......This paper presents a transformerless inverter topology, which is capable of simultaneously solving leakage current and pulsating power issues in grid-connected photovoltaic (PV) systems. Without adding any additional components to the system, the leakage current caused by the PV......-to-ground parasitic capacitance can be bypassed by introducing a common-mode (CM) conducting path to the inverter. The resulting ground leakage current is therefore well controlled to be below the regulation limit. Furthermore, the proposed inverter can also eliminate the well-known double-line-frequency pulsating...... power that is inherent in single-phase PV systems. By properly injecting CM voltages to the output filter capacitors, the pulsating power can be decoupled from the dc-link. Therefore, it is possible to use long-lifetime film capacitors instead of electrolytic capacitors to improve the reliability...

A double-gate double-feedback JFET charge-sensitive preamplifier

International Nuclear Information System (INIS)

Fazzi, A.

1996-01-01

A new charge-sensitive preamplifier (CSP) without a physical resistance in the feedback is presented. The input device has to be a double-gate JFET. In this new preamplifier configuration the feedback capacitor is continuously discharged by means of a second DC current feedback loop closed through the bottom gate of the input JFET. The top gate-channel junction works as usual in reverse bias, the bottom gate-channel is forward biased. A fraction of the current injected by the bottom gate reaches the top gate discharging the feedback capacitor. The n-channel double-gate JFET is considered from the viewpoint of the restoring action as a parasitic p-n-p ''transversal'' bipolar junction transistor. The new preamplifier is also suited for detectors operating at room temperature with leakage current which may vary with time. The DC behaviour and the dynamic behaviour of the circuit is analyzed and new measurements presented. (orig.)

Open-gated pH sensor fabricated on an undoped-AlGaN/GaN HEMT structure.

Science.gov (United States)

Abidin, Mastura Shafinaz Zainal; Hashim, Abdul Manaf; Sharifabad, Maneea Eizadi; Rahman, Shaharin Fadzli Abd; Sadoh, Taizoh

2011-01-01

The sensing responses in aqueous solution of an open-gated pH sensor fabricated on an AlGaN/GaN high-electron-mobility-transistor (HEMT) structure are investigated. Under air-exposed ambient conditions, the open-gated undoped AlGaN/GaN HEMT only shows the presence of a linear current region. This seems to show that very low Fermi level pinning by surface states exists in the undoped AlGaN/GaN sample. In aqueous solution, typical current-voltage (I-V) characteristics with reasonably good gate controllability are observed, showing that the potential of the AlGaN surface at the open-gated area is effectively controlled via aqueous solution by the Ag/AgCl gate electrode. The open-gated undoped AlGaN/GaN HEMT structure is capable of distinguishing pH level in aqueous electrolytes and exhibits linear sensitivity, where high sensitivity of 1.9 mA/pH or 3.88 mA/mm/pH at drain-source voltage, V(DS) = 5 V is obtained. Due to the large leakage current where it increases with the negative gate voltage, Nernstian like sensitivity cannot be determined as commonly reported in the literature. This large leakage current may be caused by the technical factors rather than any characteristics of the devices. Surprisingly, although there are some imperfections in the device preparation and measurement, the fabricated devices work very well in distinguishing the pH levels. Suppression of current leakage by improving the device preparation is likely needed to improve the device performance. The fabricated device is expected to be suitable for pH sensing applications.

Open-Gated pH Sensor Fabricated on an Undoped-AlGaN/GaN HEMT Structure

Directory of Open Access Journals (Sweden)

Taizoh Sadoh

2011-03-01

Full Text Available The sensing responses in aqueous solution of an open-gated pH sensor fabricated on an AlGaN/GaN high-electron-mobility-transistor (HEMT structure are investigated. Under air-exposed ambient conditions, the open-gated undoped AlGaN/GaN HEMT only shows the presence of a linear current region. This seems to show that very low Fermi level pinning by surface states exists in the undoped AlGaN/GaN sample. In aqueous solution, typical current-voltage (I-V characteristics with reasonably good gate controllability are observed, showing that the potential of the AlGaN surface at the open-gated area is effectively controlled via aqueous solution by the Ag/AgCl gate electrode. The open-gated undoped AlGaN/GaN HEMT structure is capable of distinguishing pH level in aqueous electrolytes and exhibits linear sensitivity, where high sensitivity of 1.9 mA/pH or 3.88 mA/mm/pH at drain-source voltage, VDS = 5 V is obtained. Due to the large leakage current where it increases with the negative gate voltage, Nernstian like sensitivity cannot be determined as commonly reported in the literature. This large leakage current may be caused by the technical factors rather than any characteristics of the devices. Surprisingly, although there are some imperfections in the device preparation and measurement, the fabricated devices work very well in distinguishing the pH levels. Suppression of current leakage by improving the device preparation is likely needed to improve the device performance. The fabricated device is expected to be suitable for pH sensing applications.

Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

Science.gov (United States)

Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

2018-01-01

Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

Gate length variation effect on performance of gate-first self-aligned In₀.₅₃Ga₀.₄₇As MOSFET.

Science.gov (United States)

Mohd Razip Wee, Mohd F; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y

2013-01-01

A multi-gate n-type In₀.₅₃Ga₀.₄₇As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm(2)/Vs are achieved for the gate length and width of 0.2 µm and 30 µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10(-8) A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared.

Gate Length Variation Effect on Performance of Gate-First Self-Aligned In0.53Ga0.47As MOSFET

Science.gov (United States)

Mohd Razip Wee, Mohd F.; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y.

2013-01-01

A multi-gate n-type In0.53Ga0.47As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm2/Vs are achieved for the gate length and width of 0.2 µm and 30µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10−8 A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared. PMID:24367548

Low-leakage, high-current power crowbar transformer

International Nuclear Information System (INIS)

Buck, R.T.; Galbraith, J.D.; Nunnally, W.C.

1979-01-01

The design, fabrication, and testing of two sizes of power crowbar transformers for the ZT-40 Toroidal Z-Pinch experiment at the Los Alamos Scientific Laboratory are described. Low-leakage transformers in series with the poloidal and the toroidal field coils are used to sustain magnetic field currents initially produced by 50-kV capacitor banks. The transformer primaries are driven by cost-effective, ignitron-switched, 10-kV high-density capacitor banks. The transformer secondaries, in series with the field coils, provide from 1,000 to 1,500 V to cancel the resistive voltage drop in the coil circuits. Prototype transformers, with a total leakage inductance measured in the secondary of 5 nH, have been tested with peak secondary currents in excess of 600 kA resulting from a 10-kV primary charge voltage. The test procedures and results and the mechanical construction details are presented

An “ohmic-first” self-terminating gate-recess technique for normally-off Al2O3/GaN MOSFET

Science.gov (United States)

Wang, Hongyue; Wang, Jinyan; Li, Mengjun; He, Yandong; Wang, Maojun; Yu, Min; Wu, Wengang; Zhou, Yang; Dai, Gang

2018-04-01

In this article, an ohmic-first AlGaN/GaN self-terminating gate-recess etching technique was demonstrated where ohmic contact formation is ahead of gate-recess-etching/gate-dielectric-deposition (GRE/GDD) process. The ohmic contact exhibits few degradations after the self-terminating gate-recess process. Besides, when comparing with that using the conventional fabrication process, the fabricated device using the ohmic-first fabrication process shows a better gate dielectric quality in terms of more than 3 orders lower forward gate leakage current, more than twice higher reverse breakdown voltage as well as better stability. Based on this proposed technique, the normally-off Al2O3/GaN MOSFET exhibits a threshold voltage (V th) of ˜1.8 V, a maximum drain current of ˜328 mA/mm, a forward gate leakage current of ˜10-6 A/mm and an off-state breakdown voltage of 218 V at room temperature. Meanwhile, high temperature characteristics of the device was also evaluated and small variations (˜7.6%) of the threshold voltage was confirmed up to 300 °C.

Microdose Induced Drain Leakage Effects in Power Trench MOSFETs: Experiment and Modeling

Science.gov (United States)

Zebrev, Gennady I.; Vatuev, Alexander S.; Useinov, Rustem G.; Emeliyanov, Vladimir V.; Anashin, Vasily S.; Gorbunov, Maxim S.; Turin, Valentin O.; Yesenkov, Kirill A.

2014-08-01

We study experimentally and theoretically the micro-dose induced drain-source leakage current in the trench power MOSFETs under irradiation with high-LET heavy ions. We found experimentally that cumulative increase of leakage current occurs by means of stochastic spikes corresponding to a strike of single heavy ion into the MOSFET gate oxide. We simulate this effect with the proposed analytic model allowing to describe (including Monte Carlo methods) both the deterministic (cumulative dose) and stochastic (single event) aspects of the problem. Based on this model the survival probability assessment in space heavy ion environment with high LETs was proposed.

Online junction temperature measurement using peak gate current

DEFF Research Database (Denmark)

Baker, Nick; Munk-Nielsen, Stig; Iannuzzo, Francesco

2015-01-01

A new method for junction temperature measurement of MOS-gated power semiconductor switches is presented. The measurement method involves detecting the peak voltage over the external gate resistor of an IGBT or MOSFET during turn-on. This voltage is directly proportional to the peak gate current...

Acoustic control of sodium leakage in valve gates of NPP

International Nuclear Information System (INIS)

Trykov, E.L.; Kovtun, S.N.; Anan'ev, A.A.; Yugov, S.I.

2014-01-01

Short description of sodium bench and acoustic investigation results on leakage monitoring of valves DN10 and DN40 are given. It is shown that acoustic method can be used successfully to control the leakages of sodium valves. Leakages on both type of valves increase the acoustic signal dispersion by 2-3 orders. For each type of valve acoustic system of leakage determination allows to conduct the preliminary graduation of signal dispersion on the sodium discharge rate. It make possible not only to record the leakage presence but also to determine the sodium discharge rate through the valve during the leakage [ru

Design and simulation of nanoscale double-gate TFET/tunnel CNTFET

Science.gov (United States)

Bala, Shashi; Khosla, Mamta

2018-04-01

A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si), gallium arsenide (GaAs), alminium gallium arsenide (Al x Ga1‑x As) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are compared on the basis of inverse subthreshold slope (SS), I ON/I OFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the Al x Ga1‑x As based DG tunnel FET provides a better I ON/I OFF current ratio (2.51 × 106) as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.

An analytical gate tunneling current model for MOSFETs

Energy Technology Data Exchange (ETDEWEB)

Kazerouni, Iman Abaspur, E-mail: imanabaspur@gmail.com; Hosseini, Seyed Ebrahim [Sabzevar Tarbiat Moallem University, Electrical and Computer Department (Iran, Islamic Republic of)

2012-03-15

Gate tunneling current of MOSFETs is an important factor in modeling ultra small devices. In this paper, gate tunneling in present-generation MOSFETs is studied. In the proposed model, we calculate the electron wave function at the semiconductor-oxide interface and inversion charge by treating the inversion layer as a potential well, including some simplifying assumptions. Then we compute the gate tunneling current using the calculated wave function. The proposed model results have an excellent agreement with experimental results in the literature.

The Challenges of Implementing Fine-Grained Power Gating

NARCIS (Netherlands)

Niedermeier, A.; Svarstad, Kjetil; Bouwens, Frank; Hulzink, Jos; Huisken, Jos

2010-01-01

Power consumption in digital systems, especially in portable devices, is a crucial design factor. Due to downscaling of technology, dynamic switching power is not the only relevant source of power consumption anymore as power dissipation caused by leakage currents increases. Even though power gating

Single phase cascaded H5 inverter with leakage current elimination for transformerless photovoltaic system

DEFF Research Database (Denmark)

Guo, Xiaoqiang; Jia, X.; Lu, Z.

2016-01-01

Leakage current reduction is one of the important issues for the transformelress PV systems. In this paper, the transformerless single-phase cascaded H-bridge PV inverter is investigated. The common mode model for the cascaded H4 inverter is analyzed. And the reason why the conventional cascade H4...... inverter fails to reduce the leakage current is clarified. In order to solve the problem, a new cascaded H5 inverter is proposed to solve the leakage current issue. Finally, the experimental results are presented to verify the effectiveness of the proposed topology with the leakage current reduction...... for the single-phase transformerless PV systems....

Analysis of the Effect of Channel Leakage on Design, Characterization and Modelling of a High Voltage Pseudo-Floating Gate Sensor-Front-End

Directory of Open Access Journals (Sweden)

Luca Marchetti

2017-10-01

Full Text Available In this paper, we analyze the effects of channel leakage on the design, modelling and characterization of a high voltage pseudo-floating gate amplifier (PFGA used as sensor front-end. Leakages are known as a major challenge in new modern CMOS technologies, which are used to bias the PFGA, and consequently affect the behavior of the amplifier. As high voltages are desired for actuation of many types of resonating sensors, especially in ultrasound applications, PFGA implemented in high voltage and low leakage technologies, such as older CMOS fabrication processes or power MOSFET can be the only option. The challenge with these technologies used to implement the PFGA is that the leakages are very low, which affect the biasing of the floating gate. However, the numerous advantages of this type of amplifier, implemented with modern fabrication processes, such as high flexibility, compactness, low power consumption , etc. encouraged the authors to research about this topic. This work provides analysis of the working principle and the design rules for this amplifier, emphasizing the major differences between PFGA implemented in low leakage and high leakage technologies. Static and dynamic analysis, input offset and non-linearity of the PFGA are the main topics of this article. Three different design approaches are presented in this paper, in order to provide a more general design procedure and offset compensation for any low leakage PFGA. The amplifier has been simulated in AMS- 0 . 35 μ m CMOS models for supply voltages of 5 V and 10 V. Two prototypes have been realized to verify the validity of the modelling and the simulation results. Both devices have been realized by using discrete components and mounted on a printed circuit board. In this work, MOSFETs are realized by using commercial IC CD4007UB and 2N7000. Measurement results of the first prototype proved that the implementation of a low leakage PFGA is possible after that the input offset of

Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor

Science.gov (United States)

Madan, Jaya; Gupta, R. S.; Chaujar, Rishu

2015-09-01

In this work, an analytical drain current model for gate dielectric engineered (hetero dielectric)-dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed. Parabolic approximation has been used to solve the two-dimensional (2D) Poisson equation with appropriate boundary conditions and continuity equations to evaluate analytical expressions for surface potential, electric field, tunneling barrier width and drain current. Further, the analog performance of the device is studied for three high-k dielectrics (Si3N4, HfO2, and ZrO2), and it has been investigated that the problem of lower ION, can be overcome by using the hetero-gate architecture. Moreover, the impact of scaling the gate oxide thickness and bias variations has also been studied. The HD-DMG-GAA-TFET shows an enhanced ION of the order of 10-4 A. The effectiveness of the proposed model is validated by comparing it with ATLAS device simulations.

Parametrization of the radiation induced leakage current increase of NMOS transistors

CERN Document Server

Backhaus, Malte

2017-01-13

The increase of the leakage current of NMOS transistors during exposure to ionizing radiation is known and well studied. Radiation hardness by design techniques have been developed to mitigate this effect and have been successfully used. More recent developments in smaller feature size technologies do not make use of these techniques due to their drawbacks in terms of logic density and requirement of dedicated libraries. During operation the resulting increase of the supply current is a serious challenge and needs to be considered during the system design. A simple parametrization of the leakage current of NMOS transistors as a function of total ionizing dose is presented. The parametrization uses a transistor transfer characteristics of the parasitic transistor along the shallow trench isolation to describe the leakage current of the nominal transistor. Together with a parametrization of the number of positive charges trapped in the silicon dioxide and number of activated interface traps in the silicon to si...

The influence of interband tunneling on leakage current in manganite/titanate heterojunction

International Nuclear Information System (INIS)

Han Peng; Jia Jinfeng

2008-01-01

The behavior of leakage current at reverse bias in p-La 0.9 Sr 0.1 MnO 3 /n-SrNb 0.01 Ti 0.99 O 3 heterojunction has been theoretically studied by calculating interband tunneling current with various doping densities and temperatures. Our results reveal that the reduction of leakage current with decrease of doping density and increase of temperature originates from properties of interband tunneling

Power gating of VLSI circuits using MEMS switches in low power applications

KAUST Repository

Shobak, Hosam

2011-12-01

Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

Estimation of leakage power and delay in CMOS circuits using parametric variation

Directory of Open Access Journals (Sweden)

Preeti Verma

2016-09-01

Full Text Available With the advent of deep-submicron technologies, leakage power dissipation is a major concern for scaling down portable devices that have burst-mode type integrated circuits. In this paper leakage reduction technique HTLCT (High Threshold Leakage Control Transistor is discussed. Using high threshold transistors at the place of low threshold leakage control transistors, result in more leakage power reduction as compared to LCT (leakage control transistor technique but at the scarifies of area and delay. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. It is found that the leakage power dissipation increases with increasing temperature, supply voltage and aspect ratio. However, opposite pattern is noticed for the propagation delay. Leakage power dissipation for LCT NAND gate increases up to 14.32%, 6.43% and 36.21% and delay decreases by 22.5%, 42% and 9% for variation of temperature, supply voltage and aspect ratio. Maximum peak of equivalent output noise is obtained as 127.531 nV/Sqrt(Hz at 400 mHz.

Leakage current reduction of vertical GaN junction barrier Schottky diodes using dual-anode process

Science.gov (United States)

Hayashida, Tetsuro; Nanjo, Takuma; Furukawa, Akihiko; Watahiki, Tatsuro; Yamamuka, Mikio

2018-04-01

The origin of the leakage current of a trench-type vertical GaN diode was discussed. We found that the edge of p-GaN is the main leakage spot. To reduce the reverse leakage current at the edge of p-GaN, a dual-anode process was proposed. As a result, the reverse blocking voltage defined at the leakage current density of 1 mA/cm2 of a vertical GaN junction barrier Schottky (JBS) diode was improved from 780 to 1,190 V, which is the highest value ever reported for vertical GaN Schottky barrier diodes (SBDs).

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

Science.gov (United States)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Compilation of current literature on seals, closures, and leakage for radioactive material packagings

International Nuclear Information System (INIS)

Warrant, M.M.; Ottinger, C.A.

1989-01-01

This report presents an overview of the features that affect the sealing capability of radioactive material packagings currently certified by the US Nuclear Regulatory Commission. The report is based on a review of current literature on seals, closures, and leakage for radioactive material packagings. Federal regulations that relate to the sealing capability of radioactive material packagings, as well as basic equations for leakage calculations and some of the available leakage test procedures are presented. The factors which affect the sealing capability of a closure, including the properties of the sealing surfaces, the gasket material, the closure method and the contents are discussed in qualitative terms. Information on the general properties of both elastomer and metal gasket materials and some specific designs are presented. A summary of the seal material, closure method, and leakage tests for currently certified packagings with large diameter seals is provided. 18 figs., 9 tabs

Leakage current measurement in transformerless PV inverters

DEFF Research Database (Denmark)

Kerekes, Tamas; Sera, Dezso; Mathe, Laszlo

2012-01-01

Photovoltaic (PV) installations have seen a huge increase during the last couple of years. Transformerless PV inverters are gaining more share of the total inverter market, due to their high conversion efficiency, small weight and size. Nevertheless safety should have an important role in case...... of these tranformerless systems, due to the missing galvanic isolation. Leakage and fault current measurement is a key issue for these inverter topologies to be able to comply with the required safety standards. This article presents the test results of two different current measurement sensors that were suggested...

Leakage current of amorphous silicon p-i-n diodes made by ion shower doping

International Nuclear Information System (INIS)

Kim, Hee Joon; Cho, Gyuseong; Choi, Joonhoo; Jung, Kwan-Wook

2002-01-01

In this letter, we report the leakage current of amorphous silicon (a-Si:H) p-i-n photodiodes, of which the p layer is formed by ion shower doping. The ion shower doping technique has an advantage over plasma-enhanced chemical vapor deposition (PECVD) in the fabrication of a large-area amorphous silicon flat-panel detector. The leakage current of the ion shower diodes shows a better uniformity within a 30 cmx40 cm substrate than that of the PECVD diodes. However, it shows a higher leakage current of 2-3 pA/mm 2 at -5 V. This high current originates from the high injection current at the p-i junction

Ultra-low power thin film transistors with gate oxide formed by nitric acid oxidation method

International Nuclear Information System (INIS)

Kobayashi, H.; Kim, W. B.; Matsumoto, T.

2011-01-01

We have developed a low temperature fabrication method of SiO 2 /Si structure by use of nitric acid, i.e., nitric acid oxidation of Si (NAOS) method, and applied it to thin film transistors (TFT). A silicon dioxide (SiO 2 ) layer formed by the NAOS method at room temperature possesses 1.8 nm thickness, and its leakage current density is as low as that of thermally grown SiO 2 layer with the same thickness formed at ∼900 deg C. The fabricated TFTs possess an ultra-thin NAOS SiO 2 /CVD SiO 2 stack gate dielectric structure. The ultrathin NAOS SiO 2 layer effectively blocks a gate leakage current, and thus, the thickness of the gate oxide layer can be decreased from 80 to 20 nm. The thin gate oxide layer enables to decrease the operation voltage to 2 V (cf. the conventional operation voltage of TFTs with 80 nm gate oxide: 12 V) because of the low threshold voltages, i.e., -0.5 V for P-ch TFTs and 0.5 V for N-ch TFTs, and thus the consumed power decreases to 1/36 of that of the conventional TFTs. The drain current increases rapidly with the gate voltage, and the sub-threshold voltage is ∼80 mV/dec. The low sub-threshold swing is attributable to the thin gate oxide thickness and low interface state density of the NAOS SiO 2 layer. (authors)

GaN-on-silicon high-electron-mobility transistor technology with ultra-low leakage up to 3000 V using local substrate removal and AlN ultra-wide bandgap

Science.gov (United States)

Dogmus, Ezgi; Zegaoui, Malek; Medjdoub, Farid

2018-03-01

We report on extremely low off-state leakage current in AlGaN/GaN-on-silicon metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) up to a high blocking voltage. Remarkably low off-state gate and drain leakage currents below 1 µA/mm up to 3 kV have been achieved owing to the use of a thick in situ SiN gate dielectric under the gate, and a local Si substrate removal technique combined with a cost effective 15-µm-thick AlN dielectric layer followed by a Cu deposition. This result establishes a manufacturable state-of-the-art high-voltage GaN-on-silicon power transistors while maintaining a low specific on-resistance of approximately 10 mΩ·cm2.

Gate less-FET pH Sensor Fabricated on Undoped AlGaN/ GaN HEMT Structure

International Nuclear Information System (INIS)

Maneea Eizadi Sharifabad; Mastura Shafinaz Zainal Abidin; Shaharin Fadzli Abd Rahman; Abdul Manaf Hashim; Abdul Rahim Abdul Rahman

2011-01-01

Gallium nitride with wurtzite crystal structure is a chemically stable semiconductor with high internal spontaneous and piezoelectric polarization, which make it highly suitable materials to create very sensitive and robust sensors for the detection of ions, gases and liquids. Sensing characteristics of an open-gate liquid-phase sensor fabricated on undoped-AlGaN/ GaN high-electron-mobility-transistor (HEMT) structure in aqueous solution was investigated. In ambient atmosphere, the open-gate undoped AlGaN/ GaN HEMT clearly showed only the presence of linear region of currents while Si-doped AlGaN/ GaN showed the linear and saturation regions of currents, very similar to those of gated devices. This seems to show that very low Fermi level pinning by surface states exists in undoped AlGaN/ GaN sample. In aqueous solution, the typical current-voltage (I-V) characteristics of HEMTs with good gate controllability were observed. The potential of the AlGaN surface at the open-gate area is effectively controlled via aqueous solution by Ag/ AgCl reference gate electrode. The open-gate undoped AlGaN/ GaN HEMT structure is capable of stable operation in aqueous electrolytes and exhibit linear sensitivity, and high sensitivity of 1.9 mA/ pH or 3.88 mA/ mm/ pH at drain-source voltage, VDS = 5 V was obtained. Due to large leakage current where it increases with the negative reference gate voltage, the Nernstians like sensitivity cannot be determined. Suppression of current leakage is likely to improve the device performance. The open-gate undoped-AlGaN/ GaN structure is expected to be suitable for pH sensing application. (author)

Spin-polarized current generated by magneto-electrical gating

International Nuclear Information System (INIS)

Ma Minjie; Jalil, Mansoor Bin Abdul; Tan, Seng Ghee

2012-01-01

We theoretically study spin-polarized current through a single electron tunneling transistor (SETT), in which a quantum dot (QD) is coupled to non-magnetic source and drain electrodes via tunnel junctions, and gated by a ferromagnetic (FM) electrode. The I–V characteristics of the device are investigated for both spin and charge currents, based on the non-equilibrium Green's function formalism. The FM electrode generates a magnetic field, which causes a Zeeman spin-splitting of the energy levels in the QD. By tuning the size of the Zeeman splitting and the source–drain bias, a fully spin-polarized current is generated. Additionally, by modulating the electrical gate bias, one can effect a complete switch of the polarization of the tunneling current from spin-up to spin-down current, or vice versa. - Highlights: ► The spin polarized transport through a single electron tunneling transistor is systematically studied. ► The study is based on Keldysh non-equilibrium Green's function and equation of motion method. ► A fully spin polarized current is observed. ► We propose to reverse current polarization by the means of gate voltage modulation. ► This device can be used as a bi-polarization current generator.

Effects of trap-assisted tunneling on gate-induced drain leakage in silicon-germanium channel p-type FET for scaled supply voltages

Science.gov (United States)

Tiwari, Vishal A.; Divakaruni, Rama; Hook, Terence B.; Nair, Deleep R.

2016-04-01

Silicon-germanium is considered as an alternative channel material to silicon p-type FET (pFET) for the development of energy efficient high performance transistors for 28 nm and beyond in a high-k metal gate technology because of its lower threshold voltage and higher mobility. However, gate-induced drain leakage (GIDL) is a concern for high threshold voltage device design because of tunneling at reduced bandgap. In this work, the trap-assisted tunneling and band-to-band tunneling (BTBT) effects on GIDL is analyzed and modeled for SiGe pFETs. Experimental results and Monte Carlo simulation results reveal that the pre-halo germanium pre-amorphization implant used to contain the short channel effects contribute to GIDL at the drain sidewall in addition to GIDL due to BTBT in SiGe devices. The results are validated by comparing the experimental observations with the numerical simulation and a set of calibrated models are used to describe the GIDL mechanisms for various drain and gate bias.

Instrumentation for Gate Current Noise Measurements on sub-100 nm MOS Transistors

CERN Document Server

Gaioni, L; Ratti, L; Re, V; Speziali, V; Traversi, G

2008-01-01

This work describes a measuring system that was developed to characterize the gate current noise performances of CMOS devices with minimum feature size in the 100 nm span. These devices play an essential role in the design of present daymixedsignal integrated circuits, because of the advantages associated with the scaling process. The reduction in the gate oxide thickness brought about by CMOS technology downscaling leads to a non-negligible gate current due to direct tunneling phenomena; this current represents a noise source which requires an accurate characterization for optimum analog design. In this paper, two instruments able to perform measurements in two different ranges of gate current values will be discussed. Some of the results of gate current noise characterization will also be presented.

Oscillation of Critical Current by Gate Voltage in Cooper Pair Transistor

International Nuclear Information System (INIS)

Kim, N.; Cheong, Y.; Song, W.

2010-01-01

We measured the critical current of a Cooper pair transistor consisting of two Josephson junctions and a gate electrode. The Cooper pair transistors were fabricated by using electron-beam lithography and double-angle evaporation technique. The Gate voltage dependence of critical current was measured by observing voltage jumps at various gate voltages while sweeping bias current. The observed oscillation was 2e-periodic, which shows the Cooper pair transistor had low level of quasiparticle poisoning.

Correlation among ESDD, NSDD and leakage current in distribution insulators

International Nuclear Information System (INIS)

Montoya, G.; Ramirez, I.; Montoya, J.I.

2004-01-01

The maintenance of distribution networks is more effective if the insulation contamination levels are known. The selection of measuring methods of pollution levels is then crucial. The relationship between several evaluation methods of pollution levels and the operating behaviour of several insulator profiles in a polluted zone is described. Laboratory tests were carried out to reproduce pollution levels found in the field. The quantity of non-soluble materials deposited over the insulators' surface affect the magnitude of the leakage current generated over a contaminated insulator. The relationship that defines leakage current with respect to the equivalent salt deposit density (ESDD) level for a specific non-soluble material level is almost linear, from which it is possible to develop a relationship between them for each insulator. (author)

Leakage Currents in Low-Voltage PME and BME Ceramic Capacitors

Science.gov (United States)

Teverovsky, Alexander

2015-01-01

Introduction of BME capacitors to high-reliability electronics as a replacement for PME capacitors requires better understanding of changes in performance and reliability of MLCCs to set justified screening and qualification requirements. In this work, absorption and leakage currents in various lots of commercial and military grade X7R MLCCs rated to 100V and less have been measured to reveal difference in behavior of PME and BME capacitors in a wide range of voltages and temperatures. Degradation of leakage currents and failures in virgin capacitors and capacitors with introduced cracks has been studied at different voltages and temperatures during step stress highly accelerated life testing. Mechanisms of charge absorption, conduction and degradation have been discussed and a failure model in capacitors with defects suggested.

Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

Science.gov (United States)

An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

2016-11-01

Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

Unusual Voltage-Gated Sodium Currents as Targets for Pain.

Science.gov (United States)

Barbosa, C; Cummins, T R

2016-01-01

Pain is a serious health problem that impacts the lives of many individuals. Hyperexcitability of peripheral sensory neurons contributes to both acute and chronic pain syndromes. Because voltage-gated sodium currents are crucial to the transmission of electrical signals in peripheral sensory neurons, the channels that underlie these currents are attractive targets for pain therapeutics. Sodium currents and channels in peripheral sensory neurons are complex. Multiple-channel isoforms contribute to the macroscopic currents in nociceptive sensory neurons. These different isoforms exhibit substantial variations in their kinetics and pharmacology. Furthermore, sodium current complexity is enhanced by an array of interacting proteins that can substantially modify the properties of voltage-gated sodium channels. Resurgent sodium currents, atypical currents that can enhance recovery from inactivation and neuronal firing, are increasingly being recognized as playing potentially important roles in sensory neuron hyperexcitability and pain sensations. Here we discuss unusual sodium channels and currents that have been identified in nociceptive sensory neurons, describe what is known about the molecular determinants of the complex sodium currents in these neurons. Finally, we provide an overview of therapeutic strategies to target voltage-gated sodium currents in nociceptive neurons. Copyright © 2016 Elsevier Inc. All rights reserved.

Leakage current measurements on pixelated CdZnTe detectors

International Nuclear Information System (INIS)

Dirks, B.P.F.; Blondel, C.; Daly, F.; Gevin, O.; Limousin, O.; Lugiez, F.

2006-01-01

In the field of the R and D of a new generation hard X-ray cameras for space applications we focus on the use of pixelated CdTe or CdZnTe semiconductor detectors. They are covered with 64 (0.9x0.9 mm 2 ) or 256 (0.5x0.5 mm 2 ) pixels, surrounded by a guard ring and operate in the energy ranging from several keV to 1 MeV, at temperatures between -20 and +20 o C. A critical parameter in the characterisation of these detectors is the leakage current per pixel under polarisation (∼50-500 V/mm). In operation mode each pixel will be read-out by an integrated spectroscopy channel of the multi-channel IDeF-X ASIC currently developed in our lab. The design and functionality of the ASIC depends directly on the direction and value of the current. A dedicated and highly insulating electronics circuit is designed to automatically measure the current in each individual pixel, which is in the order of tens of pico-amperes. Leakage current maps of different CdZnTe detectors of 2 and 6 mm thick and at various temperatures are presented and discussed. Defect density diagnostics have been performed by calculation of the activation energy of the material

Physical and electrical properties of bilayer CeO{sub 2}/TiO{sub 2} gate dielectric stack

Energy Technology Data Exchange (ETDEWEB)

Chong, M.M.V. [School of Materials Science and Engineering, Nanyang Technological University of Singapore, Block N 4.1Nanyang Avenue, Singapore 639798 (Singapore); GlobalFoundries Singapore Private Limited, 60 Woodlands Industrial Park D Street 2, Singapore 738406 (Singapore); Lee, P.S. [School of Materials Science and Engineering, Nanyang Technological University of Singapore, Block N 4.1Nanyang Avenue, Singapore 639798 (Singapore); Tok, A.I.Y., E-mail: MIYTOK@ntu.edu.sg [School of Materials Science and Engineering, Nanyang Technological University of Singapore, Block N 4.1Nanyang Avenue, Singapore 639798 (Singapore)

2016-08-15

Highlights: • A bilayer gate dielectric stack of CeO{sub 2}/TiO{sub 2} to study the dependency of film growth with varying annealing temperatures is proposed. • The study demonstrates CeO{sub 2}/TiO{sub 2} bilayer stack with comparable κ-value as that of HfO{sub 2} but with reduced leakage current density of 4 orders of magnitude. • Schottky emission is the dominant leakage conduction mechanism of annealed CeO{sub 2}/TiO{sub 2} stack due to thermionic effect of interface properties. - Abstract: This study demonstrates a bilayer gate oxide structure of cerium oxide deposited via pulsed laser deposition and titanium oxide using conventional atomic layer deposition. Samples were deposited on p-type Si (100) substrate and exhibit interesting physical and electrical properties such that 600 °C annealed CeO{sub 2}/TiO{sub 2} samples having κ-value of 18 whereas pure CeO{sub 2} deposited samples have dielectric constant of 17.1 with leakage current density of 8.94 × 10{sup −6} A/cm{sup 2} at 1 V applied voltage. The result shows promising usage of the synthesized rare earth oxides as gate dielectric where ideal κ-value and significant reduction of the leakage current by 5 orders of magnitude is achieved. Leakage current conduction mechanism for as-deposited sample is found to be dominated by Poole–Frenkel (PF) emission; the trap level is found to be at 1.29 eV whereas annealed samples (600 °C and 800 °C) exhibited Schottky emission with trap levels at 1.45 eV and 0.81 eV, respectively.

Poole Frenkel current and Schottky emission in SiN gate dielectric in AlGaN/GaN metal insulator semiconductor heterostructure field effect transistors

Science.gov (United States)

Hanna, Mina J.; Zhao, Han; Lee, Jack C.

2012-10-01

We analyze the anomalous I-V behavior in SiN prepared by plasma enhanced chemical vapor deposition for use as a gate insulator in AlGaN/GaN metal insulator semiconductor heterostructure filed effect transistors (HFETs). We observe leakage current across the dielectric with opposite polarity with respect to the applied electric field once the voltage sweep reaches a level below a determined threshold. This is observed as the absolute minimum of the leakage current does not occur at minimum voltage level (0 V) but occurs earlier in the sweep interval. Curve-fitting analysis suggests that the charge-transport mechanism in this region is Poole-Frenkel current, followed by Schottky emission due to band bending. Despite the current anomaly, the sample devices have shown a notable reduction of leakage current of over 2 to 6 order of magnitudes compared to the standard Schottky HFET. We show that higher pressures and higher silane concentrations produce better films manifesting less trapping. This conforms to our results that we reported in earlier publications. We found that higher chamber pressure achieves higher sheet carrier concentration that was found to be strongly dependent on the trapped space charge at the SiN/GaN interface. This would suggest that a lower chamber pressure induces more trap states into the SiN/GaN interface.

AlGaN/GaN high-electron-mobility transistors with transparent gates by Al-doped ZnO

International Nuclear Information System (INIS)

Wang Chong; He Yun-Long; Zheng Xue-Feng; Ma Xiao-Hua; Zhang Jin-Cheng; Hao Yue

2013-01-01

AlGaN/GaN high-electron-mobility transistors (HEMTs) with Al-doped ZnO (AZO) transparent gate electrodes are fabricated, and Ni/Au/Ni-gated HEMTs are produced in comparison. The AZO-gated HEMTs show good DC characteristics and Schottky rectifying characteristics, and the gate electrodes achieve excellent transparencies. Compared with Ni/Au/Ni-gated HEMTs, AZO-gated HEMTs show a low saturation current, high threshold voltage, high Schottky barrier height, and low gate reverse leakage current. Due to the higher gate resistivity, AZO-gated HEMTs exhibit a current—gain cutoff frequency (f T ) of 10 GHz and a power gain cutoff frequency (f max ) of 5 GHz, and lower maximum oscillation frequency than Ni/Au/Ni-gated HEMTs. Moreover, the C—V characteristics are measured and the gate interface characteristics of the AZO-gated devices are investigated by a C—V dual sweep

Chemical vapor deposited monolayer MoS2 top-gate MOSFET with atomic-layer-deposited ZrO2 as gate dielectric

Science.gov (United States)

Hu, Yaoqiao; Jiang, Huaxing; Lau, Kei May; Li, Qiang

2018-04-01

For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec-1, and a field-effect electron mobility of 12.1 cm2 V-1 s-1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm-1 at V DS = 5 V. The gate leakage current is below 10-2 A cm-2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm-1 is obtained. Gate hysteresis and frequency-dependent capacitance-voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ˜3 × 1012 cm-2 eV-1.

Role of Ga vacancies in enhancing the leakage current of GaN Schottky barrier ultraviolet photodetectors

International Nuclear Information System (INIS)

De-Gang, Zhao; Shuang, Zhang; Wen-Bao, Liu; De-Sheng, Jiang; Jian-Jun, Zhu; Zong-Shun, Liu; Hui, Wang; Shu-Ming, Zhang; Hui, Yang; Xiao-Peng, Hao; Long, Wei

2010-01-01

The leakage current of GaN Schottky barrier ultraviolet photodetectors is investigated. It is found that the photodetectors adopting undoped GaN instead of lightly Si-doped GaN as an active layer show a much lower leakage current even when they have a higher dislocation density. It is also found that the density of Ga vacancies in undoped GaN is much lower than in Si-doped GaN. The Ga vacancies may enhance tunneling and reduce effective Schottky barrier height, leading to an increase of leakage current. It suggests that when undoped GaN is used as the active layer, it is necessary to reduce the leakage current of GaN Schottky barrier ultraviolet photodetector. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Leakage Current Suppression with A Novel Six-Switch Photovoltaic Grid-Connected Inverter

DEFF Research Database (Denmark)

Wei, Baoze; Guo, Xiaoqiang; Guerrero, Josep M.

2015-01-01

In order to solve the problem of the leakage current in non-isolated photovoltaic (PV) systems, a novel six-switch topology and control strategy are proposed in this paper. The inductor-bypass strategy solves the common-mode voltage limitation of the conventional six-switch topology in case...... of unmatched inductances. And the stray capacitor voltage of the non-isolated photovoltaic system is free of high frequency ripples. Theoretical analysis and simulation are carried out to verify the proposed topology and its control strategy. Results indicate that the leakage current suppression can...

SEMICONDUCTOR DEVICES: Structural and electrical characteristics of lanthanum oxide gate dielectric film on GaAs pHEMT technology

Science.gov (United States)

Chia-Song, Wu; Hsing-Chung, Liu

2009-11-01

This paper investigates the feasibility of using a lanthanum oxide thin film (La2O3) with a high dielectric constant as a gate dielectric on GaAs pHEMTs to reduce gate leakage current and improve the gate to drain breakdown voltage relative to the conventional GaAs pHEMT. An E/D mode pHEMT in a single chip was realized by selecting the appropriate La2O3 thickness. The thin La2O3 film was characterized: its chemical composition and crystalline structure were determined by X-ray photoelectron spectroscopy and X-ray diffraction, respectively. La2O3 exhibited good thermal stability after post-deposition annealing at 200, 400 and 600 °C because of its high binding-energy (835.6 eV). Experimental results clearly demonstrated that the La2O3 thin film was thermally stable. The DC and RF characteristics of Pt/La2O3/Ti/Au gate and conventional Pt/Ti/Au gate pHEMTs were examined. The measurements indicated that the transistor with the Pt/La2O3/Ti/Au gate had a higher breakdown voltage and lower gate leakage current. Accordingly, the La2O3 thin film is a potential high-k material for use as a gate dielectric to improve electrical performance and the thermal effect in high-power applications.

High performance top-gated indium–zinc–oxide thin film transistors with in-situ formed HfO{sub 2} gate insulator

Energy Technology Data Exchange (ETDEWEB)

Song, Yang, E-mail: yang_song@brown.edu [Department of Physics, Brown University, 182 Hope Street, Providence, RI 02912 (United States); Zaslavsky, A. [Department of Physics, Brown University, 182 Hope Street, Providence, RI 02912 (United States); School of Engineering, Brown University, 184 Hope Street, Providence, RI 02912 (United States); Paine, D.C. [School of Engineering, Brown University, 184 Hope Street, Providence, RI 02912 (United States)

2016-09-01

We report on top-gated indium–zinc–oxide (IZO) thin film transistors (TFTs) with an in-situ formed HfO{sub 2} gate dielectric insulator. Building on our previous demonstration of high-performance IZO TFTs with Al{sub 2}O{sub 3}/HfO{sub 2} gate dielectric, we now report on a one-step process, in which Hf is evaporated onto the 20 nm thick IZO channel, forming a partially oxidized HfO{sub x} layer, without any additional insulator in-between. After annealing in air at 300 °C, the in-situ reaction between partially oxidized Hf and IZO forms a high quality HfO{sub 2} gate insulator with a low interface trapped charge density N{sub TC} ~ 2.3 × 10{sup 11} cm{sup −2} and acceptably low gate leakage < 3 × 10{sup −7} A/cm{sup 2} at gate voltage V{sub G} = 1 V. The annealed TFTs with gate length L{sub G} = 50 μm have high mobility ~ 95 cm{sup 2}/V ∙ s (determined via the Y-function technique), high on/off ratio ~ 10{sup 7}, near-zero threshold voltage V{sub T} = − 0.02 V, and a subthreshold swing of 0.062 V/decade, near the theoretical limit. The on-current of our proof-of-concept TFTs is relatively low, but can be improved by reducing L{sub G}, indicating that high-performance top-gated HfO{sub 2}-isolated IZO TFTs can be fabricated using a single-step in-situ dielectric formation approach. - Highlights: • High-performance indium–zinc–oxide (IZO) thin film transistors (TFTs). • Single-step in-situ dielectric formation approach simplifies fabrication process. • During anneal, reaction between HfO{sub x} and IZO channel forms a high quality HfO{sub 2} layer. • Gate insulator HfO{sub 2} shows low interface trapped charge and small gate leakage. • TFTs have high mobility, near-zero threshold voltage, and a low subthreshold swing.

Influence of the device geometry on the Schottky gate characteristics of AlGaN/GaN HEMTs

International Nuclear Information System (INIS)

Lu, C Y; Chang, E Y; Bahat-Treidel, E; Hilt, O; Lossy, R; Chaturvedi, N; Würfl, J; Tränkle, G

2010-01-01

In this work, we investigate the relevance of device geometry to the Schottky gate characteristics of AlGaN/GaN high electron mobility transistors. Changes of three-terminal gate turn-on voltage and gate leakage current on the gate—drain spacing, source—gate spacing and recess depth have been observed. Further examinations comparing device simulations and measurements suggest that gate turn-on voltage is influenced by the distribution of electric potential under the gate region which is related to the geometry. By proper design of the device, high gate turn-on voltage can be obtained for both depletion-mode and recessed enhancement-mode devices

Reverse leakage current characteristics of InGaN/GaN multiple quantum well ultraviolet/blue/green light-emitting diodes

Science.gov (United States)

Zhou, Shengjun; Lv, Jiajiang; Wu, Yini; Zhang, Yuan; Zheng, Chenju; Liu, Sheng

2018-05-01

We investigated the reverse leakage current characteristics of InGaN/GaN multiple quantum well (MQW) near-ultraviolet (NUV)/blue/green light-emitting diodes (LEDs). Experimental results showed that the NUV LED has the smallest reverse leakage current whereas the green LED has the largest. The reason is that the number of defects increases with increasing nominal indium content in InGaN/GaN MQWs. The mechanism of the reverse leakage current was analyzed by temperature-dependent current–voltage measurement and capacitance–voltage measurement. The reverse leakage currents of NUV/blue/green LEDs show similar conduction mechanisms: at low temperatures, the reverse leakage current of these LEDs is attributed to variable-range hopping (VRH) conduction; at high temperatures, the reverse leakage current of these LEDs is attributed to nearest-neighbor hopping (NNH) conduction, which is enhanced by the Poole–Frenkel effect.

Highly conducting leakage-free electrolyte for SrCoOx-based non-volatile memory device

Science.gov (United States)

Katase, Takayoshi; Suzuki, Yuki; Ohta, Hiromichi

2017-10-01

The electrochemical switching of SrCoOx-based non-volatile memory with a thin-film-transistor structure was examined by using liquid-leakage-free electrolytes with different conductivities (σ) as the gate insulator. We first examined leakage-free water, which is incorporated in the amorphous (a-) 12CaO.7Al2O3 film with a nanoporous structure (Calcium Aluminate with Nanopore), but the electrochemical oxidation/reduction of the SrCoOx layer required the application of a high gate voltage (Vg) up to 20 V for a very long current-flowing-time (t) ˜40 min, primarily due to the low σ [2.0 × 10-8 S cm-1 at room temperature (RT)] of leakage-free water. We then controlled the σ of the leakage-free electrolyte, infiltrated in the a-NaxTaO3 film with a nanopillar array structure, from 8.0 × 10-8 S cm-1 to 2.5 × 10-6 S cm-1 at RT by changing the x = 0.01-1.0. As the result, the t, required for the metallization of the SrCoOx layer under small Vg = -3 V, becomes two orders of magnitude shorter with increase of the σ of the a-NaxTaO3 leakage-free electrolyte. These results indicate that the ion migration in the leakage-free electrolyte is the rate-determining step for the electrochemical switching, compared to the other electrochemical process, and the high σ of the leakage-free electrolyte is the key factor for the development of the non-volatile SrCoOx-based electro-magnetic phase switching device.

Modeling of leakage currents in high-k dielectrics

International Nuclear Information System (INIS)

Jegert, Gunther Christian

2012-01-01

Leakage currents are one of the major bottlenecks impeding the downscaling efforts of the semiconductor industry. Two core devices of integrated circuits, the transistor and, especially, the DRAM storage capacitor, suffer from the increasing loss currents. In this perspective a fundamental understanding of the physical origin of these leakage currents is highly desirable. However, the complexity of the involved transport phenomena so far has prevented the development of microscopic models. Instead, the analysis of transport through the ultra-thin layers of high-permittivity (high-k) dielectrics, which are employed as insulating layers, was carried out at an empirical level using simple compact models. Unfortunately, these offer only limited insight into the physics involved on the microscale. In this context the present work was initialized in order to establish a framework of microscopic physical models that allow a fundamental description of the transport processes relevant in high-k thin films. A simulation tool that makes use of kinetic Monte Carlo techniques was developed for this purpose embedding the above models in an environment that allows qualitative and quantitative analyses of the electronic transport in such films. Existing continuum approaches, which tend to conceal the important physics behind phenomenological fitting parameters, were replaced by three-dimensional transport simulations at the level of single charge carriers. Spatially localized phenomena, such as percolation of charge carriers across pointlike defects, being subject to structural relaxation processes, or electrode roughness effects, could be investigated in this simulation scheme. Stepwise a self-consistent, closed transport model for the TiN/ZrO 2 material system, which is of outmost importance for the semiconductor industry, was developed. Based on this model viable strategies for the optimization of TiN/ZrO 2 /TiN capacitor structures were suggested and problem areas that may

Modeling of leakage currents in high-k dielectrics

Energy Technology Data Exchange (ETDEWEB)

Jegert, Gunther Christian

2012-03-15

Leakage currents are one of the major bottlenecks impeding the downscaling efforts of the semiconductor industry. Two core devices of integrated circuits, the transistor and, especially, the DRAM storage capacitor, suffer from the increasing loss currents. In this perspective a fundamental understanding of the physical origin of these leakage currents is highly desirable. However, the complexity of the involved transport phenomena so far has prevented the development of microscopic models. Instead, the analysis of transport through the ultra-thin layers of high-permittivity (high-k) dielectrics, which are employed as insulating layers, was carried out at an empirical level using simple compact models. Unfortunately, these offer only limited insight into the physics involved on the microscale. In this context the present work was initialized in order to establish a framework of microscopic physical models that allow a fundamental description of the transport processes relevant in high-k thin films. A simulation tool that makes use of kinetic Monte Carlo techniques was developed for this purpose embedding the above models in an environment that allows qualitative and quantitative analyses of the electronic transport in such films. Existing continuum approaches, which tend to conceal the important physics behind phenomenological fitting parameters, were replaced by three-dimensional transport simulations at the level of single charge carriers. Spatially localized phenomena, such as percolation of charge carriers across pointlike defects, being subject to structural relaxation processes, or electrode roughness effects, could be investigated in this simulation scheme. Stepwise a self-consistent, closed transport model for the TiN/ZrO{sub 2} material system, which is of outmost importance for the semiconductor industry, was developed. Based on this model viable strategies for the optimization of TiN/ZrO{sub 2}/TiN capacitor structures were suggested and problem areas

A 200 mV low leakage current subthreshold SRAM bitcell in a 130 nm CMOS process

International Nuclear Information System (INIS)

Bai Na; Lü Baitao

2012-01-01

A low leakage current subthreshold SRAM in 130 nm CMOS technology is proposed for ultra low voltage (200 mV) applications. Almost all of the previous subthreshold works ignore the leakage current in both active and standby modes. To minimize leakage, a self-adaptive leakage cut off scheme is adopted in the proposed design without any extra dynamic energy dissipation or performance penalty. Combined with buffering circuit and reconfigurable operation, the proposed design ensures both read and standby stability without deteriorating writability in the subthreshold region. Compared to the referenced subthreshold SRAM bitcell, the proposed bitcell shows: (1) a better critical state noise margin, and (2) smaller leakage current in both active and standby modes. Measurement results show that the proposed SRAM functions well at a 200 mV supply voltage with 0.13 μW power consumption at 138 kHz frequency. (semiconductor integrated circuits)

Image artifacts in concurrent transcranial magnetic stimulation (TMS) and fMRI caused by leakage currents: modeling and compensation.

Science.gov (United States)

Weiskopf, Nikolaus; Josephs, Oliver; Ruff, Christian C; Blankenburg, Felix; Featherstone, Eric; Thomas, Anthony; Bestmann, Sven; Driver, Jon; Deichmann, Ralf

2009-05-01

To characterize and eliminate a new type of image artifact in concurrent transcranial magnetic stimulation and functional MRI (TMS-fMRI) caused by small leakage currents originating from the high-voltage capacitors in the TMS stimulator system. The artifacts in echo-planar images (EPI) caused by leakage currents were characterized and quantified in numerical simulations and phantom studies with different phantom-coil geometries. A relay-diode combination was devised and inserted in the TMS circuit that shorts the leakage current. Its effectiveness for artifact reduction was assessed in a phantom scan resembling a realistic TMS-fMRI experiment. The leakage-current-induced signal changes exhibited a multipolar spatial pattern and the maxima exceeded 1% at realistic coil-cortex distances. The relay-diode combination effectively reduced the artifact to a negligible level. The leakage-current artifacts potentially obscure effects of interest or lead to false-positives. Since the artifact depends on the experimental setup and design (eg, amplitude of the leakage current, coil orientation, paradigm, EPI parameters), we recommend its assessment for each experiment. The relay-diode combination can eliminate the artifacts if necessary.

Microscopic origin of gating current fluctuations in a potassium channel voltage sensor.

Science.gov (United States)

Freites, J Alfredo; Schow, Eric V; White, Stephen H; Tobias, Douglas J

2012-06-06

Voltage-dependent ion channels open and close in response to changes in membrane electrical potential due to the motion of their voltage-sensing domains (VSDs). VSD charge displacements within the membrane electric field are observed in electrophysiology experiments as gating currents preceding ionic conduction. The elementary charge motions that give rise to the gating current cannot be observed directly, but appear as discrete current pulses that generate fluctuations in gating current measurements. Here we report direct observation of gating-charge displacements in an atomistic molecular dynamics simulation of the isolated VSD from the KvAP channel in a hydrated lipid bilayer on the timescale (10-μs) expected for elementary gating charge transitions. The results reveal that gating-charge displacements are associated with the water-catalyzed rearrangement of salt bridges between the S4 arginines and a set of conserved acidic side chains on the S1-S3 transmembrane segments in the hydrated interior of the VSD. Copyright © 2012 Biophysical Society. Published by Elsevier Inc. All rights reserved.

GaN MOSHEMT employing HfO2 as a gate dielectric with partially etched barrier

Science.gov (United States)

Han, Kefeng; Zhu, Lin

2017-09-01

In order to suppress the gate leakage current of a GaN high electron mobility transistor (GaN HEMT), a GaN metal-oxide-semiconductor high electron mobility transistor (MOSHEMT) is proposed, in which a metal-oxide-semiconductor gate with high-dielectric-constant HfO2 as an insulating dielectric is employed to replace the traditional GaN HEMT Schottky gate. A 0.5 μm gate length GaN MOSHEMT was fabricated based on the proposed structure, the {{{Al}}}0.28{{{Ga}}}0.72{{N}} barrier layer is partially etched to produce a higher transconductance without deteriorating the transport characteristics of the two-dimensional electron gas in the channel, the gate dielectric is HfO2 deposited by atomic layer deposition. Current-voltage characteristics and radio frequency characteristics are obtained after device preparation, the maximum current density of the device is 900 mA mm-1, the source-drain breakdown voltage is 75 V, gate current is significantly suppressed and the forward gate voltage swing range is about ten times higher than traditional GaN HEMTs, the GaN MOSHEMT also demonstrates radio frequency characteristics comparable to traditional GaN HEMTs with the same gate length.

A gate enhanced power U-shaped MOSFET integrated with a Schottky rectifier

International Nuclear Information System (INIS)

Wang Ying; Jiao Wen-Li; Hu Hai-Fan; Liu Yun-Tao; Cao Fei

2012-01-01

An accumulation gate enhanced power U-shaped metal-oxide-semiconductor field-effect-transistor (UMOSFET) integrated with a Schottky rectifier is proposed. In this device, a Schottky rectifier is integrated into each cell of the accumulation gate enhanced power UMOSFET. Specific on-resistances of 7.7 mΩ·mm 2 and 6.5 mΩ·mm 2 for the gate bias voltages of 5 V and 10 V are achieved, respectively, and the breakdown voltage is 61 V. The numerical simulation shows a 25% reduction in the reverse recovery time and about three orders of magnitude reduction in the leakage current as compared with the accumulation gate enhanced power UMOSFET. (condensed matter: structural, mechanical, and thermal properties)

Determination of the Steady State Leakage Current in Structures with Ferroelectric Ceramic Films

Science.gov (United States)

Podgornyi, Yu. V.; Vorotilov, K. A.; Sigov, A. S.

2018-03-01

Steady state leakage currents have been investigated in capacitor structures with ferroelectric solgel films of lead zirconate titanate (PZT) formed on silicon substrates with a lower Pt electrode. It is established that Pt/PZT/Hg structures, regardless of the PZT film thickness, are characterized by the presence of a rectifying contact similar to p-n junction. The steady state leakage current in the forward direction increases with a decrease in the film thickness and is determined by the ferroelectric bulk conductivity.

Experimental evaluation of IGBT junction temperature measurement via peak gate current

DEFF Research Database (Denmark)

Baker, Nick; Munk-Nielsen, Stig; Iannuzzo, Francesco

2015-01-01

Temperature sensitive electrical parameters allow junction temperature measurements on power semiconductors without modification to module packaging. The peak gate current has recently been proposed for IGBT junction temperature measurement and relies on the temperature dependent resistance...... of the gate pad. Consequently, a consideration of chip geometry and location of the gate pad is required before interpreting temperature data from this method. Results are also compared with a traditional electrical temperature measurement method: the voltage drop under low current....

Analyses on the measurement of leakage currents in CdZnTe radiation detectors

International Nuclear Information System (INIS)

Mescher, M.J.; Hoburg, J.F.; Schlesinger, T.E.; James, R.B.

1999-01-01

Models that place design constraints on devices which are used to measure the leakage currents in high-resistivity semiconductor materials are presented. If these design constraints are met, these models can then be used to quantitatively predict the surface sheet resistance of devices which are dominated by surface leakage currents. As a result, a means is provided to directly compare passivation techniques which are developed to decrease surface leakage currents. Furthermore, these models illustrate the necessity for inclusion of relevant geometrical data on sample size and shape and electrode configuration when reporting results of surface passivation techniques. These models specifically examine the case where a dc potential is applied across two electrodes on the surface of a semiconductor substrate which has a surface layer with lower resistivity than the bulk material. The authors describe several of the more common configurations used in analyzing passivation techniques for compounds of Cd 1-x Zn x Te (CZT) used for room-temperature radiation detection

Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS

KAUST Repository

Dadgour, Hamed F.; Hussain, Muhammad Mustafa; Smith, Casey Eben; Banerjee, Kaustav

2010-01-01

Nano-Electro-Mechanical Switches (NEMS) are among the most promising emerging devices due to their near-zero subthreshold-leakage currents. This paper reports device fabrication and modeling, as well as novel logic gate design using "laterally

On Leakage Current Measured at High Cell Voltages in Lithium-Ion Batteries

Energy Technology Data Exchange (ETDEWEB)

Vadivel, Nicole R.; Ha, Seungbum; He, Meinan; Dees, Dennis; Trask, Steve; Polzin, Bryant; Gallagher, Kevin G.

2017-01-01

In this study, parasitic side reactions in lithium-ion batteries were examined experimentally using a potentiostatic hold at high cell voltage. The experimental leakage current measured during the potentiostatic hold was compared to the Tafel expression and showed poor agreement with the expected transfer coefficient values, indicating that a more complicated expression could be needed to accurately capture the physics of this side reaction. Here we show that cross-talk between the electrodes is the primary contribution to the observed leakage current after the relaxation of concentration gradients has ceased. This cross-talk was confirmed with experiments using a lithium-ion conducting glass ceramic (LICGC) separator, which has high conductance only for lithium cations. The cells with LICGC separators showed significantly less leakage current during the potentiostatic hold test compared to cells with standard microporous separators where cross-talk is present. In addition, direct-current pulse power tests show an impedance rise for cells held at high potentials and for cells held at high temperatures, which could be attributed to film formation from the parasitic side reaction. Based on the experimental findings, a phenomenological mechanism is proposed for the parasitic side reaction which accounts for cross-talk and mass transport of the decomposition products across the separator.

Initial leakage current paths in the vertical-type GaN-on-GaN Schottky barrier diodes

Science.gov (United States)

Sang, Liwen; Ren, Bing; Sumiya, Masatomo; Liao, Meiyong; Koide, Yasuo; Tanaka, Atsushi; Cho, Yujin; Harada, Yoshitomo; Nabatame, Toshihide; Sekiguchi, Takashi; Usami, Shigeyoshi; Honda, Yoshio; Amano, Hiroshi

2017-09-01

Electrical characteristics of leakage current paths in vertical-type n-GaN Schottky barrier diodes (SBDs) on free-standing GaN substrates are investigated by using photon emission microscopy (PEM). The PEM mapping shows that the initial failure of the SBD devices at low voltages is due to the leakage current paths from polygonal pits in the GaN epilayers. It is observed that these polygonal pits originate from carbon impurity accumulation to the dislocations with a screw-type component by microstructure analysis. For the SBD without polygonal pits, no initial failure is observed and the first leakage appeals at the edge of electrodes as a result of electric field concentration. The mechanism of leakage at pits is explained in terms of trap assisted tunneling through fitting current-voltage characteristics.

Leakage current-induced effects in the silicon microstrip and gas electron multiplier readout chain and their compensation method

Science.gov (United States)

Zubrzycka, W.; Kasinski, K.

2018-04-01

Leakage current flowing into the charge sensitive amplifier (CSA) is a common issue in many radiation detection systems as it can increase overall system noise, shift a DC baseline or even lead a recording channel to instability. The commonly known leakage current contributor is a detector, however other system components like wires or an input protection circuit may become a serious problem. Compensation of the leakage current resulting from the electrostatic discharge (ESD) protection circuit by properly sizing its components is possible only for a narrow temperature range. Moreover, the leakage current from external sources can be significantly larger. Many applications, especially High Energy Physics (HEP) experiments, require a fast baseline restoration for high input hit rates by applying either a low-value feedback resistor or a high feedback resistance combined with a pulsed reset circuit. Leakage current flowing in the feedback in conjunction with a large feedback resistance supplied with a pulsed reset results in a significant voltage offset between the CSA input and output which can cause problems (e.g. fake hits or instability). This paper shows an issue referred to the leakage current of the ESD protection circuit flowing into the input amplifier. The following analysis and proposed solution is a result of the time and energy readout ASIC project realization for the Compressed Baryonic Matter (CBM) experiment at FAIR (Facility for Antiproton and Ion Research) in Darmstadt, Germany. This chip is purposed to work with microstrip and gaseous detectors, with high average input pulses frequencies (250 kHit/s per channel) and the possibility to process input charge of both polarities. We present measurements of the test structure fabricated in UMC 180 nm technology and propose a solution addressing leakage current related issues. This work combines the leakage current compensation capabilities at the CSA level with high, controllable value of the amplifier

A gate current 1/f noise model for GaN/AlGaN HEMTs

International Nuclear Information System (INIS)

Liu Yu'an; Zhuang Yiqi

2014-01-01

This work presents a theoretical and experimental study on the gate current 1/f noise in AlGaN/GaN HEMTs. Based on the carrier number fluctuation in the two-dimensional electron gas channel of AlGaN/GaN HEMTs, a gate current 1/f noise model containing a trap-assisted tunneling current and a space charge limited current is built. The simulation results are in good agreement with the experiment. Experiments show that, if V g < V x (critical gate voltage of dielectric relaxation), gate current 1/f noise comes from the superimposition of trap-assisted tunneling RTS (random telegraph noise), while V g > V x , gate current 1/f noise comes from not only the trap-assisted tunneling RTS, but also the space charge limited current RTS. This indicates that the gate current 1/f noise of the GaN-based HEMTs device is sensitive to the interaction of defects and the piezoelectric relaxation. It provides a useful characterization tool for deeper information about the defects and their evolution in AlGaN/GaN HEMTs. (semiconductor devices)

Nanoscale leakage current measurements in metal organic chemical vapor deposition crystalline SrTiO3 films

International Nuclear Information System (INIS)

Rozier, Y.; Gautier, B.; Hyvert, G.; Descamps, A.; Plossu, C.; Dubourdieu, C.; Ducroquet, F.

2009-01-01

The properties of SrTiO 3 thin films, grown by liquid injection metal organic chemical vapor deposition on Si/SiO 2 , using a mixture of precursors, have been investigated at the nanoscale using an Atomic Force Microscope in the so-called Conductive Atomic Force Microscopy mode. Maps of the leakage currents with a nanometric resolution have been obtained on films elaborated at different temperatures and stoichiometries in order to discriminate the role of each parameter on the onset of leakage currents in the resulting layers. It appears that the higher the deposition temperature, the higher the leakage currents of the films. The mapping with a nanometric precision allows to show a heterogeneous behaviour of the surface with leaky grains and insulating boundaries. The study of films elaborated at the same temperature with different compositions supports the assumption that the leakage currents on Ti-rich layers are far higher than on Sr-rich layers

GIDL analysis of the process variation effect in gate-all-around nanowire FET

Science.gov (United States)

Kim, Shinkeun; Seo, Youngsoo; Lee, Jangkyu; Kang, Myounggon; Shin, Hyungcheol

2018-02-01

In this paper, the gate-induced drain leakage (GIDL) is analyzed on gate-all-around (GAA) Nanowire FET (NW FET) with ellipse-shaped channel induced by process variation effect (PVE). The fabrication process of nanowire can lead to change the shape of channel cross section from circle to ellipse. The effect of distorted channel shape is investigated and verified by technology computer-aided design (TCAD) simulation in terms of the GIDL current. The simulation results demonstrate that the components of GIDL current are two mechanisms of longitudinal band-to-band tunneling (L-BTBT) at body/drain junction and transverse band-to-band tunneling (T-BTBT) at gate/drain junction. These two mechanisms are investigated on channel radius (rnw) and aspect ratio of ellipse-shape respectively and together.

Image Artifacts in Concurrent Transcranial Magnetic Stimulation (TMS) and fMRI Caused by Leakage Currents: Modeling and Compensation

Science.gov (United States)

Weiskopf, Nikolaus; Josephs, Oliver; Ruff, Christian C; Blankenburg, Felix; Featherstone, Eric; Thomas, Anthony; Bestmann, Sven; Driver, Jon; Deichmann, Ralf

2009-01-01

Purpose To characterize and eliminate a new type of image artifact in concurrent transcranial magnetic stimulation and functional MRI (TMS-fMRI) caused by small leakage currents originating from the high-voltage capacitors in the TMS stimulator system. Materials and Methods The artifacts in echo-planar images (EPI) caused by leakage currents were characterized and quantified in numerical simulations and phantom studies with different phantom-coil geometries. A relay-diode combination was devised and inserted in the TMS circuit that shorts the leakage current. Its effectiveness for artifact reduction was assessed in a phantom scan resembling a realistic TMS-fMRI experiment. Results The leakage-current-induced signal changes exhibited a multipolar spatial pattern and the maxima exceeded 1% at realistic coil-cortex distances. The relay-diode combination effectively reduced the artifact to a negligible level. Conclusion The leakage-current artifacts potentially obscure effects of interest or lead to false-positives. Since the artifact depends on the experimental setup and design (eg, amplitude of the leakage current, coil orientation, paradigm, EPI parameters), we recommend its assessment for each experiment. The relay-diode combination can eliminate the artifacts if necessary. J. Magn. Reson. Imaging 2009;29:1211–1217. © 2009 Wiley-Liss, Inc. PMID:19388099

Study on the low leakage current of an MIS structure fabricated by ICP-CVD

Energy Technology Data Exchange (ETDEWEB)

Tsai, S-Y; Hon, M-H [Department of Materials Science and Engineering, National Cheng Kung University, 1, Ta-Hsueh Road, Tainan, 701 Taiwan (China); Lu, Y-M, E-mail: ymlumit@yahoo.com.tw

2008-03-15

As the dimensions of electric devices continue to shrink, it is becoming increasingly important to understand how to obtain good quality gate oxide film materials wilth higher carrier mobility, lower leakage current and greater reliability. All of them have become major concerns in the fabrication of thin film oxide transistors. A novel film deposition method called Inductively Coupled Plasma-Chemical Vapor Deposition (ICP-CVD) has received attraction in the semiconductor industry, because it can be capable of generating high density plasmas at extremely low temperature, resulting in less ion bombardment of the material surface. In this work, we present the results of crystallized silicon dioxide films deposited by inductively coupled plasma chemical vapor deposition technique at an extremely low temperature of 90 deg. C. The value of the refractive index of the crystallized ICP-CVD SiO{sub 2} film depends on the r.f. power of the ICP system, and approximates to be 1.46. This value is comparable to that of SiO{sub 2} films prepared by thermal oxidation. As the r.f. power of ICP applied more than 1250 Watts, still only the (111) diffraction peak is observed by XRD, which implies a very strong preferred orientation or single crystal structure. Too low or too high r.f. power both produces amorphous SiO{sub 2} films. From the I-V curve, the MIS device with a SiO{sub 2} dielectric film has a lower leakage current density of 6.8x10{sup -8}A/cm{sup 2} at 1V as the film prepared at 1750 watts. The highest breakdown field in this study is 15.8 MV/cm. From the FTIR analysis, it was found that more hydrogen atoms incorporate into films and form Si-OH bonds as the r.f. power increases. The existence of Si-OH bonds leads to a poor reliability of the MIS device.

Fabrication and characterization of V-gate AlGaN/GaN high-electron-mobility transistors

International Nuclear Information System (INIS)

Zhang Kai; Cao Meng-Yi; Chen Yong-He; Yang Li-Yuan; Wang Chong; Ma Xiao-Hua; Hao Yue

2013-01-01

V-gate GaN high-electron-mobility transistors (HEMTs) are fabricated and investigated systematically. A V-shaped recess geometry is obtained using an improved Si 3 N 4 recess etching technology. Compared with standard HEMTs, the fabricated V-gate HEMTs exhibit a 17% higher peak extrinsic transconductance due to a narrowed gate foot. Moreover, both the gate leakage and current dispersion are dramatically suppressed simultaneously, although a slight degradation of frequency response is observed. Based on a two-dimensional electric field simulation using Silvaco “ATLAS” for both standard HEMTs and V-gate HEMTs, the relaxation in peak electric field at the gate edge is identified as the predominant factor leading to the superior performance of V-gate HEMTs. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Space Vector Modulation Technique to Reduce Leakage Current of a Transformerless Three-Phase Four-Leg Photovoltaic System

Directory of Open Access Journals (Sweden)

F. Hasanzad

2017-06-01

Full Text Available Photovoltaic systems integrated to the grid have received considerable attention around the world. They can be connected to the electrical grid via galvanic isolation (transformer or without it (transformerless. Despite making galvanic isolation, low frequency transformer increases size, cost and losses. On the other hand, transformerless PV systems increase the leakage current (common-mode current, (CMC through the parasitic capacitors of the PV array. Inverter topology and switching technique are the most important parameters the leakage current depends on. As there is no need to extra hardware for switching scheme modification, it's an economical method for reducing leakage current. This paper evaluates the effect of different space vector modulation techniques on leakage current for a two-level three-phase four-leg inverter used in PV system. It proposes an efficient space vector modulation method which decreases the leakage current to below the quantity specified in VDE-0126-1-1 standard. furthermore, some other characteristics of the space vector modulation schemes that have not been significantly discussed for four-leg inverter, are considered, such as, modulation index, switching actions per period, common-mode voltage (CMV, and total harmonic distortion (THD. An extend software simulation using MATLAB/Simulink is performed to verify the effectiveness of the modulation technique.

Detection of defect states responsible for leakage current in ultrathin tantalum pentoxide (Ta2O5) films by zero-bias thermally stimulated current spectroscopy

International Nuclear Information System (INIS)

Lau, W.S.; Zhong, L.; Lee, A.; See, C.H.; Han, T.; Sandler, N.P.; Chong, T.C.

1997-01-01

Defect states responsible for leakage current in ultrathin (physical thickness 2 O 5 ) films were measured with a novel zero-bias thermally stimulated current technique. It was found that defect states A, whose activation energy was estimated to be about 0.2 eV, can be more efficiently suppressed by using N 2 O rapid thermal annealing (RTA) instead of using O 2 RTA for postdeposition annealing. The leakage current was also smaller for samples with N 2 O RTA than those with O 2 RTA for postdeposition annealing. Hence, defect states A are quite likely to be important in causing leakage current. copyright 1997 American Institute of Physics

Bimodal gate-dielectric deposition for improved performance of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

International Nuclear Information System (INIS)

Pang Liang; Kim, Kyekyoon

2012-01-01

A bimodal deposition scheme combining radiofrequency magnetron sputtering and plasma enhanced chemical vapour deposition (PECVD) is proposed as a means for improving the performance of GaN-based metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs). High-density sputtered-SiO 2 is utilized to reduce the gate leakage current and enhance the breakdown voltage while low-density PECVD-SiO 2 is employed to buffer the sputtering damage and further increase the drain current by engineering the stress-induced-polarization. Thus-fabricated MOSHEMT exhibited a low leakage current of 4.21 × 10 -9 A mm -1 and high breakdown voltage of 634 V for a gate-drain distance of 6 µm, demonstrating the promise of bimodal-SiO 2 deposition scheme for the development of GaN-based MOSHEMTs for high-power application. (paper)

Design of Higher-k and More Stable Rare Earth Oxides as Gate Dielectrics for Advanced CMOS Devices

Directory of Open Access Journals (Sweden)

Yi Zhao

2012-08-01

Full Text Available High permittivity (k gate dielectric films are widely studied to substitute SiO₂ as gate oxides to suppress the unacceptable gate leakage current when the traditional SiO₂ gate oxide becomes ultrathin. For high-k gate oxides, several material properties are dominantly important. The first one, undoubtedly, is permittivity. It has been well studied by many groups in terms of how to obtain a higher permittivity for popular high-k oxides, like HfO₂ and La₂O₃. The second one is crystallization behavior. Although it’s still under the debate whether an amorphous film is definitely better than ploy-crystallized oxide film as a gate oxide upon considering the crystal boundaries induced leakage current, the crystallization behavior should be well understood for a high-k gate oxide because it could also, to some degree, determine the permittivity of the high-k oxide. Finally, some high-k gate oxides, especially rare earth oxides (like La₂O₃, are not stable in air and very hygroscopic, forming hydroxide. This topic has been well investigated in over the years and significant progresses have been achieved. In this paper, I will intensively review the most recent progresses of the experimental and theoretical studies for preparing higher-k and more stable, in terms of hygroscopic tolerance and crystallization behavior, Hf- and La-based ternary high-k gate oxides.

Study of leakage current behaviour on artificially polluted surface of ceramic insulator

International Nuclear Information System (INIS)

Subba Reddy, B.; Nagabhushana, G.R.

2003-01-01

This paper presents the results of the study concerning to the leakage current behaviour on artificially polluted ceramic insulator surface. From the present study it was observed that there is a reasonably well-defined inception of current i.e. scintillations at a finite voltage. The corresponding voltages for extinction of the current are in the range of 0.8 kV to 2.1 kV. Obviously, the dry band formed in the immediate vicinity of the pin prevents smooth current flow as the voltage rises from zero. Only when the voltage is adequate it causes a flashover of the dray band and current starts flowing. As is common in similar current extinction phenomena, here also, the extinction voltages are significantly lower than the inception voltages. Further, the voltage-current curves invariably show hysteresis-the leakage currents are lower in the reducing portion of the voltage. This is obviously due to drying of the wet pollutant layer thereby increasing its resistance. It is believed that this is the first time that such a direct quantitative evidence of drying in individual half cycles is experimentally visualized

Analysis of chemical bond states and electrical properties of stacked AlON/HfO{sub 2} gate oxides formed by using a layer-by-layer technique

Energy Technology Data Exchange (ETDEWEB)

Choi, Wonjoon; Lee, Jonghyun; Yang, Jungyup; Kim, Chaeok; Hong, Jinpyo; Nahm, Tschanguh; Byun, Byungsub; Kim, Moseok [Hanyang University, Seoul (Korea, Republic of)

2006-06-15

Stacked AlON/HfO{sub 2} thin films for gate oxides in metal-oxide-semiconductor devices are successfully prepared on Si substrates by utilizing a layer-by-layer technique integrated with an off-axis RF remote plasma sputtering process at room temperature. This off-axis structure is designed to improve the uniformity and the quality of gate oxide films. Also, a layer-by-layer technique is used to control the interface layer between the gate oxide and the Si substrate. The electrical properties of our stacked films are characterized by using capacitance versus voltage and leakage current versus voltage measurements. The stacked AlON/HfO{sub 2} gate oxide exhibits a low leakage current of about 10{sup -6} A/cm{sup 2} and a high dielectric constant value of 14.26 by effectively suppressing the interface layer between gate oxide and Si substrate. In addition, the chemical bond states and the optimum thickness of each AlON and HfO{sub 2} thin film are analyzed using X-ray photoemission spectroscopy and transmission electron microscopy measurement.

Air-gating and chemical-gating in transistors and sensing devices made from hollow TiO2 semiconductor nanotubes

Science.gov (United States)

Alivov, Yahya; Funke, Hans; Nagpal, Prashant

2015-07-01

Rapid miniaturization of electronic devices down to the nanoscale, according to Moore’s law, has led to some undesirable effects like high leakage current in transistors, which can offset additional benefits from scaling down. Development of three-dimensional transistors, by spatial extension in the third dimension, has allowed higher contact area with a gate electrode and better control over conductivity in the semiconductor channel. However, these devices do not utilize the large surface area and interfaces for new electronic functionality. Here, we demonstrate air gating and chemical gating in hollow semiconductor nanotube devices and highlight the potential for development of novel transistors that can be modulated using channel bias, gate voltage, chemical composition, and concentration. Using chemical gating, we reversibly altered the conductivity of nanoscaled semiconductor nanotubes (10-500 nm TiO2 nanotubes) by six orders of magnitude, with a tunable rectification factor (ON/OFF ratio) ranging from 1-106. While demonstrated air- and chemical-gating speeds were slow here (˜seconds) due to the mechanical-evacuation rate and size of our chamber, the small nanoscale volume of these hollow semiconductors can enable much higher switching speeds, limited by the rate of adsorption/desorption of molecules at semiconductor interfaces. These chemical-gating effects are completely reversible, additive between different chemical compositions, and can enable semiconductor nanoelectronic devices for ‘chemical transistors’, ‘chemical diodes’, and very high-efficiency sensing applications.

Gate-Recessed AlGaN/GaN MOSHEMTs with the Maximum Oscillation Frequency Exceeding 120 GHz on Sapphire Substrates

International Nuclear Information System (INIS)

Kong Xin; Wei Ke; Liu Guo-Guo; Liu Xin-Yu

2012-01-01

Gate-recessed AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) on sapphire substrates are fabricated. The devices with a gate length of 160 nm and a gate periphery of 2 × 75 μm exhibit two orders of magnitude reduction in gate leakage current and enhanced off-state breakdown characteristics, compared with conventional HEMTs. Furthermore, the extrinsic transconductance of an MOSHEMT is 237.2 mS/mm, only 7% lower than that of Schottky-gate HEMT. An extrinsic current gain cutoff frequency f T of 65 GHz and a maximum oscillation frequency f max of 123 GHz are deduced from rf small signal measurements. The high f max demonstrates that gate-recessed MOSHEMTs are of great potential in millimeter wave frequencies. (cross-disciplinary physics and related areas of science and technology)

A transformerless single-phase symmetrical Z-source HERIC inverter with reduced leakage currents for PV systems

DEFF Research Database (Denmark)

Li, Kerui; Shen, Yanfeng; Yang, Yongheng

2018-01-01

and thus low leakage currents in PV applications. The symmetric Z-source HERIC inverter requires two extra active switches. Nevertheless, the operation frequency of the two switches is the line frequency, leading to negligible losses. More importantly, the performance in terms of low leakage currents...... and harmonics is improved. Experimental tests are performed to validate the analysis and performance of the proposed system....

Gate-tunable current partition in graphene-based topological zero lines

Science.gov (United States)

Wang, Ke; Ren, Yafei; Deng, Xinzhou; Yang, Shengyuan A.; Jung, Jeil; Qiao, Zhenhua

2017-06-01

We demonstrate new mechanisms for gate-tunable current partition at topological zero-line intersections in a graphene-based current splitter. Based on numerical calculations of the nonequilibrium Green's functions and Landauer-Büttiker formula, we show that the presence of a perpendicular magnetic field on the order of a few Teslas allows for carrier sign dependent current routing. In the zero-field limit the control on current routing and partition can be achieved within a range of 10-90 % of the total incoming current by tuning the carrier density at tilted intersections or by modifying the relative magnitude of the bulk band gaps via gate voltage. We discuss the implications of our findings in the design of topological zero-line networks where finite orbital magnetic moments are expected when the current partition is asymmetric.

High-κ gate dielectrics: Current status and materials properties considerations

Science.gov (United States)

Wilk, G. D.; Wallace, R. M.; Anthony, J. M.

2001-05-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward successful integration into the expected processing conditions for future CMOS technologies, especially due to their tendency to form at interfaces with Si (e.g. silicates). These pseudobinary systems also thereby enable the use of other high-κ materials by serving as an interfacial high-κ layer. While work is ongoing, much research is still required, as it is clear that any material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Comparison of recessed gate-head structures on normally-off AlGaN/GaN high-electron-mobility transistor performance.

Science.gov (United States)

Khan, Mansoor Ali; Heo, Jun-Woo; Kim, Hyun-Seok; Park, Hyun-Chang

2014-11-01

In this work, different gate-head structures have been compared in the context of AlGaN/GaN-based high-electron-mobility transistors (HEMTs). Field-plate (FP) technology self-aligned to the gate electrode leads to various gate-head structures, most likely gamma (γF)-gate, camel (see symbol)-gate, and mushroom-shaped (T)-gate. In-depth comparison of recessed gate-head structures demonstrated that key performance metrics such as transconductance, output current, and breakdown voltage are better with the T-gate head structure. The recessed T-gate with its one arm toward the source side not only reduces the source-access resistance (R(g) +R(gs)), but also minimizes the source-side dispersion and current leakage, resulting in high transconductance (G(m)) and output current (I(DS)). At the same time, the other arm toward the drain-side reduces the drain-side dispersion and tends to distribute electric field peaks uniformly, resulting in high breakdown voltage (V(BR)). DC and RF analysis showed that the recessed T-gate FP-HEMT is a suitable candidate not only for high-frequency operation, but also for high-power applications.

Effect of the critical current density and the junction size on the leakage current of Nb/Al-AlOx/Nb superconducting tunnel junctions for radiation detection

International Nuclear Information System (INIS)

Joosse, K.; Nakagawa, Hiroshi; Akoh, Hiroshi; Takada, Susumu; Maehata, Keisuke; Ishibashi, Kenji.

1996-01-01

Nb/Al-AlO x /Nb superconducting tunnel junctions (STJ's) designed for X-ray detection have been fabricated. The behavior of the low-temperature subgap leakage current, which severely limits the energy resolution obtained in such devices, is investigated. From trends in the dependence of the leakage currents on the critical current density and the size of the STJ, as well as from the low-temperature current-voltage characteristics, and an analysis of the base electrode surface morphology, it is concluded that physical defects in the barrier region are the most probable cause of the leakage currents. Suggestions are given for optimization of the device processing. (author)

Leakage current transport mechanisms of La 0.67 Sr 0.33 MnO 3 ...

Indian Academy of Sciences (India)

limited current mechanism under forward bias while thermionic emission model under reverse bias. Analysis indicates that a modulating Schottky barrier exists at the LSMO/BTO interface, which dominates the leakage current transport properties ...

Capacitance-voltage characterization of fully silicided gated MOS capacitor

International Nuclear Information System (INIS)

Wang Baomin; Ru Guoping; Jiang Yulong; Qu Xinping; Li Bingzong; Liu Ran

2009-01-01

This paper investigates the capacitance-voltage (C-V) measurement on fully silicided (FUSI) gated metal-oxide-semiconductor (MOS) capacitors and the applicability of MOS capacitor models. When the oxide leakage current of an MOS capacitor is large, two-element parallel or series model cannot be used to obtain its real C-V characteristic. A three-element model simultaneously consisting of parallel conductance and series resistance or a four-element model with further consideration of a series inductance should be used. We employed the three-element and the four-element models with the help of two-frequency technique to measure the Ni FUSI gated MOS capacitors. The results indicate that the capacitance of the MOS capacitors extracted by the three-element model still shows some frequency dispersion, while that extracted by the four-element model is close to the real capacitance, showing little frequency dispersion. The obtained capacitance can be used to calculate the dielectric thickness with quantum effect correction by NCSU C-V program. We also investigated the influence of MOS capacitor's area on the measurement accuracy. The results indicate that the decrease of capacitor area can reduce the dissipation factor and improve the measurement accuracy. As a result, the frequency dispersion of the measured capacitance is significantly reduced, and real C-V characteristic can be obtained directly by the series model. In addition, this paper investigates the quasi-static C-V measurement and the photonic high-frequency C-V measurement on Ni FUSI metal gated MOS capacitor with a thin leaky oxide. The results indicate that the large tunneling current through the gate oxide significantly perturbs the accurate measurement of the displacement current, which is essential for the quasi-static C-V measurement. On the other hand, the photonic high-frequency C-V measurement can bypass the leakage problem, and get reliable low-frequency C-V characteristic, which can be used to

Correlation between dislocations and leakage current of p-n diodes on a free-standing GaN substrate

Science.gov (United States)

Usami, Shigeyoshi; Ando, Yuto; Tanaka, Atsushi; Nagamatsu, Kentaro; Deki, Manato; Kushimoto, Maki; Nitta, Shugo; Honda, Yoshio; Amano, Hiroshi; Sugawara, Yoshihiro; Yao, Yong-Zhao; Ishikawa, Yukari

2018-04-01

Dislocations that cause a reverse leakage current in vertical p-n diodes on a GaN free-standing substrate were investigated. Under a high reverse bias, dot-like leakage spots were observed using an emission microscope. Subsequent cathodoluminescence (CL) observations revealed that the leakage spots coincided with part of the CL dark spots, indicating that some types of dislocation cause reverse leakage. When etch pits were formed on the dislocations by KOH etching, three sizes of etch pits were obtained (large, medium, and small). Among these etch pits, only the medium pits coincided with leakage spots. Additionally, transmission electron microscopy observations revealed that pure screw dislocations are present under the leakage spots. The results revealed that 1c pure screw dislocations are related to the reverse leakage in vertical p-n diodes.

Performance of an X-ray spectroscopic system based on a double-gate double-feedback charge preamplifier

CERN Document Server

Fazzi, A

2000-01-01

The performance of a near room temperature X-ray spectroscopic system is reported. The system is based on a charge preamplifier with the first transistor having two separated gates. The preamplifier operates in a continuous reset mode without any physical resistor connected to the input node. The leakage current and the current due to the rate of X-rays is neutralized by an average current of holes, flowing under the control of an additional feedback, from the bottom to the top gate. The preamplifier is followed by a simple circuit which exactly cancels the long tail of the impulse response of a pure double-gate preamplifier. The compensation of this tail, due to the very principle of the preamplifier's continuous reset through the double-gate mechanism, improves substantially the high-rate performance of the system. The preamplifier based on a commercially available double-gate front JFET MX-40 (MOXTEK) coupled to a silicon drift detector produced at BNL achieved ENC of 13 electrons at -30 deg. C. The analys...

Power crowbar system coupled by a current transformer with very low leakage inductance

International Nuclear Information System (INIS)

Kitagawa, S.; Hirano, K.I.

1976-01-01

A reliable, efficient power crowbar system has been developed for fast pinch experiments. In order to reduce the effective impedance of series capacitor system, a current transformer with extremely low leakage inductance has been designed and used. Primary and secondary windings of the transformer are alternately arranged as closely as possible. As a result, the leakage inductance is reduced to 2 nH. It is demonstrated that a current of 390 kA, the rise time of which is 4.5 μsec, is sustained for 100 μsec. Much larger system is being built, which maintains a current of 1 MA over 1 msec. The life of crowbar gap switches is prolonged by the aid of a mechanically-driven metal-to-metal contact switch. Another crowbar switch system with a high coulomb rating is under consideration, in which a gap switch is used together with a saturable reactor and a current transformer

Use of water vapor for suppressing the growth of unstable low-κ interlayer in HfTiO gate-dielectric Ge metal-oxide-semiconductor capacitors with sub-nanometer capacitance equivalent thickness

International Nuclear Information System (INIS)

Xu, J.P.; Zou, X.; Lai, P.T.; Li, C.X.; Chan, C.L.

2009-01-01

Annealing of high-permittivity HfTiO gate dielectric on Ge substrate in different gases (N 2 , NH 3 , NO and N 2 O) with or without water vapor is investigated. Analysis by transmission electron microscopy indicates that the four wet anneals can greatly suppress the growth of a GeO x interlayer at the dielectric/Ge interface, and thus decrease interface states, oxide charges and gate leakage current. Moreover, compared with the wet N 2 anneal, the wet NH 3 , NO and N 2 O anneals decrease the equivalent permittivity of the gate dielectric due to the growth of a GeO x N y interlayer. Among the eight anneals, the wet N 2 anneal produces the best dielectric performance with an equivalent relative permittivity of 35, capacitance equivalent thickness of 0.81 nm, interface-state density of 6.4 x 10 11 eV -1 cm -2 and gate leakage current of 2.7 x 10 -4 A/cm 2 at V g = 1 V

Improved performance of nanoscale junctionless tunnel field-effect transistor based on gate engineering approach

Science.gov (United States)

Molaei Imen Abadi, Rouzbeh; Sedigh Ziabari, Seyed Ali

2016-11-01

In this paper, a first qualitative study on the performance characteristics of dual-work function gate junctionless TFET (DWG-JLTFET) on the basis of energy band profile modulation is investigated. A dual-work function gate technique is used in a JLTFET in order to create a downward band bending on the source side similar to PNPN structure. Compared with the single-work function gate junctionless TFET (SWG-JLTFET), the numerical simulation results demonstrated that the DWG-JLTFET simultaneously optimizes the ON-state current, the OFF-state leakage current, and the threshold voltage and also improves average subthreshold slope. It is illustrated that if appropriate work functions are selected for the gate materials on the source side and the drain side, the JLTFET exhibits a considerably improved performance. Furthermore, the optimization design of the tunnel gate length ( L Tun) for the proposed DWG-JLTFET is studied. All the simulations are done in Silvaco TCAD for a channel length of 20 nm using the nonlocal band-to-band tunneling (BTBT) model.

Novel technique of source and drain engineering for dual-material double-gate (DMDG) SOI MOSFETS

Science.gov (United States)

Yadav, Himanshu; Malviya, Abhishek Kumar; Chauhan, R. K.

2018-04-01

The dual-metal dual-gate (DMDG) SOI has been used with Dual Sided Source and Drain Engineered 50nm SOI MOSFET with various high-k gate oxide. It has been scrutinized in this work to enhance its electrical performance. The proposed structure is designed by creating Dual Sided Source and Drain Modification and its characteristics are evaluated on ATLAS device simulator. The consequence of this dual sided assorted doping on source and drain side of the DMDG transistor has better leakage current immunity and heightened ION current with higher ION to IOFF Ratio. Which thereby vesting the proposed device appropriate for low power digital applications.

Investigation of defect-induced abnormal body current in fin field-effect-transistors

International Nuclear Information System (INIS)

Liu, Kuan-Ju; Tsai, Jyun-Yu; Lu, Ying-Hsin; Liu, Xi-Wen; Chang, Ting-Chang; Chen, Ching-En; Yang, Ren-Ya; Cheng, Osbert; Huang, Cheng-Tung

2015-01-01

This letter investigates the mechanism of abnormal body current at the linear region in n-channel high-k/metal gate stack fin field effect transistors. Unlike body current, which is generated by impact ionization at high drain voltages, abnormal body current was found to increase with decreasing drain voltages. Notably, the unusual body leakage only occurs in three-dimensional structure devices. Based on measurements under different operation conditions, the abnormal body current can be attributed to fin surface defect-induced leakage current, and the mechanism is electron tunneling to the fin via the defects, resulting in holes left at the body terminal

A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects

Science.gov (United States)

Ramezani, Zeinab; Orouji, Ali A.

2018-03-01

In this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.

Low Noise Bias Current/Voltage References Based on Floating-Gate MOS Transistors

DEFF Research Database (Denmark)

Igor, Mucha

1997-01-01

The exploitation of floating-gate MOS transistors as reference current and voltage sources is investigated. Test structures of common source and common drain floating-gate devices have been implemented in a commercially available 0.8 micron double-poly CMOS process. The measurements performed...

Modeling of a quantized current and gate field-effect in gated three-terminal Cu2-αS electrochemical memristors

Directory of Open Access Journals (Sweden)

Y. Zhang

2015-02-01

Full Text Available Memristors exhibit very sharp off-to-on transitions with a large on/off resistance ratio. These remarkable characteristics coupled with their long retention time and very simple device geometry make them nearly ideal for three-terminal devices where the gate voltage can change their on/off voltages and/or simply turn them off, eliminating the need for bipolar operations. In this paper, we propose a cation migration-based computational model to explain the quantized current conduction and the gate field-effect in Cu2-αS memristors. Having tree-shaped conductive filaments inside a memristor is the reason for the quantized current conduction effect. Applying a gate voltage causes a deformation of the conductive filaments and thus controls the SET and the RESET process of the device.

Process effects on leakage current of Si-PIN neutron detectors with porous microstructure

Energy Technology Data Exchange (ETDEWEB)

Yu, Baoning; Zhao, Kangkang; Yang, Taotao [Beijing University of Technology, Chaoyang District, Pingleyuan 100, 100124 Beijing (China); Suzhou Institute of Nano-tech and Nano-bionics, Chinese Academy of Sciences, Ruoshui Road 398, 215123 Suzhou (China); Jiang, Yong; Fan, Xiaoqiang [Institute of Nuclear Physics and Chemistry, CAEP, Mianshan Road 64, 621900 Mianyang (China); Lu, Min [Suzhou Institute of Nano-tech and Nano-bionics, Chinese Academy of Sciences, Ruoshui Road 398, 215123 Suzhou (China); Han, Jun [Beijing University of Technology, Chaoyang District, Pingleyuan 100, 100124 Beijing (China)

2017-06-15

Using the technique of Microfabrication, such as deep silicon dry etching, lithography, etc. Si-PIN neutron detectors with porous microstructure have been successfully fabricated. In order to lower the leakage current, the key fabrication processes, including the Al windows opening, deep silicon etching and the porous side wall smoothing, have been optimized. The cross-section morphology and current-voltage characteristics have been measured to evaluate the microfabrication processes. With the optimized conditions presented by the measurements, a neutron detector with a leakage current density of 2.67 μA cm{sup -2} at a bias of -20 V is obtained. A preliminary neutron irradiation test with {sup 252}Cf neutron source has also been carried out. The neutron irradiation test shows that the neutron detection efficiency of the microstructured neutron detectors is almost 3.6 times higher than that of the planar ones. (copyright 2017 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Top-gated chemical vapor deposition grown graphene transistors with current saturation.

Science.gov (United States)

Bai, Jingwei; Liao, Lei; Zhou, Hailong; Cheng, Rui; Liu, Lixin; Huang, Yu; Duan, Xiangfeng

2011-06-08

Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.

Ionic screening effect on low-frequency drain current fluctuations in liquid-gated nanowire FETs

International Nuclear Information System (INIS)

Lu, Ming-Pei; Vire, Eric; Montès, Laurent

2015-01-01

The ionic screening effect plays an important role in determining the fundamental surface properties within liquid–semiconductor interfaces. In this study, we investigated the characteristics of low-frequency drain current noise in liquid-gated nanowire (NW) field effect transistors (FETs) to obtain physical insight into the effect of ionic screening on low-frequency current fluctuation. When the NW FET was operated close to the gate voltage corresponding to the maximum transconductance, the magnitude of the low-frequency noise for the NW exposed to a low-ionic-strength buffer (0.001 M) was approximately 70% greater than that when exposed to a high-ionic-strength buffer (0.1 M). We propose a noise model, considering the charge coupling efficiency associated with the screening competition between the electrolyte buffer and the NW, to describe the ionic screening effect on the low-frequency drain current noise in liquid-gated NW FET systems. This report not only provides a physical understanding of the ionic screening effect behind the low-frequency current noise in liquid-gated FETs but also offers useful information for developing the technology of NW FETs with liquid-gated architectures for application in bioelectronics, nanosensors, and hybrid nanoelectronics. (paper)

Combining a multi deposition multi annealing technique with a scavenging (Ti) to improve the high-k/metal gate stack performance for a gate-last process

International Nuclear Information System (INIS)

Zhang ShuXiang; Yang Hong; Tang Bo; Tang Zhaoyun; Xu Yefeng; Xu Jing; Yan Jiang

2014-01-01

ALD HfO 2 films fabricated by a novel multi deposition multi annealing (MDMA) technique are investigated, we have included samples both with and without a Ti scavenging layer. As compared to the reference gate stack treated by conventional one-time deposition and annealing (D and A), devices receiving MDMA show a significant reduction in leakage current. Meanwhile, EOT growth is effectively controlled by the Ti scavenging layer. This improvement strongly correlates with the cycle number of D and A (while keeping the total annealing time and total dielectrics thickness the same). Transmission electron microscope and energy-dispersive X-ray spectroscopy analysis suggests that oxygen incorporation into both the high-k film and the interfacial layer is likely to be responsible for the improvement of the device. This novel MDMA is promising for the development of gate stack technology in a gate last integration scheme. (semiconductor technology)

Demonstration of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with silicon-oxy-nitride as the gate insulator

International Nuclear Information System (INIS)

Balachander, K.; Arulkumaran, S.; Egawa, T.; Sano, Y.; Baskar, K.

2005-01-01

AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs) were fabricated with plasma enhanced chemical vapor deposited silicon oxy-nitride (SiON) as an insulating layer. The compositions of SiON thin films were confirmed using X-ray photoelectron spectroscopy. The fabricated MOSHEMTs exhibited a very high saturation current density of 1.1 A/mm coupled with high positive operational gate voltage up to +7 V. The MOSHEMTs also exhibited four orders of low gate leakage current and high forward-on voltage when compared with the conventional HEMTs. The drain current collapse using gate pulse measurements showed only a negligible difference in the saturation current density revealing the drastic improvement in passivation of the surface states due to the high quality of dielectric thin films deposited. Thus, based on the improved direct-current operation, SiON can be considered to be a potential gate oxide comparable with other dielectric insulators

Anomalous degradation behaviors under illuminated gate bias stress in a-Si:H thin film transistor

International Nuclear Information System (INIS)

Tsai, Ming-Yen; Chang, Ting-Chang; Chu, Ann-Kuo; Hsieh, Tien-Yu; Lin, Kun-Yao; Wu, Yi-Chun; Huang, Shih-Feng; Chiang, Cheng-Lung; Chen, Po-Lin; Lai, Tzu-Chieh; Lo, Chang-Cheng; Lien, Alan

2014-01-01

This study investigates the impact of gate bias stress with and without light illumination in a-Si:H thin film transistors. It has been observed that the I–V curve shifts toward the positive direction after negative and positive gate bias stress due to interface state creation at the gate dielectric. However, this study found that threshold voltages shift negatively and that the transconductance curve maxima are anomalously degraded under illuminated positive gate bias stress. In addition, threshold voltages shift positively under illuminated negative gate bias stress. These degradation behaviors can be ascribed to charge trapping in the passivation layer dominating degradation instability and are verified by a double gate a-Si:H device. - Highlights: • There is abnormal V T shift induced by illuminated gate bias stress in a-Si:H thin film transistors. • Electron–hole pair is generated via trap-assisted photoexcitation. • Abnormal transconductance hump is induced by the leakage current from back channel. • Charge trapping in the passivation layer is likely due to the fact that a constant voltage has been applied to the top gate

Electric current modulation by gate frequency in a quantum ring nanotransistor

International Nuclear Information System (INIS)

Konopka, M.; Bokes, P.

2013-01-01

We presented a computational study of a dynamical gate effect applied to a tight-binding model of a ring-shaped quantum-interference nanotransistor. Compared to our former analysis, we used a model of the gate that not only controls on-site energies of the atoms but can also transfer electrons to or from the device. We have found that the electric current is modulated by the gate frequency also in this more general model. The simulations have been performed using our home-developed generalised stroboscopic wave packet approach which is very suitable for open systems and time-dependent effects. (authors)

Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance

Science.gov (United States)

Yadav, Dharmendra Singh; Verma, Abhishek; Sharma, Dheeraj; Tirkey, Sukeshni; Raad, Bhagwan Ram

2017-11-01

Tunnel-field-effect-transistor (TFET) has emerged as one of the most prominent devices to replace conventional MOSFET due to its ability to provide sub-threshold slope below 60 mV/decade (SS ≤ 60 mV/decade) and low leakage current. Despite this, TFETs suffer from ambipolar behavior, lower ON-state current, and poor RF performance. To address these issues, we have introduced drain and gate work function engineering with hetero gate dielectric for the first time in charge plasma based doping-less TFET (DL TFET). In this, the usage of dual work functionality over the drain region significantly reduces the ambipolar behavior of the device by varying the energy barrier at drain/channel interface. Whereas, the presence of dual work function at the gate terminal increases the ON-state current (ION). The combined effect of dual work function at the gate and drain electrode results in the increment of ON-state current (ION) and decrement of ambipolar conduction (Iambi) respectively. Furthermore, the incorporation of hetero gate dielectric along with dual work functionality at the drain and gate electrode provides an overall improvement in the performance of the device in terms of reduction in ambipolarity, threshold voltage and sub-threshold slope along with improved ON-state current and high frequency figures of merit.

Detailed simulation study of a dual material gate carbon nanotube field-effect transistor

Science.gov (United States)

Orouji, Ali A.; Arefinia, Zahra

2009-02-01

For the first time, a new type of carbon nanotube field-effect transistor (CNTFET), the dual material gate (DMG)-CNTFET, is proposed and simulated using quantum simulation that is based on self-consistent solution between two-dimensional Poisson equation and Schrödinger equation with open boundary conditions, within the nonequilibrium Green's function (NEGF) framework. The proposed structure is similar to that of the conventional coaxial CNTFET with the exception that the gate of the DMG-CNTFET consists of two laterally contacting metals with different work functions. Simulation results show DMG-CNTFET significantly decreases leakage current, drain conductance and subthreshold swing, and increases on-off current ratio and voltage gain as compared to conventional CNTFET. We demonstrate that the potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed short-channel effects like the drain-induced barrier lowering (DIBL) and hot-carrier effect.

Influence of process parameters on threshold voltage and leakage current in 18nm NMOS device

Science.gov (United States)

Atan, Norani Binti; Ahmad, Ibrahim Bin; Majlis, Burhanuddin Bin Yeop; Fauzi, Izzati Binti Ahmad

2015-04-01

The process parameters are very crucial factor in the development of transistors. There are many process parameters that influenced in the development of the transistors. In this research, we investigate the effects of the process parameters variation on response characteristics such as threshold voltage (VTH) and sub-threshold leakage current (IOFF) in 18nm NMOS device. The technique to identify semiconductor process parameters whose variability would impact most on the device characteristic is realized through the process by using Taguchi robust design method. This paper presents the process parameters that influenced in threshold voltage (VTH) and sub-threshold leakage current (IOFF) which includes the Halo Implantation, Compensation Implantation, Adjustment Threshold voltage Implantation and Source/Drain Implantation. The design, fabrication and characterization of 18nm HfO2/TiSi2 NMOS device is simulated and performed via a tool called Virtual Wafer Fabrication (VWF) Silvaco TCAD Tool known as ATHENA and ATLAS simulators. These two simulators were combined with Taguchi L9 Orthogonal method to aid in the design and the optimization of the process parameters to achieve the optimum average of threshold voltage (VTH) and sub-threshold leakage current, (IOFF) in 18nm device. Results from this research were obtained; where Halo Implantation dose was identified as one of the process parameter that has the strongest effect on the response characteristics. Whereby the Compensation Implantation dose was identified as an adjustment factor to get the nominal values of threshold voltage VTH, and sub-threshold leakage current, IOFF for 18nm NMOS devices equal to 0.302849 volts and 1.9123×10-16 A/μm respectively. The design values are referred to ITRS 2011 prediction.

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET.

Science.gov (United States)

Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Wang, Qianqiong

2017-09-06

The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure has the superior performance-higher retention time (RT) and weak temperature dependence. But the performance of TFET DRAM cell is sensitive to programming condition. In this paper, the guideline of programming optimization is discussed in detail by using simulation tool-Silvaco Atlas. Both the writing and reading operations of DG-TFET DRAM depend on the band-to-band tunneling (BTBT). During the writing operation, the holes coming from BTBT governed by Gate2 are stored in potential well under Gate2. A small negative voltage is applied at Gate2 to retain holes for a long time during holding "1". The BTBT governed by Gate1 mainly influences the reading current. Using the optimized programming condition, the DG-TFET DRAM obtains the higher current ratio of reading "1" to reading "0" (10 7 ) and RT of more than 2 s. The higher RT reduces the refresh rate and dynamic power consumption of DRAM.

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

Science.gov (United States)

Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Wang, Qianqiong

2017-09-01

The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure has the superior performance-higher retention time (RT) and weak temperature dependence. But the performance of TFET DRAM cell is sensitive to programming condition. In this paper, the guideline of programming optimization is discussed in detail by using simulation tool—Silvaco Atlas. Both the writing and reading operations of DG-TFET DRAM depend on the band-to-band tunneling (BTBT). During the writing operation, the holes coming from BTBT governed by Gate2 are stored in potential well under Gate2. A small negative voltage is applied at Gate2 to retain holes for a long time during holding "1". The BTBT governed by Gate1 mainly influences the reading current. Using the optimized programming condition, the DG-TFET DRAM obtains the higher current ratio of reading "1" to reading "0" (107) and RT of more than 2 s. The higher RT reduces the refresh rate and dynamic power consumption of DRAM.

Osteoblastic cells trigger gate currents on nanocrystalline diamond transistor

Czech Academy of Sciences Publication Activity Database

Ižák, Tibor; Krátká, Marie; Kromka, Alexander; Rezek, Bohuslav

2015-01-01

Roč. 129, May (2015), 95-99 ISSN 0927-7765 R&D Projects: GA ČR GAP108/12/0996 Grant - others:AVČR(CZ) M100101209 Institutional support: RVO:68378271 Keywords : field-effect transistors * nanocrystalline diamond * osteoblastic cells * leakage currents Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 3.902, year: 2015

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

Science.gov (United States)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

Use of water vapor for suppressing the growth of unstable low-{kappa} interlayer in HfTiO gate-dielectric Ge metal-oxide-semiconductor capacitors with sub-nanometer capacitance equivalent thickness

Energy Technology Data Exchange (ETDEWEB)

Xu, J.P. [Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan, 430074 (China); Zou, X. [School of Electromachine and Architecture Engineering, Jianghan University, Wuhan, 430056 (China); Lai, P.T. [Department of Electrical and Electronic Engineering, University of Hong Kong, Pokfulam Road (Hong Kong)], E-mail: laip@eee.hku.hk; Li, C.X.; Chan, C.L. [Department of Electrical and Electronic Engineering, University of Hong Kong, Pokfulam Road (Hong Kong)

2009-03-02

Annealing of high-permittivity HfTiO gate dielectric on Ge substrate in different gases (N{sub 2}, NH{sub 3}, NO and N{sub 2}O) with or without water vapor is investigated. Analysis by transmission electron microscopy indicates that the four wet anneals can greatly suppress the growth of a GeO{sub x} interlayer at the dielectric/Ge interface, and thus decrease interface states, oxide charges and gate leakage current. Moreover, compared with the wet N{sub 2} anneal, the wet NH{sub 3}, NO and N{sub 2}O anneals decrease the equivalent permittivity of the gate dielectric due to the growth of a GeO{sub x}N{sub y} interlayer. Among the eight anneals, the wet N{sub 2} anneal produces the best dielectric performance with an equivalent relative permittivity of 35, capacitance equivalent thickness of 0.81 nm, interface-state density of 6.4 x 10{sup 11} eV{sup -1} cm{sup -2} and gate leakage current of 2.7 x 10{sup -4} A/cm{sup 2} at V{sub g} = 1 V.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

Science.gov (United States)

Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

Influence of implantation energy on the electrical properties of ultrathin gate oxides grown on nitrogen implanted Si substrates

International Nuclear Information System (INIS)

Kapetanakis, E.; Skarlatos, D.; Tsamis, C.; Normand, P.; Tsoukalas, D.

2003-01-01

Metal-oxide-semiconductor tunnel diodes with gate oxides, in the range of 2.5-3.5 nm, grown either on 25 or 3 keV nitrogen-implanted Si substrates at (0.3 or 1) x10 15 cm -2 dose, respectively, are investigated. The dependence of N 2 + ion implant energy on the electrical quality of the growing oxide layers is studied through capacitance, equivalent parallel conductance, and gate current measurements. Superior electrical characteristics in terms of interface state trap density, leakage current, and breakdown fields are found for oxides obtained through 3 keV nitrogen implants. These findings together with the full absence of any extended defect in the silicon substrate make the low-energy nitrogen implantation technique an attractive option for reproducible low-cost growth of nanometer-thick gate oxides

Low operating voltage n-channel organic field effect transistors using lithium fluoride/PMMA bilayer gate dielectric

Energy Technology Data Exchange (ETDEWEB)

Kumar, S.; Dhar, A., E-mail: adhar@phy.iitkgp.ernet.in

2015-10-15

Highlights: • Alternative to chemically crosslinking of PMMA to achieve low leakage in provided. • Effect of LiF in reducing gate leakage through the OFET device is studied. • Effect of gate leakage on transistor performance has been investigated. • Low voltage operable and low temperature processed n-channel OFETs were fabricated. - Abstract: We report low temperature processed, low voltage operable n-channel organic field effect transistors (OFETs) using N,N′-Dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C{sub 8}) organic semiconductor and poly(methylmethacrylate) (PMMA)/lithium fluoride (LiF) bilayer gate dielectric. We have studied the role of LiF buffer dielectric in effectively reducing the gate leakage through the device and thus obtaining superior performance in contrast to the single layer PMMA dielectric devices. The bilayer OFET devices had a low threshold voltage (V{sub t}) of the order of 5.3 V. The typical values of saturation electron mobility (μ{sub s}), on/off ratio and inverse sub-threshold slope (S) for the range of devices made were estimated to be 2.8 × 10{sup −3} cm{sup 2}/V s, 385, and 3.8 V/decade respectively. Our work thus provides a potential substitution for much complicated process of chemically crosslinking PMMA to achieve low leakage, high capacitance, and thus low operating voltage OFETs.

A novel hetero-material gate-underlap electrically doped TFET for improving DC/RF and ambipolar behaviour

Science.gov (United States)

Yadav, Shivendra; Sharma, Dheeraj; Chandan, Bandi Venkata; Aslam, Mohd; Soni, Deepak; Sharma, Neeraj

2018-05-01

In this article, the impact of gate-underlap with hetero material (low band gap) has been investigated in terms of DC and Analog/RF parameters by proposed device named as hetero material gate-underlap electrically doped TFET (HM-GUL-ED-TFET). Gate-underlap resolves the problem of ambipolarity, gate leakage current (Ig) and slightly improves the gate to drain capacitance, but DC performance is almost unaffected. Further, the use of low band gap material (Si0.5 Ge) in proposed device causes a drastic improvement in the DC as well as RF figures of merit. We have investigated the Si0.5 Ge as a suitable candidate among different low band gap materials. In addition, the sensitivity of gate-underlap in terms of gate to drain inversion and parasitic capacitances has been studied for HM-GUL-ED-TFET. Further, relatively it is observed that gate-underlap is a better way than drain-underlap in the proposed structure to improve Analog/RF performances without degrading the DC parameters of device. Additionally, hetero-junction alignment analysis has been done for fabrication feasibility.

Comparison of the Standard of Air Leakage in Current Metal Duct Systems in the World

Science.gov (United States)

Di, Yuhui; Wang, Jiqian; Feng, Lu; Li, Xingwu; Hu, Chunlin; Shi, Junshe; Xu, Qingsong; Qiao, Leilei

2018-01-01

Based on the requirements of air leakage of metal ducts in Chinese design standards, technical measures and construction standards, this paper compares the development history, the classification of air pressure levels and the air tightness levels of air leakage standards of current Chinese and international metal ducts, sums up the differences, finds shortage by investigating the design and construction status and access to information, and makes recommendations, hoping to help the majority of engineering and technical personnel.

Leakage current analysis of a single-phase transformer-less PV inverter connected to the grid

DEFF Research Database (Denmark)

Ma, Lin; Tang, F.; Zhou, F.

2009-01-01

Due to the large surface of the PV generator, its stray capacity with respect to the ground reaches values that can be quite high. When no transformer is used in a grid-connected PV system, common-mode current, which caused by the common mode voltage, can flow through the stray capacitance between...... the PV array and the ground. It is quite harmful to the body safety and PV system. In order to avoid leakage current, different inverter topologies that generate no varying common-mode voltages, such as bipolar pulse-width modulation (PWM) full-bridge topology, NPC topology have been proposed. From...... the safety and energy saving viewpoint, it is necessary to develop a higher efficiency topology. In this paper, the generation mechanism of common mode current is discussed. Then different methods used to eliminate the leakage current are compared. Finally, the full-bridge which generates no varying common...

Current leakage relaxation and charge trapping in ultra-porous low-k materials

International Nuclear Information System (INIS)

Borja, Juan; Plawsky, Joel L.; Gill, William N.; Lu, T.-M.; Bakhru, Hassaram

2014-01-01

Time dependent dielectric failure has become a pivotal aspect of interconnect design as industry pursues integration of sub-22 nm process-technology nodes. Literature has provided key information about the role played by individual species such as electrons, holes, ions, and neutral impurity atoms. However, no mechanism has been shown to describe how such species interact and influence failure. Current leakage relaxation in low-k dielectrics was studied using bipolar field experiments to gain insight into how charge carrier flow becomes impeded by defects within the dielectric matrix. Leakage current decay was correlated to injection and trapping of electrons. We show that current relaxation upon inversion of the applied field can be described by the stretched exponential function. The kinetics of charge trapping events are consistent with a time-dependent reaction rate constant, k=k 0 ⋅(t+1) β−1 , where 0 < β < 1. Such dynamics have previously been observed in studies of charge trapping reactions in amorphous solids by W. H. Hamill and K. Funabashi, Phys. Rev. B 16, 5523–5527 (1977). We explain the relaxation process in charge trapping events by introducing a nonlinear charge trapping model. This model provides a description on the manner in which the transport of mobile defects affects the long-tail current relaxation processes in low-k films

The analysis of leakage current in MIS Au/SiO{sub 2}/n-GaAs at room temperature

Energy Technology Data Exchange (ETDEWEB)

Altuntas, H., E-mail: altunhalit@gmail.com [Cankiri Karatekin University, Department of Physics, Faculty of Science (Turkey); Ozcelik, S. [Gazi University, Department of Physics, Faculty of Science (Turkey)

2013-10-15

The aim of this study is to determine the reverse-bias leakage current conduction mechanisms in Au/SiO{sub 2}/n-GaAs metal-insulator-semiconductor type Schottky contacts. Reverse-bias current-voltage measurements (I-V) were performed at room temperature. The using of leakage current values in SiO{sub 2} at electric fields of 1.46-3.53 MV/cm, ln(J/E) vs. {radical}E graph showed good linearity. Rom this plot, dielectric constant of SiO{sub 2} was calculated as 3.7 and this value is perfect agreement with 3.9 which is value of SiO{sub 2} dielectric constant. This indicates, Poole-Frenkel type emission mechanism is dominant in this field region. On the other hand, electric fields between 0.06-0.73 and 0.79-1.45 MV/cm, dominant leakage current mechanisms were found as ohmic type conduction and space charge limited conduction, respectively.

Investigation of leakage current and breakdown voltage in irradiated double-sided 3D silicon sensors

International Nuclear Information System (INIS)

Betta, G.-F. Dalla; Mendicino, R.; Povoli, M.; Sultan, D.M.S.; Ayllon, N.; Hoeferkamp, M.; McDuff, H.; Seidel, S.; Boscardin, M.; Zorzi, N.; Mattiazzo, S.

2016-01-01

We report on an experimental study aimed at gaining deeper insight into the leakage current and breakdown voltage of irradiated double-sided 3D silicon sensors from FBK, so as to improve both the design and the fabrication technology for use at future hadron colliders such as the High Luminosity LHC. Several 3D diode samples of different technologies and layout are considered, as well as several irradiations with different particle types. While the leakage current follows the expected linear trend with radiation fluence, the breakdown voltage is found to depend on both the bulk damage and the surface damage, and its values can vary significantly with sensor geometry and process details.

A Labview Based Leakage Current Monitoring System For HV Insulators

Directory of Open Access Journals (Sweden)

N. Mavrikakis

2015-10-01

Full Text Available In this paper, a Labview based leakage current monitoring system for High Voltage insulators is described. The system uses a general purpose DAQ system with the addition of different current sensors. The DAQ system consists of a chassis and hot-swappable modules. Through the proper design of current sensors, low cost modules operating with a suitable input range can be employed. Fully customizable software can be developed using Labview, allowing on-demand changes and incorporation of upgrades. Such a system provides a low cost alternative to specially designed equipment with the added advantage of maximum flexibility. Further, it can be modified to satisfy the specifications (technical and economical set under different scenarios. In fact, the system described in this paper has already been installed in the HV Lab of the TEI of Crete whereas a variation of it is currently in use in TALOS High Voltage Test Station.

Reduction of leakage current in In{sub 0.53}Ga{sub 0.47}As channel metal-oxide-semiconductor field-effect-transistors using AlAs{sub 0.56}Sb{sub 0.44} confinement layers

Energy Technology Data Exchange (ETDEWEB)

Huang, Cheng-Ying, E-mail: cyhuang@ece.ucsb.edu; Lee, Sanghoon; Cohen-Elias, Doron; Law, Jeremy J. M.; Carter, Andrew D.; Rodwell, Mark J. W. [Department of Electrical and Computer Engineering, University of California, Santa Barbara, California 93106 (United States); Chobpattana, Varistha; Stemmer, Susanne [Materials Department, University of California, Santa Barbara, California 93106 (United States); Gossard, Arthur C. [Department of Electrical and Computer Engineering, University of California, Santa Barbara, California 93106 (United States); Materials Department, University of California, Santa Barbara, California 93106 (United States)

2013-11-11

We compare the DC characteristics of planar In{sub 0.53}Ga{sub 0.47}As channel MOSFETs using AlAs{sub 0.56}Sb{sub 0.44} barriers to similar MOSFETs using In{sub 0.52}Al{sub 0.48}As barriers. AlAs{sub 0.56}Sb{sub 0.44}, with ∼1.0 eV conduction-band offset to In{sub 0.53}Ga{sub 0.47}As, improves electron confinement within the channel. At gate lengths below 100 nm and V{sub DS} = 0.5 V, the MOSFETs with AlAs{sub 0.56}Sb{sub 0.44} barriers show steeper subthreshold swing (SS) and reduced drain-source leakage current. We attribute the greater leakage observed with the In{sub 0.52}Al{sub 0.48}As barrier to thermionic emission from the N + In{sub 0.53}Ga{sub 0.47}As source over the In{sub 0.53}Ga{sub 0.47}As/In{sub 0.52}Al{sub 0.48}As heterointerface. A 56 nm gate length device with the AlAs{sub 0.56}Sb{sub 0.44} barrier exhibits 1.96 mS/μm peak transconductance and SS = 134 mV/dec at V{sub DS} = 0.5 V.

Liquid helium boil-off measurements of heat leakage from sinter-forged BSCCO current leads under DC and AC conditions

International Nuclear Information System (INIS)

Cha, Y.S.; Niemann, R.C.; Hull, J.R.; Youngdahl, C.A.; Lanagan, M.T.; Nakade, M.; Hara, T.

1995-06-01

Liquid helium boil-off experiments are conducted to determine the heat leakage rate of a pair of BSCCO 2223 high-temperature superconductor current leads made by sinter forging. The experiments are carried out in both DC and AC conditions and with and without an intermediate heat intercept. Current ranges are from 0-500 A for DC tests and 0-1,000 A rms for AC tests. The leads are self-cooled. Results show that magnetic hysteresis (AC) losses for both the BSCCO leads and the low-temperature superconductor current jumper are small for the current range. It is shown that significant reduction in heat leakage rate (liquid helium boil-off rate) is realized by using the BSCCO superconductor leads. At 100 A, the heat leakage rate of the BSCCO/copper binary lead is approximately 29% of that of the conventional copper lead. Further reduction in liquid helium boil-off rate can be achieved by using an intermediate heat intercept. For example, at 500 K, the heat leakage rate of the BSCCO/copper binary lead is only 7% of that of the conventional copper lead when an intermediate heat intercept is used

Ultra Low Voltage Class AB Switched Current Memory Cells Based on Floating Gate Transistors

DEFF Research Database (Denmark)

Mucha, Igor

1999-01-01

current memory cells were designed using a CMOS process with threshold voltages V-T0n = \\V-T0p\\ = 0.9 V for the n- and p-channel devices. Both hand calculations and PSPICE simulations showed that the designed example switched current memory cell allowed a maximum signal range better than +/-18 mu......A proposal for a class AB switched current memory cell, suitable for ultra-low-voltage applications is presented. The proposal employs transistors with floating gates, allowing to build analog building blocks for ultralow supply voltage operation also in CMOS processes with high threshold voltages....... This paper presents the theoretical basis for the design of "floating-gate'' switched current memory cells by giving a detailed description and analysis of the most important impacts degrading the performance of the cells. To support the theoretical assumptions circuits based on "floating-gate'' switched...

Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process

International Nuclear Information System (INIS)

Wang Yan-Rong; Yang Hong; Xu Hao; Wang Xiao-Lei; Luo Wei-Chun; Qi Lu-Wei; Zhang Shu-Xiang; Wang Wen-Wu; Yan Jiang; Zhu Hui-Long; Zhao Chao; Chen Da-Peng; Ye Tian-Chun

2015-01-01

A multi-deposition multi-annealing technique (MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device’s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown (TDDB) characteristics of positive channel metal oxide semiconductor (PMOS) under different MDMA process conditions, including the deposition/annealing (D and A) cycles, the D and A time, and the total annealing time. The results show that the increases of the number of D and A cycles (from 1 to 2) and D and A time (from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail (TTF) at 63.2% increases by about several times. However, too many D and A cycles (such as 4 cycles) make the equivalent oxide thickness (EOT) increase by about 1 Å and the TTF of PMOS worsen. Moreover, different D and A times and numbers of D and A cycles induce different breakdown mechanisms. (paper)

Lateral current generation in n-AlGaAs/GaAs heterojunction channels by Schottky-barrier gate illumination

Energy Technology Data Exchange (ETDEWEB)

Kawazu, Takuya; Noda, Takeshi; Sakuma, Yoshiki [National Institute for Materials Science, 1-2-1 Sengen, Tsukuba, Ibaraki 305-0047 (Japan); Sakaki, Hiroyuki [National Institute for Materials Science, 1-2-1 Sengen, Tsukuba, Ibaraki 305-0047 (Japan); Toyota Technological Institute, 2-12-1 Hisakata, Tempaku-ku, Nagoya 468-8511 (Japan)

2015-01-12

We observe lateral currents induced in an n-AlGaAs/GaAs heterojunction channel of Hall bar geometry, when an asymmetric position of the Schottky metal gate is locally irradiated by a near-infrared laser beam. When the left side of the Schottky gate is illuminated with the laser, the lateral current flows from left to right in the two dimensional electron gas (2DEG) channel. In contrast, the right side illumination leads to the current from right to left. The magnitude of the lateral current is almost linearly dependent on the beam position, the current reaching its maximum for the beam at the edge of the Schottky gate. The experimental findings are well explained by a theory based on the current-continuity equation, where the lateral current in the 2DEG channel is driven by the photocurrent which vertically flows from the 2DEG to the Schottky gate.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

OpenAIRE

Roeckerath, M.; Lopes, J. M. J.; Durgun Özben, E.; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D.G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of < 1 nA/cm(2). Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated ...

Capacitor Property and Leakage Current Mechanism of ZrO2 Thin Dielectric Films Prepared by Anodic Oxidation

Science.gov (United States)

Kamijyo, Masahiro; Onozuka, Tomotake; Shinkai, Satoko; Sasaki, Katsutaka; Yamane, Misao; Abe, Yoshio

2003-07-01

Polycrystalline ZrO2 thin film capacitors were prepared by anodizing sputter-deposited Zr films. Electrical measurements are performed for the parallel-plate anodized capacitors with an Al-ZrO2-Zr (metal-insulator-metal) structure, and a high capacitance density (0.6 μF/cm2) and a low dielectric loss of nearly 1% are obtained for a very thin-oxide capacitor anodized at 10 V. In addition, the leakage current density of this capacitor is about 1.8 × 10-8 A/cm2 at an applied voltage of 5 V. However, the leakage current is somewhat larger than that of a low-loss HfO2 capacitor. The leakage current density (J) of ZrO2 capacitors as a function of applied electric field (E) was investigated for several capacitors with different oxide thicknesses, by plotting \\ln(J) vs E1/2 curves. As a result, it is revealed that the conduction mechanism is due to the Poole-Frenkel effect, irrespective of the oxide thickness.

Analysis of Gas Leakage and Current Loss of Solid Oxide Fuel Cells by Screen Printing

DEFF Research Database (Denmark)

Jia, Chuan; Han, Minfang; Chen, Ming

2017-01-01

Two types of anode supported solid oxide fuel cell (SOFC) NiO-YSZ/YSZ/GDC/LSCF with the same structure and different manufacturing process were tested. Gas leakage was suspected for cells manufactured with screen printing technique. Effective leak current densities for both types of cells were...... calculated. Their performances of electrochemical impedance spectroscopy (EIS) were compared and distribution function of relaxation times (DRT) technique was also used to find the clue of gas leakage. Finally, thinning and penetrating holes were observed in electrolyte layer, which confirmed the occurrence...

Device performance of in situ steam generated gate dielectric nitrided by remote plasma nitridation

International Nuclear Information System (INIS)

Al-Shareef, H. N.; Karamcheti, A.; Luo, T. Y.; Bersuker, G.; Brown, G. A.; Murto, R. W.; Jackson, M. D.; Huff, H. R.; Kraus, P.; Lopes, D.

2001-01-01

In situ steam generated (ISSG) oxides have recently attracted interest for use as gate dielectrics because of their demonstrated reliability improvement over oxides formed by dry oxidation. [G. Minor, G. Xing, H. S. Joo, E. Sanchez, Y. Yokota, C. Chen, D. Lopes, and A. Balakrishna, Electrochem. Soc. Symp. Proc. 99-10, 3 (1999); T. Y. Luo, H. N. Al-Shareef, G. A. Brown, M. Laughery, V. Watt, A. Karamcheti, M. D. Jackson, and H. R. Huff, Proc. SPIE 4181, 220 (2000).] We show in this letter that nitridation of ISSG oxide using a remote plasma decreases the gate leakage current of ISSG oxide by an order of magnitude without significantly degrading transistor performance. In particular, it is shown that the peak normalized transconductance of n-channel devices with an ISSG oxide gate dielectric decreases by only 4% and the normalized drive current by only 3% after remote plasma nitridation (RPN). In addition, it is shown that the reliability of the ISSG oxide exhibits only a small degradation after RPN. These observations suggest that the ISSG/RPN process holds promise for gate dielectric applications. [copyright] 2001 American Institute of Physics

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

Science.gov (United States)

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with reduced leakage current and enhanced breakdown voltage using aluminum ion implantation

Energy Technology Data Exchange (ETDEWEB)

Sun, Shichuang [Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan 430074 (China); Key Laboratory of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, CAS, Suzhou 215123 (China); Fu, Kai, E-mail: kfu2009@sinano.ac.cn, E-mail: cqchen@mail.hust.edu.cn; Yu, Guohao; Zhang, Zhili; Song, Liang; Deng, Xuguang; Li, Shuiming; Sun, Qian; Cai, Yong; Zhang, Baoshun [Key Laboratory of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, CAS, Suzhou 215123 (China); Qi, Zhiqiang; Dai, Jiangnan; Chen, Changqing, E-mail: kfu2009@sinano.ac.cn, E-mail: cqchen@mail.hust.edu.cn [Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan 430074 (China)

2016-01-04

This letter has studied the performance of AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors on silicon substrate with GaN buffer treated by aluminum ion implantation for insulating followed by a channel regrown by metal–organic chemical vapor deposition. For samples with Al ion implantation of multiple energies of 140 keV (dose: 1.4 × 10{sup 14} cm{sup −2}) and 90 keV (dose: 1 × 10{sup 14} cm{sup −2}), the OFF-state leakage current is decreased by more than 3 orders and the breakdown voltage is enhanced by nearly 6 times compared to the samples without Al ion implantation. Besides, little degradation of electrical properties of the 2D electron gas channel is observed where the maximum drain current I{sub DSmax} at a gate voltage of 3 V was 701 mA/mm and the maximum transconductance g{sub mmax} was 83 mS/mm.

The study of human bodies' impedance networks in testing leakage currents of electrical equipments

Science.gov (United States)

Zhang, Zhaohui; Wang, Xiaofei

2006-11-01

In the testing of electrical equipments' leakage currents, impedance networks of human bodies are used to simulate the current's effect on human bodies, and they are key to the preciseness of the testing result. This paper analyses and calculates three human bodies' impedance networks of measuring electric burn current, perception or reaction current, let-go current in IEC60990, by using Matlab, compares the research result of current effect thresholds' change with sine wave's frequency published in IEC479-2, and amends parameters of measuring networks. It also analyses the change of perception or reaction current with waveform by Multisim.

A high performance gate drive for large gate turn off thyristors

Energy Technology Data Exchange (ETDEWEB)

Szilagyi, C.P.

1993-01-01

Past approaches to gate turn-off (GTO) gating are application oriented, inefficient and dissipate power even when inactive. They allow the gate to avalanch, and do not reduce GTO turn-on and turn-off losses. A new approach is proposed which will allow modular construction and adaptability to large GTOs in the 50 amp to 2000 amp range. The proposed gate driver can be used in large voltage source and current source inverters and other power converters. The approach consists of a power metal-oxide-silicon field effect transistor (MOSFET) technology gating unit, with associated logic and supervisory circuits and an isolated flyback converter as the dc power source for the gating unit. The gate driver formed by the gating unit and the flyback converter is designed for 4000 V isolation. Control and supervisory signals are exchanged between the gate driver and the remote control system via fiber optics. The gating unit has programmable front-porch current amplitude and pulse-width, programmable closed-loop controlled back-porch current, and a turn-off switch capable of supplying negative gate current at demand as a function of peak controllable forward anode current. The GTO turn-on, turn-off and gate avalanch losses are reduced to a minimum. The gate driver itself has minimum operating losses. Analysis, design and practical realization are reported. 19 refs., 54 figs., 1 tab.

Radiation effects in a CMOS/SOS/Al-Gate D/A converter and on-chip diagnostic transistors

International Nuclear Information System (INIS)

Brucker, G.J.; Heagerty, W.

1976-01-01

This paper presents the results obtained from total dose and transient radiation tests on a CMOS/SOS/Al-Gate D/A converter and on-chip diagnostic transistors. Samples were irradiated by cobalt-60 gamma rays under worst-case conditions, and by 10-MeV electron pulses of 50-ns and 4.4-μs duration. Devices were fabricated with three different insulators; the two discussed here are standard wet oxide and a pyrogenic oxide. Test transistors on the D/A chips made it possible to diagnose the failure modes of the converter and to evaluate some special designs. These consisted of standard edge p- and n-channel transistors, edgeless units, edgeless tetrode transistors, and an edgeless type transmission gate with a diode clamp from substrate to gate. The total dose results indicate that the pyrogenic oxide increased the failure dose of the operational amplifier portion of the converter from 10 3 rads (Si) to 2 x 10 6 rads (Si); however, the sample and hold failed after exposure to a low level of 10 3 rads (Si). Test devices indicated this to be due to the radiation-induced leakage current of the transmission gate which discharges the sample and hold capacitor. The diode clamp decreased the threshold voltage shifts and the leakage currents. The edgeless devices improved the device performance because of a more abrupt turn-on. Narrow-pulse test data indicated that the edgeless units produced less photocurrent than the edge units by about a factor of three to four. Converter upset levels are less than or equal to 10 9 rads/s due to precision requirements which make a few millivolt transients untenable

Polarization retention loss in PbTiO3 ferroelectric films due to leakage currents

NARCIS (Netherlands)

Morelli, A.; Venkatesan, Sriram; Palasantzas, G.; Kooi, B. J.; De Hosson, J. Th. M.

2007-01-01

The relationship between retention loss in single crystal PbTiO3 ferroelectric thin films and leakage currents is demonstrated by piezoresponse and conductive atomic force microscopy measurements. It was found that the polarization reversal in the absence of an electric field followed a stretched

Effects of neglecting carrier tunneling on electrostatic potential in calculating direct tunneling gate current in deep submicron MOSFETs

OpenAIRE

Hakim, MMA; Haque, A

2002-01-01

We investigate the validity of the assumption of neglecting carrier tunneling effects on self-consistent electrostatic potential in calculating direct tunneling gate current in deep submicron MOSFETs. Comparison between simulated and experimental results shows that for accurate modeling of direct tunneling current, tunneling effects on potential profile need to be considered. The relative error in gate current due to neglecting carrier tunneling is higher at higher gate voltages and increases...

Role of Oxygen in Ionic Liquid Gating on Two-Dimensional Cr2Ge2Te6: A Non-oxide Material.

Science.gov (United States)

Chen, Yangyang; Xing, Wenyu; Wang, Xirui; Shen, Bowen; Yuan, Wei; Su, Tang; Ma, Yang; Yao, Yunyan; Zhong, Jiangnan; Yun, Yu; Xie, X C; Jia, Shuang; Han, Wei

2018-01-10

Ionic liquid gating can markedly modulate a material's carrier density so as to induce metallization, superconductivity, and quantum phase transitions. One of the main issues is whether the mechanism of ionic liquid gating is an electrostatic field effect or an electrochemical effect, especially for oxide materials. Recent observation of the suppression of the ionic liquid gate-induced metallization in the presence of oxygen for oxide materials suggests the electrochemical effect. However, in more general scenarios, the role of oxygen in the ionic liquid gating effect is still unclear. Here, we perform ionic liquid gating experiments on a non-oxide material: two-dimensional ferromagnetic Cr 2 Ge 2 Te 6 . Our results demonstrate that despite the large increase of the gate leakage current in the presence of oxygen, the oxygen does not affect the ionic liquid gating effect on  the channel resistance of Cr 2 Ge 2 Te 6 devices (ionic liquid gating is more effective on the modulation of the channel resistances compared to the back gating across the 300 nm thick SiO 2 .

Investigation and statistical modeling of InAs-based double gate tunnel FETs for RF performance enhancement

Science.gov (United States)

Poorvasha, S.; Lakshmi, B.

2018-05-01

In this paper, RF performance analysis of InAs-based double gate (DG) tunnel field effect transistors (TFETs) is investigated in both qualitative and quantitative fashion. This investigation is carried out by varying the geometrical and doping parameters of TFETs to extract various RF parameters, unity gain cut-off frequency (f t), maximum oscillation frequency (f max), intrinsic gain and admittance (Y) parameters. An asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. Higher ON-current (I ON) of about 0.2 mA and less leakage current (I OFF) of 29 fA is achieved for DG TFET with gate-drain overlap. Due to increase in transconductance (g m), higher f t and intrinsic gain is attained for DG TFET with gate-drain overlap. Higher f max of 985 GHz is obtained for drain doping of 5 × 1017 cm‑3 because of the reduced gate-drain capacitance (C gd) with DG TFET with gate-drain overlap. In terms of Y-parameters, gate oxide thickness variation offers better performance due to the reduced values of C gd. A second order numerical polynomial model is generated for all the RF responses as a function of geometrical and doping parameters. The simulation results are compared with this numerical model where the predicted values match with the simulated values. Project supported by the Department of Science and Technology, Government of India under SERB Scheme (No. SERB/F/2660).

Dextromethorphan inhibition of voltage-gated proton currents in BV2 microglial cells.

Science.gov (United States)

Song, Jin-Ho; Yeh, Jay Z

2012-05-10

Dextromethorphan, an antitussive drug, has a neuroprotective property as evidenced by its inhibition of microglial production of pro-inflammatory cytokines and reactive oxygen species. The microglial activation requires NADPH oxidase activity, which is sustained by voltage-gated proton channels in microglia as they dissipate an intracellular acid buildup. In the present study, we examined the effect of dextromethorphan on proton currents in microglial BV2 cells. Dextromethorphan reversibly inhibited proton currents with an IC(50) value of 51.7 μM at an intracellular/extracellular pH gradient of 5.5/7.3. Dextromethorphan did not change the reversal potential or the voltage dependence of the gating. Dextrorphan and 3-hydroxymorphinan, major metabolites of dextromethorphan, and dextromethorphan methiodide were ineffective in inhibiting proton currents. The results indicate that dextromethorphan inhibition of proton currents would suppress NADPH oxidase activity and, eventually, microglial activation. Copyright © 2012 Elsevier Ireland Ltd. All rights reserved.

Leakage Current Degradation Due to Ion Drift and Diffusion in Tantalum and Niobium Oxide Capacitors

Directory of Open Access Journals (Sweden)

Kuparowitz Martin

2017-06-01

Full Text Available High temperature and high electric field applications in tantalum and niobium capacitors are limited by the mechanism of ion migration and field crystallization in a tantalum or niobium pentoxide insulating layer. The study of leakage current (DCL variation in time as a result of increasing temperature and electric field might provide information about the physical mechanism of degradation. The experiments were performed on tantalum and niobium oxide capacitors at temperatures of about 125°C and applied voltages ranging up to rated voltages of 35 V and 16 V for tantalum and niobium oxide capacitors, respectively. Homogeneous distribution of oxygen vacancies acting as positive ions within the pentoxide layer was assumed before the experiments. DCL vs. time characteristics at a fixed temperature have several phases. At the beginning of ageing the DCL increases exponentially with time. In this period ions in the insulating layer are being moved in the electric field by drift only. Due to that the concentration of ions near the cathode increases producing a positively charged region near the cathode. The electric field near the cathode increases and the potential barrier between the cathode and insulating layer decreases which results in increasing DCL. However, redistribution of positive ions in the insulator layer leads to creation of a ion concentration gradient which results in a gradual increase of the ion diffusion current in the direction opposite to the ion drift current component. The equilibrium between the two for a given temperature and electric field results in saturation of the leakage current value. DCL vs. time characteristics are described by the exponential stretched law. We found that during the initial part of ageing an exponent n = 1 applies. That corresponds to the ion drift motion only. After long-time application of the electric field at a high temperature the DCL vs. time characteristics are described by the exponential

Leakage current phenomena in Mn-doped Bi(Na,K)TiO_3-based ferroelectric thin films

International Nuclear Information System (INIS)

Walenza-Slabe, J.; Gibbons, B. J.

2016-01-01

Mn-doped 80(Bi_0_._5Na_0_._5)TiO_3-20(Bi_0_._5K_0_._5)TiO_3 thin films were fabricated by chemical solution deposition on Pt/TiO_2/SiO_2/Si substrates. Steady state and time-dependent leakage current were investigated from room temperature to 180 °C. Undoped and low-doped films showed space-charge-limited current (SCLC) at high temperatures. The electric field marking the transition from Ohmic to trap-filling-limited current increased monotonically with Mn-doping. With 2 mol. % Mn, the current was Ohmic up to 430 kV/cm, even at 180 °C. Modeling of the SCLC showed that all films exhibited shallow trap levels and high trap concentrations. In the regime of steady state leakage, there were also observations of negative differential resistivity and positive temperature coefficient of resistivity near room temperature. Both of these phenomena were confined to relatively low temperatures (below ∼60 °C). Transient currents were observed in the time-dependent leakage data, which was measured out to several hundred seconds. In the undoped films, these were found to be a consequence of oxygen vacancy migration modulating the electronic conductivity. The mobility and thermal activation energy for oxygen vacancies was extracted as μ_i_o_n ≈ 1.7 × 10"−"1"2 cm"2 V"−"1 s"−"1 and E_A_,_i_o_n ≈ 0.92 eV, respectively. The transient current displayed different characteristics in the 1 mol. % Mn-doped films which were not readily explained by oxygen vacancy migration.

Reliability study of ultra-thin gate oxides on strained-Si/SiGe MOS structures

International Nuclear Information System (INIS)

Varzgar, John B.; Kanoun, Mehdi; Uppal, Suresh; Chattopadhyay, Sanatan; Tsang, Yuk Lun; Escobedo-Cousins, Enrique; Olsen, Sarah H.; O'Neill, Anthony; Hellstroem, Per-Erik; Edholm, Jonas; Ostling, Mikael; Lyutovich, Klara; Oehme, Michael; Kasper, Erich

2006-01-01

The reliability of gate oxides on bulk Si and strained Si (s-Si) has been evaluated using constant voltage stressing (CVS) to investigate their breakdown characteristics. The s-Si architectures exhibit a shorter life time compared to that of bulk Si, which is attributed to higher bulk oxide charges (Q ox ) and increased surface roughness in the s-Si structures. The gate oxide in the s-Si structure exhibits a hard breakdown (HBD) at 1.9 x 10 4 s, whereas HBD is not observed in bulk Si up to a measurement period of 1.44 x 10 5 s. The shorter lifetime of the s-Si gate oxide is attributed to a larger injected charge (Q inj ) compared to Q inj in bulk Si. Current-voltage (I-V) measurements for bulk Si samples at different stress intervals show an increase in stress induced leakage current (SILC) of two orders in the low voltage regime from zero stress time to up to 5 x 10 4 s. In contrast, superior performance enhancements in terms of drain current, maximum transconductance and effective channel mobility are observed in s-Si MOSFET devices compared to bulk Si. The results from this study indicate that further improvement in gate oxide reliability is needed to exploit the sustained performance enhancement of s-Si devices over bulk Si

Radiation-hardened gate-around n-MOSFET structure for radiation-tolerant application-specific integrated circuits

International Nuclear Information System (INIS)

Lee, Min Su; Lee, Hee Chul

2012-01-01

To overcome the total ionizing dose effect on an n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET), we designed a radiation-hardened gate-around n-MOSFET structure and evaluated it through a radiation-exposure experiment. Each test device was fabricated in a commercial 0.35-micron complementary metal-oxide-semiconductor (CMOS) process. The fabricated devices were evaluated under a total dose of 1 Mrad (Si) at a dose rate of 250 krad/h to obtain very high reliability for space electronics. The experimental results showed that the gate-around n-MOSFET structure had very good performance against 1 Mrad (Si) of gamma radiation, while the conventional n-MOSFET experienced a considerable amount of radiation-induced leakage current. Furthermore, a source follower designed with the gate-around transistor worked properly at 1 Mrad (Si) of gamma radiation while a source follower designed with the conventional n-MOSFET lost its functionality.

AlGaN/GaN MISHEMTs with AlN gate dielectric grown by thermal ALD technique.

Science.gov (United States)

Liu, Xiao-Yong; Zhao, Sheng-Xun; Zhang, Lin-Qing; Huang, Hong-Fan; Shi, Jin-Shan; Zhang, Chun-Min; Lu, Hong-Liang; Wang, Peng-Fei; Zhang, David Wei

2015-01-01

Recently, AlN plasma-enhanced atomic layer deposition (ALD) passivation technique had been proposed and investigated for suppressing the dynamic on-resistance degradation behavior of high-electron-mobility transistors (HEMTs). In this paper, a novel gate dielectric and passivation technique for GaN-on-Si AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMTs) is presented. This technique features the AlN thin film grown by thermal ALD at 400°C without plasma enhancement. A 10.6-nm AlN thin film was grown upon the surface of the HEMT serving as the gate dielectric under the gate electrode and as the passivation layer in the access region at the same time. The MISHEMTs with thermal ALD AlN exhibit enhanced on/off ratio, reduced channel sheet resistance, reduction of gate leakage by three orders of magnitude at a bias of 4 V, reduced threshold voltage hysteresis of 60 mV, and suppressed current collapse degradation.

Suppression of Lateral Diffusion and Surface Leakage Currents in nBn Photodetectors Using an Inverted Design

Science.gov (United States)

Du, X.; Savich, G. R.; Marozas, B. T.; Wicks, G. W.

2018-02-01

Surface leakage and lateral diffusion currents in InAs-based nBn photodetectors have been investigated. Devices fabricated using a shallow etch processing scheme that etches through the top contact and stops at the barrier exhibited large lateral diffusion current but undetectably low surface leakage. Such large lateral diffusion current significantly increased the dark current, especially in small devices, and causes pixel-to-pixel crosstalk in detector arrays. To eliminate the lateral diffusion current, two different approaches were examined. The conventional solution utilized a deep etch process, which etches through the top contact, barrier, and absorber. This deep etch processing scheme eliminated lateral diffusion, but introduced high surface current along the device mesa sidewalls, increasing the dark current. High device failure rate was also observed in deep-etched nBn structures. An alternative approach to limit lateral diffusion used an inverted nBn structure that has its absorber grown above the barrier. Like the shallow etch process on conventional nBn structures, the inverted nBn devices were fabricated with a processing scheme that only etches the top layer (the absorber, in this case) but avoids etching through the barrier. The results show that inverted nBn devices have the advantage of eliminating the lateral diffusion current without introducing elevated surface current.

SiO2/AlON stacked gate dielectrics for AlGaN/GaN MOS heterojunction field-effect transistors

Science.gov (United States)

Watanabe, Kenta; Terashima, Daiki; Nozaki, Mikito; Yamada, Takahiro; Nakazawa, Satoshi; Ishida, Masahiro; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

Stacked gate dielectrics consisting of wide bandgap SiO2 insulators and thin aluminum oxynitride (AlON) interlayers were systematically investigated in order to improve the performance and reliability of AlGaN/GaN metal–oxide–semiconductor (MOS) devices. A significantly reduced gate leakage current compared with that in a single AlON layer was achieved with these structures, while maintaining the superior thermal stability and electrical properties of the oxynitride/AlGaN interface. Consequently, distinct advantages in terms of the reliability of the gate dielectrics, such as an improved immunity against electron injection and an increased dielectric breakdown field, were demonstrated for AlGaN/GaN MOS capacitors with optimized stacked structures having a 3.3-nm-thick AlON interlayer.

Band alignments and improved leakage properties of (La2O3)0.5(SiO2)0.5/SiO2/GaN stacks for high-temperature metal-oxide-semiconductor field-effect transistor applications

Science.gov (United States)

Gao, L. G.; Xu, B.; Guo, H. X.; Xia, Y. D.; Yin, J.; Liu, Z. G.

2009-06-01

The band alignments of (La2O3)0.5(SiO2)0.5(LSO)/GaN and LSO/SiO2/GaN gate dielectric stacks were investigated comparatively by using x-ray photoelectron spectroscopy. The valence band offsets for LSO/GaN stack and LSO/SiO2/GaN stack are 0.88 and 1.69 eV, respectively, while the corresponding conduction band offsets are found to be 1.40 and 1.83 eV, respectively. Measurements of the leakage current density as function of temperature revealed that the LSO/SiO2/GaN stack has much lower leakage current density than that of the LSO/GaN stack, especially at high temperature. It is concluded that the presence of a SiO2 buffer layer increases band offsets and reduces the leakage current density effectively.

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

Science.gov (United States)

Kumar, Manoj; Pratap, Yogesh; Haldar, Subhasis; Gupta, Mridula; Gupta, R. S.

2017-12-01

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported, to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions. This novel structure offers low barrier height at the source and offers high ON-state current. The I ON/I OFF of ISE-CGAA-SB-MOSFET increases by 1177 times and offers steeper subthreshold slope (~60 mV/decade). However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate, dual metal gate, single metal gate with ISE, and dual metal gate with ISE has been presented. The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design. The numerical simulation is performed using the ATLAS-3D device simulator.

The Leakage Current Improvement of a Ni-Silicided SiGe/Si Junction Using a Si Cap Layer and the PAI Technique

International Nuclear Information System (INIS)

Chang Jian-Guang; Wu Chun-Bo; Ji Xiao-Li; Ma Hao-Wen; Yan Feng; Shi Yi; Zhang Rong

2012-01-01

We investigate the leakage current of ultra-shallow Ni-silicided SiGe/Si junctions for 45 nm CMOS technology using a Si cap layer and the pre-amorphization implantation (PAI) process. It is found that with the conventional Ni silicide method, the leakage current of a p + (SiGe)—n(Si) junction is large and attributed to band-to-band tunneling and the generation-recombination process. The two leakage contributors can be suppressed quite effectively when a Si cap layer is added in the Ni silicide method. The leakage reduction is about one order of magnitude and could be associated with the suppression of the agglomeration of the Ni germano-silicide film. In addition, the PAI process after the application of a Si cap layer has little effect on improving the junction leakage but reduces the sheet resistance of the silicide film. As a result, the novel Ni silicide method using a Si cap combined with PAI is a promising choice for SiGe junctions in advanced technology. (cross-disciplinary physics and related areas of science and technology)

Leakage Current Suppression with A Novel Six-Switch Photovoltaic Grid-Connected Inverter

OpenAIRE

Wei, Baoze; Guo, Xiaoqiang; Guerrero, Josep M.; Savaghebi, Mehdi

2015-01-01

In order to solve the problem of the leakage current in non-isolated photovoltaic (PV) systems, a novel six-switch topology and control strategy are proposed in this paper. The inductor-bypass strategy solves the common-mode voltage limitation of the conventional six-switch topology in case of unmatched inductances. And the stray capacitor voltage of the non-isolated photovoltaic system is free of high frequency ripples. Theoretical analysis and simulation are carried out to verify the propos...

IR Camera Validation of IGBT Junction Temperature Measurement via Peak Gate Current

DEFF Research Database (Denmark)

Baker, Nick; Dupont, Laurent; Munk-Nielsen, Stig

2017-01-01

partial bond-wire lift-off. Results are also compared with a traditional electrical temperature measurement method: the voltage drop under low current (VCE(low)). In all cases, the IGPeak method is found to provide a temperature slightly overestimating the temperature of the gate pad. Consequently, both...... the gate pad position and chip temperature distribution influence whether the measurement is representative of the mean junction temperature. These results remain consistent after chips are degraded through bondwire lift-off. In a paralleled IGBT configuration with non-negligible temperature disequilibrium...

Calculation of Leakage Inductance for High Frequency Transformers

DEFF Research Database (Denmark)

Ouyang, Ziwei; Jun, Zhang; Hurley, William Gerard

2015-01-01

Frequency dependent leakage inductance is often observed. High frequency eddy current effects cause a reduction in leakage inductance. The proximity effect between adjacent layers is responsible for the reduction of leakage inductance. This paper gives a detailed analysis of high frequency leakag...

Performance and Design Considerations of a Novel Dual-Material Gate Carbon Nanotube Field-Effect Transistors: Nonequilibrium Green's Function Approach

Science.gov (United States)

Arefinia, Zahra; Orouji, Ali A.

2009-02-01

The concept of dual-material gate (DMG) is applied to the carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions, and the features exhibited by the resulting new structure, i.e., the DMG-CNTFET structure, have been examined for the first time by developing a two-dimensional (2D) full quantum simulation. The simulations have been done by the self-consistent solution of 2D Poisson-Schrödinger equations, within the nonequilibrium Green's function (NEGF) formalism. The results show DMG-CNTFET decreases significantly leakage current and drain conductance and increases on-off current ratio and voltage gain as compared to the single material gate counterparts CNTFET. It is seen that short channel effects in this structure are suppressed because of the perceivable step in the surface potential profile, which screens the drain potential. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate metals. Therefore, this work provides an incentive for further experimental exploration.

A Very Robust AlGaN/GaN HEMT Technology to High Forward Gate Bias and Current

Directory of Open Access Journals (Sweden)

Bradley D. Christiansen

2012-01-01

Full Text Available Reports to date of GaN HEMTs subjected to forward gate bias stress include varied extents of degradation. We report an extremely robust GaN HEMT technology that survived—contrary to conventional wisdom—high forward gate bias (+6 V and current (>1.8 A/mm for >17.5 hours exhibiting only a slight change in gate diode characteristic, little decrease in maximum drain current, with only a 0.1 V positive threshold voltage shift, and, remarkably, a persisting breakdown voltage exceeding 200 V.

Dual-Gate p-GaN Gate High Electron Mobility Transistors for Steep Subthreshold Slope.

Science.gov (United States)

Bae, Jong-Ho; Lee, Jong-Ho

2016-05-01

A steep subthreshold slope characteristic is achieved through p-GaN gate HEMT with dual-gate structure. Obtained subthreshold slope is less than 120 μV/dec. Based on the measured and simulated data obtained from single-gate device, breakdown of parasitic floating-base bipolar transistor and floating gate charged with holes are responsible to increase abruptly in drain current. In the dual-gate device, on-current degrades with high temperature but subthreshold slope is not changed. To observe the switching speed of dual-gate device and transient response of drain current are measured. According to the transient responses of drain current, switching speed of the dual-gate device is about 10(-5) sec.

Respiratory gated radiotherapy: current techniques and potential benefits

International Nuclear Information System (INIS)

Giraud, P.; Campana, F.; Rosenwald, J.C.; Cosset, J.M.; Reboul, F.; Garcia, R.; Clippe, S.; Carrie, C.; Dubray, B.

2003-01-01

Respiration-gated radiotherapy offers a significant potential for improvement in the irradiation of tumor sites affected by respiratory motion such as lung, breast and liver tumors. An increased conformality of irradiation fields leading to decreased complications rates of organs at risk (lung, heart...) is expected. Respiratory gating is in line with the need for improved precision required by radiotherapy techniques such as 3D conformal radiotherapy or intensity modulated radiotherapy. Reduction of respiratory motion can be achieved by using either breath hold techniques or respiration synchronized gating techniques. Breath-hold techniques can be achieved with active, in which airflow of the patient is temporarily blocked by a valve, or passive techniques, in which the patient voluntarily breath-hold. Synchronized gating techniques use external devices to predict the phase of the respiration cycle while the patient breaths freely. These techniques presently investigated in several medical centers worldwide. Although promising, the first results obtained in lung and liver cancer patients require confirmation. Physical, technical and physiological questions still remain to be answered. This paper describes the most frequently used gated techniques and the main published clinical reports on the use of respiration-gated radiotherapy in order to evaluate the impact of these techniques. (author)

Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS

KAUST Repository

Dadgour, Hamed F.

2010-01-01

Nano-Electro-Mechanical Switches (NEMS) are among the most promising emerging devices due to their near-zero subthreshold-leakage currents. This paper reports device fabrication and modeling, as well as novel logic gate design using "laterally-actuated double-electrode NEMS" structures. The new device structure has several advantages over existing NEMS architectures such as being immune to impact bouncing and release vibrations (unlike a vertically-actuated NEMS) and offer higher flexibility to implement compact logic gates (unlike a single-electrode NEMS). A comprehensive analytical framework is developed to model different properties of these devices by solving the Euler-Bernoulli\\'s beam equation. The proposed model is validated using measurement data for the fabricated devices. It is shown that by ignoring the non-uniformity of the electrostatic force distribution, the existing models "underestimate" the actual value of Vpull-in and Vpull-out. Furthermore, novel energy efficient NEMS-based circuit topologies are introduced to implement compact inverter, NAND, NOR and XOR gates. For instance, the proposed XOR gate can be implemented by using only two NEMS devices compared to that of a static CMOS-based XOR gate that requires at least 10 transistors. © Copyright 2010 ACM.

Feedback-tuned, noise resilient gates for encoded spin qubits

Science.gov (United States)

Bluhm, Hendrik

Spin 1/2 particles form native two level systems and thus lend themselves as a natural qubit implementation. However, encoding a single qubit in several spins entails benefits, such as reducing the resources necessary for qubit control and protection from certain decoherence channels. While several varieties of such encoded spin qubits have been implemented, accurate control remains challenging, and leakage out of the subspace of valid qubit states is a potential issue. Optimal performance typically requires large pulse amplitudes for fast control, which is prone to systematic errors and prohibits standard control approaches based on Rabi flopping. Furthermore, the exchange interaction typically used to electrically manipulate encoded spin qubits is inherently sensitive to charge noise. I will discuss all-electrical, high-fidelity single qubit operations for a spin qubit encoded in two electrons in a GaAs double quantum dot. Starting from a set of numerically optimized control pulses, we employ an iterative tuning procedure based on measured error syndromes to remove systematic errors.Randomized benchmarking yields an average gate fidelity exceeding 98 % and a leakage rate into invalid states of 0.2 %. These gates exhibit a certain degree of resilience to both slow charge and nuclear spin fluctuations due to dynamical correction analogous to a spin echo. Furthermore, the numerical optimization minimizes the impact of fast charge noise. Both types of noise make relevant contributions to gate errors. The general approach is also adaptable to other qubit encodings and exchange based two-qubit gates.

A Novel Hybrid Nano Scale MOSFET Structure for Low Leak Application

Directory of Open Access Journals (Sweden)

A. Rana

2011-06-01

Full Text Available In this paper, novel hybrid MOSFET(HMOS structure has been proposed to reduce the gate leakage current drastically. This novel hybrid MOSFET (HMOS uses source/drain-to-gate non-overlap region in combination with high-K layer/interfacial oxide as gate stack. The extended S/D in the non-overlap region is induced by fringing gate electric field through the high-k dielectric spacer. The gate leakage behaviour of HMOS has been investigated with the help of compact analytical model and Sentaurus Simulation. The results so obtained show good agreement between model and simulation data. It is found that HMOS structure has reduced the gate leakage current to great extent as compared to conventional overlapped MOSFET structure. Further, the proposed structure had demonstrated improved on current, off current, subthreshold slope and DIBL characteristic.

Physical and electrical characteristics of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with rare earth Er2O3 as a gate dielectric

International Nuclear Information System (INIS)

Lin, Ray-Ming; Chu, Fu-Chuan; Das, Atanu; Liao, Sheng-Yu; Chou, Shu-Tsun; Chang, Liann-Be

2013-01-01

In this study, the rare earth erbium oxide (Er 2 O 3 ) was deposited using an electron beam onto an AlGaN/GaN heterostructure to fabricate metal-oxide-semiconductor high-electron-mobility transistors (MOS–HEMTs) that exhibited device performance superior to that of a conventional HEMT. Under similar bias conditions, the gate leakage currents of these MOS–HEMT devices were four orders of magnitude lower than those of conventional Schottky gate HEMTs. The measured sub-threshold swing (SS) and the effective trap state density (N t ) of the MOS–HEMT were 125 mV/decade and 4.3 × 10 12 cm −2 , respectively. The dielectric constant of the Er 2 O 3 layer in this study was 14, as determined through capacitance–voltage measurements. In addition, the gate–source reverse breakdown voltage increased from –166 V for the conventional HEMT to –196 V for the Er 2 O 3 MOS–HEMT. - Highlights: ► GaN/AlGaN/Er 2 O 3 metal-oxide semiconductor high electron mobility transistor ► Physical and electrical characteristics are presented. ► Electron beam evaporated Er 2 O 3 with excellent surface roughness ► Device exhibits reduced gate leakage current and improved I ON /I OFF ratio

Motor current and leakage flux signature analysis technique for condition monitoring

International Nuclear Information System (INIS)

Pillai, M.V.; Moorthy, R.I.K.; Mahajan, S.C.

1994-01-01

Till recently analysis of vibration signals was the only means available to predict the state of health of plant equipment. Motor current and leakage magnetic flux signature analysis is acquiring importance as a technique for detection of incipient damages in the electrical machines and as a supplementary technique for diagnostics of driven equipment such as centrifugal and reciprocating pumps. The state of health of the driven equipment is assessed by analysing time signal, frequency spectrum and trend analysis. For example, the pump vane frequency, piston stroke frequency, gear frequency and bearing frequencies are indicated in the current and flux spectra. By maintaining a periodic record of the amplitudes of various frequency lines in the frequency spectra, it is possible to understand the trend of deterioration of parts and components of the pump. All problems arising out of inappropriate mechanical alignment of vertical pumps are easily identified by a combined analysis of current, flux and vibration signals. It is found that current signature analysis technique is a sufficient method in itself for the analysis of state of health of reciprocating pumps and compressors. (author). 10 refs., 4 figs

New Leakage Current Particulate Matter Sensor for On-Board Diagnostics

Directory of Open Access Journals (Sweden)

Jiawei Wang

2016-01-01

Full Text Available Structure and principle of the new leakage current particulate matter (PM sensor are introduced and further study is performed on the PM sensor with the combination of numerical simulation and bench test. High voltage electrode, conductive shell, and heaters are all built-in. Based on the principle of Venturi tube and maze structure design, this sensor can detect transient PM concentrations. Internal flow field of the sensor and distribution condition of PM inside the sensor are analyzed through gas-solid two-phase flow numerical simulation. The experiment was also carried out on the whole sensor system (including mechanical and electronic circuit part and the output signals were analyzed. The results of simulation and experiment reveal the possibility of PM concentration (mass detection by the sensor.

Permanent supervision of leakage currents in low voltage installations; Supervisao permanente de correntes de fuga em instalacoes BT

Energy Technology Data Exchange (ETDEWEB)

Muhm, Helmut [W. Bender GmbH (Germany)

2010-09-15

Electromagnetic compatibility (EMC) is a premise for the electrical installations operate free of disturbances and reliably. Therefor, It is important detect dispersed leakage currents. This article show the corrective measures of this problem.

Gate-controlled current and inelastic electron tunneling spectrum of benzene: a self-consistent study.

Science.gov (United States)

Liang, Y Y; Chen, H; Mizuseki, H; Kawazoe, Y

2011-04-14

We use density functional theory based nonequilibrium Green's function to self-consistently study the current through the 1,4-benzenedithiol (BDT). The elastic and inelastic tunneling properties through this Au-BDT-Au molecular junction are simulated, respectively. For the elastic tunneling case, it is found that the current through the tilted molecule can be modulated effectively by the external gate field, which is perpendicular to the phenyl ring. The gate voltage amplification comes from the modulation of the interaction between the electrodes and the molecules in the junctions. For the inelastic case, the electron tunneling scattered by the molecular vibrational modes is considered within the self-consistent Born approximation scheme, and the inelastic electron tunneling spectrum is calculated.

High performance solution processed zirconium oxide gate dielectric appropriate for low temperature device application

Energy Technology Data Exchange (ETDEWEB)

Hasan, Musarrat; Nguyen, Manh-Cuong; Kim, Hyojin; You, Seung-Won; Jeon, Yoon-Seok; Tong, Duc-Tai; Lee, Dong-Hwi; Jeong, Jae Kyeong; Choi, Rino, E-mail: rino.choi@inha.ac.kr

2015-08-31

This paper reports a solution processed electrical device with zirconium oxide gate dielectric that was fabricated at a low enough temperature appropriate for flexible electronics. Both inorganic dielectric and channel materials were synthesized in the same organic solvent. The dielectric constant achieved was 13 at 250 °C with a reasonably low leakage current. The bottom gate transistor devices showed the highest mobility of 75 cm{sup 2}/V s. The device is operated at low voltage with high-k dielectric with excellent transconductance and low threshold voltage. Overall, the results highlight the potential of low temperature solution based deposition in fabricating more complicated circuits for a range of applications. - Highlights: • We develop a low temperature inorganic dielectric deposition process. • We fabricate oxide semiconductor channel devices using all-solution processes. • Same solvent is used for dielectric and oxide semiconductor deposition.

Temperature-dependent leakage current behavior of epitaxial Bi0.5Na0.5TiO3-based thin films made by pulsed laser deposition

Science.gov (United States)

Hejazi, M. M.; Safari, A.

2011-11-01

This paper discusses the electrical conduction mechanisms in a 0.88 Bi0.5Na0.5TiO3-0.08 Bi0.5K0.5TiO3-0.04 BaTiO3 thin film in the temperature range of 200-350 K. The film was deposited on a SrRuO3/SrTiO3 substrate by pulsed laser deposition technique. At all measurement temperatures, the leakage current behavior of the film matched well with the Lampert's triangle bounded by three straight lines of different slopes. The relative location of the triangle sides varied with temperature due to its effect on the density of charge carriers and un-filled traps. At low electric fields, the ohmic conduction governed the leakage mechanism. The calculated activation energy of the trap is 0.19 eV implying the presence of shallow traps in the film. With increasing the applied field, an abrupt increase in the leakage current was observed. This was attributed to a trap-filling process by the injected carriers. At sufficiently high electric fields, the leakage current obeyed the Child's trap-free square law suggesting the space charge limited current was the dominant mechanism.

Gate length scaling trends of drive current enhancement in CMOSFETs with dual stress overlayers and embedded-SiGe

International Nuclear Information System (INIS)

Flachowsky, S.; Wei, A.; Herrmann, T.; Illgen, R.; Horstmann, M.; Richter, R.; Salz, H.; Klix, W.; Stenzel, R.

2008-01-01

Strain engineering in MOSFETs using tensile nitride overlayer (TOL) films, compressive nitride overlayer (COL) films, and embedded-SiGe (eSiGe) is studied by extensive device experiments and numerical simulations. The scaling behavior was analyzed by gate length reduction down to 40 nm and it was found that drive current strongly depends on the device dimensions. The reduction of drain-current enhancement for short-channel devices can be attributed to two competing factors: shorter gate length devices have increased longitudinal and vertical stress components which should result in improved drain-currents. However, there is a larger degradation from external resistance as the gate length decreases, due to a larger voltage dropped across the external resistance. Adding an eSiGe stressor reduces the external resistance in the p-MOSFET, to the extent that the drive current improvement from COL continues to increase even down the shortest gate length studied. This is due to the reduced resistivity of SiGe itself and the SiGe valence band offset relative to Si, leading to a smaller silicide-active contact resistance. It demonstrates the advantage of combining eSiGe and COL, not only for increased stress, but also for parasitic resistance reduction to enable better COL drive current benefit

Junction leakage measurements with micro four-point probes

DEFF Research Database (Denmark)

Lin, Rong; Petersen, Dirch Hjorth; Wang, Fei

2012-01-01

We present a new, preparation-free method for measuring the leakage current density on ultra-shallow junctions. The junction leakage is found by making a series of four-point sheet resistance measurements on blanket wafers with variable electrode spacings. The leakage current density is calculated...... using a fit of the measured four-point resistances to an analytical two-sheet model. The validity of the approximation involved in the two-sheet model is verified by a comparison to finite element model calculations....

Research and development of a high-temperature helium-leak detection system (joint research). Part 1 survey on leakage events and current leak detection technology

Energy Technology Data Exchange (ETDEWEB)

Sakaba, Nariaki; Nakazawa, Toshio; Kawasaki, Kozo [Japan Atomic Energy Research Inst., Oarai, Ibaraki (Japan). Oarai Research Establishment; Urakami, Masao; Saisyu, Sadanori [Japan Atomic Power Co., Tokyo (Japan)

2003-03-01

In High Temperature Gas-cooled Reactors (HTGR), the detection of leakage of helium at an early stage is very important for the safety and stability of operations. Since helium is a colourless gas, it is generally difficult to identify the location and the amount of leakage when very little leakage has occurred. The purpose of this R and D is to develop a helium leak detection system for the high temperature environment appropriate to the HTGR. As the first step in the development, this paper describes the result of surveying leakage events at nuclear facilities inside and outside Japan and current gas leakage detection technology to adapt optical-fibre detection technology to HTGRs. (author)

Control phase shift of spin-wave by spin-polarized current and its application in logic gates

International Nuclear Information System (INIS)

Chen, Xiangxu; Wang, Qi; Liao, Yulong; Tang, Xiaoli; Zhang, Huaiwu; Zhong, Zhiyong

2015-01-01

We proposed a new ways to control the phase shift of propagating spin waves by applying a local spin-polarized current on ferromagnetic stripe. Micromagnetic simulation showed that a phase shift of about π can be obtained by designing appropriate width and number of pinned magnetic layers. The ways can be adopted in a Mach-Zehnder-type interferometer structure to fulfill logic NOT gates based on spin waves. - Highlights: • Spin-wave phase shift can be controlled by a local spin-polarized current. • Spin-wave phase shift increased with the increasing of current density. • Spin-wave phase shift can reach about 0.3π at a particular current density. • The ways can be used in a Mach-Zehnder-type interferometer to fulfill logic gates

Fabrication and electrical properties of metal-oxide semiconductor capacitors based on polycrystalline p-Cu{sub x}O and HfO{sub 2}/SiO{sub 2} high-{kappa} stack gate dielectrics

Energy Technology Data Exchange (ETDEWEB)

Zou Xiao [Department of Electronic Science and Technology, School of Physical Science and Technology, Wuhan University, Wuhan, 430074 (China); Department of Electromachine Engineering, Jianghan University, Wuhan, 430056 (China); Fang Guojia, E-mail: gjfang@whu.edu.c [Department of Electronic Science and Technology, School of Physical Science and Technology, Wuhan University, Wuhan, 430074 (China); Yuan Longyan; Liu Nishuang; Long Hao; Zhao Xingzhong [Department of Electronic Science and Technology, School of Physical Science and Technology, Wuhan University, Wuhan, 430074 (China)

2010-05-31

Polycrystalline p-type Cu{sub x}O films were deposited after the growth of HfO{sub 2} dielectric on Si substrate by pulsed laser deposition, and Cu{sub x}O metal-oxide-semiconductor (MOS) capacitors with HfO{sub 2}/SiO{sub 2} stack gate dielectric were primarily fabricated and investigated. X-ray diffraction and X-ray photoelectron spectroscopy were applied to analyze crystalline structure and Cu{sup +}/Cu{sup 2+} ratios of Cu{sub x}O films respectively. SiO{sub 2} interlayer formed between the high-{kappa} dielectric and substrate was estimated by the transmission electron microscope. Results of electrical characteristic measurement indicate that the permittivity of HfO{sub 2} is about 22, and the gate leakage current density of MOS capacitor with 11.3 nm HfO{sub 2}/SiO{sub 2} stack dielectrics is {approx} 10{sup -4} A/cm{sup 2}. Results also show that the annealing in N{sub 2} can improve the quality of Cu{sub x}O/HfO{sub 2} interface and thus reduce the gate leakage density.

Degradation of Ultra-Thin Gate Oxide NMOSFETs under CVDT and SHE Stresses

International Nuclear Information System (INIS)

Shi-Gang, Hu; Yan-Rong, Cao; Yue, Hao; Xiao-Hua, Ma; Chi, Chen; Xiao-Feng, Wu; Qing-Jun, Zhou

2008-01-01

Degradation of device under substrate hot-electron (SHE) and constant voltage direct-tunnelling (CVDT) stresses are studied using NMOSFET with 1.4-nm gate oxides. The degradation of device parameters and the degradation of the stress induced leakage current (SILC) under these two stresses are reported. The emphasis of this paper is on SILC and breakdown of ultra-thin-gate-oxide under these two stresses. SILC increases with stress time and several soft breakdown events occur during direct-tunnelling (DT) stress. During SHE stress, SILC firstly decreases with stress time and suddenly jumps to a high level, and no soft breakdown event is observed. For DT injection, the positive hole trapped in the oxide and hole direct-tunnelling play important roles in the breakdown. For SHE injection, it is because injected hot electrons accelerate the formation of defects and these defects formed by hot electrons induce breakdown. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

First principle leakage current reduction technique for CMOS devices

CSIR Research Space (South Africa)

Tsague, HD

2015-12-01

Full Text Available This paper presents a comprehensive study of leakage reduction techniques applicable to CMOS based devices. In the process, mathematical equations that model the power-performance trade-offs in CMOS logic circuits are presented. From those equations...

The effect of cathode bias (field effect) on the surface leakage current of CdZnTe detectors

DEFF Research Database (Denmark)

Bolotnikov, A.E.; Chen, C.M.H.; Cook, W.R.

2003-01-01

Surface resistivity is an important parameter of multi-electrode CZT detectors such as coplanar-grid, strip, or pixel detectors. Low surface resistivity results in a high leakage current and affects the charge collection efficiency in the areas near contacts. Thus, it is always desirable to have ...

Electrical Properties of Ultrathin Hf-Ti-O Higher k Gate Dielectric Films and Their Application in ETSOI MOSFET.

Science.gov (United States)

Xiong, Yuhua; Chen, Xiaoqiang; Wei, Feng; Du, Jun; Zhao, Hongbin; Tang, Zhaoyun; Tang, Bo; Wang, Wenwu; Yan, Jiang

2016-12-01

Ultrathin Hf-Ti-O higher k gate dielectric films (~2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) ~9.4%, low equivalent gate oxide thickness (EOT) of ~0.69 nm and acceptable gate leakage current density of 0.61 A/cm 2 @ (V fb  - 1)V could be obtained. The conduction mechanism through the gate dielectric is dominated by the F-N tunneling in the gate voltage range of -0.5 to -2 V. Under the same physical thickness and process flow, lower EOT and higher I on /I off ratio could be obtained while using Hf-Ti-O as gate dielectric compared with HfO 2 . With Hf-Ti-O as gate dielectric, two ETSOI PMOSFETs with gate width/gate length (W/L) of 0.5 μm/25 nm and 3 μm/40 nm show good performances such as high I on , I on /I off ratio in the magnitude of 10 5 , and peak transconductance, as well as suitable threshold voltage (-0.3~-0.2 V). Particularly, ETSOI PMOSFETs show superior short-channel control capacity with DIBL <82 mV/V and subthreshold swing <70 mV/decade.

Effects of vacuum ultraviolet irradiation on trapped charges and leakage currents of low-k organosilicate dielectrics

Energy Technology Data Exchange (ETDEWEB)

Zheng, H.; Guo, X.; Pei, D.; Shohet, J. L. [Plasma Processing and Technology Laboratory and Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States); Ryan, E. T. [GLOBALFOUNDRIES, Albany, New York 12203 (United States); Nishi, Y. [Stanford University, Stanford, California 94305 (United States)

2015-05-11

Vacuum ultraviolet (VUV) photoemission spectroscopy is utilized to investigate the distribution of trapped charges within the bandgap of low dielectric constant (low-k) organosilicate (SiCOH) materials. It was found that trapped charges are continuously distributed within the bandgap of porous SiCOH and the center of the trapped states is 1.3 eV above the valence band of the tested sample. By comparing photoemission spectroscopic results before and after VUV exposure, VUV irradiation with photon energies between 7.6 and 8.9 eV was found to deplete trapped charge while UV exposure with photon energies less than 6.0 eV induces more trapped charges in tested samples. Current-Voltage (IV) characteristics results show that the reliability of dielectrics is improved after VUV irradiation with photon energies between 7.6 and 8.9 eV, while UV exposure results in an increased level of leakage current and a decreased breakdown voltage, both of which are harmful to the reliability of the dielectric. This work shows that VUV irradiation holds the potential to substitute for UV curing in microelectronic processing to improve the reliability of low-k dielectrics by mitigating the leakage currents and trapped charges induced by UV irradiation.

Tungsten trioxide as high-{kappa} gate dielectric for highly transparent and temperature-stable zinc-oxide-based thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Lorenz, Michael; Wenckstern, Holger von; Grundmann, Marius [Universitaet Leipzig, Fakultaet fuer Physik und Geowissenschaften, Institut fuer Experimentelle Physik II, Linnestr. 5, 04103 Leipzig (Germany)

2012-07-01

We demonstrate metal-insulator-semiconductor field-effect transistors with high-{kappa}, room-temperature deposited, highly transparent tungsten trioxide (WO{sub 3}) as gate dielectric. The channel material consists of a zinc oxide (ZnO) thin-film. The transmittance and resistivity of WO{sub 3} films was tuned in order to obtain a highly transparent and insulating WO{sub 3} dielectric. The devices were processed by standard photolithography using lift-off technique. On top of the WO{sub 3} dielectric a highly transparent and conductive oxide consisting of ZnO: Al 3% wt. was deposited. The gate structure of the devices exhibits an average transmittance in the visible spectral range of 86%. The on/off-current ratio is larger than 10{sup 8} with off- and gate leakage-currents below 3 x 10{sup -8} A/cm{sup 2}. Due to the high relative permittivity of {epsilon}{sub r} {approx} 70, a gate voltage sweep of only 2 V is necessary to turn the transistor on and off with a minimum subthreshold swing of 80 mV/decade. The channel mobility of the transistors equals the Hall-effect mobility with a value of 5 cm{sup 2}/Vs. It is furthermore shown, that the devices are stable up to operating temperatures of at least 150 C.

SU-E-T-66: Characterization of Radiation Dose Associated with Dark Currents During Beam Hold for Respiratory-Gated Electron Therapy

International Nuclear Information System (INIS)

Hessler, J; Gupta, N; Rong, Y; Weldon, M

2014-01-01

Purpose: The main objective of this study was to estimate the radiation dose contributed by dark currents associated with the respiratory-gated electron therapy during beam hold. The secondary aim was to determine clinical benefits of using respiratory-gated electron therapy for left-sided breast cancer patients with positive internal mammary nodes (IMN). Methods: Measurements of the dark current-induced dose in all electron modes were performed on multiple Siemens and Varian linear accelerators by manually simulating beam-hold during respiratory gating. Dose was quantified at the machine isocenter by comparing the collected charge to the known output for all energies ranging from 6 to 18 MeV for a 10cm × 10cm field at 100 SSD with appropriate solid-water buildup. Using the Eclipse treatment planning system, we compared the additional dose associated with dark current using gated electron fields to the dose uncertainties associated with matching gated photon fields and ungated electron fields. Dose uncertainties were seen as hot and cold spots along the match line of the fields. Results: The magnitude of the dose associated with dark current is highly correlated to the energy of the beam and the amount of time the beam is on hold. For lower energies (6–12 MeV), there was minimal dark current dose (0.1–1.3 cGy/min). Higher energies (15–18 MeV) showed measurable amount of doses. The dark current associated with the electron beam-hold varied between linear accelerator vendors and depended on dark current suppression and the age of the linear accelerator. Conclusion: For energies up to 12 MeV, the dose associated with the dark current for respiratorygated electron therapy was shown to be negligible, and therefore should be considered an option for treating IMN positive left-sided breast cancer patients. However, at higher energies the benefit of respiratory gating may be outweighed by dose due to the dark current

Power gating of VLSI circuits using MEMS switches in low power applications

KAUST Repository

Shobak, Hosam; Ghoneim, Mohamed T.; El Boghdady, Nawal; Halawa, Sarah; Iskander, Sophinese M.; Anis, Mohab H.

2011-01-01

-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result

Modulation of voltage-gated channel currents by harmaline and harmane.

Science.gov (United States)

Splettstoesser, Frank; Bonnet, Udo; Wiemann, Martin; Bingmann, Dieter; Büsselberg, Dietrich

2005-01-01

Harmala alkaloids are endogenous substances, which are involved in neurodegenerative disorders such as M. Parkinson, but some of them also have neuroprotective effects in the nervous system. While several sites of action at the cellular level (e.g. benzodiazepine receptors, 5-HT and GABA(A) receptors) have been identified, there is no report on how harmala alkaloids interact with voltage-gated membrane channels. The aim of this study was to investigate the effects of harmaline and harmane on voltage-activated calcium- (I(Ca(V))), sodium- (I(Na(V))) and potassium (I(K(V)))-channel currents, using the whole-cell patch-clamp method with cultured dorsal root ganglion neurones of 3-week-old rats. Currents were elicited by voltage steps from the holding potential to different command potentials. Harmaline and harmane reduced I(Ca(V)), I(Na(V)) and I(K(V)) concentration-dependent (10-500 microM) over the voltage range tested. I(Ca(V)) was reduced with an IC(50) of 100.6 microM for harmaline and by a significantly lower concentration of 75.8 microM (P<0.001, t-test) for harmane. The Hill coefficient was close to 1. Threshold concentration was around 10 microM for both substances. The steady state of inhibition of I(Ca(V)) by harmaline or harmane was reached within several minutes. The action was not use-dependent and at least partly reversible. It was mainly due to a reduction in the sustained calcium channel current (I(Ca(L+N))), while the transient voltage-gated calcium channel current (I(Ca(T))) was only partially affected. We conclude that harmaline and harmane are modulators of I(Ca(V)) in vitro. This might be related to their neuroprotective effects.

Apparatus for detecting leakage of liquid sodium

Science.gov (United States)

Himeno, Yoshiaki

1978-01-01

An apparatus for detecting the leakage of liquid sodium includes a cable-like sensor adapted to be secured to a wall of piping or other equipment having sodium on the opposite side of the wall, and the sensor includes a core wire electrically connected to the wall through a leak current detector and a power source. An accidental leakage of the liquid sodium causes the corrosion of a metallic layer and an insulative layer of the sensor by products resulted from a reaction of sodium with water or oxygen in the atmospheric air so as to decrease the resistance between the core wire and the wall. Thus, the leakage is detected as an increase in the leaking electrical current. The apparatus is especially adapted for use in detecting the leakage of liquid sodium from sodium-conveying pipes or equipment in a fast breeder reactor.

Low-voltage organic field-effect transistors based on novel high-κ organometallic lanthanide complex for gate insulating materials

Directory of Open Access Journals (Sweden)

Qi Liu

2014-08-01

Full Text Available A novel high-κ organometallic lanthanide complex, Eu(tta3L (tta=2-thenoyltrifluoroacetonate, L = 4,5-pinene bipyridine, is used as gate insulating material to fabricate low-voltage pentacene field-effect transistors (FETs. The optimized gate insulator exhibits the excellent properties such as low leakage current density, low surface roughness, and high dielectric constant. When operated under a low voltage of −5 V, the pentacene FET devices show the attractive electrical performance, e.g. carrier mobility (μFET of 0.17 cm2 V−1 s−1, threshold voltage (Vth of −0.9 V, on/off current ratio of 5 × 103, and subthreshold slope (SS of 1.0 V dec−1, which is much better than that of devices obtained on conventional 300 nm SiO2 substrate (0.13 cm2 V−1 s−1, −7.3 V and 3.1 V dec−1 for μFET, Vth and SS value when operated at −30 V. These results indicate that this kind of high-κ organometallic lanthanide complex becomes a promising candidate as gate insulator for low-voltage organic FETs.

Analysis of Reverse-Bias Leakage Current Mechanisms in Metal/GaN Schottky Diodes

Directory of Open Access Journals (Sweden)

P. Pipinys

2010-01-01

Full Text Available Temperature-dependent reverse-bias current-voltage characteristics obtained by other researchers for Schottky diodes fabricated on GaN are reinterpreted in terms of phonon-assisted tunneling (PhAT model. Temperature dependence of reverse-bias leakage current is shown could be caused by the temperature dependence of electron tunneling rate from traps in the metal-semiconductor interface to the conduction band of semiconductor. A good fit of experimental data with the theory is received in a wide temperature range (from 80 K to 500 K using for calculation the effective mass of 0.222 me. and for the phonon energy the value of 70 meV. The temperature and bias voltages dependences of an apparent barrier height (activation energy are also explicable in the framework of the PhAT model.

Leakage current conduction mechanisms and electrical properties of atomic-layer-deposited HfO2/Ga2O3 MOS capacitors

Science.gov (United States)

Zhang, Hongpeng; Jia, Renxu; Lei, Yuan; Tang, Xiaoyan; Zhang, Yimen; Zhang, Yuming

2018-02-01

In this paper, current conduction mechanisms in HfO2/β-Ga2O3 metal-oxide-semiconductor (MOS) capacitors under positive and negative biases are investigated using the current-voltage (I-V) measurements conducted at temperatures from 298 K to 378 K. The Schottky emission is dominant under positively biased electric fields of 0.37-2.19 MV cm-1, and the extracted Schottky barrier height ranged from 0.88 eV to 0.91 eV at various temperatures. The Poole-Frenkel emission dominates under negatively biased fields of 1.92-4.83 MV cm-1, and the trap energy levels are from 0.71 eV to 0.77 eV at various temperatures. The conduction band offset (ΔE c) of HfO2/β-Ga2O3 is extracted to be 1.31  ±  0.05 eV via x-ray photoelectron spectroscopy, while a large negative sheet charge density of 1.04  ×  1013 cm-2 is induced at the oxide layer and/or HfO2/β-Ga2O3 interface. A low C-V hysteresis of 0.76 V, low interface state density (D it) close to 1  ×  1012 eV-1 cm-2, and low leakage current density of 2.38  ×  10-5 A cm-2 at a gate voltage of 7 V has been obtained, suggesting the great electrical properties of HfO2/β-Ga2O3 MOSCAP. According to the above analysis, ALD-HfO2 is an attractive candidate for high voltage β-Ga2O3 power devices.

Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID: Device and Circuit Co-Design

Directory of Open Access Journals (Sweden)

Tony T. Kim

2011-07-01

Full Text Available Recently, double-gate MOSFETs (DGMOSFETs have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for strong inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier design, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32 nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption.

An analytical drain current model for symmetric double-gate MOSFETs

Science.gov (United States)

Yu, Fei; Huang, Gongyi; Lin, Wei; Xu, Chuanzhong

2018-04-01

An analytical surface-potential-based drain current model of symmetric double-gate (sDG) MOSFETs is described as a SPICE compatible model in this paper. The continuous surface and central potentials from the accumulation to the strong inversion regions are solved from the 1-D Poisson's equation in sDG MOSFETs. Furthermore, the drain current is derived from the charge sheet model as a function of the surface potential. Over a wide range of terminal voltages, doping concentrations, and device geometries, the surface potential calculation scheme and drain current model are verified by solving the 1-D Poisson's equation based on the least square method and using the Silvaco Atlas simulation results and experimental data, respectively. Such a model can be adopted as a useful platform to develop the circuit simulator and provide the clear understanding of sDG MOSFET device physics.

Mechanistic analysis of temperature-dependent current conduction through thin tunnel oxide in n+-polySi/SiO2/n+-Si structures

Science.gov (United States)

Samanta, Piyas

2017-09-01

We present a detailed investigation on temperature-dependent current conduction through thin tunnel oxides grown on degenerately doped n-type silicon (n+-Si) under positive bias ( VG ) on heavily doped n-type polycrystalline silicon (n+-polySi) gate in metal-oxide-semiconductor devices. The leakage current measured between 298 and 573 K and at oxide fields ranging from 6 to 10 MV/cm is primarily attributed to Poole-Frenkel (PF) emission of trapped electrons from the neutral electron traps located in the silicon dioxide (SiO2) band gap in addition to Fowler-Nordheim (FN) tunneling of electrons from n+-Si acting as the drain node in FLOating gate Tunnel OXide Electrically Erasable Programmable Read-Only Memory devices. Process-induced neutral electron traps are located at 0.18 eV and 0.9 eV below the SiO2 conduction band. Throughout the temperature range studied here, PF emission current IPF dominates FN electron tunneling current IFN at oxide electric fields Eox between 6 and 10 MV/cm. A physics based new analytical formula has been developed for FN tunneling of electrons from the accumulation layer of degenerate semiconductors at a wide range of temperatures incorporating the image force barrier rounding effect. FN tunneling has been formulated in the framework of Wentzel-Kramers-Brilloiun taking into account the correction factor due to abrupt variation of the energy barrier at the cathode/oxide interface. The effect of interfacial and near-interfacial trapped-oxide charges on FN tunneling has also been investigated in detail at positive VG . The mechanism of leakage current conduction through SiO2 films plays a crucial role in simulation of time-dependent dielectric breakdown of the memory devices and to precisely predict the normal operating field or applied floating gate (FG) voltage for lifetime projection of the devices. In addition, we present theoretical results showing the effect of drain doping concentration on the FG leakage current.

High-current and low acceleration voltage arsenic ion implanted polysilicon-gate and source-drain electrode Si mos transistor

International Nuclear Information System (INIS)

Saito, Yasuyuki; Sugimura, Yoshiro; Sugihara, Michiyuki

1993-01-01

The fabrication process of high current arsenic (As) ion implanted polysilicon (Si) gate and source drain (SD) electrode Si n-channel metal oxide-semiconductor field effect transistor (MOSFET) was examined. Poly Si film n-type doping was performed by using high current (typical current: 2mA) and relatively low acceleration voltage (40keV) As ion implantation technique (Lintott series 3). It was observed that high dose As implanted poly Si films as is show refractoriness against radical fluorine excited by microwave. Using GCA MANN4800 (m/c ID No.2, resist: OFPR) mask pattern printing technique, the high current As ion implantation technique and radical fluorine gas phase etching (Chemical dry etching: CDE) technique, the n-channel Poly Si gate (ρs = ≅100Ω/□) enhancement MQSFETs(ρs source drain = ≅50Ω/□, SiO 2 gate=380 angstrom) with off-leak-less were obtained on 3 inch Czochralski grown 2Ωcm boron doped p type wafers (Osaka titanium). By the same process, a 8 bit single chip μ-processor with 26MHz full operation was performed

Effect of ZnO channel thickness on the device behaviour of nonvolatile memory thin film transistors with double-layered gate insulators of Al2O3 and ferroelectric polymer

International Nuclear Information System (INIS)

Yoon, Sung-Min; Yang, Shin-Hyuk; Ko Park, Sang-Hee; Jung, Soon-Won; Cho, Doo-Hee; Byun, Chun-Won; Kang, Seung-Youl; Hwang, Chi-Sun; Yu, Byoung-Gon

2009-01-01

Poly(vinylidene fluoride trifluoroethylene) and ZnO were employed for nonvolatile memory thin film transistors as ferroelectric gate insulator and oxide semiconducting channel layers, respectively. It was proposed that the thickness of the ZnO layer be carefully controlled for realizing the lower programming voltage, because the serially connected capacitor by the formation of a fully depleted ZnO channel had a critical effect on the off programming voltage. The fabricated memory transistor with Al/P(VDF-TrFE) (80 nm)/Al 2 O 3 (4 nm)/ZnO (5 nm) exhibits encouraging behaviour such as a memory window of 3.8 V at the gate voltage of -10 to 12 V, and 10 7 on/off ratio, and a gate leakage current of 10 -11 A.

Effect of atomic layer deposition temperature on current conduction in Al{sub 2}O{sub 3} films formed using H{sub 2}O oxidant

Energy Technology Data Exchange (ETDEWEB)

Hiraiwa, Atsushi, E-mail: hiraiwa@aoni.waseda.jp, E-mail: qs4a-hriw@asahi-net.or.jp [Research Organization for Nano and Life Innovation, Waseda University, 513 Waseda-Tsurumaki, Shinjuku, Tokyo 162-0041 (Japan); Matsumura, Daisuke [Faculty of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kawarada, Hiroshi, E-mail: kawarada@waseda.jp [Research Organization for Nano and Life Innovation, Waseda University, 513 Waseda-Tsurumaki, Shinjuku, Tokyo 162-0041 (Japan); Faculty of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); The Kagami Memorial Laboratory for Materials Science and Technology, Waseda University, 2-8-26 Nishiwaseda, Shinjuku, Tokyo 169-0051 (Japan)

2016-08-28

To develop high-performance, high-reliability gate insulation and surface passivation technologies for wide-bandgap semiconductor devices, the effect of atomic layer deposition (ALD) temperature on current conduction in Al{sub 2}O{sub 3} films is investigated based on the recently proposed space-charge-controlled field emission model. Leakage current measurement shows that Al{sub 2}O{sub 3} metal-insulator-semiconductor capacitors formed on the Si substrates underperform thermally grown SiO{sub 2} capacitors at the same average field. However, using equivalent oxide field as a more practical measure, the Al{sub 2}O{sub 3} capacitors are found to outperform the SiO{sub 2} capacitors in the cases where the capacitors are negatively biased and the gate material is adequately selected to reduce virtual dipoles at the gate/Al{sub 2}O{sub 3} interface. The Al{sub 2}O{sub 3} electron affinity increases with the increasing ALD temperature, but the gate-side virtual dipoles are not affected. Therefore, the leakage current of negatively biased Al{sub 2}O{sub 3} capacitors is approximately independent of the ALD temperature because of the compensation of the opposite effects of increased electron affinity and permittivity in Al{sub 2}O{sub 3}. By contrast, the substrate-side sheet of charge increases with increasing ALD temperature above 210 °C and hence enhances the current of positively biased Al{sub 2}O{sub 3} capacitors more significantly at high temperatures. Additionally, an anomalous oscillatory shift of the current-voltage characteristics with ALD temperature was observed in positively biased capacitors formed by low-temperature (≤210 °C) ALD. This shift is caused by dipoles at the Al{sub 2}O{sub 3}/underlying SiO{sub 2} interface. Although they have a minimal positive-bias leakage current, the low-temperature-grown Al{sub 2}O{sub 3} films cause the so-called blisters problem when heated above 400 °C. Therefore, because of the absence of blistering, a 450�

100-nm gate lithography for double-gate transistors

Science.gov (United States)

Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

2001-09-01

The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

GaN-Based High-k Praseodymium Oxide Gate MISFETs with P2S5/(NH42SX + UV Interface Treatment Technology

Directory of Open Access Journals (Sweden)

Chao-Wei Lin

2012-01-01

Full Text Available This study examines the praseodymium-oxide- (Pr2O3- passivated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs with high dielectric constant in which the AlGaN Schottky layers are treated with P2S5/(NH42SX + ultraviolet (UV illumination. An electron-beam evaporated Pr2O3 insulator is used instead of traditional plasma-assisted chemical vapor deposition (PECVD, in order to prevent plasma-induced damage to the AlGaN. In this work, the HEMTs are pretreated with P2S5/(NH42SX solution and UV illumination before the gate insulator (Pr2O3 is deposited. Since stable sulfur that is bound to the Ga species can be obtained easily and surface oxygen atoms are reduced by the P2S5/(NH42SX pretreatment, the lowest leakage current is observed in MIS-HEMT. Additionally, a low flicker noise and a low surface roughness (0.38 nm are also obtained using this novel process, which demonstrates its ability to reduce the surface states. Low gate leakage current Pr2O3 and high-k AlGaN/GaN MIS-HEMTs, with P2S5/(NH42SX + UV illumination treatment, are suited to low-noise applications, because of the electron-beam-evaporated insulator and the new chemical pretreatment.

Leakage and sweet spots in triple-quantum-dot spin qubits: A molecular-orbital study

Science.gov (United States)

Zhang, Chengxian; Yang, Xu-Chen; Wang, Xin

2018-04-01

A triple-quantum-dot system can be operated as either an exchange-only qubit or a resonant-exchange qubit. While it is generally believed that the decisive advantage of the resonant-exchange qubit is the suppression of charge noise because it is operated at a sweet spot, we show that the leakage is also an important factor. Through molecular-orbital-theoretic calculations, we show that when the system is operated in the exchange-only scheme, the leakage to states with double electron occupancy in quantum dots is severe when rotations around the axis 120∘ from z ̂ is performed. While this leakage can be reduced by either shrinking the dots or separating them further, the exchange interactions are also suppressed at the same time, making the gate operations unfavorably slow. When the system is operated as a resonant-exchange qubit, the leakage is three to five orders of magnitude smaller. We have also calculated the optimal detuning point which minimizes the leakage for the resonant-exchange qubit, and have found that although it does not coincide with the double sweet spot for the charge noise, they are rather close. Our results suggest that the resonant-exchange qubit has another advantage, that leakage can be greatly suppressed compared to the exchange-only qubit, and operating at the double sweet spot point should be optimal both for reducing charge noise and suppressing leakage.

Direct observation of the leakage current in epitaxial diamond Schottky barrier devices by conductive-probe atomic force microscopy and Raman imaging

Science.gov (United States)

Alvarez, J.; Boutchich, M.; Kleider, J. P.; Teraji, T.; Koide, Y.

2014-09-01

The origin of the high leakage current measured in several vertical-type diamond Schottky devices is conjointly investigated by conducting probe atomic force microscopy and confocal micro-Raman/photoluminescence imaging analysis. Local areas characterized by a strong decrease of the local resistance (5-6 orders of magnitude drop) with respect to their close surrounding have been identified in several different regions of the sample surface. The same local areas, also referenced as electrical hot-spots, reveal a slightly constrained diamond lattice and three dominant Raman bands in the low-wavenumber region (590, 914 and 1040 cm-1). These latter bands are usually assigned to the vibrational modes involving boron impurities and its possible complexes that can electrically act as traps for charge carriers. Local current-voltage measurements performed at the hot-spots point out a trap-filled-limited current as the main conduction mechanism favouring the leakage current in the Schottky devices.

An analytical drain current model for symmetric double-gate MOSFETs

Directory of Open Access Journals (Sweden)

Fei Yu

2018-04-01

Full Text Available An analytical surface-potential-based drain current model of symmetric double-gate (sDG MOSFETs is described as a SPICE compatible model in this paper. The continuous surface and central potentials from the accumulation to the strong inversion regions are solved from the 1-D Poisson’s equation in sDG MOSFETs. Furthermore, the drain current is derived from the charge sheet model as a function of the surface potential. Over a wide range of terminal voltages, doping concentrations, and device geometries, the surface potential calculation scheme and drain current model are verified by solving the 1-D Poisson’s equation based on the least square method and using the Silvaco Atlas simulation results and experimental data, respectively. Such a model can be adopted as a useful platform to develop the circuit simulator and provide the clear understanding of sDG MOSFET device physics.

Development and characterization of ultrathin hafnium titanates as high permittivity gate insulators

Science.gov (United States)

Li, Min

High permittivity or high-kappa materials are being developed for use as gate insulators for future ultrascaled metal oxide semiconductor field effect transistors (MOSFETs). Hafnium containing compounds are the leading candidates. Due to its moderate permittivity, however, it is difficult to achieve HfO2 gate structures with an EOT well below 1.0 nm. One approach to increase HfO2 permittivity is combining it with a very high-kappa material, such as TiO2. In this thesis, we systematically studied the electrical and physical characteristics of high-kappa hafnium titanates films as gate insulators. A series of HfxTi1-xO2 films with well-controlled composition were deposited using an MOCVD system. The physical properties of the films were analyzed using a variety of characterization techniques. X-ray micro diffraction indicates that the Ti-rich thin film is more immune to crystallization. TEM analysis showed that the thick stoichiometric HfTiO 4 film has an orthorhombic structure and large anisotropic grains. The C-V curves from the devices with the hafnium titanates films displayed relatively low hysteresis. In a certain composition range, the interfacial layer (IL) EOT and permittivity of HfxTi1-x O2 increases linearly with increasing Ti. The charge is negative for HfxTi1-xO2/IL and positive for Si/IL interface, and the magnitude increases as Hf increases. For ultra-thin films (less than 2 nm EOT), the leakage current increases with increasing HE Moreover, the Hf-rich sample has weaker temperature dependence of the current. In the MOSFET devices with the hafnium titanates films, normal transistor characteristics were observed, also electron mobility degradation. Next, we investigated the effects that different pre-deposition surface treatments, including HF dipping, NH3 surface nitridation, and HfO2 deposition, have on the electrical properties of hafnium titanates. Surface nitridation shows stronger effect than the thin HfO2 layer. The nitrided samples displayed a

Thickness engineering of atomic layer deposited Al2O3 films to suppress interfacial reaction and diffusion of Ni/Au gate metal in AlGaN/GaN HEMTs up to 600 °C in air

Science.gov (United States)

Suria, Ateeq J.; Yalamarthy, Ananth Saran; Heuser, Thomas A.; Bruefach, Alexandra; Chapin, Caitlin A.; So, Hongyun; Senesky, Debbie G.

2017-06-01

In this paper, we describe the use of 50 nm atomic layer deposited (ALD) Al2O3 to suppress the interfacial reaction and inter-diffusion between the gate metal and semiconductor interface, to extend the operation limit up to 600 °C in air. Suppression of diffusion is verified through Auger electron spectroscopy (AES) depth profiling and X-ray diffraction (XRD) and is further supported with electrical characterization. An ALD Al2O3 thin film (10 nm and 50 nm), which functions as a dielectric layer, was inserted between the gate metal (Ni/Au) and heterostructure-based semiconductor material (AlGaN/GaN) to form a metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). This extended the 50 nm ALD Al2O3 MIS-HEMT (50-MIS) current-voltage (Ids-Vds) and gate leakage (Ig,leakage) characteristics up to 600 °C. Both, the 10 nm ALD Al2O3 MIS-HEMT (10-MIS) and HEMT, failed above 350 °C, as evidenced by a sudden increase of approximately 50 times and 5.3 × 106 times in Ig,leakage, respectively. AES on the HEMT revealed the formation of a Ni-Au alloy and Ni present in the active region. Additionally, XRD showed existence of metal gallides in the HEMT. The 50-MIS enables the operation of AlGaN/GaN based electronics in oxidizing high-temperature environments, by suppressing interfacial reaction and inter-diffusion of the gate metal with the semiconductor.

Medium band gap polymer based solution-processed high-κ composite gate dielectrics for ambipolar OFET

Science.gov (United States)

Canımkurbey, Betül; Unay, Hande; Çakırlar, Çiğdem; Büyükköse, Serkan; Çırpan, Ali; Berber, Savas; Altürk Parlak, Elif

2018-03-01

The authors present a novel ambipolar organic filed-effect transistors (OFETs) composed of a hybrid dielectric thin film of Ta2O5:PMMA nanocomposite material, and solution processed poly(selenophene, benzotriazole and dialkoxy substituted [1,2-b:4, 5-b‧] dithiophene (P-SBTBDT)-based organic semiconducting material as the active layer of the device. We find that the Ta2O5:PMMA insulator shows n-type conduction character, and its combination with the p-type P-SBTBDT organic semiconductor leads to an ambipolar OFET device. Top-gated OFETs were fabricated on glass substrate consisting of interdigitated ITO electrodes. P-SBTBDT-based material was spin coated on the interdigitated ITO electrodes. Subsequently, a solution processed Ta2O5:PMMA nanocomposite material was spin coated, thereby creating the gate dielectric layer. Finally, as a gate metal, an aluminum layer was deposited by thermal evaporation. The fabricated OFETs exhibited an ambipolar performance with good air-stability, high field-induced current and relatively high electron and hole mobilities although Ta2O5:PMMA nanocomposite films have slightly higher leakage current compared to the pure Ta2O5 films. Dielectric properties of the devices with different ratios of Ta2O5:PMMA were also investigated. The dielectric constant varied between 3.6 and 5.3 at 100 Hz, depending on the Ta2O5:PMMA ratio.

Hyperpolarization-activated inward leakage currents caused by deletion or mutation of carboxy-terminal tyrosines of the Na+/K+-ATPase {alpha} subunit.

Science.gov (United States)

Meier, Susan; Tavraz, Neslihan N; Dürr, Katharina L; Friedrich, Thomas

2010-02-01

The Na(+)/K(+)-ATPase mediates electrogenic transport by exporting three Na(+) ions in exchange for two K(+) ions across the cell membrane per adenosine triphosphate molecule. The location of two Rb(+) ions in the crystal structures of the Na(+)/K(+)-ATPase has defined two "common" cation binding sites, I and II, which accommodate Na(+) or K(+) ions during transport. The configuration of site III is still unknown, but the crystal structure has suggested a critical role of the carboxy-terminal KETYY motif for the formation of this "unique" Na(+) binding site. Our two-electrode voltage clamp experiments on Xenopus oocytes show that deletion of two tyrosines at the carboxy terminus of the human Na(+)/K(+)-ATPase alpha(2) subunit decreases the affinity for extracellular and intracellular Na(+), in agreement with previous biochemical studies. Apparently, the DeltaYY deletion changes Na(+) affinity at site III but leaves the common sites unaffected, whereas the more extensive DeltaKETYY deletion affects the unique site and the common sites as well. In the absence of extracellular K(+), the DeltaYY construct mediated ouabain-sensitive, hyperpolarization-activated inward currents, which were Na(+) dependent and increased with acidification. Furthermore, the voltage dependence of rate constants from transient currents under Na(+)/Na(+) exchange conditions was reversed, and the amounts of charge transported upon voltage pulses from a certain holding potential to hyperpolarizing potentials and back were unequal. These findings are incompatible with a reversible and exclusively extracellular Na(+) release/binding mechanism. In analogy to the mechanism proposed for the H(+) leak currents of the wild-type Na(+)/K(+)-ATPase, we suggest that the DeltaYY deletion lowers the energy barrier for the intracellular Na(+) occlusion reaction, thus destabilizing the Na(+)-occluded state and enabling inward leak currents. The leakage currents are prevented by aromatic amino acids at the

Gating-by-rotation: a solution to the problem of intratreatment motion in helical tomotherapy

International Nuclear Information System (INIS)

Kapatoes, J.M.; Olivera, G.H.; Schloesser, E.A.; Pearson, D.W.; Balog, J.P.; Ruchala, K.J.; Schmidt, R.; Reckwerdt, P.J.; Mehta, M.P.; Mackie, T.R.

2001-01-01

Purpose: To assess the feasibility of addressing intratreatment motion issues in helical tomotherapy by gating the treatments by rotation. Intratreatment motion is a problem common to all IMRT techniques. Traditional methods of gating in conformal radiotherapy and some forms of IMRT are not applicable to helical tomotherapy due to the continuous rotation of the gantry. An alternative method is presented. Materials and Methods: Rotation-gating in helical tomotherapy is the process in which one rotation of treatment is immediately followed by a rotation of non-treatment. This on-off strategy is repeated for the full treatment volume. During the treatment rotations, the patient is required to hold their breath while the intensity-modulated fan beam deposits dose. For the non-treatment rotations, the patient is allowed to breathe freely as all leaves of the MLC will be closed, the accelerator disabled, or both. The couch indexes normally for treatment rotations and holds the patient stationary during non-treatment rotations. An investigation was conducted to assess the feasibility of rotation-gating. Film was placed between two hemispheres of a water phantom and a continuous helical delivery was carried out with all leaves opened. The film was replaced and another treatment was performed employing rotation-gating. The two films were compared to assess the process. The films were irradiated to dose levels within the linear region of the film response curve (maximum film dose ∼35 cGy). Films were also acquired with all leaves closed to quantify leakage dose through the collimation systems. Results: Central profiles for the inferior-superior direction (parallel to the direction of translation) for both films are displayed in Figure 1. The profiles agree very well, illustrating that a rotation-gated treatment closely mimics a continuous helical delivery. The only significant discrepancy lay in the tails of the profiles: a higher film dose is seen for the rotation-gated

An accurate low current measurement circuit for heavy iron beam current monitor

International Nuclear Information System (INIS)

Zhou Chaoyang; Su Hong; Mao Ruishi; Dong Chengfu; Qian Yi; Kong Jie

2012-01-01

Heavy-ion beams at 10 6 particles per second have been applied to the treatment of deep-seated inoperable tumors in the therapy terminal of the Heavy Ion Research Facility in Lanzhou (HIRFL) which is located at the Institute of Modern Physics, Chinese Academy of Sciences (IMP, CAS). An accurate low current measurement circuit following a Faraday cup was developed to monitor the beam current at pA range. The circuit consisted of a picoammeter with a bandwidth of 1 kHz and a gated integrator (GI). A low input bias current precision amplifier and new guarding and shielding techniques were used in the picoammeter circuit which allowed as to measure current less than 1 pA with a current gain of 0.22 V/pA and noise less than 10 fA. This paper will also describe a novel compensation approach which reduced the charge injection from switches in the GI to 10 −18 C, and a T-switch configuration which was used to eliminate leakage current in the reset switch.

Low voltage operation of IGZO thin film transistors enabled by ultrathin Al2O3 gate dielectric

Science.gov (United States)

Ma, Pengfei; Du, Lulu; Wang, Yiming; Jiang, Ran; Xin, Qian; Li, Yuxiang; Song, Aimin

2018-01-01

An ultrathin, 5 nm, Al2O3 film grown by atomic-layer deposition was used as a gate dielectric for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The Al2O3 layer showed a low surface roughness of 0.15 nm, a low leakage current, and a high breakdown voltage of 6 V. In particular, a very high gate capacitance of 720 nF/cm2 was achieved, making it possible for the a-IGZO TFTs to not only operate at a low voltage of 1 V but also exhibit desirable properties including a low threshold voltage of 0.3 V, a small subthreshold swing of 100 mV/decade, and a high on/off current ratio of 1.2 × 107. Furthermore, even under an ultralow operation voltage of 0.6 V, well-behaved transistor characteristics were still observed with an on/off ratio as high as 3 × 106. The electron transport through the Al2O3 layer has also been analyzed, indicating the Fowler-Nordheim tunneling mechanism.

Interfacial characteristics and leakage current transfer mechanisms in organometal trihalide perovskite gate-controlled devices via doping of PCBM

International Nuclear Information System (INIS)

Wang, Yucheng; Zhang, Yuming; Liu, Yintao; Pang, Tiqiang; Luan, Suzhen; Jia, Renxu; Hu, Ziyang; Zhu, Yuejin

2017-01-01

Two types of perovskite (with and without doping of PCBM) based metal-oxide-semiconductor (MOS) gate-controlled devices were fabricated and characterized. The study of the interfacial characteristics and charge transfer mechanisms by doping of PCBM were analyzed by material and electrical measurements. Doping of PCBM does not affect the size and crystallinity of perovskite films, but has an impact on carrier extraction in perovskite MOS devices. The electrical hysteresis observed in capacitance–voltage and current–voltage measurements can be alleviated by doping of PCBM. Experimental results demonstrate that extremely low trap densities are found for the perovskite device without doping, while the doped sample leads to higher density of interface state. Three mechanisms including Ohm’s law, trap-filled-limit (TFL) emission, and child’s law were used to analyze possible charge transfer mechanisms. Ohm’s law mechanism is well suitable for charge transfer of both the perovskite MOS devices under light condition at large voltage, while TFL emission well addresses the behavior of charge transfer under dark at small voltage. This change of charge transfer mechanism is attributed to the impact of the ion drift within perovskites. (paper)

PERFORMANCE OF LEAKAGE POWER MINIMIZATION TECHNIQUE FOR CMOS VLSI TECHNOLOGY

Directory of Open Access Journals (Sweden)

T. Tharaneeswaran

2012-06-01

Full Text Available Leakage power of CMOS VLSI Technology is a great concern. To reduce leakage power in CMOS circuits, a Leakage Power Minimiza-tion Technique (LPMT is implemented in this paper. Leakage cur-rents are monitored and compared. The Comparator kicks the charge pump to give body voltage (Vbody. Simulations of these circuits are done using TSMC 0.35µm technology with various operating temper-atures. Current steering Digital-to-Analog Converter (CSDAC is used as test core to validate the idea. The Test core (eg.8-bit CSDAC had power consumption of 347.63 mW. LPMT circuit alone consumes power of 6.3405 mW. This technique results in reduction of leakage power of 8-bit CSDAC by 5.51mW and increases the reliability of test core. Mentor Graphics ELDO and EZ-wave are used for simulations.

Poly(methyl methacrylate) as a self-assembled gate dielectric for graphene field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Sanne, A.; Movva, H. C. P.; Kang, S.; McClellan, C.; Corbet, C. M.; Banerjee, S. K. [Microelectronics Research Center, University of Texas, Austin, Texas 78758 (United States)

2014-02-24

We investigate poly(methyl methacrylate) (PMMA) as a low thermal budget organic gate dielectric for graphene field effect-transistors (GFETs) based on a simple process flow. We show that high temperature baking steps above the glass transition temperature (∼130 °C) can leave a self-assembled, thin PMMA film on graphene, where we get a gate dielectric almost for “free” without additional atomic layer deposition type steps. Electrical characterization of GFETs with PMMA as a gate dielectric yields a dielectric constant of k = 3.0. GFETs with thinner PMMA dielectrics have a lower dielectric constant due to decreased polarization arising from neutralization of dipoles and charged carriers as baking temperatures increase. The leakage through PMMA gate dielectric increases with decreasing dielectric thickness and increasing electric field. Unlike conventional high-k gate dielectrics, such low-k organic gate dielectrics are potentially attractive for devices such as the proposed Bilayer pseudoSpin Field-Effect Transistor or flexible high speed graphene electronics.

Low-voltage organic field-effect transistors based on novel high-κ organometallic lanthanide complex for gate insulating materials

Energy Technology Data Exchange (ETDEWEB)

Liu, Qi; Li, Yi; Zhang, Yang; Song, You, E-mail: wangxzh@nju.edu.cn, E-mail: yli@nju.edu.cn, E-mail: yousong@nju.edu.cn; Wang, Xizhang, E-mail: wangxzh@nju.edu.cn, E-mail: yli@nju.edu.cn, E-mail: yousong@nju.edu.cn; Hu, Zheng [Key Laboratory of Mesoscopic Chemistry of MOE, Jiangsu Provincial Lab for Nanotechnology, School of Chemistry and Chemical Engineering, Nanjing University, Nanjing 210093, China. High-Tech Research Institute of Nanjing University (Suzhou), Suzhou 215123 (China); Sun, Huabin; Li, Yun, E-mail: wangxzh@nju.edu.cn, E-mail: yli@nju.edu.cn, E-mail: yousong@nju.edu.cn; Shi, Yi [School of Electronic Science and Engineering and Jiangsu Provincial Key Laboratory of Photonic and Electronic Materials, Nanjing University, Nanjing 210093 (China)

2014-08-15

A novel high-κ organometallic lanthanide complex, Eu(tta){sub 3}L (tta=2-thenoyltrifluoroacetonate, L = 4,5-pinene bipyridine), is used as gate insulating material to fabricate low-voltage pentacene field-effect transistors (FETs). The optimized gate insulator exhibits the excellent properties such as low leakage current density, low surface roughness, and high dielectric constant. When operated under a low voltage of −5 V, the pentacene FET devices show the attractive electrical performance, e.g. carrier mobility (μ{sub FET}) of 0.17 cm{sup 2} V{sup −1} s{sup −1}, threshold voltage (V{sub th}) of −0.9 V, on/off current ratio of 5 × 10{sup 3}, and subthreshold slope (SS) of 1.0 V dec{sup −1}, which is much better than that of devices obtained on conventional 300 nm SiO{sub 2} substrate (0.13 cm{sup 2} V{sup −1} s{sup −1}, −7.3 V and 3.1 V dec{sup −1} for μ{sub FET}, V{sub th} and SS value when operated at −30 V). These results indicate that this kind of high-κ organometallic lanthanide complex becomes a promising candidate as gate insulator for low-voltage organic FETs.

Effects of doping on ferroelectric properties and leakage current behavior of KNN-LT-LS thin films on SrTiO3 substrate

Science.gov (United States)

Abazari, M.; Safari, A.

2009-05-01

We report the effects of Ba, Ti, and Mn dopants on ferroelectric polarization and leakage current of (K0.44Na0.52Li0.04)(Nb0.84Ta0.1Sb0.06)O3 (KNN-LT-LS) thin films deposited by pulsed laser deposition. It is shown that donor dopants such as Ba2+, which increased the resistivity in bulk KNN-LT-LS, had an opposite effect in the thin film. Ti4+ as an acceptor B-site dopant reduces the leakage current by an order of magnitude, while the polarization values showed a slight degradation. Mn4+, however, was found to effectively suppress the leakage current by over two orders of magnitude while enhancing the polarization, with 15 and 23 μC/cm2 remanent and saturated polarization, whose values are ˜70% and 82% of the reported values for bulk composition. This phenomenon has been associated with the dual effect of Mn4+ in KNN-LT-LS thin film, by substituting both A- and B-site cations. A detailed description on how each dopant affects the concentrations of vacancies in the lattice is presented. Mn-doped KNN-LT-LS thin films are shown to be a promising candidate for lead-free thin films and applications.

New AlGaN/GaN HEMTs employing both a floating gate and a field plate

International Nuclear Information System (INIS)

Lim, Jiyong; Choi, Young-Hwan; Kim, Young-Shil; Han, Min-Koo

2010-01-01

We designed and fabricated AlGaN/GaN high-electron-mobility transistors (HEMTs) employing both a floating gate (FG) and a field plate (FP), which increase the breakdown voltage of AlGaN/GaN HEMTs significantly without sacrificing forward electric characteristics. The electric field strength at the gate-drain region of the proposed AlGaN/GaN HEMT was reduced successfully due to an increase in the number of depletion region edges. The breakdown voltage of the proposed AlGaN/GaN HEMT was 1106 V, while those of the conventional devices with only an FP or FG were 688 and 828 V, respectively. The leakage current of the proposed AlGaN/GaN HEMTs was 1.68 μA under a reverse bias of -100 V while those of the conventional devices with only an FP or FG were 3.21 and 1.91 μA, respectively, under the same condition. The forward electric characteristics of the proposed and conventional AlGaN/GaN HEMTs are similar. The maximum drain current of the proposed AlGaN/GaN HEMTs was 344 mA mm -1 while those of the conventional devices with only an FP or FG were 350 and 357 mA mm -1 , respectively. The maximum transconductance of the proposed device was 102.9 mS mm -1 , while those of the conventional devices were 97.8 and 101.9 mS mm -1 . The breakdown voltage and the leakage current of the proposed device were improved considerably without sacrificing the forward electric characteristics. It should be noted that there were no additional processing steps and mask levels compared to the conventional FP process.

Study of radiation-induced leakage current between adjacent devices in a CMOS integrated circuit

Institute of Scientific and Technical Information of China (English)

Ding Lili; Guo Hongxia; Chen Wei; Fan Ruyu

2012-01-01

Radiation-induced inter-device leakage is studied using an analytical model and TCAD simulation.There were some different opinions in understanding the process of defect build-up in trench oxide and parasitic leakage path turning on from earlier studies.To reanalyze this problem and make it beyond argument,every possible variable is considered using theoretical analysis,not just the change of electric field or oxide thickness independently.Among all possible inter-device leakage paths,parasitic structures with N-well as both drain and source are comparatively more sensitive to the total dose effect when a voltage discrepancy exists between the drain and source region.Since N-well regions are commonly connected to the same power supply,these kinds of structures will not be a problem in a real CMOS integrated circuit.Generally speaking,conduction paths of inter-device leakage existing in a real integrated circuit and under real electrical circumstances are not very sensitive to the total ionizing dose effect.

Inner volume leakage during integrated leakage rate testing

International Nuclear Information System (INIS)

Glover, J.P.

1987-01-01

During an integrated leak rate test (ILRT), the containment structure is maintained at test pressure with most penetrations isolated. Since penetrations typically employ dual isolation, the possibility exists for the inner isolation to leak while the outer holds. In this case, the ILRT instrumentation system would indicate containment out-leakage when, in fact, only the inner volume between closures is being pressurized. The problem is compounded because this false leakage is not readily observable outside of containment by standard leak inspection techniques. The inner volume leakage eventually subsides after the affected volumes reach test pressure. Depending on the magnitude of leakage and the size of the volumes, equalization could occur prior to the end of the pretest stabilization period, or significant false leakages may persist throughout the entire test. Two simple analyses were performed to quantify the effects of inside volume leakages. First, a lower bound for the equalization time was found. A second analysis was performed to find an approximate upper bound for the stabilization time. The results of both analyses are shown

Optimal inverter logic gate using 10-nm double gate-all-around (DGAA transistor with asymmetric channel width

Directory of Open Access Journals (Sweden)

Myunghwan Ryu

2016-01-01

Full Text Available We investigate the electrical characteristics of a double-gate-all-around (DGAA transistor with an asymmetric channel width using three-dimensional device simulation. The DGAA structure creates a silicon nanotube field-effect transistor (NTFET with a core-shell gate architecture, which can solve the problem of loss of gate controllability of the channel and provides improved short-channel behavior. The channel width asymmetry is analyzed on both sides of the terminals of the transistors, i.e., source and drain. In addition, we consider both n-type and p-type DGAA FETs, which are essential to forming a unit logic cell, the inverter. Simulation results reveal that, according to the carrier types, the location of the asymmetry has a different effect on the electrical properties of the devices. Thus, we propose the N/P DGAA FET structure with an asymmetric channel width to form the optimal inverter. Various electrical metrics are analyzed to investigate the benefits of the optimal inverter structure over the conventional inverter structure. Simulation results show that 27% delay and 15% leakage power improvement are enabled in the optimum structure.

On Probability Leakage

OpenAIRE

Briggs, William M.

2012-01-01

The probability leakage of model M with respect to evidence E is defined. Probability leakage is a kind of model error. It occurs when M implies that events $y$, which are impossible given E, have positive probability. Leakage does not imply model falsification. Models with probability leakage cannot be calibrated empirically. Regression models, which are ubiquitous in statistical practice, often evince probability leakage.

Temperature dependence of the current in Schottky-barrier source-gated transistors

Science.gov (United States)

Sporea, R. A.; Overy, M.; Shannon, J. M.; Silva, S. R. P.

2015-05-01

The temperature dependence of the drain current is an important parameter in thin-film transistors. In this paper, we propose that in source-gated transistors (SGTs), this temperature dependence can be controlled and tuned by varying the length of the source electrode. SGTs comprise a reverse biased potential barrier at the source which controls the current. As a result, a large activation energy for the drain current may be present which, although useful in specific temperature sensing applications, is in general deleterious in many circuit functions. With support from numerical simulations with Silvaco Atlas, we describe how increasing the length of the source electrode can be used to reduce the activation energy of SGT drain current, while maintaining the defining characteristics of SGTs: low saturation voltage, high output impedance in saturation, and tolerance to geometry variations. In this study, we apply the dual current injection modes to obtain drain currents with high and low activation energies and propose mechanisms for their exploitation in future large-area integrated circuit designs.

High speed and leakage-tolerant domino circuits for high fan-in applications in 70nm CMOS technology

DEFF Research Database (Denmark)

Moradi, Farshad; Wisland, Dag; Mahmoodi, Hamid

This paper presents two proposed circuits that employ a footer transistor that is initially OFF in the evaluation phase to reduce leakage and then turned ON to complete the evaluation. Also a new circuit is added using a NAND gate that improves the performance more than 10% -15% compared...... with latter proposed circuit. According to simulations in a predictive 70 nm process, the proposed circuit increases noise immunity by more than 26X for wide OR gates and shows performance improvement of up to 20% compared to conventional domino logic circuits. The proposed circuit reduces the contention...

Direct observation of the leakage current in epitaxial diamond Schottky barrier devices by conductive-probe atomic force microscopy and Raman imaging

International Nuclear Information System (INIS)

Alvarez, J; Boutchich, M; Kleider, J P; Teraji, T; Koide, Y

2014-01-01

The origin of the high leakage current measured in several vertical-type diamond Schottky devices is conjointly investigated by conducting probe atomic force microscopy and confocal micro-Raman/photoluminescence imaging analysis. Local areas characterized by a strong decrease of the local resistance (5–6 orders of magnitude drop) with respect to their close surrounding have been identified in several different regions of the sample surface. The same local areas, also referenced as electrical hot-spots, reveal a slightly constrained diamond lattice and three dominant Raman bands in the low-wavenumber region (590, 914 and 1040 cm −1 ). These latter bands are usually assigned to the vibrational modes involving boron impurities and its possible complexes that can electrically act as traps for charge carriers. Local current–voltage measurements performed at the hot-spots point out a trap-filled-limited current as the main conduction mechanism favouring the leakage current in the Schottky devices. (paper)

Efficient one- and two-qubit pulsed gates for an oscillator-stabilized Josephson qubit

International Nuclear Information System (INIS)

Brito, Frederico; DiVincenzo, David P; Koch, Roger H; Steffen, Matthias

2008-01-01

We present theoretical schemes for performing high-fidelity one- and two-qubit pulsed gates for a superconducting flux qubit. The 'IBM qubit' consists of three Josephson junctions, three loops and a superconducting transmission line. Assuming a fixed inductive qubit-qubit coupling, we show that the effective qubit-qubit interaction is tunable by changing the applied fluxes, and can be made negligible, allowing one to perform high-fidelity single qubit gates. Our schemes are tailored to alleviate errors due to 1/f noise; we find gates with only 1% loss of fidelity due to this source, for pulse times in the range of 20-30 ns for one-qubit gates (Z rotations, Hadamard) and 60 ns for a two-qubit gate (controlled-Z). Our relaxation and dephasing time estimates indicate a comparable loss of fidelity from this source. The control of leakage plays an important role in the design of our shaped pulses, preventing shorter pulse times. However, we have found that imprecision in the control of the quantum phase plays a major role in the limitation of the fidelity of our gates

Electrical characteristics of vapor deposited amorphous MoS2 two-terminal structures and back gate thin film transistors with Al, Au, Cu and Ni-Au contacts

International Nuclear Information System (INIS)

Kouvatsos, Dimitrios N.; Papadimitropoulos, Georgios; Spiliotis, Thanassis; Vasilopoulou, Maria; Davazoglou, Dimitrios; Barreca, Davide; Gasparotto, Alberto

2015-01-01

Amorphous molybdenum sulphide (a-MoS 2 ) thin films were deposited at near room temperature on oxidized silicon substrates and were electrically characterized with the use of two-terminal structures and of back-gated thin film transistors utilizing the substrate silicon as gate. Current-voltage characteristics were extracted for various metals used as pads, showing significant current variations attributable to different metal-sulphide interface properties and contact resistances, while the effect of a forming gas anneal was determined. With the use of heavily doped silicon substrates and aluminum backside deposition, thin film transistor (TFT) structures with the a-MoS 2 film as active layer were fabricated and characterized. Transfer characteristics showing a gate field effect, despite a leakage often present, were extracted for these devices, indicating that high mobility devices can be fabricated. SEM and EDXA measurements were also performed in an attempt to clarify issues related to material properties and fabrication procedures, so as to achieve a reliable and optimized a-MoS 2 TFT fabrication process. (copyright 2015 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

On the problem of internal optical loss and current leakage in laser heterostructures based on AlGaInAs/InP solid solutions

International Nuclear Information System (INIS)

Veselov, D. A.; Shashkin, I. S.; Bakhvalov, K. V.; Lyutetskiy, A. V.; Pikhtin, N. A.; Rastegaeva, M. G.; Slipchenko, S. O.; Bechvay, E. A.; Strelets, V. A.; Shamakhov, V. V.; Tarasov, I. S.

2016-01-01

Semiconductor lasers based on MOCVD-grown AlGaInAs/InP separate-confinement heterostructures are studied. It is shown that raising only the energy-gap width of AlGaInAs-waveguides without the introduction of additional barriers results in more pronounced current leakage into the cladding layers. It is found that the introduction of additional barrier layers at the waveguide–cladding-layer interface blocks current leakage into the cladding layers, but results in an increase in the internal optical loss with increasing pump current. It is experimentally demonstrated that the introduction of blocking layers makes it possible to obtain maximum values of the internal quantum efficiency of stimulated emission (92%) and continuouswave output optical power (3.2 W) in semiconductor lasers in the eye-safe wavelength range (1400–1600 nm).

On the problem of internal optical loss and current leakage in laser heterostructures based on AlGaInAs/InP solid solutions

Energy Technology Data Exchange (ETDEWEB)

Veselov, D. A., E-mail: dmitriy90@list.ru; Shashkin, I. S.; Bakhvalov, K. V.; Lyutetskiy, A. V.; Pikhtin, N. A.; Rastegaeva, M. G.; Slipchenko, S. O.; Bechvay, E. A.; Strelets, V. A.; Shamakhov, V. V.; Tarasov, I. S. [Russian Academy of Sciences, Ioffe Physical–Technical Institute (Russian Federation)

2016-09-15

Semiconductor lasers based on MOCVD-grown AlGaInAs/InP separate-confinement heterostructures are studied. It is shown that raising only the energy-gap width of AlGaInAs-waveguides without the introduction of additional barriers results in more pronounced current leakage into the cladding layers. It is found that the introduction of additional barrier layers at the waveguide–cladding-layer interface blocks current leakage into the cladding layers, but results in an increase in the internal optical loss with increasing pump current. It is experimentally demonstrated that the introduction of blocking layers makes it possible to obtain maximum values of the internal quantum efficiency of stimulated emission (92%) and continuouswave output optical power (3.2 W) in semiconductor lasers in the eye-safe wavelength range (1400–1600 nm).

Effects of Energy Relaxation via Quantum Coupling Among Three-Dimensional Motion on the Tunneling Current of Graphene Field-Effect Transistors.

Science.gov (United States)

Mao, Ling-Feng; Ning, Huansheng; Li, Xijun

2015-12-01

We report theoretical study of the effects of energy relaxation on the tunneling current through the oxide layer of a two-dimensional graphene field-effect transistor. In the channel, when three-dimensional electron thermal motion is considered in the Schrödinger equation, the gate leakage current at a given oxide field largely increases with the channel electric field, electron mobility, and energy relaxation time of electrons. Such an increase can be especially significant when the channel electric field is larger than 1 kV/cm. Numerical calculations show that the relative increment of the tunneling current through the gate oxide will decrease with increasing the thickness of oxide layer when the oxide is a few nanometers thick. This highlights that energy relaxation effect needs to be considered in modeling graphene transistors.

A novel optical gating method for laser gated imaging

Science.gov (United States)

Ginat, Ran; Schneider, Ron; Zohar, Eyal; Nesher, Ofer

2013-06-01

For the past 15 years, Elbit Systems is developing time-resolved active laser-gated imaging (LGI) systems for various applications. Traditional LGI systems are based on high sensitive gated sensors, synchronized to pulsed laser sources. Elbit propriety multi-pulse per frame method, which is being implemented in LGI systems, improves significantly the imaging quality. A significant characteristic of the LGI is its ability to penetrate a disturbing media, such as rain, haze and some fog types. Current LGI systems are based on image intensifier (II) sensors, limiting the system in spectral response, image quality, reliability and cost. A novel propriety optical gating module was developed in Elbit, untying the dependency of LGI system on II. The optical gating module is not bounded to the radiance wavelength and positioned between the system optics and the sensor. This optical gating method supports the use of conventional solid state sensors. By selecting the appropriate solid state sensor, the new LGI systems can operate at any desired wavelength. In this paper we present the new gating method characteristics, performance and its advantages over the II gating method. The use of the gated imaging systems is described in a variety of applications, including results from latest field experiments.

Antipsychotics, chlorpromazine and haloperidol inhibit voltage-gated proton currents in BV2 microglial cells.

Science.gov (United States)

Shin, Hyewon; Song, Jin-Ho

2014-09-05

Microglial dysfunction and neuroinflammation are thought to contribute to the pathogenesis of schizophrenia. Some antipsychotic drugs have anti-inflammatory activity and can reduce the secretion of pro-inflammatory cytokines and reactive oxygen species from activated microglial cells. Voltage-gated proton channels on the microglial cells participate in the generation of reactive oxygen species and neuronal toxicity by supporting NADPH oxidase activity. In the present study, we examined the effects of two typical antipsychotics, chlorpromazine and haloperidol, on proton currents in microglial BV2 cells using the whole-cell patch clamp method. Chlorpromazine and haloperidol potently inhibited proton currents with IC50 values of 2.2 μM and 8.4 μM, respectively. Chlorpromazine and haloperidol are weak bases that can increase the intracellular pH, whereby they reduce the proton gradient and affect channel gating. Although the drugs caused a marginal positive shift of the activation voltage, they did not change the reversal potential. This suggested that proton current inhibition was not due to an alteration of the intracellular pH. Chlorpromazine and haloperidol are strong blockers of dopamine receptors. While dopamine itself did not affect proton currents, it also did not alter proton current inhibition by the two antipsychotics, indicating dopamine receptors are not likely to mediate the proton current inhibition. Given that proton channels are important for the production of reactive oxygen species and possibly pro-inflammatory cytokines, the anti-inflammatory and antipsychotic activities of chlorpromazine and haloperidol may be partly derived from their ability to inhibit microglial proton currents. Copyright © 2014 Elsevier B.V. All rights reserved.

Analytical model for subthreshold current and subthreshold swing of short-channel double-material-gate MOSFETs with strained-silicon channel on silicon—germanium substrates

International Nuclear Information System (INIS)

Tiwari Pramod Kumar; Saramekala Gopi Krishna; Mukhopadhyay Anand Kumar; Dubey Sarvesh

2014-01-01

The present work gives some insight into the subthreshold behaviour of short-channel double-material-gate strained-silicon on silicon—germanium MOSFETs in terms of subthreshold swing and off-current. The formulation of subthreshold current and, thereupon, the subthreshold swing have been done by exploiting the expression of potential distribution in the channel region of the device. The dependence of the subthreshold characteristics on the device parameters, such as Ge mole fraction, gate length ratio, work function of control gate metal and gate length, has been tested in detail. The analytical models have been validated by the numerical simulation results that were obtained from the device simulation software ATLAS™ by Silvaco Inc. (semiconductor devices)

Millennial-scale Agulhas Current variability and its implications for salt-leakage through the Indian–Atlantic Ocean Gateway

NARCIS (Netherlands)

Simon, M.H.; Arthur, K.L.; Hall, I.R.; Peeters, F.J.C.; Loveday, B.R.; Barker, S.; Zahn, R.

2013-01-01

The inter-ocean exchange of warm and salt-enriched waters around South Africa (Agulhas leakage), may have played an important role in the mechanism of deglaciations. Paleoceanographic reconstructions from the Agulhas leakage corridor show that leakage maxima occurred during glacial terminations.

Mechanism of Estradiol-Induced Block of Voltage-Gated K+ Currents in Rat Medial Preoptic Neurons

Science.gov (United States)

Druzin, Michael; Malinina, Evgenya; Grimsholm, Ola; Johansson, Staffan

2011-01-01

The present study was conducted to characterize possible rapid effects of 17-β-estradiol on voltage-gated K+ channels in preoptic neurons and, in particular, to identify the mechanisms by which 17-β-estradiol affects the K+ channels. Whole-cell currents from dissociated rat preoptic neurons were studied by perforated-patch recording. 17-β-estradiol rapidly (within seconds) and reversibly reduced the K+ currents, showing an EC50 value of 9.7 µM. The effect was slightly voltage dependent, but independent of external Ca2+, and not sensitive to an estrogen-receptor blocker. Although 17-α-estradiol also significantly reduced the K+ currents, membrane-impermeant forms of estradiol did not reduce the K+ currents and other estrogens, testosterone and cholesterol were considerably less effective. The reduction induced by estradiol was overlapping with that of the KV-2-channel blocker r-stromatoxin-1. The time course of K+ current in 17-β-estradiol, with a time-dependent inhibition and a slight dependence on external K+, suggested an open-channel block mechanism. The properties of block were predicted from a computational model where 17-β-estradiol binds to open K+ channels. It was concluded that 17-β-estradiol rapidly reduces voltage-gated K+ currents in a way consistent with an open-channel block mechanism. This suggests a new mechanism for steroid action on ion channels. PMID:21625454

Analytical drift-current threshold voltage model of long-channel double-gate MOSFETs

International Nuclear Information System (INIS)

Shih, Chun-Hsing; Wang, Jhong-Sheng

2009-01-01

This paper presents a new, physical threshold voltage model to solve the ambiguity in determining the threshold voltage of double-gate (DG) MOSFETs. To avoid the difficulties of the conventional 2ψ B model in nearly undoped DG MOSFETs, this study proposes to define the on–off switching based on the actual roles of the drift and diffusion components in the total drain current. The drift current strongly enhances beyond the threshold voltage, while the diffusion current plays a major role in the subthreshold. The threshold voltage is defined as the drift component that exceeds the diffusion counterpart. From the solutions of Poisson's equation, the drift and diffusion currents of DG MOSFETs are separately formulated to derive the analytical expressions of the threshold voltage and associated threshold current. This model provides a comprehensive description of the switching behavior of DG MOSFET devices, and offers a physical onset threshold current to determine the threshold voltage in practical extraction

Sistem Proteksi Arus Bocor Menggunakan Earth Leakage Circuit Breaker Berbasis Arduino

Directory of Open Access Journals (Sweden)

Syukriyadin Syukriyadin

2017-02-01

Full Text Available Touching a live part of electrical equipment either intentionally or unintentionally can cause an electric shock. The touch can occur directly or indirectly and results in the flow of electric current through the human body to the ground. This electric current is known as the leakage current and can have fatal effects on the human body such as burns, cramps, faint and death. This paper aims to design a prototype protection model of the earth leakage circuit breaker device based on Arduino (ELCBA to protect the human body from the electrical hazards. The performance of the ELCBA is investigated by detecting the earth leakage current to the grounding system (TN.  The prototype is designed and simulated by using Proteus software. Based on the response test carried out on the prototype, it can be concluded that the ELCBA can operate properly to disconnect the electric circuit if the leakage current is detected greater than or equal to 30 mA with a time delay of 15 ms and to reclose the circuit again after 5 minutes.

Ternary rare-earth based alternative gate-dielectrics for future integration in MOSFETs

Energy Technology Data Exchange (ETDEWEB)

Schubert, Juergen; Lopes, Joao Marcelo; Durgun Oezben, Eylem; Luptak, Roman; Lenk, Steffi; Zander, Willi; Roeckerath, Martin [IBN 1-IT, Forschungszentrum Juelich, 52425 Juelich (Germany)

2009-07-01

The dielectric SiO{sub 2} has been the key to the tremendous improvements in Si-based metal-oxide-semiconductor (MOS) device performance over the past four decades. It has, however, reached its limit in terms of scaling since it exhibits a leakage current density higher than 1 A/cm{sup 2} and does not retain its intrinsic physical properties at thicknesses below 1.5 nm. In order to overcome these problems and keep Moore's law ongoing, the use of higher dielectric constant (k) gate oxides has been suggested. These high-k materials must satisfy numerous requirements such as the high k, low leakage currents, suitable band gap und offsets to silicon. Rare-earth based dielectrics are promising materials which fulfill these needs. We will review the properties of REScO{sub 3} (RE = La, Dy, Gd, Sm, Tb) and LaLuO{sub 3} thin films, grown with pulsed laser deposition, e-gun evaporation or molecular beam deposition, integrated in capacitors and transistors. A k > 20 for the REScO{sub 3} (RE = Dy, Gd) and around 30 for (RE = La, Sm, Tb) and LaLuO{sub 3} are obtained. Transistors prepared on SOI and sSOI show mobility values up to 380 cm{sup 2}/Vs on sSOI, which are comparable to such prepared with HfO{sub 2}.

A gate drive circuit for gate-turn-off (GTO) devices in series stack

International Nuclear Information System (INIS)

Despe, O.

1999-01-01

A gate-turn-off (GTO) switch is under development at the Advanced Photon Source as a replacement for a thyratron switch in high power pulsed application. The high voltage in the application requires multiple GTOs connected in series. One component that is critical to the success of GTO operation is the gate drive circuit. The gate drive circuit has to provide fast high-current pulses to the GTO gate for fast turn-on and turn-off. It also has to be able to operate while floating at high voltage. This paper describes a gate drive circuit that meets these requirements

Step-and-shoot prospectively ECG-gated vs. retrospectively ECG-gated with tube current modulation coronary CT angiography using 128-slice MDCT patients with chest pain: diagnostic performance and radiation dose

International Nuclear Information System (INIS)

Kim, Jeong Su; Choo, Ki Seok; Jeong, Dong Wook

2011-01-01

Background With increasing awareness for radiation exposure, the study of diagnostic accuracy of coronary CT angiography (CCTA) with low radiation dose techniques is mandatory to both radiologist and clinician. Purpose To compare diagnostic performance and effective radiation dose between step-and-shoot prospectively ECG-gated and retrospectively ECG-gated with tube current modulation (TCM) CCTA using 128-slice multidetector computed tomography (MDCT). Material and Methods We retrospectively evaluated 60 patients who underwent CCTA with either of two different low-dose techniques using 128-slice MDCT (23 patients for step-and shoot-prospectively ECG-gated and 37 patients for retrospectively ECG-gated with TCM CCTA) followed by conventional coronary angiography. All coronary arteries and all segments thereof, except anatomical variants or small size (< 1.5 mm) ones, were included in analysis. Results In per-segment analysis, sensitivity, specificity, positive predictive value, and negative predictive value were 91/96%, 95/94%, 75/73%, and 98/99% for step-and-shoot prospectively ECG-gated and retrospectively ECG gated with TCM CCTA, respectively, relative to conventional coronary angiography. Effective radiation dose were 1.75 ± 0.83 mSv, 4.91 ± 1.71 mSv in the step-and-shoot prospectively ECG-gated and retrospectively ECG-gated with TCM CCTA groups, respectively. Conclusion The two low-radiation dose CCTA techniques using 128-slice MDCT yields comparable diagnostic performance for coronary artery disease in symptomatic patients with low heart rates

Land-use Leakage

Energy Technology Data Exchange (ETDEWEB)

Calvin, Katherine V.; Edmonds, James A.; Clarke, Leon E.; Bond-Lamberty, Benjamin; Kim, Son H.; Wise, Marshall A.; Thomson, Allison M.; Kyle, G. Page

2009-12-01

Leakage occurs whenever actions to mitigate greenhouse gas emissions in one part of the world unleash countervailing forces elsewhere in the world so that reductions in global emissions are less than emissions mitigation in the mitigating region. While many researchers have examined the concept of industrial leakage, land-use policies can also result in leakage. We show that land-use leakage is potentially as large as or larger than industrial leakage. We identify two potential land-use leakage drivers, land-use policies and bioenergy. We distinguish between these two pathways and run numerical experiments for each. We also show that the land-use policy environment exerts a powerful influence on leakage and that under some policy designs leakage can be negative. International “offsets” are a potential mechanism to communicate emissions mitigation beyond the borders of emissions mitigating regions, but in a stabilization regime designed to limit radiative forcing to 3.7 2/m2, this also implies greater emissions mitigation commitments on the part of mitigating regions.

Evaluation of Information Leakage from Cryptographic Hardware via Common-Mode Current

Science.gov (United States)

Hayashi, Yu-Ichi; Homma, Naofumi; Mizuki, Takaaki; Sugawara, Takeshi; Kayano, Yoshiki; Aoki, Takafumi; Minegishi, Shigeki; Satoh, Akashi; Sone, Hideaki; Inoue, Hiroshi

This paper presents a possibility of Electromagnetic (EM) analysis against cryptographic modules outside their security boundaries. The mechanism behind the information leakage is explained from the view point of Electromagnetic Compatibility: electric fluctuation released from cryptographic modules can conduct to peripheral circuits based on ground bounce, resulting in radiation. We demonstrate the consequence of the mechanism through experiments where the ISO/IEC standard block cipher AES (Advanced Encryption Standard) is implemented on an FPGA board and EM radiations from power and communication cables are measured. Correlation Electromagnetic Analysis (CEMA) is conducted in order to evaluate the information leakage. The experimental results show that secret keys are revealed even though there are various disturbing factors such as voltage regulators and AC/DC converters between the target module and the measurement points. We also discuss information-suppression techniques as electrical-level countermeasures against such CEMAs.

Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

International Nuclear Information System (INIS)

Bhartia, Mini; Chatterjee, Arun Kumar

2015-01-01

A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2. (paper)

Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

Science.gov (United States)

Bhartia, Mini; Chatterjee, Arun Kumar

2015-04-01

A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.

Current-driven plasmonic boom instability in three-dimensional gated periodic ballistic nanostructures

Science.gov (United States)

Aizin, G. R.; Mikalopas, J.; Shur, M.

2016-05-01

An alternative approach of using a distributed transmission line analogy for solving transport equations for ballistic nanostructures is applied for solving the three-dimensional problem of electron transport in gated ballistic nanostructures with periodically changing width. The structures with varying width allow for modulation of the electron drift velocity while keeping the plasma velocity constant. We predict that in such structures biased by a constant current, a periodic modulation of the electron drift velocity due to the varying width results in the instability of the plasma waves if the electron drift velocity to plasma wave velocity ratio changes from below to above unity. The physics of such instability is similar to that of the sonic boom, but, in the periodically modulated structures, this analog of the sonic boom is repeated many times leading to a larger increment of the instability. The constant plasma velocity in the sections of different width leads to resonant excitation of the unstable plasma modes with varying bias current. This effect (that we refer to as the superplasmonic boom condition) results in a strong enhancement of the instability. The predicted instability involves the oscillating dipole charge carried by the plasma waves. The plasmons can be efficiently coupled to the terahertz electromagnetic radiation due to the periodic geometry of the gated structure. Our estimates show that the analyzed instability should enable powerful tunable terahertz electronic sources.

A Minimum Leakage Quasi-Static RAM Bitcell

Directory of Open Access Journals (Sweden)

Adam Teman

2011-05-01

Full Text Available As SRAMs continue to grow and comprise larger percentages of the area and power consumption in advanced systems, the need to minimize static currents becomes essential. This brief presents a novel 9T Quasi-Static RAM Bitcell that provides aggressive leakage reduction and high write margins. The quasi-static operation method of this cell, based on internal feedback and leakage ratios, minimizes static power while maintaining sufficient, albeit depleted, noise margins. This paper presents the concept of the novel cell, and discusses the stability of the cell under hold, read and write operations. The cell was implemented in a low-power 40 nm TSMC process, showing as much as a 12× reduction in leakage current at typical conditions, as compared to a standard 6T or 8T bitcell at the same supply voltage. The implemented cell showed full functionality under global and local process variations at nominal and low voltages, as low as 300 mV.

Electrical parameters of silicon on sapphire; influence on aluminium gate MOS devices performances

International Nuclear Information System (INIS)

Suat, J.P.; Borel, J.

1976-01-01

The question is the quality level of the substrate obtained with MOS technologies on silicon on an insulating substrate. Experimental results are presented on the main electrical parameters of MOS transistors made on silicon on sapphire, e.g. mean values and spreads of: threhold voltage and surface mobilities of transistors, breakdown voltages, and leakage currents of diodes. These devices have been made in three different technologies: enhancement P. channel technology, depletion-enhancement P. channel technology, and complementary MOS technology. These technologies are all aluminium gate processes with standard design rules and 5μm channel length. Measurements show that presently available silicon on sapphire can be considered as a very suitable substrate for many MOS digital applications (but not for dynamic circuits) [fr

Specific features of the switch-on gate current and different switch-on modes in silicon carbide thyristors

International Nuclear Information System (INIS)

Yurkov, S N; Mnatsakanov, T T; Levinshtein, M E; Cheng, L; Palmour, J W

2014-01-01

The specific features of the temperature and bias dependences of the switch-on gate current in SiC thyristors are examined analytically for two possible switching mechanisms. The so-called γ-mechanism, which is highly typical of the conventional Si thyristors, is characterized by very weak temperature and bias dependences. By contrast, the so-called α-mechanism, which is very characteristic of SiC thyristors, is highly sensitive to changes in temperature and bias. If the thyristor is switched on by the α-mechanism, the switch-on gate current density decreases very steeply with increasing temperature. As a result, the thyristor can lose its working capacity at elevated temperatures due to the instability against even very weak impacts. With decreasing the bias voltage U a , the gate switch-on current increases very steeply, which can make switching the thyristor on difficult. The unintentional shunting, which is apparently present in high-voltage SiC thyristors, causes the transition from the α- to the γ-mechanism at elevated temperatures and high biases. It can be supposed that introduction of a controllable technological shunting of the emitter–thin base junction allows stabilization of the temperature and bias parameters of SiC thyristors. The analytical results are confirmed by computer simulations performed in wide temperature and bias ranges for a 4H-SiC thyristor of the 18 kV class. (paper)

Source-Drain Punch-Through Analysis of High Voltage Off-State AlGaN/GaN HEMT Breakdown

Science.gov (United States)

Jiang, H.; Li, X.; Wang, J.; Zhu, L.; Wang, H.; Liu, J.; Wang, M.; Yu, M.; Wu, W.; Zhou, Y.; Dai, G.

2017-06-01

AlGaN/GaN high-electron mobility transistor’s (HEMT’s) off-state breakdown is investigated using conventional three-terminal off-state breakdown I-V measurement. Competition between gate leakage and source-injection buffer leakage (SIBL) is discussed in detail. It is found that the breakdown is dominated by source-injection which is sensitive to gate voltage and gate length at large gate-to-drain spacing (Lgd > 7μm), where a threshold drain voltage of the occurrence of the SIBL current in GaN buffer exists, and after this threshold voltage the SIBL current continually increased till the buffer breakdown. Our analysis showed that due to the punch-through effect in the buffer, a potential barrier between 2DEG and GaN buffer at the source side mainly controlled by the drain voltage determines the buffer leakage current and the occurrence of the following buffer breakdown, which could explain the experimentally observed breakdown phenomenon.

Reliability of AlGaN/GaN high electron mobility transistors on low dislocation density bulk GaN substrate: Implications of surface step edges

Energy Technology Data Exchange (ETDEWEB)

Killat, N., E-mail: Nicole.Killat@bristol.ac.uk, E-mail: Martin.Kuball@bristol.ac.uk; Montes Bajo, M.; Kuball, M., E-mail: Nicole.Killat@bristol.ac.uk, E-mail: Martin.Kuball@bristol.ac.uk [Center for Device Thermography and Reliability (CDTR), H.H. Wills Physics Laboratory, Tyndall Avenue, Bristol BS8 1TL (United Kingdom); Paskova, T. [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States); Materials Science and Engineering Department, North Carolina State University, Raleigh, North Carolina 27695 (United States); Evans, K. R. [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States); Leach, J. [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States); Electrical and Computer Engineering Department, Virginia Commonwealth University, Richmond, Virginia 23284 (United States); Li, X.; Özgür, Ü.; Morkoç, H. [Electrical and Computer Engineering Department, Virginia Commonwealth University, Richmond, Virginia 23284 (United States); Chabak, K. D.; Crespo, A.; Gillespie, J. K.; Fitch, R.; Kossler, M.; Walker, D. E.; Trejo, M.; Via, G. D.; Blevins, J. D. [Air Force Research Laboratory, Wright-Patterson Air Force Base, Dayton, Ohio 45433 (United States)

2013-11-04

To enable gaining insight into degradation mechanisms of AlGaN/GaN high electron mobility transistors, devices grown on a low-dislocation-density bulk-GaN substrate were studied. Gate leakage current and electroluminescence (EL) monitoring revealed a progressive appearance of EL spots during off-state stress which signify the generation of gate current leakage paths. Atomic force microscopy evidenced the formation of semiconductor surface pits at the failure location, which corresponds to the interaction region of the gate contact edge and the edges of surface steps.

Macrophage migration inhibitory factor induces vascular leakage via autophagy

Directory of Open Access Journals (Sweden)

Hong-Ru Chen

2015-01-01

Full Text Available Vascular leakage is an important feature of acute inflammatory shock, which currently has no effective treatment. Macrophage migration inhibitory factor (MIF is a pro-inflammatory cytokine that can induce vascular leakage and plays an important role in the pathogenesis of shock. However, the mechanism of MIF-induced vascular leakage is still unclear. In this study, using recombinant MIF (rMIF, we demonstrated that MIF induced disorganization and degradation of junction proteins and increased the permeability of human endothelial cells in vitro. Western blotting analysis showed that rMIF treatment induced LC3 conversion and p62 degradation. Inhibition of autophagy with a PI3K inhibitor (3-MA, a ROS scavenger (NAC or autophagosomal-lysosomal fusion inhibitors (bafilomycin A1 and chloroquine rescued rMIF-induced vascular leakage, suggesting that autophagy mediates MIF-induced vascular leakage. The potential involvement of other signaling pathways was also studied using different inhibitors, and the results suggested that MIF-induced vascular leakage may occur through the ERK pathway. In conclusion, we showed that MIF triggered autophagic degradation of endothelial cells, resulting in vascular leakage. Inhibition of MIF-induced autophagy may provide therapeutic targets against vascular leakage in inflammatory shock.

Voltage-gated Na+ currents in human dorsal root ganglion neurons

Science.gov (United States)

Zhang, Xiulin; Priest, Birgit T; Belfer, Inna; Gold, Michael S

2017-01-01

Available evidence indicates voltage-gated Na+ channels (VGSCs) in peripheral sensory neurons are essential for the pain and hypersensitivity associated with tissue injury. However, our understanding of the biophysical and pharmacological properties of the channels in sensory neurons is largely based on the study of heterologous systems or rodent tissue, despite evidence that both expression systems and species differences influence these properties. Therefore, we sought to determine the extent to which the biophysical and pharmacological properties of VGSCs were comparable in rat and human sensory neurons. Whole cell patch clamp techniques were used to study Na+ currents in acutely dissociated neurons from human and rat. Our results indicate that while the two major current types, generally referred to as tetrodotoxin (TTX)-sensitive and TTX-resistant were qualitatively similar in neurons from rats and humans, there were several differences that have important implications for drug development as well as our understanding of pain mechanisms. DOI: http://dx.doi.org/10.7554/eLife.23235.001 PMID:28508747

Surface modification of polyimide gate insulators for solution-processed 2,7-didecyl[1]benzothieno[3,2-b][1]benzothiophene (C10-BTBT) thin-film transistors.

Science.gov (United States)

Jang, Kwang-Suk; Kim, Won Soo; Won, Jong-Myung; Kim, Yun-Ho; Myung, Sung; Ka, Jae-Won; Kim, Jinsoo; Ahn, Taek; Yi, Mi Hye

2013-01-21

The surface property of a polyimide gate insulator was successfully modified with an n-octadecyl side-chain. Alkyl chain-grafted poly(amic acid), the polyimide precursor, was synthesized using the diamine comonomer with an alkyl side-chain. By adding a base catalyst to the poly(amic acid) coating solution, the imidization temperature of the spin-coated film could be reduced to 200 °C. The 350 nm-thick polyimide film had a dielectric constant of 3.3 at 10 kHz and a leakage current density of less than 8.7 × 10(-10) A cm(-2), while biased from 0 to 100 V. To investigate the potential of the alkyl chain-grafted polyimide film as a gate insulator for solution-processed organic thin-film transistors (TFTs), we fabricated C(10)-BTBT TFTs. C(10)-BTBT was deposited on the alkyl chain-grafted polyimide gate insulator by spin-coating, forming a well-ordered crystal structure. The field-effect mobility and the on/off current ratio of the TFT device were measured to be 0.20-0.56 cm(2) V(-1) s(-1) and >10(5), respectively.

Electrical and materials properties of AlN/ HfO{sub 2} high-k stack with a metal gate

Energy Technology Data Exchange (ETDEWEB)

Reid, Kimberly G. [Tokyo Electron U.S., 14338 FM 1826, Austin, TX 78737 (United States)], E-mail: kim@ireid.com; Dip, Anthony [Tokyo Electron U.S., 2400 Grove Blvd., Austin, TX 78747 (United States)], E-mail: anthony.dip@us.tel.com; Sasaki, Sadao [Tokyo Electron U.S. (United States)], E-mail: Sadao.sasaki@us.tel.com; Triyoso, Dina [Freescale Semiconductor Inc., 3501 Ed Bluestein Blvd, Austin, TX 78721 (United States)], E-mail: Dina.Triyoso@freescale.com; Samavedam, Sri [Freescale Semiconductor Inc., 3501 Ed Bluestein Blvd, Austin, TX 78721 (United States)], E-mail: Sri.Samavedam@freescale.com; Gilmer, David [SEMATECH 2706 Montopolis Drive, Austin, TX 78741 (United States)], E-mail: David.Gilmer@sematech.org; Gondran, Carolyn F.H. [Process Characterization Laboratory, ATDF/SEMATECH, 2706 Montopolis Drive, Austin, Texas 78741 (United States)], E-mail: Carolyn.Gondran@atdf.com

2009-02-27

In this study, aluminum nitride (AlN) was grown by molecular layer deposition on HfO{sub 2} that had been deposited on 200 mm Si (100) substrates. The AlN was grown on HfO{sub 2} using sequential exposures of trimethyl-aluminum and ammonia (NH{sub 3}) in a batch vertical furnace. Excellent thickness uniformity on test wafers from the top of the furnace to the bottom of the furnace (across the furnace load) was obtained. The equivalent oxide thickness was 16.5-18.8 A for the AlN/HfO{sub 2} stack on patterned device wafers with a molybdenum oxynitride metal gate with leakage current densities from low 10{sup -5} to mid 10{sup -6} A/cm{sup 2} at threshold voltage minus one volt. There was no change in the work function with the AlN cap on HfO{sub 2} with the MoN metal gate, even with a 1000 deg. C anneal.

Forest Carbon Leakage Quantification Methods and Their Suitability for Assessing Leakage in REDD

Directory of Open Access Journals (Sweden)

Sabine Henders

2012-01-01

Full Text Available This paper assesses quantification methods for carbon leakage from forestry activities for their suitability in leakage accounting in a future Reducing Emissions from Deforestation and Forest Degradation (REDD mechanism. To that end, we first conducted a literature review to identify specific pre-requisites for leakage assessment in REDD. We then analyzed a total of 34 quantification methods for leakage emissions from the Clean Development Mechanism (CDM, the Verified Carbon Standard (VCS, the Climate Action Reserve (CAR, the CarbonFix Standard (CFS, and from scientific literature sources. We screened these methods for the leakage aspects they address in terms of leakage type, tools used for quantification and the geographical scale covered. Results show that leakage methods can be grouped into nine main methodological approaches, six of which could fulfill the recommended REDD leakage requirements if approaches for primary and secondary leakage are combined. The majority of methods assessed, address either primary or secondary leakage; the former mostly on a local or regional and the latter on national scale. The VCS is found to be the only carbon accounting standard at present to fulfill all leakage quantification requisites in REDD. However, a lack of accounting methods was identified for international leakage, which was addressed by only two methods, both from scientific literature.

Modeling valve leakage

International Nuclear Information System (INIS)

Bell, S.R.; Rohrscheib, R.

1994-01-01

The American Society of Mechanical Engineers (ASME) Code requires individual valve leakage testing for Category A valves. Although the U.S. Nuclear Regulatory Commission (USNRC) has recognized that it is more appropriate to test containment isolation valves in groups, as allowed by 10 CFR 50, Appendix J, a utility seeking relief from these Code requirements must provide technical justification for the relief and establish a conservative alternate acceptance criteria. In order to provide technical justification for group testing of containment isolation valves, Illinois Power developed a calculation (model) for determining the size of a leakage pathway in a valve disc or seat for a given leakage rate. The model was verified experimentally by machining leakage pathways of known size and then measuring the leakage and comparing this value to the calculated value. For the range of values typical of leakage rate testing, the correlation between the experimental values and calculated values was quote good. Based upon these results, Illinois Power established a conservative acceptance criteria for all valves in the inservice testing (IST) program and was granted relief by the USNRC from the individual leakage testing requirements of the ASME Code. This paper presents the results of Illinois Power's work in the area of valve leakage rate testing

Enhanced ZnO Thin-Film Transistor Performance Using Bilayer Gate Dielectrics

KAUST Repository

Alshammari, Fwzah Hamud; Nayak, Pradipta K.; Wang, Zhenwei; Alshareef, Husam N.

2016-01-01

We report ZnO TFTs using Al2O3/Ta2O5 bilayer gate dielectrics grown by atomic layer deposition. The saturation mobility of single layer Ta2O5 dielectric TFT was 0.1 cm2 V-1 s-1, but increased to 13.3 cm2 V-1 s-1 using Al2O3/Ta2O5 bilayer dielectric with significantly lower leakage current and hysteresis. We show that point defects present in ZnO film, particularly VZn, are the main reason for the poor TFT performance with single layer dielectric, although interfacial roughness scattering effects cannot be ruled out. Our approach combines the high dielectric constant of Ta2O5 and the excellent Al2O3/ZnO interface quality, resulting in improved device performance. © 2016 American Chemical Society.

Enhanced ZnO Thin-Film Transistor Performance Using Bilayer Gate Dielectrics

KAUST Repository

Alshammari, Fwzah Hamud

2016-08-24

We report ZnO TFTs using Al2O3/Ta2O5 bilayer gate dielectrics grown by atomic layer deposition. The saturation mobility of single layer Ta2O5 dielectric TFT was 0.1 cm2 V-1 s-1, but increased to 13.3 cm2 V-1 s-1 using Al2O3/Ta2O5 bilayer dielectric with significantly lower leakage current and hysteresis. We show that point defects present in ZnO film, particularly VZn, are the main reason for the poor TFT performance with single layer dielectric, although interfacial roughness scattering effects cannot be ruled out. Our approach combines the high dielectric constant of Ta2O5 and the excellent Al2O3/ZnO interface quality, resulting in improved device performance. © 2016 American Chemical Society.

Drain current enhancement induced by hole injection from gate of 600-V-class normally off gate injection transistor under high temperature conditions up to 200 °C

Science.gov (United States)

Ishii, Hajime; Ueno, Hiroaki; Ueda, Tetsuzo; Endoh, Tetsuo

2018-06-01

In this paper, the current–voltage (I–V) characteristics of a 600-V-class normally off GaN gate injection transistor (GIT) from 25 to 200 °C are analyzed, and it is revealed that the drain current of the GIT increases during high-temperature operation. It is found that the maximum drain current (I dmax) of the GIT is 86% higher than that of a conventional 600-V-class normally off GaN metal insulator semiconductor hetero-FET (MIS-HFET) at 150 °C, whereas the GIT obtains 56% I dmax even at 200 °C. Moreover, the mechanism of the drain current increase of the GIT is clarified by examining the relationship between the temperature dependence of the I–V characteristics of the GIT and the gate hole injection effect determined from the shift of the second transconductance (g m) peak of the g m–V g characteristic. From the above, the GIT is a promising device with enough drivability for future power switching applications even under high-temperature conditions.

Effect of gamma irradiation on leakage current in CMOS read-out chips for the ATLAS upgrade silicon strip tracker at the HL-LHC

CERN Document Server

Stucci, Stefania Antonia; Lynn, Dave; Kierstead, James; Kuczewski, Philip; van Nieuwenhuizen, Gerrit J; Rosin, Guy; Tricoli, Alessandro

2017-01-01

The increase of the leakage current of NMOS transistors in detector readout chips in certain 130 nm CMOS technologies during exposure to ionising radiation needs special consideration in the design of detector systems, as this can result in a large increase of the supply current and power dissipation. As part of the R&D; program for the upgrade of the ATLAS inner detector tracker for the High Luminosity upgrade of the LHC at CERN, a dedicated set of irradiations have been carried out with the $^60$Co gamma-ray source at the Brookhaven National Laboratory. Measurements will be presented that characterise the increase in the digital leakage current in the 130 nm-technology ABC130 readout chips. The variation of the current as a function of time and total ionising dose has been studied under various conditions of dose rate, temperature and power applied to the chip. The range of variation of dose rates and temperatures has been set to be close to those expected at the High Luminosity LHC, i.e. in the range 0...

Two-dimensional model for subthreshold current and subthreshold swing of graded-channel dual-material double-gate (GCDMDG) MOSFETs

Science.gov (United States)

Goel, Ekta; Kumar, Sanjay; Singh, Balraj; Singh, Kunal; Jit, Satyabrata

2017-06-01

The subthreshold performance of graded-channel dual-material double-gate (GCDMDG) MOSFETs is examined through two-dimensional (2D) analytical modeling of subthreshold-current (SC) and subthreshold-swing (SS). The potential function obtained by using the parabolic approach to solve the 2D Poisson's equation, has been used to formulate SC and SS characteristics of the device. The variations of SS against different device parameters have been obtained with the help of effective conduction path parameter. The SC and SS characteristics of the GCDMDG MOS transistor have been compared with those of the dual-material double-gate (DMDG) and simple graded-channel double-gate (GCDG) MOS structures to show its better subthreshold characteristics over the latter two devices. The results of the developed model are well-agreed with the commercially available SILVACO ATLAS™ simulator data.

Mechanisms for plasma etching of HfO{sub 2} gate stacks with Si selectivity and photoresist trimming

Energy Technology Data Exchange (ETDEWEB)

Shoeb, Juline; Kushner, Mark J. [Department of Electrical and Computer Engineering, Iowa State University, Ames, Iowa 50011 (United States); Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109-2122 (United States)

2009-11-15

To minimize leakage currents resulting from the thinning of the insulator in the gate stack of field effect transistors, high-dielectric constant (high-k) metal oxides, and HfO{sub 2} in particular, are being implemented as a replacement for SiO{sub 2}. To speed the rate of processing, it is desirable to etch the gate stack (e.g., metal gate, antireflection layers, and dielectric) in a single process while having selectivity to the underlying Si. Plasma etching using Ar/BCl{sub 3}/Cl{sub 2} mixtures effectively etches HfO{sub 2} while having good selectivity to Si. In this article, results from integrated reactor and feature scale modeling of gate-stack etching in Ar/BCl{sub 3}/Cl{sub 2} plasmas, preceded by photoresist trimming in Ar/O{sub 2} plasmas, are discussed. It was found that BCl{sub n} species react with HfO{sub 2}, which under ion impact, form volatile etch products such as B{sub m}OCl{sub n} and HfCl{sub n}. Selectivity to Si is achieved by creating Si-B bonding as a precursor to the deposition of a BCl{sub n} polymer which slows the etch rate relative to HfO{sub 2}. The low ion energies required to achieve this selectivity then challenge one to obtain highly anisotropic profiles in the metal gate portion of the stack. Validation was performed with data from literature. The effect of bias voltage and key reactant probabilities on etch rate, selectivity, and profile are discussed.

Interfacial Cation-Defect Charge Dipoles in Stacked TiO2/Al2O3 Gate Dielectrics.

Science.gov (United States)

Zhang, Liangliang; Janotti, Anderson; Meng, Andrew C; Tang, Kechao; Van de Walle, Chris G; McIntyre, Paul C

2018-02-14

Layered atomic-layer-deposited and forming-gas-annealed TiO 2 /Al 2 O 3 dielectric stacks, with the Al 2 O 3 layer interposed between the TiO 2 and a p-type germanium substrate, are found to exhibit a significant interface charge dipole that causes a ∼-0.2 V shift of the flat-band voltage and suppresses the leakage current density for gate injection of electrons. These effects can be eliminated by the formation of a trilayer dielectric stack, consistent with the cancellation of one TiO 2 /Al 2 O 3 interface dipole by the addition of another dipole of opposite sign. Density functional theory calculations indicate that the observed interface-dependent properties of TiO 2 /Al 2 O 3 dielectric stacks are consistent in sign and magnitude with the predicted behavior of Al Ti and Ti Al point-defect dipoles produced by local intermixing of the Al 2 O 3 /TiO 2 layers across the interface. Evidence for such intermixing is found in both electrical and physical characterization of the gate stacks.

Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography

Science.gov (United States)

Lim, Cheol-Min; Lee, In-Kyu; Lee, Ki Joong; Oh, Young Kyoung; Shin, Yong-Beom; Cho, Won-Ju

2017-12-01

This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.

Oligo- and polymeric FET devices: Thiophene-based active materials and their interaction with different gate dielectrics

International Nuclear Information System (INIS)

Porzio, W.; Destri, S.; Pasini, M.; Bolognesi, A.; Angiulli, A.; Di Gianvincenzo, P.; Natali, D.; Sampietro, M.; Caironi, M.; Fumagalli, L.; Ferrari, S.; Peron, E.; Perissinotti, F.

2006-01-01

Derivatives of both oligo- and polythiophene-based FET were recently considered for low cost electronic applications. In the device optimization, factors like redox reversibility of the molecule/polymer, electronic level compatibility with source/drain electrodes, packing closeness, and orientation versus the electrodes, can determine the overall performance. In addition, a gate insulator with a high dielectric constant, a low leakage current, and capability to promote ordering in the semiconductor is required to increase device performances and to lower the FET operating voltage. In this view, Al 2 O 3 appears a good candidate, although its widespread adoption is limited by the disorder that such oxide induces on the semiconductor with detrimental consequences on semiconductor electrical properties. In this contribution, an overview of recent results obtained on thiophene-derivative-based FET devices, fabricated by different growth techniques, and using both thermally grown SiO 2 and Al 2 O 3 from atomic layer deposition gate insulators will be reported and discussed with particular reference to organic solid state aggregation, morphology, and organic-inorganic interface

Leakage current analysis for dislocations in Na-flux GaN bulk single crystals by conductive atomic force microscopy

Science.gov (United States)

Hamachi, T.; Takeuchi, S.; Tohei, T.; Imanishi, M.; Imade, M.; Mori, Y.; Sakai, A.

2018-04-01

The mechanisms associated with electrical conduction through individual threading dislocations (TDs) in a Na-flux GaN crystal grown with a multipoint-seed-GaN technique were investigated by conductive atomic force microscopy (C-AFM). To focus on individual TDs, dislocation-related etch pits (DREPs) were formed on the Na-flux GaN surface by wet chemical etching, after which microscopic Pt electrodes were locally fabricated on the DREPs to form conformal contacts to the Na-flux GaN crystal, using electron beam assisted deposition. The C-AFM data clearly demonstrate that the leakage current flows through the individual TD sites. It is also evident that the leakage current and the electrical conduction mechanism vary significantly based on the area within the Na-flux GaN crystal where the TDs are formed. These regions include the c-growth sector (cGS) in which the GaN grows in the [0001 ] direction on top of the point-seed with a c-plane growth front, the facet-growth sector (FGS) in which the GaN grows with {10 1 ¯ 1 } facets on the side of the cGS, the boundary region between the cGS and FGS (BR), and the coalescence boundary region between FGSs (CBR). The local current-voltage (I-V) characteristics of the specimen demonstrate space charge limited current conduction and conduction related to band-like trap states associated with TDs in the FGS, BR, and CBR. A detailed analysis of the I-V data indicates that the electrical conduction through TDs in the cGS may proceed via the Poole-Frenkel emission mechanism.

Double gate graphene nanoribbon field effect transistor with single halo pocket in channel region

Science.gov (United States)

Naderi, Ali

2016-01-01

A new structure for graphene nanoribbon field-effect transistors (GNRFETs) is proposed and investigated using quantum simulation with a nonequilibrium Green's function (NEGF) method. Tunneling leakage current and ambipolar conduction are known effects for MOSFET-like GNRFETs. To minimize these issues a novel structure with a simple change of the GNRFETs by using single halo pocket in the intrinsic channel region, "Single Halo GNRFET (SH-GNRFET)", is proposed. An appropriate halo pocket at source side of channel is used to modify potential distribution of the gate region and weaken band to band tunneling (BTBT). In devices with materials like Si in channel region, doping type of halo and source/drain regions are different. But, here, due to the smaller bandgap of graphene, the mentioned doping types should be the same to reduce BTBT. Simulations have shown that in comparison with conventional GNRFET (C-GNRFET), an SH-GNRFET with appropriately halo doping results in a larger ON current (Ion), smaller OFF current (Ioff), a larger ON-OFF current ratio (Ion/Ioff), superior ambipolar characteristics, a reduced power-delay product and lower delay time.

Suppression of photo-leakage current in amorphous silicon thin-film transistors by n-doped nanocrystalline silicon

International Nuclear Information System (INIS)

Lin, Hung-Chien; Ho, King-Yuan; Hsu, Chih-Chieh; Yan, Jing-Yi; Ho, Jia-Chong

2011-01-01

The reduction of photo-leakage current of amorphous silicon thin-film transistors (a-Si TFTs) is investigated and is found to be successfully suppressed by the use of an n-doped nanocrystalline silicon layer (n+ nc-Si) as an ohmic contact layer. The shallow-level defects of n+ nc-Si can become trapping centres of photo-induced electrons as the a-Si TFT is operated under light illumination. A lower oxygen concentration during n+ nc-Si deposition can increase the creation of shallow-level defects and improve the contrast ratio of active matrix organic light-emitting diode panels.

Sistem Proteksi Arus Bocor Menggunakan Earth Leakage Circuit Breaker Berbasis Arduino

OpenAIRE

Syukriyadin, Syukriyadin

2016-01-01

Touching a live part of electrical equipment either intentionally or unintentionally can cause an electric shock. The touch can occur directly or indirectly and results in the flow of electric current through the human body to the ground. This electric current is known as the leakage current and can have fatal effects on the human body such as burns, cramps, faint and death. This paper aims to design a prototype protection model of the earth leakage circuit breaker device based on Arduino (EL...

Artificial-Crack-Behavior Test Evaluation of the Water-Leakage Repair Materials Used for the Repair of Water-Leakage Cracks in Concrete Structures

Directory of Open Access Journals (Sweden)

Soo-Yeon Kim

2016-09-01

Full Text Available There are no existing standard test methods at home and abroad that can verify the performance of water leakage repair materials, and it is thus very difficult to perform quality control checks in the field of water leakage repair. This study determined that the key factors that have the greatest impact on the water leakage repair materials are the micro-behaviors of cracks, and proposed an artificial-crack-behavior test method for the performance verification of the repair materials. The performance of the 15 kinds of repair materials that are currently being used in the field of water leakage repair was evaluated by applying the proposed test method. The main aim of such a test method is to determine if there is water leakage by injecting water leakage repair materials into a crack behavior test specimen with an artificial 5-mm crack width, applying a 2.5 mm vertical behavior load at 100 cycles, and applying 0.3 N/mm2 constant water pressure. The test results showed that of the 15 kinds of repair materials, only two effectively sealed the crack and thus stopped the water leakage. The findings of this study confirmed the effectiveness of the proposed artificial-crack-behavior test method and suggest that it can be used as a performance verification method for checking the responsiveness of the repair materials being used in the field of water leakage repair to the repetitive water leakage behaviors that occur in concrete structures. The study findings further suggest that the use of the proposed test method makes it possible to quantify the water leakage repair quality control in the field.

ANALYTICAL MODELING OF ELECTRON BACK-BOMBARDMENT INDUCED CURRENT INCREASE IN UN-GATED THERMIONIC CATHODE RF GUNS

Energy Technology Data Exchange (ETDEWEB)

Edelen, J. P. [Fermilab; Sun, Y. [Argonne; Harris, J. R. [AFRL, NM; Lewellen, J. W. [Los Alamos Natl. Lab.

2016-09-28

In this paper we derive analytical expressions for the output current of an un-gated thermionic cathode RF gun in the presence of back-bombardment heating. We provide a brief overview of back-bombardment theory and discuss comparisons between the analytical back-bombardment predictions and simulation models. We then derive an expression for the output current as a function of the RF repetition rate and discuss relationships between back-bombardment, fieldenhancement, and output current. We discuss in detail the relevant approximations and then provide predictions about how the output current should vary as a function of repetition rate for some given system configurations.

Effect of ciguatoxin 3C on voltage-gated Na+ and K+ currents in mouse taste cells.

Science.gov (United States)

Ghiaroni, Valeria; Fuwa, Haruhiko; Inoue, Masayuki; Sasaki, Makoto; Miyazaki, Keisuke; Hirama, Masahiro; Yasumoto, Takeshi; Rossini, Gian Paolo; Scalera, Giuseppe; Bigiani, Albertino

2006-09-01

The marine dinoflagellate Gambierdiscus toxicus produces highly lipophilic, polycyclic ether toxins that cause a seafood poisoning called ciguatera. Ciguatoxins (CTXs) and gambierol represent the two major causative agents of ciguatera intoxication, which include taste alterations (dysgeusiae). However, information on the mode of action of ciguatera toxins in taste cells is scarce. Here, we have studied the effect of synthetic CTX3C (a CTX congener) on mouse taste cells. By using the patch-clamp technique to monitor membrane ion currents, we found that CTX3C markedly affected the operation of voltage-gated Na(+) channels but was ineffective on voltage-gated K(+) channels. This result was the exact opposite of what we obtained earlier with gambierol, which inhibits K(+) channels but not Na(+) channels. Thus, CTXs and gambierol affect with high potency the operation of separate classes of voltage-gated ion channels in taste cells. Our data suggest that taste disturbances reported in ciguatera poisoning might be due to the ability of ciguatera toxins to interfere with ion channels in taste buds.

Analysis of bias effects on the total ionizing dose response in a 180 nm technology

International Nuclear Information System (INIS)

Liu Zhangli; Hu Zhiyuan; Zhang, Zhengxuan; Shao Hua; Chen Ming; Bi Dawei; Ning Bingxu; Zou Shichang

2011-01-01

The effects of gamma ray irradiation on the shallow trench isolation (STI) leakage current in a 180 nm technology are investigated. The radiation response is strongly influenced by the bias modes, gate bias during irradiation, substrate bias during irradiation and operating substrate bias after irradiation. We found that the worst case occurs under the ON bias condition for the ON, OFF and PASS bias mode. A positive gate bias during irradiation significantly enhances the STI leakage current, indicating the electric field influence on the charge buildup process during radiation. Also, a negative substrate bias during irradiation enhances the STI leakage current. However a negative operating substrate bias effectively suppresses the STI leakage current, and can be used to eliminate the leakage current produced by the charge trapped in the deep STI oxide. Appropriate substrate bias should be introduced to alleviate the total ionizing dose (TID) response, and lead to acceptable threshold voltage shift and subthreshold hump effect. Depending on the simulation results, we believe that the electric field distribution in the STI oxide is the key parameter influencing bias effects on the radiation response of transistor. - Highlights: → ON bias is the worst bias condition for the ON, PASS and OFF bias modes. → Larger gate bias during irradiation leads to more pronounced characteristic degradation. → TID induced STI leakage can be suppressed by negative operating substrate bias voltage. → Negative substrate bias during irradiation leads to larger increase of off-state leakage. → Electric field in the STI oxide greatly influences the device's radiation effect.

Current collapse imaging of Schottky gate AlGaN/GaN high electron mobility transistors by electric field-induced optical second-harmonic generation measurement

International Nuclear Information System (INIS)

Katsuno, Takashi; Ishikawa, Tsuyoshi; Ueda, Hiroyuki; Uesugi, Tsutomu; Manaka, Takaaki; Iwamoto, Mitsumasa

2014-01-01

Two-dimensional current collapse imaging of a Schottky gate AlGaN/GaN high electron mobility transistor device was achieved by optical electric field-induced second-harmonic generation (EFISHG) measurements. EFISHG measurements can detect the electric field produced by carriers trapped in the on-state of the device, which leads to current collapse. Immediately after (e.g., 1, 100, or 800 μs) the completion of drain-stress voltage (200 V) in the off-state, the second-harmonic (SH) signals appeared within 2 μm from the gate edge on the drain electrode. The SH signal intensity became weak with time, which suggests that the trapped carriers are emitted from the trap sites. The SH signal location supports the well-known virtual gate model for current collapse.

Precise linear gating circuit on integrated microcircuits

Energy Technology Data Exchange (ETDEWEB)

Butskii, V.V.; Vetokhin, S.S.; Reznikov, I.V.

Precise linear gating circuit on four microcircuits is described. A basic flowsheet of the gating circuit is given. The gating circuit consists of two input differential cascades total load of which is two current followers possessing low input and high output resistances. Follower outlets are connected to high ohmic dynamic load formed with a current source which permits to get high amplification (>1000) at one cascade. Nonlinearity amounts to <0.1% in the range of input signal amplitudes of -10-+10 V. Front duration for an output signal with 10 V amplitude amounts to 100 ns. Attenuation of input signal with a closed gating circuit is 60 db. The gating circuits described is used in the device intended for processing of scintillation sensor signals.

Current transmission and nonlinear effects in un-gated thermionic cathode RF guns

Energy Technology Data Exchange (ETDEWEB)

Edelen, J. P. [Fermilab; Harris, J. R. [Air Force Weapons Lab

2017-05-03

Un-gated thermionic cathode RF guns are well known as a robust source of electrons for many accelerator applications. These sources are in principle scalable to high currents without degradation of the transverse emittance due to control grids but they are also known for being limited by back-bombardment. While back-bombardment presents a significant limitation, there is still a lack of general understanding on how emission over the whole RF period will affect the nature of the beams produced from these guns. In order to improve our understanding of how these guns can be used in general we develop analytical models that predict the transmission efficiency as a function of the design parameters, study how bunch compression and emission enhancement caused by Schottky barrier lowering affect the output current profile in the gun, and study the onset of space-charge limited effects and the resultant virtual cathode formation leading to a modulation in the output current distribution.

Modeling and simulation of floating gate nanocrystal FET devices and circuits

Science.gov (United States)

Hasaneen, El-Sayed A. M.

The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to

Laser-assisted electron emission from gated field-emitters

CERN Document Server

Ishizuka, H; Yokoo, K; Mimura, H; Shimawaki, H; Hosono, A

2002-01-01

Enhancement of electron emission by illumination of gated field-emitters was studied using a 100 mW cw YAG laser at a wavelength of 532 nm, intensities up to 10 sup 7 W/m sup 2 and mechanically chopped with a rise time of 4 mu s. When shining an array of 640 silicon emitters, the emission current responded quickly to on-off of the laser. The increase of the emission current was proportional to the basic emission current at low gate voltages, but it was saturated at approx 3 mu A as the basic current approached 100 mu A with the increase of gate voltage. The emission increase was proportional to the square root of laser power at low gate voltages and to the laser power at elevated gate voltages. For 1- and 3-tip silicon emitters, the rise and fall of the current due to on-off of the laser showed a significant time lag. The magnitude of emission increase was independent of the position of laser spot on the emitter base and reached 2 mu A at a basic current of 5 mu A without showing signs of saturation. The mech...

A Review of Nanoscale Channel and Gate Engineered FINFETs for VLSI Mixed Signal Applications Using Zirconium-di-Oxide Dielectrics

Directory of Open Access Journals (Sweden)

D.Nirmal

2014-07-01

Full Text Available In the past, most of the research and development efforts in the area of CMOS and IC’s are oriented towards reducing the power and increasing the gain of the circuits. While focusing the attention on low power and high gain in the device, the materials of the device also been taken into consideration. In the present technology, Computationally intensive devices with low power dissipation and high gain are becoming a critical application domain. Several factors have contributed to this paradigm shift. The primary driving factor being the increase in scale of integration, the chip has to accommodate smaller and faster transistors than their predecessors. During the last decade semiconductor technology has been led by conventional scaling. Scaling, has been aimed towards higher speed, lower power and higher density of the semiconductor devices. However, as scaling approached its physical limits, it has become more difficult and challenging for fabrication industry. Therefore, tremendous research has been carried out to investigate the alternatives, and this led to the introduction of new Nano materials and concepts to overcome the difficulties in the device fabrications. In order to reduce the leakage current and parasitic capacitance in devices, gate oxide high-k dielectric materials are explored. Among the different high-k materials available the nano size Zirconium dioxide material is suggested as an alternate gate oxide material for devices due to its thermal stability and small grain size of material. To meet the requirements of ITRS roadmap 2012, the Multi gate devices are considered to be one of the most promising technologies for the future microelectronics industry due to its excellent immunity to short channel effects and high value of On current. The double gate or multi gate devices provide a better scalability option due to its excellent immunity to short-channel effects. Here the different high-k materials are replaced in different

Carrier Transport of Silver Nanowire Contact to p-GaN and its Influence on Leakage Current of LEDs

Science.gov (United States)

Oh, Munsik; Kang, Jae-Wook; Kim, Hyunsoo

2018-03-01

The authors investigated the silver nanowires (AgNWs) contact formed on p-GaN. Transmission line model applied to the AgNWs contact to p-GaN produced near ohmic contact with a specific contact resistance (ρ sc) of 10-1˜10-4 Ω·cm2. Noticeably, the contact resistance had a strong bias-voltage (or current-density) dependence associated with a local joule heating effect. Current-voltage-temperature (I-V-T) measurement revealed a strong temperature dependence with respect to ρ sc, indicating that the temperature played a key role of an enhanced carrier transport. The local joule heating at AgNW/GaN interface, however, resulted in a generation of leakage current of light-emitting diodes (LEDs) caused by degradation of AgNW contact.

Leakage characterization of top select transistor for program disturbance optimization in 3D NAND flash

Science.gov (United States)

Zhang, Yu; Jin, Lei; Jiang, Dandan; Zou, Xingqi; Zhao, Zhiguo; Gao, Jing; Zeng, Ming; Zhou, Wenbin; Tang, Zhaoyun; Huo, Zongliang

2018-03-01

In order to optimize program disturbance characteristics effectively, a characterization approach that measures top select transistor (TSG) leakage from bit-line is proposed to quantify TSG leakage under program inhibit condition in 3D NAND flash memory. Based on this approach, the effect of Vth modulation of two-cell TSG on leakage is evaluated. By checking the dependence of leakage and corresponding program disturbance on upper and lower TSG Vth, this approach is validated. The optimal Vth pattern with high upper TSG Vth and low lower TSG Vth has been suggested for low leakage current and high boosted channel potential. It is found that upper TSG plays dominant role in preventing drain induced barrier lowering (DIBL) leakage from boosted channel to bit-line, while lower TSG assists to further suppress TSG leakage by providing smooth potential drop from dummy WL to edge of TSG, consequently suppressing trap assisted band-to-band tunneling current (BTBT) between dummy WL and TSG.

Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure.

Directory of Open Access Journals (Sweden)

Z N Khan

Full Text Available Metal Oxide Semiconductor (MOS capacitors (MOSCAP have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer, time-temperature cycle and sequence are key parameters influencing the device's output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application.

FNR demonstration experiments Part I: Beam port leakage currents and spectra

International Nuclear Information System (INIS)

Wehe, D.K.; King, J.S.

1983-01-01

The goal of the NR-LEU experimental program has been to measure the changes in numerous reactor characteristics when the conventional HEU core is replaced by a complete LEU fueled core or by a single LEU element in the normal HEU core. We have observed comparisons in a) thermal flux intensity, spatial distribution and cadmium ratios, both in the core and in the light and heavy water reflectors, b) fast flux intensity and spectral shape at a special element within the core, c) the thermal leakage flux intensity at the exit positions of several beam ports and its spectral shape at one beam port, d) shim and control rod worths, e) temperature coefficient of reactivity, and f) xenon poison worth. The NR is a 2 MW light water pool reactor, reflected on three faces by light water and on one face by D 2 O, composed of MTR plate fuel elements. Figure shows a plan view of the core grid, D 2 O reflector tank, and beam ports. The conventional HEU fuel element contains eighteen MTR Al plates 30 in x 24 in x 0.06 in. The center 0.02 in of each plate is 93% U-235 enriched UAl x . A normal equilibrium HEU core loading is outlined. Each new HEU element contains ∼ 140 grams of U-235. The LEU low enrichment fuel retains the same plate and element geometry but the fuel is contained in a central 0.03 in thick UA l x matrix with 19.5% U-235 enrichment. Each new LEU element contains ov 167.3 grams U-235. In-core neutron fluxes were routinely mapped by a rhodium SPND and by many wire and foil activations. The same data, but in more restricted positions, were obtained through the light water reflector (south) and D 2 O reflector tank (north). Beam port leakage currents were measured during all power cycles, by transmission fission chambers at the exits of ports GI, and J, by a B3 detector at A-port, and by a prompt detector at the F-port exit. Thermal neutron spectra for both HEU and LEU cores were measured at I port using a single crystal silicon diffractometer. These measurements

Analysis of gate underlap channel double gate MOS transistor for electrical detection of bio-molecules

Science.gov (United States)

Ajay; Narang, Rakhi; Saxena, Manoj; Gupta, Mridula

2015-12-01

In this paper, an analytical model for gate drain underlap channel Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG-MOSFET) for label free electrical detection of biomolecules has been proposed. The conformal mapping technique has been used to derive the expressions for surface potential, lateral electric field, energy bands (i.e. conduction and valence band) and threshold voltage (Vth). Subsequently a full drain current model to analyze the sensitivity of the biosensor has been developed. The shift in the threshold voltage and drain current (after the biomolecules interaction with the gate underlap channel region of the MOS transistor) has been used as a sensing metric. All the characteristic trends have been verified through ATLAS (SILVACO) device simulation results.

Gated-controlled electron pumping in connected quantum rings

International Nuclear Information System (INIS)

Lima, R.P.A.; Domínguez-Adame, F.

2014-01-01

We study the electronic transport across connected quantum rings attached to leads and subjected to time-harmonic side-gate voltages. Using the Floquet formalism, we calculate the net pumped current generated and controlled by the side-gate voltage. The control of the current is achieved by varying the phase shift between the two side-gate voltages as well as the Fermi energy. In particular, the maximum current is reached when the side-gate voltages are in quadrature. This new design based on connected quantum rings controlled without magnetic fields can be easily integrated in standard electronic devices. - Highlights: • We introduce and study a minimal setup to pump electrons through connected quantum rings. • Quantum pumping is achieved by time-harmonic side-gate voltages instead of the more conventional time-dependent magnetic fluxes. • Our new design could be easily integrated in standard electronic devices

2-D analytical modeling of subthreshold current and subthreshold swing for ion-implanted strained-Si double-material double-gate (DMDG) MOSFETs

Science.gov (United States)

Goel, Ekta; Singh, Kunal; Singh, Balraj; Kumar, Sanjay; Jit, Satyabrata

2017-09-01

In this paper, the subthreshold behavior of ion-implanted strained-Si double-material double-gate (DMDG) MOSFETs has been analyzed by means of subthreshold current and subthreshold swing. The surface potential based formulation of subthreshold current and subthreshold swing is done by solving the 2-D Poisson's equations in the channel region using parabolic approximation method. The dependence of subthreshold characteristics on various device parameters such as gate length ratio, Ge mole fraction, peak doping concentration, projected range, straggle parameter etc. has been studied. The modeling results are found to be well matched with the simulation data obtained by a 2-D device simulator, ATLAS™, from SILVACO.

Practical Leakage-Resilient Symmetric Cryptography

DEFF Research Database (Denmark)

Faust, Sebastian; Pietrzak, Krzysztof; Schipper, Joachim

2012-01-01

Leakage resilient cryptography attempts to incorporate side-channel leakage into the black-box security model and designs cryptographic schemes that are provably secure within it. Informally, a scheme is leakage-resilient if it remains secure even if an adversary learns a bounded amount of arbitr......Leakage resilient cryptography attempts to incorporate side-channel leakage into the black-box security model and designs cryptographic schemes that are provably secure within it. Informally, a scheme is leakage-resilient if it remains secure even if an adversary learns a bounded amount...

Model for Electromagnetic Information Leakage

OpenAIRE

Mao Jian; Li Yongmei; Zhang Jiemin; Liu Jinming

2013-01-01

Electromagnetic leakage will happen in working information equipments; it could lead to information leakage. In order to discover the nature of information in electromagnetic leakage, this paper combined electromagnetic theory with information theory as an innovative research method. It outlines a systematic model of electromagnetic information leakage, which theoretically describes the process of information leakage, intercept and reproduction based on electromagnetic radiation, and ana...

Effects of Y incorporation in TaON gate dielectric on electrical performance of GaAs metal-oxide-semiconductor capacitor

Energy Technology Data Exchange (ETDEWEB)

Liu, Li Ning; Choi, Hoi Wai; Lai, Pui To [Department of Electrical and Electronic Engineering, The University of Hong Kong (China); Xu, Jing Ping [School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan (China)

2016-09-15

In this study, GaAs metal-oxide-semiconductor (MOS) capacitors using Y-incorporated TaON as gate dielectric have been investigated. Experimental results show that the sample with a Y/(Y + Ta) atomic ratio of 27.6% exhibits the best device characteristics: high k value (22.9), low interfacestate density (9.0 x 10{sup 11} cm{sup -2} eV{sup -1}), small flatband voltage (1.05 V), small frequency dispersion and low gate leakage current (1.3 x 10{sup -5}A/cm{sup 2} at V{sub fb} + 1 V). These merits should be attributed to the complementary properties of Y{sub 2}O{sub 3} and Ta{sub 2}O{sub 5}:Y can effectively passivate the large amount of oxygen vacancies in Ta{sub 2}O{sub 5}, while the positively-charged oxygen vacancies in Ta{sub 2}O{sub 5} are capable of neutralizing the effects of the negative oxide charges in Y{sub 2}O{sub 3}. This work demonstrates that an appropriate doping of Y content in TaON gate dielectric can effectively improve the electrical performance for GaAs MOS devices. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Structured-gate organic field-effect transistors

International Nuclear Information System (INIS)

Aljada, Muhsen; Pandey, Ajay K; Velusamy, Marappan; Burn, Paul L; Meredith, Paul; Namdas, Ebinazar B

2012-01-01

We report the fabrication and electrical characteristics of structured-gate organic field-effect transistors consisting of a gate electrode patterned with three-dimensional pillars. The pillar gate electrode was over-coated with a gate dielectric (SiO 2 ) and solution processed organic semiconductors producing both unipolar p-type and bipolar behaviour. We show that this new structured-gate architecture delivers higher source-drain currents, higher gate capacitance per unit equivalent linear channel area, and enhanced charge injection (electrons and/or holes) versus the conventional planar structure in all modes of operation. For the bipolar field-effect transistor (FET) the maximum source-drain current enhancements in p- and n-channel mode were >600% and 28%, respectively, leading to p and n charge mobilities with the same order of magnitude. Thus, we have demonstrated that it is possible to use the FET architecture to manipulate and match carrier mobilities of material combinations where one charge carrier is normally dominant. Mobility matching is advantageous for creating organic logic circuit elements such as inverters and amplifiers. Hence, the method represents a facile and generic strategy for improving the performance of standard organic semiconductors as well as new materials and blends. (paper)

Structured-gate organic field-effect transistors

Science.gov (United States)

Aljada, Muhsen; Pandey, Ajay K.; Velusamy, Marappan; Burn, Paul L.; Meredith, Paul; Namdas, Ebinazar B.

2012-06-01

We report the fabrication and electrical characteristics of structured-gate organic field-effect transistors consisting of a gate electrode patterned with three-dimensional pillars. The pillar gate electrode was over-coated with a gate dielectric (SiO2) and solution processed organic semiconductors producing both unipolar p-type and bipolar behaviour. We show that this new structured-gate architecture delivers higher source-drain currents, higher gate capacitance per unit equivalent linear channel area, and enhanced charge injection (electrons and/or holes) versus the conventional planar structure in all modes of operation. For the bipolar field-effect transistor (FET) the maximum source-drain current enhancements in p- and n-channel mode were >600% and 28%, respectively, leading to p and n charge mobilities with the same order of magnitude. Thus, we have demonstrated that it is possible to use the FET architecture to manipulate and match carrier mobilities of material combinations where one charge carrier is normally dominant. Mobility matching is advantageous for creating organic logic circuit elements such as inverters and amplifiers. Hence, the method represents a facile and generic strategy for improving the performance of standard organic semiconductors as well as new materials and blends.

A Grid Connected Transformerless Inverter and its Model Predictive Control Strategy with Leakage Current Elimination Capability

Directory of Open Access Journals (Sweden)

J. Fallah Ardashir

2017-06-01

Full Text Available This paper proposes a new single phase transformerless Photovoltaic (PV inverter for grid connected systems. It consists of six power switches, two diodes, one capacitor and filter at the output stage. The neutral of the grid is directly connected to the negative terminal of the source. This results in constant common mode voltage and zero leakage current. Model Predictive Controller (MPC technique is used to modulate the converter to reduce the output current ripple and filter requirements. The main advantages of this inverter are compact size, low cost, flexible grounding configuration. Due to brevity, the operating principle and analysis of the proposed circuit are presented in brief. Simulation and experimental results of 200W prototype are shown at the end to validate the proposed topology and concept. The results obtained clearly verifies the performance of the proposed inverter and its practical application for grid connected PV systems.

Comparison of different surface passivation dielectrics in AlGaN/GaN heterostructure field-effect transistors

International Nuclear Information System (INIS)

Tan, W.S.; Parbrook, P.J.; Hill, G.; Airey, R.J.; Houston, P.A.

2002-01-01

Different dielectrics were used for post-processing surface passivation of AlGaN/GaN heterostructure field-effect transistors (HFETs) and the resulting electrical characteristics examined. An increase in the maximum drain current of approximately 25% was observed after Si 3 N 4 and SiO 2 deposition and ∼15% for annealed SiO on AlGaN/GaN HFETs. In all cases, the passivation was found to increase the gate leakage current with an observed reduction in the leakage activation energy. However, the rise in gate leakage current was least for SiO. The plasma enhanced chemical vapour deposition method was found not to contribute to the passivation mechanism, whilst the presence of Si appears to be an important factor. (author)

ATR confinement leakage determination

International Nuclear Information System (INIS)

Kuan, P.; Buescher, B.J.

1998-01-01

The air leakage rate from the Advanced Test Reactor (ATR) confinement is an important parameter in estimating hypothesized accidental releases of radiation to the environment. The leakage rate must be determined periodically to assure that the confinement has not degraded with time and such determination is one of the technical safety requirements of ATR operation. This paper reviews the methods of confinement leakage determination and presents an analysis of leakage determination under windy conditions, which can complicate the interpretation of the determined leakage rates. The paper also presents results of analyses of building air exchange under windy conditions. High wind can enhance air exchange and this could increase the release rates of radioisotopes following an accident

Performance analysis of 20 nm gate-length In0.2Al0.8N/GaN HEMT with Cu-gate having a remarkable high ION/IOFF ratio

International Nuclear Information System (INIS)

Bhattacharjee, A.; Lenka, T. R.

2014-01-01

We propose a new structure of In x Al 1−x N/GaN high electron mobility transistor (HEMT) with gate length of 20 nm. The threshold voltage of this HEMT is achieved as −0.472 V. In this device the InAlN barrier layer is intentionally n-doped to boost the I ON /I OFF ratio. The InAlN layer acts as donor barrier layer for this HEMT which exhibits an I ON = 10 −4.3 A and a very low I OFF = 10 −14.4 A resulting in an I ON /I OFF ratio of 10 10.1 . We compared our obtained results with the conventional InAlN/GaN HEMT device having undoped barrier and found that the proposed device has almost 10 5 times better I ON /I OFF ratio. Further, the mobility analysis in GaN channel of this proposed HEMT structure along with DC analysis, C–V and conductance characteristics by using small-signal analysis are also presented in this paper. Moreover, the shifts in threshold voltage by DIBL effect and gate leakage current in the proposed HEMT are also discussed. InAlN was chosen as the most preferred barrier layer as a replacement of AlGaN for its excellent thermal conductivity and very good scalability. (semiconductor devices)

Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors.

Science.gov (United States)

Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

2016-12-01

In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade(-1) and 3.62 × 10(11) eV(-1) cm(-2), respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

Leakage pattern of linear accelerator treatment heads from multiple vendors

International Nuclear Information System (INIS)

Lonski, P.R.; Taylor, M.L.; Franich, R.D.; Harty, P.; Clements, N.; Kron, T.

2011-01-01

Full text: Patient life expectancy post-radiotherapy is becoming longer. Therefore, secondary cancers caused by radiotherapy treatment have more time to develop. Increasing attention is being given to out-of-field dose resulting from scatter and accelerator head leakage. Dose leakage from equivalent positions on Varian600C, Varian21-X, Siemens Primus and Elekta Synergy-II linacs were measured with TLD 1 00 H dosimeter chips and compared. Treatment parameters such as field size and beam energy were altered. Leakage doses are presented as a percentage of the dose to isocentre (5 Gy). Results illustrate significant variations in leakage dose between linac models where no model emits consistently lower amounts of radiation leakage for all treatment parameters. Results are shown below. Leakage through the collimator assembly in different units is varying as a function of location and unit design by more than a factor of 10. Differences are more pronounced in comparing Varian or Elekta models, which are fitted with an additional collimator separate from the MLC leaves, to the Siemens model, which uses MLC leaves as its only secondary collimator. Further measurements are currently being taken at the patient plane with a directional detector system to determine the spatial distribution of high leakage sources.

Dual-gate polysilicon nanoribbon biosensors enable high sensitivity detection of proteins

International Nuclear Information System (INIS)

Zeimpekis, I; Sun, K; Hu, C; Ditshego, N M J; De Planque, M R R; Chong, H M H; Morgan, H; Ashburn, P; Thomas, O

2016-01-01

We demonstrate the advantages of dual-gate polysilicon nanoribbon biosensors with a comprehensive evaluation of different measurement schemes for pH and protein sensing. In particular, we compare the detection of voltage and current changes when top- and bottom-gate bias is applied. Measurements of pH show that a large voltage shift of 491 mV pH"−"1 is obtained in the subthreshold region when the top-gate is kept at a fixed potential and the bottom-gate is varied (voltage sweep). This is an improvement of 16 times over the 30 mV pH"−"1 measured using a top-gate sweep with the bottom-gate at a fixed potential. A similar large voltage shift of 175 mV is obtained when the protein avidin is sensed using a bottom-gate sweep. This is an improvement of 20 times compared with the 8.8 mV achieved from a top-gate sweep. Current measurements using bottom-gate sweeps do not deliver the same signal amplification as when using bottom-gate sweeps to measure voltage shifts. Thus, for detecting a small signal change on protein binding, it is advantageous to employ a double-gate transistor and to measure a voltage shift using a bottom-gate sweep. For top-gate sweeps, the use of a dual-gate transistor enables the current sensitivity to be enhanced by applying a negative bias to the bottom-gate to reduce the carrier concentration in the nanoribbon. For pH measurements, the current sensitivity increases from 65% to 149% and for avidin sensing it increases from 1.4% to 2.5%. (paper)

On photonic controlled phase gates

International Nuclear Information System (INIS)

Kieling, K; Eisert, J; O'Brien, J L

2010-01-01

As primitives for entanglement generation, controlled phase gates have a central role in quantum computing. Especially in ideas realizing instances of quantum computation in linear optical gate arrays, a closer look can be rewarding. In such architectures, all effective nonlinearities are induced by measurements. Hence the probability of success is a crucial parameter of such quantum gates. In this paper, we discuss this question for controlled phase gates that implement an arbitrary phase with one and two control qubits. Within the class of post-selected gates in dual-rail encoding with vacuum ancillas, we identify the optimal success probabilities. We construct networks that allow for implementation using current experimental capabilities in detail. The methods employed here appear specifically useful with the advent of integrated linear optical circuits, providing stable interferometers on monolithic structures.

Accurate current synchronization trigger mode for multi-framing gated camera on YANG accelerator

International Nuclear Information System (INIS)

Jiang Xiaoguo; Huang Xianbin; Li Chenggang; Yang Libing; Wang Yuan; Zhang Kaizhi; Ye Yi

2007-01-01

The current synchronization trigger mode is important for Z-pinch experiments carried out on the YANG accelerator. The technology can solve the problem of low synchronization precision. The inherent delay time between the load current waveform and the experimental phenomenon can be adopted to obtain the synchronization trigger time. The correlative time precision about ns level can be achieved in this way. The photoelectric isolator and optical fiber are used in the synchronization trigger system to eliminate the electro-magnetic interference and many accurate measurements on the YANG accelerator can be realized. The application of this trigger mode to the multi-framing gated camera synchronization trigger system has done the trick. The evolution course of Z-pinch imploding plasma has been recorded with 3 ns exposure time and 10 ns interframing time. (authors)

Universal leakage elimination

International Nuclear Information System (INIS)

Byrd, Mark S.; Lidar, Daniel A.; Wu, L.-A.; Zanardi, Paolo

2005-01-01

'Leakage' errors are particularly serious errors which couple states within a code subspace to states outside of that subspace, thus destroying the error protection benefit afforded by an encoded state. We generalize an earlier method for producing leakage elimination decoupling operations and examine the effects of the leakage eliminating operations on decoherence-free or noiseless subsystems which encode one logical, or protected qubit into three or four qubits. We find that by eliminating a large class of leakage errors, under some circumstances, we can create the conditions for a decoherence-free evolution. In other cases we identify a combined decoherence-free and quantum error correcting code which could eliminate errors in solid-state qubits with anisotropic exchange interaction Hamiltonians and enable universal quantum computing with only these interactions

Super high voltage Schottky diode with low leakage current for x- and γ-ray detector application

International Nuclear Information System (INIS)

Kosyachenko, L. A.; Sklyarchuk, V. M.; Sklyarchuk, O. F.; Maslyanchuk, O. L.; Gnatyuk, V. A.; Aoki, T.

2009-01-01

A significant improvement in x-/γ-ray detector performance has been achieved by forming both rectifying and near-Ohmic contacts by the deposition of Ni on opposite surfaces of semi-insulating CdTe crystals pretreated by special chemical etching and Ar-ion bombardment with different parameters. The reduced injection of the minority carriers from the near-Ohmic contact in the neutral part of the diode provides low leakage current even at high bias ( 2 at 2000 V and 293 K). The electrical properties of the detectors are well described quantitatively by the generation-recombination Sah-Noyce-Shockley theory excepting the high reverse voltage range where some injection of minority carriers takes place

Performance testing of prototype live loaded packed stem seals for large gate valves in pressurized hot water

International Nuclear Information System (INIS)

Pothier, N.E.

1976-01-01

Prototype live loaded packed stem seals for large gate valves have been tested in a laboratory. The test fluid was demineralized water at 547 K, 8.27 MPa and pH 10. Nine packing configurations were tested; three different commercial brands of asbestos/graphite valve packings and three different sizes for each packing brand. Conventional and live loaded packed stem seals are briefly described. Stem leakage, packing consolidation and stem friction data are given. For all tests, leakage rates of less than 10 g d -1 were observed. It was also observed that stem friction was significantly affected by thermal expansion of the stem. (author)

Coherent molecular transistor: control through variation of the gate wave function.

Science.gov (United States)

Ernzerhof, Matthias

2014-03-21

In quantum interference transistors (QUITs), the current through the device is controlled by variation of the gate component of the wave function that interferes with the wave function component joining the source and the sink. Initially, mesoscopic QUITs have been studied and more recently, QUITs at the molecular scale have been proposed and implemented. Typically, in these devices the gate lead is subjected to externally adjustable physical parameters that permit interference control through modifications of the gate wave function. Here, we present an alternative model of a molecular QUIT in which the gate wave function is directly considered as a variable and the transistor operation is discussed in terms of this variable. This implies that we specify the gate current as well as the phase of the gate wave function component and calculate the resulting current through the source-sink channel. Thus, we extend on prior works that focus on the phase of the gate wave function component as a control parameter while having zero or certain discrete values of the current. We address a large class of systems, including finite graphene flakes, and obtain analytic solutions for how the gate wave function controls the transistor.

Coherent molecular transistor: Control through variation of the gate wave function

International Nuclear Information System (INIS)

Ernzerhof, Matthias

2014-01-01

In quantum interference transistors (QUITs), the current through the device is controlled by variation of the gate component of the wave function that interferes with the wave function component joining the source and the sink. Initially, mesoscopic QUITs have been studied and more recently, QUITs at the molecular scale have been proposed and implemented. Typically, in these devices the gate lead is subjected to externally adjustable physical parameters that permit interference control through modifications of the gate wave function. Here, we present an alternative model of a molecular QUIT in which the gate wave function is directly considered as a variable and the transistor operation is discussed in terms of this variable. This implies that we specify the gate current as well as the phase of the gate wave function component and calculate the resulting current through the source-sink channel. Thus, we extend on prior works that focus on the phase of the gate wave function component as a control parameter while having zero or certain discrete values of the current. We address a large class of systems, including finite graphene flakes, and obtain analytic solutions for how the gate wave function controls the transistor

Subattoampere current induced by single ions in silicon oxide layers of nonvolatile memory cells

International Nuclear Information System (INIS)

Cellere, G.; Paccagnella, A.; Larcher, L.; Visconti, A.; Bonanomi, M.

2006-01-01

A single ion impinging on a thin silicon dioxide layer generates a number of electron/hole pairs proportional to its linear energy transfer coefficient. Defects generated by recombination can act as a conductive path for electrons that cross the oxide barrier, thanks to a multitrap-assisted mechanism. We present data on the dependence of this phenomenon on the oxide thickness by using floating gate memory arrays. The tiny number of excess electrons stored in these devices allows for extremely high sensitivity, impossible with any direct measurement of oxide leakage current. Results are of particular interest for next generation devices

[Bile leakage after liver resection: A retrospective cohort study].

Science.gov (United States)

Menclová, K; Bělina, F; Pudil, J; Langer, D; Ryska, M

2015-12-01

Many previous reports have focused on bile leakage after liver resection. Despite the improvements in surgical techniques and perioperative care the incidence of this complication rather keeps increasing. A number of predictive factors have been analyzed. There is still no consensus regarding their influence on the formation of bile leakage. The objective of our analysis was to evaluate the incidence of bile leakage, its impact on mortality and duration of hospitalization at our department. At the same time, we conducted an analysis of known predictive factors. The authors present a retrospective review of the set of 146 patients who underwent liver resection at the Department of Surgery of the 2nd Faculty of Medicine of the Charles University and Central Military Hospital Prague, performed between 20102013. We used the current ISGLS (International Study Group of Liver Surgery) classification to evaluate the bile leakage. The severity of this complication was determined according to the Clavien-Dindo classification system. Statistical significance of the predictive factors was determined using Fishers exact test and Students t-test. The incidence of bile leakage was 21%. According to ISGLS classification the A, B, and C rates were 6.5%, 61.2%, and 32.3%, respectively. The severity of bile leakage according to the Clavien-Dindo classification system - I-II, IIIa, IIIb, IV and V rates were 19.3%, 42%, 9.7%, 9.7%, and 19.3%, respectively. We determined the following predictive factors as statistically significant: surgery for malignancy (pBile leakage significantly prolonged hospitalization time (pbile leakage the perioperative mortality was 23 times higher (pBile leakage is one of the most serious complications of liver surgery. Most of the risk factors are not easily controllable and there is no clear consensus on their influence. Intraoperative leak tests could probably reduce the incidence of bile leakage. In the future, further studies will be required to improve

Edge-on gating effect in molecular wires.

Science.gov (United States)

Lo, Wai-Yip; Bi, Wuguo; Li, Lianwei; Jung, In Hwan; Yu, Luping

2015-02-11

This work demonstrates edge-on chemical gating effect in molecular wires utilizing the pyridinoparacyclophane (PC) moiety as the gate. Different substituents with varied electronic demands are attached to the gate to simulate the effect of varying gating voltages similar to that in field-effect transistor (FET). It was observed that the orbital energy level and charge carrier's tunneling barriers can be tuned by changing the gating group from strong electron acceptors to strong electron donors. The single molecule conductance and current-voltage characteristics of this molecular system are truly similar to those expected for an actual single molecular transistor.

Top-gated field-effect LaAlO{sub 3}/SrTiO{sub 3} devices made by ion-irradiation

Energy Technology Data Exchange (ETDEWEB)

Hurand, S.; Jouan, A.; Feuillet-Palma, C.; Singh, G.; Malnou, M.; Lesueur, J.; Bergeal, N. [Laboratoire de Physique et d' Etude des Matériaux-CNRS-ESPCI ParisTech-UPMC, PSL Research University, 10 Rue Vauquelin - 75005 Paris (France); Lesne, E.; Reyren, N.; Barthélémy, A.; Bibes, M.; Villegas, J. E. [Unité Mixte de Physique CNRS-Thales, 1 Av. A. Fresnel, 91767 Palaiseau (France); Ulysse, C. [Laboratoire de Photonique et de Nanostructures LPN-CNRS, Route de Nozay, 91460 Marcoussis and Universit Paris Sud, 91405 Orsay (France); Pannetier-Lecoeur, M. [DSM/IRAMIS/SPEC - CNRS UMR 3680, CEA Saclay, F-91191 Gif-sur-Yvette Cedex (France)

2016-02-01

We present a method to fabricate top-gated field-effect devices in a LaAlO{sub 3}/SrTiO{sub 3} two-dimensional electron gas (2-DEG). Prior to the gate deposition, the realisation of micron size conducting channels in the 2-DEG is achieved by an ion-irradiation with high-energy oxygen ions. After identifying the ion fluence as the key parameter that determines the electrical transport properties of the channels, we demonstrate the field-effect operation. At low temperature, the normal state resistance and the superconducting T{sub c} can be tuned over a wide range by a top-gate voltage without any leakage. A superconductor-to-insulator quantum phase transition is observed for a strong depletion of the 2-DEG.

Condensate-polisher resin-leakage quantification and resin-transport studies

International Nuclear Information System (INIS)

Stauffer, C.C.; Doss, P.L.

1983-04-01

The objectives of this program were to: (1) determine the extent of resin leakage from current generation condensate polisher systems, both deep bed and powdered resin design, during cut-in, steady-state and flow transient operation, (2) analyze moisture separator drains and other secondary system samples for resin fragments and (3) document the level of organics in the secondary system. Resin leakage samples were obtained from nine-power stations that have either recirculating steam generators or once through steam generators. Secondary system samples were obtained from steam generator feedwater, recirculating steam generator blowdown and moisture separator drains. Analysis included ultraviolet light examination, SEM/EDX, resin quantification and infrared analysis. Data obtained from the various plants were compared and factors affecting resin leakage were summarized

Gate controlled high efficiency ballistic energy conversion system

NARCIS (Netherlands)

Xie, Yanbo; Bos, Diederik; de Boer, Hans L.; van den Berg, Albert; Eijkel, Jan C.T.; Zengerle, R.

2013-01-01

Last year we demonstrated the microjet ballistic energy conversion system[1]. Here we show that the efficiency of such a system can be further improved by gate control. With gate control the electrical current generation is enhanced a hundred times with respect to the current generated from the zeta

Coolant leakage detecting device

International Nuclear Information System (INIS)

Yamauchi, Kiyoshi; Kawai, Katsunori; Ishihara, Yoshinao.

1995-01-01

The device of the present invention judges an amount of leakage of primary coolants of a PWR power plant at high speed. Namely, a mass of coolants contained in a pressurizer, a volume controlling tank and loop regions is obtained based on a preset relational formula and signals of each of process amount, summed up to determine the total mass of coolants for every period of time. The amount of leakage for every period of time is calculated by a formula of Karman's filter based on the total mass of the primary coolants for every predetermined period of time, and displays it on CRT. The Karman's filter is formed on every formula for several kinds of states formed based on the preset amount of the leakage, to calculate forecasting values for every mass of coolants. An adaptable probability for every preset leakage amount is determined based on the difference between the forecast value and the observed value and the scattering thereof. The adaptable probability is compared with a predetermined threshold value, which is displayed on the CRT. This device enables earlier detection of leakage and identification of minute leakage amount as compared with the prior device. (I.S.)

Leakage current behavior in lead-free ferroelectric (K,Na)NbO3-LiTaO3-LiSbO3 thin films

Science.gov (United States)

Abazari, M.; Safari, A.

2010-12-01

Conduction mechanisms in epitaxial (001)-oriented pure and 1 mol % Mn-doped (K0.44,Na0.52,Li0.04)(Nb0.84,Ta0.1,Sb0.06)O3 (KNN-LT-LS) thin films on SrTiO3 substrate were investigated. Temperature dependence of leakage current density was measured as a function of applied electric field in the range of 200-380 K. It was shown that the different transport mechanisms dominate in pure and Mn-doped thin films. In pure (KNN-LT-LS) thin films, Poole-Frenkel emission was found to be responsible for the leakage, while Schottky emission was the dominant mechanism in Mn-doped thin films at higher electric fields. This is a remarkable yet clear indication of effect of 1 mol % Mn on the resistive behavior of such thin films.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure.

Science.gov (United States)

Chen, Szu-Hung; Liao, Wen-Shiang; Yang, Hsin-Chia; Wang, Shea-Jue; Liaw, Yue-Gie; Wang, Hao; Gu, Haoshuang; Wang, Mu-Chun

2012-08-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal-semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

Data leakage quantification

NARCIS (Netherlands)

Vavilis, S.; Petkovic, M.; Zannone, N.; Atluri, V.; Pernul, G.

2014-01-01

The detection and handling of data leakages is becoming a critical issue for organizations. To this end, data leakage solutions are usually employed by organizations to monitor network traffic and the use of portable storage devices. These solutions often produce a large number of alerts, whose

Trapped-ion quantum logic gates based on oscillating magnetic fields.

Science.gov (United States)

Ospelkaus, C; Langer, C E; Amini, J M; Brown, K R; Leibfried, D; Wineland, D J

2008-08-29

Oscillating magnetic fields and field gradients can be used to implement single-qubit rotations and entangling multiqubit quantum gates for trapped-ion quantum information processing (QIP). With fields generated by currents in microfabricated surface-electrode traps, it should be possible to achieve gate speeds that are comparable to those of optically induced gates for realistic distances between the ion crystal and the electrode surface. Magnetic-field-mediated gates have the potential to significantly reduce the overhead in laser-beam control and motional-state initialization compared to current QIP experiments with trapped ions and will eliminate spontaneous scattering, a fundamental source of decoherence in laser-mediated gates.

Poloidal field leakage optimization in ETE

Energy Technology Data Exchange (ETDEWEB)

Shibata, Carlos Shinya; Montes, Antonio

1996-12-01

A very simple but efficient numerical algorithm is used to minimize the Ohmic coil field leakage into the plasma region of the tokamak ETE. After few interactions the code provides the positions and the current required for two pairs of compensation coils. Resulting optimum field intensity distribution is presented and commented. (author). 5 refs., 4 figs., 2 tabs.

Poloidal field leakage optimization in ETE

International Nuclear Information System (INIS)

Shibata, Carlos Shinya; Montes, Antonio.

1996-01-01

A very simple but efficient numerical algorithm is used to minimize the Ohmic coil field leakage into the plasma region of the tokamak ETE. After few interactions the code provides the positions and the current required for two pairs of compensation coils. Resulting optimum field intensity distribution is presented and commented. (author). 5 refs., 4 figs., 2 tabs

Radioactivity leakage monitoring system

International Nuclear Information System (INIS)

Nakajima, Takuichiro; Noguchi, Noboru.

1982-01-01

Purpose: To obtain a device for detecting the leakage ratio of a primary coolant by utilizing the variation in the radioactivity concentration in a reactor container when the coolant is leaked. Constitution: A measurement signal is produced from a radioactivity measuring instrument, and is continuously input to a malfunction discriminator. The discriminator inputs a measurement signal to a concentration variation discriminator when the malfunction is recognized and simultaneously inputs a measurement starting time from the inputting time to a concentration measuring instrument. On the other hand, reactor water radioactivity concentration data obtained by sampling the primary coolant is input to a concentration variation computing device. A comparator obtains the ratio of the measurement signal from the measuring instrument and the computed data signal from the computing device at the same time and hence the leakage rate, indicates the average leakage rate by averaging the leakage rate signals and also indicates the total leakage amount. (Yoshihara, H.)

Direct observation of the leakage current in epitaxial diamond Schottky barrier devices by conductive-probe atomic force microscopy and Raman imaging

OpenAIRE

Alvarez, Jose; Boutchich, M.; Kleider, J. P.; Teraji, T.; Koide, Y.

2014-01-01

The origin of the high leakage current measured in several vertical-type diamond Schottky devices is conjointly investigated by conducting probe atomic force microscopy (CP-AFM) and confocal micro-Raman/Photoluminescence (PL) imaging analysis. Local areas characterized by a strong decrease of the local resistance (5-6 orders of magnitude drop) with respect to their close surrounding have been identified in several different regions of the sample surface. The same local areas, also referenced ...

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors

Science.gov (United States)

Fan, Ching-Lin; Shang, Ming-Chi; Wang, Shea-Jue; Hsia, Mao-Yuan; Lee, Win-Der; Huang, Bohr-Ran

2017-01-01

In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W). PMID:28773101

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol for the Gate Insulator of Pentacene-Based Thin-Film Transistors

Directory of Open Access Journals (Sweden)

Ching-Lin Fan

2017-07-01

Full Text Available In this study, a proposed Microwave-Induction Heating (MIH scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO metal below the Poly(4-vinylphenol (PVP film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min and low-power microwave-irradiation (50 W.

Analytical Subthreshold Current and Subthreshold Swing Models for a Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFET with Back-Gate Control

Science.gov (United States)

Saramekala, Gopi Krishna; Tiwari, Pramod Kumar

2017-08-01

Two-dimensional (2D) analytical models for the subthreshold current and subthreshold swing of the back-gated fully depleted recessed-source/drain (Re-S/D) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) are presented. The surface potential is determined by solving the 2D Poisson equation in both channel and buried-oxide (BOX) regions, considering suitable boundary conditions. To derive closed-form expressions for the subthreshold characteristics, the virtual cathode potential expression has been derived in terms of the minimum of the front and back surface potentials. The effect of various device parameters such as gate oxide and Si film thicknesses, thickness of source/drain penetration into BOX, applied back-gate bias voltage, etc. on the subthreshold current and subthreshold swing has been analyzed. The validity of the proposed models is established using the Silvaco ATLAS™ 2D device simulator.

Prediction of leakage current of non-ceramic insulators in early aging period

Energy Technology Data Exchange (ETDEWEB)

El-Hag, Ayman H. [Electrical Engineering Department, American University of Sharjah, Sharjah (United Arab Emirates); Jahromi, Ali Naderian [Kinectrics Inc., Transmission and Distribution Technologies, Toronto (Canada); Sanaye-Pasand, Majid [Electrical and Computer Engineering Department, University of Tehran (Iran)

2008-10-15

The paper presents a neural network based prediction technique for the leakage current (LC) of non-ceramic insulators during salt-fog test. Nearly 50 distribution class silicone rubber (SIR) insulators with three different voltage classes have been tested in a salt-fog chamber, where the LC has been continuously recorded for at least 100 h. A boundary for early aging period is defined by the rate of change of the LC instead of a fixed threshold value. Consequently, the Gaussian radial basis network has been adopted to predict the level of LC at the early stage of aging of the SIR insulators and is compared with a classical network. The initial values of LC and its rate of change at 10 min intervals for the first 5 h are selected as the input to the network, and the final value of LC of the early aging period is considered as the output of the network. It is found that Gaussian radial basis function network with a random optimizing training method is an appropriate network to predict the LC with a 3.5-5.3% accuracy, if the training data and the testing data are selected from the same type of SIR insulators. (author)

Preventive testing and leakage detection in pipe-lines of steam condensers and generators of a PWR type reactor

International Nuclear Information System (INIS)

Canalini, A.; Carvalho, N.C. de

1985-01-01

The non-destructive methods: Spum, Helium and Hydrostatic used in leakage detection in condenser pipelines for PWR type reactors are presented. The time, costs, sensitivity, resources necessary and personnel development factors are considered to choose adequated method, in function of nuclear power plant conditions. The leakage tests are applied in pressurized systems or vacuum. Eddy Current testing is used in condensers and steam generators aiming to avoid leakage in these equipments. The spume testing for leakage detection in condenser pipelines - which operation - and hydrostatic testing for leakage detection through reaming with shutdown - were most efficients. The Helium testing applied in pressurized systems or submitted to vacuum systems presented satisfactory results. The Eddy Current testing in condenser and steam generator pipelines reached desired objective, reducing leakage in the first and preserving the integrity in the second. (M.C.K.) [pt

Proposal of unilateral single-flux-quantum logic gate

International Nuclear Information System (INIS)

Mikaye, H.; Fukaya, N.; Okabe, Y.; Sugamo, T.

1985-01-01

A new type of single flux quantum logic gate is proposed, which can perform unilateral propagation of signal without using three-phase clock. This gate is designed to be built with bridge-type Josephson junctions. A basic logic gate consists of two one-junction interferometers coupled by superconducting interconnecting lines, and the logical states are represented by zero or one quantized fluxoid in one of one-junction interferometers. The bias current of the unequal magnitude to each of the two one-junction interferometers results in unilateral signal flow. By adjusting design parameters such as the ratio of the critical current of Josephson junctions and the inductances, circuits with the noise immunity of greater than 50% with respect to the bias current have been designed. Three cascaded gates were modeled and simulated on a computer, and the unilateral signal flow was confirmed. The simulation also shows that a switching delay about 2 picoseconds is feasible

Indoor-Outdoor Air Leakage of Apartments and Commercial Buildings

Energy Technology Data Exchange (ETDEWEB)

Price, P.N.; Shehabi, A.; Chan, R.W.; Gadgil, A.J.

2006-06-01

We compiled and analyzed available data concerning indoor-outdoor air leakage rates and building leakiness parameters for commercial buildings and apartments. We analyzed the data, and reviewed the related literature, to determine the current state of knowledge of the statistical distribution of air exchange rates and related parameters for California buildings, and to identify significant gaps in the current knowledge and data. Very few data were found from California buildings, so we compiled data from other states and some other countries. Even when data from other developed countries were included, data were sparse and few conclusive statements were possible. Little systematic variation in building leakage with construction type, building activity type, height, size, or location within the u.s. was observed. Commercial buildings and apartments seem to be about twice as leaky as single-family houses, per unit of building envelope area. Although further work collecting and analyzing leakage data might be useful, we suggest that a more important issue may be the transport of pollutants between units in apartments and mixed-use buildings, an under-studied phenomenon that may expose occupants to high levels of pollutants such as tobacco smoke or dry cleaning fumes.

Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

Science.gov (United States)

Jayanti, Srikant

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG

Electrical characteristics of AlO sub x N sub y prepared by oxidation of sub-10-nm-thick AlN films for MOS gate dielectric applications

CERN Document Server

Jeon, S H; Kim, H S; Noh, D Y; Hwang, H S

2000-01-01

In this research, the feasibility of ultrathin AlO sub x N sub y prepared by oxidation of sub 100-A-thick AlN thin films for metal-oxide-semiconductor (MOS) gate dielectric applications was investigated. Oxidation of 51-A-and 98-A-thick as-deposited AlN at 800 .deg. C was used to form 72-A-and 130-A-thick AlO sub x N sub y , respectively. Based on the capacitance-voltage (C-V) measurements of the MOS capacitor, the dielectric constants of 72 A-thick and 130 A-thick Al-oxynitride were 5.15 and 7, respectively. The leakage current of Al-oxynitride at low field was almost the same as that of thermal SiO sub 2. based on the CV data, the interface state density of Al-oxynitride was relatively higher than that of SiO sub 2. Although process optimization is still necessary, the Al-oxynitride exhibits some possibility for future MOS gate dielectric applications.

Electrical characteristics of AlO{sub x}N{sub y} prepared by oxidation of sub-10-nm-thick AlN films for MOS gate dielectric applications

Energy Technology Data Exchange (ETDEWEB)

Jeon, Sang Hun; Jang, Hyeon Woo; Kim, Hyun Soo; Noh, Do Young; Hwang, Hyun Sang [Kwangju Institute of Science and Technology, Kwangju (Korea, Republic of)

2000-12-01

In this research, the feasibility of ultrathin AlO{sub x}N{sub y} prepared by oxidation of sub 100-A-thick AlN thin films for metal-oxide-semiconductor (MOS) gate dielectric applications was investigated. Oxidation of 51-A-and 98-A-thick as-deposited AlN at 800 .deg. C was used to form 72-A-and 130-A-thick AlO{sub x}N{sub y}, respectively. Based on the capacitance-voltage (C-V) measurements of the MOS capacitor, the dielectric constants of 72 A-thick and 130 A-thick Al-oxynitride were 5.15 and 7, respectively. The leakage current of Al-oxynitride at low field was almost the same as that of thermal SiO{sub 2}. based on the CV data, the interface state density of Al-oxynitride was relatively higher than that of SiO{sub 2}. Although process optimization is still necessary, the Al-oxynitride exhibits some possibility for future MOS gate dielectric applications.

Trapped-ion quantum logic gates based on oscillating magnetic fields

Science.gov (United States)

Ospelkaus, Christian; Langer, Christopher E.; Amini, Jason M.; Brown, Kenton R.; Leibfried, Dietrich; Wineland, David J.

2009-05-01

Oscillating magnetic fields and field gradients can be used to implement single-qubit rotations and entangling multiqubit quantum gates for trapped-ion quantum information processing. With fields generated by currents in microfabricated surface-electrode traps, it should be possible to achieve gate speeds that are comparable to those of optically induced gates for realistic distances between the ions and the electrode surface. Magnetic-field-mediated gates have the potential to significantly reduce the overhead in laser-beam control and motional-state initialization compared to current QIP experiments with trapped ions and will eliminate spontaneous scattering decoherence, a fundamental source of decoherence in laser-mediated gates. A potentially beneficial environment for the implementation of such schemes is a cryogenic ion trap, because small length scale traps with low motional heating rates can be realized. A cryogenic ion trap experiment is currently under construction at NIST.

Toward spin-based Magneto Logic Gate in Graphene

Science.gov (United States)

Wen, Hua; Dery, Hanan; Amamou, Walid; Zhu, Tiancong; Lin, Zhisheng; Shi, Jing; Zutic, Igor; Krivorotov, Ilya; Sham, Lu; Kawakami, Roland

Graphene has emerged as a leading candidate for spintronic applications due to its long spin diffusion length at room temperature. A universal magnetologic gate (MLG) based on spin transport in graphene has been recently proposed as the building block of a logic circuit which could replace the current CMOS technology. This MLG has five ferromagnetic electrodes contacting a graphene channel and can be considered as two three-terminal XOR logic gates. Here we demonstrate this XOR logic gate operation in such a device. This was achieved by systematically tuning the injection current bias to balance the spin polarization efficiency of the two inputs, and offset voltage in the detection circuit to obtain binary outputs. The output is a current which corresponds to different logic states: zero current is logic `0', and nonzero current is logic `1'. We find improved performance could be achieved by reducing device size and optimizing the contacts.

Systematic review of methods to predict and detect anastomotic leakage in colorectal surgery.

Science.gov (United States)

Hirst, N A; Tiernan, J P; Millner, P A; Jayne, D G

2014-02-01

Anastomotic leakage is a serious complication of gastrointestinal surgery resulting in increased morbidity and mortality, poor function and predisposing to cancer recurrence. Earlier diagnosis and intervention can minimize systemic complications but is hindered by current diagnostic methods that are non-specific and often uninformative. The purpose of this paper is to review current developments in the field and to identify strategies for early detection and treatment of anastomotic leakage. A systematic literature search was performed using the MEDLINE, Embase, PubMed and Cochrane Library databases. Search terms included 'anastomosis' and 'leak' and 'diagnosis' or 'detection' and 'gastrointestinal' or 'colorectal'. Papers concentrating on the diagnosis of gastrointestinal anastomotic leak were identified and further searches were performed by cross-referencing. Computerized tomography CT scanning and water-soluble contrast studies are the current preferred techniques for diagnosing anastomotic leakage but suffer from variable sensitivity and specificity, have logistical constraints and may delay timely intervention. Intra-operative endoscopy and imaging may offer certain advantages, but the ability to predict anastomotic leakage is unproven. Newer techniques involve measurement of biomarkers for anastomotic leakage and have the potential advantage of providing cheap real-time monitoring for postoperative complications. Current diagnostic tests often fail to diagnose anastomotic leak at an early stage that enables timely intervention and minimizes serious morbidity and mortality. Emerging technologies, based on detection of local biomarkers, have achieved proof of concept status but require further evaluation to determine whether they translate into improved patient outcomes. Further research is needed to address this important, yet relatively unrecognized, area of unmet clinical need. Colorectal Disease © 2013 The Association of Coloproctology of Great Britain

Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance

Science.gov (United States)

Anand, Sunny; Sarin, R. K.

2017-02-01

In this paper, charge-plasma-based tunnel FET is proposed by employing dual material gate with hetero gate dielectric technique and it is named hetero-dielectric dual material gate doping-less TFET (HD_DMG_DLTFET). It is compared with conventional doping-less TFET (DLTFET) and dual material gate doping-less TFET (DMG_DLTFET) on the basis of analog and RF performance. The HD_DMG_DLTFET provides better ON state current ({I}\\text{ON}=94 μ \\text{A}/μ \\text{m}), {I}\\text{ON}/{I}\\text{OFF}(≈ 1.36× {10}13), \\text{point} (≈ 3\\text{mV}/\\text{dec}) and average subthreshold slope (\\text{AV}-\\text{SS}=40.40 \\text{mV}/\\text{dec}). The proposed device offers low total gate capacitance (C gg) along with higher drive current. However, with a better transconductance (g m) and cut-off frequency (f T), the HD_DMG_DLTFET can be a good candidate for RF circuitry. The early voltage (V EA) and output conductance (g d) are also moderate for the proposed device with comparison to other devices and therefore can be a candidate for analog devices. From all these simulation results and their study, it is observed that HD_DMG_DLTFET has improved analog/RF performance compared to DLTFET and DMG_DLTFET.

A comparative study of amorphous InGaZnO thin-film transistors with HfOxNy and HfO2 gate dielectrics

International Nuclear Information System (INIS)

Zou, Xiao; Tong, Xingsheng; Fang, Guojia; Yuan, Longyan; Zhao, Xingzhong

2010-01-01

High-κ HfO x N y and HfO 2 films are applied to amorphous InGaZnO (a-IGZO) devices as gate dielectric using radio-frequency reactive sputtering. The electrical characteristics and reliability of a-IGZO metal–insulator–semiconductor (MIS) capacitors and thin-film transistors (TFTs) are then investigated. Experimental results indicate that the nitrogen incorporation into HfO 2 can effectively improve the interface quality and enhance the reliability of the devices. Electrical properties with an interface-state density of 5.2 × 10 11 eV −1 cm −2 , capacitance equivalent thickness of 1.65 nm, gate leakage current density of 3.4 × 10 −5 A cm −2 at V fb +1 V, equivalent permittivity of 23.6 and hysteresis voltage of 110 mV are obtained for an Al/HfO x N y /a-IGZO MIS capacitor. Superior performance of HfO x N y /a-IGZO TFTs has also been achieved with a low threshold voltage of 0.33 V, a high saturation mobility of 12.1 cm 2 V −1 s −1 and a large on–off current ratio up to 7 × 10 7 (W/L = 500/20 µm) at 3 V

High-Fidelity Single-Shot Toffoli Gate via Quantum Control.

Science.gov (United States)

Zahedinejad, Ehsan; Ghosh, Joydip; Sanders, Barry C

2015-05-22

A single-shot Toffoli, or controlled-controlled-not, gate is desirable for classical and quantum information processing. The Toffoli gate alone is universal for reversible computing and, accompanied by the Hadamard gate, forms a universal gate set for quantum computing. The Toffoli gate is also a key ingredient for (nontopological) quantum error correction. Currently Toffoli gates are achieved by decomposing into sequentially implemented single- and two-qubit gates, which require much longer times and yields lower overall fidelities compared to a single-shot implementation. We develop a quantum-control procedure to construct a single-shot Toffoli gate for three nearest-neighbor-coupled superconducting transmon systems such that the fidelity is 99.9% and is as fast as an entangling two-qubit gate under the same realistic conditions. The gate is achieved by a nongreedy quantum control procedure using our enhanced version of the differential evolution algorithm.

Sulfuric acid and hydrogen peroxide surface passivation effects on AlGaN/GaN high electron mobility transistors

Energy Technology Data Exchange (ETDEWEB)

Zaidi, Z. H., E-mail: zaffar.zaidi@sheffield.ac.uk; Lee, K. B.; Qian, H.; Jiang, S.; Houston, P. A. [Department of Electronic and Electrical Engineering, The University of Sheffield, Mappin Street, Sheffield S1 3JD (United Kingdom); Guiney, I.; Wallis, D. J.; Humphreys, C. J. [Department of Materials Science and Metallurgy, The University of Cambridge, 27 Charles Babbage Road, Cambridge CB3 0FS (United Kingdom)

2014-12-28

In this work, we have compared SiN{sub x} passivation, hydrogen peroxide, and sulfuric acid treatment on AlGaN/GaN HEMTs surface after full device fabrication on Si substrate. Both the chemical treatments resulted in the suppression of device pinch-off gate leakage current below 1 μA/mm, which is much lower than that for SiN{sub x} passivation. The greatest suppression over the range of devices is observed with the sulfuric acid treatment. The device on/off current ratio is improved (from 10{sup 4}–10{sup 5} to 10{sup 7}) and a reduction in the device sub-threshold (S.S.) slope (from ∼215 to 90 mV/decade) is achieved. The sulfuric acid is believed to work by oxidizing the surface which has a strong passivating effect on the gate leakage current. The interface trap charge density (D{sub it}) is reduced (from 4.86 to 0.90 × 10{sup 12 }cm{sup −2} eV{sup −1}), calculated from the change in the device S.S. The gate surface leakage current mechanism is explained by combined Mott hopping conduction and Poole Frenkel models for both untreated and sulfuric acid treated devices. Combining the sulfuric acid treatment underneath the gate with the SiN{sub x} passivation after full device fabrication results in the reduction of D{sub it} and improves the surface related current collapse.

Sulfuric acid and hydrogen peroxide surface passivation effects on AlGaN/GaN high electron mobility transistors

International Nuclear Information System (INIS)

Zaidi, Z. H.; Lee, K. B.; Qian, H.; Jiang, S.; Houston, P. A.; Guiney, I.; Wallis, D. J.; Humphreys, C. J.

2014-01-01

In this work, we have compared SiN x passivation, hydrogen peroxide, and sulfuric acid treatment on AlGaN/GaN HEMTs surface after full device fabrication on Si substrate. Both the chemical treatments resulted in the suppression of device pinch-off gate leakage current below 1 μA/mm, which is much lower than that for SiN x passivation. The greatest suppression over the range of devices is observed with the sulfuric acid treatment. The device on/off current ratio is improved (from 10 4 –10 5 to 10 7 ) and a reduction in the device sub-threshold (S.S.) slope (from ∼215 to 90 mV/decade) is achieved. The sulfuric acid is believed to work by oxidizing the surface which has a strong passivating effect on the gate leakage current. The interface trap charge density (D it ) is reduced (from 4.86 to 0.90 × 10 12  cm −2 eV −1 ), calculated from the change in the device S.S. The gate surface leakage current mechanism is explained by combined Mott hopping conduction and Poole Frenkel models for both untreated and sulfuric acid treated devices. Combining the sulfuric acid treatment underneath the gate with the SiN x passivation after full device fabrication results in the reduction of D it and improves the surface related current collapse

Impact of the Indonesian Throughflow on Agulhas leakage

Directory of Open Access Journals (Sweden)

D. Le Bars

2013-09-01

Full Text Available Using ocean models of different complexity we show that opening the Indonesian Passage between the Pacific and the Indian oceans increases the input of Indian Ocean water into the South Atlantic via the Agulhas leakage. In a strongly eddying global ocean model this response results from an increased Agulhas Current transport and a constant proportion of Agulhas retroflection south of Africa. The leakage increases through an increased frequency of ring shedding events. In an idealized two-layer and flat-bottom eddy resolving model, the proportion of the Agulhas Current transport that retroflects is (for a wide range of wind stress forcing not affected by an opening of the Indonesian Passage. Using a comparison with a linear model and previous work on the retroflection problem, the result is explained as a balance between two mechanisms: decrease retroflection due to large-scale momentum balance and increase due to local barotropic/baroclinic instabilities.

Electron transport in a double quantum ring: Evidence of an AND gate

International Nuclear Information System (INIS)

Maiti, Santanu K.

2009-01-01

We explore AND gate response in a double quantum ring where each ring is threaded by a magnetic flux φ. The double quantum ring is attached symmetrically to two semi-infinite one-dimensional metallic electrodes and two gate voltages, namely, V a and V b , are applied, respectively, in the lower arms of the two rings which are treated as two inputs of the AND gate. The system is described in the tight-binding framework and the calculations are done using the Green's function formalism. Here we numerically compute the conductance-energy and current-voltage characteristics as functions of the ring-to-electrode coupling strengths, magnetic flux and gate voltages. Our study suggests that, for a typical value of the magnetic flux φ=φ 0 /2 (φ 0 =ch/e, the elementary flux-quantum) a high output current (1) (in the logical sense) appears only if both the two inputs to the gate are high (1), while if neither or only one input to the gate is high (1), a low output current (0) results. It clearly demonstrates the AND gate behavior and this aspect may be utilized in designing an electronic logic gate.