Stable Low-Voltage Operation Top-Gate Organic Field-Effect Transistors on Cellulose Nanocrystal Substrates

Science.gov (United States)

Cheng-Yin Wang; Canek Fuentes-Hernandez; Jen-Chieh Liu; Amir Dindar; Sangmoo Choi; Jeffrey P. Youngblood; Robert J. Moon; Bernard Kippelen

2015-01-01

We report on the performance and the characterization of top-gate organic field-effect transistors (OFETs), comprising a bilayer gate dielectric of CYTOP/ Al2O3 and a solution-processed semiconductor layer made of a blend of TIPS-pentacene:PTAA, fabricated on recyclable cellulose nanocrystal−glycerol (CNC/glycerol...

Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor

Science.gov (United States)

Madan, Jaya; Gupta, R. S.; Chaujar, Rishu

2015-09-01

In this work, an analytical drain current model for gate dielectric engineered (hetero dielectric)-dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed. Parabolic approximation has been used to solve the two-dimensional (2D) Poisson equation with appropriate boundary conditions and continuity equations to evaluate analytical expressions for surface potential, electric field, tunneling barrier width and drain current. Further, the analog performance of the device is studied for three high-k dielectrics (Si3N4, HfO2, and ZrO2), and it has been investigated that the problem of lower ION, can be overcome by using the hetero-gate architecture. Moreover, the impact of scaling the gate oxide thickness and bias variations has also been studied. The HD-DMG-GAA-TFET shows an enhanced ION of the order of 10-4 A. The effectiveness of the proposed model is validated by comparing it with ATLAS device simulations.

Fabrication and electrical properties of MoS2 nanodisc-based back-gated field effect transistors.

Science.gov (United States)

Gu, Weixia; Shen, Jiaoyan; Ma, Xiying

2014-02-28

Two-dimensional (2D) molybdenum disulfide (MoS2) is an attractive alternative semiconductor material for next-generation low-power nanoelectronic applications, due to its special structure and large bandgap. Here, we report the fabrication of large-area MoS2 nanodiscs and their incorporation into back-gated field effect transistors (FETs) whose electrical properties we characterize. The MoS2 nanodiscs, fabricated via chemical vapor deposition (CVD), are homogeneous and continuous, and their thickness of around 5 nm is equal to a few layers of MoS2. In addition, we find that the MoS2 nanodisc-based back-gated field effect transistors with nickel electrodes achieve very high performance. The transistors exhibit an on/off current ratio of up to 1.9 × 105, and a maximum transconductance of up to 27 μS (5.4 μS/μm). Moreover, their mobility is as high as 368 cm2/Vs. Furthermore, the transistors have good output characteristics and can be easily modulated by the back gate. The electrical properties of the MoS2 nanodisc transistors are better than or comparable to those values extracted from single and multilayer MoS2 FETs.

Functionalization and microfluidic integration of silicon nanowire biologically gated field effect transistors

DEFF Research Database (Denmark)

Pfreundt, Andrea

This thesis deals with the development of a novel biosensor for the detection of biomolecules based on a silicon nanowire biologically gated field-effect transistor and its integration into a point-of-care device. The sensor and electrical on-chip integration was developed in a different project...

Functionalization and microfluidic integration of silicon nanowire biologically gated field effect transistors

DEFF Research Database (Denmark)

Pfreundt, Andrea; Svendsen, Winnie Edith; Dimaki, Maria

2016-01-01

This thesis deals with the development of a novel biosensor for the detection of biomolecules based on a silicon nanowire biologically gated field-effect transistor and its integration into a point-of-care device. The sensor and electrical on-chip integration was developed in a different project...

The Bipolar Field-Effect Transistor: XIII. Physical Realizations of the Transistor and Circuits (One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)

International Nuclear Information System (INIS)

Sah, C.-T.; Jie Binbin

2009-01-01

This paper reports the physical realization of the Bipolar Field-Effect Transistor (BiFET) and its one-transistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These examples include the one-MOS-gate on semi-infinite thick impure base transistor (the bulk transistor) and the impurethin-base Silicon-on-Insulator (SOI) transistor and the two-MOS-gates on thin base transistors (the FinFET and the Thin Film Transistor TFT). Figures are given with the cross-section views containing the electron and hole concentration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.

Gate Tunable Transport in Graphene/MoS₂/(Cr/Au) Vertical Field-Effect Transistors.

Science.gov (United States)

Nazir, Ghazanfar; Khan, Muhammad Farooq; Aftab, Sikandar; Afzal, Amir Muhammad; Dastgeer, Ghulam; Rehman, Malik Abdul; Seo, Yongho; Eom, Jonghwa

2017-12-28

Two-dimensional materials based vertical field-effect transistors have been widely studied due to their useful applications in industry. In the present study, we fabricate graphene/MoS₂/(Cr/Au) vertical transistor based on the mechanical exfoliation and dry transfer method. Since the bottom electrode was made of monolayer graphene (Gr), the electrical transport in our Gr/MoS₂/(Cr/Au) vertical transistors can be significantly modified by using back-gate voltage. Schottky barrier height at the interface between Gr and MoS₂ can be modified by back-gate voltage and the current bias. Vertical resistance (R vert ) of a Gr/MoS₂/(Cr/Au) transistor is compared with planar resistance (R planar ) of a conventional lateral MoS₂ field-effect transistor. We have also studied electrical properties for various thicknesses of MoS₂ channels in both vertical and lateral transistors. As the thickness of MoS₂ increases, R vert increases, but R planar decreases. The increase of R vert in the thicker MoS₂ film is attributed to the interlayer resistance in the vertical direction. However, R planar shows a lower value for a thicker MoS₂ film because of an excess of charge carriers available in upper layers connected directly to source/drain contacts that limits the conduction through layers closed to source/drain electrodes. Hence, interlayer resistance associated with these layers contributes to planer resistance in contrast to vertical devices in which all layers contribute interlayer resistance.

Tunnel field-effect transistor with two gated intrinsic regions

Directory of Open Access Journals (Sweden)

Y. Zhang

2014-07-01

Full Text Available In this paper, we propose and validate (using simulations a novel design of silicon tunnel field-effect transistor (TFET, based on a reverse-biased p+-p-n-n+ structure. 2D device simulation results show that our devices have significant improvements of switching performance compared with more conventional devices based on p-i-n structure. With independent gate voltages applied to two gated intrinsic regions, band-to-band tunneling (BTBT could take place at the p-n junction, and no abrupt degenerate doping profile is required. We developed single-side-gate (SSG structure and double-side-gate (DSG structure. SSG devices with HfO2 gate dielectric have a point subthreshold swing of 9.58 mV/decade, while DSG devices with polysilicon gate electrode material and HfO2 gate dielectric have a point subthreshold swing of 16.39 mV/decade. These DSG devices have ON-current of 0.255 μA/μm, while that is lower for SSG devices. Having two nano-scale independent gates will be quite challenging to realize with good uniformity across the wafer and the improved behavior of our TFET makes it a promising steep-slope switch candidate for further investigations.

Phosphorus oxide gate dielectric for black phosphorus field effect transistors

Science.gov (United States)

Dickerson, W.; Tayari, V.; Fakih, I.; Korinek, A.; Caporali, M.; Serrano-Ruiz, M.; Peruzzini, M.; Heun, S.; Botton, G. A.; Szkopek, T.

2018-04-01

The environmental stability of the layered semiconductor black phosphorus (bP) remains a challenge. Passivation of the bP surface with phosphorus oxide, POx, grown by a reactive ion etch with oxygen plasma is known to improve photoluminescence efficiency of exfoliated bP flakes. We apply phosphorus oxide passivation in the fabrication of bP field effect transistors using a gate stack consisting of a POx layer grown by reactive ion etching followed by atomic layer deposition of Al2O3. We observe room temperature top-gate mobilities of 115 cm2 V-1 s-1 in ambient conditions, which we attribute to the low defect density of the bP/POx interface.

Gate Tunable Transport in Graphene/MoS2/(Cr/Au Vertical Field-Effect Transistors

Directory of Open Access Journals (Sweden)

Ghazanfar Nazir

2017-12-01

Full Text Available Two-dimensional materials based vertical field-effect transistors have been widely studied due to their useful applications in industry. In the present study, we fabricate graphene/MoS2/(Cr/Au vertical transistor based on the mechanical exfoliation and dry transfer method. Since the bottom electrode was made of monolayer graphene (Gr, the electrical transport in our Gr/MoS2/(Cr/Au vertical transistors can be significantly modified by using back-gate voltage. Schottky barrier height at the interface between Gr and MoS2 can be modified by back-gate voltage and the current bias. Vertical resistance (Rvert of a Gr/MoS2/(Cr/Au transistor is compared with planar resistance (Rplanar of a conventional lateral MoS2 field-effect transistor. We have also studied electrical properties for various thicknesses of MoS2 channels in both vertical and lateral transistors. As the thickness of MoS2 increases, Rvert increases, but Rplanar decreases. The increase of Rvert in the thicker MoS2 film is attributed to the interlayer resistance in the vertical direction. However, Rplanar shows a lower value for a thicker MoS2 film because of an excess of charge carriers available in upper layers connected directly to source/drain contacts that limits the conduction through layers closed to source/drain electrodes. Hence, interlayer resistance associated with these layers contributes to planer resistance in contrast to vertical devices in which all layers contribute interlayer resistance.

Extended Gate Field-Effect Transistor Biosensors for Point-Of-Care Testing of Uric Acid.

Science.gov (United States)

Guan, Weihua; Reed, Mark A

2017-01-01

An enzyme-free redox potential sensor using off-chip extended-gate field effect transistor (EGFET) with a ferrocenyl-alkanethiol modified gold electrode has been used to quantify uric acid concentration in human serum and urine. Hexacyanoferrate (II) and (III) ions are used as redox reagent. The potentiometric sensor measures the interface potential on the ferrocene immobilized gold electrode, which is modulated by the redox reaction between uric acid and hexacyanoferrate ions. The device shows a near Nernstian response to uric acid and is highly specific to uric acid in human serum and urine. The interference that comes from glucose, bilirubin, ascorbic acid, and hemoglobin is negligible in the normal concentration range of these interferents. The sensor also exhibits excellent long term reliability and is regenerative. This extended gate field effect transistor based sensor is promising for point-of-care detection of uric acid due to the small size, low cost, and low sample volume consumption.

Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

International Nuclear Information System (INIS)

Besleaga, C.; Stan, G.E.; Pintilie, I.; Barquinha, P.; Fortunato, E.; Martins, R.

2016-01-01

Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

Energy Technology Data Exchange (ETDEWEB)

Besleaga, C.; Stan, G.E.; Pintilie, I. [National Institute of Materials Physics, 405A Atomistilor, 077125 Magurele-Ilfov (Romania); Barquinha, P.; Fortunato, E. [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal); Martins, R., E-mail: rm@uninova.pt [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal)

2016-08-30

Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

Ferroelectric field-effect transistors based on solution-processed electrochemically exfoliated graphene

Science.gov (United States)

Heidler, Jonas; Yang, Sheng; Feng, Xinliang; Müllen, Klaus; Asadi, Kamal

2018-06-01

Memories based on graphene that could be mass produced using low-cost methods have not yet received much attention. Here we demonstrate graphene ferroelectric (dual-gate) field effect transistors. The graphene has been obtained using electrochemical exfoliation of graphite. Field-effect transistors are realized using a monolayer of graphene flakes deposited by the Langmuir-Blodgett protocol. Ferroelectric field effect transistor memories are realized using a random ferroelectric copolymer poly(vinylidenefluoride-co-trifluoroethylene) in a top gated geometry. The memory transistors reveal ambipolar behaviour with both electron and hole accumulation channels. We show that the non-ferroelectric bottom gate can be advantageously used to tune the on/off ratio.

Universal core model for multiple-gate field-effect transistors with short channel and quantum mechanical effects

Science.gov (United States)

Shin, Yong Hyeon; Bae, Min Soo; Park, Chuntaek; Park, Joung Won; Park, Hyunwoo; Lee, Yong Ju; Yun, Ilgu

2018-06-01

A universal core model for multiple-gate (MG) field-effect transistors (FETs) with short channel effects (SCEs) and quantum mechanical effects (QMEs) is proposed. By using a Young’s approximation based solution for one-dimensional Poisson’s equations the total inversion charge density (Q inv ) in the channel is modeled for double-gate (DG) and surrounding-gate SG (SG) FETs, following which a universal charge model is derived based on the similarity of the solutions, including for quadruple-gate (QG) FETs. For triple-gate (TG) FETs, the average of DG and QG FETs are used. A SCEs model is also proposed considering the potential difference between the channel’s surface and center. Finally, a QMEs model for MG FETs is developed using the quantum correction compact model. The proposed universal core model is validated on commercially available three-dimensional ATLAS numerical simulations.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

Science.gov (United States)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-01

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

Science.gov (United States)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-17

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Continuous adjustment of threshold voltage in carbon nanotube field-effect transistors through gate engineering

Science.gov (United States)

Zhong, Donglai; Zhao, Chenyi; Liu, Lijun; Zhang, Zhiyong; Peng, Lian-Mao

2018-04-01

In this letter, we report a gate engineering method to adjust threshold voltage of carbon nanotube (CNT) based field-effect transistors (FETs) continuously in a wide range, which makes the application of CNT FETs especially in digital integrated circuits (ICs) easier. Top-gated FETs are fabricated using solution-processed CNT network films with stacking Pd and Sc films as gate electrodes. By decreasing the thickness of the lower layer metal (Pd) from 20 nm to zero, the effective work function of the gate decreases, thus tuning the threshold voltage (Vt) of CNT FETs from -1.0 V to 0.2 V. The continuous adjustment of threshold voltage through gate engineering lays a solid foundation for multi-threshold technology in CNT based ICs, which then can simultaneously provide high performance and low power circuit modules on one chip.

Extended-gate organic field-effect transistor for the detection of histamine in water

Science.gov (United States)

Minamiki, Tsukuru; Minami, Tsuyoshi; Yokoyama, Daisuke; Fukuda, Kenjiro; Kumaki, Daisuke; Tokito, Shizuo

2015-04-01

As part of our ongoing research program to develop health care sensors based on organic field-effect transistor (OFET) devices, we have attempted to detect histamine using an extended-gate OFET. Histamine is found in spoiled or decayed fish, and causes foodborne illness known as scombroid food poisoning. The new OFET device possesses an extended gate functionalized by carboxyalkanethiol that can interact with histamine. As a result, we have succeeded in detecting histamine in water through a shift in OFET threshold voltage. This result indicates the potential utility of the designed OFET devices in food freshness sensing.

A novel Tunneling Graphene Nano Ribbon Field Effect Transistor with dual material gate: Numerical studies

Science.gov (United States)

Ghoreishi, Seyed Saleh; Saghafi, Kamyar; Yousefi, Reza; Moravvej-farshi, Mohammad Kazem

2016-09-01

In this work, we present Dual Material Gate Tunneling Graphene Nano-Ribbon Field Effect Transistors (DMG-T-GNRFET) mainly to suppress the am-bipolar current with assumption that sub-threshold swing which is one of the important characteristics of tunneling transistors must not be degraded. In the proposed structure, dual material gates with different work functions are used. Our investigations are based on numerical simulations which self-consistently solves the 2D Poisson based on an atomistic mode-space approach and Schrodinger equations, within the Non-Equilibrium Green's (NEGF). The proposed device shows lower off-current and on-off ratio becomes 5order of magnitude greater than the conventional device. Also two different short channel effects: Drain Induced Barrier Shortening (DIBS) and hot-electron effect are improved in the proposed device compare to the main structure.

Pulsed laser deposition of oxide gate dielectrics for pentacene organic field-effect transistors

International Nuclear Information System (INIS)

Yaginuma, S.; Yamaguchi, J.; Itaka, K.; Koinuma, H.

2005-01-01

We have fabricated Al 2 O 3 , LaAlO 3 (LAO), CaHfO 3 (CHO) and CaZrO 3 (CZO) thin films for the dielectric layers of field-effect transistors (FETs) by pulsed laser deposition (PLD). The films exhibited very smooth surfaces with root-mean-squares (rms) roughnesses of ∼1.3 A as evaluated by using atomic force microscopy (AFM). The breakdown electric fields of Al 2 O 3 , LAO, CHO and CZO films were 7, 6, 10 and 2 MV/cm, respectively. The magnitude of the leak current in each film was low enough to operate FET. We performed a comparative study of pentacene FET fabricated using these oxide dielectrics as gate insulators. High field-effect mobility of 1.4 cm 2 /V s and on/off current ratio of 10 7 were obtained in the pentacene FET using LAO gate insulating film. Use of the LAO films as gate dielectrics has been found to suppress the hysteresis of pentacene FET operations. The LAO films are relevant to the dielectric layer of organic FETs

Graphene-graphite oxide field-effect transistors.

Science.gov (United States)

Standley, Brian; Mendez, Anthony; Schmidgall, Emma; Bockrath, Marc

2012-03-14

Graphene's high mobility and two-dimensional nature make it an attractive material for field-effect transistors. Previous efforts in this area have used bulk gate dielectric materials such as SiO(2) or HfO(2). In contrast, we have studied the use of an ultrathin layered material, graphene's insulating analogue, graphite oxide. We have fabricated transistors comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. The graphite oxide layers show relatively minimal leakage at room temperature. The breakdown electric field of graphite oxide was found to be comparable to SiO(2), typically ~1-3 × 10(8) V/m, while its dielectric constant is slightly higher, κ ≈ 4.3. © 2012 American Chemical Society

Organic tunnel field effect transistors

KAUST Repository

Tietze, Max Lutz; Lussem, Bjorn; Liu, Shiyi

2017-01-01

Various examples are provided for organic tunnel field effect transistors (OTFET), and methods thereof. In one example, an OTFET includes a first intrinsic layer (i-layer) of organic semiconductor material disposed over a gate insulating layer

High mobility polymer gated organic field effect transistor using zinc ...

Indian Academy of Sciences (India)

Organic thin film transistors were fabricated using evaporated zinc phthalocyanine as the active layer. Parylene film ... At room temperature, these transistors exhibit p-type conductivity with field-effect ... Keywords. Organic semiconductor; field effect transistor; phthalocyanine; high mobility. ... The evaporation rate was kept at ...

MIS field effect transistor with barium titanate thin film as a gate insulator

Energy Technology Data Exchange (ETDEWEB)

Firek, P., E-mail: pfirek@elka.pw.edu.p [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland); Werbowy, A.; Szmidt, J. [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland)

2009-11-25

The properties of barium titanate (BaTiO{sub 3}, BT) like, e.g. high dielectric constant and resistivity, allow it to find numerous applications in field of microelectronics. In this work silicon metal insulator semiconductor field effect transistor (MISFET) structures with BaTiO{sub 3} (containing La{sub 2}O{sub 3} admixture) thin films in a role of gate insulator were investigated. The films were produced by means of radio frequency plasma sputtering (RF PS) of sintered BaTiO{sub 3} + La{sub 2}O{sub 3} (2 wt.%) target. In the paper transfer and output current-voltage (I-V), transconductance and output conductance characteristics of obtained transistors are presented and discussed. Basic parameters of these devices like, e.g. threshold voltage (V{sub TH}), are determined and discussed.

Plasma Deposited SiO2 for Planar Self-Aligned Gate Metal-Insulator-Semiconductor Field Effect Transistors on Semi-Insulating InP

Science.gov (United States)

Tabory, Charles N.; Young, Paul G.; Smith, Edwyn D.; Alterovitz, Samuel A.

1994-01-01

Metal-insulator-semiconductor (MIS) field effect transistors were fabricated on InP substrates using a planar self-aligned gate process. A 700-1000 A gate insulator of Si02 doped with phosphorus was deposited by a direct plasma enhanced chemical vapor deposition at 400 mTorr, 275 C, 5 W, and power density of 8.5 MW/sq cm. High frequency capacitance-voltage measurements were taken on MIS capacitors which have been subjected to a 700 C anneal and an interface state density of lxl0(exp 11)/eV/cq cm was found. Current-voltage measurements of the capacitors show a breakdown voltage of 107 V/cm and a insulator resistivity of 10(exp 14) omega cm. Transistors were fabricated on semi-insulating InP using a standard planar self-aligned gate process in which the gate insulator was subjected to an ion implantation activation anneal of 700 C. MIS field effect transistors gave a maximum extrinsic transconductance of 23 mS/mm for a gate length of 3 microns. The drain current drift saturated at 87.5% of the initial current, while reaching to within 1% of the saturated value after only 1x10(exp 3). This is the first reported viable planar InP self-aligned gate transistor process reported to date.

The memory effect of a pentacene field-effect transistor with a polarizable gate dielectric

Science.gov (United States)

Unni, K. N. N.; de Bettignies, Remi; Dabos-Seignon, Sylvie; Nunzi, Jean-Michel

2004-06-01

The nonvolatile transistor memory element is an interesting topic in organic electronics. In this case a memory cell consists of only one device where the stored information is written as a gate insulator polarization by a gate voltage pulse and read by the channel conductance control with channel voltage pulse without destruction of the stored information. Therefore such transistor could be the base of non-volatile non-destructively readable computer memory of extremely high density. Also devices with polarizable gate dielectrics can function more effectively in certain circuits. The effective threshold voltage Vt can be brought very close to zero, for applications where the available gate voltage is limited. Resonant and adaptive circuits can be tuned insitu by polarizing the gates. Poly(vinylidene fluoride), PVDF and its copolymer with trifluoroethylene P(VDF-TrFE) are among the best known and most widely used ferroelectric polymers. In this manuscript, we report new results of an organic FET, fabricated with pentacene as the active material and P(VDF-TrFE) as the gate insulator. Application of a writing voltage of -50 V for short duration results in significant change in the threshold voltage and remarkable increase in the drain current. The memory effect is retained over a period of 20 hours.

Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

KAUST Repository

Fahad, Hossain M.; Smith, Casey; Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

2011-01-01

We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

KAUST Repository

Fahad, Hossain M.

2011-10-12

We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around

Science.gov (United States)

Guerfi, Youssouf; Larrieu, Guilhem

2016-04-01

Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires' suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-scale process of GAA vertical silicon nanowire (VNW) MOSFETs is presented. A top-down approach is adopted for the realization of VNWs with an optimum reproducibility followed by thin layer engineering at nanoscale. Good overall electrical performances were obtained, with excellent electrostatic behavior (a subthreshold slope (SS) of 95 mV/dec and a drain induced barrier lowering (DIBL) of 25 mV/V) for a 15-nm gate length. Finally, a first demonstration of dual integration of n-type and p-type VNW transistors for the realization of CMOS inverter is proposed.

Proton migration mechanism for the instability of organic field-effect transistors

NARCIS (Netherlands)

Sharma, A.; Mathijssen, S.G.J.; Kemerink, M.; Leeuw, de D.M.; Bobbert, P.A.

2009-01-01

During prolonged application of a gate bias, organic field-effect transistors show an instability involving a gradual shift of the threshold voltage toward the applied gate bias voltage. We propose a model for this instability in p-type transistors with a silicon-dioxide gate dielectric, based on

Chemo-Electrical Signal Transduction by Using Stimuli-Responsive Polymer Gate-Modified Field Effect Transistor

Directory of Open Access Journals (Sweden)

Akira Matsumoto

2014-03-01

Full Text Available A glucose-responsive polymer brush was designed on a gold electrode and exploited as an extended gate for a field effect transistor (FET based biosensor. A permittivity change at the gate interface due to the change in hydration upon specific binding with glucose was detectable. The rate of response was markedly enhanced compared to the previously studied cross-linked or gel-coupled electrode, owing to its kinetics involving no process of the polymer network diffusion. This finding may offer a new strategy of the FET-based biosensors effective not only for large molecules but also for electrically neutral molecules such as glucose with improved kinetics.

Ultrashort Channel Length Black Phosphorus Field-Effect Transistors.

Science.gov (United States)

Miao, Jinshui; Zhang, Suoming; Cai, Le; Scherr, Martin; Wang, Chuan

2015-09-22

This paper reports high-performance top-gated black phosphorus (BP) field-effect transistors with channel lengths down to 20 nm fabricated using a facile angle evaporation process. By controlling the evaporation angle, the channel length of the transistors can be reproducibly controlled to be anywhere between 20 and 70 nm. The as-fabricated 20 nm top-gated BP transistors exhibit respectable on-state current (174 μA/μm) and transconductance (70 μS/μm) at a VDS of 0.1 V. Due to the use of two-dimensional BP as the channel material, the transistors exhibit relatively small short channel effects, preserving a decent on-off current ratio of 10(2) even at an extremely small channel length of 20 nm. Additionally, unlike the unencapsulated BP devices, which are known to be chemically unstable in ambient conditions, the top-gated BP transistors passivated by the Al2O3 gate dielectric layer remain stable without noticeable degradation in device performance after being stored in ambient conditions for more than 1 week. This work demonstrates the great promise of atomically thin BP for applications in ultimately scaled transistors.

Touch sensors based on planar liquid crystal-gated-organic field-effect transistors

International Nuclear Information System (INIS)

Seo, Jooyeok; Lee, Chulyeon; Han, Hyemi; Lee, Sooyong; Nam, Sungho; Kim, Youngkyoo; Kim, Hwajeong; Lee, Joon-Hyung; Park, Soo-Young; Kang, Inn-Kyu

2014-01-01

We report a tactile touch sensor based on a planar liquid crystal-gated-organic field-effect transistor (LC-g-OFET) structure. The LC-g-OFET touch sensors were fabricated by forming the 10 μm thick LC layer (4-cyano-4 ′ -pentylbiphenyl - 5CB) on top of the 50 nm thick channel layer (poly(3-hexylthiophene) - P3HT) that is coated on the in-plane aligned drain/source/gate electrodes (indium-tin oxide - ITO). As an external physical stimulation to examine the tactile touch performance, a weak nitrogen flow (83.3 μl/s) was employed to stimulate the LC layer of the touch device. The LC-g-OFET device exhibited p-type transistor characteristics with a hole mobility of 1.5 cm 2 /Vs, but no sensing current by the nitrogen flow touch was measured at sufficiently high drain (V D ) and gate (V G ) voltages. However, a clear sensing current signal was detected at lower voltages, which was quite sensitive to the combination of V D and V G . The best voltage combination was V D = −0.2 V and V G = −1 V for the highest ratio of signal currents to base currents (i.e., signal-to-noise ratio). The change in the LC alignment upon the nitrogen flow touch was assigned as the mechanism for the present LC-g-OFET touch sensors

Detailed simulation study of a dual material gate carbon nanotube field-effect transistor

Science.gov (United States)

Orouji, Ali A.; Arefinia, Zahra

2009-02-01

For the first time, a new type of carbon nanotube field-effect transistor (CNTFET), the dual material gate (DMG)-CNTFET, is proposed and simulated using quantum simulation that is based on self-consistent solution between two-dimensional Poisson equation and Schrödinger equation with open boundary conditions, within the nonequilibrium Green's function (NEGF) framework. The proposed structure is similar to that of the conventional coaxial CNTFET with the exception that the gate of the DMG-CNTFET consists of two laterally contacting metals with different work functions. Simulation results show DMG-CNTFET significantly decreases leakage current, drain conductance and subthreshold swing, and increases on-off current ratio and voltage gain as compared to conventional CNTFET. We demonstrate that the potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed short-channel effects like the drain-induced barrier lowering (DIBL) and hot-carrier effect.

Vertically aligned carbon nanotube field-effect transistors

KAUST Repository

Li, Jingqi

2012-10-01

Vertically aligned carbon nanotube field-effect transistors (CNTFETs) have been developed using pure semiconducting carbon nanotubes. The source and drain were vertically stacked, separated by a dielectric, and the carbon nanotubes were placed on the sidewall of the stack to bridge the source and drain. Both the effective gate dielectric and gate electrode were normal to the substrate surface. The channel length is determined by the dielectric thickness between source and drain electrodes, making it easier to fabricate sub-micrometer transistors without using time-consuming electron beam lithography. The transistor area is much smaller than the planar CNTFET due to the vertical arrangement of source and drain and the reduced channel area. © 2012 Elsevier Ltd. All rights reserved.

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

Science.gov (United States)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

Investigations on field-effect transistors based on two-dimensional materials

Energy Technology Data Exchange (ETDEWEB)

Finge, T.; Riederer, F.; Grap, T.; Knoch, J. [Institute of Semiconductor Electronics, RWTH Aachen University (Germany); Mueller, M.R. [Institute of Semiconductor Electronics, RWTH Aachen University (Germany); Infineon Technologies, Villach (Austria); Kallis, K. [Intelligent Microsystems Chair, TU Dortmund University (Germany)

2017-11-15

In the present article, experimental and theoretical investigations regarding field-effect transistors based on two-dimensional (2D) materials are presented. First, the properties of contacts between a metal and 2D material are discussed. To this end, metal-to-graphene contacts as well to transition metal dichalcogenides (TMD) are studied. Whereas metal-graphene contacts can be tuned with an appropriate back-gate, metal-TMD contacts exhibit strong Fermi level pinning showing substantially limited maximum possible drive current. Next, tungsten diselenide (WSe{sub 2}) field-effect transistors are presented. Employing buried-triple-gate substrates allows tuning source, channel and drain by applying appropriate gate voltages so that the device can be reconfigured to work as n-type, p-type and as so-called band-to-band tunnel field-effect transistor on the same WSe{sub 2} flake. (copyright 2017 by WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Microwave annealing effect for highly reliable biosensor: dual-gate ion-sensitive field-effect transistor using amorphous InGaZnO thin-film transistor.

Science.gov (United States)

Lee, In-Kyu; Lee, Kwan Hyi; Lee, Seok; Cho, Won-Ju

2014-12-24

We used a microwave annealing process to fabricate a highly reliable biosensor using amorphous-InGaZnO (a-IGZO) thin-film transistors (TFTs), which usually experience threshold voltage instability. Compared with furnace-annealed a-IGZO TFTs, the microwave-annealed devices showed superior threshold voltage stability and performance, including a high field-effect mobility of 9.51 cm(2)/V·s, a low threshold voltage of 0.99 V, a good subthreshold slope of 135 mV/dec, and an outstanding on/off current ratio of 1.18 × 10(8). In conclusion, by using the microwave-annealed a-IGZO TFT as the transducer in an extended-gate ion-sensitive field-effect transistor biosensor, we developed a high-performance biosensor with excellent sensing properties in terms of pH sensitivity, reliability, and chemical stability.

High carrier mobility of CoPc wires based field-effect transistors using bi-layer gate dielectric

Directory of Open Access Journals (Sweden)

Murali Gedda

2013-11-01

Full Text Available Polyvinyl alcohol (PVA and anodized Al2O3 layers were used as bi-layer gate for the fabrication of cobalt phthalocyanine (CoPc wire base field-effect transistors (OFETs. CoPc wires were grown on SiO2 surfaces by organic vapor phase deposition method. These devices exhibit a field-effect carrier mobility (μEF value of 1.11 cm2/Vs. The high carrier mobility for CoPc molecules is attributed to the better capacitive coupling between the channel of CoPc wires and the gate through organic-inorganic dielectric layer. Our measurements also demonstrated the way to determine the thicknesses of the dielectric layers for a better process condition of OFETs.

Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

International Nuclear Information System (INIS)

Jiang Zhi; Zhuang Yi-Qi; Li Cong; Wang Ping; Liu Yu-Qi

2016-01-01

Trap-assisted tunneling (TAT) has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor (TFET). In this paper, we assess subthreshold performance of double gate TFET (DG-TFET) through a band-to-band tunneling (BTBT) model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile (D it ) and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current. (paper)

Hysteresis behaviour of low-voltage organic field-effect transistors employing high dielectric constant polymer gate dielectrics

International Nuclear Information System (INIS)

Kim, Se Hyun; Yun, Won Min; Kwon, Oh-Kwan; Hong, Kipyo; Yang, Chanwoo; Park, Chan Eon; Choi, Woon-Seop

2010-01-01

Here, we report on the fabrication of low-voltage-operating pentacene-based organic field-effect transistors (OFETs) that utilize crosslinked cyanoethylated poly(vinyl alcohol) (CR-V) gate dielectrics. The crosslinked CR-V-based OFET could be operated successfully at low voltages (below 4 V), but abnormal behaviour during device operation, such as uncertainty in the field-effect mobility (μ) and hysteresis, was induced by the slow polarization of moieties embedded in the gate dielectric (e.g. polar functionalities, ionic impurities, water and solvent molecules). In an effort to improve the stability of OFET operation, we measured the dependence of μ and hysteresis on dielectric thickness, CR-V crosslinking conditions and sweep rate of the gate bias. The influence of the CR-V surface properties on μ, hysteresis, and the structural and morphological features of the pentacene layer grown on the gate dielectric was characterized and compared with the properties of pentacene grown on a polystyrene surface.

Low operating voltage n-channel organic field effect transistors using lithium fluoride/PMMA bilayer gate dielectric

Energy Technology Data Exchange (ETDEWEB)

Kumar, S.; Dhar, A., E-mail: adhar@phy.iitkgp.ernet.in

2015-10-15

Highlights: • Alternative to chemically crosslinking of PMMA to achieve low leakage in provided. • Effect of LiF in reducing gate leakage through the OFET device is studied. • Effect of gate leakage on transistor performance has been investigated. • Low voltage operable and low temperature processed n-channel OFETs were fabricated. - Abstract: We report low temperature processed, low voltage operable n-channel organic field effect transistors (OFETs) using N,N′-Dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C{sub 8}) organic semiconductor and poly(methylmethacrylate) (PMMA)/lithium fluoride (LiF) bilayer gate dielectric. We have studied the role of LiF buffer dielectric in effectively reducing the gate leakage through the device and thus obtaining superior performance in contrast to the single layer PMMA dielectric devices. The bilayer OFET devices had a low threshold voltage (V{sub t}) of the order of 5.3 V. The typical values of saturation electron mobility (μ{sub s}), on/off ratio and inverse sub-threshold slope (S) for the range of devices made were estimated to be 2.8 × 10{sup −3} cm{sup 2}/V s, 385, and 3.8 V/decade respectively. Our work thus provides a potential substitution for much complicated process of chemically crosslinking PMMA to achieve low leakage, high capacitance, and thus low operating voltage OFETs.

Drain-induced barrier lowering effect for short channel dual material gate 4H silicon carbide metal—semiconductor field-effect transistor

Science.gov (United States)

Zhang, Xian-Jun; Yang, Yin-Tang; Duan, Bao-Xing; Chai, Chang-Chun; Song, Kun; Chen, Bin

2012-09-01

Sub-threshold characteristics of the dual material gate 4H-SiC MESFET (DMGFET) are investigated and the analytical models to describe the drain-induced barrier lowering (DIBL) effect are derived by solving one- and two-dimensional Poisson's equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering (DIBL) effect. The calculated results reveal that the dual material gate (DMG) structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal—semiconductor field-effect transistor (SMGFET).

Drain-induced barrier lowering effect for short channel dual material gate 4H silicon carbide metal—semiconductor field-effect transistor

International Nuclear Information System (INIS)

Zhang Xian-Jun; Yang Yin-Tang; Duan Bao-Xing; Chai Chang-Chun; Song Kun; Chen Bin

2012-01-01

Sub-threshold characteristics of the dual material gate 4H-SiC MESFET (DMGFET) are investigated and the analytical models to describe the drain-induced barrier lowering (DIBL) effect are derived by solving one- and two-dimensional Poisson's equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering (DIBL) effect. The calculated results reveal that the dual material gate (DMG) structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal—semiconductor field-effect transistor (SMGFET)

Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

Energy Technology Data Exchange (ETDEWEB)

Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn; Chi, Li-Feng, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn [Jiangsu Key Laboratory for Carbon-Based Functional Materials and Devices, Institute of Functional Nano and Soft Materials (FUNSOM), Soochow University, Suzhou, Jiangsu 215123 (China)

2015-03-23

Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

International Nuclear Information System (INIS)

Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin; Chi, Li-Feng; Wang, Sui-Dong

2015-01-01

Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process

Influence of gate dielectric on the ambipolar characteristics of solution-processed organic field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Ribierre, J C; Ghosh, S; Takaishi, K; Muto, T; Aoyama, T, E-mail: jcribierre@ewha.ac.kr, E-mail: taoyama@riken.jp [Advanced Science Institute, RIKEN, 2-1 Hirosawa, Wako, Saitama 351-0198 (Japan)

2011-05-25

Solution-processed ambipolar organic field-effect transistors based on dicyanomethylene-substituted quinoidal quaterthiophene derivative [QQT(CN)4] are fabricated using various gate dielectric materials including cross-linked polyimide and poly-4-vinylphenol. Devices with spin-coated polymeric gate dielectric layers show a reduced hysteresis in their transfer characteristics. Among the insulating polymers examined in this study, a new fluorinated polymer with a low dielectric constant of 2.8 significantly improves both hole and electron field-effect mobilities of QQT(CN)4 thin films to values as high as 0.04 and 0.002 cm{sup 2} V{sup -1} s{sup -1}. These values are close to the best mobilities obtained in QQT(CN)4 devices fabricated on SiO{sub 2} treated with octadecyltrichlorosilane. The influence of the metal used for source/drain metal electrodes on the device performance is also investigated. Whereas best device performances are achieved with gold electrodes, more balanced electron and hole field-effect mobilities could be obtained using chromium.

Dual metal gate tunneling field effect transistors based on MOSFETs: A 2-D analytical approach

Science.gov (United States)

Ramezani, Zeinab; Orouji, Ali A.

2018-01-01

A novel 2-D analytical drain current model of novel Dual Metal Gate Tunnel Field Effect Transistors Based on MOSFETs (DMG-TFET) is presented in this paper. The proposed Tunneling FET is extracted from a MOSFET structure by employing an additional electrode in the source region with an appropriate work function to induce holes in the N+ source region and hence makes it as a P+ source region. The electric field is derived which is utilized to extract the expression of the drain current by analytically integrating the band to band tunneling generation rate in the tunneling region based on the potential profile by solving the Poisson's equation. Through this model, the effects of the thin film thickness and gate voltage on the potential, the electric field, and the effects of the thin film thickness on the tunneling current can be studied. To validate our present model we use SILVACO ATLAS device simulator and the analytical results have been compared with it and found a good agreement.

Light-effect transistor (LET with multiple independent gating controls for optical logic gates and optical amplification

Directory of Open Access Journals (Sweden)

Jason eMarmon

2016-03-01

Full Text Available Modern electronics are developing electronic-optical integrated circuits, while their electronic backbone, e.g. field-effect transistors (FETs, remains the same. However, further FET down scaling is facing physical and technical challenges. A light-effect transistor (LET offers electronic-optical hybridization at the component level, which can continue Moore’s law to quantum region without requiring a FET’s fabrication complexity, e.g. physical gate and doping, by employing optical gating and photoconductivity. Multiple independent gates are therefore readily realized to achieve unique functionalities without increasing chip space. Here we report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs show output and transfer characteristics resembling advanced FETs, e.g. on/off ratios up to ~1.0x106 with a source-drain voltage of ~1.43 V, gate-power of ~260 nW, and subthreshold swing of ~0.3 nW/decade (excluding losses. Our work offers new electronic-optical integration strategies and electronic and optical computing approaches.

Bias stress effect and recovery in organic field effect transistors : proton migration mechanism

NARCIS (Netherlands)

Sharma, A.; Mathijssen, S.G.J.; Kemerink, M.; Leeuw, de D.M.; Bobbert, P.A.; Bao, Z.; McCulloch, I.

2010-01-01

Organic field-effect transistors exhibit operational instabilities when a gate bias is applied. For a constant gate bias the threshold voltage shifts towards the applied gate bias voltage, an effect known as the bias-stress effect. We have performed a detailed experimental and theoretical study of

Wafer-Scale Gigahertz Graphene Field Effect Transistors on SiC Substrates

Institute of Scientific and Technical Information of China (English)

潘洪亮; 金智; 麻芃; 郭建楠; 刘新宇; 叶甜春; 李佳; 敦少博; 冯志红

2011-01-01

Wafer-scale graphene field-effect transistors are fabricated using benzocyclobutene and atomic layer deposition Al2O3 as the top-gate dielectric.The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate.The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found.For the intrinsic characteristic of this particular channel material,the devices cannot be switched off.The cut-off frequencies of these graphene field-effect transistors,which have a gate length of l μm,are larger than 800 MHz.The largest one can reach 1.24 GHz.There are greater than 95％ active devices that can be successfully applied.We thus succeed in fabricating wafer-scale gigahertz graphene field-effect transistors,which paves the way for high-performance graphene devices and circuits.%Wafer-scale graphene Beld-effect transistors are fabricated using benzocyclobutene and atomic layer deposition AI2O3 as the top-gate dielectric. The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate. The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found. For the intrinsic characteristic of this particular channel material, the devices cannot be switched off. The cut-off frequencies of these graphene field-effect transistors, which have a gate length of l μm, are larger than 800MHz. The largest one can reach 1.24 GHz. There are greater than 95% active devices that can be successfully applied. We thus succeed in fabricating wafer-scale gigahertz graphene Geld-effect transistors, which paves the way for high-performance graphene devices and circuits.

Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

Energy Technology Data Exchange (ETDEWEB)

Inaba, Masafumi, E-mail: inaba-ma@ruri.waseda.jp; Muta, Tsubasa; Kobayashi, Mikinori; Saito, Toshiki; Shibata, Masanobu; Matsumura, Daisuke; Kudo, Takuya; Hiraiwa, Atsushi [Graduate School of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kawarada, Hiroshi [Graduate School of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kagami Memorial Laboratory for Materials Science and Technology, Waseda University, 2-8-26 Nishiwaseda, Shinjuku, Tokyo 169-0051 (Japan)

2016-07-18

The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al{sub 2}O{sub 3}. Using Al{sub 2}O{sub 3} as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulation by the gate and pinch off.

Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

Science.gov (United States)

Zhi, Jiang; Yi-Qi, Zhuang; Cong, Li; Ping, Wang; Yu-Qi, Liu

2016-02-01

Trap-assisted tunneling (TAT) has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor (TFET). In this paper, we assess subthreshold performance of double gate TFET (DG-TFET) through a band-to-band tunneling (BTBT) model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile (Dit) and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current. Project supported by the National Natural Science Foundation of China (Grant Nos. 61574109 and 61204092).

Lateral energy band profile modulation in tunnel field effect transistors based on gate structure engineering

Directory of Open Access Journals (Sweden)

Ning Cui

2012-06-01

Full Text Available Choosing novel materials and structures is important for enhancing the on-state current in tunnel field-effect transistors (TFETs. In this paper, we reveal that the on-state performance of TFETs is mainly determined by the energy band profile of the channel. According to this interpretation, we present a new concept of energy band profile modulation (BPM achieved with gate structure engineering. It is believed that this approach can be used to suppress the ambipolar effect. Based on this method, a Si TFET device with a symmetrical tri-material-gate (TMG structure is proposed. Two-dimensional numerical simulations demonstrated that the special band profile in this device can boost on-state performance, and it also suppresses the off-state current induced by the ambipolar effect. These unique advantages are maintained over a wide range of gate lengths and supply voltages. The BPM concept can serve as a guideline for improving the performance of nanoscale TFET devices.

Field emission current from a junction field-effect transistor

International Nuclear Information System (INIS)

Monshipouri, Mahta; Abdi, Yaser

2015-01-01

Fabrication of a titanium dioxide/carbon nanotube (TiO 2 /CNT)-based transistor is reported. The transistor can be considered as a combination of a field emission transistor and a junction field-effect transistor. Using direct current plasma-enhanced chemical vapor deposition (DC-PECVD) technique, CNTs were grown on a p-typed (100)-oriented silicon substrate. The CNTs were then covered by TiO 2 nanoparticles 2–5 nm in size, using an atmospheric pressure CVD technique. In this device, TiO 2 /CNT junction is responsible for controlling the emission current. High on/off-current ratio and proper gate control are the most important advantages of device. A model based on Fowler–Nordheim equation is utilized for calculation of the emission current and the results are compared with experimental data. The effect of TiO 2 /CNT hetero-structure is also investigated, and well modeled

Graphene Field Effect Transistor for Radiation Detection

Science.gov (United States)

Li, Mary J. (Inventor); Chen, Zhihong (Inventor)

2016-01-01

The present invention relates to a graphene field effect transistor-based radiation sensor for use in a variety of radiation detection applications, including manned spaceflight missions. The sensing mechanism of the radiation sensor is based on the high sensitivity of graphene in the local change of electric field that can result from the interaction of ionizing radiation with a gated undoped silicon absorber serving as the supporting substrate in the graphene field effect transistor. The radiation sensor has low power and high sensitivity, a flexible structure, and a wide temperature range, and can be used in a variety of applications, particularly in space missions for human exploration.

Effect of liquid gate bias rising time in pH sensors based on Si nanowire ion sensitive field effect transistors

Science.gov (United States)

Jang, Jungkyu; Choi, Sungju; Kim, Jungmok; Park, Tae Jung; Park, Byung-Gook; Kim, Dong Myong; Choi, Sung-Jin; Lee, Seung Min; Kim, Dae Hwan; Mo, Hyun-Sun

2018-02-01

In this study, we investigate the effect of rising time (TR) of liquid gate bias (VLG) on transient responses in pH sensors based on Si nanowire ion-sensitive field-effect transistors (ISFETs). As TR becomes shorter and pH values decrease, the ISFET current takes a longer time to saturate to the pH-dependent steady-state value. By correlating VLG with the internal gate-to-source voltage of the ISFET, we found that this effect occurs when the drift/diffusion of mobile ions in analytes in response to VLG is delayed. This gives us useful insight on the design of ISFET-based point-of-care circuits and systems, particularly with respect to determining an appropriate rising time for the liquid gate bias.

Field emission current from a junction field-effect transistor

Energy Technology Data Exchange (ETDEWEB)

Monshipouri, Mahta; Abdi, Yaser, E-mail: y.abdi@ut.ac.ir [University of Tehran, Nano-Physics Research Laboratory, Department of Physics (Iran, Islamic Republic of)

2015-04-15

Fabrication of a titanium dioxide/carbon nanotube (TiO{sub 2}/CNT)-based transistor is reported. The transistor can be considered as a combination of a field emission transistor and a junction field-effect transistor. Using direct current plasma-enhanced chemical vapor deposition (DC-PECVD) technique, CNTs were grown on a p-typed (100)-oriented silicon substrate. The CNTs were then covered by TiO{sub 2} nanoparticles 2–5 nm in size, using an atmospheric pressure CVD technique. In this device, TiO{sub 2}/CNT junction is responsible for controlling the emission current. High on/off-current ratio and proper gate control are the most important advantages of device. A model based on Fowler–Nordheim equation is utilized for calculation of the emission current and the results are compared with experimental data. The effect of TiO{sub 2}/CNT hetero-structure is also investigated, and well modeled.

Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation

Science.gov (United States)

Seema; Chauhan, Sudakar Singh

2018-05-01

In this paper, we demonstrate the double gate vertical tunnel field-effect transistor using homo/hetero dielectric buried oxide (HDB) to obtain the optimized device characteristics. In this concern, the existence of double gate, HDB and electrode work-function engineering enhances DC performance and Analog/RF performance. The use of electrostatic doping helps to achieve higher on-current owing to occurrence of higher tunneling generation rate of charge carriers at the source/epitaxial interface. Further, lightly doped drain region and high- k dielectric below channel and drain region are responsible to suppress the ambipolar current. Simulated results clarifies that proposed device have achieved the tremendous performance in terms of driving current capability, steeper subthreshold slope (SS), drain induced barrier lowering (DIBL), hot carrier effects (HCEs) and high frequency parameters for better device reliability.

Strain-Gated Field Effect Transistor of a MoS2-ZnO 2D-1D Hybrid Structure.

Science.gov (United States)

Chen, Libo; Xue, Fei; Li, Xiaohui; Huang, Xin; Wang, Longfei; Kou, Jinzong; Wang, Zhong Lin

2016-01-26

Two-dimensional (2D) molybdenum disulfide (MoS2) is an exciting material due to its unique electrical, optical, and piezoelectric properties. Owing to an intrinsic band gap of 1.2-1.9 eV, monolayer or a-few-layer MoS2 is used for fabricating field effect transistors (FETs) with high electron mobility and on/off ratio. However, the traditional FETs are controlled by an externally supplied gate voltage, which may not be sensitive enough to directly interface with a mechanical stimulus for applications in electronic skin. Here we report a type of top-pressure/force-gated field effect transistors (PGFETs) based on a hybrid structure of a 2D MoS2 flake and 1D ZnO nanowire (NW) array. Once an external pressure is applied, the piezoelectric polarization charges created at the tips of ZnO NWs grown on MoS2 act as a gate voltage to tune/control the source-drain transport property in MoS2. At a 6.25 MPa applied stimulus on a packaged device, the source-drain current can be tuned for ∼25%, equivalent to the results of applying an extra -5 V back gate voltage. Another type of PGFET with a dielectric layer (Al2O3) sandwiched between MoS2 and ZnO also shows consistent results. A theoretical model is proposed to interpret the received data. This study sets the foundation for applying the 2D material-based FETs in the field of artificial intelligence.

An analytic model for gate-all-around silicon nanowire tunneling field effect transistors

International Nuclear Information System (INIS)

Liu Ying; He Jin; Chan Mansun; Ye Yun; Zhao Wei; Wu Wen; Deng Wan-Ling; Wang Wen-Ping; Du Cai-Xia

2014-01-01

An analytical model of gate-all-around (GAA) silicon nanowire tunneling field effect transistors (NW-TFETs) is developted based on the surface potential solutions in the channel direction and considering the band to band tunneling (BTBT) efficiency. The three-dimensional Poisson equation is solved to obtain the surface potential distributions in the partition regions along the channel direction for the NW-TFET, and a tunneling current model using Kane's expression is developed. The validity of the developed model is shown by the good agreement between the model predictions and the TCAD simulation results. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

High performance tunnel field-effect transistor by gate and source engineering.

Science.gov (United States)

Huang, Ru; Huang, Qianqian; Chen, Shaowen; Wu, Chunlei; Wang, Jiaxin; An, Xia; Wang, Yangyuan

2014-12-19

As one of the most promising candidates for future nanoelectronic devices, tunnel field-effect transistors (TFET) can overcome the subthreshold slope (SS) limitation of MOSFET, whereas high ON-current, low OFF-current and steep switching can hardly be obtained at the same time for experimental TFETs. In this paper, we developed a new nanodevice technology based on TFET concepts. By designing the gate configuration and introducing the optimized Schottky junction, a multi-finger-gate TFET with a dopant-segregated Schottky source (mFSB-TFET) is proposed and experimentally demonstrated. A steeper SS can be achieved in the fabricated mFSB-TFET on the bulk Si substrate benefiting from the coupled quantum band-to-band tunneling (BTBT) mechanism, as well as a high I(ON)/I(OFF) ratio (∼ 10(7)) at V(DS) = 0.2 V without an area penalty. By compatible SOI CMOS technology, the fabricated Si mFSB-TFET device was further optimized with a high ION/IOFF ratio of ∼ 10(8) and a steeper SS of over 5.5 decades of current. A minimum SS of below 60 mV dec(-1) was experimentally obtained, indicating its dominant quantum BTBT mechanism for switching.

Perspective analysis of tri gate germanium tunneling field-effect transistor with dopant segregation region at source/drain

Science.gov (United States)

Liu, Liang-kui; Shi, Cheng; Zhang, Yi-bo; Sun, Lei

2017-04-01

A tri gate Ge-based tunneling field-effect transistor (TFET) has been numerically studied with technology computer aided design (TCAD) tools. Dopant segregated Schottky source/drain is applied to the device structure design (DS-TFET). The characteristics of the DS-TFET are compared and analyzed comprehensively. It is found that the performance of n-channel tri gate DS-TFET with a positive bias is insensitive to the dopant concentration and barrier height at n-type drain, and that the dopant concentration and barrier height at a p-type source considerably affect the device performance. The domination of electron current in the entire BTBT current of this device accounts for this phenomenon and the tri-gate DS-TFET is proved to have a higher performance than its dual-gate counterpart.

CMOS-compatible fabrication of top-gated field-effect transistor silicon nanowire-based biosensors

International Nuclear Information System (INIS)

Ginet, Patrick; Akiyama, Sho; Takama, Nobuyuki; Fujita, Hiroyuki; Kim, Beomjoon

2011-01-01

Field-effect transistor (FET) nanowire-based biosensors are very promising tools for medical diagnosis. In this paper, we introduce a simple method to fabricate FET silicon nanowires using only standard microelectromechanical system (MEMS) processes. The key steps of our fabrication process were a local oxidation of silicon (LOCOS) and anisotropic KOH etchings that enabled us to reduce the width of the initial silicon structures from 10 µm to 170 nm. To turn the nanowires into a FET, a top-gate electrode was patterned in gold next to them in order to apply the gate voltage directly through the investigated liquid environment. An electrical characterization demonstrated the p-type behaviour of the nanowires. Preliminary chemical sensing tested the sensitivity to pH of our device. The effect of the binding of streptavidin on biotinylated nanowires was monitored in order to evaluate their biosensing ability. In this way, streptavidin was detected down to a 100 ng mL −1 concentration in phosphate buffered saline by applying a gate voltage less than 1.2 V. The use of a top-gate electrode enabled the detection of biological species with only very low voltages that were compatible with future handheld-requiring applications. We thus demonstrated the potential of our devices and their fabrication as a solution for the mass production of efficient and reliable FET nanowire-based biological sensors

Triggering the Electrolyte-Gated Organic Field-Effect Transistor output characteristics through gate functionalization using diazonium chemistry: Application to biodetection of 2,4-dichlorophenoxyacetic acid.

Science.gov (United States)

Nguyen, T T K; Nguyen, T N; Anquetin, G; Reisberg, S; Noël, V; Mattana, G; Touzeau, J; Barbault, F; Pham, M C; Piro, B

2018-04-26

We investigated an Electrolyte-Gated Organic Field-Effect transistor based on poly(N-alkyldiketopyrrolo-pyrrole dithienylthieno[3,2-b]thiophene) as organic semiconductor whose gate electrode was functionalized by electrografting a functional diazonium salt capable to bind an antibody specific to 2,4-dichlorophenoxyacetic acid (2,4-D), an herbicide well-known to be a soil and water pollutant. Molecular docking computations were performed to design the functional diazonium salt to rationalize the antibody capture on the gate surface. Sensing of 2,4-D was performed through a displacement immunoassay. The limit of detection was estimated at around 2.5 fM. Copyright © 2018 Elsevier B.V. All rights reserved.

Fabrication and independent control of patterned polymer gate for a few-layer WSe{sub 2} field-effect transistor

Energy Technology Data Exchange (ETDEWEB)

Hong, Sung Ju; Park, Min; Kang, Hojin; Park, Yung Woo, E-mail: ywpark@snu.ac.kr [Department of Physics and Astronomy, Seoul National University, Seoul 151-747 (Korea, Republic of); Lee, Minwoo; Jeong, Dae Hong [Department of Chemistry Education, Seoul National University, Seoul 151-742 (Korea, Republic of)

2016-08-15

We report the fabrication of a patterned polymer electrolyte for a two-dimensional (2D) semiconductor, few-layer tungsten diselenide (WSe{sub 2}) field-effect transistor (FET). We expose an electron-beam in a desirable region to form the patterned structure. The WSe{sub 2} FET acts as a p-type semiconductor in both bare and polymer-covered devices. We observe a highly efficient gating effect in the polymer-patterned device with independent gate control. The patterned polymer gate operates successfully in a molybdenum disulfide (MoS{sub 2}) FET, indicating the potential for general applications to 2D semiconductors. The results of this study can contribute to large-scale integration and better flexibility in transition metal dichalcogenide (TMD)-based electronics.

Analysis of gate underlap channel double gate MOS transistor for electrical detection of bio-molecules

Science.gov (United States)

Ajay; Narang, Rakhi; Saxena, Manoj; Gupta, Mridula

2015-12-01

In this paper, an analytical model for gate drain underlap channel Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG-MOSFET) for label free electrical detection of biomolecules has been proposed. The conformal mapping technique has been used to derive the expressions for surface potential, lateral electric field, energy bands (i.e. conduction and valence band) and threshold voltage (Vth). Subsequently a full drain current model to analyze the sensitivity of the biosensor has been developed. The shift in the threshold voltage and drain current (after the biomolecules interaction with the gate underlap channel region of the MOS transistor) has been used as a sensing metric. All the characteristic trends have been verified through ATLAS (SILVACO) device simulation results.

Graphene field effect transistor without an energy gap.

Science.gov (United States)

Jang, Min Seok; Kim, Hyungjun; Son, Young-Woo; Atwater, Harry A; Goddard, William A

2013-05-28

Graphene is a room temperature ballistic electron conductor and also a very good thermal conductor. Thus, it has been regarded as an ideal material for postsilicon electronic applications. A major complication is that the relativistic massless electrons in pristine graphene exhibit unimpeded Klein tunneling penetration through gate potential barriers. Thus, previous efforts to realize a field effect transistor for logic applications have assumed that introduction of a band gap in graphene is a prerequisite. Unfortunately, extrinsic treatments designed to open a band gap seriously degrade device quality, yielding very low mobility and uncontrolled on/off current ratios. To solve this dilemma, we propose a gating mechanism that leads to a hundredfold enhancement in on/off transmittance ratio for normally incident electrons without any band gap engineering. Thus, our saw-shaped geometry gate potential (in place of the conventional bar-shaped geometry) leads to switching to an off state while retaining the ultrahigh electron mobility in the on state. In particular, we report that an on/off transmittance ratio of 130 is achievable for a sawtooth gate with a gate length of 80 nm. Our switching mechanism demonstrates that intrinsic graphene can be used in designing logic devices without serious alteration of the conventional field effect transistor architecture. This suggests a new variable for the optimization of the graphene-based device--geometry of the gate electrode.

Effect of a gate buffer layer on the performance of a 4H-SiC Schottky barrier field-effect transistor

International Nuclear Information System (INIS)

Zhang Xianjun; Yang Yintang; Chai Changchun; Duan Baoxing; Song Kun; Chen Bin

2012-01-01

A lower doped layer is inserted between the gate and channel layer and its effect on the performance of a 4H-SiC Schottky barrier field-effect transistor (MESFET) is investigated. The dependences of the drain current and small signal parameters on this inserted gate-buffer layer are obtained by solving one-dimensional (1-D) and two-dimensional (2-D) Poisson's equations. The drain current and small signal parameters of the 4H-SiC MESFET with a gate-buffer layer thickness of 0.15 μm are calculated and the breakdown characteristics are simulated. The results show that the current is increased by increasing the thickness of the gate-buffer layer; the breakdown voltage is 160 V, compared with 125 V for the conventional 4H-SiC MESFET; the cutoff frequency is 27 GHz, which is higher than 20 GHz of the conventional structure due to the lower doped gate-buffer layer. (semiconductor devices)

Tunable Mobility in Double-Gated MoTe2 Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites.

Science.gov (United States)

Ji, Hyunjin; Joo, Min-Kyu; Yi, Hojoon; Choi, Homin; Gul, Hamza Zad; Ghimire, Mohan Kumar; Lim, Seong Chu

2017-08-30

There is a general consensus that the carrier mobility in a field-effect transistor (FET) made of semiconducting transition-metal dichalcogenides (s-TMDs) is severely degraded by the trapping/detrapping and Coulomb scattering of carriers by ionic charges in the gate oxides. Using a double-gated (DG) MoTe 2 FET, we modulated and enhanced the carrier mobility by adjusting the top- and bottom-gate biases. The relevant mechanism for mobility tuning in this device was explored using static DC and low-frequency (LF) noise characterizations. In the investigations, LF-noise analysis revealed that for a strong back-gate bias the Coulomb scattering of carriers by ionized traps in the gate dielectrics is strongly screened by accumulation charges. This significantly reduces the electrostatic scattering of channel carriers by the interface trap sites, resulting in increased mobility. The reduction of the number of effective trap sites also depends on the gate bias, implying that owing to the gate bias, the carriers are shifted inside the channel. Thus, the number of active trap sites decreases as the carriers are repelled from the interface by the gate bias. The gate-controlled Coulomb-scattering parameter and the trap-site density provide new handles for improving the carrier mobility in TMDs, in a fundamentally different way from dielectric screening observed in previous studies.

Proposal for a dual-gate spin field effect transistor: A device with very small switching voltage and a large ON to OFF conductance ratio

Science.gov (United States)

Wan, J.; Cahay, M.; Bandyopadhyay, S.

2008-06-01

We propose a new dual gate spin field effect transistor (SpinFET) consisting of a quasi one-dimensional semiconductor channel sandwiched between two half-metallic contacts. The gate voltage aligns and de-aligns the incident electron energy with Ramsauer resonance levels in the channel, thereby modulating the source-to-drain conductance. The device can be switched from ON to OFF with a few mV change in the gate voltage, resulting in exceedingly low dynamic power dissipation during switching. The conductance ON/OFF ratio stays fairly large ( ∼60) up to a temperature of 10 K. This conductance ratio is comparable to that achievable with carbon nanotube transistors.

Cylindrical-shaped nanotube field effect transistor

KAUST Repository

Hussain, Muhammad Mustafa; Fahad, Hossain M.; Smith, Casey E.; Rojas, Jhonathan Prieto

2015-01-01

A cylindrical-shaped nanotube FET may be manufactured on silicon (Si) substrates as a ring etched into a gate stack and filled with semiconductor material. An inner gate electrode couples to a region of the gate stack inside the inner circumference of the ring. An outer gate electrode couples to a region of the gate stack outside the outer circumference of the ring. The multi-gate cylindrical-shaped nanotube FET operates in volume inversion for ring widths below 15 nanometers. The cylindrical-shaped nanotube FET demonstrates better short channel effect (SCE) mitigation and higher performance (I.sub.on/I.sub.off) than conventional transistor devices. The cylindrical-shaped nanotube FET may also be manufactured with higher yields and cheaper costs than conventional transistors.

Cylindrical-shaped nanotube field effect transistor

KAUST Repository

Hussain, Muhammad Mustafa

2015-12-29

A cylindrical-shaped nanotube FET may be manufactured on silicon (Si) substrates as a ring etched into a gate stack and filled with semiconductor material. An inner gate electrode couples to a region of the gate stack inside the inner circumference of the ring. An outer gate electrode couples to a region of the gate stack outside the outer circumference of the ring. The multi-gate cylindrical-shaped nanotube FET operates in volume inversion for ring widths below 15 nanometers. The cylindrical-shaped nanotube FET demonstrates better short channel effect (SCE) mitigation and higher performance (I.sub.on/I.sub.off) than conventional transistor devices. The cylindrical-shaped nanotube FET may also be manufactured with higher yields and cheaper costs than conventional transistors.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

Science.gov (United States)

Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

2014-10-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

International Nuclear Information System (INIS)

Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

2014-01-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

Research of the voltage and current stabilization processes by using the silicon field-effect transistor

International Nuclear Information System (INIS)

Karimov, A.V.; Yodgorova, D.M.; Kamanov, B.M.; Giyasova, F.A.; Yakudov, A.A.

2012-01-01

The silicon field-effect transistors were investigated to use in circuits for stabilization of current and voltage. As in gallium arsenide field-effect transistors, in silicon field-effect transistors with p-n-junction a new mechanism of saturation of the drain current is experimentally found out due to both transverse and longitudinal compression of channel by additional resistance between the source and the gate of the transistor. The criteria for evaluating the coefficients of stabilization of transient current suppressors and voltage stabilizator based on the field-effect transistor are considered. (authors)

Molecular-beam-deposited yttrium-oxide dielectrics in aluminum-gated metal - oxide - semiconductor field-effect transistors: Effective electron mobility

International Nuclear Information System (INIS)

Ragnarsson, L.-A degree.; Guha, S.; Copel, M.; Cartier, E.; Bojarczuk, N. A.; Karasinski, J.

2001-01-01

We report on high effective mobilities in yttrium-oxide-based n-channel metal - oxide - semiconductor field-effect transistors (MOSFETs) with aluminum gates. The yttrium oxide was grown in ultrahigh vacuum using a reactive atomic-beam-deposition system. Medium-energy ion-scattering studies indicate an oxide with an approximate composition of Y 2 O 3 on top of a thin layer of interfacial SiO 2 . The thickness of this interfacial oxide as well as the effective mobility are found to be dependent on the postgrowth anneal conditions. Optimum conditions result in mobilities approaching that of SiO 2 -based MOSFETs at higher fields with peak mobilities at approximately 210 cm 2 /Vs. [copyright] 2001 American Institute of Physics

Microscopic gate-modulation imaging of charge and field distribution in polycrystalline organic transistors

Science.gov (United States)

Matsuoka, Satoshi; Tsutsumi, Jun'ya; Kamata, Toshihide; Hasegawa, Tatsuo

2018-04-01

In this work, a high-resolution microscopic gate-modulation imaging (μ-GMI) technique is successfully developed to visualize inhomogeneous charge and electric field distributions in operating organic thin-film transistors (TFTs). We conduct highly sensitive and diffraction-limit gate-modulation sensing for acquiring difference images of semiconducting channels between at gate-on and gate-off states that are biased at an alternate frequency of 15 Hz. As a result, we observe unexpectedly inhomogeneous distribution of positive and negative local gate-modulation (GM) signals at a probe photon energy of 1.85 eV in polycrystalline pentacene TFTs. Spectroscopic analyses based on a series of μ-GMI at various photon energies reveal that two distinct effects appear, simultaneously, within the polycrystalline pentacene channel layers: Negative GM signals at 1.85 eV originate from the second-derivative-like GM spectrum which is caused by the effect of charge accumulation, whereas positive GM signals originate from the first-derivative-like GM spectrum caused by the effect of leaked gate fields. Comparisons with polycrystalline morphologies indicate that grain centers are predominated by areas with high leaked gate fields due to the low charge density, whereas grain edges are predominantly high-charge-density areas with a certain spatial extension as associated with the concentrated carrier traps. Consequently, it is reasonably understood that larger grains lead to higher device mobility, but with greater inhomogeneity in charge distribution. These findings provide a clue to understand and improve device characteristics of polycrystalline TFTs.

High performance tunnel field-effect transistor by gate and source engineering

International Nuclear Information System (INIS)

Huang, Ru; Huang, Qianqian; Chen, Shaowen; Wu, Chunlei; Wang, Jiaxin; An, Xia; Wang, Yangyuan

2014-01-01

As one of the most promising candidates for future nanoelectronic devices, tunnel field-effect transistors (TFET) can overcome the subthreshold slope (SS) limitation of MOSFET, whereas high ON-current, low OFF-current and steep switching can hardly be obtained at the same time for experimental TFETs. In this paper, we developed a new nanodevice technology based on TFET concepts. By designing the gate configuration and introducing the optimized Schottky junction, a multi-finger-gate TFET with a dopant-segregated Schottky source (mFSB-TFET) is proposed and experimentally demonstrated. A steeper SS can be achieved in the fabricated mFSB-TFET on the bulk Si substrate benefiting from the coupled quantum band-to-band tunneling (BTBT) mechanism, as well as a high I ON /I OFF ratio (∼10 7 ) at V DS  = 0.2 V without an area penalty. By compatible SOI CMOS technology, the fabricated Si mFSB-TFET device was further optimized with a high I ON /I OFF ratio of ∼10 8 and a steeper SS of over 5.5 decades of current. A minimum SS of below 60 mV dec −1 was experimentally obtained, indicating its dominant quantum BTBT mechanism for switching. (paper)

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

Science.gov (United States)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

Science.gov (United States)

Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

2018-04-01

In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

High performance top-gated ferroelectric field effect transistors based on two-dimensional ZnO nanosheets

Science.gov (United States)

Tian, Hongzheng; Wang, Xudong; Zhu, Yuankun; Liao, Lei; Wang, Xianying; Wang, Jianlu; Hu, Weida

2017-01-01

High quality ultrathin two-dimensional zinc oxide (ZnO) nanosheets (NSs) are synthesized, and the ZnO NS ferroelectric field effect transistors (FeFETs) are demonstrated based on the P(VDF-TrFE) polymer film used as the top gate insulating layer. The ZnO NSs exhibit a maximum field effect mobility of 588.9 cm2/Vs and a large transconductance of 2.5 μS due to their high crystalline quality and ultrathin two-dimensional structure. The polarization property of the P(VDF-TrFE) film is studied, and a remnant polarization of >100 μC/cm2 is achieved with a P(VDF-TrFE) thickness of 300 nm. Because of the ultrahigh remnant polarization field generated in the P(VDF-TrFE) film, the FeFETs show a large memory window of 16.9 V and a high source-drain on/off current ratio of more than 107 at zero gate voltage and a source-drain bias of 0.1 V. Furthermore, a retention time of >3000 s of the polarization state is obtained, inspiring a promising candidate for applications in data storage with non-volatile features.

Ferroelectric-gate field effect transistor memories device physics and applications

CERN Document Server

Ishiwara, Hiroshi; Okuyama, Masanori; Sakai, Shigeki; Yoon, Sung-Min

2016-01-01

This book provides comprehensive coverage of the materials characteristics, process technologies, and device operations for memory field-effect transistors employing inorganic or organic ferroelectric thin films. This transistor-type ferroelectric memory has interesting fundamental device physics and potentially large industrial impact. Among the various applications of ferroelectric thin films, the development of nonvolatile ferroelectric random access memory (FeRAM) has progressed most actively since the late 1980s and has achieved modest mass production levels for specific applications since 1995. There are two types of memory cells in ferroelectric nonvolatile memories. One is the capacitor-type FeRAM and the other is the field-effect transistor (FET)-type FeRAM. Although the FET-type FeRAM claims ultimate scalability and nondestructive readout characteristics, the capacitor-type FeRAMs have been the main interest for the major semiconductor memory companies, because the ferroelectric FET has fatal handic...

Screening-induced surface polar optical phonon scattering in dual-gated graphene field effect transistors

Energy Technology Data Exchange (ETDEWEB)

Hu, Bo, E-mail: hubo2011@semi.ac.cn

2015-03-15

The effect of surface polar optical phonons (SOs) from the dielectric layers on electron mobility in dual-gated graphene field effect transistors (GFETs) is studied theoretically. By taking into account SO scattering of electron as a main scattering mechanism, the electron mobility is calculated by the iterative solution of Boltzmann transport equation. In treating scattering with the SO modes, the dynamic dielectric screening is included and compared to the static dielectric screening and the dielectric screening in the static limit. It is found that the dynamic dielectric screening effect plays an important role in the range of low net carrier density. More importantly, in-plane acoustic phonon scattering and charged impurity scattering are also included in the total mobility for SiO{sub 2}-supported GFETs with various high-κ top-gate dielectric layers considered. The calculated total mobility results suggest both Al{sub 2}O{sub 3} and AlN are the promising candidate dielectric layers for the enhancement in room temperature mobility of graphene in the future.

A Label-Free Immunosensor for IgG Based on an Extended-Gate Type Organic Field Effect Transistor

Directory of Open Access Journals (Sweden)

Tsukuru Minamiki

2014-09-01

Full Text Available A novel biosensor for immunoglobulin G (IgG detection based on an extended-gate type organic field effect transistor (OFET has been developed that possesses an anti-IgG antibody on its extended-gate electrode and can be operated below 3 V. The titration results from the target IgG in the presence of a bovine serum albumin interferent, clearly exhibiting a negative shift in the OFET transfer curve with increasing IgG concentration. This is presumed to be due an interaction between target IgG and the immobilized anti-IgG antibody on the extended-gate electrode. As a result, a linear range from 0 to 10 µg/mL was achieved with a relatively low detection limit of 0.62 µg/mL (=4 nM. We believe that these results open up opportunities for applying extended-gate-type OFETs to immunosensing.

Performance of organic field effect transistors with high-k gate oxide after application of consecutive bias stress

Energy Technology Data Exchange (ETDEWEB)

Lee, Sunwoo; Choi, Changhwan; Lee, Kilbock [Department of Materials Science and Engineering, Hanyang University, Seoul, 133-791 (Korea, Republic of); Cho, Joong Hwee [Department of Embedded Systems Engineering,University of Incheon, Incheon 406-722 (Korea, Republic of); Ko, Ki-Young [Korea Institute of Patent Information, Seoul, 146-8 (Korea, Republic of); Ahn, Jinho, E-mail: jhahn@hanyang.ac.kr [Department of Materials Science and Engineering, Hanyang University, Seoul, 133-791 (Korea, Republic of)

2012-10-30

We report the effect of consecutive electrical stress on the performance of organic field effect transistors (OFETs). Sputtered aluminum oxide (Al{sub 2}O{sub 3}) and hafnium oxide (HfO{sub 2}) were used as gate oxide layers. After the electrical stress, the threshold voltage, which strongly depends on bulk defects, was remarkably shifted to the negative direction, while the other performance characteristics of OFETs such as on-current, transconductance and mobility, which are sensitive to interface defects, were slightly decreased. This result implies that the defects in the bulk layer are significantly affected compared to the defects in the interface layer. Thus, it is important to control the defects in the pentacene bulk layer in order to maintain the good reliabilities of pentacene devices. Those defects in HfO{sub 2} gate oxide devices were larger compared to those in Al{sub 2}O{sub 3} gate oxide devices.

Influence of the gate position on source-to-drain resistance in AlGaN/AlN/GaN heterostructure field-effect transistors

Directory of Open Access Journals (Sweden)

Yan Liu

2017-08-01

Full Text Available Using a suitable dual-gate structure, the source-to-drain resistance (RSD of AlGaN/AlN/GaN heterostructure field-effect transistor (HFET with varying gate position has been studied at room temperature. The theoretical and experimental results have revealed a dependence of RSD on the gate position. The variation of RSD with the gate position is found to stem from the polarization Coulomb field (PCF scattering. This finding is of great benefit to the optimization of the performance of AlGaN/AlN/GaN HFET. Especially, when the AlGaN/AlN/GaN HFET works as a microwave device, it is beneficial to achieve the impedance matching by designing the appropriate gate position based on PCF scattering.

Uniformity of fully gravure printed organic field-effect transistors

International Nuclear Information System (INIS)

Hambsch, M.; Reuter, K.; Stanel, M.; Schmidt, G.; Kempa, H.; Fuegmann, U.; Hahn, U.; Huebler, A.C.

2010-01-01

Fully mass-printed organic field-effect transistors were made completely by means of gravure printing. Therefore a special printing layout was developed in order to avoid register problems in print direction. Upon using this layout, contact pads for source-drain electrodes of the transistors are printed together with the gate electrodes in one and the same printing run. More than 50,000 transistors have been produced and by random tests a yield of approximately 75% has been determined. The principle suitability of the gravure printed transistors for integrated circuits has been shown by the realization of ring oscillators.

Modeling of subthreshold characteristics of short channel junctionless cylindrical surrounding-gate nanowire metal–oxide–silicon field effect transistors

International Nuclear Information System (INIS)

Jin, Xiaoshi; Liu, Xi; Lee, Jung-Hee; Lee, Jong-Ho

2014-01-01

A subthreshold model of short-channel junctionless field effect transistors with cylindrical surrounding-gate nanowire structure has been proposed. It was based on an approximated solution of two-dimensional Poisson's equation. The derivation of this model was introduced and the accuracy of the proposed models have been verified by comparison with both previous models and the SILVACO Atlas TCAD simulation results, which show good agreement. (paper)

Double-gate junctionless transistor model including short-channel effects

International Nuclear Information System (INIS)

Paz, B C; Pavanello, M A; Ávila-Herrera, F; Cerdeira, A

2015-01-01

This work presents a physically based model for double-gate junctionless transistors (JLTs), continuous in all operation regimes. To describe short-channel transistors, short-channel effects (SCEs), such as increase of the channel potential due to drain bias, carrier velocity saturation and mobility degradation due to vertical and longitudinal electric fields, are included in a previous model developed for long-channel double-gate JLTs. To validate the model, an analysis is made by using three-dimensional numerical simulations performed in a Sentaurus Device Simulator from Synopsys. Different doping concentrations, channel widths and channel lengths are considered in this work. Besides that, the series resistance influence is numerically included and validated for a wide range of source and drain extensions. In order to check if the SCEs are appropriately described, besides drain current, transconductance and output conductance characteristics, the following parameters are analyzed to demonstrate the good agreement between model and simulation and the SCEs occurrence in this technology: threshold voltage (V TH ), subthreshold slope (S) and drain induced barrier lowering. (paper)

Fluorinated copper-phthalocyanine-based n-type organic field-effect transistors with a polycarbonate gate insulator

International Nuclear Information System (INIS)

Sethuraman, Kunjithapatham; Kumar, Palanisamy; Santhakumar, Kannappan; Ochiai, Shizuyasu; Shin, Paikkyun

2012-01-01

Fluorinated copper-phthalocyanine (F 16 CuPc) thin films were prepared by using a vacuum evaporation technique and were applied to n-type organic field-effect transistors (OFETs) as active channel layers combined with a spin-coated polycarbonate thin-film gate insulator. The output characteristics of the resulting n-type OFET devices with bottom-gate/bottom-contact structures were investigated to evaluate the performances such as the field effect mobility (μ FE ), the on/off current ratio (I on/off ), and the threshold voltage (V th ). A relatively high field effect mobility of 6.0 x 10 -3 cm 2 /Vs was obtained for the n-type semiconductor under atmospheric conditions with an on/off current ratio of 1 x 10 4 and a threshold voltage of 5 V. The electron mobility of the n-type semiconductor was found to depend strongly on the growth temperature of the F 16 CuPc thin films. X-ray diffraction profiles showed that the crystallinity and the orientation of the F 16 CuPc on a polycarbonate thin film were enhanced with increasing growth temperature. Atomic force microscopy studies revealed various surface morphologies of the active layer. The field effect mobility of the F 16 CuPc-OFET was closely related to the crystallinity and the orientation of the F 16 CuPc thin film.

Interface-Dependent Effective Mobility in Graphene Field-Effect Transistors

Science.gov (United States)

Ahlberg, Patrik; Hinnemo, Malkolm; Zhang, Shi-Li; Olsson, Jörgen

2018-03-01

By pretreating the substrate of a graphene field-effect transistor (G-FET), a stable unipolar transfer characteristic, instead of the typical V-shape ambipolar behavior, has been demonstrated. This behavior is achieved through functionalization of the SiO2/Si substrate that changes the SiO2 surface from hydrophilic to hydrophobic, in combination with postdeposition of an Al2O3 film by atomic layer deposition (ALD). Consequently, the back-gated G-FET is found to have increased apparent hole mobility and suppressed apparent electron mobility. Furthermore, with addition of a top-gate electrode, the G-FET is in a double-gate configuration with independent top- or back-gate control. The observed difference in mobility is shown to also be dependent on the top-gate bias, with more pronounced effect at higher electric field. Thus, the combination of top and bottom gates allows control of the G-FET's electron and hole mobilities, i.e., of the transfer behavior. Based on these observations, it is proposed that polar ligands are introduced during the ALD step and, depending on their polarization, result in an apparent increase of the effective hole mobility and an apparent suppressed effective electron mobility.

Fabrication, electrical characterization and device simulation of vertical P3HT field-effect transistors

Directory of Open Access Journals (Sweden)

Bojian Xu

2017-12-01

Full Text Available Vertical organic field-effect transistors (VOFETs provide an advantage over lateral ones with respect to the possibility to conveniently reduce the channel length. This is beneficial for increasing both the cut-off frequency and current density in organic field-effect transistor devices. We prepared P3HT (poly[3-hexylthiophene-2,5-diyl] VOFETs with a surrounding gate electrode and gate dielectric around the vertical P3HT pillar junction. Measured output and transfer characteristics do not show a distinct gate effect, in contrast to device simulations. By introducing in the simulations an edge layer with a strongly reduced charge mobility, the gate effect is significantly reduced. We therefore propose that a damaged layer at the P3HT/dielectric interface could be the reason for the strong suppression of the gate effect. We also simulated how the gate effect depends on the device parameters. A smaller pillar diameter and a larger gate electrode-dielectric overlap both lead to better gate control. Our findings thus provide important design parameters for future VOFETs.

Insights into operation of planar tri-gate tunnel field effect transistor for dynamic memory application

Science.gov (United States)

Navlakha, Nupur; Kranti, Abhinav

2017-07-01

Insights into device physics and operation through the control of energy barriers are presented for a planar tri-gate Tunnel Field Effect Transistor (TFET) based dynamic memory. The architecture consists of a double gate (G1) at the source side and a single gate (G2) at the drain end of the silicon film. Dual gates (G1) effectively enhance the tunneling based read mechanism through the enhanced coupling and improved electrostatic control over the channel. The single gate (G2) controls the holes in the potential barrier induced through the proper selection of bias and workfunction. The results indicate that the planar tri-gate achieves optimum performance evaluated in terms of two composite metrics (M1 and M2), namely, product of (i) Sense Margin (SM) and Retention Time (RT) i.e., M1 = SM × RT and (ii) Sense Margin and Current Ratio (CR) i.e., M2 = SM × CR. The regulation of barriers created by the gates (G1 and G2) through the optimal use of device parameters leads to better performance metrics, with significant improvement at scaled lengths as compared to other tunneling based dynamic memory architectures. The investigation shows that lengths of G1, G2 and lateral spacing can be scaled down to 25 nm, 50 nm, and 30 nm, respectively, while achieving reasonable values for (M1, M2). The work demonstrates a systematic approach to showcase the advancement in TFET based Dynamic Random Access Memory (DRAM) through the use of planar tri-gate topology at a lower bias value. The concept, design, and operation of planar tri-gate architecture provide valuable viewpoints for TFET based DRAM.

Nanoscaled biological gated field effect transistors for cytogenetic analysis

DEFF Research Database (Denmark)

Kwasny, Dorota; Dimaki, Maria; Andersen, Karsten Brandt

2014-01-01

Cytogenetic analysis is the study of chromosome structure and function, and is often used in cancer diagnosis, as many chromosome abnormalities are linked to the onset of cancer. A novel label free detection method for chromosomal translocation analysis using nanoscaled field effect transistors...

Carbon nanotube feedback-gate field-effect transistor: suppressing current leakage and increasing on/off ratio.

Science.gov (United States)

Qiu, Chenguang; Zhang, Zhiyong; Zhong, Donglai; Si, Jia; Yang, Yingjun; Peng, Lian-Mao

2015-01-27

Field-effect transistors (FETs) based on moderate or large diameter carbon nanotubes (CNTs) usually suffer from ambipolar behavior, large off-state current and small current on/off ratio, which are highly undesirable for digital electronics. To overcome these problems, a feedback-gate (FBG) FET structure is designed and tested. This FBG FET differs from normal top-gate FET by an extra feedback-gate, which is connected directly to the drain electrode of the FET. It is demonstrated that a FBG FET based on a semiconducting CNT with a diameter of 1.5 nm may exhibit low off-state current of about 1 × 10(-13) A, high current on/off ratio of larger than 1 × 10(8), negligible drain-induced off-state leakage current, and good subthreshold swing of 75 mV/DEC even at large source-drain bias and room temperature. The FBG structure is promising for CNT FETs to meet the standard for low-static-power logic electronics applications, and could also be utilized for building FETs using other small band gap semiconductors to suppress leakage current.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

Science.gov (United States)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

Science.gov (United States)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

Tunable SnSe2 /WSe2 Heterostructure Tunneling Field Effect Transistor.

Science.gov (United States)

Yan, Xiao; Liu, Chunsen; Li, Chao; Bao, Wenzhong; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2017-09-01

The burgeoning 2D semiconductors can maintain excellent device electrostatics with an ultranarrow channel length and can realize tunneling by electrostatic gating to avoid deprivation of band-edge sharpness resulting from chemical doping, which make them perfect candidates for tunneling field effect transistors. Here this study presents SnSe 2 /WSe 2 van der Waals heterostructures with SnSe 2 as the p-layer and WSe 2 as the n-layer. The energy band alignment changes from a staggered gap band offset (type-II) to a broken gap (type-III) when changing the negative back-gate voltage to positive, resulting in the device operating as a rectifier diode (rectification ratio ~10 4 ) or an n-type tunneling field effect transistor, respectively. A steep average subthreshold swing of 80 mV dec -1 for exceeding two decades of drain current with a minimum of 37 mV dec -1 at room temperature is observed, and an evident trend toward negative differential resistance is also accomplished for the tunneling field effect transistor due to the high gate efficiency of 0.36 for single gate devices. The I ON /I OFF ratio of the transfer characteristics is >10 6 , accompanying a high ON current >10 -5 A. This work presents original phenomena of multilayer 2D van der Waals heterostructures which can be applied to low-power consumption devices. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Charge-density depinning at metal contacts of graphene field-effect transistors

OpenAIRE

Nouchi, Ryo; Tanigaki, Katsumi

2010-01-01

An anomalous distortion is often observed in the transfer characteristics of graphene field-effect transistors. We fabricate graphene transistors with ferromagnetic metal electrodes, which reproducibly display distorted transfer characteristics, and show that the distortion is caused by metal-graphene contacts with no charge-density pinning effect. The pinning effect, where the gate voltage cannot tune the charge density of graphene at the metal electrodes, has been experimentally observed; h...

Si/Ge hetero-structure nanotube tunnel field effect transistor

KAUST Repository

Hanna, A. N.

2015-01-07

We discuss the physics of conventional channel material (silicon/germanium hetero-structure) based transistor topology mainly core/shell (inner/outer) gated nanotube vs. gate-all-around nanowire architecture for tunnel field effect transistor application. We show that nanotube topology can result in higher performance through higher normalized current when compared to nanowire architecture at Vdd-=-1-V due to the availability of larger tunneling cross section and lower Shockley-Reed-Hall recombination. Both architectures are able to achieve sub 60-mV/dec performance for more than five orders of magnitude of drain current. This enables the nanotube configuration achieving performance same as the nanowire architecture even when Vdd is scaled down to 0.5-V.

Si/Ge hetero-structure nanotube tunnel field effect transistor

KAUST Repository

Hanna, A. N.; Hussain, Muhammad Mustafa

2015-01-01

We discuss the physics of conventional channel material (silicon/germanium hetero-structure) based transistor topology mainly core/shell (inner/outer) gated nanotube vs. gate-all-around nanowire architecture for tunnel field effect transistor application. We show that nanotube topology can result in higher performance through higher normalized current when compared to nanowire architecture at Vdd-=-1-V due to the availability of larger tunneling cross section and lower Shockley-Reed-Hall recombination. Both architectures are able to achieve sub 60-mV/dec performance for more than five orders of magnitude of drain current. This enables the nanotube configuration achieving performance same as the nanowire architecture even when Vdd is scaled down to 0.5-V.

High performance organic field-effect transistors with ultra-thin HfO2 gate insulator deposited directly onto the organic semiconductor

International Nuclear Information System (INIS)

Ono, S.; Häusermann, R.; Chiba, D.; Shimamura, K.; Ono, T.; Batlogg, B.

2014-01-01

We have produced stable organic field-effect transistors (OFETs) with an ultra-thin HfO 2 gate insulator deposited directly on top of rubrene single crystals by atomic layer deposition (ALD). We find that ALD is a gentle deposition process to grow thin films without damaging rubrene single crystals, as results these devices have a negligibly small threshold voltage and are very stable against gate-bias-stress, and the mobility exceeds 1 cm 2 /V s. Moreover, the devices show very little degradation even when kept in air for more than 2 months. These results demonstrate thin HfO 2 layers deposited by ALD to be well suited as high capacitance gate dielectrics in OFETs operating at small gate voltage. In addition, the dielectric layer acts as an effective passivation layer to protect the organic semiconductor

Improved transfer of graphene for gated Schottky-junction, vertical, organic, field-effect transistors.

Science.gov (United States)

Lemaitre, Maxime G; Donoghue, Evan P; McCarthy, Mitchell A; Liu, Bo; Tongay, Sefaattin; Gila, Brent; Kumar, Purushottam; Singh, Rajiv K; Appleton, Bill R; Rinzler, Andrew G

2012-10-23

An improved process for graphene transfer was used to demonstrate high performance graphene enabled vertical organic field effect transistors (G-VFETs). The process reduces disorder and eliminates the polymeric residue that typically plagues transferred films. The method also allows for purposely creating pores in the graphene of a controlled areal density. Transconductance observed in G-VFETs fabricated with a continuous (pore-free) graphene source electrode is attributed to modulation of the contact barrier height between the graphene and organic semiconductor due to a gate field induced Fermi level shift in the low density of electronic-states graphene electrode. Pores introduced in the graphene source electrode are shown to boost the G-VFET performance, which scales with the areal pore density taking advantage of both barrier height lowering and tunnel barrier thinning. Devices with areal pore densities of 20% exhibit on/off ratios and output current densities exceeding 10(6) and 200 mA/cm(2), respectively, at drain voltages below 5 V.

Solvothermal synthesis of gallium-indium-zinc-oxide nanoparticles for electrolyte-gated transistors.

Science.gov (United States)

Santos, Lídia; Nunes, Daniela; Calmeiro, Tomás; Branquinho, Rita; Salgueiro, Daniela; Barquinha, Pedro; Pereira, Luís; Martins, Rodrigo; Fortunato, Elvira

2015-01-14

Solution-processed field-effect transistors are strategic building blocks when considering low-cost sustainable flexible electronics. Nevertheless, some challenges (e.g., processing temperature, reliability, reproducibility in large areas, and cost effectiveness) are requirements that must be surpassed in order to achieve high-performance transistors. The present work reports electrolyte-gated transistors using as channel layer gallium-indium-zinc-oxide nanoparticles produced by solvothermal synthesis combined with a solid-state electrolyte based on aqueous dispersions of vinyl acetate stabilized with cellulose derivatives, acrylic acid ester in styrene and lithium perchlorate. The devices fabricated using this approach display a ION/IOFF up to 1 × 10(6), threshold voltage (VTh) of 0.3-1.9 V, and mobility up to 1 cm(2)/(V s), as a function of gallium-indium-zinc-oxide ink formulation and two different annealing temperatures. These results validates the usage of electrolyte-gated transistors as a viable and promising alternative for nanoparticle based semiconductor devices as the electrolyte improves the interface and promotes a more efficient step coverage of the channel layer, reducing the operating voltage when compared with conventional dielectrics gating. Moreover, it is shown that by controlling the applied gate potential, the operation mechanism of the electrolyte-gated transistors can be modified from electric double layer to electrochemical doping.

Liquid–Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing

KAUST Repository

Zhang, Yu

2017-10-17

Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid–liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the “sensing channel” can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

Liquid-Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing.

Science.gov (United States)

Zhang, Yu; Li, Jun; Li, Rui; Sbircea, Dan-Tiberiu; Giovannitti, Alexander; Xu, Junling; Xu, Huihua; Zhou, Guodong; Bian, Liming; McCulloch, Iain; Zhao, Ni

2017-11-08

Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid-liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the "sensing channel" can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons.

Science.gov (United States)

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; Shi, Wu; Lee, Kyunghoon; Wu, Shuang; Yong Choi, Byung; Braganza, Rohit; Lear, Jordan; Kau, Nicholas; Choi, Wonwoo; Chen, Chen; Pedramrazi, Zahra; Dumslaff, Tim; Narita, Akimitsu; Feng, Xinliang; Müllen, Klaus; Fischer, Felix; Zettl, Alex; Ruffieux, Pascal; Yablonovitch, Eli; Crommie, Michael; Fasel, Roman; Bokor, Jeffrey

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch  ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on  > 1 μA at V d  = -1 V) and high I on /I off  ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.Graphene nanoribbons show promise for high-performance field-effect transistors, however they often suffer from short lengths and wide band gaps. Here, the authors use a bottom-up synthesis approach to fabricate 9- and 13-atom wide ribbons, enabling short-channel transistors with 10 5 on-off current ratio.

Performance evaluation of parallel electric field tunnel field-effect transistor by a distributed-element circuit model

Science.gov (United States)

Morita, Yukinori; Mori, Takahiro; Migita, Shinji; Mizubayashi, Wataru; Tanabe, Akihito; Fukuda, Koichi; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shin-ichi; Liu, Yongxun; Masahara, Meishoku; Ota, Hiroyuki

2014-12-01

The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field was evaluated. The TFET was fabricated by inserting an epitaxially-grown parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit of the drain current caused by the self-voltage-drop effect in the ultrathin channel layer.

100-nm gate lithography for double-gate transistors

Science.gov (United States)

Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

2001-09-01

The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

Cylindrical Field Effect Transistor: A Full Volume Inversion Device

KAUST Repository

Fahad, Hossain M.

2010-12-01

The increasing demand for high performance as well as low standby power devices has been the main reason for the aggressive scaling of conventional CMOS transistors. Current devices are at the 32nm technology node. However, due to physical limitations as well as increase in short-channel effects, leakage, power dissipation, this scaling trend cannot continue and will eventually hit a barrier. In order to overcome this, alternate device topologies have to be considered altogether. Extensive research on ultra thin body double gate FETs and gate all around nanowire FETs has shown a lot of promise. Under strong inversion, these devices have demonstrated increased performance over their bulk counterparts. This is mainly attributed to full carrier inversion in the body. However, these devices are still limited by lithographic and processing challenges making them unsuitable for commercial production. This thesis explores a unique device structure called the CFET (Cylindrical Field Effect Transistors) which also like the above, relies on complete inversion of carriers in the body/bulk. Using dual gates; an outer and an inner gate, full-volume inversion is possible with benefits such as enhanced drive currents, high Ion/Ioff ratios and reduced short channel effects.

Graphene-based field effect transistor in two-dimensional paper networks

Energy Technology Data Exchange (ETDEWEB)

Cagang, Aldrine Abenoja; Abidi, Irfan Haider; Tyagi, Abhishek [Department of Chemical and Biomolecular Engineering, Hong Kong University of Science and Technology, Clear Water Bay (Hong Kong); Hu, Jie; Xu, Feng [Bioinspired Engineering and Biomechanics Center (BEBC), Xi' an Jiaotong University, Xi' an 710049 (China); The Key Laboratory of Biomedical Information Engineering of Ministry of Education, School of Life Science and Technology, Xi' an Jiaotong University, Xi' an 710049 (China); Lu, Tian Jian [Bioinspired Engineering and Biomechanics Center (BEBC), Xi' an Jiaotong University, Xi' an 710049 (China); Luo, Zhengtang, E-mail: keztluo@ust.hk [Department of Chemical and Biomolecular Engineering, Hong Kong University of Science and Technology, Clear Water Bay (Hong Kong)

2016-04-21

We demonstrate the fabrication of a graphene-based field effect transistor (GFET) incorporated in a two-dimensional paper network format (2DPNs). Paper serves as both a gate dielectric and an easy-to-fabricate vessel for holding the solution with the target molecules in question. The choice of paper enables a simpler alternative approach to the construction of a GFET device. The fabricated device is shown to behave similarly to a solution-gated GFET device with electron and hole mobilities of ∼1256 cm{sup 2} V{sup −1} s{sup −1} and ∼2298 cm{sup 2} V{sup −1} s{sup −1} respectively and a Dirac point around ∼1 V. When using solutions of ssDNA and glucose it was found that the added molecules induce negative electrolytic gating effects shifting the conductance minimum to the right, concurrent with increasing carrier concentrations which results to an observed increase in current response correlated to the concentration of the solution used. - Highlights: • A graphene-based field effect transistor sensor was fabricated for two-dimensional paper network formats. • The constructed GFET on 2DPN was shown to behave similarly to solution-gated GFETs. • Electrolyte gating effects have more prominent effect over adsorption effects on the behavior of the device. • The GFET incorporated on 2DPN was shown to yield linear response to presence of glucose and ssDNA soaked inside the paper.

Graphene-based field effect transistor in two-dimensional paper networks

International Nuclear Information System (INIS)

Cagang, Aldrine Abenoja; Abidi, Irfan Haider; Tyagi, Abhishek; Hu, Jie; Xu, Feng; Lu, Tian Jian; Luo, Zhengtang

2016-01-01

We demonstrate the fabrication of a graphene-based field effect transistor (GFET) incorporated in a two-dimensional paper network format (2DPNs). Paper serves as both a gate dielectric and an easy-to-fabricate vessel for holding the solution with the target molecules in question. The choice of paper enables a simpler alternative approach to the construction of a GFET device. The fabricated device is shown to behave similarly to a solution-gated GFET device with electron and hole mobilities of ∼1256 cm 2  V −1  s −1 and ∼2298 cm 2  V −1  s −1 respectively and a Dirac point around ∼1 V. When using solutions of ssDNA and glucose it was found that the added molecules induce negative electrolytic gating effects shifting the conductance minimum to the right, concurrent with increasing carrier concentrations which results to an observed increase in current response correlated to the concentration of the solution used. - Highlights: • A graphene-based field effect transistor sensor was fabricated for two-dimensional paper network formats. • The constructed GFET on 2DPN was shown to behave similarly to solution-gated GFETs. • Electrolyte gating effects have more prominent effect over adsorption effects on the behavior of the device. • The GFET incorporated on 2DPN was shown to yield linear response to presence of glucose and ssDNA soaked inside the paper.

Modeling of strain effects on the device behaviors of ferroelectric memory field-effect transistors

International Nuclear Information System (INIS)

Yang, Feng; Hu, Guangda; Wu, Weibing; Yang, Changhong; Wu, Haitao; Tang, Minghua

2013-01-01

The influence of strains on the channel current–gate voltage behaviors and memory windows of ferroelectric memory field-effect transistors (FeMFETs) were studied using an improved model based on the Landau–Devonshire theory. ‘Channel potential–gate voltage’ ferroelectric polarization and silicon surface potential diagrams were constructed for strained single-domain BaTiO 3 FeMFETs. The compressive strains can increase (or decrease) the amplitude of transistor currents and enlarge memory windows. However, tensile strains only decrease the maximum value of transistor currents and compress memory windows. Mismatch strains were found to have a significant influence on the electrical behaviors of the devices, therefore, they must be considered in FeMFET device designing. (fast track communication)

Probing organic field effect transistors in situ during operation using SFG.

Science.gov (United States)

Ye, Hongke; Abu-Akeel, Ashraf; Huang, Jia; Katz, Howard E; Gracias, David H

2006-05-24

In this communication, we report results obtained using surface-sensitive IR+Visible Sum Frequency Generation (SFG) nonlinear optical spectroscopy on interfaces of organic field effect transistors during operation. We observe remarkable correlations between trends in the surface vibrational spectra and electrical properties of the transistor, with changes in gate voltage (VG). These results suggest that field effects on electronic conduction in thin film organic semiconductor devices are correlated to interfacial nonlinear optical characteristics and point to the possibility of using SFG spectroscopy to monitor electronic properties of OFETs.

Problems of noise modeling in the presence of total current branching in high electron mobility transistor and field-effect transistor channels

International Nuclear Information System (INIS)

Shiktorov, P; Starikov, E; Gružinskis, V; Varani, L; Sabatini, G; Marinchio, H; Reggiani, L

2009-01-01

In the framework of analytical and hydrodynamic models for the description of carrier transport and noise in high electron mobility transistor/field-effect transistor channels the main features of the intrinsic noise of transistors are investigated under continuous branching of the current between channel and gate. It is shown that the current-noise and voltage-noise spectra at the transistor terminals contain an excess noise related to thermal excitation of plasma wave modes in the dielectric layer between the channel and gate. It is found that the set of modes of excited plasma waves can be governed by the external embedding circuits, thus violating a universal description of noise in terms of Norton and Thevenin noise generators

An Al₂O₃ Gating Substrate for the Greater Performance of Field Effect Transistors Based on Two-Dimensional Materials.

Science.gov (United States)

Yang, Hang; Qin, Shiqiao; Zheng, Xiaoming; Wang, Guang; Tan, Yuan; Peng, Gang; Zhang, Xueao

2017-09-22

We fabricated 70 nm Al₂O₃ gated field effect transistors based on two-dimensional (2D) materials and characterized their optical and electrical properties. Studies show that the optical contrast of monolayer graphene on an Al₂O₃/Si substrate is superior to that on a traditional 300 nm SiO₂/Si substrate (2.4 times). Significantly, the transconductance of monolayer graphene transistors on the Al₂O₃/Si substrate shows an approximately 10-fold increase, due to a smaller dielectric thickness and a higher dielectric constant. Furthermore, this substrate is also suitable for other 2D materials, such as WS₂, and can enhance the transconductance remarkably by 61.3 times. These results demonstrate a new and ideal substrate for the fabrication of 2D materials-based electronic logic devices.

High Sensitivity pH Sensor Based on Porous Silicon (PSi) Extended Gate Field-Effect Transistor.

Science.gov (United States)

Al-Hardan, Naif H; Abdul Hamid, Muhammad Azmi; Ahmed, Naser M; Jalar, Azman; Shamsudin, Roslinda; Othman, Norinsan Kamil; Kar Keng, Lim; Chiu, Weesiong; Al-Rawi, Hamzah N

2016-06-07

In this study, porous silicon (PSi) was prepared and tested as an extended gate field-effect transistor (EGFET) for pH sensing. The prepared PSi has pore sizes in the range of 500 to 750 nm with a depth of approximately 42 µm. The results of testing PSi for hydrogen ion sensing in different pH buffer solutions reveal that the PSi has a sensitivity value of 66 mV/pH that is considered a super Nernstian value. The sensor considers stability to be in the pH range of 2 to 12. The hysteresis values of the prepared PSi sensor were approximately 8.2 and 10.5 mV in the low and high pH loop, respectively. The result of this study reveals a promising application of PSi in the field for detecting hydrogen ions in different solutions.

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors

Directory of Open Access Journals (Sweden)

Nandu B Chaure, Andrew N Cammidge, Isabelle Chambrier, Michael J Cook, Markys G Cain, Craig E Murphy, Chandana Pal and Asim K Ray

2011-01-01

Full Text Available Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl copper phthalocyanine (CuPc6 were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO2 as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS resulted in values of 4×10−2 cm2 V−1 s−1 and 106 for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones.

Benzocyclobutene (BCB) Polymer as Amphibious Buffer Layer for Graphene Field-Effect Transistor.

Science.gov (United States)

Wu, Yun; Zou, Jianjun; Huo, Shuai; Lu, Haiyan; Kong, Yuecan; Chen, Tangshen; Wu, Wei; Xu, Jingxia

2015-08-01

Owing to the scattering and trapping effects, the interfaces of dielectric/graphene or substrate/graphene can tailor the performance of field-effect transistor (FET). In this letter, the polymer of benzocyclobutene (BCB) was used as an amphibious buffer layer and located at between the layers of substrate and graphene and between the layers of dielectric and graphene. Interestingly, with the help of nonpolar and hydrophobic BCB buffer layer, the large-scale top-gated, chemical vapor deposited (CVD) graphene transistors was prepared on Si/SiO2 substrate, its cutoff frequency (fT) and the maximum cutoff frequency (fmax) of the graphene field-effect transistor (GFET) can be reached at 12 GHz and 11 GHz, respectively.

Simulation of 50-nm Gate Graphene Nanoribbon Transistors

Directory of Open Access Journals (Sweden)

Cedric Nanmeni Bondja

2016-01-01

Full Text Available An approach to simulate the steady-state and small-signal behavior of GNR MOSFETs (graphene nanoribbon metal-semiconductor-oxide field-effect transistor is presented. GNR material parameters and a method to account for the density of states of one-dimensional systems like GNRs are implemented in a commercial device simulator. This modified tool is used to calculate the current-voltage characteristics as well the cutoff frequency fT and the maximum frequency of oscillation fmax of GNR MOSFETs. Exemplarily, we consider 50-nm gate GNR MOSFETs with N = 7 armchair GNR channels and examine two transistor configurations. The first configuration is a simplified MOSFET structure with a single GNR channel as usually studied by other groups. Furthermore, and for the first time in the literature, we study in detail a transistor structure with multiple parallel GNR channels and interribbon gates. It is shown that the calculated fT of GNR MOSFETs is significantly lower than that of GFETs (FET with gapless large-area graphene channel with comparable gate length due to the mobility degradation in GNRs. On the other hand, GNR MOSFETs show much higher fmax compared to experimental GFETs due the semiconducting nature of the GNR channels and the resulting better saturation of the drain current. Finally, it is shown that the gate control in FETs with multiple parallel GNR channels is improved while the cutoff frequency is degraded compared to single-channel GNR MOSFETs due to parasitic capacitances of the interribbon gates.

New membrane materials for potassium-selective ion-sensitive field-effect transistors

NARCIS (Netherlands)

van der Wal, P.D.; van der Wal, Peter D.; Skowronska-Ptasinska, Maria; van den Berg, Albert; Bergveld, Piet; Sudholter, Ernst; Sudholter, Ernst J.R.; Reinhoudt, David

1990-01-01

Several polymeric materials were studied as membrane materials for potassium-selective ion-sensitive field-effect transistors (ISFETs) to overcome the problems related with the use of conventional plasticized poly(vinyl chloride) membranes casted on ISFET gate surfaces. Several acrylate materials,

Performance and Design Considerations of a Novel Dual-Material Gate Carbon Nanotube Field-Effect Transistors: Nonequilibrium Green's Function Approach

Science.gov (United States)

Arefinia, Zahra; Orouji, Ali A.

2009-02-01

The concept of dual-material gate (DMG) is applied to the carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions, and the features exhibited by the resulting new structure, i.e., the DMG-CNTFET structure, have been examined for the first time by developing a two-dimensional (2D) full quantum simulation. The simulations have been done by the self-consistent solution of 2D Poisson-Schrödinger equations, within the nonequilibrium Green's function (NEGF) formalism. The results show DMG-CNTFET decreases significantly leakage current and drain conductance and increases on-off current ratio and voltage gain as compared to the single material gate counterparts CNTFET. It is seen that short channel effects in this structure are suppressed because of the perceivable step in the surface potential profile, which screens the drain potential. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate metals. Therefore, this work provides an incentive for further experimental exploration.

Ambipolar transport of silver nanoparticles decorated graphene oxide field effect transistors

Science.gov (United States)

Sarkar, Kalyan Jyoti; Sarkar, K.; Pal, B.; Kumar, Aparabal; Das, Anish; Banerji, P.

2018-05-01

In this article, we report ambipolar field effect transistor (FET) by using graphene oxide (GO) as a gate dielectric material for silver nanoparticles (AgNPs) decorated GO channel layer. GO was synthesized by Hummers' method. The AgNPs were prepared via photochemical reduction of silver nitrate solution by using monoethanolamine as a reducing agent. Morphological properties of channel layer were characterized by Field Effect Scanning Electron Microscopy (FESEM). Fourier Transform Infrared Spectroscopy (FTIR) was carried out to characterize GO thin film. For device fabrication gold (Au) was deposited as source-drain contact and aluminum (Al) was taken as bottom contact. Electrical measurements were performed by back gate configuration. Ambipolar transport behavior was explained from transfer characteristics. A maximum electron mobiliy of 6.65 cm2/Vs and a hole mobility of 2.46 cm2/Vs were extracted from the transfer characteristics. These results suggest that GO is a potential candidate as a gate dielectric material for thin film transistor applications and also provides new insights in GO based research.

Revealing Buried Interfaces to Understand the Origins of Threshold Voltage Shifts in Organic Field-Effect Transistors

NARCIS (Netherlands)

Mathijssen, Simon G. J.; Spijkman, Mark-Jan; Andringa, Anne-Marije; van Hal, Paul A.; McCulloch, Iain; Kemerink, Martijn; Janssen, Rene A. J.; de Leeuw, Dago M.

2010-01-01

The semiconductor of an organic field-effect transistor is stripped with adhesive tape, yielding an exposed gate dielectric, accessible for various characterization techniques. By using scanning Kelvin probe microscopy we reveal that trapped charges after gate bias stress are located at the gate

Piezoelectric potential gated field-effect transistor based on a free-standing ZnO wire.

Science.gov (United States)

Fei, Peng; Yeh, Ping-Hung; Zhou, Jun; Xu, Sheng; Gao, Yifan; Song, Jinhui; Gu, Yudong; Huang, Yanyi; Wang, Zhong Lin

2009-10-01

We report an external force triggered field-effect transistor based on a free-standing piezoelectric fine wire (PFW). The device consists of an Ag source electrode and an Au drain electrode at two ends of a ZnO PFW, which were separated by an insulating polydimethylsiloxane (PDMS) thin layer. The working principle of the sensor is proposed based on the piezoelectric potential gating effect. Once subjected to a mechanical impact, the bent ZnO PFW cantilever creates a piezoelectric potential distribution across it width at its root and simultaneously produces a local reverse depletion layer with much higher donor concentration than normal, which can dramatically change the current flowing from the source electrode to drain electrode when the device is under a fixed voltage bias. Due to the free-standing structure of the sensor device, it has a prompt response time less than 20 ms and quite high and stable sensitivity of 2%/microN. The effect from contact resistance has been ruled out.

Transfer-free graphene synthesis on sapphire by catalyst metal agglomeration technique and demonstration of top-gate field-effect transistors

International Nuclear Information System (INIS)

Miyoshi, Makoto; Arima, Yukinori; Kubo, Toshiharu; Egawa, Takashi; Mizuno, Masaya; Soga, Tetsuo

2015-01-01

Transfer-free graphene synthesis was performed on sapphire substrates by using the catalyst metal agglomeration technique, and the graphene film quality was compared to that synthesized on sputtered SiO 2 /Si substrates. Raman scattering measurements indicated that the graphene film on sapphire has better structural qualities than that on sputtered SiO 2 /Si substrates. The cross-sectional transmission microscopic study also revealed that the film flatness was drastically improved by using sapphire substrates instead of sputtered SiO 2 /Si substrates. These quality improvements seemed to be due the chemical and thermal stabilities of sapphire. Top-gate field-effect transistors were fabricated using the graphene films on sapphire, and it was confirmed that their drain current can be modulated with applied gate voltages. The maximum field-effect mobilities were estimated to be 720 cm 2 /V s for electrons and 880 cm 2 /V s for holes, respectively

Transfer-free graphene synthesis on sapphire by catalyst metal agglomeration technique and demonstration of top-gate field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Miyoshi, Makoto, E-mail: miyoshi.makoto@nitech.ac.jp; Arima, Yukinori; Kubo, Toshiharu; Egawa, Takashi [Research Center for Nano Device and Advanced Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan); Mizuno, Masaya [Research Center for Nano Device and Advanced Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan); Department of Frontier Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan); Soga, Tetsuo [Department of Frontier Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan)

2015-08-17

Transfer-free graphene synthesis was performed on sapphire substrates by using the catalyst metal agglomeration technique, and the graphene film quality was compared to that synthesized on sputtered SiO{sub 2}/Si substrates. Raman scattering measurements indicated that the graphene film on sapphire has better structural qualities than that on sputtered SiO{sub 2}/Si substrates. The cross-sectional transmission microscopic study also revealed that the film flatness was drastically improved by using sapphire substrates instead of sputtered SiO{sub 2}/Si substrates. These quality improvements seemed to be due the chemical and thermal stabilities of sapphire. Top-gate field-effect transistors were fabricated using the graphene films on sapphire, and it was confirmed that their drain current can be modulated with applied gate voltages. The maximum field-effect mobilities were estimated to be 720 cm{sup 2}/V s for electrons and 880 cm{sup 2}/V s for holes, respectively.

Graphene field effect transistors with niobium contacts and asymmetric transfer characteristics

International Nuclear Information System (INIS)

Bartolomeo, Antonio Di; Romeo, Francesco; Sabatino, Paolo; Carapella, Giovanni; Iemmo, Laura; Giubileo, Filippo; Schroeder, Thomas; Lupina, Grzegorz

2015-01-01

We fabricate back-gated field effect transistors using niobium electrodes on mechanically exfoliated monolayer graphene and perform electrical characterization in the pressure range from atmospheric down to 10 −4 mbar. We study the effect of room temperature vacuum degassing and report asymmetric transfer characteristics with a resistance plateau in the n-branch. We show that weakly chemisorbed Nb acts as p-dopant on graphene and explain the transistor characteristics by Nb/graphene interaction with unpinned Fermi level at the interface. (paper)

An All-Solid-State pH Sensor Employing Fluorine-Terminated Polycrystalline Boron-Doped Diamond as a pH-Insensitive Solution-Gate Field-Effect Transistor.

Science.gov (United States)

Shintani, Yukihiro; Kobayashi, Mikinori; Kawarada, Hiroshi

2017-05-05

A fluorine-terminated polycrystalline boron-doped diamond surface is successfully employed as a pH-insensitive SGFET (solution-gate field-effect transistor) for an all-solid-state pH sensor. The fluorinated polycrystalline boron-doped diamond (BDD) channel possesses a pH-insensitivity of less than 3mV/pH compared with a pH-sensitive oxygenated channel. With differential FET (field-effect transistor) sensing, a sensitivity of 27 mv/pH was obtained in the pH range of 2-10; therefore, it demonstrated excellent performance for an all-solid-state pH sensor with a pH-sensitive oxygen-terminated polycrystalline BDD SGFET and a platinum quasi-reference electrode, respectively.

High Sensitivity pH Sensor Based on Porous Silicon (PSi Extended Gate Field-Effect Transistor

Directory of Open Access Journals (Sweden)

Naif H. Al-Hardan

2016-06-01

Full Text Available In this study, porous silicon (PSi was prepared and tested as an extended gate field-effect transistor (EGFET for pH sensing. The prepared PSi has pore sizes in the range of 500 to 750 nm with a depth of approximately 42 µm. The results of testing PSi for hydrogen ion sensing in different pH buffer solutions reveal that the PSi has a sensitivity value of 66 mV/pH that is considered a super Nernstian value. The sensor considers stability to be in the pH range of 2 to 12. The hysteresis values of the prepared PSi sensor were approximately 8.2 and 10.5 mV in the low and high pH loop, respectively. The result of this study reveals a promising application of PSi in the field for detecting hydrogen ions in different solutions.

Low Temperature Noise and Electrical Characterization of the Company Heterojunction Field-Effect Transistor

Science.gov (United States)

Cunningham, Thomas J.; Gee, Russell C.; Fossum, Eric R.; Baier, Steven M.

1993-01-01

This paper discusses the electrical properties of the complementary heterojunction field-effect transistor (CHFET) at 4K, including the gate leakage current, the subthreshold transconductance, and the input-referred noise voltage.

Transport and performance of a gate all around InAs nanowire transistor

International Nuclear Information System (INIS)

Alam, Khairul

2009-01-01

The transport physics and performance metrics of a gate all around an InAs nanowire transistor are studied using a three-dimensional quantum simulation. The transistor action of an InAs nanowire transistor occurs by modulating the transmission coefficient of the device. This action is different from a conventional metal-oxide-semiconductor field effect transistor, where the transistor action occurs by modulating the charge in the channel. The device has 82% tunneling current in the off-state and 81% thermal current in the on-state. The two current components become equal at a gate bias at which an approximate source-channel flat-band condition is achieved. Prior to this gate bias, the tunneling current dominates and the thermal current dominates beyond it. The device has an on/off current ratio of 7.84 × 10 5 and an inverse subthreshold slope of 63 mV dec −1 . The transistor operates in the quantum capacitance limit with a normalized transconductance value of 14.43 mS µm −1 , an intrinsic switching delay of 90.1675 fs, and an intrinsic unity current gain frequency of 6.8697 THz

Low-power bacteriorhodopsin-silicon n-channel metal-oxide field-effect transistor photoreceiver.

Science.gov (United States)

Shin, Jonghyun; Bhattacharya, Pallab; Yuan, Hao-Chih; Ma, Zhenqiang; Váró, György

2007-03-01

A bacteriorhodopsin (bR)-silicon n-channel metal-oxide field-effect transistor (NMOSFET) monolithically integrated photoreceiver is demonstrated. The bR film is selectively formed on an external gate electrode of the transistor by electrophoretic deposition. A modified biasing circuit is incorporated, which helps to match the resistance of the bR film to the input impedance of the NMOSFET and to shift the operating point of the transistor to coincide with the maximum gain. The photoreceiver exhibits a responsivity of 4.7 mA/W.

Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

International Nuclear Information System (INIS)

Ghosh, Bahniman; Mondal, Partha; Akram, M. W.; Bal, Punyasloka; Salimath, Akshay Kumar

2014-01-01

We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel. These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n–p–n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability. (semiconductor devices)

SiC Optically Modulated Field-Effect Transistor

Science.gov (United States)

Tabib-Azar, Massood

2009-01-01

An optically modulated field-effect transistor (OFET) based on a silicon carbide junction field-effect transistor (JFET) is under study as, potentially, a prototype of devices that could be useful for detecting ultraviolet light. The SiC OFET is an experimental device that is one of several devices, including commercial and experimental photodiodes, that were initially evaluated as detectors of ultraviolet light from combustion and that could be incorporated into SiC integrated circuits to be designed to function as combustion sensors. The ultraviolet-detection sensitivity of the photodiodes was found to be less than desired, such that it would be necessary to process their outputs using high-gain amplification circuitry. On the other hand, in principle, the function of the OFET could be characterized as a combination of detection and amplification. In effect, its sensitivity could be considerably greater than that of a photodiode, such that the need for amplification external to the photodetector could be reduced or eliminated. The experimental SiC OFET was made by processes similar to JFET-fabrication processes developed at Glenn Research Center. The gate of the OFET is very long, wide, and thin, relative to the gates of typical prior SiC JFETs. Unlike in prior SiC FETs, the gate is almost completely transparent to near-ultraviolet and visible light. More specifically: The OFET includes a p+ gate layer less than 1/4 m thick, through which photons can be transported efficiently to the p+/p body interface. The gate is relatively long and wide (about 0.5 by 0.5 mm), such that holes generated at the body interface form a depletion layer that modulates the conductivity of the channel between the drain and the source. The exact physical mechanism of modulation of conductivity is a subject of continuing research. It is known that injection of minority charge carriers (in this case, holes) at the interface exerts a strong effect on the channel, resulting in amplification

Influence of the semiconductor oxidation potential on the operational stability of organic field-effect transistors

NARCIS (Netherlands)

Sharma, A.; Mathijssen, S.G.J.; Bobbert, P.A.; Leeuw, de D.M.

2011-01-01

During prolonged application of a gate bias, organic field-effect transistors show a gradual shift of the threshold voltage towards the applied gate bias voltage. The shift follows a stretched-exponential time dependence governed by a relaxation time. Here, we show that a thermodynamic analysis

A novel gate and drain engineered charge plasma tunnel field-effect transistor for low sub-threshold swing and ambipolar nature

Science.gov (United States)

Yadav, Dharmendra Singh; Raad, Bhagwan Ram; Sharma, Dheeraj

2016-12-01

In this paper, we focus on the improvement of figures of merit for charge plasma based tunnel field-effect transistor (TFET) in terms of ON-state current, threshold voltage, sub-threshold swing, ambipolar nature, and gate to drain capacitance which provides better channel controlling of the device with improved high frequency response at ultra-low supply voltages. Regarding this, we simultaneously employ work function engineering on the drain and gate electrode of the charge plasma TFET. The use of gate work function engineering modulates the barrier on the source/channel interface leads to improvement in the ON-state current, threshold voltage, and sub-threshold swing. Apart from this, for the first time use of work function engineering on the drain electrode increases the tunneling barrier for the flow of holes on the drain/channel interface, it results into suppression of ambipolar behavior. The lowering of gate to drain capacitance therefore enhanced high frequency parameters. Whereas, the presence of dual work functionality at the gate electrode and over the drain region improves the overall performance of the charge plasma based TFET.

Organic tunnel field effect transistors

KAUST Repository

Tietze, Max Lutz

2017-06-29

Various examples are provided for organic tunnel field effect transistors (OTFET), and methods thereof. In one example, an OTFET includes a first intrinsic layer (i-layer) of organic semiconductor material disposed over a gate insulating layer; source (or drain) contact stacks disposed on portions of the first i-layer; a second i-layer of organic semiconductor material disposed on the first i-layer surrounding the source (or drain) contact stacks; an n-doped organic semiconductor layer disposed on the second i-layer; and a drain (or source) contact layer disposed on the n-doped organic semiconductor layer. The source (or drain) contact stacks can include a p-doped injection layer, a source (or drain) contact layer, and a contact insulating layer. In another example, a method includes disposing a first i-layer over a gate insulating layer; forming source or drain contact stacks; and disposing a second i-layer, an n-doped organic semiconductor layer, and a drain or source contact.

Reconfigurable Complementary Monolayer MoTe2 Field-Effect Transistors for Integrated Circuits.

Science.gov (United States)

Larentis, Stefano; Fallahazad, Babak; Movva, Hema C P; Kim, Kyounghwan; Rai, Amritesh; Taniguchi, Takashi; Watanabe, Kenji; Banerjee, Sanjay K; Tutuc, Emanuel

2017-05-23

Transition metal dichalcogenides are of interest for next generation switches, but the lack of low resistance electron and hole contacts in the same material has hindered the development of complementary field-effect transistors and circuits. We demonstrate an air-stable, reconfigurable, complementary monolayer MoTe 2 field-effect transistor encapsulated in hexagonal boron nitride, using electrostatically doped contacts. The introduction of a multigate design with prepatterned bottom contacts allows us to independently achieve low contact resistance and threshold voltage tuning, while also decoupling the Schottky contacts and channel gating. We illustrate a complementary inverter and a p-i-n diode as potential applications.

Ionizing/displacement synergistic effects induced by gamma and neutron irradiation in gate-controlled lateral PNP bipolar transistors

Energy Technology Data Exchange (ETDEWEB)

Wang, Chenhui, E-mail: wangchenhui@nint.ac.cn [State Key Laboratory of Intense Pulsed Irradiation Simulation and Effect, Northwest Institute of Nuclear Technology, P.O. Box 69-10, Xi’an 710024 (China); Chen, Wei; Yao, Zhibin; Jin, Xiaoming; Liu, Yan; Yang, Shanchao [State Key Laboratory of Intense Pulsed Irradiation Simulation and Effect, Northwest Institute of Nuclear Technology, P.O. Box 69-10, Xi’an 710024 (China); Wang, Zhikuan [State Key Laboratory of Analog Integrated Circuit, Chongqing 400060 (China)

2016-09-21

A kind of gate-controlled lateral PNP bipolar transistor has been specially designed to do experimental validations and studies on the ionizing/displacement synergistic effects in the lateral PNP bipolar transistor. The individual and mixed irradiation experiments of gamma rays and neutrons are accomplished on the transistors. The common emitter current gain, gate sweep characteristics and sub-threshold sweep characteristics are measured after each exposure. The results indicate that under the sequential irradiation of gamma rays and neutrons, the response of the gate-controlled lateral PNP bipolar transistor does exhibit ionizing/displacement synergistic effects and base current degradation is more severe than the simple artificial sum of those under the individual gamma and neutron irradiation. Enough attention should be paid to this phenomenon in radiation damage evaluation. - Highlights: • A kind of gate-controlled lateral PNP bipolar transistor has been specially designed to facilitate the analysis of ionizing/displacement synergistic effects induced by the mixed irradiation of gamma and neutron. • The difference between ionizing/displacement synergistic effects and the simple sum of TID and displacement effects is analyzed. • The physical mechanisms of synergistic effects are explained.

Tin - an unlikely ally for silicon field effect transistors?

KAUST Repository

Hussain, Aftab M.

2014-01-13

We explore the effectiveness of tin (Sn), by alloying it with silicon, to use SiSn as a channel material to extend the performance of silicon based complementary metal oxide semiconductors. Our density functional theory based simulation shows that incorporation of tin reduces the band gap of Si(Sn). We fabricated our device with SiSn channel material using a low cost and scalable thermal diffusion process of tin into silicon. Our high-κ/metal gate based multi-gate-field-effect-transistors using SiSn as channel material show performance enhancement, which is in accordance with the theoretical analysis. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Enhancement of the saturation mobility in a ferroelectric-gated field-effect transistor by the surface planarization of ferroelectric film

Energy Technology Data Exchange (ETDEWEB)

Kim, Woo Young, E-mail: semigumi@kaist.ac.kr [Department of Mechanical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 373-1, Guseong-dong, Yuseong-gu, Daejeon 305-701 (Korea, Republic of); Jeon, Gwang-Jae; Kang, In-Ku; Shim, Hyun Bin; Lee, Hee Chul [Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 373-1, Guseong-dong, Yuseong-gu, Daejeon 305-701 (Korea, Republic of)

2015-09-30

Ferroelectricity refers to the property of a dielectric material to undergo spontaneous polarization which originates from the crystalline phase. Hence, ferroelectric materials have a certain degree of surface roughness when they are formed as a thin film. A high degree of surface roughness may cause unintended phenomena when the ferroelectric material is used in electronic devices. Specifically, the quality of subsequently deposited film could be affected by the rough surface. The present study reports that the surface roughness of ferroelectric polymer film can be reduced by a double-spin-coating method of a solution, with control of the solubility of the solution. At an identical thickness of 350 nm, double-spin-coated ferroelectric film has a root-mean-square roughness of only 3 nm, while for single-spin-coated ferroelectric film this value is approximately 16 nm. A ferroelectric-gated field-effect transistor was fabricated using the proposed double-spin-coating method, showing a maximum saturation mobility as much as seven-fold than that of a transistor fabricated with single-spin-coated ferroelectric film. The enhanced saturation mobility could be explained by the Poole–Frenkel conduction mechanism. The proposed method to reduce the surface roughness of ferroelectric film would be useful for high performance organic electronic devices, including crystalline-phase dielectric film. - Highlights: • Single and double-layer solution-processed polymer ferroelectric films were obtained. • Adjusting the solvent solubility allows making double-layer ferroelectric (DF) films. • The DF film has a smoother surface than single-layer ferroelectric (SF) film. • DF-gated transistor has faster saturation mobility than SF-based transistor. • Solvent solubility adjustment led to higher performance organic devices.

Germanium field-effect transistor made from a high-purity substrate

International Nuclear Information System (INIS)

Hansen, W.L.; Goulding, F.S.; Haller, E.E.

1978-11-01

Field effect transistors have been fabricated on high-purity germanium substrates using low-temperature technology. The aim of this work is to preserve the low density of trapping centers in high-quality starting material by low-temperature ( 0 C) processing. The use of germanium promises to eliminate some of the traps which cause generation-recombination noise in silicon field-effect transistors (FET's) at low temperatures. Typically, the transconductance (g/sub m/) in the germanium FET's is 10 mA/V and the gate leakage can be less than 10 -12 A. Present devices exhibit a large 1/f noise component and most of this noise must be eliminated if they are to be competitive with silicon FET's commonly used in high-resolution nuclear spectrometers

Extended-gate field-effect transistor (EG-FET) with molecularly imprinted polymer (MIP) film for selective inosine determination.

Science.gov (United States)

Iskierko, Zofia; Sosnowska, Marta; Sharma, Piyush Sindhu; Benincori, Tiziana; D'Souza, Francis; Kaminska, Izabela; Fronc, Krzysztof; Noworyta, Krzysztof

2015-12-15

A novel recognition unit of chemical sensor for selective determination of the inosine, renal disfunction biomarker, was devised and prepared. For that purpose, inosine-templated molecularly imprinted polymer (MIP) film was deposited on an extended-gate field-effect transistor (EG-FET) signal transducing unit. The MIP film was prepared by electrochemical polymerization of bis(bithiophene) derivatives bearing cytosine and boronic acid substituents, in the presence of the inosine template and a thiophene cross-linker. After MIP film deposition, the template was removed, and was confirmed by UV-visible spectroscopy. Subsequently, the film composition was characterized by spectroscopic techniques, and its morphology and thickness were determined by AFM. The finally MIP film-coated extended-gate field-effect transistor (EG-FET) was used for signal transduction. This combination is not widely studied in the literature, despite the fact that it allows for facile integration of electrodeposited MIP film with FET transducer. The linear dynamic concentration range of the chemosensor was 0.5-50 μM with inosine detectability of 0.62 μM. The obtained detectability compares well to the levels of the inosine in body fluids which are in the range 0-2.9 µM for patients with diagnosed diabetic nephropathy, gout or hyperuricemia, and can reach 25 µM in certain cases. The imprinting factor for inosine, determined from piezomicrogravimetric experiments with use of the MIP film-coated quartz crystal resonator, was found to be 5.5. Higher selectivity for inosine with respect to common interferents was also achieved with the present molecularly engineered sensing element. The obtained analytical parameters of the devised chemosensor allow for its use for practical sample measurements. Copyright © 2015 Elsevier B.V. All rights reserved.

Intrinsic noise in aggressively scaled field-effect transistors

International Nuclear Information System (INIS)

Albareda, G; Jiménez, D; Oriols, X

2009-01-01

According to roadmap projections, nanoscale field-effect transistors (FETs) with channel lengths below 30 nm and several gates (for improving their gate control over the source–drain conductance) will come to the market in the next few years. However, few studies deal with the noise performance of these aggressively scaled FETs. In this work, a study of the effect of the intrinsic (thermal and shot) noise of such FETs on the performance of an analog amplifier and a digital inverter is carried out by means of numerical simulations with a powerful Monte Carlo (quantum) simulator. The numerical data indicate important drawbacks in the noise performance of aggressively scaled FETs that could invalidate roadmap projections as regards analog and digital applications

Fabrication of a vertical channel field effect transistor and a study of its electrical performances

International Nuclear Information System (INIS)

Bhuiyan, A.S.

1983-01-01

A vertical channel field effect transistor on silicon was fabricated by diffusion technique and its electrical characteristics were studied as a function of voltage and temperature. It was found that this transistor has relatively high breakdown voltage of 65 volts for drain source and of 7.5 volts for gate source terminals. (author)

Optimal inverter logic gate using 10-nm double gate-all-around (DGAA transistor with asymmetric channel width

Directory of Open Access Journals (Sweden)

Myunghwan Ryu

2016-01-01

Full Text Available We investigate the electrical characteristics of a double-gate-all-around (DGAA transistor with an asymmetric channel width using three-dimensional device simulation. The DGAA structure creates a silicon nanotube field-effect transistor (NTFET with a core-shell gate architecture, which can solve the problem of loss of gate controllability of the channel and provides improved short-channel behavior. The channel width asymmetry is analyzed on both sides of the terminals of the transistors, i.e., source and drain. In addition, we consider both n-type and p-type DGAA FETs, which are essential to forming a unit logic cell, the inverter. Simulation results reveal that, according to the carrier types, the location of the asymmetry has a different effect on the electrical properties of the devices. Thus, we propose the N/P DGAA FET structure with an asymmetric channel width to form the optimal inverter. Various electrical metrics are analyzed to investigate the benefits of the optimal inverter structure over the conventional inverter structure. Simulation results show that 27% delay and 15% leakage power improvement are enabled in the optimum structure.

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

Science.gov (United States)

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Carbon nanotube transistors with graphene oxide films as gate dielectrics

Institute of Scientific and Technical Information of China (English)

无

2010-01-01

Carbon nanomaterials,including the one-dimensional(1-D) carbon nanotube(CNT) and two-dimensional(2-D) graphene,are heralded as ideal candidates for next generation nanoelectronics.An essential component for the development of advanced nanoelectronics devices is processing-compatible oxide.Here,in analogy to the widespread use of silicon dioxide(SiO2) in silicon microelectronic industry,we report the proof-of-principle use of graphite oxide(GO) as a gate dielectrics for CNT field-effect transistor(FET) via a fast and simple solution-based processing in the ambient condition.The exceptional transistor characteristics,including low operation voltage(2 V),high carrier mobility(950 cm2/V-1 s-1),and the negligible gate hysteresis,suggest a potential route to the future all-carbon nanoelectronics.

Monte Carlo simulations of spin transport in a strained nanoscale InGaAs field effect transistor

Science.gov (United States)

Thorpe, B.; Kalna, K.; Langbein, F. C.; Schirmer, S.

2017-12-01

Spin-based logic devices could operate at a very high speed with a very low energy consumption and hold significant promise for quantum information processing and metrology. We develop a spintronic device simulator by combining an in-house developed, experimentally verified, ensemble self-consistent Monte Carlo device simulator with spin transport based on a Bloch equation model and a spin-orbit interaction Hamiltonian accounting for Dresselhaus and Rashba couplings. It is employed to simulate a spin field effect transistor operating under externally applied voltages on a gate and a drain. In particular, we simulate electron spin transport in a 25 nm gate length In0.7Ga0.3As metal-oxide-semiconductor field-effect transistor with a CMOS compatible architecture. We observe a non-uniform decay of the net magnetization between the source and the gate and a magnetization recovery effect due to spin refocusing induced by a high electric field between the gate and the drain. We demonstrate a coherent control of the polarization vector of the drain current via the source-drain and gate voltages, and show that the magnetization of the drain current can be increased twofold by the strain induced into the channel.

Flexible Proton-Gated Oxide Synaptic Transistors on Si Membrane.

Science.gov (United States)

Zhu, Li Qiang; Wan, Chang Jin; Gao, Ping Qi; Liu, Yang Hui; Xiao, Hui; Ye, Ji Chun; Wan, Qing

2016-08-24

Ion-conducting materials have received considerable attention for their applications in fuel cells, electrochemical devices, and sensors. Here, flexible indium zinc oxide (InZnO) synaptic transistors with multiple presynaptic inputs gated by proton-conducting phosphorosilicate glass-based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton-gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton-gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multigates coupled flexible proton-gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing.

Bias temperature instability in tunnel field-effect transistors

Science.gov (United States)

Mizubayashi, Wataru; Mori, Takahiro; Fukuda, Koichi; Ishikawa, Yuki; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Liu, Yongxun; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Matsukawa, Takashi; Masahara, Meishoku; Endo, Kazuhiko

2017-04-01

We systematically investigated the bias temperature instability (BTI) of tunnel field-effect transistors (TFETs). The positive BTI and negative BTI mechanisms in TFETs are the same as those in metal-oxide-semiconductor FETs (MOSFETs). In TFETs, although traps are generated in high-k gate dielectrics by the bias stress and/or the interface state is degraded at the interfacial layer/channel interface, the threshold voltage (V th) shift due to BTI degradation is caused by the traps and/or the degradation of the interface state locating the band-to-band tunneling (BTBT) region near the source/gate edge. The BTI lifetime in n- and p-type TFETs is improved by applying a drain bias corresponding to the operation conditions.

Edge-on gating effect in molecular wires.

Science.gov (United States)

Lo, Wai-Yip; Bi, Wuguo; Li, Lianwei; Jung, In Hwan; Yu, Luping

2015-02-11

This work demonstrates edge-on chemical gating effect in molecular wires utilizing the pyridinoparacyclophane (PC) moiety as the gate. Different substituents with varied electronic demands are attached to the gate to simulate the effect of varying gating voltages similar to that in field-effect transistor (FET). It was observed that the orbital energy level and charge carrier's tunneling barriers can be tuned by changing the gating group from strong electron acceptors to strong electron donors. The single molecule conductance and current-voltage characteristics of this molecular system are truly similar to those expected for an actual single molecular transistor.

Double gate graphene nanoribbon field effect transistor with single halo pocket in channel region

Science.gov (United States)

Naderi, Ali

2016-01-01

A new structure for graphene nanoribbon field-effect transistors (GNRFETs) is proposed and investigated using quantum simulation with a nonequilibrium Green's function (NEGF) method. Tunneling leakage current and ambipolar conduction are known effects for MOSFET-like GNRFETs. To minimize these issues a novel structure with a simple change of the GNRFETs by using single halo pocket in the intrinsic channel region, "Single Halo GNRFET (SH-GNRFET)", is proposed. An appropriate halo pocket at source side of channel is used to modify potential distribution of the gate region and weaken band to band tunneling (BTBT). In devices with materials like Si in channel region, doping type of halo and source/drain regions are different. But, here, due to the smaller bandgap of graphene, the mentioned doping types should be the same to reduce BTBT. Simulations have shown that in comparison with conventional GNRFET (C-GNRFET), an SH-GNRFET with appropriately halo doping results in a larger ON current (Ion), smaller OFF current (Ioff), a larger ON-OFF current ratio (Ion/Ioff), superior ambipolar characteristics, a reduced power-delay product and lower delay time.

Single ZnO nanowire-PZT optothermal field effect transistors.

Science.gov (United States)

Hsieh, Chun-Yi; Lu, Meng-Lin; Chen, Ju-Ying; Chen, Yung-Ting; Chen, Yang-Fang; Shih, Wan Y; Shih, Wei-Heng

2012-09-07

A new type of pyroelectric field effect transistor based on a composite consisting of single zinc oxide nanowire and lead zirconate titanate (ZnO NW-PZT) has been developed. Under infrared (IR) laser illumination, the transconductance of the ZnO NW can be modulated by optothermal gating. The drain current can be increased or decreased by IR illumination depending on the polarization orientation of the Pb(Zr(0.3)Ti(0.7))O(3) (PZT) substrate. Furthermore, by combining the photocurrent behavior in the UV range and the optothermal gating effect in the IR range, the wide spectrum of response of current by light offers a variety of opportunities for nanoscale optoelectronic devices.

Effects of Energy Relaxation via Quantum Coupling Among Three-Dimensional Motion on the Tunneling Current of Graphene Field-Effect Transistors.

Science.gov (United States)

Mao, Ling-Feng; Ning, Huansheng; Li, Xijun

2015-12-01

We report theoretical study of the effects of energy relaxation on the tunneling current through the oxide layer of a two-dimensional graphene field-effect transistor. In the channel, when three-dimensional electron thermal motion is considered in the Schrödinger equation, the gate leakage current at a given oxide field largely increases with the channel electric field, electron mobility, and energy relaxation time of electrons. Such an increase can be especially significant when the channel electric field is larger than 1 kV/cm. Numerical calculations show that the relative increment of the tunneling current through the gate oxide will decrease with increasing the thickness of oxide layer when the oxide is a few nanometers thick. This highlights that energy relaxation effect needs to be considered in modeling graphene transistors.

A Novel Multi-Finger Gate Structure of AlGaN/GaN High Electron Mobility Transistor

International Nuclear Information System (INIS)

Cui Lei; Wang Quan; Wang Xiao-Liang; Xiao Hong-Ling; Wang Cui-Mei; Jiang Li-Juan; Feng Chun; Yin Hai-Bo; Gong Jia-Min; Li Bai-Quan; Wang Zhan-Guo

2015-01-01

A novel multi-finger gate high electron mobility transistor (HEMT) is designed to reduce the peak electric field value at the drain-side gate edge when the device is at off-state. The effective gate length (L_e_f_f) of the multi-finger gate device is smaller than that of the field plate gate device. In this work, field plate gate, five-finger gate and ten-finger gate devices are simulated. The results of the simulation indicate that the multi-finger gate device has a lower peak value than the device with the gate field plate. Moreover, this value would be further reduced when the number of gate fingers is increased. In addition, it has the potential to make the HEMT work in a higher frequency since it has a lower effective length of gate. (paper)

Top-gate organic depletion and inversion transistors with doped channel and injection contact

Energy Technology Data Exchange (ETDEWEB)

Liu, Xuhai; Kasemann, Daniel, E-mail: daniel.kasemann@iapp.de; Leo, Karl [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Strasse 1, 01069 Dresden (Germany)

2015-03-09

Organic field-effect transistors constitute a vibrant research field and open application perspectives in flexible electronics. For a commercial breakthrough, however, significant performance improvements are still needed, e.g., stable and high charge carrier mobility and on-off ratio, tunable threshold voltage, as well as integrability criteria such as n- and p-channel operation and top-gate architecture. Here, we show pentacene-based top-gate organic transistors operated in depletion and inversion regimes, realized by doping source and drain contacts as well as a thin layer of the transistor channel. By varying the doping concentration and the thickness of the doped channel, we control the position of the threshold voltage without degrading on-off ratio or mobility. Capacitance-voltage measurements show that an inversion channel can indeed be formed, e.g., an n-doped channel can be inverted to a p-type inversion channel with highly p-doped contacts. The Cytop polymer dielectric minimizes hysteresis, and the transistors can be biased for prolonged cycles without a shift of threshold voltage, indicating excellent operation stability.

Low-voltage organic field-effect transistors based on novel high-κ organometallic lanthanide complex for gate insulating materials

Directory of Open Access Journals (Sweden)

Qi Liu

2014-08-01

Full Text Available A novel high-κ organometallic lanthanide complex, Eu(tta3L (tta=2-thenoyltrifluoroacetonate, L = 4,5-pinene bipyridine, is used as gate insulating material to fabricate low-voltage pentacene field-effect transistors (FETs. The optimized gate insulator exhibits the excellent properties such as low leakage current density, low surface roughness, and high dielectric constant. When operated under a low voltage of −5 V, the pentacene FET devices show the attractive electrical performance, e.g. carrier mobility (μFET of 0.17 cm2 V−1 s−1, threshold voltage (Vth of −0.9 V, on/off current ratio of 5 × 103, and subthreshold slope (SS of 1.0 V dec−1, which is much better than that of devices obtained on conventional 300 nm SiO2 substrate (0.13 cm2 V−1 s−1, −7.3 V and 3.1 V dec−1 for μFET, Vth and SS value when operated at −30 V. These results indicate that this kind of high-κ organometallic lanthanide complex becomes a promising candidate as gate insulator for low-voltage organic FETs.

pH sensing characteristics and biosensing application of solution-gated reduced graphene oxide field-effect transistors.

Science.gov (United States)

Sohn, Il-Yung; Kim, Duck-Jin; Jung, Jin-Heak; Yoon, Ok Ja; Thanh, Tien Nguyen; Quang, Trung Tran; Lee, Nae-Eung

2013-07-15

Solution-gated reduced graphene oxide field-effect transistors (R-GO FETs) were investigated for pH sensing and biochemical sensing applications. A channel of a networked R-GO film formed by self-assembly was incorporated as a sensing layer into a solution-gated FET structure for pH sensing and the detection of acetylcholine (Ach), which is a neurotransmitter in the nerve system, through enzymatic reactions. The fabricated R-GO FET was sensitive to protons (H(+)) with a pH sensitivity of 29 mV/pH in terms of the shift of the charge neutrality point (CNP), which is attributed to changes in the surface potential caused by the interaction of protons with OH surface functional groups present on the R-GO surface. The R-GO FET immobilized with acetylcholinesterase (AchE) was used to detect Ach in the concentration range of 0.1-10mM by sensing protons generated during the enzymatic reactions. The results indicate that R-GO FETs provide the capability to detect protons, demonstrating their applicability as a biosensing device for enzymatic reactions. Copyright © 2013 Elsevier B.V. All rights reserved.

Trap assisted tunneling and its effect on subthreshold swing of tunnel field effect transistors

OpenAIRE

Sajjad, Redwan N.; Chern, Winston; Hoyt, Judy L.; Antoniadis, Dimitri A.

2016-01-01

We provide a detailed study of the interface Trap Assisted Tunneling (TAT) mechanism in tunnel field effect transistors to show how it contributes a major leakage current path before the Band To Band Tunneling (BTBT) is initiated. With a modified Shockley-Read-Hall formalism, we show that at room temperature, the phonon assisted TAT current always dominates and obscures the steep turn ON of the BTBT current for common densities of traps. Our results are applicable to top gate, double gate and...

Hysteresis analysis of graphene transistor under repeated test and gate voltage stress

International Nuclear Information System (INIS)

Yang Jie; Jia Kunpeng; Su Yajuan; Zhao Chao; Chen Yang

2014-01-01

The current transport characteristic is studied systematically based on a back-gate graphene field effect transistor, under repeated test and gate voltage stress. The interface trapped charges caused by the gate voltage sweep process screens the gate electric field, and results in the neutral point voltage shift between the forth and back sweep direction. In the repeated test process, the neutral point voltage keeps increasing with test times in both forth and back sweeps, which indicates the existence of interface trapped electrons residual and accumulation. In gate voltage stress experiment, the relative neutral point voltage significantly decreases with the reducing of stress voltage, especially in −40 V, which illustrates the driven-out phenomenon of trapped electrons under negative voltage stress. (semiconductor devices)

Effect of Coulomb scattering from trapped charges on the mobility in an organic field-effect transistor

NARCIS (Netherlands)

Sharma, A.; Janssen, N.M.A.; Matthijssen, S.J.G.; de Leeuw, D.M.; Kemerink, M.; Bobbert, P.A.

2011-01-01

We investigate the effect of Coulomb scattering from trapped charges on the mobility in the two-dimensional channel of an organic field-effect transistor. The number of trapped charges can be tuned by applying a prolonged gate bias. Surprisingly, after increasing the number of trapped charges to a

Fabrication and characterization of novel gate-all-around polycrystalline silicon junctionless field-effect transistors with ultrathin horizontal tube-shape channel

Science.gov (United States)

Chang, You-Tai; Peng, Kang-Ping; Li, Pei-Wen; Lin, Horng-Chih

2018-04-01

In this paper, we report on a novel fabrication process for the production of junctionless field-effect transistors with an ultrathin polycrystalline silicon (poly-Si) tube channel in a gate-all-around (GAA) configuration. The core of the poly-Si tube channel is filled with either a silicon nitride or a silicon oxide layer, and the effects of the core layers on the device characteristics are evaluated. The devices show excellent switching performance, thanks to the combination of the ultrathin tube channel and the GAA structure. Hysteresis loops in the transfer characteristics of the nitride-core devices are observed, owing to the dynamic trapping of electrons in the nitride core.

The effects of transistor source-to-gate bridging faults in complex CMOS gates

Science.gov (United States)

Visweswaran, G. S.; Ali, Akhtar-Uz-Zaman M.; Lala, Parag K.; Hartmann, Carlos R. P.

1991-06-01

A study of the effect of gate-to-source bridging faults in the pull-up section of a complex CMOS gate is presented. The manifestation of these faults depends on the resistance value of the connection causing the bridging. It is shown that such faults manifest themselves either as stuck-at or stuck-open faults and can be detected by tests for stuck-at and stuck-open faults generated for the equivalent logic current. It is observed that for transistor channel lengths larger than 1 microns there exists a range of values of the bridging resistance for which the fault behaves as a pseudo-stuck-open fault.

Low dielectric constant-based organic field-effect transistors and metal-insulator-semiconductor capacitors

Science.gov (United States)

Ukah, Ndubuisi Benjamin

This thesis describes a study of PFB and pentacene-based organic field-effect transistors (OFET) and metal-insulator-semiconductor (MIS) capacitors with low dielectric constant (k) poly(methyl methacrylate) (PMMA), poly(4-vinyl phenol) (PVP) and cross-linked PVP (c-PVP) gate dielectrics. A physical method -- matrix assisted pulsed laser evaporation (MAPLE) -- of fabricating all-polymer field-effect transistors and MIS capacitors that circumvents inherent polymer dissolution and solvent-selectivity problems, is demonstrated. Pentacene-based OFETs incorporating PMMA and PVP gate dielectrics usually have high operating voltages related to the thickness of the dielectric layer. Reduced PMMA layer thickness (≤ 70 nm) was obtained by dissolving the PMMA in propylene carbonate (PC). The resulting pentacene-based transistors exhibited very low operating voltage (below -3 V), minimal hysteresis in their transfer characteristics, and decent electrical performance. Also low voltage (within -2 V) operation using thin (≤ 80 nm) low-k and hydrophilic PVP and c-PVP dielectric layers obtained via dissolution in high dipole moment and high-k solvents -- PC and dimethyl sulfoxide (DMSO), is demonstrated to be a robust means of achieving improved electrical characteristics and high operational stability in OFETs incorporating PVP and c-PVP dielectrics.

High temperature study of flexible silicon-on-insulator fin field-effect transistors

KAUST Repository

Diab, Amer El Hajj

2014-09-29

We report high temperature electrical transport characteristics of a flexible version of the semiconductor industry\\'s most advanced architecture: fin field-effect transistor on silicon-on-insulator with sub-20 nm fins and high-κ/metal gate stacks. Characterization from room to high temperature (150 °C) was completed to determine temperature dependence of drain current (Ids), gate leakage current (Igs), transconductance (gm), and extracted low-field mobility (μ0). Mobility degradation with temperature is mainly caused by phonon scattering. The other device characteristics show insignificant difference at high temperature which proves the suitability of inorganic flexible electronics with advanced device architecture.

Ambipolar phosphorene field effect transistor.

Science.gov (United States)

Das, Saptarshi; Demarteau, Marcel; Roelofs, Andreas

2014-11-25

In this article, we demonstrate enhanced electron and hole transport in few-layer phosphorene field effect transistors (FETs) using titanium as the source/drain contact electrode and 20 nm SiO2 as the back gate dielectric. The field effect mobility values were extracted to be ∼38 cm(2)/Vs for electrons and ∼172 cm(2)/Vs for the holes. On the basis of our experimental data, we also comprehensively discuss how the contact resistances arising due to the Schottky barriers at the source and the drain end effect the different regime of the device characteristics and ultimately limit the ON state performance. We also propose and implement a novel technique for extracting the transport gap as well as the Schottky barrier height at the metal-phosphorene contact interface from the ambipolar transfer characteristics of the phosphorene FETs. This robust technique is applicable to any ultrathin body semiconductor which demonstrates symmetric ambipolar conduction. Finally, we demonstrate a high gain, high noise margin, chemical doping free, and fully complementary logic inverter based on ambipolar phosphorene FETs.

Ultra-thin films of polysilsesquioxanes possessing 3-methacryloxypropyl groups as gate insulator for organic field-effect transistors

International Nuclear Information System (INIS)

Nakahara, Yoshio; Kawa, Haruna; Yoshiki, Jun; Kumei, Maki; Yamamoto, Hiroyuki; Oi, Fumio; Yamakado, Hideo; Fukuda, Hisashi; Kimura, Keiichi

2012-01-01

Polysilsesquioxanes (PSQs) possessing 3-methacryloxypropyl groups as an organic moiety of the side chain were synthesized by sol–gel condensation copolymerization of the corresponding trialkoxysilanes. The ultra-thin PSQ film with a radical initiator and a cross-linking agent was prepared by a spin-coating method, and the film was cured integrally at low temperatures of less than 120 °C through two different kinds of polymeric reactions, which were radical polymerization of vinyl groups and sol–gel condensation polymerization of terminated silanol and alkoxy groups. The obtained PSQ film showed the almost perfect solubilization resistance to acetone, which is a good solvent of PSQ before polymerization. It became clear by atomic force microscopy observation that the surface of the PSQ film was very smooth at a nano-meter level. Furthermore, pentacene-based organic field-effect transistor (OFET) with the PSQ film as a gate insulator showed typical p-channel enhancement mode operation characteristics and therefore the ultra-thin PSQ film has the potential to be applicable for solution-processed OFET systems. - Highlights: ► Polysilsesquioxanes (PSQs) possessing 3-methacryloxypropyl groups were synthesized. ► The ultra-thin PSQ film could be cured at low temperatures of less than 120 °C. ► The PSQ film showed the almost perfect solubilization resistance to organic solvent. ► The surface of the PSQ film was very smooth at a nano-meter level. ► Pentacene-based organic field-effect transistor with the PSQ film was fabricated.

Junctionless Thin-Film Transistors Gated by an H₃PO₄-Incorporated Chitosan Proton Conductor.

Science.gov (United States)

Liu, Huixuan; Xun, Damao

2018-04-01

We fabricated an H3PO4-incorporated chitosan proton conductor film that exhibited the electric double layer effect and showed a high specific capacitance of 4.42 μF/cm2. Transparent indium tin oxide thin-film transistors gated by H3PO4-incorporated chitosan films were fabricated by sputtering through a shadow mask. The operating voltage was as low as 1.2 V because of the high specific capacitance of the H3PO4-incorporated chitosan dielectrics. The junctionless transparent indium tin oxide thin film transistors exhibited good performance, including an estimated current on/off ratio and field-effect mobility of 1.2 × 106 and 6.63 cm2V-1s-1, respectively. These low-voltage thin-film electric-double-layer transistors gated by H3PO4-incorporated chitosan are promising for next generation battery-powered "see-through" portable sensors.

Near interface traps in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

Energy Technology Data Exchange (ETDEWEB)

Fiorenza, Patrick; La Magna, Antonino; Vivona, Marilena; Roccaforte, Fabrizio [Consiglio Nazionale delle Ricerche-Istituto per la Microelettronica e Microsistemi (CNR-IMM), Strada VIII 5, Zona Industriale 95121 Catania (Italy)

2016-07-04

This letter reports on the impact of gate oxide trapping states on the conduction mechanisms in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs). The phenomena were studied by gate current transient measurements, performed on n-channel MOSFETs operated in “gate-controlled-diode” configuration. The measurements revealed an anomalous non-steady conduction under negative bias (V{sub G} > |20 V|) through the SiO{sub 2}/4H-SiC interface. The phenomenon was explained by the coexistence of a electron variable range hopping and a hole Fowler-Nordheim (FN) tunnelling. A semi-empirical modified FN model with a time-depended electric field is used to estimate the near interface traps in the gate oxide (N{sub trap} ∼ 2 × 10{sup 11} cm{sup −2}).

Effect of Coercive Voltage and Charge Injection on Performance of a Ferroelectric-Gate Thin-Film Transistor

Directory of Open Access Journals (Sweden)

P. T. Tue

2013-01-01

Full Text Available We adopted a lanthanum oxide capping layer between semiconducting channel and insulator layers for fabrication of a ferroelectric-gate thin-film transistor memory (FGT which uses solution-processed indium-tin-oxide (ITO and lead-zirconium-titanate (PZT film as a channel layer and a gate insulator, respectively. Good transistor characteristics such as a high “on/off” current ratio, high channel mobility, and a large memory window of 108, 15.0 cm2 V−1 s−1, and 3.5 V were obtained, respectively. Further, a correlation between effective coercive voltage, charge injection effect, and FGT’s memory window was investigated. It is found that the charge injection from the channel to the insulator layer, which occurs at a high electric field, dramatically influences the memory window. The memory window’s enhancement can be explained by a dual effect of the capping layer: (1 a reduction of the charge injection and (2 an increase of effective coercive voltage dropped on the insulator.

Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

International Nuclear Information System (INIS)

Takano, H.; Hosogi, K.; Kato, T.

1995-01-01

A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier with an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs

Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate

International Nuclear Information System (INIS)

Liu, Hsi-Wen; Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Chang, Ting-Chang; Chen, Ching-En; Tseng, Tseung-Yuen; Lin, Chien-Yu; Cheng, Osbert; Huang, Cheng-Tung; Ye, Yi-Han

2016-01-01

This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

Low-voltage organic field-effect transistors based on novel high-κ organometallic lanthanide complex for gate insulating materials

Energy Technology Data Exchange (ETDEWEB)

Liu, Qi; Li, Yi; Zhang, Yang; Song, You, E-mail: wangxzh@nju.edu.cn, E-mail: yli@nju.edu.cn, E-mail: yousong@nju.edu.cn; Wang, Xizhang, E-mail: wangxzh@nju.edu.cn, E-mail: yli@nju.edu.cn, E-mail: yousong@nju.edu.cn; Hu, Zheng [Key Laboratory of Mesoscopic Chemistry of MOE, Jiangsu Provincial Lab for Nanotechnology, School of Chemistry and Chemical Engineering, Nanjing University, Nanjing 210093, China. High-Tech Research Institute of Nanjing University (Suzhou), Suzhou 215123 (China); Sun, Huabin; Li, Yun, E-mail: wangxzh@nju.edu.cn, E-mail: yli@nju.edu.cn, E-mail: yousong@nju.edu.cn; Shi, Yi [School of Electronic Science and Engineering and Jiangsu Provincial Key Laboratory of Photonic and Electronic Materials, Nanjing University, Nanjing 210093 (China)

2014-08-15

A novel high-κ organometallic lanthanide complex, Eu(tta){sub 3}L (tta=2-thenoyltrifluoroacetonate, L = 4,5-pinene bipyridine), is used as gate insulating material to fabricate low-voltage pentacene field-effect transistors (FETs). The optimized gate insulator exhibits the excellent properties such as low leakage current density, low surface roughness, and high dielectric constant. When operated under a low voltage of −5 V, the pentacene FET devices show the attractive electrical performance, e.g. carrier mobility (μ{sub FET}) of 0.17 cm{sup 2} V{sup −1} s{sup −1}, threshold voltage (V{sub th}) of −0.9 V, on/off current ratio of 5 × 10{sup 3}, and subthreshold slope (SS) of 1.0 V dec{sup −1}, which is much better than that of devices obtained on conventional 300 nm SiO{sub 2} substrate (0.13 cm{sup 2} V{sup −1} s{sup −1}, −7.3 V and 3.1 V dec{sup −1} for μ{sub FET}, V{sub th} and SS value when operated at −30 V). These results indicate that this kind of high-κ organometallic lanthanide complex becomes a promising candidate as gate insulator for low-voltage organic FETs.

Comprehensive study of gate-terminated and source-terminated field-plate 0.13 µm NMOS transistors

International Nuclear Information System (INIS)

Chiu, Hsien-Chin; Lin, Shao-Wei; Cheng, Chia-Shih; Wei, Chien-Cheng

2008-01-01

This study systematically investigated microwave noise, power and linearity characteristics of field-plate (FP) 0.13 µm CMOS transistors in which the field-plate metal is connected to the gate terminal and the source terminal. The gate-terminated FP NMOS (FP-G NMOS) provided the best noise figure (NF) at 6 GHz compared with standard devices and the source-terminated FP device (FP-S NMOS) as the lowest gate resistance (R g ) was obtained by this structure. By adopting the field-plate metal in NMOS, both FP-S and FP-G devices achieved higher current density at high gate bias voltages. Moreover, these two devices also had higher efficiency under high drain-to-source voltages at the high input power swing. The third-order inter-modulation product (IM3) is −39.4 dBm for FP-S NMOS at P in of −20 dBm; the corresponding values for FP-G and standard devices are −34.9 dBm and −37.3 dBm, respectively. Experimental results indicate that the FP-G architecture is suitable for low noise applications and FP-S is suitable for high power and high linearity operation

High-sensitivity pH sensor using separative extended-gate field-effect transistors with single-walled carbon-nanotube networks

Science.gov (United States)

Pyo, Ju-Young; Cho, Won-Ju

2018-04-01

We fabricate high-sensitivity pH sensors using single-walled carbon-nanotube (SWCNT) network thin-film transistors (TFTs). The sensing and transducer parts of the pH sensor are composed of separative extended-sensing gates (ESGs) with SnO2 ion-sensitive membranes and double-gate structure TFTs with thin SWCNT network channels of ∼1 nm and AlO x top-gate insulators formed by the solution-deposition method. To prevent thermal process-induced damages on the SWCNT channel layer due to the post-deposition annealing process and improve the electrical characteristics of the SWCNT-TFTs, microwave irradiation is applied at low temperatures. As a result, a pH sensitivity of 7.6 V/pH, far beyond the Nernst limit, is obtained owing to the capacitive coupling effect between the top- and bottom-gate insulators of the SWCNT-TFTs. Therefore, double-gate structure SWCNT-TFTs with separated ESGs are expected to be highly beneficial for high-sensitivity disposable biosensor applications.

High-performance carbon-nanotube-based complementary field-effect-transistors and integrated circuits with yttrium oxide

Energy Technology Data Exchange (ETDEWEB)

Liang, Shibo; Zhang, Zhiyong, E-mail: zyzhang@pku.edu.cn; Si, Jia; Zhong, Donglai; Peng, Lian-Mao, E-mail: lmpeng@pku.edu.cn [Key Laboratory for the Physics and Chemistry of Nanodevices, Department of Electronics, Peking University, Beijing 100871 (China)

2014-08-11

High-performance p-type carbon nanotube (CNT) transistors utilizing yttrium oxide as gate dielectric are presented by optimizing oxidization and annealing processes. Complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) are then fabricated on CNTs, and the p- and n-type devices exhibit symmetrical high performances, especially with low threshold voltage near to zero. The corresponding CMOS CNT inverter is demonstrated to operate at an ultra-low supply voltage down to 0.2 V, while displaying sufficient voltage gain, high noise margin, and low power consumption. Yttrium oxide is proven to be a competitive gate dielectric for constructing high-performance CNT CMOS FETs and integrated circuits.

Threshold voltage roll-off modelling of bilayer graphene field-effect transistors

International Nuclear Information System (INIS)

Saeidmanesh, M; Ismail, Razali; Khaledian, M; Karimi, H; Akbari, E

2013-01-01

An analytical model is presented for threshold voltage roll-off of double gate bilayer graphene field-effect transistors. To this end, threshold voltage models of short- and long-channel states have been developed. In the short-channel case, front and back gate potential distributions have been modelled and used. In addition, the tunnelling probability is modelled and its effect is taken into consideration in the potential distribution model. To evaluate the accuracy of the potential model, FlexPDE software is employed with proper boundary conditions and a good agreement is observed. Using the proposed models, the effect of several structural parameters on the threshold voltage and its roll-off are studied at room temperature. (paper)

Large current modulation and tunneling magnetoresistance change by a side-gate electric field in a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor.

Science.gov (United States)

Kanaki, Toshiki; Yamasaki, Hiroki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

2018-05-08

A vertical spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) is a promising low-power device for the post scaling era. Here, using a ferromagnetic-semiconductor GaMnAs-based vertical spin MOSFET with a GaAs channel layer, we demonstrate a large drain-source current I DS modulation by a gate-source voltage V GS with a modulation ratio up to 130%, which is the largest value that has ever been reported for vertical spin field-effect transistors thus far. We find that the electric field effect on indirect tunneling via defect states in the GaAs channel layer is responsible for the large I DS modulation. This device shows a tunneling magnetoresistance (TMR) ratio up to ~7%, which is larger than that of the planar-type spin MOSFETs, indicating that I DS can be controlled by the magnetization configuration. Furthermore, we find that the TMR ratio can be modulated by V GS . This result mainly originates from the electric field modulation of the magnetic anisotropy of the GaMnAs ferromagnetic electrodes as well as the potential modulation of the nonmagnetic semiconductor GaAs channel layer. Our findings provide important progress towards high-performance vertical spin MOSFETs.

Ultra-thin films of polysilsesquioxanes possessing 3-methacryloxypropyl groups as gate insulator for organic field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Nakahara, Yoshio; Kawa, Haruna [Department of Applied Chemistry, Faculty of Systems Engineering, Wakayama University, 930 Sakae-dani, Wakayama 640-8510 (Japan); Yoshiki, Jun [Division of Information and Electronic Engineering, Faculty of Engineering, Muroran Institute of Technology, 27-1 Mizumoto-cho, Muroran 050-8585 (Japan); Kumei, Maki; Yamamoto, Hiroyuki; Oi, Fumio [Konishi Chemical IND. Co., LTD., 3-4-77 Kozaika, Wakayama 641-0007 (Japan); Yamakado, Hideo [Department of Applied Chemistry, Faculty of Systems Engineering, Wakayama University, 930 Sakae-dani, Wakayama 640-8510 (Japan); Fukuda, Hisashi [Division of Engineering for Composite Functions, Faculty of Engineering, Muroran Institute of Technology, 27-1 Mizumoto-cho, Muroran 050-8585 (Japan); Kimura, Keiichi, E-mail: kkimura@center.wakayama-u.ac.jp [Department of Applied Chemistry, Faculty of Systems Engineering, Wakayama University, 930 Sakae-dani, Wakayama 640-8510 (Japan)

2012-10-01

Polysilsesquioxanes (PSQs) possessing 3-methacryloxypropyl groups as an organic moiety of the side chain were synthesized by sol-gel condensation copolymerization of the corresponding trialkoxysilanes. The ultra-thin PSQ film with a radical initiator and a cross-linking agent was prepared by a spin-coating method, and the film was cured integrally at low temperatures of less than 120 Degree-Sign C through two different kinds of polymeric reactions, which were radical polymerization of vinyl groups and sol-gel condensation polymerization of terminated silanol and alkoxy groups. The obtained PSQ film showed the almost perfect solubilization resistance to acetone, which is a good solvent of PSQ before polymerization. It became clear by atomic force microscopy observation that the surface of the PSQ film was very smooth at a nano-meter level. Furthermore, pentacene-based organic field-effect transistor (OFET) with the PSQ film as a gate insulator showed typical p-channel enhancement mode operation characteristics and therefore the ultra-thin PSQ film has the potential to be applicable for solution-processed OFET systems. - Highlights: Black-Right-Pointing-Pointer Polysilsesquioxanes (PSQs) possessing 3-methacryloxypropyl groups were synthesized. Black-Right-Pointing-Pointer The ultra-thin PSQ film could be cured at low temperatures of less than 120 Degree-Sign C. Black-Right-Pointing-Pointer The PSQ film showed the almost perfect solubilization resistance to organic solvent. Black-Right-Pointing-Pointer The surface of the PSQ film was very smooth at a nano-meter level. Black-Right-Pointing-Pointer Pentacene-based organic field-effect transistor with the PSQ film was fabricated.

Atomic-Monolayer MoS2 Band-to-Band Tunneling Field-Effect Transistor

KAUST Repository

Lan, Yann Wen

2016-09-05

The experimental observation of band-to-band tunneling in novel tunneling field-effect transistors utilizing a monolayer of MoS2 as the conducting channel is demonstrated. Our results indicate that the strong gate-coupling efficiency enabled by two-dimensional materials, such as monolayer MoS2, results in the direct manifestation of a band-to-band tunneling current and an ambipolar transport.

Sensing properties of separative paper-based extended-gate ion-sensitive field-effect transistor for cost effective pH sensor applications

Science.gov (United States)

Cho, Won-Ju; Lim, Cheol-Min

2018-02-01

In this study, we developed a cost-effective ion-sensing field-effect transistor (FET) with an extended gate (EG) fabricated on a separative paper substrate. The pH sensing characteristics of the paper EG was compared with those of other EGs fabricated on silicon, glass, or polyimide substrates. The fabricated paper-based EGFET exhibited excellent sensitivity close to the Nernst response limit as well as to that of the other substrate-based EGFETs. In addition, we found that all EGFETs, regardless of the substrate, have similar non-ideal behavior, i.e., drift phenomenon and hysteresis width. To investigate the degradation and durability of the paper EG after prolonged use, aging-effect tests were carried out in terms of the hysteresis width and sensitivity over a course of 30 days. As a result, the paper EG maintained stable pH sensing characteristics after 30 days. Therefore, we expect that paper EGFETs can provide a cost-effective sensor platform.

Gate-modulated conductance of few-layer WSe2 field-effect transistors in the subgap regime: Schottky barrier transistor and subgap impurity states

International Nuclear Information System (INIS)

Wang, Junjie; Feng, Simin; Rhodes, Daniel; Balicas, Luis; Nguyen, Minh An T.; Watanabe, K.; Taniguchi, T.; Mallouk, Thomas E.; Terrones, Mauricio; Zhu, J.

2015-01-01

Two key subjects stand out in the pursuit of semiconductor research: material quality and contact technology. The fledging field of atomically thin transition metal dichalcogenides (TMDCs) faces a number of challenges in both efforts. This work attempts to establish a connection between the two by examining the gate-dependent conductance of few-layer (1-5L) WSe 2 field effect devices. Measurements and modeling of the subgap regime reveal Schottky barrier transistor behavior. We show that transmission through the contact barrier is dominated by thermionic field emission (TFE) at room temperature, despite the lack of intentional doping. The TFE process arises due to a large number of subgap impurity states, the presence of which also leads to high mobility edge carrier densities. The density of states of such impurity states is self-consistently determined to be approximately 1–2 × 10 13 /cm 2 /eV in our devices. We demonstrate that substrate is unlikely to be a major source of the impurity states and suspect that lattice defects within the material itself are primarily responsible. Our experiments provide key information to advance the quality and understanding of TMDC materials and electrical devices

Analysis of the two dimensional Datta-Das Spin Field Effect Transistor

OpenAIRE

Bandyopadhyay, S.

2010-01-01

An analytical expression is derived for the conductance modulation of a ballistic two dimensional Datta-Das Spin Field Effect Transistor (SPINFET) as a function of gate voltage. Using this expression, we show that the recently observed conductance modulation in a two-dimensional SPINFET structure does not match the theoretically expected result very well. This calls into question the claimed demonstration of the SPINFET and underscores the need for further careful investigation.

Analysis of the two-dimensional Datta-Das spin field effect transistor

Science.gov (United States)

Agnihotri, P.; Bandyopadhyay, S.

2010-03-01

An analytical expression is derived for the conductance modulation of a ballistic two-dimensional Datta-das spin field effect transistor (SPINFET) as a function of gate voltage. Using this expression, we show that the recently observed conductance modulation in a two-dimensional SPINFET structure does not match the theoretically expected result very well. This calls into question the claimed demonstration of the SPINFET and underscores the need for further careful investigation.

Subthreshold characteristics of pentacene field-effect transistors influenced by grain boundaries.

OpenAIRE

Park, J.; Jeong, Y-S.; Park, K-S.; Do, L-M.; Bae, J-H.; Choi, J.S.; Pearson, C.; Petty, M.C.

2012-01-01

Grain boundaries in polycrystalline pentacene films significantly affect the electrical characteristics of pentacene field-effect transistors (FETs). Upon reversal of the gate voltage sweep direction, pentacene FETs exhibited hysteretic behaviours in the subthreshold region, which was more pronounced for the FET having smaller pentacene grains. No shift in the flat-band voltage of the metal-insulator-semiconductor capacitor elucidates that the observed hysteresis was mainly caused by the infl...

Gas Sensors Based on Semiconducting Nanowire Field-Effect Transistors

Directory of Open Access Journals (Sweden)

Ping Feng

2014-09-01

Full Text Available One-dimensional semiconductor nanostructures are unique sensing materials for the fabrication of gas sensors. In this article, gas sensors based on semiconducting nanowire field-effect transistors (FETs are comprehensively reviewed. Individual nanowires or nanowire network films are usually used as the active detecting channels. In these sensors, a third electrode, which serves as the gate, is used to tune the carrier concentration of the nanowires to realize better sensing performance, including sensitivity, selectivity and response time, etc. The FET parameters can be modulated by the presence of the target gases and their change relate closely to the type and concentration of the gas molecules. In addition, extra controls such as metal decoration, local heating and light irradiation can be combined with the gate electrode to tune the nanowire channel and realize more effective gas sensing. With the help of micro-fabrication techniques, these sensors can be integrated into smart systems. Finally, some challenges for the future investigation and application of nanowire field-effect gas sensors are discussed.

Dual origin of room temperature sub-terahertz photoresponse in graphene field effect transistors

Science.gov (United States)

Bandurin, D. A.; Gayduchenko, I.; Cao, Y.; Moskotin, M.; Principi, A.; Grigorieva, I. V.; Goltsman, G.; Fedorov, G.; Svintsov, D.

2018-04-01

Graphene is considered as a promising platform for detectors of high-frequency radiation up to the terahertz (THz) range due to its superior electron mobility. Previously, it has been shown that graphene field effect transistors (FETs) exhibit room temperature broadband photoresponse to incoming THz radiation, thanks to the thermoelectric and/or plasma wave rectification. Both effects exhibit similar functional dependences on the gate voltage, and therefore, it was difficult to disentangle these contributions in previous studies. In this letter, we report on combined experimental and theoretical studies of sub-THz response in graphene field-effect transistors analyzed at different temperatures. This temperature-dependent study allowed us to reveal the role of the photo-thermoelectric effect, p-n junction rectification, and plasmonic rectification in the sub-THz photoresponse of graphene FETs.

Photolithographically Patterned TiO2 Films for Electrolyte-Gated Transistors.

Science.gov (United States)

Valitova, Irina; Kumar, Prajwal; Meng, Xiang; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2016-06-15

Metal oxides constitute a class of materials whose properties cover the entire range from insulators to semiconductors to metals. Most metal oxides are abundant and accessible at moderate cost. Metal oxides are widely investigated as channel materials in transistors, including electrolyte-gated transistors, where the charge carrier density can be modulated by orders of magnitude upon application of relatively low electrical bias (2 V). Electrolyte gating offers the opportunity to envisage new applications in flexible and printed electronics as well as to improve our current understanding of fundamental processes in electronic materials, e.g. insulator/metal transitions. In this work, we employ photolithographically patterned TiO2 films as channels for electrolyte-gated transistors. TiO2 stands out for its biocompatibility and wide use in sensing, electrochromics, photovoltaics and photocatalysis. We fabricated TiO2 electrolyte-gated transistors using an original unconventional parylene-based patterning technique. By using a combination of electrochemical and charge carrier transport measurements we demonstrated that patterning improves the performance of electrolyte-gated TiO2 transistors with respect to their unpatterned counterparts. Patterned electrolyte-gated (EG) TiO2 transistors show threshold voltages of about 0.9 V, ON/OFF ratios as high as 1 × 10(5), and electron mobility above 1 cm(2)/(V s).

Large-current-controllable carbon nanotube field-effect transistor in electrolyte solution

Science.gov (United States)

Myodo, Miho; Inaba, Masafumi; Ohara, Kazuyoshi; Kato, Ryogo; Kobayashi, Mikinori; Hirano, Yu; Suzuki, Kazuma; Kawarada, Hiroshi

2015-05-01

Large-current-controllable carbon nanotube field-effect transistors (CNT-FETs) were fabricated with mm-long CNT sheets. The sheets, synthesized by remote-plasma-enhanced CVD, contained both single- and double-walled CNTs. Titanium was deposited on the sheet as source and drain electrodes, and an electrolyte solution was used as a gate electrode (solution gate) to apply a gate voltage to the CNTs through electric double layers formed around the CNTs. The drain current came to be well modulated as electrolyte solution penetrated into the sheets, and one of the solution gate CNT-FETs was able to control a large current of over 2.5 A. In addition, we determined the transconductance parameter per tube and compared it with values for other CNT-FETs. The potential of CNT sheets for applications requiring the control of large current is exhibited in this study.

Artificial Synapses Based on in-Plane Gate Organic Electrochemical Transistors.

Science.gov (United States)

Qian, Chuan; Sun, Jia; Kong, Ling-An; Gou, Guangyang; Yang, Junliang; He, Jun; Gao, Yongli; Wan, Qing

2016-10-05

Realization of biological synapses using electronic devices is regarded as the basic building blocks for neuromorphic engineering and artificial neural network. With the advantages of biocompatibility, low cost, flexibility, and compatible with printing and roll-to-roll processes, the artificial synapse based on organic transistor is of great interest. In this paper, the artificial synapse simulation by ion-gel gated organic field-effect transistors (FETs) with poly(3-hexylthiophene) (P3HT) active channel is demonstrated. Key features of the synaptic behaviors, such as paired-pulse facilitation (PPF), short-term plasticity (STP), self-tuning, the spike logic operation, spatiotemporal dentritic integration, and modulation are successfully mimicked. Furthermore, the interface doping processes of electrolyte ions between the active P3HT layer and ion gels is comprehensively studied for confirming the operating processes underlying the conductivity and excitatory postsynaptic current (EPSC) variations in the organic synaptic devices. This study represents an important step toward building future artificial neuromorphic systems with newly emerged ion gel gated organic synaptic devices.

Water-gel for gating graphene transistors.

Science.gov (United States)

Kim, Beom Joon; Um, Soong Ho; Song, Woo Chul; Kim, Yong Ho; Kang, Moon Sung; Cho, Jeong Ho

2014-05-14

Water, the primary electrolyte in biology, attracts significant interest as an electrolyte-type dielectric material for transistors compatible with biological systems. Unfortunately, the fluidic nature and low ionic conductivity of water prevents its practical usage in such applications. Here, we describe the development of a solid state, megahertz-operating, water-based gate dielectric system for operating graphene transistors. The new electrolyte systems were prepared by dissolving metal-substituted DNA polyelectrolytes into water. The addition of these biocompatible polyelectrolytes induced hydrogelation to provide solid-state integrity to the system. They also enhanced the ionic conductivities of the electrolytes, which in turn led to the quick formation of an electric double layer at the graphene/electrolyte interface that is beneficial for modulating currents in graphene transistors at high frequencies. At the optimized conditions, the Na-DNA water-gel-gated flexible transistors and inverters were operated at frequencies above 1 MHz and 100 kHz, respectively.

Transport properties of hydrogen passivated silicon nanotubes and silicon nanotube field effect transistors

KAUST Repository

Montes Muñoz, Enrique

2017-01-24

We investigate the electronic transport properties of silicon nanotubes attached to metallic electrodes from first principles, using density functional theory and the non-equilibrium Green\\'s function method. The influence of the surface termination is studied as well as the dependence of the transport characteristics on the chirality, diameter, and length. Strong electronic coupling between nanotubes and electrodes is found to be a general feature that results in low contact resistance. The conductance in the tunneling regime is discussed in terms of the complex band structure. Silicon nanotube field effect transistors are simulated by applying a uniform potential gate. Our results demonstrate very high values of transconductance, outperforming the best commercial silicon field effect transistors, combined with low values of sub-threshold swing.

Comment on "Performance of a spin based insulated gate field effect transistor" [cond-mat/0603260] [cond-mat/0603260

OpenAIRE

Bandyopadhyay, S.; Cahay, M.

2006-01-01

In a recent e-print [cond-mat/0603260] Hall and Flatte claim that a particular spin based field effect transistor (SPINFET), which they have analyzed, will have a lower threshold voltage, lower switching energy and lower leakage current than a comparable metal oxide semiconductor field effect transistor (MOSFET). Here, we show that all three claims of HF are invalid.

AlN metal-semiconductor field-effect transistors using Si-ion implantation

Science.gov (United States)

Okumura, Hironori; Suihkonen, Sami; Lemettinen, Jori; Uedono, Akira; Zhang, Yuhao; Piedra, Daniel; Palacios, Tomás

2018-04-01

We report on the electrical characterization of Si-ion implanted AlN layers and the first demonstration of metal-semiconductor field-effect transistors (MESFETs) with an ion-implanted AlN channel. The ion-implanted AlN layers with Si dose of 5 × 1014 cm-2 exhibit n-type characteristics after thermal annealing at 1230 °C. The ion-implanted AlN MESFETs provide good drain current saturation and stable pinch-off operation even at 250 °C. The off-state breakdown voltage is 2370 V for drain-to-gate spacing of 25 µm. These results show the great potential of AlN-channel transistors for high-temperature and high-power applications.

Polarization sensitive detection of 100 GHz radiation by high mobility field-effect transistors

International Nuclear Information System (INIS)

Sakowicz, M.; Lusakowski, J.; Karpierz, K.; Grynberg, M.; Knap, W.; Gwarek, W.

2008-01-01

Detection of 100 GHz electromagnetic radiation by a GaAs/AlGaAs high electron mobility field-effect transistor was investigated at 300 K as a function of the angle α between the direction of linear polarization of the radiation and the symmetry axis of the transistor. The angular dependence of the detected signal was found to be A 0 cos 2 (α-α 0 )+C with A 0 , α 0 , and C dependent on the electrical polarization of the transistor gate. This dependence is interpreted as due to excitation of two crossed phase-shifted oscillators. A response of the transistor chip (including bonding wires and the substrate) to 100 GHz radiation was numerically simulated. Results of calculations confirmed experimentally observed dependencies and showed that the two oscillators result from an interplay of 100 GHz currents defined by the transistor impedance together with bonding wires and substrate related modes

Evaluation of Anisotropic Biaxial Stress Induced Around Trench Gate of Si Power Transistor Using Water-Immersion Raman Spectroscopy

Science.gov (United States)

Suzuki, Takahiro; Yokogawa, Ryo; Oasa, Kohei; Nishiwaki, Tatsuya; Hamamoto, Takeshi; Ogura, Atsushi

2018-05-01

The trench gate structure is one of the promising techniques to reduce on-state resistance (R on) for silicon power devices, such as insulated gate bipolar transistors and power metal-oxide-semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the R on of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.

Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks

International Nuclear Information System (INIS)

Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Liu, Xi-Wen; Chang, Ting-Chang; Chen, Ching-En; Ho, Szu-Han; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Lu, Ching-Sen

2014-01-01

This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO 2 interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks.

A computational study of a novel graphene nanoribbon field effect transistor

Science.gov (United States)

Ghoreishi, Seyed Saleh; Yousefi, Reza

2017-04-01

In this paper, using gate structure engineering and modification of channel dopant profile, we propose a new double gate graphene nanoribbon field effect transistor (DG-GNRFET) mainly to suppress the band-to-band tunneling (BTBT) of carriers. In the new device, the intrinsic part of the channel is replaced by an intrinsic-lightly doped-intrinsic (I -N--I) configuration in a way that only the intrinsic parts are covered by the gate contact. Transport characteristics of the device are investigated theoretically using the nonequilibrium Green’s function (NEGF) formalism. Numerical simulations show that off-current, ambipolar behavior, on/off-current ratio and the switching characteristics such as intrinsic delay and power-delay product are improved. In addition, the new device demonstrates better sub-threshold swing and less drain-induced barrier lowering (DIBL).

Gate-modulated conductance of few-layer WSe{sub 2} field-effect transistors in the subgap regime: Schottky barrier transistor and subgap impurity states

Energy Technology Data Exchange (ETDEWEB)

Wang, Junjie; Feng, Simin [Department of Physics, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Rhodes, Daniel; Balicas, Luis [National High Magnetic Field Lab, Florida State University, Tallahassee, Florida 32310 (United States); Nguyen, Minh An T. [Department of Chemistry, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Watanabe, K.; Taniguchi, T. [National Institute for Materials Science, 1-1 Namiki, Tsukuba 305-0044 (Japan); Mallouk, Thomas E. [Department of Physics, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Department of Chemistry, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Department of Biochemistry and Molecular Biology, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Terrones, Mauricio [Department of Physics, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Department of Chemistry, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Department of Materials Science and Engineering, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Center for 2-Dimensional and Layered Materials, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Zhu, J., E-mail: jzhu@phys.psu.edu [Department of Physics, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Center for 2-Dimensional and Layered Materials, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States)

2015-04-13

Two key subjects stand out in the pursuit of semiconductor research: material quality and contact technology. The fledging field of atomically thin transition metal dichalcogenides (TMDCs) faces a number of challenges in both efforts. This work attempts to establish a connection between the two by examining the gate-dependent conductance of few-layer (1-5L) WSe{sub 2} field effect devices. Measurements and modeling of the subgap regime reveal Schottky barrier transistor behavior. We show that transmission through the contact barrier is dominated by thermionic field emission (TFE) at room temperature, despite the lack of intentional doping. The TFE process arises due to a large number of subgap impurity states, the presence of which also leads to high mobility edge carrier densities. The density of states of such impurity states is self-consistently determined to be approximately 1–2 × 10{sup 13}/cm{sup 2}/eV in our devices. We demonstrate that substrate is unlikely to be a major source of the impurity states and suspect that lattice defects within the material itself are primarily responsible. Our experiments provide key information to advance the quality and understanding of TMDC materials and electrical devices.

Two dimensional analytical model for a reconfigurable field effect transistor

Science.gov (United States)

Ranjith, R.; Jayachandran, Remya; Suja, K. J.; Komaragiri, Rama S.

2018-02-01

This paper presents two-dimensional potential and current models for a reconfigurable field effect transistor (RFET). Two potential models which describe subthreshold and above-threshold channel potentials are developed by solving two-dimensional (2D) Poisson's equation. In the first potential model, 2D Poisson's equation is solved by considering constant/zero charge density in the channel region of the device to get the subthreshold potential characteristics. In the second model, accumulation charge density is considered to get above-threshold potential characteristics of the device. The proposed models are applicable for the device having lightly doped or intrinsic channel. While obtaining the mathematical model, whole body area is divided into two regions: gated region and un-gated region. The analytical models are compared with technology computer-aided design (TCAD) simulation results and are in complete agreement for different lengths of the gated regions as well as at various supply voltage levels.

Effect of dielectric layers on device stability of pentacene-based field-effect transistors.

Science.gov (United States)

Di, Chong-an; Yu, Gui; Liu, Yunqi; Guo, Yunlong; Sun, Xiangnan; Zheng, Jian; Wen, Yugeng; Wang, Ying; Wu, Weiping; Zhu, Daoben

2009-09-07

We report stable organic field-effect transistors (OFETs) based on pentacene. It was found that device stability strongly depends on the dielectric layer. Pentacene thin-film transistors based on the bare or polystyrene-modified SiO(2) gate dielectrics exhibit excellent electrical stabilities. In contrast, the devices with the octadecyltrichlorosilane (OTS)-treated SiO(2) dielectric layer showed the worst stabilities. The effects of the different dielectrics on the device stabilities were investigated. We found that the surface energy of the gate dielectric plays a crucial role in determining the stability of the pentacene thin film, device performance and degradation of electrical properties. Pentacene aggregation, phase transfer and film morphology are also important factors that influence the device stability of pentacene devices. As a result of the surface energy mismatch between the dielectric layer and organic semiconductor, the electronic performance was degraded. Moreover, when pentacene was deposited on the OTS-treated SiO(2) dielectric layer with very low surface energy, pentacene aggregation occurred and resulted in a dramatic decrease of device performance. These results demonstrated that the stable OFETs could be obtained by using pentacene as a semiconductor layer.

Effect of electrode design on crosstalk between neighboring organic field-effect transistors based on one single crystal

Science.gov (United States)

Li, Mengjie; Tang, Qingxin; Tong, Yanhong; Zhao, Xiaoli; Zhou, Shujun; Liu, Yichun

2018-03-01

The design of high-integration organic circuits must be such that the interference between neighboring devices is eliminated. Here, rubrene crystals were used to study the effect of the electrode design on crosstalk between neighboring organic field-effect transistors (OFETs). Results show that a decreased source/drain interval and gate electrode width can decrease the diffraction distance of the current, and therefore can weaken the crosstalk. In addition, the inherent low carrier concentration in organic semiconductors can create a high-resistance barrier at the space between gate electrodes of neighboring devices, limiting or even eliminating the crosstalk as a result of the gate electrode width being smaller than the source/drain electrode width.

Polymer-free graphene transfer for enhanced reliability of graphene field-effect transistors

International Nuclear Information System (INIS)

Park, Hamin; Park, Ick-Joon; Jung, Dae Yool; Lee, Khang June; Yang, Sang Yoon; Choi, Sung-Yool

2016-01-01

We propose a polymer-free graphene transfer technique for chemical vapor deposition-grown graphene to ensure the intrinsic electrical properties of graphene for reliable transistor applications. The use of a metal catalyst as a supporting layer avoids contamination from the polymer material and graphene films become free of polymer residue after the transfer process. Atomic force microscopy and Raman spectroscopy indicate that the polymer-free transferred graphene shows closer properties to intrinsic graphene properties. The reliability of graphene field-effect transistors (GFETs) was investigated through the analysis of the negative gate bias-stress-induced instability. This work reveals the effect of polymer residues on the reliability of GFETs, and that the developed new polymer-free transfer method enhances the reliability. (letter)

Air-gating and chemical-gating in transistors and sensing devices made from hollow TiO2 semiconductor nanotubes

Science.gov (United States)

Alivov, Yahya; Funke, Hans; Nagpal, Prashant

2015-07-01

Rapid miniaturization of electronic devices down to the nanoscale, according to Moore’s law, has led to some undesirable effects like high leakage current in transistors, which can offset additional benefits from scaling down. Development of three-dimensional transistors, by spatial extension in the third dimension, has allowed higher contact area with a gate electrode and better control over conductivity in the semiconductor channel. However, these devices do not utilize the large surface area and interfaces for new electronic functionality. Here, we demonstrate air gating and chemical gating in hollow semiconductor nanotube devices and highlight the potential for development of novel transistors that can be modulated using channel bias, gate voltage, chemical composition, and concentration. Using chemical gating, we reversibly altered the conductivity of nanoscaled semiconductor nanotubes (10-500 nm TiO2 nanotubes) by six orders of magnitude, with a tunable rectification factor (ON/OFF ratio) ranging from 1-106. While demonstrated air- and chemical-gating speeds were slow here (˜seconds) due to the mechanical-evacuation rate and size of our chamber, the small nanoscale volume of these hollow semiconductors can enable much higher switching speeds, limited by the rate of adsorption/desorption of molecules at semiconductor interfaces. These chemical-gating effects are completely reversible, additive between different chemical compositions, and can enable semiconductor nanoelectronic devices for ‘chemical transistors’, ‘chemical diodes’, and very high-efficiency sensing applications.

Oscillation of Critical Current by Gate Voltage in Cooper Pair Transistor

International Nuclear Information System (INIS)

Kim, N.; Cheong, Y.; Song, W.

2010-01-01

We measured the critical current of a Cooper pair transistor consisting of two Josephson junctions and a gate electrode. The Cooper pair transistors were fabricated by using electron-beam lithography and double-angle evaporation technique. The Gate voltage dependence of critical current was measured by observing voltage jumps at various gate voltages while sweeping bias current. The observed oscillation was 2e-periodic, which shows the Cooper pair transistor had low level of quasiparticle poisoning.

Tunneling field effect transistor technology

CERN Document Server

Chan, Mansun

2016-01-01

This book provides a single-source reference to the state-of-the art in tunneling field effect transistors (TFETs). Readers will learn the TFETs physics from advanced atomistic simulations, the TFETs fabrication process and the important roles that TFETs will play in enabling integrated circuit designs for power efficiency. · Provides comprehensive reference to tunneling field effect transistors (TFETs); · Covers all aspects of TFETs, from device process to modeling and applications; · Enables design of power-efficient integrated circuits, with low power consumption TFETs.

Drying Temperature Dependence of Sol-gel Spin Coated Bilayer Composite ZnO/TiO2 Thin Films for Extended Gate Field Effect Transistor pH Sensor

Science.gov (United States)

Rahman, R. A.; Zulkefle, M. A.; Yusoff, K. A.; Abdullah, W. F. H.; Rusop, M.; Herman, S. H.

2018-03-01

This study presents an investigation on zinc oxide (ZnO) and titanium dioxide (TiO2) bilayer film applied as the sensing membrane for extended-gate field effect transistor (EGFET) for pH sensing application. The influences of the drying temperatures on the pH sensing capability of ZnO/TiO2 were investigated. The sensing performance of the thin films were measured by connecting the thin film to a commercial MOSFET to form the extended gates. By varying the drying temperature, we found that the ZnO/TiO2 thin film dried at 150°C gave the highest sensitivity compared to other drying conditions, with the sensitivity value of 48.80 mV/pH.

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene-graphene composite layers for flexible thin film transistors with a polymer gate dielectric.

Science.gov (United States)

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-02-28

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene-graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene-graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm(2) V(-1) s(-1) and a threshold voltage of -0.7 V at V(gs) = -40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm(2) V(-1) s(-1) and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies.

Lowered operation voltage in Pt/SBi2Ta2O9/HfO2/Si ferroelectric-gate field-effect transistors by oxynitriding Si

International Nuclear Information System (INIS)

Horiuchi, Takeshi; Takahashi, Mitsue; Li, Qiu-Hong; Wang, Shouyu; Sakai, Shigeki

2010-01-01

Oxynitrided Si (SiON) surfaces show smaller subthreshold swings than do directly nitrided Si (SiN) surfaces when used in ferroelectric-gate field-effect transistors (FeFETs) having the following stacked-gate structure: Pt/SrBi 2 Ta 2 O 9 (SBT)/HfO 2 /Si. SiON/Si substrates for FeFETs were prepared by rapid thermal oxidation (RTO) in O 2 at 1000 °C and subsequent rapid thermal nitridation (RTN) in NH 3 at various temperatures in the range 950–1150 °C. The electrical properties of the Pt/SBT/HfO 2 /SiON/Si FeFET were compared with those of reference FETs, i.e. Pt/SBT/HfO 2 gate stacks formed on Si substrates subjected to various treatments: SiN x /Si formed by RTN, SiO 2 /Si formed by RTO and untreated Si. The Pt/SBT/HfO 2 /SiON/Si FeFET had a larger memory window than all the other reference FeFETs, particularly at low operation voltages when the RTN temperature was 1050 °C

Bias-stress characterization of solution-processed organic field-effect transistor based on highly ordered liquid crystals

Science.gov (United States)

Kunii, M.; Iino, H.; Hanna, J.

2017-06-01

Bias-stress effects in solution-processed, 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-10) field effect transistors (FETs) are studied under negative and positive direct current bias. The bottom gate, bottom contact polycrystalline Ph-BTBT-10 FET with a hybrid gate dielectric of polystyrene and SiO2 shows high field effect mobility as well as a steep subthreshold slope when fabricated with a highly ordered smectic E liquid crystalline (SmE) film as a precursor. Negative gate bias-stress causes negative threshold voltage shift (ΔVth) for Ph-BTBT-10 FET in ambient air, but ΔVth rapidly decreases as the gate bias decreases and approaches to near zero when the gate bias goes down to 9 V in amplitude. In contrast, positive gate bias-stress causes negligible ΔVth even with a relatively high bias voltage. These results conclude that Ph-BTBT-10 FET has excellent bias-stress stability in ambient air in the range of low to moderate operating voltages.

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

Science.gov (United States)

Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

2016-01-01

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations

Science.gov (United States)

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-01

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations.

Science.gov (United States)

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-15

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

Temperature Effects on a-IGZO Thin Film Transistors Using HfO2 Gate Dielectric Material

OpenAIRE

Lin, Yu-Hsien; Chou, Jay-Chi

2014-01-01

This study investigated the temperature effect on amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) using hafnium oxide (HfO2) gate dielectric material. HfO2 is an attractive candidate as a high-κ dielectric material for gate oxide because it has great potential to exhibit superior electrical properties with a high drive current. In the process of integrating the gate dielectric and IGZO thin film, postannealing treatment is an essential process for completing the chem...

Comparison of junctionless and inversion-mode p-type metal-oxide-semiconductor field-effect transistors in presence of hole-phonon interactions

Energy Technology Data Exchange (ETDEWEB)

Dib, E., E-mail: elias.dib@for.unipi.it [Dipartimento di Ingegneria dell' Informazione, Università di Pisa, 56122 Pisa (Italy); Carrillo-Nuñez, H. [Integrated Systems Laboratory ETH Zürich, Gloriastrasse 35, 8092 Zürich (Switzerland); Cavassilas, N.; Bescond, M. [IM2NP, UMR CNRS 6242, Bât. IRPHE, Technopôle de Château-Gombert, 13384 Marseille Cedex 13 (France)

2016-01-28

Junctionless transistors are being considered as one of the alternatives to conventional metal-oxide field-effect transistors. In this work, it is then presented a simulation study of silicon double-gated p-type junctionless transistors compared with its inversion-mode counterpart. The quantum transport problem is solved within the non-equilibrium Green's function formalism, whereas hole-phonon interactions are tackled by means of the self-consistent Born approximation. Our findings show that junctionless transistors should perform as good as a conventional transistor only for ultra-thin channels, with the disadvantage of requiring higher supply voltages in thicker channel configurations.

Comparison of junctionless and inversion-mode p-type metal-oxide-semiconductor field-effect transistors in presence of hole-phonon interactions

International Nuclear Information System (INIS)

Dib, E.; Carrillo-Nuñez, H.; Cavassilas, N.; Bescond, M.

2016-01-01

Junctionless transistors are being considered as one of the alternatives to conventional metal-oxide field-effect transistors. In this work, it is then presented a simulation study of silicon double-gated p-type junctionless transistors compared with its inversion-mode counterpart. The quantum transport problem is solved within the non-equilibrium Green's function formalism, whereas hole-phonon interactions are tackled by means of the self-consistent Born approximation. Our findings show that junctionless transistors should perform as good as a conventional transistor only for ultra-thin channels, with the disadvantage of requiring higher supply voltages in thicker channel configurations

Field-Effect Transistors Based on Networks of Highly Aligned, Chemically Synthesized N = 7 Armchair Graphene Nanoribbons.

Science.gov (United States)

Passi, Vikram; Gahoi, Amit; Senkovskiy, Boris V; Haberer, Danny; Fischer, Felix R; Grüneis, Alexander; Lemme, Max C

2018-03-28

We report on the experimental demonstration and electrical characterization of N = 7 armchair graphene nanoribbon (7-AGNR) field effect transistors. The back-gated transistors are fabricated from atomically precise and highly aligned 7-AGNRs, synthesized with a bottom-up approach. The large area transfer process holds the promise of scalable device fabrication with atomically precise nanoribbons. The channels of the FETs are approximately 30 times longer than the average nanoribbon length of 30 nm to 40 nm. The density of the GNRs is high, so that transport can be assumed well-above the percolation threshold. The long channel transistors exhibit a maximum I ON / I OFF current ratio of 87.5.

Investigation of Electronic and Opto-Electronic Properties of Two-Dimensional (2D) Layers of Copper Indium Selenide Field Effect Transistors

Science.gov (United States)

Patil, Prasanna Dnyaneshwar

Investigations performed in order to understand the electronic and optoelectronic properties of field effect transistors based on few layers of 2D Copper Indium Selenide (CuIn7Se11) are reported. In general, field effect transistors (FETs), electric double layer field effect transistors (EDL-FETs), and photodetectors are crucial part of several electronics based applications such as tele-communication, bio-sensing, and opto-electronic industry. After the discovery of graphene, several 2D semiconductor materials like TMDs (MoS2, WS2, and MoSe2 etc.), group III-VI materials (InSe, GaSe, and SnS2 etc.) are being studied rigorously in order to develop them as components in next generation FETs. Traditionally, thin films of ternary system of Copper Indium Selenide have been extensively studied and used in optoelectronics industry as photoactive component in solar cells. Thus, it is expected that atomically thin 2D layered structure of Copper Indium Selenide can have optical properties that could potentially be more advantageous than its thin film counterpart and could find use for developing next generation nano devices with utility in opto/nano electronics. Field effect transistors were fabricated using few-layers of CuIn7Se11 flakes, which were mechanically exfoliated from bulk crystals grown using chemical vapor transport technique. Our FET transport characterization measurements indicate n-type behavior with electron field effect mobility microFE ≈ 36 cm2 V-1 s-1 at room temperature when Silicon dioxide (SiO2) is used as a back gate. We found that in such back gated field effect transistor an on/off ratio of 104 and a subthreshold swing ≈ 1 V/dec can be obtained. Our investigations further indicate that Electronic performance of these materials can be increased significantly when gated from top using an ionic liquid electrolyte [1-Butyl-3-methylimidazolium hexafluorophosphate (BMIM-PF6)]. We found that electron field effect mobility microFE can be increased from

Gate Control Coefficient Effect on CNFET Characteristic

International Nuclear Information System (INIS)

Sanudin, Rahmat; Ma'Radzi, Ahmad Alabqari; Nayan, Nafarizal

2009-01-01

The development of carbon nanotube field-effect transistor (CNFET) as alternative to existing transistor technology has long been published and discussed. The emergence of this device offers new material and structure in building a transistor. This paper intends to do an analysis of gate control coefficient effect on CNFET performance. The analysis is based on simulation study of current-voltage (I-V) characteristic of ballistic CNFET. The simulation study used the MOSFET-like CNFET mathematical model to establish the device output characteristic. Based on the analysis of simulation result, it is found that the gate control coefficient contributes to a significant effect on the performance of CNFET. The result also shown the parameter could help to improve the device performance in terms of its output and response as well. Nevertheless, the characteristic of the carbon nanotube that acts as the channel is totally important in determining the performance of the transistor as a whole.

Large-Area CVD-Grown Sub-2 V ReS2 Transistors and Logic Gates.

Science.gov (United States)

Dathbun, Ajjiporn; Kim, Youngchan; Kim, Seongchan; Yoo, Youngjae; Kang, Moon Sung; Lee, Changgu; Cho, Jeong Ho

2017-05-10

We demonstrated the fabrication of large-area ReS 2 transistors and logic gates composed of a chemical vapor deposition (CVD)-grown multilayer ReS 2 semiconductor channel and graphene electrodes. Single-layer graphene was used as the source/drain and coplanar gate electrodes. An ion gel with an ultrahigh capacitance effectively gated the ReS 2 channel at a low voltage, below 2 V, through a coplanar gate. The contact resistance of the ion gel-gated ReS 2 transistors with graphene electrodes decreased dramatically compared with the SiO 2 -devices prepared with Cr electrodes. The resulting transistors exhibited good device performances, including a maximum electron mobility of 0.9 cm 2 /(V s) and an on/off current ratio exceeding 10 4 . NMOS logic devices, such as NOT, NAND, and NOR gates, were assembled using the resulting transistors as a proof of concept demonstration of the applicability of the devices to complex logic circuits. The large-area synthesis of ReS 2 semiconductors and graphene electrodes and their applications in logic devices open up new opportunities for realizing future flexible electronics based on 2D nanomaterials.

Investigation of Impact of the Gate Circuitry on IGBT Transistor Dynamic Parameters

Directory of Open Access Journals (Sweden)

Vytautas Bleizgys

2011-03-01

Full Text Available The impact of Insulated Gate Bipolar Transistor driver circuit parameters on the rise and fall time of the collector current and voltage collector-emitter was investigated. The influence of transistor driver circuit parameters on heating of Insulated Gate Bipolar Transistors was investigated as well.Article in Lithuanian

Removing the current-limit of vertical organic field effect transistors

Science.gov (United States)

Sheleg, Gil; Greenman, Michael; Lussem, Bjorn; Tessler, Nir

2017-11-01

The reported Vertical Organic Field Effect Transistors (VOFETs) show either superior current and switching speeds or well-behaved transistor performance, especially saturation in the output characteristics. Through the study of the relationship between the device architecture or dimensions and the device performance, we find that achieving a saturation regime in the output characteristics requires that the device operates in the injection limited regime. In current structures, the existence of the injection limited regime depends on the source's injection barrier as well as on the buried semiconductor layer thickness. To overcome the injection limit imposed by the necessity of injection barrier, we suggest a new architecture to realize VOFETs. This architecture shows better gate control and is independent of the injection barrier at the source, thus allowing for several A cm-2 for a semiconductor having a mobility value of 0.1 cm2 V-1 s-1.

Attofarad resolution capacitance-voltage measurement of nanometer scale field effect transistors utilizing ambient noise

International Nuclear Information System (INIS)

Gokirmak, Ali; Inaltekin, Hazer; Tiwari, Sandip

2009-01-01

A high resolution capacitance-voltage (C-V) characterization technique, enabling direct measurement of electronic properties at the nanoscale in devices such as nanowire field effect transistors (FETs) through the use of random fluctuations, is described. The minimum noise level required for achieving sub-aF (10 -18 F) resolution, the leveraging of stochastic resonance, and the effect of higher levels of noise are illustrated through simulations. The non-linear ΔC gate-source/drain -V gate response of FETs is utilized to determine the inversion layer capacitance (C inv ) and carrier mobility. The technique is demonstrated by extracting the carrier concentration and effective electron mobility in a nanoscale Si FET with C inv = 60 aF.

Room Temperature Silicene Field-Effect Transistors

Science.gov (United States)

Akinwande, Deji

Silicene, a buckled Si analogue of graphene, holds significant promise for future electronics beyond traditional CMOS. In our predefined experiments via encapsulated delamination with native electrodes approach, silicene devices exhibit an ambipolar charge transport behavior, corroborating theories on Dirac band in Ag-free silicene. Monolayer silicene device has extracted field-effect mobility within the theoretical expectation and ON/OFF ratio greater than monolayer graphene, while multilayer silicene devices show decreased mobility and gate modulation. Air-stability of silicene devices depends on the number of layers of silicene and intrinsic material structure determined by growth temperature. Few or multi-layer silicene devices maintain their ambipolar behavior for days in contrast to minutes time scale for monolayer counterparts under similar conditions. Multilayer silicene grown at different temperatures below 300oC possess different intrinsic structures and yield different electrical property and air-stability. This work suggests a practical prospect to enable more air-stable silicene devices with layer and growth condition control, which can be leveraged for other air-sensitive 2D materials. In addition, we describe quantum and classical transistor device concepts based on silicene and related buckled materials that exploit the 2D topological insulating phenomenon. The transistor device physics offer the potential for ballistic transport that is robust against scattering and can be employed for both charge and spin transport. This work was supported by the ARO.

Change in carrier type in high-k gate carbon nanotube field-effect transistors by interface fixed charges

International Nuclear Information System (INIS)

Moriyama, N; Ohno, Y; Kitamura, T; Kishimoto, S; Mizutani, T

2010-01-01

We study the phenomenon of change in carrier type in carbon nanotube field-effect transistors (CNFETs) caused by the atomic layer deposition (ALD) of a HfO 2 gate insulator. When a HfO 2 layer is deposited on a CNFET, the type of carrier changes from p-type to n-type. The so-obtained n-type device has good performance and stability in air. The conductivity of such a device with a channel length of 0.7 μm is 11% of the quantum conductance 4e 2 /h. The contact resistance for electron current is estimated to be 14 kΩ. The n-type conduction of this CNFET is maintained for more than 100 days. The change in carrier type is attributed to positive fixed charges introduced at the interface between the HfO 2 and SiO 2 layers. We also propose a novel technique to control the type of conduction by utilizing interface fixed charges; this technique is compatible with Si CMOS process technology.

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene–graphene composite layers for flexible thin film transistors with a polymer gate dielectric

International Nuclear Information System (INIS)

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-01-01

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene–graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene–graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm 2  V −1  s −1 and a threshold voltage of −0.7 V at V gs = −40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm 2  V −1  s −1 and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies. (paper)

First-principles simulations of Graphene/Transition-metal-Dichalcogenides/Graphene Field-Effect Transistor

Science.gov (United States)

Li, Xiangguo; Wang, Yun-Peng; Zhang, X.-G.; Cheng, Hai-Ping

A prototype field-effect transistor (FET) with fascinating properties can be made by assembling graphene and two-dimensional insulating crystals into three-dimensional stacks with atomic layer precision. Transition metal dichalcogenides (TMDCs) such as WS2, MoS2 are good candidates for the atomically thin barrier between two layers of graphene in the vertical FET due to their sizable bandgaps. We investigate the electronic properties of the Graphene/TMDCs/Graphene sandwich structure using first-principles method. We find that the effective tunnel barrier height of the TMDC layers in contact with the graphene electrodes has a layer dependence and can be modulated by a gate voltage. Consequently a very high ON/OFF ratio can be achieved with appropriate number of TMDC layers and a suitable range of the gate voltage. The spin-orbit coupling in TMDC layers is also layer dependent but unaffected by the gate voltage. These properties can be important in future nanoelectronic device designs. DOE/BES-DE-FG02-02ER45995; NERSC.

Field Effect Transistors Using Atomically Thin Layers of Copper Indium Selenide (CuInSe)

Science.gov (United States)

Patil, Prasanna; Ghosh, Sujoy; Wasala, Milinda; Lei, Sidong; Vajtai, Robert; Ajayan, Pulickel; Talapatra, Saikat

We will report fabrication of field-effect transistors (FETs) using few-layers of Copper Indium Selenide (CuInSe) flakes exfoliated from crystals grown using chemical vapor transport technique. Our transport measurements indicate n-type FET with electron mobility µ ~ 3 cm2 V-1 s-1 at room temperature when Silicon dioxide (SiO2) is used as a back gate. Mobility can be further increased significantly when ionic liquid 1-Butyl-3-methylimidazolium hexafluorophosphate (BMIM-PF6) is used as top gate. Similarly subthreshold swing can be further improved from 103 V/dec to 0.55 V/dec by using ionic liquid as a top gate. We also found ON/OFF ratio of ~ 102 for both top and back gate. Comparison between ionic liquid top gate and SiO2 back gate will be presented and discussed. This work is supported by the U.S. Army Research Office through a MURI Grant # W911NF-11-1-0362.

Memristive device based on a depletion-type SONOS field effect transistor

Science.gov (United States)

Himmel, N.; Ziegler, M.; Mähne, H.; Thiem, S.; Winterfeld, H.; Kohlstedt, H.

2017-06-01

State-of-the-art SONOS (silicon-oxide-nitride-oxide-polysilicon) field effect transistors were operated in a memristive switching mode. The circuit design is a variation of the MemFlash concept and the particular properties of depletion type SONOS-transistors were taken into account. The transistor was externally wired with a resistively shunted pn-diode. Experimental current-voltage curves show analog bipolar switching characteristics within a bias voltage range of ±10 V, exhibiting a pronounced asymmetric hysteresis loop. The experimental data are confirmed by SPICE simulations. The underlying memristive mechanism is purely electronic, which eliminates an initial forming step of the as-fabricated cells. This fact, together with reasonable design flexibility, in particular to adjust the maximum R ON/R OFF ratio, makes these cells attractive for neuromorphic applications. The relative large set and reset voltage around ±10 V might be decreased by using thinner gate-oxides. The all-electric operation principle, in combination with an established silicon manufacturing process of SONOS devices at the Semiconductor Foundry X-FAB, promise reliable operation, low parameter spread and high integration density.

Ambipolar organic tri-gate transistor for low-power complementary electronics

NARCIS (Netherlands)

Torricelli, F.; Ghittorelli, M.; Smits, E.C.P.; Roelofs, C.; Janssen, R.A.J.; Gelinck, G.H.; Kovács-Vajna, Z.M.; Cantatore, E.

2016-01-01

Ambipolar transistors typically suffer from large off-current inherently due to ambipolar conduction. Using a tri-gate transistor it is shown that it is possible to electrostatically switch ambipolar polymer transistors from ambipolar to unipolar mode. In unipolar mode, symmetric characteristics

Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

Energy Technology Data Exchange (ETDEWEB)

Chun, Minkyu; Um, Jae Gwang; Park, Min Sang; Chowdhury, Md Delwar Hossain; Jang, Jin, E-mail: jjang@khu.ac.kr [Advanced Display Research Center and Department of Information Display, Kyung Hee University, Seoul 02447 (Korea, Republic of)

2016-07-15

We report the abnormal behavior of the threshold voltage (V{sub TH}) shift under positive bias Temperature stress (PBTS) and negative bias temperature stress (NBTS) at top/bottom gate in dual gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). It is found that the PBTS at top gate shows negative transfer shift and NBTS shows positive transfer shift for both top and bottom gate sweep. The shift of bottom/top gate sweep is dominated by top gate bias (V{sub TG}), while bottom gate bias (V{sub BG}) is less effect than V{sub TG}. The X-ray photoelectron spectroscopy (XPS) depth profile provides the evidence of In metal diffusion to the top SiO{sub 2}/a-IGZO and also the existence of large amount of In{sup +} under positive top gate bias around top interfaces, thus negative transfer shift is observed. On the other hand, the formation of OH{sup −} at top interfaces under the stress of negative top gate bias shows negative transfer shift. The domination of V{sub TG} both on bottom/top gate sweep after PBTS/NBTS is obviously occurred due to thin active layer.

Ferroelectric polymer gates for non-volatile field effect control of ferromagnetism in (Ga, Mn)As layers

International Nuclear Information System (INIS)

Stolichnov, I; Riester, S W E; Mikheev, E; Setter, N; Rushforth, A W; Edmonds, K W; Campion, R P; Foxon, C T; Gallagher, B L; Jungwirth, T; Trodahl, H J

2011-01-01

(Ga, Mn)As and other diluted magnetic semiconductors (DMS) attract a great deal of attention for potential spintronic applications because of the possibility of controlling the magnetic properties via electrical gating. Integration of a ferroelectric gate on the DMS channel adds to the system a non-volatile memory functionality and permits nanopatterning via the polarization domain engineering. This topical review is focused on the multiferroic system, where the ferromagnetism in the (Ga, Mn)As DMS channel is controlled by the non-volatile field effect of the spontaneous polarization. Use of ferroelectric polymer gates in such heterostructures offers a viable alternative to the traditional oxide ferroelectrics generally incompatible with DMS. Here we review the proof-of-concept experiments demonstrating the ferroelectric control of ferromagnetism, analyze the performance issues of the ferroelectric gates and discuss prospects for further development of the ferroelectric/DMS heterostructures toward the multiferroic field effect transistor. (topical review)

Bottom-Up Tri-gate Transistors and Submicrosecond Photodetectors from Guided CdS Nanowalls.

Science.gov (United States)

Xu, Jinyou; Oksenberg, Eitan; Popovitz-Biro, Ronit; Rechav, Katya; Joselevich, Ernesto

2017-11-08

Tri-gate transistors offer better performance than planar transistors by exerting additional gate control over a channel from two lateral sides of semiconductor nanowalls (or "fins"). Here we report the bottom-up assembly of aligned CdS nanowalls by a simultaneous combination of horizontal catalytic vapor-liquid-solid growth and vertical facet-selective noncatalytic vapor-solid growth and their parallel integration into tri-gate transistors and photodetectors at wafer scale (cm 2 ) without postgrowth transfer or alignment steps. These tri-gate transistors act as enhancement-mode transistors with an on/off current ratio on the order of 10 8 , 4 orders of magnitude higher than the best results ever reported for planar enhancement-mode CdS transistors. The response time of the photodetector is reduced to the submicrosecond level, 1 order of magnitude shorter than the best results ever reported for photodetectors made of bottom-up semiconductor nanostructures. Guided semiconductor nanowalls open new opportunities for high-performance 3D nanodevices assembled from the bottom up.

Top-gated chemical vapor deposition grown graphene transistors with current saturation.

Science.gov (United States)

Bai, Jingwei; Liao, Lei; Zhou, Hailong; Cheng, Rui; Liu, Lixin; Huang, Yu; Duan, Xiangfeng

2011-06-08

Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.

Theoretical study of phosphorene tunneling field effect transistors

International Nuclear Information System (INIS)

Chang, Jiwon; Hobbs, Chris

2015-01-01

In this work, device performances of tunneling field effect transistors (TFETs) based on phosphorene are explored via self-consistent atomistic quantum transport simulations. Phosphorene is an ultra-thin two-dimensional (2-D) material with a direct band gap suitable for TFETs applications. Our simulation shows that phosphorene TFETs exhibit subthreshold slope below 60 mV/dec and a wide range of on-current depending on the transport direction due to highly anisotropic band structures of phosphorene. By benchmarking with monolayer MoTe 2 TFETs, we predict that phosphorene TFETs oriented in the small effective mass direction can yield much larger on-current at the same on-current/off-current ratio than monolayer MoTe 2 TFETs. It is also observed that a gate underlap structure is required for scaling down phosphorene TFETs in the small effective mass direction to suppress the source-to-drain direct tunneling leakage current

Theoretical study of phosphorene tunneling field effect transistors

Energy Technology Data Exchange (ETDEWEB)

Chang, Jiwon; Hobbs, Chris [SEMATECH, 257 Fuller Rd #2200, Albany, New York 12203 (United States)

2015-02-23

In this work, device performances of tunneling field effect transistors (TFETs) based on phosphorene are explored via self-consistent atomistic quantum transport simulations. Phosphorene is an ultra-thin two-dimensional (2-D) material with a direct band gap suitable for TFETs applications. Our simulation shows that phosphorene TFETs exhibit subthreshold slope below 60 mV/dec and a wide range of on-current depending on the transport direction due to highly anisotropic band structures of phosphorene. By benchmarking with monolayer MoTe{sub 2} TFETs, we predict that phosphorene TFETs oriented in the small effective mass direction can yield much larger on-current at the same on-current/off-current ratio than monolayer MoTe{sub 2} TFETs. It is also observed that a gate underlap structure is required for scaling down phosphorene TFETs in the small effective mass direction to suppress the source-to-drain direct tunneling leakage current.

High-frequency self-aligned graphene transistors with transferred gate stacks

Science.gov (United States)

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-01-01

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra–high-frequency circuits. PMID:22753503

Modeling quantization effects in field effect transistors

International Nuclear Information System (INIS)

Troger, C.

2001-06-01

Numerical simulation in the field of semiconductor device development advanced to a valuable, cost-effective and flexible facility. The most widely used simulators are based on classical models, as they need to satisfy time and memory constraints. To improve the performance of field effect transistors such as MOSFETs and HEMTs these devices are continuously scaled down in their dimensions. Consequently the characteristics of such devices are getting more and more determined by quantum mechanical effects arising from strong transversal fields in the channel. In this work an approach based on a two-dimensional electron gas is used to describe the confinement of the carriers. Quantization is considered in one direction only. For the derivation of a one-dimensional Schroedinger equation in the effective mass framework a non-parabolic correction for the energy dispersion due to Kane is included. For each subband a non-parabolic dispersion relation characterized by subband masses and subband non-parabolicity coefficients is introduced and the parameters are calculated via perturbation theory. The method described in this work has been implemented in a software tool that performs a self-consistent solution of Schroedinger- and Poisson-equation for a one-dimensional cut through a MOS structure or heterostructure. The calculation of the carrier densities is performed assuming Fermi-Dirac statistics. In the case of a MOS structure a metal or a polysilicon gate is considered and an arbitrary gate bulk voltage can be applied. This allows investigating quantum mechanical effects in capacity calculations, to compare the simulated data with measured CV curves and to evaluate the results obtained with a quantum mechanical correction for the classical electron density. The behavior of the defined subband parameters is compared to the value of the mass and the non-parabolicity coefficient from the model due to Kane. Finally the presented characterization of the subbands is applied

Quantum ballistic analysis of transition metal dichalcogenides based double gate junctionless field effect transistor and its application in nano-biosensor

Science.gov (United States)

Shadman, Abir; Rahman, Ehsanur; Khosru, Quazi D. M.

2017-11-01

To reduce the thermal budget and the short channel effects in state of the art CMOS technology, Junctionless field effect transistor (JLFET) has been proposed in the literature. Numerous experimental, modeling, and simulation based works have been done on this new FET with bulk materials for various geometries until now. On the other hand, the two-dimensional layered material is considered as an alternative to current Si technology because of its ultra-thin body and high mobility. Very recently few simulation based works have been done on monolayer molybdenum disulfide based JLFET mainly to show the advantage of JLFET over conventional FET. However, no comprehensive simulation-based work has been done for double gate JLFET keeping in mind the prominent transition metal dichalcogenides (TMDC) to the authors' best knowledge. In this work, we have studied quantum ballistic drain current-gate voltage characteristics of such FETs within non-equilibrium Green's function (NEGF) framework. Our simulation results reveal that all these TMDC materials are viable options for implementing state of the art Junctionless MOSFET with emphasis on their performance at short gate lengths. Besides evaluating the prospect of TMDC materials in the digital logic application, the performance of Junctionless Double Gate trilayer TMDC heterostructure FET for the label-free electrical detection of biomolecules in dry environment has been investigated for the first time to the authors' best knowledge. The impact of charge neutral biomolecules on the electrical characteristics of the biosensor has been analyzed under dry environment situation. Our study shows that these materials could provide high sensitivity in the sub-threshold region as a channel material in nano-biosensor, a trend demonstrated by silicon on insulator FET sensor in the literature. Thus, going by the trend of replacing silicon with these novel materials in device level, TMDC heterostructure could be a viable alternative to

Coherent molecular transistor: control through variation of the gate wave function.

Science.gov (United States)

Ernzerhof, Matthias

2014-03-21

In quantum interference transistors (QUITs), the current through the device is controlled by variation of the gate component of the wave function that interferes with the wave function component joining the source and the sink. Initially, mesoscopic QUITs have been studied and more recently, QUITs at the molecular scale have been proposed and implemented. Typically, in these devices the gate lead is subjected to externally adjustable physical parameters that permit interference control through modifications of the gate wave function. Here, we present an alternative model of a molecular QUIT in which the gate wave function is directly considered as a variable and the transistor operation is discussed in terms of this variable. This implies that we specify the gate current as well as the phase of the gate wave function component and calculate the resulting current through the source-sink channel. Thus, we extend on prior works that focus on the phase of the gate wave function component as a control parameter while having zero or certain discrete values of the current. We address a large class of systems, including finite graphene flakes, and obtain analytic solutions for how the gate wave function controls the transistor.

Coherent molecular transistor: Control through variation of the gate wave function

International Nuclear Information System (INIS)

Ernzerhof, Matthias

2014-01-01

In quantum interference transistors (QUITs), the current through the device is controlled by variation of the gate component of the wave function that interferes with the wave function component joining the source and the sink. Initially, mesoscopic QUITs have been studied and more recently, QUITs at the molecular scale have been proposed and implemented. Typically, in these devices the gate lead is subjected to externally adjustable physical parameters that permit interference control through modifications of the gate wave function. Here, we present an alternative model of a molecular QUIT in which the gate wave function is directly considered as a variable and the transistor operation is discussed in terms of this variable. This implies that we specify the gate current as well as the phase of the gate wave function component and calculate the resulting current through the source-sink channel. Thus, we extend on prior works that focus on the phase of the gate wave function component as a control parameter while having zero or certain discrete values of the current. We address a large class of systems, including finite graphene flakes, and obtain analytic solutions for how the gate wave function controls the transistor

The Complete Semiconductor Transistor and Its Incomplete Forms

International Nuclear Information System (INIS)

Jie Binbin; Sah, C.-T.

2009-01-01

This paper describes the definition of the complete transistor. For semiconductor devices, the complete transistor is always bipolar, namely, its electrical characteristics contain both electron and hole currents controlled by their spatial charge distributions. Partially complete or incomplete transistors, via coined names or/and designed physical geometries, included the 1949 Shockley p/n junction transistor (later called Bipolar Junction Transistor, BJT), the 1952 Shockley unipolar 'field-effect' transistor (FET, later called the p/n Junction Gate FET or JGFET), as well as the field-effect transistors introduced by later investigators. Similarities between the surface-channel MOS-gate FET (MOSFET) and the volume-channel BJT are illustrated. The bipolar currents, identified by us in a recent nanometer FET with 2-MOS-gates on thin and nearly pure silicon base, led us to the recognition of the physical makeup and electrical current and charge compositions of a complete transistor and its extension to other three or more terminal signal processing devices, and also the importance of the terminal contacts.

Polymer-electrolyte-gated nanowire synaptic transistors for neuromorphic applications

Science.gov (United States)

Zou, Can; Sun, Jia; Gou, Guangyang; Kong, Ling-An; Qian, Chuan; Dai, Guozhang; Yang, Junliang; Guo, Guang-hua

2017-09-01

Polymer-electrolytes are formed by dissolving a salt in polymer instead of water, the conducting mechanism involves the segmental motion-assisted diffusion of ion in the polymer matrix. Here, we report on the fabrication of tin oxide (SnO2) nanowire synaptic transistors using polymer-electrolyte gating. A thin layer of poly(ethylene oxide) and lithium perchlorate (PEO/LiClO4) was deposited on top of the devices, which was used to boost device performances. A voltage spike applied on the in-plane gate attracts ions toward the polymer-electrolyte/SnO2 nanowire interface and the ions are gradually returned after the pulse is removed, which can induce a dynamic excitatory postsynaptic current in the nanowire channel. The SnO2 synaptic transistors exhibit the behavior of short-term plasticity like the paired-pulse facilitation and self-adaptation, which is related to the electric double-effect regulation. In addition, the synaptic logic functions and the logical function transformation are also discussed. Such single SnO2 nanowire-based synaptic transistors are of great importance for future neuromorphic devices.

Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

KAUST Repository

Salas-Villasenor, A. L.; Mejia, I.; Hovarth, J.; Alshareef, Husam N.; Cha, D. K.; Ramirez-Bon, R.; Gnade, B. E.; Quevedo-Lopez, M. A.

2010-01-01

Cadmium sulfide thin film transistors were demonstrated as the n-type device for use in flexible electronics. CdS thin films were deposited by chemical bath deposition (70° C) on either 100 nm HfO2 or SiO2 as the gate dielectrics. Common gate transistors with channel lengths of 40-100 μm were fabricated with source and drain aluminum top contacts defined using a shadow mask process. No thermal annealing was performed throughout the device process. X-ray diffraction results clearly show the hexagonal crystalline phase of CdS. The electrical performance of HfO 2 /CdS -based thin film transistors shows a field effect mobility and threshold voltage of 25 cm2 V-1 s-1 and 2 V, respectively. Improvement in carrier mobility is associated with better nucleation and growth of CdS films deposited on HfO2. © 2010 The Electrochemical Society.

Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

KAUST Repository

Salas-Villasenor, A. L.

2010-06-29

Cadmium sulfide thin film transistors were demonstrated as the n-type device for use in flexible electronics. CdS thin films were deposited by chemical bath deposition (70° C) on either 100 nm HfO2 or SiO2 as the gate dielectrics. Common gate transistors with channel lengths of 40-100 μm were fabricated with source and drain aluminum top contacts defined using a shadow mask process. No thermal annealing was performed throughout the device process. X-ray diffraction results clearly show the hexagonal crystalline phase of CdS. The electrical performance of HfO 2 /CdS -based thin film transistors shows a field effect mobility and threshold voltage of 25 cm2 V-1 s-1 and 2 V, respectively. Improvement in carrier mobility is associated with better nucleation and growth of CdS films deposited on HfO2. © 2010 The Electrochemical Society.

Sub-50 nm gate length SOI transistor development for high performance microprocessors

International Nuclear Information System (INIS)

Horstmann, M.; Greenlaw, D.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, R. van; Grasshoff, G.; Schwan, C.; Cheek, J.; Buller, J.; Krishnan, S.; Raab, M.; Kepler, N.

2004-01-01

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI

In-situ doped junctionless polysilicon nanowires field effect transistors for low-cost biosensors

Directory of Open Access Journals (Sweden)

Azeem Zulfiqar

2017-04-01

Full Text Available Silicon nanowire (SiNW field effect transistor based biosensors have already been proven to be a promising tool to detect biomolecules. However, the most commonly used fabrication techniques involve expensive Silicon-On-Insulator (SOI wafers, E-beam lithography and ion-implantation steps. In the work presented here, a top down approach to fabricate SiNW junctionless field effect biosensors using novel in-situ doped polysilicon is demonstrated. The p-type polysilicon is grown with an optimum boron concentration that gives a good metal-silicon electrical contact while maintaining the doping level at a low enough level to provide a good sensitivity for the biosensor. The silicon nanowires are patterned using standard photolithography and a wet etch method. The metal contacts are made from magnetron sputtered TiW and e-beam evaporation of gold. The passivation of electrodes has been done by sputtered Si3N4 which is patterned by a lift-off process. The characterization of the critical fabrication steps is done by Secondary Ion Mass Spectroscopy (SIMS and by statistical analysis of the measurements made on the width of the SiNWs. The electrical characterization of the SiNW in air is done by sweeping the back gate voltage while keeping the source drain potential to a constant value and surface characterization is done by applying liquid gate in phosphate buffered saline (PBS solution. The fabricated SiNWs sensors functionalized with (3-aminopropyltriethoxysilane (APTES have demonstrated good sensitivity in detecting different pH buffer solutions. Keywords: In-situ doped, Polysilicon nanowire, Field effect transistor, Biosensor

Tunnel Field-Effect Transistors in 2-D Transition Metal Dichalcogenide Materials

Science.gov (United States)

Ilatikhameneh, Hesameddin; Tan, Yaohua; Novakovic, Bozidar; Klimeck, Gerhard; Rahman, Rajib; Appenzeller, Joerg

2015-12-01

In this work, the performance of Tunnel Field-Effect Transistors (TFETs) based on two-dimensional Transition Metal Dichalcogenide (TMD) materials is investigated by atomistic quantum transport simulations. One of the major challenges of TFETs is their low ON-currents. 2D material based TFETs can have tight gate control and high electric fields at the tunnel junction, and can in principle generate high ON-currents along with a sub-threshold swing smaller than 60 mV/dec. Our simulations reveal that high performance TMD TFETs, not only require good gate control, but also rely on the choice of the right channel material with optimum band gap, effective mass and source/drain doping level. Unlike previous works, a full band atomistic tight binding method is used self-consistently with 3D Poisson equation to simulate ballistic quantum transport in these devices. The effect of the choice of TMD material on the performance of the device and its transfer characteristics are discussed. Moreover, the criteria for high ON-currents are explained with a simple analytic model, showing the related fundamental factors. Finally, the subthreshold swing and energy-delay of these TFETs are compared with conventional CMOS devices.

Nanometer size field effect transistors for terahertz detectors

International Nuclear Information System (INIS)

Knap, W; Rumyantsev, S; Coquillat, D; Dyakonova, N; Teppe, F; Vitiello, M S; Tredicucci, A; Blin, S; Shur, M; Nagatsuma, T

2013-01-01

Nanometer size field effect transistors can operate as efficient resonant or broadband terahertz detectors, mixers, phase shifters and frequency multipliers at frequencies far beyond their fundamental cut-off frequency. This work is an overview of some recent results concerning the application of nanometer scale field effect transistors for the detection of terahertz radiation. (paper)

Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window

Science.gov (United States)

Kino, Hisashi; Fukushima, Takafumi; Tanaka, Tetsu

2018-04-01

Charge-trapping memory requires the increase of bit density per cell and a larger memory window for lower-power operation. A tunnel field-effect transistor (TFET) can achieve to increase the bit density per cell owing to its steep subthreshold slope. In addition, a TFET structure has an asymmetric structure, which is promising for achieving a larger memory window. A TFET with the N-type gate shows a higher electric field between the P-type source and the N-type gate edge than the conventional FET structure. This high electric field enables large amounts of charges to be injected into the charge storage layer. In this study, we fabricated silicon-oxide-nitride-oxide-semiconductor (SONOS) memory devices with the TFET structure and observed a steep subthreshold slope and a larger memory window.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

Science.gov (United States)

Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

Enzyme-polyelectrolyte multilayer assemblies on reduced graphene oxide field-effect transistors for biosensing applications.

Science.gov (United States)

Piccinini, Esteban; Bliem, Christina; Reiner-Rozman, Ciril; Battaglini, Fernando; Azzaroni, Omar; Knoll, Wolfgang

2017-06-15

We present the construction of layer-by-layer (LbL) assemblies of polyethylenimine and urease onto reduced-graphene-oxide based field-effect transistors (rGO FETs) for the detection of urea. This versatile biosensor platform simultaneously exploits the pH dependency of liquid-gated graphene-based transistors and the change in the local pH produced by the catalyzed hydrolysis of urea. The use of an interdigitated microchannel resulted in transistors displaying low noise, high pH sensitivity (20.3µA/pH) and transconductance values up to 800 µS. The modification of rGO FETs with a weak polyelectrolyte improved the pH response because of its transducing properties by electrostatic gating effects. In the presence of urea, the urease-modified rGO FETs showed a shift in the Dirac point due to the change in the local pH close to the graphene surface. Markedly, these devices operated at very low voltages (less than 500mV) and were able to monitor urea in the range of 1-1000µm, with a limit of detection (LOD) down to 1µm, fast response and good long-term stability. The urea-response of the transistors was enhanced by increasing the number of bilayers due to the increment of the enzyme surface coverage onto the channel. Moreover, quantification of the heavy metal Cu 2+ (with a LOD down to 10nM) was performed in aqueous solution by taking advantage of the urease specific inhibition. Copyright © 2016 The Authors. Published by Elsevier B.V. All rights reserved.

Gate-bias controlled charge trapping as a mechanism for NO2 detection with field-effect transistors

NARCIS (Netherlands)

Andringa, A.-M.; Meijboom, J.R.; Smits, E.C.P.; Mathijssen, S.G.J.; Blom, P.W.M.; Leeuw, D.M. de

2011-01-01

Detection of nitrogen dioxide, NO2, is required to monitor the air-quality for human health and safety. Commercial sensors are typically chemiresistors, however field-effect transistors are being investigated. Although numerous investigations have been reported, the NO2 sensing mechanism is not

Effective mass approximation versus full atomistic model to calculate the output characteristics of a gate-all-around germanium nanowire field effect transistor (GAA-GeNW-FET)

Science.gov (United States)

Bayani, Amir Hossein; Voves, Jan; Dideban, Daryoosh

2018-01-01

Here, we compare the output characteristics of a gate-all-around germanium nanowire field effect transistor (GAA-GeNW-FET) with 2.36 nm2 square cross-section area using tight-binding (TB) sp3d5s∗ model (full atomistic model (FAM)) and effective mass approximation (EMA). Synopsys/QuantumWise Atomistix ToolKit (ATK) and Silvaco Atlas3D are used to consider the TB model and EMA, respectively. Results show that EMA predicted only one quantum state (QS) for quantum transport, whereas FAM predicted three QSs. A cosine function behavior is obtained by both methods for the first quantum state. The calculated bandgap value by EMA is almost twice smaller than that of the FAM. Also, a fluctuating current is predicted by both methods but in different oscillation values.

In situ monitoring of myenteric neuron activity using acetylcholinesterase-modified AlGaN/GaN solution-gate field-effect transistors.

Science.gov (United States)

Müntze, Gesche Mareike; Pouokam, Ervice; Steidle, Julia; Schäfer, Wladimir; Sasse, Alexander; Röth, Kai; Diener, Martin; Eickhoff, Martin

2016-03-15

The response characteristics of acetylcholinesterase-modified AlGaN/GaN solution-gate field-effect transistors (AcFETs) are quantitatively analyzed by means of a kinetic model. The characterization shows that the covalent enzyme immobilization process yields reproducible AcFET characteristics with a Michaelis constant KM of (122 ± 4) μM for the immobilized enzyme layer. The increase of KM by a factor of 2.4 during the first four measurement cycles is attributed to partial denaturation of the enzyme. The AcFETs were used to record the release of acetylcholine (ACh) by neuronal tissue cultivated on the gate area upon stimulation by rising the extracellular K(+) concentration. The neuronal tissue constituted of isolated myenteric neurons from four to 12 days old Wistar rats, or sections from the muscularis propria containing the myenteric plexus from adult rats. For both cases the AcFET response was demonstrated to be related to the activity of the immobilized acetylcholinesterase using the reversible acetylcholinesterase blocker donepezil. A concentration response curve of this blocking agent revealed a half maximal inhibitory concentration of 40 nM which is comparable to values measured by complementary in vitro methods. Copyright © 2015 Elsevier B.V. All rights reserved.

Homostructured ZnO-based metal-oxide-semiconductor field-effect transistors deposited at low temperature by vapor cooling condensation system

Energy Technology Data Exchange (ETDEWEB)

Lin, Tzu-Shun [Institute of Nanotechnology and Microsystems Engineering, National Cheng Kung University, 701 Tainan, Taiwan, ROC (China); Lee, Ching-Ting, E-mail: ctlee@ee.ncku.edu.tw [Institute of Nanotechnology and Microsystems Engineering, National Cheng Kung University, 701 Tainan, Taiwan, ROC (China); Institute of Microelectronics, Department of Electrical Engineering, Advanced Optoelectronic Technology Center, National Cheng Kung University, 701 Tainan, Taiwan, ROC (China)

2015-11-01

Highlights: • The vapor cooling condensation system was designed and used to deposit homostructured ZnO-based metal-oxide-semiconductor field-effect transistors. • The resulting homostructured ZnO-based MOSFETs operated at a reverse voltage of −6 V had a very low gate leakage current of 24 nA. • The associated I{sub DSS} and the g{sub m(max)} were 5.64 mA/mm and 1.31 mS/mm, respectively. - Abstract: The vapor cooling condensation system was designed and used to deposit homostructured ZnO-based metal-oxide-semiconductor field-effect transistors (MOSFETs) on sapphire substrates. Owing to the high quality of the deposited, various ZnO films and interfaces, the resulting MOSFETs manifested attractive characteristics, such as the low gate leakage current of 24 nA, the low average interface state density of 2.92 × 10{sup 11} cm{sup −2} eV{sup −1}, and the complete pinch-off performance. The saturation drain–source current, the maximum transconductance, and the gate voltage swing of the resulting homostructured ZnO-based MOSFETs were 5.64 mA/mm, 1.31 mS/mm, and 3.2 V, respectively.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

OpenAIRE

Roeckerath, M.; Lopes, J. M. J.; Durgun Özben, E.; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D.G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of < 1 nA/cm(2). Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated ...

Self-aligned top-gate InGaZnO thin film transistors using SiO{sub 2}/Al{sub 2}O{sub 3} stack gate dielectric

Energy Technology Data Exchange (ETDEWEB)

Chen, Rongsheng; Zhou, Wei; Zhang, Meng; Wong, Man; Kwok, Hoi Sing

2013-12-02

Self-aligned top-gate amorphous indium–gallium–zinc oxide (a-IGZO) thin film transistors (TFTs) utilizing SiO{sub 2}/Al{sub 2}O{sub 3} stack thin films as gate dielectric are developed in this paper. Due to high quality of the high-k Al{sub 2}O{sub 3} and good interface between active layer and gate dielectric, the resulting a-IGZO TFT exhibits good electrical performance including field-effect mobility of 9 cm{sup 2}/Vs, threshold voltage of 2.2 V, subthreshold swing of 0.2 V/decade, and on/off current ratio of 1 × 10{sup 7}. With scaling down of the channel length, good characteristics are also obtained with a small shift of the threshold voltage and no degradation of subthreshold swing. - Highlights: • Self-aligned top-gate indium–gallium–zinc oxide thin-film transistor is proposed. • SiO{sub 2}/Al{sub 2}O{sub 3} stack gate dielectric is proposed. • The source/drain areas are hydrogen-doped by CHF{sub 3} plasma. • The devices show good electrical performance and scaling down behavior.

Tungsten trioxide as high-{kappa} gate dielectric for highly transparent and temperature-stable zinc-oxide-based thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Lorenz, Michael; Wenckstern, Holger von; Grundmann, Marius [Universitaet Leipzig, Fakultaet fuer Physik und Geowissenschaften, Institut fuer Experimentelle Physik II, Linnestr. 5, 04103 Leipzig (Germany)

2012-07-01

We demonstrate metal-insulator-semiconductor field-effect transistors with high-{kappa}, room-temperature deposited, highly transparent tungsten trioxide (WO{sub 3}) as gate dielectric. The channel material consists of a zinc oxide (ZnO) thin-film. The transmittance and resistivity of WO{sub 3} films was tuned in order to obtain a highly transparent and insulating WO{sub 3} dielectric. The devices were processed by standard photolithography using lift-off technique. On top of the WO{sub 3} dielectric a highly transparent and conductive oxide consisting of ZnO: Al 3% wt. was deposited. The gate structure of the devices exhibits an average transmittance in the visible spectral range of 86%. The on/off-current ratio is larger than 10{sup 8} with off- and gate leakage-currents below 3 x 10{sup -8} A/cm{sup 2}. Due to the high relative permittivity of {epsilon}{sub r} {approx} 70, a gate voltage sweep of only 2 V is necessary to turn the transistor on and off with a minimum subthreshold swing of 80 mV/decade. The channel mobility of the transistors equals the Hall-effect mobility with a value of 5 cm{sup 2}/Vs. It is furthermore shown, that the devices are stable up to operating temperatures of at least 150 C.

Dithiopheneindenofluorene (TIF) Semiconducting Polymers with Very High Mobility in Field-Effect Transistors

KAUST Repository

Chen, Hu

2017-07-19

The charge-carrier mobility of organic semiconducting polymers is known to be enhanced when the energetic disorder of the polymer is minimized. Fused, planar aromatic ring structures contribute to reducing the polymer conformational disorder, as demonstrated by polymers containing the indacenodithiophene (IDT) repeat unit, which have both a low Urbach energy and a high mobility in thin-film-transistor (TFT) devices. Expanding on this design motif, copolymers containing the dithiopheneindenofluorene repeat unit are synthesized, which extends the fused aromatic structure with two additional phenyl rings, further rigidifying the polymer backbone. A range of copolymers are prepared and their electrical properties and thin-film morphology evaluated, with the co-benzothiadiazole polymer having a twofold increase in hole mobility when compared to the IDT analog, reaching values of almost 3 cm2 V−1 s−1 in bottom-gate top-contact organic field-effect transistors.

Dual-Material Gate Approach to Suppression of Random-Dopant-Induced Characteristic Fluctuation in 16 nm Metal-Oxide-Semiconductor Field-Effect-Transistor Devices

Science.gov (United States)

Li, Yiming; Lee, Kuo-Fu; Yiu, Chun-Yen; Chiu, Yung-Yueh; Chang, Ru-Wei

2011-04-01

In this work, we explore for the first time dual-material gate (DMG) and inverse DMG devices for suppressing the random-dopant (RD)-induced characteristic fluctuation in 16 nm metal-oxide-semiconductor field-effect-transistor (MOSFET) devices. The physical mechanism of suppressing the characteristic fluctuation of DMG devices is observed and discussed. The achieved improvement in suppressing the RD-induced threshold voltage, on-state current, and off-state current fluctuations are 28, 12.3, and 59%, respectively. To further suppress the fluctuations, an approach that combines the DMG method and channel-doping-profile engineering is also advanced and explored. The results of our study show that among the suppression techniques, the use of the DMG device with an inverse lateral asymmetric channel-doping-profile has good immunity to fluctuation.

Dynamic response of carbon nanotube field-effect transistors analyzed by S-parameters measurement

International Nuclear Information System (INIS)

Bethoux, J.-M.; Happy, H.; Dambrine, G.; Derycke, V.; Goffman, M.; Bourgoin, J.-P.

2006-01-01

Carbon nanotube field-effect transistors (CN-FET) with a metallic back gate have been fabricated. By assembling a number of CNs in parallel, driving currents in the mA range have been obtained. The dynamic response of the CN-FETs has been investigated through S-parameters measurements. A current gain (|H 21 | 2 ) cut-off frequency (f t ) of 8 GHz, and a maximum stable gain (MSG) value of 10 dB at 1 GHz have been obtained. The extraction of an equivalent circuit is proposed

Impact of device engineering on analog/RF performances of tunnel field effect transistors

Science.gov (United States)

Vijayvargiya, V.; Reniwal, B. S.; Singh, P.; Vishvakarma, S. K.

2017-06-01

The tunnel field effect transistor (TFET) and its analog/RF performance is being aggressively studied at device architecture level for low power SoC design. Therefore, in this paper we have investigated the influence of the gate-drain underlap (UL) and different dielectric materials for the spacer and gate oxide on DG-TFET (double gate TFET) and its analog/RF performance for low power applications. Here, it is found that the drive current behavior in DG-TFET with a UL feature while implementing dielectric material for the spacer is different in comparison to that of DG-FET. Further, hetero gate dielectric-based DG-TFET (HGDG-TFET) is more resistive against drain-induced barrier lowering (DIBL) as compared to DG-TFET with high-k (HK) gate dielectric. Along with that, as compared to DG-FET, this paper also analyses the attributes of UL and dielectric material on analog/RF performance of DG-TFET in terms of transconductance (gm ), transconductance generation factor (TGF), capacitance, intrinsic resistance (Rdcr), cut-off frequency (F T), and maximum oscillation frequency (F max). The LK spacer-based HGDG-TFET with a gate-drain UL has the potential to improve the RF performance of device.

Nanosecond Time-Resolved Microscopic Gate-Modulation Imaging of Polycrystalline Organic Thin-Film Transistors

Science.gov (United States)

Matsuoka, Satoshi; Tsutsumi, Jun'ya; Matsui, Hiroyuki; Kamata, Toshihide; Hasegawa, Tatsuo

2018-02-01

We develop a time-resolved microscopic gate-modulation (μ GM ) imaging technique to investigate the temporal evolution of the channel current and accumulated charges in polycrystalline pentacene thin-film transistors (TFTs). A time resolution of as high as 50 ns is achieved by using a fast image-intensifier system that could amplify a series of instantaneous optical microscopic images acquired at various time intervals after the stepped gate bias is switched on. The differential images obtained by subtracting the gate-off image allows us to acquire a series of temporal μ GM images that clearly show the gradual propagation of both channel charges and leaked gate fields within the polycrystalline channel layers. The frontal positions for the propagations of both channel charges and leaked gate fields coincide at all the time intervals, demonstrating that the layered gate dielectric capacitors are successively transversely charged up along the direction of current propagation. The initial μ GM images also indicate that the electric field effect is originally concentrated around a limited area with a width of a few micrometers bordering the channel-electrode interface, and that the field intensity reaches a maximum after 200 ns and then decays. The time required for charge propagation over the whole channel region with a length of 100 μ m is estimated at about 900 ns, which is consistent with the measured field-effect mobility and the temporal-response model for organic TFTs. The effect of grain boundaries can be also visualized by comparison of the μ GM images for the transient and the steady states, which confirms that the potential barriers at the grain boundaries cause the transient shift in the accumulated charges or the transient accumulation of additional charges around the grain boundaries.

Fabrication and characterization of V-gate AlGaN/GaN high-electron-mobility transistors

International Nuclear Information System (INIS)

Zhang Kai; Cao Meng-Yi; Chen Yong-He; Yang Li-Yuan; Wang Chong; Ma Xiao-Hua; Hao Yue

2013-01-01

V-gate GaN high-electron-mobility transistors (HEMTs) are fabricated and investigated systematically. A V-shaped recess geometry is obtained using an improved Si 3 N 4 recess etching technology. Compared with standard HEMTs, the fabricated V-gate HEMTs exhibit a 17% higher peak extrinsic transconductance due to a narrowed gate foot. Moreover, both the gate leakage and current dispersion are dramatically suppressed simultaneously, although a slight degradation of frequency response is observed. Based on a two-dimensional electric field simulation using Silvaco “ATLAS” for both standard HEMTs and V-gate HEMTs, the relaxation in peak electric field at the gate edge is identified as the predominant factor leading to the superior performance of V-gate HEMTs. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Field-effect transistors as electrically controllable nonlinear rectifiers for the characterization of terahertz pulses

Science.gov (United States)

Lisauskas, Alvydas; Ikamas, Kestutis; Massabeau, Sylvain; Bauer, Maris; ČibiraitÄ--, DovilÄ--; Matukas, Jonas; Mangeney, Juliette; Mittendorff, Martin; Winnerl, Stephan; Krozer, Viktor; Roskos, Hartmut G.

2018-05-01

We propose to exploit rectification in field-effect transistors as an electrically controllable higher-order nonlinear phenomenon for the convenient monitoring of the temporal characteristics of THz pulses, for example, by autocorrelation measurements. This option arises because of the existence of a gate-bias-controlled super-linear response at sub-threshold operation conditions when the devices are subjected to THz radiation. We present measurements for different antenna-coupled transistor-based THz detectors (TeraFETs) employing (i) AlGaN/GaN high-electron-mobility and (ii) silicon CMOS field-effect transistors and show that the super-linear behavior in the sub-threshold bias regime is a universal phenomenon to be expected if the amplitude of the high-frequency voltage oscillations exceeds the thermal voltage. The effect is also employed as a tool for the direct determination of the speed of the intrinsic TeraFET response which allows us to avoid limitations set by the read-out circuitry. In particular, we show that the build-up time of the intrinsic rectification signal of a patch-antenna-coupled CMOS detector changes from 20 ps in the deep sub-threshold voltage regime to below 12 ps in the vicinity of the threshold voltage.

N-channel thin-film transistors based on 1,4,5,8-naphthalene tetracarboxylic dianhydride with ultrathin polymer gate buffer layer

International Nuclear Information System (INIS)

Tanida, Shinji; Noda, Kei; Kawabata, Hiroshi; Matsushige, Kazumi

2009-01-01

N-channel operation of thin-film transistors based on 1,4,5,8-naphthalene tetracarboxylic dianhydride (NTCDA) with a 9-nm-thick poly(methyl methacrylate) (PMMA) gate buffer layer was examined. The uniform coverage of the ultrathin PMMA layer on an SiO 2 gate insulator, verified by X-ray reflectivity measurement, caused the increase of electron field-effect mobility because of the suppression of electron traps existing on the SiO 2 surface. In addition, air stability for n-channel operation of the NTCDA transistor was also improved by the PMMA layer which possibly prevented the adsorption of ambient water molecules onto the SiO 2 surface.

Transfer characteristics and contact resistance in Ni- and Ti-contacted graphene-based field-effect transistors

International Nuclear Information System (INIS)

Di Bartolomeo, A; Giubileo, F; Iemmo, L; Romeo, F; Santandrea, S; Gambardella, U

2013-01-01

We produced graphene-based field-effect transistors by contacting mono- and bi-layer graphene by sputtering Ni or Ti as metal electrodes. We performed electrical characterization of the devices by measuring their transfer and output characteristics. We clearly observed the presence of a double-dip feature in the conductance curve for Ni-contacted transistors, and we explain it in terms of charge transfer and graphene doping under the metal contacts. We also studied the contact resistance between the graphene and the metal electrodes with larger values of ∼30 kΩμm 2 recorded for Ti contacts. Importantly, we prove that the contact resistance is modulated by the back-gate voltage. (paper)

Silicon junctionless field effect transistors as room temperature terahertz detectors

Energy Technology Data Exchange (ETDEWEB)

Marczewski, J., E-mail: jmarcz@ite.waw.pl; Tomaszewski, D.; Zaborowski, M. [Institute of Electron Technology, al. Lotnikow 32/46, 02-668 Warsaw (Poland); Knap, W. [Institute of High Pressure Physics of the Polish Academy of Sciences, ul. Sokolowska 29/37, 01-142 Warsaw (Poland); Laboratory Charles Coulomb, Montpellier University & CNRS, Place E. Bataillon, Montpellier 34095 (France); Zagrajek, P. [Institute of Optoelectronics, Military University of Technology, ul. gen. S. Kaliskiego 2, 00-908 Warsaw (Poland)

2015-09-14

Terahertz (THz) radiation detection by junctionless metal-oxide-semiconductor field-effect transistors (JL MOSFETs) was studied and compared with THz detection using conventional MOSFETs. It has been shown that in contrast to the behavior of standard transistors, the junctionless devices have a significant responsivity also in the open channel (low resistance) state. The responsivity for a photolithographically defined JL FET was 70 V/W and the noise equivalent power 460 pW/√Hz. Working in the open channel state may be advantageous for THz wireless and imaging applications because of its low thermal noise and possible high operating speed or large bandwidth. It has been proven that the junctionless MOSFETs can also operate in a zero gate bias mode, which enables simplification of the THz array circuitry. Existing models of THz detection by MOSFETs were considered and it has been demonstrated that the process of detection by these junctionless devices cannot be explained within the framework of the commonly accepted models and therefore requires a new theoretical approach.

Gold nanoparticle-pentacene memory-transistors

OpenAIRE

Novembre , Christophe; Guerin , David; Lmimouni , Kamal; Gamrat , Christian; Vuillaume , Dominique

2008-01-01

We demonstrate an organic memory-transistor device based on a pentacene-gold nanoparticles active layer. Gold (Au) nanoparticles are immobilized on the gate dielectric (silicon dioxide) of a pentacene transistor by an amino-terminated self-assembled monolayer. Under the application of writing and erasing pulses on the gate, large threshold voltage shift (22 V) and on/off drain current ratio of ~3E4 are obtained. The hole field-effect mobility of the transistor is similar in the on and off sta...

Lateral protonic/electronic hybrid oxide thin-film transistor gated by SiO2 nanogranular films

International Nuclear Information System (INIS)

Zhu, Li Qiang; Chao, Jin Yu; Xiao, Hui

2014-01-01

Ionic/electronic interaction offers an additional dimension in the recent advancements of condensed materials. Here, lateral gate control of conductivities of indium-zinc-oxide (IZO) films is reported. An electric-double-layer (EDL) transistor configuration was utilized with a phosphorous-doped SiO 2 nanogranular film to provide a strong lateral electric field. Due to the strong lateral protonic/electronic interfacial coupling effect, the IZO EDL transistor could operate at a low-voltage of 1 V. A resistor-loaded inverter is built, showing a high voltage gain of ∼8 at a low supply voltage of 1 V. The lateral ionic/electronic coupling effects are interesting for bioelectronics and portable electronics

Theoretical investigation of performance of armchair graphene nanoribbon field effect transistors

Science.gov (United States)

Hur, Ji-Hyun; Kim, Deok-Kee

2018-05-01

In this paper, we theoretically investigate the highest possible expected performance for graphene nanoribbon field effect transistors (GNRFETs) for a wide range of operation voltages and device structure parameters, such as the width of the graphene nanoribbon and gate length. We formulated a self-consistent, non-equilibrium Green’s function method in conjunction with the Poisson equation and modeled the operation of nanometer sized GNRFETs, of which GNR channels have finite bandgaps so that the GNRFET can operate as a switch. We propose a metric for competing with the current silicon CMOS high performance or low power devices and explain that this can vary greatly depending on the GNRFET structure parameters.

Organic field-effect transistors using single crystals

International Nuclear Information System (INIS)

Hasegawa, Tatsuo; Takeya, Jun

2009-01-01

Organic field-effect transistors using small-molecule organic single crystals are developed to investigate fundamental aspects of organic thin-film transistors that have been widely studied for possible future markets for 'plastic electronics'. In reviewing the physics and chemistry of single-crystal organic field-effect transistors (SC-OFETs), the nature of intrinsic charge dynamics is elucidated for the carriers induced at the single crystal surfaces of molecular semiconductors. Materials for SC-OFETs are first reviewed with descriptions of the fabrication methods and the field-effect characteristics. In particular, a benchmark carrier mobility of 20-40 cm 2 Vs -1 , achieved with thin platelets of rubrene single crystals, demonstrates the significance of the SC-OFETs and clarifies material limitations for organic devices. In the latter part of this review, we discuss the physics of microscopic charge transport by using SC-OFETs at metal/semiconductor contacts and along semiconductor/insulator interfaces. Most importantly, Hall effect and electron spin resonance (ESR) measurements reveal that interface charge transport in molecular semiconductors is properly described in terms of band transport and localization by charge traps. (topical review)

MOSFET-BJT hybrid mode of the gated lateral bipolar junction transistor for C-reactive protein detection.

Science.gov (United States)

Yuan, Heng; Kwon, Hyurk-Choon; Yeom, Se-Hyuk; Kwon, Dae-Hyuk; Kang, Shin-Won

2011-10-15

In this study, we propose a novel biosensor based on a gated lateral bipolar junction transistor (BJT) for biomaterial detection. The gated lateral BJT can function as both a BJT and a metal-oxide-semiconductor field-effect transistor (MOSFET) with both the emitter and source, and the collector and drain, coupled. C-reactive protein (CRP), which is an important disease marker in clinical examinations, can be detected using the proposed device. In the MOSFET-BJT hybrid mode, the sensitivity, selectivity, and reproducibility of the gated lateral BJT for biosensors were evaluated in this study. According to the results, in the MOSFET-BJT hybrid mode, the gated lateral BJT shows good selectivity and reproducibility. Changes in the emitter (source) current of the device for CRP antigen detection were approximately 0.65, 0.72, and 0.80 μA/decade at base currents of -50, -30, and -10 μA, respectively. The proposed device has significant application in the detection of certain biomaterials that require a dilution process using a common biosensor, such as a MOSFET-based biosensor. Copyright © 2011 Elsevier B.V. All rights reserved.

A III-V nanowire channel on silicon for high-performance vertical transistors.

Science.gov (United States)

Tomioka, Katsuhiro; Yoshimura, Masatoshi; Fukui, Takashi

2012-08-09

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

Investigation of defect-induced abnormal body current in fin field-effect-transistors

International Nuclear Information System (INIS)

Liu, Kuan-Ju; Tsai, Jyun-Yu; Lu, Ying-Hsin; Liu, Xi-Wen; Chang, Ting-Chang; Chen, Ching-En; Yang, Ren-Ya; Cheng, Osbert; Huang, Cheng-Tung

2015-01-01

This letter investigates the mechanism of abnormal body current at the linear region in n-channel high-k/metal gate stack fin field effect transistors. Unlike body current, which is generated by impact ionization at high drain voltages, abnormal body current was found to increase with decreasing drain voltages. Notably, the unusual body leakage only occurs in three-dimensional structure devices. Based on measurements under different operation conditions, the abnormal body current can be attributed to fin surface defect-induced leakage current, and the mechanism is electron tunneling to the fin via the defects, resulting in holes left at the body terminal

Air-stable π-conjugated amorphous copolymer field-effect transistors with high mobility of 0.3 cm²/Vs

DEFF Research Database (Denmark)

Georgakopoulos, S.; Gu, Y.; Nielsen, Martin Meedom

2012-01-01

We have fabricated organic bottom-contact top-gate field-effect transistors with an indenofluorene-phenanthrene co-polymer semiconductor, exhibiting ON/OFF ratio of 10(7) and uncommonly high mobility for an amorphous conjugated polymer of up to 0.3 cm(2)/Vs. Lack of crystallinity in this material...

Dynamic response of carbon nanotube field-effect transistors analyzed by S-parameters measurement

Energy Technology Data Exchange (ETDEWEB)

Bethoux, J.-M. [Institut d' Electronique, de Microelectronique et de Nanotechnologie, C.N.R.S. U.M.R. 8520, BP 60069, F-59652, Villeneuve d' Ascq Cedex (France); Happy, H. [Institut d' Electronique, de Microelectronique et de Nanotechnologie, C.N.R.S. U.M.R. 8520, BP 60069, F-59652, Villeneuve d' Ascq Cedex (France)]. E-mail: henri.happy@iemn.univ-lille1.fr; Dambrine, G. [Institut d' Electronique, de Microelectronique et de Nanotechnologie, C.N.R.S. U.M.R. 8520, BP 60069, F-59652, Villeneuve d' Ascq Cedex (France); Derycke, V. [Laboratoire d' Electronique Moleculaire, SPEC, Commissariat a l' Energie Atomique, Saclay F-91191, Gif sur Yvette Cedex (France); Goffman, M. [Laboratoire d' Electronique Moleculaire, SPEC, Commissariat a l' Energie Atomique, Saclay F-91191, Gif sur Yvette Cedex (France); Bourgoin, J.-P. [Laboratoire d' Electronique Moleculaire, SPEC, Commissariat a l' Energie Atomique, Saclay F-91191, Gif sur Yvette Cedex (France)

2006-12-15

Carbon nanotube field-effect transistors (CN-FET) with a metallic back gate have been fabricated. By assembling a number of CNs in parallel, driving currents in the mA range have been obtained. The dynamic response of the CN-FETs has been investigated through S-parameters measurements. A current gain (|H {sub 21}|{sup 2}) cut-off frequency (f {sub t}) of 8 GHz, and a maximum stable gain (MSG) value of 10 dB at 1 GHz have been obtained. The extraction of an equivalent circuit is proposed.

Electromechanical field effect transistors based on multilayer phosphorene nanoribbons

Energy Technology Data Exchange (ETDEWEB)

Jiang, Z.T., E-mail: jiangzhaotan@hotmail.com; Lv, Z.T.; Zhang, X.D.

2017-06-21

Based on the tight-binding Hamiltonian approach, we demonstrate that the electromechanical field effect transistors (FETs) can be realized by using the multilayer phosphorene nanoribbons (PNRs). The synergistic combination of the electric field and the external strains can establish the on–off switching since the electric field can shift or split the energy band, and the mechanical strains can widen or narrow the band widths. This kind of multilayer PNR FETs, much solider than the monolayer PNR one and more easily biased by different electric fields, has more transport channels consequently leading to the higher on–off current ratio or the higher sensitivity to the electric fields. Meanwhile, the strain-induced band-flattening will be beneficial for improving the flexibility in designing the electromechanical FETs. In addition, such electromechanical FETs can act as strain-controlled FETs or mechanical detectors for detecting the strains, indicating their potential applications in nano- and micro-electromechanical fields. - Highlights: • Electromechanical transistors are designed with multilayer phosphorene nanoribbons. • Electromechanical synergistic effect can establish the on–off switching more flexibly. • Multilayer transistors, solider and more easily biased, has more transport channels. • Electromechanical transistors can act as strain-controlled transistors or mechanical detectors.

SnTe field effect transistors and the anomalous electrical response of structural phase transition

International Nuclear Information System (INIS)

Li, Haitao; Zhu, Hao; Yuan, Hui; Li, Qiliang; You, Lin; Kopanski, Joseph J.; Richter, Curt A.; Zhao, Erhai

2014-01-01

SnTe is a conventional thermoelectric material and has been newly found to be a topological crystalline insulator. In this work, back-gate SnTe field-effect transistors have been fabricated and fully characterized. The devices exhibit n-type transistor behaviors with excellent current-voltage characteristics and large on/off ratio (>10 6 ). The device threshold voltage, conductance, mobility, and subthreshold swing have been studied and compared at different temperatures. It is found that the subthreshold swings as a function of temperature have an apparent response to the SnTe phase transition between cubic and rhombohedral structures at 110 K. The abnormal and rapid increase in subthreshold swing around the phase transition temperature may be due to the soft phonon/structure change which causes the large increase in SnTe dielectric constant. Such an interesting and remarkable electrical response to phase transition at different temperatures makes the small SnTe transistor attractive for various electronic devices.

Enhanced performance of C60 N-type organic field-effect transistors using a pentacene passivation layer

International Nuclear Information System (INIS)

Liang Xiaoyu; Cheng Xiaoman; Du Boqun; Bai Xiao; Fan Jianfeng

2013-01-01

We investigated the properties of C 60 -based organic field-effect transistors (OFETs) with a pentacene passivation layer inserted between the C 60 active layer and the gate dielectric. After modification of the pentacene passivation layer, the performance of the devices was considerably improved compared to C 60 -based OFETs with only a PMMA dielectric. The peak field-effect mobility was up to 1.01 cm 2 /(V·s) and the on/off ratio shifted to 10 4 . This result indicates that using a pentacene passivation layer is an effective way to improve the performance of N-type OFETs. (semiconductor devices)

Characterization of a Common-Gate Amplifier Using Ferroelectric Transistors

Science.gov (United States)

Hunt, Mitchell; Sayyah, Rana; MacLeod, Todd C.; Ho, Fat D.

2011-01-01

In this paper, the empirical data collected through experiments performed using a FeFET in the common-gate amplifier circuit is presented. The FeFET common-gate amplifier was characterized by varying all parameters in the circuit, such as load resistance, biasing of the transistor, and input voltages. Due to the polarization of the ferroelectric layer, the particular behavior of the FeFET common-gate amplifier presents interesting results. Furthermore, the differences between a FeFET common-gate amplifier and a MOSFET common-gate amplifier are examined.

Are Nanotube Architectures More Advantageous Than Nanowire Architectures For Field Effect Transistors?

KAUST Repository

Fahad, Hossain M.

2012-06-27

Decade long research in 1D nanowire field effect transistors (FET) shows although it has ultra-low off-state leakage current and a single device uses a very small area, its drive current generation per device is extremely low. Thus it requires arrays of nanowires to be integrated together to achieve appreciable amount of current necessary for high performance computation causing an area penalty and compromised functionality. Here we show that a FET with a nanotube architecture and core-shell gate stacks is capable of achieving the desirable leakage characteristics of the nanowire FET while generating a much larger drive current with area efficiency. The core-shell gate stacks of silicon nanotube FETs tighten the electrostatic control and enable volume inversion mode operation leading to improved short channel behavior and enhanced performance. Our comparative study is based on semi-classical transport models with quantum confinement effects which offers new opportunity for future generation high performance computation.

T-gate aligned nanotube radio frequency transistors and circuits with superior performance.

Science.gov (United States)

Che, Yuchi; Lin, Yung-Chen; Kim, Pyojae; Zhou, Chongwu

2013-05-28

In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics.

Assessment of pseudo-bilayer structures in the heterogate germanium electron-hole bilayer tunnel field-effect transistor

International Nuclear Information System (INIS)

Padilla, J. L.; Alper, C.; Ionescu, A. M.; Medina-Bailón, C.; Gámiz, F.

2015-01-01

We investigate the effect of pseudo-bilayer configurations at low operating voltages (≤0.5 V) in the heterogate germanium electron-hole bilayer tunnel field-effect transistor (HG-EHBTFET) compared to the traditional bilayer structures of EHBTFETs arising from semiclassical simulations where the inversion layers for electrons and holes featured very symmetric profiles with similar concentration levels at the ON-state. Pseudo-bilayer layouts are attained by inducing a certain asymmetry between the top and the bottom gates so that even though the hole inversion layer is formed at the bottom of the channel, the top gate voltage remains below the required value to trigger the formation of the inversion layer for electrons. Resulting benefits from this setup are improved electrostatic control on the channel, enhanced gate-to-gate efficiency, and higher I ON levels. Furthermore, pseudo-bilayer configurations alleviate the difficulties derived from confining very high opposite carrier concentrations in very thin structures

Assessment of pseudo-bilayer structures in the heterogate germanium electron-hole bilayer tunnel field-effect transistor

Energy Technology Data Exchange (ETDEWEB)

Padilla, J. L., E-mail: jose.padilladelatorre@epfl.ch; Alper, C.; Ionescu, A. M. [Nanoelectronic Devices Laboratory, École Polytechnique Fédérale de Lausanne, Lausanne CH-1015 (Switzerland); Medina-Bailón, C.; Gámiz, F. [Departamento de Electrónica y Tecnología de los Computadores, Universidad de Granada, Avda. Fuentenueva s/n, 18071 Granada (Spain)

2015-06-29

We investigate the effect of pseudo-bilayer configurations at low operating voltages (≤0.5 V) in the heterogate germanium electron-hole bilayer tunnel field-effect transistor (HG-EHBTFET) compared to the traditional bilayer structures of EHBTFETs arising from semiclassical simulations where the inversion layers for electrons and holes featured very symmetric profiles with similar concentration levels at the ON-state. Pseudo-bilayer layouts are attained by inducing a certain asymmetry between the top and the bottom gates so that even though the hole inversion layer is formed at the bottom of the channel, the top gate voltage remains below the required value to trigger the formation of the inversion layer for electrons. Resulting benefits from this setup are improved electrostatic control on the channel, enhanced gate-to-gate efficiency, and higher I{sub ON} levels. Furthermore, pseudo-bilayer configurations alleviate the difficulties derived from confining very high opposite carrier concentrations in very thin structures.

Electronic Cortisol Detection Using an Antibody-Embedded Polymer Coupled to a Field-Effect Transistor.

Science.gov (United States)

Jang, Hyun-June; Lee, Taein; Song, Jian; Russell, Luisa; Li, Hui; Dailey, Jennifer; Searson, Peter C; Katz, Howard E

2018-05-16

A field-effect transistor-based cortisol sensor was demonstrated in physiological conditions. An antibody-embedded polymer on the remote gate was proposed to overcome the Debye length issue (λ D ). The sensing membrane was made by linking poly(styrene- co-methacrylic acid) (PSMA) with anticortisol before coating the modified polymer on the remote gate. The embedded receptor in the polymer showed sensitivity from 10 fg/mL to 10 ng/mL for cortisol and a limit of detection (LOD) of 1 pg/mL in 1× PBS where λ D is 0.2 nm. A LOD of 1 ng/mL was shown in lightly buffered artificial sweat. Finally, a sandwich ELISA confirmed the antibody binding activity of antibody-embedded PSMA.

Effect of initial material on the electrolytic parameters of field-effect transistors

International Nuclear Information System (INIS)

Antonov, A.V.; Sinitsyn, V.N.; Fursov, V.V.

1978-01-01

The effect of initial material parameters upon the main electric characteristics of field transistors at room and optimum (170 deg C) temperatures is studied. For that purpose, the values of parasitic resistances rsub(s), specific resistances rho and steepness S of field transistors, depending on temperature and electrical conditions were measured. The output volt-ampere characteristics of the transistors at room and optimum temperatures are given. An analysis of the results obtained permits to conclude that there is an unambiguous relationship between rho and rsub(s). Impact ionization is shown to occur for field transistors with lower rho at lower drain voltage. When manufacturing field transistors designed for operation at low temperatures, one should remember that a minimum rho may restrict maximum possible steepness. When designing field transistors with optimum noise characteristics, one should variate not only such material parameters as mobility and carrier density, but also select optimum geometry

Organic field-effect transistors using single crystals

Directory of Open Access Journals (Sweden)

Tatsuo Hasegawa and Jun Takeya

2009-01-01

Full Text Available Organic field-effect transistors using small-molecule organic single crystals are developed to investigate fundamental aspects of organic thin-film transistors that have been widely studied for possible future markets for 'plastic electronics'. In reviewing the physics and chemistry of single-crystal organic field-effect transistors (SC-OFETs, the nature of intrinsic charge dynamics is elucidated for the carriers induced at the single crystal surfaces of molecular semiconductors. Materials for SC-OFETs are first reviewed with descriptions of the fabrication methods and the field-effect characteristics. In particular, a benchmark carrier mobility of 20–40 cm2 Vs−1, achieved with thin platelets of rubrene single crystals, demonstrates the significance of the SC-OFETs and clarifies material limitations for organic devices. In the latter part of this review, we discuss the physics of microscopic charge transport by using SC-OFETs at metal/semiconductor contacts and along semiconductor/insulator interfaces. Most importantly, Hall effect and electron spin resonance (ESR measurements reveal that interface charge transport in molecular semiconductors is properly described in terms of band transport and localization by charge traps.

Nonlinear photoresponse of field effect transistors terahertz detectors at high irradiation intensities

International Nuclear Information System (INIS)

But, D. B.; Drexler, C.; Ganichev, S. D.; Sakhno, M. V.; Sizov, F. F.; Dyakonova, N.; Drachenko, O.; Gutin, A.; Knap, W.

2014-01-01

Terahertz power dependence of the photoresponse of field effect transistors, operating at frequencies from 0.1 to 3 THz for incident radiation power density up to 100 kW/cm 2 was studied for Si metal–oxide–semiconductor field-effect transistors and InGaAs high electron mobility transistors. The photoresponse increased linearly with increasing radiation intensity up to the kW/cm 2 range. Nonlinearity followed by saturation of the photoresponse was observed for all investigated field effect transistors for intensities above several kW/cm 2 . The observed photoresponse nonlinearity is explained by nonlinearity and saturation of the transistor channel current. A theoretical model of terahertz field effect transistor photoresponse at high intensity was developed. The model explains quantitative experimental data both in linear and nonlinear regions. Our results show that dynamic range of field effect transistors is very high and can extend over more than six orders of magnitudes of power densities (from ∼0.5 mW/cm 2 to ∼5 kW/cm 2 )

Enhanced Device and Circuit-Level Performance Benchmarking of Graphene Nanoribbon Field-Effect Transistor against a Nano-MOSFET with Interconnects

Directory of Open Access Journals (Sweden)

Huei Chaeng Chin

2014-01-01

Full Text Available Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET for applications in ultralarge-scale integration (ULSI is reported. GNRFET is found to be distinctly superior in the circuit-level architecture. The remarkable transport properties of GNR propel it into an alternative technology to circumvent the limitations imposed by the silicon-based electronics. Budding GNRFET, using the circuit-level modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nm process technology. The assessment of these performance metrics includes energy-delay product (EDP and power-delay product (PDP of inverter and NOR and NAND gates, forming the building blocks for ULSI. The evaluation of EDP and PDP is carried out for an interconnect length that ranges up to 100 μm. An analysis, based on the drain and gate current-voltage (Id-Vd and Id-Vg, for subthreshold swing (SS, drain-induced barrier lowering (DIBL, and current on/off ratio for circuit implementation is given. GNRFET can overcome the short-channel effects that are prevalent in sub-100 nm Si MOSFET. GNRFET provides reduced EDP and PDP one order of magnitude that is lower than that of a MOSFET. Even though the GNRFET is energy efficient, the circuit performance of the device is limited by the interconnect capacitances.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET.

Science.gov (United States)

Tan, Michael Loong Peng; Lentaris, Georgios; Amaratunga Aj, Gehan

2012-08-19

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.

Lateral protonic/electronic hybrid oxide thin-film transistor gated by SiO{sub 2} nanogranular films

Energy Technology Data Exchange (ETDEWEB)

Zhu, Li Qiang, E-mail: lqzhu@nimte.ac.cn; Chao, Jin Yu; Xiao, Hui [Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China)

2014-12-15

Ionic/electronic interaction offers an additional dimension in the recent advancements of condensed materials. Here, lateral gate control of conductivities of indium-zinc-oxide (IZO) films is reported. An electric-double-layer (EDL) transistor configuration was utilized with a phosphorous-doped SiO{sub 2} nanogranular film to provide a strong lateral electric field. Due to the strong lateral protonic/electronic interfacial coupling effect, the IZO EDL transistor could operate at a low-voltage of 1 V. A resistor-loaded inverter is built, showing a high voltage gain of ∼8 at a low supply voltage of 1 V. The lateral ionic/electronic coupling effects are interesting for bioelectronics and portable electronics.

Dual-Gate p-GaN Gate High Electron Mobility Transistors for Steep Subthreshold Slope.

Science.gov (United States)

Bae, Jong-Ho; Lee, Jong-Ho

2016-05-01

A steep subthreshold slope characteristic is achieved through p-GaN gate HEMT with dual-gate structure. Obtained subthreshold slope is less than 120 μV/dec. Based on the measured and simulated data obtained from single-gate device, breakdown of parasitic floating-base bipolar transistor and floating gate charged with holes are responsible to increase abruptly in drain current. In the dual-gate device, on-current degrades with high temperature but subthreshold slope is not changed. To observe the switching speed of dual-gate device and transient response of drain current are measured. According to the transient responses of drain current, switching speed of the dual-gate device is about 10(-5) sec.

Simulation study of 14-nm-gate III-V trigate field effect transistor devices with In1−xGaxAs channel capping layer

Directory of Open Access Journals (Sweden)

Cheng-Hao Huang

2015-06-01

Full Text Available In this work, we study characteristics of 14-nm-gate InGaAs-based trigate MOSFET (metal-oxide-semiconductor field effect transistor devices with a channel capping layer. The impacts of thickness and gallium (Ga concentration of the channel capping layer on the device characteristic are firstly simulated and optimized by using three-dimensional quantum-mechanically corrected device simulation. Devices with In1−xGaxAs/In0.53Ga0.47As channels have the large driving current owing to small energy band gap and low alloy scattering at the channel surface. By simultaneously considering various physical and switching properties, a 4-nm-thick In0.68Ga0.32As channel capping layer can be adopted for advanced applications. Under the optimized channel parameters, we further examine the effects of channel fin angle and the work-function fluctuation (WKF resulting from nano-sized metal grains of NiSi gate on the characteristic degradation and variability. To maintain the device characteristics and achieve the minimal variation induced by WKF, the physical findings of this study indicate a critical channel fin angle of 85o is needed for the device with an averaged grain size of NiSi below 4x4 nm2.

Sidewall gated double well quasi-one-dimensional resonant tunneling transistors

Science.gov (United States)

Kolagunta, V. R.; Janes, D. B.; Melloch, M. R.; Youtsey, C.

1997-12-01

We present gating characteristics of submicron vertical resonant tunneling transistors in double quantum well heterostructures. Current-voltage characteristics at room temperature and 77 K for devices with minimum feature widths of 0.9 and 0.7 μm are presented and discussed. The evolution of the I-V characteristics with increasing negative gate biases is related to the change in the lateral confinement, with a transition from a large area 2D to a quasi-1D. Even gating of multiple wells and lateral confinement effects observable at 77 K make these devices ideally suited for applications in multi-valued logic systems and low-dimensional structures.

Progresses in organic field-effect transistors and molecular electronics

Institute of Scientific and Technical Information of China (English)

Wu Weiping; Xu Wei; Hu Wenping; Liu Yunqi; Zhu Daoben

2006-01-01

In the past years,organic semiconductors have been extensively investigated as electronic materials for organic field-effect transistors (OFETs).In this review,we briefly summarize the current status of organic field-effect transistors including materials design,device physics,molecular electronics and the applications of carbon nanotubes in molecular electronics.Future prospects and investigations required to improve the OFET performance are also involved.

Coaxial-structured ZnO/silicon nanowires extended-gate field-effect transistor as pH sensor

International Nuclear Information System (INIS)

Li, Hung-Hsien; Yang, Chi-En; Kei, Chi-Chung; Su, Chung-Yi; Dai, Wei-Syuan; Tseng, Jung-Kuei; Yang, Po-Yu; Chou, Jung-Chuan; Cheng, Huang-Chung

2013-01-01

An extended-gate field-effect transistor (EGFET) of coaxial-structured ZnO/silicon nanowires as pH sensor was demonstrated in this paper. The oriented 1-μm-long silicon nanowires with the diameter of about 50 nm were vertically synthesized by the electroless metal deposition method at room temperature and were sequentially capped with the ZnO films using atomic layer deposition at 50 °C. The transfer characteristics (I DS –V REF ) of such ZnO/silicon nanowire EGFET sensor exhibited the sensitivity and linearity of 46.25 mV/pH and 0.9902, respectively for the different pH solutions (pH 1–pH 13). In contrast to the ZnO thin-film ones, the ZnO/silicon nanowire EGFET sensor achieved much better sensitivity and superior linearity. It was attributed to a high surface-to-volume ratio of the nanowire structures, reflecting a larger effective sensing area. The output voltage and time characteristics were also measured to indicate good reliability and durability for the ZnO/silicon nanowires sensor. Furthermore, the hysteresis was 9.74 mV after the solution was changed as pH 7 → pH 3 → pH 7 → pH 11 → pH 7. - Highlights: ► Coaxial-structured ZnO/silicon nanowire EGFET was demonstrated as pH sensor. ► EMD and ALD methods were proposed to fabricate ZnO/silicon nanowires. ► ZnO/silicon nanowire EGFET sensor achieved better sensitivity and linearity. ► ZnO/silicon nanowire EGFET sensor had good reliability and durability

Self-Heating Effects In Polysilicon Source Gated Transistors

Science.gov (United States)

Sporea, R. A.; Burridge, T.; Silva, S. R. P.

2015-01-01

Source-gated transistors (SGTs) are thin-film devices which rely on a potential barrier at the source to achieve high gain, tolerance to fabrication variability, and low series voltage drop, relevant to a multitude of energy-efficient, large-area, cost effective applications. The current through the reverse-biased source barrier has a potentially high positive temperature coefficient, which may lead to undesirable thermal runaway effects and even device failure through self-heating. Using numerical simulations we show that, even in highly thermally-confined scenarios and at high current levels, self-heating is insufficient to compromise device integrity. Performance is minimally affected through a modest increase in output conductance, which may limit the maximum attainable gain. Measurements on polysilicon devices confirm the simulated results, with even smaller penalties in performance, largely due to improved heat dissipation through metal contacts. We conclude that SGTs can be reliably used for high gain, power efficient analog and digital circuits without significant performance impact due to self-heating. This further demonstrates the robustness of SGTs. PMID:26351099

Temperature Effects on a-IGZO Thin Film Transistors Using HfO2 Gate Dielectric Material

Directory of Open Access Journals (Sweden)

Yu-Hsien Lin

2014-01-01

Full Text Available This study investigated the temperature effect on amorphous indium gallium zinc oxide (a-IGZO thin film transistors (TFTs using hafnium oxide (HfO2 gate dielectric material. HfO2 is an attractive candidate as a high-κ dielectric material for gate oxide because it has great potential to exhibit superior electrical properties with a high drive current. In the process of integrating the gate dielectric and IGZO thin film, postannealing treatment is an essential process for completing the chemical reaction of the IGZO thin film and enhancing the gate oxide quality to adjust the electrical characteristics of the TFTs. However, the hafnium atom diffused the IGZO thin film, causing interface roughness because of the stability of the HfO2 dielectric thin film during high-temperature annealing. In this study, the annealing temperature was optimized at 200°C for a HfO2 gate dielectric TFT exhibiting high mobility, a high ION/IOFF ratio, low IOFF current, and excellent subthreshold swing (SS.

Method of making a self-aligned schottky metal semi-conductor field effect transistor with buried source and drain

International Nuclear Information System (INIS)

Bol, I.

1984-01-01

A semi-conductor structure and particularly a high speed VLSI Self-Aligned Schottky Metal Semi-Conductor Field Effect Transistor with buried source and drain, fabricated by the ion implantation of source and drain areas at a predetermined range of depths followed by very localized laser annealing to electrically reactivate the amorphous buried source and drain areas thereby providing effective vertical separation of the channel from the buried source and drain respectively. Accordingly, spatial separations between the self-aligned gate-to-drain, and gate-to-source can be relatively very closely controlled by varying the doping intensity and duration of the implantation thereby reducing the series resistance and increasing the operating speed

Radiation effects on junction field-effect transistors (JFETS), MOSFETs, and bipolar transistors, as related to SSC circuit design

International Nuclear Information System (INIS)

Kennedy, E.J.; Alley, G.T.; Britton, C.L. Jr.; Skubic, P.L.; Gray, B.; Wu, A.

1990-01-01

Some results of radiation effects on selected junction field-effect transistors, MOS field-effect transistors, and bipolar junction transistors are presented. The evaluations include dc parameters, as well as capacitive variations and noise evaluations. The tests are made at the low current and voltage levels (in particular, at currents ≤1 mA) that are essential for the low-power regimes required by SSC circuitry. Detailed noise data are presented both before and after 5-Mrad (gamma) total-dose exposure. SPICE radiation models for three high-frequency bipolar processes are compared for a typical charge-sensitive preamplifier

Molecular materials for organic field-effect transistors

International Nuclear Information System (INIS)

Mori, T

2008-01-01

Organic field-effect transistors are important applications of thin films of molecular materials. A variety of materials have been explored for improving the performance of organic transistors. The materials are conventionally classified as p-channel and n-channel, but not only the performance but also even the carrier polarity is greatly dependent on the combinations of organic semiconductors and electrode materials. In this review, particular emphasis is laid on multi-sulfur compounds such as tetrathiafulvalenes and metal dithiolates. These compounds are components of highly conducting materials such as organic superconductors, but are also used in organic transistors. The charge-transfer complexes are used in organic transistors as active layers as well as electrodes. (topical review)

Non-Planar Nanotube and Wavy Architecture Based Ultra-High Performance Field Effect Transistors

KAUST Repository

Hanna, Amir

2016-11-01

This dissertation presents a unique concept for a device architecture named the nanotube (NT) architecture, which is capable of higher drive current compared to the Gate-All-Around Nanowire architecture when applied to heterostructure Tunnel Field Effect Transistors. Through the use of inner/outer core-shell gates, heterostructure NT TFET leverages physically larger tunneling area thus achieving higher driver current (ION) and saving real estates by eliminating arraying requirement. We discuss the physics of p-type (Silicon/Indium Arsenide) and n-type (Silicon/Germanium hetero-structure) based TFETs. Numerical TCAD simulations have shown that NT TFETs have 5x and 1.6 x higher normalized ION when compared to GAA NW TFET for p and n-type TFETs, respectively. This is due to the availability of larger tunneling junction cross sectional area, and lower Shockley-Reed-Hall recombination, while achieving sub 60 mV/dec performance for more than 5 orders of magnitude of drain current, thus enabling scaling down of Vdd to 0.5 V. This dissertation also introduces a novel thin-film-transistors architecture that is named the Wavy Channel (WC) architecture, which allows for extending device width by integrating vertical fin-like substrate corrugations giving rise to up to 50% larger device width, without occupying extra chip area. The novel architecture shows 2x higher output drive current per unit chip area when compared to conventional planar architecture. The current increase is attributed to both the extra device width and 50% enhancement in field effect mobility due to electrostatic gating effects. Digital circuits are fabricated to demonstrate the potential of integrating WC TFT based circuits. WC inverters have shown 2× the peak-to-peak output voltage for the same input, and ~2× the operation frequency of the planar inverters for the same peak-to-peak output voltage. WC NAND circuits have shown 2× higher peak-to-peak output voltage, and 3× lower high-to-low propagation

Electric field confinement effect on charge transport in organic field-effect transistors

NARCIS (Netherlands)

Li, X.; Kadashchuk, A.; Fishchuk, I.I.; Smaal, W.T.T.; Gelinck, G.H.; Broer, D.J.; Genoe, J.; Heremans, P.; Bässler, H.

2012-01-01

While it is known that the charge-carrier mobility in organic semiconductors is only weakly dependent on the electric field at low fields, the experimental mobility in organic field-effect transistors using silylethynyl-substituted pentacene is found to be surprisingly field dependent at low

Ambipolar Small-Molecule:Polymer Blend Semiconductors for Solution-Processable Organic Field-Effect Transistors.

Science.gov (United States)

Kang, Minji; Hwang, Hansu; Park, Won-Tae; Khim, Dongyoon; Yeo, Jun-Seok; Kim, Yunseul; Kim, Yeon-Ju; Noh, Yong-Young; Kim, Dong-Yu

2017-01-25

We report on the fabrication of an organic thin-film semiconductor formed using a blend solution of soluble ambipolar small molecules and an insulating polymer binder that exhibits vertical phase separation and uniform film formation. The semiconductor thin films are produced in a single step from a mixture containing a small molecular semiconductor, namely, quinoidal biselenophene (QBS), and a binder polymer, namely, poly(2-vinylnaphthalene) (PVN). Organic field-effect transistors (OFETs) based on QBS/PVN blend semiconductor are then assembled using top-gate/bottom-contact device configuration, which achieve almost four times higher mobility than the neat QBS semiconductor. Depth profile via secondary ion mass spectrometry and atomic force microscopy images indicate that the QBS domains in the films made from the blend are evenly distributed with a smooth morphology at the bottom of the PVN layer. Bias stress test and variable-temperature measurements on QBS-based OFETs reveal that the QBS/PVN blend semiconductor remarkably reduces the number of trap sites at the gate dielectric/semiconductor interface and the activation energy in the transistor channel. This work provides a one-step solution processing technique, which makes use of soluble ambipolar small molecules to form a thin-film semiconductor for application in high-performance OFETs.

Ambipolar charge transport in organic field-effect transistors

NARCIS (Netherlands)

Smits, E.C.P.; Anthopoulos, T.D.; Setayesh, S.; Veenendaal, van E.; Coehoorn, R.; Blom, P.W.M.; Boer, de B.; Leeuw, de D.M.

2006-01-01

A model describing charge transport in disordered ambipolar organic field-effect transistors is presented. The basis of this model is the variable-range hopping in an exponential density of states developed for disordered unipolar organic transistors. We show that the model can be used to calculate

Tunnel field-effect transistors with germanium/strained-silicon hetero-junctions for low power applications

International Nuclear Information System (INIS)

Kim, Minsoo; Kim, Younghyun; Yokoyama, Masafumi; Nakane, Ryosho; Kim, SangHyeon; Takenaka, Mitsuru; Takagi, Shinichi

2014-01-01

We have studied a simple structure n-channel tunnel field-effect transistor with a pure-Ge/strained-Si hetero-junction. The device operation was demonstrated for the devices fabricated by combining epitaxially-grown Ge on strained-silicon-on-insulator substrates. Atomic-layer-deposition-Al 2 O 3 -based gate stacks were formed with electron cyclotron resonance plasma post oxidation to ensure the high quality metal–oxide–semiconductor interface between the high-k insulator and Ge. While the gate leakage current and drain current saturation are well controlled, relatively higher minimum subthreshold swing of 125 mV/dec and lower I ON /I OFF ratio of 10 3 –10 4 were obtained. It is expected that these device characteristics can be improved by further process optimization. - Highlights: • Layer by layer growth of Ge • Uniform interface between Ge and the insulator • Gate leakage current and drain current saturation seem to be well controlled. • The output characteristics show good saturation

Current collapse imaging of Schottky gate AlGaN/GaN high electron mobility transistors by electric field-induced optical second-harmonic generation measurement

International Nuclear Information System (INIS)

Katsuno, Takashi; Ishikawa, Tsuyoshi; Ueda, Hiroyuki; Uesugi, Tsutomu; Manaka, Takaaki; Iwamoto, Mitsumasa

2014-01-01

Two-dimensional current collapse imaging of a Schottky gate AlGaN/GaN high electron mobility transistor device was achieved by optical electric field-induced second-harmonic generation (EFISHG) measurements. EFISHG measurements can detect the electric field produced by carriers trapped in the on-state of the device, which leads to current collapse. Immediately after (e.g., 1, 100, or 800 μs) the completion of drain-stress voltage (200 V) in the off-state, the second-harmonic (SH) signals appeared within 2 μm from the gate edge on the drain electrode. The SH signal intensity became weak with time, which suggests that the trapped carriers are emitted from the trap sites. The SH signal location supports the well-known virtual gate model for current collapse.

Recent progress in photoactive organic field-effect transistors.

Science.gov (United States)

Wakayama, Yutaka; Hayakawa, Ryoma; Seo, Hoon-Seok

2014-04-01

Recent progress in photoactive organic field-effect transistors (OFETs) is reviewed. Photoactive OFETs are divided into light-emitting (LE) and light-receiving (LR) OFETs. In the first part, LE-OFETs are reviewed from the viewpoint of the evolution of device structures. Device performances have improved in the last decade with the evolution of device structures from single-layer unipolar to multi-layer ambipolar transistors. In the second part, various kinds of LR-OFETs are featured. These are categorized according to their functionalities: phototransistors, non-volatile optical memories, and photochromism-based transistors. For both, various device configurations are introduced: thin-film based transistors for practical applications, single-crystalline transistors to investigate fundamental physics, nanowires, multi-layers, and vertical transistors based on new concepts.

Recent progress in photoactive organic field-effect transistors

International Nuclear Information System (INIS)

Wakayama, Yutaka; Hayakawa, Ryoma; Seo, Hoon-Seok

2014-01-01

Recent progress in photoactive organic field-effect transistors (OFETs) is reviewed. Photoactive OFETs are divided into light-emitting (LE) and light-receiving (LR) OFETs. In the first part, LE-OFETs are reviewed from the viewpoint of the evolution of device structures. Device performances have improved in the last decade with the evolution of device structures from single-layer unipolar to multi-layer ambipolar transistors. In the second part, various kinds of LR-OFETs are featured. These are categorized according to their functionalities: phototransistors, non-volatile optical memories, and photochromism-based transistors. For both, various device configurations are introduced: thin-film based transistors for practical applications, single-crystalline transistors to investigate fundamental physics, nanowires, multi-layers, and vertical transistors based on new concepts. (review)

Field effect transistors and phototransistors based upon p-type solution-processed PbS nanowires

Science.gov (United States)

Giraud, Paul; Hou, Bo; Pak, Sangyeon; Inn Sohn, Jung; Morris, Stephen; Cha, SeungNam; Kim, Jong Min

2018-02-01

We demonstrate the fabrication of solution processed highly crystalline p-type PbS nanowires via the oriented attachment of nanoparticles. The analysis of single nanowire field effect transistor (FET) devices revealed a hole conduction behaviour with average mobilities greater than 30 cm2 V-1 s-1, which is an order of magnitude higher than that reported to date for p-type PbS colloidal nanowires. We have investigated the response of the FETs to near-infrared light excitation and show herein that the nanowires exhibited gate-dependent photo-conductivities, enabling us to tune the device performances. The responsivity was found to be greater than 104 A W-1 together with a detectivity of 1013 Jones, which benefits from a photogating effect occurring at negative gate voltages. These encouraging detection parameters are accompanied by relatively short switching times of 15 ms at positive gate voltages, resulting from a combination of the standard photoconduction and the high crystallinity of the nanowires. Collectively, these results indicate that solution-processed PbS nanowires are promising nanomaterials for infrared photodetectors as well as p-type nanowire FETs.

Enhancing Photoresponsivity of Self-Aligned MoS2 Field-Effect Transistors by Piezo-Phototronic Effect from GaN Nanowires.

Science.gov (United States)

Liu, Xingqiang; Yang, Xiaonian; Gao, Guoyun; Yang, Zhenyu; Liu, Haitao; Li, Qiang; Lou, Zheng; Shen, Guozhen; Liao, Lei; Pan, Caofeng; Lin Wang, Zhong

2016-08-23

We report high-performance self-aligned MoS2 field-effect transistors (FETs) with enhanced photoresponsivity by the piezo-phototronic effect. The FETs are fabricated based on monolayer MoS2 with a piezoelectric GaN nanowire (NW) as the local gate, and a self-aligned process is employed to define the source/drain electrodes. The fabrication method allows the preservation of the intrinsic property of MoS2 and suppresses the scattering center density in the MoS2/GaN interface, which results in high electrical and photoelectric performances. MoS2 FETs with channel lengths of ∼200 nm have been fabricated with a small subthreshold slope of 64 mV/dec. The photoresponsivity is 443.3 A·W(-1), with a fast response and recovery time of ∼5 ms under 550 nm light illumination. When strain is introduced into the GaN NW, the photoresponsivity is further enhanced to 734.5 A·W(-1) and maintains consistent response and recovery time, which is comparable with that of the mechanical exfoliation of MoS2 transistors. The approach presented here opens an avenue to high-performance top-gated piezo-enhanced MoS2 photodetectors.

MoS2 Negative-Capacitance Field-Effect Transistors with Subthreshold Swing below the Physics Limit.

Science.gov (United States)

Liu, Xingqiang; Liang, Renrong; Gao, Guoyun; Pan, Caofeng; Jiang, Chunsheng; Xu, Qian; Luo, Jun; Zou, Xuming; Yang, Zhenyu; Liao, Lei; Wang, Zhong Lin

2018-05-21

The Boltzmann distribution of electrons induced fundamental barrier prevents subthreshold swing (SS) from less than 60 mV dec -1 at room temperature, leading to high energy consumption of MOSFETs. Herein, it is demonstrated that an aggressive introduction of the negative capacitance (NC) effect of ferroelectrics can decisively break the fundamental limit governed by the "Boltzmann tyranny". Such MoS 2 negative-capacitance field-effect transistors (NC-FETs) with self-aligned top-gated geometry demonstrated here pull down the SS value to 42.5 mV dec -1 , and simultaneously achieve superior performance of a transconductance of 45.5 μS μm and an on/off ratio of 4 × 10 6 with channel length less than 100 nm. Furthermore, the inserted HfO 2 layer not only realizes a stable NC gate stack structure, but also prevents the ferroelectric P(VDF-TrFE) from fatigue with robust stability. Notably, the fabricated MoS 2 NC-FETs are distinctly different from traditional MOSFETs. The on-state current increases as the temperature decreases even down to 20 K, and the SS values exhibit nonlinear dependence with temperature due to the implementation of the ferroelectric gate stack. The NC-FETs enable fundamental applications through overcoming the Boltzmann limit in nanoelectronics and open up an avenue to low-power transistors needed for many exciting long-endurance portable consumer products. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

3D modeling of dual-gate FinFET.

Science.gov (United States)

Mil'shtein, Samson; Devarakonda, Lalitha; Zanchi, Brian; Palma, John

2012-11-13

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at Vg1 >Vg2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.

A self-amplified transistor immunosensor under dual gate operation: highly sensitive detection of hepatitis B surface antigen

Science.gov (United States)

Lee, I.-K.; Jeun, M.; Jang, H.-J.; Cho, W.-J.; Lee, K. H.

2015-10-01

Ion-sensitive field-effect transistors (ISFETs), although they have attracted considerable attention as effective immunosensors, have still not been adopted for practical applications owing to several problems: (1) the poor sensitivity caused by the short Debye screening length in media with high ion concentration, (2) time-consuming preconditioning processes for achieving the highly-diluted media, and (3) the low durability caused by undesirable ions such as sodium chloride in the media. Here, we propose a highly sensitive immunosensor based on a self-amplified transistor under dual gate operation (immuno-DG ISFET) for the detection of hepatitis B surface antigen. To address the challenges in current ISFET-based immunosensors, we have enhanced the sensitivity of an immunosensor by precisely tailoring the nanostructure of the transistor. In the pH sensing test, the immuno-DG ISFET showed superior sensitivity (2085.53 mV per pH) to both standard ISFET under single gate operation (58.88 mV per pH) and DG ISFET with a non-tailored transistor (381.14 mV per pH). Moreover, concerning the detection of hepatitis B surface antigens (HBsAg) using the immuno-DG ISFET, we have successfully detected trace amounts of HBsAg (22.5 fg mL-1) in a non-diluted 1× PBS medium with a high sensitivity of 690 mV. Our results demonstrate that the proposed immuno-DG ISFET can be a biosensor platform for practical use in the diagnosis of various diseases.Ion-sensitive field-effect transistors (ISFETs), although they have attracted considerable attention as effective immunosensors, have still not been adopted for practical applications owing to several problems: (1) the poor sensitivity caused by the short Debye screening length in media with high ion concentration, (2) time-consuming preconditioning processes for achieving the highly-diluted media, and (3) the low durability caused by undesirable ions such as sodium chloride in the media. Here, we propose a highly sensitive immunosensor

Simulation of diode characteristics of carbon nanotube field-effect transistors with symmetric source and drain contacts

KAUST Repository

Li, Jingqi; Zhang, Xixiang

2011-01-01

The diode characteristics of carbon nanotube field-effect transistors (CNTFETs) with symmetric source and drain contacts have been experimentally found at zero gate voltage (Li J. et al., Appl. Phys. Lett., 92 (2008) 133111). We calculate this characteristic using a semiclassical method based on Schottky barrier transistor mechanism. The influences of metal work function, the diameter of the carbon nanotubes and the dielectric thickness on the rectification behavior have been studied. The calculation results show that the metal with a higher work function results in a better diode characteristics for a p-type CNTFET. For single-walled carbon nanotubes (SWNTs) with different band gaps, both forward current and reverse current increase with decreasing band gap, but the ratio of forward current to reverse current decreases with decreasing band gap. This result is well consistent with the experimental observations reported previously. The simulation of the dielectric thickness effect indicates that the thinner the dielectric layer, the better the rectification behavior. The CNTFETs without a bottom gate could not show the diode characteristics, which is consistent with the reported experimental observation. © 2011 Europhysics Letters Association.

Simulation of diode characteristics of carbon nanotube field-effect transistors with symmetric source and drain contacts

KAUST Repository

Li, Jingqi

2011-09-01

The diode characteristics of carbon nanotube field-effect transistors (CNTFETs) with symmetric source and drain contacts have been experimentally found at zero gate voltage (Li J. et al., Appl. Phys. Lett., 92 (2008) 133111). We calculate this characteristic using a semiclassical method based on Schottky barrier transistor mechanism. The influences of metal work function, the diameter of the carbon nanotubes and the dielectric thickness on the rectification behavior have been studied. The calculation results show that the metal with a higher work function results in a better diode characteristics for a p-type CNTFET. For single-walled carbon nanotubes (SWNTs) with different band gaps, both forward current and reverse current increase with decreasing band gap, but the ratio of forward current to reverse current decreases with decreasing band gap. This result is well consistent with the experimental observations reported previously. The simulation of the dielectric thickness effect indicates that the thinner the dielectric layer, the better the rectification behavior. The CNTFETs without a bottom gate could not show the diode characteristics, which is consistent with the reported experimental observation. © 2011 Europhysics Letters Association.

Gate-controlled quantum collimation in nanocolumn resonant tunnelling transistors

International Nuclear Information System (INIS)

Wensorra, J; Lepsa, M I; Trellenkamp, S; Moers, J; Lueth, H; Indlekofer, K M

2009-01-01

Nanoscaled resonant tunneling transistors (RTT) based on MBE-grown GaAs/AlAs double-barrier quantum well (DBQW) structures have been fabricated by a top-down approach using electron-beam lithographic definition of the vertical nanocolumns. In the preparation process, a reproducible mask alignment accuracy of below 10 nm has been achieved and the all-around metal gate at the level of the DBQW structure has been positioned at a distance of about 20 nm relative to the semiconductor nanocolumn. Due to the specific doping profile n ++ /i/n ++ along the transistor nanocolumn, a particular confining potential is established for devices with diameters smaller than 70 nm, which causes a collimation effect of the propagating electrons. Under these conditions, room temperature optimum performance of the nano-RTTs is achieved with peak-to-valley current ratios above 2 and a peak current swing factor of about 6 for gate voltages between -6 and +6 V. These values indicate that our nano-RTTs can be successfully used in low power fast nanoelectronic circuits.

Radiation effects in a CMOS/SOS/Al-Gate D/A converter and on-chip diagnostic transistors

International Nuclear Information System (INIS)

Brucker, G.J.; Heagerty, W.

1976-01-01

This paper presents the results obtained from total dose and transient radiation tests on a CMOS/SOS/Al-Gate D/A converter and on-chip diagnostic transistors. Samples were irradiated by cobalt-60 gamma rays under worst-case conditions, and by 10-MeV electron pulses of 50-ns and 4.4-μs duration. Devices were fabricated with three different insulators; the two discussed here are standard wet oxide and a pyrogenic oxide. Test transistors on the D/A chips made it possible to diagnose the failure modes of the converter and to evaluate some special designs. These consisted of standard edge p- and n-channel transistors, edgeless units, edgeless tetrode transistors, and an edgeless type transmission gate with a diode clamp from substrate to gate. The total dose results indicate that the pyrogenic oxide increased the failure dose of the operational amplifier portion of the converter from 10 3 rads (Si) to 2 x 10 6 rads (Si); however, the sample and hold failed after exposure to a low level of 10 3 rads (Si). Test devices indicated this to be due to the radiation-induced leakage current of the transmission gate which discharges the sample and hold capacitor. The diode clamp decreased the threshold voltage shifts and the leakage currents. The edgeless devices improved the device performance because of a more abrupt turn-on. Narrow-pulse test data indicated that the edgeless units produced less photocurrent than the edge units by about a factor of three to four. Converter upset levels are less than or equal to 10 9 rads/s due to precision requirements which make a few millivolt transients untenable

Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits.

Science.gov (United States)

Chen, Bingyan; Zhang, Panpan; Ding, Li; Han, Jie; Qiu, Song; Li, Qingwen; Zhang, Zhiyong; Peng, Lian-Mao

2016-08-10

Top-gated p-type field-effect transistors (FETs) have been fabricated in batch based on carbon nanotube (CNT) network thin films prepared from CNT solution and present high yield and highly uniform performance with small threshold voltage distribution with standard deviation of 34 mV. According to the property of FETs, various logical and arithmetical gates, shifters, and d-latch circuits were designed and demonstrated with rail-to-rail output. In particular, a 4-bit adder consisting of 140 p-type CNT FETs was demonstrated with higher packing density and lower supply voltage than other published integrated circuits based on CNT films, which indicates that CNT based integrated circuits can reach to medium scale. In addition, a 2-bit multiplier has been realized for the first time. Benefitted from the high uniformity and suitable threshold voltage of CNT FETs, all of the fabricated circuits based on CNT FETs can be driven by a single voltage as small as 2 V.

Characteristics of dual-gate thin-film transistors for applications in digital radiology

International Nuclear Information System (INIS)

Waechter, D.; Huang, Z.; Zhao, W.; Blevis, I.; Rowlands, J.A.

1996-01-01

A large-area flat-panel detector for digital radiology is being developed. The detector uses an array of dual-gate thin-film transistors (TFTs) to read out X-ray-generated charge produced in an amorphous selenium (a-Se) layer. The TFTs use CdSe as the semiconductor and use the bottom gate for row selection. The top gate can be divided into a 'deliberate' gate, covering most of the channel length, and small 'parasitic' gates that consist of: overlap of source or drain metal over the top-gate oxide; and gap regions in the metal that are covered only by the a-Se. In this paper we present the properties of dual-gate TFTs and examine the effect of both the deliberate and parasitic gates on the detector operation. Various options for controlling the top-gate potential are analyzed and discussed. (author)

Electrical characteristics of GdTiO{sub 3} gate dielectric for amorphous InGaZnO thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Her, Jim-Long [Division of Natural Science, Center for General Education, Chang Gung University, Taoyuan 333, Taiwan (China); Pan, Tung-Ming, E-mail: tmpan@mail.cgu.edu.tw [Department of Electronics Engineering, Chang Gung University, Taoyuan 333, Taiwan (China); Liu, Jiang-Hung; Wang, Hong-Jun; Chen, Ching-Hung [Department of Electronics Engineering, Chang Gung University, Taoyuan 333, Taiwan (China); Koyama, Keiichi [Graduate School of Science and Engineering, Kagoshima University, Kagoshima 890-0065 (Japan)

2014-10-31

In this article, we studied the structural properties and electrical characteristics of GdTiO{sub 3} gate dielectric for amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) applications. The a-IGZO TFT device featuring the GdTiO{sub 3} gate dielectric exhibited better electrical characteristics, including a small threshold voltage of 0.14 V, a large field-effect mobility of 32.3 cm{sup 2}/V-s, a high I{sub on}/I{sub off} current ratio of 4.2 × 10{sup 8}, and a low subthreshold swing of 213 mV/decade. Furthermore, the electrical instability of GdTiO{sub 3} a-IGZO TFTs was investigated under both positive gate-bias stress (PGBS) and negative gate-bias stress (NGBS) conditions. The electron charge trapping in the gate dielectric dominates the PGBS degradation, while the oxygen vacancies control the NGBS degradation. - Highlights: • Indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) • Structural and electrical properties of the GdTiO{sub 3} film were studied. • a-IGZO TFT featuring GdTi{sub x}O{sub y} dielectric exhibited better electrical characteristics. • TFT instability investigated under positive and negative gate-bias stress conditions.

Multi-material gate poly-crystalline thin film transistors: Modeling and simulation for an improved gate transport efficiency

International Nuclear Information System (INIS)

Sehgal, Amit; Mangla, Tina; Gupta, Mridula; Gupta, R.S.

2008-01-01

In this work, a two-dimensional potential distribution formulation is presented for multi-material gate poly-crystalline silicon thin film transistors. The developed formulation incorporates the effects due to traps and grain-boundaries. In short-channel devices, short-channel effects and drain-induced barrier lowering (DIBL) effect exists, and are accounted for in the analysis. The work aims at the reduction of DIBL effect and grain-boundary effects i.e. to reduce the potential barriers generated in the channel by employing gate-engineered structures. A study of work-functions and electrode lengths of multi-material gate electrode is done to suppress the potential barriers, hot electron effect and to improve the carrier transport efficiency. Green's function approach is adopted for the two-dimensional potential solution. The results obtained show a good agreement with simulated results, thus, demonstrating the validity of our model

Nonvolatile ferroelectric memory based on PbTiO3 gated single-layer MoS2 field-effect transistor

Science.gov (United States)

Shin, Hyun Wook; Son, Jong Yeog

2018-01-01

We fabricated ferroelectric non-volatile random access memory (FeRAM) based on a field effect transistor (FET) consisting of a monolayer MoS2 channel and a ferroelectric PbTiO3 (PTO) thin film of gate insulator. An epitaxial PTO thin film was deposited on a Nb-doped SrTiO3 (Nb:STO) substrate via pulsed laser deposition. A monolayer MoS2 sheet was exfoliated from a bulk crystal and transferred to the surface of the PTO/Nb:STO. Structural and surface properties of the PTO thin film were characterized by X-ray diffraction and atomic force microscopy, respectively. Raman spectroscopy analysis was performed to identify the single-layer MoS2 sheet on the PTO/Nb:STO. We obtained mobility value (327 cm2/V·s) of the MoS2 channel at room temperature. The MoS2-PTO FeRAM FET showed a wide memory window with 17 kΩ of resistance variation which was attributed to high remnant polarization of the epitaxially grown PTO thin film. According to the fatigue resistance test for the FeRAM FET, however, the resistance states gradually varied during the switching cycles of 109. [Figure not available: see fulltext.

All-Electrical Spin Field Effect Transistor in van der Waals Heterostructures at Room Temperature

Science.gov (United States)

Dankert, André; Dash, Saroj

Spintronics aims to exploit the spin degree of freedom in solid state devices for data storage and information processing. Its fundamental concepts (creation, manipulation and detection of spin polarization) have been demonstrated in semiconductors and spin transistor structures using electrical and optical methods. However, an unsolved challenge is the realization of all-electrical methods to control the spin polarization in a transistor manner at ambient temperatures. Here we combine graphene and molybdenum disulfide (MoS2) in a van der Waals heterostructure to realize a spin field-effect transistor (spin-FET) at room temperature. These two-dimensional crystals offer a unique platform due to their contrasting properties, such as weak spin-orbit coupling (SOC) in graphene and strong SOC in MoS2. The gate-tuning of the Schottky barrier at the MoS2/graphene interface and MoS2 channel yields spins to interact with high SOC material and allows us to control the spin polarization and lifetime. This all-electrical spin-FET at room temperature is a substantial step in the field of spintronics and opens a new platform for testing a plethora of exotic physical phenomena, which can be key building blocks in future device architectures.

Investigation of Corner Effect and Identification of Tunneling Regimes in L-Shaped Tunnel Field-Effect-Transistor.

Science.gov (United States)

Najam, Faraz; Yu, Yun Seop

2018-09-01

Corner-effect existing in L-shaped tunnel field-effect-transistor (LTFET) was investigated using numerical simulations and band diagram analysis. It was found that the corner-effect is caused by the convergence of electric field in the sharp source corner present in an LTFET, thereby increasing the electric field in the sharp source corner region. It was found that in the corner-effect region tunneling starts early, as a function of applied bias, as compared to the rest of the channel not affected by corner-effect. Further, different tunneling regimes as a function of applied bias were identified in the LTFET including source to channel and channel to channel tunneling regimes. Presence of different tunneling regimes in LTFET was analytically justified with a set of equations developed to model source to channel, and channel to channel tunneling currents. Drain-current-gate-voltage (Ids-Vgs) characteristics obtained from the equations is in reasonable qualitative agreement with numerical simulation.

Graphene quantum dot (GQD)-induced photovoltaic and photoelectric memory elements in a pentacene/GQD field effect transistor as a probe of functional interface

Science.gov (United States)

Kim, Youngjun; Cho, Seongeun; Kim, Hyeran; Seo, Soonjoo; Lee, Hyun Uk; Lee, Jouhahn; Ko, Hyungduk; Chang, Mincheol; Park, Byoungnam

2017-09-01

Electric field-induced charge trapping and exciton dissociation were demonstrated at a penatcene/grapheme quantum dot (GQD) interface using a bottom contact bi-layer field effect transistor (FET) as an electrical nano-probe. Large threshold voltage shift in a pentacene/GQD FET in the dark arises from field-induced carrier trapping in the GQD layer or GQD-induced trap states at the pentacene/GQD interface. As the gate electric field increases, hysteresis characterized by the threshold voltage shift depending on the direction of the gate voltage scan becomes stronger due to carrier trapping associated with the presence of a GQD layer. Upon illumination, exciton dissociation and gate electric field-induced charge trapping simultaneously contribute to increase the threshold voltage window, which can potentially be exploited for photoelectric memory and/or photovoltaic devices through interface engineering.

Multiple-channel detection of cellular activities by ion-sensitive transistors

Science.gov (United States)

Machida, Satoru; Shimada, Hideto; Motoyama, Yumi

2018-04-01

An ion-sensitive field-effect transistor to record cellular activities was demonstrated. This field-effect transistor (bio transistor) includes cultured cells on the gate insulator instead of gate electrode. The bio transistor converts a change in potential underneath the cells into variation of the drain current when ion channels open. The bio transistor has high detection sensitivity to even minute variations in potential utilizing a subthreshold swing region. To open ion channels, a reagent solution (acetylcholine) was added to a human-originating cell cultured on the bio transistor. The drain current was successfully decreased with the addition of acetylcholine. Moreover, we attempted to detect the opening of ion channels using a multiple-channel measurement circuit containing several bio transistors. As a consequence, the drain current distinctly decreased only after the addition of acetylcholine. We confirmed that this measurement system including bio transistors enables to observation of cellular activities sensitively and simultaneously.

Silicon dioxide with a silicon interfacial layer as an insulating gate for highly stable indium phosphide metal-insulator-semiconductor field effect transistors

Science.gov (United States)

Kapoor, V. J.; Shokrani, M.

1991-01-01

A novel gate insulator consisting of silicon dioxide (SiO2) with a thin silicon (Si) interfacial layer has been investigated for high-power microwave indium phosphide (InP) metal-insulator-semiconductor field effect transistors (MISFETs). The role of the silicon interfacial layer on the chemical nature of the SiO2/Si/InP interface was studied by high-resolution X-ray photoelectron spectroscopy. The results indicated that the silicon interfacial layer reacted with the native oxide at the InP surface, thus producing silicon dioxide, while reducing the native oxide which has been shown to be responsible for the instabilities in InP MISFETs. While a 1.2-V hysteresis was present in the capacitance-voltage (C-V) curve of the MIS capacitors with silicon dioxide, less than 0.1 V hysteresis was observed in the C-V curve of the capacitors with the silicon interfacial layer incorporated in the insulator. InP MISFETs fabricated with the silicon dioxide in combination with the silicon interfacial layer exhibited excellent stability with drain current drift of less than 3 percent in 10,000 sec, as compared to 15-18 percent drift in 10,000 sec for devices without the silicon interfacial layer. High-power microwave InP MISFETs with Si/SiO2 gate insulators resulted in an output power density of 1.75 W/mm gate width at 9.7 GHz, with an associated power gain of 2.5 dB and 24 percent power added efficiency.

MOBILITAS PEMBAWA MUATAN PADA OFET (ORGANIC FIELD EFFECT TRANSISTOR BERBASIS FILM TIPIS

Directory of Open Access Journals (Sweden)

Sujarwata -

2014-06-01

Full Text Available Abstrak __________________________________________________________________________________________ Tujuan penelitian ini adalah pembuatan dan karakterisasi pada OFET (Organic Field Effect Transistor berbasis film tipis dengan struktur bottom-contact. Pembuatan OFET dilakukan dengan cara pencucian substrat dengan etanol dalam ultrasonic cleaner, kemudian dilakukan deposisi elektroda source dan drain di atas substrat SiO2 dengan metode  penguapan hampa udara pada suhu ruang dan teknik lithography. Selanjutnya dilakukan deposisi film tipis CuPc diantara source (S dan drain (D sebagai panjang saluran (channel dan diakhiri dengan deposisi elektrode gate (G. Karakterisai OFET berbasis film tipis dilakukan dengan El-Kahfi 100, untuk menentukan karakteristik keluaran V-I. Hasil karakterisasi OFET dengan panjang channel (L 100 μm dan lebar (W 1 mm, mempunyai daerah aktif, yaitu: 2,80 V sampai dengan 3,42. Mobilitas pembawa muatan OFET untuk daerah saturasi, µ = 0,00182278 cm2 /Vs dan untuk daerah linier, µ = 0,000343818  cm2 /Vs   Abstract __________________________________________________________________________________________ The purpose of this research is to produce and characterize the OFET (Organic Field Effect Transistor based on thin film with bottom-contact structure. The OFET production consists of the substract wash by using ethanol in the ultrasonic cleaner, then electrode deposition of source and drain on the SiO2 substract by using vacuum evaporation in the room temperature and lithography technique.  Then, the deposition of thin film of CuPc between source (S and drain (D was done as the channel length and ended with electrode gate (G deposition. The OFET characterization  with channel length (L  100 μm and wide (W 1 mm  obtained the active area of 2,80 - 3,42 v. While the mobility of OFET charge carrier  obtained µ =  0,00182278 cm2 /Vs for the saturation area and µ = 0,000343818  cm2 /Vs for linier area.

Optimization of L-shaped tunneling field-effect transistor for ambipolar current suppression and Analog/RF performance enhancement

Science.gov (United States)

Li, Cong; Zhao, Xiaolong; Zhuang, Yiqi; Yan, Zhirui; Guo, Jiaming; Han, Ru

2018-03-01

L-shaped tunneling field-effect transistor (LTFET) has larger tunnel area than planar TFET, which leads to enhanced on-current ION . However, LTFET suffers from severe ambipolar behavior, which needs to be further optimized for low power and high-frequency applications. In this paper, both hetero-gate-dielectric (HGD) and lightly doped drain (LDD) structures are introduced into LTFET for suppression of ambipolarity and improvement of analog/RF performance of LTFET. Current-voltage characteristics, the variation of energy band diagrams, distribution of band-to-band tunneling (BTBT) generation and distribution of electric field are analyzed for our proposed HGD-LDD-LTFET. In addition, the effect of LDD on the ambipolar behavior of LTFET is investigated, the length and doping concentration of LDD is also optimized for better suppression of ambipolar current. Finally, analog/RF performance of HGD-LDD-LTFET are studied in terms of gate-source capacitance, gate-drain capacitance, cut-off frequency, and gain bandwidth production. TCAD simulation results show that HGD-LDD-LTFET not only drastically suppresses ambipolar current but also improves analog/RF performance compared with conventional LTFET.

Electrical characterisation of ferroelectric field effect transistors based on ferroelectric HfO2 thin films

International Nuclear Information System (INIS)

Yurchuk, Ekaterina

2015-01-01

Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric material (silicon doped hafnium oxide) were studied within the scope of the present work. Utilisation of silicon doped hafnium oxide (Si:HfO 2 ) thin films instead of conventional perovskite ferroelectrics as a functional layer in FeFETs provides compatibility to the CMOS process as well as improved device scalability. The influence of different process parameters on the properties of Si:HfO 2 thin films was analysed in order to gain better insight into the occurrence of ferroelectricity in this system. A subsequent examination of the potential of this material as well as its possible limitations with the respect to the application in non-volatile memories followed. The Si:HfO 2 -based ferroelectric transistors that were fully integrated into the state-of-the-art high-k metal gate CMOS technology were studied in this work for the first time. The memory performance of these devices scaled down to 28 nm gate length was investigated. Special attention was paid to the charge trapping phenomenon shown to significantly affect the device behaviour.

Properties of InGaAs/GaAs metal-oxide-semiconductor heterostructure field-effect transistors modified by surface treatment

Energy Technology Data Exchange (ETDEWEB)

Gregušová, D., E-mail: Dagmar.Gregusova@savba.sk [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Gucmann, F.; Kúdela, R. [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Mičušík, M. [Polymer Institute of Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84541 (Slovakia); Stoklas, R.; Válik, L. [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Greguš, J. [Faculty of Mathematics, Physics and Informatics, Comenius University, Mlynská dolina, Bratislava SK-84248 (Slovakia); Blaho, M. [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Kordoš, P. [Institute of Electronics and Photonics, Faculty of Electrical Engineering and Information Technology STU, Ilkovičova 3, Bratislava SK-81219 (Slovakia)

2017-02-15

Highlights: • AlGaAs/InGaAs/GaAs-based metal oxide semiconductor transistors-MOSHFET. • Thin Al-layer deposited in-situ and oxidize in air – gate insulator. • MOSHFET vs HFET transistor properties, density of traps evaluated. - Abstract: GaAs-based heterostructures exhibit excellent carrier transport properties, mainly the high carrier velocity. An AlGaAs-GaAs heterostructure field-effect transistor (HFET) with an InGaAs channel was prepared using metal-organic chemical vapor deposition (MOVPE). An AlOx layer was formed on the AlGaAs barrier layer by the air-assisted oxidation of a thin Al layer deposited in-situ in an MOVPE reactor immediately after AlGaAs/InGaAs growth. The HFETs and MOSHFETs exhibited a very low trap state density in the order of 10{sup 11} cm{sup −2} eV{sup −1}. Capacitance measurement yielded no significant difference between the HFET and MOSHFET structures. The formation of an AlOx layer modified the surface by partially eliminating surface states that arise from Ga-and As-based native oxides. The presence of an AlOx layer reflected in a reduced gate leakage current, which was evidenced by the two-terminal transistor measurement. Presented preparation procedure and device properties show great potential of AlGaAs/InGaAs-based MOSHFETs.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

Science.gov (United States)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-05-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

Science.gov (United States)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-02-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

Organic semiconductors for organic field-effect transistors

International Nuclear Information System (INIS)

Yamashita, Yoshiro

2009-01-01

The advantages of organic field-effect transistors (OFETs), such as low cost, flexibility and large-area fabrication, have recently attracted much attention due to their electronic applications. Practical transistors require high mobility, large on/off ratio, low threshold voltage and high stability. Development of new organic semiconductors is key to achieving these parameters. Recently, organic semiconductors have been synthesized showing comparable mobilities to amorphous-silicon-based FETs. These materials make OFETs more attractive and their applications have been attempted. New organic semiconductors resulting in high-performance FET devices are described here and the relationship between transistor characteristics and chemical structure is discussed. (topical review)

Organic semiconductors for organic field-effect transistors

Directory of Open Access Journals (Sweden)

Yoshiro Yamashita

2009-01-01

Full Text Available The advantages of organic field-effect transistors (OFETs, such as low cost, flexibility and large-area fabrication, have recently attracted much attention due to their electronic applications. Practical transistors require high mobility, large on/off ratio, low threshold voltage and high stability. Development of new organic semiconductors is key to achieving these parameters. Recently, organic semiconductors have been synthesized showing comparable mobilities to amorphous-silicon-based FETs. These materials make OFETs more attractive and their applications have been attempted. New organic semiconductors resulting in high-performance FET devices are described here and the relationship between transistor characteristics and chemical structure is discussed.

Nanogranular SiO{sub 2} proton gated silicon layer transistor mimicking biological synapses

Energy Technology Data Exchange (ETDEWEB)

Liu, M. J.; Huang, G. S., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Guo, Q. L.; Tian, Z. A.; Li, G. J.; Mei, Y. F. [Department of Materials Science, Fudan University, Shanghai 200433 (China); Feng, P., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Shao, F.; Wan, Q. [School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)

2016-06-20

Silicon on insulator (SOI)-based transistors gated by nanogranular SiO{sub 2} proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

Broadening of Distribution of Trap States in PbS Quantum Dot Field-Effect Transistors with High-k Dielectrics.

Science.gov (United States)

Nugraha, Mohamad I; Häusermann, Roger; Watanabe, Shun; Matsui, Hiroyuki; Sytnyk, Mykhailo; Heiss, Wolfgang; Takeya, Jun; Loi, Maria A

2017-02-08

We perform a quantitative analysis of the trap density of states (trap DOS) in PbS quantum dot field-effect transistors (QD-FETs), which utilize several polymer gate insulators with a wide range of dielectric constants. With increasing gate dielectric constant, we observe increasing trap DOS close to the lowest unoccupied molecular orbital (LUMO) of the QDs. In addition, this increase is also consistently followed by broadening of the trap DOS. We rationalize that the increase and broadening of the spectral trap distribution originate from dipolar disorder as well as polaronic interactions, which are appearing at strong dielectric polarization. Interestingly, the increased polaron-induced traps do not show any negative effect on the charge carrier mobility in our QD devices at the highest applied gate voltage, giving the possibility to fabricate efficient low-voltage QD devices without suppressing carrier transport.

Hysteresis mechanism and control in pentacene organic field-effect transistors with polymer dielectric

Directory of Open Access Journals (Sweden)

Wei Huang

2013-05-01

Full Text Available Hysteresis mechanism of pentacene organic field-effect transistors (OFETs with polyvinyl alcohol (PVA and/or polymethyl methacrylate (PMMA dielectrics is studied. Through analyzing the electrical characteristics of OFETs with various PVA/PMMA arrangements, it shows that charge, which is trapped in PVA bulk and at the interface of pentacene/PVA, is one of the origins of hysteresis. The results also show that memory window is proportional to both trap amount in PVA and charge density at the gate/PVA or PVA/pentacene interfaces. Hence, the controllable memory window of around 0 ∼ 10 V can be realized by controlling the thickness and combination of triple-layer polymer dielectrics.

Method for double-sided processing of thin film transistors

Science.gov (United States)

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2008-04-08

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

Science.gov (United States)

Marmon, Jason; Rai, Satish; Wang, Kai; Zhou, Weilie; Zhang, Yong

The pathway for CMOS technology beyond the 5-nm technology node remains unclear for both physical and technological reasons. A new transistor paradigm is required. A LET (Marmon et. al., Front. Phys. 2016, 4, No. 8) offers electronic-optical hybridization at the component level, and is capable of continuing Moore's law to the quantum scale. A LET overcomes a FET's fabrication complexity, e.g., physical gate and doping, by employing optical gating and photoconductivity, while multiple independent, optical gates readily realize unique functionalities. We report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs, incorporating an M-S-M structure, show output and transfer characteristics resembling advanced FETs, e.g., on/off ratios up to 106 with a source-drain voltage of 1.43V, gate-power of 260nW, and a subthreshold swing of 0.3nW/decade (excluding losses). A LET has potential for high-switching (THz) speeds and extremely low-switching energies (aJ) in the ballistic transport region. Our work offers new electronic-optical integration strategies for high speed and low energy computing approaches, which could potentially be extended to other materials and devices.

Improved performance of InSe field-effect transistors by channel encapsulation

Science.gov (United States)

Liang, Guangda; Wang, Yiming; Han, Lin; Yang, Zai-Xing; Xin, Qian; Kudrynskyi, Zakhar R.; Kovalyuk, Zakhar D.; Patanè, Amalia; Song, Aimin

2018-06-01

Due to the high electron mobility and photo-responsivity, InSe is considered as an excellent candidate for next generation electronics and optoelectronics. In particular, in contrast to many high-mobility two-dimensional (2D) materials, such as phosphorene, InSe is more resilient to oxidation in air. Nevertheless, its implementation in future applications requires encapsulation techniques to prevent the adsorption of gas molecules on its surface. In this work, we use a common lithography resist, poly(methyl methacrylate) (PMMA) to encapsulate InSe-based field-effect transistors (FETs). The encapsulation of InSe by PMMA improves the electrical stability of the FETs under a gate bias stress, and increases both the drain current and electron mobility. These findings indicate the effectiveness of the PMMA encapsulation method, which could be applied to other 2D materials.

Modeling and simulation of 4H-SiC field effect transistor

Science.gov (United States)

Pedryc, A.; Martychowiec, A.; Kociubiński, A.

2017-08-01

This paper presents the technological issue of silicon carbide MOSFET design. Through the use of simulations of silicon carbide transistor, the influence of the different the technological parameters are described and discussed. MOSFET transistor was performed in Silvaco TCAD using technology elaborated at Lublin University of Technology. The most important parameters related to ion implantation, which was used in p-i-n photodiode technology. The electrical simulations were performed, transfer and output characteristics for different values of technological parameters were generated - influence of gate oxide thickness on threshold voltage and influence of channel length modulation were checked. The results of simulations as well as transfer and output characteristics allowed to select optimal parameters between expected device working and available technology - gate oxide thickness and transistor channel length were established. This work was in fact carried out to increase our understanding of the device characteristics so as to allow the design of new SiC circuits which could meet the stressful requirements of ultraviolet detector systems.

N Channel JFET Based Digital Logic Gate Structure

Science.gov (United States)

Krasowski, Michael J (Inventor)

2013-01-01

An apparatus is provided that includes a first field effect transistor with a source tied to zero volts and a drain tied to voltage drain drain (Vdd) through a first resistor. The apparatus also includes a first node configured to tie a second resistor to a third resistor and connect to an input of a gate of the first field effect transistor in order for the first field effect transistor to receive a signal. The apparatus also includes a second field effect transistor configured as a unity gain buffer having a drain tied to Vdd and an uncommitted source.

Comparison of different surface passivation dielectrics in AlGaN/GaN heterostructure field-effect transistors

International Nuclear Information System (INIS)

Tan, W.S.; Parbrook, P.J.; Hill, G.; Airey, R.J.; Houston, P.A.

2002-01-01

Different dielectrics were used for post-processing surface passivation of AlGaN/GaN heterostructure field-effect transistors (HFETs) and the resulting electrical characteristics examined. An increase in the maximum drain current of approximately 25% was observed after Si 3 N 4 and SiO 2 deposition and ∼15% for annealed SiO on AlGaN/GaN HFETs. In all cases, the passivation was found to increase the gate leakage current with an observed reduction in the leakage activation energy. However, the rise in gate leakage current was least for SiO. The plasma enhanced chemical vapour deposition method was found not to contribute to the passivation mechanism, whilst the presence of Si appears to be an important factor. (author)

Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations

Science.gov (United States)

Chambonneau, Maxime; Souiki-Figuigui, Sarra; Chiquet, Philippe; Della Marca, Vincenzo; Postel-Pellerin, Jérémy; Canet, Pierre; Portal, Jean-Michel; Grojo, David

2017-04-01

We demonstrate that infrared femtosecond laser pulses with intensity above the two-photon ionization threshold of crystalline silicon induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor transistor devices. With repeated irradiations of Flash memory cells, we show how the laser-produced free-electrons naturally redistribute on both sides of the tunnel oxide until the electric field of the transistor is suppressed. This ability enables us to determine in a nondestructive, rapid and contactless way the flat band and the neutral threshold voltages of the tested device. The physical mechanisms including nonlinear ionization, quantum tunneling of free-carriers, and flattening of the band diagram are discussed for interpreting the experiments. The possibility to control the carriers in memory transistors with ultrashort pulses holds promises for fast and remote device analyses (reliability, security, and defectivity) and for considerable developments in the growing field of ultrafast microelectronics.

Plasma-assisted ohmic contact for AlGaN/GaN heterostructure field-effect transistors

International Nuclear Information System (INIS)

Zhang, Jiaqi; Wang, Lei; Wang, Qingpeng; Jiang, Ying; Li, Liuan; Ao, Jin-Ping; Zhu, Huichao

2016-01-01

An Al-based ohmic process assisted by an inductively coupled plasma (ICP) recess treatment is proposed for AlGaN/GaN heterostructure field-effect transistors (HFETs) to realize ohmic contact, which is only needed to anneal at 500 °C. The recess treatment was done with SiCl 4 plasma with 100 W ICP power for 20 s and annealing at 575 °C for 1 min. Under these conditions, contact resistance of 0.52 Ωmm was confirmed. To suppress the ball-up phenomenon and improve the surface morphology, an Al/TiN structure was also fabricated with the same conditions. The contact resistance was further improved to 0.30 Ωmm. By using this plasma-assisted ohmic process, a gate-first HFET was fabricated. The device showed high drain current density and high transconductance. The leakage current of the TiN-gate device decreased to 10 −9 A, which was 5 orders of magnitude lower than that of the device annealed at 800 °C. The results showed that the low-temperature ohmic contact process assisted by ICP treatment is promising for the fabrication of gate-first and self-aligned gate HFETs. (paper)

Temperature-dependent field-effect carrier mobility in organic thin-film transistors with a gate SiO2 dielectric modified by H2O2 treatment

Science.gov (United States)

Lin, Yow-Jon; Hung, Cheng-Chun

2018-02-01

The effect of the modification of a gate SiO2 dielectric using an H2O2 solution on the temperature-dependent behavior of carrier transport for pentacene-based organic thin-film transistors (OTFTs) is studied. H2O2 treatment leads to the formation of Si(-OH) x (i.e., the formation of a hydroxylated layer) on the SiO2 surface that serves to reduce the SiO2 capacitance and weaken the pentacene-SiO2 interaction, thus increasing the field-effect carrier mobility ( µ) in OTFTs. The temperature-dependent behavior of carrier transport is dominated by the multiple trapping model. Note that H2O2 treatment leads to a reduction in the activation energy. The increased value of µ is also attributed to the weakening of the interactions of the charge carriers with the SiO2 dielectric that serves to reduce the activation energy.

The Hall coefficient: a tool for characterizing graphene field effect transistors

International Nuclear Information System (INIS)

Wehrfritz, Peter; Seyller, Thomas

2014-01-01

Graphene field effect transistors are considered as a candidate for future high-frequency applications. For their realization, the optimal combination of substrate, graphene preparation, and insulator deposition and composition is required. This optimization must be based on an in-depth characterization of the obtained graphene insulator metal (GIM) stack. Hall effect measurements are frequently employed to study such systems, thereby focussing primarily on the charge carrier mobility. In this work we show how an analysis of the sheet Hall coefficient can reveal further important properties of the GIM stack, like, e.g., the interface trap density and the spacial charge inhomogeneity. To that end, we provide an extensive description of the GIM diode, which leads to an accurate calculation of the sheet Hall coefficient dependent on temperature and gate voltage. The gate dependent inverse sheet Hall coefficient is discussed in detail before we introduce the concept of an equivalent temperature, which is a measure of the spacial charge inhomogeneity. In order to test the concept, we apply it to evaluate already measured Hall data taken from the literature. This evaluation allows us to determine the Drude mobility, even at the charge neutrality point, which is inaccessible with a simple one band Hall mobility analysis, and to shed light on the spacial charge inhomogeneity. The formalism is easily adaptable and provides experimentalists a powerful tool for the characterization of their graphene field effect devices. (paper)

Nonplanar Nanoscale Fin Field Effect Transistors on Textile, Paper, Wood, Stone, and Vinyl via Soft Material-Enabled Double-Transfer Printing.

Science.gov (United States)

Rojas, Jhonathan P; Torres Sevilla, Galo A; Alfaraj, Nasir; Ghoneim, Mohamed T; Kutbee, Arwa T; Sridharan, Ashvitha; Hussain, Muhammad Mustafa

2015-05-26

The ability to incorporate rigid but high-performance nanoscale nonplanar complementary metal-oxide semiconductor (CMOS) electronics with curvilinear, irregular, or asymmetric shapes and surfaces is an arduous but timely challenge in enabling the production of wearable electronics with an in situ information-processing ability in the digital world. Therefore, we are demonstrating a soft-material enabled double-transfer-based process to integrate flexible, silicon-based, nanoscale, nonplanar, fin-shaped field effect transistors (FinFETs) and planar metal-oxide-semiconductor field effect transistors (MOSFETs) on various asymmetric surfaces to study their compatibility and enhanced applicability in various emerging fields. FinFET devices feature sub-20 nm dimensions and state-of-the-art, high-κ/metal gate stacks, showing no performance alteration after the transfer process. A further analysis of the transferred MOSFET devices, featuring 1 μm gate length, exhibits an ION value of nearly 70 μA/μm (VDS = 2 V, VGS = 2 V) and a low subthreshold swing of around 90 mV/dec, proving that a soft interfacial material can act both as a strong adhesion/interposing layer between devices and final substrate as well as a means to reduce strain, which ultimately helps maintain the device's performance with insignificant deterioration even at a high bending state.

Investigation on the corner effect of L-shaped tunneling field-effect transistors and their fabrication method.

Science.gov (United States)

Kim, Sang Wan; Choi, Woo Young; Sun, Min-Chul; Park, Byung-Gook

2013-09-01

In this work, electrical characteristics of L-shaped tunneling field-effect transistors (TFETs) have been studied and optimized by a commercial device simulator: Synopsys Sentaurus. Unlike our previous study performed by using Silvaco Atlas, there exists a kink phenomenon in a transfer curve which degrades the subthreshold swing (SS) and on-current (lon) of TFETs. According to simulation results, the kink results from abrupt source doping. Rounding the source junction edge with gradual doping profile is helpful to alleviate it. Based on those results, a novel fabrication flow has been proposed to suppress the kink effect induced by source corners. It is predicted that the performance of L-shaped TFETs is improved in terms of SS and Ion under the optimized process condition. Furthremore, the effect of high-k gate dielectric and narrow band gap material on device performance has been examined. Using 2-nm-thick HfO2 for gate dielectric and Si0.7Ge0.3 for intrinsic tunneling region, gate controllability to the channel and tunneling probability have been enhanced. As a result, its threshold voltage (Vth), SS and Ion have been improved by 0.13 V, 16 mV/dec, and 3.62 microA/microm, respectively.

Direct Effect of Dielectric Surface Energy on Carrier Transport in Organic Field-Effect Transistors.

Science.gov (United States)

Zhou, Shujun; Tang, Qingxin; Tian, Hongkun; Zhao, Xiaoli; Tong, Yanhong; Barlow, Stephen; Marder, Seth R; Liu, Yichun

2018-05-09

The understanding of the characteristics of gate dielectric that leads to optimized carrier transport remains controversial, and the conventional studies applied organic semiconductor thin films, which introduces the effect of dielectric on the growth of the deposited semiconductor thin films and hence only can explore the indirect effects. Here, we introduce pregrown organic single crystals to eliminate the indirect effect (semiconductor growth) in the conventional studies and to undertake an investigation of the direct effect of dielectric on carrier transport. It is shown that the matching of the polar and dispersive components of surface energy between semiconductor and dielectric is favorable for higher mobility. This new empirical finding may show the direct relationship between dielectric and carrier transport for the optimized mobility of organic field-effect transistors and hence show a promising potential for the development of next-generation high-performance organic electronic devices.

Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

International Nuclear Information System (INIS)

Wan, Chang Jin; Wan, Qing; Zhu, Li Qiang; Wan, Xiang; Shi, Yi

2016-01-01

The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors

Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

Energy Technology Data Exchange (ETDEWEB)

Wan, Chang Jin; Wan, Qing, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn [School of Electronic Science & Engineering, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China); Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Zhu, Li Qiang [Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Wan, Xiang; Shi, Yi, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn [School of Electronic Science & Engineering, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)

2016-01-25

The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors.