Pentacene based thin film transistors with high-k dielectric Nd2O3 as a gate insulator

International Nuclear Information System (INIS)

Sarma, R.; Saikia, D.

2010-01-01

We have investigated the pentacene based Organic Thin Film Transistors (OTFTs) with high-k dielectric Nd 2 O 3 . Use of high dielectric constant (high-k) gate insulator Nd 2 O 3 reduces the threshold voltage and sub threshold swing of the OTFTs. The calculated threshold voltage -2.2V and sub-threshold swing 1V/decade, current ON-OFF ratio is 1.7 X 10 4 and mobility is 0.13cm 2 /V.s. Pentacene film is deposited on Nd 2 O 3 surface using two step deposition method. Deposited pentacene film is found poly crystalline in nature. (author)

Tungsten trioxide as high-{kappa} gate dielectric for highly transparent and temperature-stable zinc-oxide-based thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Lorenz, Michael; Wenckstern, Holger von; Grundmann, Marius [Universitaet Leipzig, Fakultaet fuer Physik und Geowissenschaften, Institut fuer Experimentelle Physik II, Linnestr. 5, 04103 Leipzig (Germany)

2012-07-01

We demonstrate metal-insulator-semiconductor field-effect transistors with high-{kappa}, room-temperature deposited, highly transparent tungsten trioxide (WO{sub 3}) as gate dielectric. The channel material consists of a zinc oxide (ZnO) thin-film. The transmittance and resistivity of WO{sub 3} films was tuned in order to obtain a highly transparent and insulating WO{sub 3} dielectric. The devices were processed by standard photolithography using lift-off technique. On top of the WO{sub 3} dielectric a highly transparent and conductive oxide consisting of ZnO: Al 3% wt. was deposited. The gate structure of the devices exhibits an average transmittance in the visible spectral range of 86%. The on/off-current ratio is larger than 10{sup 8} with off- and gate leakage-currents below 3 x 10{sup -8} A/cm{sup 2}. Due to the high relative permittivity of {epsilon}{sub r} {approx} 70, a gate voltage sweep of only 2 V is necessary to turn the transistor on and off with a minimum subthreshold swing of 80 mV/decade. The channel mobility of the transistors equals the Hall-effect mobility with a value of 5 cm{sup 2}/Vs. It is furthermore shown, that the devices are stable up to operating temperatures of at least 150 C.

Plasma nitridation optimization for sub-15 A gate dielectrics

NARCIS (Netherlands)

Cubaynes, F.N; Schmitz, Jurriaan; van der Marel, C.; Snijders, J.H.M.; Veloso, A.; Rothschild, A.; Olsen, C.; Date, L.

The work investigates the impact of plasma nitridation process parameters upon the physical properties and upon the electrical performance of sub-15 A plasma nitrided gate dielectrics. The nitrogen distribution and chemical bonding of ultra-thin plasma nitrided films have been investigated using

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

Science.gov (United States)

Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

Direct deposition of aluminum oxide gate dielectric on graphene channel using nitrogen plasma treatment

International Nuclear Information System (INIS)

Lim, Taekyung; Kim, Dongchool; Ju, Sanghyun

2013-01-01

Deposition of high-quality dielectric on a graphene channel is an essential technology to overcome structural constraints for the development of nano-electronic devices. In this study, we investigated a method for directly depositing aluminum oxide (Al 2 O 3 ) on a graphene channel through nitrogen plasma treatment. The deposited Al 2 O 3 thin film on graphene demonstrated excellent dielectric properties with negligible charge trapping and de-trapping in the gate insulator. A top-gate-structural graphene transistor was fabricated using Al 2 O 3 as the gate dielectric with nitrogen plasma treatment on graphene channel region, and exhibited p-type transistor characteristics

SEMICONDUCTOR DEVICES: Structural and electrical characteristics of lanthanum oxide gate dielectric film on GaAs pHEMT technology

Science.gov (United States)

Chia-Song, Wu; Hsing-Chung, Liu

2009-11-01

This paper investigates the feasibility of using a lanthanum oxide thin film (La2O3) with a high dielectric constant as a gate dielectric on GaAs pHEMTs to reduce gate leakage current and improve the gate to drain breakdown voltage relative to the conventional GaAs pHEMT. An E/D mode pHEMT in a single chip was realized by selecting the appropriate La2O3 thickness. The thin La2O3 film was characterized: its chemical composition and crystalline structure were determined by X-ray photoelectron spectroscopy and X-ray diffraction, respectively. La2O3 exhibited good thermal stability after post-deposition annealing at 200, 400 and 600 °C because of its high binding-energy (835.6 eV). Experimental results clearly demonstrated that the La2O3 thin film was thermally stable. The DC and RF characteristics of Pt/La2O3/Ti/Au gate and conventional Pt/Ti/Au gate pHEMTs were examined. The measurements indicated that the transistor with the Pt/La2O3/Ti/Au gate had a higher breakdown voltage and lower gate leakage current. Accordingly, the La2O3 thin film is a potential high-k material for use as a gate dielectric to improve electrical performance and the thermal effect in high-power applications.

Investigation of Ultraviolet Light Curable Polysilsesquioxane Gate Dielectric Layers for Pentacene Thin Film Transistors.

Science.gov (United States)

Shibao, Hideto; Nakahara, Yoshio; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) comprising 3-methacryloxypropyl groups was investigated as an ultraviolet (UV)-light curable gate dielectric-material for pentacene thin film transistors (TFTs). The surface of UV-light cured PSQ films was smoother than that of thermally cured ones, and the pentacene layers deposited on the UV-Iight cured PSQ films consisted of larger grains. However, carrier mobility of the TFTs using the UV-light cured PSQ films was lower than that of the TFTs using the thermally cured ones. It was shown that the cross-linker molecules, which were only added to the UV-light cured PSQ films, worked as a major mobility-limiting factor for the TFTs.

Pentacene thin-film transistors and inverters with plasma-enhanced atomic-layer-deposited Al2O3 gate dielectric

International Nuclear Information System (INIS)

Koo, Jae Bon; Lim, Jung Wook; Kim, Seong Hyun; Yun, Sun Jin; Ku, Chan Hoe; Lim, Sang Chul; Lee, Jung Hun

2007-01-01

The performances of pentacene thin-film transistor with plasma-enhanced atomic-layer-deposited (PEALD) 150 nm thick Al 2 O 3 dielectric are reported. Saturation mobility of 0.38 cm 2 /V s, threshold voltage of 1 V, subthreshold swing of 0.6 V/decade, and on/off current ratio of about 10 8 have been obtained. Both depletion and enhancement mode inverter have been realized with the change of treatment method of hexamethyldisilazane on PEALD Al 2 O 3 gate dielectric. Full swing depletion mode inverter has been demonstrated at input voltages ranging from 5 V to - 5 V at supply voltage of - 5 V

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors.

Science.gov (United States)

Chen, Fa-Hsyang; Her, Jim-Long; Shao, Yu-Hsuan; Matsuda, Yasuhiro H; Pan, Tung-Ming

2013-01-08

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric.

Low-temperature fabrication of sputtered high-k HfO2 gate dielectric for flexible a-IGZO thin film transistors

Science.gov (United States)

Yao, Rihui; Zheng, Zeke; Xiong, Mei; Zhang, Xiaochen; Li, Xiaoqing; Ning, Honglong; Fang, Zhiqiang; Xie, Weiguang; Lu, Xubing; Peng, Junbiao

2018-03-01

In this work, low temperature fabrication of a sputtered high-k HfO2 gate dielectric for flexible a-IGZO thin film transistors (TFTs) on polyimide substrates was investigated. The effects of Ar-pressure during the sputtering process and then especially the post-annealing treatments at low temperature (≤200 °C) for HfO2 on reducing the density of defects in the bulk and on the surface were systematically studied. X-ray reflectivity, UV-vis and X-ray photoelectron spectroscopy, and micro-wave photoconductivity decay measurements were carried out and indicated that the high quality of optimized HfO2 film and its high dielectric properties contributed to the low concentration of structural defects and shallow localized defects such as oxygen vacancies. As a result, the well-structured HfO2 gate dielectric exhibited a high density of 9.7 g/cm3, a high dielectric constant of 28.5, a wide optical bandgap of 4.75 eV, and relatively low leakage current. The corresponding flexible a-IGZO TFT on polyimide exhibited an optimal device performance with a saturation mobility of 10.3 cm2 V-1 s-1, an Ion/Ioff ratio of 4.3 × 107, a SS value of 0.28 V dec-1, and a threshold voltage (Vth) of 1.1 V, as well as favorable stability under NBS/PBS gate bias and bending stress.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

OpenAIRE

Roeckerath, M.; Lopes, J. M. J.; Durgun Özben, E.; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D.G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of < 1 nA/cm(2). Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated ...

Enhanced ZnO Thin-Film Transistor Performance Using Bilayer Gate Dielectrics

KAUST Repository

Alshammari, Fwzah Hamud; Nayak, Pradipta K.; Wang, Zhenwei; Alshareef, Husam N.

2016-01-01

We report ZnO TFTs using Al2O3/Ta2O5 bilayer gate dielectrics grown by atomic layer deposition. The saturation mobility of single layer Ta2O5 dielectric TFT was 0.1 cm2 V-1 s-1, but increased to 13.3 cm2 V-1 s-1 using Al2O3/Ta2O5 bilayer dielectric with significantly lower leakage current and hysteresis. We show that point defects present in ZnO film, particularly VZn, are the main reason for the poor TFT performance with single layer dielectric, although interfacial roughness scattering effects cannot be ruled out. Our approach combines the high dielectric constant of Ta2O5 and the excellent Al2O3/ZnO interface quality, resulting in improved device performance. © 2016 American Chemical Society.

Enhanced ZnO Thin-Film Transistor Performance Using Bilayer Gate Dielectrics

KAUST Repository

Alshammari, Fwzah Hamud

2016-08-24

We report ZnO TFTs using Al2O3/Ta2O5 bilayer gate dielectrics grown by atomic layer deposition. The saturation mobility of single layer Ta2O5 dielectric TFT was 0.1 cm2 V-1 s-1, but increased to 13.3 cm2 V-1 s-1 using Al2O3/Ta2O5 bilayer dielectric with significantly lower leakage current and hysteresis. We show that point defects present in ZnO film, particularly VZn, are the main reason for the poor TFT performance with single layer dielectric, although interfacial roughness scattering effects cannot be ruled out. Our approach combines the high dielectric constant of Ta2O5 and the excellent Al2O3/ZnO interface quality, resulting in improved device performance. © 2016 American Chemical Society.

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO₂ Gate Dielectrics by CF₄ Plasma Treatment.

Science.gov (United States)

Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

2018-05-17

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO₂ gate insulator and CF₄ plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO₂ gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm²/V∙s (without treatment) to 54.6 cm²/V∙s (with CF₄ plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO₂ gate dielectric has also been improved by the CF₄ plasma treatment. By applying the CF₄ plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device's immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF₄ plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO₂ gate dielectric, but also enhances the device's reliability.

Thin film transistors for flexible electronics: Contacts, dielectrics and semiconductors

KAUST Repository

Quevedo-López, Manuel Angel Quevedo

2011-06-01

The development of low temperature, thin film transistor processes that have enabled flexible displays also present opportunities for flexible electronics and flexible integrated systems. Of particular interest are possible applications in flexible sensor systems for unattended ground sensors, smart medical bandages, electronic ID tags for geo-location, conformal antennas, radiation detectors, etc. In this paper, we review the impact of gate dielectrics, contacts and semiconductor materials on thin film transistors for flexible electronics applications. We present our recent results to fully integrate hybrid complementary metal oxide semiconductors comprising inorganic and organic-based materials. In particular, we demonstrate novel gate dielectric stacks and semiconducting materials. The impact of source and drain contacts on device performance is also discussed. Copyright © 2011 American Scientific Publishers.

Thin film transistors for flexible electronics: Contacts, dielectrics and semiconductors

KAUST Repository

Quevedo-Ló pez, Manuel Angel Quevedo; Wondmagegn, Wudyalew T.; Alshareef, Husam N.; Ramí rez-Bon, Rafael; Gnade, Bruce E.

2011-01-01

The development of low temperature, thin film transistor processes that have enabled flexible displays also present opportunities for flexible electronics and flexible integrated systems. Of particular interest are possible applications in flexible sensor systems for unattended ground sensors, smart medical bandages, electronic ID tags for geo-location, conformal antennas, radiation detectors, etc. In this paper, we review the impact of gate dielectrics, contacts and semiconductor materials on thin film transistors for flexible electronics applications. We present our recent results to fully integrate hybrid complementary metal oxide semiconductors comprising inorganic and organic-based materials. In particular, we demonstrate novel gate dielectric stacks and semiconducting materials. The impact of source and drain contacts on device performance is also discussed. Copyright © 2011 American Scientific Publishers.

Sodium beta-alumina thin films as gate dielectrics for AlGaN/GaN metal—insulator—semiconductor high-electron-mobility transistors

International Nuclear Information System (INIS)

Tian Ben-Lang; Chen Chao; Li Yan-Rong; Zhang Wan-Li; Liu Xing-Zhao

2012-01-01

Sodium beta-alumina (SBA) is deposited on AlGaN/GaN by using a co-deposition process with sodium and Al 2 O 3 as the precursors. The X-ray diffraction (XRD) spectrum reveals that the deposited thin film is amorphous. The binding energy and composition of the deposited thin film, obtained from the X-ray photoelectron spectroscopy (XPS) measurement, are consistent with those of SBA. The dielectric constant of the SBA thin film is about 50. Each of the capacitance—voltage characteristics obtained at five different frequencies shows a high-quality interface between SBA and AlGaN. The interface trap density of metal—insulator—semiconductor high-electron-mobility transistor (MISHEMT) is measured to be (3.5∼9.5)×10 10 cm −2 ·eV −1 by the conductance method. The fixed charge density of SBA dielectric is on the order of 2.7×10 12 cm −2 . Compared with the AlGaN/GaN metal—semiconductor heterostructure high-electron-mobility transistor (MESHEMT), the AlGaN/GaN MISHEMT usually has a threshold voltage that shifts negatively. However, the threshold voltage of the AlGaN/GaN MISHEMT using SBA as the gate dielectric shifts positively from −5.5 V to −3.5 V. From XPS results, the surface valence-band maximum (VBM-EF) of AlGaN is found to decrease from 2.56 eV to 2.25 eV after the SBA thin film deposition. The possible reasons why the threshold voltage of AlGaN/GaN MISHEMT with the SBA gate dielectric shifts positively are the influence of SBA on surface valence-band maximum (VBM-EF), the reduction of interface traps and the effects of sodium ions, and/or the fixed charges in SBA on the two-dimensional electron gas (2DEG). (condensed matter: structural, mechanical, and thermal properties)

High-Mobility 6,13-Bis(triisopropylsilylethynyl) Pentacene Transistors Using Solution-Processed Polysilsesquioxane Gate Dielectric Layers.

Science.gov (United States)

Matsuda, Yu; Nakahara, Yoshio; Michiura, Daisuke; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) is a low-temperature curable polymer that is compatible with low-cost plastic substrates. We cured PSQ gate dielectric layers by irradiation with ultraviolet light at ~60 °C, and used them for 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) thin film transistors (TFTs). The fabricated TFTs have shown the maximum and average hole mobility of 1.3 and 0.78 ± 0.3 cm2V-1s-1, which are comparable to those of the previously reported transistors using single-crystalline TIPS-pentacene micro-ribbons for their active layers and thermally oxidized SiO2 for their gate dielectric layers. Itis therefore demonstrated that PSQ is a promising polymer gate dielectric material for low-cost organic TFTs.

Pulsed laser deposition of oxide gate dielectrics for pentacene organic field-effect transistors

International Nuclear Information System (INIS)

Yaginuma, S.; Yamaguchi, J.; Itaka, K.; Koinuma, H.

2005-01-01

We have fabricated Al 2 O 3 , LaAlO 3 (LAO), CaHfO 3 (CHO) and CaZrO 3 (CZO) thin films for the dielectric layers of field-effect transistors (FETs) by pulsed laser deposition (PLD). The films exhibited very smooth surfaces with root-mean-squares (rms) roughnesses of ∼1.3 A as evaluated by using atomic force microscopy (AFM). The breakdown electric fields of Al 2 O 3 , LAO, CHO and CZO films were 7, 6, 10 and 2 MV/cm, respectively. The magnitude of the leak current in each film was low enough to operate FET. We performed a comparative study of pentacene FET fabricated using these oxide dielectrics as gate insulators. High field-effect mobility of 1.4 cm 2 /V s and on/off current ratio of 10 7 were obtained in the pentacene FET using LAO gate insulating film. Use of the LAO films as gate dielectrics has been found to suppress the hysteresis of pentacene FET operations. The LAO films are relevant to the dielectric layer of organic FETs

AlGaN/GaN MISHEMTs with AlN gate dielectric grown by thermal ALD technique.

Science.gov (United States)

Liu, Xiao-Yong; Zhao, Sheng-Xun; Zhang, Lin-Qing; Huang, Hong-Fan; Shi, Jin-Shan; Zhang, Chun-Min; Lu, Hong-Liang; Wang, Peng-Fei; Zhang, David Wei

2015-01-01

Recently, AlN plasma-enhanced atomic layer deposition (ALD) passivation technique had been proposed and investigated for suppressing the dynamic on-resistance degradation behavior of high-electron-mobility transistors (HEMTs). In this paper, a novel gate dielectric and passivation technique for GaN-on-Si AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMTs) is presented. This technique features the AlN thin film grown by thermal ALD at 400°C without plasma enhancement. A 10.6-nm AlN thin film was grown upon the surface of the HEMT serving as the gate dielectric under the gate electrode and as the passivation layer in the access region at the same time. The MISHEMTs with thermal ALD AlN exhibit enhanced on/off ratio, reduced channel sheet resistance, reduction of gate leakage by three orders of magnitude at a bias of 4 V, reduced threshold voltage hysteresis of 60 mV, and suppressed current collapse degradation.

High performance top-gated indium–zinc–oxide thin film transistors with in-situ formed HfO{sub 2} gate insulator

Energy Technology Data Exchange (ETDEWEB)

Song, Yang, E-mail: yang_song@brown.edu [Department of Physics, Brown University, 182 Hope Street, Providence, RI 02912 (United States); Zaslavsky, A. [Department of Physics, Brown University, 182 Hope Street, Providence, RI 02912 (United States); School of Engineering, Brown University, 184 Hope Street, Providence, RI 02912 (United States); Paine, D.C. [School of Engineering, Brown University, 184 Hope Street, Providence, RI 02912 (United States)

2016-09-01

We report on top-gated indium–zinc–oxide (IZO) thin film transistors (TFTs) with an in-situ formed HfO{sub 2} gate dielectric insulator. Building on our previous demonstration of high-performance IZO TFTs with Al{sub 2}O{sub 3}/HfO{sub 2} gate dielectric, we now report on a one-step process, in which Hf is evaporated onto the 20 nm thick IZO channel, forming a partially oxidized HfO{sub x} layer, without any additional insulator in-between. After annealing in air at 300 °C, the in-situ reaction between partially oxidized Hf and IZO forms a high quality HfO{sub 2} gate insulator with a low interface trapped charge density N{sub TC} ~ 2.3 × 10{sup 11} cm{sup −2} and acceptably low gate leakage < 3 × 10{sup −7} A/cm{sup 2} at gate voltage V{sub G} = 1 V. The annealed TFTs with gate length L{sub G} = 50 μm have high mobility ~ 95 cm{sup 2}/V ∙ s (determined via the Y-function technique), high on/off ratio ~ 10{sup 7}, near-zero threshold voltage V{sub T} = − 0.02 V, and a subthreshold swing of 0.062 V/decade, near the theoretical limit. The on-current of our proof-of-concept TFTs is relatively low, but can be improved by reducing L{sub G}, indicating that high-performance top-gated HfO{sub 2}-isolated IZO TFTs can be fabricated using a single-step in-situ dielectric formation approach. - Highlights: • High-performance indium–zinc–oxide (IZO) thin film transistors (TFTs). • Single-step in-situ dielectric formation approach simplifies fabrication process. • During anneal, reaction between HfO{sub x} and IZO channel forms a high quality HfO{sub 2} layer. • Gate insulator HfO{sub 2} shows low interface trapped charge and small gate leakage. • TFTs have high mobility, near-zero threshold voltage, and a low subthreshold swing.

Effect of annealing temperature on structural and electrical properties of high-κ YbTixOy gate dielectrics for InGaZnO thin film transistors

International Nuclear Information System (INIS)

Pan, Tung-Ming; Chen, Fa-Hsyang; Hung, Meng-Ning

2015-01-01

This paper describes the effect of annealing temperature on the structural properties and electrical characteristics of high–κ YbTi x O y gate dielectrics for indium–gallium–zinc–oxide (IGZO) thin-film transistors (TFTs). X-ray diffraction, x-ray photoelectron spectroscopy and atomic force microscopy were used to study the structural, chemical and morphological features, respectively, of these dielectric films annealed at 200, 300 and 400 °C. The YbTi x O y IGZO TFT that had been annealed at 400 °C exhibited better electrical characteristics, such as a small threshold voltage of 0.53 V, a large field-effect mobility of 19.1 cm 2 V −1 s −1 , a high I on /I off ratio of 2.8 × 10 7 , and a low subthreshold swing of 176 mV dec. −1 , relative to those of the systems that had been subjected to other annealing conditions. This result suggests that YbTi x O y dielectric possesses a higher dielectric constant as well as lower oxygen vacancies (or defects) in the film. In addition, the instability of YbTi x O y IGZO TFT was studied under positive gate-bias stress and negative gate-bias stress conditions. (paper)

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO2 Gate Dielectrics by CF4 Plasma Treatment

Science.gov (United States)

Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

2018-01-01

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO2 gate insulator and CF4 plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO2 gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm2/V∙s (without treatment) to 54.6 cm2/V∙s (with CF4 plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO2 gate dielectric has also been improved by the CF4 plasma treatment. By applying the CF4 plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device’s immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF4 plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO2 gate dielectric, but also enhances the device’s reliability. PMID:29772767

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO2 Gate Dielectrics by CF4 Plasma Treatment

Directory of Open Access Journals (Sweden)

Ching-Lin Fan

2018-05-01

Full Text Available In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs with a HfO2 gate insulator and CF4 plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO2 gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm2/V∙s (without treatment to 54.6 cm2/V∙s (with CF4 plasma treatment, which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO2 gate dielectric has also been improved by the CF4 plasma treatment. By applying the CF4 plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device’s immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF4 plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO2 gate dielectric, but also enhances the device’s reliability.

The electrical performance and gate bias stability of an amorphous InGaZnO thin-film transistor with HfO2 high-k dielectrics

Science.gov (United States)

Wang, Ruo Zheng; Wu, Sheng Li; Li, Xin Yu; Zhang, Jin Tao

2017-07-01

In this study, we set out to fabricate an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with SiNx/HfO2/SiNx (SHS) sandwiched dielectrics. The J-V and C-V of this SHS film were extracted by the Au/p-Si/SHS/Ti structure. At room temperature the a-IGZO with SHS dielectrics showed the following electrical properties: a threshold voltage of 2.9 V, a subthreshold slope of 0.35 V/decade, an on/off current ratio of 3.5 × 107, and a mobility of 12.8 cm2 V-1 s-1. Finally, we tested the influence of gate bias stress on the TFT, and the result showed that the threshold voltage shifted to a positive voltage when applying a positive gate voltage to the TFT.

High-performance pentacene OTFT by incorporating Ti in LaON gate dielectric

Science.gov (United States)

Ma, Y. X.; Han, C. Y.; Tang, W. M.; Lai, P. T.

2017-07-01

Pentacene organic thin-film transistors (OTFT) using high-k LaTiON gate dielectric with different Ti contents are investigated. The LaxTi(1-x)ON films (with x = 1, 0.87, 0.76, and 0.67) are deposited by reactive sputtering followed by an annealing in N2 at 200 °C. The OTFT with La0.87Ti0.13ON can achieve a high carrier mobility of 2.6 cm2/V.s, a small threshold voltage of -1.5 V, a small sub-threshold swing of 0.07 V/dec, and a small hysteresis of 0.17 V. AFM and X-ray photoelectron spectroscopy reveal that Ti can suppress the hygroscopicity of La oxide to achieve a smoother dielectric surface, which can result in larger pentacene grains and thus higher carrier mobility. All the devices show a clockwise hysteresis because both the LaOH formation and Ti incorporation can generate acceptor-like traps in the gate dielectric.

Comparative studies of AlGaN/GaN MOS-HEMTs with stacked gate dielectrics by the mixed thin film growth method

International Nuclear Information System (INIS)

Chou, Bo-Yi; Hsu, Wei-Chou; Liu, Han-Yin; Ho, Chiu-Sheng; Lee, Ching-Sung

2013-01-01

This paper reports Al 0.27 Ga 0.73 N/GaN metal–oxide–semiconductor high electron mobility transistors (MOS-HEMTs) with stacked Al 2 O 3 /HfO 2 gate dielectrics by using hydrogen peroxideoxidation/sputtering techniques. The Al 2 O 3 employed as a gate dielectric and surface passivation layer effectively suppresses the gate leakage current, improves RF drain current collapse and exhibits good thermal stability. Moreover, by stacking the good insulating high-k HfO 2 dielectric further suppresses the gate leakage, enhances the dielectric breakdown field and power-added efficiency, and decreases the equivalent oxide thickness. The present MOS-HEMT design has demonstrated superior improvements of 10.1% (16.4%) in the maximum drain–source current (I DS,max ), 11.4% (22.5%) in the gate voltage swing and 12.5%/14.4% (21.9%/22.3%) in the two-terminal gate–drain breakdown/turn-on voltages (BV GD /V ON ), and the present design also demonstrates the lowest gate leakage current and best thermal stability characteristics as compared to two reference MOS-HEMTs with a single Al 2 O 3 /(HfO 2 ) dielectric layer of the same physical thickness. (invited paper)

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

Science.gov (United States)

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

Effect of dual-dielectric hydrogen-diffusion barrier layers on the performance of low-temperature processed transparent InGaZnO thin-film transistors

Science.gov (United States)

Tari, Alireza; Wong, William S.

2018-02-01

Dual-dielectric SiOx/SiNx thin-film layers were used as back-channel and gate-dielectric barrier layers for bottom-gate InGaZnO (IGZO) thin-film transistors (TFTs). The concentration profiles of hydrogen, indium, gallium, and zinc oxide were analyzed using secondary-ion mass spectroscopy characterization. By implementing an effective H-diffusion barrier, the hydrogen concentration and the creation of H-induced oxygen deficiency (H-Vo complex) defects during the processing of passivated flexible IGZO TFTs were minimized. A bilayer back-channel passivation layer, consisting of electron-beam deposited SiOx on plasma-enhanced chemical vapor-deposition (PECVD) SiNx films, effectively protected the TFT active region from plasma damage and minimized changes in the chemical composition of the semiconductor layer. A dual-dielectric PECVD SiOx/PECVD SiNx gate-dielectric, using SiOx as a barrier layer, also effectively prevented out-diffusion of hydrogen atoms from the PECVD SiNx-gate dielectric to the IGZO channel layer during the device fabrication.

High performance organic field-effect transistors with ultra-thin HfO2 gate insulator deposited directly onto the organic semiconductor

International Nuclear Information System (INIS)

Ono, S.; Häusermann, R.; Chiba, D.; Shimamura, K.; Ono, T.; Batlogg, B.

2014-01-01

We have produced stable organic field-effect transistors (OFETs) with an ultra-thin HfO 2 gate insulator deposited directly on top of rubrene single crystals by atomic layer deposition (ALD). We find that ALD is a gentle deposition process to grow thin films without damaging rubrene single crystals, as results these devices have a negligibly small threshold voltage and are very stable against gate-bias-stress, and the mobility exceeds 1 cm 2 /V s. Moreover, the devices show very little degradation even when kept in air for more than 2 months. These results demonstrate thin HfO 2 layers deposited by ALD to be well suited as high capacitance gate dielectrics in OFETs operating at small gate voltage. In addition, the dielectric layer acts as an effective passivation layer to protect the organic semiconductor

A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

Science.gov (United States)

Wallace, Robert M.

2001-03-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

SiO2/AlON stacked gate dielectrics for AlGaN/GaN MOS heterojunction field-effect transistors

Science.gov (United States)

Watanabe, Kenta; Terashima, Daiki; Nozaki, Mikito; Yamada, Takahiro; Nakazawa, Satoshi; Ishida, Masahiro; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

Stacked gate dielectrics consisting of wide bandgap SiO2 insulators and thin aluminum oxynitride (AlON) interlayers were systematically investigated in order to improve the performance and reliability of AlGaN/GaN metal–oxide–semiconductor (MOS) devices. A significantly reduced gate leakage current compared with that in a single AlON layer was achieved with these structures, while maintaining the superior thermal stability and electrical properties of the oxynitride/AlGaN interface. Consequently, distinct advantages in terms of the reliability of the gate dielectrics, such as an improved immunity against electron injection and an increased dielectric breakdown field, were demonstrated for AlGaN/GaN MOS capacitors with optimized stacked structures having a 3.3-nm-thick AlON interlayer.

Low voltage operation of IGZO thin film transistors enabled by ultrathin Al2O3 gate dielectric

Science.gov (United States)

Ma, Pengfei; Du, Lulu; Wang, Yiming; Jiang, Ran; Xin, Qian; Li, Yuxiang; Song, Aimin

2018-01-01

An ultrathin, 5 nm, Al2O3 film grown by atomic-layer deposition was used as a gate dielectric for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The Al2O3 layer showed a low surface roughness of 0.15 nm, a low leakage current, and a high breakdown voltage of 6 V. In particular, a very high gate capacitance of 720 nF/cm2 was achieved, making it possible for the a-IGZO TFTs to not only operate at a low voltage of 1 V but also exhibit desirable properties including a low threshold voltage of 0.3 V, a small subthreshold swing of 100 mV/decade, and a high on/off current ratio of 1.2 × 107. Furthermore, even under an ultralow operation voltage of 0.6 V, well-behaved transistor characteristics were still observed with an on/off ratio as high as 3 × 106. The electron transport through the Al2O3 layer has also been analyzed, indicating the Fowler-Nordheim tunneling mechanism.

Low-voltage organic thin film transistors (OTFTs) using crosslinked polyvinyl alcohol (PVA)/neodymium oxide (Nd2O3) bilayer gate dielectrics

Science.gov (United States)

Khound, Sagarika; Sarma, Ranjit

2018-01-01

We have reported here on the design, processing and dielectric properties of pentacene-based organic thin film transitors (OTFTs) with a bilayer gate dilectrics of crosslinked PVA/Nd2O3 which enables low-voltage organic thin film operations. The dielectric characteristics of PVA/Nd2O3 bilayer films are studied by capacitance-voltage ( C- V) and current-voltage ( I- V) curves in the metal-insulator-metal (MIM) structure. We have analysed the output electrical responses and transfer characteristics of the OTFT devices to determine their performance of OTFT parameters. The mobility of 0.94 cm2/Vs, the threshold voltage of - 2.8 V, the current on-off ratio of 6.2 × 105, the subthreshold slope of 0.61 V/decade are evaluated. Low leakage current of the device is observed from current density-electric field ( J- E) curve. The structure and the morphology of the device are studied using X-ray diffraction (XRD) and atomic force microscope (AFM), respectively. The study demonstrates an effective way to realize low-voltage, high-performance OTFTs at low cost.

Feasibility study of using thin aluminum nitride film as a buffer layer for dual metal gate process

International Nuclear Information System (INIS)

Park, Chang Seo; Cho, Byung Jin; Balasubramanian, N.; Kwong, Dim-Lee

2004-01-01

We evaluated the feasibility of using an ultra thin aluminum nitride (AlN) buffer layer for dual metal gates CMOS process. Since the buffer layer should not affect the thickness of gate dielectric, it should be removed or consumed during subsequent process. In this work, it was shown that a thin AlN dielectric layer would be reacted with initial gate metals and would be consumed during subsequent annealing, resulting in no increase of equivalent oxide thickness (EOT). The reaction of AlN layer with tantalum (Ta) and hafnium (Hf) during subsequent annealing, which was confirmed with X-ray photoelectron spectroscopy (XPS) analysis, shifted the flat-band voltage of AlN buffered MOS capacitors. No contribution to equivalent oxide thickness (EOT) was also an indication showing the full consumption of AIN, which was confirmed with TEM analysis. The work functions of gate metals were modulated through the reaction, suggesting that the consumption of AlN resulted in new thin metal alloys. Finally, it was found that the barrier heights of the new alloys were consistent with their work functions

Electrical Properties of Ultrathin Hf-Ti-O Higher k Gate Dielectric Films and Their Application in ETSOI MOSFET.

Science.gov (United States)

Xiong, Yuhua; Chen, Xiaoqiang; Wei, Feng; Du, Jun; Zhao, Hongbin; Tang, Zhaoyun; Tang, Bo; Wang, Wenwu; Yan, Jiang

2016-12-01

Ultrathin Hf-Ti-O higher k gate dielectric films (~2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) ~9.4%, low equivalent gate oxide thickness (EOT) of ~0.69 nm and acceptable gate leakage current density of 0.61 A/cm 2 @ (V fb  - 1)V could be obtained. The conduction mechanism through the gate dielectric is dominated by the F-N tunneling in the gate voltage range of -0.5 to -2 V. Under the same physical thickness and process flow, lower EOT and higher I on /I off ratio could be obtained while using Hf-Ti-O as gate dielectric compared with HfO 2 . With Hf-Ti-O as gate dielectric, two ETSOI PMOSFETs with gate width/gate length (W/L) of 0.5 μm/25 nm and 3 μm/40 nm show good performances such as high I on , I on /I off ratio in the magnitude of 10 5 , and peak transconductance, as well as suitable threshold voltage (-0.3~-0.2 V). Particularly, ETSOI PMOSFETs show superior short-channel control capacity with DIBL <82 mV/V and subthreshold swing <70 mV/decade.

Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor

Science.gov (United States)

Madan, Jaya; Gupta, R. S.; Chaujar, Rishu

2015-09-01

In this work, an analytical drain current model for gate dielectric engineered (hetero dielectric)-dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed. Parabolic approximation has been used to solve the two-dimensional (2D) Poisson equation with appropriate boundary conditions and continuity equations to evaluate analytical expressions for surface potential, electric field, tunneling barrier width and drain current. Further, the analog performance of the device is studied for three high-k dielectrics (Si3N4, HfO2, and ZrO2), and it has been investigated that the problem of lower ION, can be overcome by using the hetero-gate architecture. Moreover, the impact of scaling the gate oxide thickness and bias variations has also been studied. The HD-DMG-GAA-TFET shows an enhanced ION of the order of 10-4 A. The effectiveness of the proposed model is validated by comparing it with ATLAS device simulations.

Fabrication of Nonvolatile Memory Effects in High-k Dielectric Thin Films Using Electron Irradiation

International Nuclear Information System (INIS)

Park, Chanrock; Cho, Daehee; Kim, Jeongeun; Hwang, Jinha

2010-01-01

Electron Irradiation can be applied towards nano-floating gate memories which are recognized as one of the next-generation nonvolatile memory semiconductors. NFGMs can overcome the preexisting limitations encountered in Dynamic Random Access Memories and Flash memories with the excellent advantages, i. e. high-density information storage, high response speed, high compactness, etc. The traditional nano-floating gate memories are fabricated through multi-layered nano structures of the dissimilar materials where the charge-trapping portions are sandwiched into the high-k dielectrics. However, this work reports the unique nonvolatile responses in single-layered high-k dielectric thin films if irradiated with highly accelerated electron beams. The implications of the electron irradiation will be discussed towards high-performance nano-floating gate memories

On the Evaluation of Gate Dielectrics for 4H-SiC Based Power MOSFETs

Directory of Open Access Journals (Sweden)

Muhammad Nawaz

2015-01-01

Full Text Available This work deals with the assessment of gate dielectric for 4H-SiC MOSFETs using technology based two-dimensional numerical computer simulations. Results are studied for variety of gate dielectric candidates with varying thicknesses using well-known Fowler-Nordheim tunneling model. Compared to conventional SiO2 as a gate dielectric for 4H-SiC MOSFETs, high-k gate dielectric such as HfO2 reduces significantly the amount of electric field in the gate dielectric with equal gate dielectric thickness and hence the overall gate current density. High-k gate dielectric further reduces the shift in the threshold voltage with varying dielectric thicknesses, thus leading to better process margin and stable device operating behavior. For fixed dielectric thickness, a total shift in the threshold voltage of about 2.5 V has been observed with increasing dielectric constant from SiO2 (k=3.9 to HfO2 (k=25. This further results in higher transconductance of the device with the increase of the dielectric constant from SiO2 to HfO2. Furthermore, 4H-SiC MOSFETs are found to be more sensitive to the shift in the threshold voltage with conventional SiO2 as gate dielectric than high-k dielectric with the presence of interface state charge density that is typically observed at the interface of dielectric and 4H-SiC MOS surface.

Simulation of dual-gate SOI MOSFET with different dielectric layers

Science.gov (United States)

Yadav, Jyoti; Chaudhary, R.; Mukhiya, R.; Sharma, R.; Khanna, V. K.

2016-04-01

The paper presents the process design and simulation of silicon-on-insulator (SOI)-based dual-gate metal oxide field-effect transistor (DG-MOSFET) stacked with different dielectric layers on the top of gate oxide. A detailed 2D process simulation of SOI-MOSFETs and its electrical characterization has been done using SILVACO® TCAD tool. A variation in transconductance was observed with different dielectric layers, AlN-gate MOSFET having the highest tranconductance value as compared to other three dielectric layers (SiO2, Si3N4 and Al2O3).

Influence of gate dielectric on the ambipolar characteristics of solution-processed organic field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Ribierre, J C; Ghosh, S; Takaishi, K; Muto, T; Aoyama, T, E-mail: jcribierre@ewha.ac.kr, E-mail: taoyama@riken.jp [Advanced Science Institute, RIKEN, 2-1 Hirosawa, Wako, Saitama 351-0198 (Japan)

2011-05-25

Solution-processed ambipolar organic field-effect transistors based on dicyanomethylene-substituted quinoidal quaterthiophene derivative [QQT(CN)4] are fabricated using various gate dielectric materials including cross-linked polyimide and poly-4-vinylphenol. Devices with spin-coated polymeric gate dielectric layers show a reduced hysteresis in their transfer characteristics. Among the insulating polymers examined in this study, a new fluorinated polymer with a low dielectric constant of 2.8 significantly improves both hole and electron field-effect mobilities of QQT(CN)4 thin films to values as high as 0.04 and 0.002 cm{sup 2} V{sup -1} s{sup -1}. These values are close to the best mobilities obtained in QQT(CN)4 devices fabricated on SiO{sub 2} treated with octadecyltrichlorosilane. The influence of the metal used for source/drain metal electrodes on the device performance is also investigated. Whereas best device performances are achieved with gold electrodes, more balanced electron and hole field-effect mobilities could be obtained using chromium.

Hysteresis behaviour of low-voltage organic field-effect transistors employing high dielectric constant polymer gate dielectrics

International Nuclear Information System (INIS)

Kim, Se Hyun; Yun, Won Min; Kwon, Oh-Kwan; Hong, Kipyo; Yang, Chanwoo; Park, Chan Eon; Choi, Woon-Seop

2010-01-01

Here, we report on the fabrication of low-voltage-operating pentacene-based organic field-effect transistors (OFETs) that utilize crosslinked cyanoethylated poly(vinyl alcohol) (CR-V) gate dielectrics. The crosslinked CR-V-based OFET could be operated successfully at low voltages (below 4 V), but abnormal behaviour during device operation, such as uncertainty in the field-effect mobility (μ) and hysteresis, was induced by the slow polarization of moieties embedded in the gate dielectric (e.g. polar functionalities, ionic impurities, water and solvent molecules). In an effort to improve the stability of OFET operation, we measured the dependence of μ and hysteresis on dielectric thickness, CR-V crosslinking conditions and sweep rate of the gate bias. The influence of the CR-V surface properties on μ, hysteresis, and the structural and morphological features of the pentacene layer grown on the gate dielectric was characterized and compared with the properties of pentacene grown on a polystyrene surface.

Energy-loss return gate via liquid dielectric polarization.

Science.gov (United States)

Kim, Taehun; Yong, Hyungseok; Kim, Banseok; Kim, Dongseob; Choi, Dukhyun; Park, Yong Tae; Lee, Sangmin

2018-04-12

There has been much research on renewable energy-harvesting techniques. However, owing to increasing energy demands, significant energy-related issues remain to be solved. Efforts aimed at reducing the amount of energy loss in electric/electronic systems are essential for reducing energy consumption and protecting the environment. Here, we design an energy-loss return gate system that reduces energy loss from electric/electronic systems by utilizing the polarization of liquid dielectrics. The use of a liquid dielectric material in the energy-loss return gate generates electrostatic potential energy while reducing the dielectric loss of the electric/electronic system. Hence, an energy-loss return gate can make breakthrough impacts possible by amplifying energy-harvesting efficiency, lowering the power consumption of electronics, and storing the returned energy. Our study indicates the potential for enhancing energy-harvesting technologies for electric/electronics systems, while increasing the widespread development of these systems.

High mobility and low operating voltage ZnGaO and ZnGaLiO transistors with spin-coated Al2O3 as gate dielectric

International Nuclear Information System (INIS)

Xia, D X; Xu, J B

2010-01-01

Spin-coated alumina serving as a gate dielectric in thin film transistors shows interesting dielectric properties for low-voltage applications, despite a moderate capacitance. With Ga singly doped and Ga, Li co-doped ZnO as the active channel layers, typical mobilities of 4.7 cm 2 V -1 s -1 and 2.1 cm 2 V -1 s -1 are achieved, respectively. At a given gate bias, the operation current is much smaller than the previously reported values in low-voltage thin film transistors, primarily relying on the giant-capacitive dielectric. The reported devices combine advantages of high mobility, low power consumption, low cost and ease of fabrication. In addition to the transparent nature of both the dielectric and semiconducting active channels, the superior electrical properties of the devices may provide a new avenue for future transparent electronics. (fast track communication)

Medium band gap polymer based solution-processed high-κ composite gate dielectrics for ambipolar OFET

Science.gov (United States)

Canımkurbey, Betül; Unay, Hande; Çakırlar, Çiğdem; Büyükköse, Serkan; Çırpan, Ali; Berber, Savas; Altürk Parlak, Elif

2018-03-01

The authors present a novel ambipolar organic filed-effect transistors (OFETs) composed of a hybrid dielectric thin film of Ta2O5:PMMA nanocomposite material, and solution processed poly(selenophene, benzotriazole and dialkoxy substituted [1,2-b:4, 5-b‧] dithiophene (P-SBTBDT)-based organic semiconducting material as the active layer of the device. We find that the Ta2O5:PMMA insulator shows n-type conduction character, and its combination with the p-type P-SBTBDT organic semiconductor leads to an ambipolar OFET device. Top-gated OFETs were fabricated on glass substrate consisting of interdigitated ITO electrodes. P-SBTBDT-based material was spin coated on the interdigitated ITO electrodes. Subsequently, a solution processed Ta2O5:PMMA nanocomposite material was spin coated, thereby creating the gate dielectric layer. Finally, as a gate metal, an aluminum layer was deposited by thermal evaporation. The fabricated OFETs exhibited an ambipolar performance with good air-stability, high field-induced current and relatively high electron and hole mobilities although Ta2O5:PMMA nanocomposite films have slightly higher leakage current compared to the pure Ta2O5 films. Dielectric properties of the devices with different ratios of Ta2O5:PMMA were also investigated. The dielectric constant varied between 3.6 and 5.3 at 100 Hz, depending on the Ta2O5:PMMA ratio.

Effect of gate dielectrics on the performance of p-type Cu2O TFTs processed at room temperature

KAUST Repository

Al-Jawhari, Hala A.

2013-12-01

Single-phase Cu2O films with p-type semiconducting properties were successfully deposited by reactive DC magnetron sputtering at room temperature followed by post annealing process at 200°C. Subsequently, such films were used to fabricate bottom gate p-channel Cu2O thin film transistors (TFTs). The effect of using high-κ SrTiO3 (STO) as a gate dielectric on the Cu2O TFT performance was investigated. The results were then compared to our baseline process which uses a 220 nm aluminum titanium oxide (ATO) dielectric deposited on a glass substrate coated with a 200 nm indium tin oxide (ITO) gate electrode. We found that with a 150 nm thick STO, the Cu2O TFTs exhibited a p-type behavior with a field-effect mobility of 0.54 cm2.V-1.s-1, an on/off ratio of around 44, threshold voltage equaling -0.62 V and a sub threshold swing of 1.64 V/dec. These values were obtained at a low operating voltage of -2V. The advantages of using STO as a gate dielectric relative to ATO are discussed. © (2014) Trans Tech Publications, Switzerland.

High-κ gate dielectrics: Current status and materials properties considerations

Science.gov (United States)

Wilk, G. D.; Wallace, R. M.; Anthony, J. M.

2001-05-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward successful integration into the expected processing conditions for future CMOS technologies, especially due to their tendency to form at interfaces with Si (e.g. silicates). These pseudobinary systems also thereby enable the use of other high-κ materials by serving as an interfacial high-κ layer. While work is ongoing, much research is still required, as it is clear that any material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene-graphene composite layers for flexible thin film transistors with a polymer gate dielectric.

Science.gov (United States)

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-02-28

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene-graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene-graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm(2) V(-1) s(-1) and a threshold voltage of -0.7 V at V(gs) = -40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm(2) V(-1) s(-1) and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies.

Structural and electrical characteristics of high-κ ErTixOy gate dielectrics on InGaZnO thin-film transistors

International Nuclear Information System (INIS)

Chen, Fa-Hsyang; Her, Jim-Long; Shao, Yu-Hsuan; Li, Wei-Chen; Matsuda, Yasuhiro H.; Pan, Tung-Ming

2013-01-01

In this paper, we investigated the structural properties and electrical characteristics of high-κ ErTi x O y gate dielectrics on indium-gallium-zinc oxide thin-film transistors (IGZO TFTs). We used X-ray diffraction, X-ray photoelectron spectroscopy, and atomic force microscopy to investigate the structural and morphological features of these dielectric films after they had been subjected to annealing at various temperatures. The high-κ ErTi x O y IGZO TFT device annealed at 400 °C exhibited better electrical characteristics in terms of a large field-effect mobility (8.24 cm 2 /V-s), low threshold voltage (0.36 V), small subthreshold swing (130 mV/dec), and high I on/off ratio(3.73 × 10 6 ). These results are attributed to the reduction of the trap states and oxygen vacancies between the ErTi x O y film and IGZO active layer interface during high-temperature annealing in oxygen ambient. The reliability of voltage stress also can be improved by the oxygen annealing at 400 °C. - Highlights: • ErTi x O y InGaZnO thin-film transistors (TFT). • Structural and electrical properties of the TFT were investigated. • TFT device annealed at 400 °C exhibited better electrical characteristics. • Reliability of TFT device can be improved by annealing at 400 °C

Anomalous degradation behaviors under illuminated gate bias stress in a-Si:H thin film transistor

International Nuclear Information System (INIS)

Tsai, Ming-Yen; Chang, Ting-Chang; Chu, Ann-Kuo; Hsieh, Tien-Yu; Lin, Kun-Yao; Wu, Yi-Chun; Huang, Shih-Feng; Chiang, Cheng-Lung; Chen, Po-Lin; Lai, Tzu-Chieh; Lo, Chang-Cheng; Lien, Alan

2014-01-01

This study investigates the impact of gate bias stress with and without light illumination in a-Si:H thin film transistors. It has been observed that the I–V curve shifts toward the positive direction after negative and positive gate bias stress due to interface state creation at the gate dielectric. However, this study found that threshold voltages shift negatively and that the transconductance curve maxima are anomalously degraded under illuminated positive gate bias stress. In addition, threshold voltages shift positively under illuminated negative gate bias stress. These degradation behaviors can be ascribed to charge trapping in the passivation layer dominating degradation instability and are verified by a double gate a-Si:H device. - Highlights: • There is abnormal V T shift induced by illuminated gate bias stress in a-Si:H thin film transistors. • Electron–hole pair is generated via trap-assisted photoexcitation. • Abnormal transconductance hump is induced by the leakage current from back channel. • Charge trapping in the passivation layer is likely due to the fact that a constant voltage has been applied to the top gate

Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

KAUST Repository

Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Young, Chadwin D.; Bersuker, Gennadi; Hussain, Muhammad Mustafa

2015-01-01

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard

The TDDB Characteristics of Ultra-Thin Gate Oxide MOS Capacitors under Constant Voltage Stress and Substrate Hot-Carrier Injection

Directory of Open Access Journals (Sweden)

Jingyu Shen

2018-01-01

Full Text Available The breakdown characteristics of ultra-thin gate oxide MOS capacitors fabricated in 65 nm CMOS technology under constant voltage stress and substrate hot-carrier injection are investigated. Compared to normal thick gate oxide, the degradation mechanism of time-dependent dielectric breakdown (TDDB of ultra-thin gate oxide is found to be different. It is found that the gate current (Ig of ultra-thin gate oxide MOS capacitor is more likely to be induced not only by Fowler-Nordheim (F-N tunneling electrons, but also by electrons surmounting barrier and penetrating electrons in the condition of constant voltage stress. Moreover it is shown that the time to breakdown (tbd under substrate hot-carrier injection is far less than that under constant voltage stress when the failure criterion is defined as a hard breakdown according to the experimental results. The TDDB mechanism of ultra-thin gate oxide will be detailed. The differences in TDDB characteristics of MOS capacitors induced by constant voltage stress and substrate hot-carrier injection will be also discussed.

Ambipolar transport in CVD grown MoSe2 monolayer using an ionic liquid gel gate dielectric

Directory of Open Access Journals (Sweden)

Deliris N. Ortiz

2018-03-01

Full Text Available CVD grown MoSe2 monolayers were electrically characterized at room temperature in a field effect transistor (FET configuration using an ionic liquid (IL as the gate dielectric. During the growth, instead of using MoO3 powder, ammonium heptamolybdate was used for better Mo control of the source and sodium cholate added for lager MoSe2 growth areas. In addition, a high specific capacitance (∼7 μF/cm2 IL was used as the gate dielectric to significantly reduce the operating voltage. The device exhibited ambipolar charge transport at low voltages with enhanced parameters during n- and p-FET operation. IL gating thins the Schottky barrier at the metal/semiconductor interface permitting efficient charge injection into the channel and reduces the effects of contact resistance on device performance. The large specific capacitance of the IL was also responsible for a much higher induced charge density compared to the standard SiO2 dielectric. The device was successfully tested as an inverter with a gain of ∼2. Using a common metal for contacts simplifies fabrication of this ambipolar device, and the possibility of radiative recombination of holes and electrons could further extend its use in low power optoelectronic applications.

Ultra-low power thin film transistors with gate oxide formed by nitric acid oxidation method

International Nuclear Information System (INIS)

Kobayashi, H.; Kim, W. B.; Matsumoto, T.

2011-01-01

We have developed a low temperature fabrication method of SiO 2 /Si structure by use of nitric acid, i.e., nitric acid oxidation of Si (NAOS) method, and applied it to thin film transistors (TFT). A silicon dioxide (SiO 2 ) layer formed by the NAOS method at room temperature possesses 1.8 nm thickness, and its leakage current density is as low as that of thermally grown SiO 2 layer with the same thickness formed at ∼900 deg C. The fabricated TFTs possess an ultra-thin NAOS SiO 2 /CVD SiO 2 stack gate dielectric structure. The ultrathin NAOS SiO 2 layer effectively blocks a gate leakage current, and thus, the thickness of the gate oxide layer can be decreased from 80 to 20 nm. The thin gate oxide layer enables to decrease the operation voltage to 2 V (cf. the conventional operation voltage of TFTs with 80 nm gate oxide: 12 V) because of the low threshold voltages, i.e., -0.5 V for P-ch TFTs and 0.5 V for N-ch TFTs, and thus the consumed power decreases to 1/36 of that of the conventional TFTs. The drain current increases rapidly with the gate voltage, and the sub-threshold voltage is ∼80 mV/dec. The low sub-threshold swing is attributable to the thin gate oxide thickness and low interface state density of the NAOS SiO 2 layer. (authors)

Junctionless Thin-Film Transistors Gated by an H₃PO₄-Incorporated Chitosan Proton Conductor.

Science.gov (United States)

Liu, Huixuan; Xun, Damao

2018-04-01

We fabricated an H3PO4-incorporated chitosan proton conductor film that exhibited the electric double layer effect and showed a high specific capacitance of 4.42 μF/cm2. Transparent indium tin oxide thin-film transistors gated by H3PO4-incorporated chitosan films were fabricated by sputtering through a shadow mask. The operating voltage was as low as 1.2 V because of the high specific capacitance of the H3PO4-incorporated chitosan dielectrics. The junctionless transparent indium tin oxide thin film transistors exhibited good performance, including an estimated current on/off ratio and field-effect mobility of 1.2 × 106 and 6.63 cm2V-1s-1, respectively. These low-voltage thin-film electric-double-layer transistors gated by H3PO4-incorporated chitosan are promising for next generation battery-powered "see-through" portable sensors.

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene–graphene composite layers for flexible thin film transistors with a polymer gate dielectric

International Nuclear Information System (INIS)

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-01-01

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene–graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene–graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm 2  V −1  s −1 and a threshold voltage of −0.7 V at V gs = −40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm 2  V −1  s −1 and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies. (paper)

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

Science.gov (United States)

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J

2016-06-09

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

International Nuclear Information System (INIS)

Ghosh, Bahniman; Mondal, Partha; Akram, M. W.; Bal, Punyasloka; Salimath, Akshay Kumar

2014-01-01

We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel. These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n–p–n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability. (semiconductor devices)

Materials Fundamentals of Gate Dielectrics

CERN Document Server

Demkov, Alexander A

2006-01-01

This book presents materials fundamentals of novel gate dielectrics that are being introduced into semiconductor manufacturing to ensure the continuous scalling of the CMOS devices. This is a very fast evolving field of research so we choose to focus on the basic understanding of the structure, thermodunamics, and electronic properties of these materials that determine their performance in device applications. Most of these materials are transition metal oxides. Ironically, the d-orbitals responsible for the high dielectric constant cause sever integration difficulties thus intrinsically limiting high-k dielectrics. Though new in the electronics industry many of these materials are wel known in the field of ceramics, and we describe this unique connection. The complexity of the structure-property relations in TM oxides makes the use of the state of the art first-principles calculations necessary. Several chapters give a detailed description of the modern theory of polarization, and heterojunction band discont...

Fabrication of amorphous InGaZnO thin-film transistor with solution processed SrZrO3 gate insulator

Science.gov (United States)

Takahashi, Takanori; Oikawa, Kento; Hoga, Takeshi; Uraoka, Yukiharu; Uchiyama, Kiyoshi

2017-10-01

In this paper, we describe a method of fabrication of thin film transistors (TFTs) with high dielectric constant (high-k) gate insulator by a solution deposition. We chose a solution processed SrZrO3 as a gate insulator material, which possesses a high dielectric constant of 21 with smooth surface. The IGZO-TFT with solution processed SrZrO3 showed good switching property and enough saturation features, i.e. field effect mobility of 1.7cm2/Vs, threshold voltage of 4.8V, sub-threshold swing of 147mV/decade, and on/off ratio of 2.3×107. Comparing to the TFTs with conventional SiO2 gate insulator, the sub-threshold swing was improved by smooth surface and high field effect due to the high dielectric constant of SrZrO3. These results clearly showed that use of solution processed high-k SrZrO3 gate insulator could improve sub-threshold swing. In addition, the residual carbon originated from organic precursors makes TFT performances degraded.

Temperature-dependent field-effect carrier mobility in organic thin-film transistors with a gate SiO2 dielectric modified by H2O2 treatment

Science.gov (United States)

Lin, Yow-Jon; Hung, Cheng-Chun

2018-02-01

The effect of the modification of a gate SiO2 dielectric using an H2O2 solution on the temperature-dependent behavior of carrier transport for pentacene-based organic thin-film transistors (OTFTs) is studied. H2O2 treatment leads to the formation of Si(-OH) x (i.e., the formation of a hydroxylated layer) on the SiO2 surface that serves to reduce the SiO2 capacitance and weaken the pentacene-SiO2 interaction, thus increasing the field-effect carrier mobility ( µ) in OTFTs. The temperature-dependent behavior of carrier transport is dominated by the multiple trapping model. Note that H2O2 treatment leads to a reduction in the activation energy. The increased value of µ is also attributed to the weakening of the interactions of the charge carriers with the SiO2 dielectric that serves to reduce the activation energy.

Analyzing the effect of gate dielectric on the leakage currents

Directory of Open Access Journals (Sweden)

Sakshi

2016-01-01

Full Text Available An analytical threshold voltage model for MOSFETs has been developed using different gate dielectric oxides by using MATLAB software. This paper explains the dependency of threshold voltage on the dielectric material. The variation in the subthreshold currents with the change in the threshold voltage sue to the change of dielectric material has also been studied.

Constant-current corona triode adapted and optimized for the characterization of thin dielectric films

Science.gov (United States)

Giacometti, José A.

2018-05-01

This work describes an enhanced corona triode with constant current adapted to characterize the electrical properties of thin dielectric films used in organic electronic devices. A metallic grid with a high ionic transparency is employed to charge thin films (100 s of nm thick) with a large enough charging current. The determination of the surface potential is based on the grid voltage measurement, but using a more sophisticated procedure than the previous corona triode. Controlling the charging current to zero, which is the open-circuit condition, the potential decay can be measured without using a vibrating grid. In addition, the electric capacitance and the characteristic curves of current versus the stationary surface potential can also be determined. To demonstrate the use of the constant current corona triode, we have characterized poly(methyl methacrylate) thin films with films with thicknesses in the range from 300 to 500 nm, frequently used as gate dielectric in organic field-effect transistors.

Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

Science.gov (United States)

Jayanti, Srikant

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG

Accurate characterization of organic thin film transistors in the presence of gate leakage current

Directory of Open Access Journals (Sweden)

Vinay K. Singh

2011-12-01

Full Text Available The presence of gate leakage through polymer dielectric in organic thin film transistors (OTFT prevents accurate estimation of transistor characteristics especially in subthreshold regime. To mitigate the impact of gate leakage on transfer characteristics and allow accurate estimation of mobility, subthreshold slope and on/off current ratio, a measurement technique involving simultaneous sweep of both gate and drain voltages is proposed. Two dimensional numerical device simulation is used to illustrate the validity of the proposed technique. Experimental results obtained with Pentacene/PMMA OTFT with significant gate leakage show a low on/off current ratio of ∼ 102 and subthreshold is 10 V/decade obtained using conventional measurement technique. The proposed technique reveals that channel on/off current ratio is more than two orders of magnitude higher at ∼104 and subthreshold slope is 4.5 V/decade.

The Performance Improvement of N2 Plasma Treatment on ZrO2 Gate Dielectric Thin-Film Transistors with Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition IGZO Channel.

Science.gov (United States)

Wu, Chien-Hung; Huang, Bo-Wen; Chang, Kow-Ming; Wang, Shui-Jinn; Lin, Jian-Hong; Hsu, Jui-Mei

2016-06-01

The aim of this paper is to illustrate the N2 plasma treatment for high-κ ZrO2 gate dielectric stack (30 nm) with indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs). Experimental results reveal that a suitable incorporation of nitrogen atoms could enhance the device performance by eliminating the oxygen vacancies and provide an amorphous surface with better surface roughness. With N2 plasma treated ZrO2 gate, IGZO channel is fabricated by atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) technique. The best performance of the AP-PECVD IGZO TFTs are obtained with 20 W-90 sec N2 plasma treatment with field-effect mobility (μ(FET)) of 22.5 cm2/V-s, subthreshold swing (SS) of 155 mV/dec, and on/off current ratio (I(on)/I(off)) of 1.49 x 10(7).

Application of calendering for improving the electrical characteristics of a printed top-gate, bottom-contact organic thin film transistors

Science.gov (United States)

Lee, Sang Hoon; Lee, Dong Geun; Jung, Hoeryong; Lee, Sangyoon

2018-05-01

Interface between the channel and the gate dielectric of organic thin film transistors (OTFTs) needs to be smoothed in order to improve the electrical characteristics. In this study, an optimized calendering process was proposed to improve the surface roughness of the channel. Top-gate, bottom-contact structural p-type OTFT samples were fabricated using roll-to-roll gravure printing (source/drain, channel), spin coating (gate dielectric), and inkjet printing (gate electrode). The calendering process was optimized using the grey-based Taguchi method. The channel surface roughness and electrical characteristics of calendered and non-calendered samples were measured and compared. As a result, the average improvement in the surface roughness of the calendered samples was 26.61%. The average on–off ratio and field-effect mobility of the calendered samples were 3.574 × 104 and 0.1113 cm2 V‑1 s‑1, respectively, which correspond to the improvements of 16.72 and 10.20%, respectively.

Band Alignment and Optical Properties of (ZrO20.66(HfO20.34 Gate Dielectrics Thin Films on p-Si (100

Directory of Open Access Journals (Sweden)

Dahlang Tahir

2011-11-01

Full Text Available (ZrO20.66(HfO20.34 dielectric films on p-Si (100 were grown by atomic layer deposition method, for which the conduction band offsets, valence band offsets and band gaps were obtained by using X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy. The band gap, valence and conduction band offset values for (ZrO20.66(HfO20.34 dielectric thin film, grown on Si substrate were about 5.34, 2.35 and 1.87 eV respectively. This band alignment was similar to that of ZrO2. In addition, The dielectric function ε (k, ω, index of refraction n and the extinction coefficient k for the (ZrO20.66(HfO20.34 thin films were obtained from a quantitative analysis of REELS data by comparison to detailed dielectric response model calculations using the QUEELS-ε (k,ω-REELS software package. These optical properties are similar with ZrO2 dielectric thin films.

Effects of Annealing Time on the Performance of OTFT on Glass with ZrO2 as Gate Dielectric

Directory of Open Access Journals (Sweden)

W. M. Tang

2012-01-01

Full Text Available Copper phthalocyanine-based organic thin-film transistors (OTFTs with zirconium oxide (ZrO2 as gate dielectric have been fabricated on glass substrates. The gate dielectric is annealed in N2 at different durations (5, 15, 40, and 60 min to investigate the effects of annealing time on the electrical properties of the OTFTs. Experimental results show that the longer the annealing time for the OTFT, the better the performance. Among the devices studied, OTFTs with gate dielectric annealed at 350°C in N2 for 60 min exhibit the best device performance. They have a small threshold voltage of −0.58 V, a low subthreshold slope of 0.8 V/decade, and a low off-state current of 0.73 nA. These characteristics demonstrate that the fabricated device is suitable for low-voltage and low-power operations. When compared with the TFT samples annealed for 5 min, the ones annealed for 60 min have 20% higher mobility and nearly two times smaller the subthreshold slope and off-state current. The extended annealing can effectively reduce the defects in the high-k film and produces a better insulator/organic interface. This results in lower amount of carrier scattering and larger CuPc grains for carrier transport.

A novel approach for the improvement of electrostatic behaviour of physically doped TFET using plasma formation and shortening of gate electrode with hetero-gate dielectric

Science.gov (United States)

Soni, Deepak; Sharma, Dheeraj; Aslam, Mohd.; Yadav, Shivendra

2018-04-01

This article presents a new device configuration to enhance current drivability and suppress negative conduction (ambipolar conduction) with improved RF characteristics of physically doped TFET. Here, we used a new approach to get excellent electrical characteristics of hetero-dielectric short gate source electrode TFET (HD-SG SE-TFET) by depositing a metal electrode of 5.93 eV work function over the heavily doped source (P+) region. Deposition of metal electrode induces the plasma (thin layer) of holes under the Si/HfO2 interface due to work function difference of metal and semiconductor. Plasma layer of holes is advantageous to increase abruptness as well as decrease the tunneling barrier at source/channel junction for attaining higher tunneling rate of charge carriers (i.e., electrons), which turns into 86.66 times higher ON-state current compared with the conventional physically doped TFET (C-TFET). Along with metal electrode deposition, gate electrode is under-lapped for inducing asymmetrical concentration of charge carriers in the channel region, which is helpful for widening the tunneling barrier width at the drain/channel interface. Consequently, HD-SG SE-TFET shows suppression of ambipolar behavior with reduction in gate-to-drain capacitance which is beneficial for improvement in RF performance. Furthermore, the effectiveness of hetero-gate dielectric concept has been used for improving the RF performance. Furthermore, reliability of C-TFET and proposed structures has been confirmed in term of linearity.

A complementary organic inverter of porphyrazine thin films: low-voltage operation using ionic liquid gate dielectrics.

Science.gov (United States)

Fujimoto, Takuya; Miyoshi, Yasuhito; Matsushita, Michio M; Awaga, Kunio

2011-05-28

We studied a complementary organic inverter consisting of a p-type semiconductor, metal-free phthalocyanine (H(2)Pc), and an n-type semiconductor, tetrakis(thiadiazole)porphyrazine (H(2)TTDPz), operated through the ionic-liquid gate dielectrics of N,N-diethyl-N-methyl(2-methoxyethyl)ammonium bis(trifluoromethylsulfonyl)imide (DEME-TFSI). This organic inverter exhibits high performance with a very low operation voltage below 1.0 V and a dynamic response up to 20 Hz. © The Royal Society of Chemistry 2011

Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

KAUST Repository

Ghoneim, Mohamed T.

2015-06-01

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard bulk mono-crystalline silicon substrate. A lifetime projection is extracted using statistical analysis of the ramping voltage (Vramp) breakdown and time dependent dielectric breakdown data. The obtained flexible MOSCAPs operational voltages satisfying the 10 years lifetime benchmark are compared to those of the control MOSCAPs, which are not peeled off from the silicon wafer. © 2014 IEEE.

Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics

KAUST Repository

Alshareef, Husam N.

2010-11-19

Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.

Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics

KAUST Repository

Alshareef, Husam N.; Caraveo-Frescas, J. A.; Cha, D. K.

2010-01-01

Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.

GaN MOSHEMT employing HfO2 as a gate dielectric with partially etched barrier

Science.gov (United States)

Han, Kefeng; Zhu, Lin

2017-09-01

In order to suppress the gate leakage current of a GaN high electron mobility transistor (GaN HEMT), a GaN metal-oxide-semiconductor high electron mobility transistor (MOSHEMT) is proposed, in which a metal-oxide-semiconductor gate with high-dielectric-constant HfO2 as an insulating dielectric is employed to replace the traditional GaN HEMT Schottky gate. A 0.5 μm gate length GaN MOSHEMT was fabricated based on the proposed structure, the {{{Al}}}0.28{{{Ga}}}0.72{{N}} barrier layer is partially etched to produce a higher transconductance without deteriorating the transport characteristics of the two-dimensional electron gas in the channel, the gate dielectric is HfO2 deposited by atomic layer deposition. Current-voltage characteristics and radio frequency characteristics are obtained after device preparation, the maximum current density of the device is 900 mA mm-1, the source-drain breakdown voltage is 75 V, gate current is significantly suppressed and the forward gate voltage swing range is about ten times higher than traditional GaN HEMTs, the GaN MOSHEMT also demonstrates radio frequency characteristics comparable to traditional GaN HEMTs with the same gate length.

A comparative study of amorphous InGaZnO thin-film transistors with HfOxNy and HfO2 gate dielectrics

International Nuclear Information System (INIS)

Zou, Xiao; Tong, Xingsheng; Fang, Guojia; Yuan, Longyan; Zhao, Xingzhong

2010-01-01

High-κ HfO x N y and HfO 2 films are applied to amorphous InGaZnO (a-IGZO) devices as gate dielectric using radio-frequency reactive sputtering. The electrical characteristics and reliability of a-IGZO metal–insulator–semiconductor (MIS) capacitors and thin-film transistors (TFTs) are then investigated. Experimental results indicate that the nitrogen incorporation into HfO 2 can effectively improve the interface quality and enhance the reliability of the devices. Electrical properties with an interface-state density of 5.2 × 10 11 eV −1 cm −2 , capacitance equivalent thickness of 1.65 nm, gate leakage current density of 3.4 × 10 −5 A cm −2 at V fb +1 V, equivalent permittivity of 23.6 and hysteresis voltage of 110 mV are obtained for an Al/HfO x N y /a-IGZO MIS capacitor. Superior performance of HfO x N y /a-IGZO TFTs has also been achieved with a low threshold voltage of 0.33 V, a high saturation mobility of 12.1 cm 2 V −1 s −1 and a large on–off current ratio up to 7 × 10 7 (W/L = 500/20 µm) at 3 V

High performance solution processed zirconium oxide gate dielectric appropriate for low temperature device application

Energy Technology Data Exchange (ETDEWEB)

Hasan, Musarrat; Nguyen, Manh-Cuong; Kim, Hyojin; You, Seung-Won; Jeon, Yoon-Seok; Tong, Duc-Tai; Lee, Dong-Hwi; Jeong, Jae Kyeong; Choi, Rino, E-mail: rino.choi@inha.ac.kr

2015-08-31

This paper reports a solution processed electrical device with zirconium oxide gate dielectric that was fabricated at a low enough temperature appropriate for flexible electronics. Both inorganic dielectric and channel materials were synthesized in the same organic solvent. The dielectric constant achieved was 13 at 250 °C with a reasonably low leakage current. The bottom gate transistor devices showed the highest mobility of 75 cm{sup 2}/V s. The device is operated at low voltage with high-k dielectric with excellent transconductance and low threshold voltage. Overall, the results highlight the potential of low temperature solution based deposition in fabricating more complicated circuits for a range of applications. - Highlights: • We develop a low temperature inorganic dielectric deposition process. • We fabricate oxide semiconductor channel devices using all-solution processes. • Same solvent is used for dielectric and oxide semiconductor deposition.

Enhanced dielectric properties of ZrO2 thin films prepared in nitrogen ambient by pulsed laser deposition

International Nuclear Information System (INIS)

Zhu, J; Li, T L; Pan, B; Zhou, L; Liu, Z G

2003-01-01

ZrO 2 thin films were fabricated in O 2 ambient and in N 2 ambient by pulsed laser deposition (PLD), respectively. X-ray diffraction revealed that films prepared at 400 deg. C remained amorphous. The dielectric properties of amorphous ZrO 2 films were investigated by measuring the capacitance-frequency characteristics of Pt/ZrO 2 /Pt capacitor structures. The dielectric constant of the films deposited in N 2 ambient was larger than that of the films deposited in O 2 ambient. The dielectric loss was lower for films prepared in N 2 ambient. Atom force microscopy investigation indicated that films deposited in N 2 ambient had smoother surface than films deposited in O 2 ambient. Capacitance-voltage and current-voltage characteristics were studied. The equivalent oxide thickness (EOT) of films with 6.6 nm physical thickness deposited in N 2 ambient is lower than that of films deposited in O 2 ambient. An EOT of 1.38 nm for the film deposited in N 2 ambient was obtained, while the leakage current density was 94.6 mA cm -2 . Therefore, ZrO 2 thins deposited in N 2 ambient have enhanced dielectric properties due to the incorporation of nitrogen which leads to the formation of Zr-doped nitride interfacial layer, and is suggested to be a potential material for alternative high-k (high dielectric constant) gate dielectric applications

Improved integration of ultra-thin high-k dielectrics in few-layer MoS2 FET by remote forming gas plasma pretreatment

Science.gov (United States)

Wang, Xiao; Zhang, Tian-Bao; Yang, Wen; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

2017-01-01

The effective and high-quality integration of high-k dielectrics on two-dimensional (2D) crystals is essential to the device structure engineering and performance improvement of field-effect transistor (FET) based on the 2D semiconductors. We report a 2D MoS2 transistor with ultra-thin Al2O3 top-gate dielectric (6.1 nm) and extremely low leakage current. Remote forming gas plasma pretreatment was carried out prior to the atomic layer deposition, providing nucleation sites with the physically adsorbed ions on the MoS2 surface. The top gate MoS2 FET exhibited excellent electrical performance, including high on/off current ratio over 109, subthreshold swing of 85 mV/decade and field-effect mobility of 45.03 cm2/V s. Top gate leakage current less than 0.08 pA/μm2 at 4 MV/cm has been obtained, which is the smallest compared with the reported top-gated MoS2 transistors. Such an optimized integration of high-k dielectric in 2D semiconductor FET with enhanced performance is very attractive, and it paves the way towards the realization of more advanced 2D nanoelectronic devices and integrated circuits.

Nano-CMOS gate dielectric engineering

CERN Document Server

Wong, Hei

2011-01-01

According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance

Science.gov (United States)

Anand, Sunny; Sarin, R. K.

2017-02-01

In this paper, charge-plasma-based tunnel FET is proposed by employing dual material gate with hetero gate dielectric technique and it is named hetero-dielectric dual material gate doping-less TFET (HD_DMG_DLTFET). It is compared with conventional doping-less TFET (DLTFET) and dual material gate doping-less TFET (DMG_DLTFET) on the basis of analog and RF performance. The HD_DMG_DLTFET provides better ON state current ({I}\\text{ON}=94 μ \\text{A}/μ \\text{m}), {I}\\text{ON}/{I}\\text{OFF}(≈ 1.36× {10}13), \\text{point} (≈ 3\\text{mV}/\\text{dec}) and average subthreshold slope (\\text{AV}-\\text{SS}=40.40 \\text{mV}/\\text{dec}). The proposed device offers low total gate capacitance (C gg) along with higher drive current. However, with a better transconductance (g m) and cut-off frequency (f T), the HD_DMG_DLTFET can be a good candidate for RF circuitry. The early voltage (V EA) and output conductance (g d) are also moderate for the proposed device with comparison to other devices and therefore can be a candidate for analog devices. From all these simulation results and their study, it is observed that HD_DMG_DLTFET has improved analog/RF performance compared to DLTFET and DMG_DLTFET.

Chemical vapour deposition of thin-film dielectrics

International Nuclear Information System (INIS)

Vasilev, Vladislav Yu; Repinsky, Sergei M

2005-01-01

Data on the chemical vapour deposition of thin-film dielectrics based on silicon nitride, silicon oxynitride and silicon dioxide and on phosphorus- and boron-containing silicate glasses are generalised. The equipment and layer deposition procedures are described. Attention is focussed on the analysis and discussion of the deposition kinetics and on the kinetic models for film growth. The film growth processes are characterised and data on the key physicochemical properties of thin-film covalent dielectric materials are given.

Effect of nanocomposite gate-dielectric properties on pentacene microstructure and field-effect transistor characteristics.

Science.gov (United States)

Lee, Wen-Hsi; Wang, Chun-Chieh

2010-02-01

In this study, the effect of surface energy and roughness of the nanocomposite gate dielectric on pentacene morphology and electrical properties of pentacene OTFT are reported. Nanoparticles TiO2 were added in the polyimide matrix to form a nanocomposite which has a significantly different surface characteristic from polyimide, leading to a discrepancy in the structural properties of pentacene growth. A growth mode of pentacene deposited on the nanocomposite is proposed to explain successfully the effect of surface properties of nanocomposite gate dielectric such as surface energy and roughness on the pentacene morphology and electrical properties of OTFT. To obtain the lower surface energy and smoother surface of nanocomposite gate dielectric that is responsible for the desired crystalline, microstructure of pentacene and electrical properties of device, a bottom contact OTFT-pentacene deposited on the double-layer nanocomposite gate dielectric consisting of top smoothing layer of the neat polyimide and bottom layer of (PI+ nano-TiO2 particles) nanocomposite has been successfully demonstrated to exhibit very promising performance including high current on to off ratio of about 6 x 10(5), threshold voltage of -10 V and moderately high filed mobility of 0.15 cm2V(-1)s(-1).

Interface Engineering and Gate Dielectric Engineering for High Performance Ge MOSFETs

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Jiabao Sun

2015-01-01

Full Text Available In recent years, germanium has attracted intensive interests for its promising applications in the microelectronics industry. However, to achieve high performance Ge channel devices, several critical issues still have to be addressed. Amongst them, a high quality gate stack, that is, a low defect interface layer and a dielectric layer, is of crucial importance. In this work, we first review the existing methods of interface engineering and gate dielectric engineering and then in more detail we discuss and compare three promising approaches (i.e., plasma postoxidation, high pressure oxidation, and ozone postoxidation. It has been confirmed that these approaches all can significantly improve the overall performance of the metal-oxide-semiconductor field effect transistor (MOSFET device.

Ternary rare-earth based alternative gate-dielectrics for future integration in MOSFETs

Energy Technology Data Exchange (ETDEWEB)

Schubert, Juergen; Lopes, Joao Marcelo; Durgun Oezben, Eylem; Luptak, Roman; Lenk, Steffi; Zander, Willi; Roeckerath, Martin [IBN 1-IT, Forschungszentrum Juelich, 52425 Juelich (Germany)

2009-07-01

The dielectric SiO{sub 2} has been the key to the tremendous improvements in Si-based metal-oxide-semiconductor (MOS) device performance over the past four decades. It has, however, reached its limit in terms of scaling since it exhibits a leakage current density higher than 1 A/cm{sup 2} and does not retain its intrinsic physical properties at thicknesses below 1.5 nm. In order to overcome these problems and keep Moore's law ongoing, the use of higher dielectric constant (k) gate oxides has been suggested. These high-k materials must satisfy numerous requirements such as the high k, low leakage currents, suitable band gap und offsets to silicon. Rare-earth based dielectrics are promising materials which fulfill these needs. We will review the properties of REScO{sub 3} (RE = La, Dy, Gd, Sm, Tb) and LaLuO{sub 3} thin films, grown with pulsed laser deposition, e-gun evaporation or molecular beam deposition, integrated in capacitors and transistors. A k > 20 for the REScO{sub 3} (RE = Dy, Gd) and around 30 for (RE = La, Sm, Tb) and LaLuO{sub 3} are obtained. Transistors prepared on SOI and sSOI show mobility values up to 380 cm{sup 2}/Vs on sSOI, which are comparable to such prepared with HfO{sub 2}.

Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging?

Directory of Open Access Journals (Sweden)

Takashi Ando

2012-03-01

Full Text Available Current status and challenges of aggressive equivalent-oxide-thickness (EOT scaling of high-κ gate dielectrics via higher-κ ( > 20 materials and interfacial layer (IL scavenging techniques are reviewed. La-based higher-κ materials show aggressive EOT scaling (0.5–0.8 nm, but with effective workfunction (EWF values suitable only for n-type field-effect-transistor (FET. Further exploration for p-type FET-compatible higher-κ materials is needed. Meanwhile, IL scavenging is a promising approach to extend Hf-based high-κ dielectrics to future nodes. Remote IL scavenging techniques enable EOT scaling below 0.5 nm. Mobility-EOT trends in the literature suggest that short-channel performance improvement is attainable with aggressive EOT scaling via IL scavenging or La-silicate formation. However, extreme IL scaling (e.g., zero-IL is accompanied by loss of EWF control and with severe penalty in reliability. Therefore, highly precise IL thickness control in an ultra-thin IL regime ( < 0.5 nm will be the key technology to satisfy both performance and reliability requirements for future CMOS devices.

Synthesis and electrical characterization of low-temperature thermal-cured epoxy resin/functionalized silica hybrid-thin films for application as gate dielectrics

Energy Technology Data Exchange (ETDEWEB)

Na, Moonkyong, E-mail: nmk@keri.re.kr [HVDC Research Division, Korea Electrotechnology Research Institute, Changwon, 642-120 (Korea, Republic of); System on Chip Chemical Process Research Center, Department of Chemical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, 790-784 (Korea, Republic of); Kang, Young Taec [Creative and Fundamental Research Division, Korea Electrotechnology Research Institute, Changwon, 642-120 (Korea, Republic of); Department of Polymer Science and Engineering, Pusan National University, Busan, 609-735 (Korea, Republic of); Kim, Sang Cheol [HVDC Research Division, Korea Electrotechnology Research Institute, Changwon, 642-120 (Korea, Republic of); Kim, Eun Dong [Creative and Fundamental Research Division, Korea Electrotechnology Research Institute, Changwon, 642-120 (Korea, Republic of)

2013-07-31

Thermal-cured hybrid materials were synthesized from homogenous hybrid sols of epoxy resins and organoalkoxysilane-functionalized silica. The chemical structures of raw materials and obtained hybrid materials were characterized using Fourier transform infrared spectroscopy. The thermal resistance of the hybrids was enhanced by hybridization. The interaction between epoxy matrix and the silica particles, which caused hydrogen bonding and van der Waals force was strengthened by organoalkoxysilane. The degradation temperature of the hybrids was improved by approximately 30 °C over that of the parent epoxy material. The hybrid materials were formed into uniformly coated thin films of about 50 nm-thick using a spin coater. An optimum mixing ratio was used to form smooth-surfaced hybrid films. The electrical property of the hybrid film was characterized, and the leakage current was found to be well below 10{sup −6} A cm{sup −2}. - Highlights: • Preparation of thermal-curable hybrid materials using epoxy resin and silica. • The thermal stability was enhanced through hybridization. • The insulation property of hybrid film was investigated as gate dielectrics.

Electrical characteristics of AlO sub x N sub y prepared by oxidation of sub-10-nm-thick AlN films for MOS gate dielectric applications

CERN Document Server

Jeon, S H; Kim, H S; Noh, D Y; Hwang, H S

2000-01-01

In this research, the feasibility of ultrathin AlO sub x N sub y prepared by oxidation of sub 100-A-thick AlN thin films for metal-oxide-semiconductor (MOS) gate dielectric applications was investigated. Oxidation of 51-A-and 98-A-thick as-deposited AlN at 800 .deg. C was used to form 72-A-and 130-A-thick AlO sub x N sub y , respectively. Based on the capacitance-voltage (C-V) measurements of the MOS capacitor, the dielectric constants of 72 A-thick and 130 A-thick Al-oxynitride were 5.15 and 7, respectively. The leakage current of Al-oxynitride at low field was almost the same as that of thermal SiO sub 2. based on the CV data, the interface state density of Al-oxynitride was relatively higher than that of SiO sub 2. Although process optimization is still necessary, the Al-oxynitride exhibits some possibility for future MOS gate dielectric applications.

Electrical characteristics of AlO{sub x}N{sub y} prepared by oxidation of sub-10-nm-thick AlN films for MOS gate dielectric applications

Energy Technology Data Exchange (ETDEWEB)

Jeon, Sang Hun; Jang, Hyeon Woo; Kim, Hyun Soo; Noh, Do Young; Hwang, Hyun Sang [Kwangju Institute of Science and Technology, Kwangju (Korea, Republic of)

2000-12-01

In this research, the feasibility of ultrathin AlO{sub x}N{sub y} prepared by oxidation of sub 100-A-thick AlN thin films for metal-oxide-semiconductor (MOS) gate dielectric applications was investigated. Oxidation of 51-A-and 98-A-thick as-deposited AlN at 800 .deg. C was used to form 72-A-and 130-A-thick AlO{sub x}N{sub y}, respectively. Based on the capacitance-voltage (C-V) measurements of the MOS capacitor, the dielectric constants of 72 A-thick and 130 A-thick Al-oxynitride were 5.15 and 7, respectively. The leakage current of Al-oxynitride at low field was almost the same as that of thermal SiO{sub 2}. based on the CV data, the interface state density of Al-oxynitride was relatively higher than that of SiO{sub 2}. Although process optimization is still necessary, the Al-oxynitride exhibits some possibility for future MOS gate dielectric applications.

Device performance of in situ steam generated gate dielectric nitrided by remote plasma nitridation

International Nuclear Information System (INIS)

Al-Shareef, H. N.; Karamcheti, A.; Luo, T. Y.; Bersuker, G.; Brown, G. A.; Murto, R. W.; Jackson, M. D.; Huff, H. R.; Kraus, P.; Lopes, D.

2001-01-01

In situ steam generated (ISSG) oxides have recently attracted interest for use as gate dielectrics because of their demonstrated reliability improvement over oxides formed by dry oxidation. [G. Minor, G. Xing, H. S. Joo, E. Sanchez, Y. Yokota, C. Chen, D. Lopes, and A. Balakrishna, Electrochem. Soc. Symp. Proc. 99-10, 3 (1999); T. Y. Luo, H. N. Al-Shareef, G. A. Brown, M. Laughery, V. Watt, A. Karamcheti, M. D. Jackson, and H. R. Huff, Proc. SPIE 4181, 220 (2000).] We show in this letter that nitridation of ISSG oxide using a remote plasma decreases the gate leakage current of ISSG oxide by an order of magnitude without significantly degrading transistor performance. In particular, it is shown that the peak normalized transconductance of n-channel devices with an ISSG oxide gate dielectric decreases by only 4% and the normalized drive current by only 3% after remote plasma nitridation (RPN). In addition, it is shown that the reliability of the ISSG oxide exhibits only a small degradation after RPN. These observations suggest that the ISSG/RPN process holds promise for gate dielectric applications. [copyright] 2001 American Institute of Physics

Logic circuits composed of flexible carbon nanotube thin-film transistor and ultra-thin polymer gate dielectric

Science.gov (United States)

Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu

2016-05-01

Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V-1 sec-1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.

Study of strained-Si p-channel MOSFETs with HfO2 gate dielectric

Science.gov (United States)

Pradhan, Diana; Das, Sanghamitra; Dash, Tara Prasanna

2016-10-01

In this work, the transconductance of strained-Si p-MOSFETs with high-K dielectric (HfO2) as gate oxide, has been presented through simulation using the TCAD tool Silvaco-ATLAS. The results have been compared with a SiO2/strained-Si p-MOSFET device. Peak transconductance enhancement factors of 2.97 and 2.73 has been obtained for strained-Si p-MOSFETs in comparison to bulk Si channel p-MOSFETs with SiO2 and high-K dielectric respectively. This behavior is in good agreement with the reported experimental results. The transconductance of the strained-Si device at low temperatures has also been simulated. As expected, the mobility and hence the transconductance increases at lower temperatures due to reduced phonon scattering. However, the enhancements with high-K gate dielectric is less as compared to that with SiO2.

Polycrystalline diamond RF MOSFET with MoO3 gate dielectric

Directory of Open Access Journals (Sweden)

Zeyang Ren

2017-12-01

Full Text Available We report the radio frequency characteristics of the diamond metal-oxide-semiconductor field effect transistor with MoO3 gate dielectric for the first time. The device with 2-μm gate length was fabricated on high quality polycrystalline diamond. The maximum drain current of 150 mA/mm at VGS = -5 V and the maximum transconductance of 27 mS/mm were achieved. The extrinsic cutoff frequency of 1.2 GHz and the maximum oscillation frequency of 1.9 GHz have been measured. The moderate frequency characteristics are attributed to the moderate transconductance limited by the series resistance along the channel. We expect that the frequency characteristics of the device can be improved by increasing the magnitude of gm, or fundamentally decreasing the gate-controlled channel resistance and series resistance along the channel, and down-scaling the gate length.

Novel organic semiconductors and dielectric materials for high performance and low-voltage organic thin-film transistors

Science.gov (United States)

Yoon, Myung-Han

Two novel classes of organic semiconductors based on perfluoroarene/arene-modified oligothiophenes and perfluoroacyl/acyl-derivatized quaterthiophens are developed. The frontier molecular orbital energies of these compounds are studied by optical spectroscopy and electrochemistry while solid-state/film properties are investigated by thermal analysis, x-ray diffraction, and scanning electron microscopy. Organic thin film transistors (OTFTs) performance parameters are discussed in terms of the interplay between semiconductor molecular energetics and film morphologies/microstructures. For perfluoroarene-thiophene oligomer systems, majority charge carrier type and mobility exhibit a strong correlation with the regiochemistry of perfluoroarene incorporation. In quaterthiophene-based semiconductors, carbonyl-functionalization allows tuning of the majority carrier type from p-type to ambipolar and to n-type. In situ conversion of a p-type semiconducting film to n-type film is also demonstrated. Very thin self-assembled or spin-on organic dielectric films have been integrated into OTFTs to achieve 1 - 2 V operating voltages. These new dielectrics are deposited either by layer-by-layer solution phase deposition of molecular precursors or by spin-coating a mixture of polymer and crosslinker, resulting in smooth and virtually pinhole-free thin films having exceptionally large capacitances (300--700 nF/cm2) and low leakage currents (10 -9 - 10-7 A/cm2). These organic dielectrics are compatible with various vapor- or solution-deposited p- and n-channel organic semiconductors. Furthermore, it is demonstrated that spin-on crosslinked-polymer-blend dielectrics can be employed for large-area/patterned electronics, and complementary inverters. A general approach for probing semiconductor-dielectric interface effects on OTFT performance parameters using bilayer gate dielectrics is presented. Organic semiconductors having p-, n-type, or ambipolar majority charge carriers are grown on

Chemical vapor deposited monolayer MoS2 top-gate MOSFET with atomic-layer-deposited ZrO2 as gate dielectric

Science.gov (United States)

Hu, Yaoqiao; Jiang, Huaxing; Lau, Kei May; Li, Qiang

2018-04-01

For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec-1, and a field-effect electron mobility of 12.1 cm2 V-1 s-1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm-1 at V DS = 5 V. The gate leakage current is below 10-2 A cm-2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm-1 is obtained. Gate hysteresis and frequency-dependent capacitance-voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ˜3 × 1012 cm-2 eV-1.

Bi-axially crumpled silver thin-film electrodes for dielectric elastomer actuators

International Nuclear Information System (INIS)

Low, Sze-Hsien; Lau, Gih-Keong

2014-01-01

Metal thin films, which have high conductivity, are much stiffer and may fracture at a much lower strain than dielectric elastomers. In order to fabricate compliant electrodes for use in dielectric elastomer actuators (DEAs), metal thin films have been formed into either zigzag patterns or corrugations, which favour bending and only allow uniaxial DEA deformations. However, biaxially compliant electrodes are desired in order to maximize generated forces of DEA. In this paper, we present crumpled metal thin-film electrodes that are biaxially compliant and have full area coverage over the dielectric elastomer. These crumpled metal thin-film electrodes are more stretchable than flat metal thin films; they remain conductive beyond 110% radial strain. Also, crumpling reduced the stiffening effect of metal thin films on the soft elastomer. As such, DEAs using crumpled metal thin-film electrodes managed to attain relatively high actuated area strains of up to 128% at 1.8 kV (102 Vμm −1 ). (paper)

A threshold-voltage model for small-scaled GaAs nMOSFET with stacked high-k gate dielectric

International Nuclear Information System (INIS)

Liu Chaowen; Xu Jingping; Liu Lu; Lu Hanhan; Huang Yuan

2016-01-01

A threshold-voltage model for a stacked high-k gate dielectric GaAs MOSFET is established by solving a two-dimensional Poisson's equation in channel and considering the short-channel, DIBL and quantum effects. The simulated results are in good agreement with the Silvaco TCAD data, confirming the correctness and validity of the model. Using the model, impacts of structural and physical parameters of the stack high-k gate dielectric on the threshold-voltage shift and the temperature characteristics of the threshold voltage are investigated. The results show that the stacked gate dielectric structure can effectively suppress the fringing-field and DIBL effects and improve the threshold and temperature characteristics, and on the other hand, the influence of temperature on the threshold voltage is overestimated if the quantum effect is ignored. (paper)

Study of high-k gate dielectrics by means of positron annihilation

International Nuclear Information System (INIS)

Uedono, A.; Naito, T.; Otsuka, T.; Ito, K.; Shiraishi, K.; Yamabe, K.; Miyazaki, S.; Watanabe, H.; Umezawa, N.; Hamid, A.; Chikyow, T.; Ohdaira, T.; Suzuki, R.; Ishibashi, S.; Inumiya, S.; Kamiyama, S.; Akasaka, Y.; Nara, Y.; Yamada, K.

2007-01-01

High-dielectric constant (high-k) gate materials, such as HfSiO x and HfAlO x , fabricated by atomic-layer-deposition techniques were characterized using monoenergetic positron beams. Measurements of the Doppler broadening spectra of annihilation radiation and the lifetime spectra of positrons indicated that positrons annihilated from the trapped state by open volumes that exist intrinsically in amorphous structures of the films. The size distributions of the open volumes and the local atomic configurations around such volumes can be discussed using positron annihilation parameters, and they were found to correlate with the electrical properties of the films. We confirmed that the positron annihilation is useful technique to characterize the matrix structure of amorphous high-k materials, and can be used to determine process parameters for the fabrication of high-k gate dielectrics. (copyright 2007 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for Advanced CMOS Devices

Directory of Open Access Journals (Sweden)

Masamichi Suzuki

2012-03-01

Full Text Available A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3 high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process.

Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

Science.gov (United States)

Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

2015-03-04

Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

Enhanced dielectric and electrical properties of annealed PVDF thin film

Science.gov (United States)

Arshad, A. N.; Rozana, M. D.; Wahid, M. H. M.; Mahmood, M. K. A.; Sarip, M. N.; Habibah, Z.; Rusop, M.

2018-05-01

Poly (vinylideneflouride) (PVDF) thin films were annealed at various annealing temperatures ranging from 70°C to 170°C. This study demonstrates that PVDF thin films annealed at temperature of 70°C (AN70) showed significant enhancement in their dielectric constant (14) at frequency of 1 kHz in comparison to un-annealed PVDF (UN-PVDF), dielectric constant (10) at the same measured frequency. As the annealing temperature was increased from 90°C (AN90) to 150°C (AN150), the dielectric constant value of PVDF thin films was observed to decrease gradually to 11. AN70 also revealed low tangent loss (tan δ) value at similar frequency. With respect to its resistivity properties, the values were found to increase from 1.98×104 Ω.cm to 3.24×104 Ω.cm for AN70 and UN-PVDF films respectively. The improved in dielectric constant, with low tangent loss and high resistivity value suggests that 70°C is the favorable annealing temperature for PVDF thin films. Hence, AN70 is a promising film to be utilized for application in electronic devices such as low frequency capacitor.

Origin of switching current transients in TIPS-pentacene based organic thin-film transistor with polymer dielectric

Science.gov (United States)

Singh, Subhash; Mohapatra, Y. N.

2017-06-01

We have investigated switch-on drain-source current transients in fully solution-processed thin film transistors based on 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) using cross-linked poly-4-vinylphenol as a dielectric. We show that the nature of the transient (increasing or decreasing) depends on both the temperature and the amplitude of the switching pulse at the gate. The isothermal transients are analyzed spectroscopically in a time domain to extract the degree of non-exponentiality and its possible origin in trap kinetics. We propose a phenomenological model in which the exchange of electrons between interfacial ions and traps controls the nature of the drain current transients dictated by the Fermi level position. The origin of interfacial ions is attributed to the essential fabrication step of UV-ozone treatment of the dielectric prior to semiconductor deposition.

A threshold-voltage model for small-scaled GaAs nMOSFET with stacked high-k gate dielectric

Science.gov (United States)

Chaowen, Liu; Jingping, Xu; Lu, Liu; Hanhan, Lu; Yuan, Huang

2016-02-01

A threshold-voltage model for a stacked high-k gate dielectric GaAs MOSFET is established by solving a two-dimensional Poisson's equation in channel and considering the short-channel, DIBL and quantum effects. The simulated results are in good agreement with the Silvaco TCAD data, confirming the correctness and validity of the model. Using the model, impacts of structural and physical parameters of the stack high-k gate dielectric on the threshold-voltage shift and the temperature characteristics of the threshold voltage are investigated. The results show that the stacked gate dielectric structure can effectively suppress the fringing-field and DIBL effects and improve the threshold and temperature characteristics, and on the other hand, the influence of temperature on the threshold voltage is overestimated if the quantum effect is ignored. Project supported by the National Natural Science Foundation of China (No. 61176100).

Effect of dielectric layers on device stability of pentacene-based field-effect transistors.

Science.gov (United States)

Di, Chong-an; Yu, Gui; Liu, Yunqi; Guo, Yunlong; Sun, Xiangnan; Zheng, Jian; Wen, Yugeng; Wang, Ying; Wu, Weiping; Zhu, Daoben

2009-09-07

We report stable organic field-effect transistors (OFETs) based on pentacene. It was found that device stability strongly depends on the dielectric layer. Pentacene thin-film transistors based on the bare or polystyrene-modified SiO(2) gate dielectrics exhibit excellent electrical stabilities. In contrast, the devices with the octadecyltrichlorosilane (OTS)-treated SiO(2) dielectric layer showed the worst stabilities. The effects of the different dielectrics on the device stabilities were investigated. We found that the surface energy of the gate dielectric plays a crucial role in determining the stability of the pentacene thin film, device performance and degradation of electrical properties. Pentacene aggregation, phase transfer and film morphology are also important factors that influence the device stability of pentacene devices. As a result of the surface energy mismatch between the dielectric layer and organic semiconductor, the electronic performance was degraded. Moreover, when pentacene was deposited on the OTS-treated SiO(2) dielectric layer with very low surface energy, pentacene aggregation occurred and resulted in a dramatic decrease of device performance. These results demonstrated that the stable OFETs could be obtained by using pentacene as a semiconductor layer.

Top-gate dielectric induced doping and scattering of charge carriers in epitaxial graphene

Science.gov (United States)

Puls, Conor P.; Staley, Neal E.; Moon, Jeong-Sun; Robinson, Joshua A.; Campbell, Paul M.; Tedesco, Joseph L.; Myers-Ward, Rachael L.; Eddy, Charles R.; Gaskill, D. Kurt; Liu, Ying

2011-07-01

We show that an e-gun deposited dielectric impose severe limits on epitaxial graphene-based device performance based on Raman spectroscopy and low-temperature transport measurements. Specifically, we show from studies of epitaxial graphene Hall bars covered by SiO2 that the measured carrier density is strongly inhomogenous and predominantly induced by charged impurities at the grapheme/dielectric interface that limit mobility via Coulomb interactions. Our work emphasizes that material integration of epitaxial graphene and a gate dielectric is the next major road block towards the realization of graphene-based electronics.

Low operating voltage InGaZnO thin-film transistors based on Al2O3 high-k dielectrics fabricated using pulsed laser deposition

International Nuclear Information System (INIS)

Geng, G. Z.; Liu, G. X.; Zhang, Q.; Shan, F. K.; Lee, W. J.; Shin, B. C.; Cho, C. R.

2014-01-01

Low-voltage-driven amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) with an Al 2 O 3 dielectric were fabricated on a Si substrate by using pulsed laser deposition. Both Al 2 O 3 and IGZO thin films are amorphous, and the thin films have very smooth surfaces. The Al 2 O 3 gate dielectric exhibits a very low leakage current density of 1.3 x 10 -8 A/cm 2 at 5 V and a high capacitance density of 60.9 nF/cm 2 . The IGZO TFT with a structure of Ni/IGZO/Al 2 O 3 /Si exhibits high performance with a low threshold voltage of 1.18 V, a high field effect mobility of 20.25 cm 2 V -1 s -1 , an ultra small subthreshold swing of 87 mV/decade, and a high on/off current ratio of 3 x 10 7 .

Influence of Gate Dielectrics, Electrodes and Channel Width on OFET Characteristics

International Nuclear Information System (INIS)

Liyana, V P; Stephania, A M; Shiju, K; Predeep, P

2015-01-01

Organic Field Effect Transistors (OFET) possess wide applications in large area electronics owing to their attractive features like easy fabrication process, light weight, flexibility, cost effectiveness etc. But instability, high operational voltages and low carrier mobility act as inhibitors to commercialization of OFETs and various approaches were tried on a regular basis so as to make it viable. In this work, Poly 3-hexylthiophene-2,5diyl (P3HT) based OFETs with bottom-contact top-gate configuration using Poly vinyl alcohol (PVA) and Poly (methyl methacrylate) (PMMA) as gate dielectrics, aluminium and copper as source-drain electrodes are investigated. An effort is made to compare the effect of these dielectric materials and electrodes on the performance of OFET. Also, an attempt has been made to optimize the channel width of the device. These devices are characterised with mobility (μ), threshold voltage (V T ), on-off ratio (I on /I off ) and their comparative analysis is reported. (paper)

Influence of Gate Dielectrics, Electrodes and Channel Width on OFET Characteristics

Science.gov (United States)

Liyana, V. P.; Stephania, A. M.; Shiju, K.; Predeep, P.

2015-06-01

Organic Field Effect Transistors (OFET) possess wide applications in large area electronics owing to their attractive features like easy fabrication process, light weight, flexibility, cost effectiveness etc. But instability, high operational voltages and low carrier mobility act as inhibitors to commercialization of OFETs and various approaches were tried on a regular basis so as to make it viable. In this work, Poly 3-hexylthiophene-2,5diyl (P3HT) based OFETs with bottom-contact top-gate configuration using Poly vinyl alcohol (PVA) and Poly (methyl methacrylate) (PMMA) as gate dielectrics, aluminium and copper as source-drain electrodes are investigated. An effort is made to compare the effect of these dielectric materials and electrodes on the performance of OFET. Also, an attempt has been made to optimize the channel width of the device. These devices are characterised with mobility (μ), threshold voltage (VT), on-off ratio (Ion/Ioff) and their comparative analysis is reported.

Al2O3 nanocrystals embedded in amorphous Lu2O3 high-k gate dielectric for floating gate memory application

International Nuclear Information System (INIS)

Yuan, C L; Chan, M Y; Lee, P S; Darmawan, P; Setiawan, Y

2007-01-01

The integration of nanoparticles has high potential in technological applications and opens up possibilities of the development of new devices. Compared to the conventional floating gate memory, a structure containing nanocrystals embedded in dielectrics shows high potential to produce a memory with high endurance, low operating voltage, fast write-erase speeds and better immunity to soft errors [S. Tiwari, F. Rana, H. Hanafi et al. 1996 Appl.Phys. Lett. 68, 1377]. A significant improvement on data retention [J. J. Lee, X. Wang et al. 2003 Proceedings of the VLSI Technol. Symposium, p33] can be observed when discrete nanodots are used instead of continuous floating gate as charge storage nodes because local defect related leakage can be reduced efficiently. Furthermore, using a high-k dielectric in place of the conventional SiO2 based dielectric, nanodots flash memory is able to achieve significantly improved programming efficiency and data retention [A. Thean and J. -P. Leburton, 2002 IEEE Potentials 21, 35; D. W. Kim, T. Kim and S. K. Banerjee, 2003 IEEE Trans. Electron Devices 50, 1823]. We have recently successfully developed a method to produce nanodots embedded in high-k gate dielectrics [C. L. Yuan, P. Darmawan, Y. Setiawan and P. S. Lee, 2006 Electrochemical and Solid-State Letters 9, F53; C. L. Yuan, P. Darmawan, Y. Setiawan and P. S. Lee, 2006 Europhys. Lett. 74, 177]. In this paper, we fabricated the memory structure of Al 2 O 3 nanocrystals embedded in amorphous Lu 2 O 3 high k dielectric using pulsed laser ablation. The mean size and density of the Al 2 O 3 nanocrystals are estimated to be about 5 nm and 7x1011 cm -2 , respectively. Good electrical performances in terms of large memory window and good data retention were observed. Our preparation method is simple, fast and economical

Bio Organic-Semiconductor Field-Effect Transistor (BioFET) Based on Deoxyribonucleic Acid (DNA) Gate Dielectric

Science.gov (United States)

2010-03-31

floating gate devices and metal-insulator-oxide-semiconductor (MIOS) devices. First attempts to use polarizable gate insulators in combination with...bulk of the semiconductor (ii) Due to the polarizable gate dielectric (iii) dipole polarization and (iv)electret effect due to mobile ions in the...characterization was carried out under an argon environment inside the glove box. An Agilent model E5273A with a two source-measurement unit instrument was

The Electrical Breakdown of Thin Dielectric Elastomers

DEFF Research Database (Denmark)

Zakaria, Shamsul Bin; Morshuis, Peter H. F.; Yahia, Benslimane Mohamed

2014-01-01

Dielectric elastomers are being developed for use in actuators, sensors and generators to be used in various applications, such as artificial eye lids, pressure sensors and human motion energy generators. In order to obtain maximum efficiency, the devices are operated at high electrical fields....... This increases the likelihood for electrical breakdown significantly. Hence, for many applications the performance of the dielectric elastomers is limited by this risk of failure, which is triggered by several factors. Amongst others thermal effects may strongly influence the electrical breakdown strength....... In this study, we model the electrothermal breakdown in thin PDMS based dielectric elastomers in order to evaluate the thermal mechanisms behind the electrical failures. The objective is to predict the operation range of PDMS based dielectric elastomers with respect to the temperature at given electric field...

Carbon nanotube network thin-film transistors on flexible/stretchable substrates

Science.gov (United States)

Takei, Kuniharu; Takahashi, Toshitake; Javey, Ali

2016-03-29

This disclosure provides systems, methods, and apparatus for flexible thin-film transistors. In one aspect, a device includes a polymer substrate, a gate electrode disposed on the polymer substrate, a dielectric layer disposed on the gate electrode and on exposed portions of the polymer substrate, a carbon nanotube network disposed on the dielectric layer, and a source electrode and a drain electrode disposed on the carbon nanotube network.

Pentacene-Based Thin Film Transistor with Inkjet-Printed Nanocomposite High-K Dielectrics

Directory of Open Access Journals (Sweden)

Chao-Te Liu

2012-01-01

Full Text Available The nanocomposite gate insulating film of a pentacene-based thin film transistor was deposited by inkjet printing. In this study, utilizing the pearl miller to crumble the agglomerations and the dispersant to well stabilize the dispersion of nano-TiO2 particles in the polymer matrix of the ink increases the dose concentration for pico-jetting, which could be as the gate dielectric film made by inkjet printing without the photography process. Finally, we realized top contact pentacene-TFTs and successfully accomplished the purpose of directly patternability and increase the performance of the device based on the nanocomposite by inkjet printing. These devices exhibited p-channel TFT characteristics with a high field-effect mobility (a saturation mobility of ̃0.58 cm2 V−1 s−1, a large current ratio (>103 and a low operation voltage (<6 V. Furthermore, we accorded the deposited mechanisms which caused the interface difference between of inkjet printing and spin coating. And we used XRD, SEM, Raman spectroscopy to help us analyze the transfer characteristics of pentacene films and the performance of OTFTs.

Dielectric and acoustical high frequency characterisation of PZT thin films

International Nuclear Information System (INIS)

Conde, Janine; Muralt, Paul

2010-01-01

Pb(Zr, Ti)O 3 (PZT) is an interesting material for bulk acoustic wave resonator applications due to its high electromechanical coupling constant, which would enable fabrication of large bandwidth frequency filters. The major challenge of the PZT solid solution system is to overcome mechanical losses generally observed in PZT ceramics. To increase the understanding of these losses in textured thin films, thin film bulk acoustic resonators (TFBAR's) based on PZT thin films with compositions either in the tetragonal region or at the morphotropic phase boundary and (111) or {100} textures were fabricated and studied up to 2 GHz. The dielectric and elastic materials coefficients were extracted from impedance measurements at the resonance frequency. The dispersion of the dielectric constant was obtained from impedance measurements up to 2 GHz. The films with varying compositions, textures and deposition methods (sol-gel or sputtering) were compared in terms of dielectric and acoustical properties.

Dielectric and acoustical high frequency characterisation of PZT thin films

Science.gov (United States)

Conde, Janine; Muralt, Paul

2010-02-01

Pb(Zr, Ti)O3 (PZT) is an interesting material for bulk acoustic wave resonator applications due to its high electromechanical coupling constant, which would enable fabrication of large bandwidth frequency filters. The major challenge of the PZT solid solution system is to overcome mechanical losses generally observed in PZT ceramics. To increase the understanding of these losses in textured thin films, thin film bulk acoustic resonators (TFBAR's) based on PZT thin films with compositions either in the tetragonal region or at the morphotropic phase boundary and (111) or {100} textures were fabricated and studied up to 2 GHz. The dielectric and elastic materials coefficients were extracted from impedance measurements at the resonance frequency. The dispersion of the dielectric constant was obtained from impedance measurements up to 2 GHz. The films with varying compositions, textures and deposition methods (sol-gel or sputtering) were compared in terms of dielectric and acoustical properties.

Label Free Detection of Biomolecules Using Charge-Plasma-Based Gate Underlap Dielectric Modulated Junctionless TFET

Science.gov (United States)

Wadhwa, Girish; Raj, Balwinder

2018-05-01

Nanoscale devices are emerging as a platform for detecting biomolecules. Various issues were observed during the fabrication process such as random dopant fluctuation and thermal budget. To reduce these issues charge-plasma-based concept is introduced. This paper proposes the implementation of charge-plasma-based gate underlap dielectric modulated junctionless tunnel field effect transistor (DM-JLTFET) for the revelation of biomolecule immobilized in the open cavity gate channel region. In this p+ source and n+ drain regions are introduced by employing different work function over the intrinsic silicon. Also dual material gate architecture is implemented to reduce short channel effect without abandoning any other device characteristic. The sensitivity of biosensor is studied for both the neutral and charge-neutral biomolecules. The effect of device parameters such as channel thickness, cavity length and cavity thickness on drain current have been analyzed through simulations. This paper investigates the performance of charge-plasma-based gate underlap DM-JLTFET for biomolecule sensing applications while varying dielectric constant, charge density at different biasing conditions.

Gate dielectric strength dependent performance of CNT MOSFET and CNT TFET: A tight binding study

Directory of Open Access Journals (Sweden)

Md. Shamim Sarker

Full Text Available This paper presents a comparative study between CNT MOSFET and CNT TFET taking into account of different dielectric strength of gate oxide materials. Here we have studied the transfer characteristics, on/off current (ION/IOFF ratio and subthreshold slope of the device using Non Equilibrium Greens Function (NEGF formalism in tight binding frameworks. The results are obtained by solving the NEGF and Poisson’s equation self-consistently in NanoTCADViDES environment and found that the ON state performance of CNT MOSFET and CNT TFET have significant dependency on the dielectric strength of the gate oxide materials. The figure of merits of the devices also demonstrates that the CNT TFET is promising for high-speed and low-power logic applications. Keywords: CNT TFET, Subthreshold slop, Barrier width, Conduction band (C.B and Valance band (V.B, Oxide dielectric strength, Tight binding approach

Investigation of SiO2 thin films dielectric constant using ellipsometry technique

Directory of Open Access Journals (Sweden)

P Sangpour

2014-11-01

Full Text Available In this paper, we studied the optical behavior of SiO2 thin films prepared via sol-gel route using spin coating deposition from tetraethylorthosilicate (TEOS as precursor. Thin films were annealed at different temperatures (400-600oC. Absorption edge and band gap of thin layers were measured using UV-Vis spectrophotometery. Optical refractive index and dielectric constant were measured by ellipsometry technique. Based on our atomic force microscopic (AFM and ellipsometry results, thin layers prepared through this method showed high surface area, and high porosity ranging between 4.9 and 16.9, low density 2 g/cm, and low dielectric constant. The dielectric constant and porosity of layers increased by increasing the temperature due to the changes in surface roughness and particle size.

Plasmonic versus dielectric enhancement in thin-film solar cells

DEFF Research Database (Denmark)

Dühring, Maria Bayard; Mortensen, N. Asger; Sigmund, Ole

2012-01-01

to its metallic counterpart. We show that the enhanced normalized short-circuit current for a cell with silicon strips can be increased 4 times compared to the best performance for strips of silver, gold, or aluminium. For this particular case, the simple dielectric grating may outperform its plasmonic......Several studies have indicated that broadband absorption of thin-film solar cells can be enhanced by use of surface-plasmon induced resonances of metallic parts like strips or particles. The metallic parts may create localized modes or scatter incoming light to increase absorption in thin......-film semiconducting material. For a particular case, we show that coupling to the same type of localized slab-waveguide modes can be obtained by a surface modulation consisting of purely dielectric strips. The purely dielectric device turns out to have a significantly higher broadband enhancement factor compared...

Dielectric and acoustical high frequency characterisation of PZT thin films

Energy Technology Data Exchange (ETDEWEB)

Conde, Janine; Muralt, Paul, E-mail: janine.conde@epfl.ch [Department of Materials Science, EPFL (Switzerland)

2010-02-15

Pb(Zr, Ti)O{sub 3} (PZT) is an interesting material for bulk acoustic wave resonator applications due to its high electromechanical coupling constant, which would enable fabrication of large bandwidth frequency filters. The major challenge of the PZT solid solution system is to overcome mechanical losses generally observed in PZT ceramics. To increase the understanding of these losses in textured thin films, thin film bulk acoustic resonators (TFBAR's) based on PZT thin films with compositions either in the tetragonal region or at the morphotropic phase boundary and (111) or {l_brace}100{r_brace} textures were fabricated and studied up to 2 GHz. The dielectric and elastic materials coefficients were extracted from impedance measurements at the resonance frequency. The dispersion of the dielectric constant was obtained from impedance measurements up to 2 GHz. The films with varying compositions, textures and deposition methods (sol-gel or sputtering) were compared in terms of dielectric and acoustical properties.

Dielectric loss of strontium titanate thin films

Science.gov (United States)

Dalberth, Mark Joseph

1999-12-01

Interest in strontium titanate (STO) thin films for microwave device applications continues to grow, fueled by the telecommunications industry's interest in phase shifters and tunable filters. The optimization of these devices depends upon increasing the phase or frequency tuning and decreasing the losses in the films. Currently, the dielectric response of thin film STO is poorly understood through lack of data and a theory to describe it. We have studied the growth of STO using pulsed laser deposition and single crystal substrates like lanthanum aluminate and neodymium gallate. We have researched ways to use ring resonators to accurately measure the dielectric response as a function of temperature, electric field, and frequency from low radio frequencies to a few gigahertz. Our films grown on lanthanum aluminate show marked frequency dispersion in the real part of the dielectric constant and hints of thermally activated loss behavior. We also found that films grown with conditions that optimized the dielectric constant showed increased losses. In an attempt to simplify the system, we developed a technique called epitaxial lift off, which has allowed us to study films removed from their growth substrates. These free standing films have low losses and show obvious thermally activated behavior. The "amount of tuning," as measured by a figure of merit, KE, is greater in these films than in the films still attached to their growth substrates. We have developed a theory that describes the real and imaginary parts of the dielectric constant. The theory models the real part using a mean field description of the ionic motion in the crystal and includes the loss by incorporating the motion of charged defects in the films.

Low operating voltage n-channel organic field effect transistors using lithium fluoride/PMMA bilayer gate dielectric

Energy Technology Data Exchange (ETDEWEB)

Kumar, S.; Dhar, A., E-mail: adhar@phy.iitkgp.ernet.in

2015-10-15

Highlights: • Alternative to chemically crosslinking of PMMA to achieve low leakage in provided. • Effect of LiF in reducing gate leakage through the OFET device is studied. • Effect of gate leakage on transistor performance has been investigated. • Low voltage operable and low temperature processed n-channel OFETs were fabricated. - Abstract: We report low temperature processed, low voltage operable n-channel organic field effect transistors (OFETs) using N,N′-Dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C{sub 8}) organic semiconductor and poly(methylmethacrylate) (PMMA)/lithium fluoride (LiF) bilayer gate dielectric. We have studied the role of LiF buffer dielectric in effectively reducing the gate leakage through the device and thus obtaining superior performance in contrast to the single layer PMMA dielectric devices. The bilayer OFET devices had a low threshold voltage (V{sub t}) of the order of 5.3 V. The typical values of saturation electron mobility (μ{sub s}), on/off ratio and inverse sub-threshold slope (S) for the range of devices made were estimated to be 2.8 × 10{sup −3} cm{sup 2}/V s, 385, and 3.8 V/decade respectively. Our work thus provides a potential substitution for much complicated process of chemically crosslinking PMMA to achieve low leakage, high capacitance, and thus low operating voltage OFETs.

MIS field effect transistor with barium titanate thin film as a gate insulator

Energy Technology Data Exchange (ETDEWEB)

Firek, P., E-mail: pfirek@elka.pw.edu.p [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland); Werbowy, A.; Szmidt, J. [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland)

2009-11-25

The properties of barium titanate (BaTiO{sub 3}, BT) like, e.g. high dielectric constant and resistivity, allow it to find numerous applications in field of microelectronics. In this work silicon metal insulator semiconductor field effect transistor (MISFET) structures with BaTiO{sub 3} (containing La{sub 2}O{sub 3} admixture) thin films in a role of gate insulator were investigated. The films were produced by means of radio frequency plasma sputtering (RF PS) of sintered BaTiO{sub 3} + La{sub 2}O{sub 3} (2 wt.%) target. In the paper transfer and output current-voltage (I-V), transconductance and output conductance characteristics of obtained transistors are presented and discussed. Basic parameters of these devices like, e.g. threshold voltage (V{sub TH}), are determined and discussed.

Application of Dielectric, Ferroelectric and Piezoelectric Thin Film Devices in Mobile Communication and Medical Systems

NARCIS (Netherlands)

Klee, M.; Beelen, D.; Keurl, W.; Kiewitt, R.; Kumar, B.; Mauczok, R.; Reimann, K.; Renders, Ch.; Roest, A.; Roozeboom, F.; Steeneken, P.G.; Tiggelman, M.P.J.; Vanhelmont, F.; Wunnicke, O.; Lok, P.; Neumann, K.; Fraser, J.; Schmitz, G.

2007-01-01

Dielectric, ferroelectric and piezoelectric thin films are getting more and more attention for next generation mobile communication and medical systems. Thin film technologies based on dielectric, ferroelectric and piezoelectric thin films enable System-in-Package (SiP) devices, resulting in optimal

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

Science.gov (United States)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

Nanosecond Time-Resolved Microscopic Gate-Modulation Imaging of Polycrystalline Organic Thin-Film Transistors

Science.gov (United States)

Matsuoka, Satoshi; Tsutsumi, Jun'ya; Matsui, Hiroyuki; Kamata, Toshihide; Hasegawa, Tatsuo

2018-02-01

We develop a time-resolved microscopic gate-modulation (μ GM ) imaging technique to investigate the temporal evolution of the channel current and accumulated charges in polycrystalline pentacene thin-film transistors (TFTs). A time resolution of as high as 50 ns is achieved by using a fast image-intensifier system that could amplify a series of instantaneous optical microscopic images acquired at various time intervals after the stepped gate bias is switched on. The differential images obtained by subtracting the gate-off image allows us to acquire a series of temporal μ GM images that clearly show the gradual propagation of both channel charges and leaked gate fields within the polycrystalline channel layers. The frontal positions for the propagations of both channel charges and leaked gate fields coincide at all the time intervals, demonstrating that the layered gate dielectric capacitors are successively transversely charged up along the direction of current propagation. The initial μ GM images also indicate that the electric field effect is originally concentrated around a limited area with a width of a few micrometers bordering the channel-electrode interface, and that the field intensity reaches a maximum after 200 ns and then decays. The time required for charge propagation over the whole channel region with a length of 100 μ m is estimated at about 900 ns, which is consistent with the measured field-effect mobility and the temporal-response model for organic TFTs. The effect of grain boundaries can be also visualized by comparison of the μ GM images for the transient and the steady states, which confirms that the potential barriers at the grain boundaries cause the transient shift in the accumulated charges or the transient accumulation of additional charges around the grain boundaries.

SEMICONDUCTOR TECHNOLOGY: TaN wet etch for application in dual-metal-gate integration technology

Science.gov (United States)

Yongliang, Li; Qiuxia, Xu

2009-12-01

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and Jg-Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.

All-solution-processed bottom-gate organic thin-film transistor with improved subthreshold behaviour using functionalized pentacene active layer

International Nuclear Information System (INIS)

Kim, Jinwoo; Jeong, Jaewook; Cho, Hyun Duk; Lee, Changhee; Hong, Yongtaek; Kim, Seul Ong; Kwon, Soon-Ki

2009-01-01

We report organic thin-film transistors (OTFTs) made by simple solution processes in an ambient air environment. Inkjet-printed silver electrodes were used for bottom-gate and bottom-contacted source/drain electrodes. A spin-coated cross-linked poly(4-vinylphenol) (PVP) and a spin-coated 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) were used as a gate dielectric layer and an active layer, respectively. A high-boiling-point solvent was used for TIPS-pentacene and the resulting film showed stem-like morphology. X-ray diffraction (XRD) measurement showed the spin-coated active layer was well crystallized, showing the (0 0 1) plane. The reasonable mobility, on/off ratio and threshold voltage of the fabricated device, which are comparable to those of the previously reported TIPS-pentacene OTFT with gold electrodes, show that the printed silver electrodes worked successfully as gate and source/drain electrodes. Furthermore, the device showed a subthreshold slope of 0.61 V/dec in the linear region (V DS = -5 V), which is the lowest value for spin-coated TIPS-pentacene TFT ever reported, and much lower than that of the thermally evaporated pentacene OTFTs. It is thought that the surface energy of the PVP dielectric layer is well matched with that of a well-ordered TIPS-pentacene (0 0 1) surface when a high-boiling-point solvent and a low-temperature drying process are used, thereby making good interface properties, and showing higher performances than those for pentacene TFT with the same structure.

Carbon nanotube transistors with graphene oxide films as gate dielectrics

Institute of Scientific and Technical Information of China (English)

无

2010-01-01

Carbon nanomaterials,including the one-dimensional(1-D) carbon nanotube(CNT) and two-dimensional(2-D) graphene,are heralded as ideal candidates for next generation nanoelectronics.An essential component for the development of advanced nanoelectronics devices is processing-compatible oxide.Here,in analogy to the widespread use of silicon dioxide(SiO2) in silicon microelectronic industry,we report the proof-of-principle use of graphite oxide(GO) as a gate dielectrics for CNT field-effect transistor(FET) via a fast and simple solution-based processing in the ambient condition.The exceptional transistor characteristics,including low operation voltage(2 V),high carrier mobility(950 cm2/V-1 s-1),and the negligible gate hysteresis,suggest a potential route to the future all-carbon nanoelectronics.

Electrical and materials properties of ZrO2 gate dielectrics grown by atomic layer chemical vapor deposition

Science.gov (United States)

Perkins, Charles M.; Triplett, Baylor B.; McIntyre, Paul C.; Saraswat, Krishna C.; Haukka, Suvi; Tuominen, Marko

2001-04-01

Structural and electrical properties of gate stack structures containing ZrO2 dielectrics were investigated. The ZrO2 films were deposited by atomic layer chemical vapor deposition (ALCVD) after different substrate preparations. The structure, composition, and interfacial characteristics of these gate stacks were examined using cross-sectional transmission electron microscopy and x-ray photoelectron spectroscopy. The ZrO2 films were polycrystalline with either a cubic or tetragonal crystal structure. An amorphous interfacial layer with a moderate dielectric constant formed between the ZrO2 layer and the substrate during ALCVD growth on chemical oxide-terminated silicon. Gate stacks with a measured equivalent oxide thickness (EOT) of 1.3 nm showed leakage values of 10-5 A/cm2 at a bias of -1 V from flatband, which is significantly less than that seen with SiO2 dielectrics of similar EOT. A hysteresis of 8-10 mV was seen for ±2 V sweeps while a midgap interface state density (Dit) of ˜3×1011 states/cm eV was determined from comparisons of measured and ideal capacitance curves.

Low operating voltage InGaZnO thin-film transistors based on Al{sub 2}O{sub 3} high-k dielectrics fabricated using pulsed laser deposition

Energy Technology Data Exchange (ETDEWEB)

Geng, G. Z.; Liu, G. X.; Zhang, Q.; Shan, F. K. [Qingdao University, Qingdao (China); DongEui University, Busan (Korea, Republic of); Lee, W. J.; Shin, B. C. [DongEui University, Busan (Korea, Republic of); Cho, C. R. [Pusan National University, Busan (Korea, Republic of)

2014-05-15

Low-voltage-driven amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) with an Al{sub 2}O{sub 3} dielectric were fabricated on a Si substrate by using pulsed laser deposition. Both Al{sub 2}O{sub 3} and IGZO thin films are amorphous, and the thin films have very smooth surfaces. The Al{sub 2}O{sub 3} gate dielectric exhibits a very low leakage current density of 1.3 x 10{sup -8} A/cm{sup 2} at 5 V and a high capacitance density of 60.9 nF/cm{sup 2}. The IGZO TFT with a structure of Ni/IGZO/Al{sub 2}O{sub 3}/Si exhibits high performance with a low threshold voltage of 1.18 V, a high field effect mobility of 20.25 cm{sup 2}V{sup -1}s{sup -1}, an ultra small subthreshold swing of 87 mV/decade, and a high on/off current ratio of 3 x 10{sup 7}.

Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high- k metal gate NMOSFET with kMC TDDB simulations

International Nuclear Information System (INIS)

Xu Hao; Yang Hong; Luo Wei-Chun; Xu Ye-Feng; Wang Yan-Rong; Tang Bo; Wang Wen-Wu; Qi Lu-Wei; Li Jun-Feng; Yan Jiang; Zhu Hui-Long; Zhao Chao; Chen Da-Peng; Ye Tian-Chun

2016-01-01

The thickness effect of the TiN capping layer on the time dependent dielectric breakdown (TDDB) characteristic of ultra-thin EOT high- k metal gate NMOSFET is investigated in this paper. Based on experimental results, it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer. From the charge pumping measurement and secondary ion mass spectroscopy (SIMS) analysis, it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density. In addition, the influences of interface and bulk trap density ratio N it / N ot are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo (kMC) method. The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses. (paper)

Dry etching of MgCaO gate dielectric and passivation layers on GaN

International Nuclear Information System (INIS)

Hlad, M.; Voss, L.; Gila, B.P.; Abernathy, C.R.; Pearton, S.J.; Ren, F.

2006-01-01

MgCaO films grown by rf plasma-assisted molecular beam epitaxy and capped with Sc 2 O 3 are promising candidates as surface passivation layers and gate dielectrics on GaN-based high electron mobility transistors (HEMTs) and metal-oxide semiconductor HEMTs (MOS-HEMTs), respectively. Two different plasma chemistries were examined for etching these thin films on GaN. Inductively coupled plasmas of CH 4 /H 2 /Ar produced etch rates only in the range 20-70 A/min, comparable to the Ar sputter rates under the same conditions. Similarly slow MgCaO etch rates (∼100 A/min) were obtained with Cl 2 /Ar discharges under the same conditions, but GaN showed rates almost an order of magnitude higher. The MgCaO removal rates are limited by the low volatilities of the respective etch products. The CH 4 /H 2 /Ar plasma chemistry produced a selectivity of around 2 for etching the MgCaO with respect to GaN

Bias Stability Enhancement in Thin-Film Transistor with a Solution-Processed ZrO2 Dielectric as Gate Insulator

Directory of Open Access Journals (Sweden)

Shangxiong Zhou

2018-05-01

Full Text Available In this paper, a high-k metal-oxide film (ZrO2 was successfully prepared by a solution-phase method, and whose physical properties were measured by X-ray diffraction (XRD, X-ray reflectivity (XRR and atomic force microscopy (AFM. Furthermore, indium–gallium–zinc oxide thin-film transistors (IGZO-TFTs with high-k ZrO2 dielectric layers were demonstrated, and the electrical performance and bias stability were investigated in detail. By spin-coating 0.3 M precursor six times, a dense ZrO2 film, with smoother surface and fewer defects, was fabricated. The TFT devices with optimal ZrO2 dielectric exhibit a saturation mobility up to 12.7 cm2 V−1 s−1, and an on/off ratio as high as 7.6 × 105. The offset of the threshold voltage was less than 0.6 V under positive and negative bias stress for 3600 s.

Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

Energy Technology Data Exchange (ETDEWEB)

Chun, Minkyu; Um, Jae Gwang; Park, Min Sang; Chowdhury, Md Delwar Hossain; Jang, Jin, E-mail: jjang@khu.ac.kr [Advanced Display Research Center and Department of Information Display, Kyung Hee University, Seoul 02447 (Korea, Republic of)

2016-07-15

We report the abnormal behavior of the threshold voltage (V{sub TH}) shift under positive bias Temperature stress (PBTS) and negative bias temperature stress (NBTS) at top/bottom gate in dual gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). It is found that the PBTS at top gate shows negative transfer shift and NBTS shows positive transfer shift for both top and bottom gate sweep. The shift of bottom/top gate sweep is dominated by top gate bias (V{sub TG}), while bottom gate bias (V{sub BG}) is less effect than V{sub TG}. The X-ray photoelectron spectroscopy (XPS) depth profile provides the evidence of In metal diffusion to the top SiO{sub 2}/a-IGZO and also the existence of large amount of In{sup +} under positive top gate bias around top interfaces, thus negative transfer shift is observed. On the other hand, the formation of OH{sup −} at top interfaces under the stress of negative top gate bias shows negative transfer shift. The domination of V{sub TG} both on bottom/top gate sweep after PBTS/NBTS is obviously occurred due to thin active layer.

Dielectric Scattering Patterns for Efficient Light Trapping in Thin-Film Solar Cells.

Science.gov (United States)

van Lare, Claire; Lenzmann, Frank; Verschuuren, Marc A; Polman, Albert

2015-08-12

We demonstrate an effective light trapping geometry for thin-film solar cells that is composed of dielectric light scattering nanocavities at the interface between the metal back contact and the semiconductor absorber layer. The geometry is based on resonant Mie scattering. It avoids the Ohmic losses found in metallic (plasmonic) nanopatterns, and the dielectric scatterers are well compatible with nearly all types of thin-film solar cells, including cells produced using high temperature processes. The external quantum efficiency of thin-film a-Si:H solar cells grown on top of a nanopatterned Al-doped ZnO, made using soft imprint lithography, is strongly enhanced in the 550-800 nm spectral band by the dielectric nanoscatterers. Numerical simulations are in good agreement with experimental data and show that resonant light scattering from both the AZO nanostructures and the embedded Si nanostructures are important. The results are generic and can be applied on nearly all thin-film solar cells.

High carrier mobility of CoPc wires based field-effect transistors using bi-layer gate dielectric

Directory of Open Access Journals (Sweden)

Murali Gedda

2013-11-01

Full Text Available Polyvinyl alcohol (PVA and anodized Al2O3 layers were used as bi-layer gate for the fabrication of cobalt phthalocyanine (CoPc wire base field-effect transistors (OFETs. CoPc wires were grown on SiO2 surfaces by organic vapor phase deposition method. These devices exhibit a field-effect carrier mobility (μEF value of 1.11 cm2/Vs. The high carrier mobility for CoPc molecules is attributed to the better capacitive coupling between the channel of CoPc wires and the gate through organic-inorganic dielectric layer. Our measurements also demonstrated the way to determine the thicknesses of the dielectric layers for a better process condition of OFETs.

Electrical characteristics of top contact pentacene organic thin film

Indian Academy of Sciences (India)

Organic thin film transistors (OTFTs) were fabricated using pentacene as the active layer with two different gate dielectrics, namely SiO2 and poly(methyl methacrylate) (PMMA), in top contact geometry for comparative studies. OTFTs with SiO2 as dielectric and gold deposited on the rough side of highly doped silicon (n+ -Si) ...

Mechanical characterization of zeolite low dielectric constant thin films by nanoindentation

International Nuclear Information System (INIS)

Johnson, Mark; Li Zijian; Wang Junlan; Ya, Yushan

2007-01-01

With semiconductor technologies continuously pushing the miniaturization limits, there is a growing interest in developing novel low dielectric constant materials to replace the traditional dense SiO 2 insulators. In order to survive the multi-level integration process and provide reliable material and structure for the desired integrated circuits (IC) functions, the new low-k materials have to be mechanically strong and stable. Therefore the material selection and mechanical characterization are vital for the successful development of next generation low-k dielectrics. A new class of low-k materials, nanoporous pure-silica zeolite, is prepared in thin films using IC compatible spin coating process and characterized using depth sensing nanoindentation technique. The elastic modulus of the zeolite thin films is found to be significantly higher than that of other low-k materials with similar porosity and dielectric constants. Correlations between the mechanical, microstructural and electrical properties of the thin films are discussed in detail

Dielectric relaxation of barium strontium titanate and application to thin films for DRAM capacitors

Science.gov (United States)

Baniecki, John David

This thesis examines the issues associated with incorporating the high dielectric constant material Barium Strontium Titanate (BSTO) in to the storage capacitor of a dynamic random access memory (DRAM). The research is focused on two areas: characterizing and understanding the factors that control charge retention in BSTO thin films and modifying the electrical properties using ion implantation. The dielectric relaxation of BSTO thin films deposited by metal-organic chemical vapor deposition (MOCVD) is investigated in the time and frequency domains. It is shown that the frequency dispersion of the complex capacitance of BSTO thin films can be understood in terms of a power-law frequency dependence from 1mHz to 20GHz. From the correspondence between the time and frequency domain measurements, it is concluded that the power-law relaxation currents extend back to the nano second regime of DRAM operation. The temperature, field, and annealing dependence of the dielectric relaxation currents are also investigated and mechanisms for the observed power law relaxation are explored. An equivalent circuit model of a high dielectric constant thin film capacitor is developed based on the electrical measurements and implemented in PSPICE. Excellent agreement is found between the experimental and simulated electrical characteristics showing the utility of the equivalent circuit model in simulating the electrical properties of high dielectric constant thin films. Using the equivalent circuit model, it is shown that the greatest charge loss due to dielectric relaxation occurs during the first read after a refresh time following a write to the opposite logic state for a capacitor that has been written to the same logic state for a long time (opposite state write charge loss). A theoretical closed form expression that is a function of three material parameters is developed which estimates the opposite state write charge loss due to dielectric relaxation. Using the closed form

Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

Science.gov (United States)

Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

2018-01-01

Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

FDTD simulations and analysis of thin sample dielectric properties measurements using coaxial probes

Energy Technology Data Exchange (ETDEWEB)

Bringhurst, S.; Iskander, M.F.; White, M.J. [Univ. of Utah, Salt Lake City, UT (United States). Electrical Engineering Dept.

1996-12-31

A metallized ceramic probe has been designed for high temperature broadband dielectric properties measurements. The probe was fabricated out of an alumina tube and rod as the outer and inner conductors respectively. The alumina was metallized with a 3 mil layer of moly-manganese and then covered with a 0.5 mil protective layer of nickel plating. The probe has been used to make complex dielectric properties measurements over the complete frequency band from 500 MHz to 3 GHz, and for temperatures as high as 1,000 C. A 3D Finite-Difference Time-Domain (FDTD) code was used to help investigate the feasibility of this probe to measure the complex permittivity of thin samples. It is shown that by backing the material under test with a standard material of known dielectric constant, the complex permittivity of thin samples can be measured accurately using the developed FDTD algorithm. This FDTD procedure for making thin sample dielectric properties measurements will be described.

Evaluation of the effects of thermal annealing temperature and high-k dielectrics on amorphous InGaZnO thin films by using pseudo-MOS transistors

International Nuclear Information System (INIS)

Lee, Se-Won; Cho, Won-Ju

2012-01-01

The effects of annealing temperatures and high-k gate dielectric materials on the amorphous In-Ga-Zn-O thin-film transistors (a-IGZO TFTs) were investigated using pseudo-metal-oxide semiconductor transistors (Ψ-MOSFETs), a method without conventional source/drain (S/D) layer deposition. Annealing of the a-IGZO film was carried out at 150 - 900 .deg. C in a N 2 ambient for 30 min. As the annealing temperature was increased, the electrical characteristics of Ψ-MOSFETs on a-IGZO were drastically improved. However, when the annealing temperature exceeded 700 .deg. C, a deterioration of the MOS parameters was observed, including a shift of the threshold voltage (V th ) in a negative direction, an increase in the subthreshold slope (SS) and hysteresis, a decrease in the field effect mobility (μ FE ), an increase in the trap density (N t ), and a decrease in the on/off ratio. Meanwhile, the high-k gate dielectrics enhanced the performance of a-IGZO Ψ-MOSFETs. The ZrO 2 gate dielectrics particularly exhibited excellent characteristics in terms of SS (128 mV/dec), μ FE (10.2 cm -2 /V·s), N t (1.1 x 10 12 cm -2 ), and on/off ratio (5.3 x 10 6 ). Accordingly, the Ψ-MOSFET structure is a useful method for rapid evaluation of the effects of the process and the material on a-IGZO TFTs without a conventional S/D layer deposition.

Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology

International Nuclear Information System (INIS)

Weng, W.T.; Lin, H.C.; Huang, T.Y.; Lee, Y.J.; Lin, H.C.

2009-01-01

This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO 2 /poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

Interfacial Cation-Defect Charge Dipoles in Stacked TiO2/Al2O3 Gate Dielectrics.

Science.gov (United States)

Zhang, Liangliang; Janotti, Anderson; Meng, Andrew C; Tang, Kechao; Van de Walle, Chris G; McIntyre, Paul C

2018-02-14

Layered atomic-layer-deposited and forming-gas-annealed TiO 2 /Al 2 O 3 dielectric stacks, with the Al 2 O 3 layer interposed between the TiO 2 and a p-type germanium substrate, are found to exhibit a significant interface charge dipole that causes a ∼-0.2 V shift of the flat-band voltage and suppresses the leakage current density for gate injection of electrons. These effects can be eliminated by the formation of a trilayer dielectric stack, consistent with the cancellation of one TiO 2 /Al 2 O 3 interface dipole by the addition of another dipole of opposite sign. Density functional theory calculations indicate that the observed interface-dependent properties of TiO 2 /Al 2 O 3 dielectric stacks are consistent in sign and magnitude with the predicted behavior of Al Ti and Ti Al point-defect dipoles produced by local intermixing of the Al 2 O 3 /TiO 2 layers across the interface. Evidence for such intermixing is found in both electrical and physical characterization of the gate stacks.

Cellulose triacetate, thin film dielectric capacitor

Science.gov (United States)

Yen, Shiao-Ping S. (Inventor); Jow, T. Richard (Inventor)

1995-01-01

Very thin films of cellulose triacetate are cast from a solution containing a small amount of high boiling temperature, non-solvent which evaporates last and lifts the film from the casting surface. Stretched, oriented, crystallized films have high electrical breakdown properties. Metallized films less than about 2 microns in thickness form self-healing electrodes for high energy density, pulsed power capacitors. Thicker films can be utilized as a dielectric for a capacitor.

Thin film silicon on silicon nitride for radiation hardened dielectrically isolated MISFET's

International Nuclear Information System (INIS)

Neamen, D.; Shedd, W.; Buchanan, B.

1975-01-01

The permanent ionizing radiation effects resulting from charge trapping in a silicon nitride isolation dielectric have been determined for a total ionizing dose up to 10 7 rads (Si). Junction FET's, whose active channel region is directly adjacent to the silicon-silicon nitride interface, were used to measure the effects of the radiation induced charge trapping in the Si 3 N 4 isolation dielectric. The JFET saturation current and channel conductance versus junction gate voltage and substrate voltage were characterized as a function of the total ionizing radiation dose. The experimental results on the Si 3 N 4 are compared to results on similar devices with SiO 2 dielectric isolation. The ramifications of using the silicon nitride for fabricating radiation hardened dielectrically isolated MIS devices are discussed

Processing and performance of organic insulators as a gate layer in ...

Indian Academy of Sciences (India)

Abstract. Fabrication of organic thin film transistor (OTFT) on flexible substrates is a challenge, because of its low softening temperature, high roughness and flexible nature. Although several organic dielectrics have been used as gate insulator, it is difficult to choose one in absence of a comparative study covering ...

High Stability Pentacene Transistors Using Polymeric Dielectric Surface Modifier.

Science.gov (United States)

Wang, Xiaohong; Lin, Guangqing; Li, Peng; Lv, Guoqiang; Qiu, Longzhen; Ding, Yunsheng

2015-08-01

1,6-bis(trichlorosilyl)hexane (C6Cl), polystyrene (PS), and cross-linked polystyrene (CPS) were investigated as gate dielectric modified layers for high performance organic transistors. The influence of the surface energy, roughness and morphology on the charge transport of the organic thin-film transistors (OTFTs) was investigated. The surface energy and roughness both affect the grain size of the pentacene films which will control the charge carrier mobility of the devices. Pentacene thin-film transistors fabricated on the CPS modified dielectric layers exhibited charge carrier mobility as high as 1.11 cm2 V-1 s-1. The bias stress stability for the CPS devices shows that the drain current only decays 1% after 1530 s and the mobility never decreases until 13530 s.

Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

Science.gov (United States)

Choi, Woo Young; Lee, Hyun Kook

2016-01-01

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

Direct Effect of Dielectric Surface Energy on Carrier Transport in Organic Field-Effect Transistors.

Science.gov (United States)

Zhou, Shujun; Tang, Qingxin; Tian, Hongkun; Zhao, Xiaoli; Tong, Yanhong; Barlow, Stephen; Marder, Seth R; Liu, Yichun

2018-05-09

The understanding of the characteristics of gate dielectric that leads to optimized carrier transport remains controversial, and the conventional studies applied organic semiconductor thin films, which introduces the effect of dielectric on the growth of the deposited semiconductor thin films and hence only can explore the indirect effects. Here, we introduce pregrown organic single crystals to eliminate the indirect effect (semiconductor growth) in the conventional studies and to undertake an investigation of the direct effect of dielectric on carrier transport. It is shown that the matching of the polar and dispersive components of surface energy between semiconductor and dielectric is favorable for higher mobility. This new empirical finding may show the direct relationship between dielectric and carrier transport for the optimized mobility of organic field-effect transistors and hence show a promising potential for the development of next-generation high-performance organic electronic devices.

Processing and performance of organic insulators as a gate layer in ...

Indian Academy of Sciences (India)

Fabrication of organic thin film transistor (OTFT) on flexible substrates is a challenge, because of its low softening temperature, high roughness and flexible nature. Although several organic dielectrics have been used as gate insulator, it is difficult to choose one in absence of a comparative study covering processing of ...

Demonstration of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with silicon-oxy-nitride as the gate insulator

International Nuclear Information System (INIS)

Balachander, K.; Arulkumaran, S.; Egawa, T.; Sano, Y.; Baskar, K.

2005-01-01

AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs) were fabricated with plasma enhanced chemical vapor deposited silicon oxy-nitride (SiON) as an insulating layer. The compositions of SiON thin films were confirmed using X-ray photoelectron spectroscopy. The fabricated MOSHEMTs exhibited a very high saturation current density of 1.1 A/mm coupled with high positive operational gate voltage up to +7 V. The MOSHEMTs also exhibited four orders of low gate leakage current and high forward-on voltage when compared with the conventional HEMTs. The drain current collapse using gate pulse measurements showed only a negligible difference in the saturation current density revealing the drastic improvement in passivation of the surface states due to the high quality of dielectric thin films deposited. Thus, based on the improved direct-current operation, SiON can be considered to be a potential gate oxide comparable with other dielectric insulators

Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance

Science.gov (United States)

Yadav, Dharmendra Singh; Verma, Abhishek; Sharma, Dheeraj; Tirkey, Sukeshni; Raad, Bhagwan Ram

2017-11-01

Tunnel-field-effect-transistor (TFET) has emerged as one of the most prominent devices to replace conventional MOSFET due to its ability to provide sub-threshold slope below 60 mV/decade (SS ≤ 60 mV/decade) and low leakage current. Despite this, TFETs suffer from ambipolar behavior, lower ON-state current, and poor RF performance. To address these issues, we have introduced drain and gate work function engineering with hetero gate dielectric for the first time in charge plasma based doping-less TFET (DL TFET). In this, the usage of dual work functionality over the drain region significantly reduces the ambipolar behavior of the device by varying the energy barrier at drain/channel interface. Whereas, the presence of dual work function at the gate terminal increases the ON-state current (ION). The combined effect of dual work function at the gate and drain electrode results in the increment of ON-state current (ION) and decrement of ambipolar conduction (Iambi) respectively. Furthermore, the incorporation of hetero gate dielectric along with dual work functionality at the drain and gate electrode provides an overall improvement in the performance of the device in terms of reduction in ambipolarity, threshold voltage and sub-threshold slope along with improved ON-state current and high frequency figures of merit.

Study of the tunnelling initiated leakage current through the carbon nanotube embedded gate oxide in metal oxide semiconductor structures

International Nuclear Information System (INIS)

Chakraborty, Gargi; Sarkar, C K; Lu, X B; Dai, J Y

2008-01-01

The tunnelling currents through the gate dielectric partly embedded with semiconducting single-wall carbon nanotubes in a silicon metal-oxide-semiconductor (MOS) structure have been investigated. The application of the gate voltage to such an MOS device results in the band bending at the interface of the partly embedded oxide dielectric and the surface of the silicon, initiating tunnelling through the gate oxide responsible for the gate leakage current whenever the thickness of the oxide is scaled. A model for silicon MOS structures, where carbon nanotubes are confined in a narrow layer embedded in the gate dielectric, is proposed to investigate the direct and the Fowler-Nordheim (FN) tunnelling currents of such systems. The idea of embedding such elements in the gate oxide is to assess the possibility for charge storage for memory device applications. Comparing the FN tunnelling onset voltage between the pure gate oxide and the gate oxide embedded with carbon nanotubes, it is found that the onset voltage decreases with the introduction of the nanotubes. The direct tunnelling current has also been studied at very low gate bias, for the thin oxide MOS structure which plays an important role in scaling down the MOS transistors. The FN tunnelling current has also been studied with varying nanotube diameter

Effect of incorporation of nitrogen atoms in Al2O3 gate dielectric of wide-bandgap-semiconductor MOSFET on gate leakage current and negative fixed charge

Science.gov (United States)

Kojima, Eiji; Chokawa, Kenta; Shirakawa, Hiroki; Araidai, Masaaki; Hosoi, Takuji; Watanabe, Heiji; Shiraishi, Kenji

2018-06-01

We performed first-principle calculations to investigate the effect of incorporation of N atoms into Al2O3 gate dielectrics. Our calculations show that the defect levels generated by VO in Al2O3 are the origin of the stress-induced gate leakage current and that VOVAl complexes in Al2O3 cause negative fixed charge. We revealed that the incorporation of N atoms into Al2O3 eliminates the VO defect levels, reducing the stress-induced gate leakage current. Moreover, this suppresses the formation of negatively charged VOVAl complexes. Therefore, AlON can reduce both stress-induced gate leakage current and negative fixed charge in wide-bandgap-semiconductor MOSFETs.

Functional Design of Dielectric-Metal-Dielectric-Based Thin-Film Encapsulation with Heat Transfer and Flexibility for Flexible Displays.

Science.gov (United States)

Kwon, Jeong Hyun; Choi, Seungyeop; Jeon, Yongmin; Kim, Hyuncheol; Chang, Ki Soo; Choi, Kyung Cheol

2017-08-16

In this study, a new and efficient dielectric-metal-dielectric-based thin-film encapsulation (DMD-TFE) with an inserted Ag thin film is proposed to guarantee the reliability of flexible displays by improving the barrier properties, mechanical flexibility, and heat dissipation, which are considered to be essential requirements for organic light-emitting diode (OLED) encapsulation. The DMD-TFE, which is composed of Al 2 O 3 , Ag, and a silica nanoparticle-embedded sol-gel hybrid nanocomposite, shows a water vapor transmission rate of 8.70 × 10 -6 g/m 2 /day and good mechanical reliability at a bending radius of 30 mm, corresponding to 0.41% strain for 1000 bending cycles. The electrical performance of a thin-film encapsulated phosphorescent organic light-emitting diode (PHOLED) was identical to that of a glass-lid encapsulated PHOLED. The operational lifetimes of the thin-film encapsulated and glass-lid encapsulated PHOLEDs are 832 and 754 h, respectively. After 80 days, the thin-film encapsulated PHOLED did not show performance degradation or dark spots on the cell image in a shelf-lifetime test. Finally, the difference in lifetime of the OLED devices in relation to the presence and thickness of a Ag film was analyzed by applying various TFE structures to fluorescent organic light-emitting diodes (FOLEDs) that could generate high amounts of heat. To demonstrate the difference in heat dissipation effect among the TFE structures, the saturated temperatures of the encapsulated FOLEDs were measured from the back side surface of the glass substrate, and were found to be 67.78, 65.12, 60.44, and 39.67 °C after all encapsulated FOLEDs were operated at an initial luminance of 10 000 cd/m 2 for sufficient heat generation. Furthermore, the operational lifetime tests of the encapsulated FOLED devices showed results that were consistent with the measurements of real-time temperature profiles taken with an infrared camera. A multifunctional hybrid thin-film encapsulation

Poly(4-vinylphenol-co-methyl methacrylate) / titanium dioxide nanocomposite gate insulators for 6,13-bis(triisopropylsilylethynyl)-pentacene thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Zhang, Xue; Park, Jiho; Baang, Sungkeun; Park, Jaehoon [Hallym University, Chuncheon (Korea, Republic of); Piao, Shanghao; Kim, Sohee; Choi, Hyoungjin [Inha University, Incheon (Korea, Republic of)

2014-12-15

Poly(4-vinylphenol-co-methyl methacrylate) / titanium dioxide (TiO{sub 2}) nanocomposite insulators were fabricated for application in 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-Pn) thin-film transistors (TFTs). The capacitance of the fabricated capacitors with this nanocomposite insulator increased with increasing content of the high-dielectric-constant TiO{sub 2} nanoparticles. Nonetheless, particle aggregates, which were invariably produced in the insulator at higher TiO{sub 2} contents, augmented gate-leakage currents during device operation while the rough surface of the insulator obstructed charge transport in the conducting channel of the TIPS-Pn TFTs. These results suggest a significant effect of the morphological characteristics of nanocomposite insulators on TFT performance, as well as on their dielectric properties. Herein, the optimal particle composition was determined to be approximately 1.5 wt%, which contributed to characteristic improvements in the drain current, field-effect mobility, and threshold voltage of TIPS-Pn TFTs.

Effect of crystal structure on strontium titanate thin films and their dielectric properties

Science.gov (United States)

Kampangkeaw, Satreerat

Strontium titanate (SrTiO3 or STO) has application in radio and microwave-frequency tunable capacitor devices particularly at low temperatures due to its high dielectric constant, low loss and the electric field tunability of its dielectric constant. The main goal of improving the performance in these devices is to increase the tunability and decrease the dielectric loss at the same time, especially at microwave frequencies. Thin films of STO however, show dramatic differences compared to the bulk. The dielectric constant of bulk STO increases nonlinearly from 300 at room temperature to 30000 at 4 K and the loss range is 10-3--10 -4. On the other hand. STO thin films, while showing a dielectric constant close to 300 at room temperature, typically reach a maximum between 1000 and 10000 in the 30 K to 100 K range before decreasing, and the high-loss range is 10-2--10-3. We have grown strontium titanate thin films using a pulsed laser deposition technique on substrates selected to have a small lattice mismatch between the film and substrate. Neodymium gallate (NdGaO3 or NGO) and lanthanum aluminate (LaAlO3 or LAO) substrates were good candidates due to only 1--2% mismatching. Film capacitor devices were fabricated with 25 micron gap separation. 1.5 mm total gap length and an overall 1 x 2 mm dimension using standard lithography and gold metal evaporative techniques. Their nonlinear dielectric constant and loss tangent were measured at low frequencies and also at 2 GHz, and from room temperature down to 4 K. The resulting films show significant variations of dielectric properties with position on the substrates with respect to the deposition plume axis. In the presence of DC electric fields up to +/-4 V/mum, STO films show improved dielectric tunability and low loss in regions far from the plume axis. We found that the films grown on NCO have lower dielectric loss than those on LAO due to a closer match of the NCO lattice to that of STO. We investigated the possible

Graphene/Pentacene Barristor with Ion-Gel Gate Dielectric: Flexible Ambipolar Transistor with High Mobility and On/Off Ratio.

Science.gov (United States)

Oh, Gwangtaek; Kim, Jin-Soo; Jeon, Ji Hoon; Won, EunA; Son, Jong Wan; Lee, Duk Hyun; Kim, Cheol Kyeom; Jang, Jingon; Lee, Takhee; Park, Bae Ho

2015-07-28

High-quality channel layer is required for next-generation flexible electronic devices. Graphene is a good candidate due to its high carrier mobility and unique ambipolar transport characteristics but typically shows a low on/off ratio caused by gapless band structure. Popularly investigated organic semiconductors, such as pentacene, suffer from poor carrier mobility. Here, we propose a graphene/pentacene channel layer with high-k ion-gel gate dielectric. The graphene/pentacene device shows both high on/off ratio and carrier mobility as well as excellent mechanical flexibility. Most importantly, it reveals ambipolar behaviors and related negative differential resistance, which are controlled by external bias. Therefore, our graphene/pentacene barristor with ion-gel gate dielectric can offer various flexible device applications with high performances.

Analyzing nitrogen concentration using carrier illumination (CI) technology for DPN ultra-thin gate oxide

International Nuclear Information System (INIS)

Li, W.S.; Wu, Bill; Fan, Aki; Kuo, C.W.; Segovia, M.; Kek, H.A.

2005-01-01

Nitrogen concentration in the gate oxide plays a key role for 90 nm and below ULSI technology. Techniques like secondary ionization mass spectroscopy (SIMS) and X-ray photoelectron spectroscopy (XPS) are commonly used for understanding N concentration. This paper describes the application of the carrier illuminationTM (CI) technique to measure the nitrogen concentration in ultra-thin gate oxides. A set of ultra-thin gate oxide wafers with different DPN (decoupled plasma nitridation) treatment conditions were measured using the CI technique. The CI signal has excellent correlation with the N concentration as measured by XPS

Electroresistance effect in gold thin film induced by ionic-liquid-gated electric double layer

International Nuclear Information System (INIS)

Nakayama, Hiroyasu; Ohtani, Takashi; Fujikawa, Yasunori; Ando, Kazuya; Saitoh, Eiji; Ye, Jianting; Iwasa, Yoshihiro

2012-01-01

Electroresistance effect was detected in a metallic thin film using ionic-liquid-gated electric-double-layer transistors (EDLTs). We observed reversible modulation of the electric resistance of a Au thin film. In this system, we found that an electric double layer works as a nanogap capacitor with 27 (-25) MV cm -1 of electric field by applying only 1.7 V of positive (negative) gate voltage. The experimental results indicate that the ionic-liquid-gated EDLT technique can be used for controlling the surface electronic states on metallic systems. (author)

Low dielectric constant-based organic field-effect transistors and metal-insulator-semiconductor capacitors

Science.gov (United States)

Ukah, Ndubuisi Benjamin

This thesis describes a study of PFB and pentacene-based organic field-effect transistors (OFET) and metal-insulator-semiconductor (MIS) capacitors with low dielectric constant (k) poly(methyl methacrylate) (PMMA), poly(4-vinyl phenol) (PVP) and cross-linked PVP (c-PVP) gate dielectrics. A physical method -- matrix assisted pulsed laser evaporation (MAPLE) -- of fabricating all-polymer field-effect transistors and MIS capacitors that circumvents inherent polymer dissolution and solvent-selectivity problems, is demonstrated. Pentacene-based OFETs incorporating PMMA and PVP gate dielectrics usually have high operating voltages related to the thickness of the dielectric layer. Reduced PMMA layer thickness (≤ 70 nm) was obtained by dissolving the PMMA in propylene carbonate (PC). The resulting pentacene-based transistors exhibited very low operating voltage (below -3 V), minimal hysteresis in their transfer characteristics, and decent electrical performance. Also low voltage (within -2 V) operation using thin (≤ 80 nm) low-k and hydrophilic PVP and c-PVP dielectric layers obtained via dissolution in high dipole moment and high-k solvents -- PC and dimethyl sulfoxide (DMSO), is demonstrated to be a robust means of achieving improved electrical characteristics and high operational stability in OFETs incorporating PVP and c-PVP dielectrics.

Dielectric property study of poly(4-vinylphenol)-graphene oxide nanocomposite thin film

Science.gov (United States)

Roy, Dhrubojyoti

2018-05-01

Thin film capacitor device having a sandwich structure of indium tin oxide (ITO)-coated glass/polymer or polymer nanocomposite /silver has been fabricated and their dielectric and leakage current properties has been studied. The dielectric properties of the capacitors were characterized for frequencies ranging from 1 KHz to 1 MHz. 5 wt% Poly(4-vinylphenol)(PVPh)-Graphene (GO) nanocomposite exhibited an increase in dielectric constant to 5.6 and small rise in dielectric loss to around˜0.05 at 10 KHz w.r.t polymer. The DC conductivity measurements reveal rise of leakage current in nanocomposite.

Total Ionizing Dose Effects of Si Vertical Diffused MOSFET with SiO2 and Si3N4/SiO2 Gate Dielectrics

Directory of Open Access Journals (Sweden)

Jiongjiong Mo

2017-01-01

Full Text Available The total ionizing dose irradiation effects are investigated in Si vertical diffused MOSFETs (VDMOSs with different gate dielectrics including single SiO2 layer and double Si3N4/SiO2 layer. Radiation-induced holes trapping is greater for single SiO2 layer than for double Si3N4/SiO2 layer. Dielectric oxidation temperature dependent TID effects are also studied. Holes trapping induced negative threshold voltage shift is smaller for SiO2 at lower oxidation temperature. Gate bias during irradiation leads to different VTH shift for different gate dielectrics. Single SiO2 layer shows the worst negative VTH at VG=0 V, while double Si3N4/SiO2 shows negative VTH shift at VG=-5 V, positive VTH shift at VG=10 V, and negligible VTH shift at VG=0 V.

Perovskite oxynitride LaTiOxNy thin films: Dielectric characterization in low and high frequencies

International Nuclear Information System (INIS)

Lu, Y.; Ziani, A.; Le Paven-Thivet, C.; Benzerga, R.; Le Gendre, L.; Fasquelle, D.; Kassem, H.

2011-01-01

Lanthanum titanium oxynitride (LaTiO x N y ) thin films are studied with respect to their dielectric properties in low and high frequencies. Thin films are deposited by radio frequency magnetron sputtering on different substrates. Effects of nitrogen content and crystalline quality on dielectric properties are investigated. In low-frequency range, textured LaTiO x N y thin films deposited on conductive single crystal Nb–STO show a dielectric constant ε′ ≈ 140 with low losses tanδ = 0.012 at 100 kHz. For the LaTiO x N y polycrystalline films deposited on conductive silicon substrates with platinum (Pt/Ti/SiO 2 /Si), the tunability reached up to 57% for a weak electric field of 50 kV/cm. In high-frequency range, epitaxial LaTiO x N y films deposited on MgO substrate present a high dielectric constant with low losses (ε′ ≈ 170, tanδ = 0.011, 12 GHz).

Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11 000 cm2/V·s

KAUST Repository

Smith, Casey; Qaisi, Ramy M.; Liu, Zhihong; Yu, Qingkai; Hussain, Muhammad Mustafa

2013-01-01

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11 000 cm 2/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low t ox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance. © 2013 American Chemical Society.

Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11 000 cm2/V·s

KAUST Repository

Smith, Casey

2013-07-23

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11 000 cm 2/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low t ox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance. © 2013 American Chemical Society.

Nonlinear dielectric thin films for high-power electric storage with energy density comparable with electrochemical supercapacitors.

Science.gov (United States)

Yao, Kui; Chen, Shuting; Rahimabady, Mojtaba; Mirshekarloo, Meysam Sharifzadeh; Yu, Shuhui; Tay, Francis Eng Hock; Sritharan, Thirumany; Lu, Li

2011-09-01

Although batteries possess high energy storage density, their output power is limited by the slow movement of charge carriers, and thus capacitors are often required to deliver high power output. Dielectric capacitors have high power density with fast discharge rate, but their energy density is typically much lower than electrochemical supercapacitors. Increasing the energy density of dielectric materials is highly desired to extend their applications in many emerging power system applications. In this paper, we review the mechanisms and major characteristics of electric energy storage with electrochemical supercapacitors and dielectric capacitors. Three types of in-house-produced ferroic nonlinear dielectric thin film materials with high energy density are described, including (Pb(0.97)La(0.02))(Zr(0.90)Sn(0.05)Ti(0.05))O(3) (PLZST) antiferroelectric ceramic thin films, Pb(Zn(1/3)Nb(2/3))O(3-)Pb(Mg(1/3)Nb(2/3))O(3-)PbTiO(3) (PZN-PMN-PT) relaxor ferroelectric ceramic thin films, and poly(vinylidene fluoride) (PVDF)-based polymer blend thin films. The results showed that these thin film materials are promising for electric storage with outstandingly high power density and fairly high energy density, comparable with electrochemical supercapacitors.

Effect of titanium oxide-polystyrene nanocomposite dielectrics on morphology and thin film transistor performance for organic and polymeric semiconductors

Energy Technology Data Exchange (ETDEWEB)

Della Pelle, Andrea M. [LGS Innovations, 15 Vreeland Rd., Florham Park, NJ 07932 (United States); Department of Chemistry, University of Massachusetts Amherst, 710 N. Pleasant St. Amherst, MA 01003 (United States); Maliakal, Ashok, E-mail: maliakal@lgsinnovations.com [LGS Innovations, 15 Vreeland Rd., Florham Park, NJ 07932 (United States); Sidorenko, Alexander [Department of Chemistry and Biochemistry, University of the Sciences, 600 South 43rd St., Philadelphia, PA 191034 (United States); Thayumanavan, S. [Department of Chemistry, University of Massachusetts Amherst, 710 N. Pleasant St. Amherst, MA 01003 (United States)

2012-07-31

Previous studies have shown that organic thin film transistors with pentacene deposited on gate dielectrics composed of a blend of high K titanium oxide-polystyrene core-shell nanocomposite (TiO{sub 2}-PS) with polystyrene (PS) perform with an order of magnitude increase in saturation mobility for TiO{sub 2}-PS (K = 8) as compared to PS devices (K = 2.5). The current study finds that this performance enhancement can be translated to alternative small single crystal organics such as {alpha}-sexithiophene ({alpha}-6T) (enhancement factor for field effect mobility ranging from 30-100 Multiplication-Sign higher on TiO{sub 2}-PS/PS blended dielectrics as compared to homogenous PS dielectrics). Interestingly however, in the case of semicrystalline polymers such as (poly-3-hexylthiophene) P3HT, this dramatic enhancement is not observed, possibly due to the difference in processing conditions used to fabricate these devices (film transfer as opposed to thermal evaporation). The morphology for {alpha}-sexithiophene ({alpha}-6T) grown by thermal evaporation on TiO{sub 2}-PS/PS blended dielectrics parallels that observed in pentacene devices. Smaller grain size is observed for films grown on dielectrics with higher TiO{sub 2}-PS content. In the case of poly(3-hexylthiophene) (P3HT) devices, constructed via film transfer, morphological differences exist for the P3HT on different substrates, as discerned by atomic force microscopy studies. However, these devices only exhibit a modest (2 Multiplication-Sign ) increase in mobility with increasing TiO{sub 2}-PS content in the films. After annealing of the transferred P3HT thin film transistor (TFT) devices, no appreciable enhancement in mobility is observed across the different blended dielectrics. Overall the results support the hypothesis that nucleation rate is responsible for changes in film morphology and device performance in thermally evaporated small molecule crystalline organic semiconductor TFTs. The increased nucleation

Effect of titanium oxide–polystyrene nanocomposite dielectrics on morphology and thin film transistor performance for organic and polymeric semiconductors

International Nuclear Information System (INIS)

Della Pelle, Andrea M.; Maliakal, Ashok; Sidorenko, Alexander; Thayumanavan, S.

2012-01-01

Previous studies have shown that organic thin film transistors with pentacene deposited on gate dielectrics composed of a blend of high K titanium oxide–polystyrene core–shell nanocomposite (TiO 2 –PS) with polystyrene (PS) perform with an order of magnitude increase in saturation mobility for TiO 2 –PS (K = 8) as compared to PS devices (K = 2.5). The current study finds that this performance enhancement can be translated to alternative small single crystal organics such as α-sexithiophene (α-6T) (enhancement factor for field effect mobility ranging from 30-100× higher on TiO 2 –PS/PS blended dielectrics as compared to homogenous PS dielectrics). Interestingly however, in the case of semicrystalline polymers such as (poly-3-hexylthiophene) P3HT, this dramatic enhancement is not observed, possibly due to the difference in processing conditions used to fabricate these devices (film transfer as opposed to thermal evaporation). The morphology for α-sexithiophene (α-6T) grown by thermal evaporation on TiO 2 –PS/PS blended dielectrics parallels that observed in pentacene devices. Smaller grain size is observed for films grown on dielectrics with higher TiO 2 –PS content. In the case of poly(3-hexylthiophene) (P3HT) devices, constructed via film transfer, morphological differences exist for the P3HT on different substrates, as discerned by atomic force microscopy studies. However, these devices only exhibit a modest (2×) increase in mobility with increasing TiO 2 –PS content in the films. After annealing of the transferred P3HT thin film transistor (TFT) devices, no appreciable enhancement in mobility is observed across the different blended dielectrics. Overall the results support the hypothesis that nucleation rate is responsible for changes in film morphology and device performance in thermally evaporated small molecule crystalline organic semiconductor TFTs. The increased nucleation rate produces organic polycrystalline films with small grain

Materials science, integration, and performance characterization of high-dielectric constant thin film based devices

Science.gov (United States)

Fan, Wei

To overcome the oxidation and diffusion problems encountered during Copper integration with oxide thin film-based devices, TiAl/Cu/Ta heterostructure has been first developed in this study. Investigation on the oxidation and diffusion resistance of the laminate structure showed high electrical conductance and excellent thermal stability in oxygen environment. Two amorphous oxide layers that were formed on both sides of the TiAl barrier after heating in oxygen have been revealed as the structure that effectively prevents oxygen penetration and protects the integrity of underlying Cu layer. Polycrystalline (BaxSr1-x)TiO3 (BST) thin films were subsequently deposited on the Cu-based bottom electrode by RF magnetron sputtering to investigate the interaction between the oxide and Cu layers. The thickness of the interfacial layer and interface roughness play critical roles in the optimization of the electrical performance of the BST capacitors using Cu-based electrode. It was determined that BST deposition at moderate temperature followed by rapid thermal annealing in pure oxygen yields BST/Cu capacitors with good electrical properties for application to high frequency devices. The knowledge obtained on the study of barrier properties of TiAl inspired a continuous research on the materials science issues related to the application of the hybrid TiAlOx, as high-k gate dielectric in MOSFET devices. Novel fabrication process such as deposition of ultra-thin TiAl alloy layer followed by oxidation with atomic oxygen has been established in this study. Stoichiometric amorphous TiAlOx layers, exhibiting only Ti4+ and Al3+ states, were produced with a large variation of oxidation temperature (700°C to room temperature). The interfacial SiOx formation between TiAlOx and Si was substantially inhibited by the use of the low temperature oxidation process. Electrical characterization revealed a large permittivity of 30 and an improved band structure for the produced TiAlOx layers

Stimulated Raman gain scattering in thin planar dielectric waveguides

NARCIS (Netherlands)

Kanger, Johannes S.; Otto, Cornelis; Greve, Jan

1995-01-01

The stimulated Raman gain effect in planar dielectric waveguides is analyzed for the study of thin layers. Calculations show high gain factors and predict the possibility of detecting monolayers. Compared with those for methods based on ref lection, the gain can be 4 orders of magnitude higher for a

Long-Term Synaptic Plasticity Emulated in Modified Graphene Oxide Electrolyte Gated IZO-Based Thin-Film Transistors.

Science.gov (United States)

Yang, Yi; Wen, Juan; Guo, Liqiang; Wan, Xiang; Du, Peifu; Feng, Ping; Shi, Yi; Wan, Qing

2016-11-09

Emulating neural behaviors at the synaptic level is of great significance for building neuromorphic computational systems and realizing artificial intelligence. Here, oxide-based electric double-layer (EDL) thin-film transistors were fabricated using 3-triethoxysilylpropylamine modified graphene oxide (KH550-GO) electrolyte as the gate dielectrics. Resulting from the EDL effect and electrochemical doping between mobile protons and the indium-zinc-oxide channel layer, long-term synaptic plasticity was emulated in our devices. Synaptic functions including long-term memory, synaptic temporal integration, and dynamic filters were successfully reproduced. In particular, spike rate-dependent plasticity (SRDP), one of the basic learning rules of long-term plasticity in the neural network where the synaptic weight changes according to the rate of presynaptic spikes, was emulated in our devices. Our results may facilitate the development of neuromorphic computational systems.

The memory effect of a pentacene field-effect transistor with a polarizable gate dielectric

Science.gov (United States)

Unni, K. N. N.; de Bettignies, Remi; Dabos-Seignon, Sylvie; Nunzi, Jean-Michel

2004-06-01

The nonvolatile transistor memory element is an interesting topic in organic electronics. In this case a memory cell consists of only one device where the stored information is written as a gate insulator polarization by a gate voltage pulse and read by the channel conductance control with channel voltage pulse without destruction of the stored information. Therefore such transistor could be the base of non-volatile non-destructively readable computer memory of extremely high density. Also devices with polarizable gate dielectrics can function more effectively in certain circuits. The effective threshold voltage Vt can be brought very close to zero, for applications where the available gate voltage is limited. Resonant and adaptive circuits can be tuned insitu by polarizing the gates. Poly(vinylidene fluoride), PVDF and its copolymer with trifluoroethylene P(VDF-TrFE) are among the best known and most widely used ferroelectric polymers. In this manuscript, we report new results of an organic FET, fabricated with pentacene as the active material and P(VDF-TrFE) as the gate insulator. Application of a writing voltage of -50 V for short duration results in significant change in the threshold voltage and remarkable increase in the drain current. The memory effect is retained over a period of 20 hours.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

Science.gov (United States)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

Structural, dielectric and AC conductivity study of Sb2O3 thin film ...

Indian Academy of Sciences (India)

52

However, to date, no reports have appeared on impedance spectroscopy, modulus behavior, electrical conductivity, dielectric relaxation and dielectric properties of crystalline Sb2O3 thin films. This paper deals for the first time with the frequency and temperature dependence of AC conductivity and complex electric modulus ...

AlN and Al oxy-nitride gate dielectrics for reliable gate stacks on Ge and InGaAs channels

Energy Technology Data Exchange (ETDEWEB)

Guo, Y.; Li, H.; Robertson, J. [Engineering Department, Cambridge University, Cambridge CB2 1PZ (United Kingdom)

2016-05-28

AlN and Al oxy-nitride dielectric layers are proposed instead of Al{sub 2}O{sub 3} as a component of the gate dielectric stacks on higher mobility channels in metal oxide field effect transistors to improve their positive bias stress instability reliability. It is calculated that the gap states of nitrogen vacancies in AlN lie further away in energy from the semiconductor band gap than those of oxygen vacancies in Al{sub 2}O{sub 3}, and thus AlN might be less susceptible to charge trapping and have a better reliability performance. The unfavourable defect energy level distribution in amorphous Al{sub 2}O{sub 3} is attributed to its larger coordination disorder compared to the more symmetrically bonded AlN. Al oxy-nitride is also predicted to have less tendency for charge trapping.

Characteristics of dual-gate thin-film transistors for applications in digital radiology

International Nuclear Information System (INIS)

Waechter, D.; Huang, Z.; Zhao, W.; Blevis, I.; Rowlands, J.A.

1996-01-01

A large-area flat-panel detector for digital radiology is being developed. The detector uses an array of dual-gate thin-film transistors (TFTs) to read out X-ray-generated charge produced in an amorphous selenium (a-Se) layer. The TFTs use CdSe as the semiconductor and use the bottom gate for row selection. The top gate can be divided into a 'deliberate' gate, covering most of the channel length, and small 'parasitic' gates that consist of: overlap of source or drain metal over the top-gate oxide; and gap regions in the metal that are covered only by the a-Se. In this paper we present the properties of dual-gate TFTs and examine the effect of both the deliberate and parasitic gates on the detector operation. Various options for controlling the top-gate potential are analyzed and discussed. (author)

Dielectric Modulated FET (DMFET)

Indian Academy of Sciences (India)

First page Back Continue Last page Graphics. Working Principle: Change in Dielectric constant due to immobilization of biomolecules in the nanogap cavity leads to change in effective gate capacitance and thus gate bias for FET. Working Principle: Change in Dielectric constant due to immobilization of biomolecules in the ...

Dielectric response of fully and partially depleted ferroelectric thin films and inversion of the thickness effect

International Nuclear Information System (INIS)

Misirlioglu, I B; Yildiz, M

2013-01-01

We study the effect of full and partial depletion on the dielectric response characteristics of ferroelectric thin films with impurities via a computational approach. Using a thermodynamic approach along with the fundamental equations for semiconductors, we show that films with partial depletion display unique features and an enhanced dielectric response compared with those fully depleted. We find that the capacitance peak at switching can be significantly suppressed in the case of high impurity densities (>10 25 m −3 ) with relatively low ionization energy, of the order of 0.5 eV. For conserved number of species in films, electromigration of ionized impurities at room temperature is negligible and has nearly no effect on the dielectric response. In films with high impurity density, the dielectric response at zero bias is enhanced with respect to charge-free films or those with relatively low impurity density ( 24 m −3 ). We demonstrate that partially depleted films should be expected to exhibit peculiar capacitance–voltage characteristics at low and high bias and that the thickness effect probed in experiments in ferroelectric thin films could be entirely inverted in thin films with depletion charges where a higher dielectric response can be measured in thicker films. Therefore, depletion charge densities in ferroelectric thin films should be estimated before size-effect-related studies. Finally, we noted that these findings are in good qualitative agreement with dielectric measurements carried out on PbZr x Ti 1−x O 3 . (paper)

Influence of Doping Concentration on Dielectric, Optical, and Morphological Properties of PMMA Thin Films

Directory of Open Access Journals (Sweden)

Lyly Nyl Ismail

2012-01-01

Full Text Available PMMA thin films were deposited by sol gel spin coating method on ITO substrates. Toluene was used as the solvent to dissolve the PMMA powder. The PMMA concentration was varied from 30 ~ 120 mg. The dielectric properties were measured at frequency of 0 ~ 100 kHz. The dielectric permittivity was in the range of 7.3 to 7.5 which decreased as the PMMA concentration increased. The dielectric loss is in the range of 0.01 ~ –0.01. All samples show dielectric characteristics which have dielectric loss is less than 0.05. The optical properties for thin films were measured at room temperature across 200 ~ 1000 nm wavelength region. All samples are highly transparent. The energy band gaps are in the range of 3.6 eV to 3.9 eV when the PMMA concentration increased. The morphologies of the samples show that all samples are uniform and the surface roughness increased as the concentration increased. From this study, it is known that, the dielectric, optical, and morphology properties were influenced by the amount of PMMA concentration in the solution.

Ultra-thin Metal and Dielectric Layers for Nanophotonic Applications

DEFF Research Database (Denmark)

Shkondin, Evgeniy; Leandro, Lorenzo; Malureanu, Radu

2015-01-01

In our talk we first give an overview of the various thin films used in the field of nanophotonics. Then we describe our own activity in fabrication and characterization of ultra-thin films of high quality. We particularly focus on uniform gold layers having thicknesses down to 6 nm fabricated by......-beam deposition on dielectric substrates and Al-oxides/Ti-oxides multilayers prepared by atomic layer deposition in high aspect ratio trenches. In the latter case we show more than 1:20 aspect ratio structures can be achieved....

Use of water vapor for suppressing the growth of unstable low-κ interlayer in HfTiO gate-dielectric Ge metal-oxide-semiconductor capacitors with sub-nanometer capacitance equivalent thickness

International Nuclear Information System (INIS)

Xu, J.P.; Zou, X.; Lai, P.T.; Li, C.X.; Chan, C.L.

2009-01-01

Annealing of high-permittivity HfTiO gate dielectric on Ge substrate in different gases (N 2 , NH 3 , NO and N 2 O) with or without water vapor is investigated. Analysis by transmission electron microscopy indicates that the four wet anneals can greatly suppress the growth of a GeO x interlayer at the dielectric/Ge interface, and thus decrease interface states, oxide charges and gate leakage current. Moreover, compared with the wet N 2 anneal, the wet NH 3 , NO and N 2 O anneals decrease the equivalent permittivity of the gate dielectric due to the growth of a GeO x N y interlayer. Among the eight anneals, the wet N 2 anneal produces the best dielectric performance with an equivalent relative permittivity of 35, capacitance equivalent thickness of 0.81 nm, interface-state density of 6.4 x 10 11 eV -1 cm -2 and gate leakage current of 2.7 x 10 -4 A/cm 2 at V g = 1 V

Quantum-dot size and thin-film dielectric constant: precision measurement and disparity with simple models.

Science.gov (United States)

Grinolds, Darcy D W; Brown, Patrick R; Harris, Daniel K; Bulovic, Vladimir; Bawendi, Moungi G

2015-01-14

We study the dielectric constant of lead sulfide quantum dot (QD) films as a function of the volume fraction of QDs by varying the QD size and keeping the ligand constant. We create a reliable QD sizing curve using small-angle X-ray scattering (SAXS), thin-film SAXS to extract a pair-distribution function for QD spacing, and a stacked-capacitor geometry to measure the capacitance of the thin film. Our data support a reduced dielectric constant in nanoparticles.

Adjustable threshold-voltage in all-inkjet-printed organic thin film transistor using double-layer dielectric structures

International Nuclear Information System (INIS)

Wu, Wen-Jong; Lee, Chang-Hung; Hsu, Chun-Hao; Yang, Shih-Hsien; Lin, Chih-Ting

2013-01-01

An all-inkjet-printed organic thin film transistor (OTFT) with a double-layer dielectric structure is proposed and implemented in this study. By using the double-layer structure with different dielectric materials (i.e., polyvinylphenol with poly(vinylidene fluoride-co-hexafluoropropylene)), the threshold-voltage of OTFT can be adjusted. The threshold-voltage shift can be controlled by changing the composition of dielectric layers. That is, an enhancement-mode OTFT can be converted to a depletion-mode OTFT by selectively printing additional dielectric layers to form a high-k/low-k double-layer structure. The printed OTFT has a carrier mobility of 5.0 × 10 −3 cm 2 /V-s. The threshold-voltages of the OTFTs ranged between − 13 V and 10 V. This study demonstrates an additional design parameter for organic electronics manufactured using inkjet printing technology. - Highlights: • A double-layer dielectric organic thin film transistor, OTFT, is implemented. • The threshold voltage of OTFT can be configured by the double dielectric structure. • The composition of the dielectric determines the threshold voltage shift. • The characteristics of OTFTs can be adjusted by double dielectric structures

Top-gate hybrid complementary inverters using pentacene and amorphous InGaZnO thin-film transistors with high operational stability

Directory of Open Access Journals (Sweden)

J. B. Kim

2012-03-01

Full Text Available We report on the operational stability of low-voltage hybrid organic-inorganic complementary inverters with a top-gate bottom source-drain geometry. The inverters are comprised of p-channel pentacene and n-channel amorphous InGaZnO thin-film transistors (TFTs with bi-layer gate dielectrics formed from an amorphous layer of a fluoropolymer (CYTOP and a high-k layer of Al2O3. The p- and n- channel TFTs show saturation mobility values of 0.1 ± 0.01 and 5.0 ± 0.5 cm2/Vs, respectively. The individual transistors show high electrical stability with less than 6% drain-to-source current variations after 1 h direct current (DC bias stress. Complementary inverters yield hysteresis-free voltage transfer characteristics for forward and reverse input biases with static DC gain values larger than 45 V/V at 8 V before and after being subjected to different conditions of electrical stress. Small and reversible variations of the switching threshold voltage of the inverters during these stress tests are compatible with the observed stability of the individual TFTs.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

Science.gov (United States)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-05-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

Science.gov (United States)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-02-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

Dielectric and piezoelectric properties of lead-free (Bi,Na)TiO3-based thin films

Science.gov (United States)

Abazari, M.; Safari, A.; Bharadwaja, S. S. N.; Trolier-McKinstry, S.

2010-02-01

Dielectric and piezoelectric properties of morphotropic phase boundary (Bi,Na)TiO3-(Bi,K)TiO3-BaTiO3 epitaxial thin films deposited on SrRuO3 coated SrTiO3 substrates were reported. Thin films of 350 nm thickness exhibited small signal dielectric permittivity and loss tangent values of 750 and 0.15, respectively, at 1 kHz. Ferroelectric hysteresis measurements indicated a remanent polarization value of 30 μC/cm2 with a coercive field of 85-100 kV/cm. The thin film transverse piezoelectric coefficient (e31,f) of these films after poling at 600 kV/cm was found to be -2.2 C/m2. The results indicate that these BNT-based thin films are a potential candidate for lead-free piezoelectric devices.

Negative differential transconductance in electrolyte-gated ruthenate

International Nuclear Information System (INIS)

Hassan, Muhammad Umair; Dhoot, Anoop Singh; Wimbush, Stuart C.

2015-01-01

We report on a study of electric field-induced doping of the highly conductive ruthenate SrRuO 3 using an ionic liquid as the gate dielectric in a field-effect transistor configuration. Two distinct carrier transport regimes are identified for increasing positive gate voltage in thin (10 nm) films grown heteroepitaxially on SrTiO 3 substrates. For V g  = 2 V and lower, the sample shows an increased conductivity of up to 13%, as might be expected for electron doping of a metal. At higher V g  = 2.5 V, we observe a large decrease in electrical conductivity of >20% (at 4.2 K) due to the prevalence of strongly blocked conduction pathways

Negative differential transconductance in electrolyte-gated ruthenate

Energy Technology Data Exchange (ETDEWEB)

Hassan, Muhammad Umair [Cavendish Laboratory, University of Cambridge, J J Thomson Avenue, Cambridge CB3 0HE (United Kingdom); Center for Micro and Nano Devices, Department of Physics, COMSATS Institute of Information Technology, Park Road, Shehzad Town 44000, Islamabad (Pakistan); Dhoot, Anoop Singh, E-mail: asd24@cam.ac.uk [Cavendish Laboratory, University of Cambridge, J J Thomson Avenue, Cambridge CB3 0HE (United Kingdom); Wimbush, Stuart C. [Department of Materials Science and Metallurgy, University of Cambridge, 27 Charles Babbage Road, Cambridge CB3 0FS (United Kingdom); The MacDiarmid Institute for Advanced Materials and Nanotechnology, Victoria University of Wellington, P.O. Box 600, Wellington 6140 (New Zealand)

2015-01-19

We report on a study of electric field-induced doping of the highly conductive ruthenate SrRuO{sub 3} using an ionic liquid as the gate dielectric in a field-effect transistor configuration. Two distinct carrier transport regimes are identified for increasing positive gate voltage in thin (10 nm) films grown heteroepitaxially on SrTiO{sub 3} substrates. For V{sub g} = 2 V and lower, the sample shows an increased conductivity of up to 13%, as might be expected for electron doping of a metal. At higher V{sub g} = 2.5 V, we observe a large decrease in electrical conductivity of >20% (at 4.2 K) due to the prevalence of strongly blocked conduction pathways.

Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

International Nuclear Information System (INIS)

Han, Jinhua; Wang, Wei; Ying, Jun; Xie, Wenfa

2014-01-01

An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized

Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

Energy Technology Data Exchange (ETDEWEB)

Han, Jinhua; Wang, Wei, E-mail: wwei99@jlu.edu.cn; Ying, Jun; Xie, Wenfa [State Key Laboratory on Integrated Optoelectronics, College of Electronic Science and Engineering, Jilin University, 2699 Qianjin Street, Changchun 130012 (China)

2014-01-06

An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized.

Use of water vapor for suppressing the growth of unstable low-{kappa} interlayer in HfTiO gate-dielectric Ge metal-oxide-semiconductor capacitors with sub-nanometer capacitance equivalent thickness

Energy Technology Data Exchange (ETDEWEB)

Xu, J.P. [Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan, 430074 (China); Zou, X. [School of Electromachine and Architecture Engineering, Jianghan University, Wuhan, 430056 (China); Lai, P.T. [Department of Electrical and Electronic Engineering, University of Hong Kong, Pokfulam Road (Hong Kong)], E-mail: laip@eee.hku.hk; Li, C.X.; Chan, C.L. [Department of Electrical and Electronic Engineering, University of Hong Kong, Pokfulam Road (Hong Kong)

2009-03-02

Annealing of high-permittivity HfTiO gate dielectric on Ge substrate in different gases (N{sub 2}, NH{sub 3}, NO and N{sub 2}O) with or without water vapor is investigated. Analysis by transmission electron microscopy indicates that the four wet anneals can greatly suppress the growth of a GeO{sub x} interlayer at the dielectric/Ge interface, and thus decrease interface states, oxide charges and gate leakage current. Moreover, compared with the wet N{sub 2} anneal, the wet NH{sub 3}, NO and N{sub 2}O anneals decrease the equivalent permittivity of the gate dielectric due to the growth of a GeO{sub x}N{sub y} interlayer. Among the eight anneals, the wet N{sub 2} anneal produces the best dielectric performance with an equivalent relative permittivity of 35, capacitance equivalent thickness of 0.81 nm, interface-state density of 6.4 x 10{sup 11} eV{sup -1} cm{sup -2} and gate leakage current of 2.7 x 10{sup -4} A/cm{sup 2} at V{sub g} = 1 V.

Interfacial nucleation behavior of inkjet-printed 6,13 bis(tri-isopropylsilylethynyl) pentacene on dielectric surfaces

International Nuclear Information System (INIS)

Wang, Xianghua; Lv, Shenchen; Chen, Mengjie; Qiu, Longzhen; Zhang, Guobing; Lu, Hongbo; Yuan, Miao; Qin, Mengzhi

2015-01-01

The performance of organic thin film transistors (OTFTs) is heavily dependent on the interface property between the organic semiconductor and the dielectric substrate. Device fabrication with bottom-gate architecture by depositing the semiconductors with a solution method is highly recommended for cost-effectiveness. Surface modification of the dielectric layer is employed as an effective approach to control film growth. Here, we perform surface modification via a self-assembled monolayer of silanes, a spin-coated polymer layer or UV-ozone cleaning, to prepare surfaces with different surface polarities and morphologies. The semiconductor is inkjet-printed on the surface-treated substrates as single-line films with overlapping drop assignment. Surface morphologies of the dielectric before film deposition and film morphologies of the inkjet-printed semiconductor are characterized with polarized microscopy and AFM. Electrical properties of the films are studied through organic thin-film transistors with bottom-gate/bottom-contact structure. With reduced surface polarity and nanoscale aggregation of silane molecules on the substrates, semiconductor nucleates from the interior interface between the ink solution and the substrate, which contributes to film growth with higher crystal coverage and better film quality at the interface. Surface treatment with hydrophobic silanes is a promising approach to fabrication of high performance OTFTs with nonpolar conjugated molecules via solution methods

Interfacial nucleation behavior of inkjet-printed 6,13 bis(tri-isopropylsilylethynyl) pentacene on dielectric surfaces

Energy Technology Data Exchange (ETDEWEB)

Wang, Xianghua, E-mail: xhwang@hfut.edu.cn; Lv, Shenchen; Chen, Mengjie; Qiu, Longzhen, E-mail: lzhqiu@hfut.edu.cn; Zhang, Guobing; Lu, Hongbo [Key Lab of Special Display Technology, Ministry of Education, National Engineering Lab of Special Display Technology, National Key Lab of Advanced Display Technology, Academy of Opto-Electronic Technology, Hefei University of Technology, Hefei 230009 (China); Yuan, Miao; Qin, Mengzhi [Key Lab of Special Display Technology, Ministry of Education, National Engineering Lab of Special Display Technology, National Key Lab of Advanced Display Technology, Academy of Opto-Electronic Technology, Hefei University of Technology, Hefei 230009 (China); School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei 230009 (China)

2015-01-14

The performance of organic thin film transistors (OTFTs) is heavily dependent on the interface property between the organic semiconductor and the dielectric substrate. Device fabrication with bottom-gate architecture by depositing the semiconductors with a solution method is highly recommended for cost-effectiveness. Surface modification of the dielectric layer is employed as an effective approach to control film growth. Here, we perform surface modification via a self-assembled monolayer of silanes, a spin-coated polymer layer or UV-ozone cleaning, to prepare surfaces with different surface polarities and morphologies. The semiconductor is inkjet-printed on the surface-treated substrates as single-line films with overlapping drop assignment. Surface morphologies of the dielectric before film deposition and film morphologies of the inkjet-printed semiconductor are characterized with polarized microscopy and AFM. Electrical properties of the films are studied through organic thin-film transistors with bottom-gate/bottom-contact structure. With reduced surface polarity and nanoscale aggregation of silane molecules on the substrates, semiconductor nucleates from the interior interface between the ink solution and the substrate, which contributes to film growth with higher crystal coverage and better film quality at the interface. Surface treatment with hydrophobic silanes is a promising approach to fabrication of high performance OTFTs with nonpolar conjugated molecules via solution methods.

Improved organic thin-film transistor performance using novel self-assembled monolayers

Science.gov (United States)

McDowell, M.; Hill, I. G.; McDermott, J. E.; Bernasek, S. L.; Schwartz, J.

2006-02-01

Pentacene-based organic thin-film transistors have been fabricated using a phosphonate-linked anthracene self-assembled monolayer as a buffer between the silicon dioxide gate dielectric and the active pentacene channel region. Vast improvements in the subthreshold slope and threshold voltage are observed compared to control devices fabricated without the buffer. Both observations are consistent with a greatly reduced density of charge trapping states at the semiconductor-dielectric interface effected by introduction of the self-assembled monolayer.

Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors.

Science.gov (United States)

Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

2016-12-01

In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade(-1) and 3.62 × 10(11) eV(-1) cm(-2), respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

Structural characterization and dielectric properties of BaTiO3 thin films obtained by spin coating

Directory of Open Access Journals (Sweden)

Branimir Bajac

2014-12-01

Full Text Available Barium titanate thin films were prepared by spin coating deposition technique of an acetic precursor sol and sintered at 750, 900 and 1050 °C. Phase composition of the obtained thin films was characterized by X-ray diffraction and Raman spectroscopy. Their morphology was analysed by scanning electron microscopy and atomic force microscopy. Dielectric properties of thin films sintered at 750 and 900 °C were characterized by LCD device, where the influence of sintering temperature on dielectric permittivity and loss tangent was inspected. It was concluded that higher sintering temperature increases grain size and amount of tetragonal phase, hence higher relative permittivity was recorded. The almost constant relative permittivity in the measured frequency (800 Hz–0.5 MHz and temperature (25–200 °C ranges as well as low dielectric loss are very important for the application of BaTiO3 films in microelectronic devices.

C-V characterization of Schottky- and MIS-gate SiGe/Si HEMT structures

International Nuclear Information System (INIS)

Onojima, Norio; Kasamatsu, Akihumi; Hirose, Nobumitsu; Mimura, Takashi; Matsui, Toshiaki

2008-01-01

Electrical properties of Schottky- and metal-insulator-semiconductor (MIS)-gate SiGe/Si high electron mobility transistors (HEMTs) were investigated with capacitance-voltage (C-V) measurements. The MIS-gate HEMT structure was fabricated using a SiN gate insulator formed by catalytic chemical vapor deposition (Cat-CVD). The Cat-CVD SiN thin film (5 nm) was found to be an effective gate insulator with good gate controllability and dielectric properties. We previously investigated device characteristics of sub-100-nm-gate-length Schottky- and MIS-gate HEMTs, and reported that the MIS-gate device had larger maximum drain current density and transconductance (g m ) than the Schottky-gate device. The radio frequency (RF) measurement of the MIS-gate device, however, showed a relatively lower current gain cutoff frequency f T compared with that of the Schottky-gate device. In this study, C-V characterization of the MIS-gate HEMT structure demonstrated that two electron transport channels existed, one at the SiGe/Si buried channel and the other at the SiN/Si surface channel

C-V characterization of Schottky- and MIS-gate SiGe/Si HEMT structures

Energy Technology Data Exchange (ETDEWEB)

Onojima, Norio [National Institute of Information and Communications Technology (NICT), Koganei, Tokyo 184-8795 (Japan)], E-mail: nonojima@nict.go.jp; Kasamatsu, Akihumi; Hirose, Nobumitsu [National Institute of Information and Communications Technology (NICT), Koganei, Tokyo 184-8795 (Japan); Mimura, Takashi [National Institute of Information and Communications Technology (NICT), Koganei, Tokyo 184-8795 (Japan); Fujitsu Laboratories Ltd., Atsugi, Kanagawa 243-0197 (Japan); Matsui, Toshiaki [National Institute of Information and Communications Technology (NICT), Koganei, Tokyo 184-8795 (Japan)

2008-07-30

Electrical properties of Schottky- and metal-insulator-semiconductor (MIS)-gate SiGe/Si high electron mobility transistors (HEMTs) were investigated with capacitance-voltage (C-V) measurements. The MIS-gate HEMT structure was fabricated using a SiN gate insulator formed by catalytic chemical vapor deposition (Cat-CVD). The Cat-CVD SiN thin film (5 nm) was found to be an effective gate insulator with good gate controllability and dielectric properties. We previously investigated device characteristics of sub-100-nm-gate-length Schottky- and MIS-gate HEMTs, and reported that the MIS-gate device had larger maximum drain current density and transconductance (g{sub m}) than the Schottky-gate device. The radio frequency (RF) measurement of the MIS-gate device, however, showed a relatively lower current gain cutoff frequency f{sub T} compared with that of the Schottky-gate device. In this study, C-V characterization of the MIS-gate HEMT structure demonstrated that two electron transport channels existed, one at the SiGe/Si buried channel and the other at the SiN/Si surface channel.

Physical and electrical properties of bilayer CeO{sub 2}/TiO{sub 2} gate dielectric stack

Energy Technology Data Exchange (ETDEWEB)

Chong, M.M.V. [School of Materials Science and Engineering, Nanyang Technological University of Singapore, Block N 4.1Nanyang Avenue, Singapore 639798 (Singapore); GlobalFoundries Singapore Private Limited, 60 Woodlands Industrial Park D Street 2, Singapore 738406 (Singapore); Lee, P.S. [School of Materials Science and Engineering, Nanyang Technological University of Singapore, Block N 4.1Nanyang Avenue, Singapore 639798 (Singapore); Tok, A.I.Y., E-mail: MIYTOK@ntu.edu.sg [School of Materials Science and Engineering, Nanyang Technological University of Singapore, Block N 4.1Nanyang Avenue, Singapore 639798 (Singapore)

2016-08-15

Highlights: • A bilayer gate dielectric stack of CeO{sub 2}/TiO{sub 2} to study the dependency of film growth with varying annealing temperatures is proposed. • The study demonstrates CeO{sub 2}/TiO{sub 2} bilayer stack with comparable κ-value as that of HfO{sub 2} but with reduced leakage current density of 4 orders of magnitude. • Schottky emission is the dominant leakage conduction mechanism of annealed CeO{sub 2}/TiO{sub 2} stack due to thermionic effect of interface properties. - Abstract: This study demonstrates a bilayer gate oxide structure of cerium oxide deposited via pulsed laser deposition and titanium oxide using conventional atomic layer deposition. Samples were deposited on p-type Si (100) substrate and exhibit interesting physical and electrical properties such that 600 °C annealed CeO{sub 2}/TiO{sub 2} samples having κ-value of 18 whereas pure CeO{sub 2} deposited samples have dielectric constant of 17.1 with leakage current density of 8.94 × 10{sup −6} A/cm{sup 2} at 1 V applied voltage. The result shows promising usage of the synthesized rare earth oxides as gate dielectric where ideal κ-value and significant reduction of the leakage current by 5 orders of magnitude is achieved. Leakage current conduction mechanism for as-deposited sample is found to be dominated by Poole–Frenkel (PF) emission; the trap level is found to be at 1.29 eV whereas annealed samples (600 °C and 800 °C) exhibited Schottky emission with trap levels at 1.45 eV and 0.81 eV, respectively.

SHI induced effects on the electrical and optical properties of HfO_2 thin films deposited by RF sputtering

International Nuclear Information System (INIS)

Manikanthababu, N.; Dhanunjaya, M.; Nageswara Rao, S.V.S.; Pathak, A.P.

2016-01-01

The continuous downscaling of Metal Oxide Semiconductor (MOS) devices has reached a limit with SiO_2 as a gate dielectric material. Introducing high-k dielectric materials as a replacement for the conservative SiO_2 is the only alternative to reduce the leakage current. HfO_2 is a reliable and an impending material for the wide usage as a gate dielectric in semiconductor industry. HfO_2 thin films were synthesized by RF sputtering technique. Here, we present a study of Swift Heavy Ion (SHI) irradiation with100 MeV Ag ions for studying the optical properties as well as 80 MeV Ni ions for studying the electrical properties of HfO_2/Si thin films. Rutherford Backscattering Spectrometry (RBS), Field Emission Scanning Electron Microscope (FESEM), energy-dispersive X-ray spectroscopy (EDS), profilometer and I–V (leakage current) measurements have been employed to study the SHI induced effects on both the structural, electrical and optical properties.

Preparation and dielectric properties of compositionally graded lead barium zirconate thin films

Energy Technology Data Exchange (ETDEWEB)

Hao, Xihong, E-mail: xhhao@imust.edu.c [Functional Materials Research Laboratory, Tongji University, Shanghai 200092 (China); School of Materials and Metallurgy, Inner Mongolia University of Science and Technology, Baotou 014010 (China); Zhang, Zhiqing [School of Materials and Metallurgy, Inner Mongolia University of Science and Technology, Baotou 014010 (China); Zhou, Jing [State Key Laboratory of Advanced Technology for Materials Synthesis and Processing, Wuhan University of Technology, Wuhan 430070 (China); An, Shengli [School of Materials and Metallurgy, Inner Mongolia University of Science and Technology, Baotou 014010 (China); Zhai, Jiwei [Functional Materials Research Laboratory, Tongji University, Shanghai 200092 (China)

2010-07-09

Both up and down compositionally graded (Pb{sub 1-x}Ba{sub x})ZrO{sub 3} (PBZ) thin films with increasing x from 0.4 to 0.6 were deposited on Pt(1 1 1)-buffer layered silicon substrates through a sol-gel method. The microstructure and dielectric properties of graded PBZ thin films were investigated systemically. X-ray diffraction patterns confirmed that both PBZ films had crystallized into a pure perovskite phase after annealed 700 {sup o}C. Electrical measurement results showed that although up graded films had a slightly larger tunability, dielectric loss of down graded films was much lower than that of up graded films. Therefore, the figure of merit of down graded PBZ films was greatly enhanced, as compared with up graded films. Moreover, down graded PBZ thin films also displayed excellent temperature stability with a smaller temperature coefficient of capacitance (TCC) of -0.59 x 10{sup -3} {sup o}C{sup -1} from 20 {sup o}C to 80 {sup o}C.

SHI induced effects on the electrical and optical properties of HfO{sub 2} thin films deposited by RF sputtering

Energy Technology Data Exchange (ETDEWEB)

Manikanthababu, N.; Dhanunjaya, M.; Nageswara Rao, S.V.S.; Pathak, A.P., E-mail: appsp@uohyd.ernet.in

2016-07-15

The continuous downscaling of Metal Oxide Semiconductor (MOS) devices has reached a limit with SiO{sub 2} as a gate dielectric material. Introducing high-k dielectric materials as a replacement for the conservative SiO{sub 2} is the only alternative to reduce the leakage current. HfO{sub 2} is a reliable and an impending material for the wide usage as a gate dielectric in semiconductor industry. HfO{sub 2} thin films were synthesized by RF sputtering technique. Here, we present a study of Swift Heavy Ion (SHI) irradiation with100 MeV Ag ions for studying the optical properties as well as 80 MeV Ni ions for studying the electrical properties of HfO{sub 2}/Si thin films. Rutherford Backscattering Spectrometry (RBS), Field Emission Scanning Electron Microscope (FESEM), energy-dispersive X-ray spectroscopy (EDS), profilometer and I–V (leakage current) measurements have been employed to study the SHI induced effects on both the structural, electrical and optical properties.

Effect of gate dielectrics on the performance of p-type Cu2O TFTs processed at room temperature

KAUST Repository

Al-Jawhari, Hala A.; Caraveo-Frescas, Jesus Alfonso

2013-01-01

/off ratio of around 44, threshold voltage equaling -0.62 V and a sub threshold swing of 1.64 V/dec. These values were obtained at a low operating voltage of -2V. The advantages of using STO as a gate dielectric relative to ATO are discussed. © (2014) Trans

Improvement in negative bias illumination stress stability of In-Ga-Zn-O thin film transistors using HfO2 gate insulators by controlling atomic-layer-deposition conditions

Science.gov (United States)

Na, So-Yeong; Kim, Yeo-Myeong; Yoon, Da-Jeong; Yoon, Sung-Min

2017-12-01

The effects of atomic layer deposition (ALD) conditions for the HfO2 gate insulators (GI) on the device characteristics of the InGaZnO (IGZO) thin film transistors (TFTs) were investigated when the ALD temperature and Hf precursor purge time were varied to 200, 225, and 250 °C, and 15 and 30 s, respectively. The HfO2 thin films showed low leakage current density of 10-8 A cm-2, high dielectric constant of over 20, and smooth surface roughness at all ALD conditions. The IGZO TFTs using the HfO2 GIs showed good device characteristics such as a saturation mobility as high as 11 cm2 V-1 s-1, a subthreshold swing as low as 0.10 V/dec, and all the devices could be operated at a gate voltage as low as  ±3 V. While there were no marked differences in transfer characteristics and PBS stabilities among the fabricated devices, the NBIS instabilities could be improved by increasing the ALD temperature for the formation of HfO2 GIs by reducing the oxygen vacancies within the IGZO channel.

Nature of Dielectric Properties, Electric Modulus and AC Electrical Conductivity of Nanocrystalline ZnIn2Se4 Thin Films

Science.gov (United States)

El-Nahass, M. M.; Attia, A. A.; Ali, H. A. M.; Salem, G. F.; Ismail, M. I.

2018-02-01

The structural characteristics of thermally deposited ZnIn2Se4 thin films were indexed utilizing x-ray diffraction as well as scanning electron microscopy techniques. Dielectric properties, electric modulus and AC electrical conductivity of ZnIn2Se4 thin films were examined in the frequency range from 42 Hz to 106 Hz. The capacitance, conductance and impedance were measured at different temperatures. The dielectric constant and dielectric loss decrease with an increase in frequency. The maximum barrier height was determined from the analysis of the dielectric loss depending on the Giuntini model. The real part of the electric modulus revealed a constant maximum value at higher frequencies and the imaginary part of the electric modulus was characterized by the appearance of dielectric relaxation peaks. The AC electrical conductivity obeyed the Jonscher universal power law. Correlated barrier hopping model was the appropriate mechanism for AC conduction in ZnIn2Se4 thin films. Estimation of the density of states at the Fermi level and activation energy, for AC conduction, was carried out based on the temperature dependence of AC electrical conductivity.

Poly(vinyl acetate)/clay nanocomposite materials for organic thin film transistor application.

Science.gov (United States)

Park, B J; Sung, J H; Park, J H; Choi, J S; Choi, H J

2008-05-01

Nanocomposite materials of poly(vinyl acetate) (PVAc) and organoclay were fabricated, in order to be utilized as dielectric materials of the organic thin film transistor (OTFT). Spin coating condition of the nanocomposite solution was examined considering shear viscosity of the composite materials dissolved in chloroform. Intercalated structure of the PVAc/clay nanocomposites was characterized using both wide-angle X-ray diffraction and TEM. Fracture morphology of the composite film on silicon wafer was also observed by SEM. Dielectric constant (4.15) of the nanocomposite materials shows that the PVAc/clay nanocomposites are applicable for the gate dielectric materials.

Experimental and theoretical investigation of the effect of SiO2 content in gate dielectrics on work function shift induced by nanoscale capping layers

KAUST Repository

Caraveo-Frescas, J. A.; Wang, H.; Schwingenschlö gl, Udo; Alshareef, Husam N.

2012-01-01

The impact of SiO2 content in ultrathin gate dielectrics on the magnitude of the effective work function (EWF) shift induced by nanoscale capping layers has been investigated experimentally and theoretically. The magnitude of the effective work function shift for four different capping layers (AlN, Al2O3, La2O3, and Gd2O3) is measured as a function of SiO2 content in the gate dielectric. A nearly linear increase of this shift with SiO2 content is observed for all capping layers. The origin of this dependence is explained using density functional theory simulations.

Experimental and theoretical investigation of the effect of SiO2 content in gate dielectrics on work function shift induced by nanoscale capping layers

KAUST Repository

Caraveo-Frescas, J. A.

2012-09-10

The impact of SiO2 content in ultrathin gate dielectrics on the magnitude of the effective work function (EWF) shift induced by nanoscale capping layers has been investigated experimentally and theoretically. The magnitude of the effective work function shift for four different capping layers (AlN, Al2O3, La2O3, and Gd2O3) is measured as a function of SiO2 content in the gate dielectric. A nearly linear increase of this shift with SiO2 content is observed for all capping layers. The origin of this dependence is explained using density functional theory simulations.

Multi-material gate poly-crystalline thin film transistors: Modeling and simulation for an improved gate transport efficiency

International Nuclear Information System (INIS)

Sehgal, Amit; Mangla, Tina; Gupta, Mridula; Gupta, R.S.

2008-01-01

In this work, a two-dimensional potential distribution formulation is presented for multi-material gate poly-crystalline silicon thin film transistors. The developed formulation incorporates the effects due to traps and grain-boundaries. In short-channel devices, short-channel effects and drain-induced barrier lowering (DIBL) effect exists, and are accounted for in the analysis. The work aims at the reduction of DIBL effect and grain-boundary effects i.e. to reduce the potential barriers generated in the channel by employing gate-engineered structures. A study of work-functions and electrode lengths of multi-material gate electrode is done to suppress the potential barriers, hot electron effect and to improve the carrier transport efficiency. Green's function approach is adopted for the two-dimensional potential solution. The results obtained show a good agreement with simulated results, thus, demonstrating the validity of our model

Electroresistance Effect in Gold Thin Film Induced by Ionic-Liquid-Gated Electric Double Layer

NARCIS (Netherlands)

Nakayama, Hiroyasu; Ye, Jianting; Ohtani, Takashi; Fujikawa, Yasunori; Ando, Kazuya; Iwasa, Yoshihiro; Saitoh, Eiji

Electroresistance effect was detected in a metallic thin film using ionic-liquid-gated electric-double-layer transistors (EDLTs). We observed reversible modulation of the electric resistance of a Au thin film. In this system, we found that an electric double layer works as a nanogap capacitor with

Bias-induced migration of ionized donors in amorphous oxide semiconductor thin-film transistors with full bottom-gate and partial top-gate structures

Directory of Open Access Journals (Sweden)

Mallory Mativenga

2012-09-01

Full Text Available Bias-induced charge migration in amorphous oxide semiconductor thin-film transistors (TFTs confirmed by overshoots of mobility after bias stressing dual gated TFTs is presented. The overshoots in mobility are reversible and only occur in TFTs with a full bottom-gate (covers the whole channel and partial top-gate (covers only a portion of the channel, indicating a bias-induced uneven distribution of ionized donors: Ionized donors migrate towards the region of the channel that is located underneath the partial top-gate and the decrease in the density of ionized donors in the uncovered portion results in the reversible increase in mobility.

Towards low-voltage organic thin film transistors (OTFTs with solution-processed high-k dielectric and interface engineering

Directory of Open Access Journals (Sweden)

Yaorong Su

2015-11-01

Full Text Available Although impressive progress has been made in improving the performance of organic thin film transistors (OTFTs, the high operation voltage resulting from the low gate capacitance density of traditional SiO2 remains a severe limitation that hinders OTFTs'development in practical applications. In this regard, developing new materials with high-k characteristics at low cost is of great scientific and technological importance in the area of both academia and industry. Here, we introduce a simple solution-based technique to fabricate high-k metal oxide dielectric system (ATO at low-temperature, which can be used effectively to realize low-voltage operation of OTFTs. On the other hand, it is well known that the properties of the dielectric/semiconductor and electrode/semiconductor interfaces are crucial in controlling the electrical properties of OTFTs. By optimizing the above two interfaces with octadecylphosphonic acid (ODPA self-assembled monolayer (SAM and properly modified low-cost Cu, obviously improved device performance is attained in our low-voltage OTFTs. Further more, organic electronic devices on flexible substrates have attracted much attention due to their low-cost, rollability, large-area processability, and so on. Basing on the above results, outstanding electrical performance is achieved in flexible devices. Our studies demonstrate an effective way to realize low-voltage, high-performance OTFTs at low-cost.

Alumina nanoparticle/polymer nanocomposite dielectric for flexible amorphous indium-gallium-zinc oxide thin film transistors on plastic substrate with superior stability

Energy Technology Data Exchange (ETDEWEB)

Lai, Hsin-Cheng [Department of Electrical Engineering, National Chung Hsing University, Taichung 40227, Taiwan (China); Pei, Zingway, E-mail: zingway@dragon.nchu.edu.tw [Department of Electrical Engineering, National Chung Hsing University, Taichung 40227, Taiwan (China); Graduate Institute of Optoelectronic Engineering, National Chung Hsing University, Taichung 40227, Taiwan (China); Center of Nanoscience and Nanotechnology, National Chung Hsing University, Taichung 40227, Taiwan (China); Jian, Jyun-Ruri; Tzeng, Bo-Jie [Graduate Institute of Optoelectronic Engineering, National Chung Hsing University, Taichung 40227, Taiwan (China)

2014-07-21

In this study, the Al{sub 2}O{sub 3} nanoparticles were incorporated into polymer as a nono-composite dielectric for used in a flexible amorphous Indium-Gallium-Zinc Oxide (a-IGZO) thin-film transistor (TFT) on a polyethylene naphthalate substrate by solution process. The process temperature was well below 100 °C. The a-IGZO TFT exhibit a mobility of 5.13 cm{sup 2}/V s on the flexible substrate. After bending at a radius of 4 mm (strain = 1.56%) for more than 100 times, the performance of this a-IGZO TFT was nearly unchanged. In addition, the electrical characteristics are less altered after positive gate bias stress at 10 V for 1500 s. Thus, this technology is suitable for use in flexible displays.

Layered Cu-based electrode for high-dielectric constant oxide thin film-based devices

International Nuclear Information System (INIS)

Fan, W.; Saha, S.; Carlisle, J.A.; Auciello, O.; Chang, R.P.H.; Ramesh, R.

2003-01-01

Ti-Al/Cu/Ta multilayered electrodes were fabricated on SiO 2 /Si substrates by ion beam sputtering deposition, to overcome the problems of Cu diffusion and oxidation encountered during the high dielectric constant (κ) materials integration. The Cu and Ta layers remained intact through the annealing in oxygen environment up to 600 deg. C. The thin oxide layer, formed on the Ti-Al surface, effectively prevented the oxygen penetration toward underneath layers. Complex oxide (Ba x Sr 1-x )TiO 3 (BST) thin films were grown on the layered Ti-Al/Cu/Ta electrodes using rf magnetron sputtering. The deposited BST films exhibited relatively high permittivity (150), low dielectric loss (0.007) at zero bias, and low leakage current -8 A/cm 2 at 100 kV/cm

Surface modification of polyimide gate insulators for solution-processed 2,7-didecyl[1]benzothieno[3,2-b][1]benzothiophene (C10-BTBT) thin-film transistors.

Science.gov (United States)

Jang, Kwang-Suk; Kim, Won Soo; Won, Jong-Myung; Kim, Yun-Ho; Myung, Sung; Ka, Jae-Won; Kim, Jinsoo; Ahn, Taek; Yi, Mi Hye

2013-01-21

The surface property of a polyimide gate insulator was successfully modified with an n-octadecyl side-chain. Alkyl chain-grafted poly(amic acid), the polyimide precursor, was synthesized using the diamine comonomer with an alkyl side-chain. By adding a base catalyst to the poly(amic acid) coating solution, the imidization temperature of the spin-coated film could be reduced to 200 °C. The 350 nm-thick polyimide film had a dielectric constant of 3.3 at 10 kHz and a leakage current density of less than 8.7 × 10(-10) A cm(-2), while biased from 0 to 100 V. To investigate the potential of the alkyl chain-grafted polyimide film as a gate insulator for solution-processed organic thin-film transistors (TFTs), we fabricated C(10)-BTBT TFTs. C(10)-BTBT was deposited on the alkyl chain-grafted polyimide gate insulator by spin-coating, forming a well-ordered crystal structure. The field-effect mobility and the on/off current ratio of the TFT device were measured to be 0.20-0.56 cm(2) V(-1) s(-1) and >10(5), respectively.

Effects of Y incorporation in TaON gate dielectric on electrical performance of GaAs metal-oxide-semiconductor capacitor

Energy Technology Data Exchange (ETDEWEB)

Liu, Li Ning; Choi, Hoi Wai; Lai, Pui To [Department of Electrical and Electronic Engineering, The University of Hong Kong (China); Xu, Jing Ping [School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan (China)

2016-09-15

In this study, GaAs metal-oxide-semiconductor (MOS) capacitors using Y-incorporated TaON as gate dielectric have been investigated. Experimental results show that the sample with a Y/(Y + Ta) atomic ratio of 27.6% exhibits the best device characteristics: high k value (22.9), low interfacestate density (9.0 x 10{sup 11} cm{sup -2} eV{sup -1}), small flatband voltage (1.05 V), small frequency dispersion and low gate leakage current (1.3 x 10{sup -5}A/cm{sup 2} at V{sub fb} + 1 V). These merits should be attributed to the complementary properties of Y{sub 2}O{sub 3} and Ta{sub 2}O{sub 5}:Y can effectively passivate the large amount of oxygen vacancies in Ta{sub 2}O{sub 5}, while the positively-charged oxygen vacancies in Ta{sub 2}O{sub 5} are capable of neutralizing the effects of the negative oxide charges in Y{sub 2}O{sub 3}. This work demonstrates that an appropriate doping of Y content in TaON gate dielectric can effectively improve the electrical performance for GaAs MOS devices. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Improving the performance of organic thin film transistors formed on a vacuum flash-evaporated acrylate insulator

Energy Technology Data Exchange (ETDEWEB)

Ding, Z., E-mail: ziqian.ding@materials.ox.ac.uk; Abbas, G. A.; Assender, H. E. [Department of Materials, University of Oxford, Oxford OX1 3PH (United Kingdom); Morrison, J. J.; Sanchez-Romaguera, V.; Yeates, S. G. [School of Chemistry, University of Manchester, Manchester M13 9PL (United Kingdom); Taylor, D. M. [School of Electronic Engineering, Bangor University, Bangor LL57 1UT (United Kingdom)

2013-12-02

A systematic investigation has been undertaken, in which thin polymer buffer layers with different ester content have been spin-coated onto a flash-evaporated, cross-linked diacrylate gate-insulator to form bottom-gate, top-contact organic thin-film transistors. The highest device mobilities, ∼0.65 cm{sup 2}/V s and ∼1.00 cm{sup 2}/V s for pentacene and dinaphtho[2,3-b:2′,3′-f]-thieno[3,2-b]thiophene (DNTT), respectively, were only observed for a combination of large-grain (∼1–2 μm) semiconductor morphology coupled with a non-polar dielectric surface. No correlation was found between semiconductor grain size and dielectric surface chemistry. The threshold voltage of pentacene devices shifted from −10 V to −25 V with decreasing surface ester content, but remained close to 0 V for DNTT.

Self-standing chitosan films as dielectrics in organic thin-film transistors

Directory of Open Access Journals (Sweden)

J. Morgado

2013-12-01

Full Text Available Organic thin film transistors, using self-standing 50 µm thick chitosan films as dielectric, are fabricated using sublimed pentacene or two conjugated polymers deposited by spin coating as semiconductors. Field-effect mobilities are found to be similar to values obtained with other dielectrics and, in the case of pentacene, a value (0.13 cm2/(V•s comparable to high performing transistors was determined. In spite of the low On/Off ratios (a maximum value of 600 was obtained for the pentacene-based transistors, these are promising results for the area of sustainable organic electronics in general and for biocompatible electronics in particular.

First-principles simulations of the leakage current in metal-oxide-semiconductor structures caused by oxygen vacancies in HfO2 high-K gate dielectric

International Nuclear Information System (INIS)

Mao, L.F.; Wang, Z.O.

2008-01-01

HfO 2 high-K gate dielectric has been used as a new gate dielectric in metal-oxide-semiconductor structures. First-principles simulations are used to study the effects of oxygen vacancies on the tunneling current through the oxide. A level which is nearly 1.25 eV from the bottom of the conduction band is introduced into the bandgap due to the oxygen vacancies. The tunneling current calculations show that the tunneling currents through the gate oxide with different defect density possess the typical characteristic of stress-induced leakage current. Further analysis shows that the location of oxygen vacancies will have a marked effect on the tunneling current. The largest increase in the tunneling current caused by oxygen vacancies comes about at the middle oxide field when defects are located at the middle of the oxide. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Investigation of optical pump on dielectric tunability in PZT/PT thin film by THz spectroscopy.

Science.gov (United States)

Ji, Jie; Luo, Chunya; Rao, Yunkun; Ling, Furi; Yao, Jianquan

2016-07-11

The dielectric spectra of single-layer PbTiO3 (PT), single-layer PbZrxTi1-xO3 (PZT) and multilayer PZT/PT thin films under an external optical field were investigated at room temperature by time-domain terahertz (THz) spectroscopy. Results showed that the real part of permittivity increased upon application of an external optical field, which could be interpreted as hardening of the soft mode and increasing of the damping coefficient and oscillator strength. Furthermore, the central mode was observed in the three films. Among the dielectric property of the three thin films studied, the tunability of the PZT/PT superlattice was the largest.

Dielectric strength of SiO2 in a CMOS transistor structure

International Nuclear Information System (INIS)

Soden, J.M.

1979-01-01

The distribution of experimental dielectric strengths of SiO 2 gate dielectric in a CMOS transistor structure is shown to be composed of a primary, statistically-normal distribution of high dielectric strength and a secondary distribution spread through the lower dielectric strength region. The dielectric strength was not significantly affected by high level (1 x 10 6 RADS (Si)) gamma radiation or high temperature (200 0 C) stress. The primary distribution breakdowns occurred at topographical edges, mainly at the gate/field oxide interface, and the secondary distribution breakdowns occurred at random locations in the central region of the gate

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure.

Science.gov (United States)

Chen, Szu-Hung; Liao, Wen-Shiang; Yang, Hsin-Chia; Wang, Shea-Jue; Liaw, Yue-Gie; Wang, Hao; Gu, Haoshuang; Wang, Mu-Chun

2012-08-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal-semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

Effects of Interfacial Charge Depletion in Organic Thin-Film Transistors with Polymeric Dielectrics on Electrical Stability

Directory of Open Access Journals (Sweden)

Jaehoon Park

2010-06-01

Full Text Available We investigated the electrical stabilities of two types of pentacene-based organic thin-film transistors (OTFTs with two different polymeric dielectrics: polystyrene (PS and poly(4-vinyl phenol (PVP, in terms of the interfacial charge depletion. Under a short-term bias stress condition, the OTFT with the PVP layer showed a substantial increase in the drain current and a positive shift of the threshold voltage, while the PS layer case exhibited no change. Furthermore, a significant increase in the off-state current was observed in the OTFT with the PVP layer which has a hydroxyl group. In the presence of the interfacial hydroxyl group in PVP, the holes are not fully depleted during repetitive operation of the OTFT with the PVP layer and a large positive gate voltage in the off-state regime is needed to effectively refresh the electrical characteristics. It is suggested that the depletion-limited holes at the interface, i.e., interfacial charge depletion, between the PVP layer and the pentacene layer play a critical role on the electrical stability during operation of the OTFT.

Solid-State Densification of Spun-Cast Self-Assembled Monolayers for Use in Ultra-Thin Hybrid Dielectrics.

Science.gov (United States)

Hutchins, Daniel O; Acton, Orb; Weidner, Tobias; Cernetic, Nathan; Baio, Joe E; Castner, David G; Ma, Hong; Jen, Alex K-Y

2012-11-15

Ultra-thin self-assembled monolayer (SAM)-oxide hybrid dielectrics have gained significant interest for their application in low-voltage organic thin film transistors (OTFTs). A [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) SAM on ultrathin AlO x (2.5 nm) has been developed to significantly enhance the dielectric performance of inorganic oxides through reduction of leakage current while maintaining similar capacitance to the underlying oxide structure. Rapid processing of this SAM in ambient conditions is achieved by spin coating, however, as-cast monolayer density is not sufficient for dielectric applications. Thermal annealing of a bulk spun-cast PhO-19-PA molecular film is explored as a mechanism for SAM densification. SAM density, or surface coverage, and order are examined as a function of annealing temperature. These SAM characteristics are probed through atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), and near edge X-ray absorption fine structure spectroscopy (NEXAFS). It is found that at temperatures sufficient to melt the as-cast bulk molecular film, SAM densification is achieved; leading to a rapid processing technique for high performance SAM-oxide hybrid dielectric systems utilizing a single wet processing step. To demonstrate low-voltage devices based on this hybrid dielectric (with leakage current density of 7.7×10 -8 A cm -2 and capacitance density of 0.62 µF cm -2 at 3 V), pentacene thin-film transistors (OTFTs) are fabricated and yield sub 2 V operation and charge carrier mobilites of up to 1.1 cm 2 V -1 s -1 .

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

Energy Technology Data Exchange (ETDEWEB)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina [Department of Materials Science and Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen D-91058 (Germany); Institute for Physical Chemistry, Universität Heidelberg, Heidelberg D-69120 (Germany); Miehler, Dominik [Department of Materials Science and Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen D-91058 (Germany); Zaumseil, Jana, E-mail: zaumseil@uni-heidelberg.de [Institute for Physical Chemistry, Universität Heidelberg, Heidelberg D-69120 (Germany)

2015-08-24

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.

Perovskite oxynitride LaTiO{sub x}N{sub y} thin films: Dielectric characterization in low and high frequencies

Energy Technology Data Exchange (ETDEWEB)

Lu, Y.; Ziani, A. [Institut d' Electronique et de Telecommunications de Rennes (IETR) UMR-CNRS 6164, groupe ' Antennes et Hyperfrequences' , University of Rennes 1, UEB, IUT Saint Brieuc, 18 rue Henri Wallon, 22004 Saint Brieuc cedex (France); Le Paven-Thivet, C., E-mail: claire.lepaven@univ-rennes1.fr [Institut d' Electronique et de Telecommunications de Rennes (IETR) UMR-CNRS 6164, groupe ' Antennes et Hyperfrequences' , University of Rennes 1, UEB, IUT Saint Brieuc, 18 rue Henri Wallon, 22004 Saint Brieuc cedex (France); Benzerga, R.; Le Gendre, L. [Institut d' Electronique et de Telecommunications de Rennes (IETR) UMR-CNRS 6164, groupe ' Antennes et Hyperfrequences' , University of Rennes 1, UEB, IUT Saint Brieuc, 18 rue Henri Wallon, 22004 Saint Brieuc cedex (France); Fasquelle, D. [Laboratoire d' Etude des Materiaux et des Composants pour l' Electronique (LEMCEL) UPRES-EA 2601, University of Littoral-Cote d' Opale, 50 rue Ferdinand Buisson, F-62228 Calais cedex (France); Kassem, H. [Laboratoire de l' Integration du Materiau au Systeme(IMS) UMR-CNRS 5218, groupe Materiaux, University of Bordeaux 1, 16 avenue Pey-Berland, 33607 Pessac (France); and others

2011-11-01

Lanthanum titanium oxynitride (LaTiO{sub x}N{sub y}) thin films are studied with respect to their dielectric properties in low and high frequencies. Thin films are deposited by radio frequency magnetron sputtering on different substrates. Effects of nitrogen content and crystalline quality on dielectric properties are investigated. In low-frequency range, textured LaTiO{sub x}N{sub y} thin films deposited on conductive single crystal Nb-STO show a dielectric constant {epsilon} Prime Almost-Equal-To 140 with low losses tan{delta} = 0.012 at 100 kHz. For the LaTiO{sub x}N{sub y} polycrystalline films deposited on conductive silicon substrates with platinum (Pt/Ti/SiO{sub 2}/Si), the tunability reached up to 57% for a weak electric field of 50 kV/cm. In high-frequency range, epitaxial LaTiO{sub x}N{sub y} films deposited on MgO substrate present a high dielectric constant with low losses ({epsilon} Prime Almost-Equal-To 170, tan{delta} = 0.011, 12 GHz).

Fabrication and electrical properties of metal-oxide semiconductor capacitors based on polycrystalline p-Cu{sub x}O and HfO{sub 2}/SiO{sub 2} high-{kappa} stack gate dielectrics

Energy Technology Data Exchange (ETDEWEB)

Zou Xiao [Department of Electronic Science and Technology, School of Physical Science and Technology, Wuhan University, Wuhan, 430074 (China); Department of Electromachine Engineering, Jianghan University, Wuhan, 430056 (China); Fang Guojia, E-mail: gjfang@whu.edu.c [Department of Electronic Science and Technology, School of Physical Science and Technology, Wuhan University, Wuhan, 430074 (China); Yuan Longyan; Liu Nishuang; Long Hao; Zhao Xingzhong [Department of Electronic Science and Technology, School of Physical Science and Technology, Wuhan University, Wuhan, 430074 (China)

2010-05-31

Polycrystalline p-type Cu{sub x}O films were deposited after the growth of HfO{sub 2} dielectric on Si substrate by pulsed laser deposition, and Cu{sub x}O metal-oxide-semiconductor (MOS) capacitors with HfO{sub 2}/SiO{sub 2} stack gate dielectric were primarily fabricated and investigated. X-ray diffraction and X-ray photoelectron spectroscopy were applied to analyze crystalline structure and Cu{sup +}/Cu{sup 2+} ratios of Cu{sub x}O films respectively. SiO{sub 2} interlayer formed between the high-{kappa} dielectric and substrate was estimated by the transmission electron microscope. Results of electrical characteristic measurement indicate that the permittivity of HfO{sub 2} is about 22, and the gate leakage current density of MOS capacitor with 11.3 nm HfO{sub 2}/SiO{sub 2} stack dielectrics is {approx} 10{sup -4} A/cm{sup 2}. Results also show that the annealing in N{sub 2} can improve the quality of Cu{sub x}O/HfO{sub 2} interface and thus reduce the gate leakage density.

Room-Temperature-Processed Flexible Amorphous InGaZnO Thin Film Transistor.

Science.gov (United States)

Xiao, Xiang; Zhang, Letao; Shao, Yang; Zhou, Xiaoliang; He, Hongyu; Zhang, Shengdong

2017-12-13

A room-temperature flexible amorphous indium-gallium-zinc oxide thin film transistor (a-IGZO TFT) technology is developed on plastic substrates, in which both the gate dielectric and passivation layers of the TFTs are formed by an anodic oxidation (anodization) technique. While the gate dielectric Al 2 O 3 is grown with a conventional anodization on an Al:Nd gate electrode, the channel passivation layer Al 2 O 3 is formed using a localized anodization technique. The anodized Al 2 O 3 passivation layer shows a superior passivation effect to that of PECVD SiO 2 . The room-temperature-processed flexible a-IGZO TFT exhibits a field-effect mobility of 7.5 cm 2 /V·s, a subthreshold swing of 0.44 V/dec, an on-off ratio of 3.1 × 10 8 , and an acceptable gate-bias stability with threshold voltage shifts of 2.65 and -1.09 V under positive gate-bias stress and negative gate-bias stress, respectively. Bending and fatigue tests confirm that the flexible a-IGZO TFT also has a good mechanical reliability, with electrical performances remaining consistent up to a strain of 0.76% as well as after 1200 cycles of fatigue testing.

Laser-induced damage to thin film dielectric coatings

International Nuclear Information System (INIS)

Walker, T.W.

1980-01-01

The laser-induced damage thresholds of dielectric thin film coatings have been found to be more than an order of magnitude lower than the bulk material damage thresholds. Prior damage studies have been inconclusive in determining the damage mechanism which is operative in thin films. A program was conducted in which thin film damage thresholds were measured as a function of laser wavelength (1.06 μm, 0.53 μm, 0.35 μm and 0.26 μm), laser pulse length (5 and 15 nanoseconds), film materials and film thickness. The large matrix of data was compared to predictions given by avalanche ionization, multiphoton ionization and impurity theories of laser damage. When Mie absorption cross-sections and the exact thermal equations were included into the impurity theory excellent agreement with the data was found. The avalanche and multiphoton damage theories could not account for most parametric variations in the data. For example, the damage thresholds for most films increased as the film thickness decreased and only the impurity theory could account for this behavior. Other observed changes in damage threshold with changes in laser wavelength, pulse length and film material could only be adequately explained by the impurity theory. The conclusion which results from this study is that laser damage in thin film coatings results from absorbing impurities included during the deposition process

Dielectric properties of electron irradiated PbZrO 3 thin films

Indian Academy of Sciences (India)

The present paper deals with the study of the effects of electron (8 MeV) irradiation on the dielectric and ferroelectric properties of PbZrO3 thin films grown by sol–gel technique. The films were (0.62 m thick) subjected to electron irradiation using Microtron accelerator (delivered dose 80, 100, 120 kGy). The films were well ...

Lithium ion intercalation in thin crystals of hexagonal TaSe2 gated by a polymer electrolyte

Science.gov (United States)

Wu, Yueshen; Lian, Hailong; He, Jiaming; Liu, Jinyu; Wang, Shun; Xing, Hui; Mao, Zhiqiang; Liu, Ying

2018-01-01

Ionic liquid gating has been used to modify the properties of layered transition metal dichalcogenides (TMDCs), including two-dimensional (2D) crystals of TMDCs used extensively recently in the device work, which has led to observations of properties not seen in the bulk. The main effect comes from the electrostatic gating due to the strong electric field at the interface. In addition, ionic liquid gating also leads to ion intercalation when the ion size of the gate electrolyte is small compared to the interlayer spacing of TMDCs. However, the microscopic processes of ion intercalation have rarely been explored in layered TMDCs. Here, we employed a technique combining photolithography device fabrication and electrical transport measurements on the thin crystals of hexagonal TaSe2 using multiple channel devices gated by a polymer electrolyte LiClO4/Polyethylene oxide (PEO). The gate voltage and time dependent source-drain resistances of these thin crystals were used to obtain information on the intercalation process, the effect of ion intercalation, and the correlation between the ion occupation of allowed interstitial sites and the device characteristics. We found a gate voltage controlled modulation of the charge density waves and a scattering rate of charge carriers. Our work suggests that ion intercalation can be a useful tool for layered materials engineering and 2D crystal device design.

Dielectric properties investigation of Cu2O/ZnO heterojunction thin films by electrodeposition

International Nuclear Information System (INIS)

Li, Qiang; Xu, Mengmeng; Fan, Huiqing; Wang, Hairong; Peng, Biaolin; Long, Changbai; Zhai, Yuchun

2013-01-01

Highlights: ► Bottom-up self-assembly Cu 2 O/ZnO heterojunction was fabricated by electrochemical deposition on indium tin oxide (ITO) flexible substrate (polyethylene terephthalate-PET). ► The dielectric response of Cu 2 O/ZnO heterojunction thin films had been investigated. ► The universal dielectric response was used to investigate the hopping behavior in Cu 2 O/ZnO heterojunction. -- Abstract: Structures and morphologies of the Cu 2 O/ZnO heterojunction electrodeposited on indium tin oxide (ITO) flexible substrate (polyethylene terephthalate-PET) were investigated by X-ray diffraction (XRD), scanning electronic microscopy (SEM), high resolution transmission electron microscopy (HRTEM), respectively. The dielectric response of bottom-up self-assembly Cu 2 O/ZnO heterojunction was investigated. The low frequency dielectric dispersion (LFDD) was observed. The universal dielectric response (UDR) was used to investigate the frequency dependence of dielectric response for Cu 2 O/ZnO heterojunction, which was attributed to the long range and the short range hopping charge carriers at the low frequency and the high frequency region, respectively

Thin-film composite materials as a dielectric layer for flexible metal-insulator-metal capacitors.

Science.gov (United States)

Tiwari, Jitendra N; Meena, Jagan Singh; Wu, Chung-Shu; Tiwari, Rajanish N; Chu, Min-Ching; Chang, Feng-Chih; Ko, Fu-Hsiang

2010-09-24

A new organic-organic nanoscale composite thin-film (NCTF) dielectric has been synthesized by solution deposition of 1-bromoadamantane and triblock copolymer (Pluronic P123, BASF, EO20-PO70-EO20), in which the precursor solution has been achieved with organic additives. We have used a sol-gel process to make a metal-insulator-metal capacitor (MIM) comprising a nanoscale (10 nm-thick) thin-film on a flexible polyimide (PI) substrate at room temperature. Scanning electron microscope and atomic force microscope revealed that the deposited NCTFs were crack-free, uniform, highly resistant to moisture absorption, and well adhered on the Au-Cr/PI. The electrical properties of 1-bromoadamantane-P123 NCTF were characterized by dielectric constant, capacitance, and leakage current measurements. The 1-bromoadamantane-P123 NCTF on the PI substrate showed a low leakage current density of 5.5 x 10(-11) A cm(-2) and good capacitance of 2.4 fF at 1 MHz. In addition, the calculated dielectric constant of 1-bromoadamantane-P123 NCTF was 1.9, making them suitable candidates for use in future flexible electronic devices as a stable intermetal dielectric. The electrical insulating properties of 1-bromoadamantane-P123 NCTF have been improved due to the optimized dipole moments of the van der Waals interactions.

Optical and microwave dielectric properties of pulsed laser deposited Na{sub 0.5}Bi{sub 0.5}TiO{sub 3} thin film

Energy Technology Data Exchange (ETDEWEB)

Joseph, Andrews; Goud, J. Pundareekam; Raju, K. C. James [School of Physics, University of Hyderabad, Hyderabad, Telangana 500046 (India); Emani, Sivanagi Reddy [Advanced Center of Research in High Energy Materials (ACRHEM), School of Physics, University of Hyderabad, Telangana 500046 (India)

2016-05-23

Optical properties of pulsed laser deposited (PLD) sodium bismuth titanate thin films (NBT), are investigated at wavelengths of 190-2500 nm. Microwave dielectric properties were investigated using the Split Post Dielectric Resonator (SPDR) technique. At 10 GHz, the NBT films have a dielectric constant of 205 and loss tangent of 0.0373 at room temperature. The optical spectra analysis reveals that NBT thin films have an optical band gap E{sub g}=3.55 eV and it has a dielectric constant of 3.37 at 1000 nm with dielectric loss of 0.299. Hence, NBT is a promising candidate for photonic device applications.

All-metallic electrically gated 2H-TaSe2 thin-film switches and logic circuits

International Nuclear Information System (INIS)

Renteria, J.; Jiang, C.; Yan, Z.; Samnakay, R.; Goli, P.; Pope, T. R.; Salguero, T. T.; Wickramaratne, D.; Lake, R. K.; Khitun, A. G.; Balandin, A. A.

2014-01-01

We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe 2 were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe 2 –Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials

All-metallic electrically gated 2H-TaSe2 thin-film switches and logic circuits

Science.gov (United States)

Renteria, J.; Samnakay, R.; Jiang, C.; Pope, T. R.; Goli, P.; Yan, Z.; Wickramaratne, D.; Salguero, T. T.; Khitun, A. G.; Lake, R. K.; Balandin, A. A.

2014-01-01

We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe2 were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe2-Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials.

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Science.gov (United States)

Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

2018-06-01

The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

Visualization of dielectric constant-electric field-temperature phase maps for imprinted relaxor ferroelectric thin films

International Nuclear Information System (INIS)

Frederick, J. C.; Kim, T. H.; Maeng, W.; Brewer, A. A.; Podkaminer, J. P.; Saenrang, W.; Vaithyanathan, V.; Schlom, D. G.; Li, F.; Chen, L.-Q.; Trolier-McKinstry, S.; Rzchowski, M. S.; Eom, C. B.

2016-01-01

The dielectric phase transition behavior of imprinted lead magnesium niobate–lead titanate relaxor ferroelectric thin films was mapped as a function of temperature and dc bias. To compensate for the presence of internal fields, an external electric bias was applied while measuring dielectric responses. The constructed three-dimensional dielectric maps provide insight into the dielectric behaviors of relaxor ferroelectric films as well as the temperature stability of the imprint. The transition temperature and diffuseness of the dielectric response correlate with crystallographic disorder resulting from strain and defects in the films grown on strontium titanate and silicon substrates; the latter was shown to induce a greater degree of disorder in the film as well as a dielectric response lower in magnitude and more diffuse in nature over the same temperature region. Strong and stable imprint was exhibited in both films and can be utilized to enhance the operational stability of piezoelectric devices through domain self-poling.

Band Offsets and Interfacial Properties of HfAlO Gate Dielectric Grown on InP by Atomic Layer Deposition.

Science.gov (United States)

Yang, Lifeng; Wang, Tao; Zou, Ying; Lu, Hong-Liang

2017-12-01

X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy have been used to determine interfacial properties of HfO 2 and HfAlO gate dielectrics grown on InP by atomic layer deposition. An undesirable interfacial InP x O y layer is easily formed at the HfO 2 /InP interface, which can severely degrade the electrical performance. However, an abrupt interface can be achieved when the growth of the HfAlO dielectric on InP starts with an ultrathin Al 2 O 3 layer. The valence and conduction band offsets for HfAlO/InP heterojunctions have been determined to be 1.87 ± 0.1 and 2.83 ± 0.1 eV, respectively. These advantages make HfAlO a potential dielectric for InP MOSFETs.

Charge carrier mobility in thin films of organic semiconductors by the gated van der Pauw method

Science.gov (United States)

Rolin, Cedric; Kang, Enpu; Lee, Jeong-Hwan; Borghs, Gustaaf; Heremans, Paul; Genoe, Jan

2017-01-01

Thin film transistors based on high-mobility organic semiconductors are prone to contact problems that complicate the interpretation of their electrical characteristics and the extraction of important material parameters such as the charge carrier mobility. Here we report on the gated van der Pauw method for the simple and accurate determination of the electrical characteristics of thin semiconducting films, independently from contact effects. We test our method on thin films of seven high-mobility organic semiconductors of both polarities: device fabrication is fully compatible with common transistor process flows and device measurements deliver consistent and precise values for the charge carrier mobility and threshold voltage in the high-charge carrier density regime that is representative of transistor operation. The gated van der Pauw method is broadly applicable to thin films of semiconductors and enables a simple and clean parameter extraction independent from contact effects. PMID:28397852

Effect of La doping on crystalline orientation, microstructure and dielectric properties of PZT thin films

Energy Technology Data Exchange (ETDEWEB)

Xu, Wencai; Li, Qi; Wang, Xing [Dalian Univ. of Technology, Dalian (China). School of Mechanical Engineering; Yin, Zhifu [Jilin Univ., Changchun (China). Faculty of the School of Mechanical Science and Engineering; Zou, Helin [Dalian Univ. of Technology, Dalian (China). Key Lab. for Micro/Nano Systems and Technology

2017-11-01

Lanthanum (La)-modified lead zirconate titanate (PLZT) thin films with doping concentration from 0 to 5 at.-% have been fabricated by sol-gel methods to investigate the effects of La doping on crystalline orientation, microstructure and dielectric properties of the modified films. The characterization of PLZT thin films were performed by X-ray diffractometry (XRD), scanning electron microscopy (SEM) and precision impedance analysis. XRD analysis showed that PLZT films with La doping concentration below 4 at.-% exhibited (100) preferred orientation. SEM results indicated that PLZT films presented dense and columnar microstructures when La doping concentration was less than 3 at.-%, while the others showed columnar microstructures only at the bottom of the cross section. The maximum dielectric constant (1502.59 at 100 Hz) was obtained in a 2 at.-% La-doped film, which increased by 53.9 % compared with undoped film. Without introducing a seed layer, (100) oriented PLZT thin films were prepared by using conventional heat treatment process and adjusting La doping concentration.

Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

Science.gov (United States)

An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

2016-11-01

Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

Structural, dielectric and ferroelectric characterization of PZT thin films

Directory of Open Access Journals (Sweden)

Araújo E.B.

1999-01-01

Full Text Available In this work ferroelectric thin films of PZT were prepared by the oxide precursor method, deposited on Pt/Si substrate. Films of 0.5 mm average thickness were obtained. Electrical and ferroelectric characterization were carried out in these films. The measured value of the dielectric constant for films was 455. Ferroelectricity was confirmed by Capacitance-Voltage (C-V characteristics and P-E hysteresis loops. Remanent polarization for films presented value around 5.0 µC/cm2 and a coercive field of 88.8 kV/cm.

Mechanistic interaction study of thin oxide dielectric with conducting organic electrode

International Nuclear Information System (INIS)

Sharma, Himani; Sethi, Kanika; Raj, P. Markondeya; Gerhardt, R.A.; Tummala, Rao

2012-01-01

Highlights: ► Thin film-oxide dielectric-organic electrode interface studies for investigating the leakage mechanism. ► XPS to elucidate chemical-structural changes on dielectric oxide surface. ► Correlates structural characterization data with capacitor leakage current and impedance spectroscopy characteristics. - Abstract: This paper aims at understanding the interaction of intrinsic conducting polymer, PEDT, with ALD-deposited Al 2 O 3 and thermally oxidized Ta 2 O 5 dielectrics, and the underlying mechanisms for increase in leakage currents in PEDT-based capacitors. Conducting polymers offer several advantages as electrodes for high surface area capacitors because of their lower resistance, self-healing and enhanced conformality. However, capacitors with in situ polymerized PEDT show poor electrical properties that are attributed to the interfacial interaction between the organic electrode and the oxide dielectric. This study focuses on characterizing these interactions. A combination of compositional, structural and electrical characterization techniques was applied to polymer-solid-state-capacitor to understand the interfacial chemical behavior and dielectric property deterioration of alumina and tantalum-oxide films. XPS and impedance studies were employed to understand the stiochiometric and compositional changes that occur in the dielectric film on interaction with in situ deposited PEDT. Based on the observations from several complimentary techniques, it is concluded that tantalum-pentoxide has more resistance towards chemical interaction with in situ polymerized PEDT. The thermally oxidized Ta 2 O 5 -PEDT system showed leakage current of 280 nA μF −1 at 3 V with a breakdown voltage of 30 V. On the other hand, Al 2 O 3 -PEDT capacitor showed leakage current of 50 μA μF −1 and a breakdown voltage of 40 V. The study reports direct evidence for the mechanism of resistivity drop in alumina dielectric with in situ polymerized PEDT electrode.

Dual-Input AND Gate From Single-Channel Thin-Film FET

Science.gov (United States)

Miranda, F. A.; Pinto, N. J.; Perez, R.; Mueller, C. H.

2008-01-01

A regio-regular poly(3-hexylthiophene) (RRP3HT) thin-film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. RRP3HT is a semiconducting polymer that has a carrier mobility and on/off ratio when used in a field effect transistor (FET) configuration. This commercially available polymer is very soluble in common organic solvents and is easily processed to form uniform thin films. The most important polymer-based device fabricated and studied is the FET, since it forms the building block in logic circuits and switches for active matrix (light-emitting-diode) (LED) displays, smart cards, and radio frequency identification (RFID) cards.

Leakage and field emission in side-gate graphene field effect transistors

Energy Technology Data Exchange (ETDEWEB)

Di Bartolomeo, A., E-mail: dibant@sa.infn.it; Iemmo, L.; Romeo, F.; Cucolo, A. M. [Physics Department “E.R. Caianiello,” University of Salerno, via G. Paolo II, 84084 Fisciano (Italy); CNR-SPIN Salerno, via G. Paolo II, 84084 Fisciano (Italy); Giubileo, F. [CNR-SPIN Salerno, via G. Paolo II, 84084 Fisciano (Italy); Russo, S.; Unal, S. [Physics Department, University of Exeter, Stocker Road 6, Exeter, Devon EX4 4QL (United Kingdom); Passacantando, M.; Grossi, V. [Department of Physical and Chemical Sciences, University of L' Aquila, Via Vetoio, 67100 Coppito, L' Aquila (Italy)

2016-07-11

We fabricate planar graphene field-effect transistors with self-aligned side-gate at 100 nm from the 500 nm wide graphene conductive channel, using a single lithographic step. We demonstrate side-gating below 1 V with conductance modulation of 35% and transconductance up to 0.5 mS/mm at 10 mV drain bias. We measure the planar leakage along the SiO{sub 2}/vacuum gate dielectric over a wide voltage range, reporting rapidly growing current above 15 V. We unveil the microscopic mechanisms driving the leakage, as Frenkel-Poole transport through SiO{sub 2} up to the activation of Fowler-Nordheim tunneling in vacuum, which becomes dominant at higher voltages. We report a field-emission current density as high as 1 μA/μm between graphene flakes. These findings are important for the miniaturization of atomically thin devices.

Solid-state densification of spun-cast self-assembled monolayers for use in ultra-thin hybrid dielectrics

Energy Technology Data Exchange (ETDEWEB)

Hutchins, Daniel O.; Acton, Orb [Department of Materials Science and Engineering, University of Washington, Seattle, WA 98195 (United States); Weidner, Tobias [Department of Bioengineering, University of Washington, Seattle, WA 98195 (United States); Cernetic, Nathan [Department of Materials Science and Engineering, University of Washington, Seattle, WA 98195 (United States); Baio, Joe E. [Department of Chemical Engineering, University of Washington, Seattle, WA 98195 (United States); Castner, David G. [Department of Bioengineering, University of Washington, Seattle, WA 98195 (United States); Department of Chemical Engineering, University of Washington, Seattle, WA 98195 (United States); Ma, Hong, E-mail: hma@uw.edu [Department of Materials Science and Engineering, University of Washington, Seattle, WA 98195 (United States); Jen, Alex K.-Y., E-mail: ajen@uw.edu [Department of Materials Science and Engineering, University of Washington, Seattle, WA 98195 (United States); Department of Chemistry, University of Washington, Seattle, WA 98195 (United States)

2012-11-15

Highlights: Black-Right-Pointing-Pointer Rapid processing of SAM in ambient conditions is achieved by spin coating. Black-Right-Pointing-Pointer Thermal annealing of a bulk spun-cast molecular film is explored as a mechanism for SAM densification. Black-Right-Pointing-Pointer High-performance SAM-oxide hybrid dielectric is obtained utilizing a single wet processing step. - Abstract: Ultra-thin self-assembled monolayer (SAM)-oxide hybrid dielectrics have gained significant interest for their application in low-voltage organic thin film transistors (OTFTs). A [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) SAM on ultrathin AlO{sub x} (2.5 nm) has been developed to significantly enhance the dielectric performance of inorganic oxides through reduction of leakage current while maintaining similar capacitance to the underlying oxide structure. Rapid processing of this SAM in ambient conditions is achieved by spin coating, however, as-cast monolayer density is not sufficient for dielectric applications. Thermal annealing of a bulk spun-cast PhO-19-PA molecular film is explored as a mechanism for SAM densification. SAM density, or surface coverage, and order are examined as a function of annealing temperature. These SAM characteristics are probed through atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), and near edge X-ray absorption fine structure spectroscopy (NEXAFS). It is found that at temperatures sufficient to melt the as-cast bulk molecular film, SAM densification is achieved; leading to a rapid processing technique for high performance SAM-oxide hybrid dielectric systems utilizing a single wet processing step. To demonstrate low-voltage devices based on this hybrid dielectric (with leakage current density of 7.7 Multiplication-Sign 10{sup -8} A cm{sup -2} and capacitance density of 0.62 {mu}F cm{sup -2} at 3 V), pentacene thin-film transistors (OTFTs) are fabricated and yield sub 2 V operation and charge carrier mobilites of up to

Dielectrophoretic deformation of thin liquid films induced by surface charge patterns on dielectric substrates

NARCIS (Netherlands)

Berendsen, C.W.J.; Kuijpers, C.J.; Zeegers, J.C.H.; Darhuber, A.A.

2013-01-01

We studied the deformation of thin liquid films induced by surface charge patterns at the solid–liquid interface quantitatively by experiments and numerical simulations. We deposited a surface charge distribution on dielectric substrates by applying potential differences between a conductive liquid

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

Science.gov (United States)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-01

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

Science.gov (United States)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-17

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Organic thin film transistors with polymer brush gate dielectrics synthesized by atom transfer radical polymerization

DEFF Research Database (Denmark)

Pinto, J.C.; Whiting, G.L.; Khodabakhsh, S.

2008-01-01

, synthesized by atom transfer radical polymerization (ATRP), were used to fabricate low voltage OFETs with both evaporated pentacene and solution deposited poly(3-hexylthiophene). The semiconductor-dielectric interfaces in these systems were studied with a variety of methods including scanning force microscopy...

Low temperature dielectric relaxation and charged defects in ferroelectric thin films

Directory of Open Access Journals (Sweden)

A. Artemenko

2013-04-01

Full Text Available We report a dielectric relaxation in BaTiO3-based ferroelectric thin films of different composition and with several growth modes: sputtering (with and without magnetron and sol-gel. The relaxation was observed at cryogenic temperatures (T < 100 K for frequencies from 100 Hz up to 10 MHz. This relaxation activation energy is always lower than 200 meV and is very similar to the relaxation that we reported in the parent bulk perovskites. Based on our Electron Paramagnetic Resonance (EPR investigation, we ascribe this dielectric relaxation to the hopping of electrons among Ti3+-V(O charged defects. Being dependent on the growth process and on the amount of oxygen vacancies, this relaxation can be a useful probe of defects in actual integrated capacitors with no need for specific shaping.

Design of Higher-k and More Stable Rare Earth Oxides as Gate Dielectrics for Advanced CMOS Devices

Directory of Open Access Journals (Sweden)

Yi Zhao

2012-08-01

Full Text Available High permittivity (k gate dielectric films are widely studied to substitute SiO₂ as gate oxides to suppress the unacceptable gate leakage current when the traditional SiO₂ gate oxide becomes ultrathin. For high-k gate oxides, several material properties are dominantly important. The first one, undoubtedly, is permittivity. It has been well studied by many groups in terms of how to obtain a higher permittivity for popular high-k oxides, like HfO₂ and La₂O₃. The second one is crystallization behavior. Although it’s still under the debate whether an amorphous film is definitely better than ploy-crystallized oxide film as a gate oxide upon considering the crystal boundaries induced leakage current, the crystallization behavior should be well understood for a high-k gate oxide because it could also, to some degree, determine the permittivity of the high-k oxide. Finally, some high-k gate oxides, especially rare earth oxides (like La₂O₃, are not stable in air and very hygroscopic, forming hydroxide. This topic has been well investigated in over the years and significant progresses have been achieved. In this paper, I will intensively review the most recent progresses of the experimental and theoretical studies for preparing higher-k and more stable, in terms of hygroscopic tolerance and crystallization behavior, Hf- and La-based ternary high-k gate oxides.

All-metallic electrically gated 2H-TaSe{sub 2} thin-film switches and logic circuits

Energy Technology Data Exchange (ETDEWEB)

Renteria, J.; Jiang, C.; Yan, Z. [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Samnakay, R.; Goli, P. [Materials Science and Engineering Program, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Pope, T. R.; Salguero, T. T. [Department of Chemistry, University of Georgia, Athens, Georgia 30602 (United States); Wickramaratne, D.; Lake, R. K. [Laboratory for Terascale and Terahertz Electronics, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Khitun, A. G. [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Materials Science and Engineering Program, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Balandin, A. A., E-mail: balandin@ee.ucr.edu [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Department of Chemistry, University of Georgia, Athens, Georgia 30602 (United States)

2014-01-21

We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe{sub 2} were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe{sub 2}–Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials.

Investigation of interface property in Al/SiO2/ n-SiC structure with thin gate oxide by illumination

Science.gov (United States)

Chang, P. K.; Hwu, J. G.

2017-04-01

The reverse tunneling current of Al/SiO2/ n-SiC structure employing thin gate oxide is introduced to examine the interface property by illumination. The gate current at negative bias decreases under blue LED illumination, yet increases under UV lamp illumination. Light-induced electrons captured by interface states may be emitted after the light sources are off, leading to the recovery of gate currents. Based on transient characteristics of gate current, the extracted trap level is close to the light energy for blue LED, indicating that electron capture induced by lighting may result in the reduction of gate current. Furthermore, bidirectional C- V measurements exhibit a positive voltage shift caused by electron trapping under blue LED illumination, while a negative voltage shift is observed under UV lamp illumination. Distinct trapping and detrapping behaviors can be observed from variations in I- V and C- V curves utilizing different light sources for 4H-SiC MOS capacitors with thin insulators.

Analytical Modeling of Triple-Metal Hetero-Dielectric DG SON TFET

Science.gov (United States)

Mahajan, Aman; Dash, Dinesh Kumar; Banerjee, Pritha; Sarkar, Subir Kumar

2018-02-01

In this paper, a 2-D analytical model of triple-metal hetero-dielectric DG TFET is presented by combining the concepts of triple material gate engineering and hetero-dielectric engineering. Three metals with different work functions are used as both front- and back gate electrodes to modulate the barrier at source/channel and channel/drain interface. In addition to this, front gate dielectric consists of high-K HfO2 at source end and low-K SiO2 at drain side, whereas back gate dielectric is replaced by air to further improve the ON current of the device. Surface potential and electric field of the proposed device are formulated solving 2-D Poisson's equation and Young's approximation. Based on this electric field expression, tunneling current is obtained by using Kane's model. Several device parameters are varied to examine the behavior of the proposed device. The analytical model is validated with TCAD simulation results for proving the accuracy of our proposed model.

Vacancy-fluorine complexes and their impact on the properties of metal-oxide transistors with high-k gate dielectrics studied using monoenergetic positron beams

Science.gov (United States)

Uedono, A.; Inumiya, S.; Matsuki, T.; Aoyama, T.; Nara, Y.; Ishibashi, S.; Ohdaira, T.; Suzuki, R.; Miyazaki, S.; Yamada, K.

2007-09-01

Vacancy-fluorine complexes in metal-oxide semiconductors (MOS) with high-k gate dielectrics were studied using a positron annihilation technique. F+ ions were implanted into Si substrates before the deposition of gate dielectrics (HfSiON). The shift of threshold voltage (Vth) in MOS capacitors and an increase in Fermi level position below the HfSiON/Si interface were observed after F+ implantation. Doppler broadening spectra of the annihilation radiation and positron lifetimes were measured before and after HfSiON fabrication processes. From a comparison between Doppler broadening spectra and those obtained by first-principles calculation, the major defect species in Si substrates after annealing treatment (1050 °C, 5 s) was identified as vacancy-fluorine complexes (V3F2). The origin of the Vth shift in the MOS capacitors was attributed to V3F2 located in channel regions.

Correlation between the dielectric constant and X-ray diffraction pattern of Si-O-C thin films with hydrogen bonds

International Nuclear Information System (INIS)

Oh, Teresa; Oh, Kyoung Suk; Lee, Kwang-Man; Choi, Chi Kyu

2004-01-01

The amorphous structure of organic-inorganic hybrid type Si-O-C thin films was studied using the first principles molecular-dynamics method with density functional techniques. The correlation between the dielectric constant and the degree of amorphous structure in organic-inorganic hybrid type Si-O-C thin films was studied. Si-O-C thin films were deposited by high-density plasma chemical vapor deposition using bis-trimethylsilylmethane and oxygen precursors. As-deposited films and films annealed at 500 deg. C were analyzed by X-ray diffraction (XRD). For quantitative analysis, the X-ray diffraction patterns of the samples were transformed to the radial distribution function (RDF) using Fourier analysis. Hybrid type Si-O-C thin films can be divided into three types using their amorphous structure and the dielectric constant: those with organic, hybrid, and inorganic properties

Dielectric Properties of Cd1-xZnxSe Thin Film Semiconductors

International Nuclear Information System (INIS)

Wahab, L.A.; Farrag, A.A.; Zayed, H.A.

2012-01-01

Cd 1-x Zn x Se (x=0, 0.5 and 1) thin films of thickness 300 nm have been deposited on highly cleaned glass substrates (Soda-lime glass) by thermal evaporation technique under pressure 10-5 Torr. The crystal structure, lattice parameters and grain size were determined from X-ray diffraction patterns of these films. The dielectric response and ac conductivity of the films are investigated in the frequency range from 80 Hz to 5 MHz and temperature range from 300 K to 420 K. AC conductivity increases linearly with the frequency according to the power relation σ a c (ψ)=A (ψ) s . The dielectric constant and loss show low values at high frequencies. The relaxation time t, resistance R and capacitance C were calculated from Nyquist diagram. The behavior can be modeled by an equivalent parallel RC circuit.

Structure dependent resistivity and dielectric characteristics of tantalum oxynitride thin films produced by magnetron sputtering

Energy Technology Data Exchange (ETDEWEB)

Cristea, D., E-mail: daniel.cristea@unitbv.ro [Department of Materials Science, Transilvania University, 500036 Brasov (Romania); Crisan, A. [Department of Materials Science, Transilvania University, 500036 Brasov (Romania); Cretu, N. [Electrical Engineering and Applied Physics Department, Transilvania University, 500036 Brasov (Romania); Borges, J. [Centro de Física, Universidade do Minho, Campus de Gualtar, 4710 - 057 Braga (Portugal); Instituto Pedro Nunes, Laboratório de Ensaios, Desgaste e Materiais, Rua Pedro Nunes, 3030-199 Coimbra (Portugal); SEG-CEMUC, Mechanical Engineering Department, University of Coimbra, 3030-788 Coimbra (Portugal); Lopes, C.; Cunha, L. [Centro de Física, Universidade do Minho, Campus de Gualtar, 4710 - 057 Braga (Portugal); Ion, V.; Dinescu, M. [National Institute for Lasers, Plasma and Radiation Physics, Lasers Department, “Photonic Processing of Advanced Materials” Group, PO Box MG-16, RO 77125 Magurele-Bucharest (Romania); Barradas, N.P. [Centro de Ciências e Tecnologias Nucleares, Instituto Superior Técnico, Universidade de Lisboa, E.N. 10 ao km 139,7, 2695-066 Bobadela LRS (Portugal); Alves, E. [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, E.N. 10 ao km 139,7, 2695-066 Bobadela LRS (Portugal); Apreutesei, M. [MATEIS Laboratory-INSA de Lyon, 21 Avenue Jean Capelle, 69621 Villeurbanne cedex (France); Université de Lyon, Institut des Nanotechnologies de Lyon INL-UMR5270, CNRS, Ecole Centrale de Lyon, Ecully F-69134 (France); Munteanu, D. [Department of Materials Science, Transilvania University, 500036 Brasov (Romania)

2015-11-01

Highlights: • Tantalum oxynitride thin films have been deposited by magnetron sputtering, in various configurations. • The rising of the reactive gases mixture flow has the consequence of a gradual increase in the non-metallic content in the films, which results in a 10 orders of magnitude resistivity domain. • The higher resistivity films exhibit dielectric constants up to 41 and quality factors up to 70. - Abstract: The main purpose of this work is to present and to interpret the change of electrical properties of Ta{sub x}N{sub y}O{sub z} thin films, produced by DC reactive magnetron sputtering. Some parameters were varied during deposition: the flow of the reactive gases mixture (N{sub 2} and O{sub 2}, with a constant concentration ratio of 17:3); the substrate voltage bias (grounded, −50 V or −100 V) and the substrate (glass, (1 0 0) Si or high speed steel). The obtained films exhibit significant differences. The variation of the deposition parameters induces variations of the composition, microstructure and morphology. These differences cause variation of the electrical resistivity essentially correlated with the composition and structural changes. The gradual decrease of the Ta concentration in the films induces amorphization and causes a raise of the resistivity. The dielectric characteristics of some of the high resistance Ta{sub x}N{sub y}O{sub z} films were obtained in the samples with a capacitor-like design (deposited onto high speed steel, with gold pads deposited on the dielectric Ta{sub x}N{sub y}O{sub z} films). Some of these films exhibited dielectric constant values higher than those reported for other tantalum based dielectric films.

Interface engineering and reliability characteristics of hafnium dioxide with poly silicon gate and dual metal (ruthenium-tantalum alloy, ruthenium) gate electrode for beyond 65 nm technology

Science.gov (United States)

Kim, Young-Hee

Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is

Indium-gallium-zinc-oxide thin-film transistor with a planar split dual-gate structure

Science.gov (United States)

Liu, Yu-Rong; Liu, Jie; Song, Jia-Qi; Lai, Pui-To; Yao, Ruo-He

2017-12-01

An amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) with a planar split dual gate (PSDG) structure has been proposed, fabricated and characterized. Experimental results indicate that the two independent gates can provide dynamical control of device characteristics such as threshold voltage, sub-threshold swing, off-state current and saturation current. The transconductance extracted from the output characteristics of the device increases from 4.0 × 10-6S to 1.6 × 10-5S for a change of control gate voltage from -2 V to 2 V, and thus the device could be used in a variable-gain amplifier. A significant advantage of the PSDG structure is its flexibility in controlling the device performance according to the need of practical applications.

High-throughput identification of higher-κ dielectrics from an amorphous N2-doped HfO2–TiO2 library

International Nuclear Information System (INIS)

Chang, K.-S.; Lu, W.-C.; Wu, C.-Y.; Feng, H.-C.

2014-01-01

Highlights: • Amorphous N 2 -doped HfO 2 –TiO 2 libraries were fabricated using sputtering. • Structure and quality of the dielectric and interfacial layers were investigated. • κ (54), J L < 10 −6 A/cm 2 , and equivalent oxide thickness (1 nm) were identified. - Abstract: High-throughput sputtering was used to fabricate high-quality, amorphous, thin HfO 2 –TiO 2 and N 2 -doped HfO 2 –TiO 2 (HfON–TiON) gate dielectric libraries. Electron probe energy dispersive spectroscopy was used to investigate the structures, compositions, and qualities of the dielectric and interfacial layers of these libraries to determine their electrical properties. A κ value of approximately 54, a leakage current density <10 −6 A/cm 2 , and an equivalent oxide thickness of approximately 1 nm were identified in an HfON–TiON library within a composition range of 68–80 at.% Ti. This library exhibits promise for application in highly advanced metal–oxide–semiconductor (higher-κ) gate stacks

Optimum source/drain overlap design for 16 nm high-k/metal gate MOSFETs

International Nuclear Information System (INIS)

Jang, Junyong; Lim, Towoo; Kim, Youngmin

2009-01-01

We explore a source/drain (S/D) design for a 16 nm MOSFET utilizing a replacement process for a high-k gate dielectric and metal gate electrode integration. Using TCAD simulation, a trade-off study between series resistance and overlap capacitance is carried out for a high-k dielectric surrounding gate structure, which results from the replacement process. An optimum S/D overlap to gate for the high-k surrounding gate structure is found to be different from the conventional gate structure, i.e. 0∼1 nm underlap is preferred for the surround high-k gate structure while 1∼2 nm overlap for the conventional gate one

Analysis of chemical bond states and electrical properties of stacked AlON/HfO{sub 2} gate oxides formed by using a layer-by-layer technique

Energy Technology Data Exchange (ETDEWEB)

Choi, Wonjoon; Lee, Jonghyun; Yang, Jungyup; Kim, Chaeok; Hong, Jinpyo; Nahm, Tschanguh; Byun, Byungsub; Kim, Moseok [Hanyang University, Seoul (Korea, Republic of)

2006-06-15

Stacked AlON/HfO{sub 2} thin films for gate oxides in metal-oxide-semiconductor devices are successfully prepared on Si substrates by utilizing a layer-by-layer technique integrated with an off-axis RF remote plasma sputtering process at room temperature. This off-axis structure is designed to improve the uniformity and the quality of gate oxide films. Also, a layer-by-layer technique is used to control the interface layer between the gate oxide and the Si substrate. The electrical properties of our stacked films are characterized by using capacitance versus voltage and leakage current versus voltage measurements. The stacked AlON/HfO{sub 2} gate oxide exhibits a low leakage current of about 10{sup -6} A/cm{sup 2} and a high dielectric constant value of 14.26 by effectively suppressing the interface layer between gate oxide and Si substrate. In addition, the chemical bond states and the optimum thickness of each AlON and HfO{sub 2} thin film are analyzed using X-ray photoemission spectroscopy and transmission electron microscopy measurement.

Stable dielectric response of low-loss aromatic polythiourea thin films on Pt/SiO2 substrate

Directory of Open Access Journals (Sweden)

A. Eršte

2016-03-01

Full Text Available We have investigated dielectric properties of aromatic polythiourea (ArPTU, a polar polymer containing high dipolar moments with very low defect levels thin films that were developed on Pt/SiO2 substrate. The detected response is compared to the response of commercially available polymers, such as high density polyethylene (HDPE and polypropylene (PP, which are at present used in foil capacitors. Stable values of the dielectric constant ε′≈5 (being twice higher than in HDPE and PP over broad temperature and frequency ranges and dielectric losses as low as in commercial systems suggest ArPTU as a promising candidate for future use in a variety of applications.

Photon-gated spin transistor

OpenAIRE

Li, Fan; Song, Cheng; Cui, Bin; Peng, Jingjing; Gu, Youdi; Wang, Guangyue; Pan, Feng

2017-01-01

Spin-polarized field-effect transistor (spin-FET), where a dielectric layer is generally employed for the electrical gating as the traditional FET, stands out as a seminal spintronic device under the miniaturization trend of electronics. It would be fundamentally transformative if optical gating was used for spin-FET. We report a new type of spin-polarized field-effect transistor (spin-FET) with optical gating, which is fabricated by partial exposure of the (La,Sr)MnO3 channel to light-emitti...

Surface, interface and thin film characterization of nano-materials using synchrotron radiation

International Nuclear Information System (INIS)

Kimura, Shigeru; Kobayashi, Keisuke

2005-01-01

From the results of studies in the nanotechnology support project of the Ministry of Education, Culture, Sports, Science and Technology of Japan, several investigations on the surface, interface and thin film characterization of nano-materials are described; (1) the MgB 2 thin film by X-ray diffraction, (2) the magnetism of the Pt thin film on a Co film by X-ray magnetic circular dichroism measurement, (3) the structure and physical properties of oxygen molecules absorbed in a micro hole of the cheleted polymer crystal by the direct observation in X-ray powder diffraction, and (4) the thin film gate insulator with a large dielectric constant, thermally treated HfO 2 /SiO 2 /Si, by X-ray photoelectron spectroscopy. (M.H.)

Breakdown of coupling dielectrics for Si microstrip detectors

International Nuclear Information System (INIS)

Candelori, A.; Paccagnella, A.; Padova Univ.; Saglimbeni, G.

1999-01-01

Double-layer coupling dielectrics for AC-coupled Si microstrip detectors have been electrically characterized in order to determine their performance in a radiation-harsh environment, with a focus on the dielectric breakdown. Two different dielectric technologies have been investigated: SiO 2 /TEOS and SiO 2 /Si 3 N 4 . Dielectrics have been tested by using a negative gate voltage ramp of 0.2 MV/(cm·s). The metal/insulator/Si I-V characteristics show different behaviours depending on the technology. The extrapolated values of the breakdown field for unirradiated devices are significantly higher for SiO 2 /Si 3 N 4 dielectrics, but the data dispersion is lower for SiO 2 /TEOS devices. No significant variation of the breakdown field has been measured after a 10 Mrad (Si) γ irradiation for SiO 2 /Si 3 N 4 dielectrics. Finally, the SiO 2 /Si 3 N 4 DC conduction is enhanced if a positive gate voltage ramp is applied with respect to the negative one, due to the asymmetric conduction of the double-layer dielectric

Effect of La and W dopants on dielectric and ferroelectric properties of PZT thin films prepared by sol-gel process

International Nuclear Information System (INIS)

Xiao, Mi; Zhang, Zebin; Zhang, Weikang; Zhang, Ping

2018-01-01

La or W-doped lead zirconate titanate thin films (PLZT or PZTW) were prepared on platinized silicon substrates by sol-gel process. The effects of La or W dopant on the phase development, microstructure, dielectric and ferroelectric characteristics of films were studied. For PLZT films, the optimum doping concentration was found to be 2 mol%. While for PZTW films, the dielectric and ferroelectric properties were found to be improved as the doping concentration increased. The fatigue properties of PLZT and PZTW thin films were also investigated, the results showed that A- or B-site donor doping could improve the fatigue properties of PZT thin films. The theory of oxygen vacancy was used to explain the performance improvement caused by donor doping. (orig.)

Effect of La and W dopants on dielectric and ferroelectric properties of PZT thin films prepared by sol-gel process

Science.gov (United States)

Xiao, Mi; Zhang, Zebin; Zhang, Weikang; Zhang, Ping

2018-01-01

La or W-doped lead zirconate titanate thin films (PLZT or PZTW) were prepared on platinized silicon substrates by sol-gel process. The effects of La or W dopant on the phase development, microstructure, dielectric and ferroelectric characteristics of films were studied. For PLZT films, the optimum doping concentration was found to be 2 mol%. While for PZTW films, the dielectric and ferroelectric properties were found to be improved as the doping concentration increased. The fatigue properties of PLZT and PZTW thin films were also investigated, the results showed that A- or B-site donor doping could improve the fatigue properties of PZT thin films. The theory of oxygen vacancy was used to explain the performance improvement caused by donor doping.

Relaxorlike dielectric behavior in Ba0.7Sr0.3TiO3 thin films

Science.gov (United States)

Zednik, Ricardo J.; McIntyre, Paul C.; Baniecki, John D.; Ishii, Masatoshi; Shioga, Takeshi; Kurihara, Kazuaki

2007-03-01

We present the results of a systematic dielectric study for sputter deposited barium strontium titanate thin film planar capacitors measured over a wide temperature range of 20-575K for frequencies between 1kHz and 1MHz. Our observations of dielectric loss peaks in the temperature and frequency domains cannot be understood in the typical framework of intrinsic phonon losses. We find that the accepted phenomenological Curie-von Schweidler dielectric behavior (universal relaxation law) in our barium strontium titanate films is only applicable over a narrow temperature range. An excellent fit to the Vogel-Fulcher expression suggests relaxorlike behavior in these films. The activation energy of the observed phenomenon suggests that oxygen ion motion play a role in the apparent relaxor behavior, although further experimental work is required to test this hypothesis.

Dielectric properties of DC reactive magnetron sputtered Al2O3 thin films

International Nuclear Information System (INIS)

Prasanna, S.; Mohan Rao, G.; Jayakumar, S.; Kannan, M.D.; Ganesan, V.

2012-01-01

Alumina (Al 2 O 3 ) thin films were sputter deposited over well-cleaned glass and Si substrates by DC reactive magnetron sputtering under various oxygen gas pressures and sputtering powers. The composition of the films was analyzed by X-ray photoelectron spectroscopy and an optimal O/Al atomic ratio of 1.59 was obtained at a reactive gas pressure of 0.03 Pa and sputtering power of 70 W. X-ray diffraction results revealed that the films were amorphous until 550 °C. The surface morphology of the films was studied using scanning electron microscopy and the as-deposited films were found to be smooth. The topography of the as-deposited and annealed films was analyzed by atomic force microscopy and a progressive increase in the rms roughness of the films from 3.2 nm to 4.53 nm was also observed with increase in the annealing temperature. Al-Al 2 O 3 -Al thin film capacitors were then fabricated on glass substrates to study the effect of temperature and frequency on the dielectric property of the films. Temperature coefficient of capacitance, AC conductivity and activation energy were determined and the results are discussed. - Highlights: ► Al 2 O 3 thin films were deposited by DC reactive magnetron sputtering. ► The films were found to be amorphous up to annealing temperature of 550 C. ► An increase in rms roughness of the films was observed with annealing. ► Al-Al 2 O 3 -Al thin film capacitors were fabricated and dielectric constant was 7.5. ► The activation energy decreased with increase in frequency.

Optical constants, dispersion energy parameters and dielectric properties of ultra-smooth nanocrystalline BiVO4 thin films prepared by rf-magnetron sputtering

Science.gov (United States)

Sarkar, S.; Das, N. S.; Chattopadhyay, K. K.

2014-07-01

BiVO4 thin films have been prepared through radio frequency (rf) magnetron sputtering of a pre-fabricated BiVO4 target on ITO coated glass (ITO-glass) substrate and bare glass substrates. BiVO4 target material was prepared through solid-state reaction method by heating Bi2O3 and V2O5 mixture at 800 °C for 8 h. The films were characterized by X-ray diffraction, UV-Vis spectroscopy, LCR meter, field emission scanning electron microscopy, transmission electron microscopy and atomic force microscopy. BiVO4 thin films deposited on the ITO-glass substrate are much smoother compared to the thin films prepared on bare glass substrate. The rms surface roughness calculated from the AFM images comes out to be 0.74 nm and 4.2 nm for the films deposited on the ITO-glass substrate and bare glass substrate for the deposition time 150 min respectively. Optical constants and energy dispersion parameters of these extra-smooth BiVO4 thin films have been investigated in detail. Dielectric properties of the BiVO4 thin films on ITO-glass substrate were also investigated. The frequency dependence of dielectric constant of the BiVO4 thin films has been measured in the frequency range from 20 Hz to 2 MHz. It was found that the dielectric constant increased from 145 to 343 at 20 Hz as the film thickness increased from 90 nm to 145 nm (deposition time increased from 60 min to 150 min). It shows higher dielectric constant compared to the literature value of BiVO4.

Effects of the gate dielectric on the subthreshold transport of carbon nanotube network transistors grown by using plasma-enhanced chemical vapor deposition

International Nuclear Information System (INIS)

Jeong, Seung Geun; Park, Wan Jun

2010-01-01

In this study, we investigated the subthreshold slope of random network carbon nanotube transistors with different geometries and passivations. Single-wall carbon nanotubes with lengths of 1-2 m were grown by using plasma-enhanced chemical vapor deposition to form the transistor channels. A critical channel length, where the subthreshold slope was saturated, of 7 μm was obtained. This was due to the percolational behavior of the nanotube random networks. With the dielectric passivation, the subthreshold slope was dramatically reduced from 9 V/decade to 0.9 V/decade by reducing interfacial trap sites, which then reduced the interface capacitance between the nanotube network and the gate dielectric.

TiN/Al2O3/ZnO gate stack engineering for top-gate thin film transistors by combination of post oxidation and annealing

Science.gov (United States)

Kato, Kimihiko; Matsui, Hiroaki; Tabata, Hitoshi; Takenaka, Mitsuru; Takagi, Shinichi

2018-04-01

Control of fabrication processes for a gate stack structure with a ZnO thin channel layer and an Al2O3 gate insulator has been examined for enhancing the performance of a top-gate ZnO thin film transistor (TFT). The Al2O3/ZnO interface and the ZnO layer are defective just after the Al2O3 layer formation by atomic layer deposition. Post treatments such as plasma oxidation, annealing after the Al2O3 deposition, and gate metal formation (PMA) are promising to improve the interfacial and channel layer qualities drastically. Post-plasma oxidation effectively reduces the interfacial defect density and eliminates Fermi level pinning at the Al2O3/ZnO interface, which is essential for improving the cut-off of the drain current of TFTs. A thermal effect of post-Al2O3 deposition annealing at 350 °C can improve the crystalline quality of the ZnO layer, enhancing the mobility. On the other hand, impacts of post-Al2O3 deposition annealing and PMA need to be optimized because the annealing can also accompany the increase in the shallow-level defect density and the resulting electron concentration, in addition to the reduction in the deep-level defect density. The development of the interfacial control technique has realized the excellent TFT performance with a large ON/OFF ratio, steep subthreshold characteristics, and high field-effect mobility.

Development of transparent thin film transistors on PES polymer substrates

International Nuclear Information System (INIS)

Yun, Eui-Jung; Jung, Jin-Woo; Ko, Kyung-Nam; Song, Young-Wook; Nam, Hyoung; Cho, Nam-Ihn

2010-01-01

In this study, we demonstrate ZnO-based transparent thin film transistors (TTFT's) implemented on polyethersulfone (PES) polymer substrates. For the developed TTFT's, radio-frequency magnetron sputter techniques were used to deposit Al-doped ZnO (AZO) at zero oxygen partial pressures for the source, the drain, and the gate-contact electrodes, undoped ZnO at low oxygen partial pressures for the active p-type layer, and SiO 2 for the gate dielectric. The TTFT's were processed at room temperature (RT), except for a 100 .deg. C sputtering step to deposit the AZO source, drain, and gate-contact electrodes. The devices have bottom-gate structures with top contacts, are optically transparent, and operate in an enhancement mode with a threshold voltage of +13 V, a mobility of 0.1 cm 2 /Vs, an on-off ratio of about 0.5 x 10 3 and, a sub-threshold slope of 4.1 V/decade.

Black metal thin films by deposition on dielectric antireflective moth-eye nanostructures

DEFF Research Database (Denmark)

Christiansen, Alexander Bruun; Caringal, Gideon Peter; Clausen, Jeppe Sandvik

2015-01-01

Although metals are commonly shiny and highly reflective, we here show that thin metal films appear black when deposited on a dielectric with antireflective moth-eye nanostructures. The nanostructures were tapered and close-packed, with heights in the range 300-600 nm, and a lateral, spatial...... frequency in the range 5-7 mu m(-1). A reflectance in the visible spectrum as low as 6%, and an absorbance of 90% was observed for an Al film of 100 nm thickness. Corresponding experiments on a planar film yielded 80% reflectance and 20% absorbance. The observed absorbance enhancement is attributed...... to a gradient effect causing the metal film to be antireflective, analogous to the mechanism in dielectrics and semiconductors. We find that the investigated nanostructures have too large spatial frequency to facilitate efficient coupling to the otherwise non-radiating surface plasmons. Applications...

Indium Sulfide and Indium Oxide Thin Films Spin-Coated from Triethylammonium Indium Thioacetate Precursor for n-Channel Thin Film Transistor

Energy Technology Data Exchange (ETDEWEB)

Tung, Duy Dao; Jeong, Hyun Dam [Chonnam Natioal University, Gwangju (Korea, Republic of)

2014-09-15

The In{sub 2}S{sub 3} thin films of tetragonal structure and In{sub 2}O{sub 3} films of cubic structure were synthesized by a spin coating method from the organometallic compound precursor triethylammonium indium thioacetate ([(Et){sub 3}NH]+ [In(SCOCH{sub 3}){sub 4}]''-; TEA-InTAA). In order to determine the electron mobility of the spin-coated TEA-InTAA films, thin film transistors (TFTs) with an inverted structure using a gate dielectric of thermal oxide (SiO{sub 2}) was fabricated. These devices exhibited n-channel TFT characteristics with a field-effect electron mobility of 10.1 cm''2 V''-1s''-1 at a curing temperature of 500 o C, indicating that the semiconducting thin film material is applicable for use in low-cost, solution-processed printable electronics.

All-optically tunable EIT-like dielectric metasurfaces hybridized with thin phase change material layers

Science.gov (United States)

Petronijevic, Emilija; Sibilia, Concita

2017-05-01

Electromagnetically induced transparency (EIT), a pump-induced narrow transparency window within the absorption region of a probe, had offered new perspectives in slow-light control in atomic physics. For applications in nanophotonics, the implementation on chip-scaled devices has later been obtained by mimicking this effect by metallic metamaterials. High losses in visible and near infrared range of metal-based metamaterialls have recently opened a new field of all-dielectric metamaterials; a proper configuration of high refractive index dielectric nanoresonators can mimick this effect without losses to get high Q, slow-light response. The next step would be the ability to tune their optical response, and in this work we investigate thin layers of phase change materials (PCM) for all-optical control of EIT-like all-dielectric metamaterials. PCM can be nonvolatively and reversibly switched between two stable phases that differ in optical properties by applying a visible laser pulse. The device is based on Si nanoresonators covered by a thin layer of PCM GeTe; optical and transient thermal simulations have been done to find and optimize the fabrication parameters and switching parameters such as the intensity and duration of the pulse. We have found that the EIT-like response can be switched on and off by applying the 532nm laser pulse to change the phase of the upper GeTe layer. We strongly believe that such approach could open new perspectives in all-optically controlled slow-light metamaterials.

Oligo- and polymeric FET devices: Thiophene-based active materials and their interaction with different gate dielectrics

International Nuclear Information System (INIS)

Porzio, W.; Destri, S.; Pasini, M.; Bolognesi, A.; Angiulli, A.; Di Gianvincenzo, P.; Natali, D.; Sampietro, M.; Caironi, M.; Fumagalli, L.; Ferrari, S.; Peron, E.; Perissinotti, F.

2006-01-01

Derivatives of both oligo- and polythiophene-based FET were recently considered for low cost electronic applications. In the device optimization, factors like redox reversibility of the molecule/polymer, electronic level compatibility with source/drain electrodes, packing closeness, and orientation versus the electrodes, can determine the overall performance. In addition, a gate insulator with a high dielectric constant, a low leakage current, and capability to promote ordering in the semiconductor is required to increase device performances and to lower the FET operating voltage. In this view, Al 2 O 3 appears a good candidate, although its widespread adoption is limited by the disorder that such oxide induces on the semiconductor with detrimental consequences on semiconductor electrical properties. In this contribution, an overview of recent results obtained on thiophene-derivative-based FET devices, fabricated by different growth techniques, and using both thermally grown SiO 2 and Al 2 O 3 from atomic layer deposition gate insulators will be reported and discussed with particular reference to organic solid state aggregation, morphology, and organic-inorganic interface

Thermal oxidation of Ni films for p-type thin-film transistors

KAUST Repository

Jiang, Jie; Wang, Xinghui; Zhang, Qing; Li, Jingqi; Zhang, Xixiang

2013-01-01

p-Type nanocrystal NiO-based thin-film transistors (TFTs) are fabricated by simply oxidizing thin Ni films at temperatures as low as 400 °C. The highest field-effect mobility in a linear region and the current on-off ratio are found to be 5.2 cm2 V-1 s-1 and 2.2 × 103, respectively. X-ray diffraction, transmission electron microscopy and electrical performances of the TFTs with "top contact" and "bottom contact" channels suggest that the upper parts of the Ni films are clearly oxidized. In contrast, the lower parts in contact with the gate dielectric are partially oxidized to form a quasi-discontinuous Ni layer, which does not fully shield the gate electric field, but still conduct the source and drain current. This simple method for producing p-type TFTs may be promising for the next-generation oxide-based electronic applications. © 2013 the Owner Societies.

Pulsed EM Field Response of a Thin, High-Contrast, Finely Layered Structure With Dielectric and Conductive Properties

NARCIS (Netherlands)

De Hoop, A.T.; Jiang, L.

2009-01-01

The response of a thin, high-contrast, finely layered structure with dielectric and conductive properties to an incident, pulsed, electromagnetic field is investigated theoretically. The fine layering causes the standard spatial discretization techniques to solve Maxwell's equations numerically to

Temperature-dependent gate-swing hysteresis of pentacene thin film transistors

Directory of Open Access Journals (Sweden)

Yow-Jon Lin

2014-10-01

Full Text Available The temperature-dependent hysteresis-type transfer characteristics of pentacene-based organic thin film transistors (OTFTs were researched. The temperature-dependent transfer characteristics exhibit hopping conduction behavior. The fitting data for the temperature-dependent off-to-on and on-to-off transfer characteristics of OTFTs demonstrate that the hopping distance (ah and the barrier height for hopping (qϕt control the carrier flow, resulting in the hysteresis-type transfer characteristics of OTFTs. The hopping model gives an explanation of the gate-swing hysteresis and the roles played by qϕt and ah.

High Mobility Flexible Amorphous IGZO Thin-Film Transistors with a Low Thermal Budget Ultra-Violet Pulsed Light Process.

Science.gov (United States)

Benwadih, M; Coppard, R; Bonrad, K; Klyszcz, A; Vuillaume, D

2016-12-21

Amorphous, sol-gel processed, indium gallium zinc oxide (IGZO) transistors on plastic substrate with a printable gate dielectric and an electron mobility of 4.5 cm 2 /(V s), as well as a mobility of 7 cm 2 /(V s) on solid substrate (Si/SiO 2 ) are reported. These performances are obtained using a low temperature pulsed light annealing technique. Ultraviolet (UV) pulsed light system is an innovative technique compared to conventional (furnace or hot-plate) annealing process that we successfully implemented on sol-gel IGZO thin film transistors (TFTs) made on plastic substrate. The photonic annealing treatment has been optimized to obtain IGZO TFTs with significant electrical properties. Organic gate dielectric layers deposited on this pulsed UV light annealed films have also been optimized. This technique is very promising for the development of amorphous IGZO TFTs on plastic substrates.

Nonlinear dielectric response in ferroelectric thin films

Directory of Open Access Journals (Sweden)

Lente, M. H.

2004-08-01

Full Text Available Electrical permittivity dependence on electric external bias field was investigated in PZT thin films. The results revealed the existence of two mechanisms contributing to the electrical permittivity. The first one was related to the domain reorientation, which was responsible for a strong no linear dielectric behavior, acting only during the poling process. The second mechanism was associated with the domain wall vibrations, which presented a reasonable linear electrical behavior with the applied bias field, contributing always to the permittivity independently of the poling state of the sample. The results also indicated that the gradual reduction of the permittivity with the increase of the bias field strength may be related to the gradual bending of the domain walls. It is believed that the domain wall bending induces a hardening and/or a thinning of the walls, thus reducing the electrical permittivity. A reinterpretation of the model proposed in the literature to explain the dielectric characteristics of ferroelectric materials at high electric field regime is proposed.

Se ha estudiado la dependencia de la permitividad eléctrica con un campo bias externo en láminas delgadas de PZT. Los resultados revelaron la existencia de dos mecanismos que contribuyen a la permitividad eléctrica. El primero está relacionado con la reorientación de dominios, actúa sólo durante el proceso de polarización y es responsable de un comportamiento dieléctrico fuertemente no lineal. El segundo mecanismo se asocia a las vibraciones de las paredes de dominio, presentando un comportamiento eléctrico razonablemente lineal con el campo bias aplicado, contribuyendo siempre a la permitividad independientemente del estado de polarización de la muestra. Los resultados indicaron también que la reducción gradual de la permitividad con el aumento de la fuerza del campo bias podría estar relacionada con el “bending” gradual de las paredes de dominio

Laser printed organic semiconductor PQT-12 for bottom-gate organic thin-film transistors: Fabrication and characterization

Energy Technology Data Exchange (ETDEWEB)

Makrygianni, M. [National Technical University of Athens, Physics Department, Iroon Polytehneiou 9, 15780 Zografou (Greece); National Technical University of Athens, Electrical and Computer Engineering Department, Iroon Polytehneiou 9, 15780 Zografou (Greece); Ainsebaa, A. [Ecole Nationale Supérieure des Mines de Saint-Etienne, Department of Flexible Electronics, CMP-EMSE, MOC, 13541 Gardanne (France); Nagel, M. [EMPA Swiss Federal Lab. for Materials Science and Technology, Laboratory for Functional Polymers, Überlandstrasse 129, 8600 Dubendorf (Switzerland); Sanaur, S. [Ecole Nationale Supérieure des Mines de Saint-Etienne, Department of Flexible Electronics, CMP-EMSE, MOC, 13541 Gardanne (France); Raptis, Y.S. [National Technical University of Athens, Physics Department, Iroon Polytehneiou 9, 15780 Zografou (Greece); Zergioti, I., E-mail: zergioti@central.ntua.gr [National Technical University of Athens, Physics Department, Iroon Polytehneiou 9, 15780 Zografou (Greece); Tsamakis, D. [National Technical University of Athens, Electrical and Computer Engineering Department, Iroon Polytehneiou 9, 15780 Zografou (Greece)

2016-12-30

Highlights: • Smooth printing of semiconducting π-conjugated polymer patterns for BG-BC OTFTs. • Well-ordering of PQT-12 when diluted in a high-boiling-point solvent yielding good interface properties. • No significant change in polymer chain orientation observed between LIFT printed patterns. • Reliable solid phase printing technique for thin, organic large area electronics applications, in a well-defined manner. - Abstract: In this work, we report on the effect of laser printed Poly (3,3‴-didodecyl quarter thiophene) on its optical, structural and electrical properties for bottom-gate/bottom-contact organic thin-film transistors applications. This semiconducting π-conjugated polymer was solution-deposited (spin-coated) on a donor substrate and transferred by means of solid phase laser-induced forward transfer (LIFT) technique on SiO{sub 2}/Si receiver substrates to form the active material. This article presents a detailed study of the electrical properties of the fabricated transistors by measuring the parasitic resistances for gold (Au) and platinum (Pt) as source-drain electrodes, for optimizing OTFTs in terms of contacts. In addition, X-ray diffraction patterns revealed that it is possible to control the polymer microstructure through the choice of solvent. Also, no significant change in polymer chain orientation was observed between two printed patterns at 90 and 130 mJ/cm{sup 2} as confirmed by Raman spectra. The results demonstrate hole mobility values of (2.6 ± 1.3) × 10{sup −2} cm{sup 2}/Vs, and lower parasitic resistance for dielectric surface roughness around 1.2 nm and Pt electrodes. Higher performances are correlated to i) the well-ordering of PQT-12 surface when a high-boiling-point solvent is used and ii) the less limitating Pt source/drain electrodes. This analytical study proves that solid phase LIFT printing is a reliable technology for the fabrication of thin, organic large area electronics in a well-defined manner.

Laser printed organic semiconductor PQT-12 for bottom-gate organic thin-film transistors: Fabrication and characterization

International Nuclear Information System (INIS)

Makrygianni, M.; Ainsebaa, A.; Nagel, M.; Sanaur, S.; Raptis, Y.S.; Zergioti, I.; Tsamakis, D.

2016-01-01

Highlights: • Smooth printing of semiconducting π-conjugated polymer patterns for BG-BC OTFTs. • Well-ordering of PQT-12 when diluted in a high-boiling-point solvent yielding good interface properties. • No significant change in polymer chain orientation observed between LIFT printed patterns. • Reliable solid phase printing technique for thin, organic large area electronics applications, in a well-defined manner. - Abstract: In this work, we report on the effect of laser printed Poly (3,3‴-didodecyl quarter thiophene) on its optical, structural and electrical properties for bottom-gate/bottom-contact organic thin-film transistors applications. This semiconducting π-conjugated polymer was solution-deposited (spin-coated) on a donor substrate and transferred by means of solid phase laser-induced forward transfer (LIFT) technique on SiO_2/Si receiver substrates to form the active material. This article presents a detailed study of the electrical properties of the fabricated transistors by measuring the parasitic resistances for gold (Au) and platinum (Pt) as source-drain electrodes, for optimizing OTFTs in terms of contacts. In addition, X-ray diffraction patterns revealed that it is possible to control the polymer microstructure through the choice of solvent. Also, no significant change in polymer chain orientation was observed between two printed patterns at 90 and 130 mJ/cm"2 as confirmed by Raman spectra. The results demonstrate hole mobility values of (2.6 ± 1.3) × 10"−"2 cm"2/Vs, and lower parasitic resistance for dielectric surface roughness around 1.2 nm and Pt electrodes. Higher performances are correlated to i) the well-ordering of PQT-12 surface when a high-boiling-point solvent is used and ii) the less limitating Pt source/drain electrodes. This analytical study proves that solid phase LIFT printing is a reliable technology for the fabrication of thin, organic large area electronics in a well-defined manner.

HfO2 as gate dielectric on Ge: Interfaces and deposition techniques

International Nuclear Information System (INIS)

Caymax, M.; Van Elshocht, S.; Houssa, M.; Delabie, A.; Conard, T.; Meuris, M.; Heyns, M.M.; Dimoulas, A.; Spiga, S.; Fanciulli, M.; Seo, J.W.; Goncharova, L.V.

2006-01-01

To fabricate MOS gate stacks on Ge, one can choose from a multitude of metal oxides as dielectric material which can be deposited by many chemical or physical vapor deposition techniques. As a few typical examples, we will discuss here the results from atomic layer deposition (ALD), metal organic CVD (MOCVD) and molecular beam deposition (MBD) using HfO 2 /Ge as materials model system. It appears that a completely interface layer free HfO 2 /Ge combination can be made in MBD, but this results in very bad capacitors. The same bad result we find if HfGe y (Hf germanides) are formed like in the case of MOCVD on HF-dipped Ge. A GeO x interfacial layer appears to be indispensable (if no other passivating materials are applied), but the composition of this interfacial layer (as determined by XPS, TOFSIMS and MEIS) is determining for the C/V quality. On the other hand, the presence of Ge in the HfO 2 layer is not the most important factor that can be responsible for poor C/V, although it can still induce bumps in C/V curves, especially in the form of germanates (Hf-O-Ge). We find that most of these interfacial GeO x layers are in fact sub-oxides, and that this could be (part of) the explanation for the high interfacial state densities. In conclusion, we find that the Ge surface preparation is determining for the gate stack quality, but it needs to be adapted to the specific deposition technique

Structural Evaluation of 5,5′-Bis(naphth-2-yl)-2,2′-bithiophene in Organic Field-Effect Transistors with n-Octadecyltrichlorosilane Coated SiO2 Gate Dielectric

DEFF Research Database (Denmark)

Lauritzen, Andreas E.; Torkkeli, Mika; Bikondoa, Oier

2018-01-01

We report on the structure and morphology of 5,5′-bis(naphth-2-yl)-2,2′-bithiophene (NaT2) films in bottom-contact organic field-effect transistors (OFETs) with octadecyltrichlorosilane (OTS) coated SiO2 gate dielectric, characterized by atomic force microscopy (AFM), grazing-incidence X......-ray diffraction (GIXRD), and electrical transport measurements. Three types of devices were investigated with the NaT2 thin-film deposited either on (1) pristine SiO2 (corresponding to higher surface energy, 47 mJ/m2) or on OTS deposited on SiO2 under (2) anhydrous or (3) humid conditions (corresponding to lower...... surface energies, 20–25 mJ/m2). NaT2 films grown on pristine SiO2 form nearly featureless three-dimensional islands. NaT2 films grown on OTS/SiO2 deposited under anhydrous conditions form staggered pyramid islands where the interlayer spacing corresponds to the size of the NaT2 unit cell. At the same time...

Mechanisms for plasma etching of HfO{sub 2} gate stacks with Si selectivity and photoresist trimming

Energy Technology Data Exchange (ETDEWEB)

Shoeb, Juline; Kushner, Mark J. [Department of Electrical and Computer Engineering, Iowa State University, Ames, Iowa 50011 (United States); Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109-2122 (United States)

2009-11-15

To minimize leakage currents resulting from the thinning of the insulator in the gate stack of field effect transistors, high-dielectric constant (high-k) metal oxides, and HfO{sub 2} in particular, are being implemented as a replacement for SiO{sub 2}. To speed the rate of processing, it is desirable to etch the gate stack (e.g., metal gate, antireflection layers, and dielectric) in a single process while having selectivity to the underlying Si. Plasma etching using Ar/BCl{sub 3}/Cl{sub 2} mixtures effectively etches HfO{sub 2} while having good selectivity to Si. In this article, results from integrated reactor and feature scale modeling of gate-stack etching in Ar/BCl{sub 3}/Cl{sub 2} plasmas, preceded by photoresist trimming in Ar/O{sub 2} plasmas, are discussed. It was found that BCl{sub n} species react with HfO{sub 2}, which under ion impact, form volatile etch products such as B{sub m}OCl{sub n} and HfCl{sub n}. Selectivity to Si is achieved by creating Si-B bonding as a precursor to the deposition of a BCl{sub n} polymer which slows the etch rate relative to HfO{sub 2}. The low ion energies required to achieve this selectivity then challenge one to obtain highly anisotropic profiles in the metal gate portion of the stack. Validation was performed with data from literature. The effect of bias voltage and key reactant probabilities on etch rate, selectivity, and profile are discussed.

Solution-Processed Dielectrics Based on Thickness-Sorted Two-Dimensional Hexagonal Boron Nitride Nanosheets

Energy Technology Data Exchange (ETDEWEB)

Zhu, Jian; Kang, Joohoon; Kang, Junmo; Jariwala, Deep; Wood, Joshua D.; Seo, Jung-Woo T.; Chen, Kan-Sheng; Marks, Tobin J.; Hersam, Mark C.

2015-10-14

Gate dielectrics directly affect the mobility, hysteresis, power consumption, and other critical device metrics in high-performance nanoelectronics. With atomically flat and dangling bond-free surfaces, hexagonal boron nitride (h-BN) has emerged as an ideal dielectric for graphene and related two-dimensional semiconductors. While high-quality, atomically thin h-BN has been realized via micromechanical cleavage and chemical vapor deposition, existing liquid exfoliation methods lack sufficient control over h-BN thickness and large-area film quality, thus limiting its use in solution-processed electronics. Here, we employ isopycnic density gradient ultracentrifugation for the preparation of monodisperse, thickness-sorted h-BN inks, which are subsequently layer-by-layer assembled into ultrathin dielectrics with low leakage currents of 3 × 10–9 A/cm2 at 2 MV/cm and high capacitances of 245 nF/cm2. The resulting solution-processed h-BN dielectric films enable the fabrication of graphene field-effect transistors with negligible hysteresis and high mobilities up to 7100 cm2 V–1 s–1 at room temperature. These h-BN inks can also be used as coatings on conventional dielectrics to minimize the effects of underlying traps, resulting in improvements in overall device performance. Overall, this approach for producing and assembling h-BN dielectric inks holds significant promise for translating the superlative performance of two-dimensional heterostructure devices to large-area, solution-processed nanoelectronics.

Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process

International Nuclear Information System (INIS)

Wang Yan-Rong; Yang Hong; Xu Hao; Wang Xiao-Lei; Luo Wei-Chun; Qi Lu-Wei; Zhang Shu-Xiang; Wang Wen-Wu; Yan Jiang; Zhu Hui-Long; Zhao Chao; Chen Da-Peng; Ye Tian-Chun

2015-01-01

A multi-deposition multi-annealing technique (MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device’s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown (TDDB) characteristics of positive channel metal oxide semiconductor (PMOS) under different MDMA process conditions, including the deposition/annealing (D and A) cycles, the D and A time, and the total annealing time. The results show that the increases of the number of D and A cycles (from 1 to 2) and D and A time (from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail (TTF) at 63.2% increases by about several times. However, too many D and A cycles (such as 4 cycles) make the equivalent oxide thickness (EOT) increase by about 1 Å and the TTF of PMOS worsen. Moreover, different D and A times and numbers of D and A cycles induce different breakdown mechanisms. (paper)

The Bipolar Field-Effect Transistor: XIII. Physical Realizations of the Transistor and Circuits (One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)

International Nuclear Information System (INIS)

Sah, C.-T.; Jie Binbin

2009-01-01

This paper reports the physical realization of the Bipolar Field-Effect Transistor (BiFET) and its one-transistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These examples include the one-MOS-gate on semi-infinite thick impure base transistor (the bulk transistor) and the impurethin-base Silicon-on-Insulator (SOI) transistor and the two-MOS-gates on thin base transistors (the FinFET and the Thin Film Transistor TFT). Figures are given with the cross-section views containing the electron and hole concentration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.

Lanthanum titanium perovskite compound: Thin film deposition and high frequency dielectric characterization

International Nuclear Information System (INIS)

Le Paven, C.; Lu, Y.; Nguyen, H.V.; Benzerga, R.; Le Gendre, L.; Rioual, S.; Benzegoutta, D.; Tessier, F.; Cheviré, F.

2014-01-01

Perovskite lanthanum titanium oxide thin films were deposited on (001) MgO, (001) LaAlO 3 and Pt(111)/TiO 2 /SiO 2 /(001)Si substrates by RF magnetron sputtering, using a La 2 Ti 2 O 7 homemade target sputtered under oxygen reactive plasma. The films deposited at 800 °C display a crystalline growth different than those reported on monoclinic ferroelectric La 2 Ti 2 O 7 films. X-ray photoelectron spectroscopy analysis shows the presence of titanium as Ti 4+ ions, with no trace of Ti 3+ , and provides a La/Ti ratio of 1.02. The depositions being performed from a La 2 Ti 2 O 7 target under oxygen rich plasma, the same composition (La 2 Ti 2 O 7 ) is proposed for the deposited films, with an unusual orthorhombic cell and Cmc2 1 space group. The films have a textured growth on MgO and Pt/Si substrates, and are epitaxially grown on LaAlO 3 substrate. The dielectric characterization displays stable values of the dielectric constant and of the losses in the frequency range [0.1–20] GHz. No variation of the dielectric constant has been observed when a DC electric field up to 250 kV/cm was applied, which does not match a classical ferroelectric behavior at high frequencies and room temperature for the proposed La 2 Ti 2 O 7 orthorhombic phase. At 10 GHz and room temperature, the dielectric constant of the obtained La 2 Ti 2 O 7 films is ε ∼ 60 and the losses are low (tanδ < 0.02). - Highlights: • Lanthanum titanium oxide films were deposited by reactive magnetron sputtering. • A La 2 Ti 2 O 7 chemical composition is proposed, with an unusual orthorhombic cell. • At 10 GHz, the dielectric losses are lower than 0.02. • No variation of the dielectric constant is observed under DC electric biasing

Radiation sensors based on the generation of mobile protons in organic dielectrics.

Science.gov (United States)

Kapetanakis, Eleftherios; Douvas, Antonios M; Argitis, Panagiotis; Normand, Pascal

2013-06-26

A sensing scheme based on mobile protons generated by radiation, including ionizing radiation (IonR), in organic gate dielectrics is investigated for the development of metal-insulator-semiconductor (MIS)-type dosimeters. Application of an electric field to the gate dielectric moves the protons and thereby alters the flat band voltage (VFB) of the MIS device. The shift in the VFB is proportional to the IonR-generated protons and, therefore, to the IonR total dose. Triphenylsulfonium nonaflate (TPSNF) photoacid generator (PAG)-containing poly(methyl methacrylate) (PMMA) polymeric films was selected as radiation-sensitive gate dielectrics. The effects of UV (249 nm) and gamma (Co-60) irradiations on the high-frequency capacitance versus the gate voltage (C-VG) curves of the MIS devices were investigated for different total dose values. Systematic improvements in sensitivity can be accomplished by increasing the concentration of the TPSNF molecules embedded in the polymeric matrix.

Computation of Dielectric Response in Molecular Solids for High Capacitance Organic Dielectrics.

Science.gov (United States)

Heitzer, Henry M; Marks, Tobin J; Ratner, Mark A

2016-09-20

The dielectric response of a material is central to numerous processes spanning the fields of chemistry, materials science, biology, and physics. Despite this broad importance across these disciplines, describing the dielectric environment of a molecular system at the level of first-principles theory and computation remains a great challenge and is of importance to understand the behavior of existing systems as well as to guide the design and synthetic realization of new ones. Furthermore, with recent advances in molecular electronics, nanotechnology, and molecular biology, it has become necessary to predict the dielectric properties of molecular systems that are often difficult or impossible to measure experimentally. In these scenarios, it is would be highly desirable to be able to determine dielectric response through efficient, accurate, and chemically informative calculations. A good example of where theoretical modeling of dielectric response would be valuable is in the development of high-capacitance organic gate dielectrics for unconventional electronics such as those that could be fabricated by high-throughput printing techniques. Gate dielectrics are fundamental components of all transistor-based logic circuitry, and the combination high dielectric constant and nanoscopic thickness (i.e., high capacitance) is essential to achieving high switching speeds and low power consumption. Molecule-based dielectrics offer the promise of cheap, flexible, and mass producible electronics when used in conjunction with unconventional organic or inorganic semiconducting materials to fabricate organic field effect transistors (OFETs). The molecular dielectrics developed to date typically have limited dielectric response, which results in low capacitances, translating into poor performance of the resulting OFETs. Furthermore, the development of better performing dielectric materials has been hindered by the current highly empirical and labor-intensive pace of synthetic

Thermal strain-induced dielectric anisotropy in Ba0.7Sr0.3TiO3 thin films grown on silicon-based substrates

International Nuclear Information System (INIS)

Zhu, X. H.; Defaye, E.; Aied, M.; Guigues, B.; Dubarry, C.

2009-01-01

Dielectric properties of Ba 0.7 Sr 0.3 TiO 3 (BST) thin films, which were prepared on silicon-based substrates by ion beam sputtering and postdeposition annealing method, were systematically investigated in different electrode configurations of metal-insulator-metal and coplanar interdigital capacitors. It was found that a large dielectric anisotropy exists in the films with better in-plane dielectric properties (higher dielectric permittivity and tunability) than those along the out-of-plane direction. The observed anisotropic dielectric responses are explained qualitatively in terms of a thermal strain effect that is related to dissimilar film strains along the in-plane and out-of-plane directions. Another reason for the dielectric anisotropy is due to different influences of the interfacial low-dielectric layer between the BST film and the substrate (metal electrode).

Thermal strain-induced dielectric anisotropy in Ba0.7Sr0.3TiO3 thin films grown on silicon-based substrates

Science.gov (United States)

Zhu, X. H.; Guigues, B.; Defaÿ, E.; Dubarry, C.; Aïd, M.

2009-07-01

Dielectric properties of Ba0.7Sr0.3TiO3 (BST) thin films, which were prepared on silicon-based substrates by ion beam sputtering and postdeposition annealing method, were systematically investigated in different electrode configurations of metal-insulator-metal and coplanar interdigital capacitors. It was found that a large dielectric anisotropy exists in the films with better in-plane dielectric properties (higher dielectric permittivity and tunability) than those along the out-of-plane direction. The observed anisotropic dielectric responses are explained qualitatively in terms of a thermal strain effect that is related to dissimilar film strains along the in-plane and out-of-plane directions. Another reason for the dielectric anisotropy is due to different influences of the interfacial low-dielectric layer between the BST film and the substrate (metal electrode).

An EELS sub-nanometer investigation of the dielectric gate stack for the realization of InGaAs based MOSFET devices

International Nuclear Information System (INIS)

Longo, P; Paterson, G W; Craven, A J; Holland, M C; Thayne, I G

2010-01-01

In this paper, a subnanometer investigation of the Ga 2 O 3 /GdGaO dielectric gate stack deposited onto InGaAs is presented. Results regarding the influence of the growth conditions on the interface region from a chemical and morphological point of view are presented. The chemical information reported in this paper has been obtained using electron energy loss spectroscopy (EELS) that was carried out in a scanning transmission electron microscope ((S)TEM) showing both spatial and depth resolution.

Growth and characteristics of PbS/polyvinyl alcohol nanocomposites for flexible high dielectric thin film applications

International Nuclear Information System (INIS)

Hmar, J.J.L.; Majumder, T.; Mondal, S.P.

2016-01-01

PbS/polyvinyl alcohol (PbS/PVA) nanocomposites have been grown by a chemical bath deposition process at various growth temperatures (60–100 °C). Transmission electron microscopy (TEM) study revealed the formation of PbS nanoparticles of diameter 6–20 nm encapsulated in PVA matrix. Optical band gap of the nanocomposite films have been found to decrease (1.45 eV–0.67 eV) with increase in growth temperature from 60 °C to 100 °C. The impedance measurements have been carried out by depositing the PbS/PVA films on indium tin oxide (ITO) coated flexible polyethylene terephthalate (PET) substrates. The room temperature dielectric permittivity and ac conductivity measurements have been carried out for ITO/PbS/PVA/Al devices deposited at various growth temperatures. The nanocomposite films demonstrate superior dielectric permittivity compare to pure PVA polymer. The flexibility studies of ITO/PbS/PVA/Al devices have been performed at different bending angles. - Highlights: • PbS nanoparticles of diameter 6–20 nm were grown in polyvinyl (PVA) matrix. • Optical band gap of nanocomposite films was varied from 1.45–0.67 eV. • The nanocomposite thin films demonstrated superior dielectric permittivity. • Flexibility study of thin film devices was performed at various bending angles.

Influence of stress on the structural and dielectric properties of rf magnetron sputtered zinc oxide thin film

Science.gov (United States)

Menon, Rashmi; Sreenivas, K.; Gupta, Vinay

2008-05-01

Highly c axis oriented zinc oxide (ZnO) thin films have been prepared on 1737 Corning glass substrate by planar rf magnetron sputtering under varying pressure (10-50mTorr) and different oxygen percentage (40%-100%) in reactive gas mixtures. The as-grown ZnO thin films were found to have stress over a wide range from -6×1010to-9×107dynes/cm2. The presence of stress depends strongly on processing conditions, and films become almost stress free under a unique combination of sputtering pressure and reactive gas composition. The studies show a correlation of stress with structural and electrical properties of the ZnO thin film. The stressed films possess high electrical conductivity and exhibits strong dielectric dispersion over a wide frequency (1kHz-1MHz). The dielectric constant ɛ'(ω) of stress free ZnO film was almost frequency independent and was close to the bulk value. The measured value of dc conductivity, σdc(ω) and ac conductivity σac(ω) of stress free ZnO film was 1.3×10-9 and 6.8×10-5Ω-1cm-1, respectively. The observed variation in the structural and electrical properties of ZnO thin film with stress has been analyzed in the light of growth kinetics.

Characteristics of sputtered Al-doped ZnO films for transparent electrodes of organic thin-film transistor

International Nuclear Information System (INIS)

Park, Yong Seob; Kim, Han-Ki

2011-01-01

Aluminum-doped ZnO (AZO) thin-films were deposited with various RF powers at room temperature by radio frequency (RF) magnetron sputtering method. The electrical properties of the AZO film were improved with the increasing RF power. These results can be explained by the improvement of the crystallinity in the AZO film. We fabricated the organic thin-film transistor (OTFT) of the bottom gate structure using pentacene active and poly-4-vinyl phenol gate dielectric layers on the indium tin oxide gate electrode, and estimated the device properties of the OTFTs including drain current-drain voltage (I D -V D ), drain current-gate voltage (I D -V G ), threshold voltage (V T ), on/off ratio and field effect mobility. The AZO film that grown at 160 W RF power exhibited low resistivity (1.54 x 10 -3 Ω.cm), high crystallinity and uniform surface morphology. The pentacene thin-film transistor using the AZO film that's fabricated at 160 W RF power exhibited good device performance such as the mobility of 0.94 cm 2 /V s and the on/off ratio of ∼ 10 5 . Consequently, the performance of the OTFT such as larger field-effect carrier mobility was determined the conductivity of the AZO source/drain (S/D) electrode. AZO films prepared at room temperature by the sputtering method are suitable for the S/D electrodes in the OTFTs.

Impedance spectroscopic and dielectric analysis of Ba0.7Sr0.3TiO3 thin films

International Nuclear Information System (INIS)

Rouahi, A.; Kahouli, A.; Sylvestre, A.; Defaÿ, E.; Yangui, B.

2012-01-01

Highlights: ► The material exhibits the contribution of both grain and grain boundaries in the electric response of Ba 0.7 Sr 0.3 TiO 3 . ► The plot of normalized complex dielectric modulus and impedance as a function of frequency exhibits both short and long-range conduction in the film. ► The frequency dependence of ac conductivity exhibits a polaron hopping mechanism with activation energy of 0.38 eV. ► The complex dielectric modulus analysis confirmed the presence of a non-Debye type of conductivity relaxation deduced from the KWW function. - Abstract: Polycrystalline Ba 0.7 Sr 0.3 TiO 3 thin film with Pt/BST/Pt/TiO 2 /SiO 2 structure was prepared by ion beam sputtering. The film was post annealed at 700 °C. The dielectric and electric modulus properties were studied by impedance spectroscopy over a wide frequency range [0.1–10 5 Hz] at different temperatures [175–350 °C]. The Nyquist plots (Z″ vs . Z′) show the contribution of both grain and grain boundaries at higher temperature on the electric response of BST thin films. Moreover, the resistance of grains decreases with the rise in temperature and the material exhibits a negative temperature coefficient of resistance. The electric modulus plot indicates the non-Debye type of dielectric relaxation. The values of the activation energy computed from both plots of Z″ and M″ are 0.86 eV and 0.81 eV respectively, which reveals that the species responsible for conduction are the same. The scaling behavior of M ″ /M ″ max shows the temperature independent nature of relaxation time. The plot of normalized complex dielectric modulus and impedance as a function of frequency exhibits both short and long-range conduction in the film.

Surface Modification of Solution-Processed ZrO2 Films through Double Coating for Pentacene Thin-Film Transistors

Science.gov (United States)

Kwon, Jin-Hyuk; Bae, Jin-Hyuk; Lee, Hyeonju; Park, Jaehoon

2018-03-01

We report the modification of surface properties of solution-processed zirconium oxide (ZrO2) dielectric films achieved by using double-coating process. It is proven that the surface properties of the ZrO2 film are modified through the double-coating process; the surface roughness decreases and the surface energy increases. The present surface modification of the ZrO2 film contributes to an increase in grain size of the pentacene film, thereby increasing the field-effect mobility and decreasing the threshold voltage of the pentacene thin-film transistors (TFTs) having the ZrO2 gate dielectric. Herein, the molecular orientation of pentacene film is also studied based on the results of contact angle and X-ray diffraction measurements. Pentacene molecules on the double-coated ZrO2 film are found to be more tilted than those on the single-coated ZrO2 film, which is attributed to the surface modification of the ZrO2 film. However, no significant differences are observed in insulating properties between the single-and the double-coated ZrO2 dielectric films. Consequently, the characteristic improvements of the pentacene TFTs with the double-coated ZrO2 gate dielectric film can be understood through the increase in pentacene grain size and the reduction in grain boundary density.

Atomic layer deposition grown composite dielectric oxides and ZnO for transparent electronic applications

International Nuclear Information System (INIS)

Gieraltowska, S.; Wachnicki, L.; Witkowski, B.S.; Godlewski, M.; Guziewicz, E.

2012-01-01

In this paper, we report on transparent transistor obtained using laminar structure of two high-k dielectric oxides (hafnium dioxide, HfO 2 and aluminum oxide, Al 2 O 3 ) and zinc oxide (ZnO) layer grown at low temperature (60 °C–100 °C) using Atomic Layer Deposition (ALD) technology. Our research was focused on the optimization of technological parameters for composite layers Al 2 O 3 /HfO 2 /Al 2 O 3 for thin film transistor structures with ZnO as a channel and a gate layer. We elaborate on the ALD growth of these oxides, finding that the 100 nm thick layers of HfO 2 and Al 2 O 3 exhibit fine surface flatness and required amorphous microstructure. Growth parameters are optimized for the monolayer growth mode and maximum smoothness required for gating.

Low-voltage bendable pentacene thin-film transistor with stainless steel substrate and polystyrene-coated hafnium silicate dielectric.

Science.gov (United States)

Yun, Dong-Jin; Lee, Seunghyup; Yong, Kijung; Rhee, Shi-Woo

2012-04-01

The hafnium silicate and aluminum oxide high-k dielectrics were deposited on stainless steel substrate using atomic layer deposition process and octadecyltrichlorosilane (OTS) and polystyrene (PS) were treated improve crystallinity of pentacene grown on them. Besides, the effects of the pentacene deposition condition on the morphologies, crystallinities and electrical properties of pentacene were characterized. Therefore, the surface treatment condition on dielectric and pentacene deposition conditions were optimized. The pentacene grown on polystyrene coated high-k dielectric at low deposition rate and temperature (0.2-0.3 Å/s and R.T.) showed the largest grain size (0.8-1.0 μm) and highest crystallinity among pentacenes deposited various deposition conditions, and the pentacene TFT with polystyrene coated high-k dielectric showed excellent device-performance. To decrease threshold voltage of pentacene TFT, the polystyrene-thickness on high-k dielectric was controlled using different concentration of polystyrene solution. As the polystyrene-thickness on hafnium silicate decreases, the dielectric constant of polystyrene/hafnium silicate increases, while the crystallinity of pentacene grown on polystyrene/hafnium silicate did not change. Using low-thickness polystyrene coated hafnium silicate dielectric, the high-performance and low voltage operating (pentacene thin film transistor (μ: ~2 cm(2)/(V s), on/off ratio, >1 × 10(4)) and complementary inverter (DC gains, ~20) could be fabricated.

Changes of optical, dielectric, and structural properties of Si15Sb85 phase change memory thin films under different initializing laser power

International Nuclear Information System (INIS)

Huang Huan; Zhang Lei; Wang Yang; Han Xiaodong; Wu Yiqun; Zhang Ze; Gan Fuxi

2011-01-01

Research highlights: → We study the optical, dielectric, and structural characteristics of Si 15 Sb 85 phase change memory thin films under a moving continuous-wave laser initialization. → The optical and dielectric constants, absorption coefficient of Si 15 Sb 85 change regularly with the increasing laser power. → The optical band gaps of Si 15 Sb 85 irradiated upon different power lasers were calculated. → HRTEM images of the samples were observed and the changes of optical and dielectric constants are determined by crystalline structures changes of the films. - Abstract: The optical, dielectric, and structural characteristics of Si 15 Sb 85 phase change memory thin films under a moving continuous-wave laser initialization are studied by using spectroscopic ellipsometry and high-resolution transmission electron microscopy. The dependence of complex refractive index, dielectric functions, absorption coefficient, and optical band gap of the films on its crystallization extents formed by the different initialization laser power are analyzed in detail. The structural change from as-deposited amorphous phase to distorted rhombohedra-Sb-like crystalline structure with the increase of initialization laser power is clearly observed with sub-nanometer resolution. The optical and dielectric constants, the relationship between them, and the local atomic arrangements of this new phase change material can help explain the phase change mechanism and design the practical phase change memory devices.

Structure and performance of dielectric films based on self-assembled nanocrystals with a high dielectric constant.

Science.gov (United States)

Huang, Limin; Liu, Shuangyi; Van Tassell, Barry J; Liu, Xiaohua; Byro, Andrew; Zhang, Henan; Leland, Eli S; Akins, Daniel L; Steingart, Daniel A; Li, Jackie; O'Brien, Stephen

2013-10-18

Self-assembled films built from nanoparticles with a high dielectric constant are attractive as a foundation for new dielectric media with increased efficiency and range of operation, due to the ability to exploit nanofabrication techniques and emergent electrical properties originating from the nanoscale. However, because the building block is a discrete one-dimensional unit, it becomes a challenge to capture potential enhancements in dielectric performance in two or three dimensions, frequently due to surface effects or the presence of discontinuities. This is a recurring theme in nanoparticle film technology when applied to the realm of thin film semiconductor and device electronics. We present the use of chemically synthesized (Ba,Sr)TiO3 nanocrystals, and a novel deposition-polymerization technique, as a means to fabricate the dielectric layer. The effective dielectric constant of the film is tunable according to nanoparticle size, and effective film dielectric constants of up to 34 are enabled. Wide area and multilayer dielectrics of up to 8 cm(2) and 190 nF are reported, for which the building block is an 8 nm nanocrystal. We describe models for assessing dielectric performance, and distinct methods for improving the dielectric constant of a nanocrystal thin film. The approach relies on evaporatively driven assembly of perovskite nanocrystals with uniform size distributions in a tunable 7-30 nm size range, coupled with the use of low molecular weight monomer/polymer precursor chemistry that can infiltrate the porous nanocrystal thin film network post assembly. The intercrystal void space (low k dielectric volume fraction) is minimized, while simultaneously promoting intercrystal connectivity and maximizing volume fraction of the high k dielectric component. Furfuryl alcohol, which has good affinity to the surface of (Ba,Sr)TiO3 nanocrystals and miscibility with a range of solvents, is demonstrated to be ideal for the production of nanocomposites. The

Comparative analysis of the effects of tantalum doping and annealing on atomic layer deposited (Ta2O5)x(Al2O3)1−x as potential gate dielectrics for GaN/AlxGa1−xN/GaN high electron mobility transistors

International Nuclear Information System (INIS)

Partida-Manzanera, T.; Roberts, J. W.; Sedghi, N.; Potter, R. J.; Bhat, T. N.; Zhang, Z.; Tan, H. R.; Dolmanan, S. B.; Tripathy, S.

2016-01-01

This paper describes a method to optimally combine wide band gap Al 2 O 3 with high dielectric constant (high-κ) Ta 2 O 5 for gate dielectric applications. (Ta 2 O 5 ) x (Al 2 O 3 ) 1−x thin films deposited by thermal atomic layer deposition (ALD) on GaN-capped Al x Ga 1−x N/GaN high electron mobility transistor (HEMT) structures have been studied as a function of the Ta 2 O 5 molar fraction. X-ray photoelectron spectroscopy shows that the bandgap of the oxide films linearly decreases from 6.5 eV for pure Al 2 O 3 to 4.6 eV for pure Ta 2 O 5 . The dielectric constant calculated from capacitance-voltage measurements also increases linearly from 7.8 for Al 2 O 3 up to 25.6 for Ta 2 O 5 . The effect of post-deposition annealing in N 2 at 600 °C on the interfacial properties of undoped Al 2 O 3 and Ta-doped (Ta 2 O 5 ) 0.12 (Al 2 O 3 ) 0.88 films grown on GaN-HEMTs has been investigated. These conditions are analogous to the conditions used for source/drain contact formation in gate-first HEMT technology. A reduction of the Ga-O to Ga-N bond ratios at the oxide/HEMT interfaces is observed after annealing, which is attributed to a reduction of interstitial oxygen-related defects. As a result, the conduction band offsets (CBOs) of the Al 2 O 3 /GaN-HEMT and (Ta 2 O 5 ) 0.16 (Al 2 O 3 ) 0.84 /GaN-HEMT samples increased by ∼1.1 eV to 2.8 eV and 2.6 eV, respectively, which is advantageous for n-type HEMTs. The results demonstrate that ALD of Ta-doped Al 2 O 3 can be used to control the properties of the gate dielectric, allowing the κ-value to be increased, while still maintaining a sufficient CBO to the GaN-HEMT structure for low leakage currents

Tunnel field-effect transistor with two gated intrinsic regions

Directory of Open Access Journals (Sweden)

Y. Zhang

2014-07-01

Full Text Available In this paper, we propose and validate (using simulations a novel design of silicon tunnel field-effect transistor (TFET, based on a reverse-biased p+-p-n-n+ structure. 2D device simulation results show that our devices have significant improvements of switching performance compared with more conventional devices based on p-i-n structure. With independent gate voltages applied to two gated intrinsic regions, band-to-band tunneling (BTBT could take place at the p-n junction, and no abrupt degenerate doping profile is required. We developed single-side-gate (SSG structure and double-side-gate (DSG structure. SSG devices with HfO2 gate dielectric have a point subthreshold swing of 9.58 mV/decade, while DSG devices with polysilicon gate electrode material and HfO2 gate dielectric have a point subthreshold swing of 16.39 mV/decade. These DSG devices have ON-current of 0.255 μA/μm, while that is lower for SSG devices. Having two nano-scale independent gates will be quite challenging to realize with good uniformity across the wafer and the improved behavior of our TFET makes it a promising steep-slope switch candidate for further investigations.

Stability Study of Flexible 6,13-Bis(triisopropylsilylethynylpentacene Thin-Film Transistors with a Cross-Linked Poly(4-vinylphenol/Yttrium Oxide Nanocomposite Gate Insulator

Directory of Open Access Journals (Sweden)

Jin-Hyuk Kwon

2016-03-01

Full Text Available We investigated the electrical and mechanical stability of flexible 6,13-bis(triisopropylsilylehtynylpentacene (TIPS-pentacene thin-film transistors (TFTs that were fabricated on polyimide (PI substrates using cross-linked poly(4-vinylphenol (c-PVP and c-PVP/yttrium oxide (Y2O3 nanocomposite films as gate insulators. Compared with the electrical characteristics of TIPS-pentacene TFTs with c-PVP insulators, the TFTs with c-PVP/Y2O3 nanocomposite insulators exhibited enhancements in the drain current and the threshold voltage due to an increase in the dielectric capacitance. In electrical stability experiments, a gradual decrease in the drain current and a negative shift in the threshold voltage occurred during prolonged bias stress tests, but these characteristic variations were comparable for both types of TFT. On the other hand, the results of mechanical bending tests showed that the characteristic degradation of the TIPS-pentacene TFTs with c-PVP/Y2O3 nanocomposite insulators was more critical than that of the TFTs with c-PVP insulators. In this study, the detrimental effect of the nanocomposite insulator on the mechanical stability of flexible TIPS-pentacene TFTs was found to be caused by physical adhesion of TIPS-pentacene molecules onto the rough surfaces of the c-PVP/Y2O3 nanocomposite insulator. These results indicate that the dielectric and morphological properties of polymeric nanocomposite insulators are significant when considering practical applications of flexible electronics operated at low voltages.

Effects of thermal annealing on the electrical characteristics of In-Ga-Zn-O thin-film transistors with Al2O3 gate dielectric

International Nuclear Information System (INIS)

Zhang, Wen-Peng; Chen, Sun; Qian, Shi-Bing; Ding, Shi-Jin

2015-01-01

We studied how the performance of In–Ga–Zn–O (IGZO) thin film transistors (TFTs) with Al 2 O 3 gate insulator was affected by post-fabrication annealing temperature and annealing time. At a fixed annealing time of 2 min, the IGZO TFT exhibited the best transfer and output characteristics in the case of 300 °C in N 2 atmosphere, which is attributed to the achievement of appropriate carrier concentration and Hall mobility in the IGZO film. Further, it was found that both of the carrier concentration and Hall mobility in the IGZO film increased with the increment of annealing temperature. For the annealing temperature of 300 °C, the performance of the IGZO TFT was further improved by extending annealing time to 5 min, i.e., the field effect mobility, sub-threshold swing and on/off current ratio were 11.6 cm 2 /(V · s), 0.42 V dec −1 and 10 6 , respectively. The underlying mechanism was discussed. (paper)

Periodicity effects on compound waves guided by a thin metal slab sandwiched between two periodically nonhomogeneous dielectric materials

Science.gov (United States)

Chiadini, Francesco; Fiumara, Vincenzo; Scaglione, Antonio; Lakhtakia, Akhlesh

2017-10-01

Surface-plasmon-polariton waves can be compounded when a sufficiently thin metal layer is sandwiched between two half spaces filled with dissimilar periodically nonhomogeneous dielectric materials. We solved the boundary-value problem for compound waves guided by a layer of a homogeneous and isotropic metal sandwiched between a structurally chiral material (SCM) and a periodically multilayered isotropic dielectric (PMLID) material. We found that the periodicities of the PMLID material and the SCM are crucial to excite a multiplicity of compound guided waves arising from strong coupling between the two interfaces.

Investigating degradation behavior of hole-trapping effect under static and dynamic gate-bias stress in a dual gate a-InGaZnO thin film transistor with etch stop layer

Energy Technology Data Exchange (ETDEWEB)

Liao, Po-Yung [Department of Physics, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang3708@gmail.com [Department of Physics, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan (China); Hsieh, Tien-Yu [Department of Physics, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Tsai, Ming-Yen; Chen, Bo-Wei; Chu, Ann-Kuo [Department of Photonics, National Sun Yat-Sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Chou, Cheng-Hsu; Chang, Jung-Fang [Product Technology Center, Chimei Innolux Corp., Tainan 741, Taiwan (China)

2016-03-31

The degree of degradation between the amorphous-indium–gallium–zinc oxide (a-IGZO) thin film transistor (TFT) using the top-gate only or bottom-gate only is compared. Under negative gate bias illumination stress (NBIS), the threshold voltage (V{sub T}) after bottom-gate NBIS monotonically shifts in the negative direction, whereas top-gate NBIS operation exhibits on-state current increases without V{sub T} shift. Such anomalous degradation behavior of NBIS under top-gate operation is due to hole-trapping in the etch stop layer above the central portion of the channel. These phenomena can be ascribed to the screening of the electric field by redundant source/drain electrodes. In addition, the device degradation of dual gate a-IGZO TFT stressed with different top gate pulse waveforms is investigated. It is observed that the degradation is dependent on the frequency of the top gate pulses. The V{sub T} shift increases with decreasing frequency, indicating the hole mobility of IGZO is low. - Highlights: • Static and dynamic gate bias stresses are imposed on dual gate InGaZnO TFTs. • Top-gate NBIS operation exhibits on-state current increases without VT shift. • The degradation behavior of top-gate NBIS is due to hole-trapping in the ESL. • The degradation is dependent on the frequency of the top gate pulses. • The V{sub T} shift increases with decreasing frequency of the top gate pulses.

Investigating degradation behavior of hole-trapping effect under static and dynamic gate-bias stress in a dual gate a-InGaZnO thin film transistor with etch stop layer

International Nuclear Information System (INIS)

Liao, Po-Yung; Chang, Ting-Chang; Hsieh, Tien-Yu; Tsai, Ming-Yen; Chen, Bo-Wei; Chu, Ann-Kuo; Chou, Cheng-Hsu; Chang, Jung-Fang

2016-01-01

The degree of degradation between the amorphous-indium–gallium–zinc oxide (a-IGZO) thin film transistor (TFT) using the top-gate only or bottom-gate only is compared. Under negative gate bias illumination stress (NBIS), the threshold voltage (V T ) after bottom-gate NBIS monotonically shifts in the negative direction, whereas top-gate NBIS operation exhibits on-state current increases without V T shift. Such anomalous degradation behavior of NBIS under top-gate operation is due to hole-trapping in the etch stop layer above the central portion of the channel. These phenomena can be ascribed to the screening of the electric field by redundant source/drain electrodes. In addition, the device degradation of dual gate a-IGZO TFT stressed with different top gate pulse waveforms is investigated. It is observed that the degradation is dependent on the frequency of the top gate pulses. The V T shift increases with decreasing frequency, indicating the hole mobility of IGZO is low. - Highlights: • Static and dynamic gate bias stresses are imposed on dual gate InGaZnO TFTs. • Top-gate NBIS operation exhibits on-state current increases without VT shift. • The degradation behavior of top-gate NBIS is due to hole-trapping in the ESL. • The degradation is dependent on the frequency of the top gate pulses. • The V T shift increases with decreasing frequency of the top gate pulses.

Radiation and Internal Charging Environments for Thin Dielectrics in Interplanetary Space

Science.gov (United States)

Minow, Joseph I.; Parker, Linda Neergaard; Altstatt, Richard L.

2004-01-01

Spacecraft designs using solar sails for propulsion or thin membranes to shade instruments from the sun to achieve cryogenic operating temperatures are being considered for a number of missions in the next decades. A common feature of these designs are thin dielectric materials that will be exposed to the solar wind, solar energetic particle events, and the distant magnetotail plasma environments encountered by spacecraft in orbit about the Earth-Sun L2 point. This paper will discuss the relevant radiation and internal charging environments developed to support spacecraft design for both total dose radiation effects as well as dose rate dependent phenomenon, such as internal charging in the solar wind and distant magnetotail environments. We will describe the development of radiation and internal charging environment models based on nearly a complete solar cycle of Ulysses solar wind plasma measurements over a complete range of heliocentric latitudes and the early years of the Geotail mission where distant magnetotail plasma environments were sampled beyond X(sub GSE) = -100 Re to nearly L2 (X(sub GSE) -236 Re). Example applications of the environment models are shown to demonstrate the radiation and internal charging environments of thin materials exposed to the interplanetary space plasma environments.

Lanthanum titanium perovskite compound: Thin film deposition and high frequency dielectric characterization

Energy Technology Data Exchange (ETDEWEB)

Le Paven, C., E-mail: claire.lepaven@univ-rennes1.fr [Institut d' Electronique et de Télécommunications de Rennes (IETR, UMR-CNRS 6164), Equipe Matériaux Fonctionnels, IUT Saint Brieuc, Université de Rennes 1, 22000 Saint Brieuc (France); Lu, Y. [Institut d' Electronique et de Télécommunications de Rennes (IETR, UMR-CNRS 6164), Equipe Matériaux Fonctionnels, IUT Saint Brieuc, Université de Rennes 1, 22000 Saint Brieuc (France); Nguyen, H.V. [Institut d' Electronique et de Télécommunications de Rennes (IETR, UMR-CNRS 6164), Equipe Matériaux Fonctionnels, IUT Saint Brieuc, Université de Rennes 1, 22000 Saint Brieuc (France); CEA LETI, Minatec Campus, 38054 Grenoble (France); Benzerga, R.; Le Gendre, L. [Institut d' Electronique et de Télécommunications de Rennes (IETR, UMR-CNRS 6164), Equipe Matériaux Fonctionnels, IUT Saint Brieuc, Université de Rennes 1, 22000 Saint Brieuc (France); Rioual, S. [Laboratoire de Magnétisme de Brest (EA CNRS 4522), Université de Bretagne Occidentale, 29000 Brest (France); Benzegoutta, D. [Institut des Nanosciences de Paris (INSP, UMR CNRS 7588), Université Pierre et Marie Curie, 75005 Paris (France); Tessier, F.; Cheviré, F. [Institut des Sciences Chimiques de Rennes (ISCR, UMR-CNRS 6226), Equipe Verres et Céramiques, Université de Rennes 1, 35000 Rennes (France); and others

2014-02-28

Perovskite lanthanum titanium oxide thin films were deposited on (001) MgO, (001) LaAlO{sub 3} and Pt(111)/TiO{sub 2}/SiO{sub 2}/(001)Si substrates by RF magnetron sputtering, using a La{sub 2}Ti{sub 2}O{sub 7} homemade target sputtered under oxygen reactive plasma. The films deposited at 800 °C display a crystalline growth different than those reported on monoclinic ferroelectric La{sub 2}Ti{sub 2}O{sub 7} films. X-ray photoelectron spectroscopy analysis shows the presence of titanium as Ti{sup 4+} ions, with no trace of Ti{sup 3+}, and provides a La/Ti ratio of 1.02. The depositions being performed from a La{sub 2}Ti{sub 2}O{sub 7} target under oxygen rich plasma, the same composition (La{sub 2}Ti{sub 2}O{sub 7}) is proposed for the deposited films, with an unusual orthorhombic cell and Cmc2{sub 1} space group. The films have a textured growth on MgO and Pt/Si substrates, and are epitaxially grown on LaAlO{sub 3} substrate. The dielectric characterization displays stable values of the dielectric constant and of the losses in the frequency range [0.1–20] GHz. No variation of the dielectric constant has been observed when a DC electric field up to 250 kV/cm was applied, which does not match a classical ferroelectric behavior at high frequencies and room temperature for the proposed La{sub 2}Ti{sub 2}O{sub 7} orthorhombic phase. At 10 GHz and room temperature, the dielectric constant of the obtained La{sub 2}Ti{sub 2}O{sub 7} films is ε ∼ 60 and the losses are low (tanδ < 0.02). - Highlights: • Lanthanum titanium oxide films were deposited by reactive magnetron sputtering. • A La{sub 2}Ti{sub 2}O{sub 7} chemical composition is proposed, with an unusual orthorhombic cell. • At 10 GHz, the dielectric losses are lower than 0.02. • No variation of the dielectric constant is observed under DC electric biasing.

Flexible suspended gate organic thin-film transistors for ultra-sensitive pressure detection

Science.gov (United States)

Zang, Yaping; Zhang, Fengjiao; Huang, Dazhen; Gao, Xike; di, Chong-An; Zhu, Daoben

2015-03-01

The utilization of organic devices as pressure-sensing elements in artificial intelligence and healthcare applications represents a fascinating opportunity for the next-generation electronic products. To satisfy the critical requirements of these promising applications, the low-cost construction of large-area ultra-sensitive organic pressure devices with outstanding flexibility is highly desired. Here we present flexible suspended gate organic thin-film transistors (SGOTFTs) as a model platform that enables ultra-sensitive pressure detection. More importantly, the unique device geometry of SGOTFTs allows the fine-tuning of their sensitivity by the suspended gate. An unprecedented sensitivity of 192 kPa-1, a low limit-of-detection pressure of <0.5 Pa and a short response time of 10 ms were successfully realized, allowing the real-time detection of acoustic waves. These excellent sensing properties of SGOTFTs, together with their advantages of facile large-area fabrication and versatility in detecting various pressure signals, make SGOTFTs a powerful strategy for spatial pressure mapping in practical applications.

Degradation of Ultra-Thin Gate Oxide NMOSFETs under CVDT and SHE Stresses

International Nuclear Information System (INIS)

Shi-Gang, Hu; Yan-Rong, Cao; Yue, Hao; Xiao-Hua, Ma; Chi, Chen; Xiao-Feng, Wu; Qing-Jun, Zhou

2008-01-01

Degradation of device under substrate hot-electron (SHE) and constant voltage direct-tunnelling (CVDT) stresses are studied using NMOSFET with 1.4-nm gate oxides. The degradation of device parameters and the degradation of the stress induced leakage current (SILC) under these two stresses are reported. The emphasis of this paper is on SILC and breakdown of ultra-thin-gate-oxide under these two stresses. SILC increases with stress time and several soft breakdown events occur during direct-tunnelling (DT) stress. During SHE stress, SILC firstly decreases with stress time and suddenly jumps to a high level, and no soft breakdown event is observed. For DT injection, the positive hole trapped in the oxide and hole direct-tunnelling play important roles in the breakdown. For SHE injection, it is because injected hot electrons accelerate the formation of defects and these defects formed by hot electrons induce breakdown. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Structural and dielectric characterization of sputtered Tantalum Titanium Oxide thin films for high temperature capacitor applications

Energy Technology Data Exchange (ETDEWEB)

Rouahi, A., E-mail: rouahi_ahlem@yahoo.fr [Univ. Grenoble Alpes, G2Elab, F-38000 (France); Laboratoire Matériaux Organisation et Propriétés (LMOP), Université de Tunis El Manar, 2092 Tunis (Tunisia); Challali, F. [Laboratoire des Sciences des Procédés et des Matériaux (LSPM)-CNRS-UPR3407, Université Paris13, 99 Avenue Jean-Baptiste Clément, 93430, Villetaneuse (France); Dakhlaoui, I. [Laboratoire Matériaux Organisation et Propriétés (LMOP), Université de Tunis El Manar, 2092 Tunis (Tunisia); Vallée, C. [CNRS, LTM, CEA-LETI, F-38000 Grenoble (France); Salimy, S. [Institut des Matériaux Jean Rouxel (IMN) UMR CNRS 6502, Université de Nantes, 2, rue de la Houssinière, B.P. 32229, 44322, Nantes, Cedex 3 (France); Jomni, F.; Yangui, B. [Laboratoire Matériaux Organisation et Propriétés (LMOP), Université de Tunis El Manar, 2092 Tunis (Tunisia); Besland, M.P.; Goullet, A. [Institut des Matériaux Jean Rouxel (IMN) UMR CNRS 6502, Université de Nantes, 2, rue de la Houssinière, B.P. 32229, 44322, Nantes, Cedex 3 (France); Sylvestre, A. [Univ. Grenoble Alpes, G2Elab, F-38000 (France)

2016-05-01

In this study, the dielectric properties of metal-oxide-metal capacitors based on Tantalum Titanium Oxide (TiTaO) thin films deposited by reactive magnetron sputtering on aluminum bottom electrode are investigated. The structure of the films was characterized by Atomic Force Microscopy, X-ray diffraction and X-ray photoelectron spectroscopy. The dielectric properties of TiTaO thin films were studied by complex impedance spectroscopy over a wide frequency range (10{sup -2} - to 10{sup 5} Hz) and temperatures in -50 °C to 325 °C range. The contributions of different phases, phases’ boundaries and conductivity effect were highlighted by Cole – Cole diagram (ε” versus ε’). Two relaxation processes have been identified in the electric modulus plot. A first relaxation process appears at low temperature with activation energy of 0.37 eV and it is related to the motion of Ti{sup 4+} (Skanavi’s model). A second relaxation process at high temperature is related to Maxwell-Wagner-Sillars relaxation with activation energy of 0.41 eV. - Highlights: • Titanium Tantalum Oxide thin films are grown on Aluminum substrate. • The existence of phases was confirmed by X-ray photoelectron spectroscopy. • Conductivity effect appears in Cole-Cole plot. • At low temperatures, a relaxation phenomenon obeys to Skanavi’s model. • Maxwell-Wagner-Sillars polarization is processed at high temperatures.

Redefinition of the self-bias voltage in a dielectrically shielded thin sheath RF discharge

Science.gov (United States)

Ho, Teck Seng; Charles, Christine; Boswell, Rod

2018-05-01

In a geometrically asymmetric capacitively coupled discharge where the powered electrode is shielded from the plasma by a layer of dielectric material, the self-bias manifests as a nonuniform negative charging in the dielectric rather than on the blocking capacitor. In the thin sheath regime where the ion transit time across the powered sheath is on the order of or less than the Radiofrequency (RF) period, the plasma potential is observed to respond asymmetrically to extraneous impedances in the RF circuit. Consequently, the RF waveform on the plasma-facing surface of the dielectric is unknown, and the behaviour of the powered sheath is not easily predictable. Sheath circuit models become inadequate for describing this class of discharges, and a comprehensive fluid, electrical, and plasma numerical model is employed to accurately quantify this behaviour. The traditional definition of the self-bias voltage as the mean of the RF waveform is shown to be erroneous in this regime. Instead, using the maxima of the RF waveform provides a more rigorous definition given its correlation with the ion dynamics in the powered sheath. This is supported by a RF circuit model derived from the computational fluid dynamics and plasma simulations.

Analysis of mobile ionic impurities in polyvinylalcohol thin films by thermal discharge current and dielectric impedance spectroscopy

Directory of Open Access Journals (Sweden)

M. Egginger

2012-12-01

Full Text Available Polyvinylalcohol (PVA is a water soluble polymer frequently applied in the field of organic electronics for insulating thin film layers. By-products of PVA synthesis are sodium acetate ions which contaminate the polymer material and can impinge on the electronic performance when applied as interlayer dielectrics in thin film transistors. Uncontrollable voltage instabilities and unwanted hysteresis effects are regularly reported with PVA devices. An understanding of these effects require knowledge about the electronic dynamics of the ionic impurities and their influence on the dielectric properties of PVA. Respective data, which are largely unknown, are being presented in this work. Experimental investigations were performed from room temperature to 125°C on drop-cast PVA films of three different quality grades. Data from thermal discharge current (TDC measurements, polarization experiments, and dielectric impedance spectroscopy concurrently show evidence of mobile ionic carriers. Results from TDC measurements indicate the existence of an intrinsic, build-in electric field of pristine PVA films. The field is caused by asymmetric ionic double layer formation at the two different film-interfaces (substrate/PVA and PVA/air. The mobile ions cause strong electrode polarization effects which dominate dielectric impedance spectra. From a quantitative electrode polarization analysis of isothermal impedance spectra temperature dependent values for the concentration, the mobility and conductivity together with characteristic relaxation times of the mobile carriers are given. Also shown are temperature dependent results for the dc-permittivity and the electronic resistivity. The obtained results demonstrate the feasibility to partly remove contaminants from a PVA solution by dialysis cleaning. Such a cleaning procedure reduces the values of ion concentration, conductivity and relaxation frequency.

PREFACE: Proceedings Symposium G of E-MRS Spring Meeting on Fundamentals and Technology of Multifunctional Oxide Thin Films

Science.gov (United States)

2010-07-01

Oxide materials exhibit a large variety of functional properties that are useful in a plethora of applications. Symposium G focused on oxide thin films that include dielectric or switching properties. Its program mirrored very well the strong worldwide search for high-K thin films for gate, memory, and on-chip capacitors, as well as the emerging field of functional thin films for MEMS. A complete session was devoted to the colossal effect of dielectric response in (Ca,Cu)TiO3, representing the major European research groups in this field. A comprehensive overview on this phenomenon was given by D Sinclair J Wolfman presented the latest results on CCTO thin films obtained by wafer scale pulsed laser deposition. A Loidl showed the analytical power of dielectric spectroscopy when covering the complete frequency range from 1-1012 Hz, i.e. from space charge to phonon contributions at the example of CCTO. Another session was devoted to applications in non-volatile memories, covering various effects including ferroelectric and resistive switching, the complex behavior of oxide tunnel junctions (H Kohlstedt), the possibility to manipulate the magnetic state of a 2d-electron gas by the polarization of an adjacent ferroelectric gate (I Stolitchnov). Latest advancements in ALD processing for high-K thin films in dynamic RAM were reported by S Ramanathan. The advancement of piezoelectric PZT thin film MEMS devices was well documented by outstanding talks on their developments in industry (M Klee, F Tyholdt), new possibilities in GHz filters (T Matshushima), advancements in sol-gel processing (B Tuttle, H Suzuki), and low temperature integration approaches by UV light curing (S Trolier-McKinstry). Recent advances in incipient ferroelectric thin films and nano composites for tunable capacitors in microwave applications were present by A Vorobiev and T Yamada. Integrated electro-optics is another field to be conquered by thin film structures. The impressive progress made in this

Highly stretchable carbon nanotube transistors enabled by buckled ion gel gate dielectrics

International Nuclear Information System (INIS)

Wu, Meng-Yin; Chang, Tzu-Hsuan; Ma, Zhenqiang; Zhao, Juan; Xu, Feng; Jacobberger, Robert M.; Arnold, Michael S.

2015-01-01

Deformable field-effect transistors (FETs) are expected to facilitate new technologies like stretchable displays, conformal devices, and electronic skins. We previously demonstrated stretchable FETs based on buckled thin films of polyfluorene-wrapped semiconducting single-walled carbon nanotubes as the channel, buckled metal films as electrodes, and unbuckled flexible ion gel films as the dielectric. The FETs were stretchable up to 50% without appreciable degradation in performance before failure of the ion gel film. Here, we show that by buckling the ion gel, the integrity and performance of the nanotube FETs are extended to nearly 90% elongation, limited by the stretchability of the elastomer substrate. The FETs maintain an on/off ratio of >10 4 and a field-effect mobility of 5 cm 2 V −1 s −1 under elongation and demonstrate invariant performance over 1000 stretching cycles

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

Science.gov (United States)

Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

2009-08-01

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

Preferential growth and enhanced dielectric properties of Ba0.7Sr0.3TiO3 thin films with preannealed Pt bottom electrode

International Nuclear Information System (INIS)

Zhu Xiaohong; Ren Yinjuan; Zhang Caiyun; Zhu Jiliang; Zhu Jianguo; Xiao Dingquan; Defaÿ, Emmanuel; Aïd, Marc

2013-01-01

Ba 0.7 Sr 0.3 TiO 3 (BST) thin films, about 100 nm in thickness, were prepared on unannealed and 700 °C-preannealed Pt bottom electrodes by the ion beam sputtering and post-deposition annealing method. It was found that the preannealed Pt layer has a more compact structure, making it not only a bottom electrode but also a good template for high-quality BST thin film growth. The BST films deposited on preannealed Pt bottom electrodes showed (0 0 l)-preferred orientation, dense and uniform microstructure with no intermediate phase formed at the film/electrode interface, and thus enhanced dielectric properties. As a result, the typical relative dielectric constant and tunability (under a dc electric field of 1 MV cm −1 ) reach 180 and 50.1%, respectively, for the BST thin films with preannealed Pt bottom electrodes, which are significantly higher than those (166 and 41.3%, respectively) for the BST thin films deposited on unannealed Pt bottom electrodes. (paper)

Preferential growth and enhanced dielectric properties of Ba0.7Sr0.3TiO3 thin films with preannealed Pt bottom electrode

Science.gov (United States)

Zhu, Xiaohong; Defaÿ, Emmanuel; Aïd, Marc; Ren, Yinjuan; Zhang, Caiyun; Zhu, Jiliang; Zhu, Jianguo; Xiao, Dingquan

2013-03-01

Ba0.7Sr0.3TiO3 (BST) thin films, about 100 nm in thickness, were prepared on unannealed and 700 °C-preannealed Pt bottom electrodes by the ion beam sputtering and post-deposition annealing method. It was found that the preannealed Pt layer has a more compact structure, making it not only a bottom electrode but also a good template for high-quality BST thin film growth. The BST films deposited on preannealed Pt bottom electrodes showed (0 0 l)-preferred orientation, dense and uniform microstructure with no intermediate phase formed at the film/electrode interface, and thus enhanced dielectric properties. As a result, the typical relative dielectric constant and tunability (under a dc electric field of 1 MV cm-1) reach 180 and 50.1%, respectively, for the BST thin films with preannealed Pt bottom electrodes, which are significantly higher than those (166 and 41.3%, respectively) for the BST thin films deposited on unannealed Pt bottom electrodes.

Dielectric properties of DC reactive magnetron sputtered Al{sub 2}O{sub 3} thin films

Energy Technology Data Exchange (ETDEWEB)

Prasanna, S. [Thin Film Center, Department of Physics, PSG College of Technology, Coimbatore, 641 004 (India); Mohan Rao, G. [Department of Instrumentation, Indian Institute of Science (IISc), Bangalore, 560 012 (India); Jayakumar, S., E-mail: s_jayakumar_99@yahoo.com [Thin Film Center, Department of Physics, PSG College of Technology, Coimbatore, 641 004 (India); Kannan, M.D. [Thin Film Center, Department of Physics, PSG College of Technology, Coimbatore, 641 004 (India); Ganesan, V. [Low Temperature Lab, UGC-DAE Consortium for Scientific Research (CSR), Indore, 452 017 (India)

2012-01-31

Alumina (Al{sub 2}O{sub 3}) thin films were sputter deposited over well-cleaned glass and Si < 100 > substrates by DC reactive magnetron sputtering under various oxygen gas pressures and sputtering powers. The composition of the films was analyzed by X-ray photoelectron spectroscopy and an optimal O/Al atomic ratio of 1.59 was obtained at a reactive gas pressure of 0.03 Pa and sputtering power of 70 W. X-ray diffraction results revealed that the films were amorphous until 550 Degree-Sign C. The surface morphology of the films was studied using scanning electron microscopy and the as-deposited films were found to be smooth. The topography of the as-deposited and annealed films was analyzed by atomic force microscopy and a progressive increase in the rms roughness of the films from 3.2 nm to 4.53 nm was also observed with increase in the annealing temperature. Al-Al{sub 2}O{sub 3}-Al thin film capacitors were then fabricated on glass substrates to study the effect of temperature and frequency on the dielectric property of the films. Temperature coefficient of capacitance, AC conductivity and activation energy were determined and the results are discussed. - Highlights: Black-Right-Pointing-Pointer Al{sub 2}O{sub 3} thin films were deposited by DC reactive magnetron sputtering. Black-Right-Pointing-Pointer The films were found to be amorphous up to annealing temperature of 550 C. Black-Right-Pointing-Pointer An increase in rms roughness of the films was observed with annealing. Black-Right-Pointing-Pointer Al-Al{sub 2}O{sub 3}-Al thin film capacitors were fabricated and dielectric constant was 7.5. Black-Right-Pointing-Pointer The activation energy decreased with increase in frequency.

Threshold-Voltage Shifts in Organic Transistors Due to Self-Assembled Monolayers at the Dielectric: Evidence for Electronic Coupling and Dipolar Effects.

Science.gov (United States)

Aghamohammadi, Mahdieh; Rödel, Reinhold; Zschieschang, Ute; Ocal, Carmen; Boschker, Hans; Weitz, R Thomas; Barrena, Esther; Klauk, Hagen

2015-10-21

The mechanisms behind the threshold-voltage shift in organic transistors due to functionalizing of the gate dielectric with self-assembled monolayers (SAMs) are still under debate. We address the mechanisms by which SAMs determine the threshold voltage, by analyzing whether the threshold voltage depends on the gate-dielectric capacitance. We have investigated transistors based on five oxide thicknesses and two SAMs with rather diverse chemical properties, using the benchmark organic semiconductor dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene. Unlike several previous studies, we have found that the dependence of the threshold voltage on the gate-dielectric capacitance is completely different for the two SAMs. In transistors with an alkyl SAM, the threshold voltage does not depend on the gate-dielectric capacitance and is determined mainly by the dipolar character of the SAM, whereas in transistors with a fluoroalkyl SAM the threshold voltages exhibit a linear dependence on the inverse of the gate-dielectric capacitance. Kelvin probe force microscopy measurements indicate this behavior is attributed to an electronic coupling between the fluoroalkyl SAM and the organic semiconductor.

Low pull-in voltage electrostatic MEMS switch using liquid dielectric

KAUST Repository

Zidan, Mohammed A.

2014-08-01

In this paper, we present an electrostatic MEMS switch with liquids as dielectric to reduce the actuation voltage. The concept is verified by simulating a lateral dual gate switch, where the required pull-in voltage is reduced by more than 8 times after using water as a dielectric, to become as low as 5.36V. The proposed switch is simulated using COMSOL multiphysics using various liquid volumes to study their effect on the switching performance. Finally, we propose the usage of the lateral switch as a single switch XOR logic gate.

An Approach for Measuring the Dielectric Strength of OLED Materials

Directory of Open Access Journals (Sweden)

Sujith Sudheendran Swayamprabha

2018-06-01

Full Text Available Surface roughness of electrodes plays a key role in the dielectric breakdown of thin-film organic devices. The rate of breakdown will increase when there are stochastic sharp spikes on the surface of electrodes. Additionally, surface having spiking morphology makes the determination of dielectric strength very challenging, specifically when the layer is relatively thin. We demonstrate here a new approach to investigate the dielectric strength of organic thin films for organic light-emitting diodes (OLEDs. The thin films were deposited on a substrate using physical vapor deposition (PVD under high vacuum. The device architectures used were glass substrate/indium tin oxide (ITO/organic material/aluminum (Al and glass substrate/Al/organic material/Al. The dielectric strength of the OLED materials was evaluated from the measured breakdown voltage and layer thickness.

Studies on dielectric properties, opto-electrical parameters and electronic polarizability of thermally evaporated amorphous Cd{sub 50}S{sub 50−x}Se{sub x} thin films

Energy Technology Data Exchange (ETDEWEB)

Hassanien, Ahmed Saeed, E-mail: a.s.hassanien@gmail.com [Engineering Mathematics and Physics Department, Faculty of Engineering (Shoubra), Benha University (Egypt); Physics Department, Faculty of Science and Humanities in Ad-Dawadmi, Shaqra University, 11911 (Saudi Arabia)

2016-06-25

The objective of this work is to study the influence of the addition of more Se on dielectric properties, opto-electrical parameters and electronic polarizability of amorphous chalcogenide Cd{sub 50}S{sub 50−x}Se{sub x} thin films (30 ≤ x ≤ 50 at%). Thin films of thickness 200 nm were synthesized by vacuum deposition at ≈8.2 × 10{sup −4} Pa. Both refractive index and extinction coefficient were used to obtain all the studied parameters. The high frequency dielectric constant, real and imaginary parts of dielectric constant were discussed. Drude theory was applied to investigate opto-electrical parameters, like optical carrier concentration, optical mobility and optical resistivity. Moreover, other parameters were investigated and studied, e.g. Drude parameters, volume and surface energy loss functions, dielectric loss factor, dielectric relaxation time, complex optical conductivity and electronic polarizability as well as optical electronegativity and third-order nonlinear optical susceptibility. Values of electronic polarizability and nonlinear optical susceptibility were found to be decreased while optical electronegativity increased as Se-content was increased. Increment of Se-content in amorphous Cd{sub 50}S{sub 50−x}Se{sub x} thin films has also led to minimize the energy losses when electromagnetic waves propagate through films as well as optical conductivity and the speed of light increased. The other studied properties and parameters of Cd{sub 50}S{sub 50−x}Se{sub x} films were found to be strongly dependent upon Se-content. - Highlights: • Thermally evaporated amorphous Cd{sub 50}S{sub 50−x}Se{sub x} (30 ≤ x ≤ 50) thin films were deposited. • Refractive index and absorption index were used to determine almost all properties. • Dielectric properties, Drude parameters and electronic polarizability were studied. • Addition of more Se to CdSSe matrix led to improve the opto-electrical properties. • New data were obtained and

Comparative study on nitridation and oxidation plasma interface treatment for AlGaN/GaN MIS-HEMTs with AlN gate dielectric

Science.gov (United States)

Zhu, Jie-Jie; Ma, Xiao-Hua; Hou, Bin; Chen, Li-Xiang; Zhu, Qing; Hao, Yue

2017-02-01

This paper demonstrated the comparative study on interface engineering of AlN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) by using plasma interface pre-treatment in various ambient gases. The 15 nm AlN gate dielectric grown by plasma-enhanced atomic layer deposition significantly suppressed the gate leakage current by about two orders of magnitude and increased the peak field-effect mobility by more than 50%. NH3/N2 nitridation plasma treatment (NPT) was used to remove the 3 nm poor-quality interfacial oxide layer and N2O/N2 oxidation plasma treatment (OPT) to improve the quality of interfacial layer, both resulting in improved dielectric/barrier interface quality, positive threshold voltage (V th) shift larger than 0.9 V, and negligible dispersion. In comparison, however, NPT led to further decrease in interface charges by 3.38 × 1012 cm-2 and an extra positive V th shift of 1.3 V. Analysis with fat field-effect transistors showed that NPT resulted in better sub-threshold characteristics and transconductance linearity for MIS-HEMTs compared with OPT. The comparative study suggested that direct removing the poor interfacial oxide layer by nitridation plasma was superior to improving the quality of interfacial layer by oxidation plasma for the interface engineering of GaN-based MIS-HEMTs.

High performance In2O3 thin film transistors using chemically derived aluminum oxide dielectric

KAUST Repository

Nayak, Pradipta K.

2013-07-18

We report high performance solution-deposited indium oxide thin film transistors with field-effect mobility of 127 cm2/Vs and an Ion/Ioff ratio of 106. This excellent performance is achieved by controlling the hydroxyl group content in chemically derived aluminum oxide (AlOx) thin-film dielectrics. The AlOx films annealed in the temperature range of 250–350 °C showed higher amount of Al-OH groups compared to the films annealed at 500 °C, and correspondingly higher mobility. It is proposed that the presence of Al-OH groups at the AlOx surface facilitates unintentional Al-doping and efficient oxidation of the indium oxide channel layer, leading to improved device performance.

High performance In2O3 thin film transistors using chemically derived aluminum oxide dielectric

KAUST Repository

Nayak, Pradipta K.; Hedhili, Mohamed N.; Cha, Dong Kyu; Alshareef, Husam N.

2013-01-01

We report high performance solution-deposited indium oxide thin film transistors with field-effect mobility of 127 cm2/Vs and an Ion/Ioff ratio of 106. This excellent performance is achieved by controlling the hydroxyl group content in chemically derived aluminum oxide (AlOx) thin-film dielectrics. The AlOx films annealed in the temperature range of 250–350 °C showed higher amount of Al-OH groups compared to the films annealed at 500 °C, and correspondingly higher mobility. It is proposed that the presence of Al-OH groups at the AlOx surface facilitates unintentional Al-doping and efficient oxidation of the indium oxide channel layer, leading to improved device performance.

Effect of yttrium doping on the dielectric properties of CaCu{sub 3}Ti{sub 4}O{sub 12} thin film produced by chemical solution deposition

Energy Technology Data Exchange (ETDEWEB)

Saji, Viswanathan S., E-mail: vssaji@chosun.ac.k [Chosun University, College of Dentistry and 2nd Stage of Brain Korea 21 for College of Dentistry, Gwangju-501-759 (Korea, Republic of); Choe, Han Cheol [Chosun University, College of Dentistry and 2nd Stage of Brain Korea 21 for College of Dentistry, Gwangju-501-759 (Korea, Republic of)

2009-05-29

Pure and yttrium substituted CaCu{sub 3}Ti{sub 4-x}Y{sub x}O{sub 12-x/} {sub 2} (x = 0, 0.02, 0.1) thin films were prepared on boron doped silica substrate employing chemical solution deposition, spin coating and rapid thermal annealing. The phase and microstructure of the sintered films were examined using X-ray diffraction and scanning electron microscopy. Dielectric properties of the films were measured at room temperature using electrochemical impedance spectroscopy. Highly ordered polycrystalline CCTO thin film with bimodal grain size distribution was achieved at a sintering temperature of 800 {sup o}C. Yttrium doping was found to have beneficial effects on the dielectric properties of CCTO thin film. Dielectric parameters obtained for a CaCu{sub 3}Ti{sub 4-x}Y{sub x}O{sub 12-x} {sub /2} (x = 0.02) film at 1 KHz were k {approx} 2700 and tan {delta} {approx} 0.07.

Structural, electrical, and dielectric properties of Cr doped ZnO thin films: Role of Cr concentration

Energy Technology Data Exchange (ETDEWEB)

Gürbüz, Osman, E-mail: osgurbuz@yildiz.edu.tr; Okutan, Mustafa

2016-11-30

Highlights: • Magnetic material of Cr and semiconductor material of ZnO were grown by the magnetron sputtering co-sputter technique. • Perfect single crystalline structures were grown. • DC and AC conductivity with dielectric properties as a function of frequency (f = 5Hz–13 MHz) at room temperature were measured and compared. • Cr doped ZnO can be used in microwave, sensor and optoelectronic devices as the electrical conductivity increases while dielectric constant decreases with the Cr content. - Abstract: An undoped zinc oxide (ZnO) and different concentrations of chromium (Cr) doped ZnO Cr{sub x}ZnO{sub 1−x} (x = 3.74, 5.67, 8.10, 11.88, and 15.96) thin films were prepared using a magnetron sputtering technique at room temperature. These films were characterized by X-ray diffraction (XRD), High resolution scanning electron microscope (HR-SEM), and Energy dispersive X-ray spectrometry (EDS). XRD patterns of all the films showed that the films possess crystalline structure with preferred orientation along the (100) crystal plane. The average crystallite size obtained was found to be between 95 and 83 nm which was beneficial in high intensity recording peak. Both crystal quality and crystallite sizes decrease with increasing Cr concentration. The crystal and grain sizes of the all film were investigated using SEM analysis. The surface morphology that is grain size changes with increase Cr concentration and small grains coalesce together to form larger grains for the Cr{sub 11.88}ZnO and Cr{sub 15.96}ZnO samples. Impedance spectroscopy studies were carried out in the frequencies ranging from 5 Hz to 13 MHz at room temperature. The undoped ZnO film had the highest dielectric value, while dielectric values of other films decreased as doping concentrations increased. Besides, the dielectric constants decreased whereas the loss tangents increased with increasing Cr content. This was considered to be related to the reduction of grain size as Cr content in Zn

The relationship between chemical structure and dielectric properties of plasma-enhanced chemical vapor deposited polymer thin films

Energy Technology Data Exchange (ETDEWEB)

Jiang Hao [Materials Sci and Tech Applications, LLC, 409 Maple Springs Drive, Dayton OH 45458 (United States)]. E-mail: hao.jiang@wpafb.af.mil; Hong Lianggou [Materials Sci and Tech Applications, LLC, 409 Maple Springs Drive, Dayton OH 45458 (United States); Venkatasubramanian, N. [Research Institute, University of Dayton, 300 College Park, Dayton, OH 45469-0168 (United States); Grant, John T. [Research Institute, University of Dayton, 300 College Park, Dayton, OH 45469-0168 (United States); Eyink, Kurt [Air Force Research Laboratory, Materials Directorate, 3005 Hobson Way, Wright-Patterson Air Force Base, OH 45433-7707 (United States); Wiacek, Kevin [Air Force Research Laboratory, Propulsion Directorate, 1950 Fifth Street, Wright-Patterson Air Force Base, OH 45433-7251 (United States); Fries-Carr, Sandra [Air Force Research Laboratory, Propulsion Directorate, 1950 Fifth Street, Wright-Patterson Air Force Base, OH 45433-7251 (United States); Enlow, Jesse [Air Force Research Laboratory, Materials Directorate, 3005 Hobson Way, Wright-Patterson Air Force Base, OH 45433-7707 (United States); Bunning, Timothy J. [Air Force Research Laboratory, Materials Directorate, 3005 Hobson Way, Wright-Patterson Air Force Base, OH 45433-7707 (United States)

2007-02-26

Polymer dielectric films fabricated by plasma enhanced chemical vapor deposition (PECVD) have unique properties due to their dense crosslinked bulk structure. These spatially uniform films exhibit good adhesion to a variety of substrates, excellent chemical inertness, high thermal resistance, and are formed from an inexpensive, solvent-free, room temperature process. In this work, we studied the dielectric properties of plasma polymerized (PP) carbon-based polymer thin films prepared from two precursors, benzene and octafluorocyclobutane. Two different monomer feed locations, directly in the plasma zone or in the downstream region (DS) and two different pressures, 80 Pa (high pressure) or 6.7 Pa (low pressure), were used. The chemical structure of the PECVD films was examined by X-ray photoelectron spectroscopy and Fourier-transform infrared spectroscopy. The dielectric constant ({epsilon} {sub r}) and dielectric loss (tan {delta}) of the films were investigated over a range of frequencies up to 1 MHz and the dielectric strength (breakdown voltage) (F {sub b}) was characterized by the current-voltage method. Spectroscopic ellipsometry was performed to determine the film thickness and refractive index. Good dielectric properties were exhibited, as PP-benzene films formed in the high pressure, DS region showed a F{sub b} of 610 V/{mu}m, an {epsilon} {sub r} of 3.07, and a tan {delta} of 7.0 x 10{sup -3} at 1 kHz. The PECVD processing pressure has a significant effect on final film structure and the film's physical density has a strong impact on dielectric breakdown strength. Also noted was that the residual oxygen content in the PP-benzene films significantly affected the frequency dependences of the dielectric constant and loss.

The relationship between chemical structure and dielectric properties of plasma-enhanced chemical vapor deposited polymer thin films

International Nuclear Information System (INIS)

Jiang Hao; Hong Lianggou; Venkatasubramanian, N.; Grant, John T.; Eyink, Kurt; Wiacek, Kevin; Fries-Carr, Sandra; Enlow, Jesse; Bunning, Timothy J.

2007-01-01

Polymer dielectric films fabricated by plasma enhanced chemical vapor deposition (PECVD) have unique properties due to their dense crosslinked bulk structure. These spatially uniform films exhibit good adhesion to a variety of substrates, excellent chemical inertness, high thermal resistance, and are formed from an inexpensive, solvent-free, room temperature process. In this work, we studied the dielectric properties of plasma polymerized (PP) carbon-based polymer thin films prepared from two precursors, benzene and octafluorocyclobutane. Two different monomer feed locations, directly in the plasma zone or in the downstream region (DS) and two different pressures, 80 Pa (high pressure) or 6.7 Pa (low pressure), were used. The chemical structure of the PECVD films was examined by X-ray photoelectron spectroscopy and Fourier-transform infrared spectroscopy. The dielectric constant (ε r ) and dielectric loss (tan δ) of the films were investigated over a range of frequencies up to 1 MHz and the dielectric strength (breakdown voltage) (F b ) was characterized by the current-voltage method. Spectroscopic ellipsometry was performed to determine the film thickness and refractive index. Good dielectric properties were exhibited, as PP-benzene films formed in the high pressure, DS region showed a F b of 610 V/μm, an ε r of 3.07, and a tan δ of 7.0 x 10 -3 at 1 kHz. The PECVD processing pressure has a significant effect on final film structure and the film's physical density has a strong impact on dielectric breakdown strength. Also noted was that the residual oxygen content in the PP-benzene films significantly affected the frequency dependences of the dielectric constant and loss

Structural and dielectric studies of Co doped MgTiO3 thin films fabricated by RF magnetron sputtering

Directory of Open Access Journals (Sweden)

T. Santhosh Kumar

2014-06-01

Full Text Available We report the structural, dielectric and leakage current properties of Co doped MgTiO3 thin films deposited on platinized silicon (Pt/TiO2/SiO2/Si substrates by RF magnetron sputtering. The role of oxygen mixing percentage (OMP on the growth, morphology, electrical and dielectric properties of the thin films has been investigated. A preferred orientation of grains along (110 direction has been observed with increasing the OMP. Such evolution of the textured growth is explained on the basis of the orientation factor analysis followed the Lotgering model. (Mg1-xCoxTiO3 (x = 0.05 thin films exhibits a maximum relative dielectric permittivity of ɛr = 12.20 and low loss (tan δ ∼ 1.2 × 10−3 over a wide range of frequencies for 75% OMP. The role of electric field frequency (f and OMP on the ac-conductivity of (Mg0.95Co0.05TiO3 have been studied. A progressive increase in the activation energy (Ea and relative permittivity ɛr values have been noticed up to 75% of OMP, beyond which the properties starts deteriorate. The I-V characteristics reveals that the leakage current density decreases from 9.93 × 10−9 to 1.14 × 10−9 A/cm2 for OMP 0% to 75%, respectively for an electric field strength of 250 kV/cm. Our experimental results reveal up to that OMP ≥ 50% the leakage current mechanism is driven by the ohmic conduction, below which it is dominated by the schottky emission.

Atomic layer deposition of dielectrics for carbon-based electronics

Energy Technology Data Exchange (ETDEWEB)

Kim, J., E-mail: jiyoung.kim@utdallas.edu; Jandhyala, S.

2013-11-01

Carbon based nanomaterials like nanotubes and graphene have emerged as future generation electronic materials for device applications because of their interesting properties such as high-mobility and ability to carry high-current densities compared to conventional semiconductor materials like silicon. Therefore, there is a need to develop techniques to integrate robust gate dielectrics with high-quality interfaces for these materials in order to attain maximum performance. To date, a variety of methods including physical vapor deposition, atomic layer deposition (ALD), physical assembly among others have been employed in order to integrate dielectrics for carbon nanotube and graphene based field-effect transistors. Owing to the difficulty in wetting pristine surfaces of nanotubes and graphene, most of the ALD methods require a seeding technique involving non-covalent functionalization of their surfaces in order to nucleate dielectric growth while maintaining their intrinsic properties. A comprehensive review regarding the various dielectric integration schemes for emerging devices and their limitations with respect to ALD based methods along with a future outlook is provided. - Highlights: • We introduce various dielectric integration schemes for carbon-based devices. • Physical vapor deposition methods tend to degrade device performance. • Atomic layer deposition on pristine surfaces of graphene and nanotube is difficult. • We review different seeding techniques for atomic layer deposition of dielectrics. • Compare the performance of graphene top-gate devices with different dielectrics.

Atomic layer deposition of dielectrics for carbon-based electronics

International Nuclear Information System (INIS)

Kim, J.; Jandhyala, S.

2013-01-01

Carbon based nanomaterials like nanotubes and graphene have emerged as future generation electronic materials for device applications because of their interesting properties such as high-mobility and ability to carry high-current densities compared to conventional semiconductor materials like silicon. Therefore, there is a need to develop techniques to integrate robust gate dielectrics with high-quality interfaces for these materials in order to attain maximum performance. To date, a variety of methods including physical vapor deposition, atomic layer deposition (ALD), physical assembly among others have been employed in order to integrate dielectrics for carbon nanotube and graphene based field-effect transistors. Owing to the difficulty in wetting pristine surfaces of nanotubes and graphene, most of the ALD methods require a seeding technique involving non-covalent functionalization of their surfaces in order to nucleate dielectric growth while maintaining their intrinsic properties. A comprehensive review regarding the various dielectric integration schemes for emerging devices and their limitations with respect to ALD based methods along with a future outlook is provided. - Highlights: • We introduce various dielectric integration schemes for carbon-based devices. • Physical vapor deposition methods tend to degrade device performance. • Atomic layer deposition on pristine surfaces of graphene and nanotube is difficult. • We review different seeding techniques for atomic layer deposition of dielectrics. • Compare the performance of graphene top-gate devices with different dielectrics

Tungsten oxide proton conducting films for low-voltage transparent oxide-based thin-film transistors

International Nuclear Information System (INIS)

Zhang, Hongliang; Wan, Qing; Wan, Changjin; Wu, Guodong; Zhu, Liqiang

2013-01-01

Tungsten oxide (WO x ) electrolyte films deposited by reactive magnetron sputtering showed a high room temperature proton conductivity of 1.38 × 10 −4 S/cm with a relative humidity of 60%. Low-voltage transparent W-doped indium-zinc-oxide thin-film transistors gated by WO x -based electrolytes were self-assembled on glass substrates by one mask diffraction method. Enhancement mode operation with a large current on/off ratio of 4.7 × 10 6 , a low subthreshold swing of 108 mV/decade, and a high field-effect mobility 42.6 cm 2 /V s was realized. Our results demonstrated that WO x -based proton conducting films were promising gate dielectric candidates for portable low-voltage oxide-based devices.

Reduction of ambipolar characteristics of vertical channel tunneling field-effect transistor by using dielectric sidewall

International Nuclear Information System (INIS)

Park, Chun Woong; Cho, Il Hwan; Choi, Woo Young; Lee, Jong-Ho

2013-01-01

Ambipolar characteristics of tunneling FETs have been improved by introducing a novel structure which contains dielectric sidewall in the gate region. In the ambipolar operation mode, gate field effect on intrinsic-drain junction region can be reduced with dielectric sidewall. As a result, ambipolar state tunneling probability is decreased at the intrinsic-drain junction. Since the sidewall region is located near the drain region, tunneling probability of source-intrinsic region is not affected by dielectric sidewall. This asymmetric characteristics means only ambipolar current of tunneling FETs can be prohibited by dielectric sidewall. Reduction of ambipolar characteristic of proposed structure has been evaluated with dimension and location of dielectric sidewall. Quantitative analysis of ambipolar characteristics is also investigated with tunneling. (paper)

A Review of Nanoscale Channel and Gate Engineered FINFETs for VLSI Mixed Signal Applications Using Zirconium-di-Oxide Dielectrics

Directory of Open Access Journals (Sweden)

D.Nirmal

2014-07-01

Full Text Available In the past, most of the research and development efforts in the area of CMOS and IC’s are oriented towards reducing the power and increasing the gain of the circuits. While focusing the attention on low power and high gain in the device, the materials of the device also been taken into consideration. In the present technology, Computationally intensive devices with low power dissipation and high gain are becoming a critical application domain. Several factors have contributed to this paradigm shift. The primary driving factor being the increase in scale of integration, the chip has to accommodate smaller and faster transistors than their predecessors. During the last decade semiconductor technology has been led by conventional scaling. Scaling, has been aimed towards higher speed, lower power and higher density of the semiconductor devices. However, as scaling approached its physical limits, it has become more difficult and challenging for fabrication industry. Therefore, tremendous research has been carried out to investigate the alternatives, and this led to the introduction of new Nano materials and concepts to overcome the difficulties in the device fabrications. In order to reduce the leakage current and parasitic capacitance in devices, gate oxide high-k dielectric materials are explored. Among the different high-k materials available the nano size Zirconium dioxide material is suggested as an alternate gate oxide material for devices due to its thermal stability and small grain size of material. To meet the requirements of ITRS roadmap 2012, the Multi gate devices are considered to be one of the most promising technologies for the future microelectronics industry due to its excellent immunity to short channel effects and high value of On current. The double gate or multi gate devices provide a better scalability option due to its excellent immunity to short-channel effects. Here the different high-k materials are replaced in different

Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

Directory of Open Access Journals (Sweden)

Minkyu Chun

2015-05-01

Full Text Available We investigated the effects of top gate voltage (VTG and temperature (in the range of 25 to 70 oC on dual-gate (DG back-channel-etched (BCE amorphous-indium-gallium-zinc-oxide (a-IGZO thin film transistors (TFTs characteristics. The increment of VTG from -20V to +20V, decreases the threshold voltage (VTH from 19.6V to 3.8V and increases the electron density to 8.8 x 1018cm−3. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on VTG. At VTG of 20V, the mobility decreases from 19.1 to 15.4 cm2/V ⋅ s with increasing temperature, showing a metallic conduction. On the other hand, at VTG of - 20V, the mobility increases from 6.4 to 7.5cm2/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.

In situ atomic layer nitridation on the top and down regions of the amorphous and crystalline high-K gate dielectrics

Energy Technology Data Exchange (ETDEWEB)

Tsai, Meng-Chen [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China); Lee, Min-Hung [Institute of Electro-Optical Science and Technology, National Taiwan Normal University, Taipei 11677, Taiwan (China); Kuo, Chin-Lung; Lin, Hsin-Chih [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China); Chen, Miin-Jang, E-mail: mjchen@ntu.edu.tw [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China)

2016-11-30

Highlights: • The structural and electrical characteristics of the ZrO{sub 2} high-K dielectrics, treated with the in situ atomic layer doping of nitrogen into the top and down regions (top and down nitridation, TN and DN, respectively), were investigated. • The amorphous DN sample has a lower leakage current density (J{sub g}) than the amorphous TN sample, attributed to the formation of SiO{sub x}N{sub y} in the interfacial layer (IL). • The crystalline TN sample exhibited a lower CET and a similar J{sub g} as compared with the crystalline DN sample, which can be ascribed to the suppression of IL regrowth. • The crystalline ZrO{sub 2} with in situ atomic layer doping of nitrogen into the top region exhibited superior scaling limit, electrical characteristics, and reliability. - Abstract: Amorphous and crystalline ZrO{sub 2} gate dielectrics treated with in situ atomic layer nitridation on the top and down regions (top and down nitridation, abbreviated as TN and DN) were investigated. In a comparison between the as-deposited amorphous DN and TN samples, the DN sample has a lower leakage current density (J{sub g}) of ∼7 × 10{sup −4} A/cm{sup 2} with a similar capacitance equivalent thickness (CET) of ∼1.53 nm, attributed to the formation of SiO{sub x}N{sub y} in the interfacial layer (IL). The post-metallization annealing (PMA) leads to the transformation of ZrO{sub 2} from the amorphous to the crystalline tetragonal/cubic phase, resulting in an increment of the dielectric constant. The PMA-treated TN sample exhibits a lower CET of 1.22 nm along with a similar J{sub g} of ∼1.4 × 10{sup −5} A/cm{sup 2} as compared with the PMA-treated DN sample, which can be ascribed to the suppression of IL regrowth. The result reveals that the nitrogen engineering in the top and down regions has a significant impact on the electrical characteristics of amorphous and crystalline ZrO{sub 2} gate dielectrics, and the nitrogen incorporation at the top of crystalline

Surface properties of SiO2 with and without H2O2 treatment as gate dielectrics for pentacene thin-film transistor applications

Science.gov (United States)

Hung, Cheng-Chun; Lin, Yow-Jon

2018-01-01

The effect of H2O2 treatment on the surface properties of SiO2 is studied. H2O2 treatment leads to the formation of Si(sbnd OH)x at the SiO2 surface that serves to reduce the number of trap states, inducing the shift of the Fermi level toward the conduction band minimum. H2O2 treatment also leads to a noticeable reduction in the value of the SiO2 capacitance per unit area. The effect of SiO2 layers with H2O2 treatment on the behavior of carrier transports for the pentacene/SiO2-based organic thin-film transistor (OTFT) is also studied. Experimental identification confirms that the shift of the threshold voltage towards negative gate-source voltages is due to the reduced number of trap states in SiO2 near the pentacene/SiO2 interface. The existence of a hydrogenated layer between pentacene and SiO2 leads to a change in the pentacene-SiO2 interaction, increasing the value of the carrier mobility.

Highly stretchable carbon nanotube transistors enabled by buckled ion gel gate dielectrics

Energy Technology Data Exchange (ETDEWEB)

Wu, Meng-Yin; Chang, Tzu-Hsuan; Ma, Zhenqiang [Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States); Zhao, Juan [School of Optoelectronic Information, University of Electronic Science and Technology of China, Chengdu 610054 (China); Department of Materials Science and Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States); Xu, Feng; Jacobberger, Robert M.; Arnold, Michael S., E-mail: michael.arnold@wisc.edu [Department of Materials Science and Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States)

2015-08-03

Deformable field-effect transistors (FETs) are expected to facilitate new technologies like stretchable displays, conformal devices, and electronic skins. We previously demonstrated stretchable FETs based on buckled thin films of polyfluorene-wrapped semiconducting single-walled carbon nanotubes as the channel, buckled metal films as electrodes, and unbuckled flexible ion gel films as the dielectric. The FETs were stretchable up to 50% without appreciable degradation in performance before failure of the ion gel film. Here, we show that by buckling the ion gel, the integrity and performance of the nanotube FETs are extended to nearly 90% elongation, limited by the stretchability of the elastomer substrate. The FETs maintain an on/off ratio of >10{sup 4} and a field-effect mobility of 5 cm{sup 2} V{sup −1} s{sup −1} under elongation and demonstrate invariant performance over 1000 stretching cycles.

Cleaning Challenges of High-κ/Metal Gate Structures

KAUST Repository

Hussain, Muhammad Mustafa; Shamiryan, Denis G.; Paraschiv, Vasile; Sano, Kenichi; Reinhardt, Karen A.

2010-01-01

High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.

Cleaning Challenges of High-κ/Metal Gate Structures

KAUST Repository

Hussain, Muhammad Mustafa

2010-12-20

High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.

Improved linearity in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with nonlinear polarization dielectric

International Nuclear Information System (INIS)

Gao, Tao; Xu, Ruimin; Kong, Yuechan; Zhou, Jianjun; Kong, Cen; Dong, Xun; Chen, Tangsheng

2015-01-01

We demonstrate highly improved linearity in a nonlinear ferroelectric of Pb(Zr 0.52 Ti 0.48 )-gated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). Distinct double-hump feature in the transconductance-gate voltage (g m -V g ) curve is observed, yielding remarkable enhancement in gate voltage swing as compared to MIS-HEMT with conventional linear gate dielectric. By incorporating the ferroelectric polarization into a self-consistent calculation, it is disclosed that in addition to the common hump corresponding to the onset of electron accumulation, the second hump at high current level is originated from the nonlinear polar nature of ferroelectric, which enhances the gate capacitance by increasing equivalent dielectric constant nonlinearly. This work paves a way for design of high linearity GaN MIS-HEMT by exploiting the nonlinear properties of dielectric

Enhanced performance of a-IGZO thin-film transistors by forming AZO/IGZO heterojunction source/drain contacts

International Nuclear Information System (INIS)

Zou, Xiao; Fang, Guojia; Wan, Jiawei; Liu, Nishuang; Long, Hao; Wang, Haolin; Zhao, Xingzhong

2011-01-01

A low-cost Al-doped ZnO (AZO) thin film was deposited by radio-frequency magnetron sputtering with different Ar/O 2 flow ratios. The optical and electrical properties of an AZO film were investigated. A highly conductive AZO film was inserted between the amorphous InGaZnO (a-IGZO) channel and the metal Al electrode to form a heterojunction source/drain contact, and bottom-gate amorphous a-IGZO thin-film transistors (TFTs) with a high κ HfON gate dielectric were fabricated. The AZO film reduced the source/drain contact resistivity down to 79 Ω cm. Enhanced device performance of a-IGZO TFT with Al/AZO bi-layer S/D electrodes (W/L = 500/40 µm) was achieved with a saturation mobility of 13.7 cm 2 V −1 s −1 , a threshold voltage of 0.6 V, an on-off current ratio of 4.7 × 10 6 , and a subthreshold gate voltage swing of 0.25 V dec −1 . It demonstrated the potential application of the AZO film as a promising S/D contact material for the fabrication of the high performance TFTs

Coupled Optical Tamm States in a Planar Dielectric Mirror Structure Containing a Thin Metal Film

International Nuclear Information System (INIS)

Zhou Hai-Chun; Yang Guang; Lu Pei-Xiang; Wang Kai; Long Hua

2012-01-01

The coupling between two optical Tamm states (OTSs) with the same eigenenergy is numerically investigated in a planar dielectric mirror structure containing a thin metal film. The reflectivity map in this structure at normal incidence is obtained by applying the transfer matrix method. Two splitting branches appear in the photonic bandgap region when both adjacent dielectric layers of metal film are properly set. The splitting energy of two branches strongly depends on the thickness of the metal film. According to the electric field distribution in this structure, it is found that the high-energy branch corresponds to the antisymmetric coupling between two OTSs, while the low-energy branch is associated with the symmetric coupling between two OTSs. Moreover, the optical difference frequency of two branches is located in a broad terahertz region. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Influence of O2 flow rate on HfO2 gate dielectrics for back-gated graphene transistors

International Nuclear Information System (INIS)

Ganapathi, Kolla Lakshmi; Bhat, Navakanta; Mohan, Sangeneni

2014-01-01

HfO 2  thin films deposited on Si substrate using electron beam evaporation, are evaluated for back-gated graphene transistors. The amount of O 2  flow rate, during evaporation is optimized for 35 nm thick HfO 2  films, to achieve the best optical, chemical and electrical properties. It has been observed that with increasing oxygen flow rate, thickness of the films increased and refractive index decreased due to increase in porosity resulting from the scattering of the evaporant. The films deposited at low O 2  flow rates (1 and 3 SCCM) show better optical and compositional properties. The effects of post-deposition annealing and post-metallization annealing in forming gas ambience (FGA) on the optical and electrical properties of the films have been analyzed. The film deposited at 3 SCCM O 2  flow rate shows the best properties as measured on MOS capacitors. To evaluate the performance of device properties, back-gated bilayer graphene transistors on HfO 2  films deposited at two O 2  flow rates of 3 and 20 SCCM have been fabricated and characterized. The transistor with HfO 2  film deposited at 3 SCCM O 2  flow rate shows better electrical properties consistent with the observations on MOS capacitor structures. This suggests that an optimum oxygen pressure is necessary to get good quality films for high performance devices. (paper)

Influence of gating design on microstructure and fluidity of thin sections AA320.0 cast hypo-eutectic Al-Si alloy

Science.gov (United States)

Ramadan, Mohamed

2018-05-01

Influence of gating design especially number of ingrates on microstructure and fluidity of thin sections of 2, 4, 6 mm AA320.0 cast hypo-eutectic Al-Si alloy was evaluated for sand casting molding technique. Increasing the number of ingates improves the microstructe to be fine and more globular. About 87 μm of α-Al grain size, 0.6 α-Al grain sphericity and 37 μm dendrite arm spacing DAS are achieved by using 4 ingates in gating system. Increasing the number of ingates up to 3 increases hardness, filling area and related fluditiy of all cast samples. The minimum thickness of 2.5 mm for each ingate should be considered in order to successfully production of high quality light weight thin sections castings in sand mold.

ALD TiO x as a top-gate dielectric and passivation layer for InGaZnO115 ISFETs

Science.gov (United States)

Pavlidis, S.; Bayraktaroglu, B.; Leedy, K.; Henderson, W.; Vogel, E.; Brand, O.

2017-11-01

The suitability of atomic layer deposited (ALD) titanium oxide (TiO x ) as a top gate dielectric and passivation layer for indium gallium zinc oxide (InGaZnO115) ion sensitive field effect transistors (ISFETs) is investigated. TiO x is an attractive barrier material, but reports of its use for InGaZnO thin film transistor (TFT) passivation have been conflicting thus far. In this work, it is found that the passivated TFT’s behavior depends on the TiO x deposition temperature, affecting critical device characteristics such as threshold voltage, field-effect mobility and sub-threshold swing. An O2 annealing step is required to recover TFT performance post passivation. It is also observed that the positive bias stress response of the passivated TFTs improves compared the original bare device. Secondary ion mass spectroscopy excludes the effects of hydrogen doping and inter-diffusion as sources of the temperature-dependent performance change, therefore indicating that oxygen gettering induced by TiO x passivation is the likely source of oxygen vacancies and, consequently, carriers in the InGaZnO film. It is also shown that potentiometric sensing using ALD TiO x exhibits a near Nernstian response to pH change, as well as minimizes V TH drift in TiO x passivated InGaZnO TFTs immersed in an acidic liquid. These results add to the understanding of InGaZnO passivation effects and underscore the potential for low-temperature fabricated InGaZnO ISFETs to be used as high-performance mobile chemical sensors.

Comparison of neat and photo-crosslinked polyvinylidene fluoride-co-hexafluoropropylene thin film dielectrics formed by spin-coating

International Nuclear Information System (INIS)

Iyore, O.D.; Roodenko, K.; Winkler, P.S.; Noriega, J.R.; Vasselli, J.J.; Chabal, Y.J.; Gnade, B.E.

2013-01-01

We report the characterization of photo-crosslinked polyvinylidene fluoride-co-hexafluoropropylene (PVDF-HFP) thin film, metal–insulator–metal capacitors fabricated using standard semiconductor processing techniques. We characterize the capacitors using in-situ vibrational spectroscopy during thermally-assisted poling and correlate the Fourier transform infrared spectroscopy (FTIR) results with X-ray diffraction (XRD) results. FTIR analysis of the neat PVDF-HFP showed α → β transformations during poling at room temperature and at 55 °C. α → β transformations were observed for the crosslinked polymer only during poling at 55 °C. XRD data revealed that photo-crosslinking caused the polymer to partially crystallize into the β-phase. The similar behavior of the neat and crosslinked samples at 55 °C suggests that a higher activation energy was needed for α → β transformations in crosslinked PVDF-HFP during poling. Electrical measurements showed that photo-crosslinking had no significant effect on the dielectric constant and dielectric loss of PVDF-HFP. However, the dielectric strength and maximum energy density of the crosslinked polymer were severely reduced. - Highlights: • Polyvinylidene fluoride-hexafluoropropylene (PVDF-HFP) dielectrics were studied. • Phase transformations were observed only at 55 °C for the crosslinked PVDF-HFP. • Crosslinking had no strong effect on the dielectric constant of PVDF-HFP. • Breakdown strengths were 620 MVm −1 and 362 MVm −1 for neat and crosslinked films

Improvements in the reliability of a-InGaZnO thin-film transistors with triple stacked gate insulator in flexible electronics applications

Energy Technology Data Exchange (ETDEWEB)

Chen, Hua-Mao [Department of Photonics & Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang3708@gmail.com [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan (China); Tai, Ya-Hsiang [Department of Photonics & Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan (China); Chen, Kuan-Fu [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Chiang, Hsiao-Cheng [Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Liu, Kuan-Hsien [Department of Electrophysics, National Chiao Tung University, Hsinchu, Taiwan (China); Lee, Chao-Kuei [Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Lin, Wei-Ting; Cheng, Chun-Cheng; Tu, Chun-Hao; Liu, Chu-Yu [Advanced Technology Research Center, AU Optronics Corp, Hsinchu, Taiwan (China)

2015-11-30

This study examined the impact of the low-temperature stacking gate insulator on the gate bias instability of a-InGaZnO thin film transistors in flexible electronics applications. Although the quality of SiN{sub x} at low process/deposition temperature is better than that of SiO{sub x} at similarly low process/deposition temperature, there is still a very large positive threshold voltage (V{sub th}) shift of 9.4 V for devices with a single low-temperature SiN{sub x} gate insulator under positive gate bias stress. However, a suitable oxide–nitride–oxide-stacked gate insulator exhibits a V{sub th} shift of only 0.23 V. This improvement results from the larger band offset and suitable gate insulator thickness that can effectively suppress carrier trapping behavior. - Highlights: • The cause of the bias instability for a low-temperature gate insulator is verified. • A triple-stacked gate insulator was fabricated. • A suitable triple stacked gate insulator shows only 0.23 V threshold voltage shift.

Volatile and Nonvolatile Characteristics of Asymmetric Dual-Gate Thyristor RAM with Vertical Structure.

Science.gov (United States)

Kim, Hyun-Min; Kwon, Dae Woong; Kim, Sihyun; Lee, Kitae; Lee, Junil; Park, Euyhwan; Lee, Ryoongbin; Kim, Hyungjin; Kim, Sangwan; Park, Byung-Gook

2018-09-01

In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (107) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.

Improved linearity in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with nonlinear polarization dielectric

Energy Technology Data Exchange (ETDEWEB)

Gao, Tao [Fundamental Science on EHF Laboratory, University of Electronic Science and Technology of China (UESTC), Chengdu 611731 (China); Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Devices Institute, Nanjing 210016 (China); Xu, Ruimin [Fundamental Science on EHF Laboratory, University of Electronic Science and Technology of China (UESTC), Chengdu 611731 (China); Kong, Yuechan, E-mail: kycfly@163.com; Zhou, Jianjun; Kong, Cen; Dong, Xun; Chen, Tangsheng [Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Devices Institute, Nanjing 210016 (China)

2015-06-15

We demonstrate highly improved linearity in a nonlinear ferroelectric of Pb(Zr{sub 0.52}Ti{sub 0.48})-gated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). Distinct double-hump feature in the transconductance-gate voltage (g{sub m}-V{sub g}) curve is observed, yielding remarkable enhancement in gate voltage swing as compared to MIS-HEMT with conventional linear gate dielectric. By incorporating the ferroelectric polarization into a self-consistent calculation, it is disclosed that in addition to the common hump corresponding to the onset of electron accumulation, the second hump at high current level is originated from the nonlinear polar nature of ferroelectric, which enhances the gate capacitance by increasing equivalent dielectric constant nonlinearly. This work paves a way for design of high linearity GaN MIS-HEMT by exploiting the nonlinear properties of dielectric.

Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

Energy Technology Data Exchange (ETDEWEB)

Chun, Minkyu; Chowdhury, Md Delwar Hossain; Jang, Jin, E-mail: jjang@khu.ac.kr [Advanced Display Research Center and Department of Information Display, Kyung Hee University, Seoul 130-701 (Korea, Republic of)

2015-05-15

We investigated the effects of top gate voltage (V{sub TG}) and temperature (in the range of 25 to 70 {sup o}C) on dual-gate (DG) back-channel-etched (BCE) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) characteristics. The increment of V{sub TG} from -20V to +20V, decreases the threshold voltage (V{sub TH}) from 19.6V to 3.8V and increases the electron density to 8.8 x 10{sup 18}cm{sup −3}. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on V{sub TG}. At V{sub TG} of 20V, the mobility decreases from 19.1 to 15.4 cm{sup 2}/V ⋅ s with increasing temperature, showing a metallic conduction. On the other hand, at V{sub TG} of - 20V, the mobility increases from 6.4 to 7.5cm{sup 2}/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.

Plasma polymerized high energy density dielectric films for capacitors

Science.gov (United States)

Yamagishi, F. G.

1983-01-01

High energy density polymeric dielectric films were prepared by plasma polymerization of a variety of gaseous monomers. This technique gives thin, reproducible, pinhole free, conformable, adherent, and insoluble coatings and overcomes the processing problems found in the preparation of thin films with bulk polymers. Thus, devices are prepared completely in a vacuum environment. The plasma polymerized films prepared all showed dielectric strengths of greater than 1000 kV/cm and in some cases values of greater than 4000 kV/cm were observed. The dielectric loss of all films was generally less than 1% at frequencies below 10 kHz, but this value increased at higher frequencies. All films were self healing. The dielectric strength was a function of the polymerization technique, whereas the dielectric constant varied with the structure of the starting material. Because of the thin films used (thickness in the submicron range) surface smoothness of the metal electrodes was found to be critical in obtaining high dielectric strengths. High dielectric strength graft copolymers were also prepared. Plasma polymerized ethane was found to be thermally stable up to 150 C in the presence of air and 250 C in the absence of air. No glass transitions were observed for this material.

Screening-induced surface polar optical phonon scattering in dual-gated graphene field effect transistors

Energy Technology Data Exchange (ETDEWEB)

Hu, Bo, E-mail: hubo2011@semi.ac.cn

2015-03-15

The effect of surface polar optical phonons (SOs) from the dielectric layers on electron mobility in dual-gated graphene field effect transistors (GFETs) is studied theoretically. By taking into account SO scattering of electron as a main scattering mechanism, the electron mobility is calculated by the iterative solution of Boltzmann transport equation. In treating scattering with the SO modes, the dynamic dielectric screening is included and compared to the static dielectric screening and the dielectric screening in the static limit. It is found that the dynamic dielectric screening effect plays an important role in the range of low net carrier density. More importantly, in-plane acoustic phonon scattering and charged impurity scattering are also included in the total mobility for SiO{sub 2}-supported GFETs with various high-κ top-gate dielectric layers considered. The calculated total mobility results suggest both Al{sub 2}O{sub 3} and AlN are the promising candidate dielectric layers for the enhancement in room temperature mobility of graphene in the future.

Insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor devices with Al2O3 or AlTiO gate dielectrics

Science.gov (United States)

Le, Son Phuong; Nguyen, Duong Dai; Suzuki, Toshi-kazu

2018-01-01

We have investigated insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor (MIS) devices with Al2O3 or AlTiO (an alloy of Al2O3 and TiO2) gate dielectrics obtained by atomic layer deposition on AlGaN. Analyzing insulator-thickness dependences of threshold voltages for the MIS devices, we evaluated positive interface fixed charges, whose density at the AlTiO/AlGaN interface is significantly lower than that at the Al2O3/AlGaN interface. This and a higher dielectric constant of AlTiO lead to rather shallower threshold voltages for the AlTiO gate dielectric than for Al2O3. The lower interface fixed charge density also leads to the fact that the two-dimensional electron concentration is a decreasing function of the insulator thickness for AlTiO, whereas being an increasing function for Al2O3. Moreover, we discuss the relationship between the interface fixed charges and interface states. From the conductance method, it is shown that the interface state densities are very similar at the Al2O3/AlGaN and AlTiO/AlGaN interfaces. Therefore, we consider that the lower AlTiO/AlGaN interface fixed charge density is not owing to electrons trapped at deep interface states compensating the positive fixed charges and can be attributed to a lower density of oxygen-related interface donors.

Ferroelectricity, Piezoelectricity, and Dielectricity of 0.06PMnN-0.94PZT(45/55 Thin Film on Silicon Substrate

Directory of Open Access Journals (Sweden)

Tao Zhang

2015-01-01

Full Text Available The high piezoelectricity and high quality factor ferroelectric thin films are important for electromechanical applications especially the micro electromechanical system (MEMS. The ternary compound ferroelectric thin films 0.06Pb(Mn1/3, Nb2/3O3 + 0.94Pb(Zr0.45, Ti0.55O3 (0.06PMnN-0.94PZT(45/55 were deposited on silicon(100 substrates by RF magnetron sputtering method considering that Mn and Nb doping will improve PZT properties in this research. For comparison, nondoped PZT(45/55 films were also deposited. The results show that both of thin films show polycrystal structures with the main (111 and (101 orientations. The transverse piezoelectric coefficients are e31,eff=−4.03 C/m2 and e31,eff=-3.5 C/m2, respectively. These thin films exhibit classical ferroelectricity, in which the coercive electric field intensities are 2Ec=147.31 kV/cm and 2Ec=135.44 kV/cm, and the saturation polarization Ps=30.86 μC/cm2 and Ps=17.74 μC/cm2, and the remnant polarization Pr=20.44 μC/cm2 and Pr=9.87 μC/cm2, respectively. Moreover, the dielectric constants and loss are εr=681 and D=5% and εr=537 and D=4.3%, respectively. In conclusion, 0.06PMnN-0.94PZT(45/55 thin films act better than nondoped films, even though their dielectric constants are higher. Their excellent ferroelectricity, piezoelectricity, and high power and energy storage property, especially the easy fabrication, integration realizable, and potentially high quality factor, make this kind of thin films available for the realistic applications.

Flexible integrated diode-transistor logic (DTL) driving circuits based on printed carbon nanotube thin film transistors with low operation voltage.

Science.gov (United States)

Liu, Tingting; Zhao, Jianwen; Xu, Weiwei; Dou, Junyan; Zhao, Xinluo; Deng, Wei; Wei, Changting; Xu, Wenya; Guo, Wenrui; Su, Wenming; Jie, Jiansheng; Cui, Zheng

2018-01-03

Fabrication and application of hybrid functional circuits have become a hot research topic in the field of printed electronics. In this study, a novel flexible diode-transistor logic (DTL) driving circuit is proposed, which was fabricated based on a light emitting diode (LED) integrated with printed high-performance single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs). The LED, which is made of AlGaInP on GaAs, is commercial off-the-shelf, which could generate free electrical charges upon white light illumination. Printed top-gate TFTs were made on a PET substrate by inkjet printing high purity semiconducting SWCNTs (sc-SWCNTs) ink as the semiconductor channel materials, together with printed silver ink as the top-gate electrode and printed poly(pyromellitic dianhydride-co-4,4'-oxydianiline) (PMDA/ODA) as gate dielectric layer. The LED, which is connected to the gate electrode of the TFT, generated electrical charge when illuminated, resulting in biased gate voltage to control the TFT from "ON" status to "OFF" status. The TFTs with a PMDA/ODA gate dielectric exhibited low operating voltages of ±1 V, a small subthreshold swing of 62-105 mV dec -1 and ON/OFF ratio of 10 6 , which enabled DTL driving circuits to have high ON currents, high dark-to-bright current ratios (up to 10 5 ) and good stability under repeated white light illumination. As an application, the flexible DTL driving circuit was connected to external quantum dot LEDs (QLEDs), demonstrating its ability to drive and to control the QLED.

Moderate temperature-dependent surface and volume resistivity and low-frequency dielectric constant measurements of pure and multi-walled carbon nanotube (MWCNT) doped polyvinyl alcohol thin films

Science.gov (United States)

Edwards, Matthew; Guggilla, Padmaja; Reedy, Angela; Ijaz, Quratulann; Janen, Afef; Uba, Samuel; Curley, Michael

2017-08-01

Previously, we have reported measurements of temperature-dependent surface resistivity of pure and multi-walled carbon nanotube (MWNCT) doped amorphous Polyvinyl Alcohol (PVA) thin films. In the temperature range from 22 °C to 40 °C with humidity-controlled environment, we found the surface resistivity to decrease initially, but to rise steadily as the temperature continued to increase. Moreover, electric surface current density (Js) was measured on the surface of pure and MWCNT doped PVA thin films. In this regard, the surface current density and electric field relationship follow Ohm's law at low electric fields. Unlike Ohmic conduction in metals where free electrons exist, selected captive electrons are freed or provided from impurities and dopants to become conduction electrons from increased thermal vibration of constituent atoms in amorphous thin films. Additionally, a mechanism exists that seemingly decreases the surface resistivity at higher temperatures, suggesting a blocking effect for conducting electrons. Volume resistivity measurements also follow Ohm's law at low voltages (low electric fields), and they continue to decrease as temperatures increase in this temperature range, differing from surface resistivity behavior. Moreover, we report measurements of dielectric constant and dielectric loss as a function of temperature and frequency. Both the dielectric constant and dielectric loss were observed to be highest for MWCNT doped PVA compared to pure PVA and commercial paper, and with frequency and temperature for all samples.

Drying Temperature Dependence of Sol-gel Spin Coated Bilayer Composite ZnO/TiO2 Thin Films for Extended Gate Field Effect Transistor pH Sensor

Science.gov (United States)

Rahman, R. A.; Zulkefle, M. A.; Yusoff, K. A.; Abdullah, W. F. H.; Rusop, M.; Herman, S. H.

2018-03-01

This study presents an investigation on zinc oxide (ZnO) and titanium dioxide (TiO2) bilayer film applied as the sensing membrane for extended-gate field effect transistor (EGFET) for pH sensing application. The influences of the drying temperatures on the pH sensing capability of ZnO/TiO2 were investigated. The sensing performance of the thin films were measured by connecting the thin film to a commercial MOSFET to form the extended gates. By varying the drying temperature, we found that the ZnO/TiO2 thin film dried at 150°C gave the highest sensitivity compared to other drying conditions, with the sensitivity value of 48.80 mV/pH.

Comparison of neat and photo-crosslinked polyvinylidene fluoride-co-hexafluoropropylene thin film dielectrics formed by spin-coating

Energy Technology Data Exchange (ETDEWEB)

Iyore, O.D.; Roodenko, K.; Winkler, P.S. [Materials Science and Engineering Department, The University of Texas at Dallas, Richardson, TX 75080 (United States); Noriega, J.R.; Vasselli, J.J. [Electrical Engineering Department, The University of Texas at Tyler, Tyler, TX 75799 (United States); Chabal, Y.J. [Materials Science and Engineering Department, The University of Texas at Dallas, Richardson, TX 75080 (United States); Gnade, B.E., E-mail: gnade@utdallas.edu [Materials Science and Engineering Department, The University of Texas at Dallas, Richardson, TX 75080 (United States)

2013-12-02

We report the characterization of photo-crosslinked polyvinylidene fluoride-co-hexafluoropropylene (PVDF-HFP) thin film, metal–insulator–metal capacitors fabricated using standard semiconductor processing techniques. We characterize the capacitors using in-situ vibrational spectroscopy during thermally-assisted poling and correlate the Fourier transform infrared spectroscopy (FTIR) results with X-ray diffraction (XRD) results. FTIR analysis of the neat PVDF-HFP showed α → β transformations during poling at room temperature and at 55 °C. α → β transformations were observed for the crosslinked polymer only during poling at 55 °C. XRD data revealed that photo-crosslinking caused the polymer to partially crystallize into the β-phase. The similar behavior of the neat and crosslinked samples at 55 °C suggests that a higher activation energy was needed for α → β transformations in crosslinked PVDF-HFP during poling. Electrical measurements showed that photo-crosslinking had no significant effect on the dielectric constant and dielectric loss of PVDF-HFP. However, the dielectric strength and maximum energy density of the crosslinked polymer were severely reduced. - Highlights: • Polyvinylidene fluoride-hexafluoropropylene (PVDF-HFP) dielectrics were studied. • Phase transformations were observed only at 55 °C for the crosslinked PVDF-HFP. • Crosslinking had no strong effect on the dielectric constant of PVDF-HFP. • Breakdown strengths were 620 MVm{sup −1} and 362 MVm{sup −1} for neat and crosslinked films.

Phase sensitive molecular dynamics of self-assembly glycolipid thin films: A dielectric spectroscopy investigation

Science.gov (United States)

Velayutham, T. S.; Ng, B. K.; Gan, W. C.; Majid, W. H. Abd.; Hashim, R.; Zahid, N. I.; Chaiprapa, Jitrin

2014-08-01

Glycolipid, found commonly in membranes, is also a liquid crystal material which can self-assemble without the presence of a solvent. Here, the dielectric and conductivity properties of three synthetic glycolipid thin films in different thermotropic liquid crystal phases were investigated over a frequency and temperature range of (10-2-106 Hz) and (303-463 K), respectively. The observed relaxation processes distinguish between the different phases (smectic A, columnar/hexagonal, and bicontinuous cubic Q) and the glycolipid molecular structures. Large dielectric responses were observed in the columnar and bicontinuous cubic phases of the longer branched alkyl chain glycolipids. Glycolipids with the shortest branched alkyl chain experience the most restricted self-assembly dynamic process over the broad temperature range studied compared to the longer ones. A high frequency dielectric absorption (Process I) was observed in all samples. This is related to the dynamics of the hydrogen bond network from the sugar group. An additional low-frequency mechanism (Process II) with a large dielectric strength was observed due to the internal dynamics of the self-assembly organization. Phase sensitive domain heterogeneity in the bicontinuous cubic phase was related to the diffusion of charge carriers. The microscopic features of charge hopping were modelled using the random walk scheme, and two charge carrier hopping lengths were estimated for two glycolipid systems. For Process I, the hopping length is comparable to the hydrogen bond and is related to the dynamics of the hydrogen bond network. Additionally, that for Process II is comparable to the bilayer spacing, hence confirming that this low-frequency mechanism is associated with the internal dynamics within the phase.

Mapping Charge Carrier Density in Organic Thin-Film Transistors by Time-Resolved Photoluminescence Lifetime Studies

DEFF Research Database (Denmark)

Leißner, Till; Jensen, Per Baunegaard With; Liu, Yiming

2017-01-01

The device performance of organic transistors is strongly influenced by the charge carrier distribution. A range of factors effect this distribution, including injection barriers at the metal-semiconductor interface, the morphology of the organic film, and charge traps at the dielectric/organic...... interface or at grain boundaries. In our comprehensive experimental and analytical work we demonstrate a method to characterize the charge carrier density in organic thin-film transistors using time-resolved photoluminescence spectroscopy. We developed a numerical model that describes the electrical...... and optical responses consistently. We determined the densities of free and trapped holes at the interface between the organic layer and the SiO2 gate dielectric by comparison to electrical measurements. Furthermore by applying fluorescence lifetime imaging microscopy we determine the local charge carrier...

All-Aluminum Thin Film Transistor Fabrication at Room Temperature

Directory of Open Access Journals (Sweden)

Rihui Yao

2017-02-01

Full Text Available Bottom-gate all-aluminum thin film transistors with multi conductor/insulator nanometer heterojunction were investigated in this article. Alumina (Al2O3 insulating layer was deposited on the surface of aluminum doping zinc oxide (AZO conductive layer, as one AZO/Al2O3 heterojunction unit. The measurements of transmittance electronic microscopy (TEM and X-ray reflectivity (XRR revealed the smooth interfaces between ~2.2-nm-thick Al2O3 layers and ~2.7-nm-thick AZO layers. The devices were entirely composited by aluminiferous materials, that is, their gate and source/drain electrodes were respectively fabricated by aluminum neodymium alloy (Al:Nd and pure Al, with Al2O3/AZO multilayered channel and AlOx:Nd gate dielectric layer. As a result, the all-aluminum TFT with two Al2O3/AZO heterojunction units exhibited a mobility of 2.47 cm2/V·s and an Ion/Ioff ratio of 106. All processes were carried out at room temperature, which created new possibilities for green displays industry by allowing for the devices fabricated on plastic-like substrates or papers, mainly using no toxic/rare materials.

Electrode/Dielectric Strip For High-Energy-Density Capacitor

Science.gov (United States)

Yen, Shiao-Ping S.

1994-01-01

Improved unitary electrode/dielectric strip serves as winding in high-energy-density capacitor in pulsed power supply. Offers combination of qualities essential for high energy density: high permittivity of dielectric layers, thinness, and high resistance to breakdown of dielectric at high electric fields. Capacitors with strip material not impregnated with liquid.

Microstructure and chemical analysis of Hf-based high-k dielectric layers in metal-insulator-metal capacitors

Energy Technology Data Exchange (ETDEWEB)

Thangadurai, P. [Department of Materials Engineering, Technion - Israel Institute of Technology, Haifa 32000 (Israel); Mikhelashvili, V.; Eisenstein, G. [Department of Electrical Engineering, Technion - Israel Institute of Technology, Haifa 32000 (Israel); Kaplan, W.D., E-mail: kaplan@tx.technion.ac.i [Department of Materials Engineering, Technion - Israel Institute of Technology, Haifa 32000 (Israel)

2010-05-31

The microstructure and chemistry of the high-k gate dielectric significantly influences the performance of metal-insulator-metal (MIM) and metal-oxide-semiconductor devices. In particular, the local structure, chemistry, and inter-layer mixing are important phenomena to be understood. In the present study, high resolution and analytical transmission electron microscopy are combined to study the local structure, morphology, and chemistry in MIM capacitors containing a Hf-based high-k dielectric. The gate dielectric, bottom and gate electrodes were deposited on p-type Si(100) wafers by electron beam evaporation. Four chemically distinguishable sub-layers were identified within the dielectric stack. One is an unintentionally formed 4.0 nm thick interfacial layer of Ta{sub 2}O{sub 5} at the interface between the Ta electrode and the dielectric. The other three layers are based on HfN{sub x}O{sub y} and HfTiO{sub y}, and intermixing between the nearby sub-layers including deposited SiO{sub 2}. Hf-rich clusters were found in the HfN{sub x}O{sub y} layer adjacent to the Ta{sub 2}O{sub 5} layer.

Photo-galvanic effect in Bi2Se3 thin films with ionic liquid gating

Science.gov (United States)

Pan, Yu; Richardella, Anthony; Lee, Joon Sue; Flanagan, Thomas; Samarth, Nitin

2013-03-01

A key challenge in three dimensional (3D) topological insulators (TIs) is to reveal the helical spin-polarized surface states via electrical transport measurements. A recent study [Nature Nanotech. 7, 96 (2012)] showed that circularly polarized light can be used to generate and control photocurrents in the 3D TI Bi2Se3, even at photon energies that are well above the bulk band gap. Symmetry considerations suggest that this ``photo-galvanic effect'' arises purely from photo-currents induced in the surface Dirac states. To gain insights into this phenomenon, we have carried out systematic measurements of the photo-galvanic effect in electrically gated MBE-grown Bi2Se3 thin films of varying thickness. By using an ionic liquid as an optically transparent gate, we map out the behavior of the photo-galvanic effect as a function of Fermi energy over a temperature range 5 K <= T <= 300 K. Supported by ONR and NSF.

Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

Energy Technology Data Exchange (ETDEWEB)

Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A., E-mail: steven.vitale@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

2015-07-28

Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

Balancing Hole and Electron Conduction in Ambipolar Split-Gate Thin-Film Transistors.

Science.gov (United States)

Yoo, Hocheon; Ghittorelli, Matteo; Lee, Dong-Kyu; Smits, Edsger C P; Gelinck, Gerwin H; Ahn, Hyungju; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2017-07-10

Complementary organic electronics is a key enabling technology for the development of new applications including smart ubiquitous sensors, wearable electronics, and healthcare devices. High-performance, high-functionality and reliable complementary circuits require n- and p-type thin-film transistors with balanced characteristics. Recent advancements in ambipolar organic transistors in terms of semiconductor and device engineering demonstrate the great potential of this route but, unfortunately, the actual development of ambipolar organic complementary electronics is currently hampered by the uneven electron (n-type) and hole (p-type) conduction in ambipolar organic transistors. Here we show ambipolar organic thin-film transistors with balanced n-type and p-type operation. By manipulating air exposure and vacuum annealing conditions, we show that well-balanced electron and hole transport properties can be easily obtained. The method is used to control hole and electron conductions in split-gate transistors based on a solution-processed donor-acceptor semiconducting polymer. Complementary logic inverters with balanced charging and discharging characteristics are demonstrated. These findings may open up new opportunities for the rational design of complementary electronics based on ambipolar organic transistors.

Influence of metal induced crystallization parameters on the performance of polycrystalline silicon thin film transistors

International Nuclear Information System (INIS)

Pereira, L.; Barquinha, P.; Fortunato, E.; Martins, R.

2005-01-01

In this work, metal induced crystallization using nickel was employed to obtain polycrystalline silicon by crystallization of amorphous films for thin film transistor applications. The devices were produced through only one lithographic process with a bottom gate configuration using a new gate dielectric consisting of a multi-layer of aluminum oxide/titanium oxide produced by atomic layer deposition. The best results were obtained for TFTs with the active layer of poly-Si crystallized for 20 h at 500 deg. C using a nickel layer of 0.5 nm where the effective mobility is 45.5 cm 2 V -1 s -1 . The threshold voltage, the on/off current ratio and the sub-threshold voltage are, respectively, 11.9 V, 5.55x10 4 and 2.49 V/dec

In-plane microwave dielectric properties of paraelectric barium strontium titanate thin films with anisotropic epitaxy

Science.gov (United States)

Simon, W. K.; Akdogan, E. K.; Safari, A.; Bellotti, J. A.

2005-08-01

In-plane dielectric properties of ⟨110⟩ oriented epitaxial (Ba0.60Sr0.40)TiO3 thin films in the thickness range from 25-1200nm have been investigated under the influence of anisotropic epitaxial strains from ⟨100⟩ NdGaO3 substrates. The measured dielectric properties show strong residual strain and in-plane directional dependence. Below 150nm film thickness, there appears to be a phase transition due to the anisotropic nature of the misfit strain relaxation. In-plane relative permittivity is found to vary from as much as 500-150 along [11¯0] and [001] respectively, in 600nm thick films, and from 75 to 500 overall. Tunability was found to vary from as much as 54% to 20% in all films and directions, and in a given film the best tunability is observed along the compressed axis in a mixed strain state, 54% along [11¯0] in the 600nm film for example.

Metal-oxide assisted surface treatment of polyimide gate insulators for high-performance organic thin-film transistors.

Science.gov (United States)

Kim, Sohee; Ha, Taewook; Yoo, Sungmi; Ka, Jae-Won; Kim, Jinsoo; Won, Jong Chan; Choi, Dong Hoon; Jang, Kwang-Suk; Kim, Yun Ho

2017-06-14

We developed a facile method for treating polyimide-based organic gate insulator (OGI) surfaces with self-assembled monolayers (SAMs) by introducing metal-oxide interlayers, called the metal-oxide assisted SAM treatment (MAST). To create sites for surface modification with SAM materials on polyimide-based OGI (KPI) surfaces, the metal-oxide interlayer, here amorphous alumina (α-Al 2 O 3 ), was deposited on the KPI gate insulator using spin-coating via a rapid sol-gel reaction, providing an excellent template for the formation of a high-quality SAM with phosphonic acid anchor groups. The SAM of octadecylphosphonic acid (ODPA) was successfully treated by spin-coating onto the α-Al 2 O 3 -deposited KPI film. After the surface treatment by ODPA/α-Al 2 O 3 , the surface energy of the KPI thin film was remarkably decreased and the molecular compatibility of the film with an organic semiconductor (OSC), 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-C 10 ), was increased. Ph-BTBT-C 10 molecules were uniformly deposited on the treated gate insulator surface and grown with high crystallinity, as confirmed by atomic force microscopy (AFM) and X-ray diffraction (XRD) analysis. The mobility of Ph-BTBT-C 10 thin-film transistors (TFTs) was approximately doubled, from 0.56 ± 0.05 cm 2 V -1 s -1 to 1.26 ± 0.06 cm 2 V -1 s -1 , after the surface treatment. The surface treatment of α-Al 2 O 3 and ODPA significantly decreased the threshold voltage from -21.2 V to -8.3 V by reducing the trap sites in the OGI and improving the interfacial properties with the OSC. We suggest that the MAST method for OGIs can be applied to various OGI materials lacking reactive sites using SAMs. It may provide a new platform for the surface treatment of OGIs, similar to that of conventional SiO 2 gate insulators.

Solution-processed p-type copper(I) thiocyanate (CuSCN) for low-voltage flexible thin-film transistors and integrated inverter circuits

KAUST Repository

Petti, Luisa

2017-03-17

We report on low operating voltage thin-film transistors (TFTs) and integrated inverters based on copper(I) thiocyanate (CuSCN) layers processed from solution at low temperature on free-standing plastic foils. As-fabricated coplanar bottom-gate and staggered top-gate TFTs exhibit hole-transporting characteristics with average mobility values of 0.0016 cm2 V−1 s−1 and 0.013 cm2 V−1 s−1, respectively, current on/off ratio in the range 102–104, and maximum operating voltages between −3.5 and −10 V, depending on the gate dielectric employed. The promising TFT characteristics enable fabrication of unipolar NOT gates on flexible free-standing plastic substrates with voltage gain of 3.4 at voltages as low as −3.5 V. Importantly, discrete CuSCN transistors and integrated logic inverters remain fully functional even when mechanically bent to a tensile radius of 4 mm, demonstrating the potential of the technology for flexible electronics.

Thin-dielectric-layer engineering for 3D nanostructure integration using an innovative planarization approach

International Nuclear Information System (INIS)

Guerfi, Y; Doucet, J B; Larrieu, G

2015-01-01

Three-dimensional (3D) nanostructures are emerging as promising building blocks for a large spectrum of applications. One critical issue in integration regards mastering the thin, flat, and chemically stable insulating layer that must be implemented on the nanostructure network in order to build striking nano-architectures. In this letter, we report an innovative method for nanoscale planarization on 3D nanostructures by using hydrogen silesquioxane as a spin-on-glass (SOG) dielectric material. To decouple the thickness of the final layer from the height of the nanostructure, we propose to embed the nanowire network in the insulator layer by exploiting the planarizing properties of the SOG approach. To achieve the desired dielectric thickness, the structure is chemically etched back with a highly diluted solution to control the etch rate precisely. The roughness of the top surface was less than 2 nm. There were no surface defects and the planarity was excellent, even in the vicinity of the nanowires. This newly developed process was used to realize a multilevel stack architecture with sub-deca-nanometer-range layer thickness. (paper)

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium–gallium–zinc oxide gate stack

Science.gov (United States)

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-01

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium–gallium–zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>104). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium-gallium-zinc oxide gate stack.

Science.gov (United States)

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-20

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium-gallium-zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>10 4 ). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Top-gate organic depletion and inversion transistors with doped channel and injection contact

Energy Technology Data Exchange (ETDEWEB)

Liu, Xuhai; Kasemann, Daniel, E-mail: daniel.kasemann@iapp.de; Leo, Karl [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Strasse 1, 01069 Dresden (Germany)

2015-03-09

Organic field-effect transistors constitute a vibrant research field and open application perspectives in flexible electronics. For a commercial breakthrough, however, significant performance improvements are still needed, e.g., stable and high charge carrier mobility and on-off ratio, tunable threshold voltage, as well as integrability criteria such as n- and p-channel operation and top-gate architecture. Here, we show pentacene-based top-gate organic transistors operated in depletion and inversion regimes, realized by doping source and drain contacts as well as a thin layer of the transistor channel. By varying the doping concentration and the thickness of the doped channel, we control the position of the threshold voltage without degrading on-off ratio or mobility. Capacitance-voltage measurements show that an inversion channel can indeed be formed, e.g., an n-doped channel can be inverted to a p-type inversion channel with highly p-doped contacts. The Cytop polymer dielectric minimizes hysteresis, and the transistors can be biased for prolonged cycles without a shift of threshold voltage, indicating excellent operation stability.

Leakage current suppression with a combination of planarized gate and overlap/off-set structure in metal-induced laterally crystallized polycrystalline-silicon thin-film transistors

Science.gov (United States)

Chae, Hee Jae; Seok, Ki Hwan; Lee, Sol Kyu; Joo, Seung Ki

2018-04-01

A novel inverted staggered metal-induced laterally crystallized (MILC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with a combination of a planarized gate and an overlap/off-set at the source-gate/drain-gate structure were fabricated and characterized. While the MILC process is advantageous for fabricating inverted staggered poly-Si TFTs, MILC TFTs reveal higher leakage current than TFTs crystallized by other processes due to their high trap density of Ni contamination. Due to this drawback, the planarized gate and overlap/off-set structure were applied to inverted staggered MILC TFTs. The proposed device shows drastic suppression of leakage current and pinning phenomenon by reducing the lateral electric field and the space-charge limited current from the gate to the drain.

Development of III-V p-MOSFETs with high-kappa gate stack for future CMOS applications

Science.gov (United States)

Nagaiah, Padmaja

As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, non-silicon materials and new device architectures are gradually being introduced to improve Si integrated circuit performance and continue transistor scaling. Recently, the replacement of SiO2 with a high-k material (HfO2) as gate dielectric has essentially removed one of the biggest advantages of Si as channel material. As a result, alternate high mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. III-V materials in particular have become of great interest as channel materials, owing to their superior electron transport properties. However, there are several critical challenges that need to be addressed before III-V based CMOS can replace Si CMOS technology. Some of these challenges include development of a high quality, thermally stable gate dielectric/III-V interface, and improvement in III-V p-channel hole mobility to complement the n-channel mobility, low source/drain resistance and integration onto Si substrate. In this thesis, we would be addressing the first two issues i.e. the development high performance III-V p-channels and obtaining high quality III-V/high-k interface. We start with using the device architecture of the already established InGaAs n-channels as a baseline to understand the effect of remote scattering from the high-k oxide and oxide/semiconductor interface on channel transport properties such as electron mobility and channel electron concentration. Temperature dependent Hall electron mobility measurements were performed to separate various scattering induced mobility limiting factors. Dependence of channel mobility on proximity of the channel to the oxide interface, oxide thickness, annealing conditions are discussed. The results from this work will be used in the design of the p-channel MOSFETs. Following this, InxGa1-xAs (x>0.53) is chosen as channel material for developing p

Electrical characteristics of vapor deposited amorphous MoS2 two-terminal structures and back gate thin film transistors with Al, Au, Cu and Ni-Au contacts

International Nuclear Information System (INIS)

Kouvatsos, Dimitrios N.; Papadimitropoulos, Georgios; Spiliotis, Thanassis; Vasilopoulou, Maria; Davazoglou, Dimitrios; Barreca, Davide; Gasparotto, Alberto

2015-01-01

Amorphous molybdenum sulphide (a-MoS 2 ) thin films were deposited at near room temperature on oxidized silicon substrates and were electrically characterized with the use of two-terminal structures and of back-gated thin film transistors utilizing the substrate silicon as gate. Current-voltage characteristics were extracted for various metals used as pads, showing significant current variations attributable to different metal-sulphide interface properties and contact resistances, while the effect of a forming gas anneal was determined. With the use of heavily doped silicon substrates and aluminum backside deposition, thin film transistor (TFT) structures with the a-MoS 2 film as active layer were fabricated and characterized. Transfer characteristics showing a gate field effect, despite a leakage often present, were extracted for these devices, indicating that high mobility devices can be fabricated. SEM and EDXA measurements were also performed in an attempt to clarify issues related to material properties and fabrication procedures, so as to achieve a reliable and optimized a-MoS 2 TFT fabrication process. (copyright 2015 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)