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Sample records for gate bipolar transistor

  1. Advanced insulated gate bipolar transistor gate drive

    Science.gov (United States)

    Short, James Evans [Monongahela, PA; West, Shawn Michael [West Mifflin, PA; Fabean, Robert J [Donora, PA

    2009-08-04

    A gate drive for an insulated gate bipolar transistor (IGBT) includes a control and protection module coupled to a collector terminal of the IGBT, an optical communications module coupled to the control and protection module, a power supply module coupled to the control and protection module and an output power stage module with inputs coupled to the power supply module and the control and protection module, and outputs coupled to a gate terminal and an emitter terminal of the IGBT. The optical communications module is configured to send control signals to the control and protection module. The power supply module is configured to distribute inputted power to the control and protection module. The control and protection module outputs on/off, soft turn-off and/or soft turn-on signals to the output power stage module, which, in turn, supplies a current based on the signal(s) from the control and protection module for charging or discharging an input capacitance of the IGBT.

  2. Precursor Parameter Identification for Insulated Gate Bipolar Transistor (IGBT) Prognostics

    Data.gov (United States)

    National Aeronautics and Space Administration — Precursor parameters have been identified to enable development of a prognostic approach for insulated gate bipolar transistors (IGBT). The IGBT were subjected to...

  3. Simulation of Heating of an Oil-Cooled Insulated Gate Bipolar Transistors Converter Model

    National Research Council Canada - National Science Library

    Ovrebo, Gregory

    2004-01-01

    I used SolidWorks a three-dimensional modeling software, and FloWorks, a fluid dynamics analysis tool, to simulate oil flow and heat transfer in a heat sink structure attached to three insulated gate bipolar transistors...

  4. Thermal Simulation of Switching Pulses in an Insulated Gate Bipolar Transistor (IGBT) Power Module

    Science.gov (United States)

    2015-02-01

    prepared with SolidWorks computer-aided design software. The module has 8 silicon IGBTs mounted on copper (Cu) lands bonded onto a dielectric circuit...aluminum nitride ARL US Army Research Laboratory Cu copper IGBT insulated gate bipolar transistor ms millisecond 3D 3-dimensional W watt...RDRL CIO LL TECHL LIB 1 GOVT PRNTG OFC (PDF) ATTN A MALHOTRA 5 US ARMY RSRCH LAB (PDF) ATTN RDRL SED C W TIPTON ATTN RDRL SED P D

  5. Low Gate Voltage Operated Multi-emitter-dot H+ Ion-Sensitive Gated Lateral Bipolar Junction Transistor

    Science.gov (United States)

    Yuan, Heng; Zhang, Ji-Xing; Zhang, Chen; Zhang, Ning; Xu, Li-Xia; Ding, Ming; Patrick, J. Clarke

    2015-02-01

    A low gate voltage operated multi-emitter-dot gated lateral bipolar junction transistor (BJT) ion sensor is proposed. The proposed device is composed of an arrayed gated lateral BJT, which is driven in the metal-oxide-semiconductor field-effect transistor (MOSFET)-BJT hybrid operation mode. Further, it has multiple emitter dots linked to each other in parallel to improve ionic sensitivity. Using hydrogen ionic solutions as reference solutions, we conduct experiments in which we compare the sensitivity and threshold voltage of the multi-emitter-dot gated lateral BJT with that of the single-emitter-dot gated lateral BJT. The multi-emitter-dot gated lateral BJT not only shows increased sensitivity but, more importantly, the proposed device can be operated under very low gate voltage, whereas the conventional ion-sensitive field-effect transistors cannot. This special characteristic is significant for low power devices and for function devices in which the provision of a gate voltage is difficult.

  6. Development of 8-inch Key Processes for Insulated-Gate Bipolar Transistor

    Directory of Open Access Journals (Sweden)

    Guoyou Liu

    2015-09-01

    Full Text Available Based on the construction of the 8-inch fabrication line, advanced process technology of 8-inch wafer, as well as the fourth-generation high-voltage double-diffused metal-oxide semiconductor (DMOS+ insulated-gate bipolar transistor (IGBT technology and the fifth-generation trench gate IGBT technology, have been developed, realizing a great-leap forward technological development for the manufacturing of high-voltage IGBT from 6-inch to 8-inch. The 1600 A/1.7 kV and 1500 A/3.3 kV IGBT modules have been successfully fabricated, qualified, and applied in rail transportation traction system.

  7. Separation of ionization and displacement damage using gate-controlled lateral PNP bipolar transistors

    Science.gov (United States)

    Ball, D. R.; Schrimpf, R. D.; Barnaby, H. J.

    2002-12-01

    Proton irradiation produces both ionization and displacement damage in semiconductor devices. In this paper, a technique for separating the effects of these two types of damage using a lateral PNP bipolar transistor with a gate contact over the active base region is described. By biasing the gate appropriately, the effects of ionization-induced damage are minimized and the effects of displacement damage can be measured independently. Experiments and simulations are used to validate this approach and provide insight into proton-induced BJT degradation.

  8. Development of insulated gate bipolar transistor-based power ...

    Indian Academy of Sciences (India)

    [5] S V Nakhe et al, National Laser Symposium, 81–82 (2001). [6] E G Cook et al, 8th IEEE Pulsed Power Conference, June 1991. [7] L Druckmann et al, IEEE Power Modulator Symposium, 213–216 (1992). [8] Hybrid gate drivers and gate drive power supplies, M57962L datasheet from Mitsubishi. Electric Corpn. Pramana ...

  9. Effect of the interface recombination current fluctuations on 1/f noise of gated lateral bipolar transistors

    Science.gov (United States)

    Romas, Gregory G., Jr.; Ul Hoque, Md Mazhar; Celik-Butler, Zeynep

    2003-05-01

    A gated lateral bipolar transistor is a bulk lateral BJT in parallel with a MOSFET at the surface. The base current components such as surface recombination and space charge recombination currents are two of the dominant noise sources in the lateral BJT. If the gate is biased such that the MOSFET is in the off-state by accumulating carriers underneath the oxide in the base surface, the noise contribution by these two base current (Ib) components can be better understood. The carrier accumulation in the base surface can be modulated with different gate bias, which in turn will affect the fluctuation of the surface recombination current component. In this paper, noise power spectral density of gated lateral PNP transistors, fabricated in Texas Instruments Standard Bipolar Process, has been discussed. The base current noise power spectral density (SIb) was extracted from the cross-correlation noise spectrum measured between the base and the collector circuits for different gate biasing conditions. Based on the frequency exponent dependence of the noise power spectral density, it was found that the noise in the low frequency range is in the form of 1/f noise. SIb was found to be the dominant noise source for these devices as the coherence between the base and collector power spectral density was very close to 1. SIb was extracted for a base current range of 8 nA to 1microA for a gate bias range of 0V to 40V. The SPICE noise model parameters, AF and KF were also determined for each case from the dependence of SIb on Ib. The noise was measured on devices with different base width values.

  10. Experimental Analysis of Proton-Induced Displacement and Ionization Damage Using Gate-Controlled Lateral PNP Bipolar Transistors

    Science.gov (United States)

    Ball, D. R.; Schrimpf, R. D.; Barnaby, H. J.

    2006-01-01

    The electrical characteristics of proton-irradiated bipolar transistors are affected by ionization damage to the insulating oxide and displacement damage to the semiconductor bulk. While both types of damage degrade the transistor, it is important to understand the mechanisms individually and to be able to analyze them separately. In this paper, a method for analyzing the effects of ionization and displacement damage using gate-controlled lateral PNP bipolar junction transistors is described. This technique allows the effects of oxide charge, surface recombination velocity, and bulk traps to be measured independently.

  11. Design of the optimum insulator gate bipolar transistor using response surface method with cluster analysis

    CERN Document Server

    Wang, Chi Ling; Huang Sy Ruen; Yeh Chao Yu

    2004-01-01

    In this paper, a statistical methodology that can be used for the optimization of the Insulator Gate Bipolar Transistor (IGBT) devices is proposed. This is achieved by integrating the response surface method (RSM) with cluster analysis, weighted composite method and genetic algorithm (GA). The device characteristic of IGBT was simulated based upon the fabrication simulator, ATHENA, and the device simulator, ATLAS. This methodology, yielded another way to investigate the IGBT device and to make a decision in the tradeoff between the breakdown voltage and the on-resistance. In this methodology, we also show how to use cluster analysis to determine the dominant factors that are not visible in the screening of all experiments. 20 Refs.

  12. Characterization of insulated-gate bipolar transistor temperature on insulating, heat-spreading polycrystalline diamond substrate

    Science.gov (United States)

    Umezawa, Hitoshi; Shikata, Shin-ichi; Kato, Yukako; Mokuno, Yoshiaki; Seki, Akinori; Suzuki, Hiroshi; Bessho, Takeshi

    2017-01-01

    Polycrystalline diamond films have been utilized as direct bonding aluminum (DBA) substrates to improve cooling efficiency. A diamond film with a high quality factor was characterized by Raman spectroscopy and showed a high thermal conductivity of more than 1800 W m-1 K-1 and a low leakage current, even at an applied bias of 3 kV, because of the suppression of electrical conduction through the grain boundaries. The operating temperatures of Insulated-gate bipolar transistors (IGBTs) on diamond DBAs were 20-28% lower than those on AlN DBAs. The thermal resistivity of the diamond DBA module was 0.32 °C/W. The uniformity of the temperature distribution on a diamond DBA was excellent.

  13. Analysis of the dynamic avalanche of punch through insulated gate bipolar transistor (PT-IGBT)

    Science.gov (United States)

    Lefranc, P.; Planson, D.; Morel, H.; Bergogne, D.

    2009-09-01

    In the paper proposed here, we are studying the dynamic avalanche from experimental results first, dynamic avalanche is identified on a punch through insulated gate bipolar transistor (PT-IGBT) module 1200 V-300 A from Mitsubishi. Secondly, the phenomenon is analysed thanks to simple solid state devices equations. Numerical simulations are used to confirm experimental results. Simulation results allows us locating the active area of the dynamic avalanche during turn-off under over-current conditions. A PT-IGBT cell is described with MEDICI™, a finite element simulator. A mixed-mode simulation is performed thanks to MEDICI™ and SPICE™. The circuit simulated here is a buck topology with an inductive load. Finally, a thermal analysis is performed to estimate temperature increase due to dynamic avalanche.

  14. A New Switching Impulse Generator Based on Transformer Boosting and Insulated Gate Bipolar Transistor Trigger Control

    Directory of Open Access Journals (Sweden)

    Ming Ren

    2016-08-01

    Full Text Available To make the switching impulse (SI generator more compact, portable and feasible in field tests, a new approach based on transformer boosting was developed. To address problems such as triggering synchronization and electromagnetic interference involved with the traditional spark gap, an insulated gate bipolar transistor (IGBT module with drive circuit was employed as the impulse trigger. An optimization design for the component parameters of the primary winding side of the transformer was realized by numerical calculation and error correction. Experiment showed that the waveform parameters of SI and oscillating switching impulse (OSI voltages generated by the new generator were consistent with the numerical calculation and the error correction. The generator was finally built on a removable high voltage transformer with small size. Thus the volume of the generator is significantly reduced. Experiments showed that the waveform parameters of SI and OSI voltages generated by the new generator were basically consistent with the numerical calculation and the error correction.

  15. Magnetic bipolar transistor

    OpenAIRE

    Fabian, Jaroslav; Zutic, Igor; Sarma, S. Das

    2003-01-01

    A magnetic bipolar transistor is a bipolar junction transistor with one or more magnetic regions, and/or with an externally injected nonequilibrium (source) spin. It is shown that electrical spin injection through the transistor is possible in the forward active regime. It is predicted that the current amplification of the transistor can be tuned by spin.

  16. Ultra-High Voltage 4H-SiC Bi-Directional Insulated Gate Bipolar Transistors

    Science.gov (United States)

    Chowdhury, Sauvik

    4H- Silicon Carbide (4H-SiC) is an attractive material for power semiconductor devices due to its large bandgap, high critical electric field and high thermal conductivity compared to Silicon (Si). For ultra-high voltage applications (BV > 10 kV), 4H-SiC Insulated Gate Bipolar Transistors (IGBTs) are favored over unipolar transistors due to lower conduction losses. With improvements in SiC materials and processing technology, promising results have been demonstrated in the area of conventional unidirectional 4H-SiC IGBTs, with breakdown voltage ratings up to 27 kV. This research presents the experimental demonstration of the world's first high voltage bi-directional power transistors in 4H-SiC. Traditionally, four (two IGBTs and two diodes) or two (two reverse blocking IGBTs) semiconductor devices are necessary to yield a bidirectional switch. With a monolithically integrated bidirectional switch as presented here, the number of semiconductor devices is reduced to only one, which results in increased reliability and reduced cost of the overall system. Additionally, by using the unique dual gate operation of BD-IGBTs, switching losses can be reduced to a small fraction of that in conventional IGBTs, resulting in increased efficiency. First, the performance limits of SiC IGBTs are calculated by using analytical methods. The performance benefits of SiC IGBTs over SiC unipolar devices and Si IGBTs are quantified. Numerical simulations are used to optimize the unit cell and edge termination structures for a 15 kV SiC BD-IGBT. The effect of different device parameters on BD-IGBT static and switching performance are quantified. Second, the process technology necessary for the fabrication of high voltage SiC BD-IGBTs is optimized. The effect of different process steps on parameters such as breakdown voltage, carrier lifetime, gate oxide reliability, SiO2-SiC interface charge density is quantified. A carrier lifetime enhancement process has been optimized for lightly doped

  17. Study of an Insulated Gate Bipolar Transistor (IGBT) and its connection in series. Application at a chopper 1500V-5A-10kHz

    International Nuclear Information System (INIS)

    Gros, P.

    1993-01-01

    In the frame of the tokamak ITER (International Thermonuclear Experimental Reactor) we have studied, for neutral particle injection, a converter with at least two static interrupters by Mosfet transistor, bipolar transistor or Insulated Gate Bipolar Transistor (IGBT). After a comparison between these three types of transistors, by the simulating software MICROCAP, a serial of tests has shown the advantages of the IGBT. A command, associated with two IGBT of equivalent characteristics, has given a simple and efficacious solution. The performances are: (1) between two blockages: 50 ns without overvoltage, (2) between two cut-off: 60 ns. 40 figs; 30 refs; 10 annexes

  18. MOSFET-BJT hybrid mode of the gated lateral bipolar junction transistor for C-reactive protein detection.

    Science.gov (United States)

    Yuan, Heng; Kwon, Hyurk-Choon; Yeom, Se-Hyuk; Kwon, Dae-Hyuk; Kang, Shin-Won

    2011-10-15

    In this study, we propose a novel biosensor based on a gated lateral bipolar junction transistor (BJT) for biomaterial detection. The gated lateral BJT can function as both a BJT and a metal-oxide-semiconductor field-effect transistor (MOSFET) with both the emitter and source, and the collector and drain, coupled. C-reactive protein (CRP), which is an important disease marker in clinical examinations, can be detected using the proposed device. In the MOSFET-BJT hybrid mode, the sensitivity, selectivity, and reproducibility of the gated lateral BJT for biosensors were evaluated in this study. According to the results, in the MOSFET-BJT hybrid mode, the gated lateral BJT shows good selectivity and reproducibility. Changes in the emitter (source) current of the device for CRP antigen detection were approximately 0.65, 0.72, and 0.80 μA/decade at base currents of -50, -30, and -10 μA, respectively. The proposed device has significant application in the detection of certain biomaterials that require a dilution process using a common biosensor, such as a MOSFET-based biosensor. Copyright © 2011 Elsevier B.V. All rights reserved.

  19. Gate voltage dependent characteristics of p-n diodes and bipolar transistors based on multiwall CN(x)/carbon nanotube intramolecular junctions.

    Science.gov (United States)

    Zhang, W J; Zhang, Q F; Chai, Y; Shen, X; Wu, J L

    2007-10-03

    The electrical transport characteristics of multiwall CN(x)/carbon nanotube intramolecular junctions were studied. The junctions could be used as diodes. We found that the rectification resulted from p-n junctions, not from metal-semiconductor junctions. The gate effect was very weak when the diodes were reverse biased. At forward bias, however, some of the p-n diodes could be n-type transistors. Experimental results supported the opinion that the gate voltage dependent property is derived from the Schottky barrier between the CN(x) part and the electrode. Using p-n diodes, a bipolar transistor with nanoscale components was built, whose behavior was very similar to that of a conventional planar bipolar transistor.

  20. Bipolar-FET combinational power transistors for power conversion applications

    Science.gov (United States)

    Chen, D. Y.; Chin, S. A.

    1984-01-01

    Four bipolar-FET (field-effect transistor) combinational transistor configurations are compared from the application point of view. The configurations included are FET-Darlington (cascade), emitter-open switch (cascode), parallel configuration, and FET-gated bipolar transistors (FGT).

  1. Silicon-on-Insulator Lateral-Insulated-Gate-Bipolar-Transistor with Built-in Self-anti-ESD Diode

    Directory of Open Access Journals (Sweden)

    Xiaojun Cheng

    2014-05-01

    Full Text Available Power SOI (Silicon-On-Insulator devices have an inherent sandwich structure of MOS (Metal-Oxide-Semiconductor gate which is very easy to suffer ESD (Electro-Static Discharge overstress. To solve this reliability problem, studies on design and modification of a built-in self-anti-ESD diode for a preliminarily optimized high voltage SOI LIGBT (Lateral-Insulated-Gate-Bipolar-Transistor were carried out on the Silvaco TCAD (Technology-Computer-Aided-Design platform. According to the constrains of the technological process, the new introduction of the N+ doped region into P-well region that form the built-in self-anti-ESD diode should be done together with the doping of source under the same mask. The modifications were done by adjusting the vertical impurity profile in P-well into retrograde distribution and designing a cathode plate with a proper length to cover the forward depletion terminal and make sure that the thickness of the cathode plate is the same as that of the gate plate. The simulation results indicate that the modified device structure is compatible with the original one in process and design, the breakdown voltage margin of the former was expanded properly, and both the transient cathode voltages are clamped low enough very quickly. Therefore, the design and optimization results of the modified device structure of the built-in self-anti-ESD diode for the given SOI LIGBT meet the given requirements.

  2. A 65-kV insulated gate bipolar transistor switch applied in damped AC voltages partial discharge detection system.

    Science.gov (United States)

    Jiang, J; Ma, G M; Luo, D P; Li, C R; Li, Q M; Wang, W

    2014-02-01

    Damped AC voltages detection system (DAC) is a productive way to detect the faults in power cables. To solve the problems of large volume, complicated structure and electromagnetic interference in existing switches, this paper developed a compact solid state switch based on electromagnetic trigger, which is suitable for DAC test system. Synchronous electromagnetic trigger of 32 Insulated Gate Bipolar Transistors (IGBTs) in series was realized by the topological structure of single line based on pulse width modulation control technology. In this way, external extension was easily achieved. Electromagnetic trigger and resistor-capacitor-diode snubber circuit were optimized to reduce the switch turn-on time and circular layout. Epoxy encapsulating was chosen to enhance the level of partial discharge initial voltage (PDIV). The combination of synchronous trigger and power supply is proposed to reduce the switch volume. Moreover, we have overcome the drawback of the electromagnetic interference and improved the detection sensitivity of DAC by using capacitor storage energy to maintain IGBT gate driving voltage. The experimental results demonstrated that the solid-state switch, with compact size, whose turn-on time was less than 400 ns and PDIV was more than 65 kV, was able to meet the actual demands of 35 kV DAC test system.

  3. Nanofluidic diode and bipolar transistor.

    Science.gov (United States)

    Daiguji, Hirofumi; Oka, Yukiko; Shirono, Katsuhiro

    2005-11-01

    Theoretical modeling of ionic distribution and transport in a nanochannel containing a surface charge on its wall, 30 nm high and 5 microm long, suggests that ionic current can be controlled by locally modifying the surface charge density through a gate electrode, even if the electrical double layers are not overlapped. When the surface charge densities at the right and left halves of a channel are the same absolute value but of different signs, this could form the basis of a nanofluidic diode. When the surface charge density at the middle part of a channel is modified, this could form the basis of a nanofluidic bipolar transistor.

  4. Enhanced Miller plateau characteristics of a 4H-SiC insulated-gate bipolar transistor in the presence of interface traps

    Science.gov (United States)

    Navarro, Dondee; Tone, Akihiro; Kikuchihara, Hideyuki; Morikawa, Yoji; Miura-Mattausch, Mitiko

    2017-04-01

    Miller plateau characteristics of a 4H-SiC insulated-gate bipolar transistor (IGBT) is investigated during a gate voltage turn-on under the presence of interface carrier traps at the MOSFET gate oxide. The plateau, which is observed in the device gate-emitter voltage, increased with respect to both height and length. The plateau height is mainly determined by the density increase of trap states, which also causes slow charging of the gate capacitance in the overlap region that results in a longer plateau length. The shallow trap states contribute mainly to the plateau increase. It is observed that the switching loss at turn-on can increase by more than 60% due mainly to the carrier traps at the shallow trap states.

  5. Improvement of Switching Speed of a 600-V Nonpunch-Through Insulated Gate Bipolar Transistor Using Fast Neutron Irradiation

    Directory of Open Access Journals (Sweden)

    Ha Ni Baek

    2017-02-01

    Full Text Available Fast neutron irradiation was used to improve the switching speed of a 600-V nonpunch-through insulated gate bipolar transistor. Fast neutron irradiation was carried out at 30-MeV energy in doses of 1 × 108 n/cm2, 1 × 109 n/cm2, 1 × 1010 n/cm2, and 1 × 1011 n/cm2. Electrical characteristics such as current–voltage, forward on-state voltage drop, and switching speed of the device were analyzed and compared with those prior to irradiation. The on-state voltage drop of the initial devices prior to irradiation was 2.08 V, which increased to 2.10 V, 2.20 V, 2.3 V, and 2.4 V, respectively, depending on the irradiation dose. This effect arises because of the lattice defects generated by the fast neutrons. In particular, the turnoff delay time was reduced to 92 nanoseconds, 45% of that prior to irradiation, which means there is a substantial improvement in the switching speed of the device.

  6. A Fast-Acting Diagnostic Algorithm of Insulated Gate Bipolar Transistor Open Circuit Faults for Power Inverters in Electric Vehicles

    Directory of Open Access Journals (Sweden)

    Lei Yu

    2017-04-01

    Full Text Available To improve the diagnostic detection speed in electric vehicles, a novel diagnostic algorithm of insulated gate bipolar transistor (IGBT open circuit faults for power inverters is proposed in this paper. The average of the difference between the actual three-phase current and referential three-phase current values over one electrical period is used as the diagnostic variable. The normalization method based on the amplitude of the d-q axis referential current is applied to the diagnostic variables to improve the response speed of diagnosis, and to avoid the noise and the delay caused by signal acquisition. In the parameter discretization process, the variable parameter moving average method (VPMAM is adopted to solve the variation of the average value over a period with the speed of the motor; hence, the diagnostic reliability of the system is improved. This algorithm is robust, independent of load variations, and has a high resistivity against false alarms. Since only the three-phase current of the motor is utilized for calculations in the time domain, a fast diagnostic detection speed can be achieved, which is significantly essential for real-time control in electric vehicles. The effectiveness of the proposed algorithm is verified by both simulation and experimental results.

  7. Ion bipolar junction transistors.

    Science.gov (United States)

    Tybrandt, Klas; Larsson, Karin C; Richter-Dahlfors, Agneta; Berggren, Magnus

    2010-06-01

    Dynamic control of chemical microenvironments is essential for continued development in numerous fields of life sciences. Such control could be achieved with active chemical circuits for delivery of ions and biomolecules. As the basis for such circuitry, we report a solid-state ion bipolar junction transistor (IBJT) based on conducting polymers and thin films of anion- and cation-selective membranes. The IBJT is the ionic analogue to the conventional semiconductor BJT and is manufactured using standard microfabrication techniques. Transistor characteristics along with a model describing the principle of operation, in which an anionic base current amplifies a cationic collector current, are presented. By employing the IBJT as a bioelectronic circuit element for delivery of the neurotransmitter acetylcholine, its efficacy in modulating neuronal cell signaling is demonstrated.

  8. Investigation of Impact of the Gate Circuitry on IGBT Transistor Dynamic Parameters

    Directory of Open Access Journals (Sweden)

    Vytautas Bleizgys

    2011-03-01

    Full Text Available The impact of Insulated Gate Bipolar Transistor driver circuit parameters on the rise and fall time of the collector current and voltage collector-emitter was investigated. The influence of transistor driver circuit parameters on heating of Insulated Gate Bipolar Transistors was investigated as well.Article in Lithuanian

  9. The four-gate transistor

    Science.gov (United States)

    Mojarradi, M. M.; Cristoveanu, S.; Allibert, F.; France, G.; Blalock, B.; Durfrene, B.

    2002-01-01

    The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

  10. The high temperature DC characteristics of a high voltage lateral insulated-gate bipolar transistors with NPN anode in junction isolation technology

    Science.gov (United States)

    Tsai, Ying-Chieh; Gong, Jeng; Chan, Wing-Chor; Wu, Shyi-Yuan; Lien, Chenhsin

    2017-06-01

    The high temperature DC characteristics of a high-voltage bulk Si lateral insulated-gate bipolar transistor in junction isolation (JI-LIGBT) technology is studied intensively in this paper. The current density distribution in the off-state at different temperatures of three types of device structure is compared. By using the Quasi-vertical DMOSFET (QVDMOS or multi-channel, MC) structure, the electron injection from the channel into the n-drift region is significantly enhanced, and the current density is improved. In addition, by extending the p-top layer to the NPN anode not only improves the breakdown voltage but also reduces the substrate current as well as ensures high temperature stability.

  11. STRUCTURAL AND TECHNOLOGICAL PARAMETERS AFFECTING THE BIPOLAR STATIC INDUCTION TRANSISTOR (BSIT RESISTANCE

    Directory of Open Access Journals (Sweden)

    T. A. Ismailov

    2016-01-01

    Full Text Available Aim. The aim of the study is to determine the impact of structural and technological parameters on the resistance of the bipolar static induction transistor.Methods. The paper provides a comparative analysis of the advantages of bipolar static induction transistor compared to the bipolar power transistors, MOSFETs and insulated-gate bipolar transistor (IGBT. Considered are structural and technological parameters that influence the resistance of BSIT-transistor.Result. As a result of experimental study on silicon substrates were formed test prototypes of BSIT transistor structure, are presented calculation and experimental works. Obtained are the resistance dependencies of the transistor cell on the thickness of the epitaxial film; the resistance dependencies of BSIT transistor cell on the effective gate length for different values of the impurity concentration in the epitaxial film; dependencies resistance of the transistor cell on the gate length at different values of the epitaxial film thickness; the resistance dependencies of BSIT transistor cell on the distance between the mask for the p-region and the gate; dependencies on the multiplication the cell resistance by its area on the gate length.Conclusion. When increasing the gate length (Lk and the mask length for the p-region (lp + in the transistor structure, the resistance decreases and the dependence of multiplication of the cell resistance by its area Q on the gate length has this case the minimum.

  12. Bipolar transistor in VESTIC technology: prototype

    Science.gov (United States)

    Mierzwiński, Piotr; Kuźmicz, Wiesław; Domański, Krzysztof; Tomaszewski, Daniel; Głuszko, Grzegorz

    2016-12-01

    VESTIC technology is an alternative for traditional CMOS technology. This paper presents first measurement data of prototypes of VES-BJT: bipolar transistors in VESTIC technology. The VES-BJT is a bipolar transistor on the SOI substrate with symmetric lateral structure and both emitter and collector made of polysilicon. The results indicate that VES-BJT can be a device with useful characteristics. Therefore, VESTIC technology has the potential to become a new BiCMOS-type technology with some unique properties.

  13. The effects of gamma irradiation on neutron displacement sensitivity of lateral PNP bipolar transistors

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Chenhui, E-mail: wangchenhui@nint.ac.cn; Chen, Wei; Liu, Yan; Jin, Xiaoming; Yang, Shanchao; Qi, Chao

    2016-09-21

    The effects of gamma irradiation on neutron displacement sensitivity of four types of lateral PNP bipolar transistors (LPNPs) with different neutral base widths, emitter widths and the doping concentrations of the epitaxial base region are studied. The physical mechanisms of the effects are explored by defect analysis using deep level transient spectroscopy (DLTS) techniques and numerical simulations of recombination process in the base region of the lateral PNP bipolar transistors, and are verified by the experiments on gate-controlled lateral PNP bipolar transistors (GCLPNPs) manufactured in the identical commercial bipolar process with different gate bias voltage. The results indicate that gamma irradiation increases neutron displacement damage sensitivity of lateral PNP bipolar transistors and the mechanism of this phenomenon is that positive charge induced by gamma irradiation enhances the recombination process in the defects induced by neutrons in the base region, leading to larger recombination component of base current and greater gain degradation.

  14. Voltage regulator for battery power source. [using a bipolar transistor

    Science.gov (United States)

    Black, J. M. (Inventor)

    1979-01-01

    A bipolar transistor in series with the battery as the control element also in series with a zener diode and a resistor is used to maintain a predetermined voltage until the battery voltage decays to very nearly the predetermined voltage. A field effect transistor between the base of the bipolar transistor and a junction between the zener diode and resistor regulates base current of the bipolar transistor, thereby regulating the conductivity of the bipolar transistor for control of the output voltage.

  15. Modelling ionising radiation induced defect generation in bipolar oxides with gated diodes

    International Nuclear Information System (INIS)

    Barnaby, H.J.; Cirba, C.; Schrimpf, R.D.; Kosier, St.; Fouillat, P.; Montagner, X.

    1999-01-01

    Radiation-induced oxide defects that degrade electrical characteristics of bipolar junction transistor (BJTs) can be measured with the use of gated diodes. The buildup of defects and their effect on device radiation response are modeled with computer simulation. (authors)

  16. Magnetoamplification in a bipolar magnetic junction transistor.

    Science.gov (United States)

    Rangaraju, N; Peters, J A; Wessels, B W

    2010-09-10

    We have demonstrated the first bipolar magnetic junction transistor using a dilute magnetic semiconductor. For an InMnAs p-n-p transistor magnetoamplification is observed at room temperature. The observed magnetoamplification is attributed to the magnetoresistance of the magnetic semiconductor InMnAs heterojunction. The magnetic field dependence of the transistor characteristics confirm that the magnetoamplification results from the junction magnetoresistance. To describe the experimentally observed transistor characteristics, we propose a modified Ebers-Moll model that includes a series magnetoresistance attributed to spin-selective conduction. The capability of magnetic field control of the amplification in an all-semiconductor transistor at room temperature potentially enables the creation of new computer logic architecture where the spin of the carriers is utilized.

  17. Radiation Damage In Advanced Bipolar Transistors

    Science.gov (United States)

    Zoutendyk, John A.; Goben, Charles A.; Berndt, Dale F.

    1989-01-01

    Report describes measurements of common-emitter current gains (hFE) of advanced bipolar silicon transistors before, during, and after irradiation with 275-MeV bromine ions, 2.5-MeV electrons, and conductivity rays from cobalt-60 atoms.

  18. Polyphosphonium-based ion bipolar junction transistors.

    Science.gov (United States)

    Gabrielsson, Erik O; Tybrandt, Klas; Berggren, Magnus

    2014-11-01

    Advancements in the field of electronics during the past few decades have inspired the use of transistors in a diversity of research fields, including biology and medicine. However, signals in living organisms are not only carried by electrons but also through fluxes of ions and biomolecules. Thus, in order to implement the transistor functionality to control biological signals, devices that can modulate currents of ions and biomolecules, i.e., ionic transistors and diodes, are needed. One successful approach for modulation of ionic currents is to use oppositely charged ion-selective membranes to form so called ion bipolar junction transistors (IBJTs). Unfortunately, overall IBJT device performance has been hindered due to the typical low mobility of ions, large geometries of the ion bipolar junction materials, and the possibility of electric field enhanced (EFE) water dissociation in the junction. Here, we introduce a novel polyphosphonium-based anion-selective material into npn-type IBJTs. The new material does not show EFE water dissociation and therefore allows for a reduction of junction length down to 2 μm, which significantly improves the switching performance of the ion transistor to 2 s. The presented improvement in speed as well the simplified design will be useful for future development of advanced iontronic circuits employing IBJTs, for example, addressable drug-delivery devices.

  19. Total Dose Effects in Conventional Bipolar Transistors

    Science.gov (United States)

    Johnston, A. H.; Swift, G. W.; Rax, B. G.

    1994-01-01

    This paper examines various factors in bipolar device construction and design, and discusses their impact on radiation hardness. The intent of the paper is to improve understanding of the underlying mechanisms for practical devices without special test structures, and to provide (1) guidance in ways to select transistor designs that are more resistant to radiation damage, and (2) methods to estimate the maximum amount of damage that might be expected from a basic transistor design. The latter factor is extremely important in assessing the risk that future lots of devices will be substantially below design limits, which are usually based on test data for older devices.

  20. Spin gated transistors for reprogrammable logic

    Science.gov (United States)

    Ciccarelli, Chiara; Gonzalez-Zalba, Fernando; Irvine, Andrew; Campion, Richard; Zarbo, Liviu; Gallagher, Brian; Ferguson, Andrew; Jungwirth, Tomas; Wunderlich, Joerg; Institute of Physics ASCR Collaboration; University of Nottingham Collaboration; Hitachi Cambridge Laboratory Team; Institute of Physics ASCR Collaboration; University of Nottingham Collaboration; University of Cambridge Team

    2014-03-01

    In spin-orbit coupled magnetic materials the chemical potential depends on the orientation of the magnetisation. By making the gate of a field effect transistor magnetic, it is possible to tune the channel conductance not only electrically but also magnetically. We show that these magnetic transistor can be used to realise non-volatile reprogrammable Boolean logic. The non-volatile reconfigurable capability resides in the magnetization-dependent band structure of the magnetic stack. A change in magnetization orientation produces a change in the electrochemical potential, which induces a charge accumulation in the correspondent gate electrode. This is readily sensed by a field-effect device such as standard field-effect transistors or more exotic single-electron transistors. We propose circuits for low power consumption applications that can be magnetically switched between NAND and OR logic functions and between NOR and AND logic functions.

  1. Dose Rate Effects in Linear Bipolar Transistors

    Science.gov (United States)

    Johnston, Allan; Swimm, Randall; Harris, R. D.; Thorbourn, Dennis

    2011-01-01

    Dose rate effects are examined in linear bipolar transistors at high and low dose rates. At high dose rates, approximately 50% of the damage anneals at room temperature, even though these devices exhibit enhanced damage at low dose rate. The unexpected recovery of a significant fraction of the damage after tests at high dose rate requires changes in existing test standards. Tests at low temperature with a one-second radiation pulse width show that damage continues to increase for more than 3000 seconds afterward, consistent with predictions of the CTRW model for oxides with a thickness of 700 nm.

  2. 100-nm gate lithography for double-gate transistors

    Science.gov (United States)

    Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

    2001-09-01

    The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

  3. Atomtronics and basic logic: Constructing AND and OR gates from atomtronic transistors

    Science.gov (United States)

    Pepino, Ronald; Cooper, John; Anderson, Dana; Holland, Murray

    2008-05-01

    Our atomtronics research focuses on creating an analogy of electronic devices and circuits with ultracold atoms. Such an analogy arises from the highly tunable band structure of ultracold neutral atoms trapped in optical lattices. In previous work it has been demonstrated that the electronic behavior of a diode, field effect transistor (FET), and bipolar junction transistor (BJT) can all be realized in systems composed of optical lattices connected to reservoirs of neutral, ultracold atoms. We demonstrate that the behavior of simple logic gates namely, the AND and OR gates, can be realized by connecting the BJTs in the traditional electronic manner.

  4. Pressure Sensitive Insulated Gate Field Effect Transistor

    Science.gov (United States)

    Suminto, James Tjan-Meng

    A pressure sensitive insulated gate field effect transistor has been developed. The device is an elevated gate field-effect-transistor. It consists of a p-type silicon substrate in which two n^+ region, the source and drain, are formed. The gate electrode is a metal film sandwiched in an insulated micro-diaphragm resembling a pill-box which covers the gate oxide, drain, and source. The space between the gate electrode and the oxide is vacuum or an air-gap. When pressure is applied on the diaphragm it deflects and causes a change in the gate capacitance, and thus modulates the conductance of the channel between source and drain. A general theory dealing with the characteristic of this pressure sensitive insulated gate field effect transistor has been derived, and the device fabricated. The fabrication process utilizes the standard integrated circuit fabrication method. It features a batch fabrication of field effect devices followed by the batch fabrication of the deposited diaphragm on top of each field effect device. The keys steps of the diaphragm fabrication are the formation of spacer layer, formation of the diaphragm layer, and the subsequent removal of the spacer layer. The chip size of the device is 600 μm x 1050 mum. The diaphragm size is 200 μm x 200 mum. Characterization of the device has been performed. The current-voltage characteristics with pressure as parameters have been demonstrated and the current-pressure transfer curves obtained. They show non-linear characteristics as those of conventional capacitive pressure sensors. The linearity of threshold voltage versus pressure transfer curves has been demonstrated. The temperature effect on the device performances has been tested. The temperature coefficient of threshold voltage, rather than the electron mobility, has dominated the temperature coefficient of the device. Two temperature compensation schemes have been tested: one method is by connecting two identical PSIGFET in a differential amplifier

  5. Silicon Germanium Heterojunction Bipolar Transistor for Digital Application

    Directory of Open Access Journals (Sweden)

    Engelin Shintadewi Julian

    2012-09-01

    Full Text Available Bipolar transistor performances can be characterized by figures of merit such as cutoff frequency, maximum frequency of oscillation and ECL gate delay. We studied the required figures of merit for digital application and the effects of lateral and vertical scaling to the figures of merit of SiGe HBT. With lateral scaling, the width of emitter finger is scaled down from 0.25 to 0.12 ?m while with the vertical scaling, the base width is scaled down to reduce the base delay. We also observed the effects of Ge profile and Ge fraction to the devices performances. Bipole3 5.3.1G is used to help us in the study. We found that high frequency cutoff and maximum frequency of oscillation as well as low ECL gate delay are all important for digital applications. Scaling down the emitter finger width enhanced the maximum frequency of oscillation and reduced ECL gate delay significantly while scaling down the base width increased the cutoff frequency and current gain.

  6. Review of Heterojunctin Bipolar Transistor Structure, Applications, and Reliability

    Science.gov (United States)

    Lee, C.; Kayali, S.

    1993-01-01

    Heterojunction Bipolar Transistors (HBTs) are increasingly employed in high frequency, high linerity, and high efficiency applications. As the utilization of these devices becomes more widespread, their operation will be viewed with more scrutiny.

  7. A high current gain gate-controlled lateral bipolar junction transistor with 90 nm CMOS technology for future RF SoC applications

    Science.gov (United States)

    Chen, Shuo-Mao; Fang, Yean-Kuen; Yeh, Wen-Kuan; Lee, I. C.; Chiang, Yen-Ting

    2008-08-01

    A CMOS-compatible gate-controlled lateral BJT (GC-LBJT) was prepared with a conventional 90 nm CMOS technology for radio frequency system-on-chip (RF SoC) applications. The emitter injection efficiency and the doping profile in P-well were optimized by properly controlling source, drain, and well implants. Consequently, the GC-LBJT with a gate length of 0.15 μm can achieve a current gain over 2000 and 17/19 GHz for the fT/fmax, respectively, which are 1000%, 200%, and 60% improvements in current gain, fT and fmax, respectively as compared to the LBJT reported previously.

  8. Flexible Proton-Gated Oxide Synaptic Transistors on Si Membrane.

    Science.gov (United States)

    Zhu, Li Qiang; Wan, Chang Jin; Gao, Ping Qi; Liu, Yang Hui; Xiao, Hui; Ye, Ji Chun; Wan, Qing

    2016-08-24

    Ion-conducting materials have received considerable attention for their applications in fuel cells, electrochemical devices, and sensors. Here, flexible indium zinc oxide (InZnO) synaptic transistors with multiple presynaptic inputs gated by proton-conducting phosphorosilicate glass-based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton-gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton-gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multigates coupled flexible proton-gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing.

  9. Employment Of IGBT-Transistors For Bipolar Impulsed Micro-Arc Oxidation

    Directory of Open Access Journals (Sweden)

    Krainyukov Alexander

    2015-09-01

    Full Text Available The paper is devoted to the use of insulated gate bipolar transistors (IGBT for the micro-arc oxidation (MAO process. The technical requirements to the current switches of power supplies for the pulsed bipolar MAO technology have been developed. The research installation for investigating the IGBT commutation processes during the pulse anode-cathode oxidation has been constructed. The experiments have been performed with its help in order to estimate the possibility of using half-bridge IGBT-modules with different drivers. The research results of the commutation processes investigation for different IGBT half- bridge modules are presented.

  10. Npn double heterostructure bipolar transistor with ingaasn base region

    Science.gov (United States)

    Chang, Ping-Chih; Baca, Albert G.; Li, Nein-Yi; Hou, Hong Q.; Ashby, Carol I. H.

    2004-07-20

    An NPN double heterostructure bipolar transistor (DHBT) is disclosed with a base region comprising a layer of p-type-doped indium gallium arsenide nitride (InGaAsN) sandwiched between n-type-doped collector and emitter regions. The use of InGaAsN for the base region lowers the transistor turn-on voltage, V.sub.on, thereby reducing power dissipation within the device. The NPN transistor, which has applications for forming low-power electronic circuitry, is formed on a gallium arsenide (GaAs) substrate and can be fabricated at commercial GaAs foundries. Methods for fabricating the NPN transistor are also disclosed.

  11. Two-dimensional bipolar junction transistors

    Science.gov (United States)

    Gharekhanlou, Behnaz; Khorasani, Sina; Sarvari, Reza

    2014-03-01

    Recent development in fabrication technology of planar two-dimensional (2D) materials has introduced the possibility of numerous novel applications. Our recent analysis has revealed that by definition of p-n junctions through appropriate patterned doping of 2D semiconductors, ideal exponential I-V characteristics may be expected. However, the theory of 2D junctions turns out to be very different to that of standard bulk junctions. Based on this theory of 2D diodes, we construct for the first time a model to describe 2D bipolar junction transistors (2D-BJTs). We derive the small-signal equivalent model, and estimate the performance of a 2D-BJT device based on graphone as the example material. A current gain of about 138 and maximum threshold frequency of 77 GHz, together with a power-delay product of only 4 fJ per 1 μm lateral width is expected at an operating voltage of 5 V. In addition, we derive the necessary formulae and a new approximate solution for the continuity equation in the 2D configuration, which have been verified against numerical solutions.

  12. Modeling of enclosed-gate layout transistors as ESD protection device based on conformal mapping method

    International Nuclear Information System (INIS)

    Zhang Jia; Yang Haigang; Sun Jiabin; Yu Le; Wei Yuanfeng

    2014-01-01

    This paper proposes a novel technique for modeling the electrostatic discharge (ESD) characteristic of the enclosed-gate layout transistors (ELTs). The model consists of an ELT, a parasitic bipolar transistor, and a substrate resistor. The ELT is decomposed into edge and corner transistors by solving the electrostatic field problem through the conformal mapping method, and these transistors are separately modeled by BSIM (Berkeley Short-channel IGFET Model). Fast simulation speed and easy implementation is obtained as the model can be incorporated into standard SPICE simulation. The model parameters are extracted from the critical point of the snapback curve, and simulation results are presented and compared to experimental data for verification. (semiconductor integrated circuits)

  13. Heterojunction bipolar transistor technology for data acquisition and communication

    Science.gov (United States)

    Wang, C.; Chang, M.; Beccue, S.; Nubling, R.; Zampardi, P.; Sheng, N.; Pierson, R.

    1992-01-01

    Heterojunction Bipolar Transistor (HBT) technology has emerged as one of the most promising technologies for ultrahigh-speed integrated circuits. HBT circuits for digital and analog applications, data conversion, and power amplification have been realized, with speed performance well above 20 GHz. At Rockwell, a baseline AlGaAs/GaAs HBT technology has been established in a manufacturing facility. This paper describes the HBT technology, transistor characteristics, and HBT circuits for data acquisition and communication.

  14. Bipolar Junction Transistors in Two-Dimensional WSe2 with Large Current and Photocurrent Gains.

    Science.gov (United States)

    Agnihotri, Pratik; Dhakras, Prathamesh; Lee, Ji Ung

    2016-07-13

    In the development of semiconductor devices, the bipolar junction transistor (BJT) features prominently as being the first solid state transistor that helped to usher in the digital revolution. For any new semiconductor, therefore, the fabrication and characterization of the BJT are important for both technological importance and historical significance. Here, we demonstrate a BJT device in exfoliated TMD semiconductor WSe2. We use buried gates to electrostatically create doped regions with back-to-back p-n junctions. We demonstrate two central characteristics of a bipolar device: current gain when operated as a BJT and a photocurrent gain when operated as a phototransistor. We demonstrate a current gain of 1000 and photocurrent gain of 40 and describe features that enhance these properties due to the doping technique that we employ.

  15. Toward complementary ionic circuits: the npn ion bipolar junction transistor.

    Science.gov (United States)

    Tybrandt, Klas; Gabrielsson, Erik O; Berggren, Magnus

    2011-07-06

    Many biomolecules are charged and may therefore be transported with ionic currents. As a step toward addressable ionic delivery circuits, we report on the development of a npn ion bipolar junction transistor (npn-IBJT) as an active control element of anionic currents in general, and specifically, demonstrate actively modulated delivery of the neurotransmitter glutamic acid. The functional materials of this transistor are ion exchange layers and conjugated polymers. The npn-IBJT shows stable transistor characteristics over extensive time of operation and ion current switch times below 10 s. Our results promise complementary chemical circuits similar to the electronic equivalence, which has proven invaluable in conventional electronic applications.

  16. A gallium phosphide high-temperature bipolar junction transistor

    Science.gov (United States)

    Zipperian, T. E.; Dawson, L. R.; Chaffin, R. J.

    1981-01-01

    Preliminary results are reported on the development of a high temperature (350 C) gallium phosphide bipolar junction transistor (BJT) for geothermal and other energy applications. This four-layer p(+)n(-)pp(+) structure was formed by liquid phase epitaxy using a supercooling technique to insure uniform nucleation of the thin layers. Magnesium was used as the p-type dopant to avoid excessive out-diffusion into the lightly doped base. By appropriate choice of electrodes, the device may also be driven as an n-channel junction field-effect transistor. The initial design suffers from a series resistance problem which limits the transistor's usefulness at high temperatures.

  17. Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

    Science.gov (United States)

    Ghosh, Bahniman; Mondal, Partha; Akram, M. W.; Bal, Punyasloka; Salimath, Akshay Kumar

    2014-06-01

    We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel. These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n-p-n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.

  18. High mobility polymer gated organic field effect transistor using zinc ...

    Indian Academy of Sciences (India)

    Organic semiconductor; field effect transistor; phthalocyanine; high mobility. Abstract. Organic thin film transistors were fabricated using evaporated zinc phthalocyanine as the active layer. Parylene film prepared by chemical vapour deposition was used as the organic gate insulator. The annealing of the samples was ...

  19. Bipolar Transistors Can Detect Charge in Electrostatic Experiments

    Science.gov (United States)

    Dvorak, L.

    2012-01-01

    A simple charge indicator with bipolar transistors is described that can be used in various electrostatic experiments. Its behaviour enables us to elucidate links between 'static electricity' and electric currents. In addition it allows us to relate the sign of static charges to the sign of the terminals of an ordinary battery. (Contains 7 figures…

  20. Experiments with Charge Indicator Based on Bipolar Transistors

    Science.gov (United States)

    Dvorak, Leos; Planinsic, Gorazd

    2012-01-01

    A simple charge indicator with bipolar transistors described recently enables us to perform a number of experiments suitable for high-school physics. Several such experiments are presented and discussed in this paper as well as some features of the indicator important for its use in schools, namely its sensitivity and robustness, i.e. the…

  1. Modeling of the bipolar transistor under different pulse ionizing radiations

    Science.gov (United States)

    Antonova, A. M.; Skorobogatov, P. K.

    2017-01-01

    This paper describes a 2D model of the bipolar transistor 2T312 under gamma, X-ray and laser pulse ionizing radiations. Both the Finite Element Discretization and Semiconductor module of Comsol 5.1 are used. There is an analysis of energy deposition in this device under different radiations and the results of transient ionizing current response for some different conditions.

  2. Gate-Controlled WSe2Transistors Using a Buried Triple-Gate Structure.

    Science.gov (United States)

    Müller, M R; Salazar, R; Fathipour, S; Xu, H; Kallis, K; Künzelmann, U; Seabaugh, A; Appenzeller, J; Knoch, J

    2016-12-01

    In the present paper, we show tungsten diselenide (WSe 2 ) devices that can be tuned to operate as n-type and p-type field-effect transistors (FETs) as well as band-to-band tunnel transistors on the same flake. Source, channel, and drain areas of the WSe 2 flake are adjusted, using buried triple-gate substrates with three independently controllable gates. The device characteristics found in the tunnel transistor configuration are determined by the particular geometry of the buried triple-gate structure, consistent with a simple estimation of the expected off-state behavior.

  3. Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

    Directory of Open Access Journals (Sweden)

    S. M. Rezaul Hasan

    2002-01-01

    Full Text Available This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power-delay product figure-of-merit is found to be significantly enhanced without any associated silicon-area penalty. In order to experimentally verify the reduction in power dissipation, original and reordered structures were fabricated using the MOSIS 2 μm N-well analog CMOS process which has a P-base layer for bipolar NPN option. Measured results shows a 20% reduction in the power dissipation for the transistor reordered structure, which is in close agreement with the simulation.

  4. Modeling of charge transport in ion bipolar junction transistors.

    Science.gov (United States)

    Volkov, Anton V; Tybrandt, Klas; Berggren, Magnus; Zozoulenko, Igor V

    2014-06-17

    Spatiotemporal control of the complex chemical microenvironment is of great importance to many fields within life science. One way to facilitate such control is to construct delivery circuits, comprising arrays of dispensing outlets, for ions and charged biomolecules based on ionic transistors. This allows for addressability of ionic signals, which opens up for spatiotemporally controlled delivery in a highly complex manner. One class of ionic transistors, the ion bipolar junction transistors (IBJTs), is especially attractive for these applications because these transistors are functional at physiological conditions and have been employed to modulate the delivery of neurotransmitters to regulate signaling in neuronal cells. Further, the first integrated complementary ionic circuits were recently developed on the basis of these ionic transistors. However, a detailed understanding of the device physics of these transistors is still lacking and hampers further development of components and circuits. Here, we report on the modeling of IBJTs using Poisson's and Nernst-Planck equations and the finite element method. A two-dimensional model of the device is employed that successfully reproduces the main characteristics of the measurement data. On the basis of the detailed concentration and potential profiles provided by the model, the different modes of operation of the transistor are analyzed as well as the transitions between the different modes. The model correctly predicts the measured threshold voltage, which is explained in terms of membrane potentials. All in all, the results provide the basis for a detailed understanding of IBJT operation. This new knowledge is employed to discuss potential improvements of ion bipolar junction transistors in terms of miniaturization and device parameters.

  5. Vertical bipolar charge plasma transistor with buried metal layer.

    Science.gov (United States)

    Nadda, Kanika; Kumar, M Jagadesh

    2015-01-19

    A self-aligned vertical Bipolar Charge Plasma Transistor (V-BCPT) with a buried metal layer between undoped silicon and buried oxide of the silicon-on-insulator substrate, is reported in this paper. Using two-dimensional device simulation, the electrical performance of the proposed device is evaluated in detail. Our simulation results demonstrate that the V-BCPT not only has very high current gain but also exhibits high BVCEO · f(T) product making it highly suitable for mixed signal high speed circuits. The proposed device structure is also suitable for realizing doping-less bipolar charge plasma transistor using compound semiconductors such as GaAs, SiC with low thermal budgets. The device is also immune to non-ideal current crowding effects cropping up at high current densities.

  6. InP Heterojunction Bipolar Transistor Amplifiers to 255 GHz

    Science.gov (United States)

    Radisic, Vesna; Sawdai, Donald; Scott, Dennis; Deal, William; Dang, Linh; Li, Danny; Cavus, Abdullah; To, Richard; Lai, Richard

    2009-01-01

    Two single-stage InP heterojunction bipolar transistor (HBT) amplifiers operate at 184 and 255 GHz, using Northrop Grumman Corporation s InP HBT MMIC (monolithic microwave integrated circuit) technology. At the time of this reporting, these are reported to be the highest HBT amplifiers ever created. The purpose of the amplifier design is to evaluate the technology capability for high-frequency designs and verify the model for future development work.

  7. Doping To Reduce Base Resistances Of Bipolar Transistors

    Science.gov (United States)

    Lin, True-Lon

    1991-01-01

    Modified doping profile proposed to reduce base resistance of bipolar transistors. A p/p+ base-doping profile reduces base resistance without reducing current gain. Proposed low/high base-doping profile realized by such low-temperature deposition techniques as molecular-beam epitaxy, ultra-high-vacuum chemical-vapor deposition, and limited-reaction epitaxy. Produces desired doping profiles without excessive diffusion of dopant.

  8. Ionizing radiation effects on conduction and low frequency noise in bipolar transistors

    International Nuclear Information System (INIS)

    Blasquez, G.; Roux-Nogatchewsky, M.

    1980-01-01

    Gate controlled NPN bipolar transistors were irradiated with doses ranging between 10 and 10 4 Gy X rays supplied by a generator functioning at 150 kV. An increase of great amplitude of the base current and of the low frequency noise were observed for both depleted and inverted base surface conditions. It has been shown that these increases were due to the enhancement of the total surface recombination velocity, of the positive charge within the oxide and also of the density of noise traps. Positive correlations were observed between these three surface parameters. These results have been attributed to the ionization of silica by X rays. The transistors partially recovered by means of thermal treatments. It has been suggested that it does not exist specific hardening methods to minimize the noise sensitivity to irradiation [fr

  9. Anomalous dose rate effects in gamma irradiated SiGe heterojunction bipolar transistors

    International Nuclear Information System (INIS)

    Banerjee, G.; Niu, G.; Cressler, J.D.; Clark, S.D.; Palmer, M.J.; Ahlgren, D.C.

    1999-01-01

    Low dose rate (LDR) cobalt-60 (0.1 rad(Si)/s) gamma irradiated Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) were studied. Comparisons were made with devices irradiated with 300 rad(Si)/s gamma radiation to verify if LDR radiation is a serious radiation hardness assurance (RHA) issue. Almost no LDR degradation was observed in this technology up to 50 krad(Si). The assumption of the presence of two competing mechanisms is justified by experimental results. At low total dose (le20 krad), an anomalous base current decrease was observed which is attributed to self-annealing of deep-level traps to shallower levels. An increase in base current at larger total doses is attributed to radiation induced generation-recombination (G/R) center generation. Experiments on gate-assisted lateral PNP transistors and 2D numerical simulations using MEDICI were used to confirm these assertions

  10. Single electron transistor with P-type sidewall spacer gates.

    Science.gov (United States)

    Lee, Jung Han; Li, Dong Hua; Lee, Joung-Eob; Kang, Kwon-Chil; Kim, Kyungwan; Park, Byung-Gook

    2011-07-01

    A single-electron transistor (SET) is one of the promising solutions to overcome the scaling limit of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). Up to now, various kinds of SETs are being proposed and SETs with a dual gate (DG) structure using an electrical potential barrier have been demonstrated for room temperature operation. To operate DG-SETs, however, extra bias of side gates is necessary. It causes new problems that the electrode for side gates and the extra bias for electrical barrier increase the complexity in circuit design and operation power consumption, respectively. For the reason, a new mechanism using work function (WF) difference is applied to operate a SET at room temperature by three electrodes. Its structure consists of an undoped active region, a control gate, n-doped source/drain electrodes, and metal/silicide or p-type silicon side gates, and a SET with metal/silicide gates or p-type silicon gates forms tunnel barriers induced by work function between an undoped channel and grounded side gates. Via simulation, the effectiveness of the new mechanism is confirmed through various silicide materials that have different WF values. Furthermore, by considering the realistic conditions of the fabrication process, SET with p-type sidewall spacer gates was designed, and its brief fabrication process was introduced. The characteristics of its electrical barrier and the controllability of its control gate were also confirmed via simulation. Finally, a single-hole transistor with n-type sidewall spacer gates was designed.

  11. Ambipolar nonvolatile memory based on a quantum-dot transistor with a nanoscale floating gate

    International Nuclear Information System (INIS)

    Che, Yongli; Zhang, Yating; Song, Xiaoxian; Cao, Mingxuan; Zhang, Guizhong; Yao, Jianquan; Cao, Xiaolong; Dai, Haitao; Yang, Junbo

    2016-01-01

    Using only solution processing methods, we developed ambipolar quantum-dot (QD) transistor floating-gate memory (FGM) that uses Au nanoparticles as a floating gate. Because of the bipolarity of the active channel of PbSe QDs, the memory could easily trap holes or electrons in the floating gate by programming/erasing (P/E) operations, which could shift the threshold voltage both up and down. As a result, the memory exhibited good programmable memory characteristics: a large memory window (ΔV th  ∼ 15 V) and a long retention time (>10 5  s). The magnitude of ΔV th depended on both P/E voltages and the bias voltage (V DS ): ΔV th was a cubic function to V P/E and linearly depended on V DS . Therefore, this FGM based on a QD transistor is a promising alternative to its inorganic counterparts owing to its advantages of bipolarity, high mobility, low cost, and large-area production.

  12. Ambipolar nonvolatile memory based on a quantum-dot transistor with a nanoscale floating gate

    Energy Technology Data Exchange (ETDEWEB)

    Che, Yongli; Zhang, Yating, E-mail: yating@tju.edu.cn; Song, Xiaoxian; Cao, Mingxuan; Zhang, Guizhong; Yao, Jianquan [Institute of Laser and Opto-Electronics, College of Precision Instruments and Opto-Electronics Engineering, Tianjin University, Tianjin 300072 (China); Key Laboratory of Opto-Electronics Information Technology, Ministry of Education, Tianjin University, Tianjin 300072 (China); Cao, Xiaolong [Institute of Laser and Opto-Electronics, College of Precision Instruments and Opto-Electronics Engineering, Tianjin University, Tianjin 300072 (China); Key Laboratory of Opto-Electronics Information Technology, Ministry of Education, Tianjin University, Tianjin 300072 (China); College of Mechanical and Electronic Engineering, Shandong University of Science and Technology, Qingdao 266590 (China); Dai, Haitao [Tianjin Key Laboratory of Low Dimensional Materials Physics and Preparing Technology, School of Science, Tianjin University, Tianjin 300072 (China); Yang, Junbo [Center of Material Science, National University of Defense Technology, Changsha 410073 (China)

    2016-07-04

    Using only solution processing methods, we developed ambipolar quantum-dot (QD) transistor floating-gate memory (FGM) that uses Au nanoparticles as a floating gate. Because of the bipolarity of the active channel of PbSe QDs, the memory could easily trap holes or electrons in the floating gate by programming/erasing (P/E) operations, which could shift the threshold voltage both up and down. As a result, the memory exhibited good programmable memory characteristics: a large memory window (ΔV{sub th} ∼ 15 V) and a long retention time (>10{sup 5 }s). The magnitude of ΔV{sub th} depended on both P/E voltages and the bias voltage (V{sub DS}): ΔV{sub th} was a cubic function to V{sub P/E} and linearly depended on V{sub DS}. Therefore, this FGM based on a QD transistor is a promising alternative to its inorganic counterparts owing to its advantages of bipolarity, high mobility, low cost, and large-area production.

  13. Interdigitated Extended Gate Field Effect Transistor Without Reference Electrode

    Science.gov (United States)

    Ali, Ghusoon M.

    2017-02-01

    An interdigitated extended gate field effect transistor (IEGFET) has been proposed as a modified pH sensor structure of an extended gate field effect transistor (EGFET). The reference electrode and the extended gate in the conventional device have been replaced by a single interdigitated extended gate. A metal-semiconductor-metal interdigitated extended gate containing two multi-finger Ni electrodes based on zinc oxide (ZnO) thin film as a pH-sensitive membrane. ZnO thin film was grown on a p-type Si (100) substrate by the sol-gel technique. The fabricated extended gate is connected to a commercial metal-oxide-semiconductor field-effect transistor device in CD4007UB. The experimental data show that this structure has real time and linear pH voltage and current sensitivities in a concentration range between pH 4 and 11. The voltage and current sensitivities are found to be about 22.4 mV/pH and 45 μA/pH, respectively. Reference electrode elimination makes the IEGFET device simple to fabricate, easy to carry out the measurements, needing a small volume of solution to test and suitable for disposable biosensor applications. Furthermore, this uncomplicated structure could be extended to fabricate multiple ions microsensors and lab-on-chip devices.

  14. High mobility polymer gated organic field effect transistor using zinc ...

    Indian Academy of Sciences (India)

    Mater. Sci., Vol. 37, No. 1, February 2014, pp. 95–99. c Indian Academy of Sciences. High mobility polymer gated organic field effect transistor using zinc phthalocyanine. K R RAJESH. ∗. , V KANNAN, M R KIM, Y S CHAE and J K RHEE. Millimeter- Wave Innovation Technology Research Centre (MINT), Dongguk University,.

  15. Irradiation effect on back-gate graphene field-effect transistor

    Science.gov (United States)

    Chen, Xinlu; Srivastava, Ashok; Sharma, Ashwani K.; Mayberry, Clay

    2017-05-01

    The effects of irradiations on MOSFET and bipolar junction transistors are well known though irradiation mechanisms in two-dimensional graphene and related devices are still being investigated. In this work, we investigate irradiation mechanism based on a semi-empirical model for the graphene back-gate transistor and quantitatively analyze the irradiation influences on electrical properties of the device structure. The irradiation shifts the current which changes the region of device operation, degrades the mobility and increases the channel resistance which can increase the power dissipation. The main mechanism causing the degradation in performance of devices is the oxide trap charges near the SiO2/graphene interface and graphene layer traps charges.

  16. Bipolar single-wall carbon nanotube field-effect transistor

    OpenAIRE

    Babic, Bakir; Iqbal, Mahdi; Schonenberger, Christian

    2002-01-01

    We use a simultaneous flow of ethylene and hydrogen gases to grow single wall carbon nanotubes by chemical vapor deposition. Strong coupling to the gate is inferred from transport measurements for both metallic and semiconducting tubes. At low-temperatures, our samples act as single-electron transistors where the transport mechanism is mainly governed by Coulomb blockade. The measurements reveal very rich quantized energy level spectra spanning from valence to conduction band. The Coulomb dia...

  17. Implantation-Free 4H-SiC Bipolar Junction Transistors with Double Base Epi-layers

    Science.gov (United States)

    2007-05-14

    junction transistor ( BJT ) which is completely free of ion implantation and hence is free of the implantation- induced crystal damages and high-temperature...Index Terms—Silicon carbide, bipolar junction transistors ( BJTs ), power transistors ...Std Z39-18 I. INTRODUCTION 4H-SiC bipolar junction transistor ( BJT ) is an important switching device for high power and high temperature

  18. Single-event burnout of power bipolar junction transistors

    International Nuclear Information System (INIS)

    Titus, J.L.; Johnson, G.H.; Schrimpf, R.D.; Galloway, K.F.

    1991-01-01

    Experimental evidence of single-event burnout of power bipolar junctions transistors (BJTs) is reported for the first time. Several commercial power BJTs were characterized in a simulated cosmic ray environment using mono-energetic ions at the tandem Van de Graaff accelerator facility at Brookhaven National Laboratory. Most of the device types exposed to this simulated environment exhibited burnout behavior. In this paper the experimental technique, data, and results are presented, while a qualitative model is used to help explain those results and trends observed in this experiment

  19. Top-gate pentacene-based organic field-effect transistor with amorphous rubrene gate insulator

    Science.gov (United States)

    Hiroki, Mizuha; Maeda, Yasutaka; Ohmi, Shun-ichiro

    2018-02-01

    The scaling of organic field-effect transistors (OFETs) is necessary for high-density integration and for this, OFETs with a top-gate configuration are required. There have been several reports of damageless lithography processes for organic semiconductor or insulator layers. However, it is still difficult to fabricate scaled OFETs with a top-gate configuration. In this study, the lift-off process and the device characteristics of the OFETs with a top-gate configuration utilizing an amorphous (α) rubrene gate insulator were investigated. We have confirmed that α-rubrene shows an insulating property, and its extracted linear mobility was 2.5 × 10‑2 cm2/(V·s). The gate length and width were 10 and 60 µm, respectively. From these results, the OFET with a top-gate configuration utilizing an α-rubrene gate insulator is promising for the high-density integration of scaled OFETs.

  20. Theoretical values of various parameters in the Gummel-Poon model of a bipolar junction transistor

    Science.gov (United States)

    Benumof, R.; Zoutendyk, J.

    1986-01-01

    Various parameters in the Gummel-Poon model of a bipolar junction transistor are expressed in terms of the basic structure of a transistor. A consistent theoretical approach is used which facilitates an understanding of the foundations and limitations of the derived formulas. The results enable one to predict how changes in the geometry and composition of a transistor would affect performance.

  1. Four-gate transistor analog multiplier circuit

    Science.gov (United States)

    Mojarradi, Mohammad M. (Inventor); Blalock, Benjamin (Inventor); Cristoloveanu, Sorin (Inventor); Chen, Suheng (Inventor); Akarvardar, Kerem (Inventor)

    2011-01-01

    A differential output analog multiplier circuit utilizing four G.sup.4-FETs, each source connected to a current source. The four G.sup.4-FETs may be grouped into two pairs of two G.sup.4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G.sup.4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

  2. Tunnel field-effect transistor with two gated intrinsic regions

    Directory of Open Access Journals (Sweden)

    Y. Zhang

    2014-07-01

    Full Text Available In this paper, we propose and validate (using simulations a novel design of silicon tunnel field-effect transistor (TFET, based on a reverse-biased p+-p-n-n+ structure. 2D device simulation results show that our devices have significant improvements of switching performance compared with more conventional devices based on p-i-n structure. With independent gate voltages applied to two gated intrinsic regions, band-to-band tunneling (BTBT could take place at the p-n junction, and no abrupt degenerate doping profile is required. We developed single-side-gate (SSG structure and double-side-gate (DSG structure. SSG devices with HfO2 gate dielectric have a point subthreshold swing of 9.58 mV/decade, while DSG devices with polysilicon gate electrode material and HfO2 gate dielectric have a point subthreshold swing of 16.39 mV/decade. These DSG devices have ON-current of 0.255 μA/μm, while that is lower for SSG devices. Having two nano-scale independent gates will be quite challenging to realize with good uniformity across the wafer and the improved behavior of our TFET makes it a promising steep-slope switch candidate for further investigations.

  3. Top- and side-gated epitaxial graphene field effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Li, Xuebin; Wu, Xiaosong; Sprinkle, Mike; Ming, Fan; Ruan, Ming; Hu, Yike; De Heer, Walt A. [Georgia Institute of Technology, School of Physics, Atlanta, GA (United States); Berger, Claire [Georgia Institute of Technology, School of Physics, Atlanta, GA (United States); CNRS-Institut Neel, Grenoble (France)

    2010-02-15

    Three types of first generation epitaxial graphene (EG) field effect transistors (FET) are presented and their relative merits are discussed. Graphene is epitaxially grown on both the carbon and silicon faces of hexagonal silicon carbide and patterned with electron beam lithography. The channels have a Hall bar geometry to facilitate magnetoresistance measurements. FETs patterned on the Si-face exhibit off-to-on channel resistance ratios that exceed 30. C-face FETs have lower off-to-on resistance ratios, but their mobilities (up to 5000 cm{sup 2}/Vs) are much larger than that for Si-face transistors. Initial investigations into all-graphene side-gate FET structures are promising. Conductivity (left panel) and transport resistances {rho}{sub xx} and {rho}{sub xy} of a top gate graphene Hall bar on SiC Si-face, showing a sign reversal of the hall coefficient at the resistance peak. (Abstract Copyright [2010], Wiley Periodicals, Inc.)

  4. Simulation of 50-nm Gate Graphene Nanoribbon Transistors

    Directory of Open Access Journals (Sweden)

    Cedric Nanmeni Bondja

    2016-01-01

    Full Text Available An approach to simulate the steady-state and small-signal behavior of GNR MOSFETs (graphene nanoribbon metal-semiconductor-oxide field-effect transistor is presented. GNR material parameters and a method to account for the density of states of one-dimensional systems like GNRs are implemented in a commercial device simulator. This modified tool is used to calculate the current-voltage characteristics as well the cutoff frequency fT and the maximum frequency of oscillation fmax of GNR MOSFETs. Exemplarily, we consider 50-nm gate GNR MOSFETs with N = 7 armchair GNR channels and examine two transistor configurations. The first configuration is a simplified MOSFET structure with a single GNR channel as usually studied by other groups. Furthermore, and for the first time in the literature, we study in detail a transistor structure with multiple parallel GNR channels and interribbon gates. It is shown that the calculated fT of GNR MOSFETs is significantly lower than that of GFETs (FET with gapless large-area graphene channel with comparable gate length due to the mobility degradation in GNRs. On the other hand, GNR MOSFETs show much higher fmax compared to experimental GFETs due the semiconducting nature of the GNR channels and the resulting better saturation of the drain current. Finally, it is shown that the gate control in FETs with multiple parallel GNR channels is improved while the cutoff frequency is degraded compared to single-channel GNR MOSFETs due to parasitic capacitances of the interribbon gates.

  5. Spin-gating of a conventional aluminum single electron transistor

    Science.gov (United States)

    Zarbo, Liviu P.; Ciccarelli, Chiara; Irvine, Andy; Wunderlich, Jörg; Champion, Richard; Gallagher, Brian; Jungwirth, Tomáš; Ferguson, Andrew

    2012-02-01

    We report the realization of a single electron transistor in which electron transport from an aluminum source electrode to an aluminum drain electrode via an aluminum island is controlled by spins in a capacitively coupled magnetic gate electrode. The origin of the effect is in the change of the chemical potential on the gate, formed by the ferromagnetic semiconductor GaMnAs, with changing the direction of the magnetization. In agreement with experimental observations, microscopically calculated anisotropies of the chemical potential with respect to the magnetization orientation are of the order of 10μV which is comparable to the electrical gate voltages required to control the on and off state of the single electron transistor. Our phenomenon belongs to the family of anisotropic magnetoresistance effects which can be observed in ohmic, tunneling or other device geometries. In our case, the entire phenomenon is coded in the dependence of the chemical potential on the spin orientation which allowed us to remove the spin functionality from all current contacts and channels and place it in the capacitively coupled gate electrode. Our spintronic device therefore operates without spin current.

  6. Analysis of gate underlap channel double gate MOS transistor for electrical detection of bio-molecules

    Science.gov (United States)

    Ajay; Narang, Rakhi; Saxena, Manoj; Gupta, Mridula

    2015-12-01

    In this paper, an analytical model for gate drain underlap channel Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG-MOSFET) for label free electrical detection of biomolecules has been proposed. The conformal mapping technique has been used to derive the expressions for surface potential, lateral electric field, energy bands (i.e. conduction and valence band) and threshold voltage (Vth). Subsequently a full drain current model to analyze the sensitivity of the biosensor has been developed. The shift in the threshold voltage and drain current (after the biomolecules interaction with the gate underlap channel region of the MOS transistor) has been used as a sensing metric. All the characteristic trends have been verified through ATLAS (SILVACO) device simulation results.

  7. Bipolar junction transistor models for circuit simulation of cosmic-ray-induced soft errors

    Science.gov (United States)

    Benumof, R.; Zoutendyk, J.

    1984-01-01

    This paper examines bipolar junction transistor models suitable for calculating the effects of large excursions of some of the variables determining the operation of a transistor. Both the Ebers-Moll and Gummel-Poon models are studied, and the junction and diffusion capacitances are evaluated on the basis of the latter model. The most interesting result of this analysis is that a bipolar junction transistor when struck by a cosmic particle may cause a single event upset in an electronic circuit if the transistor is operated at a low forward base-emitter bias.

  8. Polymer-electrolyte-gated nanowire synaptic transistors for neuromorphic applications

    Science.gov (United States)

    Zou, Can; Sun, Jia; Gou, Guangyang; Kong, Ling-An; Qian, Chuan; Dai, Guozhang; Yang, Junliang; Guo, Guang-hua

    2017-09-01

    Polymer-electrolytes are formed by dissolving a salt in polymer instead of water, the conducting mechanism involves the segmental motion-assisted diffusion of ion in the polymer matrix. Here, we report on the fabrication of tin oxide (SnO2) nanowire synaptic transistors using polymer-electrolyte gating. A thin layer of poly(ethylene oxide) and lithium perchlorate (PEO/LiClO4) was deposited on top of the devices, which was used to boost device performances. A voltage spike applied on the in-plane gate attracts ions toward the polymer-electrolyte/SnO2 nanowire interface and the ions are gradually returned after the pulse is removed, which can induce a dynamic excitatory postsynaptic current in the nanowire channel. The SnO2 synaptic transistors exhibit the behavior of short-term plasticity like the paired-pulse facilitation and self-adaptation, which is related to the electric double-effect regulation. In addition, the synaptic logic functions and the logical function transformation are also discussed. Such single SnO2 nanowire-based synaptic transistors are of great importance for future neuromorphic devices.

  9. Enhanced transconductance in a double-gate graphene field-effect transistor

    Science.gov (United States)

    Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

    2018-03-01

    Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

  10. Analysis of the dynamic avalanche of carrier stored trench bipolar transistor (CSTBT) during clamped inductive turn-off transient

    Science.gov (United States)

    Xue, Peng; Fu, Guicui

    2017-03-01

    The dynamic avalanche has a huge impact on the switching robustness of carrier stored trench bipolar transistor (CSTBT). The purpose of this work is to investigate the CSTBT's dynamic avalanche mechanism during clamped inductive turn-off transient. At first, with a Mitsubishi 600 V/150 A CSTBT and a Infineon 600 V/200 A field stop insulated gate bipolar transistor (FS-IGBT) utilized, the clamped inductive turn-off characteristics are obtained by double pulse test. The unclamped inductive switching (UIS) test is also utilized to identify the CSTBT's clamping voltage under dynamic avalanche condition. After the test data analysis, it is found that the CSTBT's dynamic avalanche is abnormal and can be triggered under much looser condition than the conventional buffer layer IGBT. The comparison between the FS-IGBT and CSTBT's experimental results implies that the CSTBT's abnormal dynamic avalanche phenomenon may be induced by the carrier storage (CS) layer. Based on the semiconductor physics, the electric field distribution and dynamic avalanche generation in the depletion region are analyzed. The analysis confirms that the CS layer is the root cause of the CSTBT's abnormal dynamic avalanche mechanism. Moreover, the CSTBT's negative gate capacitance effect is also investigated to clarify the underlying mechanism of the gate voltage bump observed in the test. In the end, the mixed-mode numerical simulation is utilized to reproduce the CSTBT's dynamic avalanche behavior. The simulation results validate the proposed dynamic avalanche mechanisms.

  11. Heterojunction Bipolar Transistor Power Amplifiers for Long-Range X-band Communications Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this SBIR Phase I project, Vega Wave Systems, Inc. will develop and demonstrate a novel InGaP-GaAs heterojunction bipolar transistor power amplifier for...

  12. Fullerene thin-film transistors fabricated on polymeric gate dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Puigdollers, J. [Micro and Nano Technology Group (MNT), Dept. Enginyeria Electronica, Universitat Politecnica Catalunya, C/ Jordi Girona 1-3, Modul C4, 08034-Barcelona (Spain)], E-mail: jpuigd@eel.upc.edu; Voz, C. [Micro and Nano Technology Group (MNT), Dept. Enginyeria Electronica, Universitat Politecnica Catalunya, C/ Jordi Girona 1-3, Modul C4, 08034-Barcelona (Spain); Cheylan, S. [ICFO - Mediterranean Technology Park, Avda del Canal Olimpic s/n, 08860-Castelldefels (Spain); Orpella, A.; Vetter, M.; Alcubilla, R. [Micro and Nano Technology Group (MNT), Dept. Enginyeria Electronica, Universitat Politecnica Catalunya, C/ Jordi Girona 1-3, Modul C4, 08034-Barcelona (Spain)

    2007-07-16

    Thin-film transistors with fullerene as n-type organic semiconductor have been fabricated. A polymeric gate dielectric, polymethyl methacrylate, has been used as an alternative to usual inorganic dielectrics. No significant differences in the microstructure of fullerene thin-films grown on polymethyl methacrylate were observed. Devices with either gold or aluminium top electrodes have been fabricated. Although the lower work-function of aluminium compared to gold should favour electron injection, similar field-effect mobilities in the range of 10{sup -2} cm{sup 2} V{sup -1} s{sup -1} were achieved in both cases. Actually, the output characteristics indicate that organic thin-film transistors behave more linearly with gold than with aluminium electrodes. These results confirm that not only energy barriers determine carrier injection at metal/organic interfaces, but also chemical interactions.

  13. Fullerene thin-film transistors fabricated on polymeric gate dielectric

    International Nuclear Information System (INIS)

    Puigdollers, J.; Voz, C.; Cheylan, S.; Orpella, A.; Vetter, M.; Alcubilla, R.

    2007-01-01

    Thin-film transistors with fullerene as n-type organic semiconductor have been fabricated. A polymeric gate dielectric, polymethyl methacrylate, has been used as an alternative to usual inorganic dielectrics. No significant differences in the microstructure of fullerene thin-films grown on polymethyl methacrylate were observed. Devices with either gold or aluminium top electrodes have been fabricated. Although the lower work-function of aluminium compared to gold should favour electron injection, similar field-effect mobilities in the range of 10 -2 cm 2 V -1 s -1 were achieved in both cases. Actually, the output characteristics indicate that organic thin-film transistors behave more linearly with gold than with aluminium electrodes. These results confirm that not only energy barriers determine carrier injection at metal/organic interfaces, but also chemical interactions

  14. Silicon Nanomembrane Bipolar Junction Transistors for Microwave Frequency Applications

    Science.gov (United States)

    Bavier, John; Ballarotto, Vince; Cumings, John

    2014-03-01

    Silicon nanomembranes (SiNMs) are a promising material for flexible semiconductor devices due to their high carrier mobility and compatibility with standard CMOS processing. Previous studies have reported SiNM field-effect transistors with operating frequencies as high as 12 GHz. In order to expand the utility of SiNM devices, a method for the fabrication of monocrystalline microwave frequency silicon bipolar junction transistors (BJTs) will be presented. High-temperature processing of SiNM BJT devices is performed on a Silicon-on-Insulator (SOI) wafer. Using angled ion implantation, conformal chemical vapor deposition and anisotropic reactive ion etching, a poly-silicon sidewall spacer is formed. This spacer defines a base region approximately 200nm wide without the use of electron beam lithography. Devices are then released using selective wet etching in HF and transferred to alternate flexible substrates. Microwave frequency data will be presented, and the effects of the transfer process on device performance will be discussed.

  15. Neutron effects on the electrical and switching characteristics of NPN bipolar power transistors

    Science.gov (United States)

    Frasca, Albert J.; Schwarze, Gene E.

    1988-01-01

    The use of nuclear reactors to generate electrical power for future space missions will require the electrical components used in the power conditioning, control, and transmission subsystem to operate in the associated radiation environments. An initial assessment of neutron irradiation on the electrical and switching characteristics of commercial high power NPN bipolar transistors was investigated. The results clearly show the detrimental effects caused by neutron irradiation on the electrical and switching characteristics of the NPN bipolar power transistor.

  16. Electrical coupling of single cardiac rat myocytes to field-effect and bipolar transistors.

    Science.gov (United States)

    Kind, Thomas; Issing, Matthias; Arnold, Rüdiger; Müller, Bernt

    2002-12-01

    A novel bipolar transistor for extracellular recording the electrical activity of biological cells is presented, and the electrical behavior compared with the field-effect transistor (FET). Electrical coupling is examined between single cells separated from the heart of adults rats (cardiac myocytes) and both types of transistors. To initiate a local extracellular voltage, the cells are periodically stimulated by a patch pipette in voltage clamp and current clamp mode. The local extracellular voltage is measured by the planar integrated electronic sensors: the bipolar and the FET. The small signal transistor currents correspond to the local extracellular voltage. The two types of sensor transistors used here were developed and manufactured in the laboratory of our institute. The manufacturing process and the interfaces between myocytes and transistors are described. The recordings are interpreted by way of simulation based on the point-contact model and the single cardiac myocyte model.

  17. Complementary vertical bipolar transistor process using high-energy ion implantation

    NARCIS (Netherlands)

    Ragay, F.W.; Ragay, F.W.; Aarnink, Antonius A.I.; Wallinga, Hans

    1991-01-01

    High-energy ion implantation is used as a key processing step in the formation of a complementary bipolar process with both transistor types being vertical. Both n-p-n and p -n-p transistors are made vertically with a deep implanted collector region. Combinations of epitaxial and buried layers are

  18. Controlled ion-beam transformation of silicon bipolar microwave power transistor's characteristics

    International Nuclear Information System (INIS)

    Solodukha, V.A.; Snitovskij, Yu.P.

    2015-01-01

    In this article, a method for changing the silicon bipolar microwave power transistor's characteristics in a direct and deliberate manner by modifying the chemical composition at the molybdenum - silicon boundary, the electro-physical properties of molybdenum - silicon contacts, and the electrophysical characteristics of transistor structure areas by the phosphorus ions irradiation of generated ohmic molybdenum - silicon contacts to the transistor emitters is proposed for the first time. The possibilities of this method are investigated and confirmed experimentally. (authors)

  19. Graphene-graphene oxide floating gate transistor memory.

    Science.gov (United States)

    Jang, Sukjae; Hwang, Euyheon; Lee, Jung Heon; Park, Ho Seok; Cho, Jeong Ho

    2015-01-21

    A novel transparent, flexible, graphene channel floating-gate transistor memory (FGTM) device is fabricated using a graphene oxide (GO) charge trapping layer on a plastic substrate. The GO layer, which bears ammonium groups (NH3+), is prepared at the interface between the crosslinked PVP (cPVP) tunneling dielectric and the Al2 O3 blocking dielectric layers. Important design rules are proposed for a high-performance graphene memory device: (i) precise doping of the graphene channel, and (ii) chemical functionalization of the GO charge trapping layer. How to control memory characteristics by graphene doping is systematically explained, and the optimal conditions for the best performance of the memory devices are found. Note that precise control over the doping of the graphene channel maximizes the conductance difference at a zero gate voltage, which reduces the device power consumption. The proposed optimization via graphene doping can be applied to any graphene channel transistor-type memory device. Additionally, the positively charged GO (GO-NH3+) interacts electrostatically with hydroxyl groups of both UV-treated Al2 O3 and PVP layers, which enhances the interfacial adhesion, and thus the mechanical stability of the device during bending. The resulting graphene-graphene oxide FGTMs exhibit excellent memory characteristics, including a large memory window (11.7 V), fast switching speed (1 μs), cyclic endurance (200 cycles), stable retention (10(5) s), and good mechanical stability (1000 cycles). © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  20. All-optical transistor- and diode-action and logic gates based on anisotropic nonlinear responsive liquid crystal

    Science.gov (United States)

    Wang, Cheng-Yu; Chen, Chun-Wei; Jau, Hung-Chang; Li, Cheng-Chang; Cheng, Chiao-Yu; Wang, Chun-Ta; Leng, Shi-Ee; Khoo, Iam-Choon; Lin, Tsung-Hsien

    2016-01-01

    In this paper, we show that anisotropic photosensitive nematic liquid crystals (PNLC) made by incorporating anisotropic absorbing dyes are promising candidates for constructing all-optical elements by virtue of the extraordinarily large optical nonlinearity of the nematic host. In particular, we have demonstrated several room-temperature ‘prototype’ PNLC-based all-optical devices such as optical diode, optical transistor and all primary logic gate operations (OR, AND, NOT) based on such optical transistor. Owing to the anisotropic absorption property and the optical activity of the twist alignment nematic cell, spatially non-reciprocal transmission response can be obtained within a sizeable optical isolation region of ~210 mW. Exploiting the same mechanisms, a tri-terminal configuration as an all-optical analogue of a bipolar junction transistor is fabricated. Its ability to be switched by an optical field enables us to realize an all-optical transistor and demonstrate cascadability, signal fan-out, logic restoration, and various logical gate operations such as OR, AND and NOT. Due to the possibility of synthesizing anisotropic dyes and wide ranging choice of liquid crystals nonlinear optical mechanisms, these all-optical operations can be optimized to have much lower thresholds and faster response speeds. The demonstrated capabilities of these devices have shown great potential in all-optical control system and photonic integrated circuits. PMID:27491391

  1. All-optical transistor- and diode-action and logic gates based on anisotropic nonlinear responsive liquid crystal.

    Science.gov (United States)

    Wang, Cheng-Yu; Chen, Chun-Wei; Jau, Hung-Chang; Li, Cheng-Chang; Cheng, Chiao-Yu; Wang, Chun-Ta; Leng, Shi-Ee; Khoo, Iam-Choon; Lin, Tsung-Hsien

    2016-08-05

    In this paper, we show that anisotropic photosensitive nematic liquid crystals (PNLC) made by incorporating anisotropic absorbing dyes are promising candidates for constructing all-optical elements by virtue of the extraordinarily large optical nonlinearity of the nematic host. In particular, we have demonstrated several room-temperature 'prototype' PNLC-based all-optical devices such as optical diode, optical transistor and all primary logic gate operations (OR, AND, NOT) based on such optical transistor. Owing to the anisotropic absorption property and the optical activity of the twist alignment nematic cell, spatially non-reciprocal transmission response can be obtained within a sizeable optical isolation region of ~210 mW. Exploiting the same mechanisms, a tri-terminal configuration as an all-optical analogue of a bipolar junction transistor is fabricated. Its ability to be switched by an optical field enables us to realize an all-optical transistor and demonstrate cascadability, signal fan-out, logic restoration, and various logical gate operations such as OR, AND and NOT. Due to the possibility of synthesizing anisotropic dyes and wide ranging choice of liquid crystals nonlinear optical mechanisms, these all-optical operations can be optimized to have much lower thresholds and faster response speeds. The demonstrated capabilities of these devices have shown great potential in all-optical control system and photonic integrated circuits.

  2. Radiation induced deep level defects in bipolar junction transistors under various bias conditions

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Chaoming; Yang, Jianqun [School of Materials Science and Engineering, Harbin Institute of Technology, Harbin 150001 (China); Li, Xingji, E-mail: lxj0218@hit.edu.cn [School of Materials Science and Engineering, Harbin Institute of Technology, Harbin 150001 (China); Ma, Guoliang [School of Materials Science and Engineering, Harbin Institute of Technology, Harbin 150001 (China); Xiao, Liyi [Department of Astronautics, Harbin Institute of Technology, Harbin 150001 (China); Bollmann, Joachim [Institute of Electronics and Sensor Materials, TU Bergakademie Freiberg, 71691 (Germany)

    2015-12-15

    Bipolar junction transistor (BJT) is sensitive to ionization and displacement radiation effects in space. In this paper, 35 MeV Si ions were used as irradiation source to research the radiation damage on NPN and PNP bipolar transistors. The changing of electrical parameters of transistors was in situ measured with increasing irradiation fluence of 35 MeV Si ions. Using deep level transient spectroscopy (DLTS), defects in the bipolar junction transistors under various bias conditions are measured after irradiation. Based on the in situ electrical measurement and DLTS spectra, it is clearly that the bias conditions can affect the concentration of deep level defects, and the radiation damage induced by heavy ions.

  3. Radiation induced deep level defects in bipolar junction transistors under various bias conditions

    Science.gov (United States)

    Liu, Chaoming; Yang, Jianqun; Li, Xingji; Ma, Guoliang; Xiao, Liyi; Bollmann, Joachim

    2015-12-01

    Bipolar junction transistor (BJT) is sensitive to ionization and displacement radiation effects in space. In this paper, 35 MeV Si ions were used as irradiation source to research the radiation damage on NPN and PNP bipolar transistors. The changing of electrical parameters of transistors was in situ measured with increasing irradiation fluence of 35 MeV Si ions. Using deep level transient spectroscopy (DLTS), defects in the bipolar junction transistors under various bias conditions are measured after irradiation. Based on the in situ electrical measurement and DLTS spectra, it is clearly that the bias conditions can affect the concentration of deep level defects, and the radiation damage induced by heavy ions.

  4. Organic transistors making use of room temperature ionic liquids as gating medium

    Science.gov (United States)

    Hoyos, Jonathan Javier Sayago

    The ability to couple ionic and electronic transport in organic transistors, based on pi conjugated organic materials for the transistor channel, can be particularly interesting to achieve low voltage transistor operation, i.e. below 1 V. The operation voltage in typical organic transistors based on conventional dielectrics (200 nm thick SiO2) is commonly higher than 10 V. Electrolyte-gated (EG) transistors, i.e. employing an electrolyte as the gating medium, permit current modulations of several orders of magnitude at relatively low gate voltages thanks to the exceptionally high capacitance at the electrolyte/transistor channel interface, in turn due to the low thickness (ca. 3 nm) of the electrical double layers forming at the electrolyte/semiconductor interface. Electrolytes based on room temperature ionic liquids (RTILs) are promising in EG transistor applications for their high electrochemical stability and good ionic conductivity. The main motivation behind this work is to achieve low voltage operation in organic transistors by making use of RTILs as gating medium. First we demonstrate the importance of the gate electrode material in the EG transistor performance. The use of high surface area carbon gate electrodes limits undesirable electrochemical processes and renders unnecessary the presence of a reference electrode to monitor the channel potential. This was demonstrated using activated carbon as gate electrode, the electronic conducting polymer MEH-PPV, poly[2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylene vinylene] channel material, and the ionic liquid [EMIM][TFSI] (1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide), as gating medium. Using high surface area gate electrodes resulted in sub-1 V operation and charge carrier mobilities of (1.0 +/- 0.5) x 10-2 cm2V -1s-1. A challenge in the field of EG transistors is to decrease their response time, a consequence of the slow ion redistribution in the transistor channel upon application of electric

  5. Comparison between Field Effect Transistors and Bipolar Junction Transistors as Transducers in Electrochemical Sensors

    Science.gov (United States)

    Zafar, Sufi; Lu, Minhua; Jagtiani, Ashish

    2017-01-01

    Field effect transistors (FET) have been widely used as transducers in electrochemical sensors for over 40 years. In this report, a FET transducer is compared with the recently proposed bipolar junction transistor (BJT) transducer. Measurements are performed on two chloride electrochemical sensors that are identical in all details except for the transducer device type. Comparative measurements show that the transducer choice significantly impacts the electrochemical sensor characteristics. Signal to noise ratio is 20 to 2 times greater for the BJT sensor. Sensitivity is also enhanced: BJT sensing signal changes by 10 times per pCl, whereas the FET signal changes by 8 or less times. Also, sensor calibration curves are impacted by the transducer choice. Unlike a FET sensor, the calibration curve of the BJT sensor is independent of applied voltages. Hence, a BJT sensor can make quantitative sensing measurements with minimal calibration requirements, an important characteristic for mobile sensing applications. As a demonstration for mobile applications, these BJT sensors are further investigated by measuring chloride levels in artificial human sweat for potential cystic fibrosis diagnostic use. In summary, the BJT device is demonstrated to be a superior transducer in comparison to a FET in an electrochemical sensor.

  6. Wide bandgap collector III-V double heterojunction bipolar transistors

    International Nuclear Information System (INIS)

    Flitcroft, R.M.

    2000-10-01

    This thesis is devoted to the study and development of Heterojunction Bipolar Transistors (HBTs) designed for high voltage operation. The work concentrates on the use of wide bandgap III-V semiconductor materials as the collector material and their associated properties influencing breakdown, such as impact ionisation coefficients. The work deals with issues related to incorporating a wide bandgap collector into double heterojunction structures such as conduction band discontinuities at the base-collector junction and results are presented which detail, a number of methods designed to eliminate the effects of such discontinuities. In particular the use of AlGaAs as the base material has been successful in eliminating the conduction band spike at this interface. A method of electrically injecting electrons into the collector has been employed to investigate impact ionisation in GaAs, GaInP and AlInP which has used the intrinsic gain of the devices to extract impact ionisation coefficients over a range of electric fields beyond the scope of conventional optical injection techniques. This data has enabled the study of ''dead space'' effects in HBT collectors and have been used to develop an analytical model of impact ionisation which has been incorporated into an existing Ebers-Moll HBT simulator. This simulator has been shown to accurately reproduce current-voltage characteristics in both the devices used in this work and for external clients. (author)

  7. Coulomb blockade in a Si channel gated by an Al single-electron transistor

    OpenAIRE

    Sun, L.; Brown, K. R.; Kane, B. E.

    2007-01-01

    We incorporate an Al-AlO_x-Al single-electron transistor as the gate of a narrow (~100 nm) metal-oxide-semiconductor field-effect transistor (MOSFET). Near the MOSFET channel conductance threshold, we observe oscillations in the conductance associated with Coulomb blockade in the channel, revealing the formation of a Si single-electron transistor. Abrupt steps present in sweeps of the Al transistor conductance versus gate voltage are correlated with single-electron charging events in the Si t...

  8. Development of solution-gated graphene transistor model for biosensors

    Science.gov (United States)

    Karimi, Hediyeh; Yusof, Rubiyah; Rahmani, Rasoul; Hosseinpour, Hoda; Ahmadi, Mohammad T.

    2014-02-01

    The distinctive properties of graphene, characterized by its high carrier mobility and biocompatibility, have stimulated extreme scientific interest as a promising nanomaterial for future nanoelectronic applications. In particular, graphene-based transistors have been developed rapidly and are considered as an option for DNA sensing applications. Recent findings in the field of DNA biosensors have led to a renewed interest in the identification of genetic risk factors associated with complex human diseases for diagnosis of cancers or hereditary diseases. In this paper, an analytical model of graphene-based solution gated field effect transistors (SGFET) is proposed to constitute an important step towards development of DNA biosensors with high sensitivity and selectivity. Inspired by this fact, a novel strategy for a DNA sensor model with capability of single-nucleotide polymorphism detection is proposed and extensively explained. First of all, graphene-based DNA sensor model is optimized using particle swarm optimization algorithm. Based on the sensing mechanism of DNA sensors, detective parameters ( I ds and V gmin) are suggested to facilitate the decision making process. Finally, the behaviour of graphene-based SGFET is predicted in the presence of single-nucleotide polymorphism with an accuracy of more than 98% which guarantees the reliability of the optimized model for any application of the graphene-based DNA sensor. It is expected to achieve the rapid, quick and economical detection of DNA hybridization which could speed up the realization of the next generation of the homecare sensor system.

  9. Electrical characterization of commercial NPN bipolar junction transistors under neutron and gamma irradiation

    Directory of Open Access Journals (Sweden)

    OO Myo Min

    2014-01-01

    Full Text Available Electronics components such as bipolar junction transistors, diodes, etc. which are used in deep space mission are required to be tolerant to extensive exposure to energetic neutrons and ionizing radiation. This paper examines neutron radiation with pneumatic transfer system of TRIGA Mark-II reactor at the Malaysian Nuclear Agency. The effects of the gamma radiation from Co-60 on silicon NPN bipolar junction transistors is also be examined. Analyses on irradiated transistors were performed in terms of the electrical characteristics such as current gain, collector current and base current. Experimental results showed that the current gain on the devices degraded significantly after neutron and gamma radiations. Neutron radiation can cause displacement damage in the bulk layer of the transistor structure and gamma radiation can induce ionizing damage in the oxide layer of emitter-base depletion layer. The current gain degradation is believed to be governed by the increasing recombination current in the base-emitter depletion region.

  10. Tuning the threshold voltage in electrolyte-gated organic field-effect transistors

    Science.gov (United States)

    Kergoat, Loïg; Herlogsson, Lars; Piro, Benoit; Pham, Minh Chau; Horowitz, Gilles; Crispin, Xavier; Berggren, Magnus

    2012-01-01

    Low-voltage organic field-effect transistors (OFETs) promise for low power consumption logic circuits. To enhance the efficiency of the logic circuits, the control of the threshold voltage of the transistors are based on is crucial. We report the systematic control of the threshold voltage of electrolyte-gated OFETs by using various gate metals. The influence of the work function of the metal is investigated in metal-electrolyte-organic semiconductor diodes and electrolyte-gated OFETs. A good correlation is found between the flat-band potential and the threshold voltage. The possibility to tune the threshold voltage over half the potential range applied and to obtain depletion-like (positive threshold voltage) and enhancement (negative threshold voltage) transistors is of great interest when integrating these transistors in logic circuits. The combination of a depletion-like and enhancement transistor leads to a clear improvement of the noise margins in depleted-load unipolar inverters. PMID:22586088

  11. Organic Field Effect Transistors with Dipole-Polarized Polymer Gate Dielectrics for Control of Threshold Voltage

    OpenAIRE

    Sakai, Heisuke; Takahashi, Yoshikazu; Murata, Hideyuki

    2007-01-01

    The authors demonstrate organic field effect transistors (OFETs) with a dipole-polarized polyurea for the gate dielectrics. In the dielectrics, the internal electric field induces the mobile charge carrier in the semiconductor layer to the semiconductor-dielectric interface. OFETs with dipole-polarized gate dielectrics exhibit lower threshold voltage. With nonpolarized gate dielectrics, the threshold voltage was -11.4 V, whereas that decreased to -5.3 V with polarized gate dielectrics. In a...

  12. Validation of Nonlinear Bipolar Transistor Model by Small-Signal Measurements

    DEFF Research Database (Denmark)

    Vidkjær, Jens; Porra, V.; Zhu, J.

    1992-01-01

    A new method for the validity analysis of nonlinear transistor models is presented based on DC-and small-signal S-parameter measurements and realistic consideration of the measurement and de-embedding errors and singularities of the small-signal equivalent circuit. As an example, some analysis...... results for an extended Gummel Poon model are presented in the case of a UHF bipolar power transistor....

  13. Investigation of the Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field Effect Transistor

    OpenAIRE

    Saurabh, Sneh; Kumar, M. Jagadesh

    2011-01-01

    In this paper, we propose the application of a Dual Material Gate (DMG) in a Tunnel Field Effect Transistor (TFET) to simultaneously optimize the on-current, the off-current and the threshold voltage, and also improve the average subthreshold slope, the nature of the output characteristics and the immunity against the DIBL effects. We demonstrate that if appropriate work-functions are chosen for the gate materials on the source side and the drain side, the tunnel field effect transistor shows...

  14. Highly stable carbon nanotube top-gate transistors with tunable threshold voltage

    NARCIS (Netherlands)

    Wang, H.; Cobb, B.; Breemen, A. van; Gelinck, G.H.; Bao, Z.

    2014-01-01

    Carbon-nanotube top-gate transistors with fluorinated dielectrics are presented. With PTrFE as the dielectric, the devices have absent or small hysteresis at different sweep rates and excellent bias-stress stability under ambient conditions. Ambipolar single-walled carbon nanotube (SWNT) transistors

  15. Heat removal from bipolar transistor by loop heat pipe with nickel and copper porous structures.

    Science.gov (United States)

    Nemec, Patrik; Smitka, Martin; Malcho, Milan

    2014-01-01

    Loop heat pipes (LHPs) are used in many branches of industry, mainly for cooling of electrical elements and systems. The loop heat pipe is a vapour-liquid phase-change device that transfers heat from evaporator to condenser. One of the most important parts of the LHP is the porous wick structure. The wick structure provides capillary force to circulate the working fluid. To achieve good thermal performance of LHP, capillary wicks with high permeability and porosity and fine pore radius are expected. The aim of this work was to develop porous structures from copper and nickel powder with different grain sizes. For experiment copper powder with grain size of 50 and 100 μm and nickel powder with grain size of 10 and 25 μm were used. Analysis of these porous structures and LHP design are described in the paper. And the measurements' influences of porous structures in LHP on heat removal from the insulated gate bipolar transistor (IGBT) have been made.

  16. Heat Removal from Bipolar Transistor by Loop Heat Pipe with Nickel and Copper Porous Structures

    Directory of Open Access Journals (Sweden)

    Patrik Nemec

    2014-01-01

    Full Text Available Loop heat pipes (LHPs are used in many branches of industry, mainly for cooling of electrical elements and systems. The loop heat pipe is a vapour-liquid phase-change device that transfers heat from evaporator to condenser. One of the most important parts of the LHP is the porous wick structure. The wick structure provides capillary force to circulate the working fluid. To achieve good thermal performance of LHP, capillary wicks with high permeability and porosity and fine pore radius are expected. The aim of this work was to develop porous structures from copper and nickel powder with different grain sizes. For experiment copper powder with grain size of 50 and 100 μm and nickel powder with grain size of 10 and 25 μm were used. Analysis of these porous structures and LHP design are described in the paper. And the measurements’ influences of porous structures in LHP on heat removal from the insulated gate bipolar transistor (IGBT have been made.

  17. CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES: Thermal analytic model of current gain for bipolar junction transistor-bipolar static induction transistor compound device

    Science.gov (United States)

    Zhang, You-Run; Zhang, Bo; Li, Ze-Hong; Lai, Chang-Jin; Li, Zhao-Ji

    2009-02-01

    This paper proposes a thermal analytical model of current gain for bipolar junction transistor-bipolar static induction transistor (BJT-BSIT) compound device in the low current operation. It also proposes a best thermal compensating factor to the compound device that indicates the relationship between the thermal variation rate of current gain and device structure. This is important for the design of compound device to be optimized. Finally, the analytical model is found to be in good agreement with numerical simulation and experimental results. The test results demonstrate that thermal variation rate of current gain is below 10% in 25 °C-85°C and 20% in -55°C-25°C.

  18. Enhancement of minority carrier injection in ambipolar carbon nanotube transistors using double-gate structures

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Bongjun; Liang, Kelly; Dodabalapur, Ananth, E-mail: ananth.dodabalapur@engr.utexas.edu [Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States); Geier, Michael L.; Hersam, Mark C. [Department of Materials Science and Engineering and Department of Chemistry, Northwestern University, Evanston, Illinois 60208 (United States)

    2016-07-11

    We show that double-gate ambipolar thin-film transistors can be operated to enhance minority carrier injection. The two gate potentials need to be significantly different for enhanced injection to be observed. This enhancement is highly beneficial in devices such as light-emitting transistors where balanced electron and hole injections lead to optimal performance. With ambipolar single-walled carbon nanotube semiconductors, we demonstrate that higher ambipolar currents are attained at lower source-drain voltages, which is desired for portable electronic applications, by employing double-gate structures. In addition, when the two gates are held at the same potential, the expected advantages of the double-gate transistors such as enhanced on-current are also observed.

  19. Liquid–Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing

    KAUST Repository

    Zhang, Yu

    2017-10-17

    Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid–liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the “sensing channel” can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

  20. Silicon on insulator bipolar junction transistors for flexible microwave applications

    Science.gov (United States)

    Bavier, John McGoldrick

    Microwave frequency flexible electronic devices require a high quality semiconducting material and a set of fabrication techniques that are compatible with device integration onto flexible polymer substrates. Over the past ten years, monocrystalline silicon nanomembranes (SiNMs) have been studied as a flexible semiconducting material that is compatible with industrial Si processing. Fabricated from commercial silicon on insulator (SOI) wafers, SiNMs can be transferred to flexible substrates using a variety of techniques. Due to their high carrier mobilities, SiNMs are a promising candidate for flexible microwave frequency devices. This dissertation presents fabrication techniques for flexible SiNM devices in general, as well as the progress made towards the development of a microwave frequency SiNM bipolar junction transistor (BJT). In order to overcome previous limitations associated with adhesion, novel methods for transfer printing of metal films and SiNMs are presented. These techniques enable transfer printing of a range of metal films and improve the alignment of small transfer printed SiNM devices. Work towards the development of a microwave frequency BJT on SOI for SiNM devices is also described. Utilizing a self-aligned polysilicon sidewall spacer technique, a BJT with an ultra-narrow base region is fabricated and tested. Two regimes of operation are identified and characterized under DC conditions. At low base currents, devices exhibited forward current gain as high as betaF = 900. At higher base current values, a transconductance of 59 mS was observed. Microwave scattering parameters were obtained for the BJTs under both biasing conditions and compared to unbiased measurements. Microwave frequency gain was not observed. Instead, bias-dependent non-reciprocal behavior was observed and examined. Limitations associated with the microwave impedance-matched electrode configuration are presented. High current densities in the narrow electrodes cause localized

  1. 4H-SiC Power Bipolar Junction Transistor with a Very Low Specific On-resistance of 2.9 mOmega.cm2

    Science.gov (United States)

    2006-04-12

    specific on-resistance (Rsp,on) of power 4H-SiC bipolar junction transistors ( BJT ). A 4H-SiC BJT based on a 12 um drift-layer shows a record low...reported for high power 4H-SiC BJTs . Index Terms—Silicon carbide, bipolar junction transistors ( BJTs ), power transistors ...bipolar junction transistor ( BJT ) is an important switching device for high power and high temperature applications, which is an intrinsically

  2. Bipolar transistor with lateral emitter and collector and method of production

    NARCIS (Netherlands)

    Hueting, Raymond Josephus Engelbart; van den Oever, Leon C.M.

    2016-01-01

    A bipolar transistor includes a substrate of semiconductor material, a high-mobility layer in the substrate, and a donor layer adjacent to the high-mobility layer. An emitter terminal forms an emitter contact on the donor layer, and a collector terminal forms a collector contact on the donor layer.

  3. Using Animation to Improve the Students' Academic Achievement on Bipolar Junction Transistor

    Science.gov (United States)

    Zoabi, W.; Sabag, N.; Gero, A.

    2012-01-01

    Teaching abstract subjects to students studying towards a degree in electronics practical engineering (a degree between a technician and an engineer) requires didactic tools that enable understanding of issues without using advanced mathematics and physics. One basic issue is the BJT (Bipolar Junction Transistor) that requires preliminary…

  4. Modeling of the collector epilayer of a bipolar transistor in the MEXTRAM model

    NARCIS (Netherlands)

    de Graaff, H.C.; de Graaff, H.C.; Kloosterman, W.J.

    1995-01-01

    A new model description for the behaviour of epitaxial collectors in bipolar transistors is given. This is part of MEXTRAM, a compact model for circuit simulation, and it gives the voltage drop and stored minority carrier charge in the collector epilayer as a function of the bias conditions. It

  5. Low Noise Bias Current/Voltage References Based on Floating-Gate MOS Transistors

    DEFF Research Database (Denmark)

    Igor, Mucha

    1997-01-01

    The exploitation of floating-gate MOS transistors as reference current and voltage sources is investigated. Test structures of common source and common drain floating-gate devices have been implemented in a commercially available 0.8 micron double-poly CMOS process. The measurements performed...

  6. Characteristics of dual-gate thin-film transistors for applications in digital radiology

    International Nuclear Information System (INIS)

    Waechter, D.; Huang, Z.; Zhao, W.; Blevis, I.; Rowlands, J.A.

    1996-01-01

    A large-area flat-panel detector for digital radiology is being developed. The detector uses an array of dual-gate thin-film transistors (TFTs) to read out X-ray-generated charge produced in an amorphous selenium (a-Se) layer. The TFTs use CdSe as the semiconductor and use the bottom gate for row selection. The top gate can be divided into a 'deliberate' gate, covering most of the channel length, and small 'parasitic' gates that consist of: overlap of source or drain metal over the top-gate oxide; and gap regions in the metal that are covered only by the a-Se. In this paper we present the properties of dual-gate TFTs and examine the effect of both the deliberate and parasitic gates on the detector operation. Various options for controlling the top-gate potential are analyzed and discussed. (author)

  7. Organic field-effect transistor nonvolatile memories utilizing sputtered C nanoparticles as nano-floating-gate

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Jie; Liu, Chang-Hai; She, Xiao-Jian; Sun, Qi-Jun; Gao, Xu; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn [Institute of Functional Nano and Soft Materials (FUNSOM), Soochow University, Suzhou, Jiangsu 215123 (China)

    2014-10-20

    High-performance organic field-effect transistor nonvolatile memories have been achieved using sputtered C nanoparticles as the nano-floating-gate. The sputtered C nano-floating-gate is prepared with low-cost material and simple process, forming uniform and discrete charge trapping sites covered by a smooth and complete polystyrene layer. The devices show large memory window, excellent retention capability, and programming/reading/erasing/reading endurance. The sputtered C nano-floating-gate can effectively trap both holes and electrons, and it is demonstrated to be suitable for not only p-type but also n-type organic field-effect transistor nonvolatile memories.

  8. Organic field-effect transistor nonvolatile memories utilizing sputtered C nanoparticles as nano-floating-gate

    International Nuclear Information System (INIS)

    Liu, Jie; Liu, Chang-Hai; She, Xiao-Jian; Sun, Qi-Jun; Gao, Xu; Wang, Sui-Dong

    2014-01-01

    High-performance organic field-effect transistor nonvolatile memories have been achieved using sputtered C nanoparticles as the nano-floating-gate. The sputtered C nano-floating-gate is prepared with low-cost material and simple process, forming uniform and discrete charge trapping sites covered by a smooth and complete polystyrene layer. The devices show large memory window, excellent retention capability, and programming/reading/erasing/reading endurance. The sputtered C nano-floating-gate can effectively trap both holes and electrons, and it is demonstrated to be suitable for not only p-type but also n-type organic field-effect transistor nonvolatile memories.

  9. Lateral PNP bipolar transistor with aiding field diffusions

    Science.gov (United States)

    Gallagher, R. C.; Mc Cann, D. H.

    1969-01-01

    Fabrication technique produces field aided lateral PNP transistors compatible with micropower switching circuits. The sub-collector diffusion is performed with phosphorus as the dopant and the epitaxy is grown using the higher temperature silicon tetrachloride process.

  10. Transferred substrate heterojunction bipolar transistors for submillimeter wave applications

    Science.gov (United States)

    Fung, A.; Samoska, L.; Siegel, P.; Rodwell, M.; Urteaga, M.; Paidi, V.

    2003-01-01

    We present ongoing work towards the development of submillimeter wave transistors with goals of realizing advanced high frequency amplifiers, voltage controlled oscillators, active multipliers, and traditional high-speed digital circuits.

  11. Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

    Science.gov (United States)

    Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

    2009-01-01

    Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

  12. Soft switch-avalanche IGBT convertor. [Insulated Gate Bipolar Transistor

    Science.gov (United States)

    Chen, K.; Stuart, T. A.

    1990-01-01

    A full bridge dc-dc converter using a zero voltage and zero current switching technique is described. This circuit utilizes the characteristics of the IGBT to achieve power and frequency combinations that are much higher than those previously reported for this device. Experimental results are included for a 1.5 kW, 100 kHz converter with 94 percent efficiency.

  13. Development of insulated gate bipolar transistor-based power ...

    Indian Academy of Sciences (India)

    325 V to 550 V with a maximum current rating of 20 A. The storage capacitor is realized using two capacitor banks C01 and C02. These capacitor banks are reso- nantly charged through the charging inductor Lc, blocking diode Db and primary of the pulse transformer by the DC source to approximately twice its value. Pulse.

  14. Low-frequency noise behavior of polysilicon emitter bipolar junction transistors: a review

    Science.gov (United States)

    Deen, M. Jamal; Pascal, Fabien

    2003-05-01

    For many analog integrated circuit applications, the polysilicon emitter bipolar junction transistor (PE-BJT) is still the preferred choice because of its higher operational frequency and lower noise performance characteristics compared to MOS transistors of similar active areas and at similar biasing currents. In this paper, we begin by motivating the reader with reasons why bipolar transistors are still of great interest for analog integrated circuits. This motivation includes a comparison between BJT and the MOSFET using a simple small-signal equivalent circuit to derive important parameters that can be used to compare these two technologies. An extensive review of the popular theories used to explain low frequency noise results is presented. However, in almost all instances, these theories have not been fully tested. The effects of different processing technologies and conditions on the noise performance of PE-BJTs is reviewed and a summary of some of the key technological steps and device parameters and their effects on noise is discussed. The effects of temperature and emitter geometries scaling is reviewed. It is shown that dispersion of the low frequency noise in ultra-small geometries is a serious issue since the rate of increase of the noise dispersion is faster than the noise itself as the emitter geometry is scaled to smaller values. Finally, some ideas for future research on PE-BJTs, some of which are also applicable to SiGe heteorjunction bipolar transistors and MOSFETs, are presented after the conclusions.

  15. DEVELOPMENT OF CONTROLLED RECTIFIERS BASED ON THE BIPOLAR WITH STATIC INDUCTION TRANSISTORS (BSIT

    Directory of Open Access Journals (Sweden)

    F. I. Bukashev

    2016-01-01

    Full Text Available Aim. The aim of this study is to develop one of the most perspective semiconductor device suitable for creation and improvement of controlled rectifiers, bipolar static induction transistor.Methods. Considered are the structural and schematic circuit controlled rectifier based on bipolar static induction transistor (BSIT, and the criterion of effectiveness controlled rectifiers - equivalent to the voltage drop.Results. Presented are the study results of controlled rectifier layout on BSIT KT698I. It sets the layout operation at an input voltage of 2.0 V at a frequency up to 750 kHz. The efficiency of the studied layouts at moderate current densities as high as 90 % .Offered is optimization of technological route microelectronic controlled rectifier manufacturing including BSIT and integrated bipolar elements of the scheme management.Conclusion. It is proved that the most efficient use of the bipolar static induction transistor occurs at the low voltage controlled rectifiers 350-400 kHz, at frequencies in conjunction with a low-voltage control circuit.It is proved that the increase of the functional characteristics of the converters is connected to the expansion of the input voltage and output current ranges

  16. Development of Gate and Base Drive Using SiC Junction Field Effect Transistors

    Science.gov (United States)

    2008-05-01

    Agarwal, Anant; Richmond, James ; Chow, T. Paul; Geil, Bruce; Jones, Ken A.; Scozzie, Charles. 4 kV, 10 A Bipolar Junction Transistors in 4H-SiC. Proc...PROVING GROUND MD 21005-5001 1 US ARMY TRADOC BATTLE LAB INTEGRATION & TECHL DIRCTRT ATTN ATCD B 10 WHISTLER LANE FT MONROE

  17. Switching Characteristics of a 4H-SiC Based Bipolar Junction Transistor to 200 C

    Science.gov (United States)

    Niedra, Janis M.

    2006-01-01

    Static curves and resistive load switching characteristics of a 600 V, 4 A rated, SiC-based NPN bipolar power transistor (BJT) were observed at selected temperatures from room to 200 C. All testing was done in a pulse mode at low duty cycle (approx.0.1 percent). Turn-on was driven by an adjustable base current pulse and turn-off was accelerated by a negative base voltage pulse of 7 V. These base drive signals were implemented by 850 V, gated power pulsers, having rise-times of roughly 10 ns, or less. Base charge sweep-out with a 7 V negative pulse did not produce the large reverse base current pulse seen in a comparably rated Si-based BJT. This may be due to a very low charge storage time. The decay of the collector current was more linear than its exponential-like rise. Switching observations were done at base drive currents (I(sub B)) up to 400 mA and collector currents (I(sub C)) up to 4 A, using a 100 Omega non-inductive load. At I(sub B) = 400 mA and I(sub C) = 4 A, turn-on times typically varied from 80 to 94 ns, over temperatures from 23 to 200 C. As expected, lowering the base drive greatly extended the turn-on time. Similarly, decreasing the load current to I(sub C) = 1 A with I(sub B) = 400 mA produced turn-on times as short as 34 ns. Over the 23 to 200 C range, with I(sub B) = 400 mA and I(sub C) = 4 A, turn-off times were in the range of 72 to 84 ns with the 7 V sweep-out.

  18. The free electron gas primary thermometer using an ordinary bipolar junction transistor approaches ppm accuracy

    Science.gov (United States)

    Mimila-Arroyo, J.

    2017-06-01

    In this paper, it is demonstrated that the free electron gas primary thermometer based on a bipolar junction transistor is able to provide the temperature with an accuracy of a few parts per million. Its simple functioning principle exploits the behavior of the collector current when properly biased to extract the temperature. Using general purpose silicon transistors at the water triple point (273.16 K) and gallium melting point (302.9146), an accuracy of a few parts per million has been reached, constituting the simplest and the easiest to operate primary thermometer, that might be considered even for the redefinition of Kelvin.

  19. Development and characterization of vertical double-gate MOS field-effect transistors

    International Nuclear Information System (INIS)

    Trellenkamp, S.

    2004-07-01

    Planar MOS-field-effect transistors are common devices today used by the computer industry. When their miniaturization reaches its limit, alternate transistor concepts become necessary. In this thesis the development of vertical Double-Gate-MOS-field-effect transistors is presented. These types of transistors have a vertically aligned p-n-p junction (or n-p-n junction, respectively). Consequently, the source-drain current flows perpendicular with respect to the surface of the wafer. A Double-Gate-field-effect transistor is characterized by a very thin channel region framed by two parallel gates. Due to the symmetry of the structure and less bulk volume better gate control and hence better short channel behavior is expected, as well as an improved scaling potential. Nanostructuring of the transistor's active region is very challenging. Approximately 300 nm high and down to 30 nm wide silicon ridges are requisite. They can be realized using hydrogen silsesquioxane (HSQ) as inorganic high resolution resist for electron beam lithography. Structures defined in HSQ are then transferred with high anisotropy and selectivity into silicon using ICP-RIE (reactive ion etching with inductive coupled plasma). 25 nm wide and 330 nm high silicon ridges are achieved. Different transistor layouts are realized. The channel length is defined by epitaxial growth of doped silicon layers before or by ion implantation after nanostructuring, respectively. The transistors show source-drain currents up to 380 μA/μm and transconductances up to 480 μS/μm. Improved short channel behavior for decreasing width of the silicon ridges is demonstrated. (orig.)

  20. Organic crystal light-emitting transistors with top-gate configuration

    Science.gov (United States)

    Inokuchi, Tatsuya; Inada, Yuhi; Yamao, Takeshi; Hotta, Shu

    2018-03-01

    We applied the top-gate configuration to organic light-emitting transistors (OLETs) having an organic semiconductor crystal and an aluminum-doped zinc oxide (AZO) layer. The AZO layer was inserted between a quartz substrate and the organic crystal. The devices had the top-contact configuration where gold and an alloy of magnesium and silver were used for the contacts. Silver and Parylene C® were used for a gate contact and a gate insulator for the top-gate configuration, respectively. These OLETs showed more efficient current injection at low voltages than both the devices without a gate contact and the devices having the bottom-gate configuration. The present results indicate that the top-gate configuration is effective for improving the crystal OLET characteristics.

  1. Auditory M50 and M100 sensory gating deficits in bipolar disorder: a MEG study.

    Science.gov (United States)

    Wang, Ying; Feng, Yigang; Jia, Yanbin; Wang, Wensheng; Xie, Yanping; Guan, Yufang; Zhong, Shuming; Zhu, Dan; Huang, Li

    2014-01-01

    Auditory sensory gating deficits have been reported in subjects with bipolar disorder, but the hemispheric and neuronal origins of this deficit are not well understood. Moreover, gating of the auditory evoked components reflecting early attentive stage of information processing has not been investigated in bipolar disorder. The objectives of this study were to investigate the right and left hemispheric auditory sensory gating of the M50 (preattentive processing) and M100 (early attentive processing) in patients diagnosed with bipolar I disorder by utilizing magnetoencephalography (MEG). Whole-head MEG data were acquired during the standard paired-click paradigm in 20 bipolar I disorder patients and 20 healthy controls. The M50 and the M100 responses were investigated, and dipole source localizations were also investigated. Sensory gating were determined by measuring the strength of the M50 and the M100 response to the second click divided by that of the first click (S2/S1). In every subject, M50 and M100 dipolar sources localized to the left and right posterior portion of superior temporal gyrus (STG). Bipolar I disorder patients showed bilateral gating deficits in M50 and M100. The bilateral M50 S2 source strengths were significantly higher in the bipolar I disorder group compared to the control group. The sample size was relatively small. More studies with larger sample sizes are warranted. Bipolar subjects were taking a wide range of medications that could not be readily controlled for. These findings suggest that bipolar I disorder patients have auditory gating deficits at both pre-attentive and early attentive levels, which might be related to STG structural abnormality. © 2013 The Authors. Published by Elsevier B.V. All rights reserved.

  2. A semi-floating gate transistor for low-voltage ultrafast memory and sensing operation.

    Science.gov (United States)

    Wang, Peng-Fei; Lin, Xi; Liu, Lei; Sun, Qing-Qing; Zhou, Peng; Liu, Xiao-Yong; Liu, Wei; Gong, Yi; Zhang, David Wei

    2013-08-09

    As the semiconductor devices of integrated circuits approach the physical limitations of scaling, alternative transistor and memory designs are needed to achieve improvements in speed, density, and power consumption. We report on a transistor that uses an embedded tunneling field-effect transistor for charging and discharging the semi-floating gate. This transistor operates at low voltages (≤2.0 volts), with a large threshold voltage window of 3.1 volts, and can achieve ultra-high-speed writing operations (on time scales of ~1 nanosecond). A linear dependence of drain current on light intensity was observed when the transistor was exposed to light, so possible applications include image sensing with high density and performance.

  3. Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

    International Nuclear Information System (INIS)

    Wan, Chang Jin; Wan, Qing; Zhu, Li Qiang; Wan, Xiang; Shi, Yi

    2016-01-01

    The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors

  4. Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

    Energy Technology Data Exchange (ETDEWEB)

    Wan, Chang Jin; Wan, Qing, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn [School of Electronic Science & Engineering, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China); Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Zhu, Li Qiang [Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Wan, Xiang; Shi, Yi, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn [School of Electronic Science & Engineering, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)

    2016-01-25

    The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors.

  5. Unified planar process for fabricating heterojunction bipolar transistors and buried-heterostructure lasers utilizing impurity-induced disordering

    Energy Technology Data Exchange (ETDEWEB)

    Thornton, R.L.; Mosby, W.J.; Chung, H.F.

    1988-12-26

    We describe results on a novel geometry of heterojunction bipolar transistor that has been realized by impurity-induced disordering. This structure is fabricated by a method that is compatible with techniques for the fabrication of low threshold current buried-heterostructure lasers. We have demonstrated this compatibility by fabricating a hybrid laser/transistor structure that operates as a laser with a threshold current of 6 mA at room temperature, and as a transistor with a current gain of 5.

  6. The Role of the Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) in Mobile Technology Platforms

    Science.gov (United States)

    2011-09-01

    1. Comparison of transistor cutoff frequency for a Si BJT and SiGe HBT over time (1...the characteristics of a SiGe HBT, and compares how SiGe fares in the worlds of the GaAs HBT and the Si bipolar junction transistors ( BJT ). 2...supremacy of the Si BJT or field effect transistor (FET) in most applications. These properties include (1) growth of comparably large Si wafers with

  7. One bipolar transistor selector - One resistive random access memory device for cross bar memory array

    Directory of Open Access Journals (Sweden)

    R. Aluguri

    2017-09-01

    Full Text Available A bipolar transistor selector was connected in series with a resistive switching memory device to study its memory characteristics for its application in cross bar array memory. The metal oxide based p-n-p bipolar transistor selector indicated good selectivity of about 104 with high retention and long endurance showing its usefulness in cross bar RRAM devices. Zener tunneling is found to be the main conduction phenomena for obtaining high selectivity. 1BT-1R device demonstrated good memory characteristics with non-linearity of 2 orders, selectivity of about 2 orders and long retention characteristics of more than 105 sec. One bit-line pull-up scheme shows that a 650 kb cross bar array made with this 1BT1R devices works well with more than 10 % read margin proving its ability in future memory technology application.

  8. One bipolar transistor selector - One resistive random access memory device for cross bar memory array

    Science.gov (United States)

    Aluguri, R.; Kumar, D.; Simanjuntak, F. M.; Tseng, T.-Y.

    2017-09-01

    A bipolar transistor selector was connected in series with a resistive switching memory device to study its memory characteristics for its application in cross bar array memory. The metal oxide based p-n-p bipolar transistor selector indicated good selectivity of about 104 with high retention and long endurance showing its usefulness in cross bar RRAM devices. Zener tunneling is found to be the main conduction phenomena for obtaining high selectivity. 1BT-1R device demonstrated good memory characteristics with non-linearity of 2 orders, selectivity of about 2 orders and long retention characteristics of more than 105 sec. One bit-line pull-up scheme shows that a 650 kb cross bar array made with this 1BT1R devices works well with more than 10 % read margin proving its ability in future memory technology application.

  9. Experimental DC extraction of the thermal resistance of bipolar transistors taking into account the Early effect

    Science.gov (United States)

    d'Alessandro, Vincenzo

    2017-01-01

    This paper presents three methods to experimentally extract the thermal resistance of bipolar transistors taking into account the Early effect. The approaches are improved variants of recently-proposed techniques relying on common-base DC measurements. The accuracy is numerically verified by making use of a compact model calibrated on I-V characteristics of state-of-the-art SOG BJTs and SiGe:C HBTs.

  10. Verification of the Simultaneous Local Extraction Method of Base and Thermal Resistance of Bipolar Transistors

    OpenAIRE

    Robert Setekera; Luuk Tiemeijer; Ramses van der Toorn

    2014-01-01

    In this paper an extensive verification of the extraction method (published earlier) that consistently accounts for self-heating and Early effect to accurately extract both base and thermal resistance of bipolar junction transistors is presented. The method verification is demonstrated on advanced RF SiGe HBTs were the extracted results for the thermal resistance are compared with those from another published method that ignores the effect of Early effect on internal base...

  11. Accurate characterization of organic thin film transistors in the presence of gate leakage current

    Directory of Open Access Journals (Sweden)

    Vinay K. Singh

    2011-12-01

    Full Text Available The presence of gate leakage through polymer dielectric in organic thin film transistors (OTFT prevents accurate estimation of transistor characteristics especially in subthreshold regime. To mitigate the impact of gate leakage on transfer characteristics and allow accurate estimation of mobility, subthreshold slope and on/off current ratio, a measurement technique involving simultaneous sweep of both gate and drain voltages is proposed. Two dimensional numerical device simulation is used to illustrate the validity of the proposed technique. Experimental results obtained with Pentacene/PMMA OTFT with significant gate leakage show a low on/off current ratio of ∼ 102 and subthreshold is 10 V/decade obtained using conventional measurement technique. The proposed technique reveals that channel on/off current ratio is more than two orders of magnitude higher at ∼104 and subthreshold slope is 4.5 V/decade.

  12. Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon

    KAUST Repository

    Lin, Che-Yu

    2017-10-04

    High-frequency operation with ultra-thin, lightweight and extremely flexible semiconducting electronics are highly desirable for the development of mobile devices, wearable electronic systems and defense technologies. In this work, the first experimental observation of quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe2-MoS2 junctions as the conducting p-n channel is demonstrated. Both lateral n-p-n and p-n-p heterojunction bipolar transistors are fabricated to exhibit the output characteristics and current gain. A maximum common-emitter current gain of around 3 is obtained in our prototype two-dimensional quasi-heterojunction bipolar transistors. Interestingly, we also observe the negative differential resistance in the electrical characteristics. A potential mechanism is that the negative differential resistance is induced by resonant tunneling phenomenon due to the formation of quantum well under applying high bias voltages. Our results open the door to two-dimensional materials for high-frequency, high-speed, high-density and flexible electronics.

  13. Gate-induced carrier delocalization in quantum dot field effect transistors.

    Science.gov (United States)

    Turk, Michael E; Choi, Ji-Hyuk; Oh, Soong Ju; Fafarman, Aaron T; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R; Kikkawa, James M

    2014-10-08

    We study gate-controlled, low-temperature resistance and magnetotransport in indium-doped CdSe quantum dot field effect transistors. We show that using the gate to accumulate electrons in the quantum dot channel increases the "localization product" (localization length times dielectric constant) describing transport at the Fermi level, as expected for Fermi level changes near a mobility edge. Our measurements suggest that the localization length increases to significantly greater than the quantum dot diameter.

  14. Analyses of Short Channel Effects of Single-Gate and Double-Gate Graphene Nanoribbon Field Effect Transistors

    Directory of Open Access Journals (Sweden)

    Hojjatollah Sarvari

    2016-01-01

    Full Text Available Short channel effects of single-gate and double-gate graphene nanoribbon field effect transistors (GNRFETs are studied based on the atomistic pz orbital model for the Hamiltonian of graphene nanoribbon using the nonequilibrium Green’s function formalism. A tight-binding Hamiltonian with an atomistic pz orbital basis set is used to describe the atomistic details in the channel of the GNRFETs. We have investigated the vital short channel effect parameters such as Ion and Ioff, the threshold voltage, the subthreshold swing, and the drain induced barrier lowering versus the channel length and oxide thickness of the GNRFETs in detail. The gate capacitance and the transconductance of both devices are also computed in order to calculate the intrinsic cut-off frequency and switching delay of GNRFETs. Furthermore, the effects of doping of the channel on the threshold voltage and the frequency response of the double-gate GNRFET are discussed. We have shown that the single-gate GNRFET suffers more from short channel effects if compared with those of the double-gate structure; however, both devices have nearly the same cut-off frequency in the range of terahertz. This work provides a collection of data comparing different features of short channel effects of the single gate with those of the double gate GNRFETs. The results give a very good insight into the devices and are very useful for their digital applications.

  15. Nanogranular SiO{sub 2} proton gated silicon layer transistor mimicking biological synapses

    Energy Technology Data Exchange (ETDEWEB)

    Liu, M. J.; Huang, G. S., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Guo, Q. L.; Tian, Z. A.; Li, G. J.; Mei, Y. F. [Department of Materials Science, Fudan University, Shanghai 200433 (China); Feng, P., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Shao, F.; Wan, Q. [School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)

    2016-06-20

    Silicon on insulator (SOI)-based transistors gated by nanogranular SiO{sub 2} proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

  16. Nanogranular SiO2 proton gated silicon layer transistor mimicking biological synapses

    International Nuclear Information System (INIS)

    Liu, M. J.; Huang, G. S.; Guo, Q. L.; Tian, Z. A.; Li, G. J.; Mei, Y. F.; Feng, P.; Shao, F.; Wan, Q.

    2016-01-01

    Silicon on insulator (SOI)-based transistors gated by nanogranular SiO 2 proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

  17. Improved compact model for double-gate tunnel field-effect transistors by the rigorous consideration of gate fringing field

    Science.gov (United States)

    Kim, Sangwan; Choi, Woo Young

    2017-08-01

    In this work, the accuracy of a compact current-voltage (I-V) model for double-gate n-channel tunnel field-effect transistors (TFETs) is improve by considering outer and inner gate fringing field effects. The refined model is benchmarked against technology computer-aided design (TCAD) device simulations and compared against a previously published compact model. The normalized root-mean-square error for current in the linear region of operation (i.e., for 0.05 V drain voltage) is reduced from ˜593 to ˜5%.

  18. Electrochemical Single-Molecule Transistors with Optimized Gate Coupling

    DEFF Research Database (Denmark)

    Osorio, Henrry M.; Catarelli, Samantha; Cea, Pilar

    2015-01-01

    . These data are rationalized in terms of a two-step electrochemical model for charge transport across the redox bridge. In this model the gate coupling in the ionic liquid is found to be fully effective with a modeled gate coupling parameter, ξ, of unity. This compares to a much lower gate coupling parameter......Electrochemical gating at the single molecule level of viologen molecular bridges in ionic liquids is examined. Contrary to previous data recorded in aqueous electrolytes, a clear and sharp peak in the single molecule conductance versus electrochemical potential data is obtained in ionic liquids...

  19. Device characteristics of polymer dual-gate field-effect transistors

    NARCIS (Netherlands)

    Maddalena, F.; Spijkman, M.; Brondijk, J. J.; Fonteijn, P.; Brouwer, F.; Hummelen, J. C.; de Leeuw, D. M.; Blom, P. W. M.; de Boer, B.

    2008-01-01

    Dual-gate organic field-effect transistors (OFETs) were fabricated by solution processing using different p-type polymer semiconductors and polymer top-dielectric materials on prefabricated substrates with gold source-drain contacts defined by photolithography. The semiconductors and top dielectrics

  20. Charge transport in dual-gate organic field-effect transistors

    NARCIS (Netherlands)

    Brondijk, J.J.; Spijkman, M.; Torricelli, F.; Blom, P.W.M.; Leeuw, D.M. de

    2012-01-01

    The charge carrier distribution in dual-gate field-effect transistors is investigated as a function of semiconductor thickness. A good agreement with 2-dimensional numerically calculated transfer curves is obtained. For semiconductor thicknesses larger than the accumulation width, two spatially

  1. Gate-bias assisted charge injection in organic field-effect transistors

    NARCIS (Netherlands)

    Brondijk, J. J.; Torricelli, F.; Smits, E. C. P.; Blom, P. W. M.; de Leeuw, D. M.

    The charge injection barriers in organic field-effect transistors (OFETs) seem to be far less critical as compared to organic light-emitting diodes (OLEDs). Counter intuitively, we show that the origin is image-force lowering of the barrier due to the gate bias at the source contact, although the

  2. Gate-bias assisted charge injection in organic field-effect transistors

    NARCIS (Netherlands)

    Brondijk, J.J.; Torricelli, F.; Smits, E.C.P.; Blom, P.W.M.; Leeuw, D.M. de

    2012-01-01

    The charge injection barriers in organic field-effect transistors (OFETs) seem to be far less critical as compared to organic light-emitting diodes (OLEDs). Counter intuitively, we show that the origin is image-force lowering of the barrier due to the gate bias at the source contact, although the

  3. Rendering high charge density of states in ionic liquid-gated MoS 2 transistors

    NARCIS (Netherlands)

    Lee, Y.; Lee, J.; Kim, S.; Park, H.S.

    2014-01-01

    We investigated high charge density of states (DOS) in the bandgap of MoS2 nanosheets with variable temperature measurements on ionic liquid-gated MoS2 transistors. The thermally activated charge transport indicates that the electrical current in the two-dimensional MoS 2 nanosheets under high

  4. Field Plate Optimization in Low-Power High-Gain Source-Gated Transistors

    NARCIS (Netherlands)

    Sporea,R.A.; Trainor, M.J.; Young, N.D.; Shannon, J.M.; Silva, S.R.P.

    2012-01-01

    Source-gated transistors (SGTs) have potentially very high output impedance and low saturation voltages, which make them ideal as building blocks for high performance analog circuits fabricated in thin-film technologies. The quality of the saturation is greatly influenced by the design of the

  5. Junctionless Thin-Film Transistors Gated by an H₃PO₄-Incorporated Chitosan Proton Conductor.

    Science.gov (United States)

    Liu, Huixuan; Xun, Damao

    2018-04-01

    We fabricated an H3PO4-incorporated chitosan proton conductor film that exhibited the electric double layer effect and showed a high specific capacitance of 4.42 μF/cm2. Transparent indium tin oxide thin-film transistors gated by H3PO4-incorporated chitosan films were fabricated by sputtering through a shadow mask. The operating voltage was as low as 1.2 V because of the high specific capacitance of the H3PO4-incorporated chitosan dielectrics. The junctionless transparent indium tin oxide thin film transistors exhibited good performance, including an estimated current on/off ratio and field-effect mobility of 1.2 × 106 and 6.63 cm2V-1s-1, respectively. These low-voltage thin-film electric-double-layer transistors gated by H3PO4-incorporated chitosan are promising for next generation battery-powered "see-through" portable sensors.

  6. X-band T/R switch with body-floating multi-gate PDSOI NMOS transistors

    Science.gov (United States)

    Park, Mingyo; Min, Byung-Wook

    2018-03-01

    This paper presents an X-band transmit/receive switch using multi-gate NMOS transistors in a silicon-on-insulator CMOS process. For low loss and high power handling capability, floating body multi-gate NMOS transistors are adopted instead of conventional stacked NMOS transistors, resulting in 53% reduction of transistor area. Comparing to the stacked NMOS transistors, the multi gate transistor shares the source and drain region between stacked transistors, resulting in reduced chip area and parasitics. The impedance between bodies of gates in multi-gate NMOS transistors is assumed to be very large during design and confirmed after measurement. The measured input 1 dB compression point is 34 dBm. The measured insertion losses of TX and RX modes are respectively 1.7 dB and 2.0 dB at 11 GHz, and the measured isolations of TX and RX modes are >27 dB and >20 dB in X-band, respectively. The chip size is 0.086 mm2 without pads, which is 25% smaller than the T/R switch with stacked transistors.

  7. GaAs vapor-grown bipolar transistors.

    Science.gov (United States)

    Nuese, C. J.; Gannon, J. J.; Dean, R. H.; Gossenberger, H. F.; Enstrom, R. E.

    1972-01-01

    Discussion of an approach for the fabrication of high-temperature GaAs transistors which is centered on the preparation of n-p-n three-layered structures entirely by a vapor-phase growth technique, as described by Tietjen and Amick (1966). The low growth temperature of approximately 750 C is thought to reduce contamination during crystal growth and to contribute to the reasonably high minority-carrier lifetimes obtained for the vapor-grown p-n junctions. The fact that impurity concentrations and layer thicknesses can be precisely controlled for epitaxial layers as thin as 1 micrometer is an important feature of this growth technique.

  8. Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

    International Nuclear Information System (INIS)

    Han, Jinhua; Wang, Wei; Ying, Jun; Xie, Wenfa

    2014-01-01

    An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized

  9. Sidewall gated double well quasi-one-dimensional resonant tunneling transistors

    Science.gov (United States)

    Kolagunta, V. R.; Janes, D. B.; Melloch, M. R.; Youtsey, C.

    1997-12-01

    We present gating characteristics of submicron vertical resonant tunneling transistors in double quantum well heterostructures. Current-voltage characteristics at room temperature and 77 K for devices with minimum feature widths of 0.9 and 0.7 μm are presented and discussed. The evolution of the I-V characteristics with increasing negative gate biases is related to the change in the lateral confinement, with a transition from a large area 2D to a quasi-1D. Even gating of multiple wells and lateral confinement effects observable at 77 K make these devices ideally suited for applications in multi-valued logic systems and low-dimensional structures.

  10. Inversion gate capacitance of undoped single-gate and double-gate field-effect transistor geometries in the extreme quantum limit

    Energy Technology Data Exchange (ETDEWEB)

    Majumdar, Amlan, E-mail: amajumd@us.ibm.com [IBM Research Division, T. J. Watson Research Center, Yorktown Heights, New York 10598 (United States)

    2015-05-28

    We present first-principle analytical derivations and numerically modeled data to show that the gate capacitance per unit gate area C{sub G} of extremely thin undoped-channel single-gate and double-gate field-effect transistor geometries in the extreme quantum limit with single-subband occupancy can be written as 1/C{sub G} = 1/C{sub OX} + N{sub G}/C{sub DOS} + N{sub G}/ηC{sub WF}, where N{sub G} is the number of gates, C{sub OX} is the oxide capacitance per unit area, C{sub DOS} is the density-of-states capacitance per unit area, C{sub WF} is the wave function spreading capacitance per unit area, and η is a constant on the order of 1.

  11. Coupling between electrolyte and organic semiconductor in electrolyte-gated organic field effect transistors (Conference Presentation)

    Science.gov (United States)

    Biscarini, Fabio; Di Lauro, Michele; Berto, Marcello; Bortolotti, Carlo A.; Geerts, Yves H.; Vuillaume, Dominique

    2016-11-01

    Organic field effect transistors (OFET) operated in aqueous environments are emerging as ultra-sensitive biosensors and transducers of electrical and electrochemical signals from a biological environment. Their applications range from detection of biomarkers in bodily fluids to implants for bidirectional communication with the central nervous system. They can be used in diagnostics, advanced treatments and theranostics. Several OFET layouts have been demonstrated to be effective in aqueous operations, which are distinguished either by their architecture or by the respective mechanism of doping by the ions in the electrolyte solution. In this work we discuss the unification of the seemingly different architectures, such as electrolyte-gated OFET (EGOFET), organic electrochemical transistor (OECT) and dual-gate ion-sensing FET. We first demonstrate that these architectures give rise to the frequency-dependent response of a synapstor (synapse-like transistor), with enhanced or depressed modulation of the output current depending on the frequency of the time-dependent gate voltage. This behavior that was reported for OFETs with embedded metal nanoparticles shows the existence of a capacitive coupling through an equivalent network of RC elements. Upon the systematic change of ions in the electrolyte and the morphology of the charge transport layer, we show how the time scale of the synapstor is changed. We finally show how the substrate plays effectively the role of a second bottom gate, whose potential is actually fixed by the pH/composition of the electrolyte and the gate voltage applied.

  12. Fabrication of ambipolar gate-all-around field-effect transistors using silicon nanobridge arrays

    Science.gov (United States)

    Oh, Jin Yong; Park, Jong-Tae; Islam, M. Saif

    2013-09-01

    Nanowire bridges have been almost dormant in a nanostructured device community due to the challenges in reproducible growth and device fabrication. In this work, we present simple methods for creating silicon nanobridge arrays with repeatability, and demonstrate integration of gate-all-around field-effect-transistors in the arrays. P-type silicon nanowires air-bridges were synthesized using gold nanoparticles via the VLS technique on the array of predefined silicon electrode-pairs, and then surrounding gates were formed on the suspended air-bridge nanowires. The nanowire air-bridge field-effect-transistors with the surrounding gate exhibited p-type accumulation-mode characteristics with a subthreshold swing of 187 mV/dec and an on/off current ratio of 1.6×106. Despite the surrounding gate that helps gate biases govern the channel, off current substantially increased as drain bias increases. This ambipolar current-voltage property was attributable to gate-induced-drain-leakage at the overlap of gate and drain electrodes and trap-assisted tunneling at the nanowire and electrode connection.

  13. Photo-electronic current transport in back-gated graphene transistor

    Science.gov (United States)

    Srivastava, Ashok; Chen, Xinlu; Pradhan, Aswini K.

    2017-04-01

    In this work, we have studied photo-electronic current transport in a back-gated graphene field-effect transistor. Under the light illumination, band bending at the metal/graphene interface develops a built-in potential which generates photonic current at varying back-gate biases. A typical MOSFET type back-gated transistor structure uses a monolayer graphene as the channel layer formed over the silicon dioxide/silicon substrate. It is shown that the photo-electronic current consists of current contributions from photovoltaic, photo-thermoelectric and photo-bolometric effects. A maximum external responsivity close to 0.0009A/W is achieved at 30μW laser power source and 633nm wavelength.

  14. Osteoblastic cells trigger gate currents on nanocrystalline diamond transistor

    Czech Academy of Sciences Publication Activity Database

    Ižák, Tibor; Krátká, Marie; Kromka, Alexander; Rezek, Bohuslav

    2015-01-01

    Roč. 129, May (2015), 95-99 ISSN 0927-7765 R&D Projects: GA ČR GAP108/12/0996 Grant - others:AVČR(CZ) M100101209 Institutional support: RVO:68378271 Keywords : field-effect transistors * nanocrystalline diamond * osteoblastic cells * leakage currents Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 3.902, year: 2015

  15. Nanoscaled biological gated field effect transistors for cytogenetic analysis

    DEFF Research Database (Denmark)

    Kwasny, Dorota; Dimaki, Maria; Andersen, Karsten Brandt

    2014-01-01

    Cytogenetic analysis is the study of chromosome structure and function, and is often used in cancer diagnosis, as many chromosome abnormalities are linked to the onset of cancer. A novel label free detection method for chromosomal translocation analysis using nanoscaled field effect transistors...

  16. Strain-gated piezotronic transistors based on vertical zinc oxide nanowires.

    Science.gov (United States)

    Han, Weihua; Zhou, Yusheng; Zhang, Yan; Chen, Cheng-Ying; Lin, Long; Wang, Xue; Wang, Sihong; Wang, Zhong Lin

    2012-05-22

    Strain-gated piezotronic transistors have been fabricated using vertically aligned ZnO nanowires (NWs), which were grown on GaN/sapphire substrates using a vapor-liquid-solid process. The gate electrode of the transistor is replaced by the internal crystal potential generated by strain, and the control over the transported current is at the interface between the nanowire and the top or bottom electrode. The current-voltage characteristics of the devices were studied using conductive atomic force microscopy, and the results show that the current flowing through the ZnO NWs can be tuned/gated by the mechanical force applied to the NWs. This phenomenon was attributed to the piezoelectric tuning of the Schottky barrier at the Au-ZnO junction, known as the piezotronic effect. Our study demonstrates the possibility of using Au droplet capped ZnO NWs as a transistor array for mapping local strain. More importantly, our design gives the possibility of fabricating an array of transistors using individual vertical nanowires that can be controlled independently by applying mechanical force/pressure over the top. Such a structure is likely to have important applications in high-resolution mapping of strain/force/pressure.

  17. The memory effect of a pentacene field-effect transistor with a polarizable gate dielectric

    Science.gov (United States)

    Unni, K. N. N.; de Bettignies, Remi; Dabos-Seignon, Sylvie; Nunzi, Jean-Michel

    2004-06-01

    The nonvolatile transistor memory element is an interesting topic in organic electronics. In this case a memory cell consists of only one device where the stored information is written as a gate insulator polarization by a gate voltage pulse and read by the channel conductance control with channel voltage pulse without destruction of the stored information. Therefore such transistor could be the base of non-volatile non-destructively readable computer memory of extremely high density. Also devices with polarizable gate dielectrics can function more effectively in certain circuits. The effective threshold voltage Vt can be brought very close to zero, for applications where the available gate voltage is limited. Resonant and adaptive circuits can be tuned insitu by polarizing the gates. Poly(vinylidene fluoride), PVDF and its copolymer with trifluoroethylene P(VDF-TrFE) are among the best known and most widely used ferroelectric polymers. In this manuscript, we report new results of an organic FET, fabricated with pentacene as the active material and P(VDF-TrFE) as the gate insulator. Application of a writing voltage of -50 V for short duration results in significant change in the threshold voltage and remarkable increase in the drain current. The memory effect is retained over a period of 20 hours.

  18. Influence of O2 flow rate on HfO2 gate dielectrics for back-gated graphene transistors

    Science.gov (United States)

    Lakshmi Ganapathi, Kolla; Bhat, Navakanta; Mohan, Sangeneni

    2014-05-01

    HfO2 thin films deposited on Si substrate using electron beam evaporation, are evaluated for back-gated graphene transistors. The amount of O2 flow rate, during evaporation is optimized for 35 nm thick HfO2 films, to achieve the best optical, chemical and electrical properties. It has been observed that with increasing oxygen flow rate, thickness of the films increased and refractive index decreased due to increase in porosity resulting from the scattering of the evaporant. The films deposited at low O2 flow rates (1 and 3 SCCM) show better optical and compositional properties. The effects of post-deposition annealing and post-metallization annealing in forming gas ambience (FGA) on the optical and electrical properties of the films have been analyzed. The film deposited at 3 SCCM O2 flow rate shows the best properties as measured on MOS capacitors. To evaluate the performance of device properties, back-gated bilayer graphene transistors on HfO2 films deposited at two O2 flow rates of 3 and 20 SCCM have been fabricated and characterized. The transistor with HfO2 film deposited at 3 SCCM O2 flow rate shows better electrical properties consistent with the observations on MOS capacitor structures. This suggests that an optimum oxygen pressure is necessary to get good quality films for high performance devices.

  19. Tunneling, Current Gain, and Transconductance in Silicon-Germanium Heterojunction Bipolar Transistors Operating at Millikelvin Temperatures

    Science.gov (United States)

    Davidović, D.; Ying, H.; Dark, J.; Wier, B. R.; Ge, L.; Lourenco, N. E.; Omprakash, A. P.; Mourigal, M.; Cressler, J. D.

    2017-08-01

    Quantum-transport measurements in advanced silicon-germanium heterojunction bipolar transistors (SiGe HBTs) are presented and analyzed, including tunneling spectroscopy of discrete impurity levels localized within the transistor and the dependence on an applied magnetic field. The collector current at millikelvin temperatures is well accounted for by ideal electron tunneling throughout the entire base. The amplification principle at millikelvin temperatures is fundamentally quantum mechanical in nature: an increase in base voltage, requiring a moderate base current, creates an equal and opposite decrease in the tunneling barrier seen by the electrons in the emitter, thereby increasing the collector current significantly more than the base current, producing current gain. Highly scaled SiGe HBTs operate predictably at millikelvin temperatures, thus opening the possibility of viable SiGe millikelvin circuitry.

  20. Performance enhancement of a heterojunction bipolar transistor (HBT) by two-step passivation

    International Nuclear Information System (INIS)

    Fu, S.-I.; Lai, P.-H.; Tsai, Y.-Y.; Hung, C.-W.; Yen, C.-H.; Cheng, S.-Y.; Liu, W.-C.

    2006-01-01

    An interesting two-step passivation (with ledge structure and sulphide based chemical treatment) on base surface, for the first time, is demonstrated to study the temperature-dependent DC characteristics and noise performance of an InGaP/GaAs heterojunction bipolar transistor (HBT). Improved transistor behaviors on maximum current gain β max , offset voltage ΔV CE , and emitter size effect are obtained by using the two-step passivation. Moreover, the device with the two-step passivation exhibits relatively temperature-independent and improved thermal stable performances as the temperature is increased. Therefore, the two-step passivationed device can be used for high-temperature and low-power electronics applications

  1. Gamma Irradiation Performance Tests of the Bipolar Junction Transistor (BJT) for Medical Dosimetry Purposes

    Energy Technology Data Exchange (ETDEWEB)

    Nazififard, Mohammad; Suh, Kune Y. [PHILOSOPHIA, Inc., Seoul (Korea, Republic of); Faghihi, Reyhaneh [Kashan Univ. of Medical Science, Kashan (Iran, Islamic Republic of); Norov, Enkhbat [POSTECH, Pohang (Korea, Republic of)

    2014-05-15

    Two basic radiation damage mechanisms may affect semiconductor devices which are Displacement damage and Ionization damage. In displacement damage mechanism, the incident radiation displaces silicon atoms from their lattice sites. The resulting defects alter the electronic characteristics of the crystal. In ionization damage mechanism, the absorbed energy by electronic ionization in insulating layers liberates charge carriers, which diffuse or drift to other locations where they are trapped, leading to unintended concentrations of charge and, as a consequence, parasitic fields. Both mechanisms are important in detectors, transistors and integrated circuits. Hardly a system is immune to either one phenomenon and most are sensitive to both. This paper investigates the behavior of Bipolar Junction Transistors (BJTs), exposed to radiation in order to establish their applicability in a radiation environment.

  2. Electrical determination of the bandgap energies of the emitter and base regions of bipolar junction transistors

    Science.gov (United States)

    Mimila-Arroyo, J.

    2016-10-01

    A pure electrical method is presented to extract emitter and base bandgaps of a bipolar junction transistor (BJT) at the locations where the minority carrier injection takes place. It is based on the simultaneous measurement of the collector and base currents as a function of the emitter-base forward bias (Gummer plot) and the corresponding current gain. From the obtained saturation currents as a function of temperature, we extract the bandgap energies. The accuracy of the method is demonstrated for InGaP-GaAs, Si, and Ge commercial devices. For InGaP-GaAs transistors, the results can be understood if the emitter-base heterojunction is not an abrupt but a gradual one. The presented method is a reliable tool that can aid in the development of new compound semiconductor based BJTs whose bandgap energies are highly sensitive to their composition.

  3. Origin of 1/f PM and AM noise in bipolar junction transistor amplifiers.

    Science.gov (United States)

    Walls, F L; Ferre-Pikal, E S; Jefferts, S R

    1997-01-01

    In this paper we report the results of extensive research on phase modulation (PM) and amplitude modulation (AM) noise in linear bipolar junction transistor (BJT) amplifiers. BJT amplifiers exhibit 1/f PM and AM noise about a carrier signal that is much larger than the amplifiers thermal noise at those frequencies in the absence of the carrier signal. Our work shows that the 1/f PM noise of a BJT based amplifier is accompanied by 1/f AM noise which can be higher, lower, or nearly equal, depending on the circuit implementation. The 1/f AM and PM noise in BJTs is primarily the result of 1/f fluctuations in transistor current, transistor capacitance, circuit supply voltages, circuit impedances, and circuit configuration. We discuss the theory and present experimental data in reference to common emitter amplifiers, but the analysis can be applied to other configurations as well. This study provides the functional dependence of 1/f AM and PM noise on transistor parameters, circuit parameters, and signal frequency, thereby laying the groundwork for a comprehensive theory of 1/f AM and PM noise in BJT amplifiers. We show that in many cases the 1/f PM and AM noise can be reduced below the thermal noise of the amplifier.

  4. T-shaped emitter metal heterojunction bipolar transistors for submillimeter wave applications

    Science.gov (United States)

    Fung, Andy; Samoska, Lorene; Velebir, Jim; Siege, Peter; Rodwell, Mark; Paidi, Vamsi; Griffth, Zach; Urteaga, Miguel; Malik, Roger

    2004-01-01

    We report on the development of submillimeter wave transistors at JPL. The goal of the effort is to produce advance-reliable high frequency and high power amplifiers, voltage controlled oscillators, active multipliers, and high-speed mixed-signal circuits for space borne applications. The technology in development to achieve this is based on the Indium Phosphide (InP) Heterojunction Bipolar Transistor (HBT). The HBT is well suited for high speed, high power and uniform (across wafer) performance, due to the ability to tailor the material structure that electrons traverse through by well-controlled epitaxial growth methods. InP with its compatible lattice matched alloys such as indium gallium arsenide (InGaAs) and indium aluminium arsenide (InAlAs) provides for high electron velocities and high voltage breakdown capabilities. The epitaxial methods for this material system are fairly mature, however the implementation of high performance and reliable transistors are still under development by many laboratories. Our most recently fabricated, second generation mesa HBTs at JPL have extrapolated current gain cutoff frequency (FJ of 142GHz and power gain cutoff frequency (Fm,) of approximately 160GHz. This represents a 13% and 33% improvement of Ft and F, respectively, compared to the first generation mesa HBTs [l]. Analysis based on the University of California, Santa Barbara (UCSB) device model, RF device characteristics can be significantly improved by reducing base contact resistance and base metal contact width. We will describe our effort towards increasing transistor performance and yield.

  5. Improved Model for Increased Surface Recombination Current in Irradiated Bipolar Junction Transistors

    Science.gov (United States)

    Barnaby, H. J.; Vermeire, B.; Campola, M. J.

    2015-08-01

    Current gain degradation in irradiated bipolar junction transistors is primarily due to excess base current caused by enhanced carrier recombination in the emitter-base space-charge region (SCR). Radiation-induced traps at the interface between silicon and the bipolar base oxide facilitate the recombination process primarily above the sensitive emitter-base junction. This leads to an increase in surface recombination current in the SCR, which is a non-ideal component of the BJT's base current characteristic under active bias conditions. In this paper, we derive a precise analytical model for surface recombination current that captures bias dependencies typically omitted from traditional models. This improved model is validated by comparisons to these traditional approaches.

  6. ESTIMATION OF THERMAL PARAMETERS OF POWER BIPOLAR TRANSISTORS BY THE METHOD OF THERMAL RELAXATION DIFFERENTIAL SPECTROMETRY

    Directory of Open Access Journals (Sweden)

    V. S. Niss

    2015-01-01

    Full Text Available Thermal performance of electronic devices determines the stability and reliability of the equipment. This leads to the need for a detailed thermal analysis of semiconductor devices. The goal of the work is evaluation of thermal parameters of high-power bipolar transistors in plastic packages TO-252 and TO-126 by a method of thermal relaxation differential spectrometry. Thermal constants of device elements and distribution structure of thermal resistance defined as discrete and continuous spectra using previously developed relaxation impedance spectrometer. Continuous spectrum, based on higher-order derivatives of the dynamic thermal impedance, follows the model of Foster, and discrete to model of Cauer. The structure of sample thermal resistance is presented in the form of siх-chain electro-thermal RC model. Analysis of the heat flow spreading in the studied structures is carried out on the basis of the concept of thermal diffusivity. For transistor structures the area and distribution of the heat flow cross-section are determined. On the basis of the measurements the thermal parameters of high-power bipolar transistors is evaluated, in particular, the structure of their thermal resistance. For all of the measured samples is obtained that the thermal resistance of the layer planting crystal makes a defining contribution to the internal thermal resistance of transistors. In the transition layer at the border of semiconductor-solder the thermal resistance increases due to changes in the mechanism of heat transfer. Defects in this area in the form of delamination of solder, voids and cracks lead to additional growth of thermal resistance caused by the reduction of the active square of the transition layer. Method of thermal relaxation differential spectrometry allows effectively control the distribution of heat flow in high-power semiconductor devices, which is important for improving the design, improve the quality of landing crystals of power

  7. Evaluation of Enhanced Low Dose Rate Sensitivity in Discrete Bipolar Junction Transistors

    Science.gov (United States)

    Chen, Dakai; Ladbury Raymond; LaBel, Kenneth; Topper, Alyson; Ladbury, Raymond; Triggs, Brian; Kazmakites, Tony

    2012-01-01

    We evaluate the low dose rate sensitivity in several families of discrete bipolar transistors across device parameter, quality assurance level, and irradiation bias configuration. The 2N2222 showed the most significant low dose rate sensitivity, with low dose rate enhancement factor of 3.91 after 100 krad(Si). The 2N2907 also showed critical degradation levels. The devices irradiated at 10 mrad(Si)/s exceeded specifications after 40 and 50 krad(Si) for the 2N2222 and 2N2907 devices, respectively.

  8. Terahertz emission from collapsing field domains during switching of a gallium arsenide bipolar transistor.

    Science.gov (United States)

    Vainshtein, Sergey; Kostamovaara, Juha; Yuferev, Valentin; Knap, Wojciech; Fatimy, Abdel; Diakonova, Nina

    2007-10-26

    Broadband pulsed THz emission with peak power in the sub-mW range has been observed experimentally during avalanche switching in a gallium arsenide bipolar junction transistor at room temperature, while significantly higher total generated power is predicted in simulations. The emission is attributed to very fast oscillations in the conductivity current across the switching channels, which appear as a result of temporal evolution of the field domains generated in highly dense electron-hole plasma. This plasma is formed in turn by powerful impact ionization in multiple field domains of ultrahigh amplitude.

  9. Total dose and dose rate models for bipolar transistors in circuit simulation.

    Energy Technology Data Exchange (ETDEWEB)

    Campbell, Phillip Montgomery; Wix, Steven D.

    2013-05-01

    The objective of this work is to develop a model for total dose effects in bipolar junction transistors for use in circuit simulation. The components of the model are an electrical model of device performance that includes the effects of trapped charge on device behavior, and a model that calculates the trapped charge densities in a specific device structure as a function of radiation dose and dose rate. Simulations based on this model are found to agree well with measurements on a number of devices for which data are available.

  10. Laser Pulse Tests of Bipolar Junction Transistors (BJTs) for SET Analysis

    Science.gov (United States)

    Daniel, C.; Plettner, C.; Poivey, C.; Schuttauf, A.; Tonicello, F.; Triggianese, M.

    2014-08-01

    In order to study the Single Event Transient (SET) sensitivity of discrete bipolar junction transistors, laser tests conducted at EADS Innovation Works in Sureness are presented and discussed. A number of different BJT samples have been tested in different operating conditions. The tests demonstrate that: discrete BJTs are indeed sensitive to collected charge; the most sensitive region is the collector/base junctions and that the different internal structure gives different SET shapes. We present measurements, simulation and comparison for SET modeled in PSPICE and tested with a laser.

  11. Bias dependence of synergistic radiation effects induced by electrons and protons on silicon bipolar junction transistors

    Science.gov (United States)

    Liu, Chaoming; Li, Xingji; Yang, Jianqun; Ma, Guoliang; Xiao, Liyi

    2015-06-01

    Bias dependence on synergistic radiation effects caused by 110 keV electrons and 170 keV protons on the current gain of 3DG130 NPN bipolar junction transistors (BJTs) is studied in this paper. Experimental results indicate that the influence induced by 170 keV protons is always enhancement effect during the sequential irradiation. However, the influence induced by 110 keV electrons on the BJT under various bias cases is different during the sequential irradiation. The transition fluence of 110 keV electrons is dependent on the bias case on the emitter-base junction of BJT.

  12. Optimization of base-to-emitter spacer thickness to maximize the frequency response of bipolar transistors

    Science.gov (United States)

    Lee, Wai-Kit; Chan, Alain C. K.; Chan, Mansun

    2005-04-01

    The impacts of base-to-emitter spacer thickness on the unity gain frequency ( fT), base resistance ( rB), base collector capacitance ( CBC) and maximum oscillation frequency ( fmax) of a bipolar junction transistor (BJT) are studied. Using the extracted Y-parameters from a simulated device with structural parameters calibrated to an actual process, the resulting fT and fmax with different spacer thickness is reported. A tradeoff between peak fT and fmax is observed and the process window to obtain high fT and fmax is proposed.

  13. Bipolar redox behaviour, field-effect mobility and transistor switching of the low-molecular azo glass AZOPD.

    Science.gov (United States)

    Arlt, Michael; Scheffler, Ayna; Suske, Irina; Eschner, Michael; Saragi, Tobat P I; Salbeck, Josef; Fuhrmann-Lieker, Thomas

    2010-11-07

    We present electrochemical and spectroelectrochemical data for the bipolar azo compound N,N'-diphenyl-N,N'-bis[4-(phenylazo)phenyl]-4,4'diaminobiphenyl (AZOPD) demonstrating reversible bipolar redox behaviour with a bandgap of 2.1 eV. The reduced species formed upon two-electron transfer can be described as bis(radical anion) as was confirmed by comparison with a reference compound with only one azo chromophore. Hole and electron transport behaviour in amorphous films was demonstrated by the fabrication of organic field-effect transistors using gold and magnesium contacts, respectively. The transistors are sensitive to light due to E-Z photoisomerization.

  14. On the Bipolar DC Flow Field-Effect-Transistor for Multifunctional Sample Handing in Microfluidics: A Theoretical Analysis under the Debye–Huckel Limit

    Directory of Open Access Journals (Sweden)

    Weiyu Liu

    2018-02-01

    Full Text Available We present herein a novel method of bipolar field-effect control on DC electroosmosis (DCEO from a physical point of view, in the context of an intelligent and robust operation tool for stratified laminar streams in microscale systems. In this unique design of the DC flow field-effect-transistor (DC-FFET, a pair of face-to-face external gate terminals are imposed with opposite gate-voltage polarities. Diffuse-charge dynamics induces heteropolar Debye screening charge within the diffuse double layer adjacent to the face-to-face oppositely-polarized gates, respectively. A background electric field is applied across the source-drain terminal and forces the face-to-face counterionic charge of reversed polarities into induced-charge electroosmotic (ICEO vortex flow in the lateral direction. The chaotic turbulence of the transverse ICEO whirlpool interacts actively with the conventional plug flow of DCEO, giving rise to twisted streamlines for simultaneous DCEO pumping and ICEO mixing of fluid samples along the channel length direction. A mathematical model in thin-layer approximation and the low-voltage limit is subsequently established to test the feasibility of the bipolar DC-FFET configuration in electrokinetic manipulation of fluids at the micrometer dimension. According to our simulation analysis, an integrated device design with two sets of side-by-side, but upside-down gate electrode pair exhibits outstanding performance in electroconvective pumping and mixing even without any externally-applied pressure difference. Moreover, a paradigm of a microdevice for fully electrokinetics-driven analyte treatment is established with an array of reversed bipolar gate-terminal pairs arranged on top of the dielectric membrane along the channel length direction, from which we can obtain almost a perfect liquid mixture by using a smaller magnitude of gate voltages for causing less detrimental effects at a small Dukhin number. Sustained by theoretical

  15. High mobility polymer gated organic field effect transistor using zinc ...

    Indian Academy of Sciences (India)

    Parylene film prepared by chemical vapour deposition was used as the organic gate insulator. ... properties, due to their spatially extended π-electron system ... tronic defects (Gershenson et al 2006). Parylene forms pin hole free, thin conformal transparent coatings with excellent dielectric and mechanical properties ...

  16. Characterization of ionizing radiation effects in MOS structures by study of bipolar operation

    International Nuclear Information System (INIS)

    Bakhtiar, H.; Picard, C.; Brisset, C.; Bakhtiar, H.; Hoffmann, A.; Charles, J.P.

    1999-01-01

    This work presents an original method to characterize radiation effects of micronic transistors. The characterization includes a study of the transistor substrate-drain junction and current gain variation of the bipolar transistor (drain-substrate-source as emitter-base-collector) for different gate voltages. (authors)

  17. Photoinduced Recovery of Organic Transistor Memories with Photoactive Floating-Gate Interlayers.

    Science.gov (United States)

    Jeong, Yong Jin; Yun, Dong-Jin; Kim, Se Hyun; Jang, Jaeyoung; Park, Chan Eon

    2017-04-05

    Optical memories based on photoresponsive organic field-effect transistors (OFETs) are of great interest due to their unique applications, such as multibit storage memories and flexible imaging circuits. Most studies of OFET-type memories have focused on the photoresponsive active channels, but more useful functions can be additionally given to the devices by using floating gates that can absorb light. In this case, effects of photoirradiation on photoactive floating-gate layers need to be fully understood. Herein, we studied the photoinduced erasing effects of floating-gate interlayers on the electrical responses of OFET-type memories and considered the possible mechanisms. Polymer/C 60 composites were inserted between pentacene and SiO 2 to form photoresponsive floating-gate interlayers in transistor memory. When exposed to light, C 60 generated excitons, and these photoexcited carriers contributed to the elimination of trapped charge carriers, which resulted in the recovery of OFET performance. Such memory devices exhibited bistable current states controlled with voltage-driven programming and light-driven erasure. Furthermore, these devices maintained their charge-storing properties over 10 000 s. This proof-of-concept study is expected to open up new avenues in information technology for the development of organic memories that exhibit photoinduced recovery over a wide range of wavelengths of light when combined with appropriate photoactive floating-gate materials.

  18. Extended-gate organic field-effect transistor for the detection of histamine in water

    Science.gov (United States)

    Minamiki, Tsukuru; Minami, Tsuyoshi; Yokoyama, Daisuke; Fukuda, Kenjiro; Kumaki, Daisuke; Tokito, Shizuo

    2015-04-01

    As part of our ongoing research program to develop health care sensors based on organic field-effect transistor (OFET) devices, we have attempted to detect histamine using an extended-gate OFET. Histamine is found in spoiled or decayed fish, and causes foodborne illness known as scombroid food poisoning. The new OFET device possesses an extended gate functionalized by carboxyalkanethiol that can interact with histamine. As a result, we have succeeded in detecting histamine in water through a shift in OFET threshold voltage. This result indicates the potential utility of the designed OFET devices in food freshness sensing.

  19. Top-gate organic field-effect transistors fabricated on shape-memory polymer substrates

    Science.gov (United States)

    Choi, Sangmoo; Fuentes-Hernandez, Canek; Wang, Cheng-Yin; Wei, Andrew; Voit, Walter; Zhang, Yadong; Barlow, Stephen; Marder, Seth R.; Kippelen, Bernard

    2015-08-01

    We demonstrate top-gate organic field-effect transistors (OFETs) with a bilayer gate dielectric and doped contacts fabricated on shape-memory polymer (SMP) substrates. SMPs exhibit large variations in Young's modulus dependent on temperature and have the ability to fix two or more geometric configurations when a proper stimulus is applied. These unique properties make SMPs desirable for three-dimensional shape applications of OFETs. The electrical properties of OFETs on SMP substrates are presented and compared to those of OFETs on traditional glass substrates.

  20. Extended Gate Field-Effect Transistor Biosensors for Point-Of-Care Testing of Uric Acid.

    Science.gov (United States)

    Guan, Weihua; Reed, Mark A

    2017-01-01

    An enzyme-free redox potential sensor using off-chip extended-gate field effect transistor (EGFET) with a ferrocenyl-alkanethiol modified gold electrode has been used to quantify uric acid concentration in human serum and urine. Hexacyanoferrate (II) and (III) ions are used as redox reagent. The potentiometric sensor measures the interface potential on the ferrocene immobilized gold electrode, which is modulated by the redox reaction between uric acid and hexacyanoferrate ions. The device shows a near Nernstian response to uric acid and is highly specific to uric acid in human serum and urine. The interference that comes from glucose, bilirubin, ascorbic acid, and hemoglobin is negligible in the normal concentration range of these interferents. The sensor also exhibits excellent long term reliability and is regenerative. This extended gate field effect transistor based sensor is promising for point-of-care detection of uric acid due to the small size, low cost, and low sample volume consumption.

  1. CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

    Science.gov (United States)

    Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

    2018-04-01

    Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

  2. Extraction of mobility and Degradation coefficients in double gate junctionless transistors

    Science.gov (United States)

    Bhuvaneshwari, Y. V.; Kranti, Abhinav

    2017-12-01

    In this work, we use the modified McLarty function to understand and extract accumulation (μ acc) and bulk (μ bulk) mobility in Double Gate (DG) Junctionless (JL) MOSFETs over a wide range of doping concentration (N d) and temperature range (250 K to 520 K). The approach enables the estimation of mobility and its attenuation factors (θ 1 and θ 2) by a single method. The extracted results indicate that μ acc can reach higher values than μ bulk due to the screening effect. Results also show that θ 2 extracted in the accumulation regime of JL transistors exhibit relatively low values in comparison to inversion and accumulation mode devices. It is shown that the attenuation factor (θ 1) in JL devices designed with higher N d (≥1019 cm‑3) is mainly affected by series resistance (R sd) whereas, in inversion mode (IM) and Accumulation mode (AM) devices, θ 1 factor is governed by both the intrinsic mobility reduction factor (θ 10) and R sd. Additionally, the impact of variation in oxide thickness (T ox), gate length (L g), N d and temperature on θ 1 and θ 2 has been investigated for JL transistor. The weak dependence of μ bulk and μ acc on temperature shows the prevalence of coulomb scattering over phonon scattering for heavily doped JL transistors. The work provides insights into different modes of operation, extraction of mobility and attenuation factors which will be useful for the development of compact models for JL transistors.

  3. Producing of pover GaAs structures of bipolar and field-effect transistor by CVD-method

    Directory of Open Access Journals (Sweden)

    Voronin V. A.

    2010-03-01

    Full Text Available Investigation results in technology of doping Sn and Bi of perfect GaAs structures preparation by the lowe-temperature isothermal chloride epitaxy method are presented. A complex problem has been solved to obtain planar layers of the n+–n–n0–p type bipolar transistors and planar layers of the i–n0–n–n+ type Schottky field-effect transistors. Heterogenetty in the thickness less than 3% and doping level less than 5% has been achieved. This allowed to get the discrete Schottky field-effect transistors with improved operation characteristics.

  4. Fabrication and high temperature characteristics of ion-implanted GaAs bipolar transistors and ring-oscillators

    Science.gov (United States)

    Doerbeck, F. H.; Yuan, H. T.; Mclevige, W. V.

    1981-01-01

    Ion implantation techniques that permit the reproducible fabrication of bipolar GaAs integrated circuits are studied. A 15 stage ring oscillator and discrete transistor were characterized between 25 and 400 C. The current gain of the transistor was found to increase slightly with temperature. The diode leakage currents increase with an activation energy of approximately 1 eV and dominate the transistor leakage current 1 sub CEO above 200 C. Present devices fail catastrophically at about 400 C because of Au-metallization.

  5. Urea biosensor based on an extended-base bipolar junction transistor.

    Science.gov (United States)

    Sun, Tai-Ping; Shieh, Hsiu-Li; Liu, Chun-Lin; Chen, Chung-Yuan

    2014-01-01

    In this study, a urea biosensor was prepared by the immobilization of urease onto the sensitive membrane of an extended-base bipolar junction transistor. The pH variation was used to detect the concentration of urea. The SnO2/ITO glass, fabricated by sputtering SnO2 on the conductive ITO glass, was used as a pH-sensitive membrane, which was connected with a commercial bipolar junction transistor device. The gels, fabricated by the poly vinyl alcohol with pendent styrylpyridinium groups, were used to immobilize the urease. This readout circuit, fabricated in a 0.35-um CMOS 2P4M process, operated at 3.3V supply voltage. This circuit occupied an area of 1.0 mm × 0.9 mm. The dynamic range of the urea biosensor was from 1.4 to 64 mg/dl at the 10 mM phosphate buffer solution and the sensitivity of this range was about 65.8 mV/pUrea. The effect of urea biosensors with different pH values was considered, and the characteristics of urea biosensors based on EBBJT were described.

  6. Physical processes of current gain in InAs bipolar junction transistors

    Science.gov (United States)

    Wu, X.; Averett, K. L.; Maimon, S.; Koch, M. W.; Wicks, G. W.

    2004-01-01

    InAs bipolar junction transistors (BJTs), grown by molecular beam epitaxy, are reported with common emitter current gains ( β's) as large as 400. The factors affecting the common emitter current gain have been studied by estimating the magnitudes of the base transport factor ( αT) and emitter injection efficiency ( γ). This has been accomplished by studying a sequence of InAs BJTs with varying emitter doping densities, NE. Minority carrier diffusion length in the base ( LB), αT, and γ have been extracted from measured electrical characteristics. The results of the study of these InAs BJTs are as follows: L B≈0.4 μm, αT≈98% and γ ranges from 92% to nearly 100% depending on NE. This knowledge of the magnitudes of the injection efficiencies suggests when it would be useful to move from the simple BJT structure to the more advanced heterojunction bipolar transistor (HBT) structure. Lower γ BJTs would be improved, however high- γ BJTs would benefit little, by the use of the widegap emitters of HBTs. The method developed here to estimate γ, αT and LB is not specific to InAs BJTs, but should be useful for study of BJTs and HBTs in any material system.

  7. Fringing field effects in negative capacitance field-effect transistors with a ferroelectric gate insulator

    Science.gov (United States)

    Hattori, Junichi; Fukuda, Koichi; Ikegami, Tsutomu; Ota, Hiroyuki; Migita, Shinji; Asai, Hidehiro; Toriumi, Akira

    2018-04-01

    We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal-oxide-semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.

  8. ``Gate-to-gate`` BJT obtained from the double-gate input JFET to reset charge preamplifiers

    Energy Technology Data Exchange (ETDEWEB)

    Fazzi, A. [Politecnico di Milano (Italy). Dipartimento di Ingegneria Nucleare; Rehak, P. [Brookhaven National Laboratory, Upton, NY 11973 (United States)

    1996-08-01

    A novel charge restoration mechanism to reset charge sensitive preamplifiers is presented. The ``gate-to-gate`` Bipolar Junction Transistor transversal to the input JFET with independent top and bottom gates is exploited as a ``reset transistor`` embodied in the preamplifier input device. The p-n junction between the bottom gate and the channel is forward-biased by a proper feedback loop supplying the necessary restoration current to the input node capacitance through the top gate-channel reversed-biased junction. The continuous reset mode is here analysed with reference to the DC stability, the pulse response and the noise behaviour. Experimental results are reported. (orig.).

  9. Influence of gate width on gate-channel carrier mobility in AlGaN/GaN heterostructure field-effect transistors

    Science.gov (United States)

    Yang, Ming; Ji, Qizheng; Gao, Zhiliang; Zhang, Shufeng; Lin, Zhaojun; Yuan, Yafei; Song, Bo; Mei, Gaofeng; Lu, Ziwei; He, Jihao

    2017-11-01

    For the fabricated AlGaN/GaN heterostructure field-effect transistors (HFETs) with different gate widths, the gate-channel carrier mobility is experimentally obtained from the measured current-voltage and capacitance-voltage curves. Under each gate voltage, the mobility gets lower with gate width increasing. Analysis shows that the phenomenon results from the polarization Coulomb field (PCF) scattering, which originates from the irregularly distributed polarization charges at the AlGaN/GaN interface. The device with a larger gate width is with a larger PCF scattering potential and a stronger PCF scattering intensity. As a function of gate width, PCF scattering potential shows a same trend with the mobility variation. And the theoretically calculated mobility values fits well with the experimentally obtained values. Varying gate widths will be a new perspective for the improvement of device characteristics by modulating the gate-channel carrier mobility.

  10. Stable Low-Voltage Operation Top-Gate Organic Field-Effect Transistors on Cellulose Nanocrystal Substrates

    Science.gov (United States)

    Cheng-Yin Wang; Canek Fuentes-Hernandez; Jen-Chieh Liu; Amir Dindar; Sangmoo Choi; Jeffrey P. Youngblood; Robert J. Moon; Bernard Kippelen

    2015-01-01

    We report on the performance and the characterization of top-gate organic field-effect transistors (OFETs), comprising a bilayer gate dielectric of CYTOP/ Al2O3 and a solution-processed semiconductor layer made of a blend of TIPS-pentacene:PTAA, fabricated on recyclable cellulose nanocrystal−glycerol (CNC/glycerol...

  11. Trivalued Memory Circuit Using Metal-Oxide-Semiconductor Field-Effect Transistor Bipolar-Junction-Transistor Negative-Differential-Resistance Circuits Fabricated by Standard SiGe Process

    Science.gov (United States)

    Gan, Kwang-Jow; Tsai, Cher-Shiung; Liang, Dong-Shong; Wen, Chun-Ming; Chen, Yaw-Hwang

    2006-09-01

    A trivalued memory circuit based on two cascoded metal-oxide-semiconductor field-effect transistor bipolar-junction-transistor negative-differential-resistance (MOS-BJT-NDR) devices is investigated. The MOS-BJT-NDR device is made of MOS and BJT devices, but it can show the NDR current-voltage characteristic by suitably arranging the MOS parameters. We demonstrate a trivalued memory circuit using the two-peak MOS-BJT-NDR circuit as the driver and a resistor as the load. The MOS-BJT-NDR devices and memory circuits are fabricated by the standard 0.35 μm SiGe process.

  12. Ultra Low Voltage Class AB Switched Current Memory Cells Based on Floating Gate Transistors

    DEFF Research Database (Denmark)

    Mucha, Igor

    1999-01-01

    A proposal for a class AB switched current memory cell, suitable for ultra-low-voltage applications is presented. The proposal employs transistors with floating gates, allowing to build analog building blocks for ultralow supply voltage operation also in CMOS processes with high threshold voltages....... This paper presents the theoretical basis for the design of "floating-gate'' switched current memory cells by giving a detailed description and analysis of the most important impacts degrading the performance of the cells. To support the theoretical assumptions circuits based on "floating-gate'' switched...... current memory cells were designed using a CMOS process with threshold voltages V-T0n = \\V-T0p\\ = 0.9 V for the n- and p-channel devices. Both hand calculations and PSPICE simulations showed that the designed example switched current memory cell allowed a maximum signal range better than +/-18 mu...

  13. Oxide-based synaptic transistors gated by solution-processed gelatin electrolytes

    Science.gov (United States)

    He, Yinke; Sun, Jia; Qian, Chuan; Kong, Ling-An; Gou, Guangyang; Li, Hongjian

    2017-04-01

    In human brain, a large number of neurons are connected via synapses. Simulation of the synaptic behaviors using electronic devices is the most important step for neuromorphic systems. In this paper, proton conducting gelatin electrolyte-gated oxide field-effect transistors (FETs) were used for emulating synaptic functions, in which the gate electrode is regarded as pre-synaptic neuron and the channel layer as the post-synaptic neuron. In analogy to the biological synapse, a potential spike can be applied at the gate electrode and trigger ionic motion in the gelatin electrolyte, which in turn generates excitatory post-synaptic current (EPSC) in the channel layer. Basic synaptic behaviors including spike time-dependent EPSC, paired-pulse facilitation (PPF), self-adaptation, and frequency-dependent synaptic transmission were successfully mimicked. Such ionic/electronic hybrid devices are beneficial for synaptic electronics and brain-inspired neuromorphic systems.

  14. Insights into operation of planar tri-gate tunnel field effect transistor for dynamic memory application

    Science.gov (United States)

    Navlakha, Nupur; Kranti, Abhinav

    2017-07-01

    Insights into device physics and operation through the control of energy barriers are presented for a planar tri-gate Tunnel Field Effect Transistor (TFET) based dynamic memory. The architecture consists of a double gate (G1) at the source side and a single gate (G2) at the drain end of the silicon film. Dual gates (G1) effectively enhance the tunneling based read mechanism through the enhanced coupling and improved electrostatic control over the channel. The single gate (G2) controls the holes in the potential barrier induced through the proper selection of bias and workfunction. The results indicate that the planar tri-gate achieves optimum performance evaluated in terms of two composite metrics (M1 and M2), namely, product of (i) Sense Margin (SM) and Retention Time (RT) i.e., M1 = SM × RT and (ii) Sense Margin and Current Ratio (CR) i.e., M2 = SM × CR. The regulation of barriers created by the gates (G1 and G2) through the optimal use of device parameters leads to better performance metrics, with significant improvement at scaled lengths as compared to other tunneling based dynamic memory architectures. The investigation shows that lengths of G1, G2 and lateral spacing can be scaled down to 25 nm, 50 nm, and 30 nm, respectively, while achieving reasonable values for (M1, M2). The work demonstrates a systematic approach to showcase the advancement in TFET based Dynamic Random Access Memory (DRAM) through the use of planar tri-gate topology at a lower bias value. The concept, design, and operation of planar tri-gate architecture provide valuable viewpoints for TFET based DRAM.

  15. Polysilsesquioxanes for Gate-Insulating Materials of Organic Thin-Film Transistors

    Directory of Open Access Journals (Sweden)

    Kimihiro Matsukawa

    2012-01-01

    Full Text Available Printable organic thin-film transistor (O-TFT is one of the most recognized technical issues nowadays. Our recent progress on the formation of organic-inorganic hybrid thin films consists of polymethylsilsesquioxane (PMSQ, and its applications for the gate-insulating layer of O-TFTs are introduced in this paper. PMSQ synthesized in toluene solution with formic acid catalyst exhibited the electric resistivity of higher than 1014 Ω cm after thermal treatment at 150°C, and the very low concentration of residual silanol groups in PMSQ was confirmed. The PMSQ film contains no mobile ionic impurities, and this is also important property for the practical use for the gate-insulating materials. In the case of top-contact type TFT using poly(3-hexylthiophene (P3HT with PMSQ gate-insulating layer, the device properties were comparable with the TFTs having thermally grown SiO2 gate-insulating layer. The feasibility of PMSQ as a gate-insulating material for O-TFTs, which was fabricated on a flexible plastic substrate, has been demonstrated. Moreover, by the modification of PMSQ, further functionalities, such as surface hydrophobicity, high permittivity that allows low driving voltage, and photocurability that allows photolithography, could be appended to the PMSQ gate-insulating layers.

  16. Technique for electronic measurement of semi-reduction layer using bipolar transistor of junction; Tecnica de medicao eletronica da camada semiredutora utilizando transistor bipolar de juncao

    Energy Technology Data Exchange (ETDEWEB)

    Santos, Luiz A.P.; Barros, Fabio R.; Santos, Marcus A.P., E-mail: lasantos@cnen.gov.br [Centro Regional de Ciencias Nucleares do Nordeste (CRCN-NE/CNEN-PE), Recife, PE (Brazil); Monte, David S.; Santos, Jose A.P., E-mail: dsmonte@scients.com.br [SCIENTS, Recife, PE (Brazil)

    2014-07-01

    Recommendations of the International Commission on Radiological Protection (ICRP), the World Health Organization (WHO) and also of the International Atomic Energy Agency (IAEA) suggest equipment for X-rays diagnosis are checked for conformance to their parameters, such as Layer Semi-Reduction (CSR). The importance of verification of diagnostic radiology in parameters is because of have records that forces patients undergoing radiation doses in some clinics, up to 300% the reference values suggested by international agencies which doses are considered unnecessary, and even harmful, either because of physical or variable greatness of being out of control nominal specification, or the fact of having to repeat the radiographs. In this context, the purpose of this study was an innovative methodology that is the use of bipolar transistor junction (TBJ) to measure the aluminum CSR in diagnostic X-ray equipment beams. Although the TBJ be a device invented in the last century, only in recent years have explored their potential as X-ray sensor applied to diagnosis. The study indicates that the tested device can operating the detection of X-rays is properly polarized with electrical signals that can detect interference of the interaction of X-ray photons with the PN junction formed by the base and emitter terminals. The result of the developed technique was compared to CSR measurements obtained with detection systems standards and it was found that the BJT provides values for aluminum CSR relative errors less than 5%.

  17. Transcap: A new integrated hybrid supercapacitor and electrolyte-gated transistor device (Presentation Recording)

    Science.gov (United States)

    Santato, Clara

    2015-10-01

    The boom in multifunctional, flexible, and portable electronics and the increasing need of low-energy cost and autonomy for applications ranging from wireless sensor networks for smart environments to biomedical applications are triggering research efforts towards the development of self-powered sustainable electronic devices. Within this context, the coupling of electronic devices (e.g. sensors, transistors) with small size energy storage systems (e.g. micro-batteries or micro-supercapacitors) is actively pursued. Micro-electrochemical supercapacitors are attracting much attention in electronics for their capability of delivering short power pulses with high stability over repeated charge/discharge cycling. For their high specific pseudocapacitance, electronically conducting polymers are well known as positive materials for hybrid supercapacitors featuring high surface carbon negative electrodes. The processability of both polymer and carbon is of great relevance for the development of flexible miniaturised devices. Electronically conducting polymers are even well known to feature an electronic conductivity that depends on their oxidation (p-doped state) and that it is modulated by the polymer potential. This property and the related pseudocapacitive response make polymer very attracting channel materials for electrolyte-gated (EG) transistors. Here, we propose a novel concept of "Trans-capacitor", an integrated device that exhibits the storage properties of a polymer/carbon hybrid supercapacitor and the low-voltage operation of an electrolyte-gated transistor.

  18. Air-gating and chemical-gating in transistors and sensing devices made from hollow TiO2 semiconductor nanotubes

    Science.gov (United States)

    Alivov, Yahya; Funke, Hans; Nagpal, Prashant

    2015-07-01

    Rapid miniaturization of electronic devices down to the nanoscale, according to Moore’s law, has led to some undesirable effects like high leakage current in transistors, which can offset additional benefits from scaling down. Development of three-dimensional transistors, by spatial extension in the third dimension, has allowed higher contact area with a gate electrode and better control over conductivity in the semiconductor channel. However, these devices do not utilize the large surface area and interfaces for new electronic functionality. Here, we demonstrate air gating and chemical gating in hollow semiconductor nanotube devices and highlight the potential for development of novel transistors that can be modulated using channel bias, gate voltage, chemical composition, and concentration. Using chemical gating, we reversibly altered the conductivity of nanoscaled semiconductor nanotubes (10-500 nm TiO2 nanotubes) by six orders of magnitude, with a tunable rectification factor (ON/OFF ratio) ranging from 1-106. While demonstrated air- and chemical-gating speeds were slow here (˜seconds) due to the mechanical-evacuation rate and size of our chamber, the small nanoscale volume of these hollow semiconductors can enable much higher switching speeds, limited by the rate of adsorption/desorption of molecules at semiconductor interfaces. These chemical-gating effects are completely reversible, additive between different chemical compositions, and can enable semiconductor nanoelectronic devices for ‘chemical transistors’, ‘chemical diodes’, and very high-efficiency sensing applications.

  19. High-Gain Graphene Transistors with a Thin AlOx Top-Gate Oxide.

    Science.gov (United States)

    Guerriero, Erica; Pedrinazzi, Paolo; Mansouri, Aida; Habibpour, Omid; Winters, Michael; Rorsman, Niklas; Behnam, Ashkan; Carrion, Enrique A; Pesquera, Amaia; Centeno, Alba; Zurutuza, Amaia; Pop, Eric; Zirath, Herbert; Sordan, Roman

    2017-05-25

    The high-frequency performance of transistors is usually assessed by speed and gain figures of merit, such as the maximum oscillation frequency f max , cutoff frequency f T , ratio f max /f T , forward transmission coefficient S 21 , and open-circuit voltage gain A v . All these figures of merit must be as large as possible for transistors to be useful in practical electronics applications. Here we demonstrate high-performance graphene field-effect transistors (GFETs) with a thin AlOx gate dielectric which outperform previous state-of-the-art GFETs: we obtained f max /f T  > 3, A v  > 30 dB, and S 21  = 12.5 dB (at 10 MHz and depending on the transistor geometry) from S-parameter measurements. A dc characterization of GFETs in ambient conditions reveals good current saturation and relatively large transconductance ~600 S/m. The realized GFETs offer the prospect of using graphene in a much wider range of electronic applications which require substantial gain.

  20. Touch sensors based on planar liquid crystal-gated-organic field-effect transistors

    International Nuclear Information System (INIS)

    Seo, Jooyeok; Lee, Chulyeon; Han, Hyemi; Lee, Sooyong; Nam, Sungho; Kim, Youngkyoo; Kim, Hwajeong; Lee, Joon-Hyung; Park, Soo-Young; Kang, Inn-Kyu

    2014-01-01

    We report a tactile touch sensor based on a planar liquid crystal-gated-organic field-effect transistor (LC-g-OFET) structure. The LC-g-OFET touch sensors were fabricated by forming the 10 μm thick LC layer (4-cyano-4 ′ -pentylbiphenyl - 5CB) on top of the 50 nm thick channel layer (poly(3-hexylthiophene) - P3HT) that is coated on the in-plane aligned drain/source/gate electrodes (indium-tin oxide - ITO). As an external physical stimulation to examine the tactile touch performance, a weak nitrogen flow (83.3 μl/s) was employed to stimulate the LC layer of the touch device. The LC-g-OFET device exhibited p-type transistor characteristics with a hole mobility of 1.5 cm 2 /Vs, but no sensing current by the nitrogen flow touch was measured at sufficiently high drain (V D ) and gate (V G ) voltages. However, a clear sensing current signal was detected at lower voltages, which was quite sensitive to the combination of V D and V G . The best voltage combination was V D = −0.2 V and V G = −1 V for the highest ratio of signal currents to base currents (i.e., signal-to-noise ratio). The change in the LC alignment upon the nitrogen flow touch was assigned as the mechanism for the present LC-g-OFET touch sensors

  1. Electro-spun PEDOT-PSS nano-ribbon transistor using ion-gel gate dielectric

    Science.gov (United States)

    Ortiz, Deliris N.; Pinto, Nicholas J.

    Poly(3,4-ethylenedioxythiophene) doped with poly(styrenesulfonic acid)-PEDOT:PSS is a p-doped conducting polymer. Using the electrospinning technique, we have fabricated nano-ribbons of this polymer and deposited them on pre-patterned doped Si/SiO2 wafers. Using the doped Si substrate as the back gate electrode and the SiO2 as the dielectric insulator, the ribbon was characterized in a 3-terminal transistor configuration. No change in the channel current was observed for back gate bias under these conditions. We also used an ion-gel gate dielectric by placing a drop of the ion-gel over the ribbon and inserting a Au wire into the drop. By applying a bias to this contact (top gate), we were able to modulate the current through the ribbon at low voltages. The device operated like a field effect/electrochemical transistor, characteristic of a p-doped semiconductor with an on/off ratio of 350, threshold voltage of 0.7V, mobility of 5 cm2/V-s, and a zero gate bias conductivity of 15 S/cm. The large specific capacitance of the ion-gel (as compared to SiO2) and the formation of an electric double layer at the semiconductor/ion-gel interface was responsible for its operation below 2V. The device was also successfully tested at 100Hz making it useful in low frequency applications. NSF-DMR: RUI 1360772; PREM-1523463.

  2. Using white noise to gate organic transistors for dynamic monitoring of cultured cell layers.

    Science.gov (United States)

    Rivnay, Jonathan; Leleux, Pierre; Hama, Adel; Ramuz, Marc; Huerta, Miriam; Malliaras, George G; Owens, Roisin M

    2015-06-26

    Impedance sensing of biological systems allows for monitoring of cell and tissue properties, including cell-substrate attachment, layer confluence, and the "tightness" of an epithelial tissue. These properties are critical for electrical detection of tissue health and viability in applications such as toxicological screening. Organic transistors based on conducting polymers offer a promising route to efficiently transduce ionic currents to attain high quality impedance spectra, but collection of complete impedance spectra can be time consuming (minutes). By applying uniform white noise at the gate of an organic electrochemical transistor (OECT), and measuring the resulting current noise, we are able to dynamically monitor the impedance and thus integrity of cultured epithelial monolayers. We show that noise sourcing can be used to track rapid monolayer disruption due to compounds which interfere with dynamic polymerization events crucial for maintaining cytoskeletal integrity, and to resolve sub-second alterations to the monolayer integrity.

  3. Contribution to the study of fluctuations in transistors (bipolar and junction field effect types)

    International Nuclear Information System (INIS)

    Borel, J.

    1970-01-01

    A brief review of the basic theory of fluctuations in semiconductors is given: shot, thermal low frequency noise. A measuring set has been built to draw noise spectrums (current or voltage). Noise parameters of bipolar transistors are given, mainly noise voltage. Noise current, noise factor and correlation between noise sources are also calculated. Measurements of noise parameters fit well with theory for various devices made in different technologies: alloyed, mesa, planar. Then we give results of the calculation of noise parameters in a FET starting from a simplified model of the device. Low frequency noise is taken into account. Measurements of the parameters and of the spectrum agree fairly well with the theory. Studies of low frequency noise versus temperature give the density and energy of traps located in the space charge layers and an idea of the impurity encountered in these space charge layers [fr

  4. Microwave characterization and modeling of GaAs/AlGaAs heterojunction bipolar transistors

    Science.gov (United States)

    Simons, Rainee N.; Romanofsky, Robert R.

    1987-01-01

    The characterization and modeling of a microwave GaAs/AlGaAs heterojunction Bipolar Transistor (HBT) are discussed. The de-embedded scattering parameters are used to derive a small signal lumped element equivalent circuit model using EEsof's Touchstone software package. Each element in the equivalent circuit model is shown to have its origin within the device. The model shows good agreement between the measured and modeled scattering parameters over a wide range of bias currents. Further, the MAG (maximum available power gain) and the h sub 21 (current gain) calculated from the measured data and those predicted by the model are also in good agreement. Consequently, the model should also be capable of predicting the f sub max and the f sub T of other HBTs.

  5. Analysis of long-term ionizing radiation effects in bipolar transistors

    Science.gov (United States)

    Stanley, A. G.; Martin, K. E.

    1978-01-01

    The ionizing radiation effects of electrons on bipolar transistors have been analyzed using the data base from the Voyager project. The data were subjected to statistical analysis, leading to a quantitative characterization of the product and to data on confidence limits which will be useful for circuit design purposes. These newly-developed methods may form the basis for a radiation hardness assurance system. In addition, an attempt was made to identify the causes of the large variations in the sensitivity observed on different product lines. This included a limited construction analysis and a determination of significant design and processes variables, as well as suggested remedies for improving the tolerance of the devices to radiation.

  6. A CMOS-MEMS arrayed resonant-gate field effect transistor (RGFET) oscillator

    Science.gov (United States)

    Chin, Chi-Hang; Li, Ming-Huang; Chen, Chao-Yu; Wang, Yu-Lin; Li, Sheng-Shian

    2015-11-01

    A high-frequency CMOS-MEMS arrayed resonant-gate field effect transistor (RGFET) fabricated by a standard 0.35 μm 2-poly-4-metal CMOS-MEMS platform is implemented to enable a Pierce-type oscillator. The proposed arrayed RGFET exhibits low motional impedance of only 5 kΩ under a purely capacitive transduction and decent power handling capability. With such features, the implemented oscillator shows impressive phase noise of  -117 dBc Hz-1 at the far-from-carrier offset (1 MHz). In this work, we design a clamped-clamped beam (CCB) arrayed resonator utilizing a high-velocity mechanical coupling scheme to serve as the resonant-gate array. To achieve a functional arrayed RGFET, a corresponding FET array is directly placed underneath the resonant gate array to convert the motional current on the resonant-gate array into a voltage output with a tunable transconductance gain. To understand the behavior of the proposed device, an equivalent circuit model consisting of the resonant unit and FET is also provided. To verify the effects of the post-CMOS process on device performance, a conventional MOS I D current measurement is carried out. Finally, a CMOS-MEMS arrayed RGFET oscillator is realized by utilizing a Pierce oscillator architecture, showing decent phase noise performance that benefits from the array design to alleviate the nonlinear effect of the resonant gate.

  7. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    International Nuclear Information System (INIS)

    Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

    2014-01-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

  8. A pentacene thin film transistor with good performance using sol-gel derived SiO2 gate dielectric layer

    Science.gov (United States)

    Cavas, M.; Al-Ghamdi, Ahmed A.; Al-Hartomy, O. A.; El-Tantawy, F.; Yakuphanoglu, F.

    2013-02-01

    A low-voltage pentacene field-effect transistor with sol-gel derived SiO2 gate dielectric was fabricated. The mobility of the transistor was achieved as high as 1.526 cm2/V on the bared SiO2/Si substrate by a higher dielectric constant. The interface state density for the transistor was found to vary from 3.8 × 1010 to 7.5 × 1010 eV-1 cm-2 at frequency range of 100 kHz-1 MHz. It is evaluated that the SiO2 derived by low cost sol-gel is quite a promising candidate as a gate dielectric layer for low-voltage pentacene field-effect transistor.

  9. Incident particle range dependence of radiation damage in a power bipolar junction transistor

    Science.gov (United States)

    Liu, Chao-Ming; Li, Xing-Ji; Geng, Hong-Bin; Rui, Er-Ming; Guo, Li-Xin; Yang, Jian-Qun

    2012-10-01

    The characteristic degradations in silicon NPN bipolar junction transistors (BJTs) of type 3DD155 are examined under the irradiations of 25-MeV carbon (C), 40-MeV silicon (Si), and 40-MeV chlorine (Cl) ions respectively. Different electrical parameters are measured in-situ during the exposure of heavy ions. The experimental data shows that the changes in the reciprocal of the gain variation (Δ(1/β)) of 3DD155 transistors irradiated respectively by 25-MeV C, 40-MeV Si, and 40-MeV Cl ions each present a nonlinear behaviour at a low fluence and a linear response at a high fluence. The Δ(1/β) of 3DD155 BJT irradiated by 25-MeV C ions is greatest at a given fluence, a little smaller when the device is irradiated by 40-MeV Si ions, and smallest in the case of the 40-MeV Cl ions irradiation. The measured and calculated results clearly show that the range of heavy ions in the base region of BJT affects the level of radiation damage.

  10. Annealing effects and DLTS study on NPN silicon bipolar junction transistors irradiated by heavy ions

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Chaoming; Li, Xingji, E-mail: lxj0218@hit.edu.cn; Yang, Jianqun; Rui, Erming

    2014-01-21

    Isochronal anneal sequences have been carried out on 3DG112 silicon NPN bipolar junction transistors (BJTs) irradiated with 20 MeV bromine (Br) heavy ions. The Gummel curve is utilized to characterize the annealing behavior of defects in both the emitter-base depletion region and the neutral base. We find that the base current (I{sub B}) decreases with the increasing annealing temperature, while the collector current (I{sub C}) remains invariable. The current gain varies slightly, when the annealing temperature (T{sub A}) is lower than 400 K, while varies rapidly at T{sub A}<450 K, and the current gain of the 3DG112 BJT annealing at 700 K almost restore to that of the pre-radiation transistor. Deep level transient spectroscopy (DLTS) data is used to assign the relative magnitude of each of the important defects. Based on the in situ electrical measurement and DLTS spectra, it is clear that the V{sub 2}(−/0)+V-P traps are the main contribution to the degradation of current gain after the 20 MeV Br ions irradiation. The V{sub 2}(−/0)+V-P peak has many of the characteristics expected for the current gain degradation.

  11. Annealing effects and DLTS study on NPN silicon bipolar junction transistors irradiated by heavy ions

    Science.gov (United States)

    Liu, Chaoming; Li, Xingji; Yang, Jianqun; Rui, Erming

    2014-01-01

    Isochronal anneal sequences have been carried out on 3DG112 silicon NPN bipolar junction transistors (BJTs) irradiated with 20 MeV bromine (Br) heavy ions. The Gummel curve is utilized to characterize the annealing behavior of defects in both the emitter-base depletion region and the neutral base. We find that the base current (IB) decreases with the increasing annealing temperature, while the collector current (IC) remains invariable. The current gain varies slightly, when the annealing temperature (TA) is lower than 400 K, while varies rapidly at TABJT annealing at 700 K almost restore to that of the pre-radiation transistor. Deep level transient spectroscopy (DLTS) data is used to assign the relative magnitude of each of the important defects. Based on the in situ electrical measurement and DLTS spectra, it is clear that the V2(-/0)+V-P traps are the main contribution to the degradation of current gain after the 20 MeV Br ions irradiation. The V2(-/0)+V-P peak has many of the characteristics expected for the current gain degradation.

  12. Base profile design for high-performance operation of bipolar transistors at liquid-nitrogen temperature

    International Nuclear Information System (INIS)

    Stork, J.M.C.; Harame, D.L.; Meyerson, B.S.; Nguyen, T.N.

    1989-01-01

    The base profile requirements of Si bipolar junction transistors (BJT's) high-performance operation at liquid-nitrogen temperature are examined. Measurements of thin epitaxial-base polysilicon-emitter n-p-n transistors with increasing base doping show the effects of bandgap narrowing, mobility changes, and carrier freezeout. At room temperature the collector current at low injection is proportional to the integrated base charge, independent of the impurity distribution. At temperatures below 150 Κ, however, minority injection is dominated by the peak base doping because of the greater effectiveness of bandgap narrowing. When the peak doping in the base approaches 10 19 cm -3 , the bandgap difference between emitter and base is sufficiently small that the current gain no longer monotonically decreases with lower temperature but instead shows a maximum as low as 180 Κ. The device design window appears limited at the low-current end by increased base-emitter leakage due to tunneling and by resistance control at the high-current end. Using the measured dc characteristics, circuit delay calculations are made to estimate the performance of an ECL ring oscillator at room and liquid-nitrogen temperatures. It is shown that if the base doping can be raised to 10 19 cm -3 while keeping the base thickness constant, the minimum delay at liquid nitrogen can approach the delay of optimized devices at room temperature

  13. Field-effect and capacitive properties of water-gated transistors based on polythiophene derivatives

    Directory of Open Access Journals (Sweden)

    R. Porrazzo

    2015-01-01

    Full Text Available Recently, water-gated organic field-effect transistors (WGOFET have been intensively studied for their application in the biological field. Surprisingly, a very limited number of conjugated polymers have been reported so far. Here, we systematically explore a series of polythiophene derivatives, presenting different alkyl side chains lengths and orientation, and characterized by various morphologies: comparative evaluation of their performances allows highlighting the critical role played by alkyl side chains, which significantly affects the polymer/water interface capacitance. Reported results provide useful guidelines towards further development of WGOFETs and represent a step forward in the understanding of the polymer/water interface phenomena.

  14. An analytic model for gate-all-around silicon nanowire tunneling field effect transistors

    Science.gov (United States)

    Liu, Ying; He, Jin; Chan, Mansun; Du, Cai-Xia; Ye, Yun; Zhao, Wei; Wu, Wen; Deng, Wan-Ling; Wang, Wen-Ping

    2014-09-01

    An analytical model of gate-all-around (GAA) silicon nanowire tunneling field effect transistors (NW-TFETs) is developted based on the surface potential solutions in the channel direction and considering the band to band tunneling (BTBT) efficiency. The three-dimensional Poisson equation is solved to obtain the surface potential distributions in the partition regions along the channel direction for the NW-TFET, and a tunneling current model using Kane's expression is developed. The validity of the developed model is shown by the good agreement between the model predictions and the TCAD simulation results.

  15. Ultra-low power thin film transistors with gate oxide formed by nitric acid oxidation method

    International Nuclear Information System (INIS)

    Kobayashi, H.; Kim, W. B.; Matsumoto, T.

    2011-01-01

    We have developed a low temperature fabrication method of SiO 2 /Si structure by use of nitric acid, i.e., nitric acid oxidation of Si (NAOS) method, and applied it to thin film transistors (TFT). A silicon dioxide (SiO 2 ) layer formed by the NAOS method at room temperature possesses 1.8 nm thickness, and its leakage current density is as low as that of thermally grown SiO 2 layer with the same thickness formed at ∼900 deg C. The fabricated TFTs possess an ultra-thin NAOS SiO 2 /CVD SiO 2 stack gate dielectric structure. The ultrathin NAOS SiO 2 layer effectively blocks a gate leakage current, and thus, the thickness of the gate oxide layer can be decreased from 80 to 20 nm. The thin gate oxide layer enables to decrease the operation voltage to 2 V (cf. the conventional operation voltage of TFTs with 80 nm gate oxide: 12 V) because of the low threshold voltages, i.e., -0.5 V for P-ch TFTs and 0.5 V for N-ch TFTs, and thus the consumed power decreases to 1/36 of that of the conventional TFTs. The drain current increases rapidly with the gate voltage, and the sub-threshold voltage is ∼80 mV/dec. The low sub-threshold swing is attributable to the thin gate oxide thickness and low interface state density of the NAOS SiO 2 layer. (authors)

  16. Improving pH sensitivity by field-induced charge regulation in flexible biopolymer electrolyte gated oxide transistors

    Science.gov (United States)

    Liu, Ning; Gan, Lu; Liu, Yu; Gui, Weijun; Li, Wei; Zhang, Xiaohang

    2017-10-01

    Electrical manipulation of charged ions in electrolyte-gated transistors is crucial for enhancing the electric-double-layer (EDL) gating effect, thereby improving their sensing abilities. Here, indium-zinc-oxide (IZO) based thin-film-transistors (TFTs) are fabricated on flexible plastic substrate. Acid doped chitosan-based biopolymer electrolyte is used as the gate dielectric, exhibiting an extremely high EDL capacitance. By regulating the dynamic EDL charging process with special gate potential profiles, the EDL gating effect of the chitosan-gated TFT is enhanced, and then resulting in higher pH sensitivities. An extremely high sensitivity of ∼57.8 mV/pH close to Nernst limit is achieved when the gate bias of the TFT sensor sweeps at a rate of 10 mV/s. Additionally, an enhanced sensitivity of 2630% in terms of current variation with pH range from 11 to 3 is realized when the device is operated in the ion depletion mode with a negative gate bias of -0.7 V. Robust ionic modulation is demonstrated in such chitosan-gated sensors. Efficiently driving the charged ions in the chitosan-gated IZO-TFT provides a new route for ultrasensitive, low voltage, and low-cost biochemical sensing technologies.

  17. Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

    OpenAIRE

    Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

    2014-01-01

    Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. ...

  18. Gate controlled magnetoresistance in a silicon metal-oxide-semiconductor field-effect-transistor

    Science.gov (United States)

    Ciccarelli, C.; Park, B. G.; Ogawa, S.; Ferguson, A. J.; Wunderlich, J.

    2010-08-01

    We present a study of the magnetoresistance (MR) of a Si metal-oxide-semiconductor field-effect-transistor (MOSFET) at the break-down regime when a magnetic field is applied perpendicular to the plane of the device. We have identified two different regimes where we observe a large and gate-voltage dependent MR. We suggest two different mechanisms which can explain the observed high MR. Moreover, we have studied how the MR of the MOSFET scales with the dimensions of the channel for gate voltages below the threshold. We observed a decrease in the MR by two orders of magnitude by reducing the dimensions of the channel from 50×280 μm2 to 5×5 μm2.

  19. Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation

    Science.gov (United States)

    Seema; Chauhan, Sudakar Singh

    2018-05-01

    In this paper, we demonstrate the double gate vertical tunnel field-effect transistor using homo/hetero dielectric buried oxide (HDB) to obtain the optimized device characteristics. In this concern, the existence of double gate, HDB and electrode work-function engineering enhances DC performance and Analog/RF performance. The use of electrostatic doping helps to achieve higher on-current owing to occurrence of higher tunneling generation rate of charge carriers at the source/epitaxial interface. Further, lightly doped drain region and high- k dielectric below channel and drain region are responsible to suppress the ambipolar current. Simulated results clarifies that proposed device have achieved the tremendous performance in terms of driving current capability, steeper subthreshold slope (SS), drain induced barrier lowering (DIBL), hot carrier effects (HCEs) and high frequency parameters for better device reliability.

  20. Single Event Gate Rupture in 130-nm CMOS Transistor Arrays Subjected to X-Ray Irradiation

    CERN Document Server

    Silvestri, M; Gerardin, Simone; Faccio, Federico; Paccagnella, Alessandro

    2010-01-01

    We present new experimental results on heavy ion-induced gate rupture on deep submicron CMOS transistor arrays. Through the use of dedicated test structures, composed by a large number of 130-nm MOSFETs connected in parallel, we show the response to heavy ion irradiation under high stress voltages of devices previously irradiated with X-rays. We found only a slight impact on gate rupture critical voltage at a LET of 32 MeV cm(2) mg(-1) for devices previously irradiated up to 3 Mrad(SiO2), and practically no change for 100 Mrad(SiO2) irradiation, dose of interest for the future super large hadron collider (SLHC).

  1. Modeling nanowire and double-gate junctionless field-effect transistors

    CERN Document Server

    Jazaeri, Farzan

    2018-01-01

    The first book on the topic, this is a comprehensive introduction to the modeling and design of junctionless field effect transistors (FETs). Beginning with a discussion of the advantages and limitations of the technology, the authors also provide a thorough overview of published analytical models for double-gate and nanowire configurations, before offering a general introduction to the EPFL charge-based model of junctionless FETs. Important features are introduced gradually, including nanowire versus double-gate equivalence, technological design space, junctionless FET performances, short channel effects, transcapacitances, asymmetric operation, thermal noise, interface traps, and the junction FET. Additional features compatible with biosensor applications are also discussed. This is a valuable resource for students and researchers looking to understand more about this new and fast developing field.

  2. Fabrication and characterization of V-gate AlGaN/GaN high-electron-mobility transistors

    International Nuclear Information System (INIS)

    Zhang Kai; Cao Meng-Yi; Chen Yong-He; Yang Li-Yuan; Wang Chong; Ma Xiao-Hua; Hao Yue

    2013-01-01

    V-gate GaN high-electron-mobility transistors (HEMTs) are fabricated and investigated systematically. A V-shaped recess geometry is obtained using an improved Si 3 N 4 recess etching technology. Compared with standard HEMTs, the fabricated V-gate HEMTs exhibit a 17% higher peak extrinsic transconductance due to a narrowed gate foot. Moreover, both the gate leakage and current dispersion are dramatically suppressed simultaneously, although a slight degradation of frequency response is observed. Based on a two-dimensional electric field simulation using Silvaco “ATLAS” for both standard HEMTs and V-gate HEMTs, the relaxation in peak electric field at the gate edge is identified as the predominant factor leading to the superior performance of V-gate HEMTs. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  3. Hybrid top-gate transistors based on ink-jet printed zinc tin oxide and different organic dielectrics

    Science.gov (United States)

    Sykora, Benedikt; von Seggern, Heinz

    2018-01-01

    We report about hybrid top-gate transistors based on ink-jet printed zinc tin oxide (ZTO) and different spin-coated organic dielectrics. Transistors using the polar dielectric poly(methyl methacrylate) (PMMA) and the nonpolar polystyrene (PS) were evaluated. By applying PMMA, we were able to process field-effect transistors with a saturation mobility of up to 4.3 cm2 V-1 s-1. This is the highest reported mobility of an ink-jet printed ZTO top-gate transistor using a spin-coated PMMA dielectric. This transistor also exhibits a small threshold voltage of 1.7 V and an on/off-current ratio exceeding 105. The usage of PS as another organic dielectric leads to functional devices with inferior performance, meaning a saturation mobility of 0.2 cm2 V-1 s-1 and a threshold voltage of 9.7 V. The more polar character of the PMMA compared to the PS dielectric leading to a better adhesion on the quite hydrophilic ZTO surface could explain the improved device performance of the ZTO top-gate transistor using PMMA.

  4. Label-free detection of interleukin-6 using electrolyte gated organic field effect transistors.

    Science.gov (United States)

    Diacci, Chiara; Berto, Marcello; Di Lauro, Michele; Bianchini, Elena; Pinti, Marcello; Simon, Daniel T; Biscarini, Fabio; Bortolotti, Carlo A

    2017-09-27

    Cytokines are small proteins that play fundamental roles in inflammatory processes in the human body. In particular, interleukin (IL)-6 is a multifunctional cytokine, whose increased levels are associated with infection, cancer, and inflammation. The quantification of IL-6 is therefore of primary importance in early stages of inflammation and in chronic diseases, but standard techniques are expensive, time-consuming, and usually rely on fluorescent or radioactive labels. Organic electronic devices and, in particular, organic field-effect transistors (OFETs) have been proposed in the recent years as novel platforms for label-free protein detection, exploiting as sensing unit surface-immobilized antibodies or aptamers. Here, the authors report two electrolyte-gated OFETs biosensors for IL-6 detection, featuring monoclonal antibodies and peptide aptamers adsorbed at the gate. Both strategies yield biosensors that can work on a wide range of IL-6 concentrations and exhibit a remarkable limit of detection of 1 pM. Eventually, electrolyte gated OFETs responses have been used to extract and compare the binding thermodynamics between the sensing moiety, immobilized at the gate electrode, and IL-6.

  5. Nanosecond Time-Resolved Microscopic Gate-Modulation Imaging of Polycrystalline Organic Thin-Film Transistors

    Science.gov (United States)

    Matsuoka, Satoshi; Tsutsumi, Jun'ya; Matsui, Hiroyuki; Kamata, Toshihide; Hasegawa, Tatsuo

    2018-02-01

    We develop a time-resolved microscopic gate-modulation (μ GM ) imaging technique to investigate the temporal evolution of the channel current and accumulated charges in polycrystalline pentacene thin-film transistors (TFTs). A time resolution of as high as 50 ns is achieved by using a fast image-intensifier system that could amplify a series of instantaneous optical microscopic images acquired at various time intervals after the stepped gate bias is switched on. The differential images obtained by subtracting the gate-off image allows us to acquire a series of temporal μ GM images that clearly show the gradual propagation of both channel charges and leaked gate fields within the polycrystalline channel layers. The frontal positions for the propagations of both channel charges and leaked gate fields coincide at all the time intervals, demonstrating that the layered gate dielectric capacitors are successively transversely charged up along the direction of current propagation. The initial μ GM images also indicate that the electric field effect is originally concentrated around a limited area with a width of a few micrometers bordering the channel-electrode interface, and that the field intensity reaches a maximum after 200 ns and then decays. The time required for charge propagation over the whole channel region with a length of 100 μ m is estimated at about 900 ns, which is consistent with the measured field-effect mobility and the temporal-response model for organic TFTs. The effect of grain boundaries can be also visualized by comparison of the μ GM images for the transient and the steady states, which confirms that the potential barriers at the grain boundaries cause the transient shift in the accumulated charges or the transient accumulation of additional charges around the grain boundaries.

  6. Long-Term Reliability of High Speed SiGe/Si Heterojunction Bipolar Transistors

    Science.gov (United States)

    Ponchak, George E. (Technical Monitor); Bhattacharya, Pallab

    2003-01-01

    Accelerated lifetime tests were performed on double-mesa structure Si/Si0.7Ge0.3/Si npn heterojunction bipolar transistors, grown by molecular beam epitaxy, in the temperature range of 175C-275C. Both single- and multiple finger transistors were tested. The single-finger transistors (with 5x20 micron sq m emitter area) have DC current gains approximately 40-50 and f(sub T) and f(sub MAX) of up to 22 GHz and 25 GHz, respectively. The multiple finger transistors (1.4 micron finger width, 9 emitter fingers with total emitter area of 403 micron sq m) have similar DC current gain but f(sub T) of 50 GHz. It is found that a gradual degradation in these devices is caused by the recombination enhanced impurity diffusion (REID) of boron atoms from the p-type base region and the associated formation of parasitic energy barriers to electron transport from the emitter to collector layers. This REID has been quantitatively modeled and explained, to the first order of approximation, and the agreement with the measured data is good. The mean time to failure (MTTF) of the devices at room temperature is estimated from the extrapolation of the Arrhenius plots of device lifetime versus reciprocal temperature. The results of the reliability tests offer valuable feedback for SiGe heterostructure design in order to improve the long-term reliability of the devices and circuits made with them. Hot electron induced degradation of the base-emitter junction was also observed during the accelerated lifetime testing. In order to improve the HBT reliability endangered by the hot electrons, deuterium sintered techniques have been proposed. The preliminary results from this study show that a deuterium-sintered HBT is, indeed, more resistant to hot-electron induced base-emitter junction degradation. SiGe/Si based amplifier circuits were also subjected to lifetime testing and we extrapolate MTTF is approximately 1.1_10(exp 6) hours at 125iC junction temperature from the circuit lifetime data.

  7. Unipolar and bipolar operation of InAs/InSb nanowire heterostructure field-effect transistors

    Science.gov (United States)

    Nilsson, Henrik A.; Caroff, Philippe; Lind, Erik; Pistol, Mats-Erik; Thelander, Claes; Wernersson, Lars-Erik

    2011-09-01

    We present temperature dependent electrical measurements on n-type InAs/InSb nanowire heterostructure field-effect transistors. The barrier height of the heterostructure junction is determined to be 220 meV, indicating a broken bandgap alignment. A clear asymmetry is observed when applying a bias to either the InAs or the InSb side of the junction. Impact ionization and band-to-band tunneling is more pronounced when the large voltage drop occurs in the narrow bandgap InSb segment. For small negative gate-voltages, the InSb segment can be tuned toward p-type conduction, which induces a strong band-to-band tunneling across the heterostructucture junction.

  8. Gate-Sensing Coherent Charge Oscillations in a Silicon Field-Effect Transistor.

    Science.gov (United States)

    Gonzalez-Zalba, M Fernando; Shevchenko, Sergey N; Barraud, Sylvain; Johansson, J Robert; Ferguson, Andrew J; Nori, Franco; Betz, Andreas C

    2016-03-09

    Quantum mechanical effects induced by the miniaturization of complementary metal-oxide-semiconductor (CMOS) technology hamper the performance and scalability prospects of field-effect transistors. However, those quantum effects, such as tunneling and coherence, can be harnessed to use existing CMOS technology for quantum information processing. Here, we report the observation of coherent charge oscillations in a double quantum dot formed in a silicon nanowire transistor detected via its dispersive interaction with a radio frequency resonant circuit coupled via the gate. Differential capacitance changes at the interdot charge transitions allow us to monitor the state of the system in the strong-driving regime where we observe the emergence of Landau-Zener-Stückelberg-Majorana interference on the phase response of the resonator. A theoretical analysis of the dispersive signal demonstrates that quantum and tunneling capacitance changes must be included to describe the qubit-resonator interaction. Furthermore, a Fourier analysis of the interference pattern reveals a charge coherence time, T2 ≈ 100 ps. Our results demonstrate charge coherent control and readout in a simple silicon transistor and open up the possibility to implement charge and spin qubits in existing CMOS technology.

  9. Artificial Synapses Based on in-Plane Gate Organic Electrochemical Transistors.

    Science.gov (United States)

    Qian, Chuan; Sun, Jia; Kong, Ling-An; Gou, Guangyang; Yang, Junliang; He, Jun; Gao, Yongli; Wan, Qing

    2016-10-05

    Realization of biological synapses using electronic devices is regarded as the basic building blocks for neuromorphic engineering and artificial neural network. With the advantages of biocompatibility, low cost, flexibility, and compatible with printing and roll-to-roll processes, the artificial synapse based on organic transistor is of great interest. In this paper, the artificial synapse simulation by ion-gel gated organic field-effect transistors (FETs) with poly(3-hexylthiophene) (P3HT) active channel is demonstrated. Key features of the synaptic behaviors, such as paired-pulse facilitation (PPF), short-term plasticity (STP), self-tuning, the spike logic operation, spatiotemporal dentritic integration, and modulation are successfully mimicked. Furthermore, the interface doping processes of electrolyte ions between the active P3HT layer and ion gels is comprehensively studied for confirming the operating processes underlying the conductivity and excitatory postsynaptic current (EPSC) variations in the organic synaptic devices. This study represents an important step toward building future artificial neuromorphic systems with newly emerged ion gel gated organic synaptic devices.

  10. Double-gate junctionless transistor model including short-channel effects

    International Nuclear Information System (INIS)

    Paz, B C; Pavanello, M A; Ávila-Herrera, F; Cerdeira, A

    2015-01-01

    This work presents a physically based model for double-gate junctionless transistors (JLTs), continuous in all operation regimes. To describe short-channel transistors, short-channel effects (SCEs), such as increase of the channel potential due to drain bias, carrier velocity saturation and mobility degradation due to vertical and longitudinal electric fields, are included in a previous model developed for long-channel double-gate JLTs. To validate the model, an analysis is made by using three-dimensional numerical simulations performed in a Sentaurus Device Simulator from Synopsys. Different doping concentrations, channel widths and channel lengths are considered in this work. Besides that, the series resistance influence is numerically included and validated for a wide range of source and drain extensions. In order to check if the SCEs are appropriately described, besides drain current, transconductance and output conductance characteristics, the following parameters are analyzed to demonstrate the good agreement between model and simulation and the SCEs occurrence in this technology: threshold voltage (V TH ), subthreshold slope (S) and drain induced barrier lowering. (paper)

  11. Contact Metallization and Packaging Technology Development for SiC Bipolar Junction Transistors, PiN Diodes, and Schottky Diodes Designed for Long-Term Operations at 350degreeC

    Science.gov (United States)

    2006-05-01

    for high temperature contacts. A Bipolar Junction Transistor ( BJT ) in 4H-SiC can operate at higher temperatures (300oC) because its operation does not...AFRL-PR-WP-TR-2006-2181 CONTACT METALLIZATION AND PACKAGING TECHNOLOGY DEVELOPMENT FOR SiC BIPOLAR JUNCTION TRANSISTORS , PiN DIODES, AND...SUBTITLE CONTACT METALLIZATION AND PACKAGING TECHNOLOGY DEVELOPMENT FOR SiC BIPOLAR JUNCTION TRANSISTORS , PiN DIODES, AND SCHOTTKY DIODES DESIGNED

  12. Effect of temperature on the performance of a bipolar transistor carrier-injected optical waveguide modulator/switch.

    Science.gov (United States)

    Okada, Y

    1991-05-15

    The effect of ambient temperature on the performance of a GaAs/AlGaAs heterojunction bipolar transistor waveguide structure carrier-injected optical intensity modulator/switch is discussed. An increase in the temperature increases the achievable optical modulation ratio at the expense of increased absorption loss, and vice versa. Analysis also shows that for practical use a tolerable temperature change should be no more than approximately 10 degrees C.

  13. Emotional processing, p50 sensory gating, and social functioning in bipolar disorder.

    Science.gov (United States)

    Vuillier, Laura; Hermens, Daniel F; Chitty, Kate; Wang, Chenyu; Kaur, Manreena; Ward, Philip B; Degabriele, Rachael; Hickie, Ian B; Lagopoulos, Jim

    2015-04-01

    Emotional processing has been reported to effect sensory gating as measured by the event-related potential known as P50. Because both P50 and emotional processing are dysfunctional in bipolar disorder (BD), we sought to investigate the impact that concurrent emotional processing has on sensory gating in this psychiatric population. P50 was recorded using a paired-click paradigm. Peak-to-peak amplitudes for stimulus 1 (S1) and stimulus 2 (S2) were acquired during the presentation of disgust and neutral faces to young adults with BD (n = 19) and controls (n = 20). Social functioning and quality-of-life self-reported measures were also obtained. The BD group had significantly larger P50 amplitudes elicited by the S2-disgust response compared with controls, but no significant difference in overall P50 sensory gating was found between the groups. There were also no differences between groups in S1-disgust or in either of the neutral P50 amplitudes. The BD group showed significant associations between sensory gating to disgust and measures of social functioning. Importantly, BD showed impaired filtering of auditory information when paired with an emotionally salient image. Thus, it appears that patients with the greatest impairment in sensory gating also have the most difficulty engaging in social situations. © EEG and Clinical Neuroscience Society (ECNS) 2014.

  14. Highly stable organic field-effect transistors with engineered gate dielectrics (Conference Presentation)

    Science.gov (United States)

    Kippelen, Bernard; Wang, Cheng-Yin; Fuentes-Hernandez, Canek; Yun, Minseong; Singh, Ankit K.; Dindar, Amir; Choi, Sangmoo; Graham, Samuel

    2016-11-01

    Organic field-effect transistors (OFETs) have the potential to lead to low-cost flexible displays, wearable electronics, and sensors. While recent efforts have focused greatly on improving the maximum charge mobility that can be achieved in such devices, studies about the stability and reliability of such high performance devices are relatively scarce. In this talk, we will discuss the results of recent studies aimed at improving the stability of OFETs under operation and their shelf lifetime. In particular, we will focus on device architectures where the gate dielectric is engineered to act simultaneously as an environmental barrier layer. In the past, our group had demonstrated solution-processed top-gate OFETs using TIPS-pentacene and PTAA blends as a semiconductor layer with a bilayer gate dielectric layer of CYTOP/Al2O3, where the oxide layer was fabricated by atomic layer deposition, ALD. Such devices displayed high operational stability with little degradation after 20,000 on/off scan cycles or continuous operation (24 h), and high environmental stability when kept in air for more than 2 years, with unchanged carrier mobility. Using this stable device geometry, simple circuits and sensors operating in aqueous conditions were demonstrated. However, the Al2O3 layer was found to degrade due to corrosion under prolonged exposure in aqueous solutions. In this talk, we will report on the use of a nanolaminate (NL) composed of Al2O3 and HfO2 by ALD to replace the Al2O3 single layer in the bilayer gate dielectric use in top-gate OFETs. Such OFETs were found to operate under harsh condition such as immersion in water at 95 °C. This work was funded by the Department of Energy (DOE) through the Bay Area Photovoltaics Consortium (BAPVC) under Award Number DE-EE0004946.

  15. Formation of a Stable p-n Junction in a Liquid-Gated MoS2 Ambipolar Transistor

    NARCIS (Netherlands)

    Zhang, Y. J.; Ye, J. T.; Yornogida, Y.; Takenobu, T.; Iwasa, Y.

    Molybdenum disulfide (MoS2) has gained attention because of its high mobility and circular dichroism. As a crucial step to merge these advantages into a single device, we present a method that electronically controls and locates p-n junctions in liquid-gated ambipolar MoS2 transistors. A

  16. Ta2O5 as gate dielectric material for low-voltage organic thin-film transistors

    NARCIS (Netherlands)

    Bartic, Carmen; Jansen, Henricus V.; Campitelli, Andrew; Borghs, Staf

    In this paper we report the use of Ta2O5 as gate dielectric material for organic thin-film transistors. Ta2O5 has already attracted a lot of attention as insulating material for VLSI applications. We have deposited Ta2O5 thin-films with different thickness by means of electron-beam evaporation.

  17. Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

    KAUST Repository

    Salas-Villasenor, A. L.

    2010-06-29

    Cadmium sulfide thin film transistors were demonstrated as the n-type device for use in flexible electronics. CdS thin films were deposited by chemical bath deposition (70° C) on either 100 nm HfO2 or SiO2 as the gate dielectrics. Common gate transistors with channel lengths of 40-100 μm were fabricated with source and drain aluminum top contacts defined using a shadow mask process. No thermal annealing was performed throughout the device process. X-ray diffraction results clearly show the hexagonal crystalline phase of CdS. The electrical performance of HfO 2 /CdS -based thin film transistors shows a field effect mobility and threshold voltage of 25 cm2 V-1 s-1 and 2 V, respectively. Improvement in carrier mobility is associated with better nucleation and growth of CdS films deposited on HfO2. © 2010 The Electrochemical Society.

  18. Short-Term Synaptic Plasticity Regulation in Solution-Gated Indium-Gallium-Zinc-Oxide Electric-Double-Layer Transistors.

    Science.gov (United States)

    Wan, Chang Jin; Liu, Yang Hui; Zhu, Li Qiang; Feng, Ping; Shi, Yi; Wan, Qing

    2016-04-20

    In the biological nervous system, synaptic plasticity regulation is based on the modulation of ionic fluxes, and such regulation was regarded as the fundamental mechanism underlying memory and learning. Inspired by such biological strategies, indium-gallium-zinc-oxide (IGZO) electric-double-layer (EDL) transistors gated by aqueous solutions were proposed for synaptic behavior emulations. Short-term synaptic plasticity, such as paired-pulse facilitation, high-pass filtering, and orientation tuning, was experimentally emulated in these EDL transistors. Most importantly, we found that such short-term synaptic plasticity can be effectively regulated by alcohol (ethyl alcohol) and salt (potassium chloride) additives. Our results suggest that solution gated oxide-based EDL transistors could act as the platforms for short-term synaptic plasticity emulation.

  19. An Evaluation of Bipolar Junction Transistors as Dosimeter for Megavoltage Electron Beams

    Energy Technology Data Exchange (ETDEWEB)

    Passos, Renan Garcia de; Vidal da Silva, Rogerio Matias; Silva, Malana Marcelina Almeida; Souza, Divanizia do Nascimento [Departamento de Fisica, Universidade Federal de Sergipe, Av. Marechal Rondon, sn, Sao Cristovao, SE, 49100-000 (Brazil); Pereira dos Santos, Luiz Antonio [Comissao Nacional de Energia Nuclear, CNEN/CRCN-NE, Av. Prof. Luiz Freire, 1, Recife, PE, 50740-540 (Brazil)

    2015-07-01

    Dosimetry is an extremely important field in medical applications of radiation and nowadays, electron beam is a good option for superficial tumor radiotherapy. Normally, the applied dose to the patient both in diagnostic and therapy must be monitored to prevent injuries and ensure the success of the treatment, therefore, we should always look for improving of the dosimetric methods. Accordingly, the aim of this work is about the use of a bipolar junction transistor (BJT) for electron beam dosimetry. After previous studies, such an electronic device can work as a dosimeter when submitted to ionizing radiation of photon beam. Actually, a typical BJT consists of two PN semiconductor junctions resulting in the NPN structure device, for while, and each semiconductor is named as collector (C), base (B) and emitter (E), respectively. Although the transistor effect, which corresponds to the current amplification, be accurately described by the quantum physics, one can utilize a simple concept from the circuit theory: the base current IB (input signal) is amplified by a factor of β resulting in the collector current IC (output signal) at least one hundred times greater the IB. In fact, the BJT is commonly used as a current amplifier with gain β=I{sub C}/I{sub B}, therefore, it was noticed that this parameter is altered when the device is exposed to ionizing radiation. The current gain alteration can be explained by the trap creation and the positive charges build up, beside the degradation of the lattice structure. Then, variations of the gain of irradiated transistors may justify their use as a dosimeter. Actually, the methodology is based on the measurements of the I{sub C} variations whereas I{sub B} is maintained constant. BC846 BJT type was used for dose monitoring from passive-mode measurements: evaluation of its electrical characteristic before and after irradiation procedure. Thus, IC readings were plotted as a function of the applied dose in 6 MeV electron beam

  20. The Complete Semiconductor Transistor and Its Incomplete Forms

    Science.gov (United States)

    Binbin, Jie; Chih-Tang, Sah

    2009-06-01

    This paper describes the definition of the complete transistor. For semiconductor devices, the complete transistor is always bipolar, namely, its electrical characteristics contain both electron and hole currents controlled by their spatial charge distributions. Partially complete or incomplete transistors, via coined names or/and designed physical geometries, included the 1949 Shockley p/n junction transistor (later called Bipolar Junction Transistor, BJT), the 1952 Shockley unipolar 'field-effect' transistor (FET, later called the p/n Junction Gate FET or JGFET), as well as the field-effect transistors introduced by later investigators. Similarities between the surface-channel MOS-gate FET (MOSFET) and the volume-channel BJT are illustrated. The bipolar currents, identified by us in a recent nanometer FET with 2-MOS-gates on thin and nearly pure silicon base, led us to the recognition of the physical makeup and electrical current and charge compositions of a complete transistor and its extension to other three or more terminal signal processing devices, and also the importance of the terminal contacts.

  1. Characterization of ionizing radiation effects in MOS structures by study of bipolar operation; Caracterisation des effets induits par irradiations ionisantes dans des structures MOS a partir de leur fonctionnement en regime bipolaire

    Energy Technology Data Exchange (ETDEWEB)

    Bakhtiar, H. [Univ. Teknologi Malaysia, Dept. of Physics, Johor (Malaysia); Picard, C.; Brisset, C. [CEA Saclay, Lab. d' Electronique et de Technologie de l' Informatique, LETI, 91 - Gif-sur-Yvette (France); Bakhtiar, H.; Hoffmann, A.; Charles, J.P. [Metz Univ., LICM-CLOES-Supelec, 57 (France)

    1999-07-01

    This work presents an original method to characterize radiation effects of micronic transistors. The characterization includes a study of the transistor substrate-drain junction and current gain variation of the bipolar transistor (drain-substrate-source as emitter-base-collector) for different gate voltages. (author000.

  2. Understanding the failure mechanisms of microwave bipolar transistors caused by electrostatic discharge

    Science.gov (United States)

    Jin, Liu; Yongguang, Chen; Zhiliang, Tan; Jie, Yang; Xijun, Zhang; Zhenxing, Wang

    2011-10-01

    Electrostatic discharge (ESD) phenomena involve both electrical and thermal effects, and a direct electrostatic discharge to an electronic device is one of the most severe threats to component reliability. Therefore, the electrical and thermal stability of multifinger microwave bipolar transistors (BJTs) under ESD conditions has been investigated theoretically and experimentally. 100 samples have been tested for multiple pulses until a failure occurred. Meanwhile, the distributions of electric field, current density and lattice temperature have also been analyzed by use of the two-dimensional device simulation tool Medici. There is a good agreement between the simulated results and failure analysis. In the case of a thermal couple, the avalanche current distribution in the fingers is in general spatially unstable and results in the formation of current crowding effects and crystal defects. The experimental results indicate that a collector-base junction is more sensitive to ESD than an emitter-base junction based on the special device structure. When the ESD level increased to 1.3 kV, the collector-base junction has been burnt out first. The analysis has also demonstrated that ESD failures occur generally by upsetting the breakdown voltage of the dielectric or overheating of the aluminum-silicon eutectic. In addition, fatigue phenomena are observed during ESD testing, with devices that still function after repeated low-intensity ESDs but whose performances have been severely degraded.

  3. Improved performance of bipolar charge plasma transistor by reducing the horizontal electric field

    Science.gov (United States)

    Bramhane, Lokesh Kumar; Singh, Jawar

    2017-04-01

    In this paper, we have proposed a modified lateral bipolar charge plasma transistor (BCPT). The appropriate work function engineering is used to induce the electron-hole concentrations under different regions. The reduced work function difference and absence of oxide layer (tox) in the proposed lateral BCPT reduce the horizontal electric field (EX) at the emitter. Also, reduced work function difference at base metal contact decreases the electric field at base-emitter and base-collector junctions. 2-D TCAD simulations of the proposed device reveal that there are evenly spaced output characteristic curves, improved cut-off frequency and breakdown voltage. The reduction in horizontal electric field about one-fourth compared to the conventional lateral BCPT results in realistic current gain (β) and reduced on-set voltage makes proposed device suitable for low power applications. The proposed device exhibits improved cut-off frequency (fT = 7.5 GHz) compared to the lateral BCPT (3.7 GHz) and improved current gain (37.67) and same cut-off frequency (= 7.5 GHz) compared to the conventional BJT (β = 26.5 &fT = 7.5 GHz).

  4. GaAsP/InGaP heterojunction bipolar transistors grown by MOCVD

    Science.gov (United States)

    Heidelberger, Christopher; Fitzgerald, Eugene A.

    2017-01-01

    Heterojunction bipolar transistors with GaAsxP1-x bases and collectors and InyGa1-yP emitters were grown on GaAs substrates via metalorganic chemical vapor deposition, fabricated using conventional techniques, and electrically tested. Four different GaAsxP1-x compositions were used, ranging from x = 0.825 to x = 1 (GaAs), while the InyGa1-yP composition was adjusted to remain lattice-matched to the GaAsP. DC gain close to or exceeding 100 is measured for 60 μm diameter devices of all compositions. Physical mechanisms governing base current and therefore current gain are investigated. The collector current is determined not to be affected by the barrier caused by the conduction band offset between the InGaP emitter and GaAsP base. While the collector current for the GaAs/InGaP devices is well-predicted by diffusion of electrons across the quasi-neutral base, the collector current of the GaAsP/InGaP devices exceeds this estimate by an order of magnitude. This results in higher transconductance for GaAsP/InGaP than would be estimated from known material properties.

  5. Radiation damage and defects in NPN bipolar junction transistors irradiated by silicon ions with various energies

    Science.gov (United States)

    Liu, Chaoming; Zhang, Xiaodong; Yang, Jianqun; Li, Xingji; Ma, Guoliang

    2017-10-01

    The characteristic of incident particle is an important factor to evaluate the correlation of radiation damage. It is useful to investigate the influence of incident particle with various energies on radiation effects of BJTs. Radiation effects in bipolar junction transistors are examined under the irradiation with 10, 24 and 40 MeV Si ions in this paper. Based on the electrical performance degradation, it is shown that the change in the reciprocal of current gain is dominated by the ionizing damage during the heavy ion irradiations at low fluence, leading to a non-linear behavior. While at a higher fluence, displacement damage is the domain effect to show a linear curve. Deep level transient spectroscopy (DLTS) is used to analyze the characteristic of the deep level defects induced by irradiations. DLTS results show that for the BJTs under various Si ions irradiations, the types of deep level defects induced by Si ions are similar, while the concentration of the defects is different at the same displacement dose.

  6. Bipolar-power-transistor-based limiter for high frequency ultrasound imaging systems.

    Science.gov (United States)

    Choi, Hojong; Yang, Hao-Chung; Shung, K Kirk

    2014-03-01

    High performance limiters are described in this paper for applications in high frequency ultrasound imaging systems. Limiters protect the ultrasound receiver from the high voltage (HV) spikes produced by the transmitter. We present a new bipolar power transistor (BPT) configuration and compare its design and performance to a diode limiter used in traditional ultrasound research and one commercially available limiter. Limiter performance depends greatly on the insertion loss (IL), total harmonic distortion (THD) and response time (RT), each of which will be evaluated in all the limiters. The results indicated that, compared with commercial limiter, BPT-based limiter had less IL (-7.7 dB), THD (-74.6 dB) and lower RT (43 ns) at 100 MHz. To evaluate the capability of these limiters, they were connected to a 100 MHz single element transducer and a two-way pulse-echo test was performed. It was found that the -6 dB bandwidth and sensitivity of the transducer using BPT-based limiter were better than those of the commercial limiter by 22% and 140%, respectively. Compared to the commercial limiter, BPT-based limiter is shown to be capable of minimizing signal attenuation, RT and THD at high frequencies and is thus suited for high frequency ultrasound applications. Copyright © 2013 Elsevier B.V. All rights reserved.

  7. Tunneling Current of Electron in Armchair Graphene Nanoribbon Bipolar Transistor Model Using Transfer Matrix Method

    Science.gov (United States)

    Fahmi, A. K.; Hasanah, L.; Rusdiana, D.; Aminudin, A.; Suhendi, E.

    2017-03-01

    The tunneling current of n-p-n bipolar junction transistor AGNR-based is modeled with semi-numerical method. The exponential solution from Schrödinger equation is used and solved analytically. The potential profile of n-p-n BJT divided into several segments in the numerical method. Then, the solved analytical result is used in the numerical method to compute the electron transmittance. Transfer Matrix Method (TMM) is the numerical method used to compute the electron transmittance. From the calculated transmittance the tunneling current can be computed by using Landauer formula with aid of Gauss-Legendre Quadrature (GLQ). Next, the tunneling current is computed with several change of variables which are base-emitter voltage (VBE), base-collector voltage (VBC), temperature and the AGNR’s width. The computed tunneling current shows that the larger value of applied voltage for both VBE and VBC results in larger value of tunneling current. At the lower temperature, the current is larger. The computed tunneling current shows that at wider width of AGNR, the current is also larger. This is due to the decreased band-gap energy (Eg) because of the wider width of AGNR.

  8. Junction-to-Case Thermal Resistance of a Silicon Carbide Bipolar Junction Transistor Measured

    Science.gov (United States)

    Niedra, Janis M.

    2006-01-01

    Junction temperature of a prototype SiC-based bipolar junction transistor (BJT) was estimated by using the base-emitter voltage (V(sub BE)) characteristic for thermometry. The V(sub BE) was measured as a function of the base current (I(sub B)) at selected temperatures (T), all at a fixed collector current (I(sub C)) and under very low duty cycle pulse conditions. Under such conditions, the average temperature of the chip was taken to be the same as that of the temperature-controlled case. At increased duty cycle such as to substantially heat the chip, but same I(sub C) pulse height, the chip temperature was identified by matching the V(sub BE) to the thermometry curves. From the measured average power, the chip-to-case thermal resistance could be estimated, giving a reasonable value. A tentative explanation for an observed bunching with increasing temperature of the calibration curves may relate to an increasing dopant atom ionization. A first-cut analysis, however, does not support this.

  9. Understanding the failure mechanisms of microwave bipolar transistors caused by electrostatic discharge

    International Nuclear Information System (INIS)

    Liu Jin; Chen Yongguang; Tan Zhiliang; Yang Jie; Zhang Xijun; Wang Zhenxing

    2011-01-01

    Electrostatic discharge (ESD) phenomena involve both electrical and thermal effects, and a direct electrostatic discharge to an electronic device is one of the most severe threats to component reliability. Therefore, the electrical and thermal stability of multifinger microwave bipolar transistors (BJTs) under ESD conditions has been investigated theoretically and experimentally. 100 samples have been tested for multiple pulses until a failure occurred. Meanwhile, the distributions of electric field, current density and lattice temperature have also been analyzed by use of the two-dimensional device simulation tool Medici. There is a good agreement between the simulated results and failure analysis. In the case of a thermal couple, the avalanche current distribution in the fingers is in general spatially unstable and results in the formation of current crowding effects and crystal defects. The experimental results indicate that a collector-base junction is more sensitive to ESD than an emitter-base junction based on the special device structure. When the ESD level increased to 1.3 kV, the collector-base junction has been burnt out first. The analysis has also demonstrated that ESD failures occur generally by upsetting the breakdown voltage of the dielectric or overheating of the aluminum-silicon eutectic. In addition, fatigue phenomena are observed during ESD testing, with devices that still function after repeated low-intensity ESDs but whose performances have been severely degraded. (semiconductor devices)

  10. A novel high breakdown voltage lateral bipolar transistor on SOI with multizone doping and multistep oxide

    International Nuclear Information System (INIS)

    Loan, Sajad A; Qureshi, S; Kumar Iyer, S S

    2009-01-01

    A novel high breakdown voltage lateral bipolar junction transistor (LBJT) on silicon-on- insulator (SOI) is proposed. The novelty of the device is the use of the combination of multistep-doped drift region and multistep buried oxide. The steps in doping and in oxide thickness have been used as a replacement for much complex linearly varying drift doping and linearly varying oxide thickness. The LBJT structure incorporating the combination of multistep doping and multistep oxide is analyzed for electrical characteristics using a two-dimensional numerical simulator MEDICI. Numerical simulation has demonstrated that the breakdown voltage of the proposed device with a two-zone step doped (TZSD) drift region is >150% higher than the conventional device. It has been observed that increasing the number of doping zones to 3 from 2 results in a >40% rise in breakdown voltage. The proposed device gives high breakdown voltage even at high doping concentration in the collector drift region. This reduces the on-resistance of the device and thus improves its speed. The dependence of breakdown voltage on various device parameters has been extensively studied to achieve optimum device performance. A process flow for the device fabrication is also being proposed

  11. Effect of bias condition on heavy ion radiation in bipolar junction transistors

    Science.gov (United States)

    Liu, Chao-Ming; Li, Xing-Ji; Geng, Hong-Bin; Yang, De-Zhuang; He, Shi-Yu

    2012-08-01

    The characteristic degradations in a silicon NPN bipolar junction transistor (BJT) of 3DG142 type are examined under irradiation with 40-MeV chlorine (Cl) ions under forward, grounded, and reverse bias conditions, respectively. Different electrical parameters are in-situ measured during the exposure under each bias condition. From the experimental data, a larger variation of base current (IB) is observed after irradiation at a given value of base-emitter voltage (VBE), while the collector current is slightly affected by irradiation at a given VBE. The gain degradation is affected mostly by the behaviour of the base current. From the experimental data, the variation of current gain in the case of forward bias is much smaller than that in the other conditions. Moreover, for 3DG142 BJT, the current gain degradation in the case of reverse bias is more severe than that in the grounded case at low fluence, while at high fluence, the gain degradation in the reverse bias case becomes smaller than that in the grounded case.

  12. Bipolar junction transistor as a detector for measuring in diagnostic X-ray beams

    Energy Technology Data Exchange (ETDEWEB)

    Cavalcanti, Francisco A.; Monte, David S.; Alves, Aline N.; Barros, Fabio R.; Santos, Marcus A.P.; Santos, Luiz A.P., E-mail: franciscoacavalcanti@gmail.com, E-mail: lasantos@cnen.gov.br [Centro Regional de Ciencias Nucleares do Nordeste (CRCN-NE/CNEN-PE), Recife, PE (Brazil)

    2013-07-01

    Photodiode and phototransistor are the most frequently used devices for measuring ionizing radiation in medical applications. The cited devices have the operating principle well known, however the bipolar junction transistor (BJT) is not a typical device used as a detector for measuring some physical quantities for diagnostic radiation. In fact, a photodiode, for example, has an area about 10 mm square and a BJT has an area which can be more than 10 thousands times smaller. The purpose of this paper is to bring a new technique to estimate some physical quantities or parameters in diagnostic radiation; for example, peak kilovoltage (kVp), deep dose measurements. The methodology for each type of evaluation depends on the energy range of the radiation and the physical quantity or parameter to be measured. Actually, some characteristics of the incident radiation under the device can be correlated with the readout signal, which is a function of the electrical currents in the electrodes of the BJT: Collector, Base and Emitter. Samples of BJT are classified and submitted to diagnostic X-ray beams. The results show that the BJT could be a new semiconductor sensor type for measuring either the ionizing radiation dose or some characteristics of diagnostic X-ray beams. (author)

  13. Inter-grain coupling effects on Coulomb oscillations in dual-gated nanocrystalline silicon point-contact transistors

    International Nuclear Information System (INIS)

    Khalafalla, M.A.H.; Durrani, Z.A.K.; Mizuta, H.; Ahmed, H.; Oda, S.

    2005-01-01

    Inter-grain electron-coupling effects are investigated at 4.2 K in dual-gated, point-contact, single-electron transistors fabricated in nanocrystalline silicon. The nanocrystalline silicon film is ∼40 nm thick, with grains ∼10-30 nm in size. The point-contact transistor channel is ∼30 nmx30 nmx40 nm in size, with two side-gates. Only a few grains exist within the channel and different grains contribute in varying degrees to the device conduction. By modifying the inter-grain coupling using selective oxidation of the grain boundaries, both electrostatic and wavefunction-coupling effects can be observed in the Coulomb oscillations vs. the two gate voltages

  14. High-mobility BaSnO3 thin-film transistor with HfO2 gate insulator

    Science.gov (United States)

    Kim, Young Mo; Park, Chulkwon; Kim, Useong; Ju, Chanjong; Char, Kookrin

    2016-01-01

    Thin-film transistors have been fabricated using La-doped BaSnO3 as n-type channels and (In,Sn)2O3 as source, drain, and gate electrodes. HfO2 was grown as gate insulators by atomic layer deposition. The field-effect mobility, Ion/Ioff ratio, and subthreshold swing of the device are 24.9 cm2 V-1 s-1, 6.0 × 106, and 0.42 V dec-1, respectively. The interface trap density, evaluated to be higher than 1013 cm-2 eV-1, was found to be slightly lower than that of the thin-film transistor with an Al2O3 gate insulator. We attribute the much smaller subthreshold swing values to the higher dielectric constant of HfO2.

  15. Ferroelectric gate tunnel field-effect transistors with low-power steep turn-on

    Directory of Open Access Journals (Sweden)

    M. H. Lee

    2014-10-01

    Full Text Available Using a ferroelectric PbZrTiO3 gate stack, the range of the steep subthreshold swing in tunnel field-effect transistors was extended by 3.5 orders of magnitude demonstrating an improvement in the swing (by approximately double the slope. The drain conductance (gd shows only 16% enhancement with large V DS (∼−1.5V indicates internal voltage amplification with ferroelectric negative capacitance effect beneficial to small lateral drain-source bias voltages (−0.1 V. The concept of coupling the ferroelectric polarization is proposed. The power consumption is also discussed in low-power applications of steep subthreshold slope devices.

  16. Functionalization and microfluidic integration of silicon nanowire biologically gated field effect transistors

    DEFF Research Database (Denmark)

    Pfreundt, Andrea; Svendsen, Winnie Edith; Dimaki, Maria

    2016-01-01

    This thesis deals with the development of a novel biosensor for the detection of biomolecules based on a silicon nanowire biologically gated field-effect transistor and its integration into a point-of-care device. The sensor and electrical on-chip integration was developed in a different project....... The presented research is based on this sensor structure and investigates its potential as a versatile biomarker detection platform by evaluating different functionalization approaches. The functionalization of the silicon sensor surface with organic molecules was investigated in detail to determine...... the suitability of different methods for the preparation of organic interfaces for protein attachment. Oxide-free silicon surfaces offer unique possibilities to create highly sensitive sensor surfaces for charge detection due to the lack of an insulating oxide layer, but the highly reactive surface presents...

  17. Functionalization and microfluidic integration of silicon nanowire biologically gated field effect transistors

    DEFF Research Database (Denmark)

    Pfreundt, Andrea

    This thesis deals with the development of a novel biosensor for the detection of biomolecules based on a silicon nanowire biologically gated field-effect transistor and its integration into a point-of-care device. The sensor and electrical on-chip integration was developed in a different project....... The presented research is based on this sensor structure and investigates its potential as a versatile biomarker detection platform by evaluating different functionalization approaches. The functionalization of the silicon sensor surface with organic molecules was investigated in detail to determine...... the suitability of different methods for the preparation of organic interfaces for protein attachment. Oxide-free silicon surfaces offer unique possibilities to create highly sensitive sensor surfaces for charge detection due to the lack of an insulating oxide layer, but the highly reactive surface presents...

  18. Detection and Sourcing of Gluten in Grain with Multiple Floating-Gate Transistor Biosensors.

    Science.gov (United States)

    White, Scott P; Frisbie, C Daniel; Dorfman, Kevin D

    2018-02-23

    We report a chemically tunable electronic sensor for quantitation of gluten based on a floating-gate transistor (FGT) architecture. The FGTs are fabricated in parallel and each one is functionalized with a different chemical moiety designed to preferentially bind a specific grain source of gluten. The resulting set of FGT sensors can detect both wheat and barley gluten below the gluten-free limit of 20 ppm (w/w) while providing a source-dependent signature for improved accuracy. This label-free transduction method does not require any secondary binding events, resulting in a ca. 45 min reduction in analysis time relative to state-of-the-art ELISA kits with a simple and easily implemented workflow.

  19. The influence of fibril composition and dimension on the performance of paper gated oxide transistors

    Science.gov (United States)

    Pereira, L.; Gaspar, D.; Guerin, D.; Delattre, A.; Fortunato, E.; Martins, R.

    2014-03-01

    Paper electronics is a topic of great interest due the possibility of having low-cost, disposable and recyclable electronic devices. The final goal is to make paper itself an active part of such devices. In this work we present new approaches in the selection of tailored paper, aiming to use it simultaneously as substrate and dielectric in oxide based paper field effect transistors (FETs). From the work performed, it was observed that the gate leakage current in paper FETs can be reduced using a dense microfiber/nanofiber cellulose paper as the dielectric. Also, the stability of these devices against changes in relative humidity is improved. On other hand, if the pH of the microfiber/nanofiber cellulose pulp is modified by the addition of HCl, the saturation mobility of the devices increases up to 16 cm2 V-1 s-1, with an ION/IOFF ratio close to 105.

  20. Modeling Radiation-Induced Degradation in Top-Gated Epitaxial Graphene Field-Effect-Transistors (FETs

    Directory of Open Access Journals (Sweden)

    Jeong-S. Moon

    2013-07-01

    Full Text Available This paper investigates total ionizing dose (TID effects in top-gated epitaxial graphene field-effect-transistors (GFETs. Measurements reveal voltage shifts in the current-voltage (I-V characteristics and degradation of carrier mobility and minimum conductivity, consistent with the buildup of oxide-trapped charges. A semi-empirical approach for modeling radiation-induced degradation in GFETs effective carrier mobility is described in the paper. The modeling approach describes Coulomb and short-range scattering based on calculations of charge and effective vertical field that incorporate radiation-induced oxide trapped charges. The transition from the dominant scattering mechanism is correctly described as a function of effective field and oxide trapped charge density. Comparison with experimental data results in good qualitative agreement when including an empirical component to account for scatterer transparency in the low field regime.

  1. High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

    Science.gov (United States)

    Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

    2018-02-01

    The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

  2. Gate sensing coherent charge oscillations in a silicon field-effect transistor

    Science.gov (United States)

    Gonzalez-Zalba, M. Fernando; Shevchenko, Sergey; Barraud, Sylvain; Johansson, J. Robert; Ferguson, Andrew; Nori, Franco; Betz, Andreas

    We report the observation of coherent charge oscillations in a double quantum dot formed in a silicon nanowire transistor detected via its dispersive interaction with a radio-frequency resonant circuit coupled via the gate. Differential capacitance changes at the inter-dot charge transitions allow us to monitor the state of the system in the strong-driving regime where we observe the emergence of Landau-Zener-Stückelberg-Majorana interference on the phase response of the resonator. A theoretical analysis of the dispersive signal demonstrates that quantum and tunnelling capacitance changes must be included to describe the qubit-resonator interaction. Furthermore, a Fourier analysis of the interference pattern reveals a charge coherence time, T2 = 100 ps. Our results demonstrate charge coherent control and readout in a simple silicon transistor and open up the possibility to implement charge and spin qubits in existing complementary metal-oxide-semiconductor technology. We thank FP7 318397, RIKEN iTHES project, AFOSR FA9550-14-1-0040, IMPACT program of JST and a Grant-in-Aid for Scientific Research.

  3. Temperature dependence of the current in Schottky-barrier source-gated transistors

    Science.gov (United States)

    Sporea, R. A.; Overy, M.; Shannon, J. M.; Silva, S. R. P.

    2015-05-01

    The temperature dependence of the drain current is an important parameter in thin-film transistors. In this paper, we propose that in source-gated transistors (SGTs), this temperature dependence can be controlled and tuned by varying the length of the source electrode. SGTs comprise a reverse biased potential barrier at the source which controls the current. As a result, a large activation energy for the drain current may be present which, although useful in specific temperature sensing applications, is in general deleterious in many circuit functions. With support from numerical simulations with Silvaco Atlas, we describe how increasing the length of the source electrode can be used to reduce the activation energy of SGT drain current, while maintaining the defining characteristics of SGTs: low saturation voltage, high output impedance in saturation, and tolerance to geometry variations. In this study, we apply the dual current injection modes to obtain drain currents with high and low activation energies and propose mechanisms for their exploitation in future large-area integrated circuit designs.

  4. The origin of excellent gate-bias stress stability in organic field-effect transistors employing fluorinated-polymer gate dielectrics.

    Science.gov (United States)

    Kim, Jiye; Jang, Jaeyoung; Kim, Kyunghun; Kim, Haekyoung; Kim, Se Hyun; Park, Chan Eon

    2014-11-12

    Tuning of the energetic barriers to charge transfer at the semiconductor/dielectric interface in organic field-effect transistors (OFETs) is achieved by varying the dielectric functionality. Based on this, the correlation between the magnitude of the energy barrier and the gate-bias stress stability of the OFETs is demonstrated, and the origin of the excellent device stability of OFETs employing fluorinated dielectrics is revealed. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  5. Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

    Energy Technology Data Exchange (ETDEWEB)

    Besleaga, C.; Stan, G.E.; Pintilie, I. [National Institute of Materials Physics, 405A Atomistilor, 077125 Magurele-Ilfov (Romania); Barquinha, P.; Fortunato, E. [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal); Martins, R., E-mail: rm@uninova.pt [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal)

    2016-08-30

    Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

  6. Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

    International Nuclear Information System (INIS)

    Besleaga, C.; Stan, G.E.; Pintilie, I.; Barquinha, P.; Fortunato, E.; Martins, R.

    2016-01-01

    Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

  7. Strain and deformations engineered germanene bilayer double gate-field effect transistor by first principles

    Science.gov (United States)

    Meher Abhinav, E.; Chandrasekaran, Gopalakrishnan; Kasmir Raja, S. V.

    2017-10-01

    Germanene, silicene, stanene, phosphorene and graphene are some of single atomic materials with novel properties. In this paper, we explored bilayer germanene-based Double Gate-Field Effect Transistor (DG-FET) with various strains and deformations using Density Functional Theory (DFT) and Green's approach by first-principle calculations. The DG-FET of 1.6 nm width, 6 nm channel length (Lch) and HfO2 as gate dielectric has been modeled. For intrinsic deformation of germanene bilayer, we have enforced minute mechanical deformation of wrap and twist (5°) and ripple (0.5 Å) on germanene bilayer channel material. By using NEGF formalism, I-V Characteristics of various strains and deformation tailored DG-FET was calculated. Our results show that rough edge and single vacancy (5-9) in bilayer germanene diminishes the current around 47% and 58% respectively as compared with pristine bilayer germanene. In case of strain tailored bilayer DG-FET, multiple NDR regions were observed which can be utilized in building stable multiple logic states in digital circuits and high frequency oscillators using negative resistive techniques.

  8. Flexible suspended gate organic thin-film transistors for ultra-sensitive pressure detection

    Science.gov (United States)

    Zang, Yaping; Zhang, Fengjiao; Huang, Dazhen; Gao, Xike; di, Chong-An; Zhu, Daoben

    2015-03-01

    The utilization of organic devices as pressure-sensing elements in artificial intelligence and healthcare applications represents a fascinating opportunity for the next-generation electronic products. To satisfy the critical requirements of these promising applications, the low-cost construction of large-area ultra-sensitive organic pressure devices with outstanding flexibility is highly desired. Here we present flexible suspended gate organic thin-film transistors (SGOTFTs) as a model platform that enables ultra-sensitive pressure detection. More importantly, the unique device geometry of SGOTFTs allows the fine-tuning of their sensitivity by the suspended gate. An unprecedented sensitivity of 192 kPa-1, a low limit-of-detection pressure of <0.5 Pa and a short response time of 10 ms were successfully realized, allowing the real-time detection of acoustic waves. These excellent sensing properties of SGOTFTs, together with their advantages of facile large-area fabrication and versatility in detecting various pressure signals, make SGOTFTs a powerful strategy for spatial pressure mapping in practical applications.

  9. Solution processed lanthanum aluminate gate dielectrics for use in metal oxide-based thin film transistors

    Energy Technology Data Exchange (ETDEWEB)

    Esro, M.; Adamopoulos, G., E-mail: g.adamopoulos@lancaster.ac.uk [Engineering Department, Lancaster University, Lancaster LA1 4YR (United Kingdom); Mazzocco, R.; Kolosov, O.; Krier, A. [Physics Department, Lancaster University, Lancaster, LA1 4YB (United Kingdom); Vourlias, G. [Physics Department, Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece); Milne, W. I. [Department of Engineering, University of Cambridge, 9 JJ Thomson Avenue, Cambridge CB3 0FA (United Kingdom); Department of Electrical and Computing Engineering, University of Canterbury, 4800 Christchurch (New Zealand)

    2015-05-18

    We report on ZnO-based thin-film transistors (TFTs) employing lanthanum aluminate gate dielectrics (La{sub x}Al{sub 1−x}O{sub y}) grown by spray pyrolysis in ambient atmosphere at 440 °C. The structural, electronic, optical, morphological, and electrical properties of the La{sub x}Al{sub 1−x}O{sub y} films and devices as a function of the lanthanum to aluminium atomic ratio were investigated using a wide range of characterization techniques such as UV-visible absorption spectroscopy, impedance spectroscopy, spectroscopic ellipsometry, atomic force microscopy, x-ray diffraction, and field-effect measurements. As-deposited LaAlO{sub y} dielectrics exhibit a wide band gap (∼6.18 eV), high dielectric constant (k ∼ 16), low roughness (∼1.9 nm), and very low leakage currents (<3 nA/cm{sup 2}). TFTs employing solution processed LaAlO{sub y} gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with hysteresis-free operation, low operation voltages (∼10 V), high on/off current modulation ratio of >10{sup 6}, subthreshold swing of ∼650 mV dec{sup −1}, and electron mobility of ∼12 cm{sup 2} V{sup −1} s{sup −1}.

  10. Single trap dynamics in electrolyte-gated Si-nanowire field effect transistors

    Science.gov (United States)

    Pud, S.; Gasparyan, F.; Petrychuk, M.; Li, J.; Offenhäusser, A.; Vitusevich, S. A.

    2014-06-01

    Liquid-gated silicon nanowire (NW) field effect transistors (FETs) are fabricated and their transport and dynamic properties are investigated experimentally and theoretically. Random telegraph signal (RTS) fluctuations were registered in the nanolength channel FETs and used for the experimental and theoretical analysis of transport properties. The drain current and the carrier interaction processes with a single trap are analyzed using a quantum-mechanical evaluation of carrier distribution in the channel and also a classical evaluation. Both approaches are applied to treat the experimental data and to define an appropriate solution for describing the drain current behavior influenced by single trap resulting in RTS fluctuations in the Si NW FETs. It is shown that quantization and tunneling effects explain the behavior of the electron capture time on the single trap. Based on the experimental data, parameters of the single trap were determined. The trap is located at a distance of about 2 nm from the interface Si/SiO2 and has a repulsive character. The theory of dynamic processes in liquid-gated Si NW FET put forward here is in good agreement with experimental observations of transport in the structures and highlights the importance of quantization in carrier distribution for analyzing dynamic processes in the nanostructures.

  11. High performance tunnel field-effect transistor by gate and source engineering.

    Science.gov (United States)

    Huang, Ru; Huang, Qianqian; Chen, Shaowen; Wu, Chunlei; Wang, Jiaxin; An, Xia; Wang, Yangyuan

    2014-12-19

    As one of the most promising candidates for future nanoelectronic devices, tunnel field-effect transistors (TFET) can overcome the subthreshold slope (SS) limitation of MOSFET, whereas high ON-current, low OFF-current and steep switching can hardly be obtained at the same time for experimental TFETs. In this paper, we developed a new nanodevice technology based on TFET concepts. By designing the gate configuration and introducing the optimized Schottky junction, a multi-finger-gate TFET with a dopant-segregated Schottky source (mFSB-TFET) is proposed and experimentally demonstrated. A steeper SS can be achieved in the fabricated mFSB-TFET on the bulk Si substrate benefiting from the coupled quantum band-to-band tunneling (BTBT) mechanism, as well as a high I(ON)/I(OFF) ratio (∼ 10(7)) at V(DS) = 0.2 V without an area penalty. By compatible SOI CMOS technology, the fabricated Si mFSB-TFET device was further optimized with a high ION/IOFF ratio of ∼ 10(8) and a steeper SS of over 5.5 decades of current. A minimum SS of below 60 mV dec(-1) was experimentally obtained, indicating its dominant quantum BTBT mechanism for switching.

  12. Dual metal gate tunneling field effect transistors based on MOSFETs: A 2-D analytical approach

    Science.gov (United States)

    Ramezani, Zeinab; Orouji, Ali A.

    2018-01-01

    A novel 2-D analytical drain current model of novel Dual Metal Gate Tunnel Field Effect Transistors Based on MOSFETs (DMG-TFET) is presented in this paper. The proposed Tunneling FET is extracted from a MOSFET structure by employing an additional electrode in the source region with an appropriate work function to induce holes in the N+ source region and hence makes it as a P+ source region. The electric field is derived which is utilized to extract the expression of the drain current by analytically integrating the band to band tunneling generation rate in the tunneling region based on the potential profile by solving the Poisson's equation. Through this model, the effects of the thin film thickness and gate voltage on the potential, the electric field, and the effects of the thin film thickness on the tunneling current can be studied. To validate our present model we use SILVACO ATLAS device simulator and the analytical results have been compared with it and found a good agreement.

  13. Isolated Photosystem I Reaction Centers on a Functionalized Gated High Electron Mobility Transistor

    Energy Technology Data Exchange (ETDEWEB)

    Eliza, Sazia A. [University of Tennessee, Knoxville (UTK); Lee, Ida [ORNL; Tulip, Fahmida S [ORNL; Islam, Syed K [University of Tennessee, Knoxville (UTK); Mostafa, Salwa [University of Tennessee, Knoxville (UTK); Greenbaum, Elias [ORNL; Ericson, Milton Nance [ORNL

    2011-01-01

    In oxygenic plants, photons are captured with high quantum efficiency by two specialized reaction centers (RC) called Photosystem I (PS I) and Photosystem II (PS II). The captured photon triggers rapid charge separation and the photon energy is converted into an electrostatic potential across the nanometer-scale nm reaction centers. The exogenous photovoltages from a single PS I RC have been previously measured using the technique of Kelvin force probe microscopy (KFM). However, biomolecular photovoltaic applications require two-terminal devices. This paper presents for the first time, a micro-device for detection and characterization of isolated PS I RCs. The device is based on an AlGaN/GaN high electron mobility transistor (HEMT) structure. AlGaN/GaN HEMTs show high current throughputs and greater sensitivity to surface charges compared to other field-effect devices. PS I complexes immobilized on the floating gate of AlGaN/GaN HEMTs resulted in significant changes in the device characteristics under illumination. An analytical model has been developed to estimate the RCs of a major orientation on the functionalized gate surface of the HEMTs.

  14. Device and circuit performance analysis of double gate junctionless transistors at L(g = 18 nm

    Directory of Open Access Journals (Sweden)

    Chitrakant Sahu

    2014-04-01

    Full Text Available The design and characteristics of double-gate (DG junctionless (JL devices are compared with the DG inversion-mode (IM field effect transistors (FETs at 45 nm technology node with effective channel length of 18 nm. The comparison are performed at iso-V(th for both n- and p-type of devices. The JL device shows lower drain-induced barrier lowering, steep subthreshold slope and lower OFF state current. For the first time, the authors demonstrate a pass gate (PG logic, inverter circuit and static random access memory (SRAM stability analysis using JL devices, rather than a complementary metal-oxide semiconductor (CMOS configuration. They observed that transient response of JL PG configuration is similar to that of conventional CMOS PGs. JL inverter also shows similar transient characteristics with 25% reduction in delay and 12% improvement in 6 T SRAM cell stability compared with IMFETs, which shows large potential in digital circuit applications. The simulations were performed using coupled device-circuit methodology in ATLAS technology aided computer design (TCAD mixed-mode simulator.

  15. Serializing off-the-shelf MOSFETs by Magnetically Coupling Their Gate Electrodes

    DEFF Research Database (Denmark)

    Dimopoulos, Emmanouil; Munk-Nielsen, Stig

    2013-01-01

    While the semiconductor industry struggles with the inherent trade-offs of solid-state devices, serialization of power switches, like the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) or the Insulated Gate Bipolar Transistor (IGBT), has been proven to be an advantageous alternative...

  16. Influence of the flux density on the radiation damage of bipolar silicon transistors by protons and electrons

    International Nuclear Information System (INIS)

    Bannikov, Y.; Gorin, B.; Kozhevnikov, V.; Mikhnovich, V.; Gusev, L.

    1981-01-01

    It was found experimentally that the radiation damage of bipolar n-p-n transistors increased by a factor of 8--12 when the proton flux density was reduced from 4.07 x 10 10 to 2.5 x 10 7 cm -2 sec -1 . In the case of p-n-p transistors the effect was opposite: there was a reduction in the radiation damage by a factor of 2--3 when the dose rate was lowered between the same limits. A similar effect was observed for electrons but at dose rates three orders of magnitude greater. The results were attributed to the dependences of the radiation defect-forming reactions on the charge state of defects which was influenced by the formation of disordered regions in the case of proton irradiation

  17. Effect of parasitic series resistances and spurious currents on the extracted temperature of a bipolar junction transistor.

    Science.gov (United States)

    Mimila-Arroyo, J

    2013-12-01

    Verster's proposition to directly extract the temperature of a bipolar junction transistor using its collector current is widely used. However, the resulting temperature is low accurate even when calibrated. Here, it is demonstrated that the misuse of the emitter current instead of the collector one, because of the presence of spurious currents other than the injection-diffusion one and transistor parasitic series resistances both contribute to the observed inaccuracy. Particularly parasitic series resistances increase the inaccuracy and introduce a strong dependence of the extracted temperature on the collector currents used to extract the temperature; the higher those resistances the higher the inaccuracy. A proposition is made to reduce the effect of those resistances on the inaccuracy of this thermometric element, which allows obtaining a more accurate value on a wider range of the collector probe currents.

  18. A Logarithmic Response Complementary Metal Oxide Semiconductor Image Sensor with Parasitic P-N-P Bipolar Junction Transistor

    Science.gov (United States)

    Lai, Cheng‑Hsiao; Lai, Liang‑Wei; Chiang, Wen‑Jen; King, Ya‑Chin

    2006-04-01

    Logarithmic-response complementary metal oxide semiconductor (CMOS) active pixel sensors provide a desirable attribute of wide dynamic range even with low supply voltages. In this paper, a log-mode pixel with employing parasitic P-N-P bipolar junction transistor (BJT) to amplify photo-current is investigated and optimized. A new log-mode cell with a calibration transistor is proposed to increase the output voltage swing as well as to reduce the fixed pattern noise. The measurement results demonstrate that, the output voltage swing of this new cell is enhanced by 4× and fixed pattern noise (FPN) of a pixel array can be reduced by 10× comparing to that of a conventional log-mode CMOS active pixel sensor.

  19. Characteristics of Novel InGaAsN Double Heterojunction Bipolar Transistors

    Energy Technology Data Exchange (ETDEWEB)

    LI,N.Y.; CHANG,PING-CHIH; BACA,ALBERT G.; LAROCHE,J.R.; REN,F.; ARMOUR,E.; SHARPS,P.R.; HOU,H.Q.

    2000-08-01

    The authors demonstrate, for the first time, both functional Pnp AlGaAs/InGaAsN/GaAs (Pnp InGaAsN) and Npn InGaP/InGaAsN/GaAs (Npn InGaAsN) double heterojunction bipolar transistors (DHBTs) using a 1.2 eV In{sub 0.03}Ga{sub 0.97}As{sub 0.99}N{sub 0.01} as the base layer for low-power electronic applications. The Pnp InGaAsN DHBT has a peak current gain ({beta}) of 25 and a low turn-on voltage (V{sub ON}) of 0.79 V. This low V{sub ON} is {approximately} 0.25 V lower than in a comparable Pnp AlGAAs/GaAs HBT. For the Npn InGaAsN DHBT, it has a low V{sub ON} of 0.81 V, which is 0.13 V lower than in an InGaP/GaAs HBT. A peak {beta} of 7 with nearly ideal I-V characteristics has been demonstrated. Since GaAs is used as the collector of both Npn and Pnp InGaAsN DHBTs, the emitter-collector breakdown voltage (BV{sub CEO}) are 10 and 12 V, respectively, consistent with the BV{sub CEO} of Npn InGaP/GaAs and Pnp AlGaAs/GaAs HBTs of comparable collector thickness and doping level. All these results demonstrate the potential of InGaAsN DHBTs as an alternative for application in low-power electronics.

  20. Copper-Based OHMIC Contracts for the Si/SiGe Heterojunction Bipolar Transistor Structure

    Science.gov (United States)

    Das, Kalyan; Hall, Harvey

    1999-01-01

    Silicon based heterojunction bipolar transistors (HBT) with SiGe base are potentially important devices for high-speed and high-frequency microelectronics. These devices are particularly attractive as they can be fabricated using standard Si processing technology. However, in order to realize the full potential of devices fabricated in this material system, it is essential to be able to form low resistance ohmic contacts using low thermal budget process steps and have full compatibility with VLSI/ULSI processing. Therefore, a study was conducted in order to better understand the contact formation and to develop optimized low resistance contacts to layers with doping densities corresponding to the p-type SiGe base and n-type Si emitter regions of the HBTS. These as-grown doped layers were implanted with BF(sub 2) up to 1 X 10(exp 16)/CM(exp 2) and As up to 5 x 10(exp 15)/CM2, both at 30 keV for the p-type SiGe base and n-type Si emitter layers, respectively, in order to produce a low sheet resistance surface layer. Standard transfer length method (TLM) contact pads on both p and n type layers were deposited using an e-beam evaporated trilayer structure of Ti/CufTi/Al (25)A/1500A/250A/1000A). The TLM pads were delineated by a photoresist lift-off procedure. These contacts in the as-deposited state were ohmic, with specific contact resistances for the highest implant doses of the order of 10(exp -7) ohm-CM2 and lower.

  1. The mixed-mode reliability stress of silicon-germanium heterojunction bipolar transistors

    Science.gov (United States)

    Zhu, Chendong

    The objective of the dissertation is to combine the recent Mixed-Mode reliability stress studies in silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs). The thesis starts with a review of SiGe HBT fundamentals, development trends, and the conventional reliability stress paths used in industry, following which the new stress path, Mixed-Mode stress, is introduced. Chapter 2 is devoted to an in-depth discussion of damage mechanisms that includes the impact ionization effect and the self-heating effect. Chapter 3 goes onto the impact ionization effect using two-dimensional calibrated MEDICI simulations. Chapter 4 assesses the reliability of SiGe HBTs in extreme temperature environments by way of comprehensive experiments and MEDICI simulations. A comparison of the device lifetimes for reverse-EB stress and mixed-mode stress indicates different damage mechanisms govern these phenomena. The thesis concludes with a summary of the project and suggestions for future research in chapter 5. This dissertation covers the following topics: (1) Introduces a new mixed-mode stress technique: time cumulative stress (Chapter II, also published in [23] and [24]). (2) Identifies impact ionization effects in the stress damage (Chapter II, also published in [23] and [24]). (3) Investigates for the first time mixed-mode damage using TCAD simulations at both room temperature and cryogenic temperatures (Chapter III and IV, also published in [23][24][62]). (4) Analyzes for the first time impact of self-heating on mixed-mode stress response, and identifies a temperature triggered damage threshold (Chapter II, will be published in [25]). (5) Explains the geometrical scaling issues in mixed-mode stress and explores mixed-mode stress reliability scaling trends (Chapter II, will be published in [25]). (6) Assesses for the first time SiGe HBT reliability at cryogenic temperatures (Chapter VI, also published in [62]).

  2. A comparative study on electrical characteristics of 1-kV pnp and npn SiC bipolar junction transistors

    Science.gov (United States)

    Okuda, Takafumi; Kimoto, Tsunenobu; Suda, Jun

    2018-04-01

    We investigate the electrical characteristics of 1-kV pnp SiC bipolar junction transistors (BJTs) and compare them with those of npn SiC BJTs. The base resistance, current gain, and blocking capability are characterized. It is found that the base resistance of pnp SiC BJTs is two orders of magnitude lower than that of npn SiC BJTs. However, the obtained current gains are low below unity in pnp SiC BJTs, whereas npn SiC BJTs exhibit a current gain of 14 without surface passivation. The reason for the poor current gain of pnp SiC BJTs is discussed.

  3. Impact ionization in the base of a hot-electron AlSb/InAs bipolar transistor

    Science.gov (United States)

    Vengurlekar, Arvind S.; Capasso, Federico; Chiu, T. Heng

    1990-01-01

    The operation of a new AlSb/InAs heterojunction bipolar transistor is studied. The electrons are injected into a p-InAs base across the AlSb/InAs heterojunction. The conduction-band discontinuity at this heterojunction is sufficiently large so that energy of the electrons injected into InAs exceeds the threshold for generating electron-hole pairs by impact ionization. The observed incremental common base current at zero collector-base bias decreases and becomes negative as the emitter current is increased, thus providing direct evidence for impact ionization entirely by band-edge discontinuities.

  4. On the choice of a head element for low-noise bipolar transistor amplifier

    International Nuclear Information System (INIS)

    Krasnokutskij, R.N.; Kurchaninov, L.L.; Fedyakin, N.N.; Shuvalov, R.S.

    1988-01-01

    The measurement results of equivalent noise charge (ENC) for KT382 transistor depending on detector capacity, formation duration and collector current are given. It is shown that the measurement results for this transistor in good agreement with calculations according to the noise model, time-consuming ENC measurements can be replaced by preliminary transistor rejection according to the distributed base resistance, current gain and simple calculations. In applications in the field of nuclear electronics the KT382 transistor enables to attain the same noise parameters as NE578, NE021 transistors (Japan) and it can be recommended for using as a head element of amplifiers

  5. Perspective analysis of tri gate germanium tunneling field-effect transistor with dopant segregation region at source/drain

    Science.gov (United States)

    Liu, Liang-kui; Shi, Cheng; Zhang, Yi-bo; Sun, Lei

    2017-04-01

    A tri gate Ge-based tunneling field-effect transistor (TFET) has been numerically studied with technology computer aided design (TCAD) tools. Dopant segregated Schottky source/drain is applied to the device structure design (DS-TFET). The characteristics of the DS-TFET are compared and analyzed comprehensively. It is found that the performance of n-channel tri gate DS-TFET with a positive bias is insensitive to the dopant concentration and barrier height at n-type drain, and that the dopant concentration and barrier height at a p-type source considerably affect the device performance. The domination of electron current in the entire BTBT current of this device accounts for this phenomenon and the tri-gate DS-TFET is proved to have a higher performance than its dual-gate counterpart.

  6. A Label-Free Immunosensor for IgG Based on an Extended-Gate Type Organic Field Effect Transistor

    Directory of Open Access Journals (Sweden)

    Tsukuru Minamiki

    2014-09-01

    Full Text Available A novel biosensor for immunoglobulin G (IgG detection based on an extended-gate type organic field effect transistor (OFET has been developed that possesses an anti-IgG antibody on its extended-gate electrode and can be operated below 3 V. The titration results from the target IgG in the presence of a bovine serum albumin interferent, clearly exhibiting a negative shift in the OFET transfer curve with increasing IgG concentration. This is presumed to be due an interaction between target IgG and the immobilized anti-IgG antibody on the extended-gate electrode. As a result, a linear range from 0 to 10 µg/mL was achieved with a relatively low detection limit of 0.62 µg/mL (=4 nM. We believe that these results open up opportunities for applying extended-gate-type OFETs to immunosensing.

  7. Constructing Diodes and Transistors for Ultracold Atoms

    Science.gov (United States)

    Pepino, Ronald; Cooper, John; Anderson, Dana; Holland, Murray

    2008-05-01

    The ultracold atom-optical analogy to electronic systems is presented, along with the master equation formalism that is applied to this novel physical context of system-reservoir interactions. The proposed formalism lends itself quite readily to not only the study of atomtronic systems, but also transport properties of ultracold atoms in optical lattices. We demonstrate how these systems can be configured so that they emulate the behavior of the electronic diode, field effect transistor (FET), and bipolar junction transistor (BJT). The behavior of simple logic gates: namely, the AND and OR gates are follow as direct consequences of the atomtronic BJTs.

  8. Plasmonic terahertz detection by a double-grating-gate field-effect transistor structure with an asymmetric unit cell

    Science.gov (United States)

    Popov, V. V.; Fateev, D. V.; Otsuji, T.; Meziani, Y. M.; Coquillat, D.; Knap, W.

    2011-12-01

    Plasmonic terahertz detection by a double-grating gate field-effect transistor structure with an asymmetric unit cell is studied theoretically. Detection responsivity exceeding 8 kV/W at room temperature in the photovoltaic response mode is predicted for strong asymmetry of the structure unit cell. This value of the responsivity is an order of magnitude greater than reported previously for the other types of uncooled plasmonic terahertz detectors. Such enormous responsivity can be obtained without using any supplementary antenna elements because the double-grating gate acts as an aerial matched antenna that effectively couples the incoming terahertz radiation to plasma oscillations in the structure channel.

  9. Nine-channel mid-power bipolar pulse generator based on a field programmable gate array

    Energy Technology Data Exchange (ETDEWEB)

    Haylock, Ben, E-mail: benjamin.haylock2@griffithuni.edu.au; Lenzini, Francesco; Kasture, Sachin; Fisher, Paul; Lobino, Mirko [Centre for Quantum Dynamics, Griffith University, Brisbane (Australia); Queensland Micro and Nanotechnology Centre, Griffith University, Brisbane (Australia); Streed, Erik W. [Centre for Quantum Dynamics, Griffith University, Brisbane (Australia); Institute for Glycomics, Griffith University, Gold Coast (Australia)

    2016-05-15

    Many channel arbitrary pulse sequence generation is required for the electro-optic reconfiguration of optical waveguide networks in Lithium Niobate. Here we describe a scalable solution to the requirement for mid-power bipolar parallel outputs, based on pulse patterns generated by an externally clocked field programmable gate array. Positive and negative pulses can be generated at repetition rates up to 80 MHz with pulse width adjustable in increments of 1.6 ns across nine independent outputs. Each channel can provide 1.5 W of RF power and can be synchronised with the operation of other components in an optical network such as light sources and detectors through an external clock with adjustable delay.

  10. The Optimization of Gate All Around-L-Shaped Bottom Select Transistor in 3D NAND Flash Memory.

    Science.gov (United States)

    Zou, Xingqi; Jin, Lei; Jiang, Dandan; Zhang, Yu; Chen, Guoxing; Xia, Zhiliang; Huo, Zongliang

    2018-08-01

    In this work, the GAA (Gate All Around) L-Shaped bottom select transistor (BSG) in 3D NAND Flash Memory has been investigated. Different methods are proposed to optimize its performance from viewpoints of process and structure. BSG in 3D NAND is a novel device structure with two connected transistors: one is horizontal MOSFET (regarded as convention MOSFET) and one is vertical MOSFET (regarded as GAA transistor). With implant dose increasing in vertical channel, BSG Vth has much more tighter Vt distribution, which is beneficial for boosting potential improvement and program disturbance suppression. Meanwhile, BSG corner rounding is proposed to improve the characteristic of BSG. Experiment and TCAD simulation data are matches quite well, giving a way to improve cell characteristics distribution and self-boosting potential control in high density 3D NAND array.

  11. Modelling of nanoscale multi-gate transistors affected by atomistic interface roughness

    Science.gov (United States)

    Nagy, Daniel; Aldegunde, Manuel; Elmessary, Muhammad A.; García-Loureiro, Antonio J.; Seoane, Natalia; Kalna, Karol

    2018-04-01

    Interface roughness scattering (IRS) is one of the major scattering mechanisms limiting the performance of non-planar multi-gate transistors, like Fin field-effect transistors (FETs). Here, two physical models (Ando’s and multi-sub-band) of electron scattering with the interface roughness induced potential are investigated using an in-house built 3D finite element ensemble Monte Carlo simulation toolbox including parameter-free 2D Schrödinger equation quantum correction that handles all relevant scattering mechanisms within highly non-equilibrium carrier transport. Moreover, we predict the effect of IRS on performance of FinFETs with realistic channel cross-section shapes with respect to the IRS correlation length (Λ) and RMS height (Δ_RMS ). The simulations of the n-type SOI FinFETs with the multi-sub-band IRS model shows its very strong effect on electron transport in the device channel compared to the Ando’s model. We have also found that the FinFETs are strongly affected by the IRS in the ON-region. The limiting effect of the IRS significantly increases as the Fin width is reduced. The FinFETs with channel orientation are affected more by the IRS than those with the crystal orientation. Finally, Λ and Δ_RMS are shown to affect the device performance similarly. A change in values by 30% (Λ) or 20% (Δ_RMS ) results in an increase (decrease) of up to 13% in the drive current.

  12. Gate Tunable Transport in Graphene/MoS2/(Cr/Au Vertical Field-Effect Transistors

    Directory of Open Access Journals (Sweden)

    Ghazanfar Nazir

    2017-12-01

    Full Text Available Two-dimensional materials based vertical field-effect transistors have been widely studied due to their useful applications in industry. In the present study, we fabricate graphene/MoS2/(Cr/Au vertical transistor based on the mechanical exfoliation and dry transfer method. Since the bottom electrode was made of monolayer graphene (Gr, the electrical transport in our Gr/MoS2/(Cr/Au vertical transistors can be significantly modified by using back-gate voltage. Schottky barrier height at the interface between Gr and MoS2 can be modified by back-gate voltage and the current bias. Vertical resistance (Rvert of a Gr/MoS2/(Cr/Au transistor is compared with planar resistance (Rplanar of a conventional lateral MoS2 field-effect transistor. We have also studied electrical properties for various thicknesses of MoS2 channels in both vertical and lateral transistors. As the thickness of MoS2 increases, Rvert increases, but Rplanar decreases. The increase of Rvert in the thicker MoS2 film is attributed to the interlayer resistance in the vertical direction. However, Rplanar shows a lower value for a thicker MoS2 film because of an excess of charge carriers available in upper layers connected directly to source/drain contacts that limits the conduction through layers closed to source/drain electrodes. Hence, interlayer resistance associated with these layers contributes to planer resistance in contrast to vertical devices in which all layers contribute interlayer resistance.

  13. Radiation effects in a CMOS/SOS/Al-Gate D/A converter and on-chip diagnostic transistors

    International Nuclear Information System (INIS)

    Brucker, G.J.; Heagerty, W.

    1976-01-01

    This paper presents the results obtained from total dose and transient radiation tests on a CMOS/SOS/Al-Gate D/A converter and on-chip diagnostic transistors. Samples were irradiated by cobalt-60 gamma rays under worst-case conditions, and by 10-MeV electron pulses of 50-ns and 4.4-μs duration. Devices were fabricated with three different insulators; the two discussed here are standard wet oxide and a pyrogenic oxide. Test transistors on the D/A chips made it possible to diagnose the failure modes of the converter and to evaluate some special designs. These consisted of standard edge p- and n-channel transistors, edgeless units, edgeless tetrode transistors, and an edgeless type transmission gate with a diode clamp from substrate to gate. The total dose results indicate that the pyrogenic oxide increased the failure dose of the operational amplifier portion of the converter from 10 3 rads (Si) to 2 x 10 6 rads (Si); however, the sample and hold failed after exposure to a low level of 10 3 rads (Si). Test devices indicated this to be due to the radiation-induced leakage current of the transmission gate which discharges the sample and hold capacitor. The diode clamp decreased the threshold voltage shifts and the leakage currents. The edgeless devices improved the device performance because of a more abrupt turn-on. Narrow-pulse test data indicated that the edgeless units produced less photocurrent than the edge units by about a factor of three to four. Converter upset levels are less than or equal to 10 9 rads/s due to precision requirements which make a few millivolt transients untenable

  14. Low Temperature Characterization of PMOS-type Gate-all-around Silicon nanowire FETs as single-hole-transistors

    Science.gov (United States)

    Hong, B. H.; Hwang, S. W.; Lee, Y. Y.; Son, M. H.; Ahn, D.; Cho, K. H.; Yeo, K. H.; Kim, D.-W.; Jin, G. Y.; Park, D.

    2011-12-01

    We report the single hole tunneling characteristics observed from a PMOS-type gate-all-around silicon nanowire field-effect-transistor with the radius 5 nm and the length 44 nm. The total capacitance of the quantum dot obtained from the measured Coulomb oscillations and Coulomb diamonds matches with the ideal capacitance of the silicon cylinder. It suggests that the observed single hole tunneling is originated from the fabricated structure.

  15. Modeling of subthreshold characteristics of short channel junctionless cylindrical surrounding-gate nanowire metal–oxide–silicon field effect transistors

    International Nuclear Information System (INIS)

    Jin, Xiaoshi; Liu, Xi; Lee, Jung-Hee; Lee, Jong-Ho

    2014-01-01

    A subthreshold model of short-channel junctionless field effect transistors with cylindrical surrounding-gate nanowire structure has been proposed. It was based on an approximated solution of two-dimensional Poisson's equation. The derivation of this model was introduced and the accuracy of the proposed models have been verified by comparison with both previous models and the SILVACO Atlas TCAD simulation results, which show good agreement. (paper)

  16. Plasmonic terahertz detection by a double-grating-gate field-effect transistor structure with an asymmetric unit cell

    OpenAIRE

    Popov, V. V.; Fateev, D. V.; Otsuji, T.; Meziani, Y. M.; Coquillat, D.; Knap, W.

    2011-01-01

    Plasmonic terahertz detection by a double-grating gate field-effect transistor structure with an asymmetric unit cell is studied theoretically. Detection responsivity exceeding 8 kV/W at room temperature in the photovoltaic response mode is predicted for strong asymmetry of the structure unit cell. This value of the responsivity is an order of magnitude greater than reported previously for the other types of uncooled plasmonic terahertz detectors. Such enormous responsivity can be obtained wi...

  17. Charge-plasma based dual-material and gate-stacked architecture of junctionless transistor for enhanced analog performance

    Science.gov (United States)

    Amin, S. Intekhab; Sarin, R. K.

    2015-12-01

    Charge plasma based doping-less dual material double gate (DL-DMDG) junctionless transistor (JLT) is proposed. This paper also demonstrate the potential impact of gate stacking (GS) (high-k + Sio2) on DL-DMDG (DL-GSDMDG) JLT device. The efficient charge plasma is created in an intrinsic silicon film to form n + source/drain (S/D) by selecting proper work function of S/D electrode which helps to minimize threshold voltage fluctuation that occurs in a heavily doped JLT device. The analog performance parameters are analyzed for both the device structures. Results are also compared with conventional dual material double gate (DMDG) and gate stacked dual material double gate (GSDMDG) JLT devices. A DL-DMDG JLT device shows improved early voltage (VEA), intrinsic gain (AV = gm/gDS) and reduced output conductance (gDS) as compared to conventional DMDG and GSDMDG JLT devices. These values are further improved for DL-GSDMDG JLT. The effect of control gate length (L1) for a fixed gate length (L = L1+L2) are also analyzed.

  18. Two-zone SiGe base heterojunction bipolar charge plasma transistor for next generation analog and RF applications

    Science.gov (United States)

    Bramhane, Lokesh Kumar; Singh, Jawar

    2017-01-01

    For next generation terahertz applications, heterojunction bipolar transistor (HBT) with reduced dimensions and charge plasma (CP) can be a potential candidate due to simplified and inexpensive process. In this paper, a symmetric lateral two-zone SiGe base heterojunction bipolar charge plasma transistor (HBCPT) with an extruded (extended) base is proposed and its performance at circuit level is studied. The linearly graded electric field in the proposed HBCPT provides improved self gain (β) and cut-off frequency (fT). Two-dimensional (2-D) TCAD and small-signal model based simulations of the proposed HBCPT demonstrates high self gain β 35-172.93 and fT of 1-4 THz for different device parameters. Moreover, fT of 1104.9 GHz and β of 35 can be achieved by decreasing Nb up to 8.2 ×1017cm-3 . Although, fT of 2 THz and 4 THz can also be achieved by reducing the base resistance up to 10 Ω and increasing the emitter/collector length up to 63 nm, respectively. The small-signal analysis of common-emitter amplifier based on the proposed HBCPT demonstrate high voltage gain of 50.11 as compared to conventional HBT (18.1).

  19. Radiation effects in advanced multiple gate and silicon-on-insulator transistors

    International Nuclear Information System (INIS)

    Simoen, E.; Gaillardin, M.; Paillet, P.; Reed, R.A.; Schrimpf, R.D.; Alles, M.L.; El-Mamouni, F.; Fleetwood, D.M.; Griffoni, A.; Claeys, C.

    2013-01-01

    The aim of this review paper is to describe in a comprehensive manner the current understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and FinFET CMOS technologies. Total Ionizing Dose (TID) response, heavy-ion micro-dose effects and single-event effects (SEEs) will be discussed. It is shown that a very high TID tolerance can be achieved by narrow-fin SOI FinFET architectures, while bulk FinFETs may exhibit similar TID response to the planar devices. Due to the vertical nature of FinFETs, a specific heavy-ion response can be obtained, whereby the angle of incidence becomes highly important with respect to the vertical sidewall gates. With respect to SEE, the buried oxide in the SOI FinFETs suppresses the diffusion tails from the charge collection in the substrate compared to the planar bulk FinFET devices. Channel lengths and fin widths are now comparable to, or smaller than the dimensions of the region affected by the single ionizing ions or lasers used in testing. This gives rise to a high degree of sensitivity to individual device parameters and source-drain shunting during ion-beam or laser-beam SEE testing. Simulations are used to illuminate the mechanisms observed in radiation testing and the progress and needs for the numerical modeling/ simulation of the radiation response of advanced SOI and FinFET transistors are highlighted. (authors)

  20. Low-Temperature Solution-Processed Gate Dielectrics for High-Performance Organic Thin Film Transistors

    Directory of Open Access Journals (Sweden)

    Jaekyun Kim

    2015-10-01

    Full Text Available A low-temperature solution-processed high-k gate dielectric layer for use in a high-performance solution-processed semiconducting polymer organic thin-film transistor (OTFT was demonstrated. Photochemical activation of sol-gel-derived AlOx films under 150 °C permitted the formation of a dense film with low leakage and relatively high dielectric-permittivity characteristics, which are almost comparable to the results yielded by the conventionally used vacuum deposition and high temperature annealing method. Octadecylphosphonic acid (ODPA self-assembled monolayer (SAM treatment of the AlOx was employed in order to realize high-performance (>0.4 cm2/Vs saturation mobility and low-operation-voltage (<5 V diketopyrrolopyrrole (DPP-based OTFTs on an ultra-thin polyimide film (3-μm thick. Thus, low-temperature photochemically-annealed solution-processed AlOx film with SAM layer is an attractive candidate as a dielectric-layer for use in high-performance organic TFTs operated at low voltages.

  1. Low operating voltage n-channel organic field effect transistors using lithium fluoride/PMMA bilayer gate dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Kumar, S.; Dhar, A., E-mail: adhar@phy.iitkgp.ernet.in

    2015-10-15

    Highlights: • Alternative to chemically crosslinking of PMMA to achieve low leakage in provided. • Effect of LiF in reducing gate leakage through the OFET device is studied. • Effect of gate leakage on transistor performance has been investigated. • Low voltage operable and low temperature processed n-channel OFETs were fabricated. - Abstract: We report low temperature processed, low voltage operable n-channel organic field effect transistors (OFETs) using N,N′-Dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C{sub 8}) organic semiconductor and poly(methylmethacrylate) (PMMA)/lithium fluoride (LiF) bilayer gate dielectric. We have studied the role of LiF buffer dielectric in effectively reducing the gate leakage through the device and thus obtaining superior performance in contrast to the single layer PMMA dielectric devices. The bilayer OFET devices had a low threshold voltage (V{sub t}) of the order of 5.3 V. The typical values of saturation electron mobility (μ{sub s}), on/off ratio and inverse sub-threshold slope (S) for the range of devices made were estimated to be 2.8 × 10{sup −3} cm{sup 2}/V s, 385, and 3.8 V/decade respectively. Our work thus provides a potential substitution for much complicated process of chemically crosslinking PMMA to achieve low leakage, high capacitance, and thus low operating voltage OFETs.

  2. Effect of thin emitter set-back layer on GaAs delta-doped emitter bipolar junction transistor

    Science.gov (United States)

    Lew, K. L.; Yoon, S. F.

    2005-05-01

    GaAs delta-doped emitter bipolar junction transistors (δ-BJT) with different emitter set-back layer thicknesses of 10to50nm were fabricated to study the emitter set-back layer thickness effect on device dc performance. We found that the current gain decreases following decrease in the emitter set-back layer thickness. A detailed analysis was performed to explain this phenomenon, which is believed to be caused by reduction of the effective barrier height in the δ-BJT. This is due to change in the electric-field distribution in the delta-doped structure caused by the built-in potential of the base-emitter (B-E ) junction. Considering the recombination and barrier height reduction effects, the thickness of the emitter set-back layer should be designed according to the B-E junction depletion width with a tolerance of ±5nm. The dc performance of a δ-BJT designed based on this criteria is compared to that of a Al0.25Ga0.75As /GaAs heterojunction bipolar transistor (HBT). Both devices employed base doping of 2×1019cm-3 and base-to-emitter doping ratio of 40. Large emitter area (AE≈1.6×10-5cm-2) and small emitter area (AE≈1.35×10-6cm-2) device current gains of 40 and 20, respectively, were obtained in both types of transistors passivated by (NH4)2S treatment. The measured current gain of the GaAs δ-BJT is the highest reported for a homojunction device with such high base-to-emitter doping ratio normally used in HBT devices.

  3. Improvement of Current Gain in Triple Ion Implanted 4H-SiC Bipolar Junction Transistor with Etched Extrinsic Base Regions

    Science.gov (United States)

    Tajima, Taku; Nakamura, Tadashi; Satoh, Masataka; Nakamura, Tohru

    We demonstrate triple ion implanted 4H-SiC bipolar junction transistor (BJT). By etching the extrinsic base regions using inductively coupled plasma dry etching, the characteristics of triple ion implanted 4H-SiC BJT were significantly improved. Maximum common emitter current gain was improved from 1.7 to 7.5.

  4. Performance of organic field effect transistors with high-k gate oxide after application of consecutive bias stress

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Sunwoo; Choi, Changhwan; Lee, Kilbock [Department of Materials Science and Engineering, Hanyang University, Seoul, 133-791 (Korea, Republic of); Cho, Joong Hwee [Department of Embedded Systems Engineering,University of Incheon, Incheon 406-722 (Korea, Republic of); Ko, Ki-Young [Korea Institute of Patent Information, Seoul, 146-8 (Korea, Republic of); Ahn, Jinho, E-mail: jhahn@hanyang.ac.kr [Department of Materials Science and Engineering, Hanyang University, Seoul, 133-791 (Korea, Republic of)

    2012-10-30

    We report the effect of consecutive electrical stress on the performance of organic field effect transistors (OFETs). Sputtered aluminum oxide (Al{sub 2}O{sub 3}) and hafnium oxide (HfO{sub 2}) were used as gate oxide layers. After the electrical stress, the threshold voltage, which strongly depends on bulk defects, was remarkably shifted to the negative direction, while the other performance characteristics of OFETs such as on-current, transconductance and mobility, which are sensitive to interface defects, were slightly decreased. This result implies that the defects in the bulk layer are significantly affected compared to the defects in the interface layer. Thus, it is important to control the defects in the pentacene bulk layer in order to maintain the good reliabilities of pentacene devices. Those defects in HfO{sub 2} gate oxide devices were larger compared to those in Al{sub 2}O{sub 3} gate oxide devices.

  5. Nano-Floating Gate Memory Devices Composed of ZnO Thin-Film Transistors on Flexible Plastics

    Directory of Open Access Journals (Sweden)

    Park Byoungjun

    2011-01-01

    Full Text Available Abstract Nano-floating gate memory devices were fabricated on a flexible plastic substrate by a low-temperature fabrication process. The memory characteristics of ZnO-based thin-film transistors with Al nanoparticles embedded in the gate oxides were investigated in this study. Their electron mobility was found to be 0.18 cm2/V·s and their on/off ratio was in the range of 104–105. The threshold voltages of the programmed and erased states were negligibly changed up to 103 cycles. The flexibility, memory properties, and low-temperature fabrication of the nano-floating gate memory devices described herein suggest that they have potential applications for future flexible integrated electronics.

  6. Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

    Energy Technology Data Exchange (ETDEWEB)

    Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn; Chi, Li-Feng, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn [Jiangsu Key Laboratory for Carbon-Based Functional Materials and Devices, Institute of Functional Nano and Soft Materials (FUNSOM), Soochow University, Suzhou, Jiangsu 215123 (China)

    2015-03-23

    Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

  7. Fabrication and independent control of patterned polymer gate for a few-layer WSe2 field-effect transistor

    Directory of Open Access Journals (Sweden)

    Sung Ju Hong

    2016-08-01

    Full Text Available We report the fabrication of a patterned polymer electrolyte for a two-dimensional (2D semiconductor, few-layer tungsten diselenide (WSe2 field-effect transistor (FET. We expose an electron-beam in a desirable region to form the patterned structure. The WSe2 FET acts as a p-type semiconductor in both bare and polymer-covered devices. We observe a highly efficient gating effect in the polymer-patterned device with independent gate control. The patterned polymer gate operates successfully in a molybdenum disulfide (MoS2 FET, indicating the potential for general applications to 2D semiconductors. The results of this study can contribute to large-scale integration and better flexibility in transition metal dichalcogenide (TMD-based electronics.

  8. Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

    International Nuclear Information System (INIS)

    Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin; Chi, Li-Feng; Wang, Sui-Dong

    2015-01-01

    Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process

  9. Influence of layout design and on-wafer heatspreaders on the thermal behavior of fully-isolated bipolar transistors: Part I - Static analysis

    Science.gov (United States)

    Russo, Salvatore; Spina, Luigi La; d'Alessandro, Vincenzo; Rinaldi, Niccolò; Nanver, Lis K.

    2010-08-01

    The impact of layout parameters on the steady-state thermal behavior of bipolar junction transistors (BJTs) with full dielectric isolation is extensively analyzed by accurate DC measurements and 3-D numerical simulations. The influence of the aspect ratio of the emitter stripe, as well as the consequences of device scaling, are investigated from a thermal viewpoint. Furthermore, the beneficial effect of implementing aluminum nitride (AlN) thin-film heatspreaders is examined. It is shown that the silicon area surrounding the heat source, as well as the distance to high-thermal-conductivity regions, can have a significant impact on the thermal behavior. A recently proposed scaling rule for the thermal resistance - fully compatible with advanced transistor models - is successfully applied to a series of test BJT structures provided that a simple parameter optimization is carried out. Based on this, some generally applicable guidelines are given to effectively downscale fully-isolated bipolar transistors without significantly worsening the thermal issues.

  10. Insulated gate and surface passivation structures for GaN-based power transistors

    Science.gov (United States)

    Yatabe, Zenji; Asubar, Joel T.; Hashizume, Tamotsu

    2016-10-01

    Recent years have witnessed GaN-based devices delivering their promise of unprecedented power and frequency levels and demonstrating their capability as an able replacement for Si-based devices. High-electron-mobility transistors (HEMTs), a key representative architecture of GaN-based devices, are well-suited for high-power and high frequency device applications, owing to highly desirable III-nitride physical properties. However, these devices are still hounded by issues not previously encountered in their more established Si- and GaAs-based devices counterparts. Metal-insulator-semiconductor (MIS) structures are usually employed with varying degrees of success in sidestepping the major problematic issues such as excessive leakage current and current instability. While different insulator materials have been applied to GaN-based transistors, the properties of insulator/III-N interfaces are still not fully understood. This is mainly due to the difficulty of characterizing insulator/AlGaN interfaces in a MIS HEMT because of the two resulting interfaces: insulator/AlGaN and AlGaN/GaN, making the potential modulation rather complicated. Although there have been many reports of low interface-trap densities in HEMT MIS capacitors, several papers have incorrectly evaluated their capacitance-voltage (C-V) characteristics. A HEMT MIS structure typically shows a 2-step C-V behavior. However, several groups reported C-V curves without the characteristic step at the forward bias regime, which is likely to the high-density states at the insulator/AlGaN interface impeding the potential control of the AlGaN surface by the gate bias. In this review paper, first we describe critical issues and problems including leakage current, current collapse and threshold voltage instability in AlGaN/GaN HEMTs. Then we present interface properties, focusing on interface states, of GaN MIS systems using oxides, nitrides and high-κ dielectrics. Next, the properties of a variety of AlGaN/GaN MIS

  11. Insulated gate and surface passivation structures for GaN-based power transistors

    International Nuclear Information System (INIS)

    Yatabe, Zenji; Asubar, Joel T; Hashizume, Tamotsu

    2016-01-01

    Recent years have witnessed GaN-based devices delivering their promise of unprecedented power and frequency levels and demonstrating their capability as an able replacement for Si-based devices. High-electron-mobility transistors (HEMTs), a key representative architecture of GaN-based devices, are well-suited for high-power and high frequency device applications, owing to highly desirable III-nitride physical properties. However, these devices are still hounded by issues not previously encountered in their more established Si- and GaAs-based devices counterparts. Metal–insulator–semiconductor (MIS) structures are usually employed with varying degrees of success in sidestepping the major problematic issues such as excessive leakage current and current instability. While different insulator materials have been applied to GaN-based transistors, the properties of insulator/III-N interfaces are still not fully understood. This is mainly due to the difficulty of characterizing insulator/AlGaN interfaces in a MIS HEMT because of the two resulting interfaces: insulator/AlGaN and AlGaN/GaN, making the potential modulation rather complicated. Although there have been many reports of low interface-trap densities in HEMT MIS capacitors, several papers have incorrectly evaluated their capacitance–voltage ( C – V ) characteristics. A HEMT MIS structure typically shows a 2-step C – V behavior. However, several groups reported C – V curves without the characteristic step at the forward bias regime, which is likely to the high-density states at the insulator/AlGaN interface impeding the potential control of the AlGaN surface by the gate bias. In this review paper, first we describe critical issues and problems including leakage current, current collapse and threshold voltage instability in AlGaN/GaN HEMTs. Then we present interface properties, focusing on interface states, of GaN MIS systems using oxides, nitrides and high- κ dielectrics. Next, the properties of a

  12. A High-Performance Top-Gated Graphene Field-Effect Transistor with Excellent Flexibility Enabled by an iCVD Copolymer Gate Dielectric.

    Science.gov (United States)

    Oh, Joong Gun; Pak, Kwanyong; Kim, Choong Sun; Bong, Jae Hoon; Hwang, Wan Sik; Im, Sung Gap; Cho, Byung Jin

    2018-03-01

    A high-performance top-gated graphene field-effect transistor (FET) with excellent mechanical flexibility is demonstrated by implementing a surface-energy-engineered copolymer gate dielectric via a solvent-free process called initiated chemical vapor deposition. The ultrathin, flexible copolymer dielectric is synthesized from two monomers composed of 1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane and 1-vinylimidazole (VIDZ). The copolymer dielectric enables the graphene device to exhibit excellent dielectric performance and substantially enhanced mechanical flexibility. The p-doping level of the graphene can be tuned by varying the polar VIDZ fraction in the copolymer dielectric, and the Dirac voltage (V Dirac ) of the graphene FET can thus be systematically controlled. In particular, the V Dirac approaches neutrality with higher VIDZ concentrations in the copolymer dielectric, which minimizes the carrier scattering and thereby improves the charge transport of the graphene device. As a result, the graphene FET with 20 nm thick copolymer dielectrics exhibits field-effect hole and electron mobility values of over 7200 and 3800 cm 2 V -1 s -1 , respectively, at room temperature. These electrical characteristics remain unchanged even at the 1 mm bending radius, corresponding to a tensile strain of 1.28%. The formed gate stack with the copolymer gate dielectric is further investigated for high-frequency flexible device applications. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  13. Improved methods of forming monolithic integrated circuits having complementary bipolar transistors

    Science.gov (United States)

    Bohannon, R. O., Jr.; Cashion, W. F.; Stehlin, R. A.

    1971-01-01

    Two new processes form complementary transistors in monolithic semiconductor circuits, require fewer steps /infusions/ than previous methods, and eliminate such problems as nonuniform h sub FE distribution, low yield, and large device formation.

  14. A study on III-nitride recessed-gate field-effect transistors using a remote-oxygen-plasma treatment

    International Nuclear Information System (INIS)

    Lee, Y-C; Kao, T-T; Shen, S-C

    2015-01-01

    We report a comparative study of the device performance of III-nitride (III-N) heterojunction field-effect transistors (HFETs) and metal-insulator-semiconductor field-effect transistors (MISFETs). The influence of a remote-oxygen-plasma treatment was investigated. The plasma-treated recessed-gate HFETs and MISFETs show normally-off characteristics with higher peak transconductance, lower sub-threshold slope, smaller hysteresis. An on-off ratio greater than 2.2E11 with a significant suppression of gate leakage can be achieved in plasma-treated III-N MISFETs. A drain current transient measurement was performed to analyze the traps in these devices and possible origins of these traps are studied. Six traps with characteristic time constants (τ) ranging from 180 s to 3 ms are identified in both HFETs and MISFETs, in addition to a trap which is associated with the ALD-grown gate dielectrics for the MISFETs. The results suggest that improved device performance in these plasma-treated III-N FETs is attributed to the reduced trap states with τ < 400 ms, which are located on III-N surfaces. The slower traps (τ > 2 s) cannot be reduced by the plasma treatment and are related to the oxygen and carbon impurities and the buffer traps in the bulk semiconductors. (paper)

  15. Normally-off fully recess-gated GaN metal-insulator-semiconductor field-effect transistor using Al2O3/Si3N4 bilayer as gate dielectrics

    Science.gov (United States)

    Wang, Hongyue; Wang, Jinyan; Liu, Jingqian; Li, Mengjun; He, Yandong; Wang, Maojun; Yu, Min; Wu, Wengang; Zhou, Yang; Dai, Gang

    2017-10-01

    By a self-terminating gate recess etching technique, a normally-off fully recess-gated GaN metal-insulator-semiconductor field-effect transistor (MISFET) was fabricated using Al2O3/Si3N4 bilayer as gate dielectrics. Owing to the high breakdown electric field (˜10 MV/cm) of the gate dielectrics, the device exhibits a large gate swing of 18 V, a high threshold voltage of 1.7 V (at I D = 100 µA/mm), a large maximum drain current of 534 mA/mm, a gate leakage current lower than 20 nA/mm in the whole gate swing, and a high OFF-state breakdown voltage of 1282 V. Furthermore, owing to the high gate overdrive (V GS - V TH), the on-resistance of the device only increases by 5.4% under a constant stress of V GS/V DS = 18 V/1 V.

  16. Lateral protonic/electronic hybrid oxide thin-film transistor gated by SiO2 nanogranular films

    International Nuclear Information System (INIS)

    Zhu, Li Qiang; Chao, Jin Yu; Xiao, Hui

    2014-01-01

    Ionic/electronic interaction offers an additional dimension in the recent advancements of condensed materials. Here, lateral gate control of conductivities of indium-zinc-oxide (IZO) films is reported. An electric-double-layer (EDL) transistor configuration was utilized with a phosphorous-doped SiO 2 nanogranular film to provide a strong lateral electric field. Due to the strong lateral protonic/electronic interfacial coupling effect, the IZO EDL transistor could operate at a low-voltage of 1 V. A resistor-loaded inverter is built, showing a high voltage gain of ∼8 at a low supply voltage of 1 V. The lateral ionic/electronic coupling effects are interesting for bioelectronics and portable electronics

  17. A self-amplified transistor immunosensor under dual gate operation: highly sensitive detection of hepatitis B surface antigen

    Science.gov (United States)

    Lee, I.-K.; Jeun, M.; Jang, H.-J.; Cho, W.-J.; Lee, K. H.

    2015-10-01

    Ion-sensitive field-effect transistors (ISFETs), although they have attracted considerable attention as effective immunosensors, have still not been adopted for practical applications owing to several problems: (1) the poor sensitivity caused by the short Debye screening length in media with high ion concentration, (2) time-consuming preconditioning processes for achieving the highly-diluted media, and (3) the low durability caused by undesirable ions such as sodium chloride in the media. Here, we propose a highly sensitive immunosensor based on a self-amplified transistor under dual gate operation (immuno-DG ISFET) for the detection of hepatitis B surface antigen. To address the challenges in current ISFET-based immunosensors, we have enhanced the sensitivity of an immunosensor by precisely tailoring the nanostructure of the transistor. In the pH sensing test, the immuno-DG ISFET showed superior sensitivity (2085.53 mV per pH) to both standard ISFET under single gate operation (58.88 mV per pH) and DG ISFET with a non-tailored transistor (381.14 mV per pH). Moreover, concerning the detection of hepatitis B surface antigens (HBsAg) using the immuno-DG ISFET, we have successfully detected trace amounts of HBsAg (22.5 fg mL-1) in a non-diluted 1× PBS medium with a high sensitivity of 690 mV. Our results demonstrate that the proposed immuno-DG ISFET can be a biosensor platform for practical use in the diagnosis of various diseases.Ion-sensitive field-effect transistors (ISFETs), although they have attracted considerable attention as effective immunosensors, have still not been adopted for practical applications owing to several problems: (1) the poor sensitivity caused by the short Debye screening length in media with high ion concentration, (2) time-consuming preconditioning processes for achieving the highly-diluted media, and (3) the low durability caused by undesirable ions such as sodium chloride in the media. Here, we propose a highly sensitive immunosensor

  18. Temperature Effects on a-IGZO Thin Film Transistors Using HfO2 Gate Dielectric Material

    Directory of Open Access Journals (Sweden)

    Yu-Hsien Lin

    2014-01-01

    Full Text Available This study investigated the temperature effect on amorphous indium gallium zinc oxide (a-IGZO thin film transistors (TFTs using hafnium oxide (HfO2 gate dielectric material. HfO2 is an attractive candidate as a high-κ dielectric material for gate oxide because it has great potential to exhibit superior electrical properties with a high drive current. In the process of integrating the gate dielectric and IGZO thin film, postannealing treatment is an essential process for completing the chemical reaction of the IGZO thin film and enhancing the gate oxide quality to adjust the electrical characteristics of the TFTs. However, the hafnium atom diffused the IGZO thin film, causing interface roughness because of the stability of the HfO2 dielectric thin film during high-temperature annealing. In this study, the annealing temperature was optimized at 200°C for a HfO2 gate dielectric TFT exhibiting high mobility, a high ION/IOFF ratio, low IOFF current, and excellent subthreshold swing (SS.

  19. Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

    Directory of Open Access Journals (Sweden)

    Minkyu Chun

    2015-05-01

    Full Text Available We investigated the effects of top gate voltage (VTG and temperature (in the range of 25 to 70 oC on dual-gate (DG back-channel-etched (BCE amorphous-indium-gallium-zinc-oxide (a-IGZO thin film transistors (TFTs characteristics. The increment of VTG from -20V to +20V, decreases the threshold voltage (VTH from 19.6V to 3.8V and increases the electron density to 8.8 x 1018cm−3. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on VTG. At VTG of 20V, the mobility decreases from 19.1 to 15.4 cm2/V ⋅ s with increasing temperature, showing a metallic conduction. On the other hand, at VTG of - 20V, the mobility increases from 6.4 to 7.5cm2/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.

  20. Modelling and Realization of a Water-Gated Field Effect Transistor (WG-FET) Using 16-nm-Thick Mono-Si Film.

    Science.gov (United States)

    Sonmez, Bedri Gurkan; Ertop, Ozan; Mutlu, Senol

    2017-09-22

    We introduced a novel water-gated field effect transistor (WG-FET) which uses 16-nm-thick mono-Si film as active layer. WG-FET devices use electrical double layer (EDL) as gate insulator and operate under 1 V without causing any electrochemical reactions. Performance parameters based on voltage distribution on EDL are extracted and current-voltage relations are modelled. Both probe- and planar-gate WG-FETs with insulated and uninsulated source-drain electrodes are simulated, fabricated and tested. Best on/off ratios are measured for probe-gate devices as 23,000 A/A and 85,000 A/A with insulated and uninsulated source-drain electrodes, respectively. Planar-gate devices with source-drain insulation had inferior on/off ratio of 1,100 A/A with 600 μm gate distance and it decreased to 45 A/A when gate distance is increased to 3000 μm. Without source-drain electrode insulation, proper transistor operation is not obtained with planar-gate devices. All measurement results were in agreement with theoretical models. WG-FET is a promising device platform for microfluidic applications where sensors and read-out circuits can be integrated at transistor level.

  1. The Aluminum-Free P-n-P InGaAsN Double Heterojunction Bipolar Transistors

    Energy Technology Data Exchange (ETDEWEB)

    CHANG,PING-CHIH; LI,N.Y.; BACA,ALBERT G.; MONIER,C.; LAROCHE,J.R.; HOU,H.Q.; REN,F.; PEARTON,S.J.

    2000-08-01

    The authors have demonstrated an aluminum-free P-n-P GaAs/InGaAsN/GaAs double heterojunction bipolar transistor (DHBT). The device has a low turn-on voltage (V{sub ON}) that is 0.27 V lower than in a comparable P-n-p AlGaAs/GaAs HBT. The device shows near-ideal D. C. characteristics with a current gain ({beta}) greater than 45. The high-speed performance of the device are comparable to a similar P-n-p AlGaAs/GaAs HBT, with f{sub T} and f{sub MAX} values of 12 GHz and 10 GHz, respectively. This device is very suitable for low-power complementary HBT circuit applications, while the aluminum-free emitter structure eliminates issues typically associated with AlGaAs.

  2. EMP injection damage effects of a bipolar transistor and its relationship between the injecting voltage and energy

    International Nuclear Information System (INIS)

    Xi Xiaowen; Chai Changchun; Ren Xingrong; Yang Yintang; Zhang Bing; Hong Xiao

    2010-01-01

    The response of a bipolar transistor (BJT) under a square-wave electromagnetic pulse (EMP) with different injecting voltages is investigated. Adopting the curve fitting method, the relationship between the burnout time, the damage energy and the injecting voltage is obtained. Research shows that the damage energy is not a constant value, but changes with the injecting voltage level. By use of the device simulator Medici, the internal behavior of the burned device is analyzed. Simulation results indicate that the variation of the damage energy with injecting voltage is caused by the distribution change of hot spot position under different injection levels. Therefore, the traditional way to evaluate the trade-off between the burnout time and the injecting voltage is not comprehensive due to the variation of the damage energy. (semiconductor devices)

  3. SEMICONDUCTOR DEVICES: EMP injection damage effects of a bipolar transistor and its relationship between the injecting voltage and energy

    Science.gov (United States)

    Xiaowen, Xi; Changchun, Chai; Xingrong, Ren; Yintang, Yang; Bing, Zhang; Xiao, Hong

    2010-04-01

    The response of a bipolar transistor (BJT) under a square-wave electromagnetic pulse (EMP) with different injecting voltages is investigated. Adopting the curve fitting method, the relationship between the burnout time, the damage energy and the injecting voltage is obtained. Research shows that the damage energy is not a constant value, but changes with the injecting voltage level. By use of the device simulator Medici, the internal behavior of the burned device is analyzed. Simulation results indicate that the variation of the damage energy with injecting voltage is caused by the distribution change of hot spot position under different injection levels. Therefore, the traditional way to evaluate the trade-off between the burnout time and the injecting voltage is not comprehensive due to the variation of the damage energy.

  4. EMP injection damage effects of a bipolar transistor and its relationship between the injecting voltage and energy

    Energy Technology Data Exchange (ETDEWEB)

    Xi Xiaowen; Chai Changchun; Ren Xingrong; Yang Yintang; Zhang Bing; Hong Xiao, E-mail: xixiaowen523103@163.co [Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi' an 710071 (China)

    2010-04-15

    The response of a bipolar transistor (BJT) under a square-wave electromagnetic pulse (EMP) with different injecting voltages is investigated. Adopting the curve fitting method, the relationship between the burnout time, the damage energy and the injecting voltage is obtained. Research shows that the damage energy is not a constant value, but changes with the injecting voltage level. By use of the device simulator Medici, the internal behavior of the burned device is analyzed. Simulation results indicate that the variation of the damage energy with injecting voltage is caused by the distribution change of hot spot position under different injection levels. Therefore, the traditional way to evaluate the trade-off between the burnout time and the injecting voltage is not comprehensive due to the variation of the damage energy. (semiconductor devices)

  5. Influence of the external component on the damage of the bipolar transistor induced by the electromagnetic pulse

    Energy Technology Data Exchange (ETDEWEB)

    Xi Xiaowen; Chai Changchun; Ren Xingrong; Yang Yintang; Ma Zhenyang; Wang Jing, E-mail: xixiaowen523103@163.co [Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi' an 710071 (China)

    2010-07-15

    A study on the influence of the external resistor and the external voltage source during the injection of the electromagnetic pulse (EMP) into the bipolar transistor (BJT) is carried out. Research shows that the increase of the external resistor R{sub b} at base makes the burnout time of the device decrease slightly, the increase of the external voltage source V{sub be} at base can aid the damage of the device when the magnitude of the injecting voltage is relatively low and has little influence when the magnitude is sufficiently high causing the device appearing the PIN structure damage, and the increase of the external resistor R{sub e} can remarkably reduce the voltage drops added to the device and improve the durability of the device. In the final analysis, the effect of the external circuit component on the BJT damage is the influence on the condition which makes the device appear current-mode second breakdown.

  6. Influence of the external component on the damage of the bipolar transistor induced by the electromagnetic pulse

    Science.gov (United States)

    Xiaowen, Xi; Changchun, Chai; Xingrong, Ren; Yintang, Yang; Zhenyang, Ma; Jing, Wang

    2010-07-01

    A study on the influence of the external resistor and the external voltage source during the injection of the electromagnetic pulse (EMP) into the bipolar transistor (BJT) is carried out. Research shows that the increase of the external resistor Rb at base makes the burnout time of the device decrease slightly, the increase of the external voltage source Vbe at base can aid the damage of the device when the magnitude of the injecting voltage is relatively low and has little influence when the magnitude is sufficiently high causing the device appearing the PIN structure damage, and the increase of the external resistor Re can remarkably reduce the voltage drops added to the device and improve the durability of the device. In the final analysis, the effect of the external circuit component on the BJT damage is the influence on the condition which makes the device appear current-mode second breakdown.

  7. 2D device-level simulation study of strained-Si pnp heterojunction bipolar transistors on virtual substrates

    Science.gov (United States)

    Jankovic, N. D.; O'Neill, A.

    2004-02-01

    A novel strained-Si pnp heterojunction bipolar transistor (HBT) design, suitable for virtual substrate technology, is proposed that is inherently free from the detrimental valence band barrier effects usually encountered in conventional SiGe pnp HBTs on silicon. It takes advantage of the heterojunction formed between a strained-Si layer and a relaxed SiGe buffer (virtual substrate), whose associated valence band offset appears favorable for minority hole transport at the base/collector junction. From two-dimensional (2D) numerical simulation, it is found that the newly proposed strained-Si pnp HBT substantially outperforms the equivalent BJT on a silicon substrate in terms of DC and high-frequency characteristics. A threefold increase in maximum current gain β, a fourfold improvement in peak ft and a 2.5 times increase in peak fmax are predicted for strained-Si pnp HBTs on a 50% Ge virtual substrate in comparison with identical conventional silicon pnp BJTs.

  8. Simultaneous integration of MOS and bipolar transistors. Application to a fast complex memory

    International Nuclear Information System (INIS)

    Mackowiak, E.; Montier, M.

    1975-01-01

    A technology allowing for a simultaneous integration of two devices T MOS and T BIP (bipolar T) is presented. The technological results obtained and an application in the field of fast complex memories are given [fr

  9. Annealing effects and DLTS study on PNP silicon bipolar junction transistors irradiated by 20 MeV Br ions

    Science.gov (United States)

    Liu, Chaoming; Li, Xingji; Yang, Jianqun; Bollmann, Joachim

    2014-01-01

    Isochronal anneal sequences have been carried out on 3CG130 silicon PNP bipolar junction transistors (BJTs) irradiated with 20 MeV bromine (Br) heavy ions. The Gummel curve was utilized to characterize the annealing behavior of defects in both the emitter-base depletion region and the neutral base. The results show that the base current (IB) decreases with the increasing annealing temperature, while the collector current (IC) keeps invariably. The current gain varies slightly, when the annealing temperature (TA) is lower than 500 K, while varies rapidly at TA>550 K, and the current gain of the 3CG130 BJT annealing at 700 K almost restore to that of the pre-radiation transistor. The deep level transient spectroscopy (DLTS) data was used to assign the relative magnitude of each of the important defects. Based on the in situ electrical measurement and DLTS spectra, it is clear that the V2(+/0) trap is the main contribution to the degradation of current gain after the 20 MeV Br ions irradiation. The V2(+/0) peak has many characteristics expected for the current gain degradation.

  10. Annealing effects and DLTS study on PNP silicon bipolar junction transistors irradiated by 20 MeV Br ions

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Chaoming [School of Materials Science and Engineering, Harbin Institute of Technology, Harbin 150001 (China); Li, Xingji, E-mail: lxj0218@hit.edu.cn [School of Materials Science and Engineering, Harbin Institute of Technology, Harbin 150001 (China); Yang, Jianqun [School of Materials Science and Engineering, Harbin Institute of Technology, Harbin 150001 (China); Bollmann, Joachim [Institute of Electronics and Sensor Materials, TU Bergakademie, Freiberg 71691 (Germany)

    2014-01-21

    Isochronal anneal sequences have been carried out on 3CG130 silicon PNP bipolar junction transistors (BJTs) irradiated with 20 MeV bromine (Br) heavy ions. The Gummel curve was utilized to characterize the annealing behavior of defects in both the emitter-base depletion region and the neutral base. The results show that the base current (I{sub B}) decreases with the increasing annealing temperature, while the collector current (I{sub C}) keeps invariably. The current gain varies slightly, when the annealing temperature (T{sub A}) is lower than 500 K, while varies rapidly at T{sub A}>550 K, and the current gain of the 3CG130 BJT annealing at 700 K almost restore to that of the pre-radiation transistor. The deep level transient spectroscopy (DLTS) data was used to assign the relative magnitude of each of the important defects. Based on the in situ electrical measurement and DLTS spectra, it is clear that the V{sub 2}(+/0) trap is the main contribution to the degradation of current gain after the 20 MeV Br ions irradiation. The V{sub 2}(+/0) peak has many characteristics expected for the current gain degradation.

  11. Memory and learning behaviors mimicked in nanogranular SiO2-based proton conductor gated oxide-based synaptic transistors.

    Science.gov (United States)

    Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

    2013-11-07

    In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements.

  12. Impact of interface layer and metal workfunction on device performance of ferroelectric junctionless cylindrical surrounding gate transistors

    Science.gov (United States)

    Mehta, Hema; Kaur, Harsupreet

    2017-11-01

    In this work, the negative capacitance phenomenon exhibited by ferroelectric materials has been incorporated in Junctionless Cylindrical Surrounding Gate (JLCSG) transistor and an analytical model has been developed to study the electrical characteristics of the device by taking into account Landau Khalatnikov equation along with parabolic potential approximation. Using the derived model various electrical parameters such as potential, gain, drain current, gate capacitance etc have been obtained. Silicon doped hafnium oxide has been incorporated as the ferroelectric material and exhaustive study has been done to study the impact of interfacial layer and metal workfunction on device characteristics as these have significant impact on the performance of Junctionless devices. It has been demonstrated by analytical model and TCAD simulations that by incorporating ferroelectric layer and optimizing metal work function and interfacial layer thickness, the device performance of JLCSG can be substantially improved.

  13. High carrier mobility of CoPc wires based field-effect transistors using bi-layer gate dielectric

    Directory of Open Access Journals (Sweden)

    Murali Gedda

    2013-11-01

    Full Text Available Polyvinyl alcohol (PVA and anodized Al2O3 layers were used as bi-layer gate for the fabrication of cobalt phthalocyanine (CoPc wire base field-effect transistors (OFETs. CoPc wires were grown on SiO2 surfaces by organic vapor phase deposition method. These devices exhibit a field-effect carrier mobility (μEF value of 1.11 cm2/Vs. The high carrier mobility for CoPc molecules is attributed to the better capacitive coupling between the channel of CoPc wires and the gate through organic-inorganic dielectric layer. Our measurements also demonstrated the way to determine the thicknesses of the dielectric layers for a better process condition of OFETs.

  14. High carrier mobility of CoPc wires based field-effect transistors using bi-layer gate dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Gedda, Murali; Obaidulla, Sk. Md. [Department of Physics, Indian Institute of Technology Guwahati, Guwahati-781039 (India); Subbarao, Nimmakayala V. V. [Centre for Nano Technology, Indian Institute of Technology Guwahati, Guwahati-781039 (India); Goswami, Dipak K. [Department of Physics, Indian Institute of Technology Guwahati, Guwahati-781039 (India); Centre for Nano Technology, Indian Institute of Technology Guwahati, Guwahati-781039 (India)

    2013-11-15

    Polyvinyl alcohol (PVA) and anodized Al{sub 2}O{sub 3} layers were used as bi-layer gate for the fabrication of cobalt phthalocyanine (CoPc) wire base field-effect transistors (OFETs). CoPc wires were grown on SiO{sub 2} surfaces by organic vapor phase deposition method. These devices exhibit a field-effect carrier mobility (μ{sub EF}) value of 1.11 cm{sup 2}/Vs. The high carrier mobility for CoPc molecules is attributed to the better capacitive coupling between the channel of CoPc wires and the gate through organic-inorganic dielectric layer. Our measurements also demonstrated the way to determine the thicknesses of the dielectric layers for a better process condition of OFETs.

  15. Flexible, Low-Cost Sensor Based on Electrolyte Gated Carbon Nanotube Field Effect Transistor for Organo-Phosphate Detection.

    Science.gov (United States)

    Bhatt, Vijay Deep; Joshi, Saumya; Becherer, Markus; Lugli, Paolo

    2017-05-18

    A flexible enzymatic acetylcholinesterase biosensor based on an electrolyte-gated carbon nanotube field effect transistor is demonstrated. The enzyme immobilization is done on a planar gold gate electrode using 3-mercapto propionic acid as the linker molecule. The sensor showed good sensing capability as a sensor for the neurotransmitter acetylcholine, with a sensitivity of 5.7 μA/decade, and demonstrated excellent specificity when tested against interfering analytes present in the body. As the flexible sensor is supposed to suffer mechanical deformations, the endurance of the sensor was measured by putting it under extensive mechanical stress. The enzymatic activity was inhibited by more than 70% when the phosphate-buffered saline (PBS) buffer was spiked with 5 mg/mL malathion (an organophosphate) solution. The biosensor was successfully challenged with tap water and strawberry juice, demonstrating its usefulness as an analytical tool for organophosphate detection.

  16. Experimental examination of tunneling paths in SiGe/Si gate-normal tunneling field-effect transistors

    Science.gov (United States)

    Glass, S.; von den Driesch, N.; Strangio, S.; Schulte-Braucks, C.; Rieger, T.; Narimani, K.; Buca, D.; Mantl, S.; Zhao, Q. T.

    2017-12-01

    The benefits of a gate-normal tunneling architecture in enhancing the on-current and average subthreshold swing of tunneling field-effect transistors were scrutinized in experiment through careful physical analysis of a Si0.50Ge0.50/Si heterostructure. In accordance with theoretical predictions, it is confirmed that the on-current is governed by line tunneling scaling with the source-gate overlap area of our devices. Our analysis identifies the early onset of parasitic diagonal tunneling paths as most detrimental for a low average subthreshold swing. By counter doping the channel, this onset can be shifted favorably, permitting low average subthreshold swings down to 87 mV/dec over four decades of drain current and high on-off current ratios exceeding 106.

  17. Extreme Temperature Performance of Automotive-Grade Small Signal Bipolar Junction Transistors

    Science.gov (United States)

    Boomer, Kristen; Damron, Benny; Gray, Josh; Hammoud, Ahmad

    2018-01-01

    Electronics designed for space exploration missions must display efficient and reliable operation under extreme temperature conditions. For example, lunar outposts, Mars rovers and landers, James Webb Space Telescope, Europa orbiter, and deep space probes represent examples of missions where extreme temperatures and thermal cycling are encountered. Switching transistors, small signal as well as power level devices, are widely used in electronic controllers, data instrumentation, and power management and distribution systems. Little is known, however, about their performance in extreme temperature environments beyond their specified operating range; in particular under cryogenic conditions. This report summarizes preliminary results obtained on the evaluation of commercial-off-the-shelf (COTS) automotive-grade NPN small signal transistors over a wide temperature range and thermal cycling. The investigations were carried out to establish a baseline on functionality of these transistors and to determine suitability for use outside their recommended temperature limits.

  18. Mathematical Models of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field effect Transistor

    Science.gov (United States)

    Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

    2013-01-01

    Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric- semiconductor field effect transistors (MOSFETs) are developed in this paper. The models are compared against data collected with MOSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth as well as differences and advantages as compared to the performance of each circuit using a MOSFET.

  19. Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High-k Gate Dielectric Materials

    Directory of Open Access Journals (Sweden)

    Yu-Hsien Lin

    2015-01-01

    Full Text Available We investigated amorphous indium gallium zinc oxide (a-IGZO thin film transistors (TFTs using different high-k gate dielectric materials such as silicon nitride (Si3N4 and aluminum oxide (Al2O3 at low temperature process (<300°C and compared them with low temperature silicon dioxide (SiO2. The IGZO device with high-k gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, postannealing treatment is an essential process for completing the process. The chemical reaction of the high-k/IGZO interface due to heat formation in high-k/IGZO materials results in reliability issue. We also used the voltage stress for testing the reliability for the device with different high-k gate dielectric materials and explained the interface effect by charge band diagram.

  20. Hysteresis behaviour of low-voltage organic field-effect transistors employing high dielectric constant polymer gate dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Se Hyun; Yun, Won Min; Kwon, Oh-Kwan; Hong, Kipyo; Yang, Chanwoo; Park, Chan Eon [POSTECH Organic Electronics Laboratory, Department of Chemical Engineering, Pohang University of Science and Technology, Pohang 790-784 (Korea, Republic of); Choi, Woon-Seop, E-mail: cep@postech.ac.k, E-mail: wschoi@hoseo.ed [School of Display Engineering, Hoseo University, Asan City, Chungnam 336-795 (Korea, Republic of)

    2010-11-24

    Here, we report on the fabrication of low-voltage-operating pentacene-based organic field-effect transistors (OFETs) that utilize crosslinked cyanoethylated poly(vinyl alcohol) (CR-V) gate dielectrics. The crosslinked CR-V-based OFET could be operated successfully at low voltages (below 4 V), but abnormal behaviour during device operation, such as uncertainty in the field-effect mobility ({mu}) and hysteresis, was induced by the slow polarization of moieties embedded in the gate dielectric (e.g. polar functionalities, ionic impurities, water and solvent molecules). In an effort to improve the stability of OFET operation, we measured the dependence of {mu} and hysteresis on dielectric thickness, CR-V crosslinking conditions and sweep rate of the gate bias. The influence of the CR-V surface properties on {mu}, hysteresis, and the structural and morphological features of the pentacene layer grown on the gate dielectric was characterized and compared with the properties of pentacene grown on a polystyrene surface.

  1. Electron energy dissipation model of gate dielectric progressive breakdown in n- and p-channel field effect transistors

    Science.gov (United States)

    Lombardo, S.; Wu, E. Y.; Stathis, J. H.

    2017-08-01

    We report the data and a model showing that the energy loss experienced by the carriers flowing through breakdown spots is the primary cause of progressive breakdown spot growth. The experiments are performed in gate dielectrics of metal-oxide-semiconductor (MOS) devices subjected to accelerated high electric field constant voltage stress under inversion conditions. The model is analytical and contains few free parameters of clear physical meaning. This is compared to a large set of data on breakdown transients at various oxide thicknesses, stress voltages, and temperatures, both in cases of n-channel and p-channel transistors and polycrystalline Si/oxynitride/Si and metal gate/high k dielectric/Si gate stacks. The basic idea is that the breakdown transient is due to the growth of one or more filaments in the dielectric promoted by electromigration driven by the energy lost by the electrons traveling through the breakdown spots. Both cases of polycrystalline Si/oxynitride/Si and metal gate/high-k dielectric/Si MOS structures are investigated. The best fit values of the model to the data, reported and discussed in the paper, consistently describe a large set of data. The case of simultaneous growth of multiple progressive breakdown spots in the same device is also discussed in detail.

  2. Electro-oxidized epitaxial graphene channel field-effect transistors with single-walled carbon nanotube thin film gate electrode.

    Science.gov (United States)

    Ramesh, Palanisamy; Itkis, Mikhail E; Bekyarova, Elena; Wang, Feihu; Niyogi, Sandip; Chi, Xiaoliu; Berger, Claire; de Heer, Walt; Haddon, Robert C

    2010-10-20

    We report the effect of electrochemical oxidation in nitric acid on the electronic properties of epitaxial graphene (EG) grown on silicon carbide substrates; we demonstrate the availability of an additional reaction channel in EG, which is not present in graphite but which facilitates the introduction of the reaction medium into the graphene galleries during electro-oxidation. The device performance of the chemically processed graphene was studied by patterning the EG wafers with two geometrically identical macroscopic channels; the electro-oxidized channel showed a logarithmic increase of resistance with decreasing temperature, which is ascribed to the scattering of charge carriers in a two-dimensional electronic gas, rather than the presence of an energy gap at the Fermi level. Field-effect transistors were fabricated on the electro-oxidized and pristine graphene channels using single-walled carbon nanotube thin film top gate electrodes, thereby allowing the study of the effect of oxidative chemistry on the transistor performance of EG. The electro-oxidized channel showed higher values for the on-off ratio and the mobility of the graphene field-effect transistor, which we ascribe to the availability of high-quality internal graphene layers after electro-oxidation of the more defective top layers. Thus, the present oxidative process provides a clear contrast with previously demonstrated covalent chemistry in which sp(3) hybridized carbon atoms are introduced into the graphitic transport layer of the lattice by carbon-carbon bond formation, thereby opening an energy gap.

  3. Effect of Coercive Voltage and Charge Injection on Performance of a Ferroelectric-Gate Thin-Film Transistor

    Directory of Open Access Journals (Sweden)

    P. T. Tue

    2013-01-01

    Full Text Available We adopted a lanthanum oxide capping layer between semiconducting channel and insulator layers for fabrication of a ferroelectric-gate thin-film transistor memory (FGT which uses solution-processed indium-tin-oxide (ITO and lead-zirconium-titanate (PZT film as a channel layer and a gate insulator, respectively. Good transistor characteristics such as a high “on/off” current ratio, high channel mobility, and a large memory window of 108, 15.0 cm2 V−1 s−1, and 3.5 V were obtained, respectively. Further, a correlation between effective coercive voltage, charge injection effect, and FGT’s memory window was investigated. It is found that the charge injection from the channel to the insulator layer, which occurs at a high electric field, dramatically influences the memory window. The memory window’s enhancement can be explained by a dual effect of the capping layer: (1 a reduction of the charge injection and (2 an increase of effective coercive voltage dropped on the insulator.

  4. The effect of fluorine in low thermal budget polysilicon emitters for SiGe heterojunction bipolar transistors

    International Nuclear Information System (INIS)

    Schiz, F.J.W.

    1999-03-01

    This thesis investigates the behaviour of fluorine in two types of polysilicon emitter. In the first type the emitter is deposited at 610 deg. C as polycrystalline silicon (p-Si). In the second type the emitter is deposited at 560 deg. C as amorphous silicon (α-Si). The amorphous silicon 1 then regrows to polysilicon during subsequent high temperature anneals. Remarkably different behaviour of fluorine is seen in as-deposited α-Si and as-deposited p-Si emitter bipolar transistors. In the most extreme case, fluorine-implanted as-deposited p-Si devices show a base current increase by a factor of 1.5 and equivalent α-Si devices a base current decrease by a factor of 10.0 compared to unimplanted devices. Cross-section TEM observations are made to study the structure of the polysilicon/silicon interface and SIMS measurements to study the distribution of the fluorine in the polysilicon. The TEM results correlate well with the electrical results and show that fluorine accelerates interfacial oxide breakup. Furthermore, they show that for a given thermal budget, more interfacial oxide breakup and thus more epitaxial regrowth is obtained for transistors with p-Si polysilicon emitters. This results in a lower emitter resistance, for example as low as 12Ωμm 2 for as-deposited p-Si devices. The base current suppression for as-deposited α-Si devices is explained by fluorine passivation of trapping states at the interface. Analysis of the fluorine SIMS profiles suggests that they do not resemble normal diffusion profiles, but are due to fluorine trapped at defects. It is shown that a reciprocal relationship exists between the fluorine dose in the bulk polysilicon layer and the fluorine dose at the interface. In as-deposited α-Si devices, there is more fluorine trapped at defects in the bulk polysilicon layer, so less is available to diffuse to the interface. As a result there is less interfacial oxide breakup and more passivation in the as-deposited α-Si devices. These

  5. In-situ Raman Spectroscopy of the Graphene / Water Interface of a Solution-Gated Field Effect Transistor: Electron-Phonon Coupling and Spectroelectrochemistry

    OpenAIRE

    Binder, J.; Urban, J. M.; Stepniewski, R.; Strupinski, W.; Wysmolek, A.

    2014-01-01

    We present a novel measurement approach which combines the electrical characterization of solution-gated field effect transistors based on epitaxial bilayer graphene on 4H-SiC (0001) with simultaneous Raman spectroscopy. By changing the gate voltage, we observed Raman signatures related to the resonant electron-phonon coupling. An analysis of these Raman bands enabled the extraction of the geometrical capacitance of the system and an accurate calculation of the Fermi levels for bilayer graphe...

  6. Two Dimensional Modeling of III-V Heterojunction Gate All Around Tunnel Field Effect Transistor

    OpenAIRE

    Manjula Vijh; R.S. Gupta; Sujata Pandey

    2017-01-01

    Tunnel Field Effect Transistor is one of the extensively researched semiconductor devices, which has captured attention over the conventional Metal Oxide Semiconductor Field Effect Transistor. This device, due to its varied advantages, is considered in applications where devices are scaled down to deep sub-micron level. Like MOSFETs, many geometries of TFETs have been studied and analyzed in the past few years. This work, presents a two dimensional analytical model for a III-V Heterojunction ...

  7. IGBT convertor with active snubber for soft switching. [Insulated Gate Bipolar Transistor

    Science.gov (United States)

    Masserant, B. J.; Shriver, J.; Stuart, T. A.

    1991-01-01

    This full bridge dc-dc convertor with IGBTs uses zero voltage switching (ZVS) for one leg of the bridge and zero current switching (ZCS) for the other. It is shown that an active snubber greatly improves the performance over previous methods. Experimental results are shown for a 6 kW circuit switching at 20 kHz.

  8. Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

    Science.gov (United States)

    Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

    2016-01-01

    The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

  9. Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Wei, E-mail: wwei99@jlu.edu.cn; Han, Jinhua; Ying, Jun; Xiang, Lanyi; Xie, Wenfa [State Key Laboratory on Integrated Optoelectronics, College of Electronic Science and Engineering, Jilin University, 2699 Qianjin Street, Changchun 130012 (China)

    2014-09-22

    Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm{sup 2}/V s. The unidirectional shift of turn-on voltage (V{sub on}) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (V{sub P}/V{sub E}) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered molecule orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm{sup 2}/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the V{sub P}/V{sub E} of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional V{sub on} shift. As a result, an enlarged memory window of 28.6 V at the V{sub P}/V{sub E} of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.

  10. Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

    International Nuclear Information System (INIS)

    Wang, Wei; Han, Jinhua; Ying, Jun; Xiang, Lanyi; Xie, Wenfa

    2014-01-01

    Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm 2 /V s. The unidirectional shift of turn-on voltage (V on ) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (V P /V E ) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered molecule orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm 2 /V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the V P /V E of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional V on shift. As a result, an enlarged memory window of 28.6 V at the V P /V E of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.

  11. Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

    Science.gov (United States)

    Wang, Wei; Han, Jinhua; Ying, Jun; Xiang, Lanyi; Xie, Wenfa

    2014-09-01

    Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm2/V s. The unidirectional shift of turn-on voltage (Von) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (VP/VE) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered molecule orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm2/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the VP/VE of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional Von shift. As a result, an enlarged memory window of 28.6 V at the VP/VE of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.

  12. Nondestructive characterization of RBSOA of high-power bipolar transistors. [Reverse-bias safe operating area

    Science.gov (United States)

    Jovanovic, M. M.; Lee, F. C.; Chen, D. Y.

    1986-01-01

    Reverse-bias safe operating area (RBSOA) of high-power Darlington transistors is characterized using a 120 A/1000 V nondestructive reverse-bias second breakdown tester designed and fabricated at Virginia Polytechnic Institute and State University. Elaborate RBSOA characteristics are generated with different forward/reverse base drives and collector current levels. The effects of elevated case temperature and second-base drive on RBSOA of four-terminal Darlington devices are also discussed.

  13. PMMA–SiO{sub 2} hybrid films as gate dielectric for ZnO based thin-film transistors

    Energy Technology Data Exchange (ETDEWEB)

    Morales-Acosta, M.D. [Centro de Investigación y de Estudios Avanzados del IPN, Unidad Querétaro, Apdo. Postal 1-798, Querétaro, Qro. 76001 (Mexico); Quevedo-López, M.A. [Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, TX 75083 (United States); Ramírez-Bon, R., E-mail: rrbon@qro.cinvestav.mx [Centro de Investigación y de Estudios Avanzados del IPN, Unidad Querétaro, Apdo. Postal 1-798, Querétaro, Qro. 76001 (Mexico)

    2014-08-01

    In this paper we report a low temperature sol–gel deposition process of PMMA–SiO{sub 2} hybrid films, with variable dielectric properties depending on the composition of the precursor solution, for applications to gate dielectric layers in field-effect thin film transistors (FE-TFT). The hybrid layers were processed by a modified sol–gel route using as precursors Tetraethyl orthosilicate (TEOS) and Methyl methacrylate (MMA), and 3-(Trimethoxysilyl)propyl methacrylate (TMSPM) as the coupling agent. Three types of hybrid films were processed with molar ratios of the precursors in the initial solution 1.0: 0.25, 0.50, 0.75: 1.0 for TEOS: TMSPM: MMA, respectively. The hybrid films were deposited by spin coating of the hybrid precursor solutions onto p-type Si (100) substrates and heat-treated at 90 °C for 24 h. The chemical bonding in the hybrid films was analyzed by Fourier Transform Infrared Spectroscopy to confirm their hybrid nature. The refractive index of the hybrid films as a function of the TMSPM coupling agent concentration, were determined from a simultaneous analysis of optical reflectance and spectroscopic ellipsometry experimental data. The PMMA–SiO{sub 2} hybrid films were studied as dielectric films using metal-insulator-metal structures. Capacitance–Voltage (C–V) and current–voltage (I–V) electrical methods were used to extract the dielectric properties of the different hybrid layers. The three types of hybrid films were tested as gate dielectric layers in thin film transistors with structure ZnO/PMMA–SiO{sub 2}/p-Si with a common bottom gate and patterned Al source/drain contacts, with different channel lengths. We analyzed the output electrical responses of the ZnO-based TFTs to determine their performance parameters as a function of channel length and hybrid gate dielectric layer. - Highlights: • PMMA–SiO{sub 2} hybrid films as dielectric material synthesized by sol–gel process at low temperature. • PMMA–SiO{sub 2

  14. A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under positive gate bias stress

    NARCIS (Netherlands)

    Niang, K.M.; Barquinha, P.M.C.; Martins, R.F.P.; Cobb, B.; Powell, M.J.; Flewitt, A.J.

    2016-01-01

    Thin film transistors (TFTs) employing an amorphous indium gallium zinc oxide (a-IGZO) channel layer exhibit a positive shift in the threshold voltage under the application of positive gate bias stress (PBS). The time and temperature dependence of the threshold voltage shift was measured and

  15. Interface passivation and trap reduction via hydrogen fluoride for molybdenum disulfide on silicon oxide back-gate transistors

    Science.gov (United States)

    Hu, Yaoqiao; San Yip, Pak; Tang, Chak Wah; Lau, Kei May; Li, Qiang

    2018-04-01

    Layered semiconductor molybdenum disulfide (MoS2) has recently emerged as a promising material for flexible electronic and optoelectronic devices because of its finite bandgap and high degree of gate control. Here, we report a hydrogen fluoride (HF) passivation technique for improving the carrier mobility and interface quality of chemical vapor deposited monolayer MoS2 on a SiO2/Si substrate. After passivation, the fabricated MoS2 back-gate transistors demonstrate a more than double improvement in average electron mobility, a reduced gate hysteresis gap of 3 V, and a low interface trapped charge density of ˜5.8 × 1011 cm-2. The improvements are attributed to the satisfied interface dangling bonds, thus a reduction of interface trap states and trapped charges. Surface x-ray photoelectron spectroscopy analysis and first-principles simulation were performed to verify the HF passivation effect. The results here highlight the necessity of a MoS2/dielectric passivation strategy and provides a viable route for enhancing the performance of MoS2 nano-electronic devices.

  16. Solution-gated graphene field effect transistors integrated in microfluidic systems and used for flow velocity detection.

    Science.gov (United States)

    He, Rong Xiang; Lin, Peng; Liu, Zhi Ke; Zhu, Hong Wei; Zhao, Xing Zhong; Chan, Helen L W; Yan, Feng

    2012-03-14

    Solution-gated graphene field effect transistors (SGGT) were integrated in microfluidic systems. The transfer characteristics of a SGGT with an Ag/AgCl gate electrode shifted horizontally with the change of the ionic concentration of KCl solution in the microchannel and the relationship can be fitted with the Nernst equation, which was attributed to the change of the potential drop at the Ag/AgCl electrode. Therefore the gate electrode is one important factor for the ion sensitive property of the SGGT. Then SGGTs were used as flow velocity sensors, which were based on measuring the streaming potentials in microfluidic channels. A linear relationship between the shift of the transfer curve of the SGGT and the flow velocity was obtained, indicating that the SGGT is a promising transducer for measuring flow velocity in a microchip. Since the streaming potential is influenced by the three physical quantities, including the flow velocity, the ionic strength of the fluid and the zeta potential of the substrate, the device can be used for sensing any one of the three quantities when the other two were known. It is noteworthy that SGGTs have been used for various types of chemical and biological sensors. Array of the devices integrated in multichannel microchips are expected to find many important applications in the lab-on-a-chip systems in the future. © 2012 American Chemical Society

  17. Detection of prostate-specific antigen with biomolecule-gated AlGaN/GaN high electron mobility transistors

    International Nuclear Information System (INIS)

    Li, Jia-dong; Miao, Bin; Wei, Xiao-wei; Xie, Jie; Wu, Dong-min; Cheng, Jun-jie; Zhang, Jin-cheng; Zhang, Zhi-qiang

    2014-01-01

    In order to improve the sensitivity of AlGaN/GaN high electron mobility transistor (HEMT) biosensors, a simple biomolecule-gated AlGaN/GaN HEMT structure was designed and successfully fabricated for prostate specific antigen (PSA) detection. UV/ozone was used to oxidize the GaN surface and then a 3-aminopropyl trimethoxysilane (APTES) self-assembled monolayer was bound to the sensing region. This monolayer serves as a binding layer for attachment of the prostate specific antibody (anti-PSA). The biomolecule-gated AlGaN/GaN HEMT sensor shows a rapid and sensitive response when the target prostate-specific antigen in buffer solution was added to the antibody-immobilized sensing area. The current change showed a logarithm relationship against the PSA concentration from 0.1 pg/ml to 0.993 ng/ml. The sensitivity of 0.215% is determined for 0.1 pg/ml PSA solution. The above experimental result of the biomolecule-gated AlGaN/GaN HEMT biosensor suggested that this biosensor might be a useful tool for prostate cancer screening. (paper)

  18. Comments on determination of bandgap narrowing from activation plots. [for bipolar transistors

    Science.gov (United States)

    Park, J.-S.; Neugroschel, A.; Lindholm, F. A.

    1986-01-01

    A determination is made of the temperature-dependence of emitter saturation current in bipolar devices which allows the derivation of a value for bandgap narrowing that is in better agreement with other determinations than previous results based on ohmic contact measurements of temperature dependence. The new values were obtained by varying the surface recombination velocity at the emitter surface. This improves accuracy by varying the minority carrier surface recombination velocity at the emitter contacts of otherwise indistinguishable emitters.

  19. Ferroelectric-gate field effect transistor memories device physics and applications

    CERN Document Server

    Ishiwara, Hiroshi; Okuyama, Masanori; Sakai, Shigeki; Yoon, Sung-Min

    2016-01-01

    This book provides comprehensive coverage of the materials characteristics, process technologies, and device operations for memory field-effect transistors employing inorganic or organic ferroelectric thin films. This transistor-type ferroelectric memory has interesting fundamental device physics and potentially large industrial impact. Among the various applications of ferroelectric thin films, the development of nonvolatile ferroelectric random access memory (FeRAM) has progressed most actively since the late 1980s and has achieved modest mass production levels for specific applications since 1995. There are two types of memory cells in ferroelectric nonvolatile memories. One is the capacitor-type FeRAM and the other is the field-effect transistor (FET)-type FeRAM. Although the FET-type FeRAM claims ultimate scalability and nondestructive readout characteristics, the capacitor-type FeRAMs have been the main interest for the major semiconductor memory companies, because the ferroelectric FET has fatal handic...

  20. Electrical performance of III-V gate-all-around nanowire transistors

    Science.gov (United States)

    Razavi, Pedram; Fagas, Giorgos

    2013-08-01

    The performance of III-V inversion-mode and junctionless nanowire field-effect transistors are investigated using quantum simulations and are compared with those of silicon devices. We show that at ultrascaled dimensions silicon can offer better electrical performance in terms of short-channel effects and drive current than other materials. This is explained simply by suppression of source-drain tunneling due to the higher effective mass, shorter natural length, and the higher density of states in the confined channel. We also confirm that III-V junctionless nanowire transistors are more immune to short-channel effects than conventional inversion-mode III-V nanowire field-effect transistors.

  1. Instrumentation for Gate Current Noise Measurements on sub-100 nm MOS Transistors

    CERN Document Server

    Gaioni, L; Ratti, L; Re, V; Speziali, V; Traversi, G

    2008-01-01

    This work describes a measuring system that was developed to characterize the gate current noise performances of CMOS devices with minimum feature size in the 100 nm span. These devices play an essential role in the design of present daymixedsignal integrated circuits, because of the advantages associated with the scaling process. The reduction in the gate oxide thickness brought about by CMOS technology downscaling leads to a non-negligible gate current due to direct tunneling phenomena; this current represents a noise source which requires an accurate characterization for optimum analog design. In this paper, two instruments able to perform measurements in two different ranges of gate current values will be discussed. Some of the results of gate current noise characterization will also be presented.

  2. Investigating degradation behavior of hole-trapping effect under static and dynamic gate-bias stress in a dual gate a-InGaZnO thin film transistor with etch stop layer

    Energy Technology Data Exchange (ETDEWEB)

    Liao, Po-Yung [Department of Physics, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang3708@gmail.com [Department of Physics, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan (China); Hsieh, Tien-Yu [Department of Physics, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Tsai, Ming-Yen; Chen, Bo-Wei; Chu, Ann-Kuo [Department of Photonics, National Sun Yat-Sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Chou, Cheng-Hsu; Chang, Jung-Fang [Product Technology Center, Chimei Innolux Corp., Tainan 741, Taiwan (China)

    2016-03-31

    The degree of degradation between the amorphous-indium–gallium–zinc oxide (a-IGZO) thin film transistor (TFT) using the top-gate only or bottom-gate only is compared. Under negative gate bias illumination stress (NBIS), the threshold voltage (V{sub T}) after bottom-gate NBIS monotonically shifts in the negative direction, whereas top-gate NBIS operation exhibits on-state current increases without V{sub T} shift. Such anomalous degradation behavior of NBIS under top-gate operation is due to hole-trapping in the etch stop layer above the central portion of the channel. These phenomena can be ascribed to the screening of the electric field by redundant source/drain electrodes. In addition, the device degradation of dual gate a-IGZO TFT stressed with different top gate pulse waveforms is investigated. It is observed that the degradation is dependent on the frequency of the top gate pulses. The V{sub T} shift increases with decreasing frequency, indicating the hole mobility of IGZO is low. - Highlights: • Static and dynamic gate bias stresses are imposed on dual gate InGaZnO TFTs. • Top-gate NBIS operation exhibits on-state current increases without VT shift. • The degradation behavior of top-gate NBIS is due to hole-trapping in the ESL. • The degradation is dependent on the frequency of the top gate pulses. • The V{sub T} shift increases with decreasing frequency of the top gate pulses.

  3. Three-terminal heterojunction bipolar transistor solar cell for high-efficiency photovoltaic conversion

    OpenAIRE

    Martí Vega, Antonio; Luque López, Antonio

    2015-01-01

    Here we propose, for the first time, a solar cell characterized by a semiconductor transistor structure (n/p/n or p/n/p) where the base?emitter junction is made of a high-bandgap semiconductor and the collector is made of a low-bandgap semiconductor. We calculate its detailed-balance efficiency limit and prove that it is the same one than that of a double-junction solar cell. The practical importance of this result relies on the simplicity of the structure that reduces the number of layers th...

  4. Single-electron effects in non-overlapped multiple-gate silicon-on-insulator metal-oxide-semiconductor field-effect transistors.

    Science.gov (United States)

    Lee, W; Su, P

    2009-02-11

    This paper systematically presents controlled single-electron effects in multiple-gate silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) with various gate lengths, fin widths, gate bias and temperature. Our study indicates that using the non-overlapped gate to source/drain structure as an approach to the single-electron transistor (SET) in MOSFETs is promising. Combining the advantage of gate control and the constriction of high source/drain resistances, single-electron effects are further enhanced using the multiple-gate architecture. From the presented results, downsizing multiple-gate SOI MOSFETs is needed for future room-temperature SET applications. Besides, the tunnel barriers and access resistances may need to be further optimized. Since the Coulomb blockade oscillation can be achieved in state-of-the-art complementary metal-oxide-semiconductor (CMOS) devices, it is beneficial to build SETs in low-power CMOS circuits for ultra-high-density purposes.

  5. Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

    KAUST Repository

    Fahad, Hossain M.

    2011-10-12

    We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

  6. Frequency-Stable Ionic-Type Hybrid Gate Dielectrics for High Mobility Solution-Processed Metal-Oxide Thin-Film Transistors

    Directory of Open Access Journals (Sweden)

    Jae Sang Heo

    2017-06-01

    Full Text Available In this paper, we demonstrate high mobility solution-processed metal-oxide thin-film transistors (TFTs by using a high-frequency-stable ionic-type hybrid gate dielectric (HGD. The HGD gate dielectric, a blend of sol-gel aluminum oxide (AlOx and poly(4-vinylphenol (PVP, exhibited high dielectric constant (ε~8.15 and high-frequency-stable characteristics (1 MHz. Using the ionic-type HGD as a gate dielectric layer, an minimal electron-double-layer (EDL can be formed at the gate dielectric/InOx interface, enhancing the field-effect mobility of the TFTs. Particularly, using the ionic-type HGD gate dielectrics annealed at 350 °C, InOx TFTs having an average field-effect mobility of 16.1 cm2/Vs were achieved (maximum mobility of 24 cm2/Vs. Furthermore, the ionic-type HGD gate dielectrics can be processed at a low temperature of 150 °C, which may enable their applications in low-thermal-budget plastic and elastomeric substrates. In addition, we systematically studied the operational stability of the InOx TFTs using the HGD gate dielectric, and it was observed that the HGD gate dielectric effectively suppressed the negative threshold voltage shift during the negative-illumination-bias stress possibly owing to the recombination of hole carriers injected in the gate dielectric with the negatively charged ionic species in the HGD gate dielectric.

  7. Long-Term Synaptic Plasticity Emulated in Modified Graphene Oxide Electrolyte Gated IZO-Based Thin-Film Transistors.

    Science.gov (United States)

    Yang, Yi; Wen, Juan; Guo, Liqiang; Wan, Xiang; Du, Peifu; Feng, Ping; Shi, Yi; Wan, Qing

    2016-11-09

    Emulating neural behaviors at the synaptic level is of great significance for building neuromorphic computational systems and realizing artificial intelligence. Here, oxide-based electric double-layer (EDL) thin-film transistors were fabricated using 3-triethoxysilylpropylamine modified graphene oxide (KH550-GO) electrolyte as the gate dielectrics. Resulting from the EDL effect and electrochemical doping between mobile protons and the indium-zinc-oxide channel layer, long-term synaptic plasticity was emulated in our devices. Synaptic functions including long-term memory, synaptic temporal integration, and dynamic filters were successfully reproduced. In particular, spike rate-dependent plasticity (SRDP), one of the basic learning rules of long-term plasticity in the neural network where the synaptic weight changes according to the rate of presynaptic spikes, was emulated in our devices. Our results may facilitate the development of neuromorphic computational systems.

  8. Low-voltage organic field-effect transistors (OFETs) with solution-processed metal-oxide as gate dielectric.

    Science.gov (United States)

    Su, Yaorong; Wang, Chengliang; Xie, Weiguang; Xie, Fangyan; Chen, Jian; Zhao, Ni; Xu, Jianbin

    2011-12-01

    In this study, low-voltage copper phthalocyanine (CuPc)-based organic field-effect transistors (OFETs) are demonstrated utilizing solution-processed bilayer high-k metal-oxide (Al(2)O(y)/TiO(x)) as gate dielectric. The high-k metal-oxide bilayer is fabricated at low temperatures (OFETs show high electric performance with high hole mobility of 0.06 cm(2)/(V s), threshold voltage of -0.5 V, on/off ration of 2 × 10(3) and a very small subthreshold slope of 160 mV/dec when operated at -1.5 V. Our study demonstrates a simple and robust approach that could be used to achieve low-voltage operation with solution-processed technique. © 2011 American Chemical Society

  9. Femtomolar detection of 2,4-dichlorophenoxyacetic acid herbicides via competitive immunoassays using microfluidic based carbon nanotube liquid gated transistor.

    Science.gov (United States)

    Wijaya, I Putu Mahendra; Nie, Tey Ju; Gandhi, Sonu; Boro, Robin; Palaniappan, Alagappan; Hau, Goh Wei; Rodriguez, Isabel; Suri, C Raman; Mhaisalkar, Subodh G

    2010-03-07

    Monitoring of environmental pollutants has become increasingly important due to concern over potential health and environmental impact inflicted by these chemicals. In this contribution, we focus on the development of an all-plastic biosensor comprising laminated single-walled carbon nanotubes as the active element and its conductance modulation in a liquid-gated field effect transistor, as the principle of transduction, for the detection of 2,4-dicholorophenoxy acetic acid (2,4-D) herbicide. The reported biosensor is capable of performing real-time label-free detection of analytes in liquid environment. This biosensor which relies on immunoassay principle for specificity is able to detect down to 500 fM levels of 2,4-D in soil samples.

  10. A strategy to minimize the sensing voltage drift error in a transistor biosensor with a nanoscale sensing gate

    Science.gov (United States)

    Son, Hyun Woo; Jeun, Minhong; Choi, Jaewon; Lee, Kwan Hyi

    2017-01-01

    An ion-sensitive field-effect transistor (ISFET) biosensor is thought to be the center of the next era of health diagnosis. However, questions are raised about its functions and reliability in liquid samples. Consequently, real-life clinical applications are few in number. In this study, we report a strategy to minimize the sensing signal drift error during bioanalyte detection in an ISFET biosensor. A nanoscale SnO2 thin film is used as a gate oxide layer (GOL), and the surface of the GOL is chemically modified for improving bioanalyte-specific binding and for reducing undesirable ion reactions in sample solutions. The ISFET biosensor with surface-modified GOL shows significantly reduced sensing signal error compared with an ISFET with bare GOL in both diluted and undiluted phosphate buffered saline solutions. PMID:28442905

  11. High Sensitivity pH Sensor Based on Porous Silicon (PSi Extended Gate Field-Effect Transistor

    Directory of Open Access Journals (Sweden)

    Naif H. Al-Hardan

    2016-06-01

    Full Text Available In this study, porous silicon (PSi was prepared and tested as an extended gate field-effect transistor (EGFET for pH sensing. The prepared PSi has pore sizes in the range of 500 to 750 nm with a depth of approximately 42 µm. The results of testing PSi for hydrogen ion sensing in different pH buffer solutions reveal that the PSi has a sensitivity value of 66 mV/pH that is considered a super Nernstian value. The sensor considers stability to be in the pH range of 2 to 12. The hysteresis values of the prepared PSi sensor were approximately 8.2 and 10.5 mV in the low and high pH loop, respectively. The result of this study reveals a promising application of PSi in the field for detecting hydrogen ions in different solutions.

  12. Compact modeling of nanoscale triple-gate junctionless transistors covering drift-diffusion to quasi-ballistic carrier transport

    Science.gov (United States)

    Oproglidis, T. A.; Karatsori, T. A.; Barraud, S.; Ghibaudo, G.; Dimitriadis, C. A.

    2018-04-01

    In this work, we extend our analytical compact model for nanoscale junctionless triple-gate (JL TG) MOSFETs, capturing carrier transport from drift-diffusion to quasi-ballistic regime. This is based on a simple formulation of the low-field mobility extracted from experimental data using the Y-function method, taking into account the ballistic carrier motion and an increased carrier scattering in process-induced defects near the source/drain regions. The case of a Schottky junction in non-ideal ohmic contact at the drain side was also taken into account by modifying the threshold voltage and ideality factor of the JL transistor. The model is validated with experimental data for n-channel JL TG MOSFETs with channel length varying from 95 down to 25 nm. It can be easily implemented as a compact model for use in Spice circuit simulators.

  13. Input Stage for Low-Voltage, Low-Noise Preamplifiers Based on a Floating-Gate MOS Transistor

    DEFF Research Database (Denmark)

    Igor, Mucha

    1997-01-01

    of the input stage is abolished and very-low-frequency signal can be handled. A preamplifier using the proposed input stage, optimized for lowest white noise operation has been fabricated in a 0.8 micron CMOS process. The circuit operates with a power supply of 1.5V and consumes only a little bias current.......A novel input stage for low-voltage, low-noise preamplifiers for integrated capacitive sensors is presented. The input stage of the preamplifier employs floating-gate MOS transistors which are capable of storing the operation point of the input stage over several years without any severe...... degradation of the performance of the circuit and without the need for a repeating programming. In this way the noise originating from any resistance previously used for the definition of the operating point is avoided completely and, moreover, by avoiding the input high-pass filter both the saturation...

  14. Non-ideal effect in 4H-SiC bipolar junction transistor with double Gaussian-doped base

    Science.gov (United States)

    Yuan, Lei; Zhang, Yu-Ming; Song, Qing-Wen; Tang, Xiao-Yan; Zhang, Yi-Men

    2015-06-01

    The non-ideal effect of 4H-SiC bipolar junction transistor (BJT) with a double Gaussian-doped base is characterized and simulated in this paper. By adding a specific interface model between SiC and SiO2, the simulation results are in good agreement with the experiment data. An obvious early effect is found from the output characteristic. As the temperature rises, the early voltage increases, while the current gain gradually decreases, which is totally different from the scenario of silicon BJT. With the same effective Gummel number in the base region, the double Gaussian-doped base structure can realize higher current gain than the single base BJT due to the built-in electric field, whereas the early effect will be more salient. Besides, the emitter current crowding effect is also analyzed. Due to the low sheet resistance in the first highly-doped base epilayer, the 4H-BJT with a double base has more uniform emitter current density across the base-emitter junction, leading to better thermal stability. Project supported by the National Natural Science Foundation of China (Grant Nos. 60876061 and 61234006), the Natural Science Foundation of Shaanxi Province, China (Grant No. 2013JQ8012), and the Doctoral Fund of the Ministry of Education of China (Grant Nos. 20130203120017 and 20110203110010).

  15. A novel 4H-SiC lateral bipolar junction transistor structure with high voltage and high current gain

    Science.gov (United States)

    Deng, Yong-Hui; Xie, Gang; Wang, Tao; Sheng, Kuang

    2013-09-01

    In this paper, a novel structure of a 4H-SiC lateral bipolar junction transistor (LBJT) with a base field plate and double RESURF in the drift region is presented. Collector-base junction depletion extension in the base region is restricted by the base field plate. Thin base as well as low base doping of the LBJT therefore can be achieved under the condition of avalanche breakdown. Simulation results show that thin base of 0.32 μm and base doping of 3 × 1017 cm-3 are obtained, and corresponding current gain is as high as 247 with avalanche breakdown voltage of 3309 V when the drift region length is 30 μm. Besides, an investigation of a 4H-SiC vertical BJT (VBJT) with comparable breakdown voltage (3357 V) shows that the minimum base width of 0.25 μm and base doping as high as 8 × 1017 cm-3 contribute to a maximum current gain of only 128.

  16. Simulation of energy and fluence dependence of heavy ion induced displacement damage factor in bipolar junction transistor

    Science.gov (United States)

    Kulkarni, S. R.; Ravindra, M.; Joshi, G. R.; Damle, R.

    2004-05-01

    This article presents the theoretical calculation of the variation of displacement damage factors as a function of energy and rad equivalent fluence in bipolar junction transistor for various particulate radiation viz ., He, Si, Cl, Ti, Ni, Br, Ag, I, and Au. The calculation is based on the experimental data on gamma-ray induced gain degradation in a commercial space borne BJT (2N3019). The method involves the calculation of gamma-ray dose (rad(Si)) equivalent of effective particle fluence. The linear energy transfer (LET) in silicon for different particle radiation obtained from TRIM calculation has been used for the conversion of gamma-dose into fluence of various particles. The estimation predicts a smooth increase in the displacement damage factor as the mass of the ion increases. Further, the displacement damage factor reaches a maximum at the same value of energy, which corresponds to maximum LET for all heavy ions. The maximum value of damage factor marginally decreases with increasing ion fluence for an ion of given energy. The results are compared with the data available in the literature for proton, deuteron, and helium induced displacement damage.

  17. Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

    Science.gov (United States)

    Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

    2018-04-01

    In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

  18. Self-consistent Capacitance-Voltage Characterization of Gate-all-around Graded Nanowire Transistor

    OpenAIRE

    Khan, Saeed Uz Zaman; Hossain, Md. Shafayat; Hossen, Md. Obaidul; Rahman, Fahim Ur; Zaman, Rifat; Khosru, Quazi D. M.

    2014-01-01

    This paper presents a self-consistent numerical model for calculating the charge profile and gate capacitance and therefore obtaining C-V characterization for a gate-all-around graded nanowire MOSFET with a high mobility axially graded In0.75Ga0.25As + In0.53Ga0.47As channel incorporating strain and atomic layer deposited Al2O3/20nm Ti gate. C-V characteristics with introduction and variation of In-composition grading and also grading in doping concentration are explored.Finite element method...

  19. Gain Improvement of Enhancement-Mode AlGaN/GaN High-Electron-Mobility Transistors Using Dual-Gate Architecture

    Science.gov (United States)

    Wang, Ruonan; Wu, Yichao; Chen, Kevin J.

    2008-04-01

    We demonstrate a dual-gate (DG) AlGaN/GaN high-electron-mobility transistor (HEMT) structure with enhancement-mode (E-mode) operation. The DG device consists of an E-mode gate and a depletion-mode (D-mode) gate instead of the dual D-mode gate electrodes used in previously reported works; thus no negative voltage supply is required when the DG device is used in amplifier circuits. The E-mode DG HEMTs exhibit similar DC characteristics to E-mode single-gate devices but show a 9 dB gain improvement at 2.1 GHz under the same bias conditions. The power gain improvement can be attributed to the higher output impedance and lower feedback capacitance in the DG structure.

  20. Flexible SiInZnO thin film transistor with organic/inorganic hybrid gate dielectric processed at 150 °C

    Science.gov (United States)

    Choi, J. Y.; Kim, S.; Hwang, B.-U.; Lee, N.-E.; Lee, S. Y.

    2016-12-01

    Silicon indium zinc oxide (SIZO) thin film transistors (TFTs) have been fabricated on a flexible polyimide (PI) substrate by using organic/inorganic hybrid gate dielectrics of poly-4vinyl phenol (PVP) and Al2O3. To improve the mechanical stability, Al2O3 has been used as a buffer layer on the flexible substrate. The Al2O3 layer of hybrid gate dielectrics protected the organic gate dielectric and improved mechanical flexibility. The different surface roughness of the gate dielectrics is investigated. The performance of the device with smooth surface roughness was significantly improved. Finally, the electrical characteristics of the TFTs with hybrid gate dielectrics were measured as well as the promising electrical endurance characteristics at the bending radius of 5 mm.

  1. Influence of the gate position on source-to-drain resistance in AlGaN/AlN/GaN heterostructure field-effect transistors

    Directory of Open Access Journals (Sweden)

    Yan Liu

    2017-08-01

    Full Text Available Using a suitable dual-gate structure, the source-to-drain resistance (RSD of AlGaN/AlN/GaN heterostructure field-effect transistor (HFET with varying gate position has been studied at room temperature. The theoretical and experimental results have revealed a dependence of RSD on the gate position. The variation of RSD with the gate position is found to stem from the polarization Coulomb field (PCF scattering. This finding is of great benefit to the optimization of the performance of AlGaN/AlN/GaN HFET. Especially, when the AlGaN/AlN/GaN HFET works as a microwave device, it is beneficial to achieve the impedance matching by designing the appropriate gate position based on PCF scattering.

  2. Leakage current suppression with a combination of planarized gate and overlap/off-set structure in metal-induced laterally crystallized polycrystalline-silicon thin-film transistors

    Science.gov (United States)

    Chae, Hee Jae; Seok, Ki Hwan; Lee, Sol Kyu; Joo, Seung Ki

    2018-04-01

    A novel inverted staggered metal-induced laterally crystallized (MILC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with a combination of a planarized gate and an overlap/off-set at the source-gate/drain-gate structure were fabricated and characterized. While the MILC process is advantageous for fabricating inverted staggered poly-Si TFTs, MILC TFTs reveal higher leakage current than TFTs crystallized by other processes due to their high trap density of Ni contamination. Due to this drawback, the planarized gate and overlap/off-set structure were applied to inverted staggered MILC TFTs. The proposed device shows drastic suppression of leakage current and pinning phenomenon by reducing the lateral electric field and the space-charge limited current from the gate to the drain.

  3. Extended-gate field-effect transistor (EG-FET) with molecularly imprinted polymer (MIP) film for selective inosine determination.

    Science.gov (United States)

    Iskierko, Zofia; Sosnowska, Marta; Sharma, Piyush Sindhu; Benincori, Tiziana; D'Souza, Francis; Kaminska, Izabela; Fronc, Krzysztof; Noworyta, Krzysztof

    2015-12-15

    A novel recognition unit of chemical sensor for selective determination of the inosine, renal disfunction biomarker, was devised and prepared. For that purpose, inosine-templated molecularly imprinted polymer (MIP) film was deposited on an extended-gate field-effect transistor (EG-FET) signal transducing unit. The MIP film was prepared by electrochemical polymerization of bis(bithiophene) derivatives bearing cytosine and boronic acid substituents, in the presence of the inosine template and a thiophene cross-linker. After MIP film deposition, the template was removed, and was confirmed by UV-visible spectroscopy. Subsequently, the film composition was characterized by spectroscopic techniques, and its morphology and thickness were determined by AFM. The finally MIP film-coated extended-gate field-effect transistor (EG-FET) was used for signal transduction. This combination is not widely studied in the literature, despite the fact that it allows for facile integration of electrodeposited MIP film with FET transducer. The linear dynamic concentration range of the chemosensor was 0.5-50 μM with inosine detectability of 0.62 μM. The obtained detectability compares well to the levels of the inosine in body fluids which are in the range 0-2.9 µM for patients with diagnosed diabetic nephropathy, gout or hyperuricemia, and can reach 25 µM in certain cases. The imprinting factor for inosine, determined from piezomicrogravimetric experiments with use of the MIP film-coated quartz crystal resonator, was found to be 5.5. Higher selectivity for inosine with respect to common interferents was also achieved with the present molecularly engineered sensing element. The obtained analytical parameters of the devised chemosensor allow for its use for practical sample measurements. Copyright © 2015 Elsevier B.V. All rights reserved.

  4. Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

    Science.gov (United States)

    Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

    2014-03-01

    Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.

  5. Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits.

    Science.gov (United States)

    Sporea, R A; Trainor, M J; Young, N D; Shannon, J M; Silva, S R P

    2014-03-06

    Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.

  6. Burnout and gate rupture of power MOS transistors with fission fragments of 252Cf

    International Nuclear Information System (INIS)

    Tang Benqi; Wang Yanping; Geng Bin; Chen Xiaohua; He Chaohui; Yang Hailiang

    2000-01-01

    A study to determine the single event burnout (SEB) and single event gate rupture (SEGR) sensitivities of power MOSFET devices is carried out by exposure to fission fragments from 252 Cf source. The test method, test results, a description of observed burnout current waveforms and a discussion of a possible failure mechanism are presented. The test results include the observed dependence upon applied drain or gate to source bias and effect of external capacitors and limited resistors

  7. Gate-modulated conductance of few-layer WSe2 field-effect transistors in the subgap regime: Schottky barrier transistor and subgap impurity states

    International Nuclear Information System (INIS)

    Wang, Junjie; Feng, Simin; Rhodes, Daniel; Balicas, Luis; Nguyen, Minh An T.; Watanabe, K.; Taniguchi, T.; Mallouk, Thomas E.; Terrones, Mauricio; Zhu, J.

    2015-01-01

    Two key subjects stand out in the pursuit of semiconductor research: material quality and contact technology. The fledging field of atomically thin transition metal dichalcogenides (TMDCs) faces a number of challenges in both efforts. This work attempts to establish a connection between the two by examining the gate-dependent conductance of few-layer (1-5L) WSe 2 field effect devices. Measurements and modeling of the subgap regime reveal Schottky barrier transistor behavior. We show that transmission through the contact barrier is dominated by thermionic field emission (TFE) at room temperature, despite the lack of intentional doping. The TFE process arises due to a large number of subgap impurity states, the presence of which also leads to high mobility edge carrier densities. The density of states of such impurity states is self-consistently determined to be approximately 1–2 × 10 13 /cm 2 /eV in our devices. We demonstrate that substrate is unlikely to be a major source of the impurity states and suspect that lattice defects within the material itself are primarily responsible. Our experiments provide key information to advance the quality and understanding of TMDC materials and electrical devices

  8. Gate-modulated conductance of few-layer WSe{sub 2} field-effect transistors in the subgap regime: Schottky barrier transistor and subgap impurity states

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Junjie; Feng, Simin [Department of Physics, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Rhodes, Daniel; Balicas, Luis [National High Magnetic Field Lab, Florida State University, Tallahassee, Florida 32310 (United States); Nguyen, Minh An T. [Department of Chemistry, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Watanabe, K.; Taniguchi, T. [National Institute for Materials Science, 1-1 Namiki, Tsukuba 305-0044 (Japan); Mallouk, Thomas E. [Department of Physics, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Department of Chemistry, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Department of Biochemistry and Molecular Biology, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Terrones, Mauricio [Department of Physics, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Department of Chemistry, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Department of Materials Science and Engineering, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Center for 2-Dimensional and Layered Materials, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Zhu, J., E-mail: jzhu@phys.psu.edu [Department of Physics, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Center for 2-Dimensional and Layered Materials, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States)

    2015-04-13

    Two key subjects stand out in the pursuit of semiconductor research: material quality and contact technology. The fledging field of atomically thin transition metal dichalcogenides (TMDCs) faces a number of challenges in both efforts. This work attempts to establish a connection between the two by examining the gate-dependent conductance of few-layer (1-5L) WSe{sub 2} field effect devices. Measurements and modeling of the subgap regime reveal Schottky barrier transistor behavior. We show that transmission through the contact barrier is dominated by thermionic field emission (TFE) at room temperature, despite the lack of intentional doping. The TFE process arises due to a large number of subgap impurity states, the presence of which also leads to high mobility edge carrier densities. The density of states of such impurity states is self-consistently determined to be approximately 1–2 × 10{sup 13}/cm{sup 2}/eV in our devices. We demonstrate that substrate is unlikely to be a major source of the impurity states and suspect that lattice defects within the material itself are primarily responsible. Our experiments provide key information to advance the quality and understanding of TMDC materials and electrical devices.

  9. Three-terminal heterojunction bipolar transistor solar cell for high-efficiency photovoltaic conversion.

    Science.gov (United States)

    Martí, A; Luque, A

    2015-04-22

    Here we propose, for the first time, a solar cell characterized by a semiconductor transistor structure (n/p/n or p/n/p) where the base-emitter junction is made of a high-bandgap semiconductor and the collector is made of a low-bandgap semiconductor. We calculate its detailed-balance efficiency limit and prove that it is the same one than that of a double-junction solar cell. The practical importance of this result relies on the simplicity of the structure that reduces the number of layers that are required to match the limiting efficiency of dual-junction solar cells without using tunnel junctions. The device naturally emerges as a three-terminal solar cell and can also be used as building block of multijunction solar cells with an increased number of junctions.

  10. Three-terminal heterojunction bipolar transistor solar cell for high-efficiency photovoltaic conversion

    Science.gov (United States)

    Martí, A.; Luque, A.

    2015-04-01

    Here we propose, for the first time, a solar cell characterized by a semiconductor transistor structure (n/p/n or p/n/p) where the base-emitter junction is made of a high-bandgap semiconductor and the collector is made of a low-bandgap semiconductor. We calculate its detailed-balance efficiency limit and prove that it is the same one than that of a double-junction solar cell. The practical importance of this result relies on the simplicity of the structure that reduces the number of layers that are required to match the limiting efficiency of dual-junction solar cells without using tunnel junctions. The device naturally emerges as a three-terminal solar cell and can also be used as building block of multijunction solar cells with an increased number of junctions.

  11. Active gate driving method for reliability improvement of IGBTs via junction temperature swing reduction

    DEFF Research Database (Denmark)

    Luo, Haoze; Iannuzzo, Francesco; Ma, Ke

    2016-01-01

    This paper introduces an advanced gate driver used as thermal swing control method for the reduction of AC load current-related ΔTj in Insulated-Gate Bipolar Transistors (IGBTs). A switchable gate resistor network is applied to the advanced gate driver, so that the switching power losses can...... be changed according to the amplitude of AC current. Accordingly, a closed-loop thermal control method including the functions of root-mean-square calculation and phase analysis is proposed. Hence ΔTj can be reduced by means of changing losses-related gate resistors on the basis of output fundamental...

  12. Improvements in the reliability of a-InGaZnO thin-film transistors with triple stacked gate insulator in flexible electronics applications

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Hua-Mao [Department of Photonics & Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang3708@gmail.com [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan (China); Tai, Ya-Hsiang [Department of Photonics & Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan (China); Chen, Kuan-Fu [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Chiang, Hsiao-Cheng [Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Liu, Kuan-Hsien [Department of Electrophysics, National Chiao Tung University, Hsinchu, Taiwan (China); Lee, Chao-Kuei [Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Lin, Wei-Ting; Cheng, Chun-Cheng; Tu, Chun-Hao; Liu, Chu-Yu [Advanced Technology Research Center, AU Optronics Corp, Hsinchu, Taiwan (China)

    2015-11-30

    This study examined the impact of the low-temperature stacking gate insulator on the gate bias instability of a-InGaZnO thin film transistors in flexible electronics applications. Although the quality of SiN{sub x} at low process/deposition temperature is better than that of SiO{sub x} at similarly low process/deposition temperature, there is still a very large positive threshold voltage (V{sub th}) shift of 9.4 V for devices with a single low-temperature SiN{sub x} gate insulator under positive gate bias stress. However, a suitable oxide–nitride–oxide-stacked gate insulator exhibits a V{sub th} shift of only 0.23 V. This improvement results from the larger band offset and suitable gate insulator thickness that can effectively suppress carrier trapping behavior. - Highlights: • The cause of the bias instability for a low-temperature gate insulator is verified. • A triple-stacked gate insulator was fabricated. • A suitable triple stacked gate insulator shows only 0.23 V threshold voltage shift.

  13. Effects of Ambient Air and Temperature on Ionic Gel Gated Single-Walled Carbon Nanotube Thin-Film Transistor and Circuits.

    Science.gov (United States)

    Li, Huaping; Zhou, Lili

    2015-10-21

    Single-walled carbon nanotube thin-film transistor (SWCNT TFT) and circuits were fabricated by fully inkjet printing gold nanoparticles as source/drain electrodes, semiconducting SWCNT thin films as channel materials, PS-PMMA-PS/EMIM TFSI composite gel as gate dielectrics, and PEDOT/PSS as gate electrodes. The ionic gel gated SWCNT TFT shows reversible conversion from p-type transistor behavior in air to ambipolar features under vacuum due to reversible oxygen doping in semiconducting SWCNT thin films. The threshold voltages of ionic gel gated SWCNT TFT and inverters are largely shifted to the low value (0.5 V for p-region and 1.0 V for n-region) by vacuum annealing at 140 °C to exhausively remove water that is incorporated in the ionic gel as floating gates. The vacuum annealed ionic gel gated SWCNT TFT shows linear temperature dependent transconductances and threshold voltages for both p- and n-regions. The strong temperature dependent transconductances (0.08 μS/K for p-region, 0.4 μS/K for n-region) indicate their potential application in thermal sensors. In the other hand, the weak temperature dependent threshold voltages (-1.5 mV/K for p-region, -1.1 mV/K for n-region) reflect their excellent thermal stability.

  14. Characterization of a power bipolar transistor as high-dose dosimeter for 1.9-2.2 MeV electron beams

    Energy Technology Data Exchange (ETDEWEB)

    Fuochi, P.G., E-mail: fuochi@isof.cnr.i [ISOF-CNR Institute, Via P. Gobetti 101, I-40129, Bologna (Italy); Lavalle, M.; Corda, U. [ISOF-CNR Institute, Via P. Gobetti 101, I-40129, Bologna (Italy); Kuntz, F.; Plumeri, S. [Aerial, Parc d' Innovation Rue Laurent Fries F-67400 Illkirch (France); Gombia, E. [IMEM-CNR Institute, Viale delle Scienze 37 A, Loc. Fontanini, 43010 Parma (Italy)

    2010-04-15

    Results of the characterization studies on a power bipolar transistor investigated as a possible radiation dosimeter under laboratory condition using electron beams of energies from 2.2 to 8.6 MeV and gamma rays from a {sup 60}Co source and tested in industrial irradiation plants having high-activity {sup 60}Co gamma-source and high-energy, high-power electron beam have previously been reported. The present paper describes recent studies performed on this type of bipolar transistor irradiated with 1.9 and 2.2 MeV electron beams in the dose range 5-50 kGy. Dose response, post-irradiation heat treatment and stability, effects of temperature during irradiation in the range from -104 to +22 deg. C, dependence on temperature during reading in the range 20-50 deg. C, and the difference in response of the transistors irradiated from the plastic side and the copper side are reported. DLTS measurements performed on the irradiated devices to identify the recombination centres introduced by radiation and their dependence on dose and energy of the electron beam are also reported.

  15. Photodetection in p–n junctions formed by electrolyte-gated transistors of two-dimensional crystals

    KAUST Repository

    Kozawa, Daichi

    2016-11-16

    Transition metal dichalcogenide monolayers have attracted much attention due to their strong light absorption and excellent electronic properties. These advantages make this type of two-dimensional crystal a promising one for optoelectronic device applications. In the case of photoelectric conversion devices such as photodetectors and photovoltaic cells, p–n junctions are one of the most important devices. Here, we demonstrate photodetection with WSe2 monolayer films. We prepare the electrolyte-gated ambipolar transistors and electrostatic p–n junctions are formed by the electrolyte-gating technique at 270 K. These p-n junctions are cooled down to fix the ion motion (and p-n junctions) and we observed the reasonable photocurrent spectra without the external bias, indicating the formation of p-n junctions. Very interestingly, two-terminal devices exhibit higher photoresponsivity than that of three-terminal ones, suggesting the formation of highly balanced anion and cation layers. The maximum photoresponsivity reaches 5 mA/W in resonance with the first excitonic peak. Our technique provides important evidence for optoelectronics in atomically thin crystals.

  16. Flexible semi-around gate silicon nanowire tunnel transistors with a sub-kT/q switch

    Science.gov (United States)

    Lee, Myeongwon; Jeon, Youngin; Kim, Minsuk; Kim, Sangsig

    2015-06-01

    Tunnel field-effect transistors (TFETs) with a subthreshold swing (SS) tunneling. In silicon (Si) channel materials, however, it still remains a challenge to obtain SS smaller than 60 mV/dec. In this study, we experimentally demonstrate the sub-60 mV/dec operation of a flexible semi-around gate TFET on a plastic substrate using Si nanowires (SiNWs) as the channel material. With the combined advantages of selectively thinned SiNW channels (width ˜ 15 nm and height ˜ 40 nm) and high-κ (Al2O3 ˜ 7 nm) gate dielectric, in conjunction with an abrupt degenerate source junction, the device with a channel length of ˜500 nm exhibits a minimal SS of ˜42 mV/dec at room temperature. Moreover, mechanical bendability of the device indicates that it has stable and good fatigue properties, providing an important step towards the realization of steep-slope switches for low-power and energy-efficient flexible electronics.

  17. Quantum and Classical Magnetoresistance in Ambipolar Topological Insulator Transistors with Gate-tunable Bulk and Surface Conduction

    Science.gov (United States)

    Tian, Jifa; Chang, Cuizu; Cao, Helin; He, Ke; Ma, Xucun; Xue, Qikun; Chen, Yong P.

    2014-01-01

    Weak antilocalization (WAL) and linear magnetoresistance (LMR) are two most commonly observed magnetoresistance (MR) phenomena in topological insulators (TIs) and often attributed to the Dirac topological surface states (TSS). However, ambiguities exist because these phenomena could also come from bulk states (often carrying significant conduction in many TIs) and are observable even in non-TI materials. Here, we demonstrate back-gated ambipolar TI field-effect transistors in (Bi0.04Sb0.96)2Te3 thin films grown by molecular beam epitaxy on SrTiO3(111), exhibiting a large carrier density tunability (by nearly 2 orders of magnitude) and a metal-insulator transition in the bulk (allowing switching off the bulk conduction). Tuning the Fermi level from bulk band to TSS strongly enhances both the WAL (increasing the number of quantum coherent channels from one to peak around two) and LMR (increasing its slope by up to 10 times). The SS-enhanced LMR is accompanied by a strongly nonlinear Hall effect, suggesting important roles of charge inhomogeneity (and a related classical LMR), although existing models of LMR cannot capture all aspects of our data. Our systematic gate and temperature dependent magnetotransport studies provide deeper insights into the nature of both MR phenomena and reveal differences between bulk and TSS transport in TI related materials. PMID:24810663

  18. Photodetection in p-n junctions formed by electrolyte-gated transistors of two-dimensional crystals

    Science.gov (United States)

    Kozawa, Daichi; Pu, Jiang; Shimizu, Ryo; Kimura, Shota; Chiu, Ming-Hui; Matsuki, Keiichiro; Wada, Yoshifumi; Sakanoue, Tomo; Iwasa, Yoshihiro; Li, Lain-Jong; Takenobu, Taishi

    2016-11-01

    Transition metal dichalcogenide monolayers have attracted much attention due to their strong light absorption and excellent electronic properties. These advantages make this type of two-dimensional crystal a promising one for optoelectronic device applications. In the case of photoelectric conversion devices such as photodetectors and photovoltaic cells, p-n junctions are one of the most important devices. Here, we demonstrate photodetection with WSe2 monolayer films. We prepare the electrolyte-gated ambipolar transistors and electrostatic p-n junctions are formed by the electrolyte-gating technique at 270 K. These p-n junctions are cooled down to fix the ion motion (and p-n junctions) and we observed the reasonable photocurrent spectra without the external bias, indicating the formation of p-n junctions. Very interestingly, two-terminal devices exhibit higher photoresponsivity than that of three-terminal ones, suggesting the formation of highly balanced anion and cation layers. The maximum photoresponsivity reaches 5 mA/W in resonance with the first excitonic peak. Our technique provides important evidence for optoelectronics in atomically thin crystals.

  19. Fluorinated copper-phthalocyanine-based n-type organic field-effect transistors with a polycarbonate gate insulator

    International Nuclear Information System (INIS)

    Sethuraman, Kunjithapatham; Kumar, Palanisamy; Santhakumar, Kannappan; Ochiai, Shizuyasu; Shin, Paikkyun

    2012-01-01

    Fluorinated copper-phthalocyanine (F 16 CuPc) thin films were prepared by using a vacuum evaporation technique and were applied to n-type organic field-effect transistors (OFETs) as active channel layers combined with a spin-coated polycarbonate thin-film gate insulator. The output characteristics of the resulting n-type OFET devices with bottom-gate/bottom-contact structures were investigated to evaluate the performances such as the field effect mobility (μ FE ), the on/off current ratio (I on/off ), and the threshold voltage (V th ). A relatively high field effect mobility of 6.0 x 10 -3 cm 2 /Vs was obtained for the n-type semiconductor under atmospheric conditions with an on/off current ratio of 1 x 10 4 and a threshold voltage of 5 V. The electron mobility of the n-type semiconductor was found to depend strongly on the growth temperature of the F 16 CuPc thin films. X-ray diffraction profiles showed that the crystallinity and the orientation of the F 16 CuPc on a polycarbonate thin film were enhanced with increasing growth temperature. Atomic force microscopy studies revealed various surface morphologies of the active layer. The field effect mobility of the F 16 CuPc-OFET was closely related to the crystallinity and the orientation of the F 16 CuPc thin film.

  20. Transistor Laser Optical NOR Gate for High Speed Optical Logic Processors

    Science.gov (United States)

    2017-03-20

    time. This has been confirmed experimentally . Recently, we demonstrated a light emitting transistor with base and emitter short as a tilted charge...low laser n assisted 2 increases tions from or IC-VCE2 s. mented by functions L2 will not ne or two ogic 0” is tunneling -Holonyak T...Kenneth Goretta) under Grant FA9550-15-1-0122 for the fundamental study of fast recombination lifetimes and tunneling modulation. This project is

  1. Improved performance of nanoscale junctionless tunnel field-effect transistor based on gate engineering approach

    Science.gov (United States)

    Molaei Imen Abadi, Rouzbeh; Sedigh Ziabari, Seyed Ali

    2016-11-01

    In this paper, a first qualitative study on the performance characteristics of dual-work function gate junctionless TFET (DWG-JLTFET) on the basis of energy band profile modulation is investigated. A dual-work function gate technique is used in a JLTFET in order to create a downward band bending on the source side similar to PNPN structure. Compared with the single-work function gate junctionless TFET (SWG-JLTFET), the numerical simulation results demonstrated that the DWG-JLTFET simultaneously optimizes the ON-state current, the OFF-state leakage current, and the threshold voltage and also improves average subthreshold slope. It is illustrated that if appropriate work functions are selected for the gate materials on the source side and the drain side, the JLTFET exhibits a considerably improved performance. Furthermore, the optimization design of the tunnel gate length ( L Tun) for the proposed DWG-JLTFET is studied. All the simulations are done in Silvaco TCAD for a channel length of 20 nm using the nonlocal band-to-band tunneling (BTBT) model.

  2. Sensing with Advanced Computing Technology: Fin Field-Effect Transistors with High-k Gate Stack on Bulk Silicon.

    Science.gov (United States)

    Rigante, Sara; Scarbolo, Paolo; Wipf, Mathias; Stoop, Ralph L; Bedner, Kristine; Buitrago, Elizabeth; Bazigos, Antonios; Bouvet, Didier; Calame, Michel; Schönenberger, Christian; Ionescu, Adrian M

    2015-05-26

    Field-effect transistors (FETs) form an established technology for sensing applications. However, recent advancements and use of high-performance multigate metal-oxide semiconductor FETs (double-gate, FinFET, trigate, gate-all-around) in computing technology, instead of bulk MOSFETs, raise new opportunities and questions about the most suitable device architectures for sensing integrated circuits. In this work, we propose pH and ion sensors exploiting FinFETs fabricated on bulk silicon by a fully CMOS compatible approach, as an alternative to the widely investigated silicon nanowires on silicon-on-insulator substrates. We also provide an analytical insight of the concept of sensitivity for the electronic integration of sensors. N-channel fully depleted FinFETs with critical dimensions on the order of 20 nm and HfO2 as a high-k gate insulator have been developed and characterized, showing excellent electrical properties, subthreshold swing, SS ∼ 70 mV/dec, and on-to-off current ratio, Ion/Ioff ∼ 10(6), at room temperature. The same FinFET architecture is validated as a highly sensitive, stable, and reproducible pH sensor. An intrinsic sensitivity close to the Nernst limit, S = 57 mV/pH, is achieved. The pH response in terms of output current reaches Sout = 60%. Long-term measurements have been performed over 4.5 days with a resulting drift in time δVth/δt = 0.10 mV/h. Finally, we show the capability to reproduce experimental data with an extended three-dimensional commercial finite element analysis simulator, in both dry and wet environments, which is useful for future advanced sensor design and optimization.

  3. Solvent-Free Processable and Photo-Patternable Hybrid Gate Dielectric for Flexible Top-Gate Organic Field-Effect Transistors.

    Science.gov (United States)

    Kwon, Jun Seon; Park, Han Wool; Kim, Do Hwan; Kwark, Young-Je

    2017-02-15

    We report a novel solvent-free and direct photopatternable poly[(mercaptopropyl)methyl-siloxane] (PMMS) hybrid dielectric for flexible top-gate organic field-effect transistors (OFETs) utilizing a photoactivated thiol-ene reaction under UV irradiation of 254 nm to induce cross-linking, even in air and at low temperatures. In particular, a solvent-free PMMS-f dielectric film, for which an optimal cross-linking density is shown by a well-organized molar ratio between thiol and vinyl in the thiol-ene reaction, exhibited a high dielectric constant (5.4 @ 100 Hz) and a low leakage current (OFETs with a high reliability against the radius of curvature (9.5, 7.0, and 5.5 mm) and repetitive bending cycles at the radius of curvature of 5.5 mm. This will eventually enable the proposed dielectric design to be used in a variety of applications such as flexible displays and soft organic sensors including chemical and tactile capability.

  4. Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

    Science.gov (United States)

    Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

    2018-01-01

    Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

  5. Silicon Carbide Junction Field Effect Transistor Digital Logic Gates Demonstrated at 600 deg. C

    Science.gov (United States)

    Neudeck, Philip G.

    1998-01-01

    The High Temperature Integrated Electronics and Sensors (HTIES) Program at the NASA Lewis Research Center is currently developing silicon carbide (SiC) for use in harsh conditions where silicon, the semiconductor used in nearly all of today's electronics, cannot function. The HTIES team recently fabricated and demonstrated the first semiconductor digital logic gates ever to function at 600 C.

  6. High performance organic field-effect transistors with ultra-thin HfO{sub 2} gate insulator deposited directly onto the organic semiconductor

    Energy Technology Data Exchange (ETDEWEB)

    Ono, S., E-mail: shimpei@criepi.denken.or.jp [Central Research Institute of Electric Power Industry, Komae, Tokyo 201-8511 (Japan); Häusermann, R. [Central Research Institute of Electric Power Industry, Komae, Tokyo 201-8511 (Japan); Laboratory for Solid State Physics, ETH Zurich, Zurich 8093 (Switzerland); Chiba, D. [Institute for Chemical Research, Kyoto University, Gokasho, Uji, Kyoto 611-0011 (Japan); PRESTO, Japan Science and Technology Agency, 4-1-8 Honcho Kawaguchi, Saitama 322-0012 (Japan); Department of Applied Physics, University of Tokyo, Tokyo 113-8656 (Japan); Shimamura, K.; Ono, T. [Institute for Chemical Research, Kyoto University, Gokasho, Uji, Kyoto 611-0011 (Japan); Batlogg, B. [Laboratory for Solid State Physics, ETH Zurich, Zurich 8093 (Switzerland)

    2014-01-06

    We have produced stable organic field-effect transistors (OFETs) with an ultra-thin HfO{sub 2} gate insulator deposited directly on top of rubrene single crystals by atomic layer deposition (ALD). We find that ALD is a gentle deposition process to grow thin films without damaging rubrene single crystals, as results these devices have a negligibly small threshold voltage and are very stable against gate-bias-stress, and the mobility exceeds 1 cm{sup 2}/V s. Moreover, the devices show very little degradation even when kept in air for more than 2 months. These results demonstrate thin HfO{sub 2} layers deposited by ALD to be well suited as high capacitance gate dielectrics in OFETs operating at small gate voltage. In addition, the dielectric layer acts as an effective passivation layer to protect the organic semiconductor.

  7. New Analytical Model for Short-Channel Fully Depleted Dual-Material-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors

    Science.gov (United States)

    Te-Kuang Chiang,

    2010-07-01

    Using the exact solution of the two-dimensional Poisson equation, a new analytical model comprising two-dimensional potential and threshold voltage for short-channel fully depleted dual-material-gate silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) is developed. The model shows that the minimum acceptable channel length can be sustained while repressing the short-channel effects if a thin gate oxide and a thin silicon body are employed in the device. Moreover, by increasing the ratio of the screen gate length to control gate length, the threshold voltage roll-off can be more effectively reduced. The model is verified by the close agreement of its results with those of a numerical simulation using the device simulator MEDICI. The model not only offers an insight into the device physics but is also an efficient model for circuit simulation.

  8. Linear gate

    International Nuclear Information System (INIS)

    Suwono.

    1978-01-01

    A linear gate providing a variable gate duration from 0,40μsec to 4μsec was developed. The electronic circuity consists of a linear circuit and an enable circuit. The input signal can be either unipolar or bipolar. If the input signal is bipolar, the negative portion will be filtered. The operation of the linear gate is controlled by the application of a positive enable pulse. (author)

  9. DC parameter extraction of equivalent circuit model in InGaAsSb heterojunction bipolar transistors including non-ideal effects in the base region

    Science.gov (United States)

    Chang, Yang-Hua; Cheng, Zong-Tai

    2011-07-01

    This paper presents the DC parameter extraction of the equivalent circuit model in an InP-InGaAsSb double heterojunction bipolar transistor (HBT). The non-ideal collector current is modeled by a non-ideal doping distribution in the base region. Then several consequent non-ideal effects, which have always been neglected in typical HBTs, are studied using Medici device simulator. Moreover, the associated DC parameters of VBIC model are extracted accordingly. The equivalent circuit model is in good agreement with the measured data in I C- V CE characteristics.

  10. Two-dimensional analysis of the interface state effect on current gain for a 4H-SiC bipolar junction transistor

    Science.gov (United States)

    Zhang, You-Run; Zhang, Bo; Li, Zhao-Ji; Deng, Xiao-Chuan

    2010-06-01

    This paper studies two-dimensional analysis of the surface state effect on current gain for a 4H-SiC bipolar junction transistor (BJT). Simulation results indicate the mechanism of current gain degradation, which is surface Fermi level pinning leading to a strong downward bending of the energy bands to form the channel of surface electron recombination current. The experimental results are well-matched with the simulation, which is modeled by exponential distributions of the interface state density replacing the single interface state trap. Furthermore, the simulation reveals that the oxide quality of the base emitter junction interface is very important for 4H-SiC BJT performance.

  11. Delay Time Analysis of Graded Gate Field-Plate AlGaN/GaN High Electron Mobility Transistors Using Monte Carlo Simulation

    Science.gov (United States)

    Hara, Kazuya; Toshima, Takuya; Hara, Shinsuke; Fujishiro, Hiroki I.

    2013-08-01

    The mechanisms of delay time generation in graded gate field-plate (FP) AlGaN/GaN high electron mobility transistors (HEMTs) are investigated using Monte Carlo simulation. The graded gate FP suppresses the increase in the maximum electric field with the drain voltage by extending the high electric field area toward the drain. However, in addition to the FP capacitance delay time caused by the capacitance between the FP and the channel, the extension of the high electric field area itself increases the electron accumulation delay time caused by electron occupation of the upper valleys. Eventually, as the FP angle increases, the intrinsic cutoff frequency fT decreases.

  12. Poly(4-vinylphenol gate insulator with cross-linking using a rapid low-power microwave induction heating scheme for organic thin-film-transistors

    Directory of Open Access Journals (Sweden)

    Ching-Lin Fan

    2016-03-01

    Full Text Available A Microwave-Induction Heating (MIH scheme is proposed for the poly(4-vinylphenol (PVP gate insulator cross-linking process to replace the traditional oven heating cross-linking process. The cross-linking time is significantly decreased from 1 h to 5 min by heating the metal below the PVP layer using microwave irradiation. The necessary microwave power was substantially reduced to about 50 W by decreasing the chamber pressure. The MIH scheme is a good candidate to replace traditional thermal heating for cross-linking of PVP as the gate insulator for organic thin-film-transistors.

  13. Extraction of contact resistance and channel parameters from the electrical characteristics of a single bottom-gate/top-contact organic transistor

    Science.gov (United States)

    Takagaki, Shunsuke; Yamada, Hirofumi; Noda, Kei

    2016-03-01

    A parameter extraction procedure for staggered-type organic field-effect transistors (OFETs), in which only the electrical characteristics of a single device are needed, was newly considered. The existing differential method and the transition voltage method for evaluating contact and channel parameters in OFETs were complementarily combined. The calibration of the total resistance between the source and the drain was also incorporated to compensate discrepancies in the total resistances calculated from output and transfer characteristics, caused by the existence of nonignorable contact resistance and carrier traps. By using our proposed method, gate-voltage-dependent contact resistance and channel mobility in the linear regime were evaluated for bottom-gate/top-contact pentacene thin-film transistors, and the channel-length dependence of these parameters was investigated. A series of results of parameter extraction confirm the validity of our proposed method, which is advantageous in avoiding the influences of characteristic variations that are frequently observed in practical OFET devices.

  14. Raman imaging of carrier distribution in the channel of an ionic liquid-gated transistor fabricated with regioregular poly(3-hexylthiophene)

    Science.gov (United States)

    Wada, Y.; Enokida, I.; Yamamoto, J.; Furukawa, Y.

    2018-05-01

    Raman images of carriers (positive polarons) at the channel of an ionic liquid-gated transistor (ILGT) fabricated with regioregular poly(3-hexylthiophene) (P3HT) have been measured with excitation at 785 nm. The observed spectra indicate that carriers generated are positive polarons. The intensities of the 1415 cm-1 band attributed to polarons in the P3HT channel were plotted as Raman images; they showed the carrier density distribution. When the source-drain voltage VD is lower than the source-gate voltage VG (linear region), the carrier density was uniform. When VD is nearly equal to VG (saturation region), a negative carrier density gradient from the source electrode towards the drain electrode was observed. This carrier density distribution is associated with the observed current-voltage characteristics, which is not consistent with the "pinch-off" theory of inorganic semiconductor transistors.

  15. N-channel thin-film transistors based on 1,4,5,8-naphthalene tetracarboxylic dianhydride with ultrathin polymer gate buffer layer

    International Nuclear Information System (INIS)

    Tanida, Shinji; Noda, Kei; Kawabata, Hiroshi; Matsushige, Kazumi

    2009-01-01

    N-channel operation of thin-film transistors based on 1,4,5,8-naphthalene tetracarboxylic dianhydride (NTCDA) with a 9-nm-thick poly(methyl methacrylate) (PMMA) gate buffer layer was examined. The uniform coverage of the ultrathin PMMA layer on an SiO 2 gate insulator, verified by X-ray reflectivity measurement, caused the increase of electron field-effect mobility because of the suppression of electron traps existing on the SiO 2 surface. In addition, air stability for n-channel operation of the NTCDA transistor was also improved by the PMMA layer which possibly prevented the adsorption of ambient water molecules onto the SiO 2 surface.

  16. Ultra-thin films of polysilsesquioxanes possessing 3-methacryloxypropyl groups as gate insulator for organic field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Nakahara, Yoshio; Kawa, Haruna [Department of Applied Chemistry, Faculty of Systems Engineering, Wakayama University, 930 Sakae-dani, Wakayama 640-8510 (Japan); Yoshiki, Jun [Division of Information and Electronic Engineering, Faculty of Engineering, Muroran Institute of Technology, 27-1 Mizumoto-cho, Muroran 050-8585 (Japan); Kumei, Maki; Yamamoto, Hiroyuki; Oi, Fumio [Konishi Chemical IND. Co., LTD., 3-4-77 Kozaika, Wakayama 641-0007 (Japan); Yamakado, Hideo [Department of Applied Chemistry, Faculty of Systems Engineering, Wakayama University, 930 Sakae-dani, Wakayama 640-8510 (Japan); Fukuda, Hisashi [Division of Engineering for Composite Functions, Faculty of Engineering, Muroran Institute of Technology, 27-1 Mizumoto-cho, Muroran 050-8585 (Japan); Kimura, Keiichi, E-mail: kkimura@center.wakayama-u.ac.jp [Department of Applied Chemistry, Faculty of Systems Engineering, Wakayama University, 930 Sakae-dani, Wakayama 640-8510 (Japan)

    2012-10-01

    Polysilsesquioxanes (PSQs) possessing 3-methacryloxypropyl groups as an organic moiety of the side chain were synthesized by sol-gel condensation copolymerization of the corresponding trialkoxysilanes. The ultra-thin PSQ film with a radical initiator and a cross-linking agent was prepared by a spin-coating method, and the film was cured integrally at low temperatures of less than 120 Degree-Sign C through two different kinds of polymeric reactions, which were radical polymerization of vinyl groups and sol-gel condensation polymerization of terminated silanol and alkoxy groups. The obtained PSQ film showed the almost perfect solubilization resistance to acetone, which is a good solvent of PSQ before polymerization. It became clear by atomic force microscopy observation that the surface of the PSQ film was very smooth at a nano-meter level. Furthermore, pentacene-based organic field-effect transistor (OFET) with the PSQ film as a gate insulator showed typical p-channel enhancement mode operation characteristics and therefore the ultra-thin PSQ film has the potential to be applicable for solution-processed OFET systems. - Highlights: Black-Right-Pointing-Pointer Polysilsesquioxanes (PSQs) possessing 3-methacryloxypropyl groups were synthesized. Black-Right-Pointing-Pointer The ultra-thin PSQ film could be cured at low temperatures of less than 120 Degree-Sign C. Black-Right-Pointing-Pointer The PSQ film showed the almost perfect solubilization resistance to organic solvent. Black-Right-Pointing-Pointer The surface of the PSQ film was very smooth at a nano-meter level. Black-Right-Pointing-Pointer Pentacene-based organic field-effect transistor with the PSQ film was fabricated.

  17. Effects of Si3N4 passivation on the dc and RF characteristics of metamorphic high-electron-mobility transistors depending on the gate-recess structures

    International Nuclear Information System (INIS)

    Oh, J H; Han, M; Baek, Y H; Moon, S W; Rhee, J K; Kim, S D

    2009-01-01

    Effects of the Si 3 N 4 passivation on the dc and RF characteristics of a 0.1 µm metamorphic high-electron-mobility transistor (HEMT) are investigated for narrow and wide gate-recess structures. Maximum drain-source saturation current (I dss,max ) and maximum extrinsic transconductance (g m,max ) are reduced by ∼14.8 and ∼11.6%, respectively, in the wide gate-recess structure after the passivation; on the other hand, only ∼5.7 and ∼4.9% reductions are measured from I dss,max and g m,max , respectively, in the narrow gate-recess structure. We examine the passivation-induced degradation by using a modified charge control model assuming the charged surface states on the Si 3 N 4 interface and a comparative study of the hydrodynamic device simulation with the experimental measurement. From the analysis, it is proposed that the difference of degradation in two different gate structures is due to an approximately three times higher charged surface state density of ∼4.5 × 10 11 cm −2 in the wide gate-recess structure than ∼1.6 × 10 11 cm −2 in the narrow gate-recess structure. The cut-off frequency (f T ) of the wide gate-recess structure also exhibits a greater reduction of ∼14.5%, while the f T of the narrow gate-recess structure is reduced by only ∼6.6% after the passivation. This is mainly due to the passivation-induced surface states of a higher density in the wide gate-recess structure. A great increase of the gate-to-drain parasitic capacitance in the wide gate-recess structure makes a major contribution to ∼13.5% degradation of the maximum frequency of oscillation

  18. Single-crystal C60 needle/CuPc nanoparticle double floating-gate for low-voltage organic transistors based non-volatile memory devices.

    Science.gov (United States)

    Chang, Hsuan-Chun; Lu, Chien; Liu, Cheng-Liang; Chen, Wen-Chang

    2015-01-07

    Low-voltage organic field-effect transistor memory devices exhibiting a wide memory window, low power consumption, acceptable retention, endurance properties, and tunable memory performance are fabricated. The performance is achieved by employing single-crystal C60 needles and copper phthalocyanine nanoparticles to produce an ambipolar (hole/electron) trapping effect in a double floating-gate architecture. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  19. Chemical Gated Field Effect Transistor by Hybrid Integration of One-Dimensional Silicon Nanowire and Two-Dimensional Tin Oxide Thin Film for Low Power Gas Sensor.

    Science.gov (United States)

    Han, Jin-Woo; Rim, Taiuk; Baek, Chang-Ki; Meyyappan, M

    2015-09-30

    Gas sensors based on metal-oxide-semiconductor transistor with the polysilicon gate replaced by a gas sensitive thin film have been around for over 50 years. These are not suitable for the emerging mobile and wearable sensor platforms due to operating voltages and powers far exceeding the supply capability of batteries. Here we present a novel approach to decouple the chemically sensitive region from the conducting channel for reducing the drive voltage and increasing reliability. This chemically gated field effect transistor uses silicon nanowire for the current conduction channel with a tin oxide film on top of the nanowire serving as the gas sensitive medium. The potential change induced by the molecular adsorption and desorption allows the electrically floating tin oxide film to gate the silicon channel. As the device is designed to be normally off, the power is consumed only during the gas sensing event. This feature is attractive for the battery operated sensor and wearable electronics. In addition, the decoupling of the chemical reaction and the current conduction regions allows the gas sensitive material to be free from electrical stress, thus increasing reliability. The device shows excellent gas sensitivity to the tested analytes relative to conventional metal oxide transistors and resistive sensors.

  20. Fluorinated copper-phthalocyanine-based n-type organic field-effect transistors with a polycarbonate gate insulator

    Energy Technology Data Exchange (ETDEWEB)

    Sethuraman, Kunjithapatham [Madurai Kamaraj University, Madurai (India); Kumar, Palanisamy; Santhakumar, Kannappan; Ochiai, Shizuyasu [Aichi Institute of Technology, Toyota City (Japan); Shin, Paikkyun [Inha University, Incheon (Korea, Republic of)

    2012-07-15

    Fluorinated copper-phthalocyanine (F{sub 16}CuPc) thin films were prepared by using a vacuum evaporation technique and were applied to n-type organic field-effect transistors (OFETs) as active channel layers combined with a spin-coated polycarbonate thin-film gate insulator. The output characteristics of the resulting n-type OFET devices with bottom-gate/bottom-contact structures were investigated to evaluate the performances such as the field effect mobility (μ{sub FE}), the on/off current ratio (I{sub on/off}), and the threshold voltage (V{sub th}). A relatively high field effect mobility of 6.0 x 10{sup -3} cm{sup 2}/Vs was obtained for the n-type semiconductor under atmospheric conditions with an on/off current ratio of 1 x 10{sup 4} and a threshold voltage of 5 V. The electron mobility of the n-type semiconductor was found to depend strongly on the growth temperature of the F{sub 16}CuPc thin films. X-ray diffraction profiles showed that the crystallinity and the orientation of the F{sub 16}CuPc on a polycarbonate thin film were enhanced with increasing growth temperature. Atomic force microscopy studies revealed various surface morphologies of the active layer. The field effect mobility of the F{sub 16}CuPc-OFET was closely related to the crystallinity and the orientation of the F{sub 16}CuPc thin film.

  1. Temas de Física para Ingeniería: El transistor de unión

    OpenAIRE

    Beléndez Vázquez, Augusto; Pastor Antón, Carlos; Martín García, Agapito

    1990-01-01

    El transistor de unión bipolar. Tensiones y corrientes en el transistor. El transistor como amplificador. El transistor como conmutador. Transistores unipolares o de efecto de campo. El tiristor. Microelectrónica y circuitos integrados.

  2. Solution-gated Field Effect Transistors based on CVD grown Graphene for chemical and bio sensing applications

    Science.gov (United States)

    Mailly Giacchetti, Benjamin; Hsu, Allen; Wang, Han; Kim, Ki Kang; Kong, Jing; Palacios, Tomas

    2011-03-01

    Graphene holds great potential for bioelectronic applications and, more specifically, for fast high-sensitivity pH measurements and biosensing. Its monolayer structure (just one carbon atom thick) in combination with its very high carrier mobility enable very high transconductance, low noise and biocompatibility which are key parameters for chemical sensors with electronic readout. In fact, single molecule detection has already been demonstrated in graphene gas sensors. In this paper we report on the fabrication and characterization of solution-gated field effect transistors (SGFET) arrays based on CVD grown graphene films on copper that can operate in various liquid environments. These devices exhibit transconductances around 20 μ Siemens, which highlights their excellent sensitivity. We also performed some pH sensing experiments and demonstrated that the transfer characteristics of the GFET are pH dependent with a pH sensitivity of 14 mV/pH. These results drive the way for chemical and bio-sensing by functionalized graphene, which is the aim of our future work.

  3. High Performance Transparent Transistor Memory Devices Using Nano-Floating Gate of Polymer/ZnO Nanocomposites

    Science.gov (United States)

    Shih, Chien-Chung; Lee, Wen-Ya; Chiu, Yu-Cheng; Hsu, Han-Wen; Chang, Hsuan-Chun; Liu, Cheng-Liang; Chen, Wen-Chang

    2016-01-01

    Nano-floating gate memory devices (NFGM) using metal nanoparticles (NPs) covered with an insulating polymer have been considered as a promising electronic device for the next-generation nonvolatile organic memory applications NPs. However, the transparency of the device with metal NPs is restricted to 60~70% due to the light absorption in the visible region caused by the surface plasmon resonance effects of metal NPs. To address this issue, we demonstrate a novel NFGM using the blends of hole-trapping poly (9-(4-vinylphenyl) carbazole) (PVPK) and electron-trapping ZnO NPs as the charge storage element. The memory devices exhibited a remarkably programmable memory window up to 60 V during the program/erase operations, which was attributed to the trapping/detrapping of charge carriers in ZnO NPs/PVPK composite. Furthermore, the devices showed the long-term retention time (>105 s) and WRER test (>200 cycles), indicating excellent electrical reliability and stability. Additionally, the fabricated transistor memory devices exhibited a relatively high transparency of 90% at the wavelength of 500 nm based on the spray-coated PEDOT:PSS as electrode, suggesting high potential for transparent organic electronic memory devices. PMID:26831222

  4. Analytical drain current model for symmetric dual-gate amorphous indium gallium zinc oxide thin-film transistors

    Science.gov (United States)

    Qin, Ting; Liao, Congwei; Huang, Shengxiang; Yu, Tianbao; Deng, Lianwen

    2018-01-01

    An analytical drain current model based on the surface potential is proposed for amorphous indium gallium zinc oxide (a-InGaZnO) thin-film transistors (TFTs) with a synchronized symmetric dual-gate (DG) structure. Solving the electric field, surface potential (φS), and central potential (φ0) of the InGaZnO film using the Poisson equation with the Gaussian method and Lambert function is demonstrated in detail. The compact analytical model of current–voltage behavior, which consists of drift and diffusion components, is investigated by regional integration, and voltage-dependent effective mobility is taken into account. Comparison results demonstrate that the calculation results obtained using the derived models match well with the simulation results obtained using a technology computer-aided design (TCAD) tool. Furthermore, the proposed model is incorporated into SPICE simulations using Verilog-A to verify the feasibility of using DG InGaZnO TFTs for high-performance circuit designs.

  5. Highly Sensitive and Wearable In2O3Nanoribbon Transistor Biosensors with Integrated On-Chip Gate for Glucose Monitoring in Body Fluids.

    Science.gov (United States)

    Liu, Qingzhou; Liu, Yihang; Wu, Fanqi; Cao, Xuan; Li, Zhen; Alharbi, Mervat; Abbas, Ahmad N; Amer, Moh R; Zhou, Chongwu

    2018-02-27

    Nanoribbon- and nanowire-based field-effect transistor (FET) biosensors have stimulated a lot of interest. However, most FET biosensors were achieved by using bulky Ag/AgCl electrodes or metal wire gates, which have prevented the biosensors from becoming truly wearable. Here, we demonstrate highly sensitive and conformal In 2 O 3 nanoribbon FET biosensors with a fully integrated on-chip gold side gate, which have been laminated onto various surfaces, such as artificial arms and watches, and have enabled glucose detection in various body fluids, such as sweat and saliva. The shadow-mask-fabricated devices show good electrical performance with gate voltage applied using a gold side gate electrode and through an aqueous electrolyte. The resulting transistors show mobilities of ∼22 cm 2 V -1 s -1 in 0.1× phosphate-buffered saline, a high on-off ratio (10 5 ), and good mechanical robustness. With the electrodes functionalized with glucose oxidase, chitosan, and single-walled carbon nanotubes, the glucose sensors show a very wide detection range spanning at least 5 orders of magnitude and a detection limit down to 10 nM. Therefore, our high-performance In 2 O 3 nanoribbon sensing platform has great potential to work as indispensable components for wearable healthcare electronics.

  6. Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

    Energy Technology Data Exchange (ETDEWEB)

    Deen, David A., E-mail: david.deen@alumni.nd.edu; Storm, David F.; Scott Katzer, D.; Bass, R.; Meyer, David J. [Naval Research Laboratory, Electronics Science and Technology Division, Washington, DC 20375 (United States)

    2016-08-08

    A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain current after bias stressed in subthreshold. These structures additionally achieved small signal metrics f{sub t}/f{sub max} of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with f{sub t}/f{sub max} of 48/60 GHz.

  7. High performance TiN gate contact on AlGaN/GaN transistor using a mechanically strain induced P-doping

    Energy Technology Data Exchange (ETDEWEB)

    Soltani, A., E-mail: ali.soltani@iemn.univ-lille1.fr; Rousseau, M.; Gerbedoen, J.-C.; Bourzgui, N. [Institut d' Electronique de Microélectronique et de Nanotechnologie, UMR-CNRS 8520, USTL, Avenue Poincaré, 59652 Villeneuve d' Ascq (France); Mattalah, M. [Laboratoire de Microélectronique, Université Djilali Liabès, 22000 Sidi Bel Abbès (Algeria); Bonanno, P. L.; Ougazzaden, A. [School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30324-0250 (United States); UMI 2958 Georgia Tech-CNRS, Georgia Tech Lorraine, 2-3 Rue Marconi, 57070 Metz-Technopôle (France); Telia, A. [LMI, Electronic Department, Faculty of Engineering, Mentouri University of Constantine, Constantine (Algeria); Patriarche, G. [Laboratoire de Photonique et Nanostructures, CNRS UPR 20, Route de Nozay, 91460 Marcoussis (France); BenMoussa, A. [Solar Terrestrial Center of Excellence, Royal Observatory of Belgium, Circular 3, B-1180 Brussels (Belgium)

    2014-06-09

    High performance titanium nitride sub-100 nm rectifying contact, deposited by sputtering on AlGaN/GaN high electron mobility transistors, shows a reverse leakage current as low as 38 pA/mm at V{sub GS} = −40 V and a Schottky barrier height of 0.95 eV. Based on structural characterization and 3D simulations, it is found that the polarization gradient induced by the gate metallization forms a P-type pseudo-doping region under the gate between the tensile surface and the compressively strained bulk AlGaN barrier layer. The strain induced by the gate metallization can compensate for the piezoelectric component. As a result, the gate contact can operate at temperatures as high as 700 °C and can withstand a large reverse bias of up to −100 V, which is interesting for high-performance transistors dedicated to power applications.

  8. Effect of liquid gate bias rising time in pH sensors based on Si nanowire ion sensitive field effect transistors

    Science.gov (United States)

    Jang, Jungkyu; Choi, Sungju; Kim, Jungmok; Park, Tae Jung; Park, Byung-Gook; Kim, Dong Myong; Choi, Sung-Jin; Lee, Seung Min; Kim, Dae Hwan; Mo, Hyun-Sun

    2018-02-01

    In this study, we investigate the effect of rising time (TR) of liquid gate bias (VLG) on transient responses in pH sensors based on Si nanowire ion-sensitive field-effect transistors (ISFETs). As TR becomes shorter and pH values decrease, the ISFET current takes a longer time to saturate to the pH-dependent steady-state value. By correlating VLG with the internal gate-to-source voltage of the ISFET, we found that this effect occurs when the drift/diffusion of mobile ions in analytes in response to VLG is delayed. This gives us useful insight on the design of ISFET-based point-of-care circuits and systems, particularly with respect to determining an appropriate rising time for the liquid gate bias.

  9. Effects of the gate recess structure on the DC electrical behavior of 0.1-μm metamorphic high-electron-mobility transistors

    International Nuclear Information System (INIS)

    Oh, Jung-Hun; Son, Myung-Sik; Lee, Bok-Hyung; Baek, Yong-Hyun; Jang, Hae-Kang; Rhee, Jin-Koo; Hwang, In-Seok; Kim, Sam-Dong

    2004-01-01

    We examine the effects of the gate recess structure on the DC characteristics of 0.1-μm metamorphic high-electron-mobility transistors (MHEMTs). Compared to the wide gate recess structure, the narrow gate recess structure shows a significant increase in the drain-source saturation current from 440 to 710 mA/mm and in the extrinsic transconductance from 420 to 910 mS/mm. We propose that the observed variations in the DC characteristics are due to deep-level accepter-type interface traps formed between the silicon-nitride passivation layer and the Schottky barrier layer. We perform device simulations by using the hydrodynamic model based upon the proposed mechanism, and the simulation results show good agreement with the data obtained from the fabricated devices.

  10. Gate-tunable transport characteristics of Bi2S3 nanowire transistors

    Science.gov (United States)

    Kilcoyne, Colin; Ali, Ahmed H.; Alsaqqa, Ali M.; Rahman, Ajara A.; Whittaker-Brooks, Luisa; Sambandamurthy, Ganapathy

    2018-02-01

    Electrical transport and resistance noise spectroscopy measurements are performed on individual, single crystalline Bi2S3 nanowires in the field-effect geometry. The nanowires exhibit n-type conduction and device characteristics such as activation energy, ON/OFF ratio, and mobility are calculated over a temperature range of 120-320 K and at several bias values. The noise magnitude is measured between 0.01 and 5 Hz at several gate voltages as the device turns from it's OFF to ON state. The presence of mid-gap states which act as charge traps within the band gap can potentially explain the observed transport characteristics. Sulfur vacancies are the likely origin of these mid-gap states which makes Bi2S3 nanowires appealing for defect engineering as a means to enhance its optoelectronic properties and also to better understand the important role of defects in nanoscale semiconductors.

  11. Enhanced ZnO Thin-Film Transistor Performance Using Bilayer Gate Dielectrics

    KAUST Repository

    Alshammari, Fwzah Hamud

    2016-08-24

    We report ZnO TFTs using Al2O3/Ta2O5 bilayer gate dielectrics grown by atomic layer deposition. The saturation mobility of single layer Ta2O5 dielectric TFT was 0.1 cm2 V-1 s-1, but increased to 13.3 cm2 V-1 s-1 using Al2O3/Ta2O5 bilayer dielectric with significantly lower leakage current and hysteresis. We show that point defects present in ZnO film, particularly VZn, are the main reason for the poor TFT performance with single layer dielectric, although interfacial roughness scattering effects cannot be ruled out. Our approach combines the high dielectric constant of Ta2O5 and the excellent Al2O3/ZnO interface quality, resulting in improved device performance. © 2016 American Chemical Society.

  12. Study of surface-modified PVP gate dielectric in organic thin film transistors with the nano-particle silver ink source/drain electrode.

    Science.gov (United States)

    Yun, Ho-Jin; Ham, Yong-Hyun; Shin, Hong-Sik; Jeong, Kwang-Seok; Park, Jeong-Gyu; Choi, Deuk-Sung; Lee, Ga-Won

    2011-07-01

    We have fabricated the flexible pentacene based organic thin film transistors (OTFTs) with formulated poly[4-vinylphenol] (PVP) gate dielectrics treated by CF4/O2 plasma on poly[ethersulfones] (PES) substrate. The solution of gate dielectrics is made by adding methylated poly[melamine-co-formaldehyde] (MMF) to PVP. The PVP gate dielectric layer was cross linked at 90 degrees under UV ozone exposure. Source/drain electrodes are formed by micro contact printing (MCP) method using nano particle silver ink for the purposes of low cost and high throughput. The optimized OTFT shows the device performance with field effect mobility of the 0.88 cm2/V s, subthreshold slope of 2.2 V/decade, and on/off current ratios of 1.8 x 10(-6) at -40 V gate bias. We found that hydrophobic PVP gate dielectric surface can influence on the initial film morphologies of pentacene making dense, which is more important for high performance OTFTs than large grain size. Moreover, hydrophobic gate dielelctric surface reduces voids and -OH groups that interrupt the carrier transport in OTFTs.

  13. Remaining Useful Life Estimation of Insulated Gate Biploar Transistors (IGBTs Based on a Novel Volterra k-Nearest Neighbor Optimally Pruned Extreme Learning Machine (VKOPP Model Using Degradation Data

    Directory of Open Access Journals (Sweden)

    Zhen Liu

    2017-11-01

    Full Text Available The insulated gate bipolar transistor (IGBT is a kind of excellent performance switching device used widely in power electronic systems. How to estimate the remaining useful life (RUL of an IGBT to ensure the safety and reliability of the power electronics system is currently a challenging issue in the field of IGBT reliability. The aim of this paper is to develop a prognostic technique for estimating IGBTs’ RUL. There is a need for an efficient prognostic algorithm that is able to support in-situ decision-making. In this paper, a novel prediction model with a complete structure based on optimally pruned extreme learning machine (OPELM and Volterra series is proposed to track the IGBT’s degradation trace and estimate its RUL; we refer to this model as Volterra k-nearest neighbor OPELM prediction (VKOPP model. This model uses the minimum entropy rate method and Volterra series to reconstruct phase space for IGBTs’ ageing samples, and a new weight update algorithm, which can effectively reduce the influence of the outliers and noises, is utilized to establish the VKOPP network; then a combination of the k-nearest neighbor method (KNN and least squares estimation (LSE method is used to calculate the output weights of OPELM and predict the RUL of the IGBT. The prognostic results show that the proposed approach can predict the RUL of IGBT modules with small error and achieve higher prediction precision and lower time cost than some classic prediction approaches.

  14. Remaining Useful Life Estimation of Insulated Gate Biploar Transistors (IGBTs) Based on a Novel Volterra k-Nearest Neighbor Optimally Pruned Extreme Learning Machine (VKOPP) Model Using Degradation Data.

    Science.gov (United States)

    Liu, Zhen; Mei, Wenjuan; Zeng, Xianping; Yang, Chenglin; Zhou, Xiuyun

    2017-11-03

    The insulated gate bipolar transistor (IGBT) is a kind of excellent performance switching device used widely in power electronic systems. How to estimate the remaining useful life (RUL) of an IGBT to ensure the safety and reliability of the power electronics system is currently a challenging issue in the field of IGBT reliability. The aim of this paper is to develop a prognostic technique for estimating IGBTs' RUL. There is a need for an efficient prognostic algorithm that is able to support in-situ decision-making. In this paper, a novel prediction model with a complete structure based on optimally pruned extreme learning machine (OPELM) and Volterra series is proposed to track the IGBT's degradation trace and estimate its RUL; we refer to this model as Volterra k-nearest neighbor OPELM prediction (VKOPP) model. This model uses the minimum entropy rate method and Volterra series to reconstruct phase space for IGBTs' ageing samples, and a new weight update algorithm, which can effectively reduce the influence of the outliers and noises, is utilized to establish the VKOPP network; then a combination of the k -nearest neighbor method (KNN) and least squares estimation (LSE) method is used to calculate the output weights of OPELM and predict the RUL of the IGBT. The prognostic results show that the proposed approach can predict the RUL of IGBT modules with small error and achieve higher prediction precision and lower time cost than some classic prediction approaches.

  15. Dual-gate photo thin-film transistor: a “smart” pixel for high- resolution and low-dose X-ray imaging

    International Nuclear Information System (INIS)

    Wang, Kai; Ou, Hai; Chen, Jun

    2015-01-01

    Since its emergence a decade ago, amorphous silicon flat panel X-ray detector has established itself as a ubiquitous platform for an array of digital radiography modalities. The fundamental building block of a flat panel detector is called a pixel. In all current pixel architectures, sensing, storage, and readout are unanimously kept separate, inevitably compromising resolution by increasing pixel size. To address this issue, we hereby propose a “smart” pixel architecture where the aforementioned three components are combined in a single dual-gate photo thin-film transistor (TFT). In other words, the dual-gate photo TFT itself functions as a sensor, a storage capacitor, and a switch concurrently. Additionally, by harnessing the amplification effect of such a thin-film transistor, we for the first time created a single-transistor active pixel sensor. The proof-of-concept device had a W/L ratio of 250μm/20μm and was fabricated using a simple five-mask photolithography process, where a 130nm transparent ITO was used as the top photo gate, and a 200nm amorphous silicon as the absorbing channel layer. The preliminary results demonstrated that the photocurrent had been increased by four orders of magnitude due to light-induced threshold voltage shift in the sub-threshold region. The device sensitivity could be simply tuned by photo gate bias to specifically target low-level light detection. The dependence of threshold voltage on light illumination indicated that a dynamic range of at least 80dB could be achieved. The 'smart' pixel technology holds tremendous promise for developing high-resolution and low-dose X-ray imaging and may potentially lower the cancer risk imposed by radiation, especially among paediatric patients. (paper)

  16. Performance analysis of asymmetric dielectric modulated dual short gate tunnel field effect transistor

    Science.gov (United States)

    Pon, Adhithan; Carmel, A. Santhia; Bhattacharyya, A.; Ramesh, R.

    2018-01-01

    In this work, a novel asymmetric dielectric modulated dual short gate (ADMDG) TFET is designed and their performance was analysed. The ADMDG TFET using silicon, germanium, and SiGe as channel and source materials were simulated and results are compared with conventional DGTFET. The device simulation has been performed using Sentaurus TCAD simulator. It is found that the proposed structure provides overall improved performance for silicon TFET such as higher on-current (Ion = 4.2 μA), smaller SS = 40mV/decade and maximum Ion/Ioff ratio (8.2 × 1010) compared to conventional DGTFET. The on-current values obtained for SiGe source, Ge source and Ge channel ADMDG TFET are 0.22 mA, 0.69 mA and 0.14 mA respectively compared to silicon ADMDG TFET but compromises other dc parameters such as SS and Ion/Ioff ratio. For CMOS circuits, the p-type silicon TFET of the proposed structure were also simulated and presented. Moreover, the proposed TFET structure is also simulated for different temperatures and its performance were compared and analysed.

  17. Behavior of faulty double BJT BiCMOS logic gates

    Science.gov (United States)

    Menon, Sankaran M.; Malaiya, Yashwant K.; Jayasumana, Anura P.

    1992-01-01

    Logic Behavior of a Double BJT BiCMOS device under transistor level shorts and opens is examined. In addition to delay faults, faults that cause the gate to exhibit sequential behavior were observed. Several faults can be detected only by monitoring the current. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS, to bring out the testability differences.

  18. Coaxial-structured ZnO/silicon nanowires extended-gate field-effect transistor as pH sensor

    International Nuclear Information System (INIS)

    Li, Hung-Hsien; Yang, Chi-En; Kei, Chi-Chung; Su, Chung-Yi; Dai, Wei-Syuan; Tseng, Jung-Kuei; Yang, Po-Yu; Chou, Jung-Chuan; Cheng, Huang-Chung

    2013-01-01

    An extended-gate field-effect transistor (EGFET) of coaxial-structured ZnO/silicon nanowires as pH sensor was demonstrated in this paper. The oriented 1-μm-long silicon nanowires with the diameter of about 50 nm were vertically synthesized by the electroless metal deposition method at room temperature and were sequentially capped with the ZnO films using atomic layer deposition at 50 °C. The transfer characteristics (I DS –V REF ) of such ZnO/silicon nanowire EGFET sensor exhibited the sensitivity and linearity of 46.25 mV/pH and 0.9902, respectively for the different pH solutions (pH 1–pH 13). In contrast to the ZnO thin-film ones, the ZnO/silicon nanowire EGFET sensor achieved much better sensitivity and superior linearity. It was attributed to a high surface-to-volume ratio of the nanowire structures, reflecting a larger effective sensing area. The output voltage and time characteristics were also measured to indicate good reliability and durability for the ZnO/silicon nanowires sensor. Furthermore, the hysteresis was 9.74 mV after the solution was changed as pH 7 → pH 3 → pH 7 → pH 11 → pH 7. - Highlights: ► Coaxial-structured ZnO/silicon nanowire EGFET was demonstrated as pH sensor. ► EMD and ALD methods were proposed to fabricate ZnO/silicon nanowires. ► ZnO/silicon nanowire EGFET sensor achieved better sensitivity and linearity. ► ZnO/silicon nanowire EGFET sensor had good reliability and durability

  19. Off-state leakage current reduction in AlGaN/GaN high electron mobility transistors by combining surface treatment and post-gate annealing

    Science.gov (United States)

    Lu, Xing; Jiang, Huaxing; Liu, Chao; Zou, Xinbo; Lau, Kei May

    2016-05-01

    We report on the reduction of off-state leakage current in AlGaN/GaN high electron mobility transistors (HEMTs) by a two-step process combining pre-gate surface treatment and post-gate annealing (PGA), which suppressed the two leakage paths, namely, lateral surface leakage and vertical tunneling leakage, separately. The lateral surface leakage current, which was mainly induced by the high-density trap states generated during the device isolation etching process, was significantly reduced by a low power O2-plasma and HCl surface treatment process. The PGA process reduced the vertical tunneling leakage current by improving the Schottky contact quality of the transistor gate. Consequently, the device off-state leakage current was decreased by about 7 orders of magnitude and no degradation was introduced to the on-state performance, leading to a high on/off current ratio of 1010 and steep subthreshold slope (SS) of 62 mV/dec. The origin and leakage suppression mechanisms are also investigated and discussed in detail.

  20. Off-state leakage current reduction in AlGaN/GaN high electron mobility transistors by combining surface treatment and post-gate annealing

    International Nuclear Information System (INIS)

    Lu, Xing; Jiang, Huaxing; Liu, Chao; Zou, Xinbo; Lau, Kei May

    2016-01-01

    We report on the reduction of off-state leakage current in AlGaN/GaN high electron mobility transistors (HEMTs) by a two-step process combining pre-gate surface treatment and post-gate annealing (PGA), which suppressed the two leakage paths, namely, lateral surface leakage and vertical tunneling leakage, separately. The lateral surface leakage current, which was mainly induced by the high-density trap states generated during the device isolation etching process, was significantly reduced by a low power O 2 -plasma and HCl surface treatment process. The PGA process reduced the vertical tunneling leakage current by improving the Schottky contact quality of the transistor gate. Consequently, the device off-state leakage current was decreased by about 7 orders of magnitude and no degradation was introduced to the on-state performance, leading to a high on/off current ratio of 10 10 and steep subthreshold slope (SS) of 62 mV/dec. The origin and leakage suppression mechanisms are also investigated and discussed in detail. (paper)

  1. Decrease in effective electron mobility in the channel of a metal-oxide-semiconductor transistor as the gate length is decreased

    International Nuclear Information System (INIS)

    Frantsuzov, A. A.; Boyarkina, N. I.; Popov, V. P.

    2008-01-01

    Effective electron mobility μ eff in channels of metal-oxide-semiconductor transistors with a gate length L in the range of 3.8 to 0.34 μm was measured; the transistors were formed on wafers of the silicon-oninsulator type. It was found that μ eff decreases as L is decreased. It is shown that this decrease can be accounted for by the effect of series resistances of the source and drain only if it is assumed that there is a rapid increase in these resistances as the gate voltage is decreased. This assumption is difficult to substantiate. A more realistic model is suggested; this model accounts for the observed decrease in μ eff as L is decreased. The model implies that zones with a mobility lower than that in the middle part of the channel originate at the edges of the gate. An analysis shows that, in this case, the plot of the dependence of 1/μ eff on 1/L should be linear, which is exactly what is observed experimentally. The use of this plot makes it possible to determine both the electron mobility μ 0 in the middle part of the channel and the quantity A that characterizes the zones with lowered mobility at the gate’s edges.

  2. Effects of the gate dielectric on the subthreshold transport of carbon nanotube network transistors grown by using plasma-enhanced chemical vapor deposition

    International Nuclear Information System (INIS)

    Jeong, Seung Geun; Park, Wan Jun

    2010-01-01

    In this study, we investigated the subthreshold slope of random network carbon nanotube transistors with different geometries and passivations. Single-wall carbon nanotubes with lengths of 1-2 m were grown by using plasma-enhanced chemical vapor deposition to form the transistor channels. A critical channel length, where the subthreshold slope was saturated, of 7 μm was obtained. This was due to the percolational behavior of the nanotube random networks. With the dielectric passivation, the subthreshold slope was dramatically reduced from 9 V/decade to 0.9 V/decade by reducing interfacial trap sites, which then reduced the interface capacitance between the nanotube network and the gate dielectric.

  3. Multi-valued logic circuits using hybrid circuit consisting of three gates single-electron transistors (TG-SETs) and MOSFETs.

    Science.gov (United States)

    Shin, SeungJun; Yu, YunSeop; Choi, JungBum

    2008-10-01

    New multi-valued logic (MVL) families using the hybrid circuits consisting of three gates single-electron transistors (TG-SETs) and a metal-oxide-semiconductor field-effect transistor (MOSFET) are proposed. The use of SETs offers periodic literal characteristics due to Coulomb oscillation of SET, which allows a realization of binary logic (BL) circuits as well as multi-valued logic (MVL) circuits. The basic operations of the proposed MVL families are successfully confirmed through SPICE circuit simulation based on the physical device model of a TG-SET. The proposed MVL circuits are found to be much faster, but much larger power consumption than a previously reported MVL, and they have a trade-off between speed and power consumption. As an example to apply the newly developed MVL families, a half-adder is introduced.

  4. High-sensitivity pH sensor using separative extended-gate field-effect transistors with single-walled carbon-nanotube networks

    Science.gov (United States)

    Pyo, Ju-Young; Cho, Won-Ju

    2018-04-01

    We fabricate high-sensitivity pH sensors using single-walled carbon-nanotube (SWCNT) network thin-film transistors (TFTs). The sensing and transducer parts of the pH sensor are composed of separative extended-sensing gates (ESGs) with SnO2 ion-sensitive membranes and double-gate structure TFTs with thin SWCNT network channels of ∼1 nm and AlO x top-gate insulators formed by the solution-deposition method. To prevent thermal process-induced damages on the SWCNT channel layer due to the post-deposition annealing process and improve the electrical characteristics of the SWCNT-TFTs, microwave irradiation is applied at low temperatures. As a result, a pH sensitivity of 7.6 V/pH, far beyond the Nernst limit, is obtained owing to the capacitive coupling effect between the top- and bottom-gate insulators of the SWCNT-TFTs. Therefore, double-gate structure SWCNT-TFTs with separated ESGs are expected to be highly beneficial for high-sensitivity disposable biosensor applications.

  5. ZIF-67 derived porous Co3O4 hollow nanopolyhedron functionalized solution-gated graphene transistors for simultaneous detection of glucose and uric acid in tears.

    Science.gov (United States)

    Xiong, Can; Zhang, Tengfei; Kong, Weiyu; Zhang, Zhixiang; Qu, Hao; Chen, Wei; Wang, Yanbo; Luo, Linbao; Zheng, Lei

    2018-03-15

    Biomarkers in tears have attracted much attention in daily healthcare sensing and monitoring. Here, highly sensitive sensors for simultaneous detection of glucose and uric acid are successfully constructed based on solution-gated graphene transistors (SGGTs) with two separate Au gate electrodes, modified with GOx-CHIT and BSA-CHIT respectively. The sensitivity of the SGGT is dramatically improved by co-modifying the Au gate with ZIF-67 derived porous Co 3 O 4 hollow nanopolyhedrons. The sensing mechanism for glucose sensor is attributed to the reaction of H 2 O 2 generated by the oxidation of glucose near the gate, while the sensing mechanism for uric acid is due to the direct electro-oxidation of uric acid molecules on the gate. The optimized glucose and uric acid sensors show the detection limits both down to 100nM, far beyond the sensitivity required for non-invasive detection of glucose and uric acid in tears. The glucose and uric acid in real tear samples was quantitatively detected at 323.2 ± 16.1μM and 98.5 ± 16.3μM by using the functionalized SGGT device. Due to the low-cost, high-biocompatibility and easy-fabrication features of the ZIF-67 derived porous Co 3 O 4 hollow nanopolyhedron, they provide excellent electrocatalytic nanomaterials for enhancing sensitivity of SGGTs for a broad range of disease-related biomarkers. Copyright © 2017 Elsevier B.V. All rights reserved.

  6. Effect of a gate buffer layer on the performance of a 4H-SiC Schottky barrier field-effect transistor

    International Nuclear Information System (INIS)

    Zhang Xianjun; Yang Yintang; Chai Changchun; Duan Baoxing; Song Kun; Chen Bin

    2012-01-01

    A lower doped layer is inserted between the gate and channel layer and its effect on the performance of a 4H-SiC Schottky barrier field-effect transistor (MESFET) is investigated. The dependences of the drain current and small signal parameters on this inserted gate-buffer layer are obtained by solving one-dimensional (1-D) and two-dimensional (2-D) Poisson's equations. The drain current and small signal parameters of the 4H-SiC MESFET with a gate-buffer layer thickness of 0.15 μm are calculated and the breakdown characteristics are simulated. The results show that the current is increased by increasing the thickness of the gate-buffer layer; the breakdown voltage is 160 V, compared with 125 V for the conventional 4H-SiC MESFET; the cutoff frequency is 27 GHz, which is higher than 20 GHz of the conventional structure due to the lower doped gate-buffer layer. (semiconductor devices)

  7. P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

    Science.gov (United States)

    Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

    2018-04-01

    In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

  8. In(0.52)Al(0.48)/In(0.53)Ga(0.47)As heterojunction bipolar transistor on GaAs by molecular beam epitaxy

    Science.gov (United States)

    Won, T.; Agarwala, S.; Morkoc, H.

    1988-12-01

    The successful operation of In(0.52)Al(0.48)As/In(0.53)Ga(0.47)As NpN double heterojunction bipolar transistors grown on GaAs substrates is reported. A 10-period AlAs/In(0.52)Al(0.48)As (20 A/20 A) strained-layer superlattice was repeated twice with intervening undoped In(0.52)Al(0.48)As layers to suppress the propagation of threading dislocations to the surface. The typical common emitter gain in 50 x 50 micron-squared emitter area devices was 50, with a maximum of 63, at a collector current density of 2000 A/sq cm.

  9. Three-dimensional simulation of fabrication process-dependent effects on single event effects of SiGe heterojunction bipolar transistor

    International Nuclear Information System (INIS)

    Zhang Jin-Xin; Guo Bao-Long; Wu Xian-Xiang; He Chao-Hui; Li Pei; Guo Hong-Xia

    2017-01-01

    The fabrication process dependent effects on single event effects (SEEs) are investigated in a commercial silicon–germanium heterojunction bipolar transistor (SiGe HBT) using three-dimensional (3D) TCAD simulations. The influences of device structure and doping concentration on SEEs are discussed via analysis of current transient and charge collection induced by ions strike. The results show that the SEEs representation of current transient is different from representation of the charge collection for the same process parameters. To be specific, the area of C/S junction is the key parameter that affects charge collection of SEE. Both current transient and charge collection are dependent on the doping of collector and substrate. The base doping slightly influences transient currents of base, emitter, and collector terminals. However, the SEEs of SiGe HBT are hardly affected by the doping of epitaxial base and the content of Ge. (paper)

  10. Study About High Influence Doping to Base Resistance and Bandgap Narrowing at Si/Si1-xGex/Si Heterojunction Bipolar Transistor

    Directory of Open Access Journals (Sweden)

    Achmad Fadhol

    2010-10-01

    Full Text Available Heterojunction is a link formed bedween two semiconductor materials and differend bandgap which has thinness under 50nm and grow the mixture of plate SiGe as bases. The link is an abrupt link or graded one. In this research learnt formulation of doping concentration influence to basis resistance and bandgap narrowing through Si/Si1-xGex/Si Heterojunction Bipolar Transistor with abrupt emitter-basis link, besides taking care to mobility and basis wide to basis resistance, it is also influence of mole fraction to bandgap power. From the result shows that doping concentration addition of NB=5.1018 cm-3 to NB=5.1020 cm-3 in basis can decrease resistance basis value about 3.6%, increase bandgap narrowing about 0.126, and increase collector current density for about 1.36 times to Ge 24%.

  11. Effects of base doping and carrier lifetime on differential current gain and temperature coefficient of 4H-SiC power bipolar junction transistors

    Science.gov (United States)

    Niu, X.; Fardi, H.

    2012-04-01

    4H-SiC NPN bipolar junction transistor (BJT) is studied systematically by performing two-dimensional numerical simulations. Several design issues are discussed. Depending on the doping concentration of the base and the carrier lifetimes, both positive and negative temperature coefficients in the common emitter current gain could exist in 4H-SiC NPN BJTs with aluminium-doped base. The temperature coefficients of the current gain at different base doping concentrations and different carrier lifetimes have been determined. A high base doping concentration can reduce the requirement for the carrier lifetime in order to obtain negative temperature coefficient in current gain. Device simulations are performed to evaluate the carrier lifetimes by fitting the measured output IC -VCE curves. An excellent fitting is obtained and the base electron lifetime and the emitter hole lifetime are extracted to be about 22 and 5.7 ns, respectively.

  12. Extended Characterization of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

    Science.gov (United States)

    Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

    2013-01-01

    Collected data for both common-source and common-gate amplifiers is presented in this paper. Characterizations of the two amplifier circuits using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed with wider input frequency ranges and varying device sizes compared to earlier characterizations. The effects of the ferroelectric layer's capacitance and variation load, quiescent point, or input signal on each circuit are discussed. Comparisons between the MFSFET and MOSFET circuit operation and performance are discussed at length as well as applications and advantages for the MFSFETs.

  13. Pentacene thin-film transistors and inverters with plasma-enhanced atomic-layer-deposited Al2O3 gate dielectric

    International Nuclear Information System (INIS)

    Koo, Jae Bon; Lim, Jung Wook; Kim, Seong Hyun; Yun, Sun Jin; Ku, Chan Hoe; Lim, Sang Chul; Lee, Jung Hun

    2007-01-01

    The performances of pentacene thin-film transistor with plasma-enhanced atomic-layer-deposited (PEALD) 150 nm thick Al 2 O 3 dielectric are reported. Saturation mobility of 0.38 cm 2 /V s, threshold voltage of 1 V, subthreshold swing of 0.6 V/decade, and on/off current ratio of about 10 8 have been obtained. Both depletion and enhancement mode inverter have been realized with the change of treatment method of hexamethyldisilazane on PEALD Al 2 O 3 gate dielectric. Full swing depletion mode inverter has been demonstrated at input voltages ranging from 5 V to - 5 V at supply voltage of - 5 V

  14. A New Analytical Subthreshold Behavior Model for Single-Halo, Dual-Material Gate Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistor

    Science.gov (United States)

    Chiang, Te-Kuang

    2008-11-01

    On the basis of the exact solution of the two-dimensional Poisson equation, a new analytical subthreshold behavior model consisting of the two-dimensional potential, threshold voltage, and subthreshold current for the single-halo, dual-material gate (SHDMG) silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) is developed. The model is verified by the good agreement with a numerical simulation using the device simulator MEDICI. The model not only offers a physical insight into device physics but is also an efficient device model for the circuit simulation.

  15. Ester-free cross-linker molecules for ultraviolet-light-cured polysilsesquioxane gate dielectric layers of organic thin-film transistors

    Science.gov (United States)

    Okada, Shuichi; Nakahara, Yoshio; Uno, Kazuyuki; Tanaka, Ichiro

    2018-04-01

    Pentacene thin-film transistors (TFTs) were fabricated with ultraviolet-light (UV)-cured polysilsesquioxane (PSQ) gate dielectric layers using cross-linker molecules with or without ester groups. To polymerize PSQ without ester groups, thiol-ene reaction was adopted. The TFTs fabricated with PSQ layers comprising ester-free cross-linkers showed a higher carrier mobility than the TFTs with PSQ layers cross-linked with ester groups, which had large electric dipole moments that limited the carrier mobility. It was demonstrated that the thiol-ene reaction is more suitable than the conventional radical reaction for UV-cured PSQ with small dielectric constant.

  16. Gate voltage and drain current stress instabilities in amorphous In–Ga–Zn–O thin-film transistors with an asymmetric graphene electrode

    Directory of Open Access Journals (Sweden)

    Joonwoo Kim

    2015-09-01

    Full Text Available The gate voltage and drain current stress instabilities in amorphous In–Ga–Zn–O thin-film transistors (a-IGZO TFTs having an asymmetric graphene electrode structure are studied. A large positive shift in the threshold voltage, which is well fitted to a stretched-exponential equation, and an increase in the subthreshold slope are observed when drain current stress is applied. This is due to an increase in temperature caused by power dissipation in the graphene/a-IGZO contact region, in addition to the channel region, which is different from the behavior in a-IGZO TFTs with a conventional transparent electrode.

  17. Identification of Fixed and Interface Trap Charges in Hot-Carrier Stressed Metal Oxide Semiconductor Field Effect Transistors (MOSFET's) through Ultraviolet Light Anneal and Gate Capacitance Measurements

    Science.gov (United States)

    Ling, C.

    1995-01-01

    Fixed and interface trap charges in hot-carrier degraded metal oxide semiconductor field effect transistors (MOSFET's) can be distinguished by ultraviolet light (λ=253.7 nm) annealing, and observing the resultant changes in the gate-to-drain capacitance. Trapped electrons anneal readily, resulting in large changes in the gate capacitance and the threshold voltage. This suggests a trap level below the conduction band edge of SiO2 that is smaller than the photon energy (4.9 eV). In contrast, trapped holes and interface traps do not anneal, or anneal insignificantly even after prolonged irradiation. This is consistent with a much deeper hole trap level in SiO2, generally reported.

  18. High power gain switched laser diodes using a novel compact picosecond switch based on a GaAs bipolar junction transistor structure for pumping

    Science.gov (United States)

    Vainshtein, Sergey; Kostamovaara, Juha

    2006-04-01

    A number of up-to-date applications, including advanced optical radars with high single-shot resolution, precise 3 D imaging, laser tomography, time imaging spectroscopy, etc., require low-cost, compact, reliable sources enabling the generation of high-power (1-100 W) single optical pulses in the picosecond range. The well-known technique of using the gain-switching operation mode of laser diodes to generate single picosecond pulses in the mW range fails to generate high-power single picosecond pulses because of a lack of high-current switches operating in the picosecond range. We report here on the achieving of optical pulses of 45W / 70ps, or alternatively 5W / 40ps, with gain-switched commercial quantum well (QW) laser diodes having emitting areas of 250 × 200 μm and 75 × 2 μm, respectively. This was made possible by the use of a novel high-current avalanche switch based on a GaAs bipolar junction transistor (BJT) structure with a switching time (transistor structure.) A simulation code developed earlier but modified and carefully verified here allowed detailed comparison of the experimental and simulated laser responses and the transient spectrum.

  19. Design Optimization of Back-Gated Thin-Body Silicon-on-Insulator Capacitorless Dynamic Random Access Memory Cell

    Science.gov (United States)

    Cho, Min Hee; Shin, Changhwan; King Liu, Tsu-Jae

    2012-02-01

    Highly scaled (22 nm-node) capacitorless single-transistor dynamic random access memory (DRAM) cell design is investigated via technology computer-aided design (TCAD) simulations. It is found that the gate-sidewall spacer width and operating voltages can be adjusted to reduce band-to-band tunneling (BTBT) and thereby increase data retention time for bipolar junction transistor (BJT)-based operation. Read current variations due to random dopant fluctuations (RDF) are investigated via three-dimensional Kinetic Monte Carlo (KMC) simulations. It is found that BJT-based operation is more robust to RDF effects than metal-oxide-semiconductor field-effect transistor (MOSFET)-based operation.

  20. Ferroelectric/Dielectric Double Gate Insulator Spin-Coated Using Barium Titanate Nanocrystals for an Indium Oxide Nanocrystal-Based Thin-Film Transistor.

    Science.gov (United States)

    Pham, Hien Thu; Yang, Jin Ho; Lee, Don-Sung; Lee, Byoung Hun; Jeong, Hyun-Dam

    2016-03-23

    Barium titanate nanocrystals (BT NCs) were prepared under solvothermal conditions at 200 °C for 24 h. The shape of the BT NCs was tuned from nanodot to nanocube upon changing the polarity of the alcohol solvent, varying the nanosize in the range of 14-22 nm. Oleic acid-passivated NCs showed good solubility in a nonpolar solvent. The effect of size and shape of the BT NCs on the ferroelectric properties was also studied. The maximum polarization value of 7.2 μC/cm(2) was obtained for the BT-5 NC thin film. Dielectric measurements of the films showed comparable dielectric constant values of BT NCs over 1-100 kHz without significant loss. Furthermore, the bottom gate In2O3 NC thin film transistors exhibited outstanding device performance with a field-effect mobility of 11.1 cm(2) V(-1) s(-1) at a low applied gate voltage with BT-5 NC/SiO2 as the gate dielectric. The low-density trapped state was observed at the interface between the In2O3 NC semiconductor and the BT-5 NCs/SiO2 dielectric film. Furthermore, compensation of the applied gate field by an electric dipole-induced dipole field within the BT-5 NC film was also observed.

  1. A double-gate double-feedback JFET charge-sensitive preamplifier

    International Nuclear Information System (INIS)

    Fazzi, A.

    1996-01-01

    A new charge-sensitive preamplifier (CSP) without a physical resistance in the feedback is presented. The input device has to be a double-gate JFET. In this new preamplifier configuration the feedback capacitor is continuously discharged by means of a second DC current feedback loop closed through the bottom gate of the input JFET. The top gate-channel junction works as usual in reverse bias, the bottom gate-channel is forward biased. A fraction of the current injected by the bottom gate reaches the top gate discharging the feedback capacitor. The n-channel double-gate JFET is considered from the viewpoint of the restoring action as a parasitic p-n-p ''transversal'' bipolar junction transistor. The new preamplifier is also suited for detectors operating at room temperature with leakage current which may vary with time. The DC behaviour and the dynamic behaviour of the circuit is analyzed and new measurements presented. (orig.)

  2. A double-gate double-feedback JFET charge-sensitive preamplifier

    Energy Technology Data Exchange (ETDEWEB)

    Fazzi, A. [Politecnico di Milano (Italy). Centro Studi Nucleari E. Fermi; Rehak, P. [Brookhaven National Lab., Upton, NY (United States)

    1996-10-01

    A new charge-sensitive preamplifier (CSP) without a physical resistance in the feedback is presented. The input device has to be a double-gate JFET. In this new preamplifier configuration the feedback capacitor is continuously discharged by means of a second DC current feedback loop closed through the bottom gate of the input JFET. The top gate-channel junction works as usual in reverse bias, the bottom gate-channel is forward biased. A fraction of the current injected by the bottom gate reaches the top gate discharging the feedback capacitor. The n-channel double-gate JFET is considered from the viewpoint of the restoring action as a parasitic p-n-p ``transversal`` bipolar junction transistor. The new preamplifier is also suited for detectors operating at room temperature with leakage current which may vary with time. The DC behaviour and the dynamic behaviour of the circuit is analyzed and new measurements presented. (orig.).

  3. Contact effects analyzed by a parameter extraction method based on a single bottom-gate/top-contact organic thin-film transistor

    Science.gov (United States)

    Takagaki, Shunsuke; Yamada, Hirofumi; Noda, Kei

    2018-03-01

    Contact effects in organic thin-film transistors (OTFTs) were examined by using our previously proposed parameter extraction method from the electrical characteristics of a single staggered-type device. Gate-voltage-dependent contact resistance and channel mobility in the linear regime were evaluated for bottom-gate/top-contact (BGTC) pentacene TFTs with active layers of different thicknesses, and for pentacene TFTs with contact-doped layers prepared by coevaporation of pentacene and tetrafluorotetracyanoquinodimethane (F4TCNQ). The extracted parameters suggested that the influence of the contact resistance becomes more prominent with the larger active-layer thickness, and that contact-doping experiments give rise to a drastic decrease in the contact resistance and a concurrent considerable improvement in the channel mobility. Additionally, the estimated energy distributions of trap density in the transistor channel probably reflect the trap filling with charge carriers injected into the channel regions. The analysis results in this study confirm the effectiveness of our proposed method, with which we can investigate contact effects and circumvent the influences of characteristic variations in OTFT fabrication.

  4. Raman imaging of carrier distribution in the channel of an ionic liquid-gated transistor fabricated with regioregular poly(3-hexylthiophene).

    Science.gov (United States)

    Wada, Y; Enokida, I; Yamamoto, J; Furukawa, Y

    2018-02-02

    Raman images of carriers (positive polarons) at the channel of an ionic liquid-gated transistor (ILGT) fabricated with regioregular poly(3-hexylthiophene) (P3HT) have been measured with excitation at 785 nm. The observed spectra indicate that carriers generated are positive polarons. The intensities of the 1415 cm -1 band attributed to polarons in the P3HT channel were plotted as Raman images; they showed the carrier density distribution. When the source-drain voltage V D is lower than the source-gate voltage V G (linear region), the carrier density was uniform. When V D is nearly equal to V G (saturation region), a negative carrier density gradient from the source electrode towards the drain electrode was observed. This carrier density distribution is associated with the observed current-voltage characteristics, which is not consistent with the "pinch-off" theory of inorganic semiconductor transistors. Copyright © 2018 Elsevier B.V. All rights reserved.

  5. Fabrication of hybrid self-assembled monolayer/hafnium oxide gate dielectric by radical oxidation for molybdenum disulfide field-effect transistors

    Science.gov (United States)

    Kawanago, Takamasa; Ikoma, Ryo; Oba, Tomoaki; Takagi, Hiroyuki

    2017-11-01

    In this study, radical oxidation is applied to the fabrication of a hybrid self-assembled monolayer (SAM)/hafnium oxide (HfOx) gate dielectric in molybdenum disulfide (MoS2) field-effect transistors. The fabrication process involves radical oxidation to form HfOx at the surface of metallic HfN, SAM formation by immersion, and the deterministic transfer of MoS2 flakes. A subthreshold slope of 75 mV/dec and small hysteresis were demonstrated, indicating superior interfacial properties. Cross-sectional transmission electron microscopy revealed the uniform formation of the HfOx layer at the surface of HfN. The SAM is indispensable for the superior interfacial properties in MoS2 field-effect transistors. The radical oxidation is not restricted to the oxidation of silicon and germanium substrates and was also found to be applicable to the fabrication of a high-k gate dielectric. This study opens up interesting possibilities of radical oxidation for research on functional electronic devices.

  6. Evolution of the MOS transistor - From conception to VLSI

    International Nuclear Information System (INIS)

    Sah, C.T.

    1988-01-01

    Historical developments of the metal-oxide-semiconductor field-effect-transistor (MOSFET) during the last sixty years are reviewed, from the 1928 patent disclosures of the field-effect conductivity modulation concept and the semiconductor triodes structures proposed by Lilienfeld to the 1947 Shockley-originated efforts which led to the laboratory demonstration of the modern silicon MOSFET thirty years later in 1960. A survey is then made of the milestones of the past thirty years leading to the latest submicron silicon logic CMOS (Complementary MOS) and BICMOS (Bipolar-Junction-Transistor CMOS combined) arrays and the three-dimensional and ferroelectric extensions of Dennard's one-transistor dynamic random access memory (DRAM) cell. Status of the submicron lithographic technologies (deep ultra-violet light, X-ray, electron-beam) are summarized. Future trends of memory cell density and logic gate speed are projected. Comparisons of the switching speed of the silicon MOSFET with that of silicon bipolar and GaAs field-effect transistors are reviewed. Use of high-temperature superconducting wires and GaAs-on-Si monolithic semiconductor optical clocks to break the interconnect-wiring delay barrier is discussed. Further needs in basic research and mathematical modeling on the failure mechanisms in submicron silicon transistors at high electric fields (hot electron effects) and in interconnection conductors at high current densities and low as well as high electric fields (electromigration) are indicated

  7. Diode, transistor & fet circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Diode, Transistor and FET Circuits Manual is a handbook of circuits based on discrete semiconductor components such as diodes, transistors, and FETS. The book also includes diagrams and practical circuits. The book describes basic and special diode characteristics, heat wave-rectifier circuits, transformers, filter capacitors, and rectifier ratings. The text also presents practical applications of associated devices, for example, zeners, varicaps, photodiodes, or LEDs, as well as it describes bipolar transistor characteristics. The transistor can be used in three basic amplifier configuration

  8. Effects of HfO2/Al2O3 gate stacks on electrical performance of planar In x Ga1- x As tunneling field-effect transistors

    Science.gov (United States)

    Ahn, Dae-Hwan; Yoon, Sang-Hee; Takenaka, Mitsuru; Takagi, Shinichi

    2017-08-01

    We study the impact of gate stacks on the electrical characteristics of Zn-diffused source In x Ga1- x As tunneling field-effect transistors (TFETs) with Al2O3 or HfO2/Al2O3 gate insulators. Ta and W gate electrodes are compared in terms of the interface trap density (D it) of InGaAs MOS interfaces. It is found that D it is lower at the W/HfO2/Al2O3 InGaAs MOS interface than at the Ta/HfO2/Al2O3 interface. The In0.53Ga0.47As TFET with a W/HfO2 (2.7 nm)/Al2O3 (0.3 nm) gate stack of 1.4-nm-thick capacitance equivalent thickness (CET) has a steep minimum subthreshold swing (SS) of 57 mV/dec, which is attributed to the thin CET and low D it. Also, the In0.53Ga0.47As (2.6 nm)/In0.67Ga0.33As (3.2 nm)/In0.53Ga0.47As (96.5 nm) quantum-well (QW) TFET supplemented with this 1.4-nm-thick CET gate stack exhibits a steeper minimum SS of 54 mV/dec and a higher on-current (I on) than those of the In0.53Ga0.47As TFET.

  9. Capacitive effective thickness of a few nanometers by atomic layer deposition and device performance in Ge gate-all-around fin field effect transistors

    Science.gov (United States)

    Chu, Chu-Lin; Chen, Bo-Yuan; Fuh, Yiin-Kuen

    2015-10-01

    Ge gate-all-around fin field-effect transistors (Ge FinFETs) with a capacitive effective thickness of a few nanometers have been successfully achieved via atomic-layer-deposited (ALD) high-dielectric Al2O3 on GeO2/Ge and by adopting low-cost thermo ALD equipment. The MOS interface properties of the ZrO2 or Al2O3/GeO2/Ge structures have been studied systematically. It has been found that a GeO2 interfacial layer that is greater than approximately 2.5 nm results in a significant degradation of the MOS interfaces, while an equivalent oxide thickness of MOS interface quality obtained with the technique developed for high-permittivity/Ge gate stacks is also extremely useful for the fabrication of triangle-fin complementary metal oxide semiconductor devices. An I/I ratio of 3.2×104 and a subthreshold swing of 103 mV/dec were obtained for the triangular n-type Ge gate-all-around FET with (111) sidewalls. The drain current at VGS-VT=VDS=-1.5 V is 88 mA/mm.

  10. High-current and low acceleration voltage arsenic ion implanted polysilicon-gate and source-drain electrode Si mos transistor

    International Nuclear Information System (INIS)

    Saito, Yasuyuki; Sugimura, Yoshiro; Sugihara, Michiyuki

    1993-01-01

    The fabrication process of high current arsenic (As) ion implanted polysilicon (Si) gate and source drain (SD) electrode Si n-channel metal oxide-semiconductor field effect transistor (MOSFET) was examined. Poly Si film n-type doping was performed by using high current (typical current: 2mA) and relatively low acceleration voltage (40keV) As ion implantation technique (Lintott series 3). It was observed that high dose As implanted poly Si films as is show refractoriness against radical fluorine excited by microwave. Using GCA MANN4800 (m/c ID No.2, resist: OFPR) mask pattern printing technique, the high current As ion implantation technique and radical fluorine gas phase etching (Chemical dry etching: CDE) technique, the n-channel Poly Si gate (ρs = ≅100Ω/□) enhancement MQSFETs(ρs source drain = ≅50Ω/□, SiO 2 gate=380 angstrom) with off-leak-less were obtained on 3 inch Czochralski grown 2Ωcm boron doped p type wafers (Osaka titanium). By the same process, a 8 bit single chip μ-processor with 26MHz full operation was performed

  11. Contribution to the study of fluctuations in transistors (bipolar and junction field effect types); Contribution a l'etude des fluctuations dans les transistors (bipolaires et a effet champ a jonctions)

    Energy Technology Data Exchange (ETDEWEB)

    Borel, J. [Commissariat a l' Energie Atomique, Grenoble (France). Centre d' Etudes Nucleaires

    1970-07-01

    A brief review of the basic theory of fluctuations in semiconductors is given: shot, thermal low frequency noise. A measuring set has been built to draw noise spectrums (current or voltage). Noise parameters of bipolar transistors are given, mainly noise voltage. Noise current, noise factor and correlation between noise sources are also calculated. Measurements of noise parameters fit well with theory for various devices made in different technologies: alloyed, mesa, planar. Then we give results of the calculation of noise parameters in a FET starting from a simplified model of the device. Low frequency noise is taken into account. Measurements of the parameters and of the spectrum agree fairly well with the theory. Studies of low frequency noise versus temperature give the density and energy of traps located in the space charge layers and an idea of the impurity encountered in these space charge layers. [French] On rappelle les notions de base de la theorie des fluctuations dans les semiconducteurs: bruit de grenaille, bruit thermique, bruit basse frequence. Un appareillage mis au point pour tracer un spectre de bruit est decrit. On presente ensuite le calcul des parametres de bruit d'un transistor bipolaire en insistant plus particulierement sur la tension de bruit ramenee a l'entree de l'element. Le courant de bruit, le facteur de bruit et la correlation entre les sources de bruit sont calcules. La mesure des parametres de bruit est faite sur divers elements realises dans diverses technologies: alliee, mesa et plane. Les mesures confirment tres bien la theorie. On presente ensuite le calcul des parametres de bruit d'un transistor a effet de champ en definissant un schema equivalent simple de l'element. Le calcul theorique des fluctuations basse frequence est aussi fait. La mesure du spectre de bruit confirme tres bien les calculs theoriques. L'etude du bruit basse frequence en fonction de la temperature permet de remonter a la

  12. Estudio teórico y práctico del régimen de avalancha en los transistores bipolares

    Directory of Open Access Journals (Sweden)

    Yunior Ávila Vázquez

    2011-09-01

    Full Text Available Normal 0 21 false false false MicrosoftInternetExplorer4 /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Tabla normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} Se realiza un estudio teórico de la zona de ruptura por avalancha de los Transistores Bipolares y la caracterización de los mismos en dichas condiciones extremas de trabajo, para obtener los datos necesarios y de esta manera un criterio de selección, que permitan utilizarlos en un generador de pulsos, basado en la topología del banco de Marx y lograr un funcionamiento adecuado de este, aunque estos transistores no estén diseñados para trabajar en avalancha. Normal 0 21 false false false MicrosoftInternetExplorer4 /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Tabla normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;}

  13. Low-Frequency Noise Characterization of Ultra-shallow Gate N-channel Junction Field Effect Transistors

    NARCIS (Netherlands)

    Piccolo, G.; Sarubbi, F.; Vandamme, L.J.K.; Macucci, M.; Scholtes, T.L.M.; Nanver, Lis Karen

    2007-01-01

    A recently developed technique for ultra shallow pn junction formation has been applied for the fabrication of ring-gate n-channel junction field effect devices (JFET) devices. Several different geometries, gate formation parameters and channel doping profiles have been realized and characterized

  14. A High-Precision Adaptive Thermal Network Model for Monitoring of Temperature Variations in Insulated Gate Bipolar Transistor (IGBT Modules

    Directory of Open Access Journals (Sweden)

    Ning An

    2018-03-01

    Full Text Available This paper proposes a novel method for optimizing the Cauer-type thermal network model considering both the temperature influence on the extraction of parameters and the errors caused by the physical structure. In terms of prediction of the transient junction temperature and the steady-state junction temperature, the conventional Cauer-type parameters are modified, and the general method for estimating junction temperature is studied by using the adaptive thermal network model. The results show that junction temperature estimated by our adaptive Cauer-type thermal network model is more accurate than that of the conventional model.

  15. A 10 kW dc-dc converter using IGBTs with active snubbers. [Insulated Gate Bipolar Transistor

    Science.gov (United States)

    Masserant, Brian J.; Shriver, Jeffrey L.; Stuart, Thomas A.

    1993-01-01

    This full bridge dc-dc converter employs zero voltage switching (ZVS) on one leg and zero current switching (ZCS) on the other. This technique produces exceptionally low IGBT switching losses through the use of an active snubber that recycles energy back to the source. Experimental results are presented for a 10 kW, 20 kHz converter.

  16. Nanoscale Vacuum Channel Transistor.

    Science.gov (United States)

    Han, Jin-Woo; Moon, Dong-Il; Meyyappan, M

    2017-04-12

    Vacuum tubes that sparked the electronics era had given way to semiconductor transistors. Despite their faster operation and better immunity to noise and radiation compared to the transistors, the vacuum device technology became extinct due to the high power consumption, integration difficulties, and short lifetime of the vacuum tubes. We combine the best of vacuum tubes and modern silicon nanofabrication technology here. The surround gate nanoscale vacuum channel transistor consists of sharp source and drain electrodes separated by sub-50 nm vacuum channel with a source to gate distance of 10 nm. This transistor performs at a low voltage (3 microamperes). The nanoscale vacuum channel transistor can be a possible alternative to semiconductor transistors beyond Moore's law.

  17. Two-dimensional analytical model for hetero-junction double-gate tunnel field-effect transistor with a stacked gate-oxide structure

    Science.gov (United States)

    Xu, Hui Fang; Gui Guan, Bang

    2017-05-01

    A two-dimensional analytical model for hetero-junction double-gate tunnel FETs (DG TFETs) with a stacked gate-oxide structure is proposed in this paper. The effects of both the channel mobile charges and source/drain depletion regions on the channel potential profile are considered for the higher accuracy of the proposed model. Poisson’s equation is solved using the superposition principle and Fourier series solution to model the channel potential. The band-to-band tunneling generation rate is expressed as a function of the channel electric field derived from the channel potential and then integrated analytically to derive the drain current of the hetero-junction DG TFETs with a stacked gate-oxide structure using the shortest tunneling path. The effects of device parameters on the channel potential, drain current, and transconductance are investigated. Very good agreements are observed between the model calculations and the simulated results.

  18. Quantum ballistic analysis of transition metal dichalcogenides based double gate junctionless field effect transistor and its application in nano-biosensor

    Science.gov (United States)

    Shadman, Abir; Rahman, Ehsanur; Khosru, Quazi D. M.

    2017-11-01

    To reduce the thermal budget and the short channel effects in state of the art CMOS technology, Junctionless field effect transistor (JLFET) has been proposed in the literature. Numerous experimental, modeling, and simulation based works have been done on this new FET with bulk materials for various geometries until now. On the other hand, the two-dimensional layered material is considered as an alternative to current Si technology because of its ultra-thin body and high mobility. Very recently few simulation based works have been done on monolayer molybdenum disulfide based JLFET mainly to show the advantage of JLFET over conventional FET. However, no comprehensive simulation-based work has been done for double gate JLFET keeping in mind the prominent transition metal dichalcogenides (TMDC) to the authors' best knowledge. In this work, we have studied quantum ballistic drain current-gate voltage characteristics of such FETs within non-equilibrium Green's function (NEGF) framework. Our simulation results reveal that all these TMDC materials are viable options for implementing state of the art Junctionless MOSFET with emphasis on their performance at short gate lengths. Besides evaluating the prospect of TMDC materials in the digital logic application, the performance of Junctionless Double Gate trilayer TMDC heterostructure FET for the label-free electrical detection of biomolecules in dry environment has been investigated for the first time to the authors' best knowledge. The impact of charge neutral biomolecules on the electrical characteristics of the biosensor has been analyzed under dry environment situation. Our study shows that these materials could provide high sensitivity in the sub-threshold region as a channel material in nano-biosensor, a trend demonstrated by silicon on insulator FET sensor in the literature. Thus, going by the trend of replacing silicon with these novel materials in device level, TMDC heterostructure could be a viable alternative to

  19. Amorphous silicon germanium carbide photo sensitive bipolar junction transistor with a base-contact and a continuous tunable high current gain

    Energy Technology Data Exchange (ETDEWEB)

    Bablich, A., E-mail: andreas.bablich@uni-siegen.de [Department of Electrical and Computer Engineering, Institute for Microsystem Technologies, University of Siegen, Hoelderlinstrasse 3, 57076 Siegen (Germany); Merfort, C., E-mail: merfort@imt.e-technik.uni-siegen.de [Department of Electrical and Computer Engineering, Institute for Microsystem Technologies, University of Siegen, Hoelderlinstrasse 3, 57076 Siegen (Germany); Eliasz, J., E-mail: jacek.eliasz@student.uni-siegen.de [Department of Electrical and Computer Engineering, Institute for Microsystem Technologies, University of Siegen, Hoelderlinstrasse 3, 57076 Siegen (Germany); Schäfer-Eberwein, H., E-mail: heiko.schaefer@uni-siegen.de [Department of Electrical and Computer Engineering, Institute of High Frequency and Quantum Electronics, University of Siegen, Hoelderlinstrasse 3, 57076 Siegen (Germany); Haring-Bolivar, P., E-mail: peter.haring@uni-siegen.de [Department of Electrical and Computer Engineering, Institute of High Frequency and Quantum Electronics, University of Siegen, Hoelderlinstrasse 3, 57076 Siegen (Germany); Boehm, M., E-mail: markus.boehm@uni-siegen.de [Department of Electrical and Computer Engineering, Institute for Microsystem Technologies, University of Siegen, Hoelderlinstrasse 3, 57076 Siegen (Germany)

    2014-05-02

    In this paper, the design, fabrication and characterization of an amorphous silicon germanium carbide (a-SiGeC:H) photo sensitive bipolar junction transistor (PS-BJT) with three terminals are presented. Whereas the current gain of similar transistor devices presented in the past (Wu et al., 1984; Hwang et al., 1993; Nascetti and Caputo, 2002; Chang et al., 1985a,b; Wu et al, 1985; Hong et al., 1990) can only be controlled with photo induced charge generation, the n–i–δp–i–n structure developed features a contacted base to provide the opportunity to adjust the current gain optically and electrically, too. Electron microscope-, current-/voltage- and spectral measurements were performed to study the PS-BJT behavior and calculate the electrical and optical current gain. The spectral response maximum of the base–collector diode has a value of 170 mA/W applying a base–collector voltage of − 1 V and is located at 620 nm. The base–emitter diode reaches a sensitivity of 25.7 mA/W at 530 nm with a base-emitter voltage of − 3 V. The good a-Si:H transport properties are validated in a μτ-product of 4.6 × 10{sup −6} cm{sup 2} V s, which is sufficient to reach a continuous base- and photo-tunable current gain of up to − 126 at a base current of I{sub B} = + 10 nA and a collector–emitter voltage of V{sub CE} = − 3 V. The transistor obtains a maximum collector current of − 65.5 μA (V{sub CE} = − 3 V) and + 56.2 μA (V{sub CE} = + 3 V) at 10,000 lx 5300 K white-light illumination. At 3300 lx, the electrical current gain reaches a value of + 100 (V{sub CE} = + 2 V) at I{sub B} = 10 nA. With a negative base current of I{sub B} = − 10 nA the electrical gain can be adjusted between 87 (V{sub CE} = + 2 V) and − 106 (V{sub CE} = -3 V), respectively. When no base charge is applied, the transistor is “off” for V{sub CE} > − 3 V. Reducing the base current increases the electrical current gain. Operating with a voltage V{sub CE} of just ± 2 V

  20. 5 V driving organic non-volatile memory transistors with poly(vinyl alcohol) gate insulator and poly(3-hexylthiophene) channel layers

    Science.gov (United States)

    Nam, Sungho; Seo, Jooyeok; Kim, Hwajeong; Kim, Youngkyoo

    2015-10-01

    Organic non-volatile memory devices were fabricated by employing organic field-effect transistors (OFETs) with poly(vinyl alcohol) (PVA) and poly(3-hexylthiophene) as a gate insulating layer and a channel layer, respectively. The 10-nm-thick nickel layers were inserted for better charge injection between the channel layer and the top source/drain electrodes. The fabricated PVA-OFET memory devices could be operated at low voltages (≤5 V) and showed pronounced hysteresis characteristics in the transfer curves, even though very small hysteresis was measured from the output curves. The degree of hysteresis was considerably dependent on the ratio of channel width (W) to channel length (L). The PVA-OFET memory device with the smaller W/L ratio (25) exhibited better retention characteristics upon 700 cycles of writing-reading-erasing-reading operations, which was assigned to the stability of charged states in devices.