A new front-end ASIC for GEM detectors with time and charge measurement capabilities

Energy Technology Data Exchange (ETDEWEB)

Ciciriello, F., E-mail: fabio.ciciriello@poliba.it [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Corsi, F. [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); De Robertis, G. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Felici, G. [INFN, Laboratori Nazionali di Frascati, Via E. Fermi 40, I-00044 Frascati (Italy); Loddo, F. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Marzocca, C.; Matarrese, G. [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Ranieri, A. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy)

2016-07-11

A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e{sup −} for a detector capacitance of 10 pF. © 2001 Elsevier Science. All rights reserved.

Design and Measurement of a Low-Noise 64-Channels Front-End Readout ASIC for CdZnTe Detectors

Energy Technology Data Exchange (ETDEWEB)

Gan, Bo; Wei, Tingcun; Gao, Wu; Liu, Hui; Hu, Yann [School of Computer Science and Technology, Northwestern Polytechnical University, Xi' an (China)

2015-07-01

Cadmium zinc telluride (CdZnTe) detectors, as one of the principal detectors for the next-generation X-ray and γ-ray imagers, have high energy resolution and supporting electrode patterning in the radiation environment at room-temperature. In the present, a number of internationally renowned research institutions and universities are actively using these detector systems to carry out researches of energy spectrum analysis, medical imaging, materials characterization, high-energy physics, nuclear plant monitoring, and astrophysics. As the most important part of the readout system for the CdZnTe detector, the front-end readout application specific integrated circuit (ASIC) would have an important impact on the performances of the whole detector system. In order to ensure the small signal to noise ratio (SNR) and sufficient range of the output signal, it is necessary to design a front-end readout ASIC with very low noise and very high dynamic range. In addition, radiation hardness should be considered when the detectors are utilized in the space applications and high energy physics experiments. In this paper, we present measurements and performances of a novel multi-channel radiation-hardness low-noise front-end readout ASIC for CdZnTe detectors. The readout circuits in each channel consist of charge sensitive amplifier, leakage current compensation circuit (LCC), CR-RC shaper, S-K filter, inverse proportional amplifier, peak detect and hold circuit (PDH), discriminator and trigger logic, time sequence control circuit and driving buffer. All of 64 readout channels' outputs enter corresponding inputs of a 64 channel multiplexer. The output of the mux goes directly out of the chip via the output buffer. The 64-channel readout ASIC is implemented using the TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 2.7 mm x 8 mm. At room temperature, the equivalent noise level of a typical channel reaches 66 e{sup -} (rms) at zero farad for a

A 32-channel front-end ASIC for GEM detectors used in beam monitoring applications

Science.gov (United States)

Ciciriello, F.; Altieri, P. R.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Lorusso, L.; Marzocca, C.; Matarrese, G.; Ranieri, A.; Stamerra, A.

2017-11-01

A multichannel, mixed-signal, front-end ASIC for GEM detectors, intended for beam monitoring in hadron therapy applications, has been designed and prototyped in a standard 0.35 μm CMOS technology. The analog channels are based on the classic CSA + shaper processing chain, followed by a peak detector which can work as an analog memory, to simplifiy the analog-to-digital conversion of the peak voltage of the output pulse, proportional to the energy of the detected event. The available hardware resources include an 8-bit A/D converter and a standard-cell digital part, which manages the read-out procedure, in sparse or serial mode. The ASIC is self-triggered and transfers energy and address data to the external DAQ via a fast 100 MHz LVDS link. Preliminary characterization results show that the non-linearity error is limited to 5% for a maximum input charge of about 70 fC, the measured ENC is about 1400e- and the time jitter of the trigger signal generated in response to an injected charge of 60 fC is close to 200 ps.

PARISROC, an autonomous front-end ASIC for triggerless acquisition in next generation neutrino experiments

Science.gov (United States)

Conforti Di Lorenzo, S.; Campagne, J. E.; Drouet, S.; Dulucq, F.; El Berni, M.; Genolini, B.; de La Taille, C.; Martin-Chassard, G.; Seguin Moreau, N.; Wanlin, E.; Xiangbo, Y.

2012-12-01

PARISROC (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is a complete readout chip in AustriaMicroSystems (AMS) SiGe 0.35 μm technology designed to read array of 16 Photomultipliers (PMTs). The ASIC is realized in the context of the PMm2 (square meter PhotoMultiplier) project that has proposed a new system of “smart photo-detectors” composed by sensor and read-out electronics dedicated to next generation neutrino experiments. The future water Cherenkov detectors will take place in megaton size water tanks then with a large surface of photo-detection. We propose to segment the large surface in arrays with a single front-end electronics and only the useful data send in surface to be stocked and analyzed. This paper describes the second version of the ASIC and illustrates the chip principle of operation and the main characteristics thank to a series of measurements. It is a 16-channel ASIC with channels that work independently, in triggerless mode and all managed by a common digital part. Then main innovation is that all the channels are handled independently by the digital part so that only channels that have triggered are digitized. Then the data are transferred to the internal memory and sent out in a data driven way. The ASIC allows charge and time measurement. We measured a charge measurement range starting from 160 fC (1 photoelectron-p.e., at PMT gain of 106) to 100 pC (around 600 p.e.) at 1% of linearity; time tagging at 1 ns thanks to a 24-bit counter at 10 MHz and a Time to Digital Converter (TDC) on a 100 ns ramp.

PARISROC, an autonomous front-end ASIC for triggerless acquisition in next generation neutrino experiments

International Nuclear Information System (INIS)

Conforti Di Lorenzo, S.; Campagne, J.E.; Drouet, S.; Dulucq, F.; El Berni, M.; Genolini, B.; La Taille, C. de; Martin-Chassard, G.; Seguin Moreau, N.; Wanlin, E.; Xiangbo, Y.

2012-01-01

PARISROC (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is a complete readout chip in AustriaMicroSystems (AMS) SiGe 0.35 μm technology designed to read array of 16 Photomultipliers (PMTs). The ASIC is realized in the context of the PMm2 (square meter PhotoMultiplier) project that has proposed a new system of “smart photo-detectors” composed by sensor and read-out electronics dedicated to next generation neutrino experiments. The future water Cherenkov detectors will take place in megaton size water tanks then with a large surface of photo-detection. We propose to segment the large surface in arrays with a single front-end electronics and only the useful data send in surface to be stocked and analyzed. This paper describes the second version of the ASIC and illustrates the chip principle of operation and the main characteristics thank to a series of measurements. It is a 16-channel ASIC with channels that work independently, in triggerless mode and all managed by a common digital part. Then main innovation is that all the channels are handled independently by the digital part so that only channels that have triggered are digitized. Then the data are transferred to the internal memory and sent out in a data driven way. The ASIC allows charge and time measurement. We measured a charge measurement range starting from 160 fC (1 photoelectron-p.e., at PMT gain of 10 6 ) to 100 pC (around 600 p.e.) at 1% of linearity; time tagging at 1 ns thanks to a 24-bit counter at 10 MHz and a Time to Digital Converter (TDC) on a 100 ns ramp.

A Front-End ASIC with Receive Sub-array Beamforming Integrated with a 32 × 32 PZT Matrix Transducer for 3-D Transesophageal Echocardiography

NARCIS (Netherlands)

Chen, C.; Chen, Z.; Bera, Deep; Raghunathan, S.B.; ShabaniMotlagh, M.; Noothout, E.C.; Chang, Z.Y.; Ponte, Jacco; Prins, Christian; Vos, H.J.; Bosch, Johan G.; Verweij, M.D.; de Jong, N.; Pertijs, M.A.P.

2017-01-01

This paper presents a power-and area-efficient front-end application-specific integrated circuit (ASIC) that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography.

ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

International Nuclear Information System (INIS)

Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

2002-01-01

An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

NINO An ultra-fast and low-power front-end amplifier/discriminator ASIC designed for the multigap resistive plate chamber

CERN Document Server

Anghinolfi, F; Martemyanov, A N; Usenko, E; Wenninger, Horst; Williams, M C S; Zichichi, A

2004-01-01

For the full exploitation of the excellent timing properties of the Multigap Resistive Plate Chamber (MRPC), front-end electronics with special characteristics are needed. These are (a) differential input, to profit from the differential signal from the MRPC (b) a fast amplifier with less than 1 ns peaking time and (c) input charge measurement by Time-Over-Threshold for slewing correction. An 8- channel amplifier and discriminator chip has been developed to match these requirements. This is the NINO ASIC, fabricated with 0.25 omegam CMOS technology. The power requirement at 40mW/channel is low. Results on the performance of the MRPCs using the NINO ASIC are presented. Typical time resolution a of the MRPC system is in the 50 ps range, with an efficiency of 99.9%.

SENSROC4: An Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

International Nuclear Information System (INIS)

Gao, W.; Liu, H.; Gao, D.; Gan, B.; Wei, T.; Hu, Y.

2013-06-01

In this paper, we present the design of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for our small animal PET systems which objective is to achieve the following performances, the spatial resolution of 1 mm 3 , the detection efficiency of 15 % and the time resolution of 1 ns. A cascade amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuit is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. Based on the above techniques, an eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm x 2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 V/pC. The best test result of ENC is 86.5 e- at zero farad plus 9.3 e- per pico-farad. The nonlinearity is less than 3 %. The crosstalk is less than 2 %. The power dissipation is about 9 mW/channel (authors)

The multichannel amplifier/discriminator CMOS ASIC for visual light photon counters

International Nuclear Information System (INIS)

Baturitsky, M.A.; Yurenya, Yu.P.Yu.P.

2002-01-01

The 18-channel CMOS custom monolithic amplifier/discriminator ASIC was designed as a front-end electronics chip for Visual Light Photon Counters which convert photons from scintillation fibre/strip detectors to electrical signals. One ASICs channel contains a charge-sensitive preamplifier, a discriminator to mark the arrival time of signals, and a charge divider to provide analog outputs for analog-to-digital conversion being performed by SVX2. The ASIC is proposed as one of the variants for possible future front-end electronics upgrading the D0 Central Fibre Tracker, Central and Forward Pre-Showers (Fermilab, Batavia, USA)

The VFAT3-Comm-Port: a complete communication port for front-end ASICs intended for use within the high luminosity radiation environments of the LHC

International Nuclear Information System (INIS)

Dabrowski, M.; Aspell, P.; Bonacini, S.; Ciaglia, D.; Kloukinas, K.; Lentdecker, G. De; Robertis, G. De; Kupiainen, M.; Talvitie, J.; Tuuva, T.; Leroux, P.; Tavernier, F.

2015-01-01

This paper presents the VFAT3 Comm-Port (V3CP), which offers a single port for all communication to and from a front-end ASIC within the HL-LHC environment. This includes synchronization to the LHC clock, slow control communication, the execution of fast control commands and the readout of data

Low noise preamplifier ASIC for the PANDA experiment

International Nuclear Information System (INIS)

Flemming, H; Wieczorek, P

2011-01-01

For the electromagnetic calorimeter of the PANDA detector a preamplifier ASIC named APFEL (ASIC for Panda Front-end ELectronics) has been developed at GSI. It is optimized for the readout of large area avalanche photodiodes (LAAPDs) with a capacitance of 300 pF and an event rate of 350 kHz. The ASIC has two equivalent analog channels each consisting of a charge sensitive amplifier, a shaper stage and differential output drivers. For operating the ASIC in a wide temperature range programmable voltage references are implemented on chip.

AVME readout module for multichannel ASIC characterization

International Nuclear Information System (INIS)

Borkar, S.P.; Lalwani, S.K.; Ghodgaonkar, M.D.; Kataria, S.K.; Reynaud, Serge; )

2004-01-01

Electronics Division, BARC has been working on the development of multi-channel ASIC, called SPAIR (Silicon-strip Pulse Amplifier Integrated Readout). It contains 8 channels of preamplifier, shaper and track-and-hold circuitry. Electronics Division has also actively participated in development of test setup for the front-end ASIC, called PACE, for the preshower detector of the Compact Muon Solenoid (CMS) Experiment at CERN, Geneva. PACE is a 32 channel ASIC for silicon strip detector, containing preamplifier, shaper, calibration circuitry, switched capacitor array, readout amplifier per channel and an analog multiplexer. A VME Readout Module, (VRM) is developed which can be utilized in data acquisition from ASICs like PACE and SPAIR. The VRM can also be used as the Detector Dependent Unit for digitally processing the data received from the front-end electronics on the 16-bit LVDS port. The processed, data can be read by the VME system. Thus the VRM is very useful in building an ASIC characterization system and/or the automated ASIC production testing system. It can be used also to build the applications using such ASICs. To cater to various requirements arising in future, variety of VME modules are to be developed like ADCs, DACs and D 1/0. VME interface remains a common part to all these modules. The different functional blocks of these modules can be designed and fabricated on small piggyback boards (called Test Boards) and mounted on the VRM, which provides the common VME interface. The design details and uses of VRM are presented here. (author)

FRONT-END ASIC FOR HIGH RESOLUTION X-RAY SPECTROMETERS

International Nuclear Information System (INIS)

DE GERONIMO, G.; CHEN, W.; FRIED, J.; LI, Z.; PINELLI, D.A.; REHAK, P.; VERNON, E.; GASKIN, J.A.; RAMSEY, B.D.; ANELLI, G.

2007-01-01

We present an application specific integrated circuit (ASIC) for high-resolution x-ray spectrometers. The ASIC is designed to read out signals from a pixelated silicon drift detector (SDD). Each hexagonal pixel has an area of 15 mmz and an anode capacitance of less than 100 fF. There is no integrated Field Effect transistor (FET) in the pixel, rather, the readout is done by wirebonding the anodes to the inputs of the ASIC. The ASIC provides 14 channels of low-noise charge amplification, high-order shaping with baseline stabilization, and peak detection with analog memory. The readout is sparse and based on low voltage differential signaling. An interposer provides all the interconnections required to bias and operate the system. The channel dissipates 1.6 mW. The complete 14-pixel unit covers an area of 210 mm 2 , dissipates 12 mW cm -2 , and can be tiled to cover an arbitrarily large detection area. We measured a preliminary resolution of 172 eV at -35 C on the 6 keV peak of a 55 Fe source

Development and characterisation of a front-end ASIC for macro array of photo-detectors of large dimensions

International Nuclear Information System (INIS)

Conforti Di Lorenzo, S.

2010-10-01

The coverage of large areas of photo-detection is a crucial element of experiments studying high energy atmospheric cosmic showers and neutrinos from different sources. The objective of this project is to realize big detectors using thousands of photomultipliers (PMT). The project proposes to segment the large surface of photo-detection into macro pixels consisting of an array of 16 PMT of 12 inches (2*2 m 2 ), connected to an autonomous front-end electronics which works in without-trigger data acquisition mode placed near the array. This is possible thanks to the microelectronics progress that allows to integrate the readout and the signal processing, of all the multipliers, in the same circuit (ASIC) named PARISROC (Photomultiplier Array Integrated ins SiGe Read Out Chip). The ASIC must only send out the digital data by network to the surface central data storage. The PARISROC chip made in AM's Silicon Germanium (SiGe) 0.35 μm technology, integrates 16 independent channels for each PMT of the array, providing charge and time measurements. The first prototype of PARISROC chip has a total surface of 19 mm 2 . The ASIC measurements have led to the realization of a second prototype. Important measurements were performed in terms of noise, dynamic range, readout frequency (from 10 MHz to 40 MHz), time measurements (TDC improvements) and charge measurements (Slow shaper improvements). This new prototype of PARISROC-2 has been tested and the characterisation has shown a good overall behavior and the verification of the improvements. (author)

Single event effect hardness for the front-end ASICs in the DAMPE satellite BGO calorimeter

Science.gov (United States)

Gao, Shan-Shan; Jiang, Di; Feng, Chang-Qing; Xi, Kai; Liu, Shu-Bin; An, Qi

2016-01-01

The Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray studies with a primary scientific goal of indirect detection of dark matter particles. As a crucial sub-detector, the BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of more than 3 years makes single event effects (SEEs) become threats to reliability. In order to evaluate SEE sensitivities of these chips and verify the effectiveness of mitigation methods, a series of laser-induced and heavy ion-induced SEE tests were performed. Benefiting from the single event latch-up (SEL) protection circuit for power supply, the triple module redundancy (TMR) technology for the configuration registers and the optimized sequential design for the data acquisition process, 52 VA160 chips and 32 VATA160 chips have been applied in the flight model of the BGO calorimeter with radiation hardness assurance. Supported by Strategic Priority Research Program on Space Science of the Chinese Academy of Sciences (XDA04040202-4) and Fundamental Research Funds for the Central Universities (WK2030040048)

NINO ASIC electronics used in MRPC/TOF experiment

International Nuclear Information System (INIS)

Sun Yongjie; Li Cheng

2008-01-01

In order to meet the excellent properties of MRPC, an front-end amplifier/discriminator chip-NINO ASIC, was developed in ALICE TOF group at CERN. This ASIC was fabricated with the 0.25 μm CMOS technology. It is highly integrated and can deal with 8 channels per chip. It has differential input and is differential signal shaping and throughout transition. The peaking time of the amplifier is less than 1 ns. It has LVDS outputs and the width of the output signal depended on the charge of input. This allows the TOT measurement of HPTDC system. A position sensitive MRPC was tested with beam facility using the front-end electronics based on NINO and good results were obtained. (authors)

Readout ASICs and Electronics for the 144-channel HAPDs for the Aerogel RICH at Belle II

Science.gov (United States)

Nishida, S.; Adachi, I.; Ikeda, H.; Hara, K.; Iijima, T.; Iwata, S.; Korpar, S.; Križan, P.; Kuroda, E.; Pestotnik, R.; Seljak, A.; Sumiyoshi, T.; Takagaki, H.

The particle identification (PID) device in the endcap of the Belle detector will be upgraded to a ring imaging Cherenkov counter (RICH) using aerogel as a radiator at the Belle II experiment. We develop the electronics to read out the 70,000 channels of hit information from the 144-channel hybrid avalanche photodetectors (HAPD), of the aerogel RICH detector. A readout ASIC is developed to digitize the HAPD signals, and was used in a beam test with the prototype detector. The performance and plan of the ASIC is reported in this study. We have also designed the readout electronics for the aerogel RICH, which consist of front-end boards with the ASICs merger boards to collect data from the front-end boards. A front-end board that fits in the actual available space for the aerogel RICH electronics was produced.

PACE3 - front-end chip for the CMS Preshower

CERN Multimedia

Aspel, Paul

2003-01-01

This is PACE3 which is the front-end chip for the CMS Preshower. In fact PACE3 is the combination of two ASICs called Delta3 and PACEAM3. Delta3 is on the left and PACEAM3 is on the right. The two ASICs are bonded together and then packaged within a single 196 pin fpBGA package.

A time-based front-end ASIC for the silicon micro strip sensors of the bar PANDA Micro Vertex Detector

Science.gov (United States)

Di Pietro, V.; Brinkmann, K.-Th.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Zambanini, A.

2016-03-01

The bar PANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA (bar PANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels.

Low power frontend ASIC (Anusuchak) for dosimeter using Si-PIN detector

International Nuclear Information System (INIS)

Darad, A.; Chandratre, V.B.

2010-01-01

A low power ASIC (Anusuchak) for silicon PIN detector signal processing channel designed for pocket dosimeter in 0.35 μm CMOS process. The ASIC contains two channels one for Beta particle and other for Gamma ray. The channel is a CSA integrated with a shaper, gain stage and comparator with total power consumption of 4.6 mW. The ASIC has gain of 12 mV/fC and can be raised to 29 mV/fC without degrading the noise, power or linearity specification of the channel. The channel has a peaking time of 1.2 μs with baseline recovery within 5.3 μs and noise figure of 420 e- at 0 pF. The noise slope is 17 e-/pF. The ASIC is designed for single supply of 3.3 V for which battery is available. (author)

Hybrid circuit prototypes for the CMS Tracker upgrade front-end electronics

International Nuclear Information System (INIS)

Blanchot, G; Honma, A; Kovacs, M; Braga, D; Raymond, M

2013-01-01

New high-density interconnect hybrid circuits are under development for the CMS tracker modules at the HL-LHC. These hybrids will provide module connectivity between flip-chip front-end ASICs, strip sensors and a service board for the data transmission and powering. Rigid organic-based substrate prototypes and also a flexible hybrid design have been built, containing up to eight front-end flip chip ASICs. A description of the function of the hybrid circuit in the tracker, the first prototype designs, results of some electrical and mechanical properties from the prototypes, and examples of the integration of the hybrids into detector modules are presented

Integrated input protection against discharges for Micro Pattern Gas Detectors readout ASICs

International Nuclear Information System (INIS)

Fiutowski, T.; Dąbrowski, W.; Koperny, S.; Wiącek, P.

2017-01-01

Immunity against possible random discharges inside active detector volume of MPGDs is one of the key aspects that should be addressed in the design of the front-end electronics. This issue becomes particularly critical for systems with high channel counts and high density readout employing the front-end electronics built as multichannel ASICs implemented in modern CMOS technologies, for which the breakdown voltages are in the range of a few Volts. The paper presents the design of various input protection structures integrated in the ASIC manufactured in a 350 nm CMOS process and test results using an electrical circuit to mimic discharges in the detectors.

A time-based front-end ASIC for the silicon micro strip sensors of the P-bar ANDA Micro Vertex Detector

International Nuclear Information System (INIS)

Pietro, V. Di; Brinkmann, K.-Th.; Riccardi, A.; Ritman, J.; Stockmanns, T.; Zambanini, A.; Rivetti, A.; Rolo, M.D.

2016-01-01

The P-bar ANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA ( P-bar ANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels

SPACIROC2: a front-end readout ASIC for the JEM-EUSO observatory

International Nuclear Information System (INIS)

Ahmad, S; Barrillon, P; Blin-Bondil, S; Dagoret-Campagne, S; Taille, C de La; Dulucq, F; Martin-Chassard, G; Kawasaki, Y; Miyamoto, H; Ikeda, H; Iguchi, T; Kajino, F

2013-01-01

The SPACIROC ASIC is designed for the JEM-EUSO observatory onboard of the International Space Station (ISS). The main goal of JEM-EUSO is to observe Extensive Air Shower (EAS) produced in the atmosphere by the passage of the high energetic extraterrestrial particles above a few 10 19 eV. A low-power, rad-hard ASIC is proposed for reading out the 64-channel Multi-Anode Photomultipliers which are going to equip the detection surface of JEM-EUSO. The two main features of this ASIC are the photon counting mode for each input and the charge-to-time (Q-to-T) conversion for the multiplexed channels. In the photon counting mode, the 100% triggering efficiency is achieved for 50 fC input charges. For the Q-to-T converter, the ASIC requires a minimum input of 2 pC. In order to comply with the strict power budget available from the ISS, the ASIC is needed to dissipate less than 1 mW/channel. The design of SPACIROC and the test results are presented in this paper.

A protocol for hit and control synchronous transfer for the front-end electronics at the CBM experiment

Energy Technology Data Exchange (ETDEWEB)

Kasinski, K., E-mail: kasinski@agh.edu.pl [AGH University of Science and Technology, Department of Measurement and Electronics, Av. Mickiewicza 30, 30-059 Cracow (Poland); Szczygiel, R. [AGH University of Science and Technology, Department of Measurement and Electronics, Av. Mickiewicza 30, 30-059 Cracow (Poland); Zabolotny, W. [Institute of Electronic Systems, Warsaw University of Technology, ul. Nowowiejska 15/19, 00-665 Warsaw (Poland); Lehnert, J.; Schmidt, C.J. [GSI Helmholtzzentrum für Schwerionenforschung GmbH, Planckstrasse 1, 64-291 Darmstadt (Germany); Müller, W.F.J. [FAIR Facility for Antiproton and Ion Research in Europe GmbH, Planckstrasse 1, 64-291 Darmstadt (Germany)

2016-11-01

The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.

A protocol for hit and control synchronous transfer for the front-end electronics at the CBM experiment

International Nuclear Information System (INIS)

Kasinski, K.; Szczygiel, R.; Zabolotny, W.; Lehnert, J.; Schmidt, C.J.; Müller, W.F.J.

2016-01-01

The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.

The GBT-SCA, a radiation tolerant ASIC for detector control applications in SLHC experiments

CERN Document Server

Gabrielli, A; Kloukinas, K; Marchioro, A; Moreira, P; Ranieri, A; De Robertis, D

2009-01-01

This work describes the architecture of the GigaBit Transceiver – Slow Control Adapter (GBT–SCA) ASIC suitable for the control and monitoring applications of the embedded front-end electronics in the future SLHC experiments. The GBT–SCA is part the GBT chipset currently under development for the SLHC detector upgrades. It is designed for radiation tolerance and it will be fabricated in a commercial 130 nm CMOS technology. The paper discusses the GBT-SCA architecture, the data transfer protocol, the ASIC interfaces, and its integration with the GBT optical link. The GBT–SCA is one the components of the GBT system chipset. It is proposed for the future SLHC experiments and is designed to be configurable matching different front-end system requirements. The GBT-SCA is intended for the slow control and monitoring of the embedded front end electronics and implements a point-to-multi point connection between one GBT optical link ASIC and several front end ASICs. The GBT-SCA connects to a dedicated electrica...

Radiation hardness on very front-end for SPD

International Nuclear Information System (INIS)

Cano, Xavier; Graciani, Ricardo; Gascon, David; Garrido, Lluis; Bota, Sebastia; Herms, Atila; Comerma, Albert; Riera, Jordi

2005-01-01

The calorimeter front-end electronics of the LHCb experiment will be located in a region, which is not protected from radiation. Therefore, all the electronics must be qualified to stand some defined radiation levels. The procedure, measurements and results of an irradiation test for every component of the very front-end SPD detector, which is part of the LHCb calorimeter are presented here. All the tested components, except a custom made ASIC, are commercially available

Anode front-end electronics for the cathode strip chambers of the CMS Endcap Muon detector

International Nuclear Information System (INIS)

Ferguson, T.; Bondar, N.; Golyash, A.; Sedov, V.; Terentiev, N.; Vorobiev, I.

2005-01-01

The front-end electronics system for the anode signals of the CMS Endcap Muon cathode strip chambers has about 183,000 channels. The purposes of the anode front-end electronics are to acquire precise muon timing information for bunch crossing number identification at the Level-1 muon trigger system and to provide a coarse radial position of the muon track. Each anode channel consists of an input protection network, amplifier, shaper, constant-fraction discriminator, and a programmable delay. The essential parts of the electronics include a 16-channel amplifier-shaper-discriminator ASIC CMP16 and a 16-channel ASIC D16G providing programmable time delay. The ASIC CMP16 was optimized for the large cathode chamber size (up to 3x2.5 m 2 ) and for the large input capacitance (up to 200 pF). The ASIC combines low power consumption (30 mW/channel) with good time resolution (2-3 ns). The delay ASIC D16G makes possible the alignment of signals with an accuracy of 2.2 ns. This paper presents the anode front-end electronics structure and results of the preproduction and the mass production tests, including radiation resistance and reliability tests. The special set of test equipment, techniques, and corresponding software developed and used in the test procedures are also described

Development of a 32-channel ASIC for an X-ray APD detector onboard the ISS

Science.gov (United States)

Arimoto, Makoto; Harita, Shohei; Sugita, Satoshi; Yatsu, Yoichi; Kawai, Nobuyuki; Ikeda, Hirokazu; Tomida, Hiroshi; Isobe, Naoki; Ueno, Shiro; Mihara, Tatehiro; Serino, Motoko; Kohmura, Takayoshi; Sakamoto, Takanori; Yoshida, Atsumasa; Tsunemi, Hiroshi; Hatori, Satoshi; Kume, Kyo; Hasegawa, Takashi

2018-02-01

We report on the design and performance of a mixed-signal application specific integrated circuit (ASIC) dedicated to avalanche photodiodes (APDs) in order to detect hard X-ray emissions in a wide energy band onboard the International Space Station. To realize wide-band detection from 20 keV to 1 MeV, we use Ce:GAGG scintillators, each coupled to an APD, with low-noise front-end electronics capable of achieving a minimum energy detection threshold of 20 keV. The developed ASIC has the ability to read out 32-channel APD signals using 0.35 μm CMOS technology, and an analog amplifier at the input stage is designed to suppress the capacitive noise primarily arising from the large detector capacitance of the APDs. The ASIC achieves a performance of 2099 e- + 1.5 e-/pF at root mean square (RMS) with a wide 300 fC dynamic range. Coupling a reverse-type APD with a Ce:GAGG scintillator, we obtain an energy resolution of 6.7% (FWHM) at 662 keV and a minimum detectable energy of 20 keV at room temperature (20 °C). Furthermore, we examine the radiation tolerance for space applications by using a 90 MeV proton beam, confirming that the ASIC is free of single-event effects and can operate properly without serious degradation in analog and digital processing.

Macro Pixel ASIC (MPA): The readout ASIC for the pixel-strip (PS) module of the CMS outer tracker at HL-LHC

CERN Document Server

Ceresa, Davide; Kloukinas, Konstantinos; Jan Kaplon; Bialas, Wojciech; Re, Valerio; Traversi, Gianluca; Gaioni, Luigi; Ratti, Lodovico

2014-01-01

The CMS tracker at HL-LHC is required to provide prompt information on particles with high transverse momentum to the central Level\\,1 trigger. For this purpose, the innermost part of the outer tracker is based on a combination of a pixelated sensor with a short strip sensor, the so-called Pixel-Strip module (PS). The readout of these sensors is carried out by distinct ASICs, the Strip Sensor ASIC (SSA), for the strip layer, and the Macro Pixel ASIC (MPA) for the pixel layer. The processing of the data directly on the front-end module represents a design challenge due to the large data volume (30720\\,pixels and 1920\\,strips per module) and the limited power budget. This is the reason why several studies have been carried out to find the best compromise between ASICs performance and power consumption. This paper describes the current status of the MPA ASIC development where the logic for generating prompt information on particles with high transverse momentum is implemented. An overview of the readout method i...

ENC Measurement for ASIC Preamp Board as a Detector Module for PET System

Directory of Open Access Journals (Sweden)

N. Nagara

2016-08-01

Full Text Available We developed a gamma ray detector with an LuAG:Pr scintillator and an avalanche photodiode as a detector for a positron emission tomography (PET system. Studies have been performed on the influences of gamma irradiation on application-specific integrated circuit (ASIC preamp boards used as a detector module. As a device used in nuclear environments for substantial durations, the ASIC has to have a lifetime long enough to ensure that there will be a negligible failure rate during this period. These front-end systems must meet the requirements for standard positron emission tomography (PET systems. Therefore, an equivalent noise charge (ENC experiment is needed to measure the front-end system's characteristics. This study showed that minimum ENC conditions can be achieved if a shorter shaping time could be applied.

An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras

Energy Technology Data Exchange (ETDEWEB)

Bolotnikov, A. E., E-mail: bolotnik@bnl.gov; Ackley, K.; Camarda, G. S.; Cherches, C.; Cui, Y.; De Geronimo, G.; Fried, J.; Hossain, A.; Mahler, G.; Maritato, M.; Roy, U.; Salwen, C.; Vernon, E.; Yang, G.; James, R. B. [Brookhaven National Laboratory, Upton, New York 11793 (United States); Hodges, D. [University of Texas at El Paso, El Paso, Texas 79968 (United States); Lee, W. [Korea University, Seoul 136-855 (Korea, Republic of); Petryk, M. [SUNY Binghamton, Vestal, New York 13902 (United States)

2015-07-15

We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm{sup 3} detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays’ performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.

VMM - An ASIC for Micropattern Detectors

Directory of Open Access Journals (Sweden)

Iakovidis George

2018-01-01

Full Text Available The VMM is a custom Application Specific Integrated Circuit (ASIC that can be used in a variety of charge interpolating tracking detectors. It is designed to be used with the resistive strip micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is designed at Brookhaven National Laboratory and fabricated in the 130 nm Global Foundries 8RF-DM process. It is packaged in a Ball Grid Array with outline dimensions of 21×21 mm2. It integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog-to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM1 and VMM2 are the first two versions of the VMM ASIC family fabricated in 2012 and 2014 respectively. The design, tests and qualification of the VMM1, VMM2 and roadmap to VMM3 are described.

VMM - An ASIC for Micropattern Detectors

Science.gov (United States)

Iakovidis, George

2018-02-01

The VMM is a custom Application Specific Integrated Circuit (ASIC) that can be used in a variety of charge interpolating tracking detectors. It is designed to be used with the resistive strip micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is designed at Brookhaven National Laboratory and fabricated in the 130 nm Global Foundries 8RF-DM process. It is packaged in a Ball Grid Array with outline dimensions of 21×21 mm2. It integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog-to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM1 and VMM2 are the first two versions of the VMM ASIC family fabricated in 2012 and 2014 respectively. The design, tests and qualification of the VMM1, VMM2 and roadmap to VMM3 are described.

VMM - An ASIC for micropattern detectors

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00215906; The ATLAS collaboration; Polychronakos, Venetios; De Geronimo, Gianluigi

2015-01-01

The VMM is a custom Application Specific Integrated Circuit (ASIC) that can be used in a variety of charge interpolating tracking detectors. It is designed to be used with the resistive strip micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is designed at Brookhaven National Laboratory and fabricated in the 130 nm Global Foundries 8RF-DM process. It is packaged in a Ball Grid Array with outline dimensions of 21 $\\times$ 21 mm$^2$. It integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog-to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM1 and VMM2 are the first two versions of the VMM ASIC family fabricated in 2012 and 2014 respectively. The design, tests and qualification of the VMM1, VMM2 and roadmap to VMM3 are...

Four-channel readout ASIC for silicon pad detectors

International Nuclear Information System (INIS)

Baturitsky, M.A.; Zamiatin, N.I.

2000-01-01

A custom front-end readout ASIC has been designed for silicon calorimeters supposed to be used in high-energy physics experiments. The ASIC was produced using BJT-JFET technology. It contains four channels of a fast low-noise charge-sensitive preamplifier (CSP) with inverting outputs summed by a linear adder (LA) followed by an RC-CR shaping amplifier (SA) with 30 ns peaking time. Availability of separate outputs of the CSPs and the LA makes it possible to join any number of silicon detector layers to obtain the longitudinal and transversal resolution required using only this ASIC in any silicon calorimeter minitower configuration. Noise performance is ENC=1800e - +18e - /pF at 30 ns peaking time for detector capacitance up to C d =400 pF. Rise time is 8 ns at input capacitance C d =100 pF. Power dissipation is less than 50 mW/ chip at voltage supply 5 V

A comparative study of the time performance between NINO and FlexToT ASICs

International Nuclear Information System (INIS)

Sarasola, I.; Rato, P.; Marín, J.; Nemallapudi, M.V.; Gundacker, S.; Auffray, E.; Sánchez, D.; Gascón, D.

2017-01-01

Universitat de Barcelona (UB) and CIEMAT have designed the FlexToT ASIC for the front-end readout of SiPM-based scintillator detectors. This ASIC is aimed at time of flight (ToF) positron emission tomography (PET) applications. In this work we have evaluated the time performance of the FlexToT v2 ASIC compared to the NINO ASIC, a fast ASIC developped at CERN. NINO electronics give 64 ps sigma for single-photon time resolution (SPTR) and 93 ps FWHM for coincidence time resolution (CTR) with 2 × 2 × 5 mm 3 LSO:Ce,Ca crystals and S13360-3050CS SiPMs. Using the same SiPMs and crystals, the FlexToT v2 ASIC yields 91 ps sigma for SPTR and 123 ps FWHM for CTR. Despite worse time performace than NINO, FlexToT v2 features lower power consumption (11 vs. 27 mW/ch) and linear ToT energy measurement.

Irradiation of the CLARO-CMOS chip, a fast ASIC for single-photon counting

International Nuclear Information System (INIS)

Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Fiorini, M.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

2015-01-01

The CLARO-CMOS is a prototype ASIC that allows fast photon counting with low power consumption, built in AMS 0.35 μm CMOS technology. It is intended to be used as a front-end readout for the upgraded LHCb RICH detectors. In this environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade, the ASIC must withstand a total fluence of about 6×10 12 1 MeV n eq /cm 2 and a total ionising dose of 400 krad. Long term stability of the electronics front-end is essential and the effects of radiation damage on the CLARO-CMOS performance must be carefully studied. This paper describes results of multi-step irradiation tests with protons up to the dose of ~8 Mrad, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step

Development of front-end ASIC for radiation detection and measurement

International Nuclear Information System (INIS)

Shimazoe, K.

2014-01-01

For realizing the multichannel spectroscopy of gamma rays, the technology of integrated circuits is necessary. Multi-channel gamma ray spectroscopy is very important for many applications including the medical imaging and the environmental monitoring. The current progress in the development of application specific integrated circuit (ASIC) for multi-channel radiation detection is introduced and reviewed. (author)

Performance of the front-end electronics of the ANTARES neutrino telescope

NARCIS (Netherlands)

Aguilar, J. A.; Al Samarai, I.; Albert, A.; Anghinolfi, M.; Anton, G.; Anvar, S.; Ardid, M.; Jesus, A. C. Assis; Astraatmadja, T.; Aubert, J-J; Auer, R.; Baret, B.; Basa, S.; Bazzotti, M.; Bertin, V.; Biagi, S.; Bigongiari, C.; Bou-Cabo, M.; Bouwhuis, M. C.; Brown, A.; Brunner, J.; Busto, J.; Camarena, F.; Capone, A.; Caponetto, L.; Carloganu, C.; Carminati, G.; Carr, J.; Castorina, E.; Cavasinni, V.; Cecchini, S.; Chaleil, Th; Charvis, [No Value; Chiarusi, T.; Sen, N. Chon; Circella, M.; Costantini, H.; Cottini, N.; Coyle, P.; Curtil, C.; De Bonis, G.; de Botton, N.; Dekeyser, I.; Delagnes, E.; Deschamps, A.; Distefano, C.; Donzaud, C.; Dornic, D.; Drouhin, D.; Druillole, F.; Eberl, T.; Emanuele, U.; Ernenwein, J-P; Escoffier, S.; Falchini, E.; Fehr, F.; Feinstein, F.; Flaminio, V.; Fopma, J.; Fratini, K.; Fritsch, U.; Fuda, J-L; Gay, P.; Giacomelli, G.; Gomez-Gonzalez, J. P.; Graf, K.; Guillard, G.; Halladjian, G.; Hallewell, G.; Hoffmann, C.; van Haren, H.; Heijboer, A. J.; Hello, Y.; Hernandez-Rey, J. J.; Herold, B.; Hoessl, J.; de Jong, M.; Kalantar-Nayestanaki, N.; Kalekin, O.; Kappes, A.; Katz, U.; Kooijman, P.; Kopper, C.; Kouchner, A.; Kretschmer, W.; Lachartre, D.; Lafoux, H.; Lahmann, R.; Lamare, P.; Lambard, G.; Larosa, G.; Laschinsky, H.; Le Provost, H.; Le Van Suu, A.; Lefevre, D.; Legou, T.; Lelaizant, G.; Lim, G.; Lo Presti, D.; Loehner, H.; Loucatos, S.; Lucarelli, F.; Mangano, S.; Marcelin, M.; Margiotta, A.; Martinez-Mora, J. A.; Mazure, A.; Monmarthe, E.; Montaruli, T.; Morganti, M.; Moscoso, L.; Motz, H.; Naumann, C.; Neff, M.; Olivetto, Ch; Ostasch, R.; Palioselitis, D.; Pavala, G. E.; Payre, P.; Petrovic, J.; Piattelli, P.; Picot-Clemente, N.; Picq, C.; Pineau, J-P; Poinsignon, J.; Popa, V.; Pradier, T.; Presani, E.; Racca, C.; Radu, A.; Reed, C.; Rethore, F.; Riccobene, G.; Richardt, C.; Rujoiu, M.; Russo, G. V.; Salesa, F.; Sapienza, P.; Schoeck, F.; Schuller, J. P.; Shanidze, R.; Simeone, F.; Spurio, M.; Steijger, J. J. M.; Stolarczyk, Th.; Tamburini, C.; Tasca, L.; Toscano, S.; Vallage, B.; Van Elewyck, V.; Vannoni, G.; Vecchi, M.; Vernin, P.; Wijnker, G.; de Wolf, E.; Yepes, H.; Zaborov, D.; Zornoza, J. D.; Zuniga, J.

2010-01-01

ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube

The GBT-SCA, a radiation tolerant ASIC for detector control and monitoring applications in HEP experiments

International Nuclear Information System (INIS)

Caratelli, A.; Bonacini, S.; Kloukinas, K.; Marchioro, A.; Moreira, P.; Oliveira, R. De; Paillard, C.

2015-01-01

The future upgrades of the LHC experiments will increase the beam luminosity leading to a corresponding growth of the amounts of data to be treated by the data acquisition systems. To address these needs, the GBT (Giga-Bit Transceiver optical link [1,2]) architecture was developed to provide the simultaneous transfer of readout data, timing and trigger signals as well as slow control and monitoring data. The GBT-SCA ASIC, part of the GBT chip-set, has the purpose to distribute control and monitoring signals to the on-detector front-end electronics and perform monitoring operations of detector environmental parameters. In order to meet the requirements of different front-end ASICs used in the experiments, it provides various user-configurable interfaces capable to perform simultaneous operations. It is designed employing radiation tolerant design techniques to ensure robustness against SEUs and TID radiation effects and is implemented in a commercial 130 nm CMOS technology. This work presents the GBT-SCA architecture, the ASIC interfaces, the data transfer protocol, and its integration with the GBT optical link

ASIC design in the KM3NeT detector

International Nuclear Information System (INIS)

Gajanana, D; Gromov, V; Timmer, P

2013-01-01

In the KM3NeT project [1], Cherenkov light from the muon interactions with transparent matter around the detector, is used to detect neutrinos. Photo multiplier tubes (PMT) used as photon sensor, are housed in a glass sphere (aka Optical Module) to detect single photons from the Cherenkov light. The PMT needs high operational voltage ( ∼ 1.5 kV) and is generated by a Cockroft-Walton (CW) multiplier circuit. The electronics required to control the PMT's and collect the signals is integrated in two ASIC's namely: 1) a front-end mixed signal ASIC (PROMiS) for the readout of the PMT and 2) an analog ASIC (CoCo) to generate pulses for charging the CW circuit and to control the feedback of the CW circuit. In this article, we discuss the two integrated circuits and test results of the complete setup. PROMiS amplifies the input charge, converts it to a pulse width and delivers the information via LVDS signals. These LVDS signals carry accurate information on the Time of arrival ( 2 C bus. This unique combination of the ASIC's results in a very cost and power efficient PMT base design.

LHCb: Test Station for the LHCb Muon Front-End Electronic

CERN Multimedia

Polycarpo, E

2005-01-01

The LHCb Muon Group has developed the CMOS ASIC CARIOCA to readout its Multiwire Proportional Chambers (MWPC) and GEM detectors, using a rad-hard IBM 0.25um process. Each ASIC holds 8 identical current-mode ASDB channels with individual input thresholds. The Muon detector contains around 120000 physical channels, requiring production of 20000 front-end chips, roughly. CARIOCA has been developed to process MWPC cathode and anode signals and two different versions have been implemented to overcome the requirement of MWP and GEM chambers operation. The test station has been devised to accomplish bipolar tests and to measure characteristics of both CARIOCA versions.

Development of the ASICs for the NA62 pixel Gigatracker

CERN Document Server

Jarron, P

2008-01-01

We present the ASIC development for the readout electronics of the Gigatracker pixel detector of NA62. Specifications of this detector are challenging in terms of timing precision with a hit time stamp accuracy of 100 ps and a peak hit rate of 50 Mhits/cm2/s. A timing precision and hit rate are more than one order of magnitude faster than pixel LHC readout ASIC. The research for pixel cell design and the readout architectures are following two approaches, which are presented and discussed in this paper. Presently demonstrator prototypes are under development and SPICE simulation results of the frontend, the readout strategy and and the pixelcolumn are also presented and discussed.

MDT-ASD, CMOS front-end for ATLAS MDT

CERN Document Server

Posch, C; Oliver, J

2007-01-01

This document serves as the main reference and user`s manual for the read-out chip of the Monitored Drift Tubes in the ATLAS Muon Spectrometer. The eight-channel front-end ASIC is referred to as MDT-ASD. The document contains the requirements and complete specifications, a detailed description of the design with characteristics of all sub-circuits and building blocks, a comprehensive section on functionality and performance test results, and a complete bibliography.

ANUSANSKAR: a 16 channel frontend electronics (FEE) ASIC targeted for silicon pixel array detector based prototype Alice FOCAL

International Nuclear Information System (INIS)

Mukhopadhyay, Sourav; Chandratre, V.B.; Sukhwani, Menka; Pithawa, C.K.; Singaraju, Ramnarayan; Muhuri, Sanjib; Nayak, T.; Khan, S.A.; Saini, Jogendra

2013-01-01

ANUSANSKAR is a 16 channel pulse processing ASIC with analog multiplexed output designed in 0.7 um standard CMOS technology with each channel consisting of CSA, Semi Gaussian pulse shaper, DC cancellation and pedestal control, track and hold, output buffer blocks. The ASIC's analog multiplexed output can be read serially in daisy-chain topology. Testing, characterization and validation of ANUSANSKAR ASIC as readout for prototype ALICE forward calorimeter (FOCAL) has been carried out in PS beam line at CERN with up to 6 GeV of pion and electron beam. This paper describes the ANUSANSKAR ASIC along with the experimental results. (author)

A 64-channel readout ASIC for nanowire biosensor array with electrical calibration scheme.

Science.gov (United States)

Chai, Kevin T C; Choe, Kunil; Bernal, Olivier D; Gopalakrishnan, Pradeep K; Zhang, Guo-Jun; Kang, Tae Goo; Je, Minkyu

2010-01-01

A 1.8-mW, 18.5-mm(2) 64-channel current readout ASIC was implemented in 0.18-µm CMOS together with a new calibration scheme for silicon nanowire biosensor arrays. The ASIC consists of 64 channels of dedicated readout and conditioning circuits which incorporate correlated double sampling scheme to reduce the effect of 1/f noise and offset from the analog front-end. The ASIC provides a 10-bit digital output with a sampling rate of 300 S/s whilst achieving a minimum resolution of 7 pA(rms). A new electrical calibration method was introduced to mitigate the issue of large variations in the nano-scale sensor device parameters and optimize the sensor sensitivity. The experimental results show that the proposed calibration technique improved the sensitivity by 2 to 10 times and reduced the variation between dataset by 9 times.

The expression profile of acid-sensing ion channel (ASIC) subunits ASIC1a, ASIC1b, ASIC2a, ASIC2b, and ASIC3 in the esophageal vagal afferent nerve subtypes.

Science.gov (United States)

Dusenkova, Svetlana; Ru, Fei; Surdenikova, Lenka; Nassenstein, Christina; Hatok, Jozef; Dusenka, Robert; Banovcin, Peter; Kliment, Jan; Tatar, Milos; Kollarik, Marian

2014-11-01

Acid-sensing ion channels (ASICs) have been implicated in esophageal acid sensing and mechanotransduction. However, insufficient knowledge of ASIC subunit expression profile in esophageal afferent nerves hampers the understanding of their role. This knowledge is essential because ASIC subunits form heteromultimeric channels with distinct functional properties. We hypothesized that the esophageal putative nociceptive C-fiber nerves (transient receptor potential vanilloid 1, TRPV1-positive) express multiple ASIC subunits and that the ASIC expression profile differs between the nodose TRPV1-positive subtype developmentally derived from placodes and the jugular TRPV1-positive subtype derived from neural crest. We performed single cell RT-PCR on the vagal afferent neurons retrogradely labeled from the esophagus. In the guinea pig, nearly all (90%-95%) nodose and jugular esophageal TRPV1-positive neurons expressed ASICs, most often in a combination (65-75%). ASIC1, ASIC2, and ASIC3 were expressed in 65-75%, 55-70%, and 70%, respectively, of both nodose and jugular TRPV1-positive neurons. The ASIC1 splice variants ASIC1a and ASIC1b and the ASIC2 splice variant ASIC2b were similarly expressed in both nodose and jugular TRPV1-positive neurons. However, ASIC2a was found exclusively in the nodose neurons. In contrast to guinea pig, ASIC3 was almost absent from the mouse vagal esophageal TRPV1-positive neurons. However, ASIC3 was similarly expressed in the nonnociceptive TRPV1-negative (tension mechanoreceptors) neurons in both species. We conclude that the majority of esophageal vagal nociceptive neurons express multiple ASIC subunits. The placode-derived nodose neurons selectively express ASIC2a, known to substantially reduce acid sensitivity of ASIC heteromultimers. ASIC3 is expressed in the guinea pig but not in the mouse vagal esophageal TRPV1-positive neurons, indicating species differences in ASIC expression. Copyright © 2014 the American Physiological Society.

Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

Energy Technology Data Exchange (ETDEWEB)

Rivetti, Angelo

2014-11-21

In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8–10 bit resolution, 50–100 MHz conversion frequency and less than 1 mW power consumption are the today's standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130 nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC's and TDC's developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.

Status Report on the LOC ASIC

CERN Document Server

Ye, J

2008-01-01

Based on a commercially available 0.25 μm Silicon on Sapphire CMOS technology, we are developing the LOC ASIC for high speed serial data transmission in the front-end electronics systems of the ATLAS upgrade for the SLHC1. Evaluation of this technology for applications in the SLHC, based on a dedicated test chip, has been performed with irradiation tests in gamma (Co-60) and in 230 MeV proton beams. Test results indicate that this may be a candidate technology of ASIC developments for the SLHC. More thorough evaluation tests will be carried out under another R&D program supported through the Advanced Detector Research (ADR) from the Department of Energy. Characterization tests on the first prototype serializer, LOC1, have been carried out in lab. Based on the lessons learned from this chip, we propose a new architecture design of the second prototype, LOC2, aiming for a serial data rate in the range of 5 Gbps. Simulation on key components of LOC2 are being carried out and the results we have so far are p...

Development and evaluation of an ultra-fast ASIC for future PET scanners using TOF-capable MPPC array detectors

International Nuclear Information System (INIS)

Ambe, T.; Ikeda, H.; Kataoka, J.; Matsuda, H.; Kato, T.

2015-01-01

We developed a front-end ASIC for future PET scanners with Time-Of-Flight (TOF) capability to be coupled with 4×4 Multi-Pixel Photon Counter (MPPC) arrays. The ASIC is designed based on the open-IP project proposed by JAXA and realized in TSMC 0.35 μm CMOS technology. The circuit comprises 16-channel, low impedance current conveyors for effectively acquiring fast MPPC signals. For precise measurement of the coincidence timing of 511-keV gamma rays, the leading-edge method was used to discriminate the signals. We first tested the time response of the ASIC by illuminating each channel of a MPPC array device 3×3 mm 2 in size with a Pico-second Light Pulsar with a light emission peak of 655 nm and pulse duration of 54 ps (FWHM). We obtained 105 ps (FWHM) on average for each channel in time jitter measurements. Moreover, we compensated for the time lag of each channel with inner delay circuits and succeeded in suppressing about a 700-ps lag to only 15 ps. This paper reports TOF measurements using back-to-back 511-keV signals, and suggests that the ASIC can be a promising device for future TOF-PET scanners based on the MPPC array. - Highlights: • We developed a newly designed large-area monolithic MPPC array. • We obtained fine gain uniformity, and good energy and time resolutions when coupled to the LYSO scintillator. • We fabricated gamma-ray camera consisting of the MPPC array and the submillimeter pixelized LYSO and GGAG scintillators. • In the flood images, each crystal of scintillator matrices was clearly resolved. • Good energy resolutions for 662 keV gamma-rays for each LYSO and GGAG scintillator matrices were obtained

Acid-sensing ion channels (ASICs) in mouse skeletal muscle afferents are heteromers composed of ASIC1a, ASIC2, and ASIC3 subunits

Science.gov (United States)

Gautam, Mamta; Benson, Christopher J.

2013-01-01

Acid-sensing ion channels (ASICs) are expressed in skeletal muscle afferents, in which they sense extracellular acidosis and other metabolites released during ischemia and exercise. ASICs are formed as homotrimers or heterotrimers of several isoforms (ASIC1a, ASIC1b, ASIC2a, ASIC2b, and ASIC3), with each channel displaying distinct properties. To dissect the ASIC composition in muscle afferents, we used whole-cell patch-clamp recordings to study the properties of acid-evoked currents (amplitude, pH sensitivity, the kinetics of desensitization and recovery from desensitization, and pharmacological modulation) in isolated, labeled mouse muscle afferents from wild-type (C57BL/6J) and specific ASIC−/− mice. We found that ASIC-like currents in wild-type muscle afferents displayed fast desensitization, indicating that they are carried by heteromeric channels. Currents from ASIC1a−/− muscle afferents were less pH-sensitive and displayed faster recovery, currents from ASIC2−/− mice showed diminished potentiation by zinc, and currents from ASIC3−/− mice displayed slower desensitization than those from wild-type mice. Finally, ASIC-like currents were absent from triple-null mice lacking ASIC1a, ASIC2a, and ASIC3. We conclude that ASIC1a, ASIC2a, and ASIC3 heteromers are the principle channels in skeletal muscle afferents. These results will help us understand the role of ASICs in exercise physiology and provide a molecular target for potential drug therapies to treat muscle pain.—Gautam, M., Benson, C. J. Acid-sensing ion channels (ASICs) in mouse skeletal muscle afferents are heteromers composed of ASIC1a, ASIC2, and ASIC3 subunits. PMID:23109675

An Updated Front-End Data Link Design for the Phase-2 Upgrade of the ATLAS Tile Calorimeter

CERN Document Server

Silverstein, Samuel; The ATLAS collaboration

2017-01-01

We present a new design for the advanced Link Daughter Board (DB) for the front-end electronics upgrade of the ATLAS hadronic Tile Calorimeter. The DB provides control, configuration and continuous ADC readout for the front-end, as well as bi-directional multi-GB/s optical links to the off-detector readout system. The DB will operate in high luminosity LHC conditions with limited detector access, so the design is fault tolerant with a high level of redundancy to avoid single-point failure modes. The DB is divided longitudinally, with an FPGA serving the ADC channels on its respective side. The new design is based on the new Xilinx Kintex Ultrascale+ FPGA family, which provides improved high-speed link timing performance as well as better signal compatibility with the CERN-developed GBTx link and timing distribution ASICs. Two GBTx ASICs each provide redundant phase-adjusted, LHC synchronous clocks, parallel control buses and remote JTAG configuration access to both FPGAs on the DB.

Acid-sensing ion channels (ASICs) in mouse skeletal muscle afferents are heteromers composed of ASIC1a, ASIC2, and ASIC3 subunits

OpenAIRE

Gautam, Mamta; Benson, Christopher J.

2013-01-01

Acid-sensing ion channels (ASICs) are expressed in skeletal muscle afferents, in which they sense extracellular acidosis and other metabolites released during ischemia and exercise. ASICs are formed as homotrimers or heterotrimers of several isoforms (ASIC1a, ASIC1b, ASIC2a, ASIC2b, and ASIC3), with each channel displaying distinct properties. To dissect the ASIC composition in muscle afferents, we used whole-cell patch-clamp recordings to study the properties of acid-evoked currents (amplitu...

A front end ASIC for the readout of the PMT in the KM3NeT detector

International Nuclear Information System (INIS)

Gajanana, D; Gromov, V; Timmer, P; Heine, E; Kluit, R

2010-01-01

In this work, we describe the front end ASIC to readout the Photo-Multiplier-Tube of the KM3NeT detector, in detail. Stringent power budgeting, area constraints and lowering cost motivate us to design a custom front-end ASIC for reading the PMT. The ASIC amplifies the PMT signal and discriminates it against a threshold level and delivers the information via low voltage differential signals (LVDS). These LVDS signals carry highly accurate timing information of the photons . The length of the LVDS signals or Time over Threshold (ToT) gives information on the number of detected photons. A one-time programmable read-only memory (PROM) block provides unique identification to the chip. The chip communicates with the data acquisition electronics via an I 2 C bus. The data is transmitted to shore via fiber optics, where processing is done. The ASIC was fabricated in 0.35u CMOS process from AustriaMicroSystems (AMS).

A Prototype PZT Matrix Transducer With Low-Power Integrated Receive ASIC for 3-D Transesophageal Echocardiography.

Science.gov (United States)

Chen, Chao; Raghunathan, Shreyas B; Yu, Zili; Shabanimotlagh, Maysam; Chen, Zhao; Chang, Zu-yao; Blaak, Sandra; Prins, Christian; Ponte, Jacco; Noothout, Emile; Vos, Hendrik J; Bosch, Johan G; Verweij, Martin D; de Jong, Nico; Pertijs, Michiel A P

2016-01-01

This paper presents the design, fabrication, and experimental evaluation of a prototype lead zirconium titanate (PZT) matrix transducer with an integrated receive ASIC, as a proof of concept for a miniature three-dimensional (3-D) transesophageal echocardiography (TEE) probe. It consists of an array of 9 ×12 piezoelectric elements mounted on the ASIC via an integration scheme that involves direct electrical connections between a bond-pad array on the ASIC and the transducer elements. The ASIC addresses the critical challenge of reducing cable count, and includes front-end amplifiers with adjustable gains and micro-beamformer circuits that locally process and combine echo signals received by the elements of each 3 ×3 subarray. Thus, an order-of-magnitude reduction in the number of receive channels is achieved. Dedicated circuit techniques are employed to meet the strict space and power constraints of TEE probes. The ASIC has been fabricated in a standard 0.18-μm CMOS process and consumes only 0.44 mW/channel. The prototype has been acoustically characterized in a water tank. The ASIC allows the array to be presteered across ±37° while achieving an overall dynamic range of 77 dB. Both the measured characteristics of the individual transducer elements and the performance of the ASIC are in good agreement with expectations, demonstrating the effectiveness of the proposed techniques.

AMIC: an expandable integrated analog front-end for light distribution moments analysis

OpenAIRE

SPAGGIARI, MICHELE; Herrero Bosch, Vicente; Lerche, Christoph Werner; Aliaga Varea, Ramón José; Monzó Ferrer, José María; Gadea Gironés, Rafael

2011-01-01

In this article we introduce AMIC (Analog Moments Integrated Circuit), a novel analog Application Specific Integrated Circuit (ASIC) front-end for Positron Emission Tomography (PET) applications. Its working principle is based on mathematical analysis of light distribution through moments calculation. Each moment provides useful information about light distribution, such as energy, position, depth of interaction, skewness (deformation due to border effect) etc. A current buffer delivers a cop...

Command Interface ASIC - Analog Interface ASIC Chip Set

Science.gov (United States)

Ruiz, Baldes; Jaffe, Burton; Burke, Gary; Lung, Gerald; Pixler, Gregory; Plummer, Joe; Katanyoutanant,, Sunant; Whitaker, William

2003-01-01

A command interface application-specific integrated circuit (ASIC) and an analog interface ASIC have been developed as a chip set for remote actuation and monitoring of a collection of switches, which can be used to control generic loads, pyrotechnic devices, and valves in a high-radiation environment. The command interface ASIC (CIA) can be used alone or in combination with the analog interface ASIC (AIA). Designed primarily for incorporation into spacecraft control systems, they are also suitable for use in high-radiation terrestrial environments (e.g., in nuclear power plants and facilities that process radioactive materials). The primary role of the CIA within a spacecraft or other power system is to provide a reconfigurable means of regulating the power bus, actuating all valves, firing all pyrotechnic devices, and controlling the switching of power to all switchable loads. The CIA is a mixed-signal (analog and digital) ASIC that includes an embedded microcontroller with supporting fault-tolerant switch control and monitoring circuitry that is capable of connecting to a redundant set of interintegrated circuit (I(sup 2)C) buses. Commands and telemetry requests are communicated to the CIA. Adherence to the I(sup 2)C bus standard helps to reduce development costs by facilitating the use of previously developed, commercially available components. The AIA is a mixed-signal ASIC that includes the analog circuitry needed to connect the CIA to a custom higher powered version of the I(sup 2)C bus. The higher-powered version is designed to enable operation with bus cables longer than those contemplated in the I(sup 2)C standard. If there are multiple higher-power I(sup 2)C-like buses, then there must an AIA between the CIA and each such bus. The AIA includes two identical interface blocks: one for the side-A I(sup 2)C clock and data buses and the other for the side B buses. All the AIAs on each side are powered from a common power converter module (PCM). Sides A and B

A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

CERN Document Server

Senkin, Sergey; The ATLAS collaboration

2017-01-01

We present a front-end readout system, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on 130 nm CMOS technology, FATALIC performs the full signal processing, including amplification, shaping and digitisation.

Scientific performances of the XAA1.2 front-end chip for silicon microstrip detectors

International Nuclear Information System (INIS)

Del Monte, Ettore; Soffitta, Paolo; Morelli, Ennio; Pacciani, Luigi; Porrovecchio, Geiland; Rubini, Alda; Uberti, Olga; Costa, Enrico; Di Persio, Giuseppe; Donnarumma, Immacolata; Evangelista, Yuri; Feroci, Marco; Lazzarotto, Francesco; Mastropietro, Marcello; Rapisarda, Massimo

2007-01-01

The XAA1.2 is a custom ASIC chip for silicon microstrip detectors adapted by Ideas for the SuperAGILE instrument on board the AGILE space mission. The chip is equipped with 128 input channels, each one containing a charge preamplifier, shaper, peak detector and stretcher. The most important features of the ASIC are the extended linearity, low noise and low power consumption. The XAA1.2 underwent extensive laboratory testing in order to study its commandability and functionality and evaluate its scientific performances. In this paper we describe the XAA1.2 features, report the laboratory measurements and discuss the results emphasizing the scientific performances in the context of the SuperAGILE front-end electronics

SPIDR, a general-purpose readout system for pixel ASICs

International Nuclear Information System (INIS)

Heijden, B. van der; Visser, J.; Beuzekom, M. van; Boterenbrood, H.; Munneke, B.; Schreuder, F.; Kulis, S.

2017-01-01

The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a 'soft core' CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four

Prototype board development for the validation of the VMM ASICs for the New Small Wheel ATLAS upgrade project

CERN Document Server

Gkountoumis, Panagiotis; The ATLAS collaboration

2018-01-01

The VMM is a custom Application Specific Integrated Circuit (ASIC) which was designed to be used in the front-end readout electronics of both micromegas (MM) and small Thin Gap Chambers (sTGC) detectors of the New Small Wheel (NSW) Phase-I upgrade project of the ATLAS experiment. A new version of the VMM was recently fabricated and for that reason various prototype boards, the micromegas Front-End (MMFE1) and the General Purpose VMM (GPVMM), have been fabricated and extensively tested in order to validate the functionality of the ASIC. These boards use commercial Field Programmable Gate Arrays (FPGAs) for direct communication with computers which is achieved through 10/100/1000 Mbps Ethernet and UDP/IP protocols. The low noise performance of these boards gave the opportunity to be used in various test beams with micromegas detectors for validating the VMM and for performance studies of the sTGC detectors. A detailed description of the boards along with the results of the test beam and the detector studies wi...

Prototype board development for the validation of the VMM ASICs for the New Small Wheel ATLAS upgrade project

CERN Document Server

Gkountoumis, Panagiotis; The ATLAS collaboration

2018-01-01

The VMM is a custom Application Specific Integrated Circuit (ASIC) which was designed to be used in the frontend readout electronics of both micromegas (MM) and small Thin Gap Chambers (sTGC) detectors of the New Small Wheel (NSW) Phase-I upgrade project of the ATLAS experiment. A new version of the VMM was recently fabricated and for that reason various prototype boards, the micromegas Front-End (MMFE1) and the General Purpose VMM (GPVMM), have been fabricated and extensively tested in order to validate the functionality of the ASIC. These boards use commercial Field Programmable Gate Arrays (FPGAs) for direct communication with computers which is achieved through 10=100=1000 Mbps Ethernet and UDP/IP protocols. The low noise performance of these boards gave the opportunity to be used in various test beams with micormegas detectors for validating the VMM and for performance studies of the sTGC detectors. A detailed description of the boards along with the results of the test beam and the detector studies will...

Simultaneous Disruption of Mouse ASIC1a, ASIC2 and ASIC3 Genes Enhances Cutaneous Mechanosensitivity

Science.gov (United States)

Kang, Sinyoung; Jang, Jun Ho; Price, Margaret P.; Gautam, Mamta; Benson, Christopher J.; Gong, Huiyu; Welsh, Michael J.; Brennan, Timothy J.

2012-01-01

Three observations have suggested that acid-sensing ion channels (ASICs) might be mammalian cutaneous mechanoreceptors; they are structurally related to Caenorhabditis elegans mechanoreceptors, they are localized in specialized cutaneous mechanosensory structures, and mechanical displacement generates an ASIC-dependent depolarization in some neurons. However, previous studies of mice bearing a single disrupted ASIC gene showed only subtle or no alterations in cutaneous mechanosensitivity. Because functional redundancy of ASIC subunits might explain limited phenotypic alterations, we hypothesized that disrupting multiple ASIC genes would markedly impair cutaneous mechanosensation. We found the opposite. In behavioral studies, mice with simultaneous disruptions of ASIC1a, -2 and -3 genes (triple-knockouts, TKOs) showed increased paw withdrawal frequencies when mechanically stimulated with von Frey filaments. Moreover, in single-fiber nerve recordings of cutaneous afferents, mechanical stimulation generated enhanced activity in A-mechanonociceptors of ASIC TKOs compared to wild-type mice. Responses of all other fiber types did not differ between the two genotypes. These data indicate that ASIC subunits influence cutaneous mechanosensitivity. However, it is unlikely that ASICs directly transduce mechanical stimuli. We speculate that physical and/or functional association of ASICs with other components of the mechanosensory transduction apparatus contributes to normal cutaneous mechanosensation. PMID:22506072

Double-differential recording and AGC using microcontrolled variable gain ASIC.

Science.gov (United States)

Rieger, Robert; Deng, Shin-Liang

2013-01-01

Low-power wearable recording of biopotentials requires acquisition front-ends with high common-mode rejection for interference suppression and adjustable gain to provide an optimum signal range to a cascading analogue-to-digital stage. A microcontroller operated double-differential (DD) recording setup and automatic gain control circuit (AGC) are discussed which reject common-mode interference and provide tunable gain, thus compensating for imbalance and variation in electrode interface impedance. Custom-designed variable gain amplifiers (ASIC) are used as part of the recording setup. The circuit gain and balance is set by the timing of microcontroller generated clock signals. Measured results are presented which confirm that improved common-mode rejection is achieved compared to a single differential amplifier in the presence of input network imbalance. Practical measured examples further validate gain control suitable for biopotential recording and power-line rejection for wearable ECG and EMG recording. The prototype front-end consumes 318 μW including amplifiers and microcontroller.

Highly integrated front-end electronics for spaceborne fluxgate sensors

International Nuclear Information System (INIS)

Magnes, W; Valavanoglou, A; Hagen, C; Jernej, I; Baumjohann, W; Oberst, M; Hauer, H; Neubauer, H; Pierce, D; Means, J; Falkner, P

2008-01-01

Scientific instruments for challenging and cost-optimized space missions have to reduce their resource requirements while keeping the high performance levels of conventional instruments. In this context the development of an instrument front-end ASIC (0.35 µm CMOS from austriamicrosystems) for magnetic field sensors based on the fluxgate principle was undertaken. It is based on the combination of the conventional readout electronics of a fluxgate magnetometer with the control loop of a sigma-delta modulator for a direct digitization of the magnetic field. The analogue part is based on a modified 2–2 cascaded sigma-delta modulator. The digital part includes a primary (128 Hz output) and secondary decimation filter (2, 4, 8,..., 64 Hz output) as well as a serial synchronous interface. The chip area is 20 mm 2 and the total power consumption is 60 mW. It has been demonstrated that the overall functionality and performance of the magnetometer front-end ASIC (MFA) is sufficient for scientific applications in space. Noise performance (SNR of 89 dB with a bandwidth of 30 Hz) and offset stability ( −1 MFA temperature, −1 is acceptable. Only a cross-tone phenomenon must be avoided in future designs even though it is possible to mitigate the effect to a level that is tolerable. The MFA stays within its parameters up to 170 krad of total ionizing dose and it keeps full functionality up to more than 300 krad. The threshold for latch-ups is 14 MeV cm 2 mg −1

Performance of the First Version of VMM Front-End ASIC with Resistive Micromegas Detectors

CERN Document Server

The ATLAS collaboration

2014-01-01

This note describes the performance of the first version of a front end ASIC, VMM1, being developed for the Micromegas and sTGC detectors of the ATLAS New Small Wheel (NSW) upgrade. The VMM1 ASIC was designed by the micro-electronics group of the Instrumentation Division of Brookhaven National Laboratory. It contains 64-channels of linear, low noise amplifiers with adaptive feedback, charge amplitude peak detectors with time stamp. It can accept inputs of both polarities, features selectable gain and shaping time and has a built-in calibration system. It is designed to operate with micro-pattern gas detectors providing both trigger and tracking information. The VMM1 was tested during August 2012 test beam campaign at SPS/H6 beam line at CERN using micromegas detectors of the Muon ATLAS MicroMega Activity R&D program. We present here the VMM1 configuration, the software that was developed to achieve its operation, as well as the calibration procedure. Furthermore, we present the analysis performed with the...

Front-end electronics and data acquisition system for imaging atmospheric Cherenkov telescopes

International Nuclear Information System (INIS)

Chen, Y.T.; La Taille, C. de; Suomijärvi, T.; Cao, Z.; Deligny, O.; Dulucq, F.; Ge, M.M.; Lhenry-Yvon, I.; Martin-Chassard, G.; Nguyen Trung, T.; Wanlin, E.; Xiao, G.; Yin, L.Q.; Yun Ky, B.; Zhang, L.; Zhang, H.Y.; Zhang, S.S.; Zhu, Z.

2015-01-01

In this paper, a front-end electronics based on an application-specific integrated circuit (ASIC) is presented for the future imaging atmospheric Cherenkov telescopes (IACTs). To achieve this purpose, a 16-channel ASIC chip, PARISROC 2 (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is used in the analog signal processing and digitization. The digitized results are sent to the server by a user-defined User Datagram Protocol/Internet Protocol (UDP/IP) hardcore engine through Ethernet that is managed by a FPGA. A prototype electronics fulfilling the requirements of the Wide Field of View Cherenkov Telescope Array (WFCTA) of the Large High Altitude Air Shower Observatory (LHAASO) project has been designed, fabricated and tested to prove the concept of the design. A detailed description of the development with the results of the test measurements are presented. By using a new input structure and a new configuration of the ASIC, the dynamic range of the circuit is extended. A highly precise-time calibrating algorithm is also proposed, verified and optimized for the mass production. The test results suggest that the proposed electronics design fulfills the general specification of the future IACTs

Front-end electronics and data acquisition system for imaging atmospheric Cherenkov telescopes

Energy Technology Data Exchange (ETDEWEB)

Chen, Y.T., E-mail: chenytao@ynu.edu.cn [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Yunnan University, 650091 Kunming (China); La Taille, C. de [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Suomijärvi, T. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Cao, Z. [Institute of High Energy Physics, 100049 Beijing (China); Deligny, O. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Dulucq, F. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Ge, M.M. [Yunnan University, 650091 Kunming (China); Lhenry-Yvon, I. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Martin-Chassard, G. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Nguyen Trung, T.; Wanlin, E. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Xiao, G.; Yin, L.Q. [Institute of High Energy Physics, 100049 Beijing (China); Yun Ky, B. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Zhang, L. [Yunnan University, 650091 Kunming (China); Zhang, H.Y. [Tsinghua University, 100084 Beijing (China); Zhang, S.S.; Zhu, Z. [Institute of High Energy Physics, 100049 Beijing (China)

2015-09-21

In this paper, a front-end electronics based on an application-specific integrated circuit (ASIC) is presented for the future imaging atmospheric Cherenkov telescopes (IACTs). To achieve this purpose, a 16-channel ASIC chip, PARISROC 2 (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is used in the analog signal processing and digitization. The digitized results are sent to the server by a user-defined User Datagram Protocol/Internet Protocol (UDP/IP) hardcore engine through Ethernet that is managed by a FPGA. A prototype electronics fulfilling the requirements of the Wide Field of View Cherenkov Telescope Array (WFCTA) of the Large High Altitude Air Shower Observatory (LHAASO) project has been designed, fabricated and tested to prove the concept of the design. A detailed description of the development with the results of the test measurements are presented. By using a new input structure and a new configuration of the ASIC, the dynamic range of the circuit is extended. A highly precise-time calibrating algorithm is also proposed, verified and optimized for the mass production. The test results suggest that the proposed electronics design fulfills the general specification of the future IACTs.

Characterization of the CBC2 readout ASIC for the CMS strip-tracker high-luminosity upgrade

International Nuclear Information System (INIS)

Braga, D; Hall, G; Pesaresi, M; Raymond, M; Jones, L; Murray, P; Prydderch, M

2014-01-01

The CMS Binary Chip 2 (CBC2) is a full-scale prototype ASIC developed for the front-end readout of the high-luminosity upgrade of the CMS silicon strip tracker. The 254-channel, 130 nm CMOS ASIC is designed for the binary readout of double-layer modules, and features cluster-width discrimination and coincidence logic for detecting high-P T track candidates. The chip was delivered in January 2013 and has since been bump-bonded to a dual-chip hybrid and extensively tested. The CBC2 is fully functional and working to specification: we present the result of electrical characterization of the chip, including gain, noise, threshold scan and power consumption, together with the performance of the stub finding logic. Finally we will outline the plan for future developments towards the production version

FF-EMU: a radiation tolerant ASIC for the distribution of timing, trigger and control signals in the CMS End-Cap Muon detector

International Nuclear Information System (INIS)

Campagnari, C; Costantino, N; Magazzù, G; Tongiani, Claudio

2012-01-01

A radiation tolerant integrated circuit for the distribution of clock, trigger and control signals in the Front-End electronics of the CMS End-Cap Muon detector has been developed in the IBM CMOS 130nm technology. The circuit houses transmitter and receiver interfaces to serial links implementing the FF-LYNX protocol that allows the integrated transmission of triggers and data frames with different latency constraints. Encoder and decoder modules associate signal transitions to FF-LYNX frames. The system and the ASIC architecture and behavior and the results of test and characterization of the ASIC prototypes will be presented.

Performance of Front-End Readout System for PHENIX RICH

International Nuclear Information System (INIS)

Oyama, K.; Hamagaki, H.; Nishimura, S.; Shigaki, K.; Hayano, R.S.; Hibino, M.; Kametani, S.; Kikuchi, J.; Matsumoto, T.; Sakaguchi, T.; Ebisu, K.; Hara, H.; Tanaka, Y.; Ushiroda, T.; Moscone, C.G.; Wintenberg, A.L.; Young, G.R.

1999-01-01

A front-end electronics system has been developed for the Ring Imaging Cerenkov (RICH) detector of the PHENIX experiment at the Relativistic Heavy Ion Collider (RHIC), Brookhaven National Laboratory (BNL). A high speed custom back-plane with source synchronous bus architecture, a full custom analog ASIC, and board modules with FPGA's and CPLD's were developed for high performance real time data acquisition. The transfer rate of the back-lane has reached 640 MB/s with 128 bits data bus. Total transaction time is estimated to be less than 30 micros per event. The design specifications and test results of the system are presented in this paper

The Panda Strip Asic: Pasta

Science.gov (United States)

Lai, A.

2018-01-01

PASTA is the 64 channel front-end chip, designed in a 110 nm CMOS technology to read out the strip sensors of the Micro Vertex Detector (MVD) of the PANDA experiment. This chip provides high resolution timestamp and deposited charge information by means of the time-over-threshold technique. Its working principle is based on a predecessor, the TOFPET ASIC, that was designed for medical applications. A general restructuring of the architecture was needed, in order to meet the specific requirements imposed by the physics programme of PANDA, especially in terms of radiation tolerance, spatial constraints, and readout in absence of a first level hardware trigger. The first revision of PASTA is currently under evaluation at the Forschungszentrum Jülich, where a data acquisition system dedicated to the MVD prototypes has been developed. This paper describes the main aspect of the chip design, gives an overview of the data acquisition system used for the verification, and shows the first results regarding the performance of PASTA.

A 130 nm ASIC prototype for the NA62 Gigatracker readout

CERN Document Server

Dellacasa, G; Wheadon, R; Mazza, G; Rivetti, A; Marchetto, F; Garbolino, S

2011-01-01

One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatracker. It consists of three hybrid silicon pixel stations, each one covering an area of 27 mm x 60 mm. While the maximum pixel size is fairly large, 300 mu m x 300 mu m the system has to sustain a very high particle rate, 1.5 MHz/mm(2), which corresponds to 800 MHz for each station. To obtain an efficient tracking with such a high rate the required track timing resolution is 150 ps (rms). Therefore the front-end ASIC should provide for each pixel a 200 Ps time measurement capability, thus leading to the requirement of time walk compensation and very compact TDCs. Moreover, Single Event Upset protection has to be implemented in order to protect the digital circuitry. An ASIC prototype has been realized in CMOS 130 nm technology, containing three pixel columns. The chip performs the time walk compensation by a Constant Fraction Discriminator circuit, while the time measurement is performed by a Time to Amplitude Co...

Heteromeric ASIC channels composed of ASIC2b and ASIC1a display novel channel properties and contribute to acidosis-induced neuronal death

Science.gov (United States)

Sherwood, Thomas W.; Lee, Kirsten G.; Gormley, Matthew G.; Askwith, Candice C.

2011-01-01

Acid-sensing ion channel (ASIC) subunits associate to form homomeric or heteromeric proton-gated ion channels in neurons throughout the nervous system. The ASIC1a subunit plays an important role in establishing the kinetics of proton-gated currents in the central nervous system and activation of ASIC1a homomeric channels induces neuronal death following local acidosis that accompanies cerebral ischemia. The ASIC2b subunit is expressed in the brain in a pattern that overlaps ASIC1a, yet the contribution of ASIC2b has remained elusive. We find that co-expression of ASIC2b with ASIC1a in Xenopus oocytes results in novel proton-gated currents with properties distinct from ASIC1a homomeric channels. In particular, ASIC2b/1a heteromeric channels are inhibited by the non-selective potassium channel blockers tetraethylammonium (TEA) and barium. In addition, steady-state desensitization is induced at more basic pH values and Big Dynorphin sensitivity is enhanced in these unique heteromeric channels. Cultured hippocampal neurons show proton-gated currents consistent with ASIC2b contribution and these currents are lacking in neurons from mice with an ACCN1 (ASIC2) gene disruption. Finally, we find that these ASIC2b/1a heteromeric channels contribute to acidosis-induced neuronal death. Together, our results show that ASIC2b confers unique properties to heteromeric channels in central neurons. Further, these data indicate that ASIC2, like ASIC1, plays a role in acidosis-induced neuronal death and implicate the ASIC2b/1a subtype as a novel pharmacological target to prevent neuronal injury following stroke. PMID:21715637

Design of front end electronics and a full scale 4k pixel readout ASIC for the DSSC X-ray detector at the European XFEL

International Nuclear Information System (INIS)

Erdinger, Florian

2016-01-01

The goal of this thesis was to design a large scale readout ASIC for the 1-Mega pixel DEPFET Sensor with Signal Compression (DSSC) detector system which is being developed by an international collaboration for the European XFEL (EuXFEL). Requirements for the DSSC detector include single photon detection down to 0.5 keV combined with a large dynamic range of up to 10000 photons at frame rates of up to 4.5 MHz. The detector core concepts include full parallel readout, signal compression on the sensor or ASIC level, filtering, immediate digitization and local storage within the pixel. The DSSC is a hybrid pixel detector, each sensor pixel mates to a dedicated ASIC pixel, which includes the entire specified signal processing chain along with auxiliary circuits. One ASIC comprises 4096 pixels and a full periphery including biasing and digital control. This thesis presents the design of the ASIC, its components and integration are described in detail. Emphasis is put on the design of the analog front-end. The first full format ASIC (F1) has been fabricated within the scope of this thesis along with numerous test chips. Furthermore, the EuXFEL and the DSSC detector system are presented to create the context for the ASIC, which is the core topic of this thesis.

Design of front end electronics and a full scale 4k pixel readout ASIC for the DSSC X-ray detector at the European XFEL

Energy Technology Data Exchange (ETDEWEB)

Erdinger, Florian

2016-11-22

The goal of this thesis was to design a large scale readout ASIC for the 1-Mega pixel DEPFET Sensor with Signal Compression (DSSC) detector system which is being developed by an international collaboration for the European XFEL (EuXFEL). Requirements for the DSSC detector include single photon detection down to 0.5 keV combined with a large dynamic range of up to 10000 photons at frame rates of up to 4.5 MHz. The detector core concepts include full parallel readout, signal compression on the sensor or ASIC level, filtering, immediate digitization and local storage within the pixel. The DSSC is a hybrid pixel detector, each sensor pixel mates to a dedicated ASIC pixel, which includes the entire specified signal processing chain along with auxiliary circuits. One ASIC comprises 4096 pixels and a full periphery including biasing and digital control. This thesis presents the design of the ASIC, its components and integration are described in detail. Emphasis is put on the design of the analog front-end. The first full format ASIC (F1) has been fabricated within the scope of this thesis along with numerous test chips. Furthermore, the EuXFEL and the DSSC detector system are presented to create the context for the ASIC, which is the core topic of this thesis.

Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC

International Nuclear Information System (INIS)

Khalid, Farah F.; Deptuch, Grzegorz; Shenai, Alpana; Yarema, Raymond J.

2010-01-01

Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12 keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC 2 shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using μ-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 (micro)m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab.

ASIC1 and ASIC3 Play Different Roles in the Development of Hyperalgesia Following Inflammatory Muscle Injury

OpenAIRE

Walder, R.Y.; Rasmussen, L.A.; Rainier, J.D.; Light, A.R.; Wemmie, J.A.; Sluka, K.A.

2009-01-01

Acid-sensing ion channels (ASICs) respond to acidosis that normally occurs after inflammation. We examined the expression of ASIC1, ASIC2, and ASIC3 mRNAs in lumbar DRG neurons before and 24h after carrageenan-induced muscle inflammation. Muscle inflammation causes bilateral increases of ASIC2 and ASIC3, but not ASIC1 (neither ASIC1a nor ASIC1b) mRNA, suggesting differential regulation of ASIC1 versus ASIC2 and ASIC3 mRNA. Similar mRNA increases were observed following inflammation in knockou...

A 130 nm ASIC prototype for the NA62 Gigatracker readout

Energy Technology Data Exchange (ETDEWEB)

Dellacasa, G., E-mail: gdellaca@to.infn.it [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); Garbolino, S. [Universita degli Studi di Torino, Dip. Fisica Sperimentale, via Giuria 1, 10125 Torino (Italy); Marchetto, F. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); Martoiu, S. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); CERN CH-1211, Geneve 23 (Switzerland); Mazza, G.; Rivetti, A.; Wheadon, R. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy)

2011-09-11

One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatracker. It consists of three hybrid silicon pixel stations, each one covering an area of 27 mmx60 mm. While the maximum pixel size is fairly large, 300{mu}mx300{mu}m the system has to sustain a very high particle rate, 1.5 MHz/mm{sup 2}, which corresponds to 800 MHz for each station. To obtain an efficient tracking with such a high rate the required track timing resolution is 150 ps (rms). Therefore the front-end ASIC should provide for each pixel a 200 ps time measurement capability, thus leading to the requirement of time walk compensation and very compact TDCs. Moreover, Single Event Upset protection has to be implemented in order to protect the digital circuitry. An ASIC prototype has been realized in CMOS 130 nm technology, containing three pixel columns. The chip performs the time walk compensation by a Constant Fraction Discriminator circuit, while the time measurement is performed by a Time to Amplitude Converter based TDC, both of them implemented on each pixel cell. The End of Column circuit containing only digital logic is responsible for the data readout from the pixel cell. The whole chip works with a system clock of 160 MHz and the digital logic is SEU protected by the use of Hamming codes. The detailed architecture of the ASIC prototype and test results are presented.

Development of a dedicated front-end electronics for straw tube trackers in the bar PANDA experiment

Science.gov (United States)

Przyborowski, D.; Fiutowski, T.; Idzik, M.; Kajetanowicz, M.; Korcyl, G.; Salabura, P.; Smyrski, J.; Strzempek, P.; Swientek, K.; Terlecki, P.; Tokarz, J.

2016-08-01

The design and tests of front-end electronics for straw tube trackers in the bar PANDA experiment at FAIR are presented. The challenges for the front-end electronics, comprising operation at high counting rate up to 1 MHz per straw tube, are discussed and the proposed architecture comprising a switched gain charge sensitive preamplifier (CSP), a pole-zero cancellation circuit (PZC), a second order variable peaking time shaper, a trimming ion tail cancellation circuit, and a baseline holder (BLH), is described. The front-end provides an analogue output and a discriminator with LVDS differential driver for the Time-of-Arrival (ToA) and Time-over-Threshold (ToT) measurements. A prototype readout ASIC featuring four channels was fabricated in 0.35 μm CMOS technology consuming 15.5 mW (analog part) and 12 mW (LVDS) per channel. The results of measurements of peaking time (25-67 ns), gain, noise (ENC 800-2500 el. for various gains), time walk and jitter are presented as well as the first results obtained with prototype straw tubes connected.

The digital ASIC for the digital front end electronics of the SPI astrophysics gamma-ray experiment

International Nuclear Information System (INIS)

Lafond, E.; Mur, M.; Schanne, S.

1998-01-01

The SPI spectrometer is one of the gamma-ray astronomy instruments that will be installed on the ESA INTEGRAL satellite, intended to be launched in 2001 by the European Space Agency. The Digital Front-End Electronics sub-system (DFEE) is in charge of the real time data processing of the various measurements produced by the Germanium (Ge) detectors and the Bismuth Germanate (BGO) anti-coincidence shield. The central processing unit of the DFEE is implemented in a digital ASIC circuit, which provides the real time association of the various time signals, acquires the associated energy measurements, and classifies the various types of physics events. The paper gives the system constraints of the DFEE, the architecture of the ASIC circuit, the technology requirements, and the strategy for test and integration. Emphasis is given to the high level language development and simulation, the automatic circuit synthesis approach, and the performance estimation

Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC

OpenAIRE

Aliaga Varea, Ramón José; Herrero Bosch, Vicente; Capra, S.; Pullia, A.; Dueñas, J. A.; Grassi, L.; Triossi, A.; Domingo Pardo, C.; Gadea Gironés, Rafael; González, V.; Hüyük, T.; Sanchís, E.; Gadea, A.; Mengoni, D.

2015-01-01

The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling. Its readout system is to be based on analog memory ASICs with 64 channels each that sample a View the MathML source window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz...

Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC

Energy Technology Data Exchange (ETDEWEB)

Khalid, Farah F.; Deptuch, Grzegorz; Shenai, Alpana; Yarema, Raymond J.; /Fermilab

2010-11-01

Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12 keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC{sup 2} shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using {mu}-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 {micro}m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab.

Development of a dedicated front-end electronics for straw tube trackers in the P-bar ANDA experiment

International Nuclear Information System (INIS)

Przyborowski, D.; Fiutowski, T.; Idzik, M.; Swientek, K.; Terlecki, P.; Tokarz, J.; Kajetanowicz, M.; Korcyl, G.; Salabura, P.; Smyrski, J.; Strzempek, P.

2016-01-01

The design and tests of front-end electronics for straw tube trackers in the P-bar ANDA experiment at FAIR are presented. The challenges for the front-end electronics, comprising operation at high counting rate up to 1 MHz per straw tube, are discussed and the proposed architecture comprising a switched gain charge sensitive preamplifier (CSP), a pole-zero cancellation circuit (PZC), a second order variable peaking time shaper, a trimming ion tail cancellation circuit, and a baseline holder (BLH), is described. The front-end provides an analogue output and a discriminator with LVDS differential driver for the Time-of-Arrival (ToA) and Time-over-Threshold (ToT) measurements. A prototype readout ASIC featuring four channels was fabricated in 0.35 μm CMOS technology consuming 15.5 mW (analog part) and 12 mW (LVDS) per channel. The results of measurements of peaking time (25–67 ns), gain, noise (ENC 800–2500 el. for various gains), time walk and jitter are presented as well as the first results obtained with prototype straw tubes connected.

ASIC proteins regulate smooth muscle cell migration.

Science.gov (United States)

Grifoni, Samira C; Jernigan, Nikki L; Hamilton, Gina; Drummond, Heather A

2008-03-01

The purpose of the present study was to investigate Acid Sensing Ion Channel (ASIC) protein expression and importance in cellular migration. We recently demonstrated that Epithelial Na(+)Channel (ENaC) proteins are required for vascular smooth muscle cell (VSMC) migration; however, the role of the closely related ASIC proteins has not been addressed. We used RT-PCR and immunolabeling to determine expression of ASIC1, ASIC2, ASIC3 and ASIC4 in A10 cells. We used small interference RNA to silence individual ASIC expression and determine the importance of ASIC proteins in wound healing and chemotaxis (PDGF-bb)-initiated migration. We found ASIC1, ASIC2, and ASIC3, but not ASIC4, expression in A10 cells. ASIC1, ASIC2, and ASIC3 siRNA molecules significantly suppressed expression of their respective proteins compared to non-targeting siRNA (RISC) transfected controls by 63%, 44%, and 55%, respectively. Wound healing was inhibited by 10, 20, and 26% compared to RISC controls following suppression of ASIC1, ASIC2, and ASIC3, respectively. Chemotactic migration was inhibited by 30% and 45%, respectively, following suppression of ASIC1 and ASIC3. ASIC2 suppression produced a small, but significant, increase in chemotactic migration (4%). Our data indicate that ASIC expression is required for normal migration and may suggest a novel role for ASIC proteins in cellular migration.

NECTAr0, a new high speed digitizer ASIC for the Cherenkov telescope array

International Nuclear Information System (INIS)

Delagnes, E.; Glicenstein, J.F.; Guilloux, F.; Bolmont, J.; Corona, P.; Naumann, C.L.; Nayman, P.; Tavemet, J.P.; Toussenel, F.; Vincent, P.; Dzahini, D.; Rarbi, F.; Feinstein, F.; Vorobiov, S.; Gascon, D.; Sanuy, A.

2011-01-01

H.E.S.S. and MAGIC experiments have demonstrated the high level of maturity of Imaging Atmospheric Cherenkov Telescopes (IACTs) dedicated to very-high-energy gamma ray astronomy domain. The astro-particle physics community is preparing the next generation of instruments, with sensitivity improved by an order of magnitude in the 10 GeV to 100 TeV range. To reach this goal, the Cherenkov Telescope Array (CTA) will consist in an array of 50-100 dishes of various sizes and various spacing, each equipped with a camera, made of few thousands fast photo-detectors and its associated front-end electronics. The total number of electronics channels will be larger than 100,000 to be compared to the total of 6,000 channels of the 5-telescopes H.E.S.S.-I H.E.S.S.-II array. To decrease the overall CTA cost, a consequent effort should be done to lower the cost of the electronics while keeping performance at least as good as the one demonstrated on the current experiments and simplifying its maintenance. This will be allowed by mass production, use of standardized modules and integration of front-end functions in ASICs. The 3-year NECTAr program started in 2009 addresses these two topics. Its final aim is to develop and test a demonstrator module of a generic CTA camera. The paper is mainly focused on one of the main components of this module, the NECTAr ASIC which samples the photo-detector signal in a circular analog memory at several GSPS and digitizes it over 12 bits after having received an external trigger. (authors)

ASIC design at Fermilab

International Nuclear Information System (INIS)

Yarema, R.

1991-06-01

In the past few years, ASIC (Application Specific Integrated Circuit) design has become important at Fermilab. The purpose of this paper is to present an overview of the in-house ASIC design activity which has taken place. This design effort has added much value to the high energy physics program and physics capability at Fermilab. The two approaches to ASIC development being pursued at Fermilab are examined by looking at some of the types of projects where ASICs are being used or contemplated. To help estimate the cost of future designs, a cost comparison is given to show the relative development and production expenses for these two ASIC approaches. 5 refs., 14 figs., 7 tabs

Front-end electronics for the readout of CdZnTe sensors

CERN Document Server

Moraes, D; Rudge, A

2006-01-01

The CERN_DxCTA is a front-end ASIC optimized for the readout of CdZn Te sensors. The chip is implemented in 0.25 mum CMOS technology. The circuit consists of 128 channels equipped with a transimpedance amplifier followed by a gain-shaper stage with 20 ns peaking time and two discriminators, allowing two threshold settings. Each discriminator includes a 5-bit trim DAC and is followed by an 18-bit static ripple-counter. The channel architecture is optimized for the detector characteristics in order to achieve the best energy resolution at counting rates of up to 5 M counts/second. Complete evaluation of the circuit is presented using electronic pulses and Cd ZnTe pixel detectors.

Localization and Behaviors in Null Mice Suggest that ASIC1 and ASIC2 Modulate Responses to Aversive Stimuli

OpenAIRE

Price, Margaret P.; Gong, Huiyu; Parsons, Meredith G.; Kundert, Jacob R.; Reznikov, Leah R.; Bernardinelli, Luisa; Chaloner, Kathryn; Buchanan, Gordon F.; Wemmie, John A.; Richerson, George B.; Cassell, Martin D.; Welsh, Michael J.

2013-01-01

Acid sensing ion channels (ASICs) generate H+-gated Na+ currents that contribute to neuronal function and animal behavior. Like ASIC1, ASIC2 subunits are expressed in the brain and multimerize with ASIC1 to influence acid-evoked currents and facilitate ASIC1 localization to dendritic spines. To better understand how ASIC2 contributes to brain function, we localized the protein and tested the behavioral consequences of ASIC2 gene disruption. For comparison, we also localized ASIC1 and studied ...

A high speed serializer ASIC for ATLAS Liquid Argon calorimeter upgrade

CERN Document Server

Liu, T; The ATLAS collaboration

2014-01-01

We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in 200 MeV proton beam. The test results indicate that the first prototype meets the design goals. The second prototype, a double-lane, 8 Gbps per lane serializer is under development. The post layout simulation indicates that 8 Gbps is achievable. In this paper we present the design and the test results of the first prototype and the design and status of the second prototype.

Coupling Front-End Separations, Ion Mobility Spectrometry, and Mass Spectrometry For Enhanced Multidimensional Biological and Environmental Analyses

Science.gov (United States)

Zheng, Xueyun; Wojcik, Roza; Zhang, Xing; Ibrahim, Yehia M.; Burnum-Johnson, Kristin E.; Orton, Daniel J.; Monroe, Matthew E.; Moore, Ronald J.; Smith, Richard D.; Baker, Erin S.

2017-01-01

Ion mobility spectrometry (IMS) is a widely used analytical technique for rapid molecular separations in the gas phase. Though IMS alone is useful, its coupling with mass spectrometry (MS) and front-end separations is extremely beneficial for increasing measurement sensitivity, peak capacity of complex mixtures, and the scope of molecular information available from biological and environmental sample analyses. In fact, multiple disease screening and environmental evaluations have illustrated that the IMS-based multidimensional separations extract information that cannot be acquired with each technique individually. This review highlights three-dimensional separations using IMS-MS in conjunction with a range of front-end techniques, such as gas chromatography, supercritical fluid chromatography, liquid chromatography, solid-phase extractions, capillary electrophoresis, field asymmetric ion mobility spectrometry, and microfluidic devices. The origination, current state, various applications, and future capabilities of these multidimensional approaches are described in detail to provide insight into their uses and benefits. PMID:28301728

Tests of the MICE Electron Muon Ranger frontend electronics with a small scale prototype

Science.gov (United States)

Bolognini, D.; Bene, P.; Blondel, A.; Cadoux, F.; Debieux, S.; Giannini, G.; Graulich, J. S.; Lietti, D.; Masciocchi, F.; Prest, M.; Rothenfusser, K.; Vallazza, E.; Wisting, H.

2011-08-01

The MICE experiment is being commissioned at RAL to demonstrate the feasibility of the muon ionization cooling technique for future applications such as the Neutrino Factory and the Muon Collider. The cooling will be evaluated by measuring the emittance before and after the cooling channel with two 4 T spectrometers; to distinguish muons from the background, a multi-detector particle identification system is foreseen: three Time of Flight stations, two Cherenkov counters and a calorimetric system consisting of a pre-shower layer and a fully active scintillator detector (EMR) are used to discriminate muons from pions and electrons. EMR consists of 48 planes of triangular scintillating bars coupled to WLS fibers readout by single PMTs on one side and MAPMTs on the other; each plane sensible area is 1 m 2. This article deals with a small scale prototype of the EMR detector which has been used to test the MAPMT frontend electronics based on the MAROC ASIC; the tests with cosmic rays using both an analog mode and a digital readout mode are presented. A very preliminary study on the cross talk problem is also shown.

Tests of the MICE Electron Muon Ranger frontend electronics with a small scale prototype

Energy Technology Data Exchange (ETDEWEB)

Bolognini, D., E-mail: davide.bolognini@gmail.com [Universita degli Studi dell' Insubria, Via Valleggio 11, 22100 Como (Italy); INFN Milano Bicocca, Piazza della Scienza 3, 20126 Milano (Italy); Bene, P.; Blondel, A.; Cadoux, F.; Debieux, S. [Universite de Geneve, Quai Ernest-Ansermet 24, 1211 Geneve (Switzerland); Giannini, G. [Universita degli Studi di Trieste, Via A.Valerio, 34127 Trieste (Italy); INFN Trieste, Padriciano 99, 34012 Trieste (Italy); Graulich, J.S. [Universite de Geneve, Quai Ernest-Ansermet 24, 1211 Geneve (Switzerland); Lietti, D. [Universita degli Studi dell' Insubria, Via Valleggio 11, 22100 Como (Italy); INFN Milano Bicocca, Piazza della Scienza 3, 20126 Milano (Italy); Masciocchi, F. [Universite de Geneve, Quai Ernest-Ansermet 24, 1211 Geneve (Switzerland); Prest, M. [Universita degli Studi dell' Insubria, Via Valleggio 11, 22100 Como (Italy); INFN Milano Bicocca, Piazza della Scienza 3, 20126 Milano (Italy); Rothenfusser, K. [Universite de Geneve, Quai Ernest-Ansermet 24, 1211 Geneve (Switzerland); Vallazza, E. [INFN Trieste, Padriciano 99, 34012 Trieste (Italy); Wisting, H. [Universite de Geneve, Quai Ernest-Ansermet 24, 1211 Geneve (Switzerland)

2011-08-01

The MICE experiment is being commissioned at RAL to demonstrate the feasibility of the muon ionization cooling technique for future applications such as the Neutrino Factory and the Muon Collider. The cooling will be evaluated by measuring the emittance before and after the cooling channel with two 4 T spectrometers; to distinguish muons from the background, a multi-detector particle identification system is foreseen: three Time of Flight stations, two Cherenkov counters and a calorimetric system consisting of a pre-shower layer and a fully active scintillator detector (EMR) are used to discriminate muons from pions and electrons. EMR consists of 48 planes of triangular scintillating bars coupled to WLS fibers readout by single PMTs on one side and MAPMTs on the other; each plane sensible area is 1 m{sup 2}. This article deals with a small scale prototype of the EMR detector which has been used to test the MAPMT frontend electronics based on the MAROC ASIC; the tests with cosmic rays using both an analog mode and a digital readout mode are presented. A very preliminary study on the cross talk problem is also shown.

Femtosecond Resolution Timing in Multi-GS/s Waveform Digitizing ASICs

Science.gov (United States)

Orel, Peter; Varner, Gary S.

2017-07-01

A waveform digitizer with high-resolution timing provides with the possibility of a novel approach to vertex detectors for high-luminosity particle colliders. Present efforts are centered on the development of an application specific integrated circuit (ASIC) intended to measure signal arrival times with timing resolution in the range of 100 fs or less. The design of such an ASIC requires very good understanding of the effects that impact the timing resolution. This paper presents the simulation results that clearly identify and quantify the sources of error and the underlying coupling mechanisms. In addition, a synthetic waveform generator, developed solely for this purpose, is presented and validated through the measurement results. Crucial knowledge, insights, and confidence have been gained for the development of the ASIC or any other fast, wideband RF systems that aim to achieve such performance.

Frontend electronics for high-precision single photo-electron timing using FPGA-TDCs

Energy Technology Data Exchange (ETDEWEB)

Cardinali, M., E-mail: cardinal@kph.uni-mainz.de [Institut für Kernphysik, Johannes Gutenberg-University Mainz, Mainz (Germany); Helmholtz Institut Mainz, Mainz (Germany); Dzyhgadlo, R.; Gerhardt, A.; Götzen, K.; Hohler, R.; Kalicy, G.; Kumawat, H.; Lehmann, D.; Lewandowski, B.; Patsyuk, M.; Peters, K.; Schepers, G.; Schmitt, L.; Schwarz, C.; Schwiening, J.; Traxler, M.; Ugur, C.; Zühlsdorf, M. [GSI Helmholtzzentrum für Schwerionenforschung GmbH, Darmstadt (Germany); Dodokhov, V.Kh. [Joint Institute for Nuclear Research, Dubna (Russian Federation); Britting, A. [Friedrich Alexander-University of Erlangen-Nuremberg, Erlangen (Germany); and others

2014-12-01

The next generation of high-luminosity experiments requires excellent particle identification detectors which calls for Imaging Cherenkov counters with fast electronics to cope with the expected hit rates. A Barrel DIRC will be used in the central region of the Target Spectrometer of the planned PANDA experiment at FAIR. A single photo-electron timing resolution of better than 100 ps is required by the Barrel DIRC to disentangle the complicated patterns created on the image plane. R and D studies have been performed to provide a design based on the TRB3 readout using FPGA-TDCs with a precision better than 20 ps RMS and custom frontend electronics with high-bandwidth pre-amplifiers and fast discriminators. The discriminators also provide time-over-threshold information thus enabling walk corrections to improve the timing resolution. Two types of frontend electronics cards optimised for reading out 64-channel PHOTONIS Planacon MCP-PMTs were tested: one based on the NINO ASIC and the other, called PADIWA, on FPGA discriminators. Promising results were obtained in a full characterisation using a fast laser setup and in a test experiment at MAMI, Mainz, with a small scale DIRC prototype. - Highlights: • Frontend electronics for Cherenkov detectors have been developed. • FPGA-TDCs have been used for high precision timing. • Time over threshold has been utilised for walk correction. • Single photo-electron timing resolution less than 100 ps has been achieved.

Acid-Sensing Ion Channel 2a (ASIC2a) Promotes Surface Trafficking of ASIC2b via Heteromeric Assembly

OpenAIRE

Kweon, Hae-Jin; Kim, Dong-Il; Bae, Yeonju; Park, Jae-Yong; Suh, Byung-Chang

2016-01-01

Acid-sensing ion channels (ASICs) are proton-activated cation channels that play important roles as typical proton sensors during pathophysiological conditions and normal synaptic activities. Among the ASIC subunits, ASIC2a and ASIC2b are alternative splicing products from the same gene, ACCN1. It has been shown that ASIC2 isoforms have differential subcellular distribution: ASIC2a targets the cell surface by itself, while ASIC2b resides in the ER. However, the underlying mechanism for this d...

Coupling Front-End Separations, Ion Mobility Spectrometry, and Mass Spectrometry For Enhanced Multidimensional Biological and Environmental Analyses

Energy Technology Data Exchange (ETDEWEB)

Zheng, Xueyun; Wojcik, Roza; Zhang, Xing; Ibrahim, Yehia M.; Burnum-Johnson, Kristin E.; Orton, Daniel J.; Monroe, Matthew E.; Moore, Ronald J.; Smith, Richard D.; Baker, Erin M.

2017-06-12

Ion mobility spectrometry (IMS) is a widely used analytical technique for rapid molecular separations in the gas phase. IMS alone is useful, but its coupling with mass spectrometry (MS) and front-end separations has been extremely beneficial for increasing measurement sensitivity, peak capacity of complex mixtures, and the scope of molecular information in biological and environmental sample analyses. Multiple studies in disease screening and environmental evaluations have even shown these IMS-based multidimensional separations extract information not possible with each technique individually. This review highlights 3-dimensional separations using IMS-MS in conjunction with a range of front-end techniques, such as gas chromatography (GC), supercritical fluid chromatography (SFC), liquid chromatography (LC), solid phase extractions (SPE), capillary electrophoresis (CE), field asymmetric ion mobility spectrometry (FAIMS), and microfluidic devices. The origination, current state, various applications, and future capabilities for these multidimensional approaches are described to provide insight into the utility and potential of each technique.

Parallel and pipelined front-end for multi-element silicon detectors in scanning electron microscopy

International Nuclear Information System (INIS)

Boulin, C.; Epstein, A.

1992-01-01

This paper discusses a silicon quadrant detector (128 elements) implemented as an electron detector in a Scanning Transmission Electron Microscope. As the electron beam scans over the sample, electrons are counted during each pixel. The authors developed an ASIC for the multichannel counting system. The digital front-end carries out the readout of all elements, in four groups, and uses these data to compute linear combinations to generate up to eight simultaneous images. For the preprocessing the authors implemented a parallel and pipelined system. Dedicated software tools were developed to generate the programs for all the processors. These tools are transparently accessed by the user via a user friendly interface

VEGA: A low-power front-end ASIC for large area multi-linear X-ray silicon drift detectors: Design and experimental characterization

Energy Technology Data Exchange (ETDEWEB)

Ahangarianabhari, Mahdi; Macera, Daniele [Politecnico di Milano, Department of Electronics Engineering, Information Science and Bioengineering, P.za L. da Vinci 32, 20133 Milano (Italy); National Institute of Nuclear Physics, INFN sez. Milano (Italy); Bertuccio, Giuseppe, E-mail: Giuseppe.Bertuccio@polimi.it [Politecnico di Milano, Department of Electronics Engineering, Information Science and Bioengineering, P.za L. da Vinci 32, 20133 Milano (Italy); National Institute of Nuclear Physics, INFN sez. Milano (Italy); Malcovati, Piero; Grassi, Marco [University of Pavia, Department of Electrical Engineering, and National Institute of Nuclear Physics, INFN sez. Pavia, Pavia (Italy)

2015-01-11

We present the design and the first experimental characterization of VEGA, an Application Specific Integrated Circuit (ASIC) designed to read out large area monolithic linear Silicon Drift Detectors (SDD’s). VEGA consists of an analog and a digital/mixed-signal section to accomplish all the functionalities and specifications required for high resolution X-ray spectroscopy in the energy range between 500 eV and 50 keV. The analog section includes a charge sensitive preamplifier, a shaper with 3-bit digitally selectable shaping times from 1.6 µs to 6.6 µs and a peak stretcher/sample-and-hold stage. The digital/mixed-signal section includes an amplitude discriminator with coarse and fine threshold level setting, a peak discriminator and a logic circuit to fulfill pile-up rejection, signal sampling, trigger generation, channel reset and the preamplifier and discriminators disabling functionalities. A Serial Peripherical Interface (SPI) is integrated in VEGA for loading and storing all configuration parameters in an internal register within few microseconds. The VEGA ASIC has been designed and manufactured in 0.35 µm CMOS mixed-signal technology in single and 32 channel versions with dimensions of 200 µm×500 µm per channel. A minimum intrinsic Equivalent Noise Charge (ENC) of 12 electrons r.m.s. at 3.6 µs peaking time and room temperature is measured and the linearity error is between −0.9% and +0.6% in the whole input energy range. The total power consumption is 481 µW and 420 µW per channel for the single and 32 channels version, respectively. A comparison with other ASICs for X-ray SDD’s shows that VEGA has a suitable low noise and offers high functionality as ADC-ready signal processing but at a power consumption that is a factor of four lower than other similar existing ASICs.

Frontend electronics for high-precision single photo-electron timing using FPGA-TDCs

Science.gov (United States)

Cardinali, M.; Dzyhgadlo, R.; Gerhardt, A.; Götzen, K.; Hohler, R.; Kalicy, G.; Kumawat, H.; Lehmann, D.; Lewandowski, B.; Patsyuk, M.; Peters, K.; Schepers, G.; Schmitt, L.; Schwarz, C.; Schwiening, J.; Traxler, M.; Ugur, C.; Zühlsdorf, M.; Dodokhov, V. Kh.; Britting, A.; Eyrich, W.; Lehmann, A.; Uhlig, F.; Düren, M.; Föhl, K.; Hayrapetyan, A.; Kröck, B.; Merle, O.; Rieke, J.; Cowie, E.; Keri, T.; Montgomery, R.; Rosner, G.; Achenbach, P.; Corell, O.; Ferretti Bondy, M. I.; Hoek, M.; Lauth, W.; Rosner, C.; Sfienti, C.; Thiel, M.; Bühler, P.; Gruber, L.; Marton, J.; Suzuki, K.

2014-12-01

The next generation of high-luminosity experiments requires excellent particle identification detectors which calls for Imaging Cherenkov counters with fast electronics to cope with the expected hit rates. A Barrel DIRC will be used in the central region of the Target Spectrometer of the planned PANDA experiment at FAIR. A single photo-electron timing resolution of better than 100 ps is required by the Barrel DIRC to disentangle the complicated patterns created on the image plane. R&D studies have been performed to provide a design based on the TRB3 readout using FPGA-TDCs with a precision better than 20 ps RMS and custom frontend electronics with high-bandwidth pre-amplifiers and fast discriminators. The discriminators also provide time-over-threshold information thus enabling walk corrections to improve the timing resolution. Two types of frontend electronics cards optimised for reading out 64-channel PHOTONIS Planacon MCP-PMTs were tested: one based on the NINO ASIC and the other, called PADIWA, on FPGA discriminators. Promising results were obtained in a full characterisation using a fast laser setup and in a test experiment at MAMI, Mainz, with a small scale DIRC prototype.

Characterisation of the NA62 GigaTracker end of column readout ASIC

International Nuclear Information System (INIS)

Noy, M; Rinella, G Aglieri; Fiorini, M; Jarron, P; Kaplon, J; Kluge, A; Morel, M; Perktold, L; Riedler, P; Martin, E

2011-01-01

The architecture and characterisation of the End Of Column demonstrator readout ASIC for the NA62 GigaTracker hybrid pixel detector is presented. This ASIC serves as a proof of principle for a pixel chip with 1800 pixels which must perform time stamping to better than 200 ps (RMS), provide 300 μm pitch position information and operate with a dead-time of 1% or less for 800 MHz-1 GHz beam rate. The demonstrator ASIC comprises a full test column with 45 pixels alongside other test structures. The timewalk correction mechanism employed is measurement of the time-over-threshold, coupled with an off-detector look-up table. The time to digital converter is a delay locked loop with 32 contributing delay cells fed with a 320 MHz to yield a nominal bin size of 97 ps. Recently, P-in-N sensors have been bump-bonded to the ASIC and characterisation of these assemblies has begun.

ASIC-enabled High Resolution Optical Time Domain Reflectometer

Science.gov (United States)

Skendzic, Sandra

Fiber optics has become the preferred technology in communication systems because of what it has to offer: high data transmission rates, immunity to electromagnetic interference, and lightweight, flexible cables. An optical time domain reflectometer (OTDR) provides a convenient method of locating and diagnosing faults (e.g. break in a fiber) along a fiber that can obstruct crucial optical pathways. Both the ability to resolve the precise location of the fault and distinguish between two discrete, closely spaced faults are figures of merit. This thesis presents an implementation of a high resolution OTDR through the use of a compact and programmable ASIC (application specific integrated circuit). The integration of many essential OTDR functions on a single chip is advantageous over existing commercial instruments because it enables small, lightweight packaging, and offers low power and cost efficiency. Furthermore, its compactness presents the option of placing multiple ASICs in parallel, which can conceivably ease the characterization of densely populated fiber optic networks. The OTDR ASIC consists of a tunable clock, pattern generator, precise timer, electrical receiver, and signal sampling circuit. During OTDR operation, the chip generates narrow electrical pulse, which can then be converted to optical format when coupled with an external laser diode driver. The ASIC also works with an external photodetector to measure the timing and amplitude of optical reflections in a fiber. It has a 1 cm sampling resolution, which allows for a 2 cm spatial resolution. While this OTDR ASIC has been previously demonstrated for multimode fiber fault diagnostics, this thesis focuses on extending its functionality to single mode fiber. To validate this novel approach to OTDR, this thesis is divided into five chapters: (1) introduction, (2) implementation, (3), performance of ASIC-based OTDR, (4) exploration in optical pre-amplification with a semiconductor optical amplifier, and

ASIC for time-of-flight measurements with picosecond timing resolution

Energy Technology Data Exchange (ETDEWEB)

Stankova, Vera; Shen, Wei; Harion, Tobias [Kirchhoff-Institute for Physics, Heidelberg Univ. (Germany)

2015-07-01

The Positron Emission Tomography (PET) images are especially affected by a high level of noise. This noise affects the potential to detect and discriminate the tumor in relation to the background. Including Time-of-Flight information, with picosecond time resolution, within the conventional PET scanners will improve the signal-to-noise ratio (SNR) and in sequence the quality of the medical images. A mix-mode ASIC (STIC3) has been developed for high precision timing measurements with Silicon Photomultipliers (SiPM). The STiC3 is 64-channel chip, with fully differential analog front-end for crosstalk and electronic noise immunity. It integrates Time to Digital Converters (TDC) with time binning of 50.2 ps for time and energy measurements. Measurements of the of the analog front-end show a time jitter less than 20 ps and jitter of the TDC together with the digital part is around 37 ps. Further the timing of a channel has been tested by injecting a pulse into two channels and measuring the time difference of the recorded timestamps. A Coincidence Time Resolution (CTR) of 215 ps FWHM has been obtained with 3.1 x 3.1 x 15 mm{sup 2} LYSO:Ce scintillator crystals and Hamamatsu SiPM matric (S12643-050CN(x)). Characterization measurements with the chip and its performances are presented.

A Batteryless Sensor ASIC for Implantable Bio-Impedance Applications.

Science.gov (United States)

Rodriguez, Saul; Ollmar, Stig; Waqar, Muhammad; Rusu, Ana

2016-06-01

The measurement of the biological tissue's electrical impedance is an active research field that has attracted a lot of attention during the last decades. Bio-impedances are closely related to a large variety of physiological conditions; therefore, they are useful for diagnosis and monitoring in many medical applications. Measuring living tissues, however, is a challenging task that poses countless technical and practical problems, in particular if the tissues need to be measured under the skin. This paper presents a bio-impedance sensor ASIC targeting a battery-free, miniature size, implantable device, which performs accurate 4-point complex impedance extraction in the frequency range from 2 kHz to 2 MHz. The ASIC is fabricated in 150 nm CMOS, has a size of 1.22 mm × 1.22 mm and consumes 165 μA from a 1.8 V power supply. The ASIC is embedded in a prototype which communicates with, and is powered by an external reader device through inductive coupling. The prototype is validated by measuring the impedances of different combinations of discrete components, measuring the electrochemical impedance of physiological solution, and performing ex vivo measurements on animal organs. The proposed ASIC is able to extract complex impedances with around 1 Ω resolution; therefore enabling accurate wireless tissue measurements.

An updated front-end data link design for the Phase-2 upgrade of the ATLAS Tile Calorimeter

CERN Document Server

Silverstein, Samuel; The ATLAS collaboration

2017-01-01

We present a new design of the advanced Link Daughter Board (DB) for the front-end electronics upgrade of the ATLAS Tile Calorimeter (TileCal) for Phase-II. The new TileCal front-end comprises 1024 “mini-drawers” (MD) installed in 256 calorimeter modules. Each MD serves up to 12 PMT channels, with ADCs and calibration provided by one “main board” (MB) per MD. The DB is connected to the MB through a dense, high-speed FMC connector, and provides bi-directional multi-Gb/s optlcal links to the off-detector electronics for timing, control, and continuous high-speed readout of the ADC channels on the MB. The DB is designed for redundancy and fault-tolerance, and previous versions have already been successfully tested at CERN and elsewhere. The new revision includes Kintex Ultrascale+ FPGAs for improved link timing and radiation tolerance, an expanded role for the rad-tolerant GBTx ASICs, and a simpler design requiring fewer components and optical links.

ASIC PROTEINS REGULATE SMOOTH MUSCLE CELL MIGRATION

OpenAIRE

Grifoni, Samira C.; Jernigan, Nikki L.; Hamilton, Gina; Drummond, Heather A.

2007-01-01

The purpose of the present study was to investigate Acid Sensing Ion Channel (ASIC) protein expression and importance in cellular migration. We recently demonstrated Epithelial Na+ Channel (ENaC) proteins are required for vascular smooth muscle cell (VSMC) migration, however the role of the closely related ASIC proteins has not been addressed. We used RT-PCR and immunolabeling to determine expression of ASIC1, ASIC2, ASIC3 and ASIC4 in A10 cells. We used small interference RNA to silence indi...

Rad-Hard Structured ASIC Body of Knowledge

Science.gov (United States)

Heidecker, Jason

2013-01-01

Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

Radiation-induced effects on the XAA1.2 ASIC chip for space application

Energy Technology Data Exchange (ETDEWEB)

Del Monte, Ettore [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy) and Dipartimento di Fisica, Universita di Roma ' Tor Vergata' , Via della Ricerca Scientifica 1, I-00133 Rome (Italy)]. E-mail: delmonte@rm.iasf.cnr.it; Pacciani, Luigi [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Porrovecchio, Geiland [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Soffitta, Paolo [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Costa, Enrico [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Di Persio, Giuseppe [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Feroci, Marco [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Mastropietro, Marcello [Istituto di Metodologie Inorganiche e dei Plasmi, CNR, Roma, Via Salaria km 29.300, I-00016 Monterotondo Scalo (RM) c.p. 10 (Italy); Morelli, Ennio [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Bologna, Via P. Gobetti 101, I-40129 Bologna (Italy); Rapisarda, Massimo [ENEA C.R. Frascati, Via Enrico Fermi 45, I-00044 Frascati, RM (Italy); Rubini, Alda [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Bisello, Dario; Candelori, Andrea [Dipartimento di Fisica, Universita di Padova, INFN Sezione di Padova, Via Marzolo 8, I-35100 Padova (Italy); Kaminski, Alexandre [Dipartimento di Fisica, Universita di Padova, INFN Sezione di Padova, Via Marzolo 8, I-35100 Padova (Italy); Wyss, Jeffery [DIMSAT, Universita di Cassino, Via Di Biasio 43, I-03043 Cassino, FR (Italy)

2005-02-11

The XAA1.2 is a custom ASIC chip for space applications built using a 0.8{mu}m complementary metal oxide semiconductor technology on epitaxial layer. It has been selected as the front-end electronics chip of the SuperAGILE experiment on board the AGILE space mission, although it is not specifically designed as a radiation hard device. To study the XAA1.2 sensitivity to Single Event Effects and Total Dose Effects we irradiate this chip at the SIRAD facility of the Laboratori Nazionali INFN of Legnaro. In this paper we describe the experimental set-up and the measurements. We then discuss how the results can be scaled to the cosmic rays environment in a low-Earth orbit.

Radiation-induced effects on the XAA1.2 ASIC chip for space application

International Nuclear Information System (INIS)

Del Monte, Ettore; Pacciani, Luigi; Porrovecchio, Geiland; Soffitta, Paolo; Costa, Enrico; Di Persio, Giuseppe; Feroci, Marco; Mastropietro, Marcello; Morelli, Ennio; Rapisarda, Massimo; Rubini, Alda; Bisello, Dario; Candelori, Andrea; Kaminski, Alexandre; Wyss, Jeffery

2005-01-01

The XAA1.2 is a custom ASIC chip for space applications built using a 0.8μm complementary metal oxide semiconductor technology on epitaxial layer. It has been selected as the front-end electronics chip of the SuperAGILE experiment on board the AGILE space mission, although it is not specifically designed as a radiation hard device. To study the XAA1.2 sensitivity to Single Event Effects and Total Dose Effects we irradiate this chip at the SIRAD facility of the Laboratori Nazionali INFN of Legnaro. In this paper we describe the experimental set-up and the measurements. We then discuss how the results can be scaled to the cosmic rays environment in a low-Earth orbit

Characterization and performance of the ASIC (CITIROC) front-end of the ASTRI camera

Energy Technology Data Exchange (ETDEWEB)

Impiombato, D., E-mail: Domenico.Impiombato@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Giarrusso, S., E-mail: Giarrusso@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Mineo, T., E-mail: Mineo@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Catalano, O., E-mail: Catalano@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Gargano, C.; La Rosa, G.; Russo, F.; Sottile, G. [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Billotta, S.; Bonanno, G.; Garozzo, S.; Grillo, A.; Marano, D.; Romeo, G. [INAF, Osservatorio Astrofisico di Catania, via S. Sofia 78, I-95123 Catania (Italy)

2015-09-11

The Cherenkov Imaging Telescope Integrated Read Out Chip, CITIROC, is a chip adopted as the front-end of the camera at the focal plane of the imaging Cherenkov ASTRI dual-mirror small size telescope (ASTRI SST-2M) prototype. This paper presents the results of the measurements performed to characterize CITIROC tailored for the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger linearity and efficiency, as a function of the pulse amplitude. Moreover, we tested its response by performing a set of measurements using a silicon photomultiplier (SiPM) in dark conditions and under light pulse illumination. The CITIROC output signal is found to vary linearly as a function of the input pulse amplitude. Our results show that it is suitable for the ASTRI SST-2M camera.

Characterization and performance of the ASIC (CITIROC) front-end of the ASTRI camera

International Nuclear Information System (INIS)

Impiombato, D.; Giarrusso, S.; Mineo, T.; Catalano, O.; Gargano, C.; La Rosa, G.; Russo, F.; Sottile, G.; Billotta, S.; Bonanno, G.; Garozzo, S.; Grillo, A.; Marano, D.; Romeo, G.

2015-01-01

The Cherenkov Imaging Telescope Integrated Read Out Chip, CITIROC, is a chip adopted as the front-end of the camera at the focal plane of the imaging Cherenkov ASTRI dual-mirror small size telescope (ASTRI SST-2M) prototype. This paper presents the results of the measurements performed to characterize CITIROC tailored for the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger linearity and efficiency, as a function of the pulse amplitude. Moreover, we tested its response by performing a set of measurements using a silicon photomultiplier (SiPM) in dark conditions and under light pulse illumination. The CITIROC output signal is found to vary linearly as a function of the input pulse amplitude. Our results show that it is suitable for the ASTRI SST-2M camera

First results of the front-end ASIC for the strip detector of the PANDA MVD

Science.gov (United States)

Quagli, T.; Brinkmann, K.-T.; Calvo, D.; Di Pietro, V.; Lai, A.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Wheadon, R.; Zambanini, A.

2017-03-01

PANDA is a key experiment of the future FAIR facility and the Micro Vertex Detector (MVD) is the innermost part of its tracking system. PASTA (PAnda STrip ASIC) is the readout chip for the strip part of the MVD. The chip is designed to provide high resolution timestamp and charge information with the Time over Threshold (ToT) technique. Its architecture is based on Time to Digital Converters with analog interpolators, with a time bin width of 50 ps. The chip implements Single Event Upset (SEU) protection techniques for its digital parts. A first full-size prototype with 64 channels was produced in a commercial 110 nm CMOS technology and the first characterizations of the prototype were performed.

Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

CERN Document Server

de La Taille, C

2008-01-01

The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

ASIC3 channels in multimodal sensory perception.

Science.gov (United States)

Li, Wei-Guang; Xu, Tian-Le

2011-01-19

Acid-sensing ion channels (ASICs), which are members of the sodium-selective cation channels belonging to the epithelial sodium channel/degenerin (ENaC/DEG) family, act as membrane-bound receptors for extracellular protons as well as nonproton ligands. At least five ASIC subunits have been identified in mammalian neurons, which form both homotrimeric and heterotrimeric channels. The highly proton sensitive ASIC3 channels are predominantly distributed in peripheral sensory neurons, correlating with their roles in multimodal sensory perception, including nociception, mechanosensation, and chemosensation. Different from other ASIC subunit composing ion channels, ASIC3 channels can mediate a sustained window current in response to mild extracellular acidosis (pH 7.3-6.7), which often occurs accompanied by many sensory stimuli. Furthermore, recent evidence indicates that the sustained component of ASIC3 currents can be enhanced by nonproton ligands including the endogenous metabolite agmatine. In this review, we first summarize the growing body of evidence for the involvement of ASIC3 channels in multimodal sensory perception and then discuss the potential mechanisms underlying ASIC3 activation and mediation of sensory perception, with a special emphasis on its role in nociception. We conclude that ASIC3 activation and modulation by diverse sensory stimuli represent a new avenue for understanding the role of ASIC3 channels in sensory perception. Furthermore, the emerging implications of ASIC3 channels in multiple sensory dysfunctions including nociception allow the development of new pharmacotherapy.

Proton and non-proton activation of ASIC channels.

Directory of Open Access Journals (Sweden)

Ivan Gautschi

Full Text Available The Acid-Sensing Ion Channels (ASIC exhibit a fast desensitizing current when activated by pH values below 7.0. By contrast, non-proton ligands are able to trigger sustained ASIC currents at physiological pHs. To analyze the functional basis of the ASIC desensitizing and sustained currents, we have used ASIC1a and ASIC2a mutants with a cysteine in the pore vestibule for covalent binding of different sulfhydryl reagents. We found that ASIC1a and ASIC2a exhibit two distinct currents, a proton-induced desensitizing current and a sustained current triggered by sulfhydryl reagents. These currents differ in their pH dependency, their sensitivity to the sulfhydryl reagents, their ionic selectivity and their relative magnitude. We propose a model for ASIC1 and ASIC2 activity where the channels can function in two distinct modes, a desensitizing mode and a sustained mode depending on the activating ligands. The pore vestibule of the channel represents a functional site for binding non-proton ligands to activate ASIC1 and ASIC2 at neutral pH and to prevent channel desensitization.

Proton and non-proton activation of ASIC channels.

Science.gov (United States)

Gautschi, Ivan; van Bemmelen, Miguel Xavier; Schild, Laurent

2017-01-01

The Acid-Sensing Ion Channels (ASIC) exhibit a fast desensitizing current when activated by pH values below 7.0. By contrast, non-proton ligands are able to trigger sustained ASIC currents at physiological pHs. To analyze the functional basis of the ASIC desensitizing and sustained currents, we have used ASIC1a and ASIC2a mutants with a cysteine in the pore vestibule for covalent binding of different sulfhydryl reagents. We found that ASIC1a and ASIC2a exhibit two distinct currents, a proton-induced desensitizing current and a sustained current triggered by sulfhydryl reagents. These currents differ in their pH dependency, their sensitivity to the sulfhydryl reagents, their ionic selectivity and their relative magnitude. We propose a model for ASIC1 and ASIC2 activity where the channels can function in two distinct modes, a desensitizing mode and a sustained mode depending on the activating ligands. The pore vestibule of the channel represents a functional site for binding non-proton ligands to activate ASIC1 and ASIC2 at neutral pH and to prevent channel desensitization.

The front-end data conversion and readout electronics for the CMS ECAL upgrade

CERN Document Server

Mazza, Gianni

2017-01-01

The High Luminosity LHC (HL-LHC) will require a significant upgrade of the readout electronics for the CMS Electromagnetic Calorimeter (ECAL). The Very Front-End (VFE) output signal will be sampled at 160 MS/s (i.e. four times the current sampling rate) with 13 bit resolution. Therefore, a high-speed, high-resolution ADC is required. Moreover, each readout channel will produce 2.08 Gb/s, thus requiring fast data transmission circuitry. A new readout architecture, based on two 12 bit, 160 MS/s ADCs, lossless data compression algorithms and fast serial links have been developed for the ECAL upgrade. These functions will be integrated in a single ASIC which is currently under design in a commercial CMOS 65 nm technology using radiation damage mitigation techniques.

Update on the high speed serializer ASIC development for ATLAS Liquid Argon calorimeter upgrade

CERN Document Server

Liu, T; The ATLAS collaboration

2011-01-01

We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in a 200 MeV proton beam. The test results indicate that the first prototype meets the design goals. The second prototype, a double-lane, 8 Gbps per lane serializer is under development. The post-layout simulation indicates that 8 Gbps is achievable. In this paper we present the design and the test results of the first prototype and the design and status of the second prototype.

A 4×8-Gbps VCSEL array driver ASIC and integration with a custom array transmitter module for the LHC front-end transmission

International Nuclear Information System (INIS)

Guo, Di; Liu, Chonghan; Chen, Jinghong; Chramowicz, John; Gong, Datao; He, Huiqin; Hou, Suen; Liu, Tiankuan; Prosser, Alan; Teng, Ping-Kun; Xiang, Annie C.; Xiao, Le; Ye, Jingbo

2016-01-01

This paper describes the design, fabrication and experiment results of a 4×8-Gbps Vertical-Cavity Surface-Emitting Laser (VCSEL) array driver ASIC with the adjustable active-shunt peaking technique and the novel balanced output structure under the Silicon-on-Sapphire (SOS) process, and a custom array optical transmitter module, featuring a compact size of 10 mm×15 mm×5.3 mm. Both the array driver ASIC and the module have been fully tested after integration as a complete parallel transmitter. Optical eye diagram of each channel passes the eye mask at 8 Gbps/ch with adjacent channel working simultaneously with a power consumption of 150 mW/ch. The optical transmission of Bit-Error Rate (BER) less than 10E-12 is achieved at an aggregated data rate of 4×8-Gbps. - Highlights: • An anode-driven VCSEL Array driver ASIC with the configurable active-shunt peaking technique in pre-driving stages. • A novel full-differential balanced output structure is used to minimize the noise and crosstalk from the power. • A custom array optical transmitter module with custom low-cost reliable alignment method.

A 4×8-Gbps VCSEL array driver ASIC and integration with a custom array transmitter module for the LHC front-end transmission

Energy Technology Data Exchange (ETDEWEB)

Guo, Di [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei Anhui 230026 (China); Liu, Chonghan [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Chen, Jinghong [Department of Electrical and Computer Engineering, University of Houston, Houston, TX 77004 (United States); Chramowicz, John [Real-Time Systems Engineering Department, Fermi National Laboratory, Batavia, IL 60510 (United States); Gong, Datao [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); He, Huiqin [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Shenzhen Polytechnic, Shenzhen 518055 (China); Hou, Suen [Institute of Physics, Academia Sinica, Nangang 11529, Taipei, Taiwan (China); Liu, Tiankuan [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Prosser, Alan [Real-Time Systems Engineering Department, Fermi National Laboratory, Batavia, IL 60510 (United States); Teng, Ping-Kun [Institute of Physics, Academia Sinica, Nangang 11529, Taipei, Taiwan (China); Xiang, Annie C. [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Xiao, Le [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Department of Physics, Central China Normal University, Wuhan, Hubei 430079 (China); Ye, Jingbo [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States)

2016-09-21

This paper describes the design, fabrication and experiment results of a 4×8-Gbps Vertical-Cavity Surface-Emitting Laser (VCSEL) array driver ASIC with the adjustable active-shunt peaking technique and the novel balanced output structure under the Silicon-on-Sapphire (SOS) process, and a custom array optical transmitter module, featuring a compact size of 10 mm×15 mm×5.3 mm. Both the array driver ASIC and the module have been fully tested after integration as a complete parallel transmitter. Optical eye diagram of each channel passes the eye mask at 8 Gbps/ch with adjacent channel working simultaneously with a power consumption of 150 mW/ch. The optical transmission of Bit-Error Rate (BER) less than 10E-12 is achieved at an aggregated data rate of 4×8-Gbps. - Highlights: • An anode-driven VCSEL Array driver ASIC with the configurable active-shunt peaking technique in pre-driving stages. • A novel full-differential balanced output structure is used to minimize the noise and crosstalk from the power. • A custom array optical transmitter module with custom low-cost reliable alignment method.

Phase-II Associative Memory ASIC Specifications

CERN Document Server

Stabile, Alberto; Warren, Matthew; Green, Barry; Konstantinidis, Nikolaos; Motuk, Halil Erdem; Frontini, Luca; Liberali, Valentino; Crescioli, Francesco; Fedi, Giacomo; Sotiropoulou, Calliope-louisa; De Canio, Francesco; Traversi, Gianluca; Shojaii, Seyed Ruhollah; Kubota, Takashi; Calderini, Giovanni; Palla, Fabrizio; Checcucci, Bruno; Spiller, Laurence Anthony; Mcnamara, Peter Charles

2018-01-01

This documents defines the specifications for the Associative Memory ASIC for Phase-II. The work-flow toward the final ASIC is organized in the following three steps • AM08 prototype: small area MPW prototype to test all the full custom features, the VHDL logic and the I/O. This chip must be fully functional with smaller memory area than the final ASIC; • AM09pre pre-production: full area ASIC to be fabricated with a full-mask set pilot run. Production corner wafers will be created; • AM09 production: full area ASIC with refinements for the mass production. The AM09 will be developed built on the AM08 extending the memory area, therefore the specification of both versions must be compatible.

Measurements of low noise 64 channel counting ASIC for Si and CdTe strip detectors

International Nuclear Information System (INIS)

Kachel, M; Grybos, P; Szczygiel, R; Takeyoshi, T

2011-01-01

We present the design and performance of a 64-channel ASIC called SXDR64. The circuit is intended to work with DC coupled CdTe detectors as well as with standard AC coupled Si detectors. A single channel of the ASIC consists of a charge sensitive amplifier with a pole-zero cancellation circuit, a 4 th order programmable shaper, a base-line restorer and two independent discriminators with 20-bit counters equipped with RAM. The circuit is able to operate correctly with both polarities of the input signal and the detectors leakage current in a few nA range, with the average rate of input pulses up to 1 Mcps.

The TDCpix readout ASIC: A 75 ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

Energy Technology Data Exchange (ETDEWEB)

Kluge, A., E-mail: alexander.kluge@cern.ch; Aglieri Rinella, G.; Bonacini, S.; Jarron, P.; Kaplon, J.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

2013-12-21

The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm{sup 2} for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection efficiency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45×40 square pixels of 300×300μm{sup 2} and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low-jitter PLL, readout and control circuits. This contribution will describe the complete design of the final TDCpix ASIC. It will discuss design choices, the challenges faced and some of the lessons learned. Furthermore, experimental results from the testing of circuit prototypes will be presented. These demonstrate the achievement of key performance figures such as a time resolution of the processing chain of 75 ps rms with a laser sent to the center of the pixel and the capability of time stamping charged particles with an overall resolution below 200 ps rms. -- Highlights: • Feasibility demonstration of a silicon pixel detector with sub-ns time tagging capability. • Demonstrator detector assembly with a time resolution of 75 ps RMS with laser charge injection; 170 ps RMS with particle beam. • Design of trigger-less TDCpix ASIC with 1800 pixels, 720 TDC channels and 4 3.2 Gbit/s serializers.

ASIC-like, proton-activated currents in rat hippocampal neurons.

Science.gov (United States)

Baron, Anne; Waldmann, Rainer; Lazdunski, Michel

2002-03-01

The expression of mRNA for acid sensing ion channels (ASIC) subunits ASIC1a, ASIC2a and ASIC2b has been reported in hippocampal neurons, but the presence of functional hippocampal ASIC channels was never assessed. We report here the first characterization of ASIC-like currents in rat hippocampal neurons in primary culture. An extracellular pH drop induces a transient Na(+) current followed by a sustained non-selective cation current. This current is highly sensitive to pH with an activation threshold around pH 6.9 and a pH(0.5) of 6.2. About half of the total peak current is inhibited by the spider toxin PcTX1, which is specific for homomeric ASIC1a channels. The remaining PcTX1-resistant ASIC-like current is increased by 300 microM Zn(2+) and, whereas not fully activated at pH 5, it shows a pH(0.5) of 6.0 between pH 7.4 and 5. We have previously shown that Zn(2+) is a co-activator of ASIC2a-containing channels. Thus, the hippocampal transient ASIC-like current appears to be generated by a mixture of homomeric ASIC1a channels and ASIC2a-containing channels, probably heteromeric ASIC1a+2a channels. The sustained non-selective current suggests the involvement of ASIC2b-containing heteromeric channels. Activation of the hippocampal ASIC-like current by a pH drop to 6.9 or 6.6 induces a transient depolarization which itself triggers an initial action potential (AP) followed by a sustained depolarization and trains of APs. Zn(2+) increases the acid sensitivity of ASIC channels, and consequently neuronal excitability. It is probably an important co-activator of ASIC channels in the central nervous system.

ASIC subunit ratio and differential surface trafficking in the brain.

Science.gov (United States)

Wu, Junjun; Xu, Yuanyuan; Jiang, Yu-Qing; Xu, Jiangping; Hu, Youjia; Zha, Xiang-ming

2016-01-08

Acid-sensing ion channels (ASICs) are key mediators of acidosis-induced responses in neurons. However, little is known about the relative abundance of different ASIC subunits in the brain. Such data are fundamental for interpreting the relative contribution of ASIC1a homomers and 1a/2 heteromers to acid signaling, and essential for designing therapeutic interventions to target these channels. We used a simple biochemical approach and semi-quantitatively determined the molar ratio of ASIC1a and 2 subunits in mouse brain. Further, we investigated differential surface trafficking of ASIC1a, ASIC2a, and ASIC2b. ASIC1a subunits outnumber the sum of ASIC2a and ASIC2b. There is a region-specific variation in ASIC2a and 2b expression, with cerebellum and striatum expressing predominantly 2b and 2a, respectively. Further, we performed surface biotinylation and found that surface ASIC1a and ASIC2a ratio correlates with their total expression. In contrast, ASIC2b exhibits little surface presence in the brain. This result is consistent with increased co-localization of ASIC2b with an ER marker in 3T3 cells. Our data are the first semi-quantitative determination of relative subunit ratio of various ASICs in the brain. The differential surface trafficking of ASICs suggests that the main functional ASICs in the brain are ASIC1a homomers and 1a/2a heteromers. This finding provides important insights into the relative contribution of various ASIC complexes to acid signaling in neurons.

Design of the Front-End Detector Control System of the ATLAS New Small Wheels

CERN Document Server

Koulouris, Aimilianos; The ATLAS collaboration

2017-01-01

The ATLAS experiment will be upgraded during the next LHC Long Shutdown (LS2). The flagship upgrade is the New Small Wheel (NSW), which consists of 2 disks of Muon Gas detectors. The detector technologies used are Micromegas (MM) and sTGC, providing a total of 16 layers of tracking and trigger. The Slow Control Adapter (SCA) is part of the GigaBit Transceiver (GBT) - “Radiation Hard Optical Link Project” family of chips designed at CERN, EP-ESE department, which will be used at the NSW upgrade. The SCA offers several interfaces to read analog and digital inputs, and configure front-end Readout ASICs, FPGAs, or other chips. This poster gives an overview of the system, data flow, and software developed for communicating with the SCA.

Back-end and interface implementation of the STS-XYTER2 prototype ASIC for the CBM experiment

International Nuclear Information System (INIS)

Kasinski, K.; Szczygiel, R.; Zabolotny, W.

2016-01-01

Each front-end readout ASIC for the High-Energy Physics experiments requires robust and effective hit data streaming and control mechanism. A new STS-XYTER2 full-size prototype chip for the Silicon Tracking System and Muon Chamber detectors in the Compressed Baryonic Matter experiment at Facility for Antiproton and Ion Research (FAIR, Germany) is a 128-channel time and amplitude measuring solution for silicon microstrip and gas detectors. It operates at 250 kHit/s/channel hit rate, each hit producing 27 bits of information (5-bit amplitude, 14-bit timestamp, position and diagnostics data). The chip back-end implements fast front-end channel read-out, timestamp-wise hit sorting, and data streaming via a scalable interface implementing the dedicated protocol (STS-HCTSP) for chip control and hit transfer with data bandwidth from 9.7 MHit/s up to 47 MHit/s. It also includes multiple options for link diagnostics, failure detection, and throttling features. The back-end is designed to operate with the data acquisition architecture based on the CERN GBTx transceivers. This paper presents the details of the back-end and interface design and its implementation in the UMC 180 nm CMOS process.

The PASTA chip - A free-running readout ASIC for silicon strip sensors in PANDA

Energy Technology Data Exchange (ETDEWEB)

Goerres, Andre; Stockmanns, Tobias; Ritman, James [Institut fuer Kernphysik, Forschungszentrum Juelich, Juelich (Germany); Rivetti, Angelo [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

2014-07-01

The PANDA experiment is a multi purpose detector, investigating hadron physics in the charm quark mass regime. It is one of the main experiments at the future FAIR accelerator facility, using pp annihilations from a 1.5-15 GeV/c anti-proton beam. Because of the broad physics spectrum and the similarity of event and background signals, PANDA does not rely on a hardware-level trigger decision. The innermost of PANDA's sub-systems is the Micro Vertex Detector (MVD), consisting of silicon pixel and strip sensors. The latter will be read out by a specialized, free-running readout front-end called PANDA Strip ASIC (PASTA). It has to face a high event rate of up to 40 kHz/ch in an radiation-intense environment. To fulfill the MVD's requirements, it has to give accurate timing information to incoming events (<10 ns) and determine the collected charge with an 8-bit precision. The design has to meet cooling and placing restrictions, leading to a very low power consumption (<4 mW/ch) and limited dimensions. Therefore, a simple, time-based readout approach is chosen. In this talk, the conceptual design of the front-end is presented.

Estimating Delays In ASIC's

Science.gov (United States)

Burke, Gary; Nesheiwat, Jeffrey; Su, Ling

1994-01-01

Verification is important aspect of process of designing application-specific integrated circuit (ASIC). Design must not only be functionally accurate, but must also maintain correct timing. IFA, Intelligent Front Annotation program, assists in verifying timing of ASIC early in design process. This program speeds design-and-verification cycle by estimating delays before layouts completed. Written in C language.

A 2D 4×4 Channel Readout ASIC for Pixelated CdTe Detectors for Medical Imaging Applications.

Science.gov (United States)

Macias-Montero, Jose-Gabriel; Sarraj, Maher; Chmeissani, Mokhtar; Martínez, Ricardo; Puigdengoles, Carles

2015-10-01

We present a 16-channel readout integrated circuit (ROIC) with nanosecond-resolution time to digital converter (TDC) for pixelated Cadmium Telluride (CdTe) gamma-ray detectors. The 4 × 4 pixel array ROIC is the proof of concept of the 10 × 10 pixel array readout ASIC for positron-emission tomography (PET) scanner, positron-emission mammography (PEM) scanner, and Compton gamma camera. The electronics of each individual pixel integrates an analog front-end with switchable gain, an analog to digital converter (ADC), configuration registers, and a 4-state digital controller. For every detected photon, the pixel electronics provides the energy deposited in the detector with 10-bit resolution, and a fast trigger signal for time stamp. The ASIC contains the 16-pixel matrix electronics, a digital controller, five global voltage references, a TDC, a temperature sensor, and a band-gap based current reference. The ASIC has been fabricated with TSMC 0.25 μ m mixed-signal CMOS technology and occupies an area of 5.3 mm × 6.8 mm. The TDC shows a resolution of 95.5 ps, a precision of 600 ps at full width half maximum (FWHM), and a power consumption of 130 μ W. In acquisition mode, the total power consumption of every pixel is 200 μ W. An equivalent noise charge (ENC) of 160 e - RMS at maximum gain and negative polarity conditions has been measured at room temperature.

The front-end data conversion and readout electronics for the CMS ECAL upgrade

Science.gov (United States)

Mazza, G.; Cometti, S.

2018-03-01

The High Luminosity LHC (HL-LHC) will require a significant upgrade of the readout electronics for the CMS Electromagnetic Calorimeter (ECAL). The Very Front-End (VFE) output signal will be sampled at 160 MS/s (i.e. four times the current sampling rate) with a 13 bits resolution. Therefore, a high-speed, high-resolution ADC is required. Moreover, each readout channel will produce 2.08 Gb/s, thus requiring a fast data transmission circuitry. A new readout architecture, based on two 12 bit, 160 MS/s ADCs, lossless data compression algorithms and fast serial links have been developed for the ECAL upgrade. These functions will be integrated in a single ASIC which is currently under design in a commercial CMOS 65 nm technology using radiation damage mitigation techniques.

Pixel readout ASIC for an APD based 2D X-ray hybrid pixel detector with sub-nanosecond resolution

Energy Technology Data Exchange (ETDEWEB)

Thil, Ch., E-mail: christophe.thil@ziti.uni-heidelberg.d [Heidelberg University, Institute of Computer Engineering, B6, 26, 68161 Mannheim (Germany); Baron, A.Q.R. [RIKEN SPring-8 Center, 1-1-1 Kouto, Sayo-cho, Sayo-gun, Hyogo 679-5148 (Japan); Fajardo, P. [ESRF, Polygone Scientifique Louis Neel, 6, rue Jules Horowitz, 38000 Grenoble (France); Fischer, P. [Heidelberg University, Institute of Computer Engineering, B6, 26, 68161 Mannheim (Germany); Graafsma, H. [DESY, Notkestrasse 85, 22607 Hamburg (Germany); Rueffer, R. [ESRF, Polygone Scientifique Louis Neel, 6, rue Jules Horowitz, 38000 Grenoble (France)

2011-02-01

The fast response and the short recovery time of avalanche photodiodes (APDs) in linear mode make those devices ideal for direct X-ray detection in applications requiring high time resolution or counting rate. In order to provide position sensitivity, the XNAP project aims at creating a hybrid pixel detector with nanosecond time resolution based on a monolithic APD sensor array with 32 x32 pixels covering about 1 cm{sup 2} active area. The readout is implemented in a pixelated front-end ASIC suited for the readout of such arrays, matched to pixels of 280{mu}mx280{mu}m size. Every single channel features a fast transimpedance amplifier, a discriminator with locally adjustable threshold and two counters with high dynamic range and counting speed able to accumulate X-ray hits with no readout dead time. Additionally, the detector can be operated in list mode by time-stamping every single event with sub-nanosecond resolution. In a first phase of the project, a 4x4 pixel test module is built to validate the conceptual design of the detector. The XNAP project is briefly presented and the performance of the readout ASIC is discussed.

Pixel readout ASIC for an APD based 2D X-ray hybrid pixel detector with sub-nanosecond resolution

International Nuclear Information System (INIS)

Thil, Ch.; Baron, A.Q.R.; Fajardo, P.; Fischer, P.; Graafsma, H.; Rueffer, R.

2011-01-01

The fast response and the short recovery time of avalanche photodiodes (APDs) in linear mode make those devices ideal for direct X-ray detection in applications requiring high time resolution or counting rate. In order to provide position sensitivity, the XNAP project aims at creating a hybrid pixel detector with nanosecond time resolution based on a monolithic APD sensor array with 32 x32 pixels covering about 1 cm 2 active area. The readout is implemented in a pixelated front-end ASIC suited for the readout of such arrays, matched to pixels of 280μmx280μm size. Every single channel features a fast transimpedance amplifier, a discriminator with locally adjustable threshold and two counters with high dynamic range and counting speed able to accumulate X-ray hits with no readout dead time. Additionally, the detector can be operated in list mode by time-stamping every single event with sub-nanosecond resolution. In a first phase of the project, a 4x4 pixel test module is built to validate the conceptual design of the detector. The XNAP project is briefly presented and the performance of the readout ASIC is discussed.

NINO an ultrafast low-power front-end amplifier discriminator for the time-of-flight detector in the ALICE experiment

CERN Document Server

Anghinolfi, F; Krummenacher, F; Usenko, E; Williams, M C S

2004-01-01

An ultrafast front-end preamplifier-discriminator chip called NINO has been developed for use in the ALICE time-of-flight detector. The chip has eight channels. Each channel is designed with an amplifier with less than 1-ns peaking time, a discriminator with a minimum detection threshold of 10 fC and an output stage. The output pulse has minimum time jitter (less than 25 ps) on the front edge, and the pulsewidth is dependent of the input signal charge. Each channel consumes 27 mW, and the eight channels fit in a 2*4 mm/sup 2/ ASIC processed in IBM 0.25- mu m CMOS technology. (3 refs).

NINO, an ultra-fast, low-power, front-end amplifier discriminator for the Time-Of-Flight detector in ALICE experiment

CERN Document Server

Anghinolfi, F; Krummenacher, F; Usenko, E; Williams, M C S

2004-01-01

An ultra fast front-end preamplifier-discriminator chip NINO has been developed for use in the ALICE Time-Of-Flight detector. The chip has 8 channels. Each channel is designed with an amplifier with less than 1 ns peaking time, a discriminator with a minimum detection threshold of 10fC and an output stage. The output pulse has minimum time jitter (less than 25ps) on the front edge, and the pulse width is dependent of the input signal charge. Each channel consumes 27mW, and the 8 channels fit in a 2*4mm/sup 2/ ASIC processed in IBM 0.2 mu m CMOS technology. (3 refs).

Abnormal Cardiac Autonomic Regulation in Mice Lacking ASIC3

Directory of Open Access Journals (Sweden)

Ching-Feng Cheng

2014-01-01

Full Text Available Integration of sympathetic and parasympathetic outflow is essential in maintaining normal cardiac autonomic function. Recent studies demonstrate that acid-sensing ion channel 3 (ASIC3 is a sensitive acid sensor for cardiac ischemia and prolonged mild acidification can open ASIC3 and evoke a sustained inward current that fires action potentials in cardiac sensory neurons. However, the physiological role of ASIC3 in cardiac autonomic regulation is not known. In this study, we elucidate the role of ASIC3 in cardiac autonomic function using Asic3−/− mice. Asic3−/− mice showed normal baseline heart rate and lower blood pressure as compared with their wild-type littermates. Heart rate variability analyses revealed imbalanced autonomic regulation, with decreased sympathetic function. Furthermore, Asic3−/− mice demonstrated a blunted response to isoproterenol-induced cardiac tachycardia and prolonged duration to recover to baseline heart rate. Moreover, quantitative RT-PCR analysis of gene expression in sensory ganglia and heart revealed that no gene compensation for muscarinic acetylcholines receptors and beta-adrenalin receptors were found in Asic3−/− mice. In summary, we unraveled an important role of ASIC3 in regulating cardiac autonomic function, whereby loss of ASIC3 alters the normal physiological response to ischemic stimuli, which reveals new implications for therapy in autonomic nervous system-related cardiovascular diseases.

Acid-sensing ion channels (ASICs) in the taste buds of adult zebrafish.

Science.gov (United States)

Viña, E; Parisi, V; Cabo, R; Laurà, R; López-Velasco, S; López-Muñiz, A; García-Suárez, O; Germanà, A; Vega, J A

2013-03-01

In detecting chemical properties of food, different molecules and ion channels are involved including members of the acid-sensing ion channels (ASICs) family. Consistently ASICs are present in sensory cells of taste buds of mammals. In the present study the presence of ASICs (ASIC1, ASIC2, ASIC3 and ASIC4) was investigated in the taste buds of adult zebrafish (zASICs) using Western blot and immunohistochemistry. zASIC1 and zASIC3 were regularly absent from taste buds, whereas faint zASIC2 and robust zASIC4 immunoreactivities were detected in sensory cells. Moreover, zASIC2 also immunolabelled nerves supplying taste buds. The present results demonstrate for the first time the presence of zASICs in taste buds of teleosts, with different patterns to that occurring in mammals, probably due to the function of taste buds in aquatic environment and feeding. Nevertheless, the role of zASICs in taste remains to be demonstrated. Copyright © 2013 Elsevier Ireland Ltd. All rights reserved.

ASIC1A in neurons is critical for fear-related behaviors.

Science.gov (United States)

Taugher, R J; Lu, Y; Fan, R; Ghobbeh, A; Kreple, C J; Faraci, F M; Wemmie, J A

2017-11-01

Acid-sensing ion channels (ASICs) have been implicated in fear-, addiction- and depression-related behaviors in mice. While these effects have been attributed to ASIC1A in neurons, it has been reported that ASICs may also function in nonneuronal cells. To determine if ASIC1A in neurons is indeed required, we generated neuron-specific knockout (KO) mice with floxed Asic1a alleles disrupted by Cre recombinase driven by the neuron-specific synapsin I promoter (SynAsic1a KO mice). We confirmed that Cre expression occurred in neurons, but not all neurons, and not in nonneuronal cells including astrocytes. Consequent loss of ASIC1A in some but not all neurons was verified by western blotting, immunohistochemistry and electrophysiology. We found ASIC1A was disrupted in fear circuit neurons, and SynAsic1a KO mice exhibited prominent deficits in multiple fear-related behaviors including Pavlovian fear conditioning to cue and context, predator odor-evoked freezing and freezing responses to carbon dioxide inhalation. In contrast, in the nucleus accumbens ASIC1A expression was relatively normal in SynAsic1a KO mice, and consistent with this observation, cocaine conditioned place preference (CPP) was normal. Interestingly, depression-related behavior in the forced swim test, which has been previously linked to ASIC1A in the amygdala, was also normal. Together, these data suggest neurons are an important site of ASIC1A action in fear-related behaviors, whereas other behaviors likely depend on ASIC1A in other neurons or cell types not targeted in SynAsic1a KO mice. These findings highlight the need for further work to discern the roles of ASICs in specific cell types and brain sites. © 2017 John Wiley & Sons Ltd and International Behavioural and Neural Genetics Society.

Receiver ASIC for timing, trigger and control distribution in LHC experiments

International Nuclear Information System (INIS)

Christiansen, J.; Marchioro, A.; Moreira, P.; Sancho, A.

1996-01-01

An ASIC receiver has been developed for the optical timing, trigger and control distribution system for LHC detectors. It is capable of recovering the LHC reference clock and the first-level trigger decisions and making them available to the front-end electronics properly deskewed in time. The timing receiver is also capable of recognizing individually addressed commands to provide some slow control capability. Its main functions include post-amplification of the signal received from a photodetector-preamplifier, automatic gain control, data/clock separation, demultiplexing of the trigger and data channels and programmable coarse/fine deskewing functions. The design has been mapped into a standard 1microm CMOS process with all the analogue and timing critical functions implemented in full custom. The jitter measured on the recovered clock is less than 100 ps for input optical powers down to -25 dBm. The time deskewing functions allow the commands and the first level trigger accept signal to be phase shifted up to a maximum of sixteen clock cycles in steps of 0.1 ns

JACoW Design of the front-end detector control system of the ATLAS New Small Wheels

CERN Document Server

Moschovakos, Paris

2018-01-01

The ATLAS experiment will be upgraded during the next LHC Long Shutdown (LS2). The flagship upgrade is the New Small Wheel (NSW) [1], which consists of 2 disks of Muon Gas detectors. The detector technologies used are Micromegas (MM) and sTGC, providing a total of 16 layers of tracking and trigger. The Slow Control Adapter (SCA) is part of the Gigabit Transceiver (GBT) - “Radiation Hard Optical Link Project” family of chips designed at CERN, EP-ESE department [2,3], which will be used at the NSW upgrade. The SCA offers several interfaces to read analogue and digital inputs, and configure front-end Readout ASICs, FPGAs, or other chips. The design of the NSW Detector Control System (DCS) takes advantage of this functionality, as described in this paper.

Gain calibration of n-XYTER 1.0 - a prototype readout ASIC for the silicon tracking system of the CBM experiment

Energy Technology Data Exchange (ETDEWEB)

Sorokin, Iurii [Goethe Univ. Frankfurt am Main (Germany); Kiev Institute for Nuclear Research (Ukraine); Collaboration: CBM-Collaboration

2013-07-01

n-XYTER is a 128-channel readout ASIC which measures both the integral signal charge and the time of occurance. Due to its self-triggering design, high gain, high rate capability and bipolar front-end, the chip has found a use as a prototype readout for the Silicon Tracking System, Muon and Cherenkov detectors of the CBM experiment. It is also going to be applied in other projects in Darmstadt, Heidelberg and Dubna. To perform gain calibration of n-XYTER, reference charge pulses of a very small (down to 3000 e{sup -}), yet precisely known amplitude had to be generated. This was achieved by attenuating a voltage step to a sub-millivolt level and passing it through a tiny (1 pF) capacitor. Special care had to be taken to check for possible systematic errors in the measurements of the attenuation factor and of the coupling capacitance. In addition, the system had to be well shielded against RF pickup, the parasitic capacitances had to be minimized and ensured to stay invariable. Correct estimate of the systematic error was confirmed by performing a measurement with a different signal source - a planar silicon detector, exposed to γ-radiation of {sup 241}Am. Finally, the dominating error came from the channel-to-channel gain variation.

Front-end multiplexing—applied to SQUID multiplexing: Athena X-IFU and QUBIC experiments

Science.gov (United States)

Prele, D.

2015-08-01

As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device) will be described.

Front-end multiplexing—applied to SQUID multiplexing: Athena X-IFU and QUBIC experiments

International Nuclear Information System (INIS)

Prele, D.

2015-01-01

As we have seen for digital camera market and a sensor resolution increasing to 'megapixels', all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, 'simple' and 'efficient' techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device) will be described

SODR Memory Control Buffer Control ASIC

Science.gov (United States)

Hodson, Robert F.

1994-01-01

The Spacecraft Optical Disk Recorder (SODR) is a state of the art mass storage system for future NASA missions requiring high transmission rates and a large capacity storage system. This report covers the design and development of an SODR memory buffer control applications specific integrated circuit (ASIC). The memory buffer control ASIC has two primary functions: (1) buffering data to prevent loss of data during disk access times, (2) converting data formats from a high performance parallel interface format to a small computer systems interface format. Ten 144 p in, 50 MHz CMOS ASIC's were designed, fabricated and tested to implement the memory buffer control function.

Design of a wideband CMOS impedance spectroscopy ASIC analog front-end for multichannel biosensor interfaces.

Science.gov (United States)

Valente, Virgilio; Dai Jiang; Demosthenous, Andreas

2015-08-01

This paper presents the preliminary design and simulation of a flexible and programmable analog front-end (AFE) circuit with current and voltage readout capabilities for electric impedance spectroscopy (EIS). The AFE is part of a fully integrated multifrequency EIS platform. The current readout comprises of a transimpedance stage and an automatic gain control (AGC) unit designed to accommodate impedance changes larger than 3 order of magnitude. The AGC is based on a dynamic peak detector that tracks changes in the input current over time and regulates the gain of a programmable gain amplifier in order to optimise the signal-to-noise ratio. The system works up to 1 MHz. The voltage readout consists of a 2 stages of fully differential current-feedback instrumentation amplifier which provide 100 dB of CMRR and a programmable gain up to 20 V/V per stage with a bandwidth in excess of 10MHz.

Dedicated multichannel readout ASIC coupled with single crystal diamond for dosimeter application

International Nuclear Information System (INIS)

Fabbri, A; Notaristefani, F De; Galasso, M; Cencelli, V Orsolini; Falco, M D; Marinelli, M; Tortora, L; Verona, C; Rinati, G Verona

2013-01-01

This paper reports on the tests of a low-noise, multi-channel readout integrated circuit used as a readout electronic front-end for a diamond multi-pixel dosimeter. The system is developed for dose distribution measurement in radiotherapy applications. The first 10-channel prototype chip was designed and fabricated in a 0.18 um CMOS process. Every channel includes a charge integrator with a 10 pF capacitor and a double slope A/D converter. The diamond multi-pixel detector, based on CVD synthetic single crystal diamond Schottky diodes, is made by a 3 × 3 sensor matrix. The overall device has been tested under irradiation with 6 MeV radio therapeutic photon beams at the Policlinico ''Tor Vergata'' (PTV) hospital. Measurements show a 20 fA RMS leakage current from the front-end input stage and a negligible dark current from the diamond detector, a stable temporal response and a good linear behaviour as a function of both dose and dose rate. These characteristics were common to each tested channel.

SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

CERN Document Server

Bouchel, Michel; Dulucq, Frédéric; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

2009-01-01

The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

CERN Document Server

Bouchel, Michel; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

2007-01-01

The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

CERN Document Server

Pacher, L.; Demaria, N.; Rivetti, A.; Da Rocha Rolo, M.; Dellacasa, G.; Mazza, G.; Rotondo, F.; Wheadon, R.; Paternò, A.; Panati, S.; Loddo, F.; Licciulli, F.; Ciciriello, F.; Marzocca, C.; Gaioni, L.; Traversi, G.; Re, V.; De Canio, F.; Ratti, L.; Marconi, S.; Placidi, P.; Magazzù, G.; Stabile, A.; Mattiazzo, S.

2018-01-01

A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 × 64 pixels with 50 μm × 50 μm pixel size embedding two different architectures of analog front-ends working in parallel. The final layout of the chip was submitted and accepted for fabrication on July 2016. Chips were received back from the foundry on October 2016 and successfully characterized before irradiation. Several irra- diation campaigns with X-rays have been accomplished during 2017 at Padova INFN and CERN EP/ESE facilities under different uniformity and temperature conditions up to 630 Mrad Total Ionizing Dose (TID). These studies corfirmed negligible degradation of analog front-ends per- formance after irradiation. First sample chips have been also bump-bonded to 50 μm × 50 μm and sin...

Three-dimensional stacked structured ASIC devices and methods of fabrication thereof

Science.gov (United States)

Shinde, Subhash L.; Teifel, John; Flores, Richard S.; Jarecki Jr., Robert L.; Bauer, Todd

2015-11-19

A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.

Evidence for the involvement of ASIC3 in sensory mechanotransduction in proprioceptors

Science.gov (United States)

Lin, Shing-Hong; Cheng, Yuan-Ren; Banks, Robert W.; Min, Ming-Yuan; Bewick, Guy S.; Chen, Chih-Cheng

2016-01-01

Acid-sensing ion channel 3 (ASIC3) is involved in acid nociception, but its possible role in neurosensory mechanotransduction is disputed. We report here the generation of Asic3-knockout/eGFPf-knockin mice and subsequent characterization of heterogeneous expression of ASIC3 in the dorsal root ganglion (DRG). ASIC3 is expressed in parvalbumin (Pv+) proprioceptor axons innervating muscle spindles. We further generate a floxed allele of Asic3 (Asic3f/f) and probe the role of ASIC3 in mechanotransduction in neurite-bearing Pv+ DRG neurons through localized elastic matrix movements and electrophysiology. Targeted knockout of Asic3 disrupts spindle afferent sensitivity to dynamic stimuli and impairs mechanotransduction in Pv+ DRG neurons because of substrate deformation-induced neurite stretching, but not to direct neurite indentation. In behavioural tasks, global knockout (Asic3−/−) and Pv-Cre::Asic3f/f mice produce similar deficits in grid and balance beam walking tasks. We conclude that, at least in mouse, ASIC3 is a molecular determinant contributing to dynamic mechanosensitivity in proprioceptors. PMID:27161260

The PASTA chip. A free-running readout ASIC for silicon strip sensors in PANDA

Energy Technology Data Exchange (ETDEWEB)

Goerres, Andre; Stockmanns, Tobias; Ritman, James [Forschungszentrum Juelich GmbH, Juelich (Germany); Rivetti, Angelo [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

2015-07-01

The PANDA experiment is a multi purpose detector, investigating hadron physics in the charm quark mass regime. It is one of the main experiments at the future FAIR accelerator facility, using anti pp annihilations from a 1.5-15 GeV/c anti-proton beam. Because of the broad physics spectrum and the similarity of event and background signals, PANDA does an event selection based on the complete raw data of the detector. The innermost of PANDA's sub-systems is the Micro Vertex Detector (MVD), consisting of silicon pixel and strip sensors. The latter will be read out by a specialized, free-running readout front-end called PANDA Strip ASIC (PASTA). It has to face a high event rate of up to 40 kHz/ch in an radiation-intense environment. To fulfill the MVD's requirements, it has to give accurate timing information to incoming events (<10 ns) and determine the collected charge with an 8-bit precision. All this has to be done with a very low power design (<4 mW/ch) on a small footprint with less than 21 mm{sup 2} and 60 μm input pitch for 64 channels per chip. Therefore, a simple, time-based readout approach with two independent thresholds is chosen. In this talk, the conceptual design of the full front-end and some aspects of the digital part are presented.

CASAGEM: a readout ASIC for micro pattern gas detectors

International Nuclear Information System (INIS)

He Li; Deng Zhi; Liu Yinong

2012-01-01

A readout ASIC for micro pattern gas detectors has been designed This ASIC integrates 16 channels for anode readout and 1 channel for cathode readout which can make use of the signal of detector's cathode to generate a trigger Every channel can provide amplification and shaping of detector signals. The ASIC can also provide adjustable gain which can be adjusted from 2 mV/fC to 40 mV/fC, and adjustable shaping time which can be adjusted from 20 ns to 80 ns; so this ASIC can be applied to detectors with wide range output signal and different counting rate. The ASIC is fabricated with Chartered 0.35 μm CMOS process More circuit design Details and test results will be presented. (authors)

Frontend and Backend Electronics for the ATLAS New Small Wheel Upgrade

CERN Document Server

Martinez Outschoorn, Verena; The ATLAS collaboration

2016-01-01

The Phase-I and Phase-II upgrades of the LHC accelerator will increase the LHC instantaneous luminosity to 2×1034 cm-2s-1 and 7.5×1034 cm-2s-1, respectively. The luminosity increase drastically impacts the ATLAS trigger and readout data rates. The present ATLAS small wheel muon detector will be replaced with a New Small Wheel (NSW) detector in 2019. The NSW will feature two new detector technologies, Resistive Micromegas (MM) and small strip Thin Gap Chambers (sTGC) conforming a system of ~2.4 million readout channels. Both detectors will be used for muon triggering and precision tracking. A common readout path and two separate trigger paths are developed for these two detector technologies. The frontend electronics will be implemented in about 8000 boards including the design of 4 custom ASICs capable of driving trigger and tracking primitives to the backend trigger processor and readout system. The readout data flow is designed through a high-throughput network approach. The large number of readout channe...

Front-end counting mode electronics for CdZnTe sensor readout

CERN Document Server

Moraes, Danielle; Kaplon, Jan

2004-01-01

The development of a front-end circuit optimized for CdZnTe detector readout, implemented in 0.25 mu m CMOS technology, is reported. The ASIC comprises 17 channels of a charge sensitive amplifier with an active feedback, followed by a gain-shaper stage and a discriminator with a 5 bit fine-tune DAC. The signal from the discriminator is sensed by a 25 ns mono-stable circuit and an 18-bit static ripple- counter. The channel architecture is optimized for the detector characteristics in order to achieve the best energy resolution at a maximum counting rate of 2 million counts/second. The amplifier shows a linear sensitivity of 24 mV/fC with 50 ns peaking time and an equivalent noise charge of about 650 e/sup -/, for a detector capacitance of 10 pF. When connected to a 3*3*7 mm/sup 3/ CdZnTe detector the amplifier gain is about 8 mV/keV with a noise around 3.6 keV.

Readout ASIC of pair-monitor for international linear collider

International Nuclear Information System (INIS)

Sato, Yutaro; Ikeda, Hirokazu; Ito, Kazutoshi; Miyamoto, Akiya; Nagamine, Tadashi; Sasaki, Rei; Takubo, Yosuke; Tauchi, Toshiaki; Yamamoto, Hitoshi

2010-01-01

The pair-monitor is a beam profile monitor at the interaction point of the international linear collider. A prototype of the readout ASIC for the pair-monitor has been designed and tested. Since the pair-monitor uses the hit distribution of electrons and positrons generated by the beam-crossing to measure the beam profile, the readout ASIC is designed to count the number of hits. In a prototype ASIC, 36 readout cells were implemented by TSMC 0.25-μm CMOS process. Each readout cell is equipped with an amplifier, comparator, 8-bit counter and 16 count-registers. By the operation test, all the ASIC component were confirmed to work correctly. As the next step, we develop the prototype ASIC with the silicon on insulator technology. It is produced with OKI 0.2-μm FD-SOI CMOS process.

Burst Mode ASIC-Based Modem

Science.gov (United States)

1997-01-01

The NASA Lewis Research Center is sponsoring the Advanced Communication Technology Insertion (ACTION) for Commercial Space Applications program. The goal of the program is to expedite the development of new technology with a clear path towards productization and enhancing the competitiveness of U.S. manufacturers. The industry has made significant investment in developing ASIC-based modem technology for continuous-mode applications and has made investigations into East, reliable acquisition of burst-mode digital communication signals. With rapid advances in analog and digital communications ICs, it is expected that more functions will be integrated onto these parts in the near future. In addition custom ASIC's can also be developed to address the areas not covered by the other IC's. Using the commercial chips and custom ASIC's, lower-cost, compact, reliable, and high-performance modems can be built for demanding satellite communication application. This report outlines a frequency-hop burst modem design based on commercially available chips.

Readout architecture for the Pixel-Strip module of the CMS Outer Tracker Phase-2 upgrade

CERN Document Server

Caratelli, Alessandro; Jan Kaplon; Kloukinas, Konstantinos; Simone Scarfi

2017-01-01

The Outer Tracker upgrade of the Compact Muon Solenoid (CMS) experiment at CERN introduces new challenges for the front-end readout electronics. In particular, the capability of identifying particles with high transverse momentum using modules with double sensor layers requires high speed real time interconnects between readout ASICs. The Pixel-Strip module combines a pixelated silicon layer with a silicon-strip layer. Consequently, it needs two different readout ASICs, namely the Short Strip ASIC (SSA) for the strip sensor and the Macro Pixel ASIC (MPA) for the pixelated sensor. The architecture proposed in this paper allows for a total data flow between readout ASICs of $\\sim$100\\,Gbps and reduces the output data flow from 1.3\\,Tbps to 30\\,Gbps per module while limiting the total power density to below 100\\,mW/cm$^2$. In addition a system-level simulation framework of all the front-end readout ASICs is developed in order to verify the data processing algorithm and the hardware implementation allowing mult...

Hsc70 regulates cell surface ASIC2 expression and vascular smooth muscle cell migration.

Science.gov (United States)

Grifoni, Samira C; McKey, Susan E; Drummond, Heather A

2008-05-01

Recent studies suggest members of the degenerin (DEG)/epithelial Na(+) channel (ENaC)/acid-sensing ion channel (ASIC) protein family play an important role in vascular smooth muscle cell (VSMC) migration. In a previous investigation, we found suppression of a certain DEG/ENaC/ASIC member, ASIC2, increased VSMC chemotactic migration, raising the possibility that ASIC2 may play an inhibitory role. Because ASIC2 protein was retained in the cytoplasm, we reasoned increasing surface expression of ASIC2 might unmask the inhibitory role of ASIC2 in VSMC migration so we could test the hypothesis that ASIC2 inhibits VSMC migration. Therefore, we used the chemical chaperone glycerol to enhance ASIC2 expression. Glycerol 1) increased cytoplasm ASIC2 expression, 2) permitted detection of ASIC2 at the cell surface, and 3) inhibited platelet-derived growth factor (PDGF)-bb mediated VSMC migration. Furthermore, ASIC2 silencing completely abolished the inhibitory effect of glycerol on migration, suggesting upregulation of ASIC2 is responsible for glycerol-induced inhibition of VSMC migration. Because other investigators have shown that glycerol regulates ENaC/ASIC via interactions with a certain heat shock protein, heat shock protein 70 (Hsc70), we wanted to determine the importance of Hsc70 on ASIC2 expression in VSMCs. We found that Hsc70 silencing increases ASIC2 cell surface expression and inhibits VSMC migration, which is abolished by cosilencing ASIC2. These data demonstrate that Hsc70 inhibits ASIC2 expression, and, when the inhibitory effect of Hsc70 is removed, ASIC2 expression increases, resulting in reduced VSMC migration. Because VSMC migration contributes to vasculogenesis and remodeling following vascular injury, our findings raise the possibility that ASIC2-Hsc70 interactions may play a role in these processes.

A distributed current stimulator ASIC for high density neural stimulation.

Science.gov (United States)

Jeong Hoan Park; Chaebin Kim; Seung-Hee Ahn; Tae Mok Gwon; Joonsoo Jeong; Sang Beom Jun; Sung June Kim

2016-08-01

This paper presents a novel distributed neural stimulator scheme. Instead of a single stimulator ASIC in the package, multiple ASICs are embedded at each electrode site for stimulation with a high density electrode array. This distributed architecture enables the simplification of wiring between electrodes and stimulator ASIC that otherwise could become too complex as the number of electrode increases. The individual ASIC chip is designed to have a shared data bus that independently controls multiple stimulating channels. Therefore, the number of metal lines is determined by the distributed ASICs, not by the channel number. The function of current steering is also implemented within each ASIC in order to increase the effective number of channels via pseudo channel stimulation. Therefore, the chip area can be used more efficiently. The designed chip was fabricated with area of 0.3 mm2 using 0.18 μm BCDMOS process, and the bench-top test was also conducted to validate chip performance.

Characterization of a DAQ system for the readout of a SiPM based shashlik calorimeter

International Nuclear Information System (INIS)

Berra, A.; Bonvicini, V.; Bosisio, L.; Lietti, D.; Penzo, A.; Prest, M.; Rabaioli, S.; Rashevskaya, I.; Vallazza, E.

2014-01-01

Silicon PhotoMultipliers (SiPMs) are a recently developed type of silicon photodetector characterized by high gain and insensitivity to magnetic fields, which make them a suitable detector for the next generation high energy and space physics experiments. This paper presents the performance of a readout system for SiPMs based on the MAROC3 ASIC. The ASIC consists of 64 channels working in parallel, each one with a variable gain pre-amplifier, a tunable slow shaper with a sample and hold circuit for the analog readout and a tunable fast shaper for the digital one. In the tests described in this paper, only the analog part of the ASIC has been used. A frontend board based on the MAROC3 ASIC has been tested at CERN coupled to a scintillator-lead shashlik calorimeter, readout with 36 large area SiPMs. The performance of the system has been characterized in terms of linearity and energy resolution on the CERN PS-T9 and SPS-H2 beamlines, using different configurations of the ASIC parameters

Design and characterization of a 64 channels ASIC front-end electronics for high-flux particle beam detectors

Science.gov (United States)

Fausti, F.; Mazza, G.; Attili, A.; Mazinani, M. Fadavi; Giordanengo, S.; Lavagno, M.; Manganaro, L.; Marchetto, F.; Monaco, V.; Sacchi, R.; Vignati, A.; Cirio, R.

2017-09-01

A new wide-input range 64-channels current-to-frequency converter ASIC has been developed and characterized for applications in beam monitoring of therapeutic particle beams. This chip, named TERA09, has been designed to extend the input current range, compared to the previous versions of the chip, for dealing with high-flux pulsed beams. A particular care was devoted in achieving a good conversion linearity over a wide bipolar input current range. Using a charge quantum of 200 fC, a linearity within ±2% for an input current range between 3 nA and 12 μA is obtained for individual channels, with a gain spread among the channels of about 3%. By connecting all the 64 channels of the chip to a common input, the current range can be increased 64 times preserving a linearity within ±3% in the range between and 20 μA and 750 μA.

2nd generation ASICs for CALICE/EUDET calorimeters

International Nuclear Information System (INIS)

Dulucq, F; Fleury, J; La Taille, C de; Martin-Chassard, G; Raux, L; Seguin-Moreau, N

2009-01-01

Imaging calorimetry depends heavily on the development of high performance, highly integrated readout ASICs embedded inside the detector which readout the millions of foreseen channels. Suitable ASICs prototypes have been fabricated in 2006-2007 and show good preliminary performance.

DAQ system for testing RPC front-end electronics of the INO experiment

International Nuclear Information System (INIS)

Hari Prasad, K.; Sukhwani, Menka; Kesarkar, Tushar A.; Kumar, Sandeep; Chandratre, V.B.; Das, D.; Shinde, R.R.; Satyanarayana, B.

2015-01-01

The Resistive Plate Chamber (RPC) is the active detector element in the INO experiment. The in-house developed ANUSPARSH-III ASICs are being used as front-end electronics of the detector. The 2 m X 2 m RPC being used has 64-readout channels on X-side and 64-readout channels on Y-side. In order to test and validate the FE along with the RPC, a 64-channel DAQ system has been designed and developed. The detector parameters to be measured are noise rate, efficiency, hit pattern register and time resolution. The salient features of the DAQ system are: 64-channel LVDS receiver in FPGA, FPGA based parameter calculations and a micro controller for acquiring the processed data from FPGAs and sent through Ethernet and USB interfaces. The DAQ system consists of following parts: Two FPGAs each receiving 32 LVDS channels, FPGA firm-ware, micro controller firm-ware, Ethernet interface, embedded web server hosting data analysis software, USB interface, and Lab-windows based data analysis software. The DAQ system has been tested at TIFR with 1 m X 1 m RPC

ASIC design used in high energy physics experiments

International Nuclear Information System (INIS)

Zhang Hongyu; Lin Tao; Wu Ling; Zhao jingwei; Gu Shudi

1997-01-01

The author introduces an ASIC (Application Specific Integrated Circuit) design environment based on PC. Some design tools used in such environment are also introduced. A kind of ASIC chip used in high energy physics experiment, weighting mean timer, is being developed now

Design and prototyping of a readout aggregation ASIC

Energy Technology Data Exchange (ETDEWEB)

Lemke, Frank; Schatral, Sven; Bruening, Ulrich [ZITI, Universitaet Heidelberg (Germany); Som, Indranil; Bhattacharyya, Tarun [Indian Institute of Technology, Kharagpur (India); Collaboration: CBM-Collaboration

2015-07-01

In close collaboration between the Indian Institute of Technology Kharagpur (IITKGP) and the Institute for Computer Engineering (ZITI) at the University of Heidelberg a readout aggregation ASIC was designed. This happened in the context of the Compressed Baryonic Matter (CBM) experiment at the Facility for Antiproton and Ion Research (FAIR). The ASIC is designed in 65nm TSMC technology. Its miniASIC tapeout to verify the analog and high-speed components is scheduled to the first quarter of 2015. This mixed-signal ASIC consists of a full-custom 5Gb/s serializer/deserializer, designed by the IITKGP including design elements such as phase-locked loop, bandgap reference, and clock data recovery, and a digital designed network communication and aggregation part designed by the ZITI. In addition, there are test structures and an I2C readout integrated to ease bring up and monitoring. A specialty of this test ASIC is the aggregation of links featuring different data rates, running with bundles of 500 MB/s LVDS. This enables flexible readout setups of mixed detectors respectively readout of various chips. As communication protocol, a unified link protocol is used including control messages, data messages, and synchronization messages on an identical lane. The design has been simulated, verified, and hardware emulated using Spartan 6 FPGAs.

Architecture of a general purpose embedded Slow-Control Adapter ASIC for future high-energy physics experiments

International Nuclear Information System (INIS)

Gabrielli, Alessandro; Loddo, Flavio; Ranieri, Antonio; De Robertis, Giuseppe

2008-01-01

This work is aimed at defining the architecture of a new digital ASIC, namely Slow-Control Adapter (SCA), which will be designed in a commercial 130-nm CMOS technology. This chip will be embedded within a high-speed data acquisition optical link (GBT) to control and monitor the front-end electronics in future high-energy physics experiments. The GBT link provides a transparent transport layer between the SCA and control electronics in the counting room. The proposed SCA supports a variety of common bus protocols to interface with end-user general-purpose electronics. Between the GBT and the SCA a standard 100 Mb/s IEEE-802.3 compatible protocol will be implemented. This standard protocol allows off-line tests of the prototypes using commercial components that support the same standard. The project is justified because embedded applications in modern large HEP experiments require particular care to assure the lowest possible power consumption, still offering the highest reliability demanded by very large particle detectors.

Architecture of a general purpose embedded Slow-Control Adapter ASIC for future high-energy physics experiments

Science.gov (United States)

Gabrielli, Alessandro; Loddo, Flavio; Ranieri, Antonio; De Robertis, Giuseppe

2008-10-01

This work is aimed at defining the architecture of a new digital ASIC, namely Slow-Control Adapter (SCA), which will be designed in a commercial 130-nm CMOS technology. This chip will be embedded within a high-speed data acquisition optical link (GBT) to control and monitor the front-end electronics in future high-energy physics experiments. The GBT link provides a transparent transport layer between the SCA and control electronics in the counting room. The proposed SCA supports a variety of common bus protocols to interface with end-user general-purpose electronics. Between the GBT and the SCA a standard 100 Mb/s IEEE-802.3 compatible protocol will be implemented. This standard protocol allows off-line tests of the prototypes using commercial components that support the same standard. The project is justified because embedded applications in modern large HEP experiments require particular care to assure the lowest possible power consumption, still offering the highest reliability demanded by very large particle detectors.

An SEU analysis approach for error propagation in digital VLSI CMOS ASICs

International Nuclear Information System (INIS)

Baze, M.P.; Bartholet, W.G.; Dao, T.A.; Buchner, S.

1995-01-01

A critical issue in the development of ASIC designs is the ability to achieve first pass fabrication success. Unsuccessful fabrication runs have serious impact on ASIC costs and schedules. The ability to predict an ASICs radiation response prior to fabrication is therefore a key issue when designing ASICs for military and aerospace systems. This paper describes an analysis approach for calculating static bit error propagation in synchronous VLSI CMOS circuits developed as an aid for predicting the SEU response of ASIC's. The technique is intended for eventual application as an ASIC development simulation tool which can be used by circuit design engineers for performance evaluation during the pre-fabrication design process in much the same way that logic and timing simulators are used

Development of high-resolution detector module with depth of interaction identification for positron emission tomography

International Nuclear Information System (INIS)

Niknejad, Tahereh; Pizzichemi, Marco; Stringhini, Gianluca; Auffray, Etiennette; Bugalho, Ricardo; Da Silva, Jose Carlos; Di Francesco, Agostino; Ferramacho, Luis; Lecoq, Paul; Leong, Carlos; Paganoni, Marco; Rolo, Manuel; Silva, Rui; Silveira, Miguel; Tavernier, Stefaan; Varela, Joao; Zorraquino, Carlos

2017-01-01

We have developed a Time-of-flight high resolution and commercially viable detector module for the application in small PET scanners. A new approach to depth of interaction (DOI) encoding with low complexity for a pixelated crystal array using a single side readout and 4-to-1 coupling between scintillators and photodetectors was investigated. In this method the DOI information is estimated using the light sharing technique. The detector module is a 1.53×1.53×15 mm"3 matrix of 8×8 LYSO scintillator with lateral surfaces optically depolished separated by reflective foils. The crystal array is optically coupled to 4×4 silicon photomultipliers (SiPM) array and readout by a high performance front-end ASIC with TDC capability (50 ps time binning). The results show an excellent crystal identification for all the scintillators in the matrix, a timing resolution of 530 ps, an average DOI resolution of 5.17 mm FWHM and an average energy resolution of 18.29% FWHM. - Highlights: • A new method for DOI encoding for PET detectors based on light sharing is proposed. • A prototype module with LYSO scintillator matrix coupled to SiPMs array is produced. • The module has one side readout and 4-to-1 coupling between scintillators and SiPMs. • A compact TOF front-end ASIC is used. • Excellent performances are shown by the prototype module.

Development of high-resolution detector module with depth of interaction identification for positron emission tomography

Energy Technology Data Exchange (ETDEWEB)

Niknejad, Tahereh, E-mail: tniknejad@lip.pt [Laboratory of Instrumentation and Experimental Particles Physics, Lisbon (Portugal); Pizzichemi, Marco [University of Milano-Bicocca (Italy); Stringhini, Gianluca [University of Milano-Bicocca (Italy); CERN, Geneve (Switzerland); Auffray, Etiennette [CERN, Geneve (Switzerland); Bugalho, Ricardo; Da Silva, Jose Carlos; Di Francesco, Agostino [Laboratory of Instrumentation and Experimental Particles Physics, Lisbon (Portugal); Ferramacho, Luis [PETsys Electronics, Oeiras (Portugal); Lecoq, Paul [CERN, Geneve (Switzerland); Leong, Carlos [PETsys Electronics, Oeiras (Portugal); Paganoni, Marco [University of Milano-Bicocca (Italy); Rolo, Manuel [Laboratory of Instrumentation and Experimental Particles Physics, Lisbon (Portugal); INFN, Turin (Italy); Silva, Rui [Laboratory of Instrumentation and Experimental Particles Physics, Lisbon (Portugal); Silveira, Miguel [PETsys Electronics, Oeiras (Portugal); Tavernier, Stefaan [PETsys Electronics, Oeiras (Portugal); Vrije Universiteit Brussel (Belgium); Varela, Joao [Laboratory of Instrumentation and Experimental Particles Physics, Lisbon (Portugal); CERN, Geneve (Switzerland); Zorraquino, Carlos [Biomedical Image Technologies Lab, Universidad Politécnica de Madrid (Spain); CIBER-BBN, Universidad Politécnica de Madrid (Spain)

2017-02-11

We have developed a Time-of-flight high resolution and commercially viable detector module for the application in small PET scanners. A new approach to depth of interaction (DOI) encoding with low complexity for a pixelated crystal array using a single side readout and 4-to-1 coupling between scintillators and photodetectors was investigated. In this method the DOI information is estimated using the light sharing technique. The detector module is a 1.53×1.53×15 mm{sup 3} matrix of 8×8 LYSO scintillator with lateral surfaces optically depolished separated by reflective foils. The crystal array is optically coupled to 4×4 silicon photomultipliers (SiPM) array and readout by a high performance front-end ASIC with TDC capability (50 ps time binning). The results show an excellent crystal identification for all the scintillators in the matrix, a timing resolution of 530 ps, an average DOI resolution of 5.17 mm FWHM and an average energy resolution of 18.29% FWHM. - Highlights: • A new method for DOI encoding for PET detectors based on light sharing is proposed. • A prototype module with LYSO scintillator matrix coupled to SiPMs array is produced. • The module has one side readout and 4-to-1 coupling between scintillators and SiPMs. • A compact TOF front-end ASIC is used. • Excellent performances are shown by the prototype module.

A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

Science.gov (United States)

Quilligan, G.; Aslam, S.; DuMonthier, J.

2012-01-01

A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

Two Aspects of ASIC Function: Synaptic Plasticity and Neuronal Injury.

Science.gov (United States)

Huang, Yan; Jiang, Nan; Li, Jun; Ji, Yong-Hua; Xiong, Zhi-Gang; Zha, Xiang-ming

2015-01-01

Extracellular brain pH fluctuates in both physiological and disease conditions. The main postsynaptic proton receptor is the acid-sensing ion channels (ASICs). During the past decade, much progress has been made on protons, ASICs, and neurological disease. This review summarizes the recent progress on synaptic role of protons and our current understanding of how ASICs contribute to various types of neuronal injury in the brain. PMID:25582290

Distinct ASIC currents are expressed in rat putative nociceptors and are modulated by nerve injury.

Science.gov (United States)

Poirot, Olivier; Berta, Temugin; Decosterd, Isabelle; Kellenberger, Stephan

2006-10-01

The H(+)-gated acid-sensing ion channels (ASICs) are expressed in dorsal root ganglion (DRG) neurones. Studies with ASIC knockout mice indicated either a pro-nociceptive or a modulatory role of ASICs in pain sensation. We have investigated in freshly isolated rat DRG neurones whether neurones with different ASIC current properties exist, which may explain distinct cellular roles, and we have investigated ASIC regulation in an experimental model of neuropathic pain. Small-diameter DRG neurones expressed three different ASIC current types which were all preferentially expressed in putative nociceptors. Type 1 currents were mediated by ASIC1a homomultimers and characterized by steep pH dependence of current activation in the pH range 6.8-6.0. Type 3 currents were activated in a similar pH range as type 1, while type 2 currents were activated at pH ASIC current density. Nerve injury induced differential regulation of ASIC subunit expression and selective changes in ASIC function in DRG neurones, suggesting a complex reorganization of ASICs during the development of neuropathic pain. In summary, we describe a basis for distinct cellular functions of different ASIC types in small-diameter DRG neurones.

Acid-sensing ion channel (ASIC) 4 predominantly localizes to an early endosome-related organelle upon heterologous expression.

Science.gov (United States)

Schwartz, Verena; Friedrich, Katharina; Polleichtner, Georg; Gründer, Stefan

2015-12-15

Acid-sensing ion channels (ASICs) are voltage-independent proton-gated amiloride sensitive sodium channels, belonging to the DEG/ENaC gene family. Six different ASICs have been identified (ASIC1a, ASIC1b, ASIC2a, ASIC2b, ASIC3, ASIC4) that are activated by a drop in extracellular pH, either as homo- or heteromers. An exception is ASIC4, which is not activated by protons as a homomer and which does not contribute to functional heteromeric ASICs. Insensitivity of ASIC4 to protons and its comparatively low sequence identity to other ASICs (45%) raises the question whether ASIC4 may have different functions than other ASICs. In this study, we therefore investigated the subcellular localization of ASIC4 in heterologous cell lines, which revealed a surprising accumulation of the channel in early endosome-related vacuoles. Moreover, we identified an unique amino-terminal motif as important for forward-trafficking from the ER/Golgi to the early endosome-related compartment. Collectively, our results show that heterologously expressed ASIC4 predominantly resides in an intracellular endosomal compartment.

MMIC front-ends for optical communication systems

DEFF Research Database (Denmark)

Petersen, Anders Kongstad

1993-01-01

Two different types of optical front-end MMIC amplifiers for a 2.5-Gb/s coherent heterodyne optical receiver are presented. A bandwidth of 6-12 GHz has been obtained for a tuned front-end and 3-13 GHz for a distributed front-end. An input noise current density of 5-15 pA/√Hz has been obtained for...

Pilot tests of a PET detector using the TOF-PET ASIC based on monolithic crystals and SiPMs

International Nuclear Information System (INIS)

Aguilar, A.; González-Montoro, A.; González, A.J.; Hernández, L.; Monzó, J.M.; Benlloch, J.M.; Bugalho, R.; Ferramacho, L.

2016-01-01

In this work we show pilot tests of PET detector blocks using the TOF-PET ASIC, coupled to SiPM detector arrays and different crystal configurations. We have characterized the main ASIC features running calibration processes to compensate the time dispersion among the different ASIC/SiPM paths as well as for the time walk on the arrival of optical photons. The aim of this work is to use of LYSO monolithic crystals and explore their photon Depth of Interaction (DOI) capabilities, keeping good energy and spatial resolutions. First tests have been carried out with crystal arrays. Here we made it possible to reach a coincidence resolving times (CRT) of 370 ps FWHM, with energy resolutions better than 20% and resolving well 2 mm sized crystal elements. When using monolithic crystals, a single-pixel LYSO reference crystal helped to explore the CRT performance. We studied different strategies to provide the best timestamp determination in the monolithic scintillator. Times around 1 ns FWHM have been achieved in these pilot studies. In terms of spatial and energy resolution, values of about 3 mm and better than 30% were found, respectively. We have also demonstrated the capability of this system (monolithic and ASIC) to return accurate DOI information.

[Effect of Scalp-acupuncture Stimulation on Neurological Function and Expression of ASIC 1 a and ASIC 2 b of Hippocampal CA 1 Region in Cerebral Ischemia Rats].

Science.gov (United States)

Tian, Liang; Wang, Jin-Hai; Zhao, Min; Bao, Ying-Cun; Shang, Jun-Fang; Yan, Qi; Zhang, Zhen-Chang; Du, Xiao-Zheng; Jiang, Hua; Sun, Run-Jie; Yuan, Bo; Zhang, Xing-Hua; Zhang, Ting-Zhuo; Li, Xing-Lan

2016-10-25

To observe the influence of scalp-acupuncture on the expression of acid-sensing ion channels (ASICs) 1 a and 2 b of hippocampal CA 1 region in cerebral ischemia (CI) rats, so as to investigate its mechanism underlying improvement of ischemic stroke. Thirty-two male SD rats were randomly allocated to normal control, model, scalp-acupuncture and Amiloride group ( n =8 in each group). The model of focal CI was established by middle cerebral artery occlusion (MCAO). Scalp acupuncture stimulation was applied to bilateral Dingnieqianxiexian (MS 6) and Dingniehouxiexian (MS 7), once daily for 7 days. Rats of the Amiloride group were fed with Amiloride solution, twice a day for 7 days, and those of the normal control and model groups were grabbled and fixed in the same way with the acupuncture and Amiloride groups. The neurological deficit score was given according to Longa's method. The expression of hippocampal ASIC 1 a and ASIC 2 b was detected by immunohistochemistry, and the Ca 2+ concentration in the hippocampal tissue assayed using flowing cytometry. After the intervention, the neurological deficit score of both the scalp-acupuncture and Amiloride groups were significantly decreased in comparison with pre-treatment ( P ASIC 1 a and ASIC 2 b in the hippocampal CA 1 region and hip-pocampal Ca 2+ concentration were significantly up-regulated in the model group compared with the normal control group ( P ASIC 1 a and ASIC 2 b expression and Ca 2+ concentration ( P >0.05). Scalp-acupuncture stimulation can improve neurological function in CI rats, which may be related to its effects in suppressing the increased expression of hippocampal ASIC 1 a and ASIC 2 b proteins and in reducing calcium overload in hip-pocampal neurocytes.

Multi-channel Waveform Sampling ASIC for radiation detection and measurement

International Nuclear Information System (INIS)

Shimazoe, K.; Takahashi, H.; Yeom, J.Y.; Furumiya, T.; Ohi, J.

2013-01-01

We have designed and fabricated a 16-channel Waveform Sampling ASIC for radiation detection and measurement. Waveform sampling is very important for the pulse shape analysis and discrimination, which is often used in radiation detection to discriminate different radiations such as alpha, beta and gamma rays. One channel of the fabricated ASIC consists of a charge-sensitive preamplifier, a VGA (Variable Gain Amplifier), an ADC (Analog to Digital Converter) and digital circuits. The preamplifier converts the current signal to the voltage signal, and the VGA amplifies the signal to appropriate level for the ADC. The ADC was designed to digitize the waveform with a frequency of 100 MHz and a resolution of 6bits. Digital circuits consist of a free-running ADC and a multiplexer which were designed to convert a digitized 100 MHz/6bit signal to a 200 MHz/3bit one, which is effective for the reduction of the number and for the achievement of the high integration in one chip. This chip was designed and fabricated with 0.35 μm CMOS technology by ROHM and the size of the ASIC is 4.9 mm by 4.9 mm. The design concept and some experimental results are shown in this paper. -- Highlights: ► Waveform sampling (WS) ASIC is newly developed for pulse shape discrimination. ► WS ASIC can be used for radiation measurement and discrimination. ► WS ASIC is fabricated by submicron CMOS technology for 5 mm × 5 mm area. ► WS ASIC achieves high integration and can be used in very limited space

A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

Directory of Open Access Journals (Sweden)

Senkin Sergey

2018-01-01

Full Text Available The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC foreseen in 2024. We present here one of the frontend readout options, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. We describe the full characterisation of FATALIC and also the Optimal Filtering signal reconstruction method adapted to fully exploit the FATALIC three-range layout. Additionally we present the resolution performance of the whole chain measured using the charge injection system designed for calibration. Finally we discuss the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN.

A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

Science.gov (United States)

Senkin, Sergey

2018-01-01

The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC) foreseen in 2024. We present here one of the frontend readout options, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. We describe the full characterisation of FATALIC and also the Optimal Filtering signal reconstruction method adapted to fully exploit the FATALIC three-range layout. Additionally we present the resolution performance of the whole chain measured using the charge injection system designed for calibration. Finally we discuss the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN.

Studies of the performance of different front-end systems for flat-panel multi-anode PMTs with CsI(Tl) scintillator arrays

International Nuclear Information System (INIS)

Sekiya, H.; Hattori, K.; Kubo, H.; Miuchi, K.; Nagayoshi, T.; Nishimura, H.; Okada, Y.; Orito, R.; Takada, A.; Takeda, A.; Tanimori, T.; Ueno, K.

2006-01-01

We have studied the performance of two different types of front-end systems for our gamma camera based on Hamamatsu H8500 (flat-panel 64 channels multi-anode PSPMT) with a CsI(Tl) scintillator array. The array consists of 64 pixels of 6x6x20mm 3 which corresponds to the anode pixels of H8500. One of the system is based on commercial ASIC chips in order to read out every anode. The others are based on resistive charge divider network between anodes to reduce readout channels. In both systems, each pixel (6mm) was clearly resolved by flood field irradiation of 137 Cs. We also investigated the energy resolution of these systems and showed the performance of the cascade connection of resistive network between some PMTs for large area detectors

Proof of concept of an imaging system demonstrator for PET applications with SiPM

International Nuclear Information System (INIS)

Morrocchi, Matteo; Marcatili, Sara; Belcari, Nicola; Giuseppina Bisogni, Maria; Collazuol, Gianmaria; Ambrosi, Giovanni; Santoni, Cristiano; Corsi, Francesco; Foresta, Maurizio; Marzocca, Cristoforo; Matarrese, Gianvito; Sportelli, Giancarlo; Guerra, Pedro; Santos, Andres; Del Guerra, Alberto

2013-01-01

A PET imaging system demonstrator based on LYSO crystal arrays coupled to SiPM matrices is under construction at the University and INFN of Pisa. Two SiPM matrices, composed of 8×8 SiPM pixels, and 1,5 mm pitch, have been coupled one to one to a LYSO crystals array and read out by a custom electronics system. front-end ASICs were used to read 8 channels of each matrix. Data from each front-end were multiplexed and sent to a DAQ board for the digital conversion; a motherboard collects the data and communicates with a host computer through a USB port for the storage and off-line data processing. In this paper we show the first preliminary tomographic image of a point-like radioactive source acquired with part of the two detection heads in time coincidence

Proof of concept of an imaging system demonstrator for PET applications with SiPM

Energy Technology Data Exchange (ETDEWEB)

Morrocchi, Matteo, E-mail: matteo.morrocchi@pi.infn.it [University of Pisa and INFN Sezione di Pisa, Pisa 56127 (Italy); Marcatili, Sara; Belcari, Nicola; Giuseppina Bisogni, Maria [University of Pisa and INFN Sezione di Pisa, Pisa 56127 (Italy); Collazuol, Gianmaria [INFN Sezione di Pisa, Pisa 56127 (Italy); Ambrosi, Giovanni; Santoni, Cristiano [INFN Sezione di Perugia, Perugia 06100 (Italy); Corsi, Francesco; Foresta, Maurizio; Marzocca, Cristoforo; Matarrese, Gianvito [Politecnico di Bari and INFN Sezione di Bari, Bari 70100 (Italy); Sportelli, Giancarlo [University of Pisa and INFN Sezione di Pisa, Pisa 56127 (Italy); Guerra, Pedro; Santos, Andres [Universidad Politecnica de Madrid, E 28040 Madrid (Spain); Centro de Investigación Biomédica en Red en Bioingeniería, Biomateriales y Nanomedicina (CIBER-BBN) (Spain); Del Guerra, Alberto [University of Pisa and INFN Sezione di Pisa, Pisa 56127 (Italy)

2013-08-21

A PET imaging system demonstrator based on LYSO crystal arrays coupled to SiPM matrices is under construction at the University and INFN of Pisa. Two SiPM matrices, composed of 8×8 SiPM pixels, and 1,5 mm pitch, have been coupled one to one to a LYSO crystals array and read out by a custom electronics system. front-end ASICs were used to read 8 channels of each matrix. Data from each front-end were multiplexed and sent to a DAQ board for the digital conversion; a motherboard collects the data and communicates with a host computer through a USB port for the storage and off-line data processing. In this paper we show the first preliminary tomographic image of a point-like radioactive source acquired with part of the two detection heads in time coincidence.

A Stimulator ASIC Featuring Versatile Management for Vestibular Prostheses.

Science.gov (United States)

Dai Jiang; Demosthenous, Andreas; Perkins, Timothy; Xiao Liu; Donaldson, Nick

2011-04-01

This paper presents a multichannel stimulator ASIC for an implantable vestibular prosthesis. The system features versatile stimulation management which allows fine setting of the parameters for biphasic stimulation pulses. To address the problem of charge imbalance due to rounding errors, the digital processor can calculate and provide accurate charge correction. A technique to reduce the data rate to the stimulator is described. The stimulator ASIC was implemented in 0.6-μ m high-voltage CMOS technology occupying an area of 2.27 mm(2). The measured performance of the ASIC has been verified using vestibular electrodes in saline.

Advanced type 1 diabetes is associated with ASIC alterations in mouse lower thoracic dorsal root ganglia neurons.

Science.gov (United States)

Radu, Beatrice Mihaela; Dumitrescu, Diana Ionela; Marin, Adela; Banciu, Daniel Dumitru; Iancu, Adina Daniela; Selescu, Tudor; Radu, Mihai

2014-01-01

Acid-sensing ion channels (ASICs) from dorsal root ganglia (DRG) neurons are proton sensors during ischemia and inflammation. Little is known about their role in type 1 diabetes (T1D). Our study was focused on ASICs alterations determined by advanced T1D status. Primary neuronal cultures were obtained from lower (T9-T12) thoracic DRG neurons from Balb/c and TCR-HA(+/-)/Ins-HA(+/-) diabetic male mice (16 weeks of age). Patch-clamp recordings indicate a change in the number of small DRG neurons presenting different ASIC-type currents. Multiple molecular sites of ASICs are distinctly affected in T1D, probably due to particular steric constraints for glycans accessibility to the active site: (i) ASIC1 current inactivates faster, while ASIC2 is slower; (ii) PcTx1 partly reverts diabetes effects against ASIC1- and ASIC2-inactivations; (iii) APETx2 maintains unaltered potency against ASIC3 current amplitude, but slows ASIC3 inactivation. Immunofluorescence indicates opposite regulation of different ASIC transcripts while qRT-PCR shows that ASIC mRNA ranking (ASIC2 > ASIC1 > ASIC3) remains unaltered. In conclusion, our study has identified biochemical and biophysical ASIC changes in lower thoracic DRG neurons due to advanced T1D. As hypoalgesia is present in advanced T1D, ASICs alterations might be the cause or the consequence of diabetic insensate neuropathy.

A 1.2-V CMOS front-end for LTE direct conversion SAW-less receiver

International Nuclear Information System (INIS)

Wang Riyan; Li Zhengping; Zhang Weifeng; Zeng Longyue; Huang Jiwei

2012-01-01

A CMOS RF front-end for the long-term evolution (LTE) direct conversion receiver is presented. With a low noise transconductance amplifier (LNA), current commutating passive mixer and transimpedance operational amplifier (TIA), the RF front-end structure enables high-integration, high linearity and simple frequency planning for LTE multi-band applications. Large variable gain is achieved using current-steering transconductance stages. A current commutating passive mixer with 25% duty-cycle LO improves gain, noise and linearity. A direct coupled current-input filter (DCF) is employed to suppress the out-of-band interferer. Fabricated in a 0.13-μm CMOS process, the RF front-end achieves a 45 dB conversion voltage gain, 2.7 dB NF, −7 dBm IIP3, and +60 dBm IIP2 with calibration from 2.3 to 2.7 GHz. The total RF front end with divider draws 40 mA from a single 1.2-V supply. (semiconductor integrated circuits)

Altered myogenic vasoconstriction and regulation of whole kidney blood flow in the ASIC2 knockout mouse.

Science.gov (United States)

Gannon, Kimberly P; McKey, Susan E; Stec, David E; Drummond, Heather A

2015-02-15

Previous studies from our laboratory have suggested that degenerin proteins contribute to myogenic constriction, a mechanism of blood flow regulation and protection against pressure-dependent organ injury, in renal vessels. The goal of the present study was to determine the importance of one family member, acid-sensing ion channel 2 (ASIC2), in myogenic constriction of renal interlobar arteries, myogenic regulation of whole kidney blood flow, renal injury, and blood pressure using ASIC2(+/+), ASIC2(+/-), and ASIC2(-/-) mice. Myogenic constriction in renal interlobar arteries was impaired in ASIC2(+/-) and ASIC2(-/-) mice, whereas constriction to KCl/phenylephrine was unchanged. Correction of whole kidney renal vascular resistance (RVR) during the first 5 s after a 10- to 20-mmHg step increase in perfusion pressure, a timeframe associated with myogenic-mediated correction of RVR, was slowed (4.2 ± 0.9, 0.3 ± 0.7, and 2.4 ± 0.3 resistance units/s in ASIC2(+/+), ASIC2(+/-), and ASIC2(-/-) mice). Although modest reductions in function were observed in ASIC2(-/-) mice, greater reductions were observed in ASIC2(+/-) mice, which may be explained by protein-protein interactions of ASIC2 with other degenerins. Isolated glomeruli from ASIC2(+/-) and ASIC2(-/-) mice had modest alterations in the expression of inflammation and injury markers (transforming growth factor-β, mouse anti-target of antiproliferative antibody-1, and nephrin), whereas ASIC2(+/-) mice had an increase in the remodeling marker collagen type III. Consistent with a more severe loss of function, mean arterial pressure was increased in ASIC2(+/-) mice (131 ± 3 mmHg) but not in ASIC2(-/-) mice (122 ± 3 vs. 117 ± 2 mmHg in ASIC2(+/+) mice). These results suggest that ASIC2 contributes to transduction of the renal myogenic response and are consistent with the protective role of myogenic constriction against renal injury and hypertension. Copyright © 2015 the American Physiological Society.

Subtype-specific Modulation of Acid-sensing Ion Channel (ASIC) Function by 2-Guanidine-4-methylquinazoline*

Science.gov (United States)

Alijevic, Omar; Kellenberger, Stephan

2012-01-01

Acid-sensing ion channels (ASICs) are neuronal Na+-selective channels that are transiently activated by extracellular acidification. ASICs are involved in fear and anxiety, learning, neurodegeneration after ischemic stroke, and pain sensation. The small molecule 2-guanidine-4-methylquinazoline (GMQ) was recently shown to open ASIC3 at physiological pH. We have investigated the mechanisms underlying this effect and the possibility that GMQ may alter the function of other ASICs besides ASIC3. GMQ shifts the pH dependence of activation to more acidic pH in ASIC1a and ASIC1b, whereas in ASIC3 this shift goes in the opposite direction and is accompanied by a decrease in its steepness. GMQ also induces an acidic shift of the pH dependence of inactivation of ASIC1a, -1b, -2a, and -3. As a consequence, the activation and inactivation curves of ASIC3 but not other ASICs overlap in the presence of GMQ at pH 7.4, thereby creating a window current. At concentrations >1 mm, GMQ decreases maximal peak currents by reducing the unitary current amplitude. Mutation of residue Glu-79 in the palm domain of ASIC3, previously shown to be critical for channel opening by GMQ, disrupted the GMQ effects on inactivation but not activation. This suggests that this residue is involved in the consequences of GMQ binding rather than in the binding interaction itself. This study describes the mechanisms underlying the effects of a novel class of ligands that modulate the function of all ASICs as well as activate ASIC3 at physiological pH. PMID:22948146

Subtype-specific modulation of acid-sensing ion channel (ASIC) function by 2-guanidine-4-methylquinazoline.

Science.gov (United States)

Alijevic, Omar; Kellenberger, Stephan

2012-10-19

Acid-sensing ion channels (ASICs) are neuronal Na(+)-selective channels that are transiently activated by extracellular acidification. ASICs are involved in fear and anxiety, learning, neurodegeneration after ischemic stroke, and pain sensation. The small molecule 2-guanidine-4-methylquinazoline (GMQ) was recently shown to open ASIC3 at physiological pH. We have investigated the mechanisms underlying this effect and the possibility that GMQ may alter the function of other ASICs besides ASIC3. GMQ shifts the pH dependence of activation to more acidic pH in ASIC1a and ASIC1b, whereas in ASIC3 this shift goes in the opposite direction and is accompanied by a decrease in its steepness. GMQ also induces an acidic shift of the pH dependence of inactivation of ASIC1a, -1b, -2a, and -3. As a consequence, the activation and inactivation curves of ASIC3 but not other ASICs overlap in the presence of GMQ at pH 7.4, thereby creating a window current. At concentrations >1 mM, GMQ decreases maximal peak currents by reducing the unitary current amplitude. Mutation of residue Glu-79 in the palm domain of ASIC3, previously shown to be critical for channel opening by GMQ, disrupted the GMQ effects on inactivation but not activation. This suggests that this residue is involved in the consequences of GMQ binding rather than in the binding interaction itself. This study describes the mechanisms underlying the effects of a novel class of ligands that modulate the function of all ASICs as well as activate ASIC3 at physiological pH.

Beamsteerable GNSS Radio Occultation ASIC

Data.gov (United States)

National Aeronautics and Space Administration — We will develop an integrated RF ASIC to enable high quality radio occultation (RO) weather observations using the Global Navigations System Satellite (GNSS)...

The 'KATOD-1' strip readout ASIC for cathode strip chamber

International Nuclear Information System (INIS)

Golutvin, I.A.; Gorbunov, N.V.; Karzhavin, V.Yu.; Khabarov, V.S.; Movchan, S.A.; Smolin, D.A.; Dvornikov, O.V.; Shumejko, N.M.; Chekhovskij, V.A.

2001-01-01

The 'KATOD-1', a 16-channels readout ASIC, has been designed to perform tests of P3 and P4 full-scale prototypes of the cathode strip chamber for the ME1/1 forward muon station of the Compact Muon Solenoid (CMS) experiment. The ASIC channel consists of two charge-sensitive preamplifiers, a three-stage shaper with cancellation, and an output driver. The ASIC is instrumented with control of gain, in the range of (-4.2 : +5.0) mV/fC, and control of output pulse-shape. The equivalent input noise is equal to 2400 e with the slope of 12 e/pF for detector capacity up to 200 pF. The peaking time is 100 ns for the chamber signal. The ASIC has been produced by a microwave Bi-jFET technology

Readout ASIC for ILC-FPCCD vertex detector

International Nuclear Information System (INIS)

Takubo, Yosuke; Miyamoto, Akiya; Ikeda, Hirokazu; Yamamoto, Hitoshi; Itagaki, Kennosuke; Nagamine, Tadashi; Sugimoto, Yasuhiro

2010-01-01

The concept of FPCCD (Fine Pixel CCD) whose pixel size is 5x5μm 2 has been proposed as vertex detector at ILC. Since FPCCD has 128 x20,000 pixels in one readout channel, its readout poses a considerable challenge. We have developed a prototype of readout ASIC to readout the large number of pixels during the inter-train gap of the ILC beam. In this paper, we report the design and performance of the readout ASIC.

Generic testability and test methods guidelines for ASIC devices

International Nuclear Information System (INIS)

Puri, K.; Takeda, H.

1996-04-01

Many industries are switching from analog equipment to digital equipment. This change has become desirable because digital devices have become cost-effective, easily available, highly reliable, easy to qualify and easy to test and replace when needed. The nuclear power industry is beginning to upgrade some of its instrumentation and control equipment from an analog design to digital design. A digital application specific integrated circuit (ASIC) device can be designed to perform the same functions as performed by analog modules. However, the ASIC must be designed for cost-effective testability and qualification. This report provides generic guidelines for designing cost-effective methods for testing and characterizing ASIC devices to accomplish qualification

Acid-sensing ion channel 2 (asic 2) and trkb interrelationships within the intervertebral disc.

Science.gov (United States)

Cuesta, Antonio; Viña, Eliseo; Cabo, Roberto; Vázquez, Gorka; Cobo, Ramón; García-Suárez, Olivia; García-Cosamalón, José; Vega, José A

2015-01-01

The cells of the intervertebral disc (IVD) have an unusual acidic and hyperosmotic microenvironment. They express acid-sensing ion channels (ASICs), gated by extracellular protons and mechanical forces, as well as neurotrophins and their signalling receptors. In the nervous tissues some neurotrophins regulate the expression of ASICs. The expression of ASIC2 and TrkB in human normal and degenerated IVD was assessed using quantitative-PCR, Western blot, and immunohistochemistry. Moreover, we investigated immunohistochemically the expression of ASIC2 in the IVD of TrkB-deficient mice. ASIC2 and TrkB mRNAs were found in normal human IVD and both increased significantly in degenerated IVD. ASIC2 and TrkB proteins were also found co-localized in a variable percentage of cells, being significantly higher in degenerated IVD than in controls. The murine IVD displayed ASIC2 immunoreactivity which was absent in the IVD of TrkB-deficient mice. Present results demonstrate the occurrence of ASIC2 and TrkB in the human IVD, and the increased expression of both in pathological IVD suggest their involvement in IVD degeneration. These data also suggest that TrkB-ligands might be involved in the regulation of ASIC2 expression, and therefore in mechanisms by which the IVD cells accommodate to low pH and hypertonicity.

The "KATOD-1" Strip Readout ASIC for Cathode Strip Chamber

CERN Document Server

Golutvin, I A; Karjavin, V Yu; Khabarov, V S; Movchan, S A; Smolin, D A; Dvornikov, O V; Shumeiko, N M; Tchekhovski, V A

2001-01-01

The "KATOD-1", a 16-channels readout ASIC, has been designed to perform tests of P3 and P4 full-scale prototypes of the cathode strip chamber for the ME1/1 forward muon station of the Compact Muon Solenoid (CMS) experiment. The ASIC channel consists of two charge-sensitive preamplifiers, a three-stage shaper with tail cancellation, and an output driver. The ASIC is instrumented with control of gain, in the range of (-4.2\\div +5.0) mV/fC, and control of output pulse-shape. The equivalent input noise is equal to 2400 e with the slope of 12 e/pF for detector capacity up to 200 pF. The peaking time is 100 ns for the chamber signal. The ASIC has been produced by a microwave Bi-jFET technology.

Two aspects of ASIC function: Synaptic plasticity and neuronal injury.

Science.gov (United States)

Huang, Yan; Jiang, Nan; Li, Jun; Ji, Yong-Hua; Xiong, Zhi-Gang; Zha, Xiang-ming

2015-07-01

Extracellular brain pH fluctuates in both physiological and disease conditions. The main postsynaptic proton receptor is the acid-sensing ion channels (ASICs). During the past decade, much progress has been made on protons, ASICs, and neurological disease. This review summarizes the recent progress on synaptic role of protons and our current understanding of how ASICs contribute to various types of neuronal injury in the brain. This article is part of the Special Issue entitled 'Acid-Sensing Ion Channels in the Nervous System'. Copyright © 2015 Elsevier Ltd. All rights reserved.

FMRFamide-gated sodium channel and ASIC channels: a new class of ionotropic receptors for FMRFamide and related peptides.

Science.gov (United States)

Lingueglia, Eric; Deval, Emmanuel; Lazdunski, Michel

2006-05-01

FMRFamide and related peptides typically exert their action through G-protein coupled receptors. However, two ionotropic receptors for these peptides have recently been identified. They are both members of the epithelial amiloride-sensitive Na+ channel and degenerin (ENaC/DEG) family of ion channels. The invertebrate FMRFamide-gated Na+ channel (FaNaC) is a neuronal Na+-selective channel which is directly gated by micromolar concentrations of FMRFamide and related tetrapeptides. Its response is fast and partially desensitizing, and FaNaC has been proposed to participate in peptidergic neurotransmission. On the other hand, mammalian acid-sensing ion channels (ASICs) are not gated but are directly modulated by FMRFamide and related mammalian peptides like NPFF and NPSF. ASICs are activated by external protons and are therefore extracellular pH sensors. They are expressed both in the central and peripheral nervous system and appear to be involved in many physiological and pathophysiological processes such as hippocampal long-term potentiation and defects in learning and memory, acquired fear-related behavior, retinal function, brain ischemia, pain sensation in ischemia and inflammation, taste perception, hearing functions, and mechanoperception. The potentiation of ASIC activity by endogenous RFamide neuropeptides probably participates in the response to noxious acidosis in sensory and central neurons. Available data also raises the possibility of the existence of still unknown FMRFamide related endogenous peptides acting as direct agonists for ASICs.

ASIC3 Channels Integrate Agmatine and Multiple Inflammatory Signals through the Nonproton Ligand Sensing Domain

Directory of Open Access Journals (Sweden)

Cao Hui

2010-12-01

Full Text Available Abstract Background Acid-sensing ion channels (ASICs have long been known to sense extracellular protons and contribute to sensory perception. Peripheral ASIC3 channels represent natural sensors of acidic and inflammatory pain. We recently reported the use of a synthetic compound, 2-guanidine-4-methylquinazoline (GMQ, to identify a novel nonproton sensing domain in the ASIC3 channel, and proposed that, based on its structural similarity with GMQ, the arginine metabolite agmatine (AGM may be an endogenous nonproton ligand for ASIC3 channels. Results Here, we present further evidence for the physiological correlation between AGM and ASIC3. Among arginine metabolites, only AGM and its analog arcaine (ARC activated ASIC3 channels at neutral pH in a sustained manner similar to GMQ. In addition to the homomeric ASIC3 channels, AGM also activated heteromeric ASIC3 plus ASIC1b channels, extending its potential physiological relevance. Importantly, the process of activation by AGM was highly sensitive to mild acidosis, hyperosmolarity, arachidonic acid (AA, lactic acid and reduced extracellular Ca2+. AGM-induced ASIC3 channel activation was not through the chelation of extracellular Ca2+ as occurs with increased lactate, but rather through a direct interaction with the newly identified nonproton ligand sensing domain. Finally, AGM cooperated with the multiple inflammatory signals to cause pain-related behaviors in an ASIC3-dependent manner. Conclusions Nonproton ligand sensing domain might represent a novel mechanism for activation or sensitization of ASIC3 channels underlying inflammatory pain-sensing under in vivo conditions.

RPC performance vs. front-end electronics

International Nuclear Information System (INIS)

Cardarelli, R.; Aielli, G.; Camarri, P.; Di Ciaccio, A.; Di Stante, L.; Liberti, B.; Pastori, E.; Santonico, R.; Zerbini, A.

2012-01-01

Moving the amplification from the gas to the front-end electronics was a milestone in the development of Resistive Plate Chambers. Here we discuss the historical evolution of RPCs and we show the results obtained with newly developed front-end electronics with threshold in the fC range.

Web-based DAQ systems: connecting the user and electronics front-ends

International Nuclear Information System (INIS)

Lenzi, Thomas

2016-01-01

Web technologies are quickly evolving and are gaining in computational power and flexibility, allowing for a paradigm shift in the field of Data Acquisition (DAQ) systems design. Modern web browsers offer the possibility to create intricate user interfaces and are able to process and render complex data. Furthermore, new web standards such as WebSockets allow for fast real-time communication between the server and the user with minimal overhead. Those improvements make it possible to move the control and monitoring operations from the back-end servers directly to the user and to the front-end electronics, thus reducing the complexity of the data acquisition chain. Moreover, web-based DAQ systems offer greater flexibility, accessibility, and maintainability on the user side than traditional applications which often lack portability and ease of use. As proof of concept, we implemented a simplified DAQ system on a mid-range Spartan6 Field Programmable Gate Array (FPGA) development board coupled to a digital front-end readout chip. The system is connected to the Internet and can be accessed from any web browser. It is composed of custom code to control the front-end readout and of a dual soft-core Microblaze processor to communicate with the client.

Web-based DAQ systems: connecting the user and electronics front-ends

Science.gov (United States)

Lenzi, Thomas

2016-12-01

Web technologies are quickly evolving and are gaining in computational power and flexibility, allowing for a paradigm shift in the field of Data Acquisition (DAQ) systems design. Modern web browsers offer the possibility to create intricate user interfaces and are able to process and render complex data. Furthermore, new web standards such as WebSockets allow for fast real-time communication between the server and the user with minimal overhead. Those improvements make it possible to move the control and monitoring operations from the back-end servers directly to the user and to the front-end electronics, thus reducing the complexity of the data acquisition chain. Moreover, web-based DAQ systems offer greater flexibility, accessibility, and maintainability on the user side than traditional applications which often lack portability and ease of use. As proof of concept, we implemented a simplified DAQ system on a mid-range Spartan6 Field Programmable Gate Array (FPGA) development board coupled to a digital front-end readout chip. The system is connected to the Internet and can be accessed from any web browser. It is composed of custom code to control the front-end readout and of a dual soft-core Microblaze processor to communicate with the client.

ASIC-dependent LTP at multiple glutamatergic synapses in amygdala network is required for fear memory.

Science.gov (United States)

Chiang, Po-Han; Chien, Ta-Chun; Chen, Chih-Cheng; Yanagawa, Yuchio; Lien, Cheng-Chang

2015-05-19

Genetic variants in the human ortholog of acid-sensing ion channel-1a subunit (ASIC1a) gene are associated with panic disorder and amygdala dysfunction. Both fear learning and activity-induced long-term potentiation (LTP) of cortico-basolateral amygdala (BLA) synapses are impaired in ASIC1a-null mice, suggesting a critical role of ASICs in fear memory formation. In this study, we found that ASICs were differentially expressed within the amygdala neuronal population, and the extent of LTP at various glutamatergic synapses correlated with the level of ASIC expression in postsynaptic neurons. Importantly, selective deletion of ASIC1a in GABAergic cells, including amygdala output neurons, eliminated LTP in these cells and reduced fear learning to the same extent as that found when ASIC1a was selectively abolished in BLA glutamatergic neurons. Thus, fear learning requires ASIC-dependent LTP at multiple amygdala synapses, including both cortico-BLA input synapses and intra-amygdala synapses on output neurons.

Mongoose ASIC microcontroller programming guide

Science.gov (United States)

Smith, Brian S.

1993-01-01

The 'Mongoose' ASIC microcontroller is a radiation-hard implementation of the R3000 microprocessor. This document describes the internals of the microcontroller in a level of detail necessary for someone implementing a software design.

Test vehicles for CMS HGCAL readout ASIC

CERN Document Server

Thienpont, Damien

2017-01-01

This paper presents first measurement results of two test vehicles ASIC embedding some building blocks for the future CMS High Granularity CALorimeter (HGCAL) read-out ASIC. They were fabricated in CMOS 130 nm, in order to first design the Analog and Mixed-Signal blocks before going to a complete and complex chip. Such a circuit needs to achieve low noise high dynamic range charge measurement and 20 ps resolution timing capability. The results show good analog performance but with higher noise levels compared to simulations. We present the results of the preamplifiers, shapers and ADCs.

ASIC2 Subunits Target Acid-Sensing Ion Channels to the Synapse via an Association with PSD-95

OpenAIRE

Zha, Xiang-ming; Costa, Vivian; Harding, Anne Marie S.; Reznikov, Leah; Benson, Christopher J.; Welsh, Michael J.

2009-01-01

Acid-sensing ion channel-1a (ASIC1a) mediates H+-gated current to influence normal brain physiology and impact several models of disease. Although ASIC2 subunits are widely expressed in brain and modulate ASIC1a current, their function remains poorly understood. We identified ASIC2a in dendrites, dendritic spines, and brain synaptosomes. This localization largely relied on ASIC2a binding to PSD-95 and matched that of ASIC1a, which does not co-immunoprecipitate with PSD-95. We found that ASIC2...

Acid-sensing ion channel (ASIC) structure and function: Insights from spider, snake and sea anemone venoms.

Science.gov (United States)

Cristofori-Armstrong, Ben; Rash, Lachlan D

2017-12-01

Acid-sensing ion channels (ASICs) are proton-activated cation channels that are expressed in a variety of neuronal and non-neuronal tissues. As proton-gated channels, they have been implicated in many pathophysiological conditions where pH is perturbed. Venom derived compounds represent the most potent and selective modulators of ASICs described to date, and thus have been invaluable as pharmacological tools to study ASIC structure, function, and biological roles. There are now ten ASIC modulators described from animal venoms, with those from snakes and spiders favouring ASIC1, while the sea anemones preferentially target ASIC3. Some modulators, such as the prototypical ASIC1 modulator PcTx1 have been studied in great detail, while some of the newer members of the club remain largely unstudied. Here we review the current state of knowledge on venom derived ASIC modulators, with a particular focus on their molecular interaction with ASICs, what they have taught us about channel structure, and what they might still reveal about ASIC function and pathophysiological roles. This article is part of the Special Issue entitled 'Venom-derived Peptides as Pharmacological Tools.' Copyright © 2017 Elsevier Ltd. All rights reserved.

Design of ultralow power receiver front-ends for 2.4 GHz wireless sensor network applications

International Nuclear Information System (INIS)

Zhang Meng; Li Zhiqun; Wang Zengqi; Wu Chenjian; Chen Liang

2014-01-01

This paper presents the design of an ultralow power receiver front-end designed for a wireless sensor network (WSN) in a 0.18 μm CMOS process. The author designs two front-ends working in the saturation region and the subthreshold region respectively. The front-ends contain a two-stage cross-coupling cascaded common-gate (CG) LNA and a quadrature Gilbert IQ mixer. The measured conversion gain is variable with high gain at 24 dB and low gain at 7 dB for the saturation one, and high gain at 22 dB and low gain at 5 dB for the subthreshold one. The noise figure (NF) at high gain mode is 5.1 dB and 6.3 dB for each. The input 1 dB compression point (IP1dB) at low gain mode is about −6 dBm and −3 dBm for each. The front-ends consume about 2.1 mA current from 1.8 V power supply for the saturation one and 1.3 mA current for the subthreshold one. The measured results show that, comparing with the power consumption saving, it is worth making sacrifices on the performance for using the subthreshold technology. (semiconductor integrated circuits)

Acid-sensing ion channel (ASIC) 1a/2a heteromers have a flexible 2:1/1:2 stoichiometry.

Science.gov (United States)

Bartoi, Tudor; Augustinowski, Katrin; Polleichtner, Georg; Gründer, Stefan; Ulbrich, Maximilian H

2014-06-03

Acid-sensing ion channels (ASICs) are widely expressed proton-gated Na(+) channels playing a role in tissue acidosis and pain. A trimeric composition of ASICs has been suggested by crystallization. Upon coexpression of ASIC1a and ASIC2a in Xenopus oocytes, we observed the formation of heteromers and their coexistence with homomers by electrophysiology, but could not determine whether heteromeric complexes have a fixed subunit stoichiometry or whether certain stoichiometries are preferred over others. We therefore imaged ASICs labeled with green and red fluorescent proteins on a single-molecule level, counted bleaching steps from GFP and colocalized them with red tandem tetrameric mCherry for many individual complexes. Combinatorial analysis suggests a model of random mixing of ASIC1a and ASIC2a subunits to yield both 2:1 and 1:2 ASIC1a:ASIC2a heteromers together with ASIC1a and ASIC2a homomers.

Atomic force microscopy imaging reveals the formation of ASIC/ENaC cross-clade ion channels

International Nuclear Information System (INIS)

Jeggle, Pia; Smith, Ewan St. J.; Stewart, Andrew P.; Haerteis, Silke; Korbmacher, Christoph; Edwardson, J. Michael

2015-01-01

ASIC and ENaC are co-expressed in various cell types, and there is evidence for a close association between them. Here, we used atomic force microscopy (AFM) to determine whether ASIC1a and ENaC subunits are able to form cross-clade hybrid ion channels. ASIC1a and ENaC could be co-isolated from detergent extracts of tsA 201 cells co-expressing the two subunits. Isolated proteins were incubated with antibodies against ENaC and Fab fragments against ASIC1a. AFM imaging revealed proteins that were decorated by both an antibody and a Fab fragment with an angle of ∼120° between them, indicating the formation of ASIC1a/ENaC heterotrimers. - Highlights: • There is evidence for a close association between ASIC and ENaC. • We used AFM to test whether ASIC1a and ENaC subunits form cross-clade ion channels. • Isolated proteins were incubated with subunit-specific antibodies and Fab fragments. • Some proteins were doubly decorated at ∼120° by an antibody and a Fab fragment. • Our results indicate the formation of ASIC1a/ENaC heterotrimers

Atomic force microscopy imaging reveals the formation of ASIC/ENaC cross-clade ion channels

Energy Technology Data Exchange (ETDEWEB)

Jeggle, Pia; Smith, Ewan St. J.; Stewart, Andrew P. [Department of Pharmacology, University of Cambridge, Tennis Court Road, Cambridge CB2 1PD (United Kingdom); Haerteis, Silke; Korbmacher, Christoph [Institut für Zelluläre und Molekulare Physiologie, Friedrich-Alexander-Universität Erlangen-Nürnberg, Waldstrasse 6, 91054 Erlangen (Germany); Edwardson, J. Michael, E-mail: jme1000@cam.ac.uk [Department of Pharmacology, University of Cambridge, Tennis Court Road, Cambridge CB2 1PD (United Kingdom)

2015-08-14

ASIC and ENaC are co-expressed in various cell types, and there is evidence for a close association between them. Here, we used atomic force microscopy (AFM) to determine whether ASIC1a and ENaC subunits are able to form cross-clade hybrid ion channels. ASIC1a and ENaC could be co-isolated from detergent extracts of tsA 201 cells co-expressing the two subunits. Isolated proteins were incubated with antibodies against ENaC and Fab fragments against ASIC1a. AFM imaging revealed proteins that were decorated by both an antibody and a Fab fragment with an angle of ∼120° between them, indicating the formation of ASIC1a/ENaC heterotrimers. - Highlights: • There is evidence for a close association between ASIC and ENaC. • We used AFM to test whether ASIC1a and ENaC subunits form cross-clade ion channels. • Isolated proteins were incubated with subunit-specific antibodies and Fab fragments. • Some proteins were doubly decorated at ∼120° by an antibody and a Fab fragment. • Our results indicate the formation of ASIC1a/ENaC heterotrimers.

ASIC Development for Three-Dimensional Silicon Imaging Array for Cold Neutrons

International Nuclear Information System (INIS)

Britton, C.L.; Jagadish, U.; Bryan, W.L.

2004-01-01

An Integrated Circuit (IC) readout chip with four channels arranged so as to receive input charge from the corners of the chip was designed for use with 5- to 7-mm pixel detectors. This Application Specific IC (ASIC) can be used for cold neutron imaging, for study of structural order in materials using cold neutron scattering or for particle physics experiments. The ASIC is fabricated in a 0.5-(micro)m n-well AMI process. The design of the ASIC and the test measurements made is reported. Noise measurements are also reported

Introduction to the Highlights of the 26th ASIC Conference.

Science.gov (United States)

Nehlig, Astrid

2017-09-10

The 26th ASIC Conference that was held in 2016 in Kunming, China has been marking the 50th anniversary of the creation of ASIC. The meeting in China was well attended by over 400 participants from all over the world and allowed fruitful exchanges among participants from all horizons of coffee science.

Memory, microprocessor, and ASIC

CERN Document Server

Chen, Wai-Kai

2003-01-01

System Timing. ROM/PROM/EPROM. SRAM. Embedded Memory. Flash Memories. Dynamic Random Access Memory. Low-Power Memory Circuits. Timing and Signal Integrity Analysis. Microprocessor Design Verification. Microprocessor Layout Method. Architecture. ASIC Design. Logic Synthesis for Field Programmable Gate Array (EPGA) Technology. Testability Concepts and DFT. ATPG and BIST. CAD Tools for BIST/DFT and Delay Faults.

EXPERIENCE WITH FPGA-BASED PROCESSOR CORE AS FRONT-END COMPUTER

International Nuclear Information System (INIS)

HOFF, L.T.

2005-01-01

The RHIC control system architecture follows the familiar ''standard model''. LINUX workstations are used as operator consoles. Front-end computers are distributed around the accelerator, close to equipment being controlled or monitored. These computers are generally based on VMEbus CPU modules running the VxWorks operating system. I/O is typically performed via the VMEbus, or via PMC daughter cards (via an internal PCI bus), or via on-board I/O interfaces (Ethernet or serial). Advances in FPGA size and sophistication now permit running virtual processor ''cores'' within the FPGA logic, including ''cores'' with advanced features such as memory management. Such systems offer certain advantages over traditional VMEbus Front-end computers. Advantages include tighter coupling with FPGA logic, and therefore higher I/O bandwidth, and flexibility in packaging, possibly resulting in a lower noise environment and/or lower cost. This paper presents the experience acquired while porting the RHIC control system to a PowerPC 405 core within a Xilinx FPGA for use in low-level RF control

ASIC channel inhibition enhances excitotoxic neuronal death in an in vitro model of spinal cord injury.

Science.gov (United States)

Mazzone, Graciela L; Veeraraghavan, Priyadharishini; Gonzalez-Inchauspe, Carlota; Nistri, Andrea; Uchitel, Osvaldo D

2017-02-20

In the spinal cord high extracellular glutamate evokes excitotoxic damage with neuronal loss and severe locomotor impairment. During the cell dysfunction process, extracellular pH becomes acid and may activate acid-sensing ion channels (ASICs) which could be important contributors to neurodegenerative pathologies. Our previous studies have shown that transient application of the glutamate analog kainate (KA) evokes delayed excitotoxic death of spinal neurons, while white matter is mainly spared. The present goal was to enquire if ASIC channels modulated KA damage in relation to locomotor network function and cell death. Mouse spinal cord slices were treated with KA (0.01 or 0.1mM) for 1h, and then washed out for 24h prior to analysis. RT-PCR results showed that KA (at 0.01mM concentration that is near-threshold for damage) increased mRNA expression of ASIC1a, ASIC1b, ASIC2 and ASIC3, an effect reversed by the ASIC inhibitor 4',6-diamidino-2-phenylindole (DAPI). A KA neurotoxic dose (0.1mM) reduced ASIC1a and ASIC2 expression. Cell viability assays demonstrated KA-induced large damage in spinal slices from mice with ASIC1a gene ablation. Likewise, immunohistochemistry indicated significant neuronal loss when KA was followed by the ASIC inhibitors DAPI or amiloride. Electrophysiological recording from ventral roots of isolated spinal cords showed that alternating oscillatory cycles were slowed down by 0.01mMKA, and intensely inhibited by subsequently applied DAPI or amiloride. Our data suggest that early rise in ASIC expression and function counteracted deleterious effects on spinal networks by raising the excitotoxicity threshold, a result with potential implications for improving neuroprotection. Copyright © 2016 IBRO. Published by Elsevier Ltd. All rights reserved.

Radiation-hard ASICs for optical data transmission in the first phase of the LHC upgrade

CERN Document Server

Gan, K K; Kagan, H P; Kass, R D; Moore, J R; Smith, D S; Wiese, A; Ziolkowskic, M; 10.1088/1748-0221/5/12/C12006

2010-01-01

We have designed two ASICs for possible applications in the optical links of a new layer of the pixel detector to be install inside the ATLAS Pixel detector for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for the VCSEL and a receiver/decoder to decode the signal received at the PIN diode to extract the data and clock. Both ASICs contain 4 channels for operation with a VCSEL or PIN array. The ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated ASICs and the performance of the ASICs is satisfactory. The receiver/decoder can properly decode the bi-phase marked input stream with low PIN current and the driver can operate a VCSEL up to ~ 5 Gb/s. The added functionalities are also successful, including redundancy to bypass a broken VCSEL or PIN channel, individual control of VCSEL current, and power-on reset circuit to set all VCSEL currents to a nominal value. The ASICs were irradiated to a dose of 46 Mrad ...

A 1.2 Gb/s Data Transmission Unit in CMOS 0.18 μm technology for the ALICE Inner Tracking System front-end ASIC

Science.gov (United States)

Mazza, G.; Aglieri Rinella, G.; Benotto, F.; Corrales Morales, Y.; Kugathasan, T.; Lattuca, A.; Lupi, M.; Ravasenga, I.

2017-02-01

The upgrade of the ALICE Inner Tracking System is based on a Monolithic Active Pixel Sensor and ASIC designed in a CMOS 0.18 μ m process. In order to provide the required output bandwidth (1.2 Gb/s for the inner layers and 400 Mb/s for the outer ones) on a single high speed serial link, a custom Data Transmission Unit (DTU) has been developed in the same process. The DTU includes a clock multiplier PLL, a double data rate serializer and a pseudo-LVDS driver with pre-emphasis and is designed to be SEU tolerant.

Multichannel readout ASIC design flow for high energy physics and cosmic rays experiments

International Nuclear Information System (INIS)

Voronin, A; Malankin, E

2016-01-01

In the large-scale high energy physics and astrophysics experiments multi-channel readout application specific integrated circuits (ASICs) are widely used. The ASICs for such experiments are complicated systems, which usually include both analog and digital building blocks. The complexity and large number of channels in such ASICs require the proper methodological approach to their design. The paper represents the mixed-signal design flow of the ASICs for high energy physics and cosmic rays experiments. This flow was successfully embedded to the development of the read-out ASIC prototype for the muon chambers of the CBM experiment. The approach was approved in UMC CMOS MMRF 180 nm process. The design flow enable to analyse the mixed-signal system operation on the different levels: functional, behavioural, schematic and post layout including parasitic elements. The proposed design flow allows reducing the simulation period and eliminating the functionality mismatches on the very early stage of the design. (paper)

Feedback from operational experience in front-end transportation

International Nuclear Information System (INIS)

Mondonel, J.L.; Parison, C.

1998-01-01

Transport forms an integral part of the nuclear fuel cycle, representing the strategic link between each stage of the cycle. In a way there is a transport cycle that parallels the nuclear fuel cycle. This concerns particularly the front-end of the cycle whose steps - mining conversion, enrichment and fuel fabrication - require numerous transports. Back-end shipments involve a handful of countries, but front-end transports involve all five continents, and many exotic countries. All over Europe such transports are routinely performed with an excellent safety track record. Transnucleaire dominates the French nuclear transportation market and carries out both front and back-end transports. For instance in 1996 more than 28,400 front-end packages were transported as well as more than 3,600 back-end packages. However front-end transport is now a business undergoing much change. A nuclear transportation company must now cope with an evolving picture including new technical requirements, new transportation schemes and new business conditions. This paper describes the latest evolutions in terms of front-end transportation and the way this activity is carried out by Transnucleaire, and goes on to discuss future prospects. (authors)

Identification of a novel protein complex containing ASIC1a and GABAA receptors and their interregulation.

Directory of Open Access Journals (Sweden)

Dongbo Zhao

Full Text Available Acid-sensing ion channels (ASICs belong to the family of the epithelial sodium channel/degenerin (ENaC/DEG and are activated by extracellular protons. They are widely distributed within both the central and peripheral nervous systems. ASICs were modified by the activation of γ-aminobutyric acid receptors (GABAA, a ligand-gated chloride channels, in hippocampal neurons. In contrast, the activity of GABAA receptors were also modulated by extracellular pH. However so far, the mechanisms underlying this intermodulation remain obscure. We hypothesized that these two receptors-GABAA receptors and ASICs channels might form a novel protein complex and functionally interact with each other. In the study reported here, we found that ASICs were modified by the activation of GABAA receptors either in HEK293 cells following transient co-transfection of GABAA and ASIC1a or in primary cultured dorsal root ganglia (DRG neurons. Conversely, activation of ASIC1a also modifies the GABAA receptor-channel kinetics. Immunoassays showed that both GABAA and ASIC1a proteins were co-immunoprecipitated mutually either in HEK293 cells co-transfected with GABAA and ASIC1a or in primary cultured DRG neurons. Our results indicate that putative GABAA and ASIC1a channels functionally interact with each other, possibly via an inter-molecular association by forming a novel protein complex.

DST9-1, an ASIC for receiving and delivery of time signals

International Nuclear Information System (INIS)

Cuzon, J.C.

1999-01-01

In order to evaluate the 1.2 μ BiCMOS technology of AMS foundry the electronics department developed a full custom ASIC for time signal receiving and shaping according to our fast TDC pre-diffused ASIC. (author)

Adaptive RF front-ends for hand-held applications

CERN Document Server

van Bezooijen, Andre; van Roermund, Arthur

2010-01-01

The RF front-end - antenna combination is a vital part of a mobile phone because its performance is very relevant to the link quality between hand-set and cellular network base-stations. The RF front-end performance suffers from changes in operating environment, like hand-effects, that are often unpredictable. ""Adaptive RF Front-Ends for Hand-Held Applications"" presents an analysis on the impact of fluctuating environmental parameters. In order to overcome undesired behavior two different adaptive control methods are treated that make RF frond-ends more resilient: adaptive impedance control,

Asic3(-/- female mice with hearing deficit affects social development of pups.

Directory of Open Access Journals (Sweden)

Wei-Li Wu

Full Text Available BACKGROUND: Infant crying is an important cue for mothers to respond adequately. Inappropriate response to infant crying can hinder social development in infants. In rodents, the pup-mother interaction largely depends on pup's calls. Mouse pups emit high frequency to ultrasonic vocalization (2-90 kHz to communicate with their dam for maternal care. However, little is known about how the maternal response to infant crying or pup calls affects social development over the long term. METHODOLOGY/PRINCIPAL FINDINGS: Here we used mice lacking acid-sensing ion channel 3 (Asic3(-/- to create a hearing deficit to probe the effect of caregiver hearing on maternal care and adolescent social development. Female Asic3(-/- mice showed elevated hearing thresholds for low to ultrasonic frequency (4-32 kHz on auditory brain stem response, which thus hindered their response to their pups' wriggling calls and ultrasonic vocalization, as well as their retrieval of pups. In adolescence, pups reared by Asic3(-/- mice showed a social deficit in juvenile social behaviors as compared with those reared by wild-type or heterozygous dams. The social-deficit phenotype in juvenile mice reared by Asic3(-/- mice was associated with the reduced serotonin transmission of the brain. However, Asic3(-/- pups cross-fostered to wild-type dams showed rescued social deficit. CONCLUSIONS/SIGNIFICANCE: Inadequate response to pups' calls as a result of ASIC3-dependent hearing loss confers maternal deficits in caregivers and social development deficits in their young.

PICK1 regulates the trafficking of ASIC1a and acidotoxicity in a BAR domain lipid binding-dependent manner

Directory of Open Access Journals (Sweden)

Jin Wenying

2010-12-01

Full Text Available Abstract Background Acid-sensing ion channel 1a (ASIC1a is the major ASIC subunit determining acid-activated currents in brain neurons. Recent studies show that ASIC1a play critical roles in acid-induced cell toxicity. While these studies raise the importance of ASIC1a in diseases, mechanisms for ASIC1a trafficking are not well understood. Interestingly, ASIC1a interacts with PICK1 (protein interacting with C-kinase 1, an intracellular protein that regulates trafficking of several membrane proteins. However, whether PICK1 regulates ASIC1a surface expression remains unknown. Results Here, we show that PICK1 overexpression increases ASIC1a surface level. A BAR domain mutant of PICK1, which impairs its lipid binding capability, blocks this increase. Lipid binding of PICK1 is also required for PICK1-induced clustering of ASIC1a. Consistent with the effect on ASIC1a surface levels, PICK1 increases ASIC1a-mediated acidotoxicity and this effect requires both the PDZ and BAR domains of PICK1. Conclusions Taken together, our results indicate that PICK1 regulates trafficking and function of ASIC1a in a lipid binding-dependent manner.

Radiation induced Single Event Effects in the ATLAS MDT-ASD front-end chip

CERN Document Server

Posch, C

2002-01-01

Single Event Effect (SEE) tests of the MDT-ASD, the ATLAS MDT front-end chip have been performed at the Harvard Cyclotron Lab. The MDT-ASD is an 8-channel drift tube read-out ASIC fabricated in a commercial 0.5um CMOS process (AMOS14TB). The chip contains a 53 bit register which holds the setup information and an associated shift register of the same length plus some additional control logic. 10 test devices were exposed to a 160 MeV proton beam with a fluence of 1.05E9 p.cm-2.s-1 up to >4.4E p.cm-2 per device. After a total fluence of 4.46E13 p.cm-2, 7 soft SEEs (non-permanent bit flips in the registers) and 0 hard/destructive SEE (e.g. latch-ups, SEL) had occurred. The simulated fluence for 10 years of LHC operation at nominal luminosity for worst case location MDT components is 2.67E11 h.cm-2. The rate of SEUs in the ASD setup register for all of ATLAS, derived from these numbers, is 2.4 per day. It is foreseen to update the active registers of the on-detector electronics at regular intervals. Depending on...

Planar millimeter wave radar frontend for automotive applications

Directory of Open Access Journals (Sweden)

J. Grubert

2003-01-01

Full Text Available A fully integrated planar sensor for 77 GHz automotive applications is presented. The frontend consists of a transceiver multichip module and an electronically steerable microstrip patch array. The antenna feed network is based on a modified Rotman-lens and connected to the array in a multilayer approach offering higher integration. Furthermore, the frontend comprises a phase lock loop to allow proper frequency-modulated continuous wave (FMCW radar operation. The latest experimental results verify the functionality of this advanced frontend design featuring automatic cruise control, precrash sensing and cut-in detection. These promising radar measurements give reason to a detailed theoretical investigation of system performance. Employing commercially available MMIC various circuit topologies are compared based on signal-tonoise considerations. Different scenarios for both sequential and parallel lobing hint to more advanced sensor designs and better performance. These improvements strongly depend on the availability of suitable MMIC and reliable packaging technologies. Within our present approach possible future MMIC developments are already considered and, thus, can be easily adapted by the flexible frontend design. Es wird ein integrierter planarer Sensor für 77 GHz Radaranwendungen vorgestellt. Das Frontend besteht aus einem Sende- und Empfangs-Multi-Chip-Modul und einer elektronisch schwenkbaren Antenne. Das Speisenetzwerk der Antenne basiert auf einer modifizierten Rotman- Linse. Für eine kompakte Bauweise sind Antenne und Speisenetzwerk mehrlagig integriert. Weiterhin umfasst das Frontend eine Phasenregelschleife für eine präzise Steuerung des frequenzmodulierten Dauerstrichradars. Die aktuellen Messergebnisse bestätigen die Funktionalit¨at dieses neuartigen Frontend-Designs, das automatische Geschwindigkeitsregelung, Kollisionswarnung sowie Nahbereichsüberwachung ermöglicht. Die Qualität der Messergebnisse hat weiterf

The TDCpix readout ASIC: A 75ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

CERN Document Server

Kluge, A; Bonacini, S; Jarron, P; Kaplon, J; Morel, M; Noy, M; Perktold, L; Poltorak, K

2013-01-01

The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak fl ow of particles crossing the detector modules reaches 1.27 MHz/mm 2 for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection ef fi ciency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45 40 square pixels of 300 300 μ m 2 and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low...

Latest generation of ASICs for photodetector readout

Science.gov (United States)

Seguin-Moreau, N.

2013-08-01

The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the "ROC" family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the "ROC" chips.

Latest generation of ASICs for photodetector readout

Energy Technology Data Exchange (ETDEWEB)

Seguin-Moreau, N., E-mail: seguin@lal.in2p3.fr [Laboratoire de l’Accélérateur Linéaire, IN2P3-CNRS, Université Paris-Sud, Bâtiment 200, 91898 Orsay Cedex (France)

2013-08-01

The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the “ROC” family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the “ROC” chips.

Latest generation of ASICs for photodetector readout

International Nuclear Information System (INIS)

Seguin-Moreau, N.

2013-01-01

The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the “ROC” family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the “ROC” chips

Radiation hardness tests and characterization of the CLARO-CMOS, a low power and fast single-photon counting ASIC in 0.35 micron CMOS technology

International Nuclear Information System (INIS)

Fiorini, M.; Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

2014-01-01

The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. This chip is capable of single-photon counting with multi-anode photomultipliers and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The prototype is realized in AMS 0.35 micron CMOS technology. In the LHCb RICH environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2 (LS2), the ASIC must withstand a total fluence of about 6×10 12 1 MeV n eq /cm 2 and a total ionizing dose of 400 krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long term stability of the electronics front-end. The results of multi-step irradiation tests with neutrons and X-rays up to the fluence of 10 14 cm −2 and a dose of 4 Mrad, respectively, are presented, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step. - Highlights: • CLARO chip capable of single-photon counting with 5 ns peaking time. • Chip irradiated up to very high neutron, proton and X-rays fluences, as expected for upgraded LHCb RICH detectors. • No significant performance degradation is observed after irradiation

Local ASIC3 modulates pain and disease progression in a rat model of osteoarthritis

Directory of Open Access Journals (Sweden)

Izumi Masashi

2012-08-01

Full Text Available Abstract Background Recent data have suggested a relationship between acute arthritic pain and acid sensing ion channel 3 (ASIC3 on primary afferent fibers innervating joints. The purpose of this study was to clarify the role of ASIC3 in a rat model of osteoarthritis (OA which is considered a degenerative rather than an inflammatory disease. Methods We induced OA via intra-articular mono-iodoacetate (MIA injection, and evaluated pain-related behaviors including weight bearing measured with an incapacitance tester and paw withdrawal threshold in a von Frey hair test, histology of affected knee joint, and immunohistochemistry of knee joint afferents. We also assessed the effect of ASIC3 selective peptide blocker (APETx2 on pain behavior, disease progression, and ASIC3 expression in knee joint afferents. Results OA rats showed not only weight-bearing pain but also mechanical hyperalgesia outside the knee joint (secondary hyperalgesia. ASIC3 expression in knee joint afferents was significantly upregulated approximately twofold at Day 14. Continuous intra-articular injections of APETx2 inhibited weight distribution asymmetry and secondary hyperalgesia by attenuating ASIC3 upregulation in knee joint afferents. Histology of ipsilateral knee joint showed APETx2 worked chondroprotectively if administered in the early, but not late phase. Conclusions Local ASIC3 immunoreactive nerve is strongly associated with weight-bearing pain and secondary hyperalgesia in MIA-induced OA model. APETx2 inhibited ASIC3 upregulation in knee joint afferents regardless of the time-point of administration. Furthermore, early administration of APETx2 prevented cartilage damage. APETx2 is a novel, promising drug for OA by relieving pain and inhibiting disease progression.

Extracellular acidosis activates ASIC-like channels in freshly isolated cerebral artery smooth muscle cells.

Science.gov (United States)

Chung, Wen-Shuo; Farley, Jerry M; Swenson, Alyssa; Barnard, John M; Hamilton, Gina; Chiposi, Rumbidzayi; Drummond, Heather A

2010-05-01

Recent studies suggest that certain acid-sensing ion channels (ASIC) are expressed in vascular smooth muscle cells (VSMCs) and are required for VSMC functions. However, electrophysiological evidence of ASIC channels in VSMCs is lacking. The purpose of this study was to test the hypothesis that isolated cerebral artery VSMCs express ASIC-like channels. To address this hypothesis, we used RT-PCR, Western blotting, immunolabeling, and conventional whole cell patch-clamp technique. We found extracellular H(+)-induced inward currents in 46% of cells tested (n = 58 of 126 VSMCs, pH 6.5-5.0). The percentage of responsive cells and the current amplitude increased as the external H(+) concentration increased (pH(6.0), n = 28/65 VSMCs responsive, mean current density = 8.1 +/- 1.2 pA/pF). Extracellular acidosis (pH(6.0)) shifted the whole cell reversal potential toward the Nernst potential of Na(+) (n = 6) and substitution of extracellular Na(+) by N-methyl-d-glucamine abolished the inward current (n = 6), indicating that Na(+) is a major charge carrier. The broad-spectrum ASIC blocker amiloride (20 microM) inhibited proton-induced currents to 16.5 +/- 8.7% of control (n = 6, pH(6.0)). Psalmotoxin 1 (PcTx1), an ASIC1a inhibitor and ASIC1b activator, had mixed effects: PcTx1 either 1) abolished H(+)-induced currents (11% of VSMCs, 5/45), 2) enhanced or promoted activation of H(+)-induced currents (76%, 34/45), or 3) failed to promote H(+) activation in nonresponsive VSMCs (13%, 6/45). These findings suggest that freshly dissociated cerebral artery VSMCs express ASIC-like channels, which are predominantly formed by ASIC1b.

Effect of a temperature increase in the non-noxious range on proton-evoked ASIC and TRPV1 activity.

Science.gov (United States)

Blanchard, Maxime G; Kellenberger, Stephan

2011-01-01

Acid-sensing ion channels (ASICs) are neuronal H(+)-gated cation channels, and the transient receptor potential vanilloid 1 channel (TRPV1) is a multimodal cation channel activated by low pH, noxious heat, capsaicin, and voltage. ASICs and TRPV1 are present in sensory neurons. It has been shown that raising the temperature increases TRPV1 and decreases ASIC H(+)-gated current amplitudes. To understand the underlying mechanisms, we have analyzed ASIC and TRPV1 function in a recombinant expression system and in dorsal root ganglion (DRG) neurons at room and physiological temperature. We show that temperature in the range studied does not affect the pH dependence of ASIC and TRPV1 activation. A temperature increase induces, however, a small alkaline shift of the pH dependence of steady-state inactivation of ASIC1a, ASIC1b, and ASIC2a. The decrease in ASIC peak current amplitudes at higher temperatures is likely in part due to the observed accelerated open channel inactivation kinetics and for some ASIC types to the changed pH dependence of steady-state inactivation. The increase in H(+)-activated TRPV1 current at the higher temperature is at least in part due to a hyperpolarizing shift in its voltage dependence. The contribution of TRPV1 relative to ASICs to H(+)-gated currents in DRG neurons increases with higher temperature and acidity. Still, ASICs remain the principal pH sensors of DRG neurons at 35°C in the pH range ≥6.

A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

CERN Document Server

Senkin, Sergey; The ATLAS collaboration

2017-01-01

The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC) foreseen in 2024. We present here one of the front-end readout options, an ASIC called FATALIC, which is proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. Hereby we describe the full characterisation of FATALIC and also the signal reconstruction up to the observables of interest for physics: the energy and the arrival time of the particle. The Optimal Filtering signal reconstruction method is adapted to fully exploit the FATALIC three-range layout. Additionally, we present the performance in terms of resolution of the whole chain measured using the charge injection system designed for calibration. Finally, the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN are discussed.

The Human Acid-Sensing Ion Channel ASIC1a: Evidence for a Homotetrameric Assembly State at the Cell Surface.

Directory of Open Access Journals (Sweden)

Miguel Xavier van Bemmelen

Full Text Available The chicken acid-sensing ion channel ASIC1 has been crystallized as a homotrimer. We address here the oligomeric state of the functional ASIC1 in situ at the cell surface. The oligomeric states of functional ASIC1a and mutants with additional cysteines introduced in the extracellular pore vestibule were resolved on SDS-PAGE. The functional ASIC1 complexes were stabilized at the cell surface of Xenopus laevis oocytes or CHO cells either using the sulfhydryl crosslinker BMOE, or sodium tetrathionate (NaTT. Under these different crosslinking conditions ASIC1a migrates as four distinct oligomeric states that correspond by mass to multiples of a single ASIC1a subunit. The relative importance of each of the four ASIC1a oligomers was critically dependent on the availability of cysteines in the transmembrane domain for crosslinking, consistent with the presence of ASIC1a homo-oligomers. The expression of ASIC1a monomers, trimeric or tetrameric concatemeric cDNA constructs resulted in functional channels. The resulting ASIC1a complexes are resolved as a predominant tetramer over the other oligomeric forms, after stabilization with BMOE or NaTT and SDS-PAGE/western blot analysis. Our data identify a major ASIC1a homotetramer at the surface membrane of the cell expressing functional ASIC1a channel.

A High-Performance Deformable Mirror with Integrated Driver ASIC for Space Based Active Optics

Science.gov (United States)

Shelton, Chris

Direct imaging of exoplanets is key to fully understanding these systems through spectroscopy and astrometry. The primary impediment to direct imaging of exoplanets is the extremely high brightness ratio between the planet and its parent star. Direct imaging requires a technique for contrast suppression, which include coronagraphs, and nulling interferometers. Deformable mirrors (DMs) are essential to both of these techniques. With space missions in mind, Microscale is developing a novel DM with direct integration of DM and its electronic control functions in a single small envelope. The Application Specific Integrated Circuit (ASIC) is key to the shrinking of the electronic control functions to a size compatible with direct integration with the DM. Through a NASA SBIR project, Microscale, with JPL oversight, has successfully demonstrated a unique deformable mirror (DM) driver ASIC prototype based on an ultra-low power switch architecture. Microscale calls this the Switch-Mode ASIC, or SM-ASIC, and has characterized it for a key set of performance parameters, and has tested its operation with a variety of actuator loads, such as piezo stack and unimorph, and over a wide temperature range. These tests show the SM-ASIC's capability of supporting active optics in correcting aberrations of a telescope in space. Microscale has also developed DMs to go with the SM-ASIC driver. The latest DM version produced uses small piezo stack elements in an 8x8 array, bonded to a novel silicon facesheet structure fabricated monolithically into a polished mirror on one side and mechanical linkage posts that connect to the piezoelectric stack actuators on the other. In this Supporting Technology proposal we propose to further develop the ASIC-DM and have assembled a very capable team to do so. It will be led by JPL, which has considerable expertise with DMs used in Adaptive Optics systems, with high-contrast imaging systems for exoplanet missions, and with designing DM driver

ASIC3, an acid-sensing ion channel, is expressed in metaboreceptive sensory neurons

Directory of Open Access Journals (Sweden)

Fierro Leonardo

2005-11-01

Full Text Available Abstract Background ASIC3, the most sensitive of the acid-sensing ion channels, depolarizes certain rat sensory neurons when lactic acid appears in the extracellular medium. Two functions have been proposed for it: 1 ASIC3 might trigger ischemic pain in heart and muscle; 2 it might contribute to some forms of touch mechanosensation. Here, we used immunocytochemistry, retrograde labelling, and electrophysiology to ask whether the distribution of ASIC3 in rat sensory neurons is consistent with either of these hypotheses. Results Less than half (40% of dorsal root ganglion sensory neurons react with anti-ASIC3, and the population is heterogeneous. They vary widely in cell diameter and express different growth factor receptors: 68% express TrkA, the receptor for nerve growth factor, and 25% express TrkC, the NT3 growth factor receptor. Consistent with a role in muscle nociception, small ( Conclusion Our data indicates that: 1 ASIC3 is expressed in a restricted population of nociceptors and probably in some non-nociceptors; 2 co-expression of ASIC3 and CGRP, and the absence of P2X3, are distinguishing properties of a class of sensory neurons, some of which innervate blood vessels. We suggest that these latter afferents may be muscle metaboreceptors, neurons that sense the metabolic state of muscle and can trigger pain when there is insufficient oxygen.

Test of a 32-channel Prototype ASIC for Photon Counting Application.

Science.gov (United States)

Chen, Y; Cui, Y; O'Connor, P; Seo, Y; Camarda, G S; Hossain, A; Roy, U; Yang, G; James, R B

2015-01-01

A new low-power application-specific integrated circuit (ASIC) for Cadmium Zinc Telluride (CZT) detectors for single-photon emission computed tomography (SPECT) application is being developed at BNL. As the first step, a 32-channel prototype ASIC was designed and tested recently. Each channel has a preamplifier followed by CR-RC 3 shaping circuits and three independent energy bins with comparators and 16-bit counters. The ASIC was fabricated with TSMC 0.35-μm complementary metal-oxide-semiconductor (CMOS) process and tested in laboratories. The power consumption is around 1 mW/ch with a 2.5-V supply. With a gain of 400 mV/fC and the peaking time of 500 ns, the equivalent noise charge (ENC) of 360 e- has been measured in room temperature while the crosstalk rate is less than 0.3%. The 10-bit DACs for global thresholds have an integral nonlinearity (INL) less than 0.56% and differential nonlinearity (DNL) less than 0.33%. In the presentation, we will report the detailed test results with this ASIC.

Radiation-hard ASICs for optical data transmission in the first phase of the LHC upgrade

International Nuclear Information System (INIS)

Gan, K K; Kagan, H P; Kass, R D; Moore, J R; Smith, D S; Buchholz, P; Wiese, A; Ziolkowskic, M

2010-01-01

We have designed two ASICs for possible applications in the optical links of a new layer of the pixel detector to be install inside the ATLAS Pixel detector for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for the VCSEL and a receiver/decoder to decode the signal received at the PIN diode to extract the data and clock. Both ASICs contain 4 channels for operation with a VCSEL or PIN array. The ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated ASICs and the performance of the ASICs is satisfactory. The receiver/decoder can properly decode the bi-phase marked input stream with low PIN current and the driver can operate a VCSEL up to ∼ 5 Gb/s. The added functionalities are also successful, including redundancy to bypass a broken VCSEL or PIN channel, individual control of VCSEL current, and power-on reset circuit to set all VCSEL currents to a nominal value. The ASICs were irradiated to a dose of 46 Mrad with 24 GeV/c protons. The observed modest degradation is acceptable and the single event upset rate is negligible.

ARTROC—a readout ASIC for GEM-based full-field XRF imaging system

Science.gov (United States)

Fiutowski, T.; Koperny, S.; Łach, B.; Mindur, B.; Świentek, K.; Wiącek, P.; Dąbrowski, W.

2017-12-01

In the paper we report on development of an Application Specific Integrated Circuit (ASIC), called ARTROC, being part of a full-field X-ray fluorescence spectroscopy (XRF) imaging system equipped with a standard three stage Gas Electron Multiplier (GEM) detector of 10×10 cm2 area. The ARTROC consists of 64 independent channels, allowing for simultaneous recording of the amplitudes (energy sub-channel) and time stamps (timing sub-channel) of incoming signals. Thanks to the implemented token-based read out of derandomizing buffers, the ASIC also provides data sparsification and full zero suppression. Reconstruction of the hit positions is performed in an external data acquisition system by matching the time stamps of signals recorded in X- and Y-strips. The amplitude information is used for centre of gravity finding in clusters of signals on neighbouring strips belonging to the same detection events. The ASIC could work in one of six gain modes and one of two speed modes. In a slower mode the maximum count rate per channel is 105/s while in a faster mode it is three times higher. The ARTROC comprises also input protection circuits against possible random discharges inside active detector volume, so it can be used without any additional input components. The ASIC has been designed in 350 nm CMOS process. The basic functionality and parameters have been evaluated using the testability functions implemented in the ASIC design. The ASIC has been also tested in a fully equipped GEM detector set-up with X-rays source.

Atomic force microscopy imaging reveals the formation of ASIC/ENaC cross-clade ion channels.

Science.gov (United States)

Jeggle, Pia; Smith, Ewan St J; Stewart, Andrew P; Haerteis, Silke; Korbmacher, Christoph; Edwardson, J Michael

2015-08-14

ASIC and ENaC are co-expressed in various cell types, and there is evidence for a close association between them. Here, we used atomic force microscopy (AFM) to determine whether ASIC1a and ENaC subunits are able to form cross-clade hybrid ion channels. ASIC1a and ENaC could be co-isolated from detergent extracts of tsA 201 cells co-expressing the two subunits. Isolated proteins were incubated with antibodies against ENaC and Fab fragments against ASIC1a. AFM imaging revealed proteins that were decorated by both an antibody and a Fab fragment with an angle of ∼120° between them, indicating the formation of ASIC1a/ENaC heterotrimers. Copyright © 2015 Elsevier Inc. All rights reserved.

The role of periodontal ASIC3 in orofacial pain induced by experimental tooth movement in rats.

Science.gov (United States)

Gao, Meiya; Long, Hu; Ma, Wenqiang; Liao, Lina; Yang, Xin; Zhou, Yang; Shan, Di; Huang, Renhuan; Jian, Fan; Wang, Yan; Lai, Wenli

2016-12-01

This study aimed to clarify the roles of Acid-sensing ion channel 3 (ASIC3) in orofacial pain following experimental tooth movement. Sixty male Sprague-Dawley rats were divided into the experimental group (40g, n = 30) and the sham group (0g, n = 30). Closed coil springs were ligated between maxillary incisor and molars to achieve experimental tooth movement. Rat grimace scale (RGS) scores were assessed at 0, 1, 3, 5, 7, and 14 days after the placement of the springs. ASIC3 immunostaining was performed and the expression levels of ASIC3 were measured through integrated optical density/area in Image-Pro Plus 6.0. Moreover, 18 rats were divided into APETx2 group (n = 6), amiloride group (n = 6), and vehicle group (n = 6), and RGS scores were obtained compared among them to verify the roles of ASIC3 in orofacial pain following tooth movement. ASIC3 expression levels became significantly higher in the experimental group than in sham group on 1, 3, and 5 days and became similar on 7 and 14 days. Pain levels (RGS scores) increased in both groups and were significantly higher in the experimental group on 1, 3, 5, and 7 days and were similar on 14 days. Periodontal ASIC3 expression levels were correlated with orofacial pain levels following experimental tooth movement. Periodontal administrations of ASIC3 antagonists (APETx2 and amiloride) could alleviate pain. This study needs to be better evidenced by RNA interference of ASIC3 in periodontal tissues in rats following experimental tooth movement. Moreover, we hope further studies would concentrate on the pain perception of ASIC3 knockout (ASIC3 -/- ) mice. Our results suggest that periodontal ASIC3 plays an important role in orofacial pain induced by experimental tooth movement. © The Author 2015. Published by Oxford University Press on behalf of the European Orthodontic Society. All rights reserved. For permissions, please email: journals.permissions@oup.com.

Ultra-wideband wireless receiver front-end for high-speed indoor applications

Directory of Open Access Journals (Sweden)

Zhe-Yang Huang

2014-12-01

Full Text Available Low-noise, ultra-wideband (UWB wireless receiver front-end circuits were presented in this study. A two-stage common-source low-noise amplifier with wideband input impedance matching network, an active-balun and a double-balanced down-conversion mixer were adopted in the UWB wireless receiver front-end. The proposed wireless receiver front-end circuits were implemented in 0.18 μm radio-frequency-CMOS process. The maximum down-conversion power gain of the front-end is 25.8 dB; minimum single-sideband noise figure of the front-end is 4.9 dB over complete UWB band ranging from 3.1 to 10.6 GHz. Power consumption including buffers is 39.2 mW.

Radiation-hard ASICs for optical data transmission in the first phase of the LHC upgrade

International Nuclear Information System (INIS)

Gan, K.K.; Buchholz, P.; Kagan, H.P.; Kass, R.D.; Moore, J.R.; Smith, D.S.; Wiese, A.; Ziolkowskic, M.

2011-01-01

We have designed two ASICs for possible applications in the optical links of a new layer of the pixel detector to be install inside the ATLAS Pixel detector for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for a VCSEL and a receiver/decoder to decode the signal received at a PIN diode to extract the data and clock. Both ASICs contain 4 channels for operation with a VCSEL or PIN array. The ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated ASICs and the performance of the ASICs is satisfactory. The receiver/decoder properly decodes the bi-phase marked input stream with low PIN current and the driver can operate a VCSEL up to ∼5 Gb/s. The added functionalities are also successful, including redundancy to bypass a broken VCSEL or PIN channel, individual control of VCSEL current, and power-on reset circuit to set all VCSEL currents to a nominal value.

A high performance multi-channel preamplifier ASIC

International Nuclear Information System (INIS)

Yarema, R.J.; Zimmerman, T.; Williams, W.; Binkley, M.; Huffman, T.; Wagner, R.

1992-01-01

This paper reports on a new preamplifier ASIC that has been designed and built to improve performance of the VTPC (Vertex Time Projection Chamber) at Fermilab's Collliding Detector Facility. Design of the semicustom IC was completed using a Tektronix QuickChip 2S bipolar linear array. The ASIC has 6 channels on a chip and provides lower noise, higher gain, lower power, and lower mass packaging than the device which it replaces. Actual performance of the preamplifier was found to match very closely the simulated performance. To reduce the mass of the complete circuit board, bare IC dice were mounted directly on a G-10 substrate using COB (chip on board) techniques. The preamplifier and packaging should be applicable to numerous other systems

A high performance multi-channel preamplifier ASIC

Energy Technology Data Exchange (ETDEWEB)

Yarema, R.J.; Zimmerman, T.; Williams, W.; Binkley, M.; Huffman, T.; Wagner, R.

1991-11-01

A new preamplifier ASIC has been designed and built to improve performance of the VTPC (Vertex Time Projection Chamber) at Fermilab's Colliding Detector Facility. Design of the semicustom IC was completed using a Tektronix Quick-Chip 2S bipolar linear array. The ASIC has 6 channels on a chip and provides lower noise, higher gain, lower power, and lower mass packaging than the device which it replaces. Actual performance of the preamplifier was found to match very closely the simulated performance. To reduce the mass of the complete circuit board, bare IC dice were mounted directly on a G-10 substrate using COB (chip on board) techniques. The preamplifier and packaging should be applicable to numerous other systems. 1 ref.

A high performance multi-channel preamplifier ASIC

International Nuclear Information System (INIS)

Yarema, R.J.; Zimmerman, T.; Williams, W.; Binkley, M.; Huffman, T.; Wagner, R.

1991-11-01

A new preamplifier ASIC has been designed and built to improve performance of the VTPC (Vertex Time Projection Chamber) at Fermilab's Colliding Detector Facility. Design of the semicustom IC was completed using a Tektronix Quick-Chip 2S bipolar linear array. The ASIC has 6 channels on a chip and provides lower noise, higher gain, lower power, and lower mass packaging than the device which it replaces. Actual performance of the preamplifier was found to match very closely the simulated performance. To reduce the mass of the complete circuit board, bare IC dice were mounted directly on a G-10 substrate using COB (chip on board) techniques. The preamplifier and packaging should be applicable to numerous other systems. 1 ref

Glioblastoma cancer stem cell lines express functional acid sensing ion channels ASIC1a and ASIC3

DEFF Research Database (Denmark)

Tian, Yuemin; Bresenitz, Pia; Reska, Anna

2017-01-01

Acidic microenvironment is commonly observed in tumour tissues, including glioblastoma (GBM), the most aggressive and lethal brain tumour in adults. Acid sensing ion channels (ASICs) are neuronal voltage-insensitive sodium channels, which are sensors of extracellular protons. Here we studied...

A Low-Power ASIC Signal Processor for a Vestibular Prosthesis.

Science.gov (United States)

Töreyin, Hakan; Bhatti, Pamela T

2016-06-01

A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm (2) and consumes 1.24 mW when supplied with ± 1.6 V.

A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond

International Nuclear Information System (INIS)

Gass, Karl; Pierson, Lyndon G.; Robertson, Perry J.; Wilcox, D. Craig; Witzke, Edward L.

1999-01-01

The Sandia National Laboratories (SNL) Data Encryption Standard (DES) Application Specific Integrated Circuit (ASIC) is the fastest known implementation of the DES algorithm as defined in the Federal Information Processing Standards (FIPS) Publication 46-2. DES is used for protecting data by cryptographic means. The SNL DES ASIC, over 10 times faster than other currently available DES chips, is a high-speed, filly pipelined implementation offering encryption, decryption, unique key input, or algorithm bypassing on each clock cycle. Operating beyond 105 MHz on 64 bit words, this device is capable of data throughputs greater than 6.7 Billion bits per second (tester limited). Simulations predict proper operation up to 9.28 Billion bits per second. In low frequency, low data rate applications, the ASIC consumes less that one milliwatt of power. The device has features for passing control signals synchronized to throughput data. Three SNL DES ASICS may be easily cascaded to provide the much greater security of triple-key, triple-DES

Synthesis, structure-activity relationship, and pharmacological profile of analogs of the ASIC-3 inhibitor A-317567.

Science.gov (United States)

Kuduk, Scott D; Di Marco, Christina N; Bodmer-Narkevitch, Vera; Cook, Sean P; Cato, Matthew J; Jovanovska, Aneta; Urban, Mark O; Leitl, Michael; Sain, Nova; Liang, Annie; Spencer, Robert H; Kane, Stefanie A; Hartman, George D; Bilodeau, Mark T

2010-01-20

The synthesis, structure-activity relationship (SAR), and pharmacological evaluation of analogs of the acid-sensing ion channel (ASIC) inhibitor A-317567 are reported. It was found that the compound with an acetylenic linkage was the most potent ASIC-3 channel blocker. This compound reversed mechanical hypersensitivity in the rat iodoacetate model of osteoarthritis pain, although sedation was noted. Sedation was also observed in ASIC-3 knockout mice, questioning whether sedation and antinociception are mediated via a non-ASIC-3 specific mechanism.

Concepts for a Muon Accelerator Front-End

Energy Technology Data Exchange (ETDEWEB)

Stratakis, Diktys [Fermilab; Berg, Scott [Brookhaven; Neuffer, David [Fermilab

2017-03-16

We present a muon capture front-end scheme for muon based applications. In this Front-End design, a proton bunch strikes a target and creates secondary pions that drift into a capture channel, decaying into muons. A series of rf cavities forms the resulting muon beams into a series of bunches of differerent energies, aligns the bunches to equal central energies, and initiates ionization cooling. We also discuss the design of a chicane system for the removal of unwanted secondary particles from the muon capture region and thus reduce activation of the machine. With the aid of numerical simulations we evaluate the performance of this Front-End scheme as well as study its sensitivity against key parameters such as the type of target, the number of rf cavities and the gas pressure of the channel.

VeloPix ASIC for the LHCb VELO Upgrade

CERN Multimedia

Cid Vidal, Xabier

2015-01-01

The LHCb Vertex Detector (VELO) will be upgraded in 2018 along with the other subsystems of LHCb in order to enable full detector readout at 40 MHz. LHCb will run without a hardware trigger and all data will be fed directly to the software triggering algorithms in the CPU farm. The upgraded VELO is a lightweight silicon hybrid pixel detector with 55 um square pixels, operating in vacuum in close proximity to the LHC beams. The readout will be provided by a dedicated front end ASIC, dubbed VeloPix, matched to the LHCb luminosity requirements. VeloPix is a binary pixel chip with a matrix of 256 x 256 pixels, covering an area of 2 cm^2. It is designed in a 130 nm CMOS technology, and is closely related to the Timepix3, from the Medipix family of ASICs. The principal challenge that the chip has to meet is a hit rate of up to 900 Mhits/s/ASIC, resulting in a data rate of more than 16 Gbit/s. Combining pixels into groups of 2x4 super-pixels enables the use of shared logic and a reduction of bandwidth due to combine...

ASIC1a regulates insular long-term depression and is required for the extinction of conditioned taste aversion.

Science.gov (United States)

Li, Wei-Guang; Liu, Ming-Gang; Deng, Shining; Liu, Yan-Mei; Shang, Lin; Ding, Jing; Hsu, Tsan-Ting; Jiang, Qin; Li, Ying; Li, Fei; Zhu, Michael Xi; Xu, Tian-Le

2016-12-07

Acid-sensing ion channel 1a (ASIC1a) has been shown to play important roles in synaptic plasticity, learning and memory. Here we identify a crucial role for ASIC1a in long-term depression (LTD) at mouse insular synapses. Genetic ablation and pharmacological inhibition of ASIC1a reduced the induction probability of LTD without affecting that of long-term potentiation in the insular cortex. The disruption of ASIC1a also attenuated the extinction of established taste aversion memory without altering the initial associative taste learning or its long-term retention. Extinction of taste aversive memory led to the reduced insular synaptic efficacy, which precluded further LTD induction. The impaired LTD and extinction learning in ASIC1a null mice were restored by virus-mediated expression of wild-type ASIC1a, but not its ion-impermeable mutant, in the insular cortices. Our data demonstrate the involvement of an ASIC1a-mediated insular synaptic depression mechanism in extinction learning, which raises the possibility of targeting ASIC1a to manage adaptive behaviours.

A Serializer ASIC for High Speed Data Transmission in Cryogenic and HiRel Environment

CERN Document Server

Liu, T; The ATLAS collaboration

2010-01-01

A high speed 16:1 serializer ASIC has been developed using a commercial 0.25 μm silicon-on-sapphire CMOS technology. At room temperature the ASIC operates from 4.0 to 5.7 Gbps with power consumption of 463 mW. The total jitter is 62 ps at the bit error rate of 10-12 at 5 Gbps. A 200-MeV proton beam test indicates that the ASIC is suitable for high energy physics applications. A liquid nitrogen temperature test indicates that the ASIC may be used at cryogenic temperature applications. The reliability of the serializer at liquid nitrogen temperature is to be studied. A 6-lane serializer array with 10 Gbps/lane with redundancy capability is under development.

The CaloRIC ASIC: Signal Processing for High Granularity Calorimeter

International Nuclear Information System (INIS)

Royer, L; Manen, S; Soumpholphakdy, X; Bonnard, J; Gay, P

2013-01-01

A readout ASIC called CaloRIC, has been developed to fulfil the signal processing requirements for the Silicon-Tungsten (Si-W) electromagnetic calorimeter of the International Linear Collider (ILC). This ASIC performs the complete processing of the signal delivered by the Si-PIN diode of the detector: charge sensitive amplification, shaping, analog memorization and digitization. Measurements show a global integral non-linearity better than 0.2% for low energy particles, and limited to 2% for high energy particles. The measured Equivalent Noise Charge (ENC) is evaluated at 0.6 fC, which corresponds to 1/6 times the signal released by a Minimum Ionizing Particle (MIP). With the timing sequence of the ILC, the power consumption of the complete channel is evaluated at 43 μW using a power pulsing. A new ASIC (CaloRIC 4 ch) with four improved readout channels has been designed and is ready for manufacturing.

PADI ASIC for straw tube read-out

Energy Technology Data Exchange (ETDEWEB)

Pietraszko, Jerzy; Traeger, Michael; Fruehauf, Jochen; Schmidt, Christian [GSI, Darmstadt (Germany); Ciobanu, Mircea [ISS, Bucharest (Romania); Collaboration: CBM-Collaboration

2016-07-01

A prototype of the CBM MUCH straw tube detector consisting of six individual straws of 6mm inner diameter and 220 mm length filled with Ar/CO{sub 2} gas mixture has been tested at the COSY accelerator in Juelich. The straw tubes were connected to the FEET-PADI6-HDa PCB equipped with PADI-6 fast amplifier/discriminator ASIC. As a reference counter in this measurement the scCVD diamond detector has been used delivering excellent timing, time resolution below 100 ps (sigma), and very precise position information, below 50 μm. The demonstrated position resolution of about 160 μm of the straw tube read out with PADI-6 ASIC confirms the capability of the PADI chip and puts this development as a very attractive readout option for straw tubes and wire chambers.

Development of a two-dimensional ASIC for hard X-ray spectroscopy and imaging with a CdTe pixel detector

International Nuclear Information System (INIS)

Hiruta, Tatsuro; Tamura, K.; Ikeda, H.; Nakazawa, K.; Takasima, T.; Takahashi, T.

2006-01-01

We are developing a two-dimensional analog ASIC for the readout of pixel sensors based on silicon (Si) or cadmium telluride (CdTe) for spectroscopic imaging observations in the X-ray and gamma-ray regions. The aim for the ASIC is to obtain a low-noise performance better than 100 electrons (rms) with self-triggering capabilities. As the first step of prototyping, we have fabricated several ASICs. We obtained an energy resolution of 5.4 keV (FWHM) for 81 keV gamma-rays from 133 Ba with a one-dimensional ASIC connected to a CdTe diode and also verified a readout architecture via a two-dimensional ASIC with 144 pixel channels. Based on the results obtained and experience gained through prototype ASICs, we are developing a 4096-channel two-dimensional analog ASIC

Driver ASIC Environmental Testing and Performance Optimization for SpaceBased Active Mirrors

Science.gov (United States)

Mejia Prada, Camilo

Direct imaging of Earth-like planets requires techniques for light suppression, such as coronagraphs or nulling interferometers, in which deformable mirrors (DM) are a principal component. On ground-based systems, DMs are used to correct for turbulence in the Earth’s atmosphere in addition to static aberrations in the optics. For space-based observations, DMs are used to correct for static and quasi- static aberrations in the optical train. State-of-the-art, high-actuator count deformable mirrors suffer from external heavy and bulky electronics in which electrical connections are made through thousands of wires. We are instead developing Application Specific Integrated Circuits (ASICs) capable of direct integration with the DM in a single small package. This integrated ASIC-DM is ideal for space missions, where it offers significant reduction in mass, power and complexity, and performance compatible with high-contrast observations of exoplanets. We have successfully prototyped and tested a 32x32 format Switch-Mode (SM) ASIC which consumes only 2mW static power (total, not per-actuator). A number of constraints were imposed on key parameters of this ASIC design, including sub-picoamp levels of leakage across turned-off switches and from switch-to-substrate, control resolution of 0.04 mV, satisfactory rise/fall times, and a near-zero on-chip crosstalk over a useful range of operating temperatures. This driver ASIC technology is currently at TRL 4. This Supporting Technology proposal will further develop the ASIC technology to TRL 5 by carrying on environmental tests and further optimizing performance, with the end goal of making ASICs suitable for space-based deployment. The effort will be led by JPL, which has considerable expertise with DMs used in highcontrast imaging systems for exoplanet missions and in adaptive optic systems, and in design of DM driver electronics. Microscale, which developed the prototype of the ASICDM, will continue its development. We

Skiroc A Front-end Chip to Read Out the Imaging Silicon-Tungsten Calorimeter for ILC

CERN Document Server

Bouchel, Michel; Fleury, Julien; de La Taille, Christophe; Martin-Chassard,Gisèle; Raux, Ludovic; Wicek, Francois; Bohner, Gérard; Gay, Pascal; Lecoq, Jacques; Manen, Samuel; Royer, Laurent

2007-01-01

Integration and low-power consumption of the read-out ASIC for the International Linear Collider (ILC) 82-millionchannel W-Si calorimeter must reach an unprecedented level as it will be embedded inside the detector. Uniformity and dynamic range performance has to reach the accuracy to achieve calorimetric measurement. A first step towards this goal has been a 10,000-channel physics prototype of 18*18 cm which is currently in test beam in CERN. A new version of a full integrated read out chip (SKIROC) has been designed to equip the technologic prototype to be built for 2009. Based on the running physics prototype ASIC (FLC_PHY3), it embeds most of the required features expected for the final detector. The dynamic range has been improved from 500 to 2000 MIP. An auto-trigger capability has been added allowing built-in zero suppress. The number of channel has been doubled reaching 36 to fit smaller silicon pads and the lownoise charge preamplifier now accepts both AC and DC coupled detectors. After an exhaustive...

Neuroprotective Effects of Psalmotoxin-1, an Acid-Sensing Ion Channel (ASIC) Inhibitor, in Ischemia Reperfusion in Mouse Eyes.

Science.gov (United States)

Dibas, Adnan; Millar, Cameron; Al-Farra, Abraham; Yorio, Thomas

2018-03-29

The purpose of the current study is to assess changes in the expression of Acid-Sensing Ion Channel (ASIC)1a and ASIC2 in retinal ganglion cells (RGCs) after retinal ischemia and reperfusion (I/R) injury and to test if inhibition of ASIC1a provides RGC neuroprotection. Transient ischemia was induced in one eye of C57BL/6 mice by raising intraocular pressure to 120 mmHg for 60 min followed by retinal reperfusion by restoring normal pressure. RGC function was measured by Pattern electroretinography (PERG). In addition, retinal ASIC1a and ASIC2 were observed by immunohistochemistry and western blot. Changes in calpain, fodrin, heat shock protein 70 (HSP70), Brn3a, super oxide dismutase-1 (SOD1), catalase, and glutathione perioxidase-4 (GPX4) protein levels were assessed by western blot. RGC numbers were measured by immunohistochemistry on whole retinal flat mounts using anti-RNA binding protein with multiple splicing (RBPMS) antibodies. Intravitreal injection of psalmotoxin-1, a selective ASIC1a blocker, was used to assess the neuroprotective effect of ASIC1a inhibition. Levels of ASIC1a and ASIC2 after I/R increased in RGCs. Upregulation of ASIC1a but not ASIC2 was attenuated by intravitreal injection of psalmotoxin-1. I/R induced activation of calpain and degradation of fodrin, HSP70, and reduction in Brn3a. In contrast, while psalmotoxin-1 attenuated calpain activation and increased Brn3a levels, it failed to block HSP70 degradation. Unlike SOD1 protein which was reduced, catalase protein levels increased after I/R. Psalmotoxin-1, although not affecting SOD1 and GPX4, increased catalase levels significantly. Psalmotoxin-1 also increased RBPMS-labeled RGCs following I/R as judged by immunohistochemistry of retinal flat mounts. Finally, psalmotoxin-1 enhanced the amplitude of PERG following I/R, suggesting partial rescue of RGC function. Psalmotoxin-1 appears to exert a neuroprotective effect under ischemic insults and targeting inhibition of ASICs may represent a

An Implantable Versatile Electrode-Driving ASIC for Chronic Epidural Stimulation in Rats.

Science.gov (United States)

Giagka, Vasiliki; Eder, Clemens; Donaldson, Nick; Demosthenous, Andreas

2015-06-01

This paper presents the design and testing of an electrode driving application specific integrated circuit (ASIC) intended for epidural spinal cord electrical stimulation in rats. The ASIC can deliver up to 1 mA fully programmable monophasic or biphasic stimulus current pulses, to 13 electrodes selected in any possible configuration. It also supports interleaved stimulation. Communication is achieved via only 3 wires. The current source and the control of the stimulation timing were kept off-chip to reduce the heat dissipation close to the spinal cord. The ASIC was designed in a 0.18- μm high voltage CMOS process. Its output voltage compliance can be up to 25 V. It features a small core area (ASIC was developed to be suitable for integration on the epidural electrode array, and two different versions were fabricated and electrically tested. Results from both versions were almost indistinguishable. The performance of the system was verified for different loads and stimulation parameters. Its suitability to drive a passive epidural 12-electrode array in saline has also been demonstrated.

A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC.

Science.gov (United States)

Xinkai Chen; Xiaoyu Zhang; Linwei Zhang; Xiaowen Li; Nan Qi; Hanjun Jiang; Zhihua Wang

2009-02-01

This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm * 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.

An Energy-Efficient ASIC for Wireless Body Sensor Networks in Medical Applications.

Science.gov (United States)

Xiaoyu Zhang; Hanjun Jiang; Lingwei Zhang; Chun Zhang; Zhihua Wang; Xinkai Chen

2010-02-01

An energy-efficient application-specific integrated circuit (ASIC) featured with a work-on-demand protocol is designed for wireless body sensor networks (WBSNs) in medical applications. Dedicated for ultra-low-power wireless sensor nodes, the ASIC consists of a low-power microcontroller unit (MCU), a power-management unit (PMU), reconfigurable sensor interfaces, communication ports controlling a wireless transceiver, and an integrated passive radio-frequency (RF) receiver with energy harvesting ability. The MCU, together with the PMU, provides quite flexible communication and power-control modes for energy-efficient operations. The always-on passive RF receiver with an RF energy harvesting block offers the sensor nodes the capability of work-on-demand with zero standby power. Fabricated in standard 0.18-¿m complementary metal-oxide semiconductor technology, the ASIC occupies a die area of 2 mm × 2.5 mm. A wireless body sensor network sensor-node prototype using this ASIC only consumes < 10-nA current under the passive standby mode, and < 10 ¿A under the active standby mode, when supplied by a 3-V battery.

A new interface weak-capacitance detection ASIC of capacitive liquid level sensor in the rocket

Science.gov (United States)

Yin, Liang; Qin, Yao; Liu, Xiao-Wei

2017-11-01

A new capacitive liquid level sensing interface weak-capacitance detection ASIC has been designed. This ASIC realized the detection of the output capacitance of the capacitive liquid level sensor, which converts the output capacitance of the capacitive liquid level sensor to voltage. The chip is fabricated in a standard 0.5μm CMOS process. The test results show that the linearity of capacitance detection of the ASIC is 0.05%, output noise is 3.7aF/Hz (when the capacitance which will be detected is 40 pF), the stability of capacitance detection is 7.4 × 10-5pF (1σ, 1h), the output zero position temperature coefficient is 4.5 uV/∘C. The test results prove that this interface ASIC can meet the requirement of high accuracy capacitance detection. Therefore, this interface ASIC can be applied in capacitive liquid level sensing and capacitive humidity sensing field.

Optical data transmission ASICs for the high-luminosity LHC (HL-LHC) experiments

International Nuclear Information System (INIS)

Li, X; Huang, G; Sun, X; Liu, G; Deng, B; Gong, D; Guo, D; Liu, C; Liu, T; Xiang, A C; Ye, J; Zhao, X; Chen, J; You, Y; He, M; Hou, S; Teng, P-K; Jin, G; Liang, H; Liang, F

2014-01-01

We present the design and test results of two optical data transmission ASICs for the High-Luminosity LHC (HL-LHC) experiments. These ASICs include a two-channel serializer (LOCs2) and a single-channel Vertical Cavity Surface Emitting Laser (VCSEL) driver (LOCld1V2). Both ASICs are fabricated in a commercial 0.25-μm Silicon-on-Sapphire (SoS) CMOS technology and operate at a data rate up to 8 Gbps per channel. The power consumption of LOCs2 and LOCld1V2 are 1.25 W and 0.27 W at 8-Gbps data rate, respectively. LOCld1V2 has been verified meeting the radiation-tolerance requirements for HL-LHC experiments

Study of preamplifier, shaper and peak detector in readout ASIC for particle detector

International Nuclear Information System (INIS)

Wang Ke; Zhang Shengjun; Fan Lei; Li Xian

2014-01-01

Recently, kinds of particle detectors have used Application Specific Integrated Circuits (ASIC) in their electronics readout system and ASICs have been designed in China now. This project designed a multi-channel readout ASIC for general detector. The chip has Preamplifier, Shaper and Peak Detector embedded for easy readout. For each channel, signal which is preprocessed by a low-noise preamplifier is sent to the shaper to form a quasi-Gaussian pulse and keep its peak for readout. This chip and modules of individual Preamplifier, Shaper and Peak Detector have been manufactured, results will be reported in time. (authors)

The Role of Custom Design in ASIC Chips

National Research Council Canada - National Science Library

Dally, William

1998-01-01

The performance of an ASIC can be greatly improved without increasing design time by judiciously employing a number of custom design techniques, including floorplanning, prerouting critical signals...

Indico front-end: From spaghetti to lasagna

CERN Multimedia

CERN. Geneva

2017-01-01

We will present how we transitioned from legacy spaghetti UI code to a more coherent, easier to understand and maintain ecosystem of front-end technologies and facilities with a strong emphasis in reusable components. In particular, we will share with you: 1) how we use Sass to maintain our home-baked CSS, 2) how we survive in 2017 without front-end Javascript frameworks, and 3) how we use template macros and WTForms for generating consistent HTML transparently.

Prototype of a transient waveform recording ASIC

Science.gov (United States)

Qin, J.; Zhao, L.; Cheng, B.; Chen, H.; Guo, Y.; Liu, S.; An, Q.

2018-01-01

The paper presents the design and measurement results of a transient waveform recording ASIC based on the Switched Capacitor Array (SCA) architecture. This 0.18 μm CMOS prototype device contains two channels and each channel employs a SCA of 128 samples deep, a 12-bit Wilkinson ADC and a serial data readout. A series of tests have been conducted and the results indicate that: a full 1 V signal voltage range is available, the input analog bandwidth is approximately 450 MHz and the sampling speed is adjustable from 0.076 to 3.2 Gsps (Gigabit Samples Per Second). For precision waveform timing extraction, careful calibration of timing intervals between samples is conducted to improve the timing resolution of such chips, and the timing precision of this ASIC is proved to be better than 15 ps RMS.

Asic developments for radiation imaging applications: The medipix and timepix family

Science.gov (United States)

Ballabriga, Rafael; Campbell, Michael; Llopart, Xavier

2018-01-01

Hybrid pixel detectors were developed to meet the requirements for tracking in the inner layers at the LHC experiments. With low input capacitance per channel (10-100 fF) it is relatively straightforward to design pulse processing readout electronics with input referred noise of ∼ 100 e-rms and pulse shaping times consistent with tagging of events to a single LHC bunch crossing providing clean 'images' of the ionising tracks generated. In the Medipix Collaborations the same concept has been adapted to provide practically noise hit free imaging in a wide range of applications. This paper reports on the development of three generations of readout ASICs. Two distinctive streams of development can be identified: the Medipix ASICs which integrate data from multiple hits on a pixel and provide the images in the form of frames and the Timepix ASICs who aim to send as much information about individual interactions as possible off-chip for further processing. One outstanding circumstance in the use of these devices has been their numerous successful applications, thanks to a large and active community of developers and users. That process has even permitted new developments for detectors for High Energy Physics. This paper reviews the ASICs themselves and details some of the many applications.

Acid sensing ion channel (ASIC) inhibitors exhibit anxiolytic-like activity in preclinical pharmacological models.

Science.gov (United States)

Dwyer, Jason M; Rizzo, Stacey J Sukoff; Neal, Sarah J; Lin, Qian; Jow, Flora; Arias, Robert L; Rosenzweig-Lipson, Sharon; Dunlop, John; Beyer, Chad E

2009-03-01

Acid sensing ion channels (ASICs) are proton-gated ion channels located in the central and peripheral nervous systems. Of particular interest is ASIC1a, which is located in areas associated with fear and anxiety behaviors. Recent reports suggest a role for ASIC1a in preclinical models of fear conditioning and anxiety. The present experiments evaluated various ASIC inhibitors in preclinical models of autonomic and behavioral parameters of anxiety. In addition, neurochemical studies evaluated the effects of an ASIC inhibitor (A-317567) on neurotransmitter levels in the amygdala. In electrophysiological studies using hippocampal primary neuronal cultures, three ASIC inhibitors (PcTX-1, A-317567, and amiloride) produced concentration-dependent inhibition of acid-evoked currents. In the stress-induced hyperthermia model, acute administration of psalmotoxin 1 (PcTX-1; 10-56 ng, i.c.v.), A-317567 (0.1-1.0 mg/kg, i.p.), and amiloride (10-100 mg/kg, i.p.) prevented stress-induced elevations in core body temperature. In the four-plate test, acute treatment with PcTX-1 (10-56 ng, i.c.v.) and A-317567 (0.01-0.1 mg/kg, i.p.), but not amiloride (3-100 mg/kg, i.p.), produced dose-dependent and significant increases in the number of punished crossings relative to vehicle-treated animals. Additionally, PcTX-1 (56-178 ng, i.c.v.), A-317567 (0.1-10 mg/kg, i.p.), and amiloride (10-100 mg/kg, i.p.) lacked significant anxiolytic-like activity in the elevated zero maze. In neurochemical studies, an infusion of A-317567 (100 microM) into the amygdala significantly elevated the extracellular levels of GABA, but not glutamate, in this brain region. These findings demonstrate that ASIC inhibition produces anxiolytic-like effects in some behavioral models and indicate a potential role for GABAergic mechanisms to underlie these anxiolytic-like effects.

A Low Power Application-Specific Integrated Circuit (ASIC) Implementation of Wavelet Transform/Inverse Transform

National Research Council Canada - National Science Library

Harvala, Daniel

2001-01-01

.... The ASIC is based on an existing four-chip FPGA implementation. Implementing the design using a dedicated ASIC enhances the speed, decreases chip count to a single die, and uses significantly less power compared to the FPGA implementation...

40 CFR 63.487 - Batch front-end process vents-reference control technology.

Science.gov (United States)

2010-07-01

... § 63.487 Batch front-end process vents—reference control technology. (a) Batch front-end process vents... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents-reference control technology. 63.487 Section 63.487 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY...

Front-end electronics for the upgraded GMRT

International Nuclear Information System (INIS)

Raut, Anil N; Bhalerao, Vilas; Kumar, A Praveen

2013-01-01

This paper first describes briefly the existing front-end receiver in use at the GMRT observatory and then details the ongoing development of next generation receiver systems for the upgraded GMRT. It covers the design of the new, two stage, room temperature, low noise amplifiers with better noise performance and matching, and improved dynamic range that are being implemented for the 130–260 MHz, 250–500 MHz and 550–900 MHz bands of the upgraded GMRT front-end systems.

ASIC1a Deficient Mice Show Unaltered Neurodegeneration in the Subacute MPTP Model of Parkinson Disease.

Directory of Open Access Journals (Sweden)

Daniel Komnig

Full Text Available Inflammation contributes to the death of dopaminergic neurons in Parkinson disease and can be accompanied by acidification of extracellular pH, which may activate acid-sensing ion channels (ASIC. Accordingly, amiloride, a non-selective inhibitor of ASIC, was protective in an acute 1-methyl-4-phenyl-1,2,3,6-tetrahydropyridine (MPTP mouse model of Parkinson disease. To complement these findings we determined MPTP toxicity in mice deficient for ASIC1a, the most common ASIC isoform in neurons. MPTP was applied i.p. in doses of 30 mg per kg on five consecutive days. We determined the number of dopaminergic neurons in the substantia nigra, assayed by stereological counting 14 days after the last MPTP injection, the number of Nissl positive neurons in the substantia nigra, and the concentration of catecholamines in the striatum. There was no difference between ASIC1a-deficient mice and wildtype controls. We are therefore not able to confirm that ASIC1a are involved in MPTP toxicity. The difference might relate to the subacute MPTP model we used, which more closely resembles the pathogenesis of Parkinson disease, or to further targets of amiloride.

Characterization of low-mass deformable mirrors and ASIC drivers for high-contrast imaging

Science.gov (United States)

Mejia Prada, Camilo; Yao, Li; Wu, Yuqian; Roberts, Lewis C.; Shelton, Chris; Wu, Xingtao

2017-09-01

The development of compact, high performance Deformable Mirrors (DMs) is one of the most important technological challenges for high-contrast imaging on space missions. Microscale Inc. has fabricated and characterized piezoelectric stack actuator deformable mirrors (PZT-DMs) and Application-Specific Integrated Circuit (ASIC) drivers for direct integration. The DM-ASIC system is designed to eliminate almost all cables, enabling a very compact optical system with low mass and low power consumption. We report on the optical tests used to evaluate the performance of the DM and ASIC units. We also compare the results to the requirements for space-based high-contrast imaging of exoplanets.

Digital Heart-Rate Variability Parameter Monitoring and Assessment ASIC.

Science.gov (United States)

Massagram, W; Hafner, N; Mingqi Chen; Macchiarulo, L; Lubecke, V M; Boric-Lubecke, O

2010-02-01

This paper describes experimental results for an application-specific integrated circuit (ASIC), designed for digital heart rate variability (HRV) parameter monitoring and assessment. This ASIC chip measures beat-to-beat (RR) intervals and stores HRV parameters into its internal memory in real time. A wide range of short-term and long-term ECG signals obtained from Physionet was used for testing. The system detects R peaks with millisecond accuracy, and stores up to 2 min of continuous RR interval data and up to 4 min of RR interval histogram. The prototype chip was fabricated in a 0.5 ¿m complementary metal-oxide semiconductor technology on a 3×3 mm(2) die area, with a measured dynamic power consumption of 10 ¿W and measured leakage current of 2.62 nA. The HRV monitoring system including this HRV ASIC, an analog-to-digital converter, and a low complexity microcontroller was estimated to consume 32.5 ¿V, which is seven times lower power than a stand-alone microcontroller performing the same functions. Compact size, low cost, and low power consumption make this chip suitable for a miniaturized portable HRV monitoring system.

A Low-Power Correlator ASIC for Arrays with Many Antennas

Science.gov (United States)

D'Addario, Larry R.; Wang, Douglas

2016-01-01

We report the design of a new application-specific integrated circuit (ASIC) for use in radio telescope correlators. It supports the construction of correlators for an arbitrarily large number of signals. The ASIC uses an intrinsically low-power architecture along with design techniques and a process that together result in unprecedentedly low power consumption. The design is flexible in that it can support telescopes with almost any number of antennas N. It is intended for use in an "FX" correlator, where a uniform filter bank breaks each signal into separate frequency channels prior to correlation.

Magnet Misalignment Studies for the Front-end of the Neutrino Factory

CERN Document Server

Prior, G; Stratakis, D; Neuffer, D; Snopok, P; Rogers, C

2013-01-01

In the Neutrino Factory front-end the muon beam coming from the interaction of a high-power (4 MW) proton beam on a mercury jet target is transformed through a buncher, a phase rotator and an ionization cooling channel before entering the downstream acceleration system. The muon front-end channel is densely packed with solenoid magnets, normal conducting radio-frequency cavities and absorber windows for the cooling section. The tolerance to the misalignment of the different components has to be determined in order on one hand to set the limits beyond which the performance of the front-end channel would be degraded; on the other hand to optimize the design and assembly of the front-end cells such that the component alignment can be checked and corrected for where crucial for the performance of the channel. In this paper we show the results of some of the simulations of the frontend channel performance where the magnetic field direction has been altered compared to the baseline.

Development of wide range charge integration application specified integrated circuit for photo-sensor

Energy Technology Data Exchange (ETDEWEB)

Katayose, Yusaku, E-mail: katayose@ynu.ac.jp [Department of Physics, Yokohama National University, 79-5 Tokiwadai, Hodogaya-ku, Yokohama, Kanagawa 240-8501 (Japan); Ikeda, Hirokazu [Institute of Space and Astronautical Science (ISAS)/Japan Aerospace Exploration Agency (JAXA), 3-1-1 Yoshinodai, Chuo-ku, Sagamihara, Kanagawa 252-5210 (Japan); Tanaka, Manobu [National Laboratory for High Energy Physics, KEK, 1-1 Oho, Tsukuba, Ibaraki 305-0801 (Japan); Shibata, Makio [Department of Physics, Yokohama National University, 79-5 Tokiwadai, Hodogaya-ku, Yokohama, Kanagawa 240-8501 (Japan)

2013-01-21

A front-end application specified integrated circuit (ASIC) is developed with a wide dynamic range amplifier (WDAMP) to read-out signals from a photo-sensor like a photodiode. The WDAMP ASIC consists of a charge sensitive preamplifier, four wave-shaping circuits with different amplification factors and Wilkinson-type analog-to-digital converter (ADC). To realize a wider range, the integrating capacitor in the preamplifier can be changed from 4 pF to 16 pF by a two-bit switch. The output of a preamplifier is shared by the four wave-shaping circuits with four gains of 1, 4, 16 and 64 to adapt the input range of ADC. A 0.25-μm CMOS process (of UMC electronics CO., LTD) is used to fabricate the ASIC with four-channels. The dynamic range of four orders of magnitude is achieved with the maximum range over 20 pC and the noise performance of 0.46 fC + 6.4×10{sup −4} fC/pF. -- Highlights: ► A front-end ASIC is developed with a wide dynamic range amplifier. ► The ASIC consists of a CSA, four wave-shaping circuits and pulse-height-to-time converters. ► The dynamic range of four orders of magnitude is achieved with the maximum range over 20 pC.

Frontend electronics for high-precision single photo-electron timing using FPGA-TDCs

Energy Technology Data Exchange (ETDEWEB)

Cardinali, Matteo [Helmholtz Institut Mainz (Germany); Collaboration: PANDA Cherenkov-Collaboration

2014-07-01

The next generation of high-luminosity experiments requires excellent Particle Identification (PID) detectors which calls for Imaging Cherenkov counters with fast electronics to cope with the expected data rates. The planned PANDA experiment at FAIR expects average interaction rates of 20 MHz. A Barrel DIRC will provide PID in the central region of the Target Spectrometer. A single photo-electron timing resolution of better than 100 ps is projected for the Barrel DIRC to disentangle the complicated patterns created by the focusing optics on the image plane. The typically large amount of readout channels (approx 15,000 in case of the PANDA Barrel DIRC) places non-negligible limits on size and power consumption of the Front-End Electronics (FEE). The proposed design is based on the TRBv3 readout using FPGA-TDCs with a precision better than 20 ps RMS and custom FEE with high-bandwidth pre-amplifiers and fast discriminators. Two types of FEE cards optimised for reading out 64-channel Photonis Planacon MCP-PMTs were tested: one based on the NINO ASIC developed for the ALICE RPC readout and the other, called PaDiWa, using FPGA-based discriminators. Both types of FEE cards were tested with a small DIRC prototype comprising a radiator bar with focusing lens and an oil-filled expansion volume instrumented with 6 Planacon 64-channel MCP-PMTs. In the presentation the result of a test experiment performed at MAMI B, Mainz, are addressed.

Driver ASICs for Advanced Deformable Mirrors, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — The overall goal of the SBIR program is to develop a new Application Specified Integrated Circuit (ASIC) driver to be used in driver electronics of a deformable...

MMIC tuned front-end for a coherent optical receiver

DEFF Research Database (Denmark)

Petersen, Anders Kongstad; Jagd, A. M.; Ebskamp, F.

1993-01-01

A low-noise transformer tuned optical front-end for a coherent optical receiver is described. The front-end is based on a GaInAs/InP p-i-n photodiode and a full custom designed GaAs monolithic microwave integrated circuit (MMIC). The measured equivalent input noise current density is between 5-16 p...

Low-power digital ASIC for on-chip spectral analysis of low-frequency physiological signals

International Nuclear Information System (INIS)

Nie Zedong; Zhang Fengjuan; Li Jie; Wang Lei

2012-01-01

A digital ASIC chip customized for battery-operated body sensing devices is presented. The ASIC incorporates a novel hybrid-architecture fast Fourier transform (FFT) unit that is capable of scalable spectral analysis, a licensed ARM7TDMI IP hardcore and several peripheral IP blocks. Extensive experimental results suggest that the complete chip works as intended. The power consumption of the FFT unit is 0.69 mW at 1 MHz with 1.8 V power supply. The low-power and programmable features of the ASIC make it suitable for ‘on-the-fly’ low-frequency physiological signal processing. (semiconductor integrated circuits)

CMOS front-end electronics for radiation sensors

CERN Document Server

AUTHOR|(CDS)2071026

2015-01-01

This book offers a comprehensive treatment of front-end electronics for radiation detection. It discusses the fundamental principles of signal processing for radiation detectors and describes circuits at the level of functional building blocks, omitting transistor-level implementation. It also covers important system-level topics commonly found in the world of front-end electronics for radiation sensors. The book develops the topics in detail, with a constant focus on practical problems. It also provides real implementation examples that offer insights and stimuli for more experienced engineers already working in the field.

ASIC For Complex Fixed-Point Arithmetic

Science.gov (United States)

Petilli, Stephen G.; Grimm, Michael J.; Olson, Erlend M.

1995-01-01

Application-specific integrated circuit (ASIC) performs 24-bit, fixed-point arithmetic operations on arrays of complex-valued input data. High-performance, wide-band arithmetic logic unit (ALU) designed for use in computing fast Fourier transforms (FFTs) and for performing ditigal filtering functions. Other applications include general computations involved in analysis of spectra and digital signal processing.

ASIC1a regulates insular long-term depression and is required for the extinction of conditioned taste aversion

OpenAIRE

Li, Wei-Guang; Liu, Ming-Gang; Deng, Shining; Liu, Yan-Mei; Shang, Lin; Ding, Jing; Hsu, Tsan-Ting; Jiang, Qin; Li, Ying; Li, Fei; Zhu, Michael Xi; Xu, Tian-Le

2016-01-01

Acid-sensing ion channel 1a (ASIC1a) has been shown to play important roles in synaptic plasticity, learning and memory. Here we identify a crucial role for ASIC1a in long-term depression (LTD) at mouse insular synapses. Genetic ablation and pharmacological inhibition of ASIC1a reduced the induction probability of LTD without affecting that of long-term potentiation in the insular cortex. The disruption of ASIC1a also attenuated the extinction of established taste aversion memory without alte...

Monolithic Active Pixel Matrix with Binary Counters ASIC with nested wells

International Nuclear Information System (INIS)

Fahim, F; Deptuch, G; Holm, S; Shenai, A; Lipton, R

2013-01-01

Monolithic Active Matrix with Binary Counters (MAMBO) V ASIC has been designed for detecting and measuring low energy X-rays. A nested well structure with a buried n-well (BNW) and a deeper buried p-well (BPW) is used to electrically isolate the detector from the electronics. BNW acts as an AC ground to electrical signals and behaves as a shield. BPW allows for a homogenous electric field in the entire detector volume. The ASIC consists of a matrix of 50 × 52 pixels, each of 105x105μm 2 . Each pixel contains analog functionality accomplished by a charge preamplifier, CR-RC 2 shaper and a baseline restorer. It also contains a window comparator with Upper and Lower thresholds which can be individually trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit counter which is reconfigured as a shift register to serially output the data from the entire ASIC.

FROST: an ASIC for digital mammography with synchrotron radiation

International Nuclear Information System (INIS)

Bergamaschi, A.; Prest, M.; Vallazza, E.; Arfelli, F.; Dreossi, D.; Longo, R.; Olivo, A.; Pani, S.; Castelli, E.

2003-01-01

The FRONTier RADiography (FRONTRAD) collaboration is developing a digital system for mammography at the Elettra Synchrotron Light Source in Trieste. The system is based on a silicon microstrip detector array. The ASIC FROST (FRONTRAD Read Out sySTem) was developed as a collaboration between INFN Trieste and Aurelia Microelettronica and is designed to operate in single photon counting mode. FROST provides low-noise and high-gain performances and is able to work at incident photon rates higher than 100 kHz with almost 100% efficiency. The ASIC has been tested and the first images of mammographic test objects will be shown. The acquisition time per breast image should be of about 10 s

Terahertz performance of quasioptical front-ends with a hotelectron bolometer

International Nuclear Information System (INIS)

Semenov, A; Richter, H; Guenther, B; Huebers, H-W; Karamarkovic, J

2006-01-01

We present terahertz performance of quasioptical front-ends consisting of a hotelectron bolometer imbedded in a planar feed antenna and integrated with an immersion lens. The impedance and radiation pattern of the log-spiral and double-slot planar feeds are evaluated using the method of moments; the collimating action of the lens is modelled using the physical optics. The total efficiency of the front-ends is computed taking into account frequency dependent impedance of the bolometer. Measured performance of the front-ends qualifies the simulation technique as a reliable tool for the design of terahertz receivers

Multichannel wireless ECoG array ASIC devices.

Science.gov (United States)

DeMichele, Glenn A; Cogan, Stuart F; Troyk, Philip R; Chen, Hongnan; Hu, Zhe

2014-01-01

Surgical resection of epileptogenic foci is often a beneficial treatment for patients suffering debilitating seizures arising from intractable epilepsy [1], [2], [3]. Electrodes placed subdurally on the surface of the brain in the form of an ECoG array is one of the multiple methods for localizing epileptogenic zones for the purpose of defining the region for surgical resection. Currently, transcutaneous wires from ECoG grids limit the duration of time that implanted grids can be used for diagnosis. A wireless ECoG recording and stimulation system may be a solution to extend the diagnostic period. To avoid the transcutaneous connections, a 64-channel wireless silicon recording/stimulating ASIC was developed as the electronic component of a wireless ECoG array that uses SIROF electrodes on a polyimide substrate[4]. Here we describe two new ASIC devices that have been developed and tested as part of the on-going wireless ECoG system design.

Indigenous design and development of digital ASICs

International Nuclear Information System (INIS)

Misra, M.K.; Kishore, G.V.; Sridhar, N.; Palanisami, K.; Thirugnana Murthy, D.

2013-01-01

FPGAs and CPLDs were extensively used for the design and development of Instrumentation and Control systems including safety systems of Prototype Fast Breeder Reactor (PFBR). The developed I and C systems have been tested extensively for their functionality and also undergone various qualification tests. Some of these I and C systems have also been deployed in Fast Breeder Test Reactor. The performance of these designs is found to be satisfactory. However FPGAs/CPLDs are rapidly evolving and the devices become obsolete in a short span of time (typically about 5 to 8 years), whereas reactor's life time is typically about 40 years. This obsolescence problem can be handled in different ways. This paper discusses design and fabrication of digital ASICs as one of the alternate for handling obsolescence problems. Aim of this development work is to establish complete digital ASIC design, fabrication and testing flow, so that the same can be used in some of the critical/strategic requirements. (author)

Role of TRPV1 and ASIC3 channels in experimental occlusal interference-induced hyperalgesia in rat masseter muscle.

Science.gov (United States)

Xu, X X; Cao, Y; Ding, T T; Fu, K Y; Li, Y; Xie, Q F

2016-04-01

Masticatory muscle pain may occur following immediate occlusal alteration by dental treatment. The underlying mechanisms are poorly understood. Transient receptor potential vanilloid-1 (TRPV1) and acid-sensing ion channel-3 (ASIC3) mediate muscle hyperalgesia under various pathologic conditions. We have developed a rat model of experimental occlusal interference (EOI) that consistently induces mechanical hyperalgesia in jaw muscles. Whether TRPV1 and ASIC3 mediate this EOI-induced hyperalgesia is unknown. Rat model of EOI-induced masseter hyperalgesia was established. Real-time polymerase chain reaction, Western blot and retrograde labelling combined with immunofluorescence were performed to evaluate the modulation of TRPV1 and ASIC3 expression in trigeminal ganglia (TGs) and masseter afferents of rats after EOI. The effects of intramuscular administration of TRPV1 and ASIC3 antagonists on the EOI-induced hyperalgesia in masseter muscle were examined. After EOI, gene expressions and protein levels of TRPV1 and ASIC3 in bilateral TGs were up-regulated. The percentage of ASIC3- (but not TRPV1-) positive neurons in masseter afferents increased after EOI. More small-sized and small to medium-sized masseter afferents expressed TRPV1 and ASIC3 separately following EOI. These changes peaked at day 7 and then returned to original status within 10 days after EOI. Intramuscular administration of the TRPV1 antagonist AMG-9810 partially reversed this mechanical hyperalgesia in masseter muscle. No improvement was exhibited after administration of the ASIC3 antagonist APETx2. Co-injection of AMG-9810 and APETx2 enhanced the effect of AMG-9810 administration alone. Peripheral TRPV1 and ASIC3 contribute to the development of the EOI-induced mechanical hyperalgesia in masseter muscle. © 2015 European Pain Federation - EFIC®

Tunable multiband ferroelectric devices for reconfigurable RF-frontends

CERN Document Server

Zheng, Yuliang

2013-01-01

Reconfigurable RF-frontends aim to cope with the continuous pursuit of wider frequency coverage, higher efficiency, further compactness and lower cost of ownership. They are expected to lay the foundations of future software defined or cognitive radios. As a potential enabling technology for the frontends, the tunable ferroelectric devices have shown not only enhanced performance but also new functionalities. This book explores the recent developments in the field. It provides a cross-sectional perspective on the interdisciplinary research. With attention to the devices based on ceramic thick-films and crystal thin-films, the book reviews the adapted technologies of material synthesis, film deposition and multilayer circuitry. Next, it highlights the original classes of thin-film ferroelectric devices, including stratified metal-insulator-metal varactors with suppression of acoustic resonance and programmable bi-stable high frequency capacitors. At the end the book analyzes how the frontends can be reformed b...

Simulation of frontend preamplifiers for the MSGC

International Nuclear Information System (INIS)

Schmitz, J.

1993-01-01

Two candidate architectures for frontend preamplifiers for the Microstrip Gas Counter are tested using a Monte Carlo simulation of the detector and frontend. The simulation describes ionisation in the gas, electron drift and diffusion, gas amplification, signal development and the discriminator. The first architecture is based on the current design of the Fastplex, while the alternative design uses a subtraction method. The simulations indicate that the current Fastplex-design matches the MSGC best when the shaping time is as high as possible (around 50 ns). The signal is extracted more accurately with the alternative design. (orig.)

A multichannel front end ASIC for PMT readout in LHAASO WCDA

Science.gov (United States)

Liang, Y.; Zhao, L.; Guo, Y.; Qin, J.; Yang, Y.; Cheng, B.; Liu, S.; An, Q.

2018-01-01

Time and charge measurements over a large dynamic range from 1 Photo Electron (P.E.) to 4000 P.E. are required for the Water Cherenkov Detector Array (WCDA), which is one of the key components in the Large High Altitude Air Shower Observatory (LHAASO). To simplify the circuit structure of the readout electronics, a front end ASIC was designed. Based on the charge-to-time conversion method, the output pulse width of the ASIC corresponds to the input signal charge information while time information of the input signal is picked off through a discriminator, and thus the time and charge information can be digitized simultaneously using this ASIC and a following Time-to-Digital Converter (TDC). To address the challenge of mismatch among the channels observed in the previous prototype version, this work presents approaches for analyzing the problem and optimizing the circuits. A new version of the ASIC was designed and fabricated in the GLOBALFOUNDRIES 0.35 μm CMOS technology, which integrates 6 channels (corresponding to the readout of the 3 PMTs) in each chip. The test results indicate that the mismatch between the channels is significantly reduced to less than 20% using the proposed approach. The time measurement resolution better than 300 ps is achieved, and the charge measurement resolution is better than 10% at 1 P.E., and 1% at 4000 P.E., which meets the application requirements.

ASIC and HMC designs for portable nuclear instruments

International Nuclear Information System (INIS)

Chandratre, V.B.

2005-01-01

This paper describes the seed activity done so far for realizing the goal of compact portable nuclear instruments and related instrumentation that can be designed, developed and manufactured without external constraints. This important activity requires critical components to be made in the country by tapping and gearing the established industrial units for this activity. A good deal of ground work has been carried out over a period of time in setting up IC design facility and CAD-FAB interface. There has been a close interaction with the production and semiconductor facilities to design and develop ASIC, hybrids, display devices, detectors/sensors etc. Efforts are also undertaken to develop the critical technologies that are required to fulfill the requirement. A status report on various technologies, ASIC, hybrids and their application development done in the face of out-standing challenges is being presented here. (author)

ASIC and ENaC type sodium channels: conformational states and the structures of the ion selectivity filters.

Science.gov (United States)

Hanukoglu, Israel

2017-02-01

The acid-sensing ion channels (ASICs) and epithelial sodium channels (ENaC) are members of a superfamily of channels that play critical roles in mechanosensation, chemosensation, nociception, and regulation of blood volume and pressure. These channels look and function like a tripartite funnel that directs the flow of Na + ions into the cytoplasm via the channel pore in the membrane. The subunits that form these channels share a common structure with two transmembrane segments (TM1 and TM2) and a large extracellular part. In most vertebrates, there are five paralogous genes that code for ASICs (ASIC1-ASIC5), and four for ENaC subunits alpha, beta, gamma, and delta (α, β, γ, and δ). While ASICs can form functional channels as a homo- or heterotrimer, ENaC functions as an obligate heterotrimer composed of α-β-γ or β-γ-δ subunits. The structure of ASIC has been determined in several conformations, including desensitized and open states. This review presents a comparison of the structures of these states using easy-to-understand molecular models of the full complex, the central tunnel that includes an outer vestibule, the channel pore, and ion selectivity filter. The differences in the secondary, tertiary, and quaternary structures of the states are summarized to pinpoint the conformational changes responsible for channel opening. Results of site-directed mutagenesis studies of ENaC subunits are examined in light of ASIC1 models. Based on these comparisons, a molecular model for the selectivity filter of ENaC is built by in silico mutagenesis of an ASIC1 structure. These models suggest that Na + ions pass through the filter in a hydrated state. © 2016 Federation of European Biochemical Societies.

Differential regulation of proton-sensitive ion channels by phospholipids: a comparative study between ASICs and TRPV1.

Directory of Open Access Journals (Sweden)

Hae-Jin Kweon

Full Text Available Protons are released in pain-generating pathological conditions such as inflammation, ischemic stroke, infection, and cancer. During normal synaptic activities, protons are thought to play a role in neurotransmission processes. Acid-sensing ion channels (ASICs are typical proton sensors in the central nervous system (CNS and the peripheral nervous system (PNS. In addition to ASICs, capsaicin- and heat-activated transient receptor potential vanilloid 1 (TRPV1 channels can also mediate proton-mediated pain signaling. In spite of their importance in perception of pH fluctuations, the regulatory mechanisms of these proton-sensitive ion channels still need to be further investigated. Here, we compared regulation of ASICs and TRPV1 by membrane phosphoinositides, which are general cofactors of many receptors and ion channels. We observed that ASICs do not require membrane phosphatidylinositol 4-phosphate (PI(4P or phosphatidylinositol 4,5-bisphosphate (PI(4,5P2 for their function. However, TRPV1 currents were inhibited by simultaneous breakdown of PI(4P and PI(4,5P2. By using a novel chimeric protein, CF-PTEN, that can specifically dephosphorylate at the D3 position of phosphatidylinositol 3,4,5-trisphosphate (PI(3,4,5P3, we also observed that neither ASICs nor TRPV1 activities were altered by depletion of PI(3,4,5P3 in intact cells. Finally, we compared the effects of arachidonic acid (AA on two proton-sensitive ion channels. We observed that AA potentiates the currents of both ASICs and TRPV1, but that they have different recovery aspects. In conclusion, ASICs and TRPV1 have different sensitivities toward membrane phospholipids, such as PI(4P, PI(4,5P2, and AA, although they have common roles as proton sensors. Further investigation about the complementary roles and respective contributions of ASICs and TRPV1 in proton-mediated signaling is necessary.

Extreme Temperature, Rad-Hard Power Management ASIC, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — Ridgetop Group will design a rad-hard Application Specific Integrated Circuit (ASIC) for spacecraft power management that is functional over a temperature range of...

Active counter electrode in a-SiC electrochemical metallization memory

Science.gov (United States)

Morgan, K. A.; Fan, J.; Huang, R.; Zhong, L.; Gowers, R.; Ou, J. Y.; Jiang, L.; De Groot, C. H.

2017-08-01

Cu/amorphous-SiC (a-SiC) electrochemical metallization memory cells have been fabricated with two different counter electrode (CE) materials, W and Au, in order to investigate the role of CEs in a non-oxide semiconductor switching matrix. In a positive bipolar regime with Cu filaments forming and rupturing, the CE influences the OFF state resistance and minimum current compliance. Nevertheless, a similarity in SET kinetics is seen for both CEs, which differs from previously published SiO2 memories, confirming that CE effects are dependent on the switching layer material or type. Both a-SiC memories are able to switch in the negative bipolar regime, indicating Au and W filaments. This confirms that CEs can play an active role in a non-oxide semiconducting switching matrix, such as a-SiC. By comparing both Au and W CEs, this work shows that W is superior in terms of a higher R OFF/R ON ratio, along with the ability to switch at lower current compliances making it a favourable material for future low energy applications. With its CMOS compatibility, a-SiC/W is an excellent choice for future resistive memory applications.

Modulation of ASIC channels in rat cerebellar purkinje neurons by ischaemia-related signals

Science.gov (United States)

Allen, Nicola J; Attwell, David

2002-01-01

Acid-sensing ion channels (ASICs), activated by a decrease of extracellular pH, are found in neurons throughout the nervous system. They have an amino acid sequence similar to that of ion channels activated by membrane stretch, and have been implicated in touch sensation. Here we characterize the pH-dependent activation of ASICs in cerebellar Purkinje cells and investigate how they are modulated by factors released in ischaemia. Lowering the external pH from 7.4 activated an inward current at −66 mV, carried largely by Na+ ions, which was half-maximal for a step to pH 6.4 and was blocked by amiloride and gadolinium. The H+-gated current desensitized within a few seconds, but approximately 30% of cells showed a sustained inward current (11% of the peak current) in response to the maintained presence of pH 6 solution. The peak H+-evoked current was potentiated by membrane stretch (which occurs in ischaemia when [K+]o rises) and by arachidonic acid (which is released when [Ca2+]i rises in ischaemia). Arachidonic acid increased to 77% the fraction of cells showing a sustained current evoked by acid pH. The ASIC currents were also potentiated by lactate (which is released when metabolism becomes anaerobic in ischaemia) and by FMRFamide (which may mimic the action of related mammalian RFamide transmitters). These data reinforce suggestions of a mechanosensory aspect to ASIC channel function, and show that the activation of ASICs reflects the integration of multiple signals which are present during ischaemia. PMID:12205186

A Radiation Hardened Housekeeping Slave Node (RH-HKSN) ASIC

Data.gov (United States)

National Aeronautics and Space Administration — This projects seeks to continue the development of the Radiation Hardened Housekeeping Slave Node (RH-HKSN) ASIC. The effort has taken parallel paths by implementing...

Application specific integrated circuit (ASIC) readout technologies for future ion beam analytical instruments

Energy Technology Data Exchange (ETDEWEB)

Whitlow, Harry J. E-mail: harry_j.whitlow@nuclear.lu.se

2000-03-01

New possibilities for ion beam analysis (IBA) are afforded by recent developments in detector technology which facilitate the parallel collection of data from a large number of channels. Application specific integrated circuit (ASIC) technologies, which have been widely employed for multi-channel readout systems in nuclear and particle physics, are more net-cost effective (160/channel for 1000 channels) and a more rational solution for readout of a large number of channels than afforded by conventional electronics. Based on results from existing and on-going chip designs, the possibilities and issues of ASIC readout technology are considered from the IBA viewpoint. Consideration is given to readout chip architecture and how the stringent resolution, linearity and stability requirements for IBA may be met. In addition the implications of the restrictions imposed by ASIC technology are discussed.

A low noise ASIC for two dimensional neutron gas detector with performance of high spatial resolution (Contract research)

International Nuclear Information System (INIS)

Yamagishi, Hideshi; Toh, Kentaro; Nakamura, Tatsuya; Sakasai, Kaoru; Soyama, Kazuhiko

2012-02-01

An ASD-ASIC (Amplifier-Shaper-Discriminator ASIC) with fast response and low noise performances has been designed for two-dimensional position sensitive neutron gas detectors (InSPaD). The InSPaD is a 2D neutron detector system with 3 He gas and provides a high spatial resolution by making distinction between proton and triton particles generated in the gas chamber. The new ASD-ASIC is required to have very low noise, a wide dynamic range, good output linearity and high counting rate. The new ASD-ASIC has been designed by using CMOS and consisted of 64-channel ASDs, a 16-channel multiplexer with LVTTL drivers and sum amplifier system for summing all analog signals. The performances were evaluated by the Spice simulation. It was confirmed that the new ASD-ASIC had very low noise performance, wide dynamic range and fast signal processing functions. (author)

A Muscle Fibre Conduction Velocity Tracking ASIC for Local Fatigue Monitoring.

Science.gov (United States)

Koutsos, Ermis; Cretu, Vlad; Georgiou, Pantelis

2016-12-01

Electromyography analysis can provide information about a muscle's fatigue state by estimating Muscle Fibre Conduction Velocity (MFCV), a measure of the travelling speed of Motor Unit Action Potentials (MUAPs) in muscle tissue. MFCV better represents the physical manifestations of muscle fatigue, compared to the progressive compression of the myoelectic Power Spectral Density, hence it is more suitable for a muscle fatigue tracking system. This paper presents a novel algorithm for the estimation of MFCV using single threshold bit-stream conversion and a dedicated application-specified integrated circuit (ASIC) for its implementation, suitable for a compact, wearable and easy to use muscle fatigue monitor. The presented ASIC is implemented in a commercially available AMS 0.35 [Formula: see text] CMOS technology and utilizes a bit-stream cross-correlator that estimates the conduction velocity of the myoelectric signal in real time. A test group of 20 subjects was used to evaluate the performance of the developed ASIC, achieving good accuracy with an error of only 3.2% compared to Matlab.

Development of n+-in-p planar pixel quadsensor flip-chipped with FE-I4 readout ASICs

International Nuclear Information System (INIS)

Unno, Y.; Hanagaki, K.; Hori, R.; Ikegami, Y.; Nakamura, K.; Takubo, Y.; Kamada, S.; Yamamura, K.; Yamamoto, H.; Takashima, R.; Tojo, J.; Kono, T.; Nagai, R.; Saito, S.; Sugibayashi, K.; Hirose, M.; Jinnouchi, O.; Sato, S.; Sawai, H.; Hara, K.

2017-01-01

We have developed flip-chip modules applicable to the pixel detector for the HL-LHC. New radiation-tolerant n + -in-p planar pixel sensors of a size of four FE-I4 application-specific integrated circuits (ASICs) are laid out in a 6-in wafer. Variation in readout connection for the pixels at the boundary of ASICs is implemented in the design of quadsensors. Bump bonding technology is developed for four ASICs onto one quadsensor. Both sensors and ASICs are thinned to 150 μm before bump bonding, and are held flat with vacuum chucks. Using lead-free SnAg solder bumps, we encounter deficiency with large areas of disconnected bumps after thermal stress treatment, including irradiation. Surface oxidation of the solder bumps is identified as a critical source of this deficiency after bump bonding trials, using SnAg bumps with solder flux, indium bumps, and SnAg bumps with a newly-introduced hydrogen-reflow process. With hydrogen-reflow, we establish flux-less bump bonding technology with SnAg bumps, appropriate for mass production of the flip-chip modules with thin sensors and thin ASICs.

Design and screening of ASIC inhibitors based on aromatic diamidines for combating neurological disorders.

Science.gov (United States)

Chen, Xuanmao; Orser, Beverley A; MacDonald, John F

2010-12-01

Acid sensing ion channels (ASICs) are implicated in various brain functions including learning and memory and are involved in a number of neurological disorders such as pain, ischemic stroke, depression, and multiple sclerosis. We have recently defined ASICs as one of receptor targets of aromatic diamidines in neurons. Aromatic diamidines are DNA-binding agents and have long been used in the treatment of leishmaniasis, trypanosomiasis, pneumocystis pneumonia and babesiosis. Moreover, some aromatic diamidines are used as skin-care and baby products and others have potential to suppress tumor growth or to combat malaria. A large number of aromatic diamidines or analogs have been synthesized. Many efforts are being made to optimize the therapeutic spectrum of aromatic diamidines, i.e. to reduce toxicity, increase oral bioavailability and enhance their penetration of the blood-brain barrier. Aromatic diamidines therefore provide a shortcut of screening for selective ASIC inhibitors with therapeutic potential. Intriguingly nafamostat, a protease inhibitor for treating acute pancreatitis, also inhibits ASIC activities. Aromatic diamidines and nafamostat have many similarities although they belong to distinct classes of medicinal agents for curing different diseases. Here we delineate background, clinical application and drug development of aromatic diamidines that could facilitate the screening for selective ASIC inhibitors for research purposes. Further studies may lead to a drug with therapeutic value and extend the therapeutic scope of aromatic diamidines to combat neurological diseases. Copyright © 2010 Elsevier B.V. All rights reserved.

VMM3, an ASIC for Micropattern Detectors

CERN Document Server

Iakovidis, Georgios; The ATLAS collaboration

2018-01-01

The VMM is a custom Application Specific Integrated Circuit (ASIC). It will be used in the front- end readout electronics of both the Micromegas and sTGC detectors of the New Small Wheel upgrade of the ATLAS experiment at CERN. It is being developed at Brookhaven National Laboratory and fabricated in the 130nm Global Foundries 8RF-DM process (former IBM 8RF- DM). The 64 channels ASIC has highly configurable parameters and is able to handle signals of opposite polarities and a high range of capacitances while being low noise and low on power consumption. The VMM has four independent data output paths. First is the “precision” (10-bit) amplitude and (effective) 20-bit time stamp read out continuously (250 ns dead-time per channel) or at when a trigger occurs. Second, a serial output called Address in Real Time (ART). This is the address of the channel which had a signal above threshold within the bunch crossing clock. Third, the parallel prompt outputs from all 64 channels in a variety of selectable formats...

A four channel time-to-digital converter ASIC with in-built calibration and SPI interface

International Nuclear Information System (INIS)

Hari Prasad, K.; Sukhwani, Menka; Saxena, Pooja; Chandratre, V.B.; Pithawa, C.K.

2014-01-01

A design of high resolution, wide dynamic range Time-to-Digital Converter (TDC) ASIC, implemented in 0.35 µm commercial CMOS technology is presented. The ASIC features four channel TDC with an in-built calibration and Serial Peripheral Interconnect (SPI) slave interface. The TDC is based on the vernier ring oscillator method in order to achieve both high resolution and wide dynamic range. This TDC ASIC is tested and found to have resolution of 127 ps (LSB), dynamic range of 1.8 µs and precision (σ) of 74 ps. The measured values of differential non-linearity (DNL) and integral non-linearity (INL) are 350 ps and 300 ps respectively

Resveratrol attenuates bone cancer pain through regulating the expression levels of ASIC3 and activating cell autophagy.

Science.gov (United States)

Zhu, Haili; Ding, Jieqiong; Wu, Ji; Liu, Tingting; Liang, Jing; Tang, Qiong; Jiao, Ming

2017-11-01

Bone cancer pain (BCP) is one of the most common pains in patients with malignant cancers. The mechanism underlying BCP is largely unknown. Our previous studies and the increasing evidence both have shown that acid-sensing ion channels 3 (ASIC3) is an important protein in the pathological pain state in some pain models. We hypothesized that the expression change of ASIC3 might be one of the factors related to BCP. In this study, we established the BCP model through intrathecally injecting rat mammary gland carcinoma cells (MRMT-1) into the left tibia of Sprague-Dawley female rats, and found that the BCP rats showed bone destruction, increased mechanical pain sensitivities and up-regulated ASIC3 protein expression levels in L4-L6 dorsal root ganglion. Then, resveratrol, which was intraperitoneally injected into the BCP rats on post-operative Day 21, dose-dependently increased the paw withdrawal threshold of BCP rats, reversed the pain behavior, and had an antinociceptive effect on BCP rats. In ASIC3-transfected SH-SY5Y cells, the ASIC3 protein expression levels were regulated by resveratrol in a dose- and time-dependent manner. Meanwhile, resveratrol also had an antinociceptive effect in ASIC3-mediated pain rat model. Furthermore, resveratrol also enhanced the phosphorylation of AMPK, SIRT1, and LC3-II levels in ASIC3-transfected SH-SY5Y cells, indicating that resveratrol could activate the AMPK-SIRT1-autophagy signal pathway in ASIC3-transfected SH-SY5Y cells. In BCP rats, SIRT1 and LC3-II were also down-regulated. These findings provide new evidence for the use of resveratrol as a therapeutic treatment during BCP states. © The Author 2017. Published by Oxford University Press on behalf of the Institute of Biochemistry and Cell Biology, Shanghai Institutes for Biological Sciences, Chinese Academy of Sciences. All rights reserved. For permissions, please e-mail: journals.permissions@oup.com.

A digital Front-End and Readout MIcrosystem for calorimetry at LHC

CERN Multimedia

2002-01-01

% RD-16 A Digital Front-End and Readout Microsystem for Calorimetry at LHC \\\\ \\\\Front-end signal processing for calorimetric detectors is essential in order to achieve adequate selectivity in the trigger function of an LHC experiment, with data identification and compaction before readout being required in the harsh, high rate environment of a high luminosity hadron machine. Other crucial considerations are the extremely wide dynamic range and bandwidth requirements, as well as the volume of data to be transferred to following stages of the trigger and readout system. These requirements are best met by an early digitalization of the detector information, followed by integrated digital signal processing and buffering functions covering the trigger latencies.\\\\ \\\\The FERMI (Front-End Readout MIcrosystem) is a digital implementation of the front-end and readout electronic chain for calorimeters. It is based on dynamic range compression, high speed A to D converters, a fully programmable pipeline/digital filter c...

ASIC design and data communications for the Boston retinal prosthesis.

Science.gov (United States)

Shire, Douglas B; Ellersick, William; Kelly, Shawn K; Doyle, Patrick; Priplata, Attila; Drohan, William; Mendoza, Oscar; Gingerich, Marcus; McKee, Bruce; Wyatt, John L; Rizzo, Joseph F

2012-01-01

We report on the design and testing of a custom application-specific integrated circuit (ASIC) that has been developed as a key component of the Boston retinal prosthesis. This device has been designed for patients who are blind due to age-related macular degeneration or retinitis pigmentosa. Key safety and communication features of the low-power ASIC are described, as are the highly configurable neural stimulation current waveforms that are delivered to its greater than 256 output electrodes. The ASIC was created using an 0.18 micron Si fabrication process utilizing standard 1.8 volt CMOS transistors as well as 20 volt lightly doped drain FETs. The communication system receives frequency-shift keyed inputs at 6.78 MHz from an implanted secondary coil, and transmits data back to the control unit through a lower-bandwidth channel that employs load-shift keying. The design's safety is ensured by on-board electrode voltage monitoring, stimulus charge limits, error checking of data transmitted to the implant, and comprehensive self-test and performance monitoring features. Each stimulus cycle is initiated by a transmitted word with a full 32-bit error check code. Taken together, these features allow researchers to safely and wirelessly tailor retinal stimulation and vision recovery for each patient.

Beam test performance of the SKIROC2 ASIC

CERN Document Server

Frisson, T; Anduze, M; Augustin, J.E; Bonis, J; Boudry, V; Bourgeois, C; Brient, J.C; Callier, S; Cerutti, M; Chen, S; Cornat, R; Cornebise, P; Cuisy, D; David, J; De la Taille, C; Dulucq, F; Frotin, M; Gastaldi, F; Ghislain, P; Giraud, J; Gonnin, A; Grondin, D; Guliyev, E; Hostachy, J.Y; Jeans, D; Kamiya, Y; Kawagoe, K; Kozakai, C; Lacour, D; Lavergne, L; Lee, S.H; Magniette, F; Ono, H; Poeschl, R; Rouëné, J; Seguin-Moreau, N; Song, H.S; Sudo, Y; Thiebault, A; Tran, H; Ueno, H; Van der Kolk, N; Yoshioka, T

2015-01-01

Beam tests of the first layers of CALICE silicon tungsten ECAL technological prototype were performed in April and July 2012 using 1–6 GeV electron beam at DESY. This paper presents an analysis of the SKIROC2 readout ASIC performance under test beam conditions.

STiC — a mixed mode silicon photomultiplier readout ASIC for time-of-flight applications

International Nuclear Information System (INIS)

Harion, T; Briggl, K; Chen, H; Gil, A; Kiworra, V; Schultz-Coulon, H-C; Shen, W; Stankova, V; Fischer, P; Ritzert, M

2014-01-01

STiC is an application specific integrated circuit (ASIC) for the readout of silicon photomultipliers. The chip has been designed to provide a very high timing resolution for time-of-flight applications in medical imaging and particle physics. It is dedicated in particular to the EndoToFPET-US project, which is developing an endoscopic PET detector combined with ultrasound imaging for early pancreas and prostate cancer detection. This PET system aims to provide a spatial resolution of 1 mm and a time-of-flight resolution of 200 ps FWHM. The analog frontend of STiC can use either a differential or single ended connection to the SiPM. The time and energy information of the detector signal is encoded into two time stamps. A special linearized time-over-threshold method is used to obtain a linear relation between the signal charge and the measured signal width, improving the energy resolution. The trigger signals are digitized by an integrated TDC module with a resolution of less than 20 ps. The TDC data is stored in an internal memory and transfered over a 160 MBit/s serial link using 8/10 bit encoding. First coincidence measurements using a 3.1 × 3.1 × 15 mm 3 LYSO crystal and a S10362-33-50 Hamamtsu MPPC show a coincidence time resolution of less than 285 ps. We present details on the chip design as well as first characterization measurements

Configurable Radiation Hardened High Speed Isolated Interface ASIC, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — NVE Corporation will design and build an innovative, low cost, flexible, configurable, radiation hardened, galvanically isolated, interface ASIC chip set that will...

Fast front-end electronics for COMPASS MWPCs

CERN Document Server

Colantoni, M L; Ferrero, A; Frolov, V; Grasso, A; Heinz, S; Maggiora, A; Maggiora, M G; Panzieri, D; Popov, A; Tchalyshev, V

2000-01-01

In the COMPASS experiment, under construction at CERN, about 23000 channels of MWPCs will be used. The very high rate of the muon and hadron beams, and the consequently high trigger rate, require front- end electronics with innovative conceptual design. A new MWPC front- end electronics that fulfills the main COMPASS requirement to have a fast DAQ with a minimum dead-time has been designed. The general concept of the front-end cards is described; the comparative tests of two front-end chips, and different fast gas mixtures, are also shown. The commissioning of the experiment will start in the summer 2000, and production running, using the muon beam, is foreseen for the year 2001. (8 refs).

A 1.0 V 78 mircoW reconfigurable ASIC embedded in an intelligent electrode for continuous remote ECG applications.

Science.gov (United States)

Yang, Geng; Chen, Jian; Jonsson, Fredrik; Tenhunen, Hannu; Zheng, Li-Rong

2009-01-01

In this paper, a reconfigurable, low-power Application Specific Integrated Circuit (ASIC) that extracts and transmits electrocardiograph (ECG) signals is presented. An Intelligent Electrode is introduced which consists of the proposed ASIC and a micro spike array, permitting onsite ECG signal acquisition, processing and transmission. Fabricated in a standard 0.18 microm CMOS process, the ASIC consumes 78 microW with 1.0 V core voltage at 6 MHz operating frequency and only occupies 2.25 mm(2). The tiny silicon size makes it possible and suitable to embed the proposed ASIC into an Intelligent Electrode, and the low power consumption makes it feasible for long term continuous ECG monitoring.

Parameters-adjustable front-end controller in digital nuclear measurement system

International Nuclear Information System (INIS)

Hao Dejian; Zhang Ruanyu; Yan Yangyang; Wang Peng; Tang Changjian

2013-01-01

Background: One digitizer is used to implement a digital nuclear measurement for the acquisition of nuclear information. Purpose: A principle and method of a parameter-adjustable front-end controller is presented for the sake of reducing the quantitative errors while getting the maximum ENOB (effective number of bits) of ADC (analog-to-digital converter) during waveform digitizing, as well as reducing the losing counts. Methods: First of all, the quantitative relationship among the radiation count rate (n), the amplitude of input signal (V in ), the conversion scale of ADC (±V) and the amplification factor (A) was derived. Secondly, the hardware and software of the front-end controller were designed to fulfill matching the output of different detectors, adjusting the amplification linearly through the control of channel switching, and setting of digital potentiometer by CPLD (Complex Programmable Logic Device). Results: (1) Through the measurement of γ-ray of Am-241 under our digital nuclear measurement set-up with CZT detector, it was validated that the amplitude of output signal of detectors of RC feedback type could be amplified linearly with adjustable amplification by the front-end controller. (2) Through the measurement of X-ray spectrum of Fe-5.5 under our digital nuclear measurement set-up with Si-PIN detector, it was validated that the front-end controller was suitable for the switch resetting type detectors, by which high precision measurement under various count rates could be fulfilled. Conclusion: The principle and method of the parameter-adjustable front-end controller presented in this paper is correct and feasible. (authors)

The Mixed-Signal ASIC design course at Twente

NARCIS (Netherlands)

Stehelin, G.; Tangelder, R.J.W.T.; Gerez, Sabih H.; Kerkhoff, Hans G.; Klumperink, Eric A.M.; Smit, J.; Snijders, H.; Speek, H.; de Vries, H.

2000-01-01

In this paper we give a detailed overview of the ASIC design course as it is being given at the Department of Electrical Engineering of the University of Twente. This course covers the complete trajectory from system design via circuit design and actual implementation to testing. Design and testing

GET: A generic electronics system for TPCs and nuclear physics instrumentation

Science.gov (United States)

Pollacco, E. C.; Grinyer, G. F.; Abu-Nimeh, F.; Ahn, T.; Anvar, S.; Arokiaraj, A.; Ayyad, Y.; Baba, H.; Babo, M.; Baron, P.; Bazin, D.; Beceiro-Novo, S.; Belkhiria, C.; Blaizot, M.; Blank, B.; Bradt, J.; Cardella, G.; Carpenter, L.; Ceruti, S.; De Filippo, E.; Delagnes, E.; De Luca, S.; De Witte, H.; Druillole, F.; Duclos, B.; Favela, F.; Fritsch, A.; Giovinazzo, J.; Gueye, C.; Isobe, T.; Hellmuth, P.; Huss, C.; Lachacinski, B.; Laffoley, A. T.; Lebertre, G.; Legeard, L.; Lynch, W. G.; Marchi, T.; Martina, L.; Maugeais, C.; Mittig, W.; Nalpas, L.; Pagano, E. V.; Pancin, J.; Poleshchuk, O.; Pedroza, J. L.; Pibernat, J.; Primault, S.; Raabe, R.; Raine, B.; Rebii, A.; Renaud, M.; Roger, T.; Roussel-Chomaz, P.; Russotto, P.; Saccà, G.; Saillant, F.; Sizun, P.; Suzuki, D.; Swartz, J. A.; Tizon, A.; Usher, N.; Wittwer, G.; Yang, J. C.

2018-04-01

General Electronics for TPCs (GET) is a generic, reconfigurable and comprehensive electronics and data-acquisition system for nuclear physics instrumentation of up to 33792 channels. The system consists of a custom-designed ASIC for signal processing, front-end cards that each house 4 ASIC chips and digitize the data in parallel through 12-bit ADCs, concentration boards to read and process the digital data from up to 16 ASICs, a 3-level trigger and master clock module to trigger the system and synchronize the data, as well as all of the associated firmware, communication and data-acquisition software. An overview of the system including its specifications and measured performances are presented.

Wide-band low-noise distributed front-end for multi-gigabit CPFSK receivers

DEFF Research Database (Denmark)

Petersen, Anders Kongstad; Ebskamp, F; Pedersen, Rune Johan Skullerud

1994-01-01

In this paper a distributed optical front-end amplifier for a coherent optical CPFSK receiver is presented. The measured average input noise current density is 20 pA/√(Hz) in a 3-13 GHz bandwidth. This is the lowest value reported for a distributed optical front-end in this frequency range....... The front-end is tested in a system set-up at a bit rate of 2.5 Gbit/s and a receiver sensitivity of -41.5 dBm is achieved at a 10-9 bit error rate...

The interaction between the first transmembrane domain and the thumb of ASIC1a is critical for its N-glycosylation and trafficking.

Directory of Open Access Journals (Sweden)

Lan Jing

Full Text Available Acid-sensing ion channel-1a (ASIC1a, the primary proton receptor in the brain, contributes to multiple diseases including stroke, epilepsy and multiple sclerosis. Thus, a better understanding of its biogenesis will provide important insights into the regulation of ASIC1a in diseases. Interestingly, ASIC1a contains a large, yet well organized ectodomain, which suggests the hypothesis that correct formation of domain-domain interactions at the extracellular side is a key regulatory step for ASIC1a maturation and trafficking. We tested this hypothesis here by focusing on the interaction between the first transmembrane domain (TM1 and the thumb of ASIC1a, an interaction known to be critical in channel gating. We mutated Tyr71 and Trp287, two key residues involved in the TM1-thumb interaction in mouse ASIC1a, and found that both Y71G and W287G decreased synaptic targeting and surface expression of ASIC1a. These defects were likely due to altered folding; both mutants showed increased resistance to tryptic cleavage, suggesting a change in conformation. Moreover, both mutants lacked the maturation of N-linked glycans through mid to late Golgi. These data suggest that disrupting the interaction between TM1 and thumb alters ASIC1a folding, impedes its glycosylation and reduces its trafficking. Moreover, reducing the culture temperature, an approach commonly used to facilitate protein folding, increased ASIC1a glycosylation, surface expression, current density and slowed the rate of desensitization. These results suggest that correct folding of extracellular ectodomain plays a critical role in ASIC1a biogenesis and function.

Development and validation of a 64 channel front end ASIC for 3D directional detection for MIMAC

International Nuclear Information System (INIS)

Richer, J P; Bourrion, O; Bosson, G; Guillaudin, O; Mayet, F; Santos, D

2011-01-01

A front end ASIC has been designed to equip the μTPC prototype developed for the MIMAC project, which requires 3D reconstruction of low energy particle tracks in order to perform directional detection of galactic Dark Matter. Each ASIC is able to monitor 64 strips of pixels and provides the 'Time Over Threshold' information for each of those. These 64 digital informations, sampled at a rate of 50 MHz, can be transferred at 400 MHz by eight LVDS serial links. Eight ASIC were validated on a 2 × 256 strips of pixels prototype.

Development of advanced I and C in nuclear power plants: ADIOS and ASICS

International Nuclear Information System (INIS)

Kim, Jung-Taek; Kwon, Kee-Choon; Hwang, In-Koo; Lee, Dong-Young; Park, Won-Man; Kim, Jung-Soo; Lee, Sang-Jeong

2001-01-01

In this paper Automatic Startup Intelligent Control System (ASICS) that automatically controls the PWR plant from cold shutdown to 5% of reactor power and Alarm and Diagnosis-Integrated Operator Support System (ADIOS) that is integrated with alarms, process values, and diagnostic information to an expert system focused on alarm processing are described. Nuclear Power Plant is manually controlled from cold shutdown to 5% according to the general operation procedures for startup operation of nuclear power plant. Alarm information is the primary sources to detect abnormalities in nuclear power plants or other process plants. The conventional hardwired alarm systems, characterized by one sensor-one indicator may lead the control room operators to be confused with avalanching alarms during plant transients. ASICS and ADIOS are designed to reduce the operator burden. The advances in computer software and hardware technology and also in information processing provide a good opportunity to improve the control systems and the annunciator systems of nuclear power plants or other similar process plants. It is very important to test and evaluate the performance and the function of the computer- or software-based systems like ASICS and ADIOS. The performance and the function of ASICS and ADIOS are evaluated with the real-time functional test facility and the results have shown that the developed systems are efficient and useful for operation and operator support

Development of advanced I and C in nuclear power plants: ADIOS and ASICS

Energy Technology Data Exchange (ETDEWEB)

Kim, Jung-Taek E-mail: jtkim@nanum.kaeri.re.kr; Kwon, Kee-Choon; Hwang, In-Koo; Lee, Dong-Young; Park, Won-Man; Kim, Jung-Soo; Lee, Sang-Jeong

2001-07-01

In this paper Automatic Startup Intelligent Control System (ASICS) that automatically controls the PWR plant from cold shutdown to 5% of reactor power and Alarm and Diagnosis-Integrated Operator Support System (ADIOS) that is integrated with alarms, process values, and diagnostic information to an expert system focused on alarm processing are described. Nuclear Power Plant is manually controlled from cold shutdown to 5% according to the general operation procedures for startup operation of nuclear power plant. Alarm information is the primary sources to detect abnormalities in nuclear power plants or other process plants. The conventional hardwired alarm systems, characterized by one sensor-one indicator may lead the control room operators to be confused with avalanching alarms during plant transients. ASICS and ADIOS are designed to reduce the operator burden. The advances in computer software and hardware technology and also in information processing provide a good opportunity to improve the control systems and the annunciator systems of nuclear power plants or other similar process plants. It is very important to test and evaluate the performance and the function of the computer- or software-based systems like ASICS and ADIOS. The performance and the function of ASICS and ADIOS are evaluated with the real-time functional test facility and the results have shown that the developed systems are efficient and useful for operation and operator support.

Specification of requirements for the implementation of ASICs and FPGA in instrumentation and control systems important to safety in German NPPs

International Nuclear Information System (INIS)

Schnurer, G.

2007-01-01

This paper gives an overview concerning the design as well as the verification and validation of Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGA) in German NPPs which are applied to carry out I and C functions. The qualification procedures dealt with restricted on ASICs without any microcontroller core. Dependent on the different safety categories, recommendations concerning the qualification level and procedures are elaborated which have to be achieved for ASICs and FPGA. Important aspects within the framework of the expert judgement for upgrading of safety relevant I and C by ASICs and FPGA are dealt with. These aspects are of general character and are mainly focused on suitability test procedures and robustness requirements of ASICs and FPGA

E-beam direct write versus reticle/stepper technology for ASICS in small volume production

International Nuclear Information System (INIS)

Wheeler, M.J.

1987-01-01

The pros and cons of using e-beam direct writing or reticles plus optical/UV steppers in fast prototyping and the small volume production of ASICs are discussed. The main conclusion is that fast prototyping is best achieved by e-beam direct write whereas small volume production of ASICs is best done via reticles and optical/UV stepping provided that the reticles are made in-house rather than by commercial maskhouses

Detector and Front-end electronics for ALICE and STAR silicon strip layers

CERN Document Server

Arnold, L; Coffin, J P; Guillaume, G; Higueret, S; Jundt, F; Kühn, C E; Lutz, Jean Robert; Suire, C; Tarchini, A; Berst, D; Blondé, J P; Clauss, G; Colledani, C; Deptuch, G; Dulinski, W; Hu, Y; Hébrard, L; Kucewicz, W; Boucham, A; Bouvier, S; Ravel, O; Retière, F

1998-01-01

Detector modules consisting of Silicon Strip Detector (SSD) and Front End Electronics (FEE) assembly have been designed in order to provide the two outer layers of the ALICE Inner Tracker System (ITS) [1] as well as the outer layer of the STAR Silicon Vertex Tracker (SVT) [2]. Several prototypes have beenproduced and tested in the SPS and PS beam at CERN to validate the final design. Double-sided, AC-coupled SSD detectors provided by two different manufacturers and also a pair of single-sided SSD have been asssociated to new low-power CMOS ALICE128C ASIC chips in a new detector module assembly. The same detectors have also been associated to current Viking electronics for reference purpose. These prototype detector modules are described and some first results are presented.

An external control unit implemented for stimulator ASIC testing ...

African Journals Online (AJOL)

) for a stimulator ASIC testing purposes. The ECU consists of a graphical user interface (GUI) from the PC, a data transceiver and a power transmitter. The GUI was developed using MATLAB for stimulation data setup. The data transceiver was ...

Design of analog front-ends for the RD53 demonstrator chip

CERN Document Server

Gaioni, L; Nodari, B; Manghisoni, M; Re, V; Traversi, G; Barbero, M B; Fougeron, D; Gensolen, F; Godiot, S; Menouni, M; Pangaud, P; Rozanov, A; Wang, A; Bomben, M; Calderini, G; Crescioli, F; Le Dortz, O; Marchiori, G; Dzahini, D; Rarbi, F E; Gaglione, R; Gonella, L; Hemperek, T; Huegging, F; Karagounis, M; Kishishita, T; Krueger, H; Rymaszewski, P; Wermes, N; Ciciriello, F; Corsi, F; Marzocca, C; De Robertis, G; Loddo, F; Licciulli, F; Andreazza, A; Liberali, V; Shojaii, S; Stabile, A; Bagatin, M; Bisello, D; Mattiazzo, S; Ding, L; Gerardin, S; Giubilato, P; Neviani, A; Paccagnella, A; Vogrig, D; Wyss, J; Bacchetta, N; Della Casa, G; Demaria, N; Mazza, G; Rivetti, A; Da Rocha Rolo, M D; Comotti, D; Ratti, L; Vacchi, C; Beccherle, R; Bellazzini, R; Magazzu, G; Minuti, M; Morsani, F; Palla, F; Poulios, S; Fanucci, L; Rizzi, A; Saponara, S; Androsov, K; Bilei, G M; Menichelli, M; Conti, E; Marconi, S; Passeri, D; Placidi, P; Monteil, E; Pacher, L; Paternò, A; Gajanana, D; Gromov, V; Hessey, N; Kluit, R; Zivkovic, V; Havranek, M; Janoska, Z; Marcisovsky, M; Neue, G; Tomasek, L; Kafka, V; Sicho, P; Vrba, V; Vila, I; Lopez-Morillo, E; Aguirre, M A; Palomo, F R; Muñoz, F; Abbaneo, D; Christiansen, J; Dannheim, D; Dobos, D; Linssen, L; Pernegger, H; Valerio, P; Alipour Tehrani, N; Bell, S; Prydderch, M L; Thomas, S; Christian, D C; Fahim, F; Hoff, J; Lipton, R; Liu, T; Zimmerman, T; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gorelov, I; Hoeferkamp, M; Seidel, S; Toms, K; De Witt, J N; Grillo, A

2017-01-01

The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

Test of ATLAS RPCs Front-End electronics

International Nuclear Information System (INIS)

Aielli, G.; Camarri, P.; Cardarelli, R.; Di Ciaccio, A.; Di Stante, L.; Liberti, B.; Paoloni, A.; Pastori, E.; Santonico, R.

2003-01-01

The Front-End Electronics performing the ATLAS RPCs readout is a full custom 8 channels GaAs circuit, which integrates in a single die both the analog and digital signal processing. The die is bonded on the Front-End board which is completely closed inside the detector Faraday cage. About 50 000 FE boards are foreseen for the experiment. The complete functionality of the FE boards will be certificated before the detector assembly. We describe here the systematic test devoted to check the dynamic functionality of each single channel and the selection criteria applied. It measures and registers all relevant electronics parameters to build up a complete database for the experiment. The statistical results from more than 1100 channels are presented

Small Microprocessor for ASIC or FPGA Implementation

Science.gov (United States)

Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

2011-01-01

A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

Low-power low-noise mixed-mode VLSI ASIC for infinite dynamic range imaging applications

Science.gov (United States)

Turchetta, Renato; Hu, Y.; Zinzius, Y.; Colledani, C.; Loge, A.

1998-11-01

Solid state solutions for imaging are mainly represented by CCDs and, more recently, by CMOS imagers. Both devices are based on the integration of the total charge generated by the impinging radiation, with no processing of the single photon information. The dynamic range of these devices is intrinsically limited by the finite value of noise. Here we present the design of an architecture which allows efficient, in-pixel, noise reduction to a practically zero level, thus allowing infinite dynamic range imaging. A detailed calculation of the dynamic range is worked out, showing that noise is efficiently suppressed. This architecture is based on the concept of single-photon counting. In each pixel, we integrate both the front-end, low-noise, low-power analog part and the digital part. The former consists of a charge preamplifier, an active filter for optimal noise bandwidth reduction, a buffer and a threshold comparator, and the latter is simply a counter, which can be programmed to act as a normal shift register for the readout of the counters' contents. Two different ASIC's based on this concept have been designed for different applications. The first one has been optimized for silicon edge-on microstrips detectors, used in a digital mammography R and D project. It is a 32-channel circuit, with a 16-bit binary static counter.It has been optimized for a relatively large detector capacitance of 5 pF. Noise has been measured to be equal to 100 + 7*Cd (pF) electron rms with the digital part, showing no degradation of the noise performances with respect to the design values. The power consumption is 3.8mW/channel for a peaking time of about 1 microsecond(s) . The second circuit is a prototype for pixel imaging. The total active area is about (250 micrometers )**2. The main differences of the electronic architecture with respect to the first prototype are: i) different optimization of the analog front-end part for low-capacitance detectors, ii) in- pixel 4-bit comparator

Functional tests of 2S modules for the CMS Phase-2 Tracker Upgrade with a MicroTCA-based readout system

CERN Document Server

Preuten, Marius; Klein, Katja; Lipinski, Martin; Rauch, Max; Feld, Lutz

2017-01-01

First full size 2S module prototypes for the CMS Phase-2 Outer Tracker Upgrade have been assembled. With two sensors of realistic dimensions and 16 CBC2 readout ASICs on two front-end hybrids, the characteristics of these novel and complex objects can be studied.A MicroTCA based readout system was developed to test multiple front-end hybrids simultaneously. Therefore the concurrent information of the full module can be used for noise and signal studies.

Test beam analysis of ultra-thin hybrid pixel detector assemblies with Timepix readout ASICs

CERN Document Server

Alipour Tehrani, Niloufar; Dannheim, Dominik; Firu, Elena; Kulis, Szymon; Redford, Sophie; Sicking, Eva

2016-01-01

The requirements for the vertex detector at the proposed Compact Linear Collider imply a very small material budget: less than 0.2% of a radiation length per detection layer including services and mechanical supports. We present here a study using Timepix readout ASICs hybridised to pixel sensors of 50 − 500 μm thickness, including assemblies with 100 μm thick sensors bonded to thinned 100μm thick ASICs. Sensors from three producers (Advacam, Micron Semiconductor Ltd, Canberra) with different edge termination technologies (active edge, slim edge) were bonded to Timepix ASICs. These devices were characterised with the EUDET telescope at the DESY II test beam using 5.6 GeV electrons. Their performance for the detection and tracking of minimum ionising particles was evaluated in terms of charge sharing, detection efficiency, single-point resolution and energy deposition.

Integrated X-band FMCW front-end in SiGe BiCMOS

NARCIS (Netherlands)

Suijker, Erwin; de Boer, Lex; Visser, Guido; van Dijk, Raymond; Poschmann, Michael; van Vliet, Frank Edward

2010-01-01

An integrated X-band FMCW front-end is reported. The front-end unites the core functionality of an FMCW transmitter and receiver in a 0.25 μm SiGe BiCMOS process. The chip integrates a PLL for the carrier generation, and single-side band and image-reject mixers for up- and down-conversion of the

Performance study of SKIROC2/A ASIC for ILD Si-W ECAL

Science.gov (United States)

Suehara, T.; Sekiya, I.; Callier, S.; Balagura, V.; Boudry, V.; Brient, J.-C.; de la Taille, C.; Kawagoe, K.; Irles, A.; Magniette, F.; Nanni, J.; Pöschl, R.; Yoshioka, T.

2018-03-01

The ILD Si-W ECAL is a sampling calorimeter with tungsten absorber and highly segmented silicon layers for the International Large Detector (ILD), one of the two detector concepts for the International Linear Collider. SKIROC2 is an ASIC for the ILD Si-W ECAL. To investigate the issues found in prototype detectors, we prepared dedicated ASIC evaluation boards with either BGA sockets or directly soldered SKIROC2. We report a performance study with the evaluation boards, including signal-to-noise ratio and TDC performance with comparing SKIROC2 and an updated version, SKIROC2A.

Design and characterization of the readout ASIC for the BESIII CGEM detector

CERN Document Server

Cossio, Fabio; Bugalho, Ricardo; Chai, Junying; Cheng, Weishuai; Da Rocha Rolo, Manuel Dionisio; Di Francesco, Agostino; Greco, Michela; Leng, Chongyang; Li, Huaishen; Maggiora, Marco; Marcello, Simonetta; Mignone, Marco; Rivetti, Angelo; Varela, Joao; Wheadon, Richard

2018-01-01

TIGER (Turin Integrated Gem Electronics for Readout) is a mixed-mode ASIC for the readout of signals from CGEM (Cylindrical Gas Electron Multiplier) detector in the upgraded inner tracker of the BESIII experiment, carried out at BEPCII in Beijing. The ASIC includes 64 channels, each of which features a dual-branch architecture optimized for timing and energy measurement. The input signal time-of-arrival and charge measurement is provided by low-power TDCs, based on analogue interpolation techniques, and Wilkinson ADCs, with a fully-digital output. The silicon results of TIGER first prototype are presented showing its full functionality.

Cryogenic and radiation hard ASIC design for large format NIR/SWIR detector

Science.gov (United States)

Gao, Peng; Dupont, Benoit; Dierickx, Bart; Müller, Eric; Verbruggen, Geert; Gielis, Stijn; Valvekens, Ramses

2014-10-01

An ASIC is developed to control and data quantization for large format NIR/SWIR detector arrays. Both cryogenic and space radiation environment issue are considered during the design. Therefore it can be integrated in the cryogenic chamber, which reduces significantly the vast amount of long wires going in and out the cryogenic chamber, i.e. benefits EMI and noise concerns, as well as the power consumption of cooling system and interfacing circuits. In this paper, we will describe the development of this prototype ASIC for image sensor driving and signal processing as well as the testing in both room and cryogenic temperature.

The Front-End Concentrator card for the RD51 Scalable Readout System

International Nuclear Information System (INIS)

Toledo, J; Esteve, R; Monzó, J M; Tarazona, A; Muller, H; Martoiu, S

2011-01-01

Conventional readout systems exist in many variants since the usual approach is to build readout electronics for one given type of detector. The Scalable Readout System (SRS) developed within the RD51 collaboration relaxes this situation considerably by providing a choice of frontends which are connected over a customizable interface to a common SRS DAQ architecture. This allows sharing development and production costs among a large base of users as well as support from a wide base of developers. The Front-end Concentrator card (FEC), a RD51 common project between CERN and the NEXT Collaboration, is a reconfigurable interface between the SRS online system and a wide range of frontends. This is accomplished by using application-specific adapter cards between the FEC and the frontends. The ensemble (FEC and adapter card are edge mounted) forms a 6U × 220 mm Eurocard combo that fits on a 19'' subchassis. Adapter cards exist already for the first applications and more are in development.

Design of a video capsule endoscopy system with low-power ASIC for monitoring gastrointestinal tract.

Science.gov (United States)

Liu, Gang; Yan, Guozheng; Zhu, Bingquan; Lu, Li

2016-11-01

In recent years, wireless capsule endoscopy (WCE) has been a state-of-the-art tool to examine disorders of the human gastrointestinal tract painlessly. However, system miniaturization, enhancement of the image-data transfer rate and power consumption reduction for the capsule are still key challenges. In this paper, a video capsule endoscopy system with a low-power controlling and processing application-specific integrated circuit (ASIC) is designed and fabricated. In the design, these challenges are resolved by employing a microimage sensor, a novel radio frequency transmitter with an on-off keying modulation rate of 20 Mbps, and an ASIC structure that includes a clock management module, a power-efficient image compression module and a power management unit. An ASIC-based prototype capsule, which measures Φ11 mm × 25 mm, has been developed here. Test results show that the designed ASIC consumes much less power than most of the other WCE systems and that its total power consumption per frame is the least. The image compression module can realize high near-lossless compression rate (3.69) and high image quality (46.2 dB). The proposed system supports multi-spectral imaging, including white light imaging and autofluorescence imaging, at a maximum frame rate of 24 fps and with a resolution of 400 × 400. Tests and in vivo trials in pigs have proved the feasibility of the entire system, but further improvements in capsule control and compression performance inside the ASIC are needed in the future.

The STAR cluster-finder ASIC

Energy Technology Data Exchange (ETDEWEB)

Botlo, M.; LeVine, M.J.; Scheetz, R.A.; Schulz, M.W. [Brookhaven National Lab., Upton, NY (United States); Short, P.; Woods, J. [InnovASIC, Inc., Albuquerque, NM (United States); Crosetto, D. [Rice Univ., Houston, TX (United States). Bonner Nuclear Lab.

1997-12-01

STAR is a large TPC-based experiment at RHIC, the relativistic heavy ion collider at Brookhaven National Laboratory. The STAR experiment reads out a TPC and an SVT (silicon vertex tracker), both of which require in-line pedestal subtraction, compression of ADC values from 10-bit to 8-bit, and location of time sequences representing responses to charged-particle tracks. The STAR cluster finder ASIC responds to all of these needs. Pedestal subtraction and compression are performed using lookup tables in attached RAM. The authors describe its design and implementation, as well as testing methodology and results of tests performed on foundry prototypes.

Characterisation of a human acid-sensing ion channel (hASIC1a) endogenously expressed in HEK293 cells.

Science.gov (United States)

Gunthorpe, M J; Smith, G D; Davis, J B; Randall, A D

2001-08-01

Acid-sensing ion channels (ASICs) are a new and expanding family of proton-gated cation (Na+/Ca2+) channels that are widely expressed in sensory neurons and the central nervous system. Their distribution suggests that they may play a critical role in the sensation of the pain that accompanies tissue acidosis and may also be important in detecting the subtle pH variations that occur during neuronal signalling. Here, using whole-cell patch-clamp electrophysiology and reverse transcriptase-polymerase chain reaction (RT-PCR), we show that HEK293 cells, a commonly used cell line for the expression and characterisation of many ion channels, functionally express an endogenous proton-gated conductance attributable to the activity of human ASIC1a. These data therefore represent the first functional characterisation of hASIC1 and have many important implications for the use of HEK293 cells as a host cell system for the study of ASICs, vanilloid receptor-1 and any other proton-gated channel. With this latter point in mind we have devised a simple desensitisation strategy to selectively remove the contribution of hASIC1a from proton-gated currents recorded from HEK293 cells expressing vanilloid receptor-1.

A CMOS ASIC Design for SiPM Arrays.

Science.gov (United States)

Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

2011-12-01

Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM).

A ±6 ms-Accuracy, 0.68 mm2, and 2.21 μW QRS Detection ASIC

Directory of Open Access Journals (Sweden)

Sheng-Chieh Huang

2012-01-01

Full Text Available Healthcare issues arose from population aging. Meanwhile, electrocardiogram (ECG is a powerful measurement tool. The first step of ECG is to detect QRS complexes. A state-of-the-art QRS detection algorithm was modified and implemented to an application-specific integrated circuit (ASIC. By the dedicated architecture design, the novel ASIC is proposed with 0.68 mm2 core area and 2.21 μW power consumption. It is the smallest QRS detection ASIC based on 0.18 μm technology. In addition, the sensitivity is 95.65% and the positive prediction of the ASIC is 99.36% based on the MIT/BIH arrhythmia database certification.

A design of a valid signal selecting and position decoding ASIC for PET using silicon photomultipliers

International Nuclear Information System (INIS)

Cho, M.; Lim, K.-T.; Kim, J.; Lee, C.; Cho, G.; Kim, H.; Yeom, J.-Y.; Choi, H.

2017-01-01

In most cases, a PET system has numerous electrical components and channel circuits and thus it would rather be a bulky product. Also, most existing systems receive analog signals from detectors which make them vulnerable to signal distortions. For these reasons, channel reduction techniques are important. In this work, an ASIC for PET module is being proposed. An ASIC chip for 16 PET detector channels, VSSPDC, has been designed and simulated. The main function of the chip is 16-to-1 channel reduction, i.e., finding the position of only the valid signals, signal timing, and magnitudes in all 16 channels at every recorded event. The ASIC comprises four of 4-channel modules and a 2 nd 4-to-1 router. A single channel module comprises a transimpedance amplifier for the silicon photomultipliers, dual comparators with high and low level references, and a logic circuitry. While the high level reference was used to test the validity of the signal, the low level reference was used for the timing. The 1-channel module of the ASIC produced an energy pulse by time-over-threshold method and it also produced a time pulse with a fixed delayed time. Since the ASIC chip outputs only a few digital pulses and does not require an external clock, it has an advantage over noise properties. The cadence simulation showed the good performance of the chip as designed.

Control and Interlocking System for Bending Magnet Front-end at Indus-2

Science.gov (United States)

Kane, Sanjeev R.; Garg, Chander Kant; Nandedkar, R. V.

2007-01-01

We present control and interlock system developed for Indus-2 bending magnet front-end. The paper describes in detail the control of various signals associated with the front-end and the interlocking scheme implemented for the installed front-end. The number of signals associated with each front-end is ˜ 75. A control system is designed for monitoring temperature, pressure, airflow, water flow and control of vacuum gauges, fast shutter, water cooled shutter, safety shutter, pneumatic gate valves, sputter ion pump power supplies, beam position monitor etc. Two independent signals are generated for critical components that are used for software interlock and hard-wired interlock. The front-end control system is VME based and window 2000/XP workstation as an operator console. The CPU used is Motorola 68000-processor board of the VME bus having OS-9 real time operating system. One VME crate serves a cluster of 2-3 front ends. The communication between the VME and the workstation is linked over RS232 serial communication. The sputter ion power supplies are connected over isolated RS485 network. Critical protection features are implemented so that no single failure can render the system unsafe. This is implemented by providing two independent chains of protection (1) Hard wired in which relay logic is used and (2) Software. A Graphical User Interface (GUI) is developed using Lab view Version 7.0.

Control and Interlocking System for Bending Magnet Front-end at Indus-2

International Nuclear Information System (INIS)

Kane, Sanjeev R.; Garg, Chander Kant; Nandedkar, R. V.

2007-01-01

We present control and interlock system developed for Indus-2 bending magnet front-end. The paper describes in detail the control of various signals associated with the front-end and the interlocking scheme implemented for the installed front-end. The number of signals associated with each front-end is ∼ 75. A control system is designed for monitoring temperature, pressure, airflow, water flow and control of vacuum gauges, fast shutter, water cooled shutter, safety shutter, pneumatic gate valves, sputter ion pump power supplies, beam position monitor etc. Two independent signals are generated for critical components that are used for software interlock and hard-wired interlock. The front-end control system is VME based and window 2000/XP workstation as an operator console. The CPU used is Motorola 68000-processor board of the VME bus having OS-9 real time operating system. One VME crate serves a cluster of 2-3 front ends. The communication between the VME and the workstation is linked over RS232 serial communication. The sputter ion power supplies are connected over isolated RS485 network. Critical protection features are implemented so that no single failure can render the system unsafe. This is implemented by providing two independent chains of protection (1) Hard wired in which relay logic is used and (2) Software. A Graphical User Interface (GUI) is developed using Lab view Version 7.0

High-performance electronics for time-of-flight PET systems

International Nuclear Information System (INIS)

Choong, W-S; Peng, Q; Vu, C Q; Turko, B T; Moses, W W

2013-01-01

We have designed and built a high-performance readout electronics system for time-of-flight positron emission tomography (TOF PET) cameras. The electronics architecture is based on the electronics for a commercial whole-body PET camera (Siemens/CPS Cardinal electronics), modified to improve the timing performance. The fundamental contributions in the electronics that can limit the timing resolution include the constant fraction discriminator (CFD), which converts the analog electrical signal from the photo-detector to a digital signal whose leading edge is time-correlated with the input signal, and the time-to-digital converter (TDC), which provides a time stamp for the CFD output. Coincident events are identified by digitally comparing the values of the time stamps. In the Cardinal electronics, the front-end processing electronics are performed by an Analog subsection board, which has two application-specific integrated circuits (ASICs), each servicing a PET block detector module. The ASIC has a built-in CFD and TDC. We found that a significant degradation in the timing resolution comes from the ASIC's CFD and TDC. Therefore, we have designed and built an improved Analog subsection board that replaces the ASIC's CFD and TDC with a high-performance CFD (made with discrete components) and TDC (using the CERN high-performance TDC ASIC). The improved Analog subsection board is used in a custom single-ring LSO-based TOF PET camera. The electronics system achieves a timing resolution of 60 ps FWHM. Prototype TOF detector modules are read out with the electronics system and give coincidence timing resolutions of 259 ps FWHM and 156 ps FWHM for detector modules coupled to LSO and LaBr 3 crystals respectively.

CLARO: an ASIC for high rate single photon counting with multi-anode photomultipliers

Science.gov (United States)

Baszczyk, M.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Dorosz, P.; Fiorini, M.; Gotti, C.; Kucewicz, W.; Malaguti, R.; Pessina, G.

2017-08-01

The CLARO is a radiation-hard 8-channel ASIC designed for single photon counting with multi-anode photomultiplier tubes. Each channel outputs a digital pulse when the input signal from the photomultiplier crosses a configurable threshold. The fast return to baseline, typically within 25 ns, and below 50 ns in all conditions, allows to count up to 107 hits/s on each channel, with a power consumption of about 1 mW per channel. The ASIC presented here is a much improved version of the first 4-channel prototype. The threshold can be precisely set in a wide range, between 30 ke- (5 fC) and 16 Me- (2.6 pC). The noise of the amplifier with a 10 pF input capacitance is 3.5 ke- (0.6 fC) RMS. All settings are stored in a 128-bit configuration and status register, protected against soft errors with triple modular redundancy. The paper describes the design of the ASIC at transistor-level, and demonstrates its performance on the test bench.

Delay 25 an ASIC for timing adjustment in LHC

NARCIS (Netherlands)

Furtado, H.; Schrader, J.H.R.; Marchioro, A.; Moreira, P.

A five channel programmable delay line ASIC was designed featuring 4 channels that allow to phase delay periodic or non-periodic digital signals and a master channel that can be used to phase delay a clock signal. The master channel serves as a calibration reference guaranteeing independence from

High Rate Digital Demodulator ASIC

Science.gov (United States)

Ghuman, Parminder; Sheikh, Salman; Koubek, Steve; Hoy, Scott; Gray, Andrew

1998-01-01

The architecture of High Rate (600 Mega-bits per second) Digital Demodulator (HRDD) ASIC capable of demodulating BPSK and QPSK modulated data is presented in this paper. The advantages of all-digital processing include increased flexibility and reliability with reduced reproduction costs. Conventional serial digital processing would require high processing rates necessitating a hardware implementation in other than CMOS technology such as Gallium Arsenide (GaAs) which has high cost and power requirements. It is more desirable to use CMOS technology with its lower power requirements and higher gate density. However, digital demodulation of high data rates in CMOS requires parallel algorithms to process the sampled data at a rate lower than the data rate. The parallel processing algorithms described here were developed jointly by NASA's Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL). The resulting all-digital receiver has the capability to demodulate BPSK, QPSK, OQPSK, and DQPSK at data rates in excess of 300 Mega-bits per second (Mbps) per channel. This paper will provide an overview of the parallel architecture and features of the HRDR ASIC. In addition, this paper will provide an over-view of the implementation of the hardware architectures used to create flexibility over conventional high rate analog or hybrid receivers. This flexibility includes a wide range of data rates, modulation schemes, and operating environments. In conclusion it will be shown how this high rate digital demodulator can be used with an off-the-shelf A/D and a flexible analog front end, both of which are numerically computer controlled, to produce a very flexible, low cost high rate digital receiver.

Fast CMOS binary front-end for silicon strip detectors at LHC experiments

CERN Document Server

Kaplon, Jan

2004-01-01

We present the design and the test results of a front-end circuit developed in a 0.25 mu m CMOS technology. The aim of this work is to study the performance of a deep submicron process in applications for fast binary front-end for silicon strip detectors. The channel comprises a fast transimpedance preamplifier working with an active feedback loop, two stages of the amplifier-integrator circuits providing 22 ns peaking time and two-stage differential discriminator. Particular effort has been made to minimize the current and the power consumption of the preamplifier, while keeping the required noise and timing performance. For a detector capacitance of 20 pF noise below 1500 e/sup -/ ENC has been achieved for 300 mu A bias current in the input transistor, which is comparable with levels achieved in the past for a front-end using bipolar input transistor. The total supply current of the front-end is 600 mu A and the power dissipation is 1.5 mW per channel. The offset spread of the comparator is below 3 mV rms.

The TDCpix Readout ASIC: A 75 ps Resolution Timing Front-End for the Gigatrackerof theNA62 Experiment

Science.gov (United States)

Rinella, G. Aglieri; Fiorini, M.; Jarron, P.; Kaplon, J.; Kluge, A.; Martin, E.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

NA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at measuring ultra rare kaon decays. The Gigatracker (GTK) detector shall combine on-beam tracking of individual particles with a time resolution of 150 ps rms. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm2 fora total rateof about 0.75 GHz.Ahybrid siliconpixel detectoris beingdevelopedto meet these requirements. The pixel chip for the Gigatracker (TDCpix) is under design. The TDCpix chip will feature 1800 square pixels of 300×300 μm2 arranged in a matrix of 45 rows × 40 columns. Bump-bonded to a silicon pixel sensor it shall perform time stamping of particle hits with a timing accuracybetter than 200 ps rms and a detection efficiencyabove 99%. The chosen architecture provides full separation of the sensitive analog amplifiers of the pixel matrix from the noisy digital circuits of the TDCs and of the readout blocks. Discriminated hit signals from each pixel are transmitted to the end of column region. An array ofTime to Digital Converters (TDC) is implemented at the bottom of the pixel array. The TDCs are based on time tagging the events with the fine time codes generated by Delay Locked Loops (DLL) and have a nominal time bin of ˜100 ps. Time stamps and time-over-threshold are recorded for each discriminated hit and the correction of the discriminator's time-walk is performed off-detector. Data are continuously transmitted on four 2.4 Gb/s serial output links. Adescription of the on-going design of the final TDCpix is given in this paper. Design choices and some technical implementation details are presented. Aprototype ASIC including thekeycomponents of this architecture has been manufactured. The achievement of specification figures such as a time resolution of the processing chain of 75 ps rms as well as charged particle time stampingwitha resolutionbetterthan200psrmswere demonstratedexperimentally.Asummaryoftheseresultsisalso presented in

A 500μW 5Mbps ULP super-regenerative RF front-end

NARCIS (Netherlands)

Vidojkovic, M.; Rampu, S.; Imamura, K.; Harpe, P.; Dolmans, G.; Groot, H. de

2010-01-01

This paper presents an ultra low power super-regenerative RF front-end for wireless body area network (WBAN) applications. The RF front-end operates in the 2.36-2.4 GHz medical BAN and 2.4-2.485 GHz ISM bands, and consumes 500 μW. It supports OOK modulation at high data rates ranging from 1-5 Mbps.

A 128-channel event driven readout ASIC for the R3B tracker

International Nuclear Information System (INIS)

Jones, L.; Bell, S.; Morrissey, Q.; Prydderch, M.; Church, I.; Lazarus, I.; Kogimtzis, M.; Pucknell, V.; Labiche, M.; Thornhill, J.; Borri, M.

2016-01-01

R 3 B is a detector with high efficiency, acceptance, and resolution for kinematically complete measurements of reactions with high-energy radioactive beams. Detectors track and identify radioactive beams into and out of a reaction target. Three layers of double-sided stereoscopic silicon strips form the tracker detector which must provide precise tracking and vertex determination and in addition include energy and multiplicity measurements. The R 3 B ASIC has been manufactured and is intended for processing and digitising signals generated by ionising particles passing through the tracker. The ASIC processes signals and provides spatial, energy and time measurements

Cryogenic and radiation-hard asic for interfacing large format NIR/SWIR detector arrays

Science.gov (United States)

Gao, Peng; Dupont, Benoit; Dierickx, Bart; Müller, Eric; Verbruggen, Geert; Gielis, Stijn; Valvekens, Ramses

2017-11-01

For scientific and earth observation space missions, weight and power consumption is usually a critical factor. In order to obtain better vehicle integration, efficiency and controllability for large format NIR/SWIR detector arrays, a prototype ASIC is designed. It performs multiple detector array interfacing, power regulation and data acquisition operations inside the cryogenic chambers. Both operation commands and imaging data are communicated via the SpaceWire interface which will significantly reduce the number of wire goes in and out the cryogenic chamber. This "ASIC" prototype is realized in 0.18um CMOS technology and is designed for radiation hardness.

ALTIROC0, a 20 pico-second time resolution ASIC for the ATLAS High Granularity Timing Detector (HGTD)

CERN Document Server

de la Taille, C.; Conforti, S.; Dinaucourt, P.; Martin-Chassard, G.; Seguin-Moreau, N.; Agapopoulou, C.; Makovec, N.; Serin, L.; Simion, S.

2018-01-01

ALTIROC0 is an 8-channel ASIC prototype designed to readout 1x1 or 2x2 mm^2 50 µm thick Low Gain Avalanche Diodes (LGAD) of the ATLAS High Granularity Timing Detector (HGTD). The targeted combined time resolution of the sensor and the readout electronics is 30 ps for one MIP. Each analog channel of the ASIC must exhibit an extremely low jitter to ensure this challenging time resolution, while keeping a low power consumption of 2 mW/channel. A “Time Over Threshold” and a “Constant Fraction Discriminator” architecture are integrated to correct for the time walk. Test bench measurements performed on the ASIC received in April 2017 are presented.

ADVANCED READOUT ELECTRONICS FOR MULTIELEMENT CdZnTe SENSORS

International Nuclear Information System (INIS)

DE GERONIMO, G.; O CONNOR, P.; KANDASAMY, A.; GROSHOLZ, J.

2002-01-01

A generation of high performance front-end and read-out ASICs customized for highly segmented CdZnTe sensors is presented. The ASICs, developed in a multi-year effort at Brookhaven National Laboratory, are targeted to a wide range of applications including medical, safeguards/security, industrial, research, and spectroscopy. The front-end multichannel ASICs provide high accuracy low noise preamplification and filtering of signals, with versions for small and large area CdZnTe elements. They implement a high order unipolar or bipolar shaper, an innovative low noise continuous reset system with self-adapting capability to the wide range of detector leakage currents, a new system for stabilizing the output baseline and high output driving capability. The general-purpose versions include programmable gain and peaking time. The read-out multichannel ASICs provide fully data driven high accuracy amplitude and time measurements, multiplexing and time domain derandomization of the shaped pulses. They implement a fast arbitration scheme and an array of innovative two-phase offset-free rail-to-rail analog peak detectors for buffering and absorption of input rate fluctuations, thus greatly relaxing the rate requirement on the external ADC. Pulse amplitude, hit timing, pulse risetime, and channel address per processed pulse are available at the output in correspondence of an external readout request. Prototype chips have been fabricated in 0.5 and 0.35 (micro)m CMOS and tested. Design concepts and experimental results are discussed

The design and development of low- and high-voltage ASICs for space-borne CCD cameras

Science.gov (United States)

Waltham, N.; Morrissey, Q.; Clapp, M.; Bell, S.; Jones, L.; Torbet, M.

2017-12-01

The CCD remains the pre-eminent visible and UV wavelength image sensor in space science, Earth and planetary remote sensing. However, the design of space-qualified CCD readout electronics is a significant challenge with requirements for low-volume, low-mass, low-power, high-reliability and tolerance to space radiation. Space-qualified components are frequently unavailable and up-screened commercial components seldom meet project or international space agency requirements. In this paper, we describe an alternative approach of designing and space-qualifying a series of low- and high-voltage mixed-signal application-specific integrated circuits (ASICs), the ongoing development of two low-voltage ASICs with successful flight heritage, and two new high-voltage designs. A challenging sub-system of any CCD camera is the video processing and digitisation electronics. We describe recent developments to improve performance and tolerance to radiation-induced single event latchup of a CCD video processing ASIC originally developed for NASA's Solar Terrestrial Relations Observatory and Solar Dynamics Observatory. We also describe a programme to develop two high-voltage ASICs to address the challenges presented with generating a CCD's bias voltages and drive clocks. A 0.35 μm, 50 V tolerant, CMOS process has been used to combine standard low-voltage 3.3 V transistors with high-voltage 50 V diffused MOSFET transistors that enable output buffers to drive CCD bias drains, gates and clock electrodes directly. We describe a CCD bias voltage generator ASIC that provides 24 independent and programmable 0-32 V outputs. Each channel incorporates a 10-bit digital-to-analogue converter, provides current drive of up to 20 mA into loads of 10 μF, and includes current-limiting and short-circuit protection. An on-chip telemetry system with a 12-bit analogue-to-digital converter enables the outputs and multiple off-chip camera voltages to be monitored. The ASIC can drive one or more CCDs and

A tunable RF Front-End with Narrowband Antennas for Mobile Devices

DEFF Research Database (Denmark)

Bahramzy, Pevand; Olesen, Poul; Madsen, Peter

2015-01-01

desensitization due to the Tx signal. The filters and antennas demonstrate tunability across multiple bands. System validation is detailed for LTE band I. Frequency response, as well as linearity measurements of the complete Tx and Rx front-end chains, show that the system requirements are fulfilled.......In conventional full-duplex radio communication systems, the transmitter (Tx) is active at the same time as the receiver (Rx). The isolation between the Tx and the Rx is ensured by duplex filters. However, an increasing number of long-term evolution (LTE) bands crave multiband operation. Therefore......, a new front-end architecture, addressing the increasing number of LTE bands, as well as multiple standards, is presented. In such an architecture, the Tx and Rx chains are separated throughout the front-end. Addition of bands is solved by making the antennas and filters tunable. Banks of duplex filters...

Next generation of optical front-ends for numerical services - 15387

International Nuclear Information System (INIS)

Fullenbaum, M.; Durieux, A.; Dubroca, G.; Fuss, P.

2015-01-01

Visual Inspection and surveillance technology means in environments exhibiting high levels of gamma and neutron radiation are nowadays fulfilled through the use of analog tubes. The images are thus acquired with analog devices whose vast majority relies on 1 and 2/3 inch imaging formats and deliver native analog images. There is a growing demand for real time image processing and distribution through Ethernet services for quicker and seamless process integration throughout many sectors. This will call for the inception of solid state sensor (CCD, CMOS) to generate numerical native images as the first step and building block towards end to end numerical processing (ICT), assuming these sensors can be hardened or protected in the field of the nuclear industry. On the one hand, these sensor sizes will be significantly reduced (by a factor of 2-3) versus those of the tubes, and on the other hand, one will also be presented with the opportunity of increased spatial resolution, stemming from the high pixel count of the solid state technology, for implementation of new or better services or of enhanced pieces of information for decision making purposes. In order to reap the benefits of such sensors, new optical front-ends will have to be designed. Over and beyond the mere aspects of matching the reduced sensor size to the size of the scenes at stake, optical performances of these front-end will also bear an impact on the whole optical chain applications. As an example, detection and tracking needs will be different from a performance standpoint and the overall performances will have to be balanced out in between the optical front-end, the image format, the image processing software capability, processing speed,...just to name a few. In this paper we will review and explain the missing gaps in order to switch to a full numerical optical chain by focusing on the optical front-end and the associated cost trade-offs. Finally, we will conclude by clearly stating the best

TRP and ASIC channels mediate the antinociceptive effect of citronellyl acetate.

Science.gov (United States)

Rios, Emiliano Ricardo Vasconcelos; Rocha, Nayrton Flávio Moura; Carvalho, Alyne Mara Rodrigues; Vasconcelos, Leonardo Freire; Dias, Marília Leite; de Sousa, Damião Pergentino; de Sousa, Francisca Cléa Florenço; Fonteles, Marta Maria de França

2013-05-25

Citronellyl acetate (CAT), a monoterpene product of the secondary metabolism of plants, has been shown in the literature to possess several different biological activities. However, no antinociceptive abilities have yet been discussed. Here, we used acute pain animal models to describe the antinociceptive action of CAT. The acetic acid-induced writhing test and the paw-licking test, in which paw licking was induced by glutamate and formalin, were performed to evaluate the antinociceptive action of CAT and to determine the involvement of PKC, PKA, TRPV1, TRPA1, TRPM8 and ASIC in its antinociceptive mechanism. To do so, we induced paw-linking using agonists. CAT was administered intragastrically (25, 50, 75, 100 and 200 mg/kg), and the two higher doses caused antinociceptive effects in the acetic acid model; the highest dose reduced pain for 4h after it was administered (200 mg/kg). In the formalin test, two doses of CAT promoted antinociception in both the early and later phases of the test. The glutamate test showed that its receptors are involved in the antinociceptive mechanism of CAT. Pretreatment with CAT did not alter locomotor activity or motor coordination. In an investigation into the participation of TRP channels and ASICs in CAT's antinociceptive mechanism, we used capsaicin (2.2 μg/paw), cinnamaldehyde (10 mmol/paw), menthol (1.2 mmol/paw) and acidified saline (2% acetic acid, pH 1.98). The results showed that TRPV1, TRPM8 and ASIC, but not TRPA1, are involved in the antinociceptive mechanism. Finally, the involvement of PKC and PKA was also studied, and we showed that both play a role in the antinociceptive mechanism of CAT. The results of this work contribute information regarding the antinociceptive properties of CAT on acute pain and show that, at least in part, TRPV1, TRPM8, ASIC, glutamate receptors, PKC and PKA participate in CAT's antinociceptive mechanism. Copyright © 2013 Elsevier Ireland Ltd. All rights reserved.

Channel control ASIC for the CMS hadron calorimeter front end readout module

International Nuclear Information System (INIS)

Ray Yarema et al.

2002-01-01

The Channel Control ASIC (CCA) is used along with a custom Charge Integrator and Encoder (QIE) ASIC to digitize signals from the hybrid photo diodes (HPDs) and photomultiplier tubes (PMTs) in the CMS hadron calorimeter. The CCA sits between the QIE and the data acquisition system. All digital signals to and from the QIE pass through the CCA chip. One CCA chip interfaces with two QIE channels. The CCA provides individually delayed clocks to each of the QIE chips in addition to various control signals. The QIE sends digitized PMT or HPD signals and time slice information to the CCA, which sends the data to the data acquisition system through an optical link

A study on the front-end VME system of BEPC II

International Nuclear Information System (INIS)

Wang Chunhong

2004-01-01

The front-end VME system is not only the heart of the control system, but also a real-time system. This paper describes the component of the front-end VME (Versa Module Eurocard) system including control computer and some related I/O modules. Particularly, the authors present a best solution for the problems about Vx-Works kernel and BSP running on MVME5100. This is a fundamental setup of the BEPC II control system. (author)

Implementation of the Timepix ASIC in the Scalable Readout System

Energy Technology Data Exchange (ETDEWEB)

Lupberger, M., E-mail: lupberger@physik.uni-bonn.de; Desch, K.; Kaminski, J.

2016-09-11

We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

A readout system for position sensitive measurements of X-ray using silicon strip detectors

CERN Document Server

Dabrowski, W; Grybos, P; Idzik, M; Kudlaty, J

2000-01-01

In this paper we describe the development of a readout system for X-ray measurements using silicon strip detectors. The limitation concerning the inherent spatial resolution of silicon strip detectors has been evaluated by Monte Carlo simulation and the results are discussed. The developed readout system is based on the binary readout architecture and consists of two ASICs: RX32 front-end chip comprising 32 channels of preamplifiers, shapers and discriminators, and COUNT32 counter chip comprising 32 20-bit asynchronous counters and the readout logic. This work focuses on the design and performance of the front-end chip. The RX32 chip has been optimised for a low detector capacitance, in the range of 1-3 pF, and high counting rate applications. It can be used with DC coupled detectors allowing the leakage current up to a few nA per strip. For the prototype chip manufactured in a CMOS process all basic parameters have been evaluated by electronic measurements. The noise below 140 el rms has been achieved for a ...

AMIC: an expandable integrated analog front-end for light distribution moments analysis

Energy Technology Data Exchange (ETDEWEB)

Spaggiari, M; Herrero, V; Lerche, C W; Aliaga, R; Monzo, J M; Gadea, R, E-mail: michele.spaggiari@gmail.com [Instituto de Instrumentacion para Imagen Molecular (I3M), Universidad Politecnica de Valencia, Camino de Vera, 46022, Valencia (Spain)

2011-01-15

In this article we introduce AMIC (Analog Moments Integrated Circuit), a novel analog Application Specific Integrated Circuit (ASIC) front-end for Positron Emission Tomography (PET) applications. Its working principle is based on mathematical analysis of light distribution through moments calculation. Each moment provides useful information about light distribution, such as energy, position, depth of interaction, skewness (deformation due to border effect) etc. A current buffer delivers a copy of each input current to several processing blocks. The current preamplifier is designed in order to achieve unconditional stability under high input capacitance, thus allowing the use of both Photo-Multiplier Tubes (PMT) and Silicon Photo-Multipliers (SiPM). Each processing block implements an analog current filtering by multiplying each input current by a programmable 8-bit coefficient. The latter is implemented through a high linear MOS current divider ladder, whose high sensitivity to variations in output voltages requires the integration of an extremely stable fully differential current collector. Output currents are then summed and sent to the output stage, that provides both a buffered output current and a linear rail-to-rail voltage for further digitalization. Since computation is purely additive, the 64 input channels of AMIC do not represent a limitation in the number of the detector's outputs. Current outputs of various AMIC structures can be combined as inputs of a final AMIC, thus providing a fully expandable structure. In this version of AMIC, 8 programmable blocks for moments calculation are integrated, as well as an I2C interface in order to program every coefficient. Extracted layout simulation results demonstrate that the information provided by moment calculation in AMIC helps to improve tridimensional positioning of the detected event. A two-detector test-bench is now being used for AMIC prototype characterization and preliminary results are presented.

α-Dendrotoxin inhibits the ASIC current in dorsal root ganglion neurons from rat.

Science.gov (United States)

Báez, Adriana; Salceda, Emilio; Fló, Martín; Graña, Martín; Fernández, Cecilia; Vega, Rosario; Soto, Enrique

2015-10-08

Dendrotoxins are a group of peptide toxins purified from the venom of several mamba snakes. α-Dendrotoxin (α-DTx, from the Eastern green mamba Dendroaspis angusticeps) is a well-known blocker of voltage-gated K(+) channels and specifically of K(v)1.1, K(v)1.2 and K(v)1.6. In this work we show that α-DTx inhibited the ASIC currents in DRG neurons (IC50=0.8 μM) when continuously perfused during 25 s (including a 5 s pulse to pH 6.1), but not when co-applied with the pH drop. Additionally, we show that α-DTx abolished a transient component of the outward current that, in some experiments, appeared immediately after the end of the acid pulse. Our data indicate that α-DTx inhibits ASICs in the high nM range while some Kv are inhibited in the low nM range. The α-DTx selectivity and its potential interaction with ASICs should be taken in consideration when DTx is used in the high nM range. Copyright © 2015 Elsevier Ireland Ltd. All rights reserved.

PAR-2 activation enhances weak acid-induced ATP release through TRPV1 and ASIC sensitization in human esophageal epithelial cells.

Science.gov (United States)

Wu, Liping; Oshima, Tadayuki; Shan, Jing; Sei, Hiroo; Tomita, Toshihiko; Ohda, Yoshio; Fukui, Hirokazu; Watari, Jiro; Miwa, Hiroto

2015-10-15

Esophageal visceral hypersensitivity has been proposed to be the pathogenesis of heartburn sensation in nonerosive reflux disease. Protease-activated receptor-2 (PAR-2) is expressed in human esophageal epithelial cells and is believed to play a role in inflammation and sensation. PAR-2 activation may modulate these responses through adenosine triphosphate (ATP) release, which is involved in transduction of sensation and pain. The transient receptor potential vanilloid receptor 1 (TRPV1) and acid-sensing ion channels (ASICs) are both acid-sensitive nociceptors. However, the interaction among these molecules and the mechanisms of heartburn sensation are still not clear. We therefore examined whether ATP release in human esophageal epithelial cells in response to acid is modulated by TRPV1 and ASICs and whether PAR-2 activation influences the sensitivity of TRPV1 and ASICs. Weak acid (pH 5) stimulated the release of ATP from primary human esophageal epithelial cells (HEECs). This effect was significantly reduced after pretreatment with 5-iodoresiniferatoxin (IRTX), a TRPV1-specific antagonist, or with amiloride, a nonselective ASIC blocker. TRPV1 and ASIC3 small interfering RNA (siRNA) transfection also decreased weak acid-induced ATP release. Pretreatment of HEECs with trypsin, tryptase, or a PAR-2 agonist enhanced weak acid-induced ATP release. Trypsin treatment led to the phosphorylation of TRPV1. Acid-induced ATP release enhancement by trypsin was partially blocked by IRTX, amiloride, or a PAR-2 antagonist. Conversely, acid-induced ATP release was augmented by PAR-2 activation through TRPV1 and ASICs. These findings suggested that the pathophysiology of heartburn sensation or esophageal hypersensitivity may be associated with the activation of PAR-2, TRPV1, and ASICs. Copyright © 2015 the American Physiological Society.

Conception et mise au point de l'électronique frontale du détecteur de pied de gerbe (Preshower) de l'expérience CMS

CERN Document Server

AUTHOR|(CDS)2071023; Ille, B

2001-01-01

Modern particle physics collider experiments consist of a number of macroscopic modules each consisting of large number of sensors measuring charge deposition from traversing particles. The CMS Preshower detector is designed as a sampling calorimeter producing electromagnetic showers for incident electrons and photons resulting from LHC p-p interactions. The ultimate aim is to provide neutral pion / gamma separation reducing the background to the most promising Higgs channel, SM Higgs to 2 photons. The detector has 4300 silicon sensors each subdivided into 32 channels with a total sensitive area of 16.4 m2. Front-end microelectronics ASICs must measure the charge of each channel accurately with low noise and over a wide dynamic range (4 fC to 1600 fC) at the rate of 40 MHz within a harsh radiation environment. This thesis presents the design and development of the Preshower front-end electronics ASIC development, PACE. The first chapter introduces the Preshower experiment and defines the specification for PAC...

Chemical synthesis, 3D structure, and ASIC binding site of the toxin mambalgin-2.

Science.gov (United States)

Schroeder, Christina I; Rash, Lachlan D; Vila-Farrés, Xavier; Rosengren, K Johan; Mobli, Mehdi; King, Glenn F; Alewood, Paul F; Craik, David J; Durek, Thomas

2014-01-20

Mambalgins are a novel class of snake venom components that exert potent analgesic effects mediated through the inhibition of acid-sensing ion channels (ASICs). The 57-residue polypeptide mambalgin-2 (Ma-2) was synthesized by using a combination of solid-phase peptide synthesis and native chemical ligation. The structure of the synthetic toxin, determined using homonuclear NMR, revealed an unusual three-finger toxin fold reminiscent of functionally unrelated snake toxins. Electrophysiological analysis of Ma-2 on wild-type and mutant ASIC1a receptors allowed us to identify α-helix 5, which borders on the functionally critical acidic pocket of the channel, as a major part of the Ma-2 binding site. This region is also crucial for the interaction of ASIC1a with the spider toxin PcTx1, thus suggesting that the binding sites for these toxins substantially overlap. This work lays the foundation for structure-activity relationship (SAR) studies and further development of this promising analgesic peptide. Copyright © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High-density expression of Ca2+-permeable ASIC1a channels in NG2 glia of rat hippocampus.

Directory of Open Access Journals (Sweden)

Yen-Chu Lin

Full Text Available NG2 cells, a fourth type of glial cell in the mammalian CNS, undergo reactive changes in response to a wide variety of brain insults. Recent studies have demonstrated that neuronally expressed acid-sensing ion channels (ASICs are implicated in various neurological disorders including brain ischemia and seizures. Acidosis is a common feature of acute neurological conditions. It is postulated that a drop in pH may be the link between the pathological process and activation of NG2 cells. Such postulate immediately prompts the following questions: Do NG2 cells express ASICs? If so, what are their functional properties and subunit composition? Here, using a combination of electrophysiology, Ca2+ imaging and immunocytochemistry, we present evidence to demonstrate that NG2 cells of the rat hippocampus express high density of Ca2+-permeable ASIC1a channels compared with several types of hippocampal neurons. First, nucleated patch recordings from NG2 cells revealed high density of proton-activated currents. The magnitude of proton-activated current was pH dependent, with a pH for half-maximal activation of 6.3. Second, the current-voltage relationship showed a reversal close to the equilibrium potential for Na+. Third, psalmotoxin 1, a blocker specific for the ASIC1a channel, largely inhibited proton-activated currents. Fourth, Ca2+ imaging showed that activation of proton-activated channels led to an increase of [Ca2+]i. Finally, immunocytochemistry showed co-localization of ASIC1a and NG2 proteins in the hippocampus. Thus the acid chemosensor, the ASIC1a channel, may serve for inducing membrane depolarization and Ca2+ influx, thereby playing a crucial role in the NG2 cell response to injury following ischemia.

A test system for electronics components of the PANDA MVD

Energy Technology Data Exchange (ETDEWEB)

Lai, Alessandra; Stockmanns, Tobias; Ritman, James [Forschungszentrum Juelich (Germany); Collaboration: PANDA-Collaboration

2016-07-01

The PANDA experiment is one of the main devices at the upcoming Facility for Antiproton and Ion Research(FAIR), under construction in Darmstadt, Germany. This fixed target experiment will study the transition region between perturbative and non-perturbative QCD in the energy regime of the charmonium. The innermost sub-detector system of the target spectrometer of the PANDA experiment is the Micro Vertex Detector(MVD). Two types of silicon detectors will be used: pixel detectors and double-sided strip detectors. Two front-end chips are required: the Torino Pixel ASIC(ToPix) and the PANDA Strip ASIC(PASTA). Both are designed to transmit data at a rate of several hundred Megabits per second and are capable of handling the expected hit rate in hot spots of the detector. One key component in the development of new front-end electronics is a test system capable to handle these high rates. It should be flexible enough to test different kinds of front-end electronics and it should be easy to adapt to new prototypes. Therefore, an FPGA-based system is the ideal candidate. For this test system suitable firmware and a software framework are needed. Such a system is under development at the Forschungszentrum Juelich. The main component of the Juelich Digital Readout System(JDRS) is a Virtex 6 FPGA on a development board from Xilinx. In this talk, the mentioned read-out system are introduced, and lab tests with the front-end electronics of the MVD are presented.

An ASIC memory buffer controller for a high speed disk system

Science.gov (United States)

Hodson, Robert F.; Campbell, Steve

1993-01-01

The need for large capacity, high speed mass memory storage devices has become increasingly evident at NASA during the past decade. High performance mass storage systems are crucial to present and future NASA systems. Spaceborne data storage system requirements have grown in response to the increasing amounts of data generated and processed by orbiting scientific experiments. Predictions indicate increases in the volume of data by orders of magnitude during the next decade. Current predictions are for storage capacities on the order of terabits (Tb), with data rates exceeding one gigabit per second (Gbps). As part of the design effort for a state of the art mass storage system, NASA Langley has designed a 144 CMOS ASIC to support high speed data transfers. This paper discusses the system architecture, ASIC design and some of the lessons learned in the development process.

Pixel front-end development in 65 nm CMOS technology

International Nuclear Information System (INIS)

Havránek, M; Hemperek, T; Kishishita, T; Krüger, H; Wermes, N

2014-01-01

Luminosity upgrade of the LHC (HL-LHC) imposes severe constraints on the detector tracking systems in terms of radiation hardness and capability to cope with higher hit rates. One possible way of keeping track with increasing luminosity is the usage of more advanced technologies. Ultra deep sub-micron CMOS technologies allow a design of complex and high speed electronics with high integration density. In addition, these technologies are inherently radiation hard. We present a prototype of analog pixel front-end integrated circuit designed in 65 nm CMOS technology with applications oriented towards the ATLAS Pixel Detector upgrade. The aspects of ultra deep sub-micron design and performance of the analog pixel front-end circuits will be discussed

Finite-element simulations of coupling capacitances in capacitively coupled pixel detectors

CERN Document Server

AUTHOR|(SzGeCERN)755510

2017-01-01

Capacitively coupled hybrid silicon pixel-detector assemblies are under study for the vertex detector at the proposed future CLIC linear electron-positron collider. The assemblies consist of active CCPDv3 sensors, with 25 μm pixel pitch implemented in a 180 nm High- Voltage CMOS process, which are glued to the CLICpix readout ASIC, with the same pixel pitch and processed in a commercial 65 nm CMOS technology. The signal created in the silicon bulk of the active sensors passes a two-stage amplifier, in each pixel, and gets transferred as a voltage pulse to metal pads facing the readout chip (ROC). The coupling of the signal to the metal pads on the ROC side proceeds through the capacitors formed between the two chips by a thin layer of epoxy glue. The coupling strength and the amount of unwanted cross coupling to neighbouring pixels depends critically on the uniformity of the glue layer, its thickness and on the alignment precision during the flip-chip assembly process. Finite-element calculations of the coup...

Front-end electronics for accurate energy measurement of double beta decays

International Nuclear Information System (INIS)

Gil, A.; Díaz, J.; Gómez-Cadenas, J.J.; Herrero, V.; Rodriguez, J.; Serra, L.; Toledo, J.; Esteve, R.; Monzó, J.M.; Monrabal, F.; Yahlali, N.

2012-01-01

NEXT, a double beta decay experiment that will operate in Canfranc Underground Laboratory (Spain), aims at measuring the neutrinoless double-β decay of the 136Xe isotope using a TPC filled with enriched Xenon gas at high pressure operated in electroluminescence mode. One technological challenge of the experiment is to achieve resolution better than 1% in the energy measurement using a plane of UV sensitive photomultipliers readout with appropriate custom-made front-end electronics. The front-end is designed to be sensitive to the single photo-electron to detect the weak primary scintillation light produced in the chamber, and also to be able to cope with the electroluminescence signal (several hundred times higher and with a duration of microseconds). For efficient primary scintillation detection and precise energy measurement of the electroluminescent signals the front-end electronics features low noise and adequate amplification. The signal shaping provided allows the digitization of the signals at a frequency as low as 40 MHz.

Low-Power Receive-Electronics for a Miniature 3D Ultrasound Probe

NARCIS (Netherlands)

Yu, Z.

2012-01-01

This thesis describes the design of a front-end application-specific integrated circuit (ASIC), which will be put into the tip of a miniature ultrasound probe for 3D Trans-Esophageal Echocardiography (TEE). To enable 3D TEE, a matrix piezoelectric ultrasound transducer with more than 2000 elements

AMPLITUDE AND TIME MEASUREMENT ASIC WITH ANALOG DERANDOMIZATION

International Nuclear Information System (INIS)

O CONNOR, P.; DE GERONIMO, G.; KANDASAMY, A.

2002-01-01

We describe a new ASIC for accurate and efficient processing of high-rate pulse signals from highly segmented detectors. In contrast to conventional approaches, this circuit affords a dramatic reduction in data volume through the use of analog techniques (precision peak detectors and time-to-amplitude converters) together with fast arbitration and sequencing logic to concentrate the data before digitization. In operation the circuit functions like a data-driven analog first-in, first-out (FIFO) memory between the preamplifiers and the ADC. Peak amplitudes of pulses arriving at any one of the 32 inputs are sampled, stored, and queued for readout and digitization through a single output port. Hit timing, pulse risetime, and channel address are also available at the output. Prototype chips have been fabricated in 0.35 micron CMOS and tested. First results indicate proper functionality for pulses down to 30 ns peaking time and input rates up to 1.6 MHz/channel. Amplitude accuracy of the peak detect and hold circuit is 0.3% (absolute). TAC accuracy is within 0.3% of full scale. Power consumption is less than 2 mW/channel. Compared with conventional techniques such as track-and-hold and analog memory, this new ASIC will enable efficient pulse height measurement at 20 to 300 times higher rates

Study of multi-channel readout ASIC and its discrete module for particle detector

International Nuclear Information System (INIS)

Wang Ke; Fan Lei; Zhang Shengjun; Li Xian

2013-01-01

Recently, kinds of particle detectors have used Application Specific Integrated Circuits (ASIC) in their electronics readout systems, it is the key part for the whole system. This project designed a multi-channel readout ASIC for general detectors. The chip has Preamplifier, Shaper and Peak Detector embedded for easy readout. For each channel, signal which is preprocessed by a low-noise preamplifier is sent to the shaper to form a quasi-Gaussian pulse and keep its peak for readout. This chip and modules of individual Preamplifier, Shaper and Peak Detector have been manufactured and tested. The discrete modules work well, and the 6-channel chip NPRE 6 is ready for test in some particle detection system. (authors)

Differential effects of temperature on acid-activated currents mediated by TRPV1 and ASIC channels in rat dorsal root ganglion neurons.

Science.gov (United States)

Neelands, Torben R; Zhang, Xu-Feng; McDonald, Heath; Puttfarcken, Pamela

2010-05-06

Elevated temperature and decreased extracellular pH are hallmarks of inflammatory pain states. Dorsal root ganglia (DRG) neurons are integral in transferring painful stimuli from the periphery to central sites. This study investigated the effect of elevated temperatures on the response of DRG neurons to acute application of acidic solutions. At room temperature (22 degrees C), in response to pH 5.5, there were a variety of kinetic responses consistent with differential expression of TRPV1 and ASIC channels. Increasing the temperature resulted in a significant increase in the peak and total current mediated by TRPV1 in response to an acidic solution. In contrast, the amplitude of a fast activating, rapidly inactivating ASIC1-like current was not affected by increasing the temperature but did result in an increased rate of desensitization that reduced the total current level. This effect on the rate of desensitization was temperature-dependent and could be reversed by returning to 22 degrees C. Likewise, cells exhibiting slowly inactivating ASIC2-like responses also had temperature-dependent increase in the rate of desensitization. The ASIC2-like responses and the TRPV1 responses tended to decrease in amplitude with repetitive application of pH 5.5 even at 22 degrees C. The rate of desensitization of ASIC-like currents activated by less acidic solutions (pH 6.8) was also increased in a temperature-dependent manner. Finally, acidic pH reduced threshold to trigger action potentials, however, the pattern of action potential firing was shaped by the distribution of ASIC and TRPV1 channels. These results indicate that the ambient temperature at which acidosis occurs has a profound effect on the contribution of ASIC and TRPV1 channels, therefore, altering the neuronal excitability. Copyright 2010 Elsevier B.V. All rights reserved.

A wireless capsule system with ASIC for monitoring the physiological signals of the human gastrointestinal tract.

Science.gov (United States)

Xu, Fei; Yan, Guozheng; Zhao, Kai; Lu, Li; Gao, Jinyang; Liu, Gang

2014-12-01

This paper presents the design of a wireless capsule system for monitoring the physiological signals of the human gastrointestinal (GI) tract. The primary components of the system include a wireless capsule, a portable data recorder, and a workstation. Temperature, pH, and pressure sensors; an RF transceiver; a controlling and processing application specific integrated circuit (ASIC); and batteries were applied in a wireless capsule. Decreasing capsule size, improving sensor precision, and reducing power needs were the primary challenges; these were resolved by employing micro sensors, optimized architecture, and an ASIC design that include power management, clock management, a programmable gain amplifier (PGA), an A/D converter (ADC), and a serial peripheral interface (SPI) communication unit. The ASIC has been fabricated in 0.18- μm CMOS technology with a die area of 5.0 mm × 5.0 mm. The wireless capsule integrating the ASIC controller measures Φ 11 mm × 26 mm. A data recorder and a workstation were developed, and 20 cases of human experiments were conducted in hospitals. Preprocessing in the workstation can significantly improve the quality of the data, and 76 original features were determined by mathematical statistics. Based on the 13 optimal features achieved in the evaluation of the features, the clustering algorithm can identify the patients who lack GI motility with a recognition rate reaching 83.3%.

A CMOS frontend chip for implantable neural recording with wide voltage supply range

International Nuclear Information System (INIS)

Liu Jialin; Zhang Xu; Hu Xiaohui; Li Peng; Liu Ming; Chen Hongda; Guo Yatao; Li Bin

2015-01-01

A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC). The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a −3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μV rms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits (ENOB) of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm 2 (including pads). In-vitro recording was successfully carried out by the proposed frontend chip. (paper)

Characterization of the front-end EASIROC for read-out of SiPM in the ASTRI camera

International Nuclear Information System (INIS)

Impiombato, D.; Giarrusso, S.; Belluso, M.; Billotta, S.; Bonanno, G.; Catalano, O.; Grillo, A.; La Rosa, G.; Marano, D.; Mineo, T.; Russo, F.; Sottile, G.

2013-01-01

The design and realization of a prototype for the Small-Size class Telescopes of the Cherenkov Telescope Array is one of the cornerstones of the ASTRI project. The prototype will adopt a focal plane camera based on Silicon Photo-Multiplier sensors that coupled with a dual mirror optics configuration represents an innovative solution for the detection of Atmospheric Cherenkov light. These detectors can be read by the Extended Analogue Silicon Photo-Multiplier Integrated Read Out Chip (EASIROC) equipped with 32-channels. In this paper, we report some preliminary results on measurements aimed to evaluate EASIROC capability of autotriggering and measurements of the trigger time walk, jitter, DAC linearity and trigger efficiency vs the injected charge. Moreover, the dynamic range of the ASIC is also reported

A 0.18 μm biosensor front-end based on 1/f noise, distortion cancelation and chopper stabilization techniques.

Science.gov (United States)

Balasubramanian, Viswanathan; Ruedi, Pierre-Francois; Temiz, Yuksel; Ferretti, Anna; Guiducci, Carlotta; Enz

2013-10-01

This paper presents a novel sensor front-end circuit that addresses the issues of 1/f noise and distortion in a unique way by using canceling techniques. The proposed front-end is a fully differential transimpedance amplifier (TIA) targeted for current mode electrochemical biosensing applications. In this paper, we discuss the architecture of this canceling based front-end and the optimization methods followed for achieving low noise, low distortion performance at minimum current consumption are presented. To validate the employed canceling based front-end, it has been realized in a 0.18 μm CMOS process and the characterization results are presented. The front-end has also been tested as part of a complete wireless sensing system and the cyclic voltammetry (CV) test results from electrochemical sensors are provided. Overall current consumption in the front-end is 50 μA while operating on a 1.8 V supply.

A low power 3-5 GHz CMOS UWB receiver front-end

International Nuclear Information System (INIS)

Li Weinan; Huang Yumei; Hong Zhiliang

2009-01-01

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13 μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below -8.5 dB across the 3.1-4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of -11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 x 1.5 mm 2 .

A 58 nW ECG ASIC With Motion-Tolerant Heartbeat Timing Extraction for Wearable Cardiovascular Monitoring.

Science.gov (United States)

Da He, David; Sodini, Charles G

2015-06-01

An ASIC for wearable cardiovascular monitoring is implemented using a topology that takes advantage of the electrocardiogram's (ECG) waveform to replace the traditional ECG instrumentation amplifier, ADC, and signal processor with a single chip solution. The ASIC can extract heartbeat timings in the presence of baseline drift, muscle artifact, and signal clipping. The circuit can operate with ECGs ranging from the chest location to remote locations where the ECG magnitude is as low as 30 μV. Besides heartbeat detection, a midpoint estimation method can accurately extract the ECG R-wave timing, enabling the calculations of heart rate variability. With 58 nW of power consumption at 0.8 V supply voltage and 0.76 mm (2) of active die area in standard 0.18 μm CMOS technology, the ECG ASIC is sufficiently low power and compact to be suitable for long term and wearable cardiovascular monitoring applications under stringent battery and size constraints.

Triroc: A Multi-Channel SiPM Read-Out ASIC for PET/PET-ToF Application

Science.gov (United States)

Ahmad, Salleh; Fleury, Julien; de la Taille, Christophe; Seguin-Moreau, Nathalie; Dulucq, Frederic; Martin-Chassard, Gisele; Callier, Stephane; Thienpont, Damien; Raux, Ludovic

2015-06-01

Triroc is the latest addition to SiPM readout ASICs family developed at Weeroc, a start-up company from the Omega microelectronics group of IN2P3/CNRS. This chip is developed under the framework TRIMAGE European project which is aimed for building a cost effective tri-modal PET/MR/EEG brain scan. To ensure the flexibility and compatibility with any SiPM in the market, the ASIC is designed to be capable of accepting negative and positive polarity input signals. This 64-channel ASIC, is suitable for SiPM readout which requires high accuracy timing and charge measurements. Targeted applications would be PET prototyping with time-of-flight capability. Main features of Triroc includes high dynamic range ADC up to 2500 photoelectrons and TDC fine time binning of 40 ps. Triroc requires very minimal external components which means it is a good contender for compact multichannel PET prototyping. Triroc is designed by using AMS 0.35 μm SiGe technology and it was submitted in March 2014. The detail design of this chip will be presented.

Front-end electronics for multichannel semiconductor detector systems

CERN Document Server

Grybos, P

2010-01-01

Front-end electronics for multichannel semiconductor detektor systems Volume 08, EuCARD Editorial Series on Accelerator Science and Technology The monograph is devoted to many different aspects related to front-end electronics for semiconductor detector systems, namely: − designing and testing silicon position sensitive detectors for HEP experiments and X-ray imaging applications, − designing and testing of multichannel readout electronics for semiconductor detectors used in X-ray imaging applications, especially for noise minimization, fast signal processing, crosstalk reduction and good matching performance, − optimization of semiconductor detection systems in respect to the effects of radiation damage. The monograph is the result mainly of the author's experience in the above-mentioned areas and it is an attempt of a comprehensive presentation of issues related to the position sensitive detection system working in a single photon counting mode and intended to X-ray imaging applications. The structure...

Coarse Grain Reconfigurable ASIC through Multiplexer Based Switches

Science.gov (United States)

2015-09-15

chip area (0.5 mm2), and from simulation their power consumption is negligible (0.002% from simulation, too small to measure in physical system...performing implementation that is also flexible. REFERENCES [1] I. Kuon and J. Rose, “ Measuring the gap between FPGAs and ASICs,” IEEE Trans...A 3GPP- LTE Example," Solid-State Circuits, IEEE Journal of , vol.47, no.3, pp.757,768, March 2012. [5] Agarwal, A.; Hassanieh, H.; Abari, O

Development of a low-noise, two-dimensional amplifier array

International Nuclear Information System (INIS)

Kishishita, Tetsuichi; Ikeda, Hirokazu; Sakumura, Takuto; Tamura, Ken-ichi; Takahashi, Tadayuki

2009-01-01

This paper describes the recent development of a low-noise, two-dimensional analog front-end ASIC for hybrid pixel imaging detectors. Based on the Open-IP LSI project, the ASIC is designed to meet a low-noise requirement of better than 100e - (rms) with self-triggering capability. The ASIC is intended for the readout of pixel sensors utilizing silicon (Si) and cadmium telluride (CdTe) as detector materials for spectroscopic imaging observations in the X-ray and gamma-ray regions. The readout chip consists of a 4x4 matrix of identical 270μmx270μm pixel cells and was implemented with TSMC 0.35-μm CMOS technology. Each pixel cell contains a charge-sensitive amplifier, pole-zero cancellation circuit, shaper, comparator, and peak hold circuit. Preliminary testing of the ASIC achieved an 88e - (rms) equivalent noise charge and a 25e - /pF noise slope with power consumption of 150μW per pixel.

A multichannel time-to-digital converter ASIC with better than 3 ps RMS time resolution

International Nuclear Information System (INIS)

Perktold, L; Christiansen, J

2014-01-01

The development of a new multichannel, fine-time resolution time-to-digital converter (TDC) ASIC is currently under development at CERN. A prototype TDC has been designed, fabricated and successfully verified with demonstrated time resolutions of better than 3 ps-rms. Least-significant-bit (LSB) sizes as small as 5 ps with a differential-non-linearity (DNL) of better than ±0.9 LSB and integral-non-linearity (INL) of better than ±1.3 LSB respectively have been achieved. The contribution describes the implemented architecture and presents measurement results of a prototype ASIC implemented in a commercial 130 nm technology

Tracker Readout ASIC for Proton Computed Tomography Data Acquisition.

Science.gov (United States)

Johnson, Robert P; Dewitt, Joel; Holcomb, Cole; Macafee, Scott; Sadrozinski, Hartmut F-W; Steinberg, David

2013-10-01

A unique CMOS chip has been designed to serve as the front-end of the tracking detector data acquisition system of a pre-clinical prototype scanner for proton computed tomography (pCT). The scanner is to be capable of measuring one to two million proton tracks per second, so the chip must be able to digitize the data and send it out rapidly while keeping the front-end amplifiers active at all times. One chip handles 64 consecutive channels, including logic for control, calibration, triggering, buffering, and zero suppression. It outputs a formatted cluster list for each trigger, and a set of field programmable gate arrays merges those lists from many chips to build the events to be sent to the data acquisition computer. The chip design has been fabricated, and subsequent tests have demonstrated that it meets all of its performance requirements, including excellent low-noise performance.

Implementation of the ASDBLR straw tube readout ASIC in DMILL technology

CERN Document Server

Dressnandt, N; Newcomer, F M; Van Berg, R; Williams, H H

2001-01-01

The ASDBLR ASIC provides eight channels of low noise, low power, high rate on-detector readout suitable for the ATLAS Transition Radiation Tracker (TRT) at the LHC. The TRT's unprecedented wire chamber readout requirements of a maximum hit rate per wire of 20MHz and double pulse resolution of similar to 25ns with position resolution of better than 150mum in a high radiation environment have been addressed in the design of the ASDBLR. A carefully tuned ion tail cancellation stage followed by an output sensing baseline restorer implemented in differential structures provides robust signal processing combination compatible with the realities of ASIC design. Two comparators track the output of the signal processing stage to provide Tracking information from charged particles and evidence of higher energy Transition Radiation (TR) photons; their outputs are summed as current steps to form a differential ternary output. The ten year total dose requirement for neutrons of 10**1**4 n/cm**2 and 1.5 MRad of ionizing ra...

Design and Characterization of the VMM1 ASIC for Micropattern Gas Detectors

CERN Document Server

Metcalfe, J; The ATLAS collaboration; Fried, J; Li, S; Nambiar, N; Polychronakos, V; Vernon, E

2013-01-01

We present here the measurements of the first prototype VMM1 ASIC designed at Brookhaven National Laboratory in 130 nm CMOS and fabricated in spring 2012. The 64-channel ASIC features a novel design for use with several types of micropattern gas detectors. The data driven system measures peak amplitude and timing information in tracking mode and first channel hit address in trigger mode. Several programmable gain and integration times allows the flexibility to work with Micromegas, Thin Gap Chambers (TGCs), and Gas Electron Multiplier (GEM) detectors. The IC design architecture and features will be presented along with measurements characterizing the performance of the VMM1 such as noise, linearity of the response, time walk, and calibration range. The concept for use with Micromegas in ATLAS Upgrade will also be covered including characterization under test beam conditions.

Upgrading FLIR NanoRaider with the next Generation of CdZnTe Detectors. Goal - Integrate VFG detectors into FLIR R200. Advanced Virtual Grid ASIC (AVG-ASIC).

Energy Technology Data Exchange (ETDEWEB)

Bolotnikov, Aleksey [Brookhaven National Lab. (BNL), Upton, NY (United States); Cui, Yonggang [Brookhaven National Lab. (BNL), Upton, NY (United States); Vernon, Emerson [Brookhaven National Lab. (BNL), Upton, NY (United States); De Geronimo, Gianluigi [Brookhaven National Lab. (BNL), Upton, NY (United States)

2016-06-01

This document presents motivations, goals and the current status of this project; development (fabrication, performance) of position-sensitive virtual Frisch-grid detectors proposed for nanoRaider, an instrument commonly used by nuclear inspectors; ASIC developments for CZT detectors; and the electronics development for the detector prototype..

ASIC-like currents in freshly isolated cerebral artery smooth muscle cells are inhibited by endogenous oxidase activity.

Science.gov (United States)

Chung, Wen-Shuo; Farley, Jerry M; Drummond, Heather A

2011-01-01

The aim of this study was to determine if VSMC ASIC-like currents are regulated by oxidative state. We used whole-cell patch clamp of isolated mouse cerebral VSMCs to determine if 1) reducing agents, such as DTT and GSH, and 2) inhibition of endogenous oxidase activity from NADPH and Xanthine oxidases potentiate active currents and activate electrically silent currents. Pretreatment with 2 mM DTT or GSH, increased the mean peak amplitude of ASIC-like currents evoked by pH 6.0 from 0.4 ± 0.1 to 14.9 ± 3.6 pA/pF, and from 0.9 ± 0.3 to 11.3 ± 2.4 pA/pF, respectively. Pretreatment with apocynin, a NADPH oxidase inhibitor, mimics the effect of the reducing agents, with the mean peak current amplitude increased from 0.9 ± 0.5 to 7.0 ± 2.6 pA/pF and from 0.5 ± 0.2 to 26.4 ± 6.8 pA/pF by 50 and 200 μM apocynin, respectively. Pretreatment with allopurinol, a xanthine oxidase inhibitor, also potentiates the VSMC ASIC-like activity. These findings suggest that VSMC ASIC-like channels are regulated by oxidative state and may be inhibited by basal endogenous oxidative sources such as NADPH and xanthine oxidase. Copyright © 2011 S. Karger AG, Basel.

The front-end amplifier for the silicon microstrip sensors of the PANDA MVD

Energy Technology Data Exchange (ETDEWEB)

Di Pietro, Valentino; Brinkmann, Kai-Thomas; Riccardi, Alberto [II. Physikalisches Institut, JLU Giessen (Germany); Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino (Italy)

2015-07-01

The most common readout systems designed for the nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made from two main building blocks: front-end amplifier and ADC. One of the issues associated with the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the possibility of using time-based architectures offering better performances from that point of view. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work will present the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The key features of the front-end amplifier are illustrated and both schematic level, and post-layout simulations are discussed.

Synchronisation of the LHC Betatron Coupling and Phase Advance Measurement System

CERN Document Server

Gasior, M

2014-01-01

The new LHC Diode ORbit and OScillation (DOROS) system will provide beam position readings with submicrometre resolution and at the same time will be able to perform measurements of local betatron coupling and beam phase advance with micrometre beam excitation. The oscillation sub-system employs gain-controlled RF amplifiers, shared with the orbit system, and followed by dedicated diode detectors to demodulate the beam oscillation signals into the kHz frequency range, subsequently digitized by multi-channel 24-bit ADCs. The digital signals are processed in each front-end with an FPGA and the results of reduced throughput are sent using an Ethernet protocol to a common concentrator, together with the orbit data. The phase advance calculation between multiple Beam Position Monitors (BPMs) requires that all DOROS front-ends have a common phase reference. This paper presents methods used to generate such a reference and to maintain a stable synchronous sampling on all system front-ends. The performance of the DOR...

RF-Frontend Design for Process-Variation-Tolerant Receivers

CERN Document Server

Sakian, Pooyan; van Roermund, Arthur

2012-01-01

This book discusses a number of challenges faced by designers of wireless receivers, given complications caused by the shrinking of electronic and mobile devices circuitry into ever-smaller sizes and the resulting complications on the manufacturability, production yield, and the end price of the products.  The authors describe the impact of process technology on the performance of the end product and equip RF designers with countermeasures to cope with such problems.  The mechanisms by which these problems arise are analyzed in detail and novel solutions are provided, including design guidelines for receivers with robustness to process variations and details of circuit blocks that obtain the required performance level. Describes RF receiver frontends and their building blocks from a system- and circuit-level perspective; Provides system-level analysis of a generic RF receiver frontend with robustness to process variations; Includes details of CMOS circuit design at 60GHz and reconfigurable circuits at 60GHz...

A generic miniature multi-feature programmable wireless powering headstage ASIC for implantable biomedical systems.

Science.gov (United States)

Kubendran, Rajkumar; Krishnan, Harish; Manola, Bhupendra; John, Simon W M; Chappell, William J; Irazoqui, Pedro P

2011-01-01

Wireless powering holds immense promise to enable a variety of implantable biomedical measurement systems with different power supply and current budget requirements. Effective power management demands more functionality in the headstage design like power level detection for range estimation and power save modes for sleep-wake operation. This paper proposes a single chip ASIC solution that addresses these problems by incorporating digitally programmable features and thus has the potential to enable wireless powering for many implantable systems. The ASIC includes an RF rectifier which has a peak efficiency of 17.9% at 900 MHz and 11.0% at 2.4 GHz, a robust 1 V bandgap reference and LDO voltage regulator whose output can be programmed in the range of 1 V-1.5 V, and can drive upto 4 mA of load current. The input RF power level detector has a threshold of 1.6 V and the power management block can be programmed to give a 6%, 12.5% or 25% duty cycle power line to the transmitter resulting in upto 60% reduction in average power. The ASIC was fabricated using the TSMC 65 nm process, occupies 1mm(2) die area and the headstage consumes ~300 μA at 1.2V regulated supply.

Design of a low-power 433/915-MHz RF front-end with a current-reuse common-gate LNA

International Nuclear Information System (INIS)

Jing Yiou; Lu Huaxiang

2013-01-01

This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier (LNA), current-reuse V—I converter, active double balanced mixer and transimpedance amplifier for short range device (SRD) applications. With the proposed current-reuse LNA, the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices. The RF front-end was fabricated in 0.18 μm RFCMOS process and occupies a silicon area of just 0.11 mm 2 . Operating in 433 MHz band, the measurement results show the RF front-end achieves a conversion gain of 29.7 dB, a double side band noise figure of 9.7 dB, an input referenced third intercept point of −24.9 dBm with only 1.44 mA power consumption from 1.8 V supply. Compared to other reported front-ends, it has an advantage in power consumption. (semiconductor integrated circuits)

A 2.5 gb/s GaAs ATM Mux Demux ASIC

DEFF Research Database (Denmark)

Madsen, Jens Kargaard; Lassen, Peter Stuhr

1995-01-01

This paper describes the design and implementation of a high speed GaAs ATM Mux Demur ASIC (AMDA) which is the key element in a high speed ATM Add-Drop unit. This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broadband switching systems. The Add-Drop unit...

Phase 1 upgrade of the CMS forward hadronic calorimeter

CERN Document Server

Noonan, Daniel Christopher

2017-01-01

The CMS experiment at the Large Hadron Collider at CERN is upgrading the photo- detection and readout system of the forward hadronic calorimeter. The phase 1 upgrade of the CMS forward calorimeter requires the replacement of the current photomultiplier tubes, as well as the installation of a new front-end readout system. The new photomultiplier tubes contain a thinner window as well as multi-anode readout. The front-end electronics will use the QIE10 ASIC which combines signal digitization with timing information. The major components of the upgrade as well as the current status are described in this paper.

arXiv Construction and beam-tests of silicon-tungsten prototype modules for the CMS High Granularity Calorimeter for HL-LHC

CERN Document Server

INSPIRE-00664095

2018-02-26

As part of its HL-LHC upgrade program, CMS is developing a High Granularity Calorimeter (HGCAL) to replace the existing endcap calorimeters. The HGCAL will be realised as a sampling calorimeter, including an electromagnetic compartment comprising 28 layers of silicon pad detectors with pad areas of 0.5–1.0 cm2 interspersed with absorbers. Prototype modules, based on 6-inch hexagonal silicon pad sensors with 128 channels, have been constructed and include many of the features required for this challenging detector. In 2016, beam tests of sampling configurations made from these modules have been conducted both at FNAL and at CERN using the Skiroc2 front-end ASIC (designed by the CALICE collaboration for ILC). In 2017, the setup has been extended with CALICE's AHCAL prototype, a scinitillator based sampling calorimeter, and it was further tested in dedicated beam tests at CERN. There, the new Skiroc2-CMS front-end ASIC was used for the first time. We highlight final results from our studies in 2016, including ...

Tuned Optical Front-End MMIC Amplifiers for a Coherent Optical Receiver

DEFF Research Database (Denmark)

Petersen, Anders Kongstad; Jagd, A M

1992-01-01

Two low noise tuned optical front-end GaAs MESFET MMIC amplifiers for a coherent optical CPFSK (Continuous Phase Frequency Shift Keying) receiver are presented. The receiver operates at 2.5 Gbit/s at an IF of approx. 9 GHz. The front-ends are based on full-custom designed MMICs and a commercially...... available GaInAs/InP pin photo diode. The procedure for measuring the transimpedance and the equivalent input noise current density is outlined in this paper and demonstrated using one of the MMICs. The MMICs were fabricated using the Plessey F20 process by GEC-Marconi through the ESPRIT programme EUROCHIP...

Threshold equalization algorithm for the XAA1.2 ASICs and its application to SuperAGILE X-ray imager

International Nuclear Information System (INIS)

Pacciani, Luigi; Uberti, Olga; Del Monte, Ettore; Argan, Andrea; Feroci, Marco; Soffitta, Paolo; Trois, Alessio; Costa, Enrico; Donnarumma, Immacolata; Evangelista, Yuri; Lazzarotto, Francesco; Rapisarda, Massimo; Morelli, Ennio; Mastropietro, Marcello; Rubini, Alda

2008-01-01

In this paper we report the procedure developed and the results achieved for the equalization of threshold levels for the 6144 discriminator units of XAA1.2 ASICs chosen for the SuperAGILE X-ray imager onboard the AGILE satellite. For these kinds of imager, we will show that the threshold equalization is a critical issue. For each XAA1.2 we reduced the threshold dispersion by a factor of 3-4, and a factor of ∼2 for daisy chains of ASICs. Despite the method being developed for XAA1.2, the discriminator units and threshold fine-adjustment circuits are common to other chips of XA and VA-TA family, so that the algorithm and results can be extended to these two families of ASICs. This work may be useful for the design of electronic boards where the threshold equalization is a crucial issue

Threshold equalization algorithm for the XAA1.2 ASICs and its application to SuperAGILE X-ray imager

Energy Technology Data Exchange (ETDEWEB)

Pacciani, Luigi [Istituto di Fisica Spaziale e Fisica Cosmica, INAF, Roma, via Fosso del Cavaliere, 100-I-00133 Roma (Italy)], E-mail: luigi.pacciani@iasf-roma.inaf.it; Uberti, Olga; Del Monte, Ettore; Argan, Andrea; Feroci, Marco; Soffitta, Paolo; Trois, Alessio; Costa, Enrico; Donnarumma, Immacolata; Evangelista, Yuri; Lazzarotto, Francesco [Istituto di Fisica Spaziale e Fisica Cosmica, INAF, Roma, via Fosso del Cavaliere, 100-I-00133 Roma (Italy); Rapisarda, Massimo [ENEA C.R. Frascati, via Enrico Fermi, 45, I-00044 Frascati (RM) (Italy); Morelli, Ennio [Istituto di Fisica Spaziale e Fisica Cosmica, INAF, Bologna, via P. Gobetti, 101-I-40129 Bologna (Italy); Mastropietro, Marcello [Istituto dei Sistemi Complessi, CNR, Roma, via Salaria, km 29300, I-00016 Monterotondo Scalo (RM) c.p. 10 (Italy); Rubini, Alda [Istituto di Fisica Spaziale e Fisica Cosmica, INAF, Roma, via Fosso del Cavaliere, 100-I-00133 Roma (Italy)

2008-08-11

In this paper we report the procedure developed and the results achieved for the equalization of threshold levels for the 6144 discriminator units of XAA1.2 ASICs chosen for the SuperAGILE X-ray imager onboard the AGILE satellite. For these kinds of imager, we will show that the threshold equalization is a critical issue. For each XAA1.2 we reduced the threshold dispersion by a factor of 3-4, and a factor of {approx}2 for daisy chains of ASICs. Despite the method being developed for XAA1.2, the discriminator units and threshold fine-adjustment circuits are common to other chips of XA and VA-TA family, so that the algorithm and results can be extended to these two families of ASICs. This work may be useful for the design of electronic boards where the threshold equalization is a crucial issue.

Second LaBr3 Compton Telescope Prototype

International Nuclear Information System (INIS)

Llosa, Gabriela; Cabello, Jorge; Gillam, John-E.; Lacasta, Carlos; Oliver, Josep F.; Rafecas, Magdalena; Solaz, Carles; Solevi, Paola; Stankova, Vera; Torres-Espallardo, Irene; Trovato, Marco

2013-06-01

A Compton telescope for dose delivery monitoring in hadron therapy is under development at IFIC Valencia within the European project ENVISION. The telescope will consist of three detector planes, each one composed of a LaBr 3 continuous scintillator crystal coupled to four silicon photomultiplier (SiPM) arrays. After the development of a first prototype which served to assess the principle, a second prototype with larger crystals has been assembled and is being tested. The current version of the prototype consists of two detector layers, each one composed of a 32.5 x 35 mm 2 crystal coupled to four SiPM arrays. The VATA64HDR16 ASIC has been employed as front-end electronics. The readout system consists of a custom made data acquisition board. Tests with point-like sources have been carried out in the laboratory, assessing the correct functioning of the device. The system optimization is ongoing. (authors)

Development of X-ray CCD camera system with high readout rate using ASIC

International Nuclear Information System (INIS)

Nakajima, Hiroshi; Matsuura, Daisuke; Anabuki, Naohisa; Miyata, Emi; Tsunemi, Hiroshi; Doty, John P.; Ikeda, Hirokazu; Katayama, Haruyoshi

2009-01-01

We report on the development of an X-ray charge-coupled device (CCD) camera system with high readout rate using application-specific integrated circuit (ASIC) and Camera Link standard. The distinctive ΔΣ type analog-to-digital converter is introduced into the chip to achieve effective noise shaping and to obtain a high resolution with relatively simple circuits. The unit test proved moderately low equivalent input noise of 70μV with a high readout pixel rate of 625 kHz, while the entire chip consumes only 100 mW. The Camera Link standard was applied for the connectivity between the camera system and frame grabbers. In the initial test of the whole system, we adopted a P-channel CCD with a thick depletion layer developed for X-ray CCD camera onboard the next Japanese X-ray astronomical satellite. The characteristic X-rays from 109 Cd were successfully read out resulting in the energy resolution of 379(±7)eV (FWHM) at 22.1 keV, that is, ΔE/E=1.7% with a readout rate of 44 kHz.

Measuring Single Event Upsets in the ATLAS Inner Tracker

CERN Multimedia

CERN. Geneva

2015-01-01

When the HL-LHC starts collecting data, the electronics inside will be subject to massive amounts of radiation. As a result, single event upsets could pose a threat to the ATLAS readout chain. The ABC130, a prototype front-end ASIC for the ATLAS inner tracker, must be tested for its susceptibility to single event upsets.

Design for ASIC reliability for low-temperature applications

Science.gov (United States)

Chen, Yuan; Mojaradi, Mohammad; Westergard, Lynett; Billman, Curtis; Cozy, Scott; Burke, Gary; Kolawa, Elizabeth

2005-01-01

In this paper, we present a methodology to design for reliability for low temperature applications without requiring process improvement. The developed hot carrier aging lifetime projection model takes into account both the transistor substrate current profile and temperature profile to determine the minimum transistor size needed in order to meet reliability requirements. The methodology is applicable for automotive, military, and space applications, where there can be varying temperature ranges. A case study utilizing this methodology is given to design for reliability into a custom application-specific integrated circuit (ASIC) for a Mars exploration mission.

Calibration method for direct conversion receiver front-ends

Directory of Open Access Journals (Sweden)

R. Müller

2008-05-01

Full Text Available Technology induced process tolerances in analog circuits cause device characteristics different from specification. For direct conversion receiver front-ends a system level calibration method is presented. The malfunctions of the devices are compensated by tuning dominant circuit parameters. Thereto optimization techniques are applied which use measurement values and special evaluation functions.

Front end readout electronics for the CMS hadron calorimeter

CERN Document Server

Shaw, Terri M

2002-01-01

The front-end electronics for the CMS Hadron Calorimeter provides digitized data at the beam interaction rate of 40 MHz. Analog signals provided by hybrid photodiodes (HPDs) or photomultiplier tubes (PMTs) are digitized and the data is sent off board through serialized fiber optic links running at 1600 Mbps. In order to maximize the input signal, the front-end electronics are housed on the detector in close proximity to the scintillating fibers or phototubes. To fit the electronics into available space, custom crates, backplanes and cooling methods have had to be developed. During the expected ten-year lifetime, the front-end readout electronics will exist in an environment where radiation levels approach 330 rads and the neutron fluence will be 1.3E11 n/cm sup 2. For this reason, the design approach relies heavily upon custom radiation tolerant ASICs. This paper will present the system architecture of the front-end readout crates and describe their results with early prototypes.

FELIX: the new detector interface for the ATLAS experiment

CERN Document Server

Wu, Weihao; The ATLAS collaboration

2018-01-01

During the next major shutdown (2019-2020), the ATLAS experiment at the LHC at CERN will adopt the Front-End Link eXchange (FELIX) system as the interface between the data acquisition, detector control and TTC (Timing, Trigger and Control) systems and new or updated trigger and detector front-end electronics. FELIX will function as a router between custom serial links from front-end ASICs and FPGAs to data collection and processing components via a commodity switched network. Links may aggregate many slower links or be a single high bandwidth link. FELIX will also forward the LHC bunch-crossing clock, fixed latency trigger accepts and resets received from the TTC system to front-end electronics. The FELIX system uses commodity server technology in combination with FPGA-based PCIe I/O cards. The FELIX servers will run a software routing platform serving data to network clients. Commodity servers connected to FELIX systems via the same network will run the new Software Readout Driver (SW ROD) infrastructure for...

FELIX: the New Detector Interface for the ATLAS Experiment arXiv

CERN Document Server

Wu, Weihao

During the next major shutdown (2019-2020), the ATLAS experiment at the LHC will adopt the Front-End Link eXchange (FELIX) system as the interface between the data acquisition, detector control and TTC (Timing, Trigger and Control) systems and new or updated trigger and detector front-end electronics. FELIX will function as a router between custom serial links from front-end ASICs and FPGAs to data collection and processing components via a commodity switched network. Links may aggregate many slower links or be a single high bandwidth link. FELIX will also forward the LHC bunch-crossing clock, fixed latency trigger accepts and resets received from the TTC system to front-end electronics. The FELIX system uses commodity server technology in combination with FPGA-based PCIe I/O cards. The FELIX servers will run a software routing platform serving data to network clients. Commodity servers connected to FELIX systems via the same network will run the new Software Readout Driver (SW ROD) infrastructure for event f...

FELIX: the New Detector Interface for the ATLAS Experiment

CERN Document Server

Aggarwal, Anamika; The ATLAS collaboration

2018-01-01

During the next major shutdown (2019-2020), the ATLAS experiment at the LHC will adopt the Front-End Link eXchange (FELIX) system as the interface between the data acquisition, detector control and TTC (Timing, Trigger and Control) systems and new or updated trigger and detector front-end electronics. FELIX will function as a router between custom serial links from front-end ASICs and FPGAs to data collection and processing components via a commodity switched network. Links may aggregate many slower links or be a single high bandwidth link. FELIX will also forward the LHC bunch-crossing clock, fixed latency trigger accepts and resets received from the TTC system to front-end electronics. The FELIX system uses commodity server technology in combination with FPGA-based PCIe I/O cards. The FELIX servers will run a software routing platform serving data to network clients. Commodity servers connected to FELIX systems via the same network will run the new Software Readout Driver (SW ROD) infrastructure for event f...

Front end readout electronics for the CMS hadron calorimeter

International Nuclear Information System (INIS)

Terri M. Shaw et al.

2002-01-01

The front-end electronics for the CMS Hadron Calorimeter provides digitized data at the beam interaction rate of 40 MHz. Analog signals provided by hybrid photodiodes (HPDs) or photomultiplier tubes (PMTs) are digitized and the data is sent off board through serialized fiber optic links running at 1600 Mbps. In order to maximize the input signal, the front-end electronics are housed on the detector in close proximity to the scintillating fibers or phototubes. To fit the electronics into available space, custom crates, backplanes and cooling methods have had to be developed. During the expected ten-year lifetime, the front-end readout electronics will exist in an environment where radiation levels approach 330 rads and the neutron fluence will be 1.3E11 n/cm 2 . For this reason, the design approach relies heavily upon custom radiation tolerant ASICs. This paper will present the system architecture of the front-end readout crates and describe their results with early prototypes

Smart Sensor ASIC for Nuclear Power Monitoring

International Nuclear Information System (INIS)

Kerwin, David B.; Merkel, Kenneth G.; Rouxel, Olivier

2013-06-01

Mixed-signal integrated circuits are used in a variety of applications where ionizing radiation is present, including satellites, space vehicles, nuclear reactor monitoring, medical imaging, and cancer therapy. While total ionizing radiation is present in each of these environments, the type of radiation (e.g. heavy ions vs. high-energy x-rays) and other environmental factors present unique challenges to the mixed-signal designer. This paper discusses a Smart Sensor radiation hardened, mixed-signal, application specific integrated circuit (ASIC) specifically designed for sensor monitoring in a nuclear reactor environment. Results after exposure to gamma rays, neutrons, and temperatures up to 200 deg. C are reported. (authors)

Modern design of a fast front-end computer

Science.gov (United States)

Šoštarić, Z.; Anic̈ić, D.; Sekolec, L.; Su, J.

1994-12-01

Front-end computers (FEC) at Paul Scherrer Institut provide access to accelerator CAMAC-based sensors and actuators by way of a local area network. In the scope of the new generation FEC project, a front-end is regarded as a collection of services. The functionality of one such service is described in terms of Yourdon's environment, behaviour, processor and task models. The computational model (software representation of the environment) of the service is defined separately, using the information model of the Shlaer-Mellor method, and Sather OO language. In parallel with the analysis and later with the design, a suite of test programmes was developed to evaluate the feasibility of different computing platforms for the project and a set of rapid prototypes was produced to resolve different implementation issues. The past and future aspects of the project and its driving forces are presented. Justification of the choice of methodology, platform and requirement, is given. We conclude with a description of the present state, priorities and limitations of our project.

A 9-Channel, 100 ps LSB Time-to-Digital Converter for the NA62 Gigatracker Readout ASIC (TDCpix)

International Nuclear Information System (INIS)

Perktold, L; Rinella, G Aglieri; Noy, M; Kluge, A; Kloukinas, K; Kaplon, J; Jarron, P; Morel, M; Fiorini, M; Martin, E

2012-01-01

The TDCpix ASIC is the readout chip for the Gigatracker station of the NA62 experiment. Each station of the Gigatracker needs to provide time stamping of individual particles to 200 ps-rms or better. Bump-bonded to the pixel sensor the ASIC serves an array of 40 columns x 40 pixels. The high precision time measurement of the discriminated hit signals is accomplished with a set of 40 TDCs sitting in the End-Of-Column region of the ASIC. Each TDC provides 9 channels per column. For the time-to-digital converter (TDC) a delay-locked-loop (DLL) approach is employed to achieve a constant time binning of 100 ps. Simulation results show that an average rms time resolution of 33 ps with a power consumption of the TDC better than 33 mW per column is achieved. This contribution will present the design, simulation results and implementation challenges of the TDC.

Measurement of Design Process Front-End – Radical Innovation Approach

DEFF Research Database (Denmark)

Berg, Pekka; Pihlajamaa, Jussi; Hansen, Poul H. Kyvsgård

2014-01-01

The overall structure and the main characteristics of the future product are all decided in the front-end phase, which then strongly affects subsequent new product development activities. Recent studies indicate that these early front-end activities represent the most troublesome phase...... of the innovation process, and at the same time one of the greatest opportunities to improve the overall innovation capability of a company. In this paper dealing with the criteria we concentrate only for the objectives viewpoint and leave the attributes discussion to the future research. Two most crucial questions...... the innovation activities front end contains five assessment viewpoints as follows; input, process, output (including impacts), social environment and structural environment. Based on the results from our first managerial implications in three Finnish manufacturing companies we argue, that the developed model...

Design of a Trigger Data Serializer ASIC for the Upgrade of the ATLAS Forward Muon Spectrometer

Science.gov (United States)

Wang, Jinhong; Guan, Liang; Chapman, J. W.; Zhou, Bing; Zhu, Junjie

2017-12-01

The small-strip Thin Gap Chamber (sTGC) will be used for both triggering and precision tracking purposes in the upgrade of the ATLAS forward muon spectrometer. Both sTGC pad and strip detectors are readout by a Trigger Data Serializer (TDS) ASIC in the trigger path. This ASIC has two operation modes to prepare trigger data from pad and strip detectors respectively. The pad mode (pad-TDS) collects the firing status for up to 104 pads from one detector layer and transmits the data at 4.8 Gbps to the pad trigger extractor every 25 ns. The pad trigger extractor collects pad-TDS data from eight detector layers and defines a region of interest along the path of a muon candidate. In the strip mode (strip-TDS), the deposited charges from up to 128 strips are buffered, time-stamped, and a trigger matching procedure is performed to read out strips underneath the region of interest. The strip-TDS output is also transmitted at 4.8 Gbps to the following FPGA processing circuits. Details about the ASIC design and test results are presented in this paper.

A low-power front-end amplifier for the microstrip sensors of the PANDA microvertex detector

Energy Technology Data Exchange (ETDEWEB)

Di Pietro, Valentino; Brinkmann, Kai-Thomas; Riccardi, Alberto [II. Physikalisches Institut, JLU Giessen, Giessen (Germany); Rivetti, Angelo; Rolo, Manuel; Garbolino, Sara [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

2014-07-01

The most common readout systems designed for nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made of two main building blocks: front-end amplifier and ADC. An issue in the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the use of time-based architectures that offer better performances. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work presents the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The architecture of the front-end amplifier is presented, and simulations in a 110 nm CMOS technology are discussed.

Exploring Many-Core Design Templates for FPGAs and ASICs

Directory of Open Access Journals (Sweden)

Ilia Lebedev

2012-01-01

Full Text Available We present a highly productive approach to hardware design based on a many-core microarchitectural template used to implement compute-bound applications expressed in a high-level data-parallel language such as OpenCL. The template is customized on a per-application basis via a range of high-level parameters such as the interconnect topology or processing element architecture. The key benefits of this approach are that it (i allows programmers to express parallelism through an API defined in a high-level programming language, (ii supports coarse-grained multithreading and fine-grained threading while permitting bit-level resource control, and (iii reduces the effort required to repurpose the system for different algorithms or different applications. We compare template-driven design to both full-custom and programmable approaches by studying implementations of a compute-bound data-parallel Bayesian graph inference algorithm across several candidate platforms. Specifically, we examine a range of template-based implementations on both FPGA and ASIC platforms and compare each against full custom designs. Throughout this study, we use a general-purpose graphics processing unit (GPGPU implementation as a performance and area baseline. We show that our approach, similar in productivity to programmable approaches such as GPGPU applications, yields implementations with performance approaching that of full-custom designs on both FPGA and ASIC platforms.

Front-end DAQ strategy and implementation for the KLOE-2 experiment

Science.gov (United States)

Branchini, P.; Budano, A.; Balla, A.; Beretta, M.; Ciambrone, P.; De Lucia, E.; D'Uffizi, A.; Marciniewski, P.

2013-04-01

A new front-end data acquisition (DAQ) system has been conceived for the data collection of the new detectors which will be installed by the KLOE2 collaboration. This system consists of a general purpose FPGA based DAQ module and a VME board hosting up to 16 optical links. The DAQ module has been built around a Virtex-4 FPGA and it is able to acquire up to 1024 different channels distributed over 16 front-end slave cards. Each module is a general interface board (GIB) which performs also first level data concentration tasks. The GIB has an optical interface, a RS-232, an USB and a Gigabit Ethernet Interface. The optical interface will be used for DAQ purposes while the Gigabit Ethernet interface for monitoring tasks and debug. Two new detectors exploit this strategy to collect data. Optical links are used to deliver data to the VME board which performs data concentration tasks. The return optical link from the board to the GIB is used to initialize the front-end cards. The VME interface of the module implements the VME 2eSST protocol in order to sustain a peak data rate of up to 320 MB/s. At the moment the system is working at the Frascati National Laboratory (LNF).

Front-end DAQ strategy and implementation for the KLOE-2 experiment

International Nuclear Information System (INIS)

Branchini, P; Budano, A; Balla, A; Beretta, M; Ciambrone, P; Lucia, E De; D'Uffizi, A; Marciniewski, P

2013-01-01

A new front-end data acquisition (DAQ) system has been conceived for the data collection of the new detectors which will be installed by the KLOE2 collaboration. This system consists of a general purpose FPGA based DAQ module and a VME board hosting up to 16 optical links. The DAQ module has been built around a Virtex-4 FPGA and it is able to acquire up to 1024 different channels distributed over 16 front-end slave cards. Each module is a general interface board (GIB) which performs also first level data concentration tasks. The GIB has an optical interface, a RS-232, an USB and a Gigabit Ethernet Interface. The optical interface will be used for DAQ purposes while the Gigabit Ethernet interface for monitoring tasks and debug. Two new detectors exploit this strategy to collect data. Optical links are used to deliver data to the VME board which performs data concentration tasks. The return optical link from the board to the GIB is used to initialize the front-end cards. The VME interface of the module implements the VME 2eSST protocol in order to sustain a peak data rate of up to 320 MB/s. At the moment the system is working at the Frascati National Laboratory (LNF).

BPM ANALOG FRONT-END ELECTRONICS BASED ON THE AD8307 LOG AMPLIFIER

International Nuclear Information System (INIS)

R. SHURTER; ET AL

2000-01-01

Beam position monitor (BPM) signal-processing electronics utilizing the Analog Devices AD8307 logarithmic amplifier has been developed for the Low Energy Demonstration Accelerator (LEDA), part of the Accelerator Production of Tritium (APT) project at Los Alamos. The low-pass filtered 350 MHz fundamental signal from each of the four microstrip electrodes in a BPM is ''detected'' by an AD8307 log amp, amplified and scaled to accommodate the 0 to +5V input of an analog-to-digital (A/D) converter. The resultant four digitized signals represent a linear power relationship to the electrode signals, which are in turn related to beam current and position. As the AD8307 has a potential dynamic range of approximately 92 dB, much attention must be given to noise reduction, sources of which can be digital signals on the same board, power supplies, inter-channel coupling, stray RF and others. This paper will describe the operational experience of this particular analog front-end electronic circuit design

A CMOS frontend chip for implantable neural recording with wide voltage supply range

Science.gov (United States)

Jialin, Liu; Xu, Zhang; Xiaohui, Hu; Yatao, Guo; Peng, Li; Ming, Liu; Bin, Li; Hongda, Chen

2015-10-01

A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC). The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits (ENOB) of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 (including pads). In-vitro recording was successfully carried out by the proposed frontend chip. Project supported by the National Natural Science Foundation of China (Nos. 61474107, 61372060, 61335010, 61275200, 61178051) and the Key Program of the Chinese Academy of Sciences (No. KJZD-EW-L11-01).

InP DHBT MMICs for millimeter-wave front-ends

DEFF Research Database (Denmark)

Johansen, Tom Keinicke; Hadziabdic, Dzenan; Krozer, Viktor

2009-01-01

In this paper, we show advanced MMIC's using InP DHBT technology. In particular, we demonstrate front-end circuits covering a broad frequency range from Q-band to E-band. Realizations of power amplifiers, quadrature VCOs, and sub-harmonic mixers, are presented and experimental results are discussed....

A custom readout electronics for the BESIII CGEM detector

International Nuclear Information System (INIS)

Rolo, M. Da Rocha; Alexeev, M.; Amoroso, A.; Bianchi, F.; Cossio, F.; Mori, F. De; Destefanis, M.; Ferroli, R. Baldini; Chai, J.Y.; Bertani, M.; Calcaterra, A.; Capodiferro, M.; Cerioni, S.; Bettoni, D.; Canale, N.; Carassiti, V.; Chiozzi, S.; Cibinetto, G.; Ramusino, A. Cotta; Bugalho, R.

2017-01-01

For the upgrade of the inner tracker of the BESIII spectrometer, planned for 2018, a lightweight tracker based on an innovative Cylindrical Gas Electron Multiplier (CGEM) detector is now under development. The analogue readout of the CGEM enables the use of a charge centroid algorithm to improve the spatial resolution to better than 130 μm while loosening the pitch strip to 650 μm, which allows to reduce the total number of channels to about 10 000. The channels are readout by 160 dedicated integrated 64-channel front-end ASICs, providing a time and charge measurement and featuring a fully-digital output. The energy measurement is extracted either from the time-over-threshold (ToT) or the 10-bit digitisation of the peak amplitude of the signal. The time of the event is generated by quad-buffered low-power TDCs, allowing for rates in excess of 60 kHz per channel. The TDCs are based on analogue interpolation techniques and produce a time stamp (or two, if working in ToT mode) of the event with a time resolution better than 50 ps. The front-end noise, based on a CSA and a two-stage complex conjugated pole shapers, dominate the channel intrinsic time jitter, which is less than 5 ns r.m.s. The time information of the hit can be used to reconstruct the track path, operating the detector as a small TPC and hence improving the position resolution when the distribution of the cloud, due to large incident angle or magnetic field, is very broad. Event data is collected by an off-detector motherboard, where each GEM-ROC readout card handles 4 ASIC carrier FEBs (512 channels). Configuration upload and data readout between the off-detector electronics and the VME-based data collector cards are managed by bi-directional fibre optical links. This paper covers the design of a custom front-end electronics for the readout of the new inner tracker of the BESIII experiment, addressing the relevant design aspects of the detector electronics and the front-end ASIC for the CGEM

A custom readout electronics for the BESIII CGEM detector

Science.gov (United States)

Da Rocha Rolo, M.; Alexeev, M.; Amoroso, A.; Baldini Ferroli, R.; Bertani, M.; Bettoni, D.; Bianchi, F.; Bugalho, R.; Calcaterra, A.; Canale, N.; Capodiferro, M.; Carassiti, V.; Cerioni, S.; Chai, J. Y.; Chiozzi, S.; Cibinetto, G.; Cossio, F.; Cotta Ramusino, A.; De Mori, F.; Destefanis, M.; Di Francesco, A.; Dong, J.; Evangelisti, F.; Farinelli, R.; Fava, L.; Felici, G.; Fioravanti, E.; Garzia, I.; Gatta, M.; Greco, M.; Lavezzi, L.; Leng, C. Y.; Li, H.; Maggiora, M.; Malaguti, R.; Marcello, S.; Marciniewski, P.; Melchiorri, M.; Mezzadri, G.; Mignone, M.; Morello, G.; Pacetti, S.; Patteri, P.; Pellegrino, J.; Pelosi, A.; Rivetti, A.; Savrié, M.; Scodeggio, M.; Soldani, E.; Sosio, S.; Spataro, S.; Tskhadadze, E.; Varela, J.; Verma, S.; Wheadon, R.; Yan, L.

2017-07-01

For the upgrade of the inner tracker of the BESIII spectrometer, planned for 2018, a lightweight tracker based on an innovative Cylindrical Gas Electron Multiplier (CGEM) detector is now under development. The analogue readout of the CGEM enables the use of a charge centroid algorithm to improve the spatial resolution to better than 130 μm while loosening the pitch strip to 650 μm, which allows to reduce the total number of channels to about 10 000. The channels are readout by 160 dedicated integrated 64-channel front-end ASICs, providing a time and charge measurement and featuring a fully-digital output. The energy measurement is extracted either from the time-over-threshold (ToT) or the 10-bit digitisation of the peak amplitude of the signal. The time of the event is generated by quad-buffered low-power TDCs, allowing for rates in excess of 60 kHz per channel. The TDCs are based on analogue interpolation techniques and produce a time stamp (or two, if working in ToT mode) of the event with a time resolution better than 50 ps. The front-end noise, based on a CSA and a two-stage complex conjugated pole shapers, dominate the channel intrinsic time jitter, which is less than 5 ns r.m.s. The time information of the hit can be used to reconstruct the track path, operating the detector as a small TPC and hence improving the position resolution when the distribution of the cloud, due to large incident angle or magnetic field, is very broad. Event data is collected by an off-detector motherboard, where each GEM-ROC readout card handles 4 ASIC carrier FEBs (512 channels). Configuration upload and data readout between the off-detector electronics and the VME-based data collector cards are managed by bi-directional fibre optical links. This paper covers the design of a custom front-end electronics for the readout of the new inner tracker of the BESIII experiment, addressing the relevant design aspects of the detector electronics and the front-end ASIC for the CGEM readout

Novel Front-end Electronics for Time Projection Chamber Detectors

CERN Document Server

García García, Eduardo José

This work has been carried out in the European Organization for Nuclear Research (CERN) and it was supported by the European Union as part of the research and development towards the European detector the (EUDET) project, specifically for the International Linear Collider (ILC). In particle physics there are several different categories of particle detectors. The presented design is focused on a particular kind of tracking detector called Time Projection Chamber (TPC). The TPC provides a three dimensional image of electrically charged particles crossing a gaseous volume. The thesis includes a study of the requirements for future TPC detectors summarizing the parameters that the front-end readout electronics must fulfill. In addition, these requirements are compared with respect to the readouts used in existing TPC detectors. It is concluded that none of the existing front-end readout designs fulfill the stringent requirements. The main requirements for future TPC detectors are high integration, an increased n...

Trends in the design of front-end systems for room temperature solid state detectors

International Nuclear Information System (INIS)

Manfredi, Pier F.; Re, Valerio

2003-01-01

The paper discusses the present trends in the design of low-noise front-end systems for room temperature semiconductor detectors. The technological advancement provided by submicron CMOS and BiCMOS processes is examined from several points of view. The noise performances are a fundamental issue in most detector applications and suitable attention is devoted to them for the purpose of judging whether or not the present processes supersede the solutions featuring a field-effect transistor as a front-end element. However, other considerations are also important in judging how well a monolithic technology suits the front-end design. Among them, the way a technology lends itself to the realization of additional functions, for instance, the charge reset in a charge-sensitive loop or the time-variant filters featuring the special weighting functions that may be requested in some applications of CdTe or CZT detectors

VME as a front-end electronics system in high energy physics experiments

International Nuclear Information System (INIS)

Ohska, T.K.

1990-01-01

It is only a few years since the VME became a standard system, yet the VME system is already so much more popular than other systems. The VME system was developed for industrial applications and not for the scientific research, and high energy physics field is a tiny market when compared with the industrial market. Considerations made here indicate that the VME system would be a good one for a rear-end system, but would not be a good candidate for front-end electronics in physics experiments. Furthermore, there is a fear that the VXI bus could become popular in this field of instrumentation since the VXI system is backed up by major suppliers of instrumentation in the high energy physics field. VXI would not be an adequate system for front-end electronics, yet advertised to be one. It would be worse to see the VXI system to become a standard system for high energy physics instrumentation than the VME system to be one. The VXI system would do a mediocre job so that people might be misled to think that the VXI system can be used as front-end system. (N.K.)

Frequency-Tunable antenna by input-impedance-tunable CMOS RF-Frontend

NARCIS (Netherlands)

Haider, Nadia; Oude Alink, M.S.; Caratelli, Diego; Klumperink, Eric A.M.; Yarovoy, Alexander G.

2013-01-01

Variable-impedance matching between the antenna and the RF-frontend provides several potential advantages, including changing operational frequency, compensating for unintentional mismatch, improving scanning capability, and reducing noise and interference signal levels. In this article a concept of

READ - Remote Analog ASIC Design System

Directory of Open Access Journals (Sweden)

Michael E. Auer

2006-11-01

Full Text Available The scope of this work is to present a solution to implement a remote electronic laboratory for testing and designing analog ASICs (ispPAC10. The application allows users to create circuit schematics, upload the design to the device and perform measurements. The software used for designing circuits is the PAC-Designer and it runs on a Citrix server. The signals are generated and the responses are acquired by a data acquisition board controlled by LabView. The virtual instruments interact with some ActiveX controls specially designed to look like real oscilloscope and function generator devices and represent the user interface of the lab. These ActiveX give users the control over the LabView VIs and the access to its facilities in order to perform electronic exercises.

An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit.

Science.gov (United States)

Tao Tang; Wang Ling Goh; Lei Yao; Jia Hao Cheong; Yuan Gao

2017-07-01

This paper describes an integrated multichannel neural recording analog front end (AFE) with a novel area-efficient driven right leg (DRL) circuit to improve the system common mode rejection ratio (CMRR). The proposed AFE consists of an AC-coupled low-noise programmable-gain amplifier, an area-efficient DRL block and a 10-bit SAR ADC. Compared to conventional DRL circuit, the proposed capacitor-less DRL design achieves 90% chip area reduction with enhanced CMRR performance, making it ideal for multichannel biomedical recording applications. The AFE circuit has been designed in a standard 0.18-μm CMOS process. Post-layout simulation results show that the AFE provides two gain settings of 54dB/60dB while consuming 1 μA per channel under a supply voltage of 1 V. The input-referred noise of the AFE integrated from 1 Hz to 10k Hz is only 4 μVrms and the CMRR is 110 dB.

Design of a deterministic link initialization mechanism for serial LVDS interconnects

International Nuclear Information System (INIS)

Schatral, S; Lemke, F; Bruening, U

2014-01-01

The Compressed Baryonic Matter experiment at FAIR in Darmstadt has special requirements for the Data Acquisition Network. One of them is deterministic latency for all the links from the back-end to the front-end, which enables synchronization in the whole read-out tree. Since the front-end electronics (FEE) contain mixed-signal circuits for processing the raw detector data, special ASICs were developed. DDR LVDS links are used to interconnect the FEEs and readout controllers. An adapted link initialization mechanism ensures determinism for them by balancing cable lengths, adjusting for phase differences, and handling environmental behavior. After re-initialization, timing must be accurate to the bit-clock level

Wide Temperature Rad-Hard ASIC for Process Control of a Fuel Cell System, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — Ridgetop Group developed a top-level design of a rad-hard application-specific integrated circuit (ASIC) for spacecraft power management that is functional over a...

Synthesis algorithm of VLSI multipliers for ASIC

Science.gov (United States)

Chua, O. H.; Eldin, A. G.

1993-01-01

Multipliers are critical sub-blocks in ASIC design, especially for digital signal processing and communications applications. A flexible multiplier synthesis tool is developed which is capable of generating multiplier blocks for word size in the range of 4 to 256 bits. A comparison of existing multiplier algorithms is made in terms of speed, silicon area, and suitability for automated synthesis and verification of its VLSI implementation. The algorithm divides the range of supported word sizes into sub-ranges and provides each sub-range with a specific multiplier architecture for optimal speed and area. The algorithm of the synthesis tool and the multiplier architectures are presented. Circuit implementation and the automated synthesis methodology are discussed.

ILC Instrumentation R and D at SCIPP

International Nuclear Information System (INIS)

Carman, J.; Crosby, S.; Fadeyev, V.; Schumm, B.A.; Spencer, N.; Wilder, M.; Partridge, R.

2011-01-01

The Santa Cruz Institute for Particle Physics (SCIPP) continues to be engaged in research and development towards an ILC detector. The latest efforts at SCIPP are described, including those associated with the LSTFE front-end readout ASIC, the use of charge division to obtain a longitudinal coordinate from silicon strip detectors, and the contribution of strip resistance to readout noise.

Hydrogenated amorphous silicon sensors based on thin film on ASIC technology

CERN Document Server

Despeisse, M; Anelli, G; Jarron, P; Kaplon, J; Rusack, R; Saramad, S; Wyrsch, N

2006-01-01

The performance and limitations of a novel detector technology based on the deposition of a thin-film sensor on top of processed integrated circuits have been studied. Hydrogenated amorphous silicon (a-Si:H) films have been deposited on top of CMOS circuits developed for these studies and the resulting "thin-film on ASIC" (TFA) detectors are presented. The leakage current of the a-Si:H sensor at high reverse biases turns out to be an important parameter limiting the performance of a TFA detector. Its detailed study and the pixel segmentation of the detector are presented. High internal electric fields (in the order of 10/sup 4/-10/sup 5/ V/cm) can be built in the a-Si:H sensor and overcome the low mobility of electrons and holes in a-Si:H. Signal induction by generated carrier motion and speed in the a-Si:H sensor have been studied with a 660 nm pulsed laser on a TFA detector based on an ASIC integrating 5 ns peaking time pre- amplifiers. The measurement set-up also permits to study the depletion of the senso...

CBC3: a CMS microstrip readout ASIC with logic for track-trigger modules at HL-LHC

CERN Document Server

Prydderch, Mark Lyndon; Bell, Stephen Jean-marc; Key-Charriere, M; Jones, Lawrence; Auzinger, Georg; Borg, Johan; Hall, Geoffrey; Pesaresi, Mark Franco; Raymond, David Mark; Uchida, Kirika; Goldstein, Joel; Seif El Nasr, Sarah

2018-01-01

The CBC3 is the latest version of the CMS Binary Chip ASIC for readout of the outer radial region of the upgraded CMS Tracker at HL-LHC. This 254-channel, 130nm CMOS ASIC is designed to be bump-bonded to a substrate to which sensors will be wire-bonded. It will instrument double-layer 2S-modules, consisting of two overlaid silicon microstrip sensors with aligned microstrips. On-chip logic identifies first level trigger primitives from high transverse-momentum tracks by selecting correlated hits in the two sensors. Delivered in late 2016, the CBC3 has been under test for several months, including X-ray irradiations and SEU testing. Results and performance are reported.

BGO front-end electronics and signal processing in the MXGS instrument for the ASIM mission

DEFF Research Database (Denmark)

Skogseide, Yngve; Cenkeramaddi, Linga Reddy; Genov, Georgi

2012-01-01

This paper presents the Bismuth Germanate Oxide (BGO) front-end electronics design and signal processing in Modular X- and Gamma ray sensor (MXGS) instrument onboard the Atmosphere Space Interaction Monitor (ASIM) mission, funded by the European Space Agency. University of Bergen is responsible...... for the design and development of the detector layers and readout electronics for the MXGS instrument. The principal objective of the instrument is to detect Terrestrial Gamma ray Flashes (TGFs), which are related to thunderstorm activity. The digital pulse processing scheme used in the MXGS BGO detector gives...... it a significantly higher rate capability than what has been achieved in other instruments used in the study of terrestrial gamma flashes. The front-end electronics for the BGO detector layer in MXGS system also uses fewer components compared to conventional analog front-ends for BGO detectors, thereby increasing...

Front-end electronics development for the SSC

International Nuclear Information System (INIS)

Levi, M.

1990-12-01

This is a status report on electronics development undertaken by the Front-End Electronics Collaboration. The overall goal of the collaboration remains the development by 1992 of complete, architecturally compatible, front end electronic systems for calorimeter, wire drift chamber, and silicon strip readout. We report here a few highlights to give a brief overview of the work underway. Performance requirements and capabilities, selected architectures, circuit designs and test results are presented. 13 refs., 21 figs., 1 tab

Progress with the SNS front-end systems

International Nuclear Information System (INIS)

Keller, R.; Abraham, W.; Ayers, J.J.; Cheng, D.W.; Cull, P.; DiGennaro, R.; Doolittle, L.; Gough, R.A.; Greer, J.B.; Hoff, M.D.; Leung, K.N.; Lewis, S.; Lionberger, C.; MacGill, R.; Minamihara, Y.; Monroy, M.; Oshatz, D.; Pruyn, J.; Ratti, A.; Reijonen, J.; Schenkel, T.; Staples, J.W.; Syversrud, D.; Thomae, R.; Virostek, S.; Yourd, R.

2001-01-01

The Front-End Systems (FES) of the Spallation Neutron Source (SNS) project have been described in detail elsewhere [1]. They comprise an rf-driven H - ion source, electrostatic LEBT, four-vane RFQ, and an elaborate MEBT. These systems are planned to be delivered to the SNS facility in Oak Ridge in June 2002. This paper discusses the latest design features, the status of development work, component fabrication and procurements, and experimental results with the first commissioned beamline elements

Involvement of Opioid System, TRPM8, and ASIC Receptors in Antinociceptive Effect of Arrabidaea brachypoda (DC) Bureau.

Science.gov (United States)

Rodrigues, Vinícius Peixoto; Rocha, Cláudia Quintino da; Périco, Larissa Lucena; Santos, Raquel de Cássia Dos; Ohara, Rie; Nishijima, Catarine Massucato; Ferreira Queiroz, Emerson; Wolfender, Jean-Luc; Rocha, Lúcia Regina Machado da; Santos, Adair Roberto Soares; Vilegas, Wagner; Hiruma-Lima, Clélia Akiko

2017-11-02

Arrabidaea brachypoda (DC) Bureau is a medicinal plant found in Brazil. Known as "cipó-una", it is popularly used as a natural therapeutic agent against pain and inflammation. This study evaluated the chemical composition and antinociceptive activity of the dichloromethane fraction from the roots of A. brachypoda (DEAB) and its mechanism of action. The chemical composition was characterized by high-performance liquid chromatography, and this fraction is composed only of dimeric flavonoids. The antinociceptive effect was evaluated in formalin and hot plate tests after oral administration (10-100 mg/kg) in male Swiss mice. We also investigated the involvement of TRPV1 (transient receptor potential vanilloid 1), TRPA1 (transient receptor potential ankyrin 1), TRPM8 (transient receptor potential melastatin 8), and ASIC (acid-sensing ion channel), as well as the opioidergic, glutamatergic, and supraspinal pathways. Moreover, the nociceptive response was reduced (30 mg/kg) in the early and late phase of the formalin test. DEAB activity appears to involve the opioid system, TRPM8, and ASIC receptors, clearly showing that the DEAB alleviates acute pain in mice and suggesting the involvement of the TRPM8 and ASIC receptors and the opioid system in acute pain relief.

Receiver Front-End Circuits for Future Generations of Wireless Communications

NARCIS (Netherlands)

Sanduleanu, M.A.T.; Vidojkovic - Andjelovic, M.; Vidojkovic, V.; Roermund, van A.H.M.; Tasic, A.

2007-01-01

In this paper, new receiver concepts and CMOS circuits for future wireless communications standards are introduced. Tradeoffs between technology, performance and circuit choices of the RF front-end circuits are discussed. In particular, power consumption, noise figure and linearity trade-offs in

Robust Multivariable Optimization and Performance Simulation for ASIC Design

Science.gov (United States)

DuMonthier, Jeffrey; Suarez, George

2013-01-01

Application-specific-integrated-circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power, and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem, which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques, which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable, are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way that facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as a framework of software modules, templates, and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation.

Development of front-end electronics and TDC LSI for the ATLAS MDT

CERN Document Server

Arai, Y

2000-01-01

Architecture of the front-end electronics for the ATLAS muon precision chamber (MDT) is presented. Especially, test results of a prototype TDC chip are described in detail. The chip was fabricated in a 0.3 mu m CMOS gate-array technology. Measurements of critical elements of the chip such as the PLL, and data buffering circuits demonstrated adequate performance. The effect of gamma-ray irradiation, using a /sup 60/Co source, and neutron irradiation, were also examined. The test results revealed radiation tolerance adequate for the operation of the circuits in the environment of the ATLAS MDT. Mounting of the front-end electronics to the MDT is scheduled to start in the year 2001. (10 refs).

Development and Demonstration of a Magnesium-Intensive Vehicle Front-End Substructure

Energy Technology Data Exchange (ETDEWEB)

Logan, Stephen D. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Forsmark, Joy H. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Osborne, Richard [United States Automotive Materials Partnership LLC, Southfield, MI (United States)

2016-07-01

This project is the final phase (designated Phase III) of an extensive, nine-year effort with the objectives of developing a knowledge base and enabling technologies for the design, fabrication and performance evaluation of magnesium-intensive automotive front-end substructures intended to partially or completely replace all-steel comparators, providing a weight savings approaching 50% of the baseline. Benefits of extensive vehicle weight reduction in terms of fuel economy increase, extended vehicle range, vehicle performance and commensurate reductions in greenhouse gas emissions are well known. An exemplary vehicle substructure considered by the project is illustrated in Figure 1, along with the exterior vehicle appearance. This unibody front-end “substructure” is one physical objective of the ultimate design and engineering aspects established at the outset of the larger collective effort.

Front-end Electronics for Unattended Measurement (FEUM). Prototype Test Plan

Energy Technology Data Exchange (ETDEWEB)

Conrad, Ryan C.; Morris, Scott J.; Smith, Leon E.; Keller, Daniel T.

2015-09-16

The IAEA has requested that PNNL perform an initial set of tests on front-end electronics for unattended measurement (FEUM) prototypes. The FEUM prototype test plan details the tests to be performed, the criteria for evaluation, and the procedures used to execute the tests.

Measurements of the performance of a beam condition monitor prototype in a 5 GeV electron beam

Energy Technology Data Exchange (ETDEWEB)

Hempel, M., E-mail: maria.hempel@desy.de [Brandenburg University of Technology Cottbus-Senftenberg, Cottbus 03013 (Germany); DESY, Zeuthen 15738 (Germany); Afanaciev, K. [NCPHEP, Minsk 220040 (Belarus); Burtowy, P.; Dabrowski, A. [CERN, Geneva 1211 (Switzerland); Henschel, H. [DESY, Zeuthen 15738 (Germany); Idzik, M. [AGH University of Science and Technology, Cracow 30-059 (Poland); Karacheban, O. [Brandenburg University of Technology Cottbus-Senftenberg, Cottbus 03013 (Germany); Lange, W.; Leonard, J. [DESY, Zeuthen 15738 (Germany); Levy, I. [Tel Aviv University, Tel Aviv 6997801 (Israel); Lohmann, W. [Brandenburg University of Technology Cottbus-Senftenberg, Cottbus 03013 (Germany); DESY, Zeuthen 15738 (Germany); Pollak, B. [Northwestern University, Evanston, IL 60208 (United States); Przyborowski, D. [AGH University of Science and Technology, Cracow 30-059 (Poland); Ryjov, V. [CERN, Geneva 1211 (Switzerland); Schuwalow, S. [DESY, Zeuthen 15738 (Germany); Stickland, D. [Princeton University, Princeton, NJ 08544 (United States); Walsh, R. [DESY, Zeuthen 15738 (Germany); Zagozdzinska, A. [CERN, Geneva 1211 (Switzerland)

2016-08-01

The Fast Beam Conditions Monitor, BCM1F, in the Compact Muon Solenoid, CMS, experiment was operated since 2008 and delivered invaluable information on the machine induced background in the inner part of the CMS detector supporting a safe operation of the inner tracker and high quality data. Due to the shortening of the time between two bunch crossings from 50 ns to 25 ns and higher expected luminosity at the Large Hadron Collider, LHC, in 2015, BCM1F needed an upgrade to higher bandwidth. In addition, BCM1F is used as an on-line luminometer operated independently of CMS. To match these requirements, the number of single crystal diamond sensors was enhanced from 8 to 24. Each sensor is subdivided into two pads, leading to 48 readout channels. Dedicated fast front-end ASICs were developed in 130 nm technology, and the back-end electronics is completely upgraded. An assembled prototype BCM1F detector comprising sensors, a fast front-end ASIC and optical analog readout was studied in a 5 GeV electron beam at the DESY-II accelerator. Results on the performance are given.

Construction and beam-tests of silicon-tungsten prototype modules for the CMS High Granularity Calorimeter for HL-LHC

Science.gov (United States)

Quast, Thorben

2018-02-01

As part of its HL-LHC upgrade program, CMS is developing a High Granularity Calorimeter (HGCAL) to replace the existing endcap calorimeters. The HGCAL will be realised as a sampling calorimeter, including an electromagnetic compartment comprising 28 layers of silicon pad detectors with pad areas of 0.5-1.0 cm2 interspersed with absorbers. Prototype modules, based on 6-inch hexagonal silicon pad sensors with 128 channels, have been constructed and include many of the features required for this challenging detector. In 2016, beam tests of sampling configurations made from these modules have been conducted both at FNAL and at CERN using the Skiroc2 front-end ASIC (designed by the CALICE collaboration for ILC). In 2017, the setup has been extended with CALICE's AHCAL prototype, a scinitillator based sampling calorimeter, and it was further tested in dedicated beam tests at CERN. There, the new Skiroc2-CMS front-end ASIC was used for the first time. We highlight final results from our studies in 2016, including position resolution as well as precision timing-measurements. Furthermore, the extended setup in 2017 is discussed and first results from beam tests with electrons and pions are shown.

A reconfigurable medically cohesive biomedical front-end with ΣΔ ADC in 0.18µm CMOS.

Science.gov (United States)

Jha, Pankaj; Patra, Pravanjan; Naik, Jairaj; Acharya, Amit; Rajalakshmi, P; Singh, Shiv Govind; Dutta, Ashudeb

2015-08-01

This paper presents a generic programmable analog front-end (AFE) for acquisition and digitization of various biopotential signals. This includes a lead-off detection circuit, an ultra-low current capacitively coupled signal conditioning stage with programmable gain and bandwidth, a new mixed signal automatic gain control (AGC) mechanism and a medically cohesive reconfigurable ΣΔ ADC. The full system is designed in UMC 0.18μm CMOS. The AFE achieves an overall linearity of more 10 bits with 0.47μW power consumption. The ADC provides 2(nd) order noise-shaping while using single integrator and an ENOB of ~11 bits with 5μW power consumption. The system was successfully verified for various ECG signals from PTB database. This system is intended for portable batteryless u-Healthcare devices.

45 Gb/s low complexity optical front-end for soft-decision LDPC decoders.

Science.gov (United States)

Sakib, Meer Nazmus; Moayedi, Monireh; Gross, Warren J; Liboiron-Ladouceur, Odile

2012-07-30

In this paper a low complexity and energy efficient 45 Gb/s soft-decision optical front-end to be used with soft-decision low-density parity-check (LDPC) decoders is demonstrated. The results show that the optical front-end exhibits a net coding gain of 7.06 and 9.62 dB for post forward error correction bit error rate of 10(-7) and 10(-12) for long block length LDPC(32768,26803) code. The performance over a hard decision front-end is 1.9 dB for this code. It is shown that the soft-decision circuit can also be used as a 2-bit flash type analog-to-digital converter (ADC), in conjunction with equalization schemes. At bit rate of 15 Gb/s using RS(255,239), LDPC(672,336), (672, 504), (672, 588), and (1440, 1344) used with a 6-tap finite impulse response (FIR) equalizer will result in optical power savings of 3, 5, 7, 9.5 and 10.5 dB, respectively. The 2-bit flash ADC consumes only 2.71 W at 32 GSamples/s. At 45 GSamples/s the power consumption is estimated to be 4.95 W.

Development of slew-rate-limited time-over-threshold (ToT) ASIC for a multi-channel silicon-based ion detector

Science.gov (United States)

Uenomachi, M.; Orita, T.; Shimazoe, K.; Takahashi, H.; Ikeda, H.; Tsujita, K.; Sekiba, D.

2018-01-01

High-resolution Elastic Recoil Detection Analysis (HERDA), which consists of a 90o sector magnetic spectrometer and a position-sensitive detector (PSD), is a method of quantitative hydrogen analysis. In order to increase sensitivity, a HERDA system using a multi-channel silicon-based ion detector has been developed. Here, as a parallel and fast readout circuit from a multi-channel silicon-based ion detector, a slew-rate-limited time-over-threshold (ToT) application-specific integrated circuit (ASIC) was designed, and a new slew-rate-limited ToT method is proposed. The designed ASIC has 48 channels and each channel consists of a preamplifier, a slew-rate-limited shaping amplifier, which makes ToT response linear, and a comparator. The measured equivalent noise charges (ENCs) of the preamplifier, the shaper, and the ToT on no detector capacitance were 253±21, 343±46, and 560±56 electrons RMS, respectively. The spectra from a 241Am source measured using a slew-rate-limited ToT ASIC are also reported.

An X-Ray facility to perform irradiation tests and TID studies on electronics and detectors

CERN Document Server

Brundu, Davide; Cadeddu, Sandro; Wyllie, Ken; Ciambrone, Paolo

2018-01-01

The X-Ray irradiation system of the LHCb group, installed in Cagliari, is presented; with a particular focus on the setup configuration and dose rate calibration. The system can be used to perform Total Ionizing Dose (TID) studies for detectors, readout and front-end electronics. It was already used to test the nSYNC chip, an ASIC for the readout of the LHCb upgraded muon system.

17β-Estradiol Enhances ASIC Activity in Primary Sensory Neurons to Produce Sex Difference in Acidosis-Induced Nociception.

Science.gov (United States)

Qu, Zu-Wei; Liu, Ting-Ting; Ren, Cuixia; Gan, Xiong; Qiu, Chun-Yu; Ren, Ping; Rao, Zhiguo; Hu, Wang-Ping

2015-12-01

Sex differences have been reported in a number of pain conditions. Women are more sensitive to most types of painful stimuli than men, and estrogen plays a key role in the sex differences in pain perception. However, it is unclear whether there is a sex difference in acidosis-evoked pain. We report here that both male and female rats exhibit nociceptive behaviors in response to acetic acid, with females being more sensitive than males. Local application of exogenous 17β-estradiol (E2) exacerbated acidosis-evoked nociceptive response in male rats. E2 and estrogen receptor (ER)-α agonist 1,3,5-Tris(4-hydroxyphenyl)-4-propyl-1H-pyrazole, but not ERβ agonist 2,3-bis(4-hydroxyphenyl)-propionitrile, replacement also reversed attenuation of the acetic acid-induced nociceptive response in ovariectomized females. Moreover, E2 can exert a rapid potentiating effect on the functional activity of acid-sensing ion channels (ASICs), which mediated the acidosis-induced events. E2 dose dependently increased the amplitude of ASIC currents with a 42.8 ± 1.6 nM of EC50. E2 shifted the concentration-response curve for proton upward with a 50.1% ± 6.2% increase of the maximal current response to proton. E2 potentiated ASIC currents via an ERα and ERK1/2 signaling pathway. E2 also altered acidosis-evoked membrane excitability of dorsal root ganglia neurons and caused a significant increase in the amplitude of the depolarization and the number of spikes induced by acidic stimuli. E2 potentiation of the functional activity of ASICs revealed a peripheral mechanism underlying this sex difference in acetic acid-induced nociception.

Increased Asics Expression via the Camkii-CREB Pathway in a Novel Mouse Model of Trigeminal Pain