WorldWideScience

Sample records for frontend asic coupled

  1. FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

    2007-10-27

    We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

  2. A front-end ASIC design for non-uniformity correction

    Science.gov (United States)

    Shen, X.; Ding, R. J.; Lin, J. M.; Liu, F.

    2008-12-01

    A front-end design of an ASIC that implements calibration and correction for IRFPA non-uniformity is presented. An algorithm suitable for ASIC implementation is introduced, and one kind of architecture that implements this algorithm has been designed. We map the architecture to TSMC 0.25um process. After evaluating the chip area and operation speed, we confirm that this architect will also be effective when the FPA scale in enlarged to 1Kby1K. Finally the flow of circuit implementation and method of verification are introduced briefly.

  3. Front-end ASIC for pixilated wide bandgap detectors

    Science.gov (United States)

    Vernon, Emerson; de Geronimo, Gianluigi; Fried, Jack; Herman, Cedric; Zhang, Feng; He, Zhong

    2009-08-01

    A CMOS application specific integrated circuit (ASIC) was developed for 3D Position Sensitive Detectors (PSD). The preamplifiers were optimized for pixellated Cadmium-Zinc-Telluride (CZT) Mercuric-Iodide (HgI2) and Thallium Bromide (TlBr) sensors. The ASIC responds to an ionizing event in the sensor by measuring both amplitude and timing in the pertinent anode and cathode channels. Each channel is sensitive to events and transients of positive or negative polarity and performs low-noise charge amplification, high-order shaping, peak and timing detection along with analog storage and multiplexing. Three methodologies are implemented to perform timing measurement in the cathode channel. Multiple sparse modes are available for the readout of channel data. The ASIC integrates 130 channels in an area of 12 x 9 mm2 and dissipates ~330 mW. With a CZT detector connected and biased, an electronic resolution of ~200 e- rms for charges up to 100 fC was measured. Spectral data from the University of Michigan revealed a cumulative single-pixel resolution of ~0.55 % FWHM at 662 KeV.

  4. Front-end ASICs for high-energy astrophysics in space

    Science.gov (United States)

    Gevin, O.; Limousin, O.; Meuris, A.

    2016-07-01

    In most of embedded imaging systems for space applications, high granularity and increasing size of focal planes justify an almost systematic use of integrated circuits. . To fulfill challenging requirements for excellent spatial and energy resolution, integrated circuits must fit the sensors perfectly and interface the system such a way to optimize simultaneously noise, geometry and architecture. Moreover, very low power consumption and radiation tolerance are mandatory to envision a use onboard a payload in space. Consequently, being part of an optimized detection system for space, the integrated circuit is specifically designed for each application and becomes an Application Specific Integrated Circuits (ASIC). The paper focuses on mixed analog and digital signal ASICs for spectro-imaging systems in the keVMeV energy band. The first part of the paper summarizes the main advantages conferred by the use of front-end ASICs for highenergy astrophysics instruments in space mission. Space qualification of ASICs requires the chip to be radiation hard. The paper will shortly describe some of the typical hardening techniques and give some guidelines that an ASIC designer should follow to choose the most efficient technology for his project. The first task of the front-end electronics is to convert the charge coming from the detector into a voltage. For most of the Silicon detectors (CCD, DEPFET, SDD) this is conversion happens in the detector itself. For other sensor materials, charge preamplifiers operate the conversion. The paper shortly describes the different key parameters of charge preamplifiers and the binding parameters for the design. Filtering is generally mandatory in order to increase the signal to noise ratio or to reduce the duration of the signal. After a brief review on the main noise sources, the paper reviews noise-filtering techniques that are commonly used in Integrated circuits designs. The way sensors and ASICs are interconnected together plays a

  5. IMOTEPAD: A mixed-signal 64-channel front-end ASIC for small-animal PET imaging

    Science.gov (United States)

    Fang, Xiaochao; Ollivier-Henry, Nicolas; Gao, Wu; Hu-Guo, Christine; Colledani, Claude; Humbert, Bernard; Brasse, David; Hu, Yann

    2011-04-01

    This paper presents the design and characteristics of a mixed-signal 64-channel front-end readout ASIC called IMOTEPAD dedicated to multi-channel plate (MCP) photodetector coupled to LYSO scintillating crystals for small-animal PET imaging. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. As a result, both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. This dedicated ASIC IMOTEPAD comprises two parts: the analog part IMOTEPA and the digital part IMOTEPD. The IMOTEPA is dedicated to energy measurement. And the timing information is digitized by the IMOTEPD in which the key principal element is a time-to-digital converter (TDC) based on a delay-locked loop (DLL) with 32 delay cells. The chip is designed and fabricated in 0.35 μm CMOS process. The measurements show that for the analog part IMOTEPA, the energy gain is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The SNR is 39 dB and the RMS noise is 300 μV. The nonlinearity is less than 3%. The crosstalk is less than 0.2%. For the IMOTEPD, the bin size of the TDC is 625 ps with a reference clock of 50 MHz. The RMS jitter of the DLL is less than 42 ps. The DNL of the TDC is equal to about 0.17 LSB and the INL is equal to 0.31 LSB. The power dissipation of each channel is less than 16.8 mW. The design of the ASIC, especially for TDC and the measurement results of the IMOTEPAD will be presented and discussed in this paper.

  6. Evaluation of a front-end ASIC for the readout of PMTs in large dynamic range

    CERN Document Server

    Wu, Weihao; Liang, Yu; Yu, Li; Liu, Jianfeng; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of major detectors for searching gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit) fabricated in Global Foundry 0.35 {\\mu}m CMOS technology, has been developed for readout of Photomultiplier Tubes (PMTs) in the WCDA. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better than 400 ps and the charge resolution is better than 1% with large input signals and remains better than 15% @ 1 Photo Electron (P.E.), both beyond the application requirement. Moreover, this ASIC has a weak ambient temperature dependence, low input rate dependence and high channel-to-channel isolation.

  7. FATALIC: A Dedicated Front-End ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Royer, Laurent; The ATLAS collaboration

    2015-01-01

    A front-end ASIC (FATALIC) has been developed to fulfil the requirements of the Phase 2 upgrade of the ATLAS Tile Calorimeter. This electronics performs the complete processing of the signal delivered by each PM tube. The first stage is a current conveyor which splits the 17-bit dynamic range of the input signal into three ranges. Each channel is followed by a shaper and a dedicated pipeline 12-bit ADC operating at 40MHz. The chip is developed using a 130nm CMOS technology. Measurements show a linearity better than 0.5% for low energy particles, and an ENC limited to 10 fC.

  8. A new front-end ASIC for GEM detectors with time and charge measurement capabilities

    Science.gov (United States)

    Ciciriello, F.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Marzocca, C.; Matarrese, G.; Ranieri, A.

    2016-07-01

    A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e- for a detector capacitance of 10 pF. © 2001 Elsevier Science. All rights reserved

  9. A new front-end ASIC for GEM detectors with time and charge measurement capabilities

    Energy Technology Data Exchange (ETDEWEB)

    Ciciriello, F., E-mail: fabio.ciciriello@poliba.it [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Corsi, F. [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); De Robertis, G. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Felici, G. [INFN, Laboratori Nazionali di Frascati, Via E. Fermi 40, I-00044 Frascati (Italy); Loddo, F. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Marzocca, C.; Matarrese, G. [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Ranieri, A. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy)

    2016-07-11

    A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e{sup −} for a detector capacitance of 10 pF. © 2001 Elsevier Science. All rights reserved.

  10. An analogue front-end ASIC prototype designed for PMT signal readout

    Science.gov (United States)

    Liu, Jian-Feng; Zhao, Lei; Yu, Li; Liang, Yu; Qin, Jia-Jun; Yang, Yun-Fan; Wu, Wei-Hao; Liu, Shu-Bin; An, Qi

    2016-06-01

    The Water Cherenkov Detector Array (WCDA) is one of the core detectors in the Large High Altitude Air Shower Observatory (LHAASO), and it consists of 3600 photomultiplier tubes (PMTs). Both high resolution time and charge measurement are required over a large dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated using Global Foundry 0.35 μm CMOS technology is designed to read out the PMT signal in the WCDA. This ASIC employs leading edge discrimination and an (RC)4 shaping structure. Combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge resolution is better than 10% at 1 P.E. and better than 1% with large input signals (300 P.E. to 4000 P.E.). Besides, this ASIC has a good channel-to-channel isolation of more than 84 dB and the temperature dependency of charge measurement is less than 5% in the range 0-50°C. Supported by Knowledge Innovation Program of Chinese Academy of Sciences (KJCX2-YW-N27), National Natural Science Foundation of China (11175174) and CAS Center for Excellence in Particle Physics (CCEPP)

  11. A low-power high dynamic range front-end ASIC for imaging calorimeters

    CERN Document Server

    Bagliesi, M G; Marrocchesi, P S; Meucci, M; Millucci, V; Morsani, F; Paoletti, R; Pilo, F; Scribano, A; Turini, N; Valle, G D

    2002-01-01

    High granularity calorimeters with shower imaging capabilities require dedicated front-end electronics. The ICON 4CH and VA4 PMT chip-set is suitable for very high dynamic range systems with strict noise requirements. The ICON 4CH is a 4 channel input, 12 channel output ASIC designed for use in a multi-anode photomultiplier system with very large dynamic range and low-noise requirements. Each of the four input signals to the ASIC is split equally into three branches by a current conveyor. Each of the three branches is scaled differently: 1:1, 1:8 and 1:80. The signal is read out by a 12 channel low noise/low power high dynamic range charge sensitive preamplifier-shaper circuit (VA4-PMT chip), with simultaneous sample- and-hold, multiplexed analog read-out, calibration facilities. Tests performed in our lab with a PMT are reported in terms of linearity, dynamic range and cross-talk of the system. (5 refs).

  12. An Analogue Front-End ASIC Prototype Designed For PMT Signal Readout

    CERN Document Server

    Liu, Jianfeng; Yu, Li; Liang, Yu; Qin, Jiajun; Yang, Yunfang; Wu, Weihao; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) is designed for high energy gamma ray and cosmic ray detection. A Water Cherenkov Detector Array which is sensitive to gamma ray showers above a few hundred GeV is proposed to survey gamma ray sources. The WCDA consists of 3600 PhotoMultiplier Tubes (PMT) which collect the Cherenkov light produced by the shower particles in water. Both high precision time and charge measurement are required over a large dynamic range from 1 photo electron (P.E.) to 4000 P.E. Prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated in Chartered 0.35 {\\mu}m CMOS technology is designed to read out PMT signal in the WCDA. This ASIC employs leading edge discrimination and RC4 shaping structure; combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge...

  13. A custom front-end ASIC for the readout and timing of 64 SiPM photosensors

    Energy Technology Data Exchange (ETDEWEB)

    Bagliesi, M.G., E-mail: mg.bagliesi@pi.infn.it [Department of Physics, University of Siena and INFN, Via Roma 56, 53100 Siena (Italy); Avanzini, C. [INFN Sezione di Pisa, Edificio C-Polo Fibonacci Largo Bruno Pontecorvo 3, 56127 Pisa (Italy); Bigongiari, G.; Cecchi, R.; Kim, M.Y.; Maestro, P.; Marrocchesi, P.S. [Department of Physics, University of Siena and INFN, Via Roma 56, 53100 Siena (Italy); Morsani, F. [INFN Sezione di Pisa, Edificio C-Polo Fibonacci Largo Bruno Pontecorvo 3, 56127 Pisa (Italy)

    2011-06-15

    A new class of instruments - based on Silicon PhotoMultiplier (SiPM) photosensors - are currently under development for the next generation of Astroparticle Physics experiments in future space missions. A custom front-end ASIC (Application Specific Integrated Circuit) for the readout of 64 SiPM sensors was specified in collaboration with GM-IDEAS (Norway) that designed and manufactured the ASIC. Our group developed a custom readout board equipped with a 16 bit ADC for the digitization of both pulse height and time information. A time stamp, generated by the ASIC in correspondence of the threshold crossing time, is digitized and recorded for each channel. This allows to define a narrow time window around the physics event that reduces significantly the background due to the SiPM dark count rate. In this paper, we report on the preliminary test results obtained with the readout board prototype.

  14. A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W.; Yin, J.; Li, C.; Zeng, H.; Gao, D. [Institute of Microelectronics, School of Computer Science and Techonology, Northwestern Polytechnical University, Xi' an (China); Hu, Y. [Institut Pluridiscipline Hubert Curien, CNRS/UDS/IN2P3, Strasbourg (France)

    2015-07-01

    This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e{sup -} to 100000 e{sup -}, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)

  15. Design and Characteristics of a Multichannel Front-End ASIC Using Current-Mode CSA for Small-Animal PET Imaging.

    Science.gov (United States)

    Ollivier-Henry, N; Wu Gao; Xiaochao Fang; Mbow, N A; Brasse, D; Humbert, B; Hu-Guo, C; Colledani, C; Yann Hu

    2011-02-01

    This paper presents the design and characteristics of a front-end readout application-specific integrated circuit (ASIC) dedicated to a multichannel-plate photodetector coupled to LYSO scintillating crystals. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. Both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. A current-mode charge-sensitive amplifier is proposed for this application. This paper presents performance characteristics of a 10-channel prototype chip designed and fabricated in a 0.35-μm complementary metal-oxide semiconductor process. The main results of simulations and measurements are presented and discussed. The gain of the chip is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The signal-to-noise ratio is 39 dB and the rms noise is 300 μV/√(Hz). The nonlinearity is less than 3% and the crosstalk is about 0.2%. The power dissipation is less than 15 mW/channel. This prototype will be extended to a 64-channel circuit with integrated time-to-digital converter and analog-to-digital converter together for a high-sensitive small-animal positron emission tomography imaging system.

  16. FRONT-END ASIC FOR HIGH RESOLUTION X-RAY SPECTROMETERS.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; CHEN, W.; FRIED, J.; LI, Z.; PINELLI, D.A.; REHAK, P.; VERNON, E.; GASKIN, J.A.; RAMSEY, B.D.; ANELLI, G.

    2007-10-27

    We present an application specific integrated circuit (ASIC) for high-resolution x-ray spectrometers. The ASIC is designed to read out signals from a pixelated silicon drift detector (SDD). Each hexagonal pixel has an area of 15 mmz and an anode capacitance of less than 100 fF. There is no integrated Field Effect transistor (FET) in the pixel, rather, the readout is done by wirebonding the anodes to the inputs of the ASIC. The ASIC provides 14 channels of low-noise charge amplification, high-order shaping with baseline stabilization, and peak detection with analog memory. The readout is sparse and based on low voltage differential signaling. An interposer provides all the interconnections required to bias and operate the system. The channel dissipates 1.6 mW. The complete 14-pixel unit covers an area of 210 mm{sup 2}, dissipates 12 mW cm{sup -2}, and can be tiled to cover an arbitrarily large detection area. We measured a preliminary resolution of 172 eV at -35 C on the 6 keV peak of a {sup 55}Fe source.

  17. Single Event Effect Hardness for the Front-end ASICs Applied in BGO Calorimeter of DAMPE Satellite

    CERN Document Server

    Gao, Shan-Shan; Feng, Chang-Qing; Xi, Kai; Liu, Shu-Bin; An, Qi

    2016-01-01

    Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray study with a primary scientific goal of indirect search of dark matter particles. As a crucial sub-detector, BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of more than 3 years makes single event effect (SEE) a probable threat to reliability. In order to evaluate the SEE sensitivity of the chips and verify the effectiveness of mitigation methods, a series of laser-induced and heavy ion-induced SEE tests were performed. Benefiting from the single event latch-up (SEL) protection circuit for power supply, the triple module redundancy (TMR) technology for the configuration regist...

  18. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    Science.gov (United States)

    Gao, W.; Liu, H.; Gan, B.; Hu, Y.

    2014-05-01

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e- to 180,000e-, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e- at zero farad plus 5.4 e- per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

  19. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W., E-mail: gaowu@nwpu.edu.cn [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Liu, H., E-mail: newhui.cn@gmail.com [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Gan, B., E-mail: shadow524@163.com [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Hu, Y., E-mail: Yann.Hu@ires.in2p3.fr [Institut Pluridisciplinaire Hubert Curien, IN2P3/CNRS/UDS, Strasbourg (France)

    2014-05-01

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e{sup −} to 180,000e{sup −}, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e{sup −} at zero farad plus 5.4 e{sup −} per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

  20. System-level considerations for the front-end readout ASIC in the CBM experiment from the power supply perspective

    Science.gov (United States)

    Kasinski, K.; Koczon, P.; Ayet, S.; Löchner, S.; Schmidt, C. J.

    2017-03-01

    New fixed target experiments using high intensity beams with energy up to 10 AGeV from the SIS100 synchrotron presently being constructed at FAIR/GSI are under preparation. Most of the readout electronics and power supplies are expected to be exposed to a very high flux of nuclear reaction products and have to be radiation tolerant up to 3 MRad (TID) and sustain up to 1014/cm2 of 1 MeV neutron equivalent in their life time. Moreover, the mostly minimum ionising particles under investigation leave very little signal in the sensors. Therefore very low noise level amplitude measurements are required by the front-end electronics for effective tracking. Sensor and interconnecting micro-cable capacitance and series resistance in conjunction with intrinsic noise of the charge sensitive amplifier are dominant noise sources in the system. However, the single-ended architecture of the amplifiers employed for the charge processing channels implies a potential problem with noise contributions from power supply sources. Strict system-level constraints leave very little freedom in selecting a power supply structure optimal with respect to: power efficiency, cooling capabilities and power density on modules, but also noise injection to the front-end via the power supply lines. Design of the power supply and distribution system of the Silicon Tracking System in the CBM experiment together with details on the front-end ASICs (STS -XYTER2) and measurement results of power supply and conditioning electronics (selected DC/DC converter and LDO regulators) are presented.

  1. Characterization of the VEGA ASIC coupled to large area position-sensitive Silicon Drift Detectors

    CERN Document Server

    Campana, R; Fuschino, F; Ahangarianabhari, M; Macera, D; Bertuccio, G; Grassi, M; Labanti, C; Marisaldi, M; Malcovati, P; Rachevski, A; Zampa, G; Zampa, N; Andreani, L; Baldazzi, G; Del Monte, E; Favre, Y; Feroci, M; Muleri, F; Rashevskaya, I; Vacchi, A; Ficorella, F; Giacomini, G; Picciotto, A; Zuffa, M

    2014-01-01

    Low-noise, position-sensitive Silicon Drift Detectors (SDDs) are particularly useful for experiments in which a good energy resolution combined with a large sensitive area is required, as in the case of X-ray astronomy space missions and medical applications. This paper presents the experimental characterization of VEGA, a custom Application Specific Integrated Circuit (ASIC) used as the front-end electronics for XDXL-2, a large-area (30.5 cm^2) SDD prototype. The ASICs were integrated on a specifically developed PCB hosting also the detector. Results on the ASIC noise performances, both stand-alone and bonded to the large area SDD, are presented and discussed.

  2. A Serializer ASIC at 5 Gbps for Detector Front-end Electronics Readout

    CERN Document Server

    Ye, J; The ATLAS collaboration

    2010-01-01

    Optical data links are used in detector front-end electronics readout systems of experiments in the Tevatron and the LHC. Optical links in high energy particle physics experiments usually have special requirements such as radiation tolerance, ultra high reliability and low power dissipation. These requirements are often not met by commercial components which are designed for applications in non-radiation, accessible (for maintenance) environment, and for multi-vendor systems so the parts must comply with certain standards. Future HEP experiments such as the upgrades for the sLHC call for optical links with ultra high data bandwidth, higher radiation tolerance and ultra low power dissipation. To meet these challenges and in particular those in the upgrade for the ATLAS Liquid Argon Calorimeter readout that calls for an optical link system of 100 Gbps for each front-end board, we adopted a full custom front-end electronics system design based on application specific integrated circuits. Reported here are the de...

  3. An ASIC design for versatile receive front-end electronics of an ultrasonic medical imaging system--16 channel analog inputs and 4 dynamically focused beam outputs.

    Science.gov (United States)

    Park, Song B; Kwak, Jaeyoung; Lee, Kwyro

    2003-04-01

    An ultra large-scale ASIC is designed for the receive front-end electronics of an ultrasonic medical imaging system. The chip receives 16 channel analog rf signals and outputs 4 sets of sample-point-wise dynamically focused partial beam data. Four complete beam data sets are obtained in parallel by simply cascading as many chips as needed in an array system. High resolution of the focusing delay is obtained by nonuniformly selecting each channel data from a quadruply-interpolated rf data stream. The proposed ASIC can be applied to most practical array transducers in the frequency range of 2 to 10 MHz. The digital part of the designed ASIC can be implemented on a chip area of 17.9 microm2 with 0.18 mm CMOS technology, leaving sufficient room for 16 ADCs of 8 bits, 50 MHz on the 5.7 mm x 5.7 mm chip with a 208 pin package.

  4. First results of the front-end ASIC for the strip detector of the PANDA MVD

    Science.gov (United States)

    Quagli, T.; Brinkmann, K.-T.; Calvo, D.; Di Pietro, V.; Lai, A.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Wheadon, R.; Zambanini, A.

    2017-03-01

    PANDA is a key experiment of the future FAIR facility and the Micro Vertex Detector (MVD) is the innermost part of its tracking system. PASTA (PAnda STrip ASIC) is the readout chip for the strip part of the MVD. The chip is designed to provide high resolution timestamp and charge information with the Time over Threshold (ToT) technique. Its architecture is based on Time to Digital Converters with analog interpolators, with a time bin width of 50 ps. The chip implements Single Event Upset (SEU) protection techniques for its digital parts. A first full-size prototype with 64 channels was produced in a commercial 110 nm CMOS technology and the first characterizations of the prototype were performed.

  5. An ultrafast front-end ASIC for APD array detectors in X-ray time-resolved experiments

    Science.gov (United States)

    Zhou, Yang-Fan; Li, Qiu-Ju; Liu, Peng; Fan, Lei; Xu, Wei; Tao, Ye; Li, Zhen-Jie

    2017-06-01

    An ultrafast front-end ASIC chip has been developed for APD array detectors in X-ray time-resolved experiments. The chip has five channels: four complete channels and one test channel with an analog output. Each complete channel consists of a preamplifier, a voltage discriminator and an open-drain output driver. A prototype chip has been designed and fabricated using 0.13 μm CMOS technology with a chip size of 1.3 mm × 1.9 mm. The electrical characterizations of the circuit demonstrate a very good intrinsic time resolution (rms) on the output pulse leading edge, with the test result better than 30 ps for high input signal charges (> 75 fC) and better than 100 ps for low input signal charges (30-75 fC), while keeping a low power consumption of 5 mW per complete channel. Supported by the National Natural Science Foundation of China (11605227), High Energy Photon Source-Test Facility Project, and the State Key Laboratory of Particle Detection and Electronics. This research used resources of the BSRF.

  6. Design of a wideband CMOS impedance spectroscopy ASIC analog front-end for multichannel biosensor interfaces.

    Science.gov (United States)

    Valente, Virgilio; Dai Jiang; Demosthenous, Andreas

    2015-08-01

    This paper presents the preliminary design and simulation of a flexible and programmable analog front-end (AFE) circuit with current and voltage readout capabilities for electric impedance spectroscopy (EIS). The AFE is part of a fully integrated multifrequency EIS platform. The current readout comprises of a transimpedance stage and an automatic gain control (AGC) unit designed to accommodate impedance changes larger than 3 order of magnitude. The AGC is based on a dynamic peak detector that tracks changes in the input current over time and regulates the gain of a programmable gain amplifier in order to optimise the signal-to-noise ratio. The system works up to 1 MHz. The voltage readout consists of a 2 stages of fully differential current-feedback instrumentation amplifier which provide 100 dB of CMRR and a programmable gain up to 20 V/V per stage with a bandwidth in excess of 10MHz.

  7. Characterization and performance of the ASIC (CITIROC) front-end of the ASTRI camera

    CERN Document Server

    Impiombato, D; Mineo, T; Catalano, O; Gargano, C; La Rosa, G; Russo, F; Sottile, G; Billotta, S; Bonanno, G; Garozzo, S; Grillo, A; Marano, D; Romeo, G

    2015-01-01

    The Cherenkov Imaging Telescope Integrated Read Out Chip, CITIROC, is a chip adopted as the front-end of the camera at the focal plane of the imaging Cherenkov ASTRI dual-mirror small size telescope (ASTRI SST-2M) prototype. This paper presents the results of the measurements performed to characterize CITIROC tailored for the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger linearity and efficiency, as a function of the pulse amplitude. Moreover, we tested its response by performing a set of measurements using a silicon photomultiplier (SiPM) in dark conditions and under light pulse illumination. The CITIROC output signal is found to vary linearly as a function of the input pulse amplitude. Our results show that it is suitable for the ASTRI SST-2M camera.

  8. Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

    Science.gov (United States)

    Zeng, Huiming; Wei, Tingcun; Wang, Jia

    2017-03-01

    A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal-oxide-semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 μm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e-+16.3e-/pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

  9. Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W., E-mail: gaowu@nwpu.edu.cn; Gan, B.; Li, X.; Wei, T.; Gao, D.; Hu, Y.

    2015-04-21

    In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e{sup −} at zero farad plus 10 e{sup −} per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source {sup 241}Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si)

  10. Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

    Science.gov (United States)

    Gao, W.; Gan, B.; Li, X.; Wei, T.; Gao, D.; Hu, Y.

    2015-04-01

    In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e- at zero farad plus 10 e- per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source 241Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si).

  11. Radiation hardness studies of the front-end ASICs for the optical links of the ATLAS semiconductor tracker

    CERN Document Server

    White, D J; Mahout, G; Jovanovic, P; Mandic, I; Weidberg, A R

    2001-01-01

    Studies have been performed on the effects of radiation on ASICs incorporating bipolar npn transistors in the AMS 0.8 mu m BiCMOS process. Radiation effects are reviewed and the approach used to achieve radiation tolerant ASICs is described. The radiation tests required to validate the ASICs for use in the ATLAS detector at the CERN Large Hadron Collider are discussed. The results demonstrate that they are sufficiently radiation tolerant for use in the ATLAS semiconductor tracker. (20 refs).

  12. Analog front-end design of the STS/MUCH-XYTER2—full size prototype ASIC for the CBM experiment

    Science.gov (United States)

    Kleczek, Rafal

    2017-01-01

    The design of the analog front-end of the STS/MUCH-XYTER2 ASIC, a full-size prototype chip for the Silicon Tracking System (STS, based on double-sided silicon strip sensors) and Muon Chamber (MUCH, based on gas sensors) detectors is presented. The ASIC contains 128 charge processing channels, each built of a charge sensitive amplifier, a polarity selection circuit and two pulse shaping amplifiers forming two parallel signal paths. The first path is used for timing measurement with a fast discriminator. The second path allows low-noise amplitude measurement with a 5-bit continuous-time flash ADC. Different operating conditions and constraints posed by two target detectors' applications require front-end electronics flexibility to meet extended system-wise requirements. The presented circuit implements switchable shaper peaking time, gain switching and trimming, input amplifier pulsed reset circuit, fail-safe measures. The power consumption is scalable (for the STS and the MUCH modes), but limited to 10 mW/channel.

  13. Performance of an analog ASIC developed for the front-end electronics of the soft x-ray imager onboard ASTRO-H

    Science.gov (United States)

    Nakajima, H.; Idehara, T.; Matsuura, D.; Anabuki, N.; Tsunemi, H.; Doty, J. P.; Ikeda, H.

    2009-08-01

    We report on the performance of an analog application-specified integrated circuit (ASIC) developed for the front-end electronics of the X-ray CCD camera system (SXI: Soft X-ray Imager) onboard the ASTRO-H satellite. The ASIC consists of four identical channels and they simultaneously process the CCD signals at the pixel rate of 68kHz. Delta-Sigma modulator is adopted to achieve effective noise shaping and obtain a high resolution decimal values with relatively simple circuits. We will implement 16 ASIC chips in total in the focal plane assembly. The results of the unit test shows that it works properly with moderately low input noise of <30μV at the pixel rate of 80kHz. Power consumption is sufficiently low of 150mW. Dynamic range of input signals is +-20mV that covers effective energy range of the CCD chips of SXI (0.2-20keV). The integrated non-linearity of 0.2% satisfies the same performance as the conventional CCD detectors in orbit. The radiation tolerance against total ionizing dose (TID) effect and single event latch-up (SEL) has also been investigated. The irradiation test using 60Co gamma-rays and proton beam showed that the ASIC has sufficient tolerance against TID up to 200 and 167krad respectively, which thoroughly exceeds the expected operating duration in the planned low-inclination low-earth orbit. The irradiation of the Fe ion beam also showed no latch-up nor malfunctions up to the fluence of 4.7x10^7ions. The threshold against SEL is larger than 1.68MeVcm^2/mg, which is sufficiently high enough that SEL events should not be a major cause of instrument downtime.

  14. Front-end readout ASIC for charged particle counting with the RADEM instrument on the ESA JUICE mission

    Science.gov (United States)

    Stein, Timo A.; Pâhlsson, Philip; Meier, Dirk; Hasanbegovic, Amir; Otnes Berge, Hans Kristian; Altan, Mehmet Akif; Ackermann, Jörg; Najafiuchevler, Bahram; Azman, Suleyman; Talebi, Jahanzad; Olsen, Alf; Gheorghe, Codin; Steenari, David; Øya, Petter; Johansen, Tor Magnus; Maehlum, Gunnar

    2016-07-01

    The detector readout for the Radiation-hard Electron Monitor (RADEM) aboard the JUpiter ICy moons Explorer (JUICE) uses a custom-made application-specific integrated circuit (ASIC, model: IDE3466) for the charge signal readout from silicon radiation sensors. RADEM measures the total ionizing dose and dose rate for protons (5 MeV to 250 MeV), electrons (0.3 MeV to 40 MeV) and ions. RADEM has in total three chips of the same design: one chip for the proton and ion detector, one for the electron detector, and one for the directional detector. The ASIC has 36 chargesensitive pre-amplifiers (CSA), 36 counters of 22-bits each, and one analogue output for multiplexing the pulse heights from all channels. The counters count pulses from charged particles in the silicon sensors depending on the charge magnitude and the coincidence trigger pattern from the 36 channels. We have designed the ASIC in 0.35-μm CMOS process and an ASIC wafer lot has been manufactured at AMS. This article presents the ASIC design specifications and design validation results. The preliminary results from tests with bare chips indicate that the design meets the technical requirements.

  15. A time-based front-end ASIC for the silicon micro strip sensors of the bar PANDA Micro Vertex Detector

    Science.gov (United States)

    Di Pietro, V.; Brinkmann, K.-Th.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Zambanini, A.

    2016-03-01

    The bar PANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA (bar PANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels.

  16. Design of a Constant Fraction Discriminator for the VFAT3 front-end ASIC of the CMS GEM detector

    CERN Document Server

    AUTHOR|(CDS)2069646; Abbas, M.; Abbrescia, M.; Abdelalim, A.A.; Abi Akl, M.; Aboamer, O.; Acosta, D.; Ahmad, A.; Ahmed, W.; Ahmed, W.; Aleksandrov, A.; Aly, R.; Altieri, P.; Asawatangtrakuldee, C.; Aspell, P.; Assran, Y.; Awan, I.; Bally, S.; Ban, Y.; Banerjee, S.; Barashko, V.; Barria, P.; Bencze, G.; Beni, N.; Benussi, L.; Bhopatkar, V.; Bianco, S.; Bos, J.; Bouhali, O.; Braghieri, A.; Braibant, S.; Buontempo, S.; Calabria, C.; Caponero, M.; Caputo, C.; Cassese, F.; Castaneda, A.; Cauwenbergh, S.; Cavallo, F.R.; Celik, A.; Choi, M.; Choi, S.; Christiansen, J.; Cimmino, A.; Colafranceschi, S.; Colaleo, A.; Conde Garcia, A.; Czellar, S.; Dabrowski, M.M.; De Lentdecker, G.; De Oliveira, R.; de Robertis, G.; Dildick, S.; Dorney, B.; Elmetenawee, W.; Endroczi, G.; Errico, F.; Fenyvesi, A.; Ferry, S.; Furic, I.; Giacomelli, P.; Gilmore, J.; Golovtsov, V.; Guiducci, L.; Guilloux, F.; Gutierrez, A.; Hadjiiska, R.M.; Hassan, A.; Hauser, J.; Hoepfner, K.; Hohlmann, M.; Hoorani, H.; Iaydjiev, P.; Jeng, Y.G.; Kamon, T.; Karchin, P.; Korytov, A.; Krutelyov, S.; Kumar, A.; Kim, H.; Lee, J.; Lenzi, T.; Litov, L.; Madorsky, A.; Maerschalk, T.; Maggi, M.; Magnani, A.; Mal, P.K.; Mandal, K.; Marchioro, A.; Marinov, A.; Masod, R.; Majumdar, N.; Merlin, J.A.; Mitselmakher, G.; Mohanty, A.K.; Mohamed, S.; Mohapatra, A.; Molnar, J.; Muhammad, S.; Mukhopadhyay, S.; Naimuddin, M.; Nuzzo, S.; Oliveri, E.; Pant, L.M.; Paolucci, P.; Park, I.; Passeggio,G.; Pavlov, B.; Philipps, B.; Piccolo, D.; Postema, H.; Puig Baranac, A.; Radi, A.; Radogna, R.; Raffone, G.; Ranieri, A.; Rashevski, G.; Riccardi, C.; Rodozov, M.; Rodrigues, A.; Ropelewski, L.; RoyChowdhury, S.; Ryu, G.; Ryu, M.S.; Safonov, A.; Salva, S.; Saviano, G.; Sharma, A.; Sharma, A.; Sharma, R.; Shah, A.H.; Shopova, M.; Sturdy, J.; Sultanov, G.; Swain, S.K.; Szillasi, Z.; Talvitie, J.; Tamma, C.; Tatarinov, A.; Tuuva, T.; Tytgat, M.; Vai, I.; Van Stenis, M.; Venditti, R.; Verhagen, E.; Verwilligen, P.; Vitulo, P.; Volkov, S.; Vorobyev, A.; Wang, D.; Wang, M.; Yang, U.; Yang, Y.; Yonamine, R.; Zaganidis, N.; Zenoni, F.; Zhang, A.

    2016-01-01

    In this work the design of a Constant Fraction Discriminator (CFD) to be used in the VFAT3 chip, currently under design for the read-out of the Triple-Gem detectors of the CMS experiment, is described. Simulations show that it is possible to extend the front-end shaping time in order to fully integrate the GEM detector signal charge whilst maintaining optimal timing resolution using the CFD technique. A prototype chip containing 8 CFDs was implemented in 130 nm CMOS technology to prove the effectiveness of the proposed architecture before its integration in the VFAT3 chip. The CFD design and test results will be shown.

  17. The TDCpix readout ASIC: A 75 ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Kluge, A., E-mail: alexander.kluge@cern.ch; Aglieri Rinella, G.; Bonacini, S.; Jarron, P.; Kaplon, J.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    2013-12-21

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm{sup 2} for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection efficiency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45×40 square pixels of 300×300μm{sup 2} and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low-jitter PLL, readout and control circuits. This contribution will describe the complete design of the final TDCpix ASIC. It will discuss design choices, the challenges faced and some of the lessons learned. Furthermore, experimental results from the testing of circuit prototypes will be presented. These demonstrate the achievement of key performance figures such as a time resolution of the processing chain of 75 ps rms with a laser sent to the center of the pixel and the capability of time stamping charged particles with an overall resolution below 200 ps rms. -- Highlights: • Feasibility demonstration of a silicon pixel detector with sub-ns time tagging capability. • Demonstrator detector assembly with a time resolution of 75 ps RMS with laser charge injection; 170 ps RMS with particle beam. • Design of trigger-less TDCpix ASIC with 1800 pixels, 720 TDC channels and 4 3.2 Gbit/s serializers.

  18. CLARO-CMOS: a fast, low power and radiation-hard front-end ASIC for single-photon counting in 0.35 micron CMOS technology

    Science.gov (United States)

    Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Fiorini, M.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2015-01-01

    The CLARO-CMOS is a prototype ASIC designed for fast photon counting with multi-anode photomultiplier tubes (MaPMT). The CLARO features a 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. The chip was designed in 0.35 μm CMOS technology, and was tested for radiation hardness with neutrons up to 1014 1 MeV neq/cm2, X-rays up to 40 kGy and protons up to 76 kGy. Its capability to read out single photons at high rate from a Hamamatsu R11265 MaPMT, the baseline photon detector for the LHCb RICH upgrade, was demonstrated both with test bench measurements and with actual signals from a R11265 MaPMT. The presented results allowed CLARO to be chosen as the front-end readout chip in the upgraded LHCb RICH detector.

  19. A 4-Channel Waveform Sampling ASIC in 0.13 μm CMOS for front-end Readout of Large-Area Micro-Channel Plate Detectors

    Science.gov (United States)

    Oberla, E.; Grabas, H.; Bogdan, M.; Frisch, H.; Genat, J. F.; Nishimura, K.; Varner, G.; Wong, A.

    We describe here the development of PSEC-3, a custom integrated circuit designed in the IBM-8RF 0.13 μm CMOS process and intended for fast, low-power waveform sampling. As part of the Large-Area Picosecond Photo-Detector (LAPPD) collaboration, this chip has been designed as a prototype application-specific integrated circuit (ASIC) for the front-end transmission line readout of large-area micro-channel plate photomultiplier tubes (MCP-PMTs). With 4 channels, PSEC-3 has a buffer depth of 256 samples on each channel, a chip-parallel ramp-compare ADC, and a serial data readout that includes the capability for region-of-interest windowing to reduce dead time. Chip calibrations and performance results, including achieved sampling rates of 2.5-17 GSa/s, are reported. Some design issues are identified, in particular the dependence of analog bandwidth on location in the sampling array. The causes have been found and addressed in a subsequent PSEC-4 submission.

  20. The TDCpix readout ASIC: A 75ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    CERN Document Server

    Kluge, A; Bonacini, S; Jarron, P; Kaplon, J; Morel, M; Noy, M; Perktold, L; Poltorak, K

    2013-01-01

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak fl ow of particles crossing the detector modules reaches 1.27 MHz/mm 2 for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection ef fi ciency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45 40 square pixels of 300 300 μ m 2 and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low...

  1. The TDCpix Readout ASIC: A 75 ps Resolution Timing Front-End for the Gigatrackerof theNA62 Experiment

    Science.gov (United States)

    Rinella, G. Aglieri; Fiorini, M.; Jarron, P.; Kaplon, J.; Kluge, A.; Martin, E.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    NA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at measuring ultra rare kaon decays. The Gigatracker (GTK) detector shall combine on-beam tracking of individual particles with a time resolution of 150 ps rms. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm2 fora total rateof about 0.75 GHz.Ahybrid siliconpixel detectoris beingdevelopedto meet these requirements. The pixel chip for the Gigatracker (TDCpix) is under design. The TDCpix chip will feature 1800 square pixels of 300×300 μm2 arranged in a matrix of 45 rows × 40 columns. Bump-bonded to a silicon pixel sensor it shall perform time stamping of particle hits with a timing accuracybetter than 200 ps rms and a detection efficiencyabove 99%. The chosen architecture provides full separation of the sensitive analog amplifiers of the pixel matrix from the noisy digital circuits of the TDCs and of the readout blocks. Discriminated hit signals from each pixel are transmitted to the end of column region. An array ofTime to Digital Converters (TDC) is implemented at the bottom of the pixel array. The TDCs are based on time tagging the events with the fine time codes generated by Delay Locked Loops (DLL) and have a nominal time bin of ˜100 ps. Time stamps and time-over-threshold are recorded for each discriminated hit and the correction of the discriminator's time-walk is performed off-detector. Data are continuously transmitted on four 2.4 Gb/s serial output links. Adescription of the on-going design of the final TDCpix is given in this paper. Design choices and some technical implementation details are presented. Aprototype ASIC including thekeycomponents of this architecture has been manufactured. The achievement of specification figures such as a time resolution of the processing chain of 75 ps rms as well as charged particle time stampingwitha resolutionbetterthan200psrmswere demonstratedexperimentally.Asummaryoftheseresultsisalso presented in

  2. X-ray imaging with a silicon microstrip detector coupled to the RX64 ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Baldazzi, G.; Bollini, D.; Cabal Rodriguez, A.E.; Dabrowski, W.; Diaz Garcia, A.; Gambaccini, M.; Giubellino, P.; Gombia, M.; Grybos, P.; Idzik, M.; Marzari-Chiesa, A.; Montano Zetina, L.M.; Prino, F.; Ramello, L. E-mail: ramello@to.infn.it; Sitta, M.; Swientek, K.; Taibi, A.; Tuffanelli, A.; Wheadon, R.; Wiacek, P

    2003-08-21

    A single photon counting X-ray imaging system, with possible applications to dual energy mammography and angiography, is presented. A silicon microstrip detector with 100 {mu}m pitch strips is coupled to RX64 ASICs, each of them including 64 channels of preamplifier, shaper, discriminator and scaler. The system has low noise, good spatial resolution and high counting rate capability. Results on energy resolution have been obtained with a fluorescence source and quasi-monochromatic X-rays beams. Preliminary images obtained with an angiographic phantom are presented.

  3. Temperature modeling and emulation of an ASIC temperature monitor system for Tightly-Coupled Processor Arrays (TCPAs)

    OpenAIRE

    E. Glocker; S. Boppu; Chen, Q; Schlichtmann, U.; Teich, J.; D. Schmitt-Landsiedel

    2014-01-01

    This contribution provides an approach for emulating the behaviour of an ASIC temperature monitoring system (TMon) during run-time for a tightly-coupled processor array (TCPA) of a heterogeneous invasive multi-tile architecture to be used for FPGA prototyping. It is based on a thermal RC modeling approach. Also different usage scenarios of TCPA are analyzed and compared.

  4. VEGA: A low-power front-end ASIC for large area multi-linear X-ray silicon drift detectors: Design and experimental characterization

    Energy Technology Data Exchange (ETDEWEB)

    Ahangarianabhari, Mahdi; Macera, Daniele [Politecnico di Milano, Department of Electronics Engineering, Information Science and Bioengineering, P.za L. da Vinci 32, 20133 Milano (Italy); National Institute of Nuclear Physics, INFN sez. Milano (Italy); Bertuccio, Giuseppe, E-mail: Giuseppe.Bertuccio@polimi.it [Politecnico di Milano, Department of Electronics Engineering, Information Science and Bioengineering, P.za L. da Vinci 32, 20133 Milano (Italy); National Institute of Nuclear Physics, INFN sez. Milano (Italy); Malcovati, Piero; Grassi, Marco [University of Pavia, Department of Electrical Engineering, and National Institute of Nuclear Physics, INFN sez. Pavia, Pavia (Italy)

    2015-01-11

    We present the design and the first experimental characterization of VEGA, an Application Specific Integrated Circuit (ASIC) designed to read out large area monolithic linear Silicon Drift Detectors (SDD’s). VEGA consists of an analog and a digital/mixed-signal section to accomplish all the functionalities and specifications required for high resolution X-ray spectroscopy in the energy range between 500 eV and 50 keV. The analog section includes a charge sensitive preamplifier, a shaper with 3-bit digitally selectable shaping times from 1.6 µs to 6.6 µs and a peak stretcher/sample-and-hold stage. The digital/mixed-signal section includes an amplitude discriminator with coarse and fine threshold level setting, a peak discriminator and a logic circuit to fulfill pile-up rejection, signal sampling, trigger generation, channel reset and the preamplifier and discriminators disabling functionalities. A Serial Peripherical Interface (SPI) is integrated in VEGA for loading and storing all configuration parameters in an internal register within few microseconds. The VEGA ASIC has been designed and manufactured in 0.35 µm CMOS mixed-signal technology in single and 32 channel versions with dimensions of 200 µm×500 µm per channel. A minimum intrinsic Equivalent Noise Charge (ENC) of 12 electrons r.m.s. at 3.6 µs peaking time and room temperature is measured and the linearity error is between −0.9% and +0.6% in the whole input energy range. The total power consumption is 481 µW and 420 µW per channel for the single and 32 channels version, respectively. A comparison with other ASICs for X-ray SDD’s shows that VEGA has a suitable low noise and offers high functionality as ADC-ready signal processing but at a power consumption that is a factor of four lower than other similar existing ASICs.

  5. VEGA: A low-power front-end ASIC for large area multi-linear X-ray silicon drift detectors: Design and experimental characterization

    Science.gov (United States)

    Ahangarianabhari, Mahdi; Macera, Daniele; Bertuccio, Giuseppe; Malcovati, Piero; Grassi, Marco

    2015-01-01

    We present the design and the first experimental characterization of VEGA, an Application Specific Integrated Circuit (ASIC) designed to read out large area monolithic linear Silicon Drift Detectors (SDD's). VEGA consists of an analog and a digital/mixed-signal section to accomplish all the functionalities and specifications required for high resolution X-ray spectroscopy in the energy range between 500 eV and 50 keV. The analog section includes a charge sensitive preamplifier, a shaper with 3-bit digitally selectable shaping times from 1.6 μs to 6.6 μs and a peak stretcher/sample-and-hold stage. The digital/mixed-signal section includes an amplitude discriminator with coarse and fine threshold level setting, a peak discriminator and a logic circuit to fulfill pile-up rejection, signal sampling, trigger generation, channel reset and the preamplifier and discriminators disabling functionalities. A Serial Peripherical Interface (SPI) is integrated in VEGA for loading and storing all configuration parameters in an internal register within few microseconds. The VEGA ASIC has been designed and manufactured in 0.35 μm CMOS mixed-signal technology in single and 32 channel versions with dimensions of 200 μm×500 μm per channel. A minimum intrinsic Equivalent Noise Charge (ENC) of 12 electrons r.m.s. at 3.6 μs peaking time and room temperature is measured and the linearity error is between -0.9% and +0.6% in the whole input energy range. The total power consumption is 481 μW and 420 μW per channel for the single and 32 channels version, respectively. A comparison with other ASICs for X-ray SDD's shows that VEGA has a suitable low noise and offers high functionality as ADC-ready signal processing but at a power consumption that is a factor of four lower than other similar existing ASICs.

  6. A silicon strip detector coupled to the RX64 ASIC for X-ray diagnostic imaging

    Energy Technology Data Exchange (ETDEWEB)

    Baldazzi, G.; Bollini, D.; Cabal Rodriguez, A.E.; Dabrowski, W.; Diaz Garcia, A.; Gambaccini, M.; Giubellino, P.; Gombia, M.; Grybos, P.; Idzik, M.; Marzari-Chiesa, A.; Montano, L.M.; Prino, F. E-mail: prino@to.infn.it; Ramello, L.; Sitta, M.; Swientek, K.; Taibi, A.; Tuffanelli, A.; Wheadon, R.; Wiacek, P

    2003-11-21

    First results from a silicon microstrip detector with 100 {mu}m pitch coupled to the RX64 ASIC are presented. The system is capable of single photon counting in digital X-ray imaging, with possible applications to dual energy mammography and angiography. The main features of the detecting system are low noise, good spatial resolution and high counting rate capability. The energy resolution and the conversion efficiency of the system are discussed, based on results obtained with fluorescence X-ray sources and quasi-monochromatic X-ray beams in the 8-36 keV energy range, with strips being either orthogonal or parallel to the incoming X-rays. We present also preliminary imaging results obtained with a plexiglass phantom with tiny cylindrical cavities filled with iodate solution, simulating patient vessels; in this case the X-ray beam has two components, respectively below and above the iodine K-edge at 33.17 keV.

  7. The Development of High-Performance Front-End Electronics Based Upon the QIE12 Custom ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2016-01-01

    We present the design of a new candidate front-end electronic readout system being developed for the ATLAS TileCal Phase 2 Upgrade. The system is based upon the QIE12 custom Application Specific Integrated Circuit. The chip features a least count sensitivity of 1.5 fC, more than 17 bits of dynamic range with logarithmic response, and an on-chip TDC with one nanosecond resolution. The design incorporates an on-board current integrator, and has several calibration systems. The new electronics will operate dead-timelessly at 40 MHz, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room using high-speed optical links. The system is one of three candidate systems for the Phase 2 Upgrade. We have built a “Demonstrator” – a fully functional prototype of the new system. Performance results from bench measurements and from a recent test beam campaign will be presented.

  8. Coupling Front-End Separations, Ion Mobility Spectrometry, and Mass Spectrometry For Enhanced Multidimensional Biological and Environmental Analyses

    Energy Technology Data Exchange (ETDEWEB)

    Zheng, Xueyun [Earth and Biological Sciences Directorate, Pacific Northwest National Laboratory, Richland, Washington 99352,; Wojcik, Roza [Earth and Biological Sciences Directorate, Pacific Northwest National Laboratory, Richland, Washington 99352,; Zhang, Xing [Skaggs School of Pharmacy and Pharmaceutical Sciences, Anschutz Medical Campus, University of Colorado, Denver, Colorado 80045; Ibrahim, Yehia M. [Earth and Biological Sciences Directorate, Pacific Northwest National Laboratory, Richland, Washington 99352,; Burnum-Johnson, Kristin E. [Earth and Biological Sciences Directorate, Pacific Northwest National Laboratory, Richland, Washington 99352,; Orton, Daniel J. [Earth and Biological Sciences Directorate, Pacific Northwest National Laboratory, Richland, Washington 99352,; Monroe, Matthew E. [Earth and Biological Sciences Directorate, Pacific Northwest National Laboratory, Richland, Washington 99352,; Moore, Ronald J. [Earth and Biological Sciences Directorate, Pacific Northwest National Laboratory, Richland, Washington 99352,; Smith, Richard D. [Earth and Biological Sciences Directorate, Pacific Northwest National Laboratory, Richland, Washington 99352,; Baker, Erin S. [Earth and Biological Sciences Directorate, Pacific Northwest National Laboratory, Richland, Washington 99352,

    2017-06-12

    Ion mobility spectrometry (IMS) is a widely used analytical technique for rapid molecular separations in the gas phase. IMS alone is useful, but its coupling with mass spectrometry (MS) and front-end separations has been extremely beneficial for increasing measurement sensitivity, peak capacity of complex mixtures, and the scope of molecular information in biological and environmental sample analyses. Multiple studies in disease screening and environmental evaluations have even shown these IMS-based multidimensional separations extract information not possible with each technique individually. This review highlights 3-dimensional separations using IMS-MS in conjunction with a range of front-end techniques, such as gas chromatography (GC), supercritical fluid chromatography (SFC), liquid chromatography (LC), solid phase extractions (SPE), capillary electrophoresis (CE), field asymmetric ion mobility spectrometry (FAIMS), and microfluidic devices. The origination, current state, various applications, and future capabilities for these multidimensional approaches are described to provide insight into the utility and potential of each technique.

  9. Dedicated multichannel readout ASIC coupled with single crystal diamond for dosimeter application

    Science.gov (United States)

    Fabbri, A.; Falco, M. D.; De Notaristefani, F.; Galasso, M.; Marinelli, M.; Orsolini Cencelli, V.; Tortora, L.; Verona, C.; Verona Rinati, G.

    2013-02-01

    This paper reports on the tests of a low-noise, multi-channel readout integrated circuit used as a readout electronic front-end for a diamond multi-pixel dosimeter. The system is developed for dose distribution measurement in radiotherapy applications. The first 10-channel prototype chip was designed and fabricated in a 0.18 um CMOS process. Every channel includes a charge integrator with a 10 pF capacitor and a double slope A/D converter. The diamond multi-pixel detector, based on CVD synthetic single crystal diamond Schottky diodes, is made by a 3 × 3 sensor matrix. The overall device has been tested under irradiation with 6 MeV radio therapeutic photon beams at the Policlinico ``Tor Vergata'' (PTV) hospital. Measurements show a 20 fA RMS leakage current from the front-end input stage and a negligible dark current from the diamond detector, a stable temporal response and a good linear behaviour as a function of both dose and dose rate. These characteristics were common to each tested channel.

  10. PACE3 - front-end chip for the CMS Preshower

    CERN Multimedia

    Aspel, Paul

    2003-01-01

    This is PACE3 which is the front-end chip for the CMS Preshower. In fact PACE3 is the combination of two ASICs called Delta3 and PACEAM3. Delta3 is on the left and PACEAM3 is on the right. The two ASICs are bonded together and then packaged within a single 196 pin fpBGA package.

  11. VMM - An ASIC for Micropattern Detectors

    CERN Document Server

    Iakovidis, Georgios; The ATLAS collaboration; De Geronimo, Gianluigi

    2015-01-01

    The VMM is an ASIC that can be used in a variety of tracking detectors. It is designed to be used with resistive Micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is fabricated in the 130nm 1.2V 8‐metal CMOS technology from IBM. The ASIC integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog-to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM2 is the second version of the VMM ASIC family fabricated in 2014. It was tested with resistive Micromegas prototypes in the 2015 test beam campaigns at CERN. The specification and performance of the VMM2 will be presented as well as the Micromegas detector performance with the VMM2.

  12. Front End Spectroscopy ASIC for Germanium Detectors

    Science.gov (United States)

    Wulf, Eric

    Large-area, tracking, semiconductor detectors with excellent spatial and spectral resolution enable exciting new access to soft (0.2-5 MeV) gamma-ray astrophysics. The improvements from semiconductor tracking detectors come with the burden of high density of strips and/or pixels that require high-density, low-power, spectroscopy quality readout electronics. CMOS ASIC technologies are a natural fit to this requirement and have led to high-quality readout systems for all current semiconducting tracking detectors except for germanium detectors. The Compton Spectrometer and Imager (COSI), formerly NCT, at University of California Berkeley and the Gamma-Ray Imager/Polarimeter for Solar flares (GRIPS) at Goddard Space Flight Center utilize germanium cross-strip detectors and are on the forefront of NASA's Compton telescope research with funded missions of long duration balloon flights. The development of a readout ASIC for germanium detectors would allow COSI to replace their discrete electronics readout and would enable the proposed Gamma-Ray Explorer (GRX) mission utilizing germanium strip-detectors. We propose a 3-year program to develop and test a germanium readout ASIC to TRL 5 and to integrate the ASIC readout onto a COSI detector allowing a TRL 6 demonstration for the following COSI balloon flight. Our group at NRL led a program, sponsored by another government agency, to produce and integrate a cross-strip silicon detector ASIC, designed and fabricated by Dr. De Geronimo at Brookhaven National Laboratory. The ASIC was designed to handle the large (>30 pF) capacitance of three 10 cm^2 detectors daisy-chained together. The front-end preamplifier, selectable inverter, shaping times, and gains make this ASIC compatible with a germanium cross-strip detector as well. We therefore have the opportunity and expertise to leverage the previous investment in the silicon ASIC for a new mission. A germanium strip detector ASIC will also require precise timing of the signals at

  13. A 1.2 Gb/s Data Transmission Unit in CMOS 0.18 μm technology for the ALICE Inner Tracking System front-end ASIC

    Science.gov (United States)

    Mazza, G.; Aglieri Rinella, G.; Benotto, F.; Corrales Morales, Y.; Kugathasan, T.; Lattuca, A.; Lupi, M.; Ravasenga, I.

    2017-02-01

    The upgrade of the ALICE Inner Tracking System is based on a Monolithic Active Pixel Sensor and ASIC designed in a CMOS 0.18 μ m process. In order to provide the required output bandwidth (1.2 Gb/s for the inner layers and 400 Mb/s for the outer ones) on a single high speed serial link, a custom Data Transmission Unit (DTU) has been developed in the same process. The DTU includes a clock multiplier PLL, a double data rate serializer and a pseudo-LVDS driver with pre-emphasis and is designed to be SEU tolerant.

  14. Radiation hardness on very front-end for SPD

    Energy Technology Data Exchange (ETDEWEB)

    Cano, Xavier [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, 08028 Barcelona (Spain)]. E-mail: xcano@ub.edu; Graciani, Ricardo [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Gascon, David [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Garrido, Lluis [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Bota, Sebastia [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, 08028 Barcelona (Spain); Herms, Atila [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, 08028 Barcelona (Spain); Comerma, Albert [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Riera, Jordi [Departament d' Electronica, Universitat Ramon Llull (Spain)

    2005-10-11

    The calorimeter front-end electronics of the LHCb experiment will be located in a region, which is not protected from radiation. Therefore, all the electronics must be qualified to stand some defined radiation levels. The procedure, measurements and results of an irradiation test for every component of the very front-end SPD detector, which is part of the LHCb calorimeter are presented here. All the tested components, except a custom made ASIC, are commercially available.

  15. Design of versatile ASIC and protocol tester for CBM readout system

    Science.gov (United States)

    Zabołotny, W. M.; Byszuk, A. P.; Emschermann, D.; Gumiński, M.; Juszczyk, B.; Kasiński, K.; Kasprowicz, G.; Lehnert, J.; Müller, W. F. J.; Poźniak, K.; Romaniuk, R.; Szczygieł, R.

    2017-02-01

    Silicon Tracking System (STS), Muon Chamber (MUCH) and Transition Radiation Detector (TRD) subdetectors in the Compressed Baryonic Matter (CBM) detector system at Facility for Antiproton and Ion Research (FAIR) use the same innovative protocol ensuring reliable synchronization of the communication link between the controller and the front-end ASIC, transmission of time-deterministic commands to the ASIC and efficient readout of data. The paper describes the FPGA-based tester platform which can be used both for the verification of the protocol implementation in a front-end ASIC at the design stage, and for testing of the produced ASICs. Due to its modularity, the platform can be easily adapted for different integrated circuits and readout systems.

  16. Integrated input protection against discharges for Micro Pattern Gas Detectors readout ASICs

    Science.gov (United States)

    Fiutowski, T.; Dąbrowski, W.; Koperny, S.; Wiącek, P.

    2017-02-01

    Immunity against possible random discharges inside active detector volume of MPGDs is one of the key aspects that should be addressed in the design of the front-end electronics. This issue becomes particularly critical for systems with high channel counts and high density readout employing the front-end electronics built as multichannel ASICs implemented in modern CMOS technologies, for which the breakdown voltages are in the range of a few Volts. The paper presents the design of various input protection structures integrated in the ASIC manufactured in a 350 nm CMOS process and test results using an electrical circuit to mimic discharges in the detectors.

  17. Chromatic X-Ray imaging with a fine pitch CdTe sensor coupled to a large area photon counting pixel ASIC

    CERN Document Server

    Bellazzini, R; Brez, A; Minuti, M; Pinchera, M; Mozzo, P

    2012-01-01

    An innovative X-ray imaging sensor with intrinsic digital characteristics is presented. It is based on Chromatic Photon Counting technology. The detector is able to count individually the incident X-ray photons and to separate them according to their energy (two 'color' images per exposure). The energy selection occurs in real time and at radiographic imaging speed (GHz global counting rate). Photon counting, color mode and a very high spatial resolution (more than 10 l.p./mm at MTF50) allow to obtain an optimal ratio between image quality and absorbed dose. The individual block of the imaging system is a two-side buttable semiconductor radiation detector made of a thin pixellated CdTe crystal (the sensor) coupled to a large area VLSI CMOS pixel ASIC. 1, 2, 4, 8 tile units have been built. The 8 tiles unit has 25cm x 2.5cm sensitive area. Results and images obtained from in depth testing of several configurations of the system are presented. The X-Ray imaging system is the technological platform of PIXIRAD Im...

  18. VMM - An ASIC for Micropattern Detectors

    CERN Document Server

    Iakovidis, Georgios; The ATLAS collaboration; De Geronimo, Gianluigi

    2015-01-01

    The VMM is a custom Application Specific Integrated Circuit (ASIC) that can be used in a va- riety of charge interpolated tracking detectors. It is designed to be used with the resistive Micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is designed at Brookhaven National Laboratory and fabricated in the 130 nm Global Foundries 8RF-DM process. The devices will be packaged in a Ball Grid Array with outline dimensions of 21 × 21 mm2 . It integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog- to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM2 is the second version of the VMM ASIC family fabricated in 2014. The design, tests and qualification of the VMM1, VMM2 and roadmap to VMM3 is described.

  19. Development and evaluation of an ultra-fast ASIC for future PET scanners using TOF-capable MPPC array detectors

    Energy Technology Data Exchange (ETDEWEB)

    Ambe, T., E-mail: hiro-a-be.n@akane.waseda.jp [Research Institute for Science and Engineering, Waseda University, 3-4-1, Okubo, Shinjuku, Tokyo (Japan); Ikeda, H. [ISAS/JAXA, 3-1-1, Yoshinodai, Chuo-ku, Sagamihara-shi, Kanagawa (Japan); Kataoka, J.; Matsuda, H.; Kato, T. [Research Institute for Science and Engineering, Waseda University, 3-4-1, Okubo, Shinjuku, Tokyo (Japan)

    2015-01-21

    We developed a front-end ASIC for future PET scanners with Time-Of-Flight (TOF) capability to be coupled with 4×4 Multi-Pixel Photon Counter (MPPC) arrays. The ASIC is designed based on the open-IP project proposed by JAXA and realized in TSMC 0.35 μm CMOS technology. The circuit comprises 16-channel, low impedance current conveyors for effectively acquiring fast MPPC signals. For precise measurement of the coincidence timing of 511-keV gamma rays, the leading-edge method was used to discriminate the signals. We first tested the time response of the ASIC by illuminating each channel of a MPPC array device 3×3 mm{sup 2} in size with a Pico-second Light Pulsar with a light emission peak of 655 nm and pulse duration of 54 ps (FWHM). We obtained 105 ps (FWHM) on average for each channel in time jitter measurements. Moreover, we compensated for the time lag of each channel with inner delay circuits and succeeded in suppressing about a 700-ps lag to only 15 ps. This paper reports TOF measurements using back-to-back 511-keV signals, and suggests that the ASIC can be a promising device for future TOF-PET scanners based on the MPPC array. - Highlights: • We developed a newly designed large-area monolithic MPPC array. • We obtained fine gain uniformity, and good energy and time resolutions when coupled to the LYSO scintillator. • We fabricated gamma-ray camera consisting of the MPPC array and the submillimeter pixelized LYSO and GGAG scintillators. • In the flood images, each crystal of scintillator matrices was clearly resolved. • Good energy resolutions for 662 keV gamma-rays for each LYSO and GGAG scintillator matrices were obtained.

  20. MDT-ASD, CMOS front-end for ATLAS MDT

    CERN Document Server

    Posch, C; Oliver, J

    2007-01-01

    This document serves as the main reference and user`s manual for the read-out chip of the Monitored Drift Tubes in the ATLAS Muon Spectrometer. The eight-channel front-end ASIC is referred to as MDT-ASD. The document contains the requirements and complete specifications, a detailed description of the design with characteristics of all sub-circuits and building blocks, a comprehensive section on functionality and performance test results, and a complete bibliography.

  1. Memory, microprocessor, and ASIC

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    System Timing. ROM/PROM/EPROM. SRAM. Embedded Memory. Flash Memories. Dynamic Random Access Memory. Low-Power Memory Circuits. Timing and Signal Integrity Analysis. Microprocessor Design Verification. Microprocessor Layout Method. Architecture. ASIC Design. Logic Synthesis for Field Programmable Gate Array (EPGA) Technology. Testability Concepts and DFT. ATPG and BIST. CAD Tools for BIST/DFT and Delay Faults.

  2. Status Report on the LOC ASIC

    CERN Document Server

    Ye, J

    2008-01-01

    Based on a commercially available 0.25 μm Silicon on Sapphire CMOS technology, we are developing the LOC ASIC for high speed serial data transmission in the front-end electronics systems of the ATLAS upgrade for the SLHC1. Evaluation of this technology for applications in the SLHC, based on a dedicated test chip, has been performed with irradiation tests in gamma (Co-60) and in 230 MeV proton beams. Test results indicate that this may be a candidate technology of ASIC developments for the SLHC. More thorough evaluation tests will be carried out under another R&D program supported through the Advanced Detector Research (ADR) from the Department of Energy. Characterization tests on the first prototype serializer, LOC1, have been carried out in lab. Based on the lessons learned from this chip, we propose a new architecture design of the second prototype, LOC2, aiming for a serial data rate in the range of 5 Gbps. Simulation on key components of LOC2 are being carried out and the results we have so far are p...

  3. ASPIC and CABAC: two ASICs to readout and pilot CCD

    Science.gov (United States)

    Antilogus, P.; Bailly, P.; Barrillon, P.; Dhellot, M.; El berni, A.; Jeglot, J.; Juramy-Gilles, C.; Lebbolo, H.; Martin, D.; Moniez, M.; Vallerand, P.

    2017-03-01

    For several years, a group of engineers and physicists from LAL and LPNHE have been working on the design of two front end ASICs dedicated to Charge Couple Devices (CCD). ASPIC (Analogue Signal Processing Integrated Circuit), designed in AMS CMOS 0.35 μm 5V technology, is meant to readout and process the analog signals of CCDs. CABAC (Clocks And Biases ASIC for CCDs), designed in AMS CMOS 0.35 μm 50V technology, produces the clocks and biases needed by the CCDs to work at their full potential. This paper presents the performances of the final versions of these two ASICs.

  4. A protocol for hit and control synchronous transfer for the front-end electronics at the CBM experiment

    Science.gov (United States)

    Kasinski, K.; Szczygiel, R.; Zabolotny, W.; Lehnert, J.; Schmidt, C. J.; Müller, W. F. J.

    2016-11-01

    The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.

  5. Performance of the front-end electronics of the ANTARES neutrino telescope

    NARCIS (Netherlands)

    Aguilar, J.A.; Kooijman, P.

    2010-01-01

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube sig

  6. Anode Front-End Electronics for the Cathode Strip Chambers of the CMS Endcap Muon Detector

    CERN Document Server

    Ferguson, Thomas; Vorobev, I; Bondar, Nikolai; Golyash, Alexander; Sedov, Vladislav

    2001-01-01

    The front-end electronics system for the anode signals of the CMS Endcap Muon cathode strip chambers has about 183000 channels. The purposes of the anode front-end electronics are to acquire precise muon timing information for bunch crossing number identification at the Level-1 muon trigger system and to provide a coarse radial position of the muon track. Each anode channel consists of an input protection network, amplifier, shaper, constant-fraction discriminator, and a programmable delay. The essential parts of the electronics include a 16-channel amplifier-shaper-discriminator ASIC CMP16 and a 16-channel ASIC D16G providing programmable time delay. The ASIC CMP16 was optimized for the large cathode chamber size (up to 3 x 2.5 m2) and for the large input capacitance (up to 200 pf). The ASIC combines low power consumption (30 mW/channel) with good time resolution (2 - 3 ns). The del ay ASIC D16G makes possible the alignment of signals with an accuracy of 2.2 ns. This note presents the anode front-end electro...

  7. Development of the read-out ASIC for muon chambers

    Science.gov (United States)

    Atkin, E.; Bulbakov, I.; Gusev, A.; Malankin, E.; Normanov, D.; Sagdiev, I.; Shumikhin, V.; Shumkin, O.; Ivanov, P.; Vinogradov, S.; Voronin, A.; Samsonov, V.; Ivanov, V.

    2016-02-01

    A front-end prototype ASIC for muon chambers is presented. ASIC was designed and prototyped in the CMOS UMC MMRF 180 nm process via Europractice. The chip includes 8 analog processing channels, each consisting of a preamplifier, two shapers (fast and slow), differential comparator and an area efficient 6 bit SAR ADC with 1.2 mW power consumption at 50 Msps. The chip also includes the threshold DAC and digital serializer. The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e- at 50 pF, power consumption of 10 mW per channel, 6 bit SAR ADC.

  8. Simultaneous disruption of mouse ASIC1a, ASIC2 and ASIC3 genes enhances cutaneous mechanosensitivity.

    Directory of Open Access Journals (Sweden)

    Sinyoung Kang

    Full Text Available Three observations have suggested that acid-sensing ion channels (ASICs might be mammalian cutaneous mechanoreceptors; they are structurally related to Caenorhabditis elegans mechanoreceptors, they are localized in specialized cutaneous mechanosensory structures, and mechanical displacement generates an ASIC-dependent depolarization in some neurons. However, previous studies of mice bearing a single disrupted ASIC gene showed only subtle or no alterations in cutaneous mechanosensitivity. Because functional redundancy of ASIC subunits might explain limited phenotypic alterations, we hypothesized that disrupting multiple ASIC genes would markedly impair cutaneous mechanosensation. We found the opposite. In behavioral studies, mice with simultaneous disruptions of ASIC1a, -2 and -3 genes (triple-knockouts, TKOs showed increased paw withdrawal frequencies when mechanically stimulated with von Frey filaments. Moreover, in single-fiber nerve recordings of cutaneous afferents, mechanical stimulation generated enhanced activity in A-mechanonociceptors of ASIC TKOs compared to wild-type mice. Responses of all other fiber types did not differ between the two genotypes. These data indicate that ASIC subunits influence cutaneous mechanosensitivity. However, it is unlikely that ASICs directly transduce mechanical stimuli. We speculate that physical and/or functional association of ASICs with other components of the mechanosensory transduction apparatus contributes to normal cutaneous mechanosensation.

  9. Performance of 2nd generation CALICE/EUDET ASICs

    Science.gov (United States)

    de La Taille, C.; CALICE Collaboration; EUDET Collaboration

    2011-04-01

    The paper reviews the performance of the three ASICs : HARDROC2, SPIROC2 and SKIROC2 developed to readout the ILC calorimeter prototypes. The chips integrate 36 to 64 channels of front-end, digitization and backend electronics in SiGe 0.35 μm technology. This second version was found mature enough to be produced in several hundreds to equip large scale technological prototypes and establish the feasibility of these highly granular "imaging" calorimeters as required for particle flow algorithms at the ILC. The low noise and low power sequential readout as well as power-pulsing operation at detector level and in magnetic field are proven.

  10. Development and experimental study of the readout ASIC for muon chambers of the CBM experiment

    Science.gov (United States)

    Atkin, E.; Ivanov, V.; Ivanov, P.; Khanzadeev, A.; Malankin, E.; Normanov, D.; Roshchin, E.; Samsonov, V.; Shumikhin, V.; Voronin, A.

    2016-01-01

    The measurement results of the front-end ASIC for the GEM detector read-out are presented. The MUCH ASIC v2 was designed and prototyped via Europractice by means of the 0.18 um CMOS MMRF process of UMC (Taiwan). The parameters of the analog channels, including the CSA, fast and slow shapers, discriminators, were measured. The channels provide a sufficient dynamic range of 100 fC, low power consumption of 10 mW per channel and ENC of 1550 el at a 50 pF detector capacitance.

  11. Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Khalid, Farah F.; Deptuch, Grzegorz; Shenai, Alpana; Yarema, Raymond J.; /Fermilab

    2010-11-01

    Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12 keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC{sup 2} shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using {mu}-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 {micro}m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab.

  12. Irradiation of the CLARO-CMOS chip, a fast ASIC for single-photon counting

    Science.gov (United States)

    Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Fiorini, M.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2015-07-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with low power consumption, built in AMS 0.35 μm CMOS technology. It is intended to be used as a front-end readout for the upgraded LHCb RICH detectors. In this environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade, the ASIC must withstand a total fluence of about 6×1012 1 MeV neq/cm2 and a total ionising dose of 400 krad. Long term stability of the electronics front-end is essential and the effects of radiation damage on the CLARO-CMOS performance must be carefully studied. This paper describes results of multi-step irradiation tests with protons up to the dose of ~8 Mrad, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  13. ENC Measurement for ASIC Preamp Board as a Detector Module for PET System

    Directory of Open Access Journals (Sweden)

    N. Nagara

    2016-08-01

    Full Text Available We developed a gamma ray detector with an LuAG:Pr scintillator and an avalanche photodiode as a detector for a positron emission tomography (PET system. Studies have been performed on the influences of gamma irradiation on application-specific integrated circuit (ASIC preamp boards used as a detector module. As a device used in nuclear environments for substantial durations, the ASIC has to have a lifetime long enough to ensure that there will be a negligible failure rate during this period. These front-end systems must meet the requirements for standard positron emission tomography (PET systems. Therefore, an equivalent noise charge (ENC experiment is needed to measure the front-end system's characteristics. This study showed that minimum ENC conditions can be achieved if a shorter shaping time could be applied.

  14. Irradiation of the CLARO-CMOS chip, a fast ASIC for single-photon counting

    Energy Technology Data Exchange (ETDEWEB)

    Andreotti, M.; Baldini, W.; Calabrese, R. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Carniti, P.; Cassina, L. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Cotta Ramusino, A. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Fiorini, M., E-mail: fiorini@fe.infn.it [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Giachero, A.; Gotti, C. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Luppi, E. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Maino, M. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Malaguti, R. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Pessina, G. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Tomassetti, L. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy)

    2015-07-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with low power consumption, built in AMS 0.35 μm CMOS technology. It is intended to be used as a front-end readout for the upgraded LHCb RICH detectors. In this environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade, the ASIC must withstand a total fluence of about 6×10{sup 12} 1 MeV n{sub eq}/cm{sup 2} and a total ionising dose of 400 krad. Long term stability of the electronics front-end is essential and the effects of radiation damage on the CLARO-CMOS performance must be carefully studied. This paper describes results of multi-step irradiation tests with protons up to the dose of ~8 Mrad, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  15. SPIDR, a general-purpose readout system for pixel ASICs

    Science.gov (United States)

    van der Heijden, B.; Visser, J.; van Beuzekom, M.; Boterenbrood, H.; Kulis, S.; Munneke, B.; Schreuder, F.

    2017-02-01

    The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a "soft core" CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four 10 Gigabit

  16. LHCb: Test Station for the LHCb Muon Front-End Electronic

    CERN Multimedia

    Polycarpo, E

    2005-01-01

    The LHCb Muon Group has developed the CMOS ASIC CARIOCA to readout its Multiwire Proportional Chambers (MWPC) and GEM detectors, using a rad-hard IBM 0.25um process. Each ASIC holds 8 identical current-mode ASDB channels with individual input thresholds. The Muon detector contains around 120000 physical channels, requiring production of 20000 front-end chips, roughly. CARIOCA has been developed to process MWPC cathode and anode signals and two different versions have been implemented to overcome the requirement of MWP and GEM chambers operation. The test station has been devised to accomplish bipolar tests and to measure characteristics of both CARIOCA versions.

  17. An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras

    Energy Technology Data Exchange (ETDEWEB)

    Bolotnikov, A. E., E-mail: bolotnik@bnl.gov; Ackley, K.; Camarda, G. S.; Cherches, C.; Cui, Y.; De Geronimo, G.; Fried, J.; Hossain, A.; Mahler, G.; Maritato, M.; Roy, U.; Salwen, C.; Vernon, E.; Yang, G.; James, R. B. [Brookhaven National Laboratory, Upton, New York 11793 (United States); Hodges, D. [University of Texas at El Paso, El Paso, Texas 79968 (United States); Lee, W. [Korea University, Seoul 136-855 (Korea, Republic of); Petryk, M. [SUNY Binghamton, Vestal, New York 13902 (United States)

    2015-07-15

    We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm{sup 3} detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays’ performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.

  18. An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras.

    Science.gov (United States)

    Bolotnikov, A E; Ackley, K; Camarda, G S; Cherches, C; Cui, Y; De Geronimo, G; Fried, J; Hodges, D; Hossain, A; Lee, W; Mahler, G; Maritato, M; Petryk, M; Roy, U; Salwen, C; Vernon, E; Yang, G; James, R B

    2015-07-01

    We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm(3) detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays' performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.

  19. The GBT-SCA, a radiation tolerant ASIC for detector control applications in SLHC experiments

    CERN Document Server

    Gabrielli, A; Kloukinas, K; Marchioro, A; Moreira, P; Ranieri, A; De Robertis, D

    2009-01-01

    This work describes the architecture of the GigaBit Transceiver – Slow Control Adapter (GBT–SCA) ASIC suitable for the control and monitoring applications of the embedded front-end electronics in the future SLHC experiments. The GBT–SCA is part the GBT chipset currently under development for the SLHC detector upgrades. It is designed for radiation tolerance and it will be fabricated in a commercial 130 nm CMOS technology. The paper discusses the GBT-SCA architecture, the data transfer protocol, the ASIC interfaces, and its integration with the GBT optical link. The GBT–SCA is one the components of the GBT system chipset. It is proposed for the future SLHC experiments and is designed to be configurable matching different front-end system requirements. The GBT-SCA is intended for the slow control and monitoring of the embedded front end electronics and implements a point-to-multi point connection between one GBT optical link ASIC and several front end ASICs. The GBT-SCA connects to a dedicated electrica...

  20. Mongoose ASIC microcontroller programming guide

    Science.gov (United States)

    Smith, Brian S.

    1993-01-01

    The 'Mongoose' ASIC microcontroller is a radiation-hard implementation of the R3000 microprocessor. This document describes the internals of the microcontroller in a level of detail necessary for someone implementing a software design.

  1. A Prototype PZT Matrix Transducer With Low-Power Integrated Receive ASIC for 3-D Transesophageal Echocardiography.

    Science.gov (United States)

    Chen, Chao; Raghunathan, Shreyas B; Yu, Zili; Shabanimotlagh, Maysam; Chen, Zhao; Chang, Zu-yao; Blaak, Sandra; Prins, Christian; Ponte, Jacco; Noothout, Emile; Vos, Hendrik J; Bosch, Johan G; Verweij, Martin D; de Jong, Nico; Pertijs, Michiel A P

    2016-01-01

    This paper presents the design, fabrication, and experimental evaluation of a prototype lead zirconium titanate (PZT) matrix transducer with an integrated receive ASIC, as a proof of concept for a miniature three-dimensional (3-D) transesophageal echocardiography (TEE) probe. It consists of an array of 9 ×12 piezoelectric elements mounted on the ASIC via an integration scheme that involves direct electrical connections between a bond-pad array on the ASIC and the transducer elements. The ASIC addresses the critical challenge of reducing cable count, and includes front-end amplifiers with adjustable gains and micro-beamformer circuits that locally process and combine echo signals received by the elements of each 3 ×3 subarray. Thus, an order-of-magnitude reduction in the number of receive channels is achieved. Dedicated circuit techniques are employed to meet the strict space and power constraints of TEE probes. The ASIC has been fabricated in a standard 0.18-μm CMOS process and consumes only 0.44 mW/channel. The prototype has been acoustically characterized in a water tank. The ASIC allows the array to be presteered across ±37° while achieving an overall dynamic range of 77 dB. Both the measured characteristics of the individual transducer elements and the performance of the ASIC are in good agreement with expectations, demonstrating the effectiveness of the proposed techniques.

  2. Development of front-end readout electronics for silicon strip detectors

    CERN Document Server

    Qian, Yi; Kong, Jie; Dong, Cheng-Fu; Ma, Xiao-Li; Li, Xiao-Gang

    2011-01-01

    A front-end readout electronics system has been developed for silicon strip detectors. The system uses an application specific integrated circuit (ASIC) ATHED to realize multi-channel E&T measurement. The slow control of ASIC chips is achieved by parallel port and the timing control signals of ASIC chips are provided by the CPLD. The data acquisition is implemented with a PXI-DAQ card. The system software has a user-friendly GUI which uses LabWindows/CVI in Windows XP operating system. Test results showed that the energy resolution is about 1.22 % for alphas at 5.48 MeV and the maximum channel crosstalk of system is 4.6%. The performance of the system is very reliable and suitable for nuclear physics experiments.

  3. ASIC-enabled High Resolution Optical Time Domain Reflectometer

    Science.gov (United States)

    Skendzic, Sandra

    Fiber optics has become the preferred technology in communication systems because of what it has to offer: high data transmission rates, immunity to electromagnetic interference, and lightweight, flexible cables. An optical time domain reflectometer (OTDR) provides a convenient method of locating and diagnosing faults (e.g. break in a fiber) along a fiber that can obstruct crucial optical pathways. Both the ability to resolve the precise location of the fault and distinguish between two discrete, closely spaced faults are figures of merit. This thesis presents an implementation of a high resolution OTDR through the use of a compact and programmable ASIC (application specific integrated circuit). The integration of many essential OTDR functions on a single chip is advantageous over existing commercial instruments because it enables small, lightweight packaging, and offers low power and cost efficiency. Furthermore, its compactness presents the option of placing multiple ASICs in parallel, which can conceivably ease the characterization of densely populated fiber optic networks. The OTDR ASIC consists of a tunable clock, pattern generator, precise timer, electrical receiver, and signal sampling circuit. During OTDR operation, the chip generates narrow electrical pulse, which can then be converted to optical format when coupled with an external laser diode driver. The ASIC also works with an external photodetector to measure the timing and amplitude of optical reflections in a fiber. It has a 1 cm sampling resolution, which allows for a 2 cm spatial resolution. While this OTDR ASIC has been previously demonstrated for multimode fiber fault diagnostics, this thesis focuses on extending its functionality to single mode fiber. To validate this novel approach to OTDR, this thesis is divided into five chapters: (1) introduction, (2) implementation, (3), performance of ASIC-based OTDR, (4) exploration in optical pre-amplification with a semiconductor optical amplifier, and

  4. KLauS: a low power Silicon Photomultiplier charge readout ASIC in 0.18 UMC CMOS

    Science.gov (United States)

    Briggl, K.; Chen, H.; Schimansky, D.; Shen, W.; Stankova, V.; Schultz-Coulon, H. C.

    2016-03-01

    We present the development of a low power Silicon Photomultiplier charge readout ASIC for an imaging calorimeter at a future linear collider. The analog front-end is designed to achieve sufficient signal-to-noise ratio for single pixel signals using low gain SiPMs, while allowing charge measurements over the full dynamic range of the sensors. The front-end consists of an input stage, two charge measurement branches and a fast comparator. A SAR ADC with a resolution of 10 bit digitizes the pulse height information. An additional pipelined SAR stage allows to increase the quantization resolution to 12 bit for calibration measurements.

  5. A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

    CERN Document Server

    Senkin, Sergey; The ATLAS collaboration

    2017-01-01

    We present a front-end readout system, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on 130 nm CMOS technology, FATALIC performs the full signal processing, including amplification, shaping and digitisation.

  6. On the detection performance of semi-insulating GaAs detectors coupled to multichannel ASIC DX64 for X-ray imaging applications

    Energy Technology Data Exchange (ETDEWEB)

    Zat' ko, Bohumir [Institute of Electrical Engineering, Slovak Academy of Sciences, Dubravska cesta 9, SK-841 04 Bratislava (Slovakia)], E-mail: elekbzat@savba.sk; Dubecky, Frantisek [Institute of Electrical Engineering, Slovak Academy of Sciences, Dubravska cesta 9, SK-841 04 Bratislava (Slovakia); Scepko, Pavol [T and N System, Ltd., Severna 5, SK-974 01 Banska Bystrica (Slovakia); Grybos, Pawel [Department of Measurement and Instrumentation, AGH University of Science and Technology, Al. Mickiewicza 30, PL-30 059 Krakow (Poland); Mudron, Jan [MTC, a. s., Kuzmanyho 11, SK-031 01 Liptovsky Mikulas (Slovakia); Maj, Piotr; Szczygiel, Robert [Department of Measurement and Instrumentation, AGH University of Science and Technology, Al. Mickiewicza 30, PL-30 059 Krakow (Poland); Frollo, Ivan [Institute of Measurement Science, Slovak Academy of Sciences, Dubravska cesta 9, SK-841 04 Bratislava (Slovakia)

    2008-06-11

    Detectors based on semi-insulating (SI) GaAs show high detection efficiency and satisfactory energy resolution for modern X-ray digital imaging applications. This work deals with the performance of SI GaAs-based detectors coupled by wire bonding to the input of multichannel readout chip DX64 (technology CMOS 0.35 {mu}m). Detectors have circular Ti/Pt/Au multilayer Schottky blocking contacts with different diameters (0.75, 0.50, 0.30 and 0.20 mm). First results of operation of the used readout system in the single-photon counting regime are given.

  7. A front-end stage with signal compression capability for XFEL detectors

    Science.gov (United States)

    Nasri, B.; Fiorini, C.; Grande, A.; Erdinger, F.; Fischer, P.; Porro, M.

    2015-01-01

    In this work, we present a front-end stage with signal compression capability to be used in detectors for the new European XFEL in Hamburg. This front-end is an alternative solution under study for the DEPFET Sensor with Signal Compression (DSSC) detection system for the European XFEL. The DEPFET sensor of the DSSC project has a high dynamic range and very good noise performance. The high gain for small collected charge and the compression for large signals will provide both desired features of single photon detection capability and wide dynamic range. However, manufacturing of the DEPFET sensor requires a sophisticated processing technology with a relatively long time fabrication process. Accordingly, an alternative solution, namely Day-0 solution, was introduced as an approach characterized not by the best performance of the DEPFET, but available in a shorter time to allow first beam tests and experiments. The alternative sensor is made of mini Silicon Drift Detector (mini-SDD) and the compression behavior is obtained from the front-end on the readout ASIC and not by the transistor integrated in the silicon sensor, as in the DEPFET. The first version of corresponding front-end of the Day-0 solution has been realized based on an input PMOSFET transistor placed on the readout chip. This simple front-end proved the working principle of the proposed compression technique and the desired noise performance. In this paper, an improved version of the Day-0 front-end is presented. In the new prototype, the current gain of the front-end stage has been increased by factor of 1.8, the total input capacitance (SDD+PMOSFET) has been reduced by factor of 2 with respect to the previous prototype and consequently the noise performance has been improved. Moreover, by introducing selectable extra branches in parallel with the main one, the compression behavior of the front-end can be tuned based on desired dynamic range.

  8. Rad-Hard Structured ASIC Body of Knowledge

    Science.gov (United States)

    Heidecker, Jason

    2013-01-01

    Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

  9. Front-End Electron Transfer Dissociation Coupled to a 21 Tesla FT-ICR Mass Spectrometer for Intact Protein Sequence Analysis

    Science.gov (United States)

    Weisbrod, Chad R.; Kaiser, Nathan K.; Syka, John E. P.; Early, Lee; Mullen, Christopher; Dunyach, Jean-Jacques; English, A. Michelle; Anderson, Lissa C.; Blakney, Greg T.; Shabanowitz, Jeffrey; Hendrickson, Christopher L.; Marshall, Alan G.; Hunt, Donald F.

    2017-09-01

    High resolution mass spectrometry is a key technology for in-depth protein characterization. High-field Fourier transform ion cyclotron resonance mass spectrometry (FT-ICR MS) enables high-level interrogation of intact proteins in the most detail to date. However, an appropriate complement of fragmentation technologies must be paired with FTMS to provide comprehensive sequence coverage, as well as characterization of sequence variants, and post-translational modifications. Here we describe the integration of front-end electron transfer dissociation (FETD) with a custom-built 21 tesla FT-ICR mass spectrometer, which yields unprecedented sequence coverage for proteins ranging from 2.8 to 29 kDa, without the need for extensive spectral averaging (e.g., 60% sequence coverage for apo-myoglobin with four averaged acquisitions). The system is equipped with a multipole storage device separate from the ETD reaction device, which allows accumulation of multiple ETD fragment ion fills. Consequently, an optimally large product ion population is accumulated prior to transfer to the ICR cell for mass analysis, which improves mass spectral signal-to-noise ratio, dynamic range, and scan rate. We find a linear relationship between protein molecular weight and minimum number of ETD reaction fills to achieve optimum sequence coverage, thereby enabling more efficient use of instrument data acquisition time. Finally, real-time scaling of the number of ETD reactions fills during method-based acquisition is shown, and the implications for LC-MS/MS top-down analysis are discussed. [Figure not available: see fulltext.

  10. Spectral response of the energy-binning Dosepix ASIC coupled to a 300 μm silicon sensor under high fluxes of synchrotron radiation

    Energy Technology Data Exchange (ETDEWEB)

    Fröjdh, E., E-mail: erik.frojdh@cern.ch [CERN, Geneva (Switzerland); Mid Sweden University, Sundsvall (Sweden); Bisello, F. [IBA Dosimetry GmbH, Schwarzenbruck (Germany); FAU University Erlangen-Nrnberg, Erlangen (Germany); Campbell, M. [CERN, Geneva (Switzerland); Damet, J. [CERN, Geneva (Switzerland); Institute of Radiation Physics, Lausanne University Hospital, Lausanne (Switzerland); Hamann, E.; Koenig, T. [ANKA Synchrotron Radiation Facility, KIT, Karlsruhe (Germany); Wong, W.S. [CERN, Geneva (Switzerland); Institute of Radiation Physics, Lausanne University Hospital, Lausanne (Switzerland); Zuber, M. [ANKA Synchrotron Radiation Facility, KIT, Karlsruhe (Germany)

    2015-12-21

    The Dosepix hybrid pixel detector was designed for dosimetry and radiation monitoring applications. It has three programmable modes of operation: photon counting mode, energy integration mode, and dosimetry mode. The dosimetry mode measures the energy of individual X-ray photons and automatically sorts events into pre-defined energy bins. The output is a histogram representing the measured X-ray energy spectrum, permitting a dose reconstruction that accounts for the attenuation of photons at each energy bin. This presents a potential radiation protection and dosimetry instrument in medical radiodiagnostic practices, including high flux systems such as computed tomography (CT). In this paper, we characterise the Dosepix chip by investigating the energy response and count rate capabilities when coupled to a 300 μm silicon sensor under high fluxes of monochromatic synchrotron radiation. Under nominal settings, the Dosepix detector can detect photons down to 3.5 keV, with an energy resolution of 16.5% FWHM for 8.5 keV photons and 8% FWHM for 40 keV photons. The chip can count up to 1.67 Mcps/mm{sup 2} of 40 keV photons whilst maintaining linear counting behaviour. This count rate range can be further increased by changing the programmable operating settings of the detector, making it suitable for a range of photon dosimetry applications.

  11. 8-channel prototype of SALT readout ASIC for Upstream Tracker in the upgraded LHCb experiment

    Science.gov (United States)

    Abellan Beteta, C.; Bugiel, S.; Dasgupta, R.; Firlej, M.; Fiutowski, T.; Idzik, M.; Kane, C.; Moron, J.; Swientek, K.; Wang, J.

    2017-02-01

    SALT is a new 128-channel readout ASIC for silicon strip detectors in the upgraded Upstream Tracker of the LHCb experiment. It will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial output data. SALT is designed in CMOS 130 nm process and uses a novel architecture comprising of an analogue front-end and an ultra-low power (SALT8), comprising all important functionalities was designed, fabricated and tested. A full 128-channel version was also submitted. The design and test results of the SALT8 prototype are presented showing its full functionality.

  12. Performance of Front-End Readout System for PHENIX RICH

    Energy Technology Data Exchange (ETDEWEB)

    Oyama, K.; Hamagaki, H.; Nishimura, S.; Shigaki, K.; Hayano, R.S.; Hibino, M.; Kametani, S.; Kikuchi, J.; Matsumoto, T.; Sakaguchi, T.; Ebisu, K.; Hara, H.; Tanaka, Y.; Ushiroda, T.; Moscone, C.G.; Wintenberg, A.L.; Young, G.R.

    1999-11-15

    A front-end electronics system has been developed for the Ring Imaging Cerenkov (RICH) detector of the PHENIX experiment at the Relativistic Heavy Ion Collider (RHIC), Brookhaven National Laboratory (BNL). A high speed custom back-plane with source synchronous bus architecture, a full custom analog ASIC, and board modules with FPGA's and CPLD's were developed for high performance real time data acquisition. The transfer rate of the back-lane has reached 640 MB/s with 128 bits data bus. Total transaction time is estimated to be less than 30 {micro}s per event. The design specifications and test results of the system are presented in this paper.

  13. Characterisation of the NA62 GigaTracker end of column readout ASIC

    CERN Document Server

    Noy, M; Perktold, L; Rinella, G A; Riedler, P; Morel, M; Kluge, A; Kaplon, J; Martin, E; Jarron, P

    2011-01-01

    The architecture and characterisation of the End Of Column demonstrator readout ASIC for the NA62 GigaTracker hybrid pixel detector is presented. This ASIC serves as a proof of principle for a pixel chip with 1800 pixels which must perform time stamping to better than 200 ps (RMS), provide 300 mu m pitch position information and operate with a dead-time of 1\\% or less for 800 MHz-1 GHz beam rate. The demonstrator ASIC comprises a full test column with 45 pixels alongside other test structures. The timewalk correction mechanism employed is measurement of the time-over-threshold, coupled with an off-detector look-up table. The time to digital converter is a delay locked loop with 32 contributing delay cells fed with a 320 MHz to yield a nominal bin size of 97 ps. Recently, P-in-N sensors have been bump-bonded to the ASIC and characterisation of these assemblies has begun.

  14. Testing of the front-end hybrid circuits for the CMS Tracker upgrade

    Science.gov (United States)

    Gadek, T.; Blanchot, G.; Honma, A.; Kovacs, M.; Raymond, M.; Rose, P.

    2017-01-01

    The upgrade of the CMS Tracker for the HL-LHC requires the design of new double-sensor, silicon detector modules, which implement Level 1 trigger functionality in the increased luminosity environment. These new modules will contain two different, high-density front-end hybrid circuits, equipped with flip-chip ASICs, auxiliary electronic components and mechanical structures. The hybrids require qualification tests before they are assembled into modules. Test methods are proposed together with the corresponding test hardware and software. They include functional tests and signal injection in a cold environment to find possible failure modes of the hybrids under real operating conditions.

  15. The Outer Tracker Detector of the HERA-B Experiment. Part II: Front-End Electronics

    OpenAIRE

    al., H. Albrecht et

    2004-01-01

    The HERA-B Outer Tracker is a large detector with 112674 drift chamber channels. It is exposed to a particle flux of up to 2x10^5/cm^2/s thus coping with conditions similar to those expected for the LHC experiments. The front-end readout system, based on the ASD-8 chip and a customized TDC chip, is designed to fulfil the requirements on low noise, high sensitivity, rate tolerance, and high integration density. The TDC system is based on an ASIC which digitizes the time in bins of about 0.5 ns...

  16. Testing of the Front-End Hybrid Circuits for the CMS Tracker Upgrade

    CERN Document Server

    Gadek, Tomasz; Honma, Alan; Kovacs, Mark Istvan; Raymond, David Mark; Rose, Pierre

    2016-01-01

    The upgrade of the CMS tracker for the HL-LHC requires the design of new double-sensor, silicon detector modules, which implement Level 1 trigger functionality in the increased luminosity environment. These new modules will contain two different, high density front-end hybrid circuits, equipped with flip-chip ASICs, auxiliary electronic components and mechanical structures. The hybrids require qualification tests before they are assembled into modules. Test methods are proposed together with the corresponding test hardware and software. They include functional tests and signal injection in a cold environment to find possible failure modes of the hybrids under real operating conditions.

  17. ERICA: an energy resolving photon counting readout ASIC for X-ray in-line cameras

    Science.gov (United States)

    Macias-Montero, J.-G.; Sarraj, M.; Chmeissani, M.; Moore, T.; Casanova, R.; Martinez, R.; Puigdengoles, C.; Prats, X.; Kolstein, M.

    2016-12-01

    We present ERICA (Energy Resolving Inline X-ray Camera) a photon-counting readout ASIC, with 6 energy bins. The ASIC is composed of a matrix of 8 × 20 pixels controlled by a global digital controller and biased with 7 independent digital to analog converters (DACs) and a band-gap current reference. The pixel analog front-end includes a charge sensitive amplifier with 16 mV/ke- gain and dynamic range of 45 ke-. ERICA has programmable pulse width, an adjustable constant current feedback resistor, a linear test pulse generator, and six discriminators with 6-bit local threshold adjustment. The pixel digital back-end includes the digital controller, 8 counters of 8-bit depth, half-full buffer flag for any of the 8 counters, a 74-bit shadow/shift register, a 74-bit configuration latch, and charge sharing compensation processing to perform the energy classification and counting operations of every detected photon in 1 μ s. The pixel size is 330 μm × 330 μm and its average consumption is 150 μW. Implemented in TSMC 0.25 μm CMOS process, the ASIC pixel's equivalent noise charge (ENC) is 90 e- RMS connected to a 1 mm thickness matching CdTe detector biased at -300 V with a total leakage current of 20 nA.

  18. A 130 nm ASIC prototype for the NA62 Gigatracker readout

    Energy Technology Data Exchange (ETDEWEB)

    Dellacasa, G., E-mail: gdellaca@to.infn.it [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); Garbolino, S. [Universita degli Studi di Torino, Dip. Fisica Sperimentale, via Giuria 1, 10125 Torino (Italy); Marchetto, F. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); Martoiu, S. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); CERN CH-1211, Geneve 23 (Switzerland); Mazza, G.; Rivetti, A.; Wheadon, R. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy)

    2011-09-11

    One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatracker. It consists of three hybrid silicon pixel stations, each one covering an area of 27 mmx60 mm. While the maximum pixel size is fairly large, 300{mu}mx300{mu}m the system has to sustain a very high particle rate, 1.5 MHz/mm{sup 2}, which corresponds to 800 MHz for each station. To obtain an efficient tracking with such a high rate the required track timing resolution is 150 ps (rms). Therefore the front-end ASIC should provide for each pixel a 200 ps time measurement capability, thus leading to the requirement of time walk compensation and very compact TDCs. Moreover, Single Event Upset protection has to be implemented in order to protect the digital circuitry. An ASIC prototype has been realized in CMOS 130 nm technology, containing three pixel columns. The chip performs the time walk compensation by a Constant Fraction Discriminator circuit, while the time measurement is performed by a Time to Amplitude Converter based TDC, both of them implemented on each pixel cell. The End of Column circuit containing only digital logic is responsible for the data readout from the pixel cell. The whole chip works with a system clock of 160 MHz and the digital logic is SEU protected by the use of Hamming codes. The detailed architecture of the ASIC prototype and test results are presented.

  19. Low power analog readout front-end electronics for time and energy measurements

    Energy Technology Data Exchange (ETDEWEB)

    Kleczek, R., E-mail: rafal.kleczek@agh.edu.pl; Grybos, P.; Szczygiel, R.

    2014-06-01

    We report on the design and measurements of an analog front-end readout electronics dedicated for silicon microstrip detectors with relatively large capacitance of the order of tens pF for time and energy measurements of incoming pulses. The front-end readout electronics is required to process input pulses with an average rate of 150 kHz/channel with low both power consumption and noise at the same time. In the presented solution the single channel is built of two different parallel processing paths: fast and slow. The fast path includes the fast CR–RC shaper with the peaking time t{sub p}=40 ns and is optimized to determine the input charge arrival time. The slow path, which consists of the slow CR–(RC){sup 2} shaper with the peaking time t{sub p}=80 ns, is dedicated for low noise accurate energy measurement. The analog front-end electronics was implemented in UMC 180 nm CMOS technology as a prototype ASIC AFE. The AFE chip contains 8 channels with the size of 58 μm×1150 μm each. It has low power dissipation P{sub diss}=3.1 mW per single channel. The article presents the details of the front-end architecture and the measurement results.

  20. FAZIA front-end electronics

    OpenAIRE

    Salomon F.; Edelbruck P.; Brulin G.; Boiano A.; Tortone G.; Ordine A.; Bini M.; Barlini S.; Valdré S.

    2015-01-01

    FAZIA is a multi-detector specifically designed to optimize ion identification in heavy-ion experiments. Its electronic is fully digital; it was designed in the laboratories of the collaboration. This paper presents the front-end part of this electronic.

  1. FAZIA front-end electronics

    Directory of Open Access Journals (Sweden)

    Salomon F.

    2015-01-01

    Full Text Available FAZIA is a multi-detector specifically designed to optimize ion identification in heavy-ion experiments. Its electronic is fully digital; it was designed in the laboratories of the collaboration. This paper presents the front-end part of this electronic.

  2. Driver ASICs for Advanced Deformable Mirrors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The program leverages on our extensive expertise in developing high-performance driver ASICs for deformable mirror systems and seeks to expand the capacities of the...

  3. Driver ASICs for Advanced Deformable Mirrors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The overall goal of the SBIR program is to develop a new Application Specified Integrated Circuit (ASIC) driver to be used in driver electronics of a deformable...

  4. Ionizing radiation effects on a 64-channel charge measurement ASIC designed in CMOS 0.35 μm technology

    Science.gov (United States)

    La Rosa, A.; Marchetto, F.; Pardo, J.; Donetti, M.; Attili, A.; Bourhaleb, F.; Cirio, R.; Garella, M. A.; Giordanengo, S.; Givehchi, N.; Iliescu, S.; Mazza, G.; Pecka, A.; Peroni, C.; Pittà, G.

    2008-08-01

    A 64-channel circuit Application Specific Integrated Circuit (ASIC) for charge measurement has been designed in CMOS 0.35 μm technology and characterized with electrical tests. The ASIC has been conceived to be used as a front-end for dosimetry and beam monitoring detector read-out. For that application, the circuitry is housed at a few centimeters from the irradiated area of the detectors and therefore radiation damages can affect the chip performances. The ASIC has been tested on an X-ray beam. In this paper, the results of the test and an estimate of the expected lifetime of the ASIC in a standard radio-therapeutical treatment environment are presented. An increase of the background current of 2 fA/Gy has been observed at low doses, whilst the gain changes by less than 3% when irradiated up to 15 kGy. Furthermore it has been assessed that, when used as an on-line beam monitor and the annealing effect has been taken into account, the background current increase is ˜440 fA/year.

  5. Ionizing radiation effects on a 64-channel charge measurement ASIC designed in CMOS 0.35 {mu}m technology

    Energy Technology Data Exchange (ETDEWEB)

    La Rosa, A. [INFN, Via P. Giuria 1, Torino 10125 (Italy); Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Torino 10125 (Italy)], E-mail: alessandro.larosa@cern.ch; Marchetto, F.; Pardo, J. [INFN, Via P. Giuria 1, Torino 10125 (Italy); Donetti, M. [INFN, Via P. Giuria 1, Torino 10125 (Italy); Fondazione CNAO, Via Caminadella 16, Milano 20123 (Italy); Attili, A. [INFN, Via P. Giuria 1, Torino 10125 (Italy); Bourhaleb, F. [Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Torino 10125 (Italy); Cirio, R. [INFN, Via P. Giuria 1, Torino 10125 (Italy); Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Torino 10125 (Italy); Garella, M.A.; Giordanengo, S. [INFN, Via P. Giuria 1, Torino 10125 (Italy); Givehchi, N. [INFN, Via P. Giuria 1, Torino 10125 (Italy); Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Torino 10125 (Italy); Iliescu, S.; Mazza, G. [INFN, Via P. Giuria 1, Torino 10125 (Italy); Pecka, A.; Peroni, C. [INFN, Via P. Giuria 1, Torino 10125 (Italy); Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Torino 10125 (Italy); Pitta, G. [Fondazione TERA, Via Puccini 11, Novara 28100 (Italy)

    2008-08-11

    A 64-channel circuit Application Specific Integrated Circuit (ASIC) for charge measurement has been designed in CMOS 0.35 {mu}m technology and characterized with electrical tests. The ASIC has been conceived to be used as a front-end for dosimetry and beam monitoring detector read-out. For that application, the circuitry is housed at a few centimeters from the irradiated area of the detectors and therefore radiation damages can affect the chip performances. The ASIC has been tested on an X-ray beam. In this paper, the results of the test and an estimate of the expected lifetime of the ASIC in a standard radio-therapeutical treatment environment are presented. An increase of the background current of 2 fA/Gy has been observed at low doses, whilst the gain changes by less than 3% when irradiated up to 15 kGy. Furthermore it has been assessed that, when used as an on-line beam monitor and the annealing effect has been taken into account, the background current increase is {approx}440 fA/year.

  6. Design and test of a 64-channel charge measurement ASIC developed in CMOS 0.35 μm technology

    Science.gov (United States)

    La Rosa, A.; Mazza, G.; Donetti, M.; Marchetto, F.; Luetto, L.; Attili, A.; Bourhaleb, F.; Cirio, R.; Garella, M. A.; Giordanengo, S.; Givehchi, N.; Iliescu, S.; Pardo, J.; Pecka, A.; Peroni, C.; Pittà, G.

    2007-12-01

    A 64-channel charge measurement (Application-Specific Integrated Circuit) ASIC has been designed and tested: it is intended to serve as a front-end electronic read-out for detectors to monitor and measure radiotherapeutical beams. The ASIC has been designed in a CMOS 0.35 μm technology with particular attention to the linearity over a wide input range and can accept currents of both polarities. The linearity is better than 1.5% for a dynamic range of the input current between 500 pA and 3 μA. For a charge resolution of 350 fC, the spread (r.m.s.) of the gain is less than 1%.

  7. Design and test of a 64-channel charge measurement ASIC developed in CMOS 0.35 {mu}m technology

    Energy Technology Data Exchange (ETDEWEB)

    La Rosa, A. [Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin 10125 (Italy); INFN, Via P. Giuria 1, Turin 10125 (Italy)], E-mail: larosa@to.infn.it; Mazza, G. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Donetti, M. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Fondazione CNAO, Via Caminadella 16, Milano 20123 (Italy); Marchetto, F. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Luetto, L. [Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin 10125 (Italy); Attili, A. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Bourhaleb, F. [Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin 10125 (Italy); Cirio, R.; Garella, M.A.; Giordanengo, S. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Givehchi, N. [Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin 10125 (Italy); INFN, Via P. Giuria 1, Turin 10125 (Italy); Iliescu, S.; Pardo, J. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Pecka, A.; Peroni, C. [Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin 10125 (Italy); INFN, Via P. Giuria 1, Turin 10125 (Italy); Pitta, G. [Fondazione TERA, Via Puccini 11, Novara 28100 (Italy)

    2007-12-21

    A 64-channel charge measurement (Application-Specific Integrated Circuit) ASIC has been designed and tested: it is intended to serve as a front-end electronic read-out for detectors to monitor and measure radiotherapeutical beams. The ASIC has been designed in a CMOS 0.35 {mu}m technology with particular attention to the linearity over a wide input range and can accept currents of both polarities. The linearity is better than 1.5% for a dynamic range of the input current between 500 pA and 3 {mu}A. For a charge resolution of 350 fC, the spread (r.m.s.) of the gain is less than 1%.

  8. Genetic mapping of ASIC4 and contrasting phenotype to ASIC1a in modulating innate fear and anxiety.

    Science.gov (United States)

    Lin, Shing-Hong; Chien, Ya-Chih; Chiang, Wei-Wei; Liu, Yan-Zhen; Lien, Cheng-Chang; Chen, Chih-Cheng

    2015-06-01

    Although ASIC4 is a member of the acid-sensing ion channel (ASIC) family, we have limited knowledge of its expression and physiological function in vivo. To trace the expression of this ion channel, we generated the ASIC4-knockout/CreERT(2)-knockin (Asic4(Cre) (ERT) (2)) mouse line. After tamoxifen induction in the Asic4(Cre) (ERT)(2)::CAG-STOP(floxed)-Td-tomato double transgenic mice, we mapped the expression of ASIC4 at the cellular level in the central nervous system (CNS). ASIC4 was expressed in many brain regions, including the olfactory bulb, cerebral cortex, striatum, hippocampus, amygdala, thalamus, hypothalamus, brain stem, cerebellum, spinal cord and pituitary gland. Colocalisation studies further revealed that ASIC4 was expressed mainly in three types of cells in the CNS: (i) calretinin (CR)-positive and/or vasoactive intestine peptide (VIP)-positive interneurons; (ii) neural/glial antigen 2 (NG2)-positive glia, also known as oligodendrocyte precursor cells; and (iii) cerebellar granule cells. To probe the possible role of ASIC4, we hypothesised that ASIC4 could modulate the membrane expression of ASIC1a and thus ASIC1a signaling in vivo. We conducted behavioral phenotyping of Asic4(Cre) (ERT)(2) mice by screening many of the known behavioral phenotypes found in Asic1a knockouts and found ASIC4 not involved in shock-evoked fear learning and memory, seizure termination or psychostimulant-induced locomotion/rewarding effects. In contrast, ASIC4 might play an important role in modulating the innate fear response to predator odor and anxious state because ASIC4-mutant mice showed increased freezing response to 2,4,5-trimethylthiazoline and elevated anxiety-like behavior in both the open-field and elevated-plus maze. ASIC4 may modulate fear and anxiety by counteracting ASIC1a activity in the brain.

  9. A 2D 4×4 Channel Readout ASIC for Pixelated CdTe Detectors for Medical Imaging Applications

    OpenAIRE

    Macias-Montero, Jose-Gabriel; Sarraj, Maher; Chmeissani, Mokhtar; Martínez, Ricardo; Puigdengoles, Carles

    2015-01-01

    We present a 16-channel readout integrated circuit (ROIC) with nanosecond-resolution time to digital converter (TDC) for pixelated Cadmium Telluride (CdTe) gamma-ray detectors. The 4 × 4 pixel array ROIC is the proof of concept of the 10 × 10 pixel array readout ASIC for positron-emission tomography (PET) scanner, positron-emission mammography (PEM) scanner, and Compton gamma camera. The electronics of each individual pixel integrates an analog front-end with switchable gain, an analog to dig...

  10. Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

    Science.gov (United States)

    Rivetti, Angelo

    2014-11-01

    In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8-10 bit resolution, 50-100 MHz conversion frequency and less than 1 mW power consumption are the today's standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130 nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC's and TDC's developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.

  11. Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

    Energy Technology Data Exchange (ETDEWEB)

    Rivetti, Angelo

    2014-11-21

    In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8–10 bit resolution, 50–100 MHz conversion frequency and less than 1 mW power consumption are the today's standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130 nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC's and TDC's developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.

  12. Multi Front-End Engineering

    Science.gov (United States)

    Botterweck, Goetz

    Multi Front-End Engineering (MFE) deals with the design of multiple consistent user interfaces (UI) for one application. One of the main challenges is the conflict between commonality (all front-ends access the same application core) and variability (multiple front-ends on different platforms). This can be overcome by extending techniques from model-driven user interface engineering.We present the MANTRA approach, where the common structure of all interfaces of an application is modelled in an abstract UI model (AUI) annotated with temporal constraints on interaction tasks. Based on these constraints we adapt the AUI, e.g., to tailor presentation units and dialogue structures for a particular platform. We use model transformations to derive concrete, platform-specific UI models (CUI) and implementation code. The presented approach generates working prototypes for three platforms (GUI, web, mobile) integrated with an application core via web service protocols. In addition to static evaluation, such prototypes facilitate early functional evaluations by practical use cases.

  13. Acid-sensing ion channels (ASICs: therapeutic targets for neurological diseases and their regulation

    Directory of Open Access Journals (Sweden)

    Hae-Jin Kweon

    2013-06-01

    Full Text Available Extracellular acidification occurs not only in pathologicalconditions such as inflammation and brain ischemia, but alsoin normal physiological conditions such as synaptic transmission.Acid-sensing ion channels (ASICs can detect a broadrange of physiological pH changes during pathological andsynaptic cellular activities. ASICs are voltage-independent,proton-gated cation channels widely expressed throughout thecentral and peripheral nervous system. Activation of ASICs isinvolved in pain perception, synaptic plasticity, learning andmemory, fear, ischemic neuronal injury, seizure termination,neuronal degeneration, and mechanosensation. Therefore,ASICs emerge as potential therapeutic targets for manipulatingpain and neurological diseases. The activity of these channelscan be regulated by many factors such as lactate, Zn2+, andPhe-Met-Arg-Phe amide (FMRFamide-like neuropeptides byinteracting with the channel’s large extracellular loop. ASICsare also modulated by G protein-coupled receptors such asCB1 cannabinoid receptors and 5-HT2. This review focuses onthe physiological roles of ASICs and the molecularmechanisms by which these channels are regulated. [BMBReports 2013; 46(6: 295-304

  14. XAMPS Detectors Readout ASIC for LCLS

    Energy Technology Data Exchange (ETDEWEB)

    Dragone, A; /SLAC; Pratte, J.F.; Rehak, P.; /Brookhaven; Carini, G.A.; /BNL, NSLS; Herbst, R.; /SLAC; O' Connor, P.; /Brookhaven; Siddons, D.P.; /BNL, NSLS

    2008-12-18

    An ASIC for the readout of signals from X-ray Active Matrix Pixel Sensor (XAMPS) detectors to be used at the Linac Coherent Light Source (LCLS) is presented. The X-ray Pump Probe (XPP) instrument, for which the ASIC has been designed, requires a large input dynamic range on the order of 104 photons at 8 keV with a resolution of half a photon FWHM. Due to the size of the pixel and the length of the readout line, large input capacitance is expected, leading to stringent requirement on the noise optimization. Furthermore, the large number of pixels needed for a good position resolution and the fixed LCLS beam period impose limitations on the time available for the single pixel readout. Considering the periodic nature of the LCLS beam, the ASIC developed for this application is a time-variant system providing low-noise charge integration, filtering and correlated double sampling. In order to cope with the large input dynamic range a charge pump scheme implementing a zero-balance measurement method has been introduced. It provides an on chip 3-bit coarse digital conversion of the integrated charge. The residual charge is sampled using correlated double sampling into analog memory and measured with the required resolution. The first 64 channel prototype of the ASIC has been fabricated in TSMC CMOS 0.25 {micro}m technology. In this paper, the ASIC architecture and performances are presented.

  15. Optical Link ASICs for the LHC Upgrade

    CERN Document Server

    Gan, K K; Kass, R D; Moore, J R; Smith, D S

    2009-01-01

    We have designed three ASICs for possible applications in the optical links of a new layer of pixel detector in the ATLAS experiment for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for the VCSEL, a receiver/decoder to decode the signal received at the PIN diode to extract the data and clock, and a clock multiplier to produce a higher frequency clock to serialize the data for transmission. These ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated ASICs and the submission has been mostly successful. We irradiated the ASICs with 24 GeV/c protons at CERN to a dosage of 70 Mrad. We observed no significant degradation except the driver circuit in the VCSEL driver fabricated using the thick oxide process in order to provide sufficient voltage to drive a VCSEL. The degradation is due to a large threshold shifts in the PMOS transistors used.

  16. Front-end electronics and data acquisition system for imaging atmospheric Cherenkov telescopes

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Y.T., E-mail: chenytao@ynu.edu.cn [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Yunnan University, 650091 Kunming (China); La Taille, C. de [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Suomijärvi, T. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Cao, Z. [Institute of High Energy Physics, 100049 Beijing (China); Deligny, O. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Dulucq, F. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Ge, M.M. [Yunnan University, 650091 Kunming (China); Lhenry-Yvon, I. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Martin-Chassard, G. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Nguyen Trung, T.; Wanlin, E. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Xiao, G.; Yin, L.Q. [Institute of High Energy Physics, 100049 Beijing (China); Yun Ky, B. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Zhang, L. [Yunnan University, 650091 Kunming (China); Zhang, H.Y. [Tsinghua University, 100084 Beijing (China); Zhang, S.S.; Zhu, Z. [Institute of High Energy Physics, 100049 Beijing (China)

    2015-09-21

    In this paper, a front-end electronics based on an application-specific integrated circuit (ASIC) is presented for the future imaging atmospheric Cherenkov telescopes (IACTs). To achieve this purpose, a 16-channel ASIC chip, PARISROC 2 (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is used in the analog signal processing and digitization. The digitized results are sent to the server by a user-defined User Datagram Protocol/Internet Protocol (UDP/IP) hardcore engine through Ethernet that is managed by a FPGA. A prototype electronics fulfilling the requirements of the Wide Field of View Cherenkov Telescope Array (WFCTA) of the Large High Altitude Air Shower Observatory (LHAASO) project has been designed, fabricated and tested to prove the concept of the design. A detailed description of the development with the results of the test measurements are presented. By using a new input structure and a new configuration of the ASIC, the dynamic range of the circuit is extended. A highly precise-time calibrating algorithm is also proposed, verified and optimized for the mass production. The test results suggest that the proposed electronics design fulfills the general specification of the future IACTs.

  17. SIDECAR ASIC firmware for astronomy applications

    Science.gov (United States)

    Chen, Jing; Loose, Markus; Ricardo, Raphael; Beletic, James; Farris, Mark; Xu, Min; Wong, Andre; Cabelli, Craig

    2014-07-01

    The SIDECAR ASIC is a fully integrated system-on-a-chip focal plane array controller that offers low power and low noise, small size and low weight. It has been widely used to operate different image sensors for ground-based and flightbased astronomy applications. A key mechanism to operating analog detectors is the SIDECAR ASIC's high level of programmability. This paper gives an overview of the SIDECAR ASIC architecture, including its optimized microcontroller featuring a customized instruction set. It describes the firmware components, including timing generation, biasing, commanding, housekeeping and synchronization of multiple detectors. The firmware development tools including compiler and supporting development environment and hardware setup are presented. The firmware capability for ground-based HxRG applications and for flight-based applications like the James Webb Space Telescope (JWST), the repair of the Advanced Camera for Surveys (ACS), and others are also discussed.

  18. Frontend electronics for high-precision single photo-electron timing using FPGA-TDCs

    Energy Technology Data Exchange (ETDEWEB)

    Cardinali, M., E-mail: cardinal@kph.uni-mainz.de [Institut für Kernphysik, Johannes Gutenberg-University Mainz, Mainz (Germany); Helmholtz Institut Mainz, Mainz (Germany); Dzyhgadlo, R.; Gerhardt, A.; Götzen, K.; Hohler, R.; Kalicy, G.; Kumawat, H.; Lehmann, D.; Lewandowski, B.; Patsyuk, M.; Peters, K.; Schepers, G.; Schmitt, L.; Schwarz, C.; Schwiening, J.; Traxler, M.; Ugur, C.; Zühlsdorf, M. [GSI Helmholtzzentrum für Schwerionenforschung GmbH, Darmstadt (Germany); Dodokhov, V.Kh. [Joint Institute for Nuclear Research, Dubna (Russian Federation); Britting, A. [Friedrich Alexander-University of Erlangen-Nuremberg, Erlangen (Germany); and others

    2014-12-01

    The next generation of high-luminosity experiments requires excellent particle identification detectors which calls for Imaging Cherenkov counters with fast electronics to cope with the expected hit rates. A Barrel DIRC will be used in the central region of the Target Spectrometer of the planned PANDA experiment at FAIR. A single photo-electron timing resolution of better than 100 ps is required by the Barrel DIRC to disentangle the complicated patterns created on the image plane. R and D studies have been performed to provide a design based on the TRB3 readout using FPGA-TDCs with a precision better than 20 ps RMS and custom frontend electronics with high-bandwidth pre-amplifiers and fast discriminators. The discriminators also provide time-over-threshold information thus enabling walk corrections to improve the timing resolution. Two types of frontend electronics cards optimised for reading out 64-channel PHOTONIS Planacon MCP-PMTs were tested: one based on the NINO ASIC and the other, called PADIWA, on FPGA discriminators. Promising results were obtained in a full characterisation using a fast laser setup and in a test experiment at MAMI, Mainz, with a small scale DIRC prototype. - Highlights: • Frontend electronics for Cherenkov detectors have been developed. • FPGA-TDCs have been used for high precision timing. • Time over threshold has been utilised for walk correction. • Single photo-electron timing resolution less than 100 ps has been achieved.

  19. Update on the high speed serializer ASIC development for ATLAS Liquid Argon calorimeter upgrade

    CERN Document Server

    Liu, T; The ATLAS collaboration

    2011-01-01

    We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in a 200 MeV proton beam. The test results indicate that the first prototype meets the design goals. The second prototype, a double-lane, 8 Gbps per lane serializer is under development. The post-layout simulation indicates that 8 Gbps is achievable. In this paper we present the design and the test results of the first prototype and the design and status of the second prototype.

  20. A high speed serializer ASIC for ATLAS Liquid Argon calorimeter upgrade

    CERN Document Server

    Liu, T; The ATLAS collaboration

    2014-01-01

    We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in 200 MeV proton beam. The test results indicate that the first prototype meets the design goals. The second prototype, a double-lane, 8 Gbps per lane serializer is under development. The post layout simulation indicates that 8 Gbps is achievable. In this paper we present the design and the test results of the first prototype and the design and status of the second prototype.

  1. Design Methodology: ASICs with complex in-pixel processing for Pixel Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Fahim, Farah [Fermilab

    2014-10-31

    The development of Application Specific Integrated Circuits (ASIC) for pixel detectors with complex in-pixel processing using Computer Aided Design (CAD) tools that are, themselves, mainly developed for the design of conventional digital circuits requires a specialized approach. Mixed signal pixels often require parasitically aware detailed analog front-ends and extremely compact digital back-ends with more than 1000 transistors in small areas below 100μm x 100μm. These pixels are tiled to create large arrays, which have the same clock distribution and data readout speed constraints as in, for example, micro-processors. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout.

  2. Dedicated front-end and readout electronics developments for real time 3D directional detection of dark matter with MIMAC

    CERN Document Server

    Bourrion, O; Grignon, C; Richer, J P; Guillaudin, O; Mayet, F; Billard, J; Santos, D

    2011-01-01

    A complete dedicated electronics, from front-end to back-end, was developed to instrument a MIMAC prototype. A front end ASIC able to monitor 64 strips of pixels and to provide their individual "Time Over Threshold" information has been designed. An associated acquisition electronics and a real time track reconstruction software have been developed to monitor a 512 channel prototype. This auto-triggered electronic uses embedded processing to reduce the data transfer to its useful part only, i.e. decoded coordinates of hit tracks and corresponding energy measurements. The electronic designs, acquisition software and the results obtained are presented.

  3. Single Front-End MIMO Architecture with Parasitic Antenna Elements

    Science.gov (United States)

    Yoshida, Mitsuteru; Sakaguchi, Kei; Araki, Kiyomichi

    In recent years, wireless communication technology has been studied intensively. In particular, MIMO which employs several transmit and receive antennas is a key technology for enhancing spectral efficiency. However, conventional MIMO architectures require some transceiver circuits for the sake of transmitting and receiving separate signals, which incurs the cost of one RF front-end per antenna. In addition to that, MIMO systems are assumed to be used in low spatial correlation environment between antennas. Since a short distance between each antenna causes high spatial correlation and coupling effect, it is difficult to miniaturize wireless terminals for mobile use. This paper shows a novel architecture which enables mobile terminals to be miniaturized and to work with a single RF front-end by means of adaptive analog beam-forming with parasitic antenna elements and antenna switching for spatial multiplexing. Furthermore, statistical analysis of the proposed architecture is also discussed in this paper.

  4. Trends in mixed signal ASIC design:

    OpenAIRE

    Trontelj, Janez

    1994-01-01

    Članek obravnava pregled nekaterih smernic razvoja v načrtovanju vezij ASIC, ki so pogojena z napredkom tehnologije, z novimi zahtevami za integracijo in znovimi načrtovalskimi prijemi. Podani so nekateri zgledi, ki prikazujejo nakazane smernice.

  5. A 130 nm ASIC prototype for the NA62 Gigatracker readout

    CERN Document Server

    Dellacasa, G; Wheadon, R; Mazza, G; Rivetti, A; Marchetto, F; Garbolino, S

    2011-01-01

    One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatracker. It consists of three hybrid silicon pixel stations, each one covering an area of 27 mm x 60 mm. While the maximum pixel size is fairly large, 300 mu m x 300 mu m the system has to sustain a very high particle rate, 1.5 MHz/mm(2), which corresponds to 800 MHz for each station. To obtain an efficient tracking with such a high rate the required track timing resolution is 150 ps (rms). Therefore the front-end ASIC should provide for each pixel a 200 Ps time measurement capability, thus leading to the requirement of time walk compensation and very compact TDCs. Moreover, Single Event Upset protection has to be implemented in order to protect the digital circuitry. An ASIC prototype has been realized in CMOS 130 nm technology, containing three pixel columns. The chip performs the time walk compensation by a Constant Fraction Discriminator circuit, while the time measurement is performed by a Time to Amplitude Co...

  6. Development of an ASIC for Si/CdTe detectors in a radioactive substance visualizing system

    Science.gov (United States)

    Harayama, Atsushi; Takeda, Shin`ichiro; Sato, Goro; Ikeda, Hirokazu; Watanabe, Shin; Takahashi, Tadayuki

    2014-11-01

    We report on the recent development of a 64-channel analog front-end ASIC for a new gamma-ray imaging system designed to visualize radioactive substances. The imaging system employs a novel Compton camera which consists of silicon (Si) and cadmium telluride (CdTe) detectors. The ASIC is intended for the readout of pixel/pad detectors utilizing Si/CdTe as detector materials, and covers a dynamic range up to 1.4 MeV. The readout chip consists of 64 identical signal channels and was implemented with X-FAB 0.35 μm CMOS technology. Each channel contains a charge-sensitive amplifier, a pole-zero cancellation circuit, a low-pass filter, a comparator, and a sample-hold circuit, along with a Wilkinson-type A-to-D converter. We observed an equivalent noise charge of 500 e- and a noise slope of 5 e-/pF (r.m.s.) with a power consumption of 2.1 mW per channel. The chip works well when connected to Schottky CdTe diodes, and delivers spectra with good energy resolution, such as 12 keV (FWHM) at 662 keV and 24 keV (FWHM) at 1.33 MeV.

  7. Development of an ASIC for Si/CdTe detectors in a radioactive substance visualizing system

    Energy Technology Data Exchange (ETDEWEB)

    Harayama, Atsushi, E-mail: harayama@astro.isas.jaxa.jp [Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, Sagamihara, Kanagawa 229-8510 (Japan); Takeda, Shin' ichiro [Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, Sagamihara, Kanagawa 229-8510 (Japan); Sato, Goro [RIKEN Nishina Center, 2-1 Hirosawa, Wako, Saitama 351-0198 (Japan); Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, Sagamihara, Kanagawa 229-8510 (Japan); Ikeda, Hirokazu; Watanabe, Shin; Takahashi, Tadayuki [Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, Sagamihara, Kanagawa 229-8510 (Japan)

    2014-11-21

    We report on the recent development of a 64-channel analog front-end ASIC for a new gamma-ray imaging system designed to visualize radioactive substances. The imaging system employs a novel Compton camera which consists of silicon (Si) and cadmium telluride (CdTe) detectors. The ASIC is intended for the readout of pixel/pad detectors utilizing Si/CdTe as detector materials, and covers a dynamic range up to 1.4 MeV. The readout chip consists of 64 identical signal channels and was implemented with X-FAB 0.35μm CMOS technology. Each channel contains a charge-sensitive amplifier, a pole-zero cancellation circuit, a low-pass filter, a comparator, and a sample-hold circuit, along with a Wilkinson-type A-to-D converter. We observed an equivalent noise charge of ∼500 e{sup −} and a noise slope of ∼5 e{sup −}/pF (r.m.s.) with a power consumption of 2.1 mW per channel. The chip works well when connected to Schottky CdTe diodes, and delivers spectra with good energy resolution, such as ∼12 keV (FWHM) at 662 keV and ∼24 keV (FWHM) at 1.33 MeV.

  8. Development of arrays of Silicon Drift Detectors and readout ASIC for the SIDDHARTA experiment

    Science.gov (United States)

    Quaglia, R.; Schembari, F.; Bellotti, G.; Butt, A. D.; Fiorini, C.; Bombelli, L.; Giacomini, G.; Ficorella, F.; Piemonte, C.; Zorzi, N.

    2016-07-01

    This work deals with the development of new Silicon Drift Detectors (SDDs) and readout electronics for the upgrade of the SIDDHARTA experiment. The detector is based on a SDDs array organized in a 4×2 format with each SDD square shaped with 64 mm2 (8×8) active area. The total active area of the array is therefore 32×16 mm2 while the total area of the detector (including 1 mm border dead area) is 34 × 18mm2. The SIDDHARTA apparatus requires 48 of these modules that are designed and manufactured by Fondazione Bruno Kessler (FBK). The readout electronics is composed by CMOS preamplifiers (CUBEs) and by the new SFERA (SDDs Front-End Readout ASIC) circuit. SFERA is a 16-channels readout ASIC designed in a 0.35 μm CMOS technology, which features in each single readout channel a high order shaping amplifier (9th order Semi-Gaussian complex-conjugate poles) and a high efficiency pile-up rejection logic. The outputs of the channels are connected to an analog multiplexer for the external analog to digital conversion. An on-chip 12-bit SAR ADC is also included. Preliminary measurements of the detectors in the single SDD format are reported. Also measurements of low X-ray energies are reported in order to prove the possible extension to the soft X-ray range.

  9. PACIFIC: the readout ASIC for the SciFi Tracker of the upgraded LHCb detector

    Science.gov (United States)

    Mazorra, J.; Chanal, H.; Comerma, A.; Gascón, D.; Gómez, S.; Han, X.; Pillet, N.; Vandaele, R.

    2016-02-01

    The LHCb detector will be upgraded during the Long Shutdown 2 (LS2) of the LHC in order to cope with higher instantaneous luminosities and will switch to a 40 MHz readout rate using a trigger-less software based system. All front-end electronics will be replaced and several sub-detectors must be redesigned to cope with the higher detector occupancy and radiation damage. The current tracking detectors downstream of the LHCb dipole magnet will be replaced by the Scintillating Fibre (SciFi) Tracker. The SciFi Tracker will use scintillating fibres read out by Silicon Photomultipliers (SiPMs). State-of-the-art multi-channel SiPM arrays are being developed and a custom ASIC, called the low-Power ASIC for the sCIntillating FIbres traCker (PACIFIC), will be used to digitise the signals from the SiPMs. This article presents an overview of the R&D for the PACIFIC. It is a 64-channel ASIC implemented in 130 nm CMOS technology, aiming at a radiation tolerant design with a power consumption below 10 mW per channel. It interfaces directly with the SiPM anode through a current mode input, and provides a configurable non-linear 2-bit per channel digital output. The SiPM signal is acquired by a current conveyor and processed with a fast shaper and a gated integrator. The digitization is performed using a three threshold non-linear flash ADC operating at 40 MHz. Simulation and test results show the PACIFIC chip prototypes functioning well.

  10. Development of the analog ASIC for multi-channel readout X-ray CCD camera

    CERN Document Server

    Nakajima, Hiroshi; Idehara, Toshihiro; Anabuki, Naohisa; Tsunemi, Hiroshi; Doty, John P; Ikeda, Hirokazu; Katayama, Haruyoshi; Kitamura, Hisashi; Uchihori, Yukio; 10.1016/j.nima.2010.12.174

    2011-01-01

    We report on the performance of an analog application-specific integrated circuit (ASIC) developed aiming for the front-end electronics of the X-ray CCDcamera system onboard the next X-ray astronomical satellite, ASTRO-H. It has four identical channels that simultaneously process the CCD signals. Distinctive capability of analog-to-digital conversion enables us to construct a CCD camera body that outputs only digital signals. As the result of the front-end electronics test, it works properly with low input noise of =<30 uV at the pixel rate below 100 kHz. The power consumption is sufficiently low of about 150 mW/chip. The input signal range of 720 mV covers the effective energy range of the typical X-ray photon counting CCD (up to 20 keV). The integrated non-linearity is 0.2% that is similar as those of the conventional CCDs in orbit. We also performed a radiation tolerance test against the total ionizing dose (TID) effect and the single event effect. The irradiation test using 60Co and proton beam showed ...

  11. The PASTA chip. A free-running readout ASIC for silicon strip sensors in PANDA

    Energy Technology Data Exchange (ETDEWEB)

    Goerres, Andre; Stockmanns, Tobias; Ritman, James [Forschungszentrum Juelich GmbH, Juelich (Germany); Rivetti, Angelo [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2015-07-01

    The PANDA experiment is a multi purpose detector, investigating hadron physics in the charm quark mass regime. It is one of the main experiments at the future FAIR accelerator facility, using anti pp annihilations from a 1.5-15 GeV/c anti-proton beam. Because of the broad physics spectrum and the similarity of event and background signals, PANDA does an event selection based on the complete raw data of the detector. The innermost of PANDA's sub-systems is the Micro Vertex Detector (MVD), consisting of silicon pixel and strip sensors. The latter will be read out by a specialized, free-running readout front-end called PANDA Strip ASIC (PASTA). It has to face a high event rate of up to 40 kHz/ch in an radiation-intense environment. To fulfill the MVD's requirements, it has to give accurate timing information to incoming events (<10 ns) and determine the collected charge with an 8-bit precision. All this has to be done with a very low power design (<4 mW/ch) on a small footprint with less than 21 mm{sup 2} and 60 μm input pitch for 64 channels per chip. Therefore, a simple, time-based readout approach with two independent thresholds is chosen. In this talk, the conceptual design of the full front-end and some aspects of the digital part are presented.

  12. The PASTA chip - A free-running readout ASIC for silicon strip sensors in PANDA

    Energy Technology Data Exchange (ETDEWEB)

    Goerres, Andre; Stockmanns, Tobias; Ritman, James [Institut fuer Kernphysik, Forschungszentrum Juelich, Juelich (Germany); Rivetti, Angelo [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2014-07-01

    The PANDA experiment is a multi purpose detector, investigating hadron physics in the charm quark mass regime. It is one of the main experiments at the future FAIR accelerator facility, using pp annihilations from a 1.5-15 GeV/c anti-proton beam. Because of the broad physics spectrum and the similarity of event and background signals, PANDA does not rely on a hardware-level trigger decision. The innermost of PANDA's sub-systems is the Micro Vertex Detector (MVD), consisting of silicon pixel and strip sensors. The latter will be read out by a specialized, free-running readout front-end called PANDA Strip ASIC (PASTA). It has to face a high event rate of up to 40 kHz/ch in an radiation-intense environment. To fulfill the MVD's requirements, it has to give accurate timing information to incoming events (<10 ns) and determine the collected charge with an 8-bit precision. The design has to meet cooling and placing restrictions, leading to a very low power consumption (<4 mW/ch) and limited dimensions. Therefore, a simple, time-based readout approach is chosen. In this talk, the conceptual design of the front-end is presented.

  13. An ASIC for fast single photon counting in the LHCb RICH upgrade

    Science.gov (United States)

    Gotti, C.

    2017-03-01

    The LHCb experiment will be upgraded during the second LHC long shutdown (years 2019–2020) to operate at higher luminosity. The new triggerless architecture of LHCb requires data from the entire detector to be read out at 40 MHz. The basic element of the front-end electronics of the Ring Imaging Cherenkov (RICH) detector upgrade is the "Elementary Cell" (EC), a readout system for multianode photomultiplier tubes designed to minimise parasitic capacitance at the anodes, to obtain a fast readout with low noise and low crosstalk. At the heart of the EC is the CLARO, an 8 channel, low power and radiation hard front-end ASIC designed in 0.35 μm CMOS technology. Each channel compares the charge signals from the photomultiplier anodes with a programmable threshold, and gives a digital pulse at the output when the threshold is exceeded. Baseline recovery occurs in less than 25 ns for typical single photon signals. In the LHCb RICH upgrade environment, the chips will have to withstand radiation up to a total ionising dose of 2 kGy (200 krad) and neutron and hadron fluences up to 03×112 cm‑2 and following irradiation, the chips have been shown to tolerate such doses with a margin of safety.

  14. Double-differential recording and AGC using microcontrolled variable gain ASIC.

    Science.gov (United States)

    Rieger, Robert; Deng, Shin-Liang

    2013-01-01

    Low-power wearable recording of biopotentials requires acquisition front-ends with high common-mode rejection for interference suppression and adjustable gain to provide an optimum signal range to a cascading analogue-to-digital stage. A microcontroller operated double-differential (DD) recording setup and automatic gain control circuit (AGC) are discussed which reject common-mode interference and provide tunable gain, thus compensating for imbalance and variation in electrode interface impedance. Custom-designed variable gain amplifiers (ASIC) are used as part of the recording setup. The circuit gain and balance is set by the timing of microcontroller generated clock signals. Measured results are presented which confirm that improved common-mode rejection is achieved compared to a single differential amplifier in the presence of input network imbalance. Practical measured examples further validate gain control suitable for biopotential recording and power-line rejection for wearable ECG and EMG recording. The prototype front-end consumes 318 μW including amplifiers and microcontroller.

  15. Abnormal Cardiac Autonomic Regulation in Mice Lacking ASIC3

    Directory of Open Access Journals (Sweden)

    Ching-Feng Cheng

    2014-01-01

    Full Text Available Integration of sympathetic and parasympathetic outflow is essential in maintaining normal cardiac autonomic function. Recent studies demonstrate that acid-sensing ion channel 3 (ASIC3 is a sensitive acid sensor for cardiac ischemia and prolonged mild acidification can open ASIC3 and evoke a sustained inward current that fires action potentials in cardiac sensory neurons. However, the physiological role of ASIC3 in cardiac autonomic regulation is not known. In this study, we elucidate the role of ASIC3 in cardiac autonomic function using Asic3−/− mice. Asic3−/− mice showed normal baseline heart rate and lower blood pressure as compared with their wild-type littermates. Heart rate variability analyses revealed imbalanced autonomic regulation, with decreased sympathetic function. Furthermore, Asic3−/− mice demonstrated a blunted response to isoproterenol-induced cardiac tachycardia and prolonged duration to recover to baseline heart rate. Moreover, quantitative RT-PCR analysis of gene expression in sensory ganglia and heart revealed that no gene compensation for muscarinic acetylcholines receptors and beta-adrenalin receptors were found in Asic3−/− mice. In summary, we unraveled an important role of ASIC3 in regulating cardiac autonomic function, whereby loss of ASIC3 alters the normal physiological response to ischemic stimuli, which reveals new implications for therapy in autonomic nervous system-related cardiovascular diseases.

  16. Characterisation of the NA62 GigaTracker end of column readout ASIC

    Science.gov (United States)

    Noy, M.; Aglieri Rinella, G.; Fiorini, M.; Jarron, P.; Kaplon, J.; Kluge, A.; Martin, E.; Morel, M.; Perktold, L.; Riedler, P.

    2011-01-01

    The architecture and characterisation of the End Of Column demonstrator readout ASIC for the NA62 GigaTracker hybrid pixel detector is presented. This ASIC serves as a proof of principle for a pixel chip with 1800 pixels which must perform time stamping to better than 200 ps (RMS), provide 300 μm pitch position information and operate with a dead-time of 1% or less for 800 MHz-1 GHz beam rate. The demonstrator ASIC comprises a full test column with 45 pixels alongside other test structures. The timewalk correction mechanism employed is measurement of the time-over-threshold, coupled with an off-detector look-up table. The time to digital converter is a delay locked loop with 32 contributing delay cells fed with a 320 MHz to yield a nominal bin size of 97 ps. Recently, P-in-N sensors have been bump-bonded to the ASIC and characterisation of these assemblies has begun.

  17. A Readout ASIC for CZT Detectors

    CERN Document Server

    Jones, L

    2008-01-01

    Spectrometers that can identify the energy of gamma radiation and determine the source isotope have until recently used low temperature semiconductors. These require cooling which makes their portability difficult. The material Cadmium Zinc Telluride (CZT) is now available which operates at room temperature and can be used to measure the energy of gamma radiation. In a compton camera configuration the direction of the radiation can also be determined. A read-out ASIC has been developed for such a system and features 100 channels of electronics, each with a charge amplifier, CR-RC shaper, and peak-hold. A 12 bit ADC converts the data which is sparsified before being read out. The energy, signal rise time, and timestamp of any hit channel is read out together with the data from all of its neighbours. The ASIC has a selectable lower dynamic range which could be used for lower energy interactions.

  18. KLauS: an ASIC for silicon photomultiplier readout and its application in a setup for production testing of scintillating tiles

    CERN Document Server

    Briggl, K; Hagdorn, R; Harion, T; Schultz-Coulon, H.C; Shen, W

    2014-01-01

    signals from silicon photomultipliers. Developed as an analog front-end for future calorimeters with high granularity as pursued by the AHCAL concept in the CALICE collaboration, the ASIC is designed to measure the charge signal of the sensors in a large dynamic range and with low electronic noise contributions. In order to tune the operation voltage of each sensor individually, an 8-bit DAC to tune the voltage at the input terminal within a range of 2V is implemented. Using an integrated fast comparator with low jitter, the time information can be measured with subnanosecond resolution. The low power consumption of the ASIC can be further decreased using power gating techniques. Future versions of KLauS are under development and will incorporate an ADC with a resolution of up to 12-bits and blocks for digital data transmission. The chip is used in a setup for mass testing and characterization of scintillator tiles for the AHCAL ...

  19. A 65 nm pixel readout ASIC with quick transverse momentum discrimination capabilities for the CMS Tracker at HL-LHC

    Science.gov (United States)

    Ceresa, D.; Kaplon, J.; Francisco, R.; Caratelli, A.; Kloukinas, K.; Marchioro, A.

    2016-01-01

    A readout ASIC for the hybrid pixel detector with the capability of performing quick recognition of particles with high transverse momentum has been designed for the requirements of the CMS Outer Tracker at the High Luminosity LHC . The particle momentum dicrimination capability represents the main challenge for this design together with the low power requirement: the constraint of low mass for the new tracker dictates a total power budget of less than 100 mW/cm2. The choice of a 65 nm CMOS technology has made it possible to satisfy this power requirement despite the fairly large amount of logic necessary to perform the momentum discrimination and the continuous operation at 40 MHz. Several techniques for low power have been used to implement this logic that performs cluster reduction, position offset correction and coordinate encoding. A prototype chip including a large part of the final functionality and the full front-end has been realized and comprises a matrix of 16 by 3 rectangular pixels of 100 μm × 1446 μm, providing 7.65 mm2 of segmented active area. Measurements of the analog front-end characteristics closely match the simulations and confirm the consumption of < 30 μA per pixel. Front-end characterization and irradiation results up to 150 MRad are also reported.

  20. Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors

    Science.gov (United States)

    Bo, Gan; Tingcun, Wei; Wu, Gao; Yongcai, Hu

    2016-06-01

    In this paper, we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit (ASIC) dedicated to CdZnTe detectors for a hard X-ray imager in space applications. The readout channel is comprised of a charge sensitive amplifier, a CR-RC shaping amplifier, an analog output buffer, a fast shaper, and a discriminator. An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 × 2.2 mm2. The input energy range is from 5 to 350 keV. For this 8-channel prototype ASIC, the measured electrical characteristics are as follows: the overall gain of the readout channel is 210 V/pC, the linearity error is less than 2%, the crosstalk is less than 0.36%, The equivalent noise charge of a typical channel is 52.9 e- at zero farad plus 8.2 e- per picofarad, and the power consumption is less than 2.4 mW/channel. Through the measurement together with a CdZnTe detector, the energy resolution is 5.9% at the 59.5-keV line under the irradiation of the radioactive source 241Am. The radiation effect experiments show that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad(Si). Project supported by the National Key Scientific Instrument and Equipment Development Project (No. 2011YQ040082), the National Natural Science Foundation of China (Nos. 11475136, 11575144, 61176094), and the Shaanxi Natural Science Foundation of China (No. 2015JM1016).

  1. Optimizing emergency department front-end operations.

    Science.gov (United States)

    Wiler, Jennifer L; Gentle, Christopher; Halfpenny, James M; Heins, Alan; Mehrotra, Abhi; Mikhail, Michael G; Fite, Diana

    2010-02-01

    As administrators evaluate potential approaches to improve cost, quality, and throughput efficiencies in the emergency department (ED), "front-end" operations become an important area of focus. Interventions such as immediate bedding, bedside registration, advanced triage (triage-based care) protocols, physician/practitioner at triage, dedicated "fast track" service line, tracking systems and whiteboards, wireless communication devices, kiosk self check-in, and personal health record technology ("smart cards") have been offered as potential solutions to streamline the front-end processing of ED patients, which becomes crucial during periods of full capacity, crowding, and surges. Although each of these operational improvement strategies has been described in the lay literature, various reports exist in the academic literature about their effect on front-end operations. In this report, we present a review of the current body of academic literature, with the goal of identifying select high-impact front-end operational improvement solutions.

  2. Charge-Sensitive Front-End Electronics with Operational Amplifiers for CdZnTe Detectors

    CERN Document Server

    Födisch, P; Lange, B; Kirschke, T; Enghardt, W; Kaever, P

    2016-01-01

    Cadmium zinc telluride (CdZnTe, "CZT") radiation detectors are announced to be a game-changing detector technology. However, state-of-the-art detector systems require high-performance readout electronics as well. Even though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, our demands on a high dynamic range for energy measurement and a high throughput are not served by any commercially available circuit. Consequently, we had to develop the analog front-end electronics with operational amplifiers for an 8x8 pixelated CZT detector. For this purpose, we model an electrical equivalent circuit of the CZT detector with the associated charge-sensitive amplifier (CSA). Therefore, we present the mathematical equations for a detailed network analysis. Additionally, we enhance the design with numerical values for various features such as ballistic deficit, charge-to-voltage gain, rise time, noise level and verify the performance with synthetic detector signals. With this benchm...

  3. Performance of the front-end electronics of the ANTARES neutrino telescope

    Science.gov (United States)

    Aguilar, J. A.; Al Samarai, I.; Albert, A.; Anghinolfi, M.; Anton, G.; Anvar, S.; Ardid, M.; Assis Jesus, A. C.; Astraatmadja, T.; Aubert, J.-J.; Auer, R.; Baret, B.; Basa, S.; Bazzotti, M.; Bertin, V.; Biagi, S.; Bigongiari, C.; Bou-Cabo, M.; Bouwhuis, M. C.; Brown, A.; Brunner, J.; Busto, J.; Camarena, F.; Capone, A.; Caponetto, L.; Cârloganu, C.; Carminati, G.; Carr, J.; Castorina, E.; Cavasinni, V.; Cecchini, S.; Chaleil, Th.; Charvis; Chiarusi, T.; Chon Sen, N.; Circella, M.; Costantini, H.; Cottini, N.; Coyle, P.; Curtil, C.; de Bonis, G.; de Botton, N.; Dekeyser, I.; Delagnes, E.; Deschamps, A.; Distefano, C.; Donzaud, C.; Dornic, D.; Drouhin, D.; Druillole, F.; Eberl, T.; Emanuele, U.; Ernenwein, J.-P.; Escoffier, S.; Falchini, E.; Fehr, F.; Feinstein, F.; Flaminio, V.; Fopma, J.; Fratini, K.; Fritsch, U.; Fuda, J.-L.; Gay, P.; Giacomelli, G.; Gómez-González, J. P.; Graf, K.; Guillard, G.; Halladjian, G.; Hallewell, G.; Hoffmann, C.; van Haren, H.; Heijboer, A. J.; Hello, Y.; Hernández-Rey, J. J.; Herold, B.; Hößl, J.; de Jong, M.; Kalantar-Nayestanaki, N.; Kalekin, O.; Kappes, A.; Katz, U.; Kooijman, P.; Kopper, C.; Kouchner, A.; Kretschmer, W.; Lachartre, D.; Lafoux, H.; Lahmann, R.; Lamare, P.; Lambard, G.; Larosa, G.; Laschinsky, H.; Le Provost, H.; Le van Suu, A.; Lefèvre, D.; Legou, T.; Lelaizant, G.; Lim, G.; Lo Presti, D.; Loehner, H.; Loucatos, S.; Lucarelli, F.; Mangano, S.; Marcelin, M.; Margiotta, A.; Martinez-Mora, J. A.; Mazure, A.; Monmarthe, E.; Montaruli, T.; Morganti, M.; Moscoso, L.; Motz, H.; Naumann, C.; Neff, M.; Olivetto, Ch.; Ostasch, R.; Palioselitis, D.; Păvăla, G. E.; Payre, P.; Petrovic, J.; Piattelli, P.; Picot-Clemente, N.; Picq, C.; Pineau, J.-P.; Poinsignon, J.; Popa, V.; Pradier, T.; Presani, E.; Racca, C.; Radu, A.; Reed, C.; Réthoré, F.; Riccobene, G.; Richardt, C.; Rujoiu, M.; Russo, G. V.; Salesa, F.; Sapienza, P.; Schöck, F.; Schuller, J. P.; Shanidze, R.; Simeone, F.; Spurio, M.; Steijger, J. J. M.; Stolarczyk, Th.; Tamburini, C.; Tasca, L.; Toscano, S.; Vallage, B.; van Elewyck, V.; Vannoni, G.; Vecchi, M.; Vernin, P.; Wijnker, G.; de Wolf, E.; Yepes, H.; Zaborov, D.; Zornoza, J. D.; Zúñiga, J.; ANTARES Collaboration

    2010-10-01

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube signals, measure their arrival time, amplitude and shape as well as perform monitoring and calibration tasks. The ARS chip processes the analogue signals from the optical modules and converts information into digital data. All the information is transmitted to shore through further multiplexing electronics and an optical link. This paper describes the performance of the ARS chip; results from the functionality and characterization tests in the laboratory are summarized and the long-term performance in the apparatus is illustrated.

  4. HDI flexible front-end hybrid prototype for the PS module of the CMS tracker upgrade

    Science.gov (United States)

    Kovacs, M.; Blanchot, G.; Gadek, T.; Honma, A.; Koliatos, A.

    2017-02-01

    The CMS tracker upgrade for the HL-LHC relies on different module types, depending on the position of the respective module. They are built with high-density interconnection flexible circuits that are wire bonded to silicon strip and pixel-strip sensors. The Front-End hybrids will contain several flip-chip bonded readout ASICs that are still under development. Mock-up prototypes are used to qualify the advanced flexible circuit technology and the parameters of the hybrids. This paper presents the Pixel-Strip (PS) mock-up hybrid in terms of testing, interconnection, fold-over, thermal properties and layout feasibility. Plans for circuit testing at operating temperature (-30o) are also presented.

  5. Developments for the upgrade of the CMS HCAL front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Baden, D [Univ. of Maryland, College Park, MD 20742 (United States); Frahm, E; Mans, J [Univ. of Minnesota, Minneapolis, MN 55455 (United States); Freeman, J; Grassi, T; Los, S; Shaw, T; Whitmore, J; Zimmerman, T [FERMILAB, Batavia, IL 60510 (United States); Tully, C, E-mail: tullio.grassi@cern.c [Princeton University, Princeton NJ 08544 (United States)

    2010-11-15

    We present a scheme to upgrade the CMS HCAL front-end electronics in 2015-16. The HCAL upgrade is required to handle a major luminosity increase of LHC which is expected for 2017. This paper focuses on the requirements for the new electronics and on the proposed solutions. The requirements include increased channel count, additional timing capabilities, and additional redundancy in a harsh environment which is constrained by the existing system. The proposed solutions span from chip level to system level. They include the development of a new ADC ASIC, the evaluation and use of circuits from other developments, evaluation of commercial FPGAs, better thermal design and improvements in the overall architecture.

  6. Onboard calibration circuit for the DAMPE BGO calorimeter front-end electronics

    Science.gov (United States)

    Zhang, De-Liang; Feng, Chang-Qing; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Shen, Zhong-Tao; Jiang, Di; Gao, Shan-Shan; Zhang, Yun-Long; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

    2016-05-01

    DAMPE (DArk Matter Particle Explorer) is a scientific satellite which is mainly aimed at indirectly searching for dark matter in space. One critical sub-detector of the DAMPE payload is the BGO (bismuth germanium oxide) calorimeter, which contains 1848 PMT (photomultiplier tube) dynodes and 16 FEE (Front-End Electronics) boards. VA160 and VATA160, two 32-channel low power ASICs (Application Specific Integrated Circuits), are adopted as the key components on the FEEs to perform charge measurement for the PMT signals. In order to monitor the parameter drift which may be caused by temperature variation, aging, or other environmental factors, an onboard calibration circuit is designed for the VA160 and VATA160 ASICs. It is mainly composed of a 12-bit DAC (Digital to Analog Converter), an operational amplifier and an analog switch. Test results showed that a dynamic range of 0-30 pC with a precision of 5 fC (Root Meam Square, RMS) was achieved, which covers the VA160’s input range. It can be used to compensate for the temperature drift and test the trigger function of the FEEs. The calibration circuit has been implemented for the front-end electronics of the BGO Calorimeter and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite was launched at the end of 2015 and the calibration circuit will operate periodically in space. Supported by Strategic Priority Research Program on Space Science of Chinese Academy of Sciences (XDA04040202-4), and National Basic Research Program (973 Program) of China (2010CB833002) and National Natural Science Foundation of China (11273070)

  7. Configurable Radiation Hardened High Speed Isolated Interface ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — NVE Corporation will design and build an innovative, low cost, flexible, configurable, radiation hardened, galvanically isolated, interface ASIC chip set that will...

  8. Imaging X-ray detector front-end with high dynamic range: IDeF-X HD

    Energy Technology Data Exchange (ETDEWEB)

    Gevin, O.; Lemaire, O.; Lugiez, F. [CEA, Irfu, Service d' Electronique, de Detecteurs et d' Informatique, Bat. 141, F-91191 Gif-sur-Yvette (France); Michalowska, A., E-mail: alicja.michalowska@cea.fr [CEA, Irfu, Service d' Electronique, de Detecteurs et d' Informatique, Bat. 141, F-91191 Gif-sur-Yvette (France); Baron, P. [CEA, Irfu, Service d' Electronique, de Detecteurs et d' Informatique, Bat. 141, F-91191 Gif-sur-Yvette (France); Limousin, O. [CEA, Irfu, Service d' Astrophysique, Bat. 709 Orme des Merisiers, F-91191 Gif-sur-Yvette (France); Delagnes, E. [CEA, Irfu, Service d' Electronique, de Detecteurs et d' Informatique, Bat. 141, F-91191 Gif-sur-Yvette (France)

    2012-12-11

    Presented circuit, IDeF-X HD (Imaging Detector Front-end) is a member of the IDeF-X ASICs family for space applications. It has been optimized for a half millimeter pitch CdTe or CdZnTe pixelated detector arranged in 16 Multiplication-Sign 16 array. It is aimed to operate in the hard X-ray range from few keV up to 250 keV or more. The ASIC has been realized in AMS 0.35 {mu}m CMOS process. The IDeF-X HD is a 32 channel analog front-end with self-triggering capability. The architecture of the analog channel includes a chain of charge sensitive amplifier with continuous reset system and non-stationary noise suppressor, adjustable gain stage, pole-zero cancellation stage, adjustable shaping time low pass filter, baseline holder and peak detector with discriminator. The power consumption of the IDeF-X HD is 800 {mu}W per channel. With the in-channel variable gain stage the nominal 250 keV dynamic range of the ASIC can be extended up to 1 MeV anticipating future applications using thick sensors. Measuring the noise performance without a detector at the input with minimized leakage current (programmable) at the input, we achieved ENC of 33 electrons rms at 10.7 {mu}s peak time. Measurements with CdTe detector show good energy resolution FWHM of 1.1 keV at 60 keV and 4.3 keV at 662 keV with detection threshold below 4 keV. In addition, an absolute temperature sensor has been integrated with resolution of 1.5 Degree-Sign C.

  9. Imaging X-ray detector front-end with high dynamic range: IDeF-X HD

    Science.gov (United States)

    Gevin, O.; Lemaire, O.; Lugiez, F.; Michalowska, A.; Baron, P.; Limousin, O.; Delagnes, E.

    2012-12-01

    Presented circuit, IDeF-X HD (Imaging Detector Front-end) is a member of the IDeF-X ASICs family for space applications. It has been optimized for a half millimeter pitch CdTe or CdZnTe pixelated detector arranged in 16×16 array. It is aimed to operate in the hard X-ray range from few keV up to 250 keV or more. The ASIC has been realized in AMS 0.35 μm CMOS process. The IDeF-X HD is a 32 channel analog front-end with self-triggering capability. The architecture of the analog channel includes a chain of charge sensitive amplifier with continuous reset system and non-stationary noise suppressor, adjustable gain stage, pole-zero cancellation stage, adjustable shaping time low pass filter, baseline holder and peak detector with discriminator. The power consumption of the IDeF-X HD is 800 μW per channel. With the in-channel variable gain stage the nominal 250 keV dynamic range of the ASIC can be extended up to 1 MeV anticipating future applications using thick sensors. Measuring the noise performance without a detector at the input with minimized leakage current (programmable) at the input, we achieved ENC of 33 electrons rms at 10.7 μs peak time. Measurements with CdTe detector show good energy resolution FWHM of 1.1 keV at 60 keV and 4.3 keV at 662 keV with detection threshold below 4 keV. In addition, an absolute temperature sensor has been integrated with resolution of 1.5 °C.

  10. Introduction to the Highlights of the 26th ASIC Conference.

    Science.gov (United States)

    Nehlig, Astrid

    2017-09-10

    The 26th ASIC Conference that was held in 2016 in Kunming, China has been marking the 50th anniversary of the creation of ASIC. The meeting in China was well attended by over 400 participants from all over the world and allowed fruitful exchanges among participants from all horizons of coffee science.

  11. Development of a dedicated front-end electronics for straw tube trackers in the bar PANDA experiment

    Science.gov (United States)

    Przyborowski, D.; Fiutowski, T.; Idzik, M.; Kajetanowicz, M.; Korcyl, G.; Salabura, P.; Smyrski, J.; Strzempek, P.; Swientek, K.; Terlecki, P.; Tokarz, J.

    2016-08-01

    The design and tests of front-end electronics for straw tube trackers in the bar PANDA experiment at FAIR are presented. The challenges for the front-end electronics, comprising operation at high counting rate up to 1 MHz per straw tube, are discussed and the proposed architecture comprising a switched gain charge sensitive preamplifier (CSP), a pole-zero cancellation circuit (PZC), a second order variable peaking time shaper, a trimming ion tail cancellation circuit, and a baseline holder (BLH), is described. The front-end provides an analogue output and a discriminator with LVDS differential driver for the Time-of-Arrival (ToA) and Time-over-Threshold (ToT) measurements. A prototype readout ASIC featuring four channels was fabricated in 0.35 μm CMOS technology consuming 15.5 mW (analog part) and 12 mW (LVDS) per channel. The results of measurements of peaking time (25-67 ns), gain, noise (ENC 800-2500 el. for various gains), time walk and jitter are presented as well as the first results obtained with prototype straw tubes connected.

  12. Expression and functions of ASIC1 in the zebrafish retina.

    Science.gov (United States)

    Liu, Sha; Wang, Mei-Xia; Mao, Cheng-Jie; Cheng, Xiao-Yu; Wang, Chen-Tao; Huang, Jian; Zhong, Zhao-Min; Hu, Wei-Dong; Wang, Fen; Hu, Li-Fang; Wang, Han; Liu, Chun-Feng

    2014-12-12

    It has been demonstrated that acid sensing ionic channels (ASICs) are present in the central and peripheral nervous system of mammals, including the retina. However, it remains unclear whether the zebrafish retina also expresses ASICs. In the present study, the expression and distribution of zasic1 were examined in the retina of zebrafish. Both zasic1 mRNA and protein expressions were detected in the adult zebrafish retina. A wide distribution of ASIC1 in zebrafish retina was confirmed using whole mount in situ hybridization and immunohistochemistry study. Acidosis-induced currents in the isolated retinal ganglion cells (RGCs) were also recorded using whole cell patch clamping. Moreover, blockade of ASICs channel significantly reduced the locomotion of larval zebrafish in response to light exposure. In sum, our data demonstrate the presence of ASIC1 and its possible functional relevance in the retina of zebrafish.

  13. Front-end conceptual platform modeling

    DEFF Research Database (Denmark)

    Guðlaugsson, Tómas Vignir; Ravn, Poul Martin; Mortensen, Niels Henrik

    2014-01-01

    Platform thinking has been the subject of investigation and deployment in many projects in both academia and industry. Most contributions involve the restructuring of product programs, and only a few support front-end development of a new platform in parallel with technology development....... This contribution deals with the development of product platforms in front-end projects and introduces a modeling tool: the Conceptual Product Platform model. State of the art within platform modeling forms the base of a modeling formalism for a Conceptual Product Platform model. The modeling formalism is explored...... through an example and applied in a case in which the Conceptual Product Platform model has supported the front-end development of a platform for an electro-active polymer technology. The case describes the contents of the model and how its application supported the development work in the project...

  14. Small Microprocessor for ASIC or FPGA Implementation

    Science.gov (United States)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  15. MuTRiG: a mixed signal Silicon Photomultiplier readout ASIC with high timing resolution and gigabit data link

    Science.gov (United States)

    Chen, H.; Briggl, K.; Eckert, P.; Harion, T.; Munwes, Y.; Shen, W.; Stankova, V.; Schultz-Coulon, H. C.

    2017-01-01

    MuTRiG is a mixed signal Silicon Photomultiplier readout ASIC designed in UMC 180 nm CMOS technology for precise timing and high event rate applications in high energy physics experiments and medical imaging. It is dedicated to the readout of the scintillating fiber detector and the scintillating tile detector of the Mu3e experiment. The MuTRiG chip extends the excellent timing performance of the STiCv3 chip with a fast digital readout for high rate applications. The high timing performance of the fully differential SiPM readout channels and 50 ps time binning TDCs are complemented by an upgraded digital readout logic and a 1.28 Gbps LVDS serial data link. The design of the chip and the characterization results of the analog front-end, TDC and the LVDS data link are presented.

  16. Pixel readout ASIC for an APD based 2D X-ray hybrid pixel detector with sub-nanosecond resolution

    Energy Technology Data Exchange (ETDEWEB)

    Thil, Ch., E-mail: christophe.thil@ziti.uni-heidelberg.d [Heidelberg University, Institute of Computer Engineering, B6, 26, 68161 Mannheim (Germany); Baron, A.Q.R. [RIKEN SPring-8 Center, 1-1-1 Kouto, Sayo-cho, Sayo-gun, Hyogo 679-5148 (Japan); Fajardo, P. [ESRF, Polygone Scientifique Louis Neel, 6, rue Jules Horowitz, 38000 Grenoble (France); Fischer, P. [Heidelberg University, Institute of Computer Engineering, B6, 26, 68161 Mannheim (Germany); Graafsma, H. [DESY, Notkestrasse 85, 22607 Hamburg (Germany); Rueffer, R. [ESRF, Polygone Scientifique Louis Neel, 6, rue Jules Horowitz, 38000 Grenoble (France)

    2011-02-01

    The fast response and the short recovery time of avalanche photodiodes (APDs) in linear mode make those devices ideal for direct X-ray detection in applications requiring high time resolution or counting rate. In order to provide position sensitivity, the XNAP project aims at creating a hybrid pixel detector with nanosecond time resolution based on a monolithic APD sensor array with 32 x32 pixels covering about 1 cm{sup 2} active area. The readout is implemented in a pixelated front-end ASIC suited for the readout of such arrays, matched to pixels of 280{mu}mx280{mu}m size. Every single channel features a fast transimpedance amplifier, a discriminator with locally adjustable threshold and two counters with high dynamic range and counting speed able to accumulate X-ray hits with no readout dead time. Additionally, the detector can be operated in list mode by time-stamping every single event with sub-nanosecond resolution. In a first phase of the project, a 4x4 pixel test module is built to validate the conceptual design of the detector. The XNAP project is briefly presented and the performance of the readout ASIC is discussed.

  17. Two aspects of ASIC function: Synaptic plasticity and neuronal injury.

    Science.gov (United States)

    Huang, Yan; Jiang, Nan; Li, Jun; Ji, Yong-Hua; Xiong, Zhi-Gang; Zha, Xiang-ming

    2015-07-01

    Extracellular brain pH fluctuates in both physiological and disease conditions. The main postsynaptic proton receptor is the acid-sensing ion channels (ASICs). During the past decade, much progress has been made on protons, ASICs, and neurological disease. This review summarizes the recent progress on synaptic role of protons and our current understanding of how ASICs contribute to various types of neuronal injury in the brain. This article is part of the Special Issue entitled 'Acid-Sensing Ion Channels in the Nervous System'. Copyright © 2015 Elsevier Ltd. All rights reserved.

  18. Back-end and interface implementation of the STS-XYTER2 prototype ASIC for the CBM experiment

    Science.gov (United States)

    Kasinski, K.; Szczygiel, R.; Zabolotny, W.

    2016-11-01

    Each front-end readout ASIC for the High-Energy Physics experiments requires robust and effective hit data streaming and control mechanism. A new STS-XYTER2 full-size prototype chip for the Silicon Tracking System and Muon Chamber detectors in the Compressed Baryonic Matter experiment at Facility for Antiproton and Ion Research (FAIR, Germany) is a 128-channel time and amplitude measuring solution for silicon microstrip and gas detectors. It operates at 250 kHit/s/channel hit rate, each hit producing 27 bits of information (5-bit amplitude, 14-bit timestamp, position and diagnostics data). The chip back-end implements fast front-end channel read-out, timestamp-wise hit sorting, and data streaming via a scalable interface implementing the dedicated protocol (STS-HCTSP) for chip control and hit transfer with data bandwidth from 9.7 MHit/s up to 47 MHit/s. It also includes multiple options for link diagnostics, failure detection, and throttling features. The back-end is designed to operate with the data acquisition architecture based on the CERN GBTx transceivers. This paper presents the details of the back-end and interface design and its implementation in the UMC 180 nm CMOS process.

  19. Low-power Cross-Correlator ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Pacific MicroCHIP Corporation offers to design an ASIC that includes a cross-correlation unit together with the interfaces to be connected to the output of the...

  20. Extreme Temperature, Rad-Hard Power Management ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group will design a rad-hard Application Specific Integrated Circuit (ASIC) for spacecraft power management that is functional over a temperature range of...

  1. Pilot tests of a PET detector using the TOF-PET ASIC based on monolithic crystals and SiPMs

    Science.gov (United States)

    Aguilar, A.; González-Montoro, A.; González, A. J.; Hernández, L.; Monzó, J. M.; Bugalho, R.; Ferramacho, L.; Benlloch, J. M.

    2016-12-01

    In this work we show pilot tests of PET detector blocks using the TOF-PET ASIC, coupled to SiPM detector arrays and different crystal configurations. We have characterized the main ASIC features running calibration processes to compensate the time dispersion among the different ASIC/SiPM paths as well as for the time walk on the arrival of optical photons. The aim of this work is to use of LYSO monolithic crystals and explore their photon Depth of Interaction (DOI) capabilities, keeping good energy and spatial resolutions. First tests have been carried out with crystal arrays. Here we made it possible to reach a coincidence resolving times (CRT) of 370 ps FWHM, with energy resolutions better than 20% and resolving well 2 mm sized crystal elements. When using monolithic crystals, a single-pixel LYSO reference crystal helped to explore the CRT performance. We studied different strategies to provide the best timestamp determination in the monolithic scintillator. Times around 1 ns FWHM have been achieved in these pilot studies. In terms of spatial and energy resolution, values of about 3 mm and better than 30% were found, respectively. We have also demonstrated the capability of this system (monolithic and ASIC) to return accurate DOI information.

  2. SLVS Transmitter and Receiver for CBM MUCH ASIC

    Science.gov (United States)

    Bulbakov, I.

    2017-01-01

    Scalable Low Voltage Signaling (SLVS) Transmitter (Tx) and Receiver (Rx) IP blocks are designed in the UMC 180 nm CMOS technology as component of the readout ASIC for the muon chambers (MUCH) of the Compressed Baryonic Matter (CBM) experiment at FAIR (Darmstadt, Germany). These blocks are a prototype of the physical layer of the e-link interface that is used for ASIC-GBTx connection. The experimental results at 320 Mbit/s are presented.

  3. Fatalic, a very-front-end Asic for the ATLAS Tile Calorimeter

    CERN Document Server

    Manen, Samuel Pierre; The ATLAS collaboration

    2016-01-01

    Abstract—The ATLAS Collaboration has started a vast program of upgrades in the context of high-luminosity LHC (HLLHC) forseen in 2024. The current readout electronics of every subdetector, including the Tile Calorimeter (TileCal), must be upgraded to comply with the new specifications aiming for the future operating conditions. The ASIC described in this document, named Front-end ATlAs tiLe Integrated Circuit (FATALIC), has been developed to fulfil the requirements of the TileCal upgrade. FATALIC is based on a 130 nm CMOS technology and performs the complete processing of the signal, including amplification, shaping and digitization. The first stage is a current conveyor which splits the input signal into three ranges, allowing to deal with a large dynamic range (from 25 fC up to 1.2 nC). Each current conveyor output is followed by a shaper and a dedicated pipeline 12 bit ADC operating at 40 MHz. Measurements show a non-linearity at the percent level for a typical input charge of interest. The noise of the ...

  4. ASIC1基因敲除小鼠的繁殖及基因鉴定%Reproduction and genotype identification of ASIC1 knockout mice

    Institute of Scientific and Technical Information of China (English)

    周仁鹏; 吴小山; 王志森; 葛金芳; 陈飞虎

    2015-01-01

    To breed and identify acid sensing ion channel 1(ASIC1) gene knockout mice, so as to lay the founda-tion for studying ASIC1 protein. The heterozygote mice were bred and reproduced. Genome DNA extracted from the murine tail was subjected to PCR test for genotype identification. Breeding and reproducing of ASIC1 knockout mice were both successful,and the genotypes of the offspring mice were heterozygous( ASIC1+/ -) ,homozygous( ASIC1-/ -) ,and wild-type( ASIC1+/ +) . Appropriate methods of breeding,reproducing and identifying can effective-ly obtain ASIC1-/ - mice.%饲养并繁殖酸敏感离子通道1(ASIC1)基因敲除杂合子小鼠,提取小鼠尾部组织DNA,采用聚合酶链反应( PCR)方法鉴定子代小鼠基因型. ASIC1 基因敲除小鼠的繁育和鉴定均获得成功,子代小鼠基因型分别为杂合子( ASIC1+/-)、纯合子( ASIC1-/ -)和野生型( ASIC1+/ +).

  5. Front-end Multiplexing - applied to SQUID multiplexing : Athena X-IFU and QUBIC experiments

    CERN Document Server

    Prêle, Damien

    2015-01-01

    As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device...

  6. Charged Particle Tracking with the Timepix ASIC

    CERN Document Server

    Akiba, Kazuyoshi; Collins, P; Crossley, M; Dumps, R; Gersabeck, M; Gligorov, Vladimir V; Llopart, X; Nicol, M; Poikela, T; Cabruja, Enric; Fleta, C; Lozano, M; Pellegrini, G; Bates, R; Eklund, L; Hynds, D; Ferre Llin, L; Maneuski, D; Parkes, C; Plackett, R; Rodrigues, E; Stewart, G; Akiba, K; van Beuzekom, M; Heijne, V; Heijne, E H M; Gordon, H; John, M; Gandelman, M; Esperante, D; Gallas, A; Vazquez Regueiro, P; Bayer, F; Michel, T; Needham, M; Artuso, M; Badman, R; Borgia, A; Garofoli, J; Wang, J; Xing, Z; Buytaert, Jan; Leflat, Alexander

    2012-01-01

    A prototype particle tracking telescope has been constructed using Timepix and Medipix ASIC hybrid pixel assemblies as the six sensing planes. Each telescope plane consisted of one 1.4 cm2 assembly, providing a 256x256 array of 55 micron square pixels. The telescope achieved a pointing resolution of 2.3 micron at the position of the device under test. During a beam test in 2009 the telescope was used to evaluate in detail the performance of two Timepix hybrid pixel assemblies; a standard planar 300 micron thick sensor, and 285 micron thick double sided 3D sensor. This paper describes a detailed charge calibration study of the pixel devices, which allows the true charge to be extracted, and reports on measurements of the charge collection characteristics and Landau distributions. The planar sensor achieved a best resolution of 4.0 micron for angled tracks, and resolutions of between 4.4 and 11 micron for perpendicular tracks, depending on the applied bias voltage. The double sided 3D sensor, which has signific...

  7. An efficient real time superresolution ASIC system

    Science.gov (United States)

    Reddy, Dikpal; Yue, Zhanfeng; Topiwala, Pankaj

    2008-04-01

    Superresolution of images is an important step in many applications like target recognition where the input images are often grainy and of low quality due to bandwidth constraints. In this paper, we present a real-time superresolution application implemented in ASIC/FPGA hardware, and capable of 30 fps of superresolution by 16X in total pixels. Consecutive frames from the video sequence are grouped and the registered values between them are used to fill the pixels in the higher resolution image. The registration between consecutive frames is evaluated using the algorithm proposed by Schaum et al. The pixels are filled by averaging a fixed number of frames associated with the smallest error distances. The number of frames (the number of nearest neighbors) is a user defined parameter whereas the weights in the averaging process are decided by inverting the corresponding smallest error distances. Wiener filter is used to post process the image. Different input parameters, such as size of input image, enlarging factor and the number of nearest neighbors, can be tuned conveniently by the user. We use a maximum word size of 32 bits to implement the algorithm in Matlab Simulink as well as the hardware, which gives us a fine balance between the number of bits and performance. The algorithm performs with real time speed with very impressive superresolution results.

  8. Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    de La Taille, C

    2008-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  9. MMIC front-ends for optical communication systems

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad

    1993-01-01

    Two different types of optical front-end MMIC amplifiers for a 2.5-Gb/s coherent heterodyne optical receiver are presented. A bandwidth of 6-12 GHz has been obtained for a tuned front-end and 3-13 GHz for a distributed front-end. An input noise current density of 5-15 pA/√Hz has been obtained for...

  10. CWICOM: A Highly Integrated & Innovative CCSDS Image Compression ASIC

    Science.gov (United States)

    Poupat, Jean-Luc; Vitulli, Raffaele

    2013-08-01

    The space market is more and more demanding in terms of on image compression performances. The earth observation satellites instrument resolution, the agility and the swath are continuously increasing. It multiplies by 10 the volume of picture acquired on one orbit. In parallel, the satellites size and mass are decreasing, requiring innovative electronic technologies reducing size, mass and power consumption. Astrium, leader on the market of the combined solutions for compression and memory for space application, has developed a new image compression ASIC which is presented in this paper. CWICOM is a high performance and innovative image compression ASIC developed by Astrium in the frame of the ESA contract n°22011/08/NLL/LvH. The objective of this ESA contract is to develop a radiation hardened ASIC that implements the CCSDS 122.0-B-1 Standard for Image Data Compression, that has a SpaceWire interface for configuring and controlling the device, and that is compatible with Sentinel-2 interface and with similar Earth Observation missions. CWICOM stands for CCSDS Wavelet Image COMpression ASIC. It is a large dynamic, large image and very high speed image compression ASIC potentially relevant for compression of any 2D image with bi-dimensional data correlation such as Earth observation, scientific data compression… The paper presents some of the main aspects of the CWICOM development, such as the algorithm and specification, the innovative memory organization, the validation approach and the status of the project.

  11. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    Science.gov (United States)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  12. A 45 nm Low Cost, Radiation Hardened, Platform Based Structured ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The proposed 45 nm radiation hardened platform based structured ASIC architecture offers the performance and density expected of a custom ASIC with the low...

  13. The read-out ASIC for the Space NUCLEON project

    Science.gov (United States)

    Atkin, E.; Voronin, A.; Karmanov, D.; Kudryashov, I.; Podorozhniy, D.; Shumikhin, V.

    2015-04-01

    This paper summarizes the design results for the read-out ASIC for the space NUCLEON project of the Russian Federal Space Agency ROSCOSMOS. The ASIC with a unique high dynamic range (1-40 000 mip) at low power consumption ( 50, generated by silicon detectors, having capacitances up to 100 pF. The chip structure includes 32 analog channels, each consisting of a charge sensitive amplifier (CSA) with a p-MOS input transistor (W = 8 mm, L = 0.5 μ m), a shaper (peaking time of 2 us) and a T&H circuit. The ASIC showed a 120 pC dynamic range at a SNR of 2.5 for the particles with minimal ionization energy (1 mip). The chip was fabricated by the 0.35 um CMOS process via Europractice and tested both at lab conditions and in the SPS beam at CERN.

  14. HEXITEC ASIC-a pixellated readout chip for CZT detectors

    Energy Technology Data Exchange (ETDEWEB)

    Jones, Lawrence [STFC Rutherford Appleton Laboratory, Didcot OX11 0QX (United Kingdom)], E-mail: l.l.jones@stfc.ac.uk; Seller, Paul; Wilson, Matthew; Hardie, Alec [STFC Rutherford Appleton Laboratory, Didcot OX11 0QX (United Kingdom)

    2009-06-01

    HEXITEC is a collaborative project with the aim of developing a new range of detectors for high-energy X-ray imaging. High-energy X-ray imaging has major advantages over current lower energy imaging for the life and physical sciences, including improved phase-contrast images on larger, higher density samples and with lower accumulated doses. However, at these energies conventional silicon-based devices cannot be used, hence, the requirement for a new range of high Z-detector materials. Underpinning the HEXITEC programme are the development of a pixellated Cadmium Zinc Telluride (CZT) detectors and a pixellated readout ASIC which will be bump-bonded to the detector. The HEXITEC ASIC is required to have low noise (20 electrons rms) and tolerate detector leakage currents. A prototype 20x20 pixel ASIC has been developed and manufactured on a standard 0.35 {mu}m CMOS process.

  15. A novel simulation and verification approach in an ASIC design process

    CERN Document Server

    Husmann, D; Mahboubi, K; Pfeiffer, U; Schumacher, C

    2000-01-01

    We have built a fast signal-processing and readout ASIC (PPrAsic) for the Pre-Processor system of the ATLAS Level-1 Calorimeter Trigger. Our novel ASIC design environment incorporates algorithm development with digital hardware synthesis and verification. The purely digital ASIC was designed in Verilog HDL (hardware description language) and embedded in a system wide analog and digital simulation or implemented algorithms. We present here our design environment and experience that we gained from the design process. (10 refs).

  16. Radiation induced Single Event Effects in the ATLAS MDT-ASD front-end chip

    CERN Document Server

    Posch, C

    2002-01-01

    Single Event Effect (SEE) tests of the MDT-ASD, the ATLAS MDT front-end chip have been performed at the Harvard Cyclotron Lab. The MDT-ASD is an 8-channel drift tube read-out ASIC fabricated in a commercial 0.5um CMOS process (AMOS14TB). The chip contains a 53 bit register which holds the setup information and an associated shift register of the same length plus some additional control logic. 10 test devices were exposed to a 160 MeV proton beam with a fluence of 1.05E9 p.cm-2.s-1 up to >4.4E p.cm-2 per device. After a total fluence of 4.46E13 p.cm-2, 7 soft SEEs (non-permanent bit flips in the registers) and 0 hard/destructive SEE (e.g. latch-ups, SEL) had occurred. The simulated fluence for 10 years of LHC operation at nominal luminosity for worst case location MDT components is 2.67E11 h.cm-2. The rate of SEUs in the ASD setup register for all of ATLAS, derived from these numbers, is 2.4 per day. It is foreseen to update the active registers of the on-detector electronics at regular intervals. Depending on...

  17. Frontend and Backend Electronics for the ATLAS New Small Wheel Upgrade

    CERN Document Server

    Martinez Outschoorn, Verena; The ATLAS collaboration

    2016-01-01

    The Phase-I and Phase-II upgrades of the LHC accelerator will increase the LHC instantaneous luminosity to 2×1034 cm-2s-1 and 7.5×1034 cm-2s-1, respectively. The luminosity increase drastically impacts the ATLAS trigger and readout data rates. The present ATLAS small wheel muon detector will be replaced with a New Small Wheel (NSW) detector in 2019. The NSW will feature two new detector technologies, Resistive Micromegas (MM) and small strip Thin Gap Chambers (sTGC) conforming a system of ~2.4 million readout channels. Both detectors will be used for muon triggering and precision tracking. A common readout path and two separate trigger paths are developed for these two detector technologies. The frontend electronics will be implemented in about 8000 boards including the design of 4 custom ASICs capable of driving trigger and tracking primitives to the backend trigger processor and readout system. The readout data flow is designed through a high-throughput network approach. The large number of readout channe...

  18. Progress on the upgrade of the CMS Hadron Calorimeter Front-End electronics

    Energy Technology Data Exchange (ETDEWEB)

    Anderson, Jake; Whitmore, Juliana; /Fermilab

    2011-11-01

    We present a scheme to upgrade the CMS HCAL front-end electronics in the second long shutdown to upgrade the LHC (LS2), which is expected to occur around 2018. The HCAL electronics upgrade is required to handle the major instantaneous luminosity increase (up to 5 * 10{sup 34} cm{sup -2} s{sup -1}) and an expected integrated luminosity of {approx}3000 fb{sup -1}. A key aspect of the HCAL upgrade is to read out longitudinal segmentation information to improve background rejection, energy resolution, and electron isolation at the L1 trigger. This paper focuses on the requirements for the new electronics and on the proposed solutions. The requirements include increased channel count, additional timing capabilities, and additional redundancy. The electronics are required to operate in a harsh environment and are constrained by the existing infrastructure. The proposed solutions span from chip level to system level. They include the development of a new ASIC ADC, the design and testing of higher speed transmitters to handle the increased data volume, the evaluation and use of circuits from other developments, evaluation of commercial FPGAs, better thermal design, and improvements in the overall readout architecture. We will report on the progress of the designs for these upgraded systems, along with performance requirements and initial design studies.

  19. Frontend electronics for high-precision single photo-electron timing using FPGA-TDCs

    Energy Technology Data Exchange (ETDEWEB)

    Cardinali, Matteo [Helmholtz Institut Mainz (Germany); Collaboration: PANDA Cherenkov-Collaboration

    2014-07-01

    The next generation of high-luminosity experiments requires excellent Particle Identification (PID) detectors which calls for Imaging Cherenkov counters with fast electronics to cope with the expected data rates. The planned PANDA experiment at FAIR expects average interaction rates of 20 MHz. A Barrel DIRC will provide PID in the central region of the Target Spectrometer. A single photo-electron timing resolution of better than 100 ps is projected for the Barrel DIRC to disentangle the complicated patterns created by the focusing optics on the image plane. The typically large amount of readout channels (approx 15,000 in case of the PANDA Barrel DIRC) places non-negligible limits on size and power consumption of the Front-End Electronics (FEE). The proposed design is based on the TRBv3 readout using FPGA-TDCs with a precision better than 20 ps RMS and custom FEE with high-bandwidth pre-amplifiers and fast discriminators. Two types of FEE cards optimised for reading out 64-channel Photonis Planacon MCP-PMTs were tested: one based on the NINO ASIC developed for the ALICE RPC readout and the other, called PaDiWa, using FPGA-based discriminators. Both types of FEE cards were tested with a small DIRC prototype comprising a radiator bar with focusing lens and an oil-filled expansion volume instrumented with 6 Planacon 64-channel MCP-PMTs. In the presentation the result of a test experiment performed at MAMI B, Mainz, are addressed.

  20. Charge-sensitive front-end electronics with operational amplifiers for CdZnTe detectors

    Science.gov (United States)

    Födisch, P.; Berthel, M.; Lange, B.; Kirschke, T.; Enghardt, W.; Kaever, P.

    2016-09-01

    Cadmium zinc telluride (CdZnTe, CZT) radiation detectors are suitable for a variety of applications, due to their high spatial resolution and spectroscopic energy performance at room temperature. However, state-of-the-art detector systems require high-performance readout electronics. Though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, requirements of high dynamic range and high throughput are not available in any commercial circuit. Consequently, the present study develops the analog front-end electronics with operational amplifiers for an 8×8 pixelated CZT detector. For this purpose, we modeled an electrical equivalent circuit of the CZT detector with the associated charge-sensitive amplifier (CSA). Based on a detailed network analysis, the circuit design is completed by numerical values for various features such as ballistic deficit, charge-to-voltage gain, rise time, and noise level. A verification of the performance is carried out by synthetic detector signals and a pixel detector. The experimental results with the pixel detector assembly and a 22Na radioactive source emphasize the depth dependence of the measured energy. After pulse processing with depth correction based on the fit of the weighting potential, the energy resolution is 2.2% (FWHM) for the 511 keV photopeak.

  1. UWB front-end for SAR-based imaging system

    NARCIS (Netherlands)

    Monni, S.; Grooters, R.; Neto, A.; Nennie, F.A.

    2010-01-01

    A planarly fed UWB leaky lens antenna is presented integrated with wide band transmit and receive front-end electronics, to be used in a SAR-based imaging system. The unique non-dispersive characteristics of this antenna over a very wide bandwidth, together with the dual band front-end electronics b

  2. Self-calibrating quadrature mixing front-end for SDR

    CSIR Research Space (South Africa)

    De Witt, JJ

    2008-01-01

    Full Text Available A quadrature mixing front-end is well-suited toward software define radio (SDR) applications, due to its low complexity and the inherent flexibility that it affords the radio front-end. Its performance is, however, severely affected by gain...

  3. Ka-Band SiGe Receiver Front-End MMIC for Transponder Applications

    Science.gov (United States)

    Venkatesan, Jaikrishna; Mysoor, Narayan R.; Hashemi, Hassein; Aflatouni, Firooz

    2010-01-01

    A fully integrated, front-end Ka-band monolithic microwave integrated circuit (MMIC) was developed that houses an LNA (low noise amplifier) stage, a down-conversion stage, and output buffer amplifiers. The MMIC design employs a two-step quadrature down-conversion architecture, illustrated in the figure, which results in improved quality of the down-converted IF quadrature signals. This is due to the improved sensitivity of this architecture to amplitude and phase mismatches in the quadrature down-conversion process. Current sharing results in reduced power consumption, while 3D-coupled inductors reduce the chip area. Improved noise figure is expected over previous SiGe-based, frontend designs

  4. DIALOG An ASIC for timing of the LHCb muon detector

    CERN Document Server

    Cadeddu, S; Deplano, C; Lai, A

    2004-01-01

    The muon detector of the LHCb experiment at CERN plays a fundamental role in the first trigger level. It is mainly realized by means of a multi-wire proportional chambers technology and consists of about 126,000 front-end channels. High efficiency is necessary both at detector and front-end level to satisfy the trigger requirement of five hits per five muon stations with an overall efficiency of 95%. This corresponds to having a single front-end channel detection efficiency of 99% within a time window of 20 ns, and also poses the problem of an accurate time alignment of the whole detector. The problem is addressed by designing two custom integrated circuits, named DIagnostic, time Adjustment and LOGics (DIALOG) and SYNC. DIALOG integrates important tools for detector time alignment procedures and time alignment monitoring on the front-end system. Many other features, necessary for the muon trigger operation and for a safe front-end monitoring, are integrated on DIALOG.

  5. Beam test performance of the SKIROC2 ASIC

    CERN Document Server

    Frisson, T; Anduze, M; Augustin, J.E; Bonis, J; Boudry, V; Bourgeois, C; Brient, J.C; Callier, S; Cerutti, M; Chen, S; Cornat, R; Cornebise, P; Cuisy, D; David, J; De la Taille, C; Dulucq, F; Frotin, M; Gastaldi, F; Ghislain, P; Giraud, J; Gonnin, A; Grondin, D; Guliyev, E; Hostachy, J.Y; Jeans, D; Kamiya, Y; Kawagoe, K; Kozakai, C; Lacour, D; Lavergne, L; Lee, S.H; Magniette, F; Ono, H; Poeschl, R; Rouëné, J; Seguin-Moreau, N; Song, H.S; Sudo, Y; Thiebault, A; Tran, H; Ueno, H; Van der Kolk, N; Yoshioka, T

    2015-01-01

    Beam tests of the first layers of CALICE silicon tungsten ECAL technological prototype were performed in April and July 2012 using 1–6 GeV electron beam at DESY. This paper presents an analysis of the SKIROC2 readout ASIC performance under test beam conditions.

  6. Beam test performance of the SKIROC2 ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Amjad, M.S. [Laboratoire de l' Accélérateur Linéaire, Centre Scientifique d' Orsay, Université de Paris-Sud XI, CNRS/IN2P3, F-91898 Orsay Cedex (France); Anduze, M. [Laboratoire Leprince-Ringuet, École Polytechnique, CNRS/IN2P3, F-91128 Palaiseau (France); Augustin, J.-E. [Laboratoire de Physique Nucléaire et de Hautes Energies, UPMC, Université Paris Diderot, CNRS/IN2P3, Paris (France); Bonis, J. [Laboratoire de l' Accélérateur Linéaire, Centre Scientifique d' Orsay, Université de Paris-Sud XI, CNRS/IN2P3, F-91898 Orsay Cedex (France); Boudry, V. [Laboratoire Leprince-Ringuet, École Polytechnique, CNRS/IN2P3, F-91128 Palaiseau (France); Bourgeois, C. [Laboratoire de l' Accélérateur Linéaire, Centre Scientifique d' Orsay, Université de Paris-Sud XI, CNRS/IN2P3, F-91898 Orsay Cedex (France); Brient, J.-C. [Laboratoire Leprince-Ringuet, École Polytechnique, CNRS/IN2P3, F-91128 Palaiseau (France); Callier, S. [OMEGA, École Polytechnique, CNRS/IN2P3, F-91128 Palaiseau (France); Cerutti, M. [Laboratoire Leprince-Ringuet, École Polytechnique, CNRS/IN2P3, F-91128 Palaiseau (France); Chen, S. [Department of Physics, Graduate School of Science, The University of Tokyo, Tokyo 113-0033 (Japan); Cornat, R. [Laboratoire Leprince-Ringuet, École Polytechnique, CNRS/IN2P3, F-91128 Palaiseau (France); and others

    2015-04-01

    Beam tests of the first layers of CALICE silicon tungsten ECAL technological prototype were performed in April and July 2012 using 1–6 GeV electron beam at DESY. This paper presents an analysis of the SKIROC2 readout ASIC performance under test beam conditions.

  7. Three-dimensional stacked structured ASIC devices and methods of fabrication thereof

    Energy Technology Data Exchange (ETDEWEB)

    Shinde, Subhash L.; Teifel, John; Flores, Richard S.; Jarecki Jr., Robert L.; Bauer, Todd

    2015-11-19

    A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.

  8. Radiation hardness tests and characterization of the CLARO-CMOS, a low power and fast single-photon counting ASIC in 0.35 micron CMOS technology

    Science.gov (United States)

    Fiorini, M.; Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2014-12-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. This chip is capable of single-photon counting with multi-anode photomultipliers and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The prototype is realized in AMS 0.35 micron CMOS technology. In the LHCb RICH environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2 (LS2), the ASIC must withstand a total fluence of about 6×1012 1 MeV neq /cm2 and a total ionizing dose of 400 krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long term stability of the electronics front-end. The results of multi-step irradiation tests with neutrons and X-rays up to the fluence of 1014 cm-2 and a dose of 4 Mrad, respectively, are presented, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  9. Results of a combined monolithic crystal and an array of ASICs controlled SiPMs

    Energy Technology Data Exchange (ETDEWEB)

    Conde, P.; González, A.J., E-mail: agonzalez@i3m.upv.es; Hernández, L.; Bellido, P.; Iborra, A.; Crespo, E.; Moliner, L.; Rigla, J.P.; Rodríguez-Álvarez, M.J.; Sánchez, F.; Seimetz, M.; Soriano, A.; Vidal, L.F.; Benlloch, J.M.

    2014-01-11

    In this work we present the energy and spatial resolutions we have obtained for a γ-ray detector based on a monolithic LYSO crystal coupled to an array of 256 SiPMs. Two crystal configurations of the same trapezoidal shape have been tried. In one approach all surfaces were black painted but the exit one facing the photosensor array which was polished. The other approach included a retroreflector (RR) layer coupled to the entrance face of the crystal powering the amount of transmitted light to the photosensors. Two coupling media between the scintillator and the SiPM array were used, namely direct coupling by means of optical grease and coupling through an array of light guides. Since the same operational voltage was supplied to the entire array, it was needed to equalize their gains before feeding their signals to the Data Acquisition system. Such a job was performed by means of 4 scalable Application Specific Circuits (ASICs). An energy resolution of about 24.4% has been achieved for the direct coupling with the RR layer together with a spatial resolution of approximately 2.9 mm at the detector center. With the light guides coupling the effects of image compression at the edges are significantly minimized, but worsening the energy resolution to about 33.1% with a spatial resolution nearing 4 mm at the detector center.

  10. Performance of VATA64HDR16 ASIC for medical physics applications based on continuous crystals and SiPMs

    Science.gov (United States)

    Barrio, J.; Etxebeste, A.; Lacasta, C.; Muñoz, E.; Oliver, J. F.; Solaz, C.; Llosá, G.

    2015-12-01

    Detectors based on Silicon Photomultipliers (SiPMs) coupled to continuous crystals are being tested in medical physics applications due to their potential high resolution and sensitivity. To cope with the high granularity required for a very good spatial resolution, SiPM matrices with a large amount of elements are needed. To be able to read the information coming from each individual channel, dedicated ASICs are employed. The VATA64HDR16 ASIC is a 64-channel, charge-sensitive amplifier that converts the collected charge into a proportional current or voltage signal. A complete assessment of the suitability of that ASIC for medical physics applications based on continuous crystals and SiPMs has been carried out. The input charge range is linear from 0-2 pC up to 55 pC. The energy resolution obtained at 511 keV is 10% FWHM with a LaBr3 crystal and 16% FWHM with a LYSO crystal. A coincidence timing resolution of 24 ns FWHM is obtained with two LYSO crystals.

  11. Development of low-noise high-speed analog ASIC for X-ray CCD cameras and wide-band X-ray imaging sensors

    Science.gov (United States)

    Nakajima, Hiroshi; Hirose, Shin-nosuke; Imatani, Ritsuko; Nagino, Ryo; Anabuki, Naohisa; Hayashida, Kiyoshi; Tsunemi, Hiroshi; Doty, John P.; Ikeda, Hirokazu; Kitamura, Hisashi; Uchihori, Yukio

    2016-09-01

    We report on the development and performance evaluation of the mixed-signal Application Specific Integrated Circuit (ASIC) developed for the signal processing of onboard X-ray CCD cameras and various types of X-ray imaging sensors in astrophysics. The quick and low-noise readout is essential for the pile-up free imaging spectroscopy with a future X-ray telescope. Our goal is the readout noise of 5e- r . m . s . at the pixel rate of 1 Mpix/s that is about 10 times faster than those of the currently working detectors. We successfully developed a low-noise ASIC as the front-end electronics of the Soft X-ray Imager onboard Hitomi that was launched on February 17, 2016. However, it has two analog-to-digital converters per chain due to the limited processing speed and hence we need to correct the difference of gain to obtain the X-ray spectra. Furthermore, its input equivalent noise performance is not satisfactory (> 100 μV) at the pixel rate higher than 500 kpix/s. Then we upgrade the design of the ASIC with the fourth-order ΔΣ modulators to enhance its inherent noise-shaping performance. Its performance is measured using pseudo CCD signals with variable processing speed. Although its input equivalent noise is comparable with the conventional one, the integrated non-linearity (0.1%) improves to about the half of that of the conventional one. The radiation tolerance is also measured with regard to the total ionizing dose effect and the single event latch-up using protons and Xenon, respectively. The former experiment shows that all of the performances does not change after imposing the dose corresponding to 590 years in a low earth orbit. We also put the upper limit on the frequency of the latch-up to be once per 48 years.

  12. Web-based DAQ systems: connecting the user and electronics front-ends

    Science.gov (United States)

    Lenzi, Thomas

    2016-12-01

    Web technologies are quickly evolving and are gaining in computational power and flexibility, allowing for a paradigm shift in the field of Data Acquisition (DAQ) systems design. Modern web browsers offer the possibility to create intricate user interfaces and are able to process and render complex data. Furthermore, new web standards such as WebSockets allow for fast real-time communication between the server and the user with minimal overhead. Those improvements make it possible to move the control and monitoring operations from the back-end servers directly to the user and to the front-end electronics, thus reducing the complexity of the data acquisition chain. Moreover, web-based DAQ systems offer greater flexibility, accessibility, and maintainability on the user side than traditional applications which often lack portability and ease of use. As proof of concept, we implemented a simplified DAQ system on a mid-range Spartan6 Field Programmable Gate Array (FPGA) development board coupled to a digital front-end readout chip. The system is connected to the Internet and can be accessed from any web browser. It is composed of custom code to control the front-end readout and of a dual soft-core Microblaze processor to communicate with the client.

  13. Adaptive RF front-ends for hand-held applications

    CERN Document Server

    van Bezooijen, Andre; van Roermund, Arthur

    2010-01-01

    The RF front-end - antenna combination is a vital part of a mobile phone because its performance is very relevant to the link quality between hand-set and cellular network base-stations. The RF front-end performance suffers from changes in operating environment, like hand-effects, that are often unpredictable. ""Adaptive RF Front-Ends for Hand-Held Applications"" presents an analysis on the impact of fluctuating environmental parameters. In order to overcome undesired behavior two different adaptive control methods are treated that make RF frond-ends more resilient: adaptive impedance control,

  14. Reconfigurable transceiver architecture for multiband RF-frontends

    CERN Document Server

    Gonzalez Rodriguez, Erick

    2016-01-01

      This book investigates and discusses the hardware design and implementation to achieve smart air interfaces with a reduced number of Radio Frequency (RF) transmitter and receiver chains, or even with a single reconfigurable RF-Frontend in the user terminal. Various hardware challenges are identified and addressed to enable the implementation of autonomous reconfigurable RF-Frontend architectures. Such challenges are (i) the conception of a transceiver with wide tuning range of at least up to 6 GHz, (ii) the system integration of reconfigurable technologies targeting current compact devices that demand voltages up to 100 V for adaptive controlling and (iii) the realization of a multiband and multistandard antenna module employing agile components to provide flexible frequency coverage. A solid design of a reconfigurable frontend is proposed from the RF part to the digital baseband. The system integration of different components in the reconfigurable RF-Frontend of a portable-oriented device architecture is ...

  15. Studies of the performance of different front-end systems for flat-panel multi-anode PMTs with CsI(Tl) scintillator arrays

    CERN Document Server

    Sekiya, H; Kubo, H; Miuchi, K; Nagayoshi, T; Nishimura, H; Okada, Y; Orito, R; Takada, A; Takeda, A; Tanimori, T; Ueno, K

    2006-01-01

    We have studied the performance of two different types of front-end systems for our gamma camera based on Hamamatsu H8500 (flat-panel 64 channels multi-anode PSPMT) with a CsI(Tl) scintillator array. The array consists of 64 pixels of $6\\times6\\times20{\\rm mm}^3$ which corresponds to the anode pixels of H8500. One of the system is based on commercial ASIC chips in order to readout every anode. The others are based on resistive charge divider network between anodes to reduce readout channels. In both systems, each pixel (6mm) was clearly resolved by flood field irradiation of $^{137}$Cs. We also investigated the energy resolution of these systems and showed the performance of the cascade connection of resistive network between some PMTs for large area detectors.

  16. Studies of the performance of different front-end systems for flat-panel multi-anode PMTs with CsI(Tl) scintillator arrays

    Science.gov (United States)

    Sekiya, H.; Hattori, K.; Kubo, H.; Miuchi, K.; Nagayoshi, T.; Nishimura, H.; Okada, Y.; Orito, R.; Takada, A.; Takeda, A.; Tanimori, T.; Ueno, K.

    2006-07-01

    We have studied the performance of two different types of front-end systems for our gamma camera based on Hamamatsu H8500 (flat-panel 64 channels multi-anode PSPMT) with a CsI(Tl) scintillator array. The array consists of 64 pixels of 6×6×20 mm3 which corresponds to the anode pixels of H8500. One of the system is based on commercial ASIC chips in order to read out every anode. The others are based on resistive charge divider network between anodes to reduce readout channels. In both systems, each pixel (6 mm) was clearly resolved by flood field irradiation of 137Cs. We also investigated the energy resolution of these systems and showed the performance of the cascade connection of resistive network between some PMTs for large area detectors.

  17. NINO an ultrafast low-power front-end amplifier discriminator for the time-of-flight detector in the ALICE experiment

    CERN Document Server

    Anghinolfi, F; Krummenacher, F; Usenko, E; Williams, M C S

    2004-01-01

    An ultrafast front-end preamplifier-discriminator chip called NINO has been developed for use in the ALICE time-of-flight detector. The chip has eight channels. Each channel is designed with an amplifier with less than 1-ns peaking time, a discriminator with a minimum detection threshold of 10 fC and an output stage. The output pulse has minimum time jitter (less than 25 ps) on the front edge, and the pulsewidth is dependent of the input signal charge. Each channel consumes 27 mW, and the eight channels fit in a 2*4 mm/sup 2/ ASIC processed in IBM 0.25- mu m CMOS technology. (3 refs).

  18. Simulation study of STS-XYTER front-end electronics in overload situations for the silicon tracking system in the CBM experiment

    Energy Technology Data Exchange (ETDEWEB)

    Balog, Tomas [GSI, Darmstadt (Germany); Collaboration: CBM-Collaboration

    2015-07-01

    In high-rate experiments, as the CBM Experiment at FAIR, a situation can occur in which the data rate temporarily exceeds the available bandwidth. With self-triggered front end electronics such overload situations would lead, without further measures, to uncontrolled data losses and potentially a large number of incomplete events. Mechanisms needed to control data losses and to ensure the collection of complete events can be understood via simulations performed with the hardware description language SystemC. Results from simulations of a simplified front-end electronics for the CBM Silicon Tracking System, based on the STS-XYTER ASIC, are presented. Performed simulations give first insight in the behavior of data flow and data losses in the DAQ system of the CBM experiment. Options and solutions for the data throttling mechanisms at beam conditions required by the CBM experiment are discussed.

  19. Studies of the performance of different front-end systems for flat-panel multi-anode PMTs with CsI(Tl) scintillator arrays

    Energy Technology Data Exchange (ETDEWEB)

    Sekiya, H. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan)]. E-mail: sekiya@cr.scphys.kyoto-u.ac.jp; Hattori, K. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Kubo, H. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Miuchi, K. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Nagayoshi, T. [Advanced Research Institute for Science and Engineering, Waseda University, 17 Kikui-cho, Shinjuku, Tokyo 162-0044 (Japan); Nishimura, H. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Okada, Y. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Orito, R. [Department of Physics, Graduate School of Science and Technology, Kobe University, 1-1 Rokkoudai, Nada, Kobe 657-8501 (Japan); Takada, A. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Takeda, A. [Kamioka Observatory, ICRR, University of Tokyo, 456 Higasi-mozumi, Hida-shi, Gifu 506-1205 (Japan); Tanimori, T. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Ueno, K. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan)

    2006-07-01

    We have studied the performance of two different types of front-end systems for our gamma camera based on Hamamatsu H8500 (flat-panel 64 channels multi-anode PSPMT) with a CsI(Tl) scintillator array. The array consists of 64 pixels of 6x6x20mm{sup 3} which corresponds to the anode pixels of H8500. One of the system is based on commercial ASIC chips in order to read out every anode. The others are based on resistive charge divider network between anodes to reduce readout channels. In both systems, each pixel (6mm) was clearly resolved by flood field irradiation of {sup 137}Cs. We also investigated the energy resolution of these systems and showed the performance of the cascade connection of resistive network between some PMTs for large area detectors.

  20. A 65 nm pixel readout ASIC with quick transverse momentum discrimination capabilities for the CMS Tracker at HL-LHC

    CERN Document Server

    AUTHOR|(CDS)2084503; Kaplon, J; Francisco, R; Caratelli, Alessandro; Kloukinas, Konstantinos; Marchioro, Alessandro

    2016-01-01

    A readout ASIC for the hybrid pixel detector with the capability of performing quick recognition of particles with high transverse momentum has been designed for the requirements of the CMS Outer Tracker at the High Luminosity LHC. The particle momentum dicrimination capability represents the main challenge for this design together with the low power requirement: the constraint of low mass for the new tracker dictates a total power budget of less than 100\\,mW/cm$^2$. The choice of a 65\\,nm CMOS technology has made it possible to satisfy this power requirement despite the fairly large amount of logic necessary to perform the momentum discrimination and the continuous operation at 40\\,MHz. Several techniques for low power have been used to implement this logic that performs cluster reduction, position offset correction and coordinate encoding. A prototype chip including a large part of the final functionality and the full front-end has been realized and comprises a matrix of 16 by 3 rectangular pixels of 100\\,$...

  1. Design and Performance of a Custom ASIC Digitizer for Wire Chamber Readout in 65 nm CMOS Technology

    CERN Document Server

    Lee, MyeongJae; Chang, Jessica K; Ding, Dawei; Gnani, Dario; Grace, Carl R; Jones, John A; Kolomensky, Yury G; von der Lippe, Henrik; Mcvittie, Patrick J; Stettler, Matthew W; Walder, Jean-Pierre

    2015-01-01

    We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Po...

  2. Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC

    Science.gov (United States)

    Aliaga, R. J.; Herrero-Bosch, V.; Capra, S.; Pullia, A.; Dueñas, J. A.; Grassi, L.; Triossi, A.; Domingo-Pardo, C.; Gadea, R.; González, V.; Hüyük, T.; Sanchís, E.; Gadea, A.; Mengoni, D.

    2015-11-01

    The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling. Its readout system is to be based on analog memory ASICs with 64 channels each that sample a 1 μs window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the total number of storage cells, particularly for large amounts of input channels. This is accomplished by partitioning the typical Switched Capacitor Array structure into two pipelined, asymmetric stages and introducing FIFO queue-like control circuitry for captured data, achieving total independence between the capture and readout operations.

  3. Design and performance of a custom ASIC digitizer for wire chamber readout in 65 nm CMOS technology

    Science.gov (United States)

    Lee, M. J.; Brown, D. N.; Chang, J. K.; Ding, D.; Gnani, D.; Grace, C. R.; Jones, J. A.; Kolomensky, Y. G.; von der Lippe, H.; Mcvittie, P. J.; Stettler, M. W.; Walder, J.-P.

    2015-06-01

    We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.

  4. Phase 1 Front-End CMS Calorimeter (HE) Upgrade Preparation

    CERN Document Server

    Bunin, Pavel

    2016-01-01

    Preparation of HE Phase 1 Front-End upgrade is shown. For the final quality control of the new generation HE front-end electronics components a Burn-in stand has been prepared. All electronics components are being tested on the burn-in stand and should pass through the burn-in QC before the installation on the CMS. First tests and results are presented.

  5. Planar millimeter wave radar frontend for automotive applications

    OpenAIRE

    2003-01-01

    A fully integrated planar sensor for 77 GHz automotive applications is presented. The frontend consists of a transceiver multichip module and an electronically steerable microstrip patch array. The antenna feed network is based on a modified Rotman-lens and connected to the array in a multilayer approach offering higher integration. Furthermore, the frontend comprises a phase lock loop to allow proper frequency-modulated continuous wave (FMCW) radar operation. The latest experimental results ...

  6. Indico front-end: From spaghetti to lasagna

    CERN Document Server

    CERN. Geneva

    2017-01-01

    We will present how we transitioned from legacy spaghetti UI code to a more coherent, easier to understand and maintain ecosystem of front-end technologies and facilities with a strong emphasis in reusable components. In particular, we will share with you: 1) how we use Sass to maintain our home-baked CSS, 2) how we survive in 2017 without front-end Javascript frameworks, and 3) how we use template macros and WTForms for generating consistent HTML transparently.

  7. A miniaturized ASIC-based multichannel scaler instrument

    Energy Technology Data Exchange (ETDEWEB)

    Ericson, M.N.; Turner, G.W.; McMillan, D.E.; Hoffheins, B.S.; Todd, R.A. [Oak Ridge National Lab., TN (United States); Hiller, J.M. [Oak Ridge Y-12 Plant, TN (United States)

    1993-12-31

    A miniaturized multichannel scaler instrument has been developed to address size and operational constraints for data acquisition in a portable laser-induced luminescence system. The multichannel scaling (MCS) function is implemented as a programmable application specific integrated circuit (ASIC) with standard interfaces for control and data acquisition. The instrument is microcontroller-based with sufficient computing power for data manipulation and algorithmic processing. The unit includes electronics for laser control, and amplification and pulse height discrimination of PMT pulses. Modification of the instrument should allow use in nuclear, chemical, and spectroscopy related applications including Mossbauer experiments. Interfaces are incorporated allowing both computer-controlled and stand alone operation. Implementation of the MCS function as an ASIC and comparison with conventional implementations are discussed. Full characterization of the MCS is presented including differential non-linearity (DNL), bin dead time, and bandwidth measurements.

  8. Implementation of the Timepix ASIC in the Scalable Readout System

    Energy Technology Data Exchange (ETDEWEB)

    Lupberger, M., E-mail: lupberger@physik.uni-bonn.de; Desch, K.; Kaminski, J.

    2016-09-11

    We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

  9. FROST: an ASIC for digital mammography with synchrotron radiation

    Energy Technology Data Exchange (ETDEWEB)

    Bergamaschi, A. E-mail: bergamaschi@ts.infn.it; Prest, M.; Vallazza, E.; Arfelli, F.; Dreossi, D.; Longo, R.; Olivo, A.; Pani, S.; Castelli, E

    2003-09-01

    The FRONTier RADiography (FRONTRAD) collaboration is developing a digital system for mammography at the Elettra Synchrotron Light Source in Trieste. The system is based on a silicon microstrip detector array. The ASIC FROST (FRONTRAD Read Out sySTem) was developed as a collaboration between INFN Trieste and Aurelia Microelettronica and is designed to operate in single photon counting mode. FROST provides low-noise and high-gain performances and is able to work at incident photon rates higher than 100 kHz with almost 100% efficiency. The ASIC has been tested and the first images of mammographic test objects will be shown. The acquisition time per breast image should be of about 10 s.

  10. Implementation of the Timepix ASIC in the Scalable Readout System

    Science.gov (United States)

    Lupberger, M.; Desch, K.; Kaminski, J.

    2016-09-01

    We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

  11. Data encryption standard ASIC design and development report.

    Energy Technology Data Exchange (ETDEWEB)

    Robertson, Perry J.; Pierson, Lyndon George; Witzke, Edward L.

    2003-10-01

    This document describes the design, fabrication, and testing of the SNL Data Encryption Standard (DES) ASIC. This device was fabricated in Sandia's Microelectronics Development Laboratory using 0.6 {micro}m CMOS technology. The SNL DES ASIC was modeled using VHDL, then simulated, and synthesized using Synopsys, Inc. software and finally IC layout was performed using Compass Design Automation's CAE tools. IC testing was performed by Sandia's Microelectronic Validation Department using a HP 82000 computer aided test system. The device is a single integrated circuit, pipelined realization of DES encryption and decryption capable of throughputs greater than 6.5 Gb/s. Several enhancements accommodate ATM or IP network operation and performance scaling. This design is the latest step in the evolution of DES modules.

  12. SPIROC (SiPM Integrated Read-Out Chip): dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    Science.gov (United States)

    Bouchel, M.; Callier, S.; Dulucq, F.; Fleury, J.; Jaeger, J.-J.; de La Taille, C.; Martin-Chassard, G.; Raux, L.

    2011-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC (International Linear Collider) prototype of hadronic calorimeter using Silicon photomultiplier (SiPM) or Multi-Pixel Photon Counters (MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2010. SPIROC is an evolution of FLC-SiPM used for the ILC Analogue HCAL physics prototype. The first prototype of SPIROC was submitted in June 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35 μm SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, dual gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2,000 photoelectron and the time with a 100 ps accurate Time-to-digital Converter (TDC). An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson Analogue-to-digital Converter (ADC) has been embedded to digitize the analogue memory content (time and charge on 2 gains). The data are then stored in a 4 Kbytes RAM. A very complex digital part has been integrated to manage all these features and to transfer the data to the DAQ which is described in Dulucq et al. After an exhaustive description, the extensive measurement results of this new front-end chip are presented.

  13. Fully Integrated Biopotential Acquisition Analog Front-End IC

    Directory of Open Access Journals (Sweden)

    Haryong Song

    2015-09-01

    Full Text Available A biopotential acquisition analog front-end (AFE integrated circuit (IC is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA to achieve low input referred noise (IRN and to block unwanted DC potential signals. A DC servo loop (DSL is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL is designed to enhance the input impedance and common mode rejection ratio (CMRR without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL at each CCIA stage. The biopotential AFE is fabricated using a 0.18 μm one polysilicon and six metal layers (1P6M complementary metal oxide semiconductor (CMOS process. The core chip size of the AFE without input/output (I/O pads is 10.5 mm2. A fourth-order band-pass filter (BPF with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 μVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.

  14. Fully Integrated Biopotential Acquisition Analog Front-End IC.

    Science.gov (United States)

    Song, Haryong; Park, Yunjong; Kim, Hyungseup; Ko, Hyoungho

    2015-09-30

    A biopotential acquisition analog front-end (AFE) integrated circuit (IC) is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA) to achieve low input referred noise (IRN) and to block unwanted DC potential signals. A DC servo loop (DSL) is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL) is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL) is designed to enhance the input impedance and common mode rejection ratio (CMRR) without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL) at each CCIA stage. The biopotential AFE is fabricated using a 0.18 μm one polysilicon and six metal layers (1P6M) complementary metal oxide semiconductor (CMOS) process. The core chip size of the AFE without input/output (I/O) pads is 10.5 mm². A fourth-order band-pass filter (BPF) with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 μVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.

  15. VeloPix ASIC for the LHCb VELO Upgrade

    CERN Multimedia

    Cid Vidal, Xabier

    2015-01-01

    The LHCb Vertex Detector (VELO) will be upgraded in 2018 along with the other subsystems of LHCb in order to enable full detector readout at 40 MHz. LHCb will run without a hardware trigger and all data will be fed directly to the software triggering algorithms in the CPU farm. The upgraded VELO is a lightweight silicon hybrid pixel detector with 55 um square pixels, operating in vacuum in close proximity to the LHC beams. The readout will be provided by a dedicated front end ASIC, dubbed VeloPix, matched to the LHCb luminosity requirements. VeloPix is a binary pixel chip with a matrix of 256 x 256 pixels, covering an area of 2 cm^2. It is designed in a 130 nm CMOS technology, and is closely related to the Timepix3, from the Medipix family of ASICs. The principal challenge that the chip has to meet is a hit rate of up to 900 Mhits/s/ASIC, resulting in a data rate of more than 16 Gbit/s. Combining pixels into groups of 2x4 super-pixels enables the use of shared logic and a reduction of bandwidth due to combine...

  16. JPIC-Rad-Hard JPEG2000 Image Compression ASIC

    Science.gov (United States)

    Zervas, Nikos; Ginosar, Ran; Broyde, Amitai; Alon, Dov

    2010-08-01

    JPIC is a rad-hard high-performance image compression ASIC for the aerospace market. JPIC implements tier 1 of the ISO/IEC 15444-1 JPEG2000 (a.k.a. J2K) image compression standard [1] as well as the post compression rate-distortion algorithm, which is part of tier 2 coding. A modular architecture enables employing a single JPIC or multiple coordinated JPIC units. JPIC is designed to support wide data sources of imager in optical, panchromatic and multi-spectral space and airborne sensors. JPIC has been developed as a collaboration of Alma Technologies S.A. (Greece), MBT/IAI Ltd (Israel) and Ramon Chips Ltd (Israel). MBT IAI defined the system architecture requirements and interfaces, The JPEG2K-E IP core from Alma implements the compression algorithm [2]. Ramon Chips adds SERDES interfaces and host interfaces and integrates the ASIC. MBT has demonstrated the full chip on an FPGA board and created system boards employing multiple JPIC units. The ASIC implementation, based on Ramon Chips' 180nm CMOS RadSafe[TM] RH cell library enables superior radiation hardness.

  17. An ASIC Low Power Primer Analysis, Techniques and Specification

    CERN Document Server

    Chadha, Rakesh

    2013-01-01

    This book provides an invaluable primer on the techniques utilized in the design of low power digital semiconductor devices.  Readers will benefit from the hands-on approach which starts form the ground-up, explaining with basic examples what power is, how it is measured and how it impacts on the design process of application-specific integrated circuits (ASICs).  The authors use both the Unified Power Format (UPF) and Common Power Format (CPF) to describe in detail the power intent for an ASIC and then guide readers through a variety of architectural and implementation techniques that will help meet the power intent.  From analyzing system power consumption, to techniques that can employed in a low power design, to a detailed description of two alternate standards for capturing the power directives at various phases of the design, this book is filled with information that will give ASIC designers a competitive edge in low-power design. Starts from the ground-up and explains what power is, how it is measur...

  18. ASIC for High Rate 3D Position Sensitive Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Vernon, E.; De Geronimo, G.; Ackley, K.; Fried, J.; He, Z.; Herman, C.; Zhang, F.

    2010-06-16

    We report on the development of an application specific integrated circuit (ASIC) for 3D position sensitive detectors (3D PSD). The ASIC is designed to operate with pixelated wide bandgap sensors like Cadmium-Zinc-Telluride (CZT), Mercuric Iodide (Hgl2) and Thallium Bromide (TIBr). It measures the amplitudes and timings associated with an ionizing event on 128 anodes, the anode grid, and the cathode. Each channel provides low-noise charge amplification, high-order shaping with peaking time adjustable from 250 ns to 12 {micro}s, gain adjustable to 20 mV/fC or 120 mV/fC (for a dynamic range of 3.2 MeV and 530 keV in CZT), amplitude discrimination with 5-bit trimming, and positive and negative peak and timing detections. The readout can be full or sparse, based on a flag and single- or multi-cycle token passing. All channels, triggered channels only, or triggered with neighbors can be read out thus increasing the rate capability of the system to more than 10 kcps. The ASIC dissipates 330 mW which corresponds to about 2.5 mW per channel.

  19. The SIRIUS Mixed analog-digital ASIC developed for the LOFT LAD and WFM instruments

    CERN Document Server

    Cros, A; Moutaye, E; Ravera, L; Barret, D; Caïs, P; Clédassou, R; Bodin, P; Seyler, JY; Bonzo, A; Feroci, M; Labanti, C; Evangelista, Y; Favre, Y

    2014-01-01

    We report on the development and characterization of the low-noise, low power, mixed analog-digital SIRIUS ASICs for both the LAD and WFM X-ray instruments of LOFT. The ASICs we developed are reading out large area silicon drift detectors (SDD). Stringent requirements in terms of noise (ENC of 17 e- to achieve an energy resolution on the LAD of 200 eV FWHM at 6 keV) and power consumption (650 {\\mu}W per channel) were basis for the ASICs design. These SIRIUS ASICs are developed to match SDD detectors characteristics: 16 channels ASICs adapted for the LAD (970 microns pitch) and 64 channels for the WFM (145 microns pitch) will be fabricated. The ASICs were developed with the 180nm mixed technology of TSMC.

  20. A Low Power Application-Specific Integrated Circuit (ASIC) Implementation of Wavelet Transform/Inverse Transform

    Science.gov (United States)

    2001-03-01

    A unique ASIC was designed implementing the Haar Wavelet transform for image compression/decompression. ASIC operations include performing the Haar... wavelet transform on a 512 by 512 square pixel image, preparing the image for transmission by quantizing and thresholding the transformed data, and...performing the inverse Haar wavelet transform , returning the original image with only minor degradation. The ASIC is based on an existing four-chip FPGA

  1. SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    Bouchel, Michel; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

    2007-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  2. SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    Bouchel, Michel; Dulucq, Frédéric; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

    2009-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  3. AMIC: an expandable integrated analog front-end for light distribution moments analysis

    Energy Technology Data Exchange (ETDEWEB)

    Spaggiari, M; Herrero, V; Lerche, C W; Aliaga, R; Monzo, J M; Gadea, R, E-mail: michele.spaggiari@gmail.com [Instituto de Instrumentacion para Imagen Molecular (I3M), Universidad Politecnica de Valencia, Camino de Vera, 46022, Valencia (Spain)

    2011-01-15

    In this article we introduce AMIC (Analog Moments Integrated Circuit), a novel analog Application Specific Integrated Circuit (ASIC) front-end for Positron Emission Tomography (PET) applications. Its working principle is based on mathematical analysis of light distribution through moments calculation. Each moment provides useful information about light distribution, such as energy, position, depth of interaction, skewness (deformation due to border effect) etc. A current buffer delivers a copy of each input current to several processing blocks. The current preamplifier is designed in order to achieve unconditional stability under high input capacitance, thus allowing the use of both Photo-Multiplier Tubes (PMT) and Silicon Photo-Multipliers (SiPM). Each processing block implements an analog current filtering by multiplying each input current by a programmable 8-bit coefficient. The latter is implemented through a high linear MOS current divider ladder, whose high sensitivity to variations in output voltages requires the integration of an extremely stable fully differential current collector. Output currents are then summed and sent to the output stage, that provides both a buffered output current and a linear rail-to-rail voltage for further digitalization. Since computation is purely additive, the 64 input channels of AMIC do not represent a limitation in the number of the detector's outputs. Current outputs of various AMIC structures can be combined as inputs of a final AMIC, thus providing a fully expandable structure. In this version of AMIC, 8 programmable blocks for moments calculation are integrated, as well as an I2C interface in order to program every coefficient. Extracted layout simulation results demonstrate that the information provided by moment calculation in AMIC helps to improve tridimensional positioning of the detected event. A two-detector test-bench is now being used for AMIC prototype characterization and preliminary results are presented.

  4. The front-end electronics of the Spectrometer Telescope for Imaging X-Rays (STIX) on the ESA Solar Orbiter satellite

    Science.gov (United States)

    Grimm, O.; Bednarzik, M.; Commichau, V.; Graczyk, R.; Gröbelbauer, H. P.; Hurford, G.; Krucker, S.; Limousin, O.; Meuris, A.; Orleański, P.; Przepiórka, A.; Seweryn, K.; Skup, K.; Viertel, G.

    2012-12-01

    Solar Orbiter is an ESA mission to study the heliosphere in proximity to the Sun, scheduled for launch in January 2017. It carries a suite of ten instruments for comprehensive remote-sensing and in-situ measurements. The Spectrometer Telescope for Imaging X-Rays (STIX), one of the remote sensing instruments, images X-rays between 4 and 150keV using an Fourier technique. The angular resolution is 7 arcsec and the spectral resolution 1keV full-width-half-maximum at 6keV. X-ray detection uses pixelized Cadmium Telluride crystals provided by the Paul Scherrer Institute. The crystals are bonded to read-out hybrids developed by CEA Saclay, called Caliste-SO, incorporating a low-noise, low-power analog front-end ASIC IDeF-X HD. The crystals are cooled to -20°C to obtain very low leakage currents of less than 60pA per pixel, the prerequisite for obtaining the required spectral resolution. This article briefly describes the mission goals and then details the front-end electronics design and main challenges, resulting in part from the allocation limit in mass of 7kg and in power of 4W. Emphasis is placed on the design influence of the cooling requirement within the warm environment of a mission approaching the Sun to within the orbit of Mercury. The design for the long-term in-flight energy calibration is also explained.

  5. Alteration of ASIC1 expression in clear cell renal cell carcinoma

    Directory of Open Access Journals (Sweden)

    Li Y

    2015-08-01

    Full Text Available Yan Li,1 Guoxiong Xu,2 Kai Huang,1 Jun Wang,3 Jihong Zhang,2 Jikai Liu,1 Zhanyu Wang,1 Gang Chen1 1Department of Urology, 2Central Laboratory, Jinshan Hospital, Fudan University, 3Department of Urology, Shanghai First People’s Hospital, Medical College of Shanghai Jiao Tong University, Shanghai, People’s Republic of China Background: Acidic extracellular pH is a major feature of tumor tissue. Acid-sensing ion channels (ASICs represent an H+-gated subgroup of the degenerin/epithelial Na+ channel family and are activated by acidic microenvironment. Little is known about the expression and clinical significance of ASICs in solid tumors. The purpose of this study was to examine the expression of ASIC1 in human clear cell renal cell carcinoma (CCRCC and to determine if the expression of ASIC1 is associated with clinicopathological features.Methods: The expression of ASIC1 in CCRCC tissues at the mRNA and protein levels was determined by real-time quantitative polymerase chain reaction and Western blot analysis, respectively. A tissue microarray was used to assess the expression of ASIC1 protein in tumor tissue and matched adjacent normal tissues from 75 patients with CCRCC.Results: ASIC1 expression was detected in normal renal and CCRCC samples. The expressions of ASIC1 protein and mRNA were significantly decreased in the CCRCC tissues compared with matched normal renal tissues (P<0.05. The staining density measurement showed that the expression of ASIC1 was significantly decreased in stage I (P=0.037, stage II (P=0.026, and stage III (P=0.026, grades I–II CCRCC (P=0.004, and CCRCC from male patients (P=0.00002. However, no significant difference was observed for ASIC1 expression between CCRCC and normal tissue in patients with stage IV CCRCC (P=0.236, patients with grades III–IV CCRCC (P=0.314, and female patients (P=0.095. Spearman correlations demonstrated that ASIC1 expression did not correlate to tumor stage (correlation coefficient [CC

  6. The role of periodontal ASIC3 in orofacial pain induced by experimental tooth movement in rats.

    Science.gov (United States)

    Gao, Meiya; Long, Hu; Ma, Wenqiang; Liao, Lina; Yang, Xin; Zhou, Yang; Shan, Di; Huang, Renhuan; Jian, Fan; Wang, Yan; Lai, Wenli

    2016-12-01

    This study aimed to clarify the roles of Acid-sensing ion channel 3 (ASIC3) in orofacial pain following experimental tooth movement. Sixty male Sprague-Dawley rats were divided into the experimental group (40g, n = 30) and the sham group (0g, n = 30). Closed coil springs were ligated between maxillary incisor and molars to achieve experimental tooth movement. Rat grimace scale (RGS) scores were assessed at 0, 1, 3, 5, 7, and 14 days after the placement of the springs. ASIC3 immunostaining was performed and the expression levels of ASIC3 were measured through integrated optical density/area in Image-Pro Plus 6.0. Moreover, 18 rats were divided into APETx2 group (n = 6), amiloride group (n = 6), and vehicle group (n = 6), and RGS scores were obtained compared among them to verify the roles of ASIC3 in orofacial pain following tooth movement. ASIC3 expression levels became significantly higher in the experimental group than in sham group on 1, 3, and 5 days and became similar on 7 and 14 days. Pain levels (RGS scores) increased in both groups and were significantly higher in the experimental group on 1, 3, 5, and 7 days and were similar on 14 days. Periodontal ASIC3 expression levels were correlated with orofacial pain levels following experimental tooth movement. Periodontal administrations of ASIC3 antagonists (APETx2 and amiloride) could alleviate pain. This study needs to be better evidenced by RNA interference of ASIC3 in periodontal tissues in rats following experimental tooth movement. Moreover, we hope further studies would concentrate on the pain perception of ASIC3 knockout (ASIC3(-/-)) mice. Our results suggest that periodontal ASIC3 plays an important role in orofacial pain induced by experimental tooth movement. © The Author 2015. Published by Oxford University Press on behalf of the European Orthodontic Society. All rights reserved. For permissions, please email: journals.permissions@oup.com.

  7. NIRCA ASIC for the readout of focal plane arrays

    Science.gov (United States)

    Pâhlsson, Philip; Steenari, David; Øya, Petter; Otnes Berge, Hans Kristian; Meier, Dirk; Olsen, Alf; Hasanbegovic, Amir; Altan, Mehmet A.; Najafiuchevler, Bahram; Talebi, Jahanzad; Azman, Suleyman; Gheorghe, Codin; Ackermann, Jörg; Mæhlum, Gunnar; Johansen, Tor Magnus; Stein, Timo

    2016-05-01

    This work is a continuation of our preliminary tests on NIRCA - the Near Infrared Readout and Controller ASIC [1]. The primary application for NIRCA is future astronomical science and Earth observation missions where NIRCA will be used with mercury cadmium telluride image sensors (HgCdTe, or MCT) [2], [3]. Recently we have completed the ASIC tests in the cryogenic environment down to 77 K. We have verified that NIRCA provides to the readout integrated circuit (ROIC) regulated power, bias voltages, and fully programmable digital sequences with sample control of the analogue to digital converters (ADC). Both analog and digital output from the ROIC can be acquired and image data is 8b/10bencoded and delivered via serial interface. The NIRCA also provides temperature measurement, and monitors several analog and digital input channels. The preliminary work confirms that NIRCA is latch-up immune and able to operate down to 77 K. We have tested the performance of the 12-bit ADC with pre-amplifier to have 10.8 equivalent number of bits (ENOB) at 1.4 Msps and maximum sampling speed at 2 Msps. The 1.8-V and 3.3-V output regulators and the 10-bit DACs show good linearity and work as expected. A programmable sequencer is implemented as a micro-controller with a custom instruction set. Here we describe the special operations of the sequencer with regards to the applications and a novel approach to parallel real-time hardware outputs. The test results of the working prototype ASIC show good functionality and performance from room temperature down to 77 K. The versatility of the chip makes the architecture a possible candidate for other research areas, defense or industrial applications that require analog and digital acquisition, voltage regulation, and digital signal generation.

  8. Tunable multiband ferroelectric devices for reconfigurable RF-frontends

    CERN Document Server

    Zheng, Yuliang

    2013-01-01

    Reconfigurable RF-frontends aim to cope with the continuous pursuit of wider frequency coverage, higher efficiency, further compactness and lower cost of ownership. They are expected to lay the foundations of future software defined or cognitive radios. As a potential enabling technology for the frontends, the tunable ferroelectric devices have shown not only enhanced performance but also new functionalities. This book explores the recent developments in the field. It provides a cross-sectional perspective on the interdisciplinary research. With attention to the devices based on ceramic thick-films and crystal thin-films, the book reviews the adapted technologies of material synthesis, film deposition and multilayer circuitry. Next, it highlights the original classes of thin-film ferroelectric devices, including stratified metal-insulator-metal varactors with suppression of acoustic resonance and programmable bi-stable high frequency capacitors. At the end the book analyzes how the frontends can be reformed b...

  9. A prototype hybrid pixel detector ASIC for the CLIC experiment

    CERN Document Server

    Valerio, P; Arfaoui, S; Ballabriga, R; Benoit, M; Bonacini, S; Campbell, M; Dannheim, D; De Gaspari, M; Felici, D; Kulis, S; Llopart, X; Nascetti, A; Poikela, T; Wong, W S

    2014-01-01

    A prototype hybrid pixel detector ASIC specifically designed to the requirements of the vertex detector for CLIC is described and first electrical measurements are presented. The chip has been designed using a commercial 65 nm CMOS technology and comprises a matrix of 64x64 square pixels with 25 μm pitch. The main features include simultaneous 4-bit measure- ment of Time-over-Threshold (ToT) and Time-of-Arrival (ToA) with 10 ns accuracy, on-chip data compression and power pulsing capability.

  10. Planar millimeter wave radar frontend for automotive applications

    Directory of Open Access Journals (Sweden)

    J. Grubert

    2003-01-01

    Full Text Available A fully integrated planar sensor for 77 GHz automotive applications is presented. The frontend consists of a transceiver multichip module and an electronically steerable microstrip patch array. The antenna feed network is based on a modified Rotman-lens and connected to the array in a multilayer approach offering higher integration. Furthermore, the frontend comprises a phase lock loop to allow proper frequency-modulated continuous wave (FMCW radar operation. The latest experimental results verify the functionality of this advanced frontend design featuring automatic cruise control, precrash sensing and cut-in detection. These promising radar measurements give reason to a detailed theoretical investigation of system performance. Employing commercially available MMIC various circuit topologies are compared based on signal-tonoise considerations. Different scenarios for both sequential and parallel lobing hint to more advanced sensor designs and better performance. These improvements strongly depend on the availability of suitable MMIC and reliable packaging technologies. Within our present approach possible future MMIC developments are already considered and, thus, can be easily adapted by the flexible frontend design. Es wird ein integrierter planarer Sensor für 77 GHz Radaranwendungen vorgestellt. Das Frontend besteht aus einem Sende- und Empfangs-Multi-Chip-Modul und einer elektronisch schwenkbaren Antenne. Das Speisenetzwerk der Antenne basiert auf einer modifizierten Rotman- Linse. Für eine kompakte Bauweise sind Antenne und Speisenetzwerk mehrlagig integriert. Weiterhin umfasst das Frontend eine Phasenregelschleife für eine präzise Steuerung des frequenzmodulierten Dauerstrichradars. Die aktuellen Messergebnisse bestätigen die Funktionalit¨at dieses neuartigen Frontend-Designs, das automatische Geschwindigkeitsregelung, Kollisionswarnung sowie Nahbereichsüberwachung ermöglicht. Die Qualität der Messergebnisse hat weiterf

  11. Design of BPS digital frontend for software defined radio receiver

    Institute of Scientific and Technical Information of China (English)

    王洪梅; KIM Jae-hyung; 王法广; LEE Sang-hyuk; 王雪松

    2015-01-01

    In radio receivers, complete implementation of the software defined radio (SDR) concept is mainly limited by frontend. Based on bandpass sampling (BPS) theory, a flexible digital frontend (DFE) platform for SDR receiver is designed. In order to increase the processing speed, Gigabit Ethernet was applied in the platform at speed of 5×108 bit/s. By appropriate design of interpolant according to the position of input RF signals, multi-band receiving can be realized in the platform with suppression more than 35 dB without changing hardware.

  12. CMOS front-end electronics for radiation sensors

    CERN Document Server

    Rivetti, Angelo

    2015-01-01

    This book offers a comprehensive treatment of front-end electronics for radiation detection. It discusses the fundamental principles of signal processing for radiation detectors and describes circuits at the level of functional building blocks, omitting transistor-level implementation. It also covers important system-level topics commonly found in the world of front-end electronics for radiation sensors. The book develops the topics in detail, with a constant focus on practical problems. It also provides real implementation examples that offer insights and stimuli for more experienced engineers already working in the field.

  13. CMS ECAL Front-End boards the XFEST project

    CERN Document Server

    Collard, Caroline; Debraine, A; Decotigny, D; Dobrzynski, L; Karar, A; Regnault, N; Romanteau, T

    2005-01-01

    The Front-End (FE) boards are part of the On-detector electronics system of the CMS electromagnetic calorimeter (ECAL). Their digital functionalities and properties are tested by a dedicated test bench located at Laboratoire Leprince-Ringuet, prior to the board integration in the CMS detector at CERN. XFEST, acronym for eXtended Front-End System Test, is designed to perform tests that can last several hours, on up to 12 FE boards in parallel. The system is designed to deliver 80 tested boards per week. This contribution presents the XFEST set-up and the results of the measurements on FE boards.

  14. The National Ignition Facility front-end laser system

    Energy Technology Data Exchange (ETDEWEB)

    Burkhart, S.C.; Beach, R.J.; Crane, J.H.; Davin, J.M.; Perry, M.D.; Wilcox, R.B.

    1995-07-07

    The proposed National Ignition Facility is a 192 beam Nd:glass laser system capable of driving targets to fusion ignition by the year 2005. A key factor in the flexibility and performance of the laser is a front-end system which provides a precisely formatted beam to each beamline. Each of the injected beams has individually controlled energy, temporal pulseshape, and spatial shape to accommodate beamline-to-beamline variations in gain and saturation. This flexibility also gives target designers the options for precisely controlling the drive to different areas of the target. The design of the Front-End laser is described, and initial results are discussed.

  15. Planar millimeter wave radar frontend for automotive applications

    Science.gov (United States)

    Grubert, J.; Heyen, J.; Metz, C.; Stange, L. C.; Jacob, A. F.

    2003-05-01

    A fully integrated planar sensor for 77 GHz automotive applications is presented. The frontend consists of a transceiver multichip module and an electronically steerable microstrip patch array. The antenna feed network is based on a modified Rotman-lens and connected to the array in a multilayer approach offering higher integration. Furthermore, the frontend comprises a phase lock loop to allow proper frequency-modulated continuous wave (FMCW) radar operation. The latest experimental results verify the functionality of this advanced frontend design featuring automatic cruise control, precrash sensing and cut-in detection. These promising radar measurements give reason to a detailed theoretical investigation of system performance. Employing commercially available MMIC various circuit topologies are compared based on signal-tonoise considerations. Different scenarios for both sequential and parallel lobing hint to more advanced sensor designs and better performance. These improvements strongly depend on the availability of suitable MMIC and reliable packaging technologies. Within our present approach possible future MMIC developments are already considered and, thus, can be easily adapted by the flexible frontend design. Es wird ein integrierter planarer Sensor für 77 GHz Radaranwendungen vorgestellt. Das Frontend besteht aus einem Sende- und Empfangs-Multi-Chip-Modul und einer elektronisch schwenkbaren Antenne. Das Speisenetzwerk der Antenne basiert auf einer modifizierten Rotman- Linse. Für eine kompakte Bauweise sind Antenne und Speisenetzwerk mehrlagig integriert. Weiterhin umfasst das Frontend eine Phasenregelschleife für eine präzise Steuerung des frequenzmodulierten Dauerstrichradars. Die aktuellen Messergebnisse bestätigen die Funktionalit¨at dieses neuartigen Frontend-Designs, das automatische Geschwindigkeitsregelung, Kollisionswarnung sowie Nahbereichsüberwachung ermöglicht. Die Qualität der Messergebnisse hat weiterführende theoretische

  16. Realization of Miniaturized Multi-/Wideband Microwave Front-Ends

    Science.gov (United States)

    Al Shamaileh, Khair A.

    the conventional design with NTLs of wideband matching nature. To bring this concept into practice, the equivalent transmission line model is used for profiling impedance variations. The proposed technique leads to flexible spectrum allocation and matching level. Moreover, the resulting structures are compact and planar. First, the analytical results of three 3-way BPDs of different fractional bandwidths are presented and discussed to validate the proposed approach. Then, two examples of 3- and 5-way BPDs with bandwidths of 4--10 GHz and 5--9 GHz, respectively, are simulated, fabricated, and measured. Simulated and measured results show an acceptable input port matching of below --15 dB and --12.5 dB for the 3- and 5-way dividers, respectively, over the bands of interest. The resulting transmission parameters of the 3- and 5-way dividers are --4.77+/-;1 dB and --7+/-1 dB, respectively, over the design bands; which are in close proximity to their theoretical values. The proposed wideband BPD dividers find many applications in microwave front-end circuitry, especially in only-transmitting antenna subsystems, such as multi-/broad-cast communications, where neither output ports matching nor isolation is a necessity. The third proposed component is a 90° hybrid branch-line coupler (BLC) with multi-/wideband frequency matching. To obtain a multi-frequency operation, NTLs of lengths equal to those in the conventional design are incorporated through the even- and odd-mode analysis. The proposed structure is relatively simple and is fabricated on a single-layered substrate. Two design examples of dual-/triple-frequency BLCs suitable for GSM, WLAN, and Wi-Fi applications are designed, fabricated and evaluated experimentally to validate the proposed methodology. The same concept is extended to realize a broadband BLC with arbitrary coupling levels. Based on how impedances are profiled, the fractional bandwidth of a single-section 90° 3-dB BLC is extended to 57%, and the

  17. Multichannel readout ASIC design flow for high energy physics and cosmic rays experiments

    Science.gov (United States)

    Voronin, A.; Malankin, E.

    2016-02-01

    In the large-scale high energy physics and astrophysics experiments multi-channel readout application specific integrated circuits (ASICs) are widely used. The ASICs for such experiments are complicated systems, which usually include both analog and digital building blocks. The complexity and large number of channels in such ASICs require the proper methodological approach to their design. The paper represents the mixed-signal design flow of the ASICs for high energy physics and cosmic rays experiments. This flow was successfully embedded to the development of the read-out ASIC prototype for the muon chambers of the CBM experiment. The approach was approved in UMC CMOS MMRF 180 nm process. The design flow enable to analyse the mixed-signal system operation on the different levels: functional, behavioural, schematic and post layout including parasitic elements. The proposed design flow allows reducing the simulation period and eliminating the functionality mismatches on the very early stage of the design.

  18. Detector and Front-end electronics for ALICE and STAR silicon strip layers

    CERN Document Server

    Arnold, L; Coffin, J P; Guillaume, G; Higueret, S; Jundt, F; Kühn, C E; Lutz, Jean Robert; Suire, C; Tarchini, A; Berst, D; Blondé, J P; Clauss, G; Colledani, C; Deptuch, G; Dulinski, W; Hu, Y; Hébrard, L; Kucewicz, W; Boucham, A; Bouvier, S; Ravel, O; Retière, F

    1998-01-01

    Detector modules consisting of Silicon Strip Detector (SSD) and Front End Electronics (FEE) assembly have been designed in order to provide the two outer layers of the ALICE Inner Tracker System (ITS) [1] as well as the outer layer of the STAR Silicon Vertex Tracker (SVT) [2]. Several prototypes have beenproduced and tested in the SPS and PS beam at CERN to validate the final design. Double-sided, AC-coupled SSD detectors provided by two different manufacturers and also a pair of single-sided SSD have been asssociated to new low-power CMOS ALICE128C ASIC chips in a new detector module assembly. The same detectors have also been associated to current Viking electronics for reference purpose. These prototype detector modules are described and some first results are presented.

  19. Exploring Many-Core Design Templates for FPGAs and ASICs

    Directory of Open Access Journals (Sweden)

    Ilia Lebedev

    2012-01-01

    Full Text Available We present a highly productive approach to hardware design based on a many-core microarchitectural template used to implement compute-bound applications expressed in a high-level data-parallel language such as OpenCL. The template is customized on a per-application basis via a range of high-level parameters such as the interconnect topology or processing element architecture. The key benefits of this approach are that it (i allows programmers to express parallelism through an API defined in a high-level programming language, (ii supports coarse-grained multithreading and fine-grained threading while permitting bit-level resource control, and (iii reduces the effort required to repurpose the system for different algorithms or different applications. We compare template-driven design to both full-custom and programmable approaches by studying implementations of a compute-bound data-parallel Bayesian graph inference algorithm across several candidate platforms. Specifically, we examine a range of template-based implementations on both FPGA and ASIC platforms and compare each against full custom designs. Throughout this study, we use a general-purpose graphics processing unit (GPGPU implementation as a performance and area baseline. We show that our approach, similar in productivity to programmable approaches such as GPGPU applications, yields implementations with performance approaching that of full-custom designs on both FPGA and ASIC platforms.

  20. Replication of Space-Shuttle Computers in FPGAs and ASICs

    Science.gov (United States)

    Ferguson, Roscoe C.

    2008-01-01

    A document discusses the replication of the functionality of the onboard space-shuttle general-purpose computers (GPCs) in field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The purpose of the replication effort is to enable utilization of proven space-shuttle flight software and software-development facilities to the extent possible during development of software for flight computers for a new generation of launch vehicles derived from the space shuttles. The replication involves specifying the instruction set of the central processing unit and the input/output processor (IOP) of the space-shuttle GPC in a hardware description language (HDL). The HDL is synthesized to form a "core" processor in an FPGA or, less preferably, in an ASIC. The core processor can be used to create a flight-control card to be inserted into a new avionics computer. The IOP of the GPC as implemented in the core processor could be designed to support data-bus protocols other than that of a multiplexer interface adapter (MIA) used in the space shuttle. Hence, a computer containing the core processor could be tailored to communicate via the space-shuttle GPC bus and/or one or more other buses.

  1. DIRAC v2 a DIgital Readout Asic for hadronic Calorimeter

    CERN Document Server

    Gaglione, R; Chefdeville, M; Drancourt, C; Vouters, G

    2009-01-01

    DIRAC is a 64 channel mixed-signal readout integrated circuit designed for Micro-Pattern Gaseous Detectors (MICROMEGAS, Gas Electron Multiplier) or Resistive Plate Chambers. These detectors are foreseen as the active part of a digital hadronic calorimeter for a high energy physics experiment at the International Linear Collider. Physic requirements lead to a highly granular hadronic calorimeter with up to thirty million channels with probably only hit information (digital calorimeter). The DIRAC ASIC has been especially designed for these constraints. Each channel of the DIRAC chip is made of a 4 gains charge preamplifier, a DC-servo loop, 3 switched comparators and a digital memory, thus providing additional energy information for a hit. A bulk MICROMEGAS detector with embedded DIRAC v1 ASIC has been built. The tests of this assembly, both in laboratory with X-Rays and in a beam at CERN are presented, demonstrating the feasibility of a bulk MICROMEGAS detector with embedded electronics. The second version of...

  2. A CMOS ASIC Design for SiPM Arrays.

    Science.gov (United States)

    Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2011-12-01

    Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM).

  3. READOUT ASIC FOR 3D POSITION-SENSITIVE DETECTORS.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; VERNON, E.; ACKLEY, K.; DRAGONE, A.; FRIED, J.; OCONNOR, P.; HE, Z.; HERMAN, C.; ZHANG, F.

    2007-10-27

    We describe an application specific integrated circuit (ASIC) for 3D position-sensitive detectors. It was optimized for pixelated CZT sensors, and it measures, corresponding to an ionizing event, the energy and timing of signals from 121 anodes and one cathode. Each channel provides low-noise charge amplification, high-order shaping, along with peak- and timing-detection. The cathode's timing can be measured in three different ways: the first is based on multiple thresholds on the charge amplifier's voltage output; the second uses the threshold crossing of a fast-shaped signal; and the third measures the peak amplitude and timing from a bipolar shaper. With its power of 2 mW per channel the ASIC measures, on a CZT sensor Connected and biased, charges up to 100 fC with an electronic resolution better than 200 e{sup -} rms. Our preliminary spectral measurements applying a simple cathode/mode ratio correction demonstrated a single-pixel resolution of 4.8 keV (0.72 %) at 662 keV, with the electronics and leakage current contributing in total with 2.1 keV.

  4. SPIROC: design and performances of a dedicated very front-end electronics for an ILC Analog Hadronic CALorimeter (AHCAL) prototype with SiPM read-out

    Science.gov (United States)

    Conforti Di Lorenzo, S.; Callier, S.; Fleury, J.; Dulucq, F.; De la Taille, C.; Chassard, G. Martin; Raux, L.; Seguin-Moreau, N.

    2013-01-01

    For the future e+ e- International Linear Collider (ILC) the ASIC SPIROC (Silicon Photomultiplier Integrated Read-Out Chip) was designed to read out the Analog Hadronic Calorimeter (AHCAL) equipped with Silicon Photomultiplier (SiPM). It is an evolution of the FLC_SiPM chip designed by the OMEGA group in 2005. SPIROC2 [1] was realized in AMS SiGe 0.35 μm technology [2] and developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of read-out channels. This ASIC is a very front-end read-out chip that integrates 36 self triggered channels with variable gain to achieve charge and time measurements. The charge measurement must be performed from 1 up to 2000 photo-electrons (p.e.) corresponding to 160 fC up to 320 pC for SiPM gain 106. The time measurement is performed with a coarse 12-bit counter related to the bunch crossing clock (up to 5 MHz) and a fine time ramp based on this clock (down to 200 ns) to achieve a resolution of 1 ns. An analog memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. The analog memory content (time and charge) is digitized thanks to an internal 12-bit Wilkinson ADC. The data is then stored in a 4kbytes RAM. A complex digital part is necessary to manage all these features and to transfer the data to the DAQ. SPIROC2 is the second generation of the SPIROC ASIC family designed in 2008 by the OMEGA group. A very similar version (SPIROC2c) was submitted in February 2012 to improve the noise performance and also to integrate a new TDC (Time to Digital Converter) structure. This paper describes SPIROC2 and SPIROC2c ASICs and illustrates the main characteristics thank to a series of measurements.

  5. Radiation hardness tests and characterization of the CLARO-CMOS, a low power and fast single-photon counting ASIC in 0.35 micron CMOS technology

    Energy Technology Data Exchange (ETDEWEB)

    Fiorini, M., E-mail: fiorini@fe.infn.it [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Andreotti, M.; Baldini, W.; Calabrese, R. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Carniti, P.; Cassina, L. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Cotta Ramusino, A. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Giachero, A.; Gotti, C. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Luppi, E. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Maino, M. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Malaguti, R. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Pessina, G. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Tomassetti, L. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy)

    2014-12-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. This chip is capable of single-photon counting with multi-anode photomultipliers and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The prototype is realized in AMS 0.35 micron CMOS technology. In the LHCb RICH environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2 (LS2), the ASIC must withstand a total fluence of about 6×10{sup 12} 1 MeV n{sub eq}/cm{sup 2} and a total ionizing dose of 400 krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long term stability of the electronics front-end. The results of multi-step irradiation tests with neutrons and X-rays up to the fluence of 10{sup 14} cm{sup −2} and a dose of 4 Mrad, respectively, are presented, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step. - Highlights: • CLARO chip capable of single-photon counting with 5 ns peaking time. • Chip irradiated up to very high neutron, proton and X-rays fluences, as expected for upgraded LHCb RICH detectors. • No significant performance degradation is observed after irradiation.

  6. Calibration method for direct conversion receiver front-ends

    Directory of Open Access Journals (Sweden)

    R. Müller

    2008-05-01

    Full Text Available Technology induced process tolerances in analog circuits cause device characteristics different from specification. For direct conversion receiver front-ends a system level calibration method is presented. The malfunctions of the devices are compensated by tuning dominant circuit parameters. Thereto optimization techniques are applied which use measurement values and special evaluation functions.

  7. The next generation CBM MVD front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Wiebusch, Michael; Michel, Jan; Klaus, Philipp; Stroth, Joachim [Goethe-Universitaet, Frankfurt (Germany); Collaboration: CBM-MVD-Collaboration

    2015-07-01

    The Micro Vertex Detector (MVD) for the CBM experiment is a highly granular precision tracking device. Due to the ambitious requirements regarding spatial resolution, radiation hardness, read-out speed and material budget, monolithic active pixel sensors (MAPS) are the most suited detector technology for this purpose. A full read-out chain for these sensors was designed and prototyped, comprising a multi-purpose FPGA platform and specialized front-end electronics. During the last year an updated version of the front-end electronics was produced and successfully commissioned. The current front-end electronics incorporate additional configuration and monitoring capabilities which shall be used to optimize the concept of biasing and routing critical analog signals to the sensor. Tests regarding these issues are ongoing. Recent efforts aim at building a quarter of an MVD station with more than a dozen individual MAPS sensors. This requires the adaption of the front-end electronics to the spacial constraints of the set-up. Also the schematics have to be streamlined based on the insights from the abovementioned tests. This contribution presents the outcomes of the adaption and optimization procedures.

  8. Smart front-ends, from vision to design

    NARCIS (Netherlands)

    Roermund, H.M. van; Baltus, P.; Bezooijen, A. van; Hegt, J.A.; Lopelli, E.; Mahmoudi, R.; Radulov, G.I.; Vidojkovic, M.

    2009-01-01

    An integral multi-disciplinary chain optimization based on a high-level cascaded Shannon-based channel modeling is proposed. It is argued that the analog part of the front-end (FE) will become a bottleneck in the overall chain. This requires a FE-centric design approach, aiming for maximizing the ef

  9. Compact wideband CMOS receiver frontends for wireless communication

    NARCIS (Netherlands)

    Blaakmeer, Stephan Carel

    2010-01-01

    There is an increasing demand for wideband receiver frontends. This is due to the emerge of wideband wireless standards (UWB) and due to the desire for flexible radios (SDR), which can comply with multiple existing and future communication standards. Existing receiver topologies are generally narro

  10. An ultra low-power front-end IC for wearable health monitoring system.

    Science.gov (United States)

    Yu-Pin Hsu; Zemin Liu; Hella, Mona M

    2016-08-01

    This paper presents a low-power front-end IC for wearable health monitoring systems. The IC, designed in a standard 0.13μm CMOS technology, fully integrates a low-noise analog front-end (AFE) to process the weak bio-signals, followed by an analog-to-digital converter (ADC) to digitize the extracted signals. An AC-coupled driving buffer, that interfaces between the AFE and the ADC is introduced to scale down the power supply of the ADC. The power consumption decreases by 50% compared to the case without power supply scaling. The AFE passes signals from 0.5Hz to 280Hz and from 0.7Hz to 160Hz with a simulated input referred noise of 1.6μVrms and achieves a maximum gain of 35dB/41dB respectively, with a noise-efficiency factor (NEF) of the AFE is 1. The 8-bit ADC achieves a simulated 7.96-bit resolution at 10KS/s sampling rate under 0.5V supply voltage. The overall system consumes only 0.86μW at dual supply voltages of 1V (AFE) and 0.5 V (ADC).

  11. Tissue acidosis induces neuronal necroptosis via ASIC1a channel independent of its ionic conduction.

    Science.gov (United States)

    Wang, Yi-Zhi; Wang, Jing-Jing; Huang, Yu; Liu, Fan; Zeng, Wei-Zheng; Li, Ying; Xiong, Zhi-Gang; Zhu, Michael X; Xu, Tian-Le

    2015-11-02

    Acidotoxicity is common among neurological disorders, such as ischemic stroke. Traditionally, Ca(2+) influx via homomeric acid-sensing ion channel 1a (ASIC1a) was considered to be the leading cause of ischemic acidotoxicity. Here we show that extracellular protons trigger a novel form of neuronal necroptosis via ASIC1a, but independent of its ion-conducting function. We identified serine/threonine kinase receptor interaction protein 1 (RIP1) as a critical component of this form of neuronal necroptosis. Acid stimulation recruits RIP1 to the ASIC1a C-terminus, causing RIP1 phosphorylation and subsequent neuronal death. In a mouse model of focal ischemia, middle cerebral artery occlusion causes ASIC1a-RIP1 association and RIP1 phosphorylation in affected brain areas. Deletion of the Asic1a gene significantly prevents RIP1 phosphorylation and brain damage, suggesting ASIC1a-mediated RIP1 activation has an important role in ischemic neuronal injury. Our findings indicate that extracellular protons function as a novel endogenous ligand that triggers neuronal necroptosis during ischemia via ASIC1a independent of its channel function.

  12. Radiation-hard ASICs for optical data transmission in the first phase of the LHC upgrade

    CERN Document Server

    Gan, K K; Kagan, H P; Kass, R D; Moore, J R; Smith, D S; Wiese, A; Ziolkowskic, M; 10.1088/1748-0221/5/12/C12006

    2010-01-01

    We have designed two ASICs for possible applications in the optical links of a new layer of the pixel detector to be install inside the ATLAS Pixel detector for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for the VCSEL and a receiver/decoder to decode the signal received at the PIN diode to extract the data and clock. Both ASICs contain 4 channels for operation with a VCSEL or PIN array. The ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated ASICs and the performance of the ASICs is satisfactory. The receiver/decoder can properly decode the bi-phase marked input stream with low PIN current and the driver can operate a VCSEL up to ~ 5 Gb/s. The added functionalities are also successful, including redundancy to bypass a broken VCSEL or PIN channel, individual control of VCSEL current, and power-on reset circuit to set all VCSEL currents to a nominal value. The ASICs were irradiated to a dose of 46 Mrad ...

  13. A 1.2-V CMOS front-end for LTE direct conversion SAW-less receiver

    Science.gov (United States)

    Riyan, Wang; Jiwei, Huang; Zhengping, Li; Weifeng, Zhang; Longyue, Zeng

    2012-03-01

    A CMOS RF front-end for the long-term evolution (LTE) direct conversion receiver is presented. With a low noise transconductance amplifier (LNA), current commutating passive mixer and transimpedance operational amplifier (TIA), the RF front-end structure enables high-integration, high linearity and simple frequency planning for LTE multi-band applications. Large variable gain is achieved using current-steering transconductance stages. A current commutating passive mixer with 25% duty-cycle LO improves gain, noise and linearity. A direct coupled current-input filter (DCF) is employed to suppress the out-of-band interferer. Fabricated in a 0.13-μm CMOS process, the RF front-end achieves a 45 dB conversion voltage gain, 2.7 dB NF, -7 dBm IIP3, and +60 dBm IIP2 with calibration from 2.3 to 2.7 GHz. The total RF front end with divider draws 40 mA from a single 1.2-V supply.

  14. Reconfigurable ASIC for a Low Level Trigger System in Cherenkov Telescope Cameras

    CERN Document Server

    Gascon, David; Blanch, Oscar; Boix, Joan; Delagnes, Eric; Delgado, Carlos; Freixas, Lluís; Guilloux, Fabrice; López-Coto, Rubén; Griffiths, Scott; Martínez, Gustavo; Martínez, Oscar; Sanuy, Andreu; Tejedor, Luis Ángel

    2016-01-01

    A versatile and reconfigurable ASIC is presented, which implements two different concepts of low level trigger (L0) for Cherenkov telescopes: the Majority trigger (sum of discriminated inputs) and the Sum trigger concept (analogue clipped sum of inputs). Up to 7 input signals can be processed following one or both of the previous trigger concepts. Each differential pair output of the discriminator is also available as a LVDS output. Differential circuitry using local feedback allows the ASIC to achieve high speed (500 MHz) while maintaining good linearity in a 1 Vpp range. Experimental results are presented. A number of prototype camera designs of the Cherenkov Telescope Array (CTA) project will use this ASIC.

  15. ASIC Design of Floating-Point FFT Processor

    Institute of Scientific and Technical Information of China (English)

    陈禾; 赵忠武

    2004-01-01

    An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.

  16. A Unified Mutual Coupling Model for Multiple Antenna Systems

    Institute of Scientific and Technical Information of China (English)

    WU Yu-jiang; NIE Zai-ping

    2006-01-01

    A unified mutual coupling model for multiple antenna communication systems based on moment methods is proposed. This model combines antenna coupling and RF front-end circuit coupling, thus providing a more accurate and complete analysis of the mutual coupling effect on multiple antenna systems.

  17. An analog front-end circuit for ISO/IEC 15693-compatible RFID transponder IC

    Institute of Scientific and Technical Information of China (English)

    LIU Dong-sheng; ZOU Xue-cheng; YANG Qiu-ping; XIONG Ting-wen

    2006-01-01

    The 13.56 MHz analog front-end circuit for ISO/IEC 15693-compatible radio frequency identification (RFID) transponder IC presented in this paper converts RF power to DC and extracts clock and data from the interrogator by 10% or 100% ASK modulation. The transponder sends data back to the interrogator by load modulation technology. The electrostatic discharge (ESD)protection circuits function to limit RF voltage to a safe level. An inductive coupling simulation modelling for 13.56 MHz RFID system is presented, with simulation results showing that the transponder operates over a wide range of electromagnetic field strength from Hmin (150 mA/m) to Hmax (5 A/m). The transponder IC is implemented in SMIC 0.35-μm three-metal two-poly mixed signal CMOS technology with embedded EEPROM.

  18. Wide Temperature Rad-Hard ASIC for Process Control of a Fuel Cell System Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group developed a top-level design of a rad-hard application-specific integrated circuit (ASIC) for spacecraft power management that is functional over a...

  19. Structure and erosion resistance ofNi60A/SiC coatting by laser cladding

    Institute of Scientific and Technical Information of China (English)

    LOU Bai-yang; CHEN Zhen; BAI Wan-jin; DONG Gang

    2006-01-01

    The Ni60A and Ni60A/SiC coatings were obtained by laser cladding on 0.45% C steel. The microstructure and hardness of the coatings were studied by SEM and XRD. The erosion resistances of Ni60A and Ni60A/SiC coatings were also investigated. The results show that the structure of different coatings is up to the temperature gradient and solidifying velocity in metal-melting region during laser cladding process. The coatings consist of a cladding layer, in which dendritic crystal and bulky cell-like crystal exist mainly, and a thermo-affected layer. Ni60A/SiC coating has higher microhardness than that of Ni60A coating, which is mainly caused by SiC and complicated phases formed by Ni, Cr, Fe, C and Si. It is obvious from the erosion test that the Ni60A/SiC coating has high erosion resistance.

  20. High-Speed, Low Power 256 Channel Gamma Radiation Array Detector ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Building on prior success in detector electronics, we propose to design and fabricate a 256 channel readout ASIC for solid state gamma radiation array detectors...

  1. Acid-sensing ion channel (ASIC) structure and function: Insights from spider, snake and sea anemone venoms.

    Science.gov (United States)

    Cristofori-Armstrong, Ben; Rash, Lachlan D

    2017-04-27

    Acid-sensing ion channels (ASICs) are proton-activated cation channels that are expressed in a variety of neuronal and non-neuronal tissues. As proton-gated channels, they have been implicated in many pathophysiological conditions where pH is perturbed. Venom derived compounds represent the most potent and selective modulators of ASICs described to date, and thus have been invaluable as pharmacological tools to study ASIC structure, function, and biological roles. There are now ten ASIC modulators described from animal venoms, with those from snakes and spiders favouring ASIC1, while the sea anemones preferentially target ASIC3. Some modulators, such as the prototypical ASIC1 modulator PcTx1 have been studied in great detail, while some of the newer members of the club remain largely unstudied. Here we review the current state of knowledge on venom derived ASIC modulators, with a particular focus on their molecular interaction with ASICs, what they have taught us about channel structure, and what they might still reveal about ASIC function and pathophysiological roles. Copyright © 2017 Elsevier Ltd. All rights reserved.

  2. ASIC2 is present in human mechanosensory neurons of the dorsal root ganglia and in mechanoreceptors of the glabrous skin.

    Science.gov (United States)

    Cabo, R; Alonso, P; Viña, E; Vázquez, G; Gago, A; Feito, J; Pérez-Moltó, F J; García-Suárez, O; Vega, J A

    2015-03-01

    Mechanosensory neurons lead to the central nervous system touch, vibration and pressure sensation. They project to the periphery and form different kinds of mechanoreceptors. The manner in which they sense mechanical signals is still not fully understood, but electrophysiological experiments have suggested that this may occur through the activation of ion channels that gate in response to mechanical stimuli. The acid-sensing ion channels (ASICs), especially ASIC2, may function as mechanosensors or are required for mechanosensation, and they are expressed in both mechanosensory neurons and mechanoreceptors. Here, we have used double immunohistochemistry for ASIC2 together with neuronal and glial markers associated with laser confocal microscopy and image analysis, to investigate the distribution of ASIC2 in human lumbar dorsal root ganglia, as well as in mechanoreceptors of the hand and foot glabrous skin. In lumbar dorsal root ganglia, ASIC2 immunoreactive neurons were almost all intermediate or large sized (mean diameter ≥20-70 µm), and no ASIC2 was detected in the satellite glial. ASIC2-positive axons were observed in Merkel cell-neurite complexes, Meissner and Pacinian corpuscles, all of them regarded as low-threshold mechanoreceptors. Moreover, a variable percent of Meissner (8 %) and Pacinian corpuscles (27 %) also displayed ASIC2 immunoreactivity in the Schwann-related cells. These results demonstrate the distribution of ASIC2 in the human cutaneous mechanosensory system and suggest the involvement of ASIC2 in mechanosensation.

  3. Novel Front-end Electronics for Time Projection Chamber Detectors

    CERN Document Server

    García García, Eduardo José

    This work has been carried out in the European Organization for Nuclear Research (CERN) and it was supported by the European Union as part of the research and development towards the European detector the (EUDET) project, specifically for the International Linear Collider (ILC). In particle physics there are several different categories of particle detectors. The presented design is focused on a particular kind of tracking detector called Time Projection Chamber (TPC). The TPC provides a three dimensional image of electrically charged particles crossing a gaseous volume. The thesis includes a study of the requirements for future TPC detectors summarizing the parameters that the front-end readout electronics must fulfill. In addition, these requirements are compared with respect to the readouts used in existing TPC detectors. It is concluded that none of the existing front-end readout designs fulfill the stringent requirements. The main requirements for future TPC detectors are high integration, an increased n...

  4. Pixel front-end development in 65 nm CMOS technology

    CERN Document Server

    Havránek, M; Kishishita, T; Krüger, H; Wermes, N

    2014-01-01

    Luminosity upgrade of the LHC (HL-LHC) imposes severe constraints on the detector tracking systems in terms of radiation hardness and capability to cope with higher hit rates. One possible way of keeping track with increasing luminosity is the usage of more advanced technologies. Ultra deep sub-micron CMOS technologies allow a design of complex and high speed electronics with high integration density. In addition, these technologies are inherently radiation hard. We present a prototype of analog pixel front-end integrated circuit designed in 65 nm CMOS technology with applications oriented towards the ATLAS Pixel Detector upgrade. The aspects of ultra deep sub-micron design and performance of the analog pixel front-end circuits will be discussed.

  5. RF-Frontend Design for Process-Variation-Tolerant Receivers

    CERN Document Server

    Sakian, Pooyan; van Roermund, Arthur

    2012-01-01

    This book discusses a number of challenges faced by designers of wireless receivers, given complications caused by the shrinking of electronic and mobile devices circuitry into ever-smaller sizes and the resulting complications on the manufacturability, production yield, and the end price of the products.  The authors describe the impact of process technology on the performance of the end product and equip RF designers with countermeasures to cope with such problems.  The mechanisms by which these problems arise are analyzed in detail and novel solutions are provided, including design guidelines for receivers with robustness to process variations and details of circuit blocks that obtain the required performance level. Describes RF receiver frontends and their building blocks from a system- and circuit-level perspective; Provides system-level analysis of a generic RF receiver frontend with robustness to process variations; Includes details of CMOS circuit design at 60GHz and reconfigurable circuits at 60GHz...

  6. Knockdown of acid-sensing ion channel 1a (ASIC1a) suppresses disease phenotype in SCA1 mouse model.

    Science.gov (United States)

    Vig, Parminder J S; Hearst, Scoty M; Shao, Qingmei; Lopez, Maripar E

    2014-08-01

    The mutated ataxin-1 protein in spinocerebellar ataxia 1 (SCA1) targets Purkinje cells (PCs) of the cerebellum and causes progressive ataxia due to loss of PCs and neurons of the brainstem. The exact mechanism of this cellular loss is still not clear. Currently, there are no treatments for SCA1; however, understanding of the mechanisms that regulate SCA1 pathology is essential for devising new therapies for SCA1 patients. We previously established a connection between the loss of intracellular calcium-buffering and calcium-signalling proteins with initiation of neurodegeneration in SCA1 transgenic (Tg) mice. Recently, acid-sensing ion channel 1a (ASIC1a) have been implicated in calcium-mediated toxicity in many brain disorders. Here, we report generating SCA1 Tg mice in the ASIC1a knockout (KO) background and demonstrate that the deletion of ASIC1a gene expression causes suppression of the SCA1 disease phenotype. Loss of the ASIC1a channel in SCA1/ASIC1a KO mice resulted in the improvement of motor deficit and decreased PC degeneration. Interestingly, the expression of the ASIC1 variant, ASIC1b, was upregulated in the cerebellum of both SCA1/ASIC1a KO and ASIC1a KO animals as compared to the wild-type (WT) and SCA1 Tg mice. Further, these SCA1/ASIC1a KO mice exhibited translocation of PC calcium-binding protein calbindin-D28k from the nucleus to the cytosol in young animals, which otherwise have both cytosolic and nuclear localization. Furthermore, in addition to higher expression of calcium-buffering protein parvalbumin, PCs of the older SCA1/ASIC1a KO mice showed a decrease in morphologic abnormalities as compared to the age-matched SCA1 animals. Our data suggest that ASIC1a may be a mediator of SCA1 pathogenesis and targeting ASIC1a could be a novel approach to treat SCA1.

  7. A 15 GSa/s, 1.5 GHz Bandwidth Waveform Digitizing ASIC

    CERN Document Server

    Oberla, E; Grabas, H; Frisch, H; Nishimura, K; Varner, G

    2013-01-01

    The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13 micron CMOS process. On each of 6 analog channels, PSEC4 employs a switched capacitor array (SCA) 256 samples deep, a ramp-compare ADC with 10.5 bits of DC dynamic range, and a serial data readout with the capability of region-of-interest windowing to reduce dead time. The sampling rate can be adjusted between 4 and 15 Gigasamples/second [GSa/s] on all channels and is servo-controlled on-chip with a low-jitter delay-locked loop (DLL). The input signals are passively coupled on-chip with a -3 dB analog bandwidth of 1.5 GHz. The power consumption in quiescent sampling mode is less than 50 mW/chip; at a sustained trigger and readout rate of 50 kHz the chip draws 100 mW. After fixed-pattern pedestal subtraction, the uncorrected integral non-linearity is 0.15% over an 750 mV dynamic range. With a linearity correction, a full ...

  8. A 15 GSa/s, 1.5 GHz bandwidth waveform digitizing ASIC

    Science.gov (United States)

    Oberla, Eric; Genat, Jean-Francois; Grabas, Hervé; Frisch, Henry; Nishimura, Kurtis; Varner, Gary

    2014-01-01

    The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13 μm CMOS process. On each of the six analog channels, PSEC4 employs a switched capacitor array (SCA) of 256 samples deep, a ramp-compare ADC with 10.5 bits of DC dynamic range, and a serial data readout with the capability of region-of-interest windowing to reduce dead time. The sampling rate can be adjusted between 4 and 15 Gigasamples/second (GSa/s) on all channels and is servo-controlled on-chip with a low-jitter delay-locked loop (DLL). The input signals are passively coupled on-chip with a -3 dB analog bandwidth of 1.5 GHz. The power consumption in quiescent sampling mode is less than 50 mW/chip; at a sustained trigger and a readout rate of 50 kHz the chip draws 100 mW. After fixed-pattern pedestal subtraction, the uncorrected integral non-linearity is 0.15% over a 750 mV dynamic range. With a linearity correction, a full 1 V signal voltage range is available. The sampling timebase has a fixed-pattern non-linearity with an RMS of 13%, which can be corrected for precision waveform feature extraction and timing.

  9. A 15 GSa/s, 1.5 GHz bandwidth waveform digitizing ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Oberla, Eric, E-mail: ejo@uchicago.edu [Enrico Fermi Institute, University of Chicago, 5640 S. Ellis Avenue, Chicago, IL 60637 (United States); Genat, Jean-Francois; Grabas, Hervé; Frisch, Henry [Enrico Fermi Institute, University of Chicago, 5640 S. Ellis Avenue, Chicago, IL 60637 (United States); Nishimura, Kurtis; Varner, Gary [University of Hawai' i at Manoa, Watanabe Hall, 2505 Correa Road, Honolulu, HI (United States)

    2014-01-21

    The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13μm CMOS process. On each of the six analog channels, PSEC4 employs a switched capacitor array (SCA) of 256 samples deep, a ramp-compare ADC with 10.5 bits of DC dynamic range, and a serial data readout with the capability of region-of-interest windowing to reduce dead time. The sampling rate can be adjusted between 4 and 15 Gigasamples/second (GSa/s) on all channels and is servo-controlled on-chip with a low-jitter delay-locked loop (DLL). The input signals are passively coupled on-chip with a −3 dB analog bandwidth of 1.5 GHz. The power consumption in quiescent sampling mode is less than 50 mW/chip; at a sustained trigger and a readout rate of 50 kHz the chip draws 100 mW. After fixed-pattern pedestal subtraction, the uncorrected integral non-linearity is 0.15% over a 750 mV dynamic range. With a linearity correction, a full 1 V signal voltage range is available. The sampling timebase has a fixed-pattern non-linearity with an RMS of 13%, which can be corrected for precision waveform feature extraction and timing.

  10. Local ASIC3 modulates pain and disease progression in a rat model of osteoarthritis

    Directory of Open Access Journals (Sweden)

    Izumi Masashi

    2012-08-01

    Full Text Available Abstract Background Recent data have suggested a relationship between acute arthritic pain and acid sensing ion channel 3 (ASIC3 on primary afferent fibers innervating joints. The purpose of this study was to clarify the role of ASIC3 in a rat model of osteoarthritis (OA which is considered a degenerative rather than an inflammatory disease. Methods We induced OA via intra-articular mono-iodoacetate (MIA injection, and evaluated pain-related behaviors including weight bearing measured with an incapacitance tester and paw withdrawal threshold in a von Frey hair test, histology of affected knee joint, and immunohistochemistry of knee joint afferents. We also assessed the effect of ASIC3 selective peptide blocker (APETx2 on pain behavior, disease progression, and ASIC3 expression in knee joint afferents. Results OA rats showed not only weight-bearing pain but also mechanical hyperalgesia outside the knee joint (secondary hyperalgesia. ASIC3 expression in knee joint afferents was significantly upregulated approximately twofold at Day 14. Continuous intra-articular injections of APETx2 inhibited weight distribution asymmetry and secondary hyperalgesia by attenuating ASIC3 upregulation in knee joint afferents. Histology of ipsilateral knee joint showed APETx2 worked chondroprotectively if administered in the early, but not late phase. Conclusions Local ASIC3 immunoreactive nerve is strongly associated with weight-bearing pain and secondary hyperalgesia in MIA-induced OA model. APETx2 inhibited ASIC3 upregulation in knee joint afferents regardless of the time-point of administration. Furthermore, early administration of APETx2 prevented cartilage damage. APETx2 is a novel, promising drug for OA by relieving pain and inhibiting disease progression.

  11. ASIC3, an acid-sensing ion channel, is expressed in metaboreceptive sensory neurons

    Directory of Open Access Journals (Sweden)

    Fierro Leonardo

    2005-11-01

    Full Text Available Abstract Background ASIC3, the most sensitive of the acid-sensing ion channels, depolarizes certain rat sensory neurons when lactic acid appears in the extracellular medium. Two functions have been proposed for it: 1 ASIC3 might trigger ischemic pain in heart and muscle; 2 it might contribute to some forms of touch mechanosensation. Here, we used immunocytochemistry, retrograde labelling, and electrophysiology to ask whether the distribution of ASIC3 in rat sensory neurons is consistent with either of these hypotheses. Results Less than half (40% of dorsal root ganglion sensory neurons react with anti-ASIC3, and the population is heterogeneous. They vary widely in cell diameter and express different growth factor receptors: 68% express TrkA, the receptor for nerve growth factor, and 25% express TrkC, the NT3 growth factor receptor. Consistent with a role in muscle nociception, small ( Conclusion Our data indicates that: 1 ASIC3 is expressed in a restricted population of nociceptors and probably in some non-nociceptors; 2 co-expression of ASIC3 and CGRP, and the absence of P2X3, are distinguishing properties of a class of sensory neurons, some of which innervate blood vessels. We suggest that these latter afferents may be muscle metaboreceptors, neurons that sense the metabolic state of muscle and can trigger pain when there is insufficient oxygen.

  12. Energy resolution of a silicon detector with the RX64 ASIC designed for X-ray imaging

    Energy Technology Data Exchange (ETDEWEB)

    Bollini, D.; Cabal Rodriguez, A.E.; Dabrowski, W.; Diaz Garcia, A.; Gambaccini, M.; Giubellino, P.; Grybos, P.; Idzik, M.; Marzari-Chiesa, A.; Montano, L.M.; Prino, F.; Ramello, L. E-mail: ramello@to.infn.it; Sitta, M.; Swientek, K.; Wheadon, R.; Wiacek, P

    2003-12-11

    Results from a silicon microstrip detector coupled to the RX64 ASIC are presented. The system is capable of single photon counting in digital X-ray imaging, with foreseen applications to dual energy mammography and angiography. The main features of the detecting system are low noise (operation with threshold as low as {approx}4 keV is possible), good spatial resolution (a pixel of 100 {mu}mx300 {mu}m when oriented edge-on) and good counting rate capability (up to one million counts per channel with a maximum rate of about 200 kHz per channel). The energy resolution of the system, as obtained with several fluorescence X-ray lines, is described.

  13. An Enhanced Front-End Algorithm for Reducing Channel Change Time in DVB-T System

    Science.gov (United States)

    Joe, Inwhee; Choi, Jongsung

    To address the low performance for channel scanning in the DVB-T system, we propose an enhanced front-end algorithm in this paper. The proposed algorithm consists of Auto Scan and Normal Scan, which is a part of the tuning algorithm for front-end (tuner) drivers in the DVB-T receiver. The key idea is that the frequency offset is saved when performing Auto Scan in order to reduce the channel change time for Normal Scan. In addition, the results of a performance evaluation demonstrate that our enhanced front-end algorithm improves the performance of channel scanning significantly, as compared to the generic front-end algorithm.

  14. ASIC Design and Implementation for Digital Pulse Compression Chip

    Institute of Scientific and Technical Information of China (English)

    高俊峰; 韩月秋; 王巍

    2004-01-01

    A novel ASIC design of changeable-point digital pulse compression (DPC) chip is presented. System hardware resource is reduced to one third of the traditional design method through operations sharing hardware, i.e. let FFT, complex multiplication and IFFT be fulfilled with the same hardware structure. Block-floating-point scaling is used to enhance the dynamic range and computation accuracy. This design applies parallel pipeline structure and the radix-4 butterfly operation to improve the processing speed. In addition, a triple-memory-space(TMS) configuration is used that allows input, computation and output operations to be overlapped, so that the dual-butterfly unit is never left in an idle state waiting for I/O operation. The whole design is implemented with only one chip of XC2V500-5 FPGA. It can implement 1 024-point DPC within 91.6 μs.The output data is converted to floating-point formation to achieve seamless interface with TMS320C6701. The validity of the design is verified by simulation and measurement results.

  15. ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

    Science.gov (United States)

    Vasile, Stefan; Lipson, Jerold

    2012-01-01

    The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

  16. VeloPix ASIC development for LHCb VELO upgrade

    CERN Document Server

    van Beuzekom, M; Campbell, M; Collins, P; Gromov, V; Kluit, R; Llopart, X; Poikela, T; Wyllie, K; Zivkovic, V

    2013-01-01

    The upgrade of the LHCb experiment, planned for 2018, will transform the readout of the entire experiment to a triggerless system operating at 40 MHz. All data reduction algorithms will be run in a high level software farm, and will have access to event information from all subdetectors. This approach will give great power and fl exibility in accessing the physics channels of interest in the future, in particular the identi fi cation of fl avour tagged events with displaced vertices. The data acquisition and front end electronics systems require signi fi cant modi fi cation to cope with the enormous throughput of data. For the silicon vertex locator (VELO) a dedicated development is underway for a new ASIC, VeloPix, which will be a derivative of the Timepix/Medipix family of chips. The chip will be radiation hard and be able to cope with pixel hit rates of above 500 MHz, highly non-uniformly distributed over the 2 cm 2 chip area. The chip will incorporate local intelligence in the pixels for time-over-thresho...

  17. Skiroc A Front-end Chip to Read Out the Imaging Silicon-Tungsten Calorimeter for ILC

    CERN Document Server

    Bouchel, Michel; Fleury, Julien; de La Taille, Christophe; Martin-Chassard,Gisèle; Raux, Ludovic; Wicek, Francois; Bohner, Gérard; Gay, Pascal; Lecoq, Jacques; Manen, Samuel; Royer, Laurent

    2007-01-01

    Integration and low-power consumption of the read-out ASIC for the International Linear Collider (ILC) 82-millionchannel W-Si calorimeter must reach an unprecedented level as it will be embedded inside the detector. Uniformity and dynamic range performance has to reach the accuracy to achieve calorimetric measurement. A first step towards this goal has been a 10,000-channel physics prototype of 18*18 cm which is currently in test beam in CERN. A new version of a full integrated read out chip (SKIROC) has been designed to equip the technologic prototype to be built for 2009. Based on the running physics prototype ASIC (FLC_PHY3), it embeds most of the required features expected for the final detector. The dynamic range has been improved from 500 to 2000 MIP. An auto-trigger capability has been added allowing built-in zero suppress. The number of channel has been doubled reaching 36 to fit smaller silicon pads and the lownoise charge preamplifier now accepts both AC and DC coupled detectors. After an exhaustive...

  18. A CMOS frontend chip for implantable neural recording with wide voltage supply range

    Science.gov (United States)

    Jialin, Liu; Xu, Zhang; Xiaohui, Hu; Yatao, Guo; Peng, Li; Ming, Liu; Bin, Li; Hongda, Chen

    2015-10-01

    A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC). The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits (ENOB) of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 (including pads). In-vitro recording was successfully carried out by the proposed frontend chip. Project supported by the National Natural Science Foundation of China (Nos. 61474107, 61372060, 61335010, 61275200, 61178051) and the Key Program of the Chinese Academy of Sciences (No. KJZD-EW-L11-01).

  19. New and Efficient Neutrino Factory Front-End Design

    CERN Document Server

    Gallardo, Juan C; Kirk, Harold G; Neuffer, David V; Palmer, Robert; Paul, Kevin; Scott Berg, J

    2005-01-01

    As part of the APS Joint Study on the Future of Neutrino Physics* we have carried out detailed studies of the Neutrino Factory front-end. A major goal of the new study was to achieve equal performance to our earlier feasibility studies** at reduced cost. The optimal channel design is described in this paper. New innovations included an adiabatic buncher for phase rotation and a simplified cooling channel with LiH absorbers. The linear channel is 295 m long and produces 0.17 muons per proton on target into the assumed accelerator transverse acceptance of 30 mm and longitudinal acceptance of 150 mm.

  20. Wideband monolithically integrated front-end subsystems and components

    Science.gov (United States)

    Mruk, Joseph Rene

    This thesis presents the analysis, design, and measurements of passive, monolithically integrated, wideband recta-coax and printed circuit board front-end components. Monolithic fabrication of antennas, impedance transformers, filters, and transitions lowers manufacturing costs by reducing assembly time and enhances performance by removing connectors and cabling between the devices. Computational design, fabrication, and measurements are used to demonstrate the capabilities of these front-end assemblies. Two-arm wideband planar log-periodic antennas fed using a horizontal feed that allows for filters and impedance transformers to be readily fabricated within the radiating region of the antenna are demonstrated. At microwave frequencies, low-cost printed circuit board processes are typically used to produce planar devices. A 1.8 to 11 GHz two-arm planar log-periodic antenna is designed with a monolithically integrated impedance transformer. Band rejection methods based on modifying the antenna aperture, use of an integrated filter, and the application of both methods are investigated with realized gain suppressions of over 25 dB achieved. The ability of standard circuit board technology to fabricate millimeter-wave devices up to 110 GHz is severely limited. Thin dielectrics are required to prevent the excitation of higher order modes in the microstrip substrate. Fabricating the thin line widths required for the antenna aperture also becomes prohibitively challenging. Surface micro-machining typically used in the fabrication of MEMS devices is capable of producing the extremely small features that can be used to fabricate antennas extending through W-band. A directly RF fed 18 to 110 GHz planar log-periodic antenna is developed. The antenna is fabricated with an integrated impedance transformer and additional transitions for measurement characterization. Singly terminated low-loss wideband millimeter-wave filters operating over V- and W- band are developed. High

  1. New RPC front-end electronics for hades

    CERN Document Server

    Gil, Alejandro; Cabanelas, P; Díaz, J; Garzón, J A; González-Díaz, D; König, W; Lange, J S; Marín, J; Montes, N; Skott, P; Traxler, M

    2007-01-01

    Time-of-flight (TOF) detectors are mainly used for both particle identification and triggering. Resistive Plate Chamber (RPC) detectors are becoming widely used because of their excellent TOF capabilities and reduced cost. The new ESTRELA* RPC wall, which is being installed in the HADES detector at Darmstadt GSI, will contain 1024 RPC modules, covering an active area of around 7 m2. It has excellent TOF and good charge resolutions. Its Front-End electronics is based on a 8-layer Mother-Board providing impedance matched paths for the output signals of each of the eight 4-channel Daughter-Boards to the TDC.

  2. Structuring front-end innovation activities throughout strategic product planning

    Directory of Open Access Journals (Sweden)

    Thaisa Rodrigues

    Full Text Available Abstract Strategic product planning (SPP for new product development (NPD in the front-end of innovation (FEI is a great challenge for managers and practitioners. This article analyzes the structuring process of FEI activities during SPP. A research was carried out with 78 industries from both food and furniture in Brazil. Our study revealed that FEI activities are structured in an intricate network with a high level of complexity and interdependence. The large amount of activities and the complexity in structuring them denote that companies are concerned to reduce uncertainties and risks intensifying the planning phase.

  3. Front-end electronics for the CMS preshower detector

    CERN Document Server

    Go, A; Barney, D; Bloch, P; Peisert, Anna; Löfstedt, B; Reynaud, S; Borkar, S; Lalwani, S

    2002-01-01

    The front-end readout system PACE2 for the CMS preshower detector consists of two chips: Delta is a 32 channel preamplifier and shaper that provides low noise, charge to voltage readout for large capacitive silicon sensors over a large dynamic range (up to 400 MIPs); PACE-AM contains a 32-channel wide, 160-cell deep, analog memory with a 32 to 1 multiplexer for serial readout. These chips are designed in .8 mu m BiCMOS DMILL radiation tolerant technology. The performance in terms of dynamic range, linearity, noise, peaking time and memory uniformity are presented. (4 refs).

  4. Front-end electronics for the FAZIA experiment

    Science.gov (United States)

    Salomon, F.; Edelbruck, P.; Brulin, G.; Borderie, B.; Richard, A.; Rivet, M. F.; Verde, G.; Wanlin, E.; Boiano, A.; Tortone, G.; Poggi, G.; Bini, M.; Casini, G.; Barlini, S.; Pasquali, G.; Valdré, S.; Petcu, M.; Bougault, R.; Le Neindre, N.; Alba, R.; Bonnet, E.; Bruno, M.; Chbihi, A.; Cinausero, M.; Dell'Aquila, D.; De Préaumont, H.; Duenas, J. A.; Fable, Q.; Fabris, D.; Francalanza, L.; Frankland, J. D.; Galichet, E.; Gramegna, F.; Gruyer, D.; Guerzoni, M.; Kordyasz, A.; Kozik, T.; La Torre, R.; Lombardo, I.; Lopez, O.; Mabiala, J.; Maiolino, C.; Marchi, T.; Maurenzig, P.; Meoli, A.; Merrer, Y.; Morelli, L.; Nannini, A.; Olmi, A.; Ordine, A.; Pârlog, M.; Pastore, G.; Piantelli, S.; Rosato, E.; Santonocito, D.; Scarlini, E.; Spadacini, G.; Stefaninni, A.; Vient, E.; Vigilante, M.

    2016-01-01

    FAZIA is a multidetector specifically designed to optimize A and Z reaction product identification in heavy-ion collision experiments. This multidetector is modular and based on three-layer telescopes made of two silicon detectors followed by a thick (10 cm) CsI(Tl) scintillator read-out by a photodiode. Its electronics is fully digital. The goal to push at maximum identification capability while preserving excellent energy resolution, can be achieved by using pulse-shape analysis techniques and by making an intensive use of high-speed flash ADCs. This paper presents the front-end part of the electronics.

  5. Instrument Front-Ends at Fermilab During Run II

    CERN Document Server

    Meyer, Thomas; Voy, Duane; 10.1088/1748-0221/6/11/T11004

    2012-01-01

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  6. Instrument Front-Ends at Fermilab During Run II

    Energy Technology Data Exchange (ETDEWEB)

    Meyer, Thomas; Slimmer, David; Voy, Duane; /Fermilab

    2011-07-13

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  7. A design of a valid signal selecting and position decoding ASIC for PET using silicon photomultipliers

    Science.gov (United States)

    Cho, M.; Lim, K.-t.; Kim, H.; Yeom, J.-y.; Kim, J.; Lee, C.; Choi, H.; Cho, G.

    2017-01-01

    In most cases, a PET system has numerous electrical components and channel circuits and thus it would rather be a bulky product. Also, most existing systems receive analog signals from detectors which make them vulnerable to signal distortions. For these reasons, channel reduction techniques are important. In this work, an ASIC for PET module is being proposed. An ASIC chip for 16 PET detector channels, VSSPDC, has been designed and simulated. The main function of the chip is 16-to-1 channel reduction, i.e., finding the position of only the valid signals, signal timing, and magnitudes in all 16 channels at every recorded event. The ASIC comprises four of 4-channel modules and a 2nd 4-to-1 router. A single channel module comprises a transimpedance amplifier for the silicon photomultipliers, dual comparators with high and low level references, and a logic circuitry. While the high level reference was used to test the validity of the signal, the low level reference was used for the timing. The 1-channel module of the ASIC produced an energy pulse by time-over-threshold method and it also produced a time pulse with a fixed delayed time. Since the ASIC chip outputs only a few digital pulses and does not require an external clock, it has an advantage over noise properties. The cadence simulation showed the good performance of the chip as designed.

  8. ASIC3 Mediates Itch Sensation in Response to Coincident Stimulation by Acid and Nonproton Ligand

    Directory of Open Access Journals (Sweden)

    Zhong Peng

    2015-10-01

    Full Text Available The regulation and mechanisms underlying itch sensation are complex. Here, we report a role for acid-sensing ion channel 3 (ASIC3 in mediating itch evoked by certain pruritogens during tissue acidosis. Co-administration of acid with Ser-Leu-Ile-Gly-Arg-Leu-NH2 (SL-NH2 increased scratching behavior in wild-type, but not ASIC3-null, mice, implicating the channel in coincident detection of acidosis and pruritogens. Mechanistically, SL-NH2 slowed desensitization of proton-evoked currents by targeting the previously identified nonproton ligand-sensing domain located in the extracellular region of ASIC3 channels in primary sensory neurons. Ablation of the ASIC3 gene reduced dry-skin-induced scratching behavior and pathological changes under conditions with concomitant inflammation. Taken together, our data suggest that ASIC3 mediates itch sensation via coincident detection of acidosis and nonproton ligands that act at the nonproton ligand-sensing domain of the channel.

  9. Front-end research for a low-cost spectrum analyser v1 0 2

    NARCIS (Netherlands)

    Rovers, K.C.

    2006-01-01

    This report discusses front-end research for a low-cost spectrum analyser. Requirement of the front-end are derived and a topology study is performed, both from an analogue as a digital perspective. Simulations are carried out to confirm the findings. This master project was initiated by Bruco B.V.,

  10. High-linearity CMOS RF front-end circuits

    CERN Document Server

    Ding, Yongwang

    2005-01-01

    This monograph presents techniques to improve the performance of linear integrated circuits (IC) in CMOS at high frequencies. Those circuits are primarily used in radio-frequency (RF) front-ends of wireless communication systems, such as low noise amplifiers (LNA) and mixers in a receiver and power amplifiers (PA) in a transmitter. A novel linearization technique is presented. With a small trade-off of gain and power consumption this technique can improve the linearity of the majority of circuits by tens of dB. Particularly, for modern CMOS processes, most of which has device matching better than 1%, the distortion can be compressed by up to 40 dB at the output. A prototype LNA has been fabricated in a 0.25um CMOS process, with a measured +18 dBm IIP3. This technique improves the dynamic range of a receiver RF front-end by 12 dB. A new class of power amplifier (parallel class A&B) is also presented to extend the linear operation range and save the DC power consumption. It has been shown by both simulation...

  11. A closed-loop MEMS accelerometer with capacitive sensing interface ASIC

    Science.gov (United States)

    Liu, Minjie; Chi, Baoyong; Liu, Yunfeng; Dong, Jingxin

    2013-01-01

    A closed-loop MEMS accelerometer with capacitive sensing interface ASIC (application specific integrated circuit) is presented. The parasitic-insensitive switched-capacitor sample-charge architecture is used to implement the capacitive sensing, which is crucial to the case where sensor and interface ASIC are combined in a two-chip approach to implement the closed-loop MEMS accelerometer. Based on the 0.35 µm CMOS sensing interface ASIC, an accelerometer prototype has been implemented, in which force-rebalance with the lag-proportional-integral controller is applied to improve the system stability and frequency response performance, and the testing results indicate the sensitivity of the presented accelerometer is 650 mV/g, the full measurement range ±15 g, the non-linearity 0.098% and the noise floor 23.17 µg/rt-Hz.

  12. Test beam analysis of ultra-thin hybrid pixel detector assemblies with Timepix readout ASICs

    CERN Document Server

    Alipour Tehrani, Niloufar; Dannheim, Dominik; Firu, Elena; Kulis, Szymon; Redford, Sophie; Sicking, Eva

    2016-01-01

    The requirements for the vertex detector at the proposed Compact Linear Collider imply a very small material budget: less than 0.2% of a radiation length per detection layer including services and mechanical supports. We present here a study using Timepix readout ASICs hybridised to pixel sensors of 50 − 500 μm thickness, including assemblies with 100 μm thick sensors bonded to thinned 100μm thick ASICs. Sensors from three producers (Advacam, Micron Semiconductor Ltd, Canberra) with different edge termination technologies (active edge, slim edge) were bonded to Timepix ASICs. These devices were characterised with the EUDET telescope at the DESY II test beam using 5.6 GeV electrons. Their performance for the detection and tracking of minimum ionising particles was evaluated in terms of charge sharing, detection efficiency, single-point resolution and energy deposition.

  13. A Low-Power ASIC Signal Processor for a Vestibular Prosthesis.

    Science.gov (United States)

    Töreyin, Hakan; Bhatti, Pamela T

    2016-06-01

    A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm (2) and consumes 1.24 mW when supplied with ± 1.6 V.

  14. Application specific integrated circuit (ASIC) readout technologies for future ion beam analytical instruments

    Energy Technology Data Exchange (ETDEWEB)

    Whitlow, Harry J. E-mail: harry_j.whitlow@nuclear.lu.se

    2000-03-01

    New possibilities for ion beam analysis (IBA) are afforded by recent developments in detector technology which facilitate the parallel collection of data from a large number of channels. Application specific integrated circuit (ASIC) technologies, which have been widely employed for multi-channel readout systems in nuclear and particle physics, are more net-cost effective (160/channel for 1000 channels) and a more rational solution for readout of a large number of channels than afforded by conventional electronics. Based on results from existing and on-going chip designs, the possibilities and issues of ASIC readout technology are considered from the IBA viewpoint. Consideration is given to readout chip architecture and how the stringent resolution, linearity and stability requirements for IBA may be met. In addition the implications of the restrictions imposed by ASIC technology are discussed.

  15. Ultra-wideband wireless receiver front-end for high-speed indoor applications

    Directory of Open Access Journals (Sweden)

    Zhe-Yang Huang

    2014-12-01

    Full Text Available Low-noise, ultra-wideband (UWB wireless receiver front-end circuits were presented in this study. A two-stage common-source low-noise amplifier with wideband input impedance matching network, an active-balun and a double-balanced down-conversion mixer were adopted in the UWB wireless receiver front-end. The proposed wireless receiver front-end circuits were implemented in 0.18 μm radio-frequency-CMOS process. The maximum down-conversion power gain of the front-end is 25.8 dB; minimum single-sideband noise figure of the front-end is 4.9 dB over complete UWB band ranging from 3.1 to 10.6 GHz. Power consumption including buffers is 39.2 mW.

  16. Atomic force microscopy imaging reveals the formation of ASIC/ENaC cross-clade ion channels

    Energy Technology Data Exchange (ETDEWEB)

    Jeggle, Pia; Smith, Ewan St. J.; Stewart, Andrew P. [Department of Pharmacology, University of Cambridge, Tennis Court Road, Cambridge CB2 1PD (United Kingdom); Haerteis, Silke; Korbmacher, Christoph [Institut für Zelluläre und Molekulare Physiologie, Friedrich-Alexander-Universität Erlangen-Nürnberg, Waldstrasse 6, 91054 Erlangen (Germany); Edwardson, J. Michael, E-mail: jme1000@cam.ac.uk [Department of Pharmacology, University of Cambridge, Tennis Court Road, Cambridge CB2 1PD (United Kingdom)

    2015-08-14

    ASIC and ENaC are co-expressed in various cell types, and there is evidence for a close association between them. Here, we used atomic force microscopy (AFM) to determine whether ASIC1a and ENaC subunits are able to form cross-clade hybrid ion channels. ASIC1a and ENaC could be co-isolated from detergent extracts of tsA 201 cells co-expressing the two subunits. Isolated proteins were incubated with antibodies against ENaC and Fab fragments against ASIC1a. AFM imaging revealed proteins that were decorated by both an antibody and a Fab fragment with an angle of ∼120° between them, indicating the formation of ASIC1a/ENaC heterotrimers. - Highlights: • There is evidence for a close association between ASIC and ENaC. • We used AFM to test whether ASIC1a and ENaC subunits form cross-clade ion channels. • Isolated proteins were incubated with subunit-specific antibodies and Fab fragments. • Some proteins were doubly decorated at ∼120° by an antibody and a Fab fragment. • Our results indicate the formation of ASIC1a/ENaC heterotrimers.

  17. Characterization of the front-end EASIROC for read-out of SiPM in the ASTRI camera

    CERN Document Server

    Impiombato, D; Belluso, M; Bilotta, S; Bonanno, G; Catalano, O; Grillo, A; La Rosa, G; Marano, D; Mineo, T; Russo, F; Sottile, G

    2013-01-01

    The design and realization of a prototype for the Small-Size class Telescopes of the Cherenkov Telescope Array is one of the cornerstones of the ASTRI project. The prototype will adopt a focal plane camera based on Silicon Photo-Multiplier sensors that coupled with a dual mirror optics configuration represents an innovative solution for the detection of Atmospheric Cherenkov light. These detectors can be read by the Extended Analogue Silicon Photo-Multiplier Integrated Read Out Chip (EASIROC) equipped with 32-channels. In this paper, we report some preliminary results on measurements aimed to evaluate EASIROC capability of autotriggering and measurements of the trigger time walk, jitter, DAC linearity and trigger efficiency vs the injected charge. Moreover, the dynamic range of the ASIC is also reported.

  18. Development of cryogenic CMOS Readout ASICs for the Point-Contact HPGe Detectors for Dark Matter Search and Neutrino Experiments

    Science.gov (United States)

    Deng, Zhi; He, Li; Liu, Feng; Liu, Yinong; Xue, Tao; Li, Yulan; Yue, Qian

    2017-05-01

    The paper presents the developments of two cryogenic readout ASICs for the point-contact HPGe detectors for dark matter search and neutrino experiments. Extremely low noise readout electronics were demanded and the capability of working at cryogenic temperatures may bring great advantages. The first ASIC was a monolithic CMOS charge sensitive preamplifier with its noise optimized for ∼1 pF input capacitance. The second ASIC was a waveform recorder based on switched capacitor array. These two ASICs were fabricated in CMOS 350 nm and 180 nm processes respectively. The prototype chips were tested and showed promising results. Both ASICs worked well at low temperature. The preamplifier had achieved ENC of 10.3 electrons with 0.7 pF input capacitance and the SCA chip could run at 9 bit effective resolution and 25 MSPS sampling rate.

  19. Channel control ASIC for the CMS hadron calorimeter front end readout module

    Energy Technology Data Exchange (ETDEWEB)

    Ray Yarema et al.

    2002-09-26

    The Channel Control ASIC (CCA) is used along with a custom Charge Integrator and Encoder (QIE) ASIC to digitize signals from the hybrid photo diodes (HPDs) and photomultiplier tubes (PMTs) in the CMS hadron calorimeter. The CCA sits between the QIE and the data acquisition system. All digital signals to and from the QIE pass through the CCA chip. One CCA chip interfaces with two QIE channels. The CCA provides individually delayed clocks to each of the QIE chips in addition to various control signals. The QIE sends digitized PMT or HPD signals and time slice information to the CCA, which sends the data to the data acquisition system through an optical link.

  20. Approach to the design of monitoring buffer for read-out ASICs

    Science.gov (United States)

    Atkin, E. V.; Vinogradov, S. M.

    2017-01-01

    The paper describes the approach to designing built-in monitoring buffers for the purpose of checking the functionality of ASICs as parts of test printed boards. A figure of merit (FOM), based on that analysis is suggested. Features of the FOM, applied to particle physics experiments, are the speed, power consumption, load driving capability and occupied chip area. As an example, illustrating the choice of buffer according to the proposed FOM, there are presented the results of designing a buffer version as part of an ASIC for the CBM MUCH(http://www.fair-center.eu/for-users/experiments/cbm.html).

  1. A silicon pixel readout ASIC with 100 ps time resolution for the NA62 experiment

    Energy Technology Data Exchange (ETDEWEB)

    Dellacasa, G; Garbolino, S; Marchetto, F; Martoiu, S; Mazza, G; Rivetti, A; Wheadon, R, E-mail: mazza@to.infn.it [INFN sez. di Torino, Via P. Giuria 1, 10125 Torino (Italy)

    2011-01-15

    The silicon tracker of the NA62 experiment requires the measurement of the particles arrival time with a resolution better than 200 ps rms and a spatial resolution of 300 {mu}m. A time measurement technique based on a Time to Amplitude Converter has been implemented in an ASIC in order to prove the possibility to integrate a TDC with resolution better than 200 ps in a pixel cell. Time-walk problem has been addressed with the use of the Constant Fraction Discriminator technique. The ASIC has been designed in a CMOS 0.13 {mu}m technology with single event upset protection of the digital logic.

  2. Mecanoproteínas ASIC y movimiento dentario: bases de la mecanotransducción

    OpenAIRE

    Stan, Claudia

    2012-01-01

    Algunas proteínas de la familia de las degenerinas/ENaC, especialmente los ASIC (canales iónicos sensibles a ácido), funcionan como sensores generales y como mecanosensores, o pueden ser necesarios para la mecanosensación, en una amplia gama de especies y tipos celulares. En el presente trabajo se investigó mediante técnicas de inmunohistoquímica la expresión del canal iónico ASIC2 en el ligamento periodontal del primer molar superior de rata, en condiciones de normalidad y tras someter el ...

  3. The ALMA Front-end Archive Setup and Performance

    Science.gov (United States)

    Wicenec, A.; Chen, A.; Checcucci, A.; Jeram, B.; Meuss, H.; Persson, A.; Burgos, P.; Cirami, R.

    2010-12-01

    The ALMA front-end archive system has to capture up to 64 MB/s for a period of several days plus the data of about 100,000 monitor points from all 66 antennas and the correlators. The main science data is delivered through corba based audio/video streams and finally stored on SATA disk arrays hosted on 6 computers and controlled by 12 daemons. All data is collected by software components running on computers in the antennas and then sent through dedicated fiber links to the Array Operations Site at 5000 m and from there to the Operations Support Facility (OSF) at 3000 m elevation. The various hardware and software components have been tuned and tested to be able to meet the performance requirements. This paper describes the setup and the various components in more detail and gives results of various test runs.

  4. Fact Sheet for KM200 Front-end Electronics

    Energy Technology Data Exchange (ETDEWEB)

    Ianakiev, Kiril Dimitrov [Los Alamos National Laboratory; Iliev, Metodi [Los Alamos National Laboratory; Swinhoe, Martyn Thomas [Los Alamos National Laboratory

    2015-07-08

    The KM200 device is a versatile, configurable front-end electronics boards that can be used as a functional replacement for Canberra’s JAB-01 boards based on the Amptek A-111 hybrid chip, which continues to be the preferred choice of electronics for large number of the boards in junction boxes of multiplicity counters that process the signal from an array of 3He detectors. Unlike the A-111 chip’s fixed time constants and sensitivity range, the shaping time and sensitivity of the new KM200 can be optimized for demanding applications such as spent fuel, and thus could improve the safeguards measurements of existing systems where the A-111 or PDT electronics does not perform well.

  5. Rapid SOA Frontend Design and Prototyping for LINC-NIRVANA

    Science.gov (United States)

    Berwein, J.; Briegel, F.; Kittmann, F.; Pavlov, A.; Gaessler, W.; Kittmann, F.

    2010-12-01

    LINC-NIRVANA is a German-Italian Fizeau (imaging) interferometer for the Large Binocular Telescope (LBT) on Mt. Graham in Arizona, USA. For laboratory testing and integration, a large number of engineering applications are needed. The process of engineering, testing and integration has to go hand in hand with an agile software development for data display and configuration frontends. Therefore we implemented software packages, which enable a rapid design and prototyping of engineering applications within an SOA oriented environment. Due to the usage of only pre-compiled software and the easy to handle workflow neither compilation nor programming knowledge is require. We will present the current development status, usage and advantages of our software, which was realized at the Max Planck Institute for Astronomy in Heidelberg, Germany.

  6. Fast Frontend Electronics for high luminosity particle detectors

    CERN Document Server

    Cardinali, M; Bondy, M I Ferretti; Hoek, M; Lauth, W; Rosner, C; Sfienti, C; Thiel, M

    2015-01-01

    Future experiments of nuclear and particle physics are moving towards the high luminosity regime, in order to access suppressed processes like rare B decays or exotic charmonium resonances. In this scenario, high rate capability is a key requirement for electronics instrumentation, together with excellent timing resolution for precise event reconstruction. The development of dedicated FrontEnd Electronics (FEE) for detectors has become increasingly challenging. A current trend in R&D is towards multipurpose FEE which can be easily adapted to a great variety of detectors, without impairing the required high performance. We report on high-precision timing solutions which utilise high-bandwidth preamplifiers and fast discriminators providing Time-over-Threshold information, which can be used for charge measurements or walk corrections thus improving the obtainable timing resolution. The output signal are LVDS and can be directly fed into a multi-hit TDC readout. The performance of the electronics was investi...

  7. A software-radio front-end for microwave applications

    Directory of Open Access Journals (Sweden)

    M. Streifinger

    2003-01-01

    Full Text Available In modern communication, sensor and signal processing systems digitisation methods are gaining importance. They allow for building software configurable systems and provide better stability and reproducibility. Moreover digital front-ends cover a wider range of applications and have better performance compared with analog ones. The quest for new architectures in radio frequency front-ends is a clear consequence of the ever increasing number of different standards and the resulting task to provide a platform which covers as many standards as possible. At microwave frequencies, in particular at frequencies beyond 10 GHz, no direct sampling receivers are available yet. A look at the roadmap of the development of commercial analog-to-digital-converters (ADC shows clearly, that they can neither be expected in near future. We present a novel architecture, which is capable of direct sampling of band-limited signals at frequencies beyond 10 GHz by means of an over-sampling technique. The wellknown Nyquist criterion states that wide-band digitisation of an RF-signal with a maximum frequency ƒ requires a minimum sampling rate of 2 · ƒ . But for a band-limited signal of bandwidth B the demands for the minimum sampling rate of the ADC relax to the value 2 · B. Employing a noise-forming sigma-delta ADC architecture even with a 1-bit-ADC a signal-to-noise ratio sufficient for many applications can be achieved. The key component of this architecture is the sample-and-hold switch. The required bandwidth of this switch must be well above 2 · ƒ . We designed, fabricated and characterized a preliminary demonstrator for the ISM-band at 2.4 GHz employing silicon Schottky diodes as a switch and SiGe-based MMICs as impedance transformers and comparators. Simulated and measured results will be presented.

  8. A software-radio front-end for microwave applications

    Science.gov (United States)

    Streifinger, M.; Müller, T.; Luy, J.-F.; Biebl, E. M.

    2003-05-01

    In modern communication, sensor and signal processing systems digitisation methods are gaining importance. They allow for building software configurable systems and provide better stability and reproducibility. Moreover digital front-ends cover a wider range of applications and have better performance compared with analog ones. The quest for new architectures in radio frequency front-ends is a clear consequence of the ever increasing number of different standards and the resulting task to provide a platform which covers as many standards as possible. At microwave frequencies, in particular at frequencies beyond 10 GHz, no direct sampling receivers are available yet. A look at the roadmap of the development of commercial analog-to-digital-converters (ADC) shows clearly, that they can neither be expected in near future. We present a novel architecture, which is capable of direct sampling of band-limited signals at frequencies beyond 10 GHz by means of an over-sampling technique. The wellknown Nyquist criterion states that wide-band digitisation of an RF-signal with a maximum frequency ƒ requires a minimum sampling rate of 2 · ƒ . But for a band-limited signal of bandwidth B the demands for the minimum sampling rate of the ADC relax to the value 2 · B. Employing a noise-forming sigma-delta ADC architecture even with a 1-bit-ADC a signal-to-noise ratio sufficient for many applications can be achieved. The key component of this architecture is the sample-and-hold switch. The required bandwidth of this switch must be well above 2 · ƒ . We designed, fabricated and characterized a preliminary demonstrator for the ISM-band at 2.4 GHz employing silicon Schottky diodes as a switch and SiGe-based MMICs as impedance transformers and comparators. Simulated and measured results will be presented.

  9. An Energy-Efficient ASIC for Wireless Body Sensor Networks in Medical Applications.

    Science.gov (United States)

    Xiaoyu Zhang; Hanjun Jiang; Lingwei Zhang; Chun Zhang; Zhihua Wang; Xinkai Chen

    2010-02-01

    An energy-efficient application-specific integrated circuit (ASIC) featured with a work-on-demand protocol is designed for wireless body sensor networks (WBSNs) in medical applications. Dedicated for ultra-low-power wireless sensor nodes, the ASIC consists of a low-power microcontroller unit (MCU), a power-management unit (PMU), reconfigurable sensor interfaces, communication ports controlling a wireless transceiver, and an integrated passive radio-frequency (RF) receiver with energy harvesting ability. The MCU, together with the PMU, provides quite flexible communication and power-control modes for energy-efficient operations. The always-on passive RF receiver with an RF energy harvesting block offers the sensor nodes the capability of work-on-demand with zero standby power. Fabricated in standard 0.18-¿m complementary metal-oxide semiconductor technology, the ASIC occupies a die area of 2 mm × 2.5 mm. A wireless body sensor network sensor-node prototype using this ASIC only consumes < 10-nA current under the passive standby mode, and < 10 ¿A under the active standby mode, when supplied by a 3-V battery.

  10. A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond

    Energy Technology Data Exchange (ETDEWEB)

    Gass, Karl; Pierson, Lyndon G.; Robertson, Perry J.; Wilcox, D. Craig; Witzke, Edward L.

    1999-04-30

    The Sandia National Laboratories (SNL) Data Encryption Standard (DES) Application Specific Integrated Circuit (ASIC) is the fastest known implementation of the DES algorithm as defined in the Federal Information Processing Standards (FIPS) Publication 46-2. DES is used for protecting data by cryptographic means. The SNL DES ASIC, over 10 times faster than other currently available DES chips, is a high-speed, filly pipelined implementation offering encryption, decryption, unique key input, or algorithm bypassing on each clock cycle. Operating beyond 105 MHz on 64 bit words, this device is capable of data throughputs greater than 6.7 Billion bits per second (tester limited). Simulations predict proper operation up to 9.28 Billion bits per second. In low frequency, low data rate applications, the ASIC consumes less that one milliwatt of power. The device has features for passing control signals synchronized to throughput data. Three SNL DES ASICS may be easily cascaded to provide the much greater security of triple-key, triple-DES.

  11. A wireless capsule system with ASIC for monitoring the physiological signals of the human gastrointestinal tract.

    Science.gov (United States)

    Xu, Fei; Yan, Guozheng; Zhao, Kai; Lu, Li; Gao, Jinyang; Liu, Gang

    2014-12-01

    This paper presents the design of a wireless capsule system for monitoring the physiological signals of the human gastrointestinal (GI) tract. The primary components of the system include a wireless capsule, a portable data recorder, and a workstation. Temperature, pH, and pressure sensors; an RF transceiver; a controlling and processing application specific integrated circuit (ASIC); and batteries were applied in a wireless capsule. Decreasing capsule size, improving sensor precision, and reducing power needs were the primary challenges; these were resolved by employing micro sensors, optimized architecture, and an ASIC design that include power management, clock management, a programmable gain amplifier (PGA), an A/D converter (ADC), and a serial peripheral interface (SPI) communication unit. The ASIC has been fabricated in 0.18- μm CMOS technology with a die area of 5.0 mm × 5.0 mm. The wireless capsule integrating the ASIC controller measures Φ 11 mm × 26 mm. A data recorder and a workstation were developed, and 20 cases of human experiments were conducted in hospitals. Preprocessing in the workstation can significantly improve the quality of the data, and 76 original features were determined by mathematical statistics. Based on the 13 optimal features achieved in the evaluation of the features, the clustering algorithm can identify the patients who lack GI motility with a recognition rate reaching 83.3%.

  12. MULTICHANNEL ENERGY AND TIMING MEASUREMENTS WITH THE PEAK DETECTOR/DERANDOMIZER ASIC.

    Energy Technology Data Exchange (ETDEWEB)

    O' CONNOR,P.; DE GERONIMO,G.; GROSHOLZ,J.; KANDASAMY,A.; JUNNARKAR,S.; FRIED,J.

    2004-10-16

    The Peak Detector/Derandomizer ASIC (PDD) provides threshold discrimination, peak detection, time-to-amplitude conversion, analog memory, sparsification, and multiplexing for 32 channels of analog pulse data. In this work the spectroscopic capabilities of the chip (high resolution and high rate) are demonstrated along with correlated measurements of pulse risetime. Imaging and coincidence detection using the PDD chip will also be illustrated.

  13. Design and measurements of 64-channel ASIC for neural signal recording.

    Science.gov (United States)

    Kmon, P; Zoladz, M; Grybos, P; Szczygiel, R

    2009-01-01

    This paper presents the design and measurements of a low noise multi-channel front-end electronics for recording extra-cellular neuronal signals using microelectrode arrays. The integrated circuit contains 64 readout channels and was fabricated in CMOS 0.18 microm technology. A single readout channel is built of an AC coupling circuit at the input, a low noise preamplifier, a band-pass filter and a second amplifier. In order to reduce the number of output lines, the 64 analog signals from readout channels are multiplexed to a single output by an analog multiplexer. The chip is optimized for low noise and matching performance with the possibility of cut-off frequencies tuning. The low cut-off frequency can be tuned in the 1 Hz-60 Hz range and the high cut-off frequency can be tuned in the 3.5 kHz-15 kHz range. For the nominal gain setting at 44 dB and power dissipation per single channel of 220 microW the equivalent input noise is in the range from 6 microV-11 microV rms depending on the band-pass filter settings. The chip has good uniformity concerning the spread of its electrical parameters from channel to channel. The spread of gain calculated as standard deviation to mean value is about 4.4% and the spread of the low cut-off frequency is on the same level. The chip occupies 5x2.3 mm(2) of silicon area.

  14. Design of a video capsule endoscopy system with low-power ASIC for monitoring gastrointestinal tract.

    Science.gov (United States)

    Liu, Gang; Yan, Guozheng; Zhu, Bingquan; Lu, Li

    2016-11-01

    In recent years, wireless capsule endoscopy (WCE) has been a state-of-the-art tool to examine disorders of the human gastrointestinal tract painlessly. However, system miniaturization, enhancement of the image-data transfer rate and power consumption reduction for the capsule are still key challenges. In this paper, a video capsule endoscopy system with a low-power controlling and processing application-specific integrated circuit (ASIC) is designed and fabricated. In the design, these challenges are resolved by employing a microimage sensor, a novel radio frequency transmitter with an on-off keying modulation rate of 20 Mbps, and an ASIC structure that includes a clock management module, a power-efficient image compression module and a power management unit. An ASIC-based prototype capsule, which measures Φ11 mm × 25 mm, has been developed here. Test results show that the designed ASIC consumes much less power than most of the other WCE systems and that its total power consumption per frame is the least. The image compression module can realize high near-lossless compression rate (3.69) and high image quality (46.2 dB). The proposed system supports multi-spectral imaging, including white light imaging and autofluorescence imaging, at a maximum frame rate of 24 fps and with a resolution of 400 × 400. Tests and in vivo trials in pigs have proved the feasibility of the entire system, but further improvements in capsule control and compression performance inside the ASIC are needed in the future.

  15. BPM Analog front-end electronics based on the AD8307 log amplifier

    Science.gov (United States)

    Shurter, R. B.; Gilpatrick, J. D.; Power, J.

    2000-11-01

    Beam position monitor (BPM) signal-processing electronics utilizing the Analog Devices AD8307 logarithmic amplifier has been developed for the Low Energy Demonstration Accelerator (LEDA), part of the Accelerator Production of Tritium (APT) project at Los Alamos. The low-pass filtered 350 MHz fundamental signal from each of the four microstrip electrodes in a BPM is "detected" by an AD8307 log amp, amplified and scaled to accommodate the 0 to +5 V input of an analog-to-digital (A/D) converter. The resultant four digitized signals represent a linear power relationship to the electrode signals, which are in turn related to beam current and position. As the AD8307 has a potential dynamic range of approximately 92 dB, much attention must be given to noise reduction, sources of which can be digital signals on the same board, power supplies, inter-channel coupling, stray RF and others. This paper will describe the operational experience of this particular analog front-end electronic circuit design.

  16. BPM ANALOG FRONT-END ELECTRONICS BASED ON THE AD8307 LOG AMPLIFIER

    Energy Technology Data Exchange (ETDEWEB)

    R. SHURTER; ET AL

    2000-06-01

    Beam position monitor (BPM) signal-processing electronics utilizing the Analog Devices AD8307 logarithmic amplifier has been developed for the Low Energy Demonstration Accelerator (LEDA), part of the Accelerator Production of Tritium (APT) project at Los Alamos. The low-pass filtered 350 MHz fundamental signal from each of the four microstrip electrodes in a BPM is ''detected'' by an AD8307 log amp, amplified and scaled to accommodate the 0 to +5V input of an analog-to-digital (A/D) converter. The resultant four digitized signals represent a linear power relationship to the electrode signals, which are in turn related to beam current and position. As the AD8307 has a potential dynamic range of approximately 92 dB, much attention must be given to noise reduction, sources of which can be digital signals on the same board, power supplies, inter-channel coupling, stray RF and others. This paper will describe the operational experience of this particular analog front-end electronic circuit design.

  17. Digital pulse processing and optimization of the front-end electronics for nuclear instrumentation.

    Science.gov (United States)

    Bobin, C; Bouchard, J; Thiam, C; Ménesguen, Y

    2014-05-01

    This article describes an algorithm developed for the digital processing of signals provided by a high-efficiency well-type NaI(Tl) detector used to apply the 4πγ technique. In order to achieve a low-energy threshold, a new front-end electronics has been specifically designed to optimize the coupling to an analog-to-digital converter (14 bit, 125 MHz) connected to a digital development kit produced by Altera(®). The digital pulse processing is based on an IIR (Infinite Impulse Response) approximation of the Gaussian filter (and its derivatives) that can be applied to the real-time processing of digitized signals. Based on measurements obtained with the photon emissions generated by an (241)Am source, the energy threshold is estimated to be equal to ~2 keV corresponding to the physical threshold of the NaI(Tl) detector. An algorithm developed for a Silicon Drift Detector used for low-energy x-ray spectrometry is also described. In that case, the digital pulse processing is specifically designed for signals provided by a reset-type preamplifier ((55)Fe source).

  18. Development and validation of a 64 channel front end ASIC for 3D directional detection with MIMAC

    CERN Document Server

    Richer, J P; Bosson, G; Guillaudin, O; Mayet, F; Santos, D

    2011-01-01

    A front end ASIC has been designed to equip the {\\mu}TPC prototype developed for the MIMAC project, which requires 3D reconstruction of low energy particle tracks in order to perform directional detection of galactic Dark Matter. Each ASIC is able to monitor 64 strips of pixels and provides the "Time Over Threshold" information for each of those. These 64 digital informations, sampled at a rate of 50 MHz, can be transferred at 400MHz by eight LVDS serial links. Eight ASIC were validated on a 2x256 strips of pixels prototype.

  19. Low-power digital ASIC for on-chip spectral analysis of low-frequency physiological signals

    Institute of Scientific and Technical Information of China (English)

    Nie Zedong; Zhang Fengjuan; Li Jie; Wang Lei

    2012-01-01

    A digital ASIC chip customized for battery-operated body sensing devices is presented.The ASIC incorporates a novel hybrid-architecture fast Fourier transform (FFT) unit that is capable of scalable spectral analysis,a licensed ARM7TDMI IP hardcore and several peripheral IP blocks.Extensive experimental results suggest that the complete chip works as intended.The power consumption of the FFT unit is 0.69 mW @ 1 MHz with 1.8 V power supply.The low-power and programmable features of the ASIC make it suitable for ‘on-the-fly' low-frequency physiological signal processing.

  20. A digital Front-End and Readout MIcrosystem for calorimetry at LHC

    CERN Multimedia

    2002-01-01

    % RD-16 A Digital Front-End and Readout Microsystem for Calorimetry at LHC \\\\ \\\\Front-end signal processing for calorimetric detectors is essential in order to achieve adequate selectivity in the trigger function of an LHC experiment, with data identification and compaction before readout being required in the harsh, high rate environment of a high luminosity hadron machine. Other crucial considerations are the extremely wide dynamic range and bandwidth requirements, as well as the volume of data to be transferred to following stages of the trigger and readout system. These requirements are best met by an early digitalization of the detector information, followed by integrated digital signal processing and buffering functions covering the trigger latencies.\\\\ \\\\The FERMI (Front-End Readout MIcrosystem) is a digital implementation of the front-end and readout electronic chain for calorimeters. It is based on dynamic range compression, high speed A to D converters, a fully programmable pipeline/digital filter c...

  1. Oxford Summer School "Intelligent Front-End Signal Processing for Frontier Exploitation in Research and Industry"

    CERN Document Server

    2013-01-01

    Interdisciplinary Summer School on Intelligent Front-End Signal Processing for Frontier Exploitation in Research and Industry. For details about the school programme and registration, please visit: http://www.physics.ox.ac.uk/INFIERI2013/

  2. Frequency-Tunable antenna by input-impedance-tunable CMOS RF-Frontend

    NARCIS (Netherlands)

    Haider, Nadia; Oude Alink, Mark S.; Caratelli, Diego; Klumperink, Eric A.M.; Yarovoy, Alexander G.

    2013-01-01

    Variable-impedance matching between the antenna and the RF-frontend provides several potential advantages, including changing operational frequency, compensating for unintentional mismatch, improving scanning capability, and reducing noise and interference signal levels. In this article a concept of

  3. A 500μW 5Mbps ULP super-regenerative RF front-end

    NARCIS (Netherlands)

    Vidojkovic, M.; Rampu, S.; Imamura, K.; Harpe, P.; Dolmans, G.; Groot, H. de

    2010-01-01

    This paper presents an ultra low power super-regenerative RF front-end for wireless body area network (WBAN) applications. The RF front-end operates in the 2.36-2.4 GHz medical BAN and 2.4-2.485 GHz ISM bands, and consumes 500 μW. It supports OOK modulation at high data rates ranging from 1-5 Mbps.

  4. Measurement of Design Process Front-End – Radical Innovation Approach

    DEFF Research Database (Denmark)

    Berg, Pekka; Pihlajamaa, Jussi; Hansen, Poul H. Kyvsgård

    2014-01-01

    The overall structure and the main characteristics of the future product are all decided in the front-end phase, which then strongly affects subsequent new product development activities. Recent studies indicate that these early front-end activities represent the most troublesome phase of the inn...... is flexible and can also be applied extensively to other purposes than manufacturing companies, like service sector, as well....

  5. Implementation of Low-Cost UHF RFID Reader Front-Ends with Carrier Leakage Suppression Circuit

    OpenAIRE

    Bin You; Bo Yang; Xuan Wen; Liangyu Qu

    2013-01-01

    A new ultrahigh frequency radio frequency identification (UHF RFID) reader’s front-end circuit which is based on zero-IF, single antenna structure and composed of discrete components has been designed. The proposed design brings a significant improvement of the reading performance by adopting a carrier leakage suppression (CLS) circuit instead of a circulator which is utilized by most of the conventional RF front-end circuit. Experimental results show that the proposed design improves both th...

  6. Polyphase Filter Banks for Embedded Sample Rate Changes in Digital Radio Front-Ends

    DEFF Research Database (Denmark)

    Awan, Mehmood-Ur-Rehman; Le Moullec, Yannick; Koch, Peter

    2011-01-01

    This paper presents efficient processing engines for software-defined radio (SDR) front-ends. These engines, based on a polyphase channelizer, perform arbitrary sample-rate changes, frequency selection, and bandwidth control. This paper presents an M-path polyphase filter bank based on a modified N...... in an SDR front-end based on a polyphase channelizer. They can also be used for translation to and from arbitrary center frequencies that are unrelated to the output sample rates....

  7. Circuit techniques for cognitive radio receiver front-ends

    Science.gov (United States)

    Sadhu, Bodhisatwa

    This thesis discusses the design of the receiver front-end for software defined radio (SDR) based cognitive radio applications. Two aspects of SDRs for cognitive radios are distinguished: signaling and spectrum sensing. Narrowband wide tuning signaling architectures and instantaneous wideband spectrum sensing architectures are identified as candidates for feasible SDR implementations. Several architectures and circuit implementations are reviewed. Wide tuning range, low phase noise frequency synthesizers for signaling, and RF samplers and signal processors for spectrum sensing are identified as critical circuit design blocks. A number of voltage controlled oscillator (VCO) techniques for wide-tuning range, and low phase noise frequency synthesis techniques are developed. Wide-tuning range techniques based on switched inductors are proposed as a way to design inductor-capacitor (LC) VCOs with wide-tuning ranges that maintain a good phase noise and power dissipation performance over the entire tuning range. Switched inductor VCOs are analyzed in detail, and a design framework is developed. Optimized capacitor array design techniques for wide-tuning ranges are discussed. Based on these techniques, measurements from two prototype designs are presented, that achieve tuning ranges of 87% and 157% in measurement. They also maintain good phase noise, power consumption, and figure of merit (FOM) over the entire tuning range. In addition, a new family of VCOs that achieve superior phase noise is introduced. This set of novel topologies are based on linearized transconductance using capacitive feedback techniques. They achieve higher amplitudes of oscillation, and consequently, a superior phase noise performance. A wide tuning range is also maintained. The VCOs are analyzed, and detailed measurement results from a design prototype are presented. For spectrum sensing, the design of CRAFT (Charge Re-use Analog Fourier Transform): an RF front-end channelizer for software defined

  8. Targeting ASIC1 in primary progressive multiple sclerosis: evidence of neuroprotection with amiloride.

    Science.gov (United States)

    Arun, Tarunya; Tomassini, Valentina; Sbardella, Emilia; de Ruiter, Michiel B; Matthews, Lucy; Leite, Maria Isabel; Gelineau-Morel, Rose; Cavey, Ana; Vergo, Sandra; Craner, Matt; Fugger, Lars; Rovira, Alex; Jenkinson, Mark; Palace, Jacqueline

    2013-01-01

    Neurodegeneration is the main cause for permanent disability in multiple sclerosis. The effect of current immunomodulatory treatments on neurodegeneration is insufficient. Therefore, direct neuroprotection and myeloprotection remain an important therapeutic goal. Targeting acid-sensing ion channel 1 (encoded by the ASIC1 gene), which contributes to the excessive intracellular accumulation of injurious Na(+) and Ca(2+) and is over-expressed in acute multiple sclerosis lesions, appears to be a viable strategy to limit cellular injury that is the substrate of neurodegeneration. While blockade of ASIC1 through amiloride, a potassium sparing diuretic that is currently licensed for hypertension and congestive cardiac failure, showed neuroprotective and myeloprotective effects in experimental models of multiple sclerosis, this strategy remains untested in patients with multiple sclerosis. In this translational study, we tested the neuroprotective effects of amiloride in patients with primary progressive multiple sclerosis. First, we assessed ASIC1 expression in chronic brain lesions from post-mortem of patients with progressive multiple sclerosis to identify the target process for neuroprotection. Second, we tested the neuroprotective effect of amiloride in a cohort of 14 patients with primary progressive multiple sclerosis using magnetic resonance imaging markers of neurodegeneration as outcome measures of neuroprotection. Patients with primary progressive multiple sclerosis underwent serial magnetic resonance imaging scans before (pretreatment phase) and during (treatment phase) amiloride treatment for a period of 3 years. Whole-brain volume and tissue integrity were measured with high-resolution T(1)-weighted and diffusion tensor imaging. In chronic brain lesions of patients with progressive multiple sclerosis, we demonstrate an increased expression of ASIC1 in axons and an association with injury markers within chronic inactive lesions. In patients with primary

  9. Differential regulation of proton-sensitive ion channels by phospholipids: a comparative study between ASICs and TRPV1.

    Directory of Open Access Journals (Sweden)

    Hae-Jin Kweon

    Full Text Available Protons are released in pain-generating pathological conditions such as inflammation, ischemic stroke, infection, and cancer. During normal synaptic activities, protons are thought to play a role in neurotransmission processes. Acid-sensing ion channels (ASICs are typical proton sensors in the central nervous system (CNS and the peripheral nervous system (PNS. In addition to ASICs, capsaicin- and heat-activated transient receptor potential vanilloid 1 (TRPV1 channels can also mediate proton-mediated pain signaling. In spite of their importance in perception of pH fluctuations, the regulatory mechanisms of these proton-sensitive ion channels still need to be further investigated. Here, we compared regulation of ASICs and TRPV1 by membrane phosphoinositides, which are general cofactors of many receptors and ion channels. We observed that ASICs do not require membrane phosphatidylinositol 4-phosphate (PI(4P or phosphatidylinositol 4,5-bisphosphate (PI(4,5P2 for their function. However, TRPV1 currents were inhibited by simultaneous breakdown of PI(4P and PI(4,5P2. By using a novel chimeric protein, CF-PTEN, that can specifically dephosphorylate at the D3 position of phosphatidylinositol 3,4,5-trisphosphate (PI(3,4,5P3, we also observed that neither ASICs nor TRPV1 activities were altered by depletion of PI(3,4,5P3 in intact cells. Finally, we compared the effects of arachidonic acid (AA on two proton-sensitive ion channels. We observed that AA potentiates the currents of both ASICs and TRPV1, but that they have different recovery aspects. In conclusion, ASICs and TRPV1 have different sensitivities toward membrane phospholipids, such as PI(4P, PI(4,5P2, and AA, although they have common roles as proton sensors. Further investigation about the complementary roles and respective contributions of ASICs and TRPV1 in proton-mediated signaling is necessary.

  10. Toward 5G software defined radio receiver front-ends

    CERN Document Server

    Spiridon, Silvian

    2016-01-01

    This book introduces a new intuitive design methodology for the optimal design path for next-generation software defined radio front-ends (SDRXs). The methodology described empowers designers to "attack" the multi-standard environment in a parallel way rather than serially, providing a critical tool for any design methodology targeting 5G circuits and systems. Throughout the book the SDRX design follows the key wireless standards of the moment (i.e., GSM, WCDMA, LTE, Bluetooth, WLAN), since a receiver compatible with these standards is the most likely candidate for the first design iteration in a 5G deployment. The author explains the fundamental choice the designer has to make regarding the optimal channel selection: how much of the blockers/interferers will be filtered in the analog domain and how much will remain to be filtered in the digital domain. The system-level analysis the author describes entails the direct sampling architecture is treated as a particular case of mixer-based direct conversion archi...

  11. Front-end electronics and trigger systems - status and challenges

    Energy Technology Data Exchange (ETDEWEB)

    Spieler, Helmuth G; Spieler, Helmuth G

    2007-08-21

    The past quarter century has brought about a revolution in front-end electronics for large-scale detector systems. Custom integrated circuits specifically tailored to the requirements of large detector systems have provided unprecedented performance and enabled systems that once were deemed impossible. The evolution of integrated circuit readouts in strip detectors is summarized, the present status described, and challenges posed by the sLHC and ILC are discussed. Performance requirements increase, but key considerations remain as in the past: power dissipation, material, and services. Smaller CMOS feature sizes will not provide the required electronic noise at lower power, but will improve digital power efficiency. Significant improvements appear to be practical in more efficient power distribution. Enhanced digital electronics have provided powerful trigger processors that greatly improve the trigger efficiency. In data readout systems they also improve data throughput, while reducing power requirements. Concurrently with new developments in high energy physics, detector systems for cosmology and astrophysics have made great strides. As an example, a large-scale readout for superconducting bolometer arrays is described.

  12. Front-end electronics for the Muon Portal project

    Science.gov (United States)

    Garozzo, S.; Marano, D.; Bonanno, G.; Grillo, A.; Romeo, G.; Timpanaro, M. C.; Lo Presti, D.; Riggi, F.; Russo, V.; Bonanno, D.; La Rocca, P.; Longhitano, F.; Bongiovanni, D. G.; Fallica, G.; Valvo, G.

    2016-10-01

    The Muon Portal Project was born as a joint initiative between Italian research and industrial partners, aimed at the construction of a real-size working detector prototype to inspect the content of traveling containers by means of secondary cosmic-ray muon radiation and recognize potentially dangerous hidden materials. The tomographic image is obtained by reconstructing the incoming and outgoing muon trajectories when crossing the inspected volume, employing two tracker planes located above and below the container under inspection. In this paper, the design and development of the front-end electronics of the Muon Portal detector is presented, with particular emphasis being devoted to the photo-sensor devices detecting the scintillation light and to the read-out circuitry which is in charge of processing and digitizing the analog pulse signals. In addition, the remote control system, mechanical housing, and thermal cooling system of all structural blocks of the Muon Portal tracker are also discussed, demonstrating the effectiveness and functionality of the adopted design.

  13. Front-End electronics configuration system for CMS

    CERN Document Server

    Gras, P; Funk, W; Gross, L; Vintache, D

    2001-01-01

    The four LHC experiments at CERN have decided to use a commercial SCADA (Supervisory Control And Data Acquisition) product for the supervision of their DCS (Detector Control System). The selected SCADA, which is therefore used for the CMS DCS, is PVSS II from the company ETM. This SCADA has its own database, which is suitable for storing conventional controls data such as voltages, temperatures and pressures. In addition, calibration data and FE (Front-End) electronics configuration need to be stored. The amount of these data is too large to be stored in the SCADA database [1]. Therefore an external database will be used for managing such data. However, this database should be completely integrated into the SCADA framework, it should be accessible from the SCADA and the SCADA features, e.g. alarming, logging should be benefited from. For prototyping, Oracle 8i was selected as the external database manager. The development of the control system for calibration constants and FE electronics configuration has bee...

  14. An implementation of the LHCb level 0 muon trigger using the 3D-Flow ASIC

    CERN Document Server

    Corti, G; Crosetto, D; Nelson, K

    1998-01-01

    The implementation of the LHCb level 0 muon trigger using the 3D-flow technique is discussed. The connection of the LHCb muon detector front-end electronics to the L0 3D-flow processor is also discussed.1

  15. Preliminary validation results of an ASIC for the readout and control of near-infrared large array detectors

    Science.gov (United States)

    Pâhlsson, Philip; Meier, Dirk; Otnes Berge, Hans Kristian; Øya, Petter; Steenari, David; Olsen, Alf; Hasanbegovic, Amir; Altan, Mehmet A.; Najafiuchevler, Bahram; Talebi, Jahanzad; Azman, Suleyman; Gheorghe, Codin; Ackermann, Jörg; Mæhlum, Gunnar

    2015-06-01

    In this paper we present initial test results of the Near Infrared Readout and Controller ASIC (NIRCA), designed for large area image sensors under contract from the European Space Agency (ESA) and the Norwegian Space Center. The ASIC is designed to read out image sensors based on mercury cadmium telluride (HgCdTe, or MCT) operating down to 77 K. IDEAS has developed, designed and initiated testing of NIRCA with promising results, showing complete functionality of all ASIC sub-components. The ASIC generates programmable digital signals to clock out the contents of an image array and to amplify, digitize and transfer the resulting pixel charge. The digital signals can be programmed into the ASIC during run-time and allows for windowing and custom readout schemes. The clocked out voltages are amplified by programmable gain amplifiers and digitized by 12-bit, 3-Msps successive approximation register (SAR) analogue-to-digital converters (ADC). Digitized data is encoded using 8-bit to 10-bit encoding and transferred over LVDS to the readout system. The ASIC will give European researchers access to high spectral sensitivity, very low noise and radiation hardened readout electronics for astronomy and Earth observation missions operating at 77 K and room temperature. The versatility of the chip makes the architecture a possible candidate for other research areas, or defense or industrial applications that require analog and digital acquisition, voltage regulation, and digital signal generation.

  16. FROST: a low-noise high-rate photon counting ASIC for X-ray applications

    Energy Technology Data Exchange (ETDEWEB)

    Prest, M. E-mail: prest@ts.infn.it; Vallazza, E.; Chiavacci, M.; Mariani, R.; Motto, S.; Neri, M.; Scantamburlo, N.; Arfelli, F.; Conighi, A.; Longo, R.; Olivo, A.; Pani, S.; Poropat, P.; Rashevsky, A.; Rigon, L.; Tromba, G.; Castelli, E

    2001-04-01

    FRONTier RADiography is an R and D project to assess the feasibility of digital mammography with Synchrotron Radiation at the ELETTRA Light Source in Trieste. In order to reach an acceptable time duration of the exam, a fast- and low-noise photon counting ASIC has been developed in collaboration with Aurelia Microelettronica, called Frontrad ReadOut SysTem. It is a multichannel counting system, each channel being made of a low-noise charge-sensitive preamplifier optimized for X-ray energy range (10-100 keV), a CR-RC{sup 2} shaper, a discriminator and a 16-bit counter. In order to set the discriminator threshold, a set of a global 6-bit DAC and a local (per channel) 3-bit DAC has been implemented within the ASIC. We report on the measurements done with the 8-channel prototype chip and the comparison with the simulation results.

  17. ASICs in nanometer and 3D technologies for readout of hybrid pixel detectors

    Science.gov (United States)

    Maj, Piotr; Grybos, Pawel; Kmon, Piotr; Szczygiel, Robert

    2013-07-01

    Hybrid pixel detectors working in a single photon counting mode are very attractive solutions for material science and medical X-ray imaging applications. Readout electronics of these detectors has to match the geometry of pixel detectors with an area of readout channel of 100 μm × 100 μm (or even less) and very small power consumption (a few tens of μW). New solutions of readout ASICs are going into directions of better spatial resolutions, higher data throughput and more advanced functionality. We report on the design and measurement results of two pixel prototype ASICs in nanometer technology and 3D technology which offer fast signal processing, low noise performance and advanced functionality per single readout pixel cell.

  18. Transmitting Performance Evaluation of ASICs for CMUT-Based Portable Ultrasound Scanners

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Diederichsen, Søren Elmin; Jørgensen, Ivan Harald Holger

    2017-01-01

    Portable ultrasound scanners (PUS) have, in recent years, raised a lot of attention, as they can potentially overcome some of the limitations of static scanners. However, PUS have a lot of design limitations including size and power consumption. These restrictions can compromise the image quality...... of the scanner. In order to overcome these restrictions, application specific integrated circuits (ASICs) are needed to implement the electronics. In this work, a comparative study of the transmitting performance of a capacitive micromachined ultrasonic transducer (CMUT) driven by a commercial generic ultrasound...... in the time and frequency domains. The difference in normalized signal amplitude evaluated at the center frequency of the CMUT is −1.9 dB and the measured bandwidth is equivalent. The ASIC consumes only 1.3% of the total power consumption used by the commercial transmitter....

  19. Comparative Analysis of ALU Implementation with RCA and Sklansky Adders In ASIC Design Flow

    Directory of Open Access Journals (Sweden)

    Abdul Rehman Buzdar

    2016-07-01

    Full Text Available An Arithmetic Logic Unit (ALU is the heart of every central processing unit (CPU which performs basic operations like addition, subtraction, multiplication, division and bitwise logic operations on binary numbers. This paper deals with implementation of a basic ALU unit using two different types of adder circuits, a ripple carry adder and a sklansky type adder. The ALU is designed using application specific integrated circuit (ASIC platform where VHDL hardware description language and standard cells are used. The target process technology is 130nm CMOS from the foundry ST Microelectronics. The Cadence EDA tools are used for the ASIC implementation. A comparative analysis is provided for the two ALU circuits designed in terms of area, power and timing requirements.

  20. Studies of the high rate coincidence timing response of the STiC and TOFPET ASICs for the SAFIR PET scanner

    Science.gov (United States)

    Becker, R.; Casella, C.; Corrodi, S.; Dissertori, G.; Fischer, J.; Howard, A.; Ito, M.; Lustermann, W.

    2016-12-01

    The proposed SAFIR PET detector will measure positron electron annihilations at injected activities up to 500 MBq in a mouse or rat. The system is required to have the best possible timing resolution in order to remove accidental coincidences (randoms) and maximise the image quality for short time frames allowing the possibility of 4-D kinetic modelling of simultaneous PET and MRI for the first time. Two different ASICs, TOFPET and STiC, have been investigated with LYSO crystal scintillators coupled to SiPM detectors and using 18F sources up to 480 MBq. Timing responses are very encouraging with a coincidence time resolution of ~100 ps measured at low activities, degrading to 130 ps at the foreseen scanner maximum event rate. Sensitivities for single event rates and coincidences are measured and compared with Geant4 Monte Carlo simulations.

  1. Timing and control requirements for a 32-channel AMU-ADC ASIC for the PHENIX detector

    Energy Technology Data Exchange (ETDEWEB)

    Emery, M.S.; Ericson, M.N.; Britton, C.L. Jr. [and others

    1998-02-01

    A custom CMOS Application Specific Integrated Circuit (ASIC) has been developed consisting of an analog memory unit (AMU) has been developed consisting of an analog memory unit (AMU) and analog to digital converter (ADC), both of which have been designed for applications in the PHENIX experiment. This IC consists of 32 pipes of analog memory with 64 cells per pipe. Each pipe also has its own ADC channel. Timing and control signal requirements for optimum performance are discussed in this paper.

  2. MATRIX: a 15 ps resistive interpolation TDC ASIC based on a novel regular structure

    Science.gov (United States)

    Mauricio, J.; Gascón, D.; Ciaglia, D.; Gómez, S.; Fernández, G.; Sanuy, A.

    2016-12-01

    This paper presents a 4-channel TDC ASIC with the following features: 15-ps LSB (9.34 ps after calibration), 10-ps jitter, commercial 180 nm technology. The main contribution of this work is the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit (patented), a two-dimensional regular structure with very good properties in terms of power consumption, area and low process variability.

  3. Large dynamic range 64-channel ASIC for CZT or CdTe detectors

    Energy Technology Data Exchange (ETDEWEB)

    Glasser, F. E-mail: francis.glasser@cea.fr; Villard, P.; Rostaing, J.P.; Accensi, M.; Baffert, N.; Girard, J.L

    2003-08-21

    We present a customized 64-channel ASIC, named ALIX, developed in a 0.8 {mu}m CMOS technology. This circuit is dedicated to measure charges from semi-conductor X-ray detectors like Cadmium Zinc Telluride (CZT) or Cadmium Telluride CdTe. The specificity of ALIX is to be able to measure charges over a very large dynamic range (from 10 fC to 3 nC), and to store eight measurements in a very short time (from every 250 ns to a few ms). Up to eight images are stored inside the ASIC and each image can be read out in 64 {mu}s. A new acquisition sequence can then be started. Two analog readouts are available, one for the X-ray signal and one for the offset and afterglow measurement in case of pulsed X-rays. The outputs are converted into digital values by two off-chip 14 bits Analog-to-Digital Converters (ADC). A first version of ALIX has been tested with CZT and CdTe detectors under high-energy pulsed X-ray photons (20 MeV, 60 ns pulses every 250 ns). We will present the different results of linearity and signal-to-noise ratio. A second version of ALIX has been designed with some corrections. Electrical tests performed on 85 ASICS showed that the corrections were successful. We are now able to integrate them behind a 64x32 pixels 1 mm pitch CZT detector. Such an ASIC could also be used for strip detectors where a large dynamic range and a fast response are necessary.

  4. Large dynamic range 64-channel ASIC for CZT or CdTe detectors

    Science.gov (United States)

    Glasser, F.; Villard, P.; Rostaing, J. P.; Accensi, M.; Baffert, N.; Girard, J. L.

    2003-08-01

    We present a customized 64-channel ASIC, named ALIX, developed in a 0.8 μm CMOS technology. This circuit is dedicated to measure charges from semi-conductor X-ray detectors like Cadmium Zinc Telluride (CZT) or Cadmium Telluride CdTe. The specificity of ALIX is to be able to measure charges over a very large dynamic range (from 10 fC to 3 nC), and to store eight measurements in a very short time (from every 250 ns to a few ms). Up to eight images are stored inside the ASIC and each image can be read out in 64 μs. A new acquisition sequence can then be started. Two analog readouts are available, one for the X-ray signal and one for the offset and afterglow measurement in case of pulsed X-rays. The outputs are converted into digital values by two off-chip 14 bits Analog-to-Digital Converters (ADC). A first version of ALIX has been tested with CZT and CdTe detectors under high-energy pulsed X-ray photons (20 MeV, 60 ns pulses every 250 ns). We will present the different results of linearity and signal-to-noise ratio. A second version of ALIX has been designed with some corrections. Electrical tests performed on 85 ASICS showed that the corrections were successful. We are now able to integrate them behind a 64×32 pixels 1 mm pitch CZT detector. Such an ASIC could also be used for strip detectors where a large dynamic range and a fast response are necessary.

  5. Active counter electrode in a-SiC electrochemical metallization memory

    Science.gov (United States)

    Morgan, K. A.; Fan, J.; Huang, R.; Zhong, L.; Gowers, R.; Ou, J. Y.; Jiang, L.; De Groot, C. H.

    2017-08-01

    Cu/amorphous-SiC (a-SiC) electrochemical metallization memory cells have been fabricated with two different counter electrode (CE) materials, W and Au, in order to investigate the role of CEs in a non-oxide semiconductor switching matrix. In a positive bipolar regime with Cu filaments forming and rupturing, the CE influences the OFF state resistance and minimum current compliance. Nevertheless, a similarity in SET kinetics is seen for both CEs, which differs from previously published SiO2 memories, confirming that CE effects are dependent on the switching layer material or type. Both a-SiC memories are able to switch in the negative bipolar regime, indicating Au and W filaments. This confirms that CEs can play an active role in a non-oxide semiconducting switching matrix, such as a-SiC. By comparing both Au and W CEs, this work shows that W is superior in terms of a higher R OFF/R ON ratio, along with the ability to switch at lower current compliances making it a favourable material for future low energy applications. With its CMOS compatibility, a-SiC/W is an excellent choice for future resistive memory applications.

  6. Development of a front end ASIC for Dark Matter directional detection with MIMAC

    CERN Document Server

    Richer, J P; Bourrion, O; Grignon, C; Guillaudin, O; Mayet, F; Santos, D

    2009-01-01

    A front end ASIC (BiCMOS-SiGe 0.35 um) has been developed within the framework of the MIMAC detector project, which aims at directional detection of non-baryonic Dark Matter. This search strategy requires 3D reconstruction of low energy (keV) tracks with a gazeous uTPC. The development of this front end ASIC is a key point in this project, allowing the 3D track reconstruction. Each ASIC monitors 16 strips of pixels with charge preamplifiers and their time over threshold is provided in real time by current discriminators via two serializing LVDS links working at 320 MHz. The charge is summed over the 16 strips and provided via a shaper. These specifications have been chosen in order to build an auto triggered electronic. An acquisition board and the related software were developed in order to validate this methodology on a prototype chamber. The prototype detector presents an anode where 2x96 strips are monitored.

  7. Development of a front end ASIC for Dark Matter directional detection with MIMAC

    Energy Technology Data Exchange (ETDEWEB)

    Richer, J.P.; Bosson, G. [Laboratoire de Physique Subatomique et de Cosmologie, Universite Joseph Fourier Grenoble 1, CNRS/IN2P3, Institut Polytechnique de Grenoble, 53, rue des Martyrs, Grenoble (France); Bourrion, O., E-mail: olivier.bourrion@lpsc.in2p3.f [Laboratoire de Physique Subatomique et de Cosmologie, Universite Joseph Fourier Grenoble 1, CNRS/IN2P3, Institut Polytechnique de Grenoble, 53, rue des Martyrs, Grenoble (France); Grignon, C.; Guillaudin, O.; Mayet, F.; Santos, D. [Laboratoire de Physique Subatomique et de Cosmologie, Universite Joseph Fourier Grenoble 1, CNRS/IN2P3, Institut Polytechnique de Grenoble, 53, rue des Martyrs, Grenoble (France)

    2010-08-21

    A front end ASIC (BiCMOS-SiGe 0.35{mu}m) has been developed within the framework of the MIMAC detector project, which aims at directional detection of non-baryonic Dark Matter. This search strategy requires 3D reconstruction of low energy (a few keV) tracks with a gaseous {mu}TPC. The development of this front end ASIC is a key point of the project, allowing the 3D track reconstruction. Each ASIC monitors 16 strips of pixels with charge preamplifiers and their time over threshold is provided in real time by current discriminators via two serializing LVDS links working at 320 MHz. The charge is summed over the 16 strips and provided via a shaper. These specifications have been chosen in order to build an auto triggered electronics. An acquisition board and the related software were developed in order to validate this methodology on a prototype chamber. The prototype detector presents an anode where 2x96 strips of pixels are monitored.

  8. 4 pi direction sensitive gamma imager with RENA-3 readout ASIC

    Science.gov (United States)

    Du, Yanfeng; Li, Wen; Yanoff, Brian; Gordon, Jeffrey; Castleberry, Donald

    2007-09-01

    A 4π direction-sensitive gamma imager is presented, using a 1 cm 3 3D CZT detector from Yinnel Tech and the RENA-3 readout ASIC from NOVA R&D. The measured readout system electronic noise is around 4-5 keV FWHM for all anode channels. The measured timing resolution between two channels within a single ASIC is around 10 ns and the resolution is 30 ns between two separate ASIC chips. After 3D material non-uniformity and charge trapping corrections, the measured single-pixel-event energy resolution is around 1% for Cs-137 at 662 keV using a 1 cm 3 CZT detector from Yinnel Tech with an 8 x 8 anode pixel array at 1.15 mm pitch. The energy resolution for two pixel events is 2.9%. A 10 uCi Cs-137 point source was moved around the detector to test the image reconstruction algorithms and demonstrate the source direction detection capability. Accurate source locations were reconstructed with around 200 two-pixel events within a total energy window +/-10 keV around the 662 keV full energy peak. The angular resolution FWHM at four of the five positions tested was between 0.05-0.07 steradians.

  9. CLARO: an ASIC for high rate single photon counting with multi-anode photomultipliers

    Science.gov (United States)

    Baszczyk, M.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Dorosz, P.; Fiorini, M.; Gotti, C.; Kucewicz, W.; Malaguti, R.; Pessina, G.

    2017-08-01

    The CLARO is a radiation-hard 8-channel ASIC designed for single photon counting with multi-anode photomultiplier tubes. Each channel outputs a digital pulse when the input signal from the photomultiplier crosses a configurable threshold. The fast return to baseline, typically within 25 ns, and below 50 ns in all conditions, allows to count up to 107 hits/s on each channel, with a power consumption of about 1 mW per channel. The ASIC presented here is a much improved version of the first 4-channel prototype. The threshold can be precisely set in a wide range, between 30 ke- (5 fC) and 16 Me- (2.6 pC). The noise of the amplifier with a 10 pF input capacitance is 3.5 ke- (0.6 fC) RMS. All settings are stored in a 128-bit configuration and status register, protected against soft errors with triple modular redundancy. The paper describes the design of the ASIC at transistor-level, and demonstrates its performance on the test bench.

  10. Plasmon-assisted optical vias for photonic ASICS

    Energy Technology Data Exchange (ETDEWEB)

    Skogen, Erik J.; Vawter, Gregory A.; Tauke-Pedretti, Anna

    2017-03-21

    The present invention relates to optical vias to optically connect multilevel optical circuits. In one example, the optical via includes a surface plasmon polariton waveguide, and a first optical waveguide formed on a first substrate is coupled to a second optical waveguide formed on a second substrate by the surface plasmon polariton waveguide. In some embodiments, the first optical waveguide includes a transition region configured to convert light from an optical mode to a surface plasmon polariton mode or from a surface plasmon polariton mode to an optical mode.

  11. Radiation Hardened Structured ASIC Platform for Rapid Chip Development for Very High Speed System on a Chip (SoC) and Complex Digital Logic Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Radiation Hardened Application Specific Integrated Circuits (ASICs) provide for the highest performance, lowest power and size for Space Missions. In order to...

  12. Magnet Misalignment Studies for the Front-end of the Neutrino Factory

    CERN Document Server

    Prior, G; Stratakis, D; Neuffer, D; Snopok, P; Rogers, C

    2013-01-01

    In the Neutrino Factory front-end the muon beam coming from the interaction of a high-power (4 MW) proton beam on a mercury jet target is transformed through a buncher, a phase rotator and an ionization cooling channel before entering the downstream acceleration system. The muon front-end channel is densely packed with solenoid magnets, normal conducting radio-frequency cavities and absorber windows for the cooling section. The tolerance to the misalignment of the different components has to be determined in order on one hand to set the limits beyond which the performance of the front-end channel would be degraded; on the other hand to optimize the design and assembly of the front-end cells such that the component alignment can be checked and corrected for where crucial for the performance of the channel. In this paper we show the results of some of the simulations of the frontend channel performance where the magnetic field direction has been altered compared to the baseline.

  13. Prediction and control of front-end curvature in hot finish rolling process

    Directory of Open Access Journals (Sweden)

    Kyunghun Lee

    2015-11-01

    Full Text Available The purpose of this study is to predict the front-end curvature in hot strip finishing mills and to prevent it by controlling the rolling conditions. A theoretical model based on the slab method is developed for predicting the front-end curvature by taking into account the entrance angle of the strip, the friction condition and the back tension. To validate the developed theoretical model, the theoretically obtained curvature value is compared with the results of finite element analysis. Consequently, it is shown that the calculation results of the theoretical model are in good agreement with the measured results of the finite element analysis. Furthermore, a curvature control model based on geometrical and mathematical approaches that can reduce the front-end curvature by the control of the roll speed ratio of the upper to lower rolls is proposed. The proposed curvature control model is verified by finite element analysis, and it is shown that the front-end curvature can be reduced considerably using the proposed model. Therefore, it is concluded that the proposed control model for reducing the front-end curvature in a hot strip finishing mill can be used to improve the quality of the rolled product.

  14. Magnet Misalignment Studies for the Front-end of the Neutrino Factory

    Energy Technology Data Exchange (ETDEWEB)

    Prior, G. [Canterbury U.; Efthymiopoulos, I. [CERN; Stratakis, D. [Brookhaven; Neuffer, D. [Fermilab; Snopok, P. [Fermilab; Rogers, C. [Rutherford

    2013-06-01

    In the Neutrino Factory front-end the muon beam coming from the interaction of a high-power (4 MW) proton beam on a mercury jet target is transformed through a buncher, a phase rotator and an ionization cooling channel before entering the downstream acceleration system. The muon front-end channel is densely packed with solenoid magnets, normal conducting radio-frequency cavities and absorber windows for the cooling section. The tolerance to the misalignment of the different components has to be determined in order on one hand to set the limits beyond which the performance of the front-end channel would be degraded; on the other hand to optimize the design and assembly of the front-end cells such that the component alignment can be checked and corrected for where crucial for the performance of the channel. In this paper we show the results of some of the simulations of the front-end channel performance where the magnetic field direction has been altered compared to the baseline.

  15. Front-End Electronics in calorimetry: from LHC to ILC

    Energy Technology Data Exchange (ETDEWEB)

    De La Taille, Ch.

    2009-09-15

    This report summarizes the electronics developments for liquid argon calorimeter read-out at LHC and the development carried out in the framework of the CALICE collaboration for those of the future linear collider (ILC). It also includes chips designed for multi-anode photomultipliers (MaPMT) used in the OPERA experiment or on ATLAS luminometer, which also find applications in medical imaging. Started in the early 90's, the development for ATLAS calorimetry was extremely challenging in terms of readout speed, radiation tolerance and measurement accuracy. The high speed has required a new approach using current-sensitive preamplifiers instead of charge sensitive ones and the redefinition of noise performance in terms of ENI. The preamplifiers developed at Orsay and the monolithic shapers are described in Chapter 1, including considerations of digital filtering, which was a new technique in our field. Chapter 2 is dedicated to the calibration system, designed and built by Orsay, for which the high performance and accuracy necessitated in-depth studies. The 3. chapter closes the studies for ATLAS with a summary of the detector measurements which had to be carried out on the 200 000 channels in order to understand and model the detector and achieve everywhere the accuracy and uniformity at per-cent level. These developments for ATLAS ended in 2004, although parallel work was also carried out for the NA48 and DO calorimeters which are not detailed here. The next generation of collider will require a new generation of calorimeters, much more granular, referred to as 'imaging calorimetry' with embedded read-out electronics. The ASICs developed for this purpose in the framework of the CALICE collaboration are described in Chapter 4. They integrate all the functionalities of amplification, digitization and read-out making them complex 'System-On-Chip' circuits extremely efficient that find many other applications. A family of 3 chips reads out the

  16. An ECG recording front-end with continuous-time level-crossing sampling.

    Science.gov (United States)

    Li, Yongjia; Mansano, Andre L; Yuan, Yuan; Zhao, Duan; Serdijn, Wouter A

    2014-10-01

    An ECG recording front-end with a continuous- time asynchronous level-crossing analog-to-digital converter (LC-ADC) is proposed. The system is a voltage and current mixed-mode system, which comprises a low noise amplifier (LNA), a programmable voltage-to-current converter (PVCC) as a programmable gain amplifier (PGA) and an LC-ADC with calibration DACs and an RC oscillator. The LNA shows an input referred noise of 3.77 μVrms over 0.06 Hz-950 Hz bandwidth. The total harmonic distortion (THD) of the LNA is 0.15% for a 10 mVPP input. The ECG front-end consumes 8.49 μW from a 1 V supply and achieves an ENOB up to 8 bits. The core area of the proposed front-end is 690 ×710 μm2, fabricated in a 0.18 μm CMOS technology.

  17. Interfirm collaboration in the Fuzzy Front-End of the innovation process

    DEFF Research Database (Denmark)

    Jørgensen, Jacob Høj; Goduscheit, René Chester; Bergenholtz, Carsten

    Innovation and innovation processes has traditionally been considered from the manufacturing companies' perspective. The innovation process is typically divided into a series of succeeding stages where the Fuzzy Front-End is the first stage to encounter. Several research projects have formulated...... and tendencies in formal R&D partnering relations. This paper, however, focuses on collaboration between independent companies prior to such formal agreements as joint ventures or other contractual agreements. This first phase of the innovation process is often referred to as the Fuzzy Front-End (FFE......) and is traditionally seen as an intra-organizational process (Jongbae & David 2002;Kim & Wilemon 2002e;Qingyu & William 2001;Reid & de Brentani 2004a). As the innovation process becomes an interfirm-collaboration the management of the Fuzzy Front-End also changes and calls for new ways of collaboration...

  18. A low noise CMOS RF front-end for UWB 6-9 GHz applications

    Energy Technology Data Exchange (ETDEWEB)

    Zhou Feng; Gao Ting; Lan Fei; Li Wei; Li Ning; Ren Junyan, E-mail: w-li@fudan.edu.cn [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2010-11-15

    An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented. A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13 {mu}m RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB, an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of -12.6 dBm while in the low gain mode. This RF front-end consumes 17 mA from a 1.2 V supply voltage.

  19. Preparation for the upgrade of CMS Hadron Endcap Calorimeter front-end

    Science.gov (United States)

    Bychkova, O. V.; Popova, E. V.; Parygin, P. P.; Bunin, P. D.; Kalinin, A. Yu

    2017-01-01

    The hadron endcap (HE) calorimeter is one of the major sections of CMS detector, used for measurement of the hadrons energy. Phase1 upgrade of the front-end electronics components in the HE calorimeter is being prepared, in particular to improve ability to handle increased pile-up and mitigate radiation damage of optical system in the high eta region. Tests of Phase1 HE Front-end system including new photo-sensors, silicon photomultipliers (SiPM), as well as new charge integrator encoder (QIE11) were performed in the Burn-in station in b904 at CERN. In this note, analysis and measurement results for the new generation front-end electronics components are presented.

  20. Front-end Electronics Test for the LHCb Muon Wire Chambers

    CERN Document Server

    Nobrega, R; Carboni, G; Massafferri, A; Santovetti, E

    2007-01-01

    This document describes the apparatus and procedures implemented to test Multi Wire Proportional Chambers (MWPC) after front-end assembly for the LHCb Muon Detector. Results of measurements of key noise parameters are also described. Given a fully equipped chamber, this system is able to diagnose every channel performing an analysis of front-end output drivers’ response and noise rate versus threshold. Besides, it allows to assess if the noise rate at the experiment threshold region is within appropriate limits. Aiming at an automatic, fast and user-friendly system for mass production tests of MWPC, the project has foreseen as well electronic identification of every chamber and front-end board, and data archiving in such a way to make it available to the Experiment Control System (ECS) while in operation.

  1. A wide bandwidth analog front-end circuit for 60-GHz wireless communication receiver

    Science.gov (United States)

    Furuta, M.; Okuni, H.; Hosoya, M.; Sai, A.; Matsuno, J.; Saigusa, S.; Itakura, T.

    2014-03-01

    This paper presents an analog front-end circuit for a 60-GHz wireless communication receiver. The feature of the proposed analog front-end circuit is a bandwidth more than 1-GHz wide. To expand the bandwidth of a low-pass filter and a voltage gain amplifier, a technique to reduce the parasitic capacitance of a transconductance amplifier is proposed. Since the bandwidth is also limited by on-resistance of the ADC sampling switch, a switch separation technique for reduction of the on-resistance is also proposed. In a high-speed ADC, the SNDR is limited by the sampling jitter. The developed high resolution VCO auto tuning effectively reduces the jitter of PLL. The prototype is fabricated in 65nm CMOS. The analog front-end circuit achieves over 1-GHz bandwidth and 27.2-dB SNDR with 224 mW Power consumption.

  2. Electronically Tunable Antenna Pair and Novel RF Front-End Architecture for Software-Defined Radios

    Directory of Open Access Journals (Sweden)

    Oh Sung-Hoon

    2005-01-01

    Full Text Available This paper proposes a novel RF front-end architecture for software-defined radios (SDRs based on an electronically tunable antenna pair controlled by an antenna control unit (ACU consisting of field effect transistor (FET switches and a field programmable gate array (FPGA. The fundamental gain-bandwidth limitations of electrically small antennas prevent a small antenna from having high efficiency and wide bandwidth simultaneously. In the age of miniaturization, especially in the wireless communication industries, a promising solution to this limitation is to introduce reconfigurable antennas that can be tuned electronically to different frequency bands with both high efficiency and narrow instantaneous bandwidth. This reconfigurable antenna technology not only simplifies current RF front-end architectures, but can be reprogrammed on demand to transmit and receive RF signals in any desired frequency band. This novel RF front-end architecture implemented by a reconfigurable antenna pair can help realize SDRs.

  3. SEMICONDUCTOR INTEGRATED CIRCUITS Design of an analog front-end for ambulatory biopotential measurement systems

    Science.gov (United States)

    Jiazhen, Wang; Jun, Xu; Lirong, Zheng; Junyan, Ren

    2010-10-01

    A continuously tunable gain and bandwidth analog front-end for ambulatory biopotential measurement systems is presented. The front-end circuit is capable of amplifying and conditioning different biosignals. To optimize the power consumption and simplify the system architecture, the front-end only adopts two-stage amplifiers. In addition, careful design eliminates the need for chopping circuits. The input-referred noise of the system is only 1.19 μVrms (0.48-2000 Hz). The chip is fabricated via a SMIC 0.18 μm CMOS process. Although the power consumption is only 32.1 μW under a 3 V voltage supply, test results show that the chip can successfully extract biopotential signals.

  4. Low power Analog Digital Converter for a silicon photomultiplier readout ASIC

    Science.gov (United States)

    Briggl, K.; Chen, H.; Shen, W.; Schultz-Coulon, H. C.

    2015-04-01

    We present an ADC designed in the UMC 0.18um CMOS technology. It will be used in the SiPM analog front-end ``KLauS" developed for the analog hadronic calorimeter at ILD. Key parameter in this application is an extremely low power consumption of the front-end electronics. For quantization of the energy depositions, a 10-bit ADC resolution is required. For calibration purposes, a 12-bit quantization is used. A successive approximation register split capacitor array structure is chosen to minimize the DC power consumption. A peak sensing block is used to minimize the required sampling rate. We present design details and simulation results of the ADC, as well as the peak sensing track & hold circuit.

  5. Coxsackievirus and adenovirus receptor (CAR) mediates trafficking of acid sensing ion channel 3 (ASIC3) via PSD-95.

    Science.gov (United States)

    Excoffon, Katherine J D A; Kolawole, Abimbola O; Kusama, Nobuyoshi; Gansemer, Nicholas D; Sharma, Priyanka; Hruska-Hageman, Alesia M; Petroff, Elena; Benson, Christopher J

    2012-08-17

    We have previously shown that the Coxsackievirus and adenovirus receptor (CAR) can interact with post-synaptic density 95 (PSD-95) and localize PSD-95 to cell-cell junctions. We have also shown that activity of the acid sensing ion channel (ASIC3), a H(+)-gated cation channel that plays a role in mechanosensation and pain signaling, is negatively modulated by PSD-95 through a PDZ-based interaction. We asked whether CAR and ASIC3 simultaneously interact with PSD-95, and if so, whether co-expression of these proteins alters their cellular distribution and localization. Results indicate that CAR and ASIC3 co-immunoprecipitate only when co-expressed with PSD-95. CAR also brings both PSD-95 and ASIC3 to the junctions of heterologous cells. Moreover, CAR rescues PSD-95-mediated inhibition of ASIC3 currents. These data suggest that, in addition to activity as a viral receptor and adhesion molecule, CAR can play a role in trafficking proteins, including ion channels, in a PDZ-based scaffolding complex. Copyright © 2012 Elsevier Inc. All rights reserved.

  6. Implementation of Low-Cost UHF RFID Reader Front-Ends with Carrier Leakage Suppression Circuit

    Directory of Open Access Journals (Sweden)

    Bin You

    2013-01-01

    Full Text Available A new ultrahigh frequency radio frequency identification (UHF RFID reader’s front-end circuit which is based on zero-IF, single antenna structure and composed of discrete components has been designed. The proposed design brings a significant improvement of the reading performance by adopting a carrier leakage suppression (CLS circuit instead of a circulator which is utilized by most of the conventional RF front-end circuit. Experimental results show that the proposed design improves both the sensitivity and detection range compared to the conventional designs.

  7. Safe operating conditions for NSLS-II Storage Ring Frontends commissioning

    Energy Technology Data Exchange (ETDEWEB)

    Seletskiy, S. [Brookhaven National Lab. (BNL), Upton, NY (United States); Amundsen, C. [Brookhaven National Lab. (BNL), Upton, NY (United States); Ha, K. [Brookhaven National Lab. (BNL), Upton, NY (United States); Hussein, A. [Brookhaven National Lab. (BNL), Upton, NY (United States)

    2015-04-02

    The NSLS-II Storage Ring Frontends are designed to safely accept the synchrotron radiation fan produced by respective insertion device when the electron beam orbit through the ID is locked inside the predefined Active Interlock Envelope. The Active Interlock is getting enabled at a particular beam current known as AI safe current limit. Below such current the beam orbit can be anywhere within the limits of the SR beam acceptance. During the FE commissioning the beam orbit is getting intentionally disturbed in the particular ID. In this paper we explore safe operating conditions for the Frontends commissioning.

  8. Simple Front-End Concept for the Complex Challenges of Multi-Band Communications

    DEFF Research Database (Denmark)

    Buskgaard, Emil Feldborg; Tatomirescu, Alexandru; Barrio, Samantha Caporal Del

    2015-01-01

    This paper proposes a new architecture for mobile phone front-ends that dramatically reduces the complexity of multi-band smart phones. Traditional smart phone front-ends consist of many parallel transmit (Tx) and receive (Rx) chains each dedicated to a single band. The proposed architecture...... with additional tunable Rx and Tx filters the Rx/Tx isolation reaches 50 dB which is comparable with the isolation achieved with commercially available static duplex filters. Based on these antenna designs it is concluded that the proposed architecture is feasible for LTE phones and makes full coverage of all LTE...

  9. A new approach to front-end electronics interfacing in the ATLAS experiment

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00015561; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Wu, Weihao; Zhang, Jinlong

    2016-01-01

    For new detector and trigger systems to be installed in the ATLAS experiment after LHC Run 2, a new approach will be followed for Front-End electronics interfacing. The FELIX (Front-End LInk eXchange) system will function as gateway connecting: on one side to detector and trigger electronics links, as well as providing timing and trigger (TTC) information; and on the other side a commodity switched network built using standard technology (either Ethernet or Infiniband). The new approach is described in this paper, and results achieved so far are presented.

  10. TARGET: A digitizing and trigger ASIC for the Cherenkov telescope array

    Science.gov (United States)

    Funk, S.; Jankowsky, D.; Katagiri, H.; Kraus, M.; Okumura, A.; Schoorlemmer, H.; Shigenaka, A.; Tajima, H.; Tibaldo, L.; Varner, G.; Zink, A.; Zorn, J.

    2017-01-01

    The future ground-based gamma-ray observatory Cherenkov Telescope Array (CTA) will feature multiple types of imaging atmospheric Cherenkov telescopes, each with thousands of pixels. To be affiordable, camera concepts for these telescopes have to feature low cost per channel and at the same time meet the requirements for CTA in order to achieve the desired scientific goals. We present the concept of the TeV Array Readout Electronics with GSa/s sampling and Event Trigger (TARGET) Application Specific Circuit (ASIC), envisaged to be used in the cameras of various CTA telescopes, e.g. the Gamma-ray Cherenkov Telescope (GCT), a proposed 2-Mirror Small-Sized Telescope, and the Schwarzschild-Couder Telescope (SCT), a proposed Medium-Sized Telescope. In the latest version of this readout concept the sampling and trigger parts are split into dedicated ASICs, TARGET C and T5TEA, both providing 16 parallel input channels. TARGET C features a tunable sampling rate (usually 1 GSa/s), a 16k sample deep buffier for each channel and on-demand digitization and transmission of waveforms with typical spans of ˜100 ns. The trigger ASIC, T5TEA, provides 4 low voltage diffierential signal (LVDS) trigger outputs and can generate a pedestal voltage independently for each channel. Trigger signals are generated by T5TEA based on the analog sum of the input in four independent groups of four adjacent channels and compared to a threshold set by the user. Thus, T5TEA generates four LVDS trigger outputs, as well as 16 pedestal voltages fed to TARGET C independently for each channel. We show preliminary results of the characterization and testing of TARGET C and T5TEA.

  11. Racing of ASIC Versus FPGA%论ASIC与FPGA之争

    Institute of Scientific and Technical Information of China (English)

    韩俊刚

    2004-01-01

    论述现场可编程门阵列(FPGA)产品的发展情况和对于专用集成电路(ASIC)的影响.介绍了目前国际上对FPGA和ASIC的竞争问题的讨论,同时对ASIC和FPGA进行了简单的比较,并对FPGA的新的应用领域作了介绍.最后提出发展我国FPGA产业的建议.

  12. An introduction to future truly wearable medical devices--from application to ASIC.

    Science.gov (United States)

    Casson, Alexander J; Logesparan, Lojini; Rodriguez-Villegas, Esther

    2010-01-01

    This talk will provide an introduction to the "Towards future truly wearable medical devices: from application to ASIC" mini-symposium. For user comfort and acceptance long term physiological sensors must be discrete, comfortable and easy to use. These requirements place stringent limits on all aspects of the system design: from the overall application aim, to power generation issues, to low power electronic design techniques. For successful devices design issues in all of these areas must be solved simultaneously. The work here presents an overview and introduction to these topics.

  13. Development of an ASIC for CCD readout at the vertex detectors of the intrenational linear collider

    CERN Document Server

    Murray, P; Stefanov, K D; Woolliscroft, T

    2007-01-01

    The Linear Collider Flavour Identification Collaboration is developing sensors and readout electronics suitable for the International Linear Collider vertex detector. In order to achieve high data rates the proposed detector utilises column parallel CCDs, each read out by a custom designed ASIC. The prototype chip (CPR2) has 250 channels of electronics, each with a preamplifier, 5-bit flash ADC, data sparsification logic for identification of significant data clusters, and local memory for storage of data awaiting readout. CPR2 also has hierarchical 2-level data multiplexing and intermediate data memory, enabling readout of the sparsified data via the 5-bit data output bus.

  14. QIE12: A New High-Performance ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration; Proudfoot, James; Stanek, Robert; Chekanov, Sergei

    2015-01-01

    We present results on the QIE12, a custom ASIC, being developed for the ATLAS TileCal Phase 2 Upgrade. The design features 1.5 fC sensitivity, more than 17 bits of dynamic range with logarithmic response, and an on-chip TDC with one nanosecond resolution. It has a programmable shunt output for monitoring the integrated current. The device operates with no dead-time at 40 MHz, making it ideal for calorimetry at the LHC. We present bench measurements and integration studies that characterize the performance, radiation tolerance measurements, and the design for the ATLAS TileCal detector for the Phase 2 Upgrade.

  15. Low-noise multichannel ASIC for high count rate X-ray diffractometry applications

    Energy Technology Data Exchange (ETDEWEB)

    Szczygiel, R. [AGH University of Science and Technology, Department of Measurement and Instrumentation, al. Mickiewicza 30, Krakow (Poland)], E-mail: robert.szczygiel@agh.edu.pl; Grybos, P.; Maj, P. [AGH University of Science and Technology, Department of Measurement and Instrumentation, al. Mickiewicza 30, Krakow (Poland); Tsukiyama, A.; Matsushita, K.; Taguchi, T. [Rigaku Corporation, 3-9-12 Matsubara-cho, Akishima-shi, Tokyo (Japan)

    2009-08-01

    RG64 is a 64-channel ASIC designed for the silicon strip detector readout and optimized for high count rate X-ray imaging applications. In this paper we report on the test results referring to the RG64 noise level, channel uniformity and the operation with a high rate of input signals. The parameters of the RG64-based diffractometry system are compared with the ones based on the scintillation counter. Diffractometry measurement results with silicon strip detectors of different strip lengths and strip pitch are also presented.

  16. Recent progress in front end ASICs for high-energy physics

    CERN Document Server

    Hall, G

    2005-01-01

    Developments of Application Specific Integrated Circuits (ASICs) for applications in the CMS experiment are briefly described, along with the motivations for the choice of technology, focussing especially on silicon strip readout of the CMS tracker. The major change in the last few years has been the widespread adoption in CMS of a commercial deep sub-micron CMOS technology in preference to specific radiation-hardened processes which seemed to be the only solution meeting the LHC requirements only a few years ago. The reasons for this are described and the performance of representative chips and the technology presented. The implications for future developments are outlined.

  17. A 64ch readout module for PPD/MPPC/SiPM using EASIROC ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Nakamura, Isamu, E-mail: isamu.nakamura@kek.jp [KEK, 1-1 Oho Tsukuba 305-0801 (Japan); Ishijima, N.; Hanagaki, K. [Osaka University, 1-1 Machikaneyama, Toyonaka, Osaka 560-0043 (Japan); Yoshimura, K. [Okayama University, 1-1 Tsushimanaka, Kita-ku, Okayama 700-8530 (Japan); Nakai, Y. [Kyushu University, 6-10-1 Hakozaki, Higashi-ku, Fukuoka 812-8581 (Japan); Ueno, K. [KEK, 1-1 Oho Tsukuba 305-0801 (Japan)

    2015-07-01

    A readout module for PPD/MPPC/GAPD/SiPM is developed using EASIROC ASIC. The module can handle 64 PPDs and has on-board bias power supply, ADC for energy measurement, 1 ns TDC on FPGA as well as 64ch Logic output for external trigger. Controls and data transfer are through SiTCP technology implemented in FPGA. The module has NIM format for convenience, but can be operated without crate with 5 V AC/DC converter. Basic performance of production module was tested and the results are presented in the poster.

  18. Operational Studies of Cadmium Zinc Telluride Microstrip Detectors using SVX ASIC Electronics

    Science.gov (United States)

    Krizmanic, John; Barbier, L. M.; Barthelmy, S.; Bartlett, L.; Birsa, F.; Gehrels, N.; Hanchak, C.; Kurczynski, P.; Odom, J.; Parsons, A.; Palmer, D.; Sheppard, D.; Snodgrass, S.; Stahle, C. M.; Teegarden, B.; Tueller, J.

    1997-04-01

    We have been investigating the operational properties of cadmium zinc telluride (CZT) microstrip detectors by using SVX ASIC readout electronics. This research is in conjunction with the development of a CZT-based, next generation gamma-ray telescope for use in the gamma-ray Burst ArcSecond Imaging and Spectroscopy (BASIS) experiment. CZT microstrip detectors with 128 channels and 100 micron strip pitch have been fabricated and were interfaced to SVX electronics at Goddard Space Flight Center. Experimental results involving position sensing, spectroscopy, and CZT operational properties will be presented.

  19. Performance and Calibration of H2RG Detectors and SIDECAR ASICs for the RATIR Camera

    Science.gov (United States)

    Fox, Ori D.; Kutyrev, Alexander S.; Rapchun, David A.; Klein, Christopher R.; Butler, Nathaniel R.; Bloom, Josh; de Diego, Jos A.; Simn Farah, Alejandro D.; Gehrels, Neil A.; Georgiev, Leonid; Gonzlez-Hernandez, J. Jess; Lee, William H.; Loose, Markus; Lotkin, Gennadiy; Moseley, Samuel H.; Prochaska, J. Xavier; Ramirez-Ruiz, Enrico; Richer, Michael G.; Robinson, Frederick D.; Romn-Zuniga, Carols; Samuel, Mathew V.; Sparr, Leroy M.; Watson, Alan M.

    2012-01-01

    The Reionization And Transient Infra,.Red (RATIR) camera has been built for rapid Gamma,.Ray Burst (GRE) followup and will provide simultaneous optical and infrared photometric capabilities. The infrared portion of this camera incorporates two Teledyne HgCdTe HAWAII-2RG detectors, controlled by Teledyne's SIDECAR ASICs. While other ground-based systems have used the SIDECAR before, this system also utilizes Teledyne's JADE2 interface card and IDE development environment. Together, this setup comprises Teledyne's Development Kit, which is a bundled solution that can be efficiently integrated into future ground-based systems. In this presentation, we characterize the system's read noise, dark current, and conversion gain.

  20. CLARO-CMOS, an ASIC for single photon counting with Ma-PMTs, MCPs and SiPMs

    Science.gov (United States)

    Carniti, P.; Cibinetto, G.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Maino, M.; Malaguti, R.; Pessina, G.

    2013-01-01

    An ASIC named CLARO-CMOS was designed for fast photon counting with MaPMTs, MCPs and SiPMs. The prototype was realized in a .35 μm CMOS technology and has four channels, each with a fast amplifier and a discriminator. The main features of the design are the high speed of operation and the low power dissipation, below 1 mW per channel. This paper focuses on the use of the CLARO for SiPM readout. The ASIC was tested with several SiPMs of various sizes, connected to the input of the chip both directly and through a coaxial cable about one meter long. In the latter case the ASIC is still fully functional although the speed of response is affected by the cable capacitance. The threshold could be set just above the single photoelectron level, and with 1 ×1 mm2 SiPMs the discrete photoelectron peaks could be well resolved.

  1. A four channel time-to-digital converter ASIC with in-built calibration and SPI interface

    Energy Technology Data Exchange (ETDEWEB)

    Hari Prasad, K.; Sukhwani, Menka [Electronics Division, Bhabha Atomic Research Center, Mumbai 400085 (India); Saxena, Pooja [Homi Bhabha National Institute, Mumbai 400094 (India); Chandratre, V.B., E-mail: vbc@barc.gov.in [Electronics Division, Bhabha Atomic Research Center, Mumbai 400085 (India); Pithawa, C.K. [Electronics Division, Bhabha Atomic Research Center, Mumbai 400085 (India)

    2014-02-11

    A design of high resolution, wide dynamic range Time-to-Digital Converter (TDC) ASIC, implemented in 0.35 µm commercial CMOS technology is presented. The ASIC features four channel TDC with an in-built calibration and Serial Peripheral Interconnect (SPI) slave interface. The TDC is based on the vernier ring oscillator method in order to achieve both high resolution and wide dynamic range. This TDC ASIC is tested and found to have resolution of 127 ps (LSB), dynamic range of 1.8 µs and precision (σ) of 74 ps. The measured values of differential non-linearity (DNL) and integral non-linearity (INL) are 350 ps and 300 ps respectively.

  2. High-density expression of Ca2+-permeable ASIC1a channels in NG2 glia of rat hippocampus.

    Directory of Open Access Journals (Sweden)

    Yen-Chu Lin

    Full Text Available NG2 cells, a fourth type of glial cell in the mammalian CNS, undergo reactive changes in response to a wide variety of brain insults. Recent studies have demonstrated that neuronally expressed acid-sensing ion channels (ASICs are implicated in various neurological disorders including brain ischemia and seizures. Acidosis is a common feature of acute neurological conditions. It is postulated that a drop in pH may be the link between the pathological process and activation of NG2 cells. Such postulate immediately prompts the following questions: Do NG2 cells express ASICs? If so, what are their functional properties and subunit composition? Here, using a combination of electrophysiology, Ca2+ imaging and immunocytochemistry, we present evidence to demonstrate that NG2 cells of the rat hippocampus express high density of Ca2+-permeable ASIC1a channels compared with several types of hippocampal neurons. First, nucleated patch recordings from NG2 cells revealed high density of proton-activated currents. The magnitude of proton-activated current was pH dependent, with a pH for half-maximal activation of 6.3. Second, the current-voltage relationship showed a reversal close to the equilibrium potential for Na+. Third, psalmotoxin 1, a blocker specific for the ASIC1a channel, largely inhibited proton-activated currents. Fourth, Ca2+ imaging showed that activation of proton-activated channels led to an increase of [Ca2+]i. Finally, immunocytochemistry showed co-localization of ASIC1a and NG2 proteins in the hippocampus. Thus the acid chemosensor, the ASIC1a channel, may serve for inducing membrane depolarization and Ca2+ influx, thereby playing a crucial role in the NG2 cell response to injury following ischemia.

  3. Advances ,n Digital Front-End and Software RF Processing: Part I

    Institute of Scientific and Technical Information of China (English)

    2011-01-01

    One of the biggest technology trends in wireless broadband, radar, sonar, and broadcasting systems is software radio frequency processing and digital front-end. This trend encompasses a broad range of topics, from circuit design and signal processing to system integration. It includes digital up-conversion (DUC) and down-conversion (DDC), digital predistortion (DPD),

  4. Radiation hardness improvement of analog front-end microelectronic devices for particle accelerator

    Science.gov (United States)

    Miroshnichenko, A. G.; Rodin, A. S.; Bakerenkov, A. S.; Felitsyn, V. A.

    2016-10-01

    Series of schematic techniques for increasing radiation hardness of the current mirrors is developed. These techniques can be used for the design of analog front-end microelectronic devices based on the operational amplifiers. The circuit simulation of radiation degradation of current transmission coefficients was performed for various circuit solutions in LTSpice software.

  5. The front-end amplifier for the silicon microstrip sensors of the PANDA MVD

    Energy Technology Data Exchange (ETDEWEB)

    Di Pietro, Valentino; Brinkmann, Kai-Thomas; Riccardi, Alberto [II. Physikalisches Institut, JLU Giessen (Germany); Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino (Italy)

    2015-07-01

    The most common readout systems designed for the nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made from two main building blocks: front-end amplifier and ADC. One of the issues associated with the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the possibility of using time-based architectures offering better performances from that point of view. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work will present the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The key features of the front-end amplifier are illustrated and both schematic level, and post-layout simulations are discussed.

  6. InP DHBT MMICs for millimeter-wave front-ends

    DEFF Research Database (Denmark)

    Johansen, Tom Keinicke; Hadziabdic, Dzenan; Krozer, Viktor

    2009-01-01

    In this paper, we show advanced MMIC's using InP DHBT technology. In particular, we demonstrate front-end circuits covering a broad frequency range from Q-band to E-band. Realizations of power amplifiers, quadrature VCOs, and sub-harmonic mixers, are presented and experimental results are discussed....

  7. Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell

    DEFF Research Database (Denmark)

    Liscidini, Antonio; Mazzanti, Andrea; Tonietto, Riccardo;

    2006-01-01

    This paper presents the first quadrature RF receiver front-end where, in a single stage, low-noise amplifier (LNA), mixer and voltage-controlled oscillator (VCO) share the same bias current. The new structure exploits the intrinsic mixing functionality of a classical LC-tank oscillator providing...

  8. Extracting whole short rotation trees with a skidder and a front-end loader

    Science.gov (United States)

    R. Spinelli; B.R. Hartsough

    2001-01-01

    We time-studied a Caterpillar 950F front-end loader and a Caterpillar 528 grapple skidder used to extract bunched whole trees to a landing in a short rotation Eucalyptus plantation. The loader was 40-60% more productive than the grapple skidder, depending on extraction distance. Alternatively, the single loader could both extract trees and handle the landing duties,...

  9. 2 MV Injector as the Elise Front-End and as an Experimental Facility

    Energy Technology Data Exchange (ETDEWEB)

    Yu, S S; Eylon, S; Henestroza, E; Peters, C; Reginato, L; Tauschwitz, A; Grote, D; Deadrick, F

    1999-12-07

    We report on progress in the preparation of the 2 MV Injector at LBNL as the front-end of Elise, and as a multi-purpose experimental facility for Heavy Ion Fusion beam dynamics studies. Recent advances on the performance and understanding of the injector are described, and some of the on-going experimental activities are summarized.

  10. BGO front-end electronics and signal processing in the MXGS instrument for the ASIM mission

    DEFF Research Database (Denmark)

    Skogseide, Yngve; Cenkeramaddi, Linga Reddy; Genov, Georgi

    2012-01-01

    This paper presents the Bismuth Germanate Oxide (BGO) front-end electronics design and signal processing in Modular X- and Gamma ray sensor (MXGS) instrument onboard the Atmosphere Space Interaction Monitor (ASIM) mission, funded by the European Space Agency. University of Bergen is responsible...

  11. Front-End Types. Automotive Mechanics. Steering & Suspension. Instructor's Guide [and] Student Guide.

    Science.gov (United States)

    Spignesi, B.

    This instructional package, one in a series of individualized instructional units on automotive steering and suspension, consists of a student guide and an instructor guide dealing with automobile front-end types. Covered in the module are three common types of passenger car front suspension systems and their major components as well as two types…

  12. Impact of Fast Shaping at the Front-end on Signals from Micro Strip Gas Chambers

    CERN Document Server

    Sciacca, G F

    1997-01-01

    The ballistic deficit due to fast shaping time constants at the front-end amplifier is evaluated using Monte Carlo generated events simulating isolated hits in MSGCs of CMS performance. The effect of the track incidence angle is also investigated up to 45 degrees.

  13. Status on the development of front-end and readout electronics for large silicon trackers

    Indian Academy of Sciences (India)

    J David; M Dhellot; J-F Genat; F Kapusta; H Lebbolo; T-H Pham; F Rossel; A Savoy-Navarro; E Deumens; P Mallisse; D Fougeron; R Hermel; Y Karyotakis; S Vilalte

    2007-12-01

    Final results on a CMOS 0.18 m front-end chip for silicon strips readout are summarized and preliminary results on time measurement are discussed. The status of the next version in 0.13 m is briefly presented.

  14. Quantitative Analysis of the Civilian Bilateral Cooperation in Front-End of the Nuclear Fuel Cycle

    Energy Technology Data Exchange (ETDEWEB)

    Nguyen, Viet Phuong; Yim, Man-Sung [Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of)

    2015-05-15

    A substantial part of such cooperation is related to the front-end of the nuclear fuel cycle, which encompasses the processes that help manufacturing nuclear fuel, including mining and milling of natural uranium, refining and chemical conversion, enrichment (in case of fuels for Pressurized Water Reactor PWR), and fuel fabrication. Traditionally, the supply of natural uranium was dominated by Canada and Australia, whereas enrichment services have been mostly provided by companies from Western states or Russia, which are also the main customers of such services. However, Kazakhstan and African countries like Niger, Namibia, and Malawi have emerged as important suppliers in the international uranium market and recent forecasts show that China will soon become a major player in the front-end market as both consumer and service provider. In this paper, the correlation between bilateral civil nuclear cooperation in front-end of the nuclear fuel cycle and the political and economic relationship among countries was examined through a dataset of bilateral nuclear cooperation in the post-Cold War era, from 1990 to 2011. Such finding has implication on not only the nonproliferation research but also the necessary reinforcement of export control regimes like such as the Nuclear Suppliers Group. Further improvement of this dataset and the regression method are also needed in order to increase the robustness of the findings as well as to cover the whole scope of the nuclear fuel cycle, including both front-end and back-end activities.

  15. Design of analog front-ends for the RD53 demonstrator chip

    CERN Document Server

    Gaioni, L; Nodari, B; Manghisoni, M; Re, V; Traversi, G; Barbero, M B; Fougeron, D; Gensolen, F; Godiot, S; Menouni, M; Pangaud, P; Rozanov, A; Wang, A; Bomben, M; Calderini, G; Crescioli, F; Le Dortz, O; Marchiori, G; Dzahini, D; Rarbi, F E; Gaglione, R; Gonella, L; Hemperek, T; Huegging, F; Karagounis, M; Kishishita, T; Krueger, H; Rymaszewski, P; Wermes, N; Ciciriello, F; Corsi, F; Marzocca, C; De Robertis, G; Loddo, F; Licciulli, F; Andreazza, A; Liberali, V; Shojaii, S; Stabile, A; Bagatin, M; Bisello, D; Mattiazzo, S; Ding, L; Gerardin, S; Giubilato, P; Neviani, A; Paccagnella, A; Vogrig, D; Wyss, J; Bacchetta, N; Della Casa, G; Demaria, N; Mazza, G; Rivetti, A; Da Rocha Rolo, M D; Comotti, D; Ratti, L; Vacchi, C; Beccherle, R; Bellazzini, R; Magazzu, G; Minuti, M; Morsani, F; Palla, F; Poulios, S; Fanucci, L; Rizzi, A; Saponara, S; Androsov, K; Bilei, G M; Menichelli, M; Conti, E; Marconi, S; Passeri, D; Placidi, P; Monteil, E; Pacher, L; Paternò, A; Gajanana, D; Gromov, V; Hessey, N; Kluit, R; Zivkovic, V; Havranek, M; Janoska, Z; Marcisovsky, M; Neue, G; Tomasek, L; Kafka, V; Sicho, P; Vrba, V; Vila, I; Lopez-Morillo, E; Aguirre, M A; Palomo, F R; Muñoz, F; Abbaneo, D; Christiansen, J; Dannheim, D; Dobos, D; Linssen, L; Pernegger, H; Valerio, P; Alipour Tehrani, N; Bell, S; Prydderch, M L; Thomas, S; Christian, D C; Fahim, F; Hoff, J; Lipton, R; Liu, T; Zimmerman, T; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gorelov, I; Hoeferkamp, M; Seidel, S; Toms, K; De Witt, J N; Grillo, A

    2017-01-01

    The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

  16. Front-end XY-slits assembly for the SPring-8 undulator beamlines.

    Science.gov (United States)

    Oura, M; Sakurai, Y; Kitamura, H

    1998-05-01

    A front-end XY-slits assembly has been designed for the SPring-8 undulator beamlines. This assembly can handle the high heat flux from the undulator, its grazing-incidence L-shaped configuration employing an enhanced heat-transfer technology.

  17. Front-end Electronics for Unattended Measurement (FEUM). Prototype Test Plan

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C.; Morris, Scott J.; Smith, Leon E.; Keller, Daniel T.

    2015-09-16

    The IAEA has requested that PNNL perform an initial set of tests on front-end electronics for unattended measurement (FEUM) prototypes. The FEUM prototype test plan details the tests to be performed, the criteria for evaluation, and the procedures used to execute the tests.

  18. Compact Front-end Prototype for Next Generation RFI-rejecting Polarimetric L-band Radiometer

    DEFF Research Database (Denmark)

    Jensen, Brian Sveistrup; Søbjærg, Sten Schmidl; Skou, Niels

    2009-01-01

    Realizing the need for lower noise figure and smaller physical size in todays higly sensitive radiometers, this paper presents a new compact analog front-end (AFE) for use with the existing L-band (1400-1427 MHz) radiometer designed and operated by the Technical University of Denmark. Using...

  19. Experimental demonstration of a scalable transmitter frontend technique in IMDD-OFDMA-PON upstream scheme

    Science.gov (United States)

    Ju, Cheng; Liu, Na; Wang, Dongdong; Zhang, Zhiguo; Chen, Xue

    2016-11-01

    Scalable transmitter frontend scheme is proposed to reduce the sampling rate of digital-to-analog converter (DAC) and the complexity of digital signal processing (DSP) in intensity modulation and direct detection (IMDD) OFDMA-PON upstream scenarios. The hardware cost of each ONU is substantially decreased. The feasibility of the proposed scheme is experimentally demonstrated.

  20. The interaction between the first transmembrane domain and the thumb of ASIC1a is critical for its N-glycosylation and trafficking.

    Directory of Open Access Journals (Sweden)

    Lan Jing

    Full Text Available Acid-sensing ion channel-1a (ASIC1a, the primary proton receptor in the brain, contributes to multiple diseases including stroke, epilepsy and multiple sclerosis. Thus, a better understanding of its biogenesis will provide important insights into the regulation of ASIC1a in diseases. Interestingly, ASIC1a contains a large, yet well organized ectodomain, which suggests the hypothesis that correct formation of domain-domain interactions at the extracellular side is a key regulatory step for ASIC1a maturation and trafficking. We tested this hypothesis here by focusing on the interaction between the first transmembrane domain (TM1 and the thumb of ASIC1a, an interaction known to be critical in channel gating. We mutated Tyr71 and Trp287, two key residues involved in the TM1-thumb interaction in mouse ASIC1a, and found that both Y71G and W287G decreased synaptic targeting and surface expression of ASIC1a. These defects were likely due to altered folding; both mutants showed increased resistance to tryptic cleavage, suggesting a change in conformation. Moreover, both mutants lacked the maturation of N-linked glycans through mid to late Golgi. These data suggest that disrupting the interaction between TM1 and thumb alters ASIC1a folding, impedes its glycosylation and reduces its trafficking. Moreover, reducing the culture temperature, an approach commonly used to facilitate protein folding, increased ASIC1a glycosylation, surface expression, current density and slowed the rate of desensitization. These results suggest that correct folding of extracellular ectodomain plays a critical role in ASIC1a biogenesis and function.

  1. Performance of CATIROC: ASIC for smart readout of large photomultiplier arrays

    Science.gov (United States)

    Blin, S.; Callier, S.; Conforti Di Lorenzo, S.; Dulucq, F.; De La Taille, C.; Martin-Chassard, G.; Seguin-Moreau, N.

    2017-03-01

    CATIROC (Charge And Time Integrated Read Out Chip) is a complete read-out chip manufactured in AustriaMicroSystem (AMS) SiGe 0.35 μm technology, designed to read arrays of 16 photomultipliers (PMTs). It is an upgraded version of PARISROC2 [1] designed in 2010 in the context of the PMm2 (square meter PhotoMultiplier) project [2]. CATIROC is a SoC (System on Chip) that processes analog signals up to the digitization and sparsification to reduce the cost and cable number. The ASIC is composed of 16 independent channels that work in triggerless mode, auto-triggering on the single photo-electron. It provides a charge measurement up to 400 photoelectrons (70 pC) on two scales of 10 bits and a timing information with an accuracy of 200 ps rms. The ASIC was sent for fabrication in February 2015 and then received in September 2015. It is a good candidate for two Chinese projects (LHAASO and JUNO). The architecture and the measurements will be detailed in the paper.

  2. Radiation-hard ASICs for optical data transmission in the ATLAS pixel detector

    CERN Document Server

    Ziolkowski, M; Buchholz, P; Ciliox, A; Gan, K K; Holder, M; Johnson, M; Kagan, H; Kass, R; Nderitu, S; Rahimi, A; Rush, C J; Smith, S; Ter-Antonian, R; Zoeller, M M

    2004-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the CERN Large Hadron Collider (LHC). The first circuit is a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode to be used for 80 Mbit/s data transmission from the detector. The second circuit is a Bi-Phase Mark, decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode on the detector side. During ten years of operation at the LHC, the ATLAS optical link circuitry will be exposed to a maximum total fluence of 10/sup 15/ 1-MeV-equivalent neutrons per cm/sup 2/. We have successfully implemented both ASICs in a commercial 0.25 mu m CMOS technology using standard layout techniques to enhance the radiation tolerance. Both chips are four- channel devices compatible with common cathode PIN and VCSEL arrays. We present results from final prototype circuits and from irradiation studies of both circuits with 24 GeV protons up to a total dose of 57 Mrad. (3 refs).

  3. An extremely low power voltage reference with high PSRR for power-aware ASICs

    Science.gov (United States)

    Jihai, Duan; Dongyu, Deng; Weilin, Xu; Baolin, Wei

    2015-09-01

    An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascode current mirror is used to increase the power supply rejection ratio (PSRR) and reduce the line sensitivity of the circuit. The voltage reference is fabricated in SMIC 0.18-μm CMOS process. The measured results for the voltage reference demonstrate that the temperature coefficient of the voltage is 66 ppm/°C in a range from 25 to 100 °C. The line sensitivity is 0.9% in a supply voltage range of 1.8 to 3.3 V, and PSRR is -49 dB at 100 Hz. The power dissipation is 200 nW. The chip area is 0.01 mm2. The circuit can be used as an elementary circuit block for power-aware ASICs. Project supported by the National Natural Science Foundation of China (Nos. 61161003, 61264001, 61166004) and the Guangxi Natural Science Foundation (No. 2013GXNSFAA019333).

  4. TARGET: A Digitizing And Trigger ASIC For The Cherenkov Telescope Array

    CERN Document Server

    Funk, S; Katagiri, H; Kraus, M; Okumura, A; Schoorlemmer, H; Shigenaka, A; Tajima, H; Tibaldo, L; Varner, G; Zink, A; Zorn, J

    2016-01-01

    The future ground-based gamma-ray observatory Cherenkov Telescope Array (CTA) will feature multiple types of imaging atmospheric Cherenkov telescopes, each with thousands of pixels. To be affordable, camera concepts for these telescopes have to feature low cost per channel and at the same time meet the requirements for CTA in order to achieve the desired scientific goals. We present the concept of the TeV Array Readout Electronics with GSa/s sampling and Event Trigger (TARGET) Application Specific Circuit (ASIC), envisaged to be used in the cameras of various CTA telescopes, e.g. the Gamma-ray Cherenkov Telescope (GCT), a proposed 2-Mirror Small-Sized Telescope, and the Schwarzschild-Couder Telescope (SCT), a proposed Medium-Sized Telescope. In the latest version of this readout concept the sampling and trigger parts are split into dedicated ASICs, TARGET C and T5TEA, both providing 16 parallel input channels. TARGET C features a tunable sampling rate (usually 1 GSa/s), a 16k sample deep buffer for each chann...

  5. Low-Power, 8-Channel EEG Recorder and Seizure Detector ASIC for a Subdermal Implantable System.

    Science.gov (United States)

    Do Valle, Bruno G; Cash, Sydney S; Sodini, Charles G

    2016-12-01

    EEG remains the mainstay test for the diagnosis and treatment of patients with epilepsy. Unfortunately, ambulatory EEG systems are far from ideal for patients who have infrequent seizures. These systems only last up to 3 days and if a seizure is not captured during the recordings, a definite diagnosis of the patient's condition cannot be given. This work aims to address this need by proposing a subdermal implantable, eight-channel EEG recorder and seizure detector that has two modes of operation: diagnosis and seizure counting. In the diagnosis mode, EEG is continuously recorded until a number of seizures are recorded. In the seizure counting mode, the system uses a low-power algorithm to track the number of seizures a patient has, providing doctors with a reliable count to help determine medication efficacy or other clinical endpoint. An ASIC that implements the EEG recording and seizure detection algorithm was designed and fabricated in a 0.18 μm CMOS process. The ASIC includes eight EEG channels and is designed to minimize the system's power and size. The result is a power-efficient analog front end that requires 2.75 μW per channel in diagnosis mode and 0.84 μW per channel in seizure counting mode. Both modes have an input referred noise of approximately 1.1 μVrms.

  6. A low power biomedical signal processor ASIC based on hardware software codesign.

    Science.gov (United States)

    Nie, Z D; Wang, L; Chen, W G; Zhang, T; Zhang, Y T

    2009-01-01

    A low power biomedical digital signal processor ASIC based on hardware and software codesign methodology was presented in this paper. The codesign methodology was used to achieve higher system performance and design flexibility. The hardware implementation included a low power 32bit RISC CPU ARM7TDMI, a low power AHB-compatible bus, and a scalable digital co-processor that was optimized for low power Fast Fourier Transform (FFT) calculations. The co-processor could be scaled for 8-point, 16-point and 32-point FFTs, taking approximate 50, 100 and 150 clock circles, respectively. The complete design was intensively simulated using ARM DSM model and was emulated by ARM Versatile platform, before conducted to silicon. The multi-million-gate ASIC was fabricated using SMIC 0.18 microm mixed-signal CMOS 1P6M technology. The die area measures 5,000 microm x 2,350 microm. The power consumption was approximately 3.6 mW at 1.8 V power supply and 1 MHz clock rate. The power consumption for FFT calculations was less than 1.5 % comparing with the conventional embedded software-based solution.

  7. Charge-sensitive front-end electronics with operational amplifiers for CdZnTe detectors

    OpenAIRE

    Födisch, P.; Berthel, M.; Lange, B; Kirschke, T.; Enghardt, W.; Kaever, P.

    2016-01-01

    Cadmium zinc telluride (CdZnTe, CZT) radiation detectors are suitable for a variety of applications, due to their high spatial resolution and spectroscopic energy performance at room temperature. However, state-of-the-art detector systems require high-performance readout electronics. Though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, requirements of high dynamic range and high throughput are not available in any commercial circuit. Consequently, ...

  8. Upgrading FLIR NanoRaider with the next Generation of CdZnTe Detectors. Goal - Integrate VFG detectors into FLIR R200. Advanced Virtual Grid ASIC (AVG-ASIC).

    Energy Technology Data Exchange (ETDEWEB)

    Bolotnikov, Aleksey [Brookhaven National Lab. (BNL), Upton, NY (United States); Cui, Yonggang [Brookhaven National Lab. (BNL), Upton, NY (United States); Vernon, Emerson [Brookhaven National Lab. (BNL), Upton, NY (United States); De Geronimo, Gianluigi [Brookhaven National Lab. (BNL), Upton, NY (United States)

    2016-06-01

    This document presents motivations, goals and the current status of this project; development (fabrication, performance) of position-sensitive virtual Frisch-grid detectors proposed for nanoRaider, an instrument commonly used by nuclear inspectors; ASIC developments for CZT detectors; and the electronics development for the detector prototype..

  9. Evaluation of the PANDA silicon pixel front-end electronics and investigation of the anti ΛΛ final state

    Energy Technology Data Exchange (ETDEWEB)

    Esch, Simone

    2014-04-28

    high precision particle beams for several experiments. The AntiProton Annihilation at Darmstadt (PANDA) experiment is one of the large detectors at FAIR. PANDAs main physics objectives center around the properties of particles and excited particles made from quarks of the first and second quark family. It is a fixed target experiment within the High Energy Storage Ring (HESR), which delivers an intense, phase-space cooled antiproton beam in the momentum range of 1.5 to 15 GeV/c. With the high precision of the HESR, PANDA will be able to perform precise spectroscopic studies of hadronic states in the charm quark mass range. The luminosity will be up to 2.10{sup 32} cm{sup -2}s{sup -1}, thus enabling very rare processes to be studied. This high luminosity leads to a high particle flux and a high radiation environment which the sub-detectors must withstand. The most highly affected sub-detector of this high radiation environment is the Micro Vertex Detector (MVD), the innermost detector of PANDA. The main task of the MVD is the detection of the interaction points of events (vertexing). This vertex finding is crucial for the analysis of short living particles like e.g. D-mesons, particles consisting of a c-quark and a light antiquark. An essential part of the MVD detector is the readout of the semiconductor sensors. The ToPix (Torino Pixel) Application Specific Integrated Circuit (ASIC) is the front-end electronics for the MVD sensor, developed at the Istituto Nazionale di Fisica Nucleare (INFN) in Turin, Italy. It measures the spatial coordinate, the time and the deposited charge of incident charged particles. The most recent prototype of this ASIC is the ToPix 3, a version of reduced size and functionality. The Juelich Digital Readout System (JDRS) was adopted and extended to be able to readout this prototype, thus enabling specific test measurements of the prototype. In addition, the performance of PANDA for detecting long lived. particles was studied, and the

  10. AIDA: A 16-channel amplifier ASIC to read out the advanced implantation detector array for experiments in nuclear decay spectroscopy

    Energy Technology Data Exchange (ETDEWEB)

    Braga, D. [STFC Rutherford Appleton Laboratory, Didcot, OX11 0QX (United Kingdom); Coleman-Smith, P. J. [STFC Daresbury Laboratory, Warrington WA4 4AD (United Kingdom); Davinson, T. [Dept. of Physics and Astronomy, Univ. of Edinburgh, Edinburgh EH9 3JZ (United Kingdom); Lazarus, I. H. [STFC Daresbury Laboratory, Warrington WA4 4AD (United Kingdom); Page, R. D. [Dept. of Physics, Univ. of Liverpool, Oliver Lodge Laboratory, Liverpool L69 7ZE (United Kingdom); Thomas, S. [STFC Rutherford Appleton Laboratory, Didcot, OX11 0QX (United Kingdom)

    2011-07-01

    We have designed a read-out ASIC for nuclear decay spectroscopy as part of the AIDA project - the Advanced Implantation Detector Array. AIDA will be installed in experiments at the Facility for Antiproton and Ion Research in GSI, Darmstadt. The AIDA ASIC will measure the signals when unstable nuclei are implanted into the detector, followed by the much smaller signals when the nuclei subsequently decay. Implant energies can be as high as 20 GeV; decay products need to be measured down to 25 keV within just a few microseconds of the initial implants. The ASIC uses two amplifiers per detector channel, one covering the 20 GeV dynamic range, the other selectable over a 20 MeV or 1 GeV range. The amplifiers are linked together by bypass transistors which are normally switched off. The arrival of a large signal causes saturation of the low-energy amplifier and a fluctuation of the input voltage, which activates the link to the high-energy amplifier. The bypass transistors switch on and the input charge is integrated by the high-energy amplifier. The signal is shaped and stored by a peak-hold, then read out on a multiplexed output. Control logic resets the amplifiers and bypass circuit, allowing the low-energy amplifier to measure the subsequent decay signal. We present simulations and test results, demonstrating the AIDA ASIC operation over a wide range of input signals. (authors)

  11. A low-power CMOS ASIC for X-ray Silicon Drift Detectors low-noise pulse processing

    Science.gov (United States)

    Ahangarianabhari, M.; Bertuccio, G.; Macera, D.; Malcovati, P.; Grassi, M.; Rashevsky, A.; Rashevskaya, I.; Vacchi, A.; Zampa, G.; Zampa, N.; Fuschino, F.; Evangelista, Y.; Campana, R.; Labanti, C.; Feroci, M.

    2014-03-01

    We present an Application Specific Integrated Circuit (ASIC), named VEGA-1, designed and manufactured for low-power analog pulse processing of signals from Silicon Drift Detectors (SDDs). The VEGA-1 ASIC consists of an analog and a digital/mixed-signal section to achieve all the functionalities and specifications required for high-resolution X-ray spectroscopy in the energy range from 500 eV to 60 keV with low power consumption. The VEGA-1 ASIC has been designed and manufactured in 0.35-μm CMOS mixed-signal technology in single and 32-channel version with dimensions of 200 μm × 500 μm per channel. A minimum intrinsic ENC of 12 electrons r.m.s. at 3.6 μs shaping time and room temperature is measured for the ASIC without detector. The VEGA-1 has been tested with Q10-SDD designed in Trieste and fabricated at FBK, with an active area of 10 mm2 and a thickness of 450 μm. The aforementioned detector has an anode current of about 180 pA at +22°C. A minimum Equivalent Noise Charge (ENC) of 16 electrons r.m.s. at 3.0 μs shaping time and -30°C has been demonstrated with a total measured power consumption of 482 μW.

  12. Evidence for the Participation of Acid-Sensing Ion Channels (ASICs) in the Antinociceptive Effect of Curcumin in a Formalin-Induced Orofacial Inflammatory Model.

    Science.gov (United States)

    Wu, Yongfu; Qin, Dongyun; Yang, Huiling; Fu, Hui

    2017-05-01

    Curcumin, a major bioactive component of turmeric, has diverse therapeutic effects such as anti-inflammatory, antioxidant, anticancer, and antinociceptive activities. The acid-sensing ion channels (ASICs), which can be activated by acute drops in the extracellular pH, play an important role in nociception. However, very little is known about the interaction between ASICs and curcumin in nociception of inflammation. In our study, we investigated whether the antinociceptive effects of curcumin are mediated via ASICs using an orofacial nociceptive model and in vitro western blotting, immunofluorescence, whole-cell patch-clamp recordings in the trigeminal system. Intraperitoneally administered curcumin at a dose of 50 mg/kg can reduce hyperalgesia in both the phases of a formalin-induced orofacial nociceptive model. Curcumin reduced the amplitude of ASICs currents in a dose-dependent manner in trigeminal ganglion (TG) neurons, and curcumin also reduced the protein quantity but did not change the distribution of ASICs in TG. Thus, our results indicate that curcumin can reduce formalin-induced ASICs activation and thus inhibit ASICs-mediated inflammatory pain hypersensitivity.

  13. A low-phase-noise wide-band CMOS quadrature VCO for multi-standard RF front-ends

    DEFF Research Database (Denmark)

    Fard, Ali; Andreani, Pietro

    2005-01-01

    A low phase noise CMOS LC quadrature VCO (QVCO) with a wide frequency range of 3.6-5.6 GHz, designed in a standard 0.18 μm process for multi-standard front-ends, is presented. A significant advantage of the topology is the larger oscillation amplitude when compared to other conventional QVCO...... structures. The QVCO is compared to a double cross-coupled LC-tank differential oscillator, both in theory and experiments, for evaluation of its phase noise, providing a good insight into its performance. The measured data displays up to 2 dBc/Hz lower phase noise in the 1/f2 region for the QVCO, when...... consuming twice the current of the differential VCO, based on an identical LC-tank. Experimental results on the QVCO show a phase noise level of -127.5 dBc/Hz at 3 MHz offset from a 5.6 GHz carrier while dissipating 8 mA of current, resulting in a figure of merit of 181.3 dBc/Hz....

  14. Analysis of RF Front-End Performance of Reconfigurable Antennas with RF Switches in the Far Field

    Directory of Open Access Journals (Sweden)

    Insu Yeom

    2014-01-01

    Full Text Available The RF front-end performances in the far-field condition of reconfigurable antennas employing two commonly used RF switching devices (PIN diodes and RF-MEMS switches were compared. Two types of antennas (monopole and slot representing general direct/coupled feed types were used for the reconfigurable antennas to compare the excited RF power to the RF switches by the reconfigurable antenna types. For the switching operation of the antennas, a biasing circuit was designed and embedded in the same antenna board, which included a battery to emphasize the antenna’s adaptability to mobile devices. The measurement results of each reconfigurable antenna (radiation patterns and return losses are presented in this study. The receiving power of the reference antenna was measured by varying the transmitting power of the reconfigurable antennas in the far-field condition. The receiving power was analyzed using the “Friis transmission equation” and compared for two switching elements. Based on the results of these measurements and comparisons, we discuss what constitutes an appropriate switch device and antenna type for reconfigurable antennas of mobile devices in the far-field condition.

  15. High strength steels, stiffness of vehicle front-end structure, and risk of injury to rear seat occupants.

    Science.gov (United States)

    Sahraei, Elham; Digges, Kennerly; Marzougui, Dhafer; Roddis, Kim

    2014-05-01

    Previous research has shown that rear seat occupant protection has decreased over model years, and front-end stiffness is a possible factor causing this trend. In this research, the effects of a change in stiffness on protection of rear seat occupants in frontal crashes were investigated. The stiffness was adjusted by using higher strength steels (DP and TRIP), or thicker metal sheets. Finite element simulations were performed, using an LS Dyna vehicle model coupled with a MADYMO dummy. Simulation results showed that an increase in stiffness, to the extent it happened in recent model years, can increase the risk of AIS3+ head injuries from 4.8% in the original model (with a stiffness of 1,000 N/mm) to 24.2% in a modified model (with a stiffness of 2,356 N/mm). The simulations also showed an increased risk of chest injury from 9.1% in the original model to 11.8% in the modified model. Distribution of injuries from real world accident data confirms the findings of the simulations. Copyright © 2014 Elsevier Ltd. All rights reserved.

  16. High Resolution Photon Timing with MCP-PMTs: A Comparison of a Commercial Constant Fraction Discriminator (CFD) with the ASIC-based Waveform Digitizers TARGET and WaveCatcher

    Energy Technology Data Exchange (ETDEWEB)

    Breton, D.; /Orsay, LAL; Delagnes, E.; /DAPNIA, Saclay; Maalmi, J.; /Orsay, LAL; Nishimura, K.; Ruckman, L.L.; Varner, G.; /Hawaii U.; Va' vra, J.; /SLAC

    2011-07-14

    There is a considerable interest to develop new time-of-flight detectors using, for example, micro-channel-plate photodetectors (MCP-PMTs). The question we pose in this paper is if new waveform digitizer ASICs, such as the WaveCatcher and TARGET, operating with a sampling rate of 2-3 GSa/s can compete with 1GHz BW CFD/TDC/ADC electronics. We have performed a series of measurements with these waveform digitizers coupled to MCP-PMTs operating at low gain and with a signal equivalent to {approx}40 photoelectrons. The tests were done with a laser diode on detectors operating under the same condition used previously in SLAC and Fermilab beam tests. Our test results indicate that one can achieve similar resolution with both methods. Although the commercial CFD-based electronics does exist and performs very well, it is difficult to implement on a very large scale, and therefore the custom electronics is needed. In addition, the analog delay line requirement makes it very difficult to incorporate CFD discriminators in ASIC designs.

  17. A high speed serializer ASIC for ATLAS Liquid Argon calorimeter upgrade

    CERN Document Server

    Liu, T; The ATLAS collaboration

    2011-01-01

    The current front-end electronics of the ATLAS Liquid Argon calorimeters need to be upgraded to sustain the higher radiation levels and data rates expected at the upgraded LHC machine (HL-LHC), which will have 5 times more luminosity than the LHC in its ultimate configuration. This upgrade calls for an optical link system of 100 Gbps per front-end board (FEB). A high speed, low power, radiation tolerant serializer is the critical component in this system. In this paper, we present the design and test results of a single channel 16:1 serializer and the design of a double-channel 16:1 serializer. Both designs are based on a commercial 0.25 μm silicon-on-sapphire CMOS technology. The single channel serializer consists of a serializing unit, a PLL clock generator and a line driver implemented in current mode logic (CML). The serializing unit multiplexes 16 bit parallel LVDS data into 1-bit width serial CMOS data. The serializing unit is composed of a cascade of 2:1 multiplexing circuits based on static D-flip-fl...

  18. High-speed readout solution for single-photon counting ASICs

    Science.gov (United States)

    Kmon, P.; Szczygiel, R.; Maj, P.; Grybos, P.; Kleczek, R.

    2016-02-01

    We report on the analysis, simulations and measurements of both noise and high-count rate performance of a single photon counting integrated circuit called UFXC32k designed for hybrid pixel detectors for various applications in X-ray imaging. The dimensions of the UFCX32k designed in CMOS 130 nm technology are 9.63 mm × 20.15 mm. The integrated circuit core is a matrix of 128 × 256 squared readout pixels with a pitch of 75 μm. Each readout pixel contains a charge sensitive amplifier (CSA), a shaper, two discriminators and two 14-bit ripple counters. The UFXC32k was bump-bonded to a silicon pixel detector with the thickness of 320 μm and characterized with the X-ray radiation source. The CSA feedback based on the Krummenacher circuit determines both the count rate performance and the noise of the readout front-end electronics. For the default setting of the CSA feedback, the measured front-end electronics dead time is 232 ns (paralyzable model) and the equivalent noise charge (ENC) is equal to 123 el. rms. For the high count rate setting of the CSA feedback, the dead time is only 101 ns and the ENC is equal to 163 el. rms.

  19. ASIC design of a digital fuzzy system on chip for medical diagnostic applications.

    Science.gov (United States)

    Roy Chowdhury, Shubhajit; Roy, Aniruddha; Saha, Hiranmay

    2011-04-01

    The paper presents the ASIC design of a digital fuzzy logic circuit for medical diagnostic applications. The system on chip under consideration uses fuzzifier, memory and defuzzifier for fuzzifying the patient data, storing the membership function values and defuzzifying the membership function values to get the output decision. The proposed circuit uses triangular trapezoidal membership functions for fuzzification patients' data. For minimizing the transistor count, the proposed circuit uses 3T XOR gates and 8T adders for its design. The entire work has been carried out using TSMC 0.35 µm CMOS process. Post layout TSPICE simulation of the whole circuit indicates a delay of 31.27 ns and the average power dissipation of the system on chip is 123.49 mW which indicates a less delay and less power dissipation than the comparable embedded systems reported earlier.

  20. Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics

    Directory of Open Access Journals (Sweden)

    Christopher Bailey

    2014-01-01

    Full Text Available Complexity in processor microarchitecture and the related issues of power density, hot spots and wire delay, are seen to be a major concern for design migration into low nanometer technologies of the future. This paper evaluates the hardware cost of an alternative to register-file organization, the superscalar stack issue array (SSIA. We believe this is the first such reported study using discrete stack elements. Several possible implementations are evaluated, using a 90 nm standard cell library as a reference model, yielding delay data and FO4 metrics. The evaluation, including reference to ASIC layout, RC extraction, and timing simulation, suggests a 4-wide issue rate of at least four Giga-ops/sec at 90 nm and opportunities for twofold future improvement by using more advanced design approaches.

  1. An important step forward in continuous spectroscopic imaging of ionising radiations using ASICs

    CERN Document Server

    Fessler, P; Eberle, H; Raad-Iseli, C D; Hilt, B; Huss, D; Krummenacher, F; Lutz, Jean Robert; Prevot, G; Renouprez, Albert Jean; Sigward, M H; Schwaller, B; Voltolini, C

    1999-01-01

    Characterization results are given for an original ASIC allowing continuous acquisition of ionising radiation images in spectroscopic mode. Ionising radiation imaging in general and spectroscopic imaging in particular must primarily be guided by the attempt to decrease statistical noise, which requires detection systems designed to allow very high counting rates. Any source of dead time must therefore be avoided. Thus, the use of on-line corrections of the inevitable dispersion of characteristics between the large number of electronic channels of the detection system, shall be precluded. Without claiming to achieve ultimate noise levels, the work described is focused on how to prevent good individual acquisition channel noise performance from being totally destroyed by the dispersion between channels without introducing dead times. With this goal, we developed an automatic charge amplifier output voltage offset compensation system which operates regardless of the cause of the offset (detector or electronic). ...

  2. Analogue Sum ASIC for L1 Trigger Decision in Cherenkov Telescope Cameras

    CERN Document Server

    Barrio, Joan Abel; Boix, Joan; Delagnes, Eric; Delgado, Carlos; Coromina, Lluis Freixas; Gascon, David; Guilloux, Fabrice; Coto, Ruben Lopez; Martinez, Gustavo; Sanuy, Andreu; Tejedor, Luis Angel

    2014-01-01

    The Cherenkov Telescope Array (CTA) project aims to build the largest ground-based gamma-ray observatory based on an array of Imaging Atmospheric Cherenkov Telescopes (IACTs). The CTA will implement a multi-level trigger system to distinguish between gamma ray-like induced showers and background images induced by night sky background (NSB) light. The trigger system is based on coincident detections among pixels (level 0 trigger), clusters of pixels (level 1) or telescopes. In this article, the first version of the application specific integrated circuit (ASIC) for Level 1 trigger system is presented, capable of working with different Level 0 strategies and different trigger region sizes. In addition, it complies with all the requirements specified by the CTA project, specially the most critical ones as regards noise, bandwidth, dynamic range and power consumption. All these features make the presented system very suitable for use in the CTA cameras and improve the features of discrete components prototypes of...

  3. Performance and future development of the ASDBLR ASIC for the ATLAS TRT

    CERN Document Server

    Bevensee, B E; Newcomer, F M; Tyrrell, B; Van Berg, R; Williams, H H; Romaniouk, A

    1998-01-01

    The ATLAS TRT straw tracker will consist of more than 420 K straw tubes filled with a Xenon-based fast gas located in a magnetic field of 2 T. Some tubes will operate at rates in excess of 20 MHz. Stringent signal processing goals $9 have been determined using both simulation tools and measurement standards set by hand tuned discrete component prototypes. These include the ability to detect the earliest clusters from ionizing tracks as well as energetic $9 transition radiation photons without baseline shifts in a low noise and low power design. We report on measurements of two ASIC's fabricated in different processes that appear to be capable of achieving these goals. (2 refs).

  4. SCOTT: A time and amplitude digitizer ASIC for PMT signal processing

    Energy Technology Data Exchange (ETDEWEB)

    Ferry, S., E-mail: sophie.ferry@cea.fr [CEA/ Irfu/ SPP, Gif-sur-Yvette (France); Guilloux, F.; Anvar, S.; Chateau, F.; Delagnes, E.; Gautard, V.; Louis, F.; Monmarthe, E.; Le Provost, H. [CEA/ Irfu/ SEDI, Gif-sur-Yvette (France); Russo, S. [Dipartimento di Scienze Fisiche Università di Napoli, Napoli (Italy); Schuller, J-P.; Stolarczyk, Th.; Vallage, B. [CEA/ Irfu/ SPP, Gif-sur-Yvette (France); Zonca, E. [CEA/ Irfu/ SEDI, Gif-sur-Yvette (France)

    2013-10-11

    SCOTT is an ASIC designed for the readout electronics of photomultiplier tubes developed for KM3NeT, the cubic-kilometer scale neutrino telescope in Mediterranean Sea. To digitize the PMT signals, the multi-time-over-threshold technique is used with up to 16 adjustable thresholds. Digital outputs of discriminators feed a circular sampling memory and a “first in first out” digital memory. A specific study has shown that five specifically chosen thresholds are suited to reach the required timing accuracy. A dedicated method based on the duration of the signal over a given threshold allows an equivalent timing precision at any charge. To verify that the KM3NeT requirements are fulfilled, this method is applied on PMT signals digitized by SCOTT.

  5. The TDCPix ASIC: Tracking for the NA62 GigaTracker

    CERN Document Server

    Noy, Matthew; Bonacini, Sandro; Kaplon, Jan; Kluge, Alexander; Morel, Michel; Perktold, Lukas; Poltorak, Karolina

    2014-01-01

    The TDCPix is a hybrid pixel detector readout ASIC designed for the NA62 GigaTracker detec- tor. The asynchronously operating pixel array consists of 1800 pixels, each 300x300 m m 2 . The requirements are a single-hit timing resolution better than 200 ps RMS and a read-out efficiency of 99% or better in the presence of a beam rate between 800 MHz and 1 GHz . The discrimina- tor time walk effect is compensated by time-over-threshold discriminators connected to an array of 360 dual TDC channels. The TDCpix processes up to 210 Mhits = s and provides the hit data without the need of a trigger in a continuous data stream via four 3.2 Gb = s serialisers. Under test since January 2014, the TDCPix chip is fully functional and shows excellent performance.

  6. The eight-channel ASIC bipolar transresistance amplifier D0M AMPL-8.3

    CERN Document Server

    Alexeev, G D; Dvornikov, O V; Khokhlov, A I; Mikhailov, V A; Odnokloubov, I A; Tokmenin, V V

    2001-01-01

    The eight-channel ASIC low-noise bipolar transresistance amplifier D0M Ampl-8.3 has been designed on the basis of BJT-JFET technology for gaseous wire detectors used in high-energy physics experiments. The amplifier has differential gain 130 mV/mu A at 1 k OMEGA, input noise 35 and 60 nA r.m.s. at 0 and 60 pF input capacitance, respectively, leading/trailing edge 7 ns, input resistance approx 50 OMEGA, crosstalks -47 dB, dissipated power 160 triple bond 640 mW/chip for +-3 triple bond 5 V supply. The Ampl-8.3 has been accepted for upgrading the Forward Angle Muon System of the D0 experiment (Fermilab, Batavia, USA), the total number of channels is about 50,000.

  7. SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades

    Science.gov (United States)

    Adolfsson, J.; Ayala Pabon, A.; Bregant, M.; Britton, C.; Brulin, G.; Carvalho, D.; Chambert, V.; Chinellato, D.; Espagnon, B.; Hernandez Herrera, H. D.; Ljubicic, T.; Mahmood, S. M.; Mjörnmark, U.; Moraes, D.; Munhoz, M. G.; Noël, G.; Oskarsson, A.; Osterman, L.; Pilyar, A.; Read, K.; Ruette, A.; Russo, P.; Sanches, B. C. S.; Severo, L.; Silvermyr, D.; Suire, C.; Tambave, G. J.; Tun-Lanoë, K. M. M.; van Noije, W.; Velure, A.; Vereschagin, S.; Wanlin, E.; Weber, T. O.; Zaporozhets, S.

    2017-04-01

    This paper presents the test results of the second prototype of SAMPA, the ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chamber (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply and provides 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel consists of a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC; a Digital Signal Processor provides digital filtering and compression capability. In the second prototype run both full chip and single test blocks were fabricated, allowing block characterization and full system behaviour studies. Experimental results are here presented showing agreement with requirements for both the blocks and the full chip.

  8. Very Low-Power Consumption Analog Pulse Processing ASIC for Semiconductor Radiation Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Wessendorf, K.O.; Lund, J.C.; Brunett, B.A.; Laguna, G.R.; Clements, J.W.

    1999-08-23

    We describe a very-low power consumption circuit for processing the pulses from a semiconductor radiation detector. The circuit was designed for use with a cadmium zinc telluride (CZT) detector for unattended monitoring of stored nuclear materials. The device is intended to be battery powered and operate at low duty-cycles over a long period of time. This system will provide adequate performance for medium resolution gamma-ray pulse-height spectroscopy applications. The circuit incorporates the functions of a charge sensitive preamplifier, shaping amplifier, and peak sample and hold circuit. An application specific integrated circuit (ASIC) version of the design has been designed, built and tested. With the exception of the input field effect transistor (FET), the circuit is constructed using bipolar components. In this paper the design philosophy and measured performance characteristics of the circuit are described.

  9. CZT strip detectors for imaging and spectroscopy: Collimated beam and ASIC readout experiments

    Energy Technology Data Exchange (ETDEWEB)

    Kurczynski, P. [Univ. of Maryland, College Park, MD (United States); Krizmanic, J.F.; Parsons, A. [Goddard Space Flight Center, Greenbelt, MD (United States)

    1996-12-31

    We report the status of ongoing investigations into Cadmium Zinc Telluride (CZT) strip detectors for application in hard x-ray astronomy. We have instrumented a nine strip by nine strip region of a two sided strip detector made in our detector fabrication facility. In order to measure the position resolution of our detectors, we have implemented a collimated beam that concentrates radiation to a spot size less than the strip width of our detector. We have also performed charge collection studies as a function of incident photon energy and bias voltage with a single sided, 100{mu}m pitch CZT strip detector wire bonded to an SVX ASIC charge amplifier. The detectors exhibited excellent strip uniformity in terms of photon count rate and spectroscopic information.

  10. Analyse und Verhaltensmodellierung des HF-Frontends von passiven CMOS-Transpondern für UHF-RFID-Anwendungen

    OpenAIRE

    Seemann, Kay

    2007-01-01

    In dieser Arbeit werden neuartige Methoden für den systematischen Entwurf, die dynamische nichtlineare Verhaltensmodellierung und die On-Wafer-Charakterisierung des HF-Frontends von passiven CMOS-Transpondern für UHF-RFID-Anwendungen vorgestellt. Außerdem wird eine optimierte Frontend-Realisierung in einer 140-nm-CMOS-Technologie präsentiert und analysiert. In der gezeigten Realisierung werden nichtlineare Substrateffekte des Begrenzungs- und Rückstreuelements zur Leistungsgleichrichtung genu...

  11. Complementary bipolar application specific analog semicustom array, intended to implement front-end units

    CERN Document Server

    Atkin, E; Kondratenko, S; Maslennikov, V; Meshcheriakov, V; Mishin, Yu; Volkov, Yu

    2002-01-01

    The structure of an analog semicustom array, intended to implement front-end electronics ICs on its basis, is considered. The features of this array are: implementation with an inexpensive bipolar process despite containing an equal number of NPN and PNP structures with well matched characteristics, supply voltages from 1.5 V to 15 V, transistor current gains Bst~100 and unity gain frequencies Ft > 3 GHz at collector currents of (100...300) mu A, high- and low-ohmic resistors, MOS capacitors, minimum two variable plating levels available. Specific circuit diagrams and parameters of the front-end electronics ICs, created on the basis of the considered array, are presented. The results of their tests are given. (4 refs).

  12. Front-end module readout and control electronics for the PHENIX Multiplicity Vertex Detector

    Energy Technology Data Exchange (ETDEWEB)

    Ericson, M.N. [Oak Ridge National Lab., TN (United States); Allen, M.D. [Univ. of Tennessee, Knoxville, TN (United States); Boissevain, J. [Los Alamos National Lab., NM (United States)] [and others

    1997-11-01

    Front-end module (FEM) readout and control are implemented as modular, high-density, reprogrammable functions in the PHENIX Multiplicity Vertex Detector. FEM control is performed by the heap manager, an FPGA-based circuit in the FEM unit. Each FEM has 256 channels of front-end electronics, readout, and control, all located on an MCM. Data readout, formatting, and control are performed by the heap manager along with 4 interface units that reside outside the MVD detector cylinder. This paper discusses the application of a generic heap manager and the addition of 4 interface module types to meet the specific control and data readout needs of the MVD. Unit functioning, interfaces, timing, data format, and communication rates will be discussed in detail. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling, and FPGA implementation and programming will be presented.

  13. Towards a new perspective of managing ideas in front-end innovation as actor networks

    DEFF Research Database (Denmark)

    Vagn, Anna Rose; Clausen, Christian; Gish, Liv

    2013-01-01

    been identified as front-end innovation processes. The front-end innovation is distinguished from linear product development and characterised as more informal, unstructured, and unpredictable. This paper presents the preliminary results of a PhD project concerning idea management in front......For decades the innovation process in R&D organisations has been discussed. Product development processes is well-established in R&D organisations and improvements has been implemented through theories as Lean product development and agile methods. In recent decades, more diffuse processes have......-end innovation of R&D organisations. Through theoretical and empirical investigations of managing activities of idea processes an indicative analysis in the perspective of actor network theory is performed. The analysis show how managers and employees navigate in a complex environment of organisational...

  14. Mitigating RF Front-End Nonlinearity of Sensor Nodes to Enhance Spectrum Sensing

    Directory of Open Access Journals (Sweden)

    Lin Hu

    2016-11-01

    Full Text Available The cognitive radio wireless sensor network (CR-WSN has gained worldwide attention in recent years for its potential applications. Reliable spectrum sensing is the premise for opportunistic access to sensor nodes. However, as a result of the radio frequency (RF front-end nonlinearity of sensor nodes, distortion products can easily degrade the spectrum sensing performance by causing false alarms and degrading the detection probability. Given the limitations of the widely-used adaptive interference cancellation (AIC algorithm, this paper develops several details to avoid these limitations and form a new mitigation architecture to alleviate nonlinear distortions. To demonstrate the efficiency of the proposed algorithm, verification tests for both simulations and actual RF front-end measurements are presented and discussed. The obtained results show that distortions can be suppressed significantly, thus improving the reliability of spectrum sensing. Moreover, compared to AIC, the proposed algorithm clearly shows better performance, especially at the band edges of the interferer signal.

  15. Mitigating RF Front-End Nonlinearity of Sensor Nodes to Enhance Spectrum Sensing.

    Science.gov (United States)

    Hu, Lin; Ma, Hong; Zhang, Hua; Zhao, Wen

    2016-11-25

    The cognitive radio wireless sensor network (CR-WSN) has gained worldwide attention in recent years for its potential applications. Reliable spectrum sensing is the premise for opportunistic access to sensor nodes. However, as a result of the radio frequency (RF) front-end nonlinearity of sensor nodes, distortion products can easily degrade the spectrum sensing performance by causing false alarms and degrading the detection probability. Given the limitations of the widely-used adaptive interference cancellation (AIC) algorithm, this paper develops several details to avoid these limitations and form a new mitigation architecture to alleviate nonlinear distortions. To demonstrate the efficiency of the proposed algorithm, verification tests for both simulations and actual RF front-end measurements are presented and discussed. The obtained results show that distortions can be suppressed significantly, thus improving the reliability of spectrum sensing. Moreover, compared to AIC, the proposed algorithm clearly shows better performance, especially at the band edges of the interferer signal.

  16. A-3 dBm RF transmitter front-end for 802.11g application

    Institute of Scientific and Technical Information of China (English)

    Zhao Jinxin; Yan Jun; Shi Yin

    2013-01-01

    A 2.4 GHz,direct-conversion RF transmitter front-end with an up converter and PA driver is fabricated in a 0.13 μm CMOS process for the reliable transmission of 54 Mb/s OFDM signals.The front-end output power is-3 dBm while the corresponding EVM is-27 dB which is necessary for the 802.11 g standard of EVM at-25 dB.With the adopted gain control strategy the output power changes from-14.3 to-3.7 dBm with every step 0.8 dB (20%) which covers the gain variation due to working temperature and process.A power detector indicates the output power and delivers a voltage to the baseband to control the output power.

  17. Development and Demonstration of a Magnesium-Intensive Vehicle Front-End Substructure

    Energy Technology Data Exchange (ETDEWEB)

    Logan, Stephen D. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Forsmark, Joy H. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Osborne, Richard [United States Automotive Materials Partnership LLC, Southfield, MI (United States)

    2016-07-01

    This project is the final phase (designated Phase III) of an extensive, nine-year effort with the objectives of developing a knowledge base and enabling technologies for the design, fabrication and performance evaluation of magnesium-intensive automotive front-end substructures intended to partially or completely replace all-steel comparators, providing a weight savings approaching 50% of the baseline. Benefits of extensive vehicle weight reduction in terms of fuel economy increase, extended vehicle range, vehicle performance and commensurate reductions in greenhouse gas emissions are well known. An exemplary vehicle substructure considered by the project is illustrated in Figure 1, along with the exterior vehicle appearance. This unibody front-end “substructure” is one physical objective of the ultimate design and engineering aspects established at the outset of the larger collective effort.

  18. The DIALOG Chip in the Front-End Electronics of the LHCb Muon Detector

    CERN Document Server

    Cadeddu, S; Lai, A

    2004-01-01

    We present a custom integrated circuit, named DIALOG, which is a fundamental building block in the front-end architecture of the LHCb Muon detector. DIALOG is realized in IBM 0.25 um technology, using radiation hardening layout techniques. DIALOG integrates important tools for detector time alignment procedures and time alignment monitoring on the front- end system. In particular, it integrates 16 programmable delays, which can be regulated in steps of 1 ns. Many other features, necessary for the Muon trigger operation and for a safe front-end monitoring are integrated: DIALOG generates the information used by the trigger as a combination of its 16 inputs from the Amplifier-Shaper-Discriminator (ASD) chips, it generates the thresholds of the ASD, it monitors the rate of all its input channels. We describe the circuit architecture, its internal blocks and its main modes of operation.

  19. Problems in Assessment of Novel Biopotential Front-End with Dry Electrode: A Brief Review

    Directory of Open Access Journals (Sweden)

    Gaetano D. Gargiulo

    2014-02-01

    Full Text Available Developers of novel or improved front-end circuits for biopotential recordings using dry electrodes face the challenge of validating their design. Dry electrodes allow more user-friendly and pervasive patient-monitoring, but proof is required that new devices can perform biopotential recording with a quality at least comparable to existing medical devices. Aside from electrical safety requirement recommended by standards and concise circuit requirement, there is not yet a complete validation procedure able to demonstrate improved or even equivalent performance of the new devices. This short review discusses the validation procedures presented in recent, landmark literature and offers interesting issues and hints for a more complete assessment of novel biopotential front-end.

  20. A VLSI front-end circuit for microstrip silicon detectors for medical imaging applications

    CERN Document Server

    Beccherle, R; Guerra, A D; Folli, M; Marchesini, R; Bisogni, M G; Ceccopieri, A; Rosso, V; Stefanini, A; Tripiccione, R; Kipnis, I

    1999-01-01

    An analog CMOS-Integrated Circuit has been developed as Front-End for a double-sided microstrip silicon detector. The IC processes and discriminates signals in the 5-30 keV energy range. Main features are low noise and precise timing information. Low noise is achieved by optimizing the cascoded integrator with the 8 pF detector capacitance and by using an inherently low noise 1.2 mu m CMOS technology. Timing information is provided by a double discriminator architecture. The output of the circuit is a digital pulse. The leading edge is determined by a fixed threshold discriminator, while the trailing edge is provided by a zero crossing discriminator. In this paper we first describe the architecture of the Front-End chip. We then present the performance of the chip prototype in terms of noise, minimum discrimination threshold and time resolution.

  1. Front-end module readout and control electronics for the PHENIX Multiplicity Vertex Detector

    Energy Technology Data Exchange (ETDEWEB)

    Ericson, M.N. [Oak Ridge National Lab., TN (United States); Allen, M.D. [Univ. of Tennessee, Knoxville, TN (United States); Boissevain, J. [Los Alamos National Lab., NM (United States)] [and others

    1997-11-01

    Front-end module (FEM) readout and control are implemented as modular, high-density, reprogrammable functions in the PHENIX Multiplicity Vertex Detector. FEM control is performed by the heap manager, an FPGA-based circuit in the FEM unit. Each FEM has 256 channels of front-end electronics, readout, and control, all located on an MCM. Data readout, formatting, and control are performed by the heap manager along with 4 interface units that reside outside the MVD detector cylinder. This paper discusses the application of a generic heap manager and the addition of 4 interface module types to meet the specific control and data readout needs of the MVD. Unit functioning, interfaces, timing, data format, and communication rates will be discussed in detail. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling, and FPGA implementation and programming will be presented.

  2. The PRISMA hyperspectral imaging spectrometer: detectors and front-end electronics

    Science.gov (United States)

    Camerini, Massimo; Mancini, Mauro; Fossati, Enrico; Battazza, Fabrizio; Formaro, Roberto

    2013-10-01

    Two detectors, SWIR and VNIR, and relevant front-end electronics were developed in the frame of the PRISMA(Precursore Iperspettrale della Missione Applicativa) project, an hyperspectral instrument for the earth observation. The two detectors were of the MCT type and, in particular, the VNIR was realized by Sofradir by using the CZT(Cadmium Zinc Telluride substrate of the PV diodes) substrate removal to obtain the sensitivity in the visible spectral range. The use of the same ROIC permitted to design an unique front-end electronics. Two test campaigns were carried out: by Sofradir, only on the detectors, and by Selex ES, by using the PRISMA flight electronics. This latter tests demonstrated that was possible to obtain the same detector performance, with respect of those ones obtained by a ground setup, with a flight hardware in terms of noise, linearity and thermal stability.

  3. Microwave integrated circuit radiometer front-ends for the Push Broom Microwave Radiometer

    Science.gov (United States)

    Harrington, R. F.; Hearn, C. P.

    1982-01-01

    Microwave integrated circuit front-ends for the L-band, S-band and C-band stepped frequency null-balanced noise-injection Dicke-switched radiometer to be installed in the NASA Langley airborne prototype Push Broom Microwave Radiometer (PBMR) are described. These front-ends were developed for the fixed frequency of 1.413 GHz and the variable frequencies of 1.8-2.8 GHz and 3.8-5.8 GHz. Measurements of the noise temperature of these units were made at 55.8 C, and the results of these tests are given. While the overall performance was reasonable, improvements need to be made in circuit losses and noise temperatures, which in the case of the C-band were from 1000 to 1850 K instead of the 500 K specified. Further development of the prototypes is underway to improve performance and extend the frequency range.

  4. Onboard Calibration Circuit for the Front-end Electronics of DAMPE BGO Calorimeter

    CERN Document Server

    Zhang, De-Liang; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Gao, Shan-Shan; Shen, Zhong-Tao; Jiang, Di; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

    2016-01-01

    An onboard calibration circuit has been designed for the front-end electronics (FEE) of DAMPE BGO Calorimeter. It is mainly composed of a 12 bit DAC, an operation amplifier and an analog switch. Test results showed that a dynamic range of 0 ~ 30 pC with a precision of 5 fC was achieved, which meets the requirements of the front-end electronics. Furthermore, it is used to test the trigger function of the FEEs. The calibration circuit has been implemented and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite will be launched at the end of 2015 and the calibration circuit will perform onboard calibration in space.

  5. A High Input Impedance Low Noise Integrated Front-End Amplifier for Neural Monitoring.

    Science.gov (United States)

    Zhou, Zhijun; Warr, Paul A

    2016-12-01

    Within neural monitoring systems, the front-end amplifier forms the critical element for signal detection and pre-processing, which determines not only the fidelity of the biosignal, but also impacts power consumption and detector size. In this paper, a novel combined feedback loop-controlled approach is proposed to compensate for input leakage currents generated by low noise amplifiers when in integrated circuit form alongside signal leakage into the input bias network. This loop topology ensures the Front-End Amplifier (FEA) maintains a high input impedance across all manufacturing and operational variations. Measured results from a prototype manufactured on the AMS 0.35 [Formula: see text] CMOS technology is provided. This FEA consumes 3.1 [Formula: see text] in 0.042 [Formula: see text], achieves input impedance of 42 [Formula: see text], and 18.2 [Formula: see text] input-referred noise.

  6. FELIX: The New Approach for Interfacing to Front-end Electronics for the ATLAS Experiment

    CERN Document Server

    AUTHOR|(SzGeCERN)754725; The ATLAS collaboration; Anderson, John Thomas; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Guest, Daniel; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Zhang, Jinlong

    2016-01-01

    From the ATLAS Phase-I upgrade and onward, new or upgraded detectors and trigger systems will be interfaced to the data acquisition, detector control and timing (TTC) systems by the Front-End Link eXchange (FELIX). FELIX is the core of the new ATLAS Trigger/DAQ architecture. Functioning as a router between custom serial links and a commodity network, FELIX is implemented by server PCs with commodity network interfaces and PCIe cards with large FPGAs and many high speed serial fiber transceivers. By separating data transport from data manipulation, the latter can be done by software in commodity servers attached to the network. Replacing traditional point-to-point links between Front-end components and the DAQ system by a switched network, FELIX provides scaling, flexibility uniformity and upgradability and reduces the diversity of custom hardware solutions in favour of software.

  7. Robust Spectrum Sensing Demonstration Using a Low-Cost Front-End Receiver

    Directory of Open Access Journals (Sweden)

    Daniele Borio

    2015-01-01

    Full Text Available Spectrum Sensing (SS is an important function in Cognitive Radio (CR to detect primary users. The design of SS algorithms is one of the most challenging tasks in CR and requires innovative hardware and software solutions to enhance detection probability and minimize low false alarm probability. Although several SS algorithms have been developed in the specialized literature, limited work has been done to practically demonstrate the feasibility of this function on platforms with significant computational and hardware constraints. In this paper, SS is demonstrated using a low cost TV tuner as agile front-end for sensing a large portion of the Ultra-High Frequency (UHF spectrum. The problems encountered and the limitations imposed by the front-end are analysed along with the solutions adopted. Finally, the spectrum sensor developed is implemented on an Android device and SS implementation is demonstrated using a smartphone.

  8. Wireless miniature implantable devices and ASICs for monitoring, treatment, and study of glaucoma and cardiac disease

    Science.gov (United States)

    Chow, Eric Y.

    Glaucoma affects about 65 million people and is the second leading cause of blindness in the world. Although the condition is irreversible and incurable, early detection is vital to slowing and even stopping the progression of the disease. Our work focuses on the design, fabrication, and assembly of a continuous active glaucoma intraocular pressure (IOP) monitor that provides clinicians with the necessary data to more accurately diagnose and treat patients. Major benefits of an active monitoring device include the potential to develop a closed-loop treatment system and to operate independently for extended periods of time. The fully wireless operation uses gigahertzfrequency electromagnetic wave propagation, which allows for an orientation independent transfer of power and data over reasonable distances. Our system is comprised of a MEMS capacitive sensor, capacitive power storage array, ASIC, and monopole antenna assembled into a biocompatible liquid crystal polymer (LCP) package. We have performed in vivo trials on rabbits, both chronic and acute, to validate system functionality, fully wireless feasibility, and biocompatibility. Heart failure (HF) affects approximately 2% of the adult population in developed countries and 6-10% of people over the age of 65. Continuous monitoring of blood pressure, flow, and chemistry from a minimally invasive device can serve as a diagnostic and early-warning system for cardiac health. We developed a miniaturized system attached to the outer surface of an FDA approved stent, used as both the antenna for wireless telemetry/powering and structural support. The system comprises of a MEMS pressure sensor, ASIC for the sensor interface and wireless capabilities, LCP substrate, and FDA approved stent. In vivo studies on pigs validated functionality and fully wireless operation and demonstrate the feasibility of a stent-based wireless implant for continuous monitoring of blood pressure as well as other parameters including oxygen, flow

  9. Science Enabling ASICs and FEEs for the JUICE and JEO Missions

    Science.gov (United States)

    Paschalidis, Nicholas; Sittler, Ed; Cooper, John; Christian, Eric; Moore, Tom

    2011-01-01

    A family of science enabling radiation hard Application Specific Integrated Circuits (ASICs), Front End Electronics (FEEs) and Event Processing Systems, with flight heritage on many NASA missions, is presented. These technologies play an important role in the miniaturization of instruments -and spacecraft systems- at the same time increasing performance and reducing power. The technologies target time of flight, position sensing, and energy measurements as well as standard housekeeping and telemetry functions for particle and fields instruments, but find applications in other instrument categories too. More specifically the technologies include: the TOF chip, 1D and 2D Delay Lines with MCP detectors, for high precision fast and low power time of flight and position sensing; the Energy chip for multichannel SSD readout with time over threshold and standard voltage read out for TDC and ADC digitization; Fast multi channel read out chip with commandable thresholds; the TRIO chip for multiplexed ADC and housekeeping etc. It should be mentioned that the ASICs include basic trigger capabilities to enable random event processing in a heavy background of penetrators and UV foreground. Typical instruments include time of flight versus energy and look angle particle analyzers such as: plasma composition, energetic particle, neutral atom imaging as well as fast plasma and deltaE/E ion/electron telescopes. Flight missions include: Cassini/LEMMS, IMAGE/HENA, MESSENGER/EPPS/MLA/X-ray/MLA, STEREO, PLUTO-NH/PEPSSI/LORI, IBEX-Lo, JUNO/JEDI, RBSP/RBSPICE, MMS/HPCA/EPD, SO/SIS. Given the proven capability on heavy radiation missions such as JUNO, MMS and RBSB, as well diverse long duration missions such as MESSENGER, PLUTO and Cassini, it is expected that these technologies will play an important role in the particle and fields (at least) instruments on the upcoming JUICE and JEO missions.

  10. Design methodology: edgeless 3D ASICs with complex in-pixel processing for pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Fahim Farah, Fahim Farah [Northwestern U. (main); Deptuch, Grzegorz W. [Fermilab; Hoff, James R. [Fermilab; Mohseni, Hooman [Northwestern U. (main)

    2015-08-28

    The design methodology for the development of 3D integrated edgeless pixel detectors with in-pixel processing using Electronic Design Automation (EDA) tools is presented. A large area 3 tier 3D detector with one sensor layer and two ASIC layers containing one analog and one digital tier, is built for x-ray photon time of arrival measurement and imaging. A full custom analog pixel is 65μm x 65μm. It is connected to a sensor pixel of the same size on one side, and on the other side it has approximately 40 connections to the digital pixel. A 32 x 32 edgeless array without any peripheral functional blocks constitutes a sub-chip. The sub-chip is an indivisible unit, which is further arranged in a 6 x 6 array to create the entire 1.248cm x 1.248cm ASIC. Each chip has 720 bump-bond I/O connections, on the back of the digital tier to the ceramic PCB. All the analog tier power and biasing is conveyed through the digital tier from the PCB. The assembly has no peripheral functional blocks, and hence the active area extends to the edge of the detector. This was achieved by using a few flavors of almost identical analog pixels (minimal variation in layout) to allow for peripheral biasing blocks to be placed within pixels. The 1024 pixels within a digital sub-chip array have a variety of full custom, semi-custom and automated timing driven functional blocks placed together. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout. The methodology uses the Cadence design platform, however it is not limited to this tool.

  11. The next generation Front-End Controller for the Phase-I Upgrade of the CMS Hadron Calorimeters

    Science.gov (United States)

    Costanza, F.; Behrens, U.; Campbell, A.; Karakaya, T.; Martens, I.; Melzer-Pellmann, I. A.; Sahin, M. O.

    2017-03-01

    The next generation Front-End Controller (ngFEC) is the system responsible for slow and fast control within the Phase-I Upgrade of the CMS Hadron Calorimeters. It is based on the FC7, a μTCA compatible Advanced Mezzanine Card developed at CERN and built around the Xilinx Kintex®-7 FPGA. The ngFEC decodes the 40.0788 MHz LHC clock and the synchronization signals received from the backplane and distributes them to the front-end electronics through six GBT links. The latency of the fast control signals is fixed across power cycles. Even if the direct link to a front-end module is broken, a redundancy scheme ensures a successful communication using the link to the neighboring front-end module. Thanks to the ngFEC all front-end modules can be remotely programmed using the JTAG standard protocol. The CCM server software interfaces the ngFEC to the Detector Control System which constantly monitors voltages and temperatures on the front-end electronics. This document reviews the characteristics and the development status of the ngFEC.

  12. A Simplified and Accurate Front-End Electronics Chain for Timing RPCs

    CERN Document Server

    Blanco, A; Fonte, Paulo J R; Ferreira-Marques, R; Gobbi, A; Policarpo, Armando

    2000-01-01

    Recent advances in electronics and construction techniques have pushed the timing resolution of Resistive Plate Chambers below 50 ps sigma with detection efficienciesclose to 99% for MIPs. In this paper we describe a new front-end electronics chain for accurate time and charge measurement in these devices, having in view a possibleapplication in ALICE's T0 counter.(Abstract only available, full text to follow).

  13. The analog front-end section of the BaBar silicon vertex tracker readout IC

    Energy Technology Data Exchange (ETDEWEB)

    Manfredi, P.F.; Leona, A.; Mandelli, E.; Re, V.; Svelto, F. [Pavia Univ. (Italy). Dipartimento di Elettronica]|[INFN, Sezione di Pavia, Via Bassi 6, 27100 Pavia (Italy); Kipnis, I.; Luo, L.; Momayezi, M.; Nyman, M.; Pedrali-Noy, M.; Roe, N. [E.O. Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States)

    1998-02-01

    This paper describes the evolution in the analog section of the vertex detector readout chip for the BaBar experiment. In order to optimize its behaviour, an intermediate chip reproducing the analog part alone was developed and tested. It provided some useful design hints that provided the basis for the final conception of the analog front-end as it is now operational in the complete BaBar chip. (orig.). 6 refs.

  14. A front-end automation tool supporting design, verification and reuse of SOC

    Institute of Scientific and Technical Information of China (English)

    严晓浪; 余龙理; 王界兵

    2004-01-01

    This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.

  15. Compensation of impedance meters when using an external front-end amplifier

    OpenAIRE

    Torrents Dolz, Josep M.; Pallàs Areny, Ramon

    2002-01-01

    Four-terminal impedance meters based on pseudo-bridges yield unexpected uncertainties when using high-contact-impedance electrodes. Adding a front-end amplifier to the impedance meter and rearranging the connection of the meter terminals overcome the contact impedance problem. However, because the compensation provisions in the instrument are meant to compensate only impedance residuals of test fixtures, by either an open/short or an open/short/load correction procedure, the external fr...

  16. Design and characterization of integrated front-end transistors in a micro-strip detector technology

    CERN Document Server

    Simi, G; Batignani, G; Bettarini, S; Bondioli, M; Boscardin, M; Bosisio, L; Dalla Betta, Gian Franco; Dittongo, S; Forti, F; Giorgi, M; Gregori, P; Manghisoni, M; Morganti, M; Ratti, L; Re, V; Rizzo, G; Speziali, V; Zorzi, N

    2002-01-01

    We present the developments in a research program aimed at the realization of silicon micro-strip detectors with front-end electronics integrated in a high resistivity substrate to be used in high-energy physics, space and medical/industrial imaging applications. We report on the fabrication process developed at IRST (Trento, Italy), the characterization of the basic wafer parameters and measurements of the relevant working characteristics of the integrated transistors and related test structures.

  17. Simple Front-End Concept for the Complex Challenges of Multi-Band Communications

    DEFF Research Database (Denmark)

    Buskgaard, Emil Feldborg; Tatomirescu, Alexandru; Barrio, Samantha Caporal Del

    2015-01-01

    with additional tunable Rx and Tx filters the Rx/Tx isolation reaches 50 dB which is comparable with the isolation achieved with commercially available static duplex filters. Based on these antenna designs it is concluded that the proposed architecture is feasible for LTE phones and makes full coverage of all LTE...... bands realistic. Current 5G investigations show that the advantages of flexible front-ends will be even bigger as technology moves toward software defined radio. \\end{abstract}...

  18. Trends in the design of front-end systems for room temperature solid state detectors

    OpenAIRE

    Manfredi, Pier F.; Re, Valerio

    2003-01-01

    The paper discusses the present trends in the design of low-noise front-end systems for room temperature semiconductor detectors. The technological advancement provided by submicron CMOS and BiCMOS processes is examined from several points of view. The noise performances are a fundamental issue in most detector applications and suitable attention is devoted to them for the purpose of judging whether or not the present processes supersede the solutions featuring a field-effect transistor...

  19. An Inductively-Powered Wireless Neural Recording System with a Charge Sampling Analog Front-End

    OpenAIRE

    Lee, Seung Bae; Lee, Byunghun; Kiani, Mehdi; Mahmoudi, Babak; Gross, Robert; Ghovanloo, Maysam

    2015-01-01

    An inductively-powered wireless integrated neural recording system (WINeR-7) is presented for wireless and battery less neural recording from freely-behaving animal subjects inside a wirelessly-powered standard homecage. The WINeR-7 system employs a novel wide-swing dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which performs amplification, filtering, sampling, and analog-to-time conversion (ATC) with minimal interference and small amount of power. The output of the D...

  20. Intelligent front-end sample preparation tool using acoustic streaming.

    Energy Technology Data Exchange (ETDEWEB)

    Cooley, Erika J.; McClain, Jaime L.; Murton, Jaclyn K.; Edwards, Thayne L.; Achyuthan, Komandoor E.; Branch, Darren W.; Clem, Paul Gilbert; Anderson, John Mueller; James, Conrad D.; Smith, Gennifer; Kotulski, Joseph Daniel

    2009-09-01

    We have successfully developed a nucleic acid extraction system based on a microacoustic lysis array coupled to an integrated nucleic acid extraction system all on a single cartridge. The microacoustic lysing array is based on 36{sup o} Y cut lithium niobate, which couples bulk acoustic waves (BAW) into the microchannels. The microchannels were fabricated using Mylar laminates and fused silica to form acoustic-fluidic interface cartridges. The transducer array consists of four active elements directed for cell lysis and one optional BAW element for mixing on the cartridge. The lysis system was modeled using one dimensional (1D) transmission line and two dimensional (2D) FEM models. For input powers required to lyse cells, the flow rate dictated the temperature change across the lysing region. From the computational models, a flow rate of 10 {micro}L/min produced a temperature rise of 23.2 C and only 6.7 C when flowing at 60 {micro}L/min. The measured temperature changes were 5 C less than the model. The computational models also permitted optimization of the acoustic coupling to the microchannel region and revealed the potential impact of thermal effects if not controlled. Using E. coli, we achieved a lysing efficacy of 49.9 {+-} 29.92 % based on a cell viability assay with a 757.2 % increase in ATP release within 20 seconds of acoustic exposure. A bench-top lysing system required 15-20 minutes operating up to 58 Watts to achieve the same level of cell lysis. We demonstrate that active mixing on the cartridge was critical to maximize binding and release of nucleic acid to the magnetic beads. Using a sol-gel silica bead matrix filled microchannel the extraction efficacy was 40%. The cartridge based magnetic bead system had an extraction efficiency of 19.2%. For an electric field based method that used Nafion films, a nucleic acid extraction efficiency of 66.3 % was achieved at 6 volts DC. For the flow rates we tested (10-50 {micro}L/min), the nucleic acid extraction

  1. An 8 channel GaAs IC front-end discriminator for RPC detectors

    CERN Document Server

    Giannini, F; Orengo, G; Cardarelli, R

    1999-01-01

    Although not traditionally considered for particle detector readout, circuit solutions based upon GaAs IC technologies can offer considerable performance advantages in high speed detector signal processing: high f sub T devices, such as the GaAs MESFET, allow the realization of front-end tuned amplifiers and comparators with the same detector time resolution. Such a feature is well-suited for RPC particle detectors, characterized by short pulse duration and constant shaping responses. A new design procedure shows the suitability of high speed narrow band GaAs amplifiers as voltage-sensitive input stages of front-end discriminators to perform the required voltage amplification for the following comparator, ensuring, at the same time, SNR optimisation, high gain and low power consumption. As an application of the proposed approach, a full-custom analog chip has been designed and realized using 0.6 mu m GaAs MESFET technology from Triquint foundry. Eight channels of a front-end discriminator composed of a tuned ...

  2. Implementing method of optimum front-end conditioner based on Butterworth filter

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    The front-end conditioner is an essential part of digital systems of nuclear spectrometer, which functions in two ways: (1) prevents saturation of the subsequent ADC; (2) limits the bandwidth of frequency to realize anti-aliasing. To realize the above-mentioned functions, an optimum front-end conditioner for a resistive feedback charge-sensitive preamplifier is designed. In the conditioner, the pole-zero compensation (P/Z compensation) technique was used to effectively filter signals from the preamplifier. The Butterworth filter was improved after the pole-zero position was optimally set up to shape the wave of output, which tallied with the whole system. The front-end conditioner can resolve the aberration of waveform of nuclear signals in a regular Butterworth filter. Compared with the traditional triple-pole filtering circuitry, the circuitry of this conditioner is more compact and flexible.Moreover, its output waveform is more symmetrical and the signal-to-noise ratio (SNR) is higher. The improvement in the resolution of spectrometer is also significant.

  3. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date ofor the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcompone...

  4. Front-end electronics for accurate energy measurement of double beta decays

    Energy Technology Data Exchange (ETDEWEB)

    Gil, A., E-mail: alejandro.gil@ific.uv.es [Instituto de Fisica Corpuscular (CSIC-UV), 46071 Valencia (Spain); Diaz, J.; Gomez-Cadenas, J.J. [Instituto de Fisica Corpuscular (CSIC-UV), 46071 Valencia (Spain); Herrero, V. [Instituto de Instrumentacion para Imagen Molecular (I3M). Centro mixto CSIC, Universitat Politecnica de Valencia, CIEMAT, Valencia (Spain); Rodriguez, J.; Serra, L. [Instituto de Fisica Corpuscular (CSIC-UV), 46071 Valencia (Spain); Toledo, J.; Esteve, R.; Monzo, J.M. [Instituto de Instrumentacion para Imagen Molecular (I3M). Centro mixto CSIC, Universitat Politecnica de Valencia, CIEMAT, Valencia (Spain); Monrabal, F.; Yahlali, N. [Instituto de Fisica Corpuscular (CSIC-UV), 46071 Valencia (Spain)

    2012-12-11

    NEXT, a double beta decay experiment that will operate in Canfranc Underground Laboratory (Spain), aims at measuring the neutrinoless double-{beta} decay of the 136Xe isotope using a TPC filled with enriched Xenon gas at high pressure operated in electroluminescence mode. One technological challenge of the experiment is to achieve resolution better than 1% in the energy measurement using a plane of UV sensitive photomultipliers readout with appropriate custom-made front-end electronics. The front-end is designed to be sensitive to the single photo-electron to detect the weak primary scintillation light produced in the chamber, and also to be able to cope with the electroluminescence signal (several hundred times higher and with a duration of microseconds). For efficient primary scintillation detection and precise energy measurement of the electroluminescent signals the front-end electronics features low noise and adequate amplification. The signal shaping provided allows the digitization of the signals at a frequency as low as 40 MHz.

  5. A differential low-voltage high gain current-mode integrated RF receiver front-end

    Science.gov (United States)

    Chunhua, Wang; Minglin, Ma; Jingru, Sun; Sichun, Du; Xiaorong, Guo; Haizhen, He

    2011-02-01

    A differential low-voltage high gain current-mode integrated RF front end for an 802.11b WLAN is proposed. It contains a differential transconductance low noise amplifier (Gm-LNA) and a differential current-mode down converted mixer. The single terminal of the Gm-LNA contains just one MOS transistor, two capacitors and two inductors. The gate-source shunt capacitors, Cx1 and Cx2, can not only reduce the effects of gate-source Cgs on resonance frequency and input-matching impedance, but they also enable the gate inductance Lg1,2 to be selected at a very small value. The current-mode mixer is composed of four switched current mirrors. Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer and accordingly increase the gain of RF receiver front-end. The RF front-end operates under 1 V supply voltage. The receiver RFIC was fabricated using a chartered 0.18 μm CMOS process. The integrated RF receiver front-end has a measured power conversion gain of 17.48 dB and an input referred third-order intercept point (IIP3) of -7.02 dBm. The total noise figure is 4.5 dB and the power is only 14 mW by post-simulations.

  6. Design of a Portable Test Facility for the ATLAS Tile Calorimeter Front-End Electronics Verification

    CERN Document Server

    Kim, H Y; The ATLAS collaboration; Carrio, F; Moreno, P; Masike, T; Reed, R; Sandrock, C; Schettino, V; Shalyugin, A; Solans, C; Souza, J; Suter, R; Usai, G; Valero, A

    2013-01-01

    The stand-alone test-bench deployed in the past for the verification of the Tile Calorimeter (TileCal) front-end electronics is reaching the end of its life cycle. A new version of the test-bench has been designed and built with the aim of improving the portability and exploring new technologies for future versions of the TileCal read-out electronics. An FPGA based motherboard with an embedded hardware processor and a few dedicated daughter-boards are used to implement all the functionalities needed to interface with the front-end electronics (TTC, G-Link, CANbus) and to verify the functionalities using electronic signals and LED pulses. The new device is portable and performs well, allowing the validation in realistic conditions of the data transmission rate. We discuss the system implementation and all the tests required to gain full confidence in the operation of the front-end electronics of the TileCal in the ATLAS detector.

  7. Effects of vehicle impact velocity, vehicle front-end shapes on pedestrian injury risk.

    Science.gov (United States)

    Han, Yong; Yang, Jikuang; Mizuno, Koji; Matsui, Yasuhiro

    2012-09-01

    This study aimed at investigating the effects of vehicle impact velocity, vehicle front-end shape, and pedestrian size on injury risk to pedestrians in collisions with passenger vehicles with various frontal shapes. A series of parametric studies was carried out using 2 total human model for safety (THUMS) pedestrian models (177 and 165 cm) and 4 vehicle finite element (FE) models with different front-end shapes (medium-size sedan, minicar, one-box vehicle, and sport utility vehicle [SUV]). The effects of the impact velocity on pedestrian injury risk were analyzed at velocities of 20, 30, 40, and 50 km/h. The dynamic response of the pedestrian was investigated, and the injury risk to the head, chest, pelvis, and lower extremities was compared in terms of the injury parameters head injury criteria (HIC), chest deflection, and von Mises stress distribution of the rib cage, pelvis force, and bending moment diagram of the lower extremities. Vehicle impact velocity has the most significant influence on injury severity for adult pedestrians. All injury parameters can be reduced in severity by decreasing vehicle impact velocities. The head and lower extremities are at greater risk of injury in medium-size sedan and SUV collisions. The chest injury risk was particularly high in one-box vehicle impacts. The fracture risk of the pelvis was also high in one-box vehicle and SUV collisions. In minicar collisions, the injury risk was the smallest if the head did not make contact with the A-pillar. The vehicle impact velocity and vehicle front-end shape are 2 dominant factors that influence the pedestrian kinematics and injury severity. A significant reduction of all injuries can be achieved for all vehicle types when the vehicle impact velocity is less than 30 km/h. Vehicle designs consisting of a short front-end and a wide windshield area can protect pedestrians from fatalities. The results also could be valuable in the design of a pedestrian-friendly vehicle front-end shape

  8. Characterization of a front-end electronics for the monitoring and control of hadrontherapy beams

    Science.gov (United States)

    La Rosa, A.; Donetti, M.; Borri, M.; Rivero, F.; Attili, A.; Bourhaleb, F.; Cirio, R.; Garella, M. A.; Giordanengo, S.; Givehchi, N.; Mazza, G.; Marchetto, F.; Pardo, J.; Pecka, A.; Peroni, C.

    2008-02-01

    An integrated 64-channel device for the read-out of parallel plate pixel and strip ionization detectors has been developed by the INFN and University of Torino. The detectors will be used for the monitoring and control of hadrontherapy beams. The ASIC has been designed in CMOS 0.8 μm technology and it is based on a current-to-frequency converter followed by a synchronous counter. In this paper, we present a detailed characterization of the device done with 113 chips.

  9. Characterization of a front-end electronics for the monitoring and control of hadrontherapy beams

    Energy Technology Data Exchange (ETDEWEB)

    La Rosa, A. [INFN, Via P. Giuria 1, Turin 10125 (Italy)], E-mail: larosa@to.infn.it; Donetti, M. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Fondazione CNAO, Via Caminadella 16, Milan 20123 (Italy); Borri, M.; Rivero, F. [Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin (Italy); Attili, A. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Bourhaleb, F. [Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin (Italy); Cirio, R. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin (Italy); Garella, M.A.; Giordanengo, S. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Givehchi, N. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin (Italy); Mazza, G.; Marchetto, F.; Pardo, J. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Pecka, A.; Peroni, C. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin (Italy)

    2008-02-21

    An integrated 64-channel device for the read-out of parallel plate pixel and strip ionization detectors has been developed by the INFN and University of Torino. The detectors will be used for the monitoring and control of hadrontherapy beams. The ASIC has been designed in CMOS 0.8 {mu}m technology and it is based on a current-to-frequency converter followed by a synchronous counter. In this paper, we present a detailed characterization of the device done with 113 chips.

  10. A low-power 12.5 Gbps serial link transmitter ASIC for particle detectors in 65 nm CMOS

    Science.gov (United States)

    Feng, Y.; Chen, J.; You, Y.; Tang, Y.; Fan, Q.; Zuo, Z.; Pendyala, P.; Gong, D.; Liu, T.; Ye, J.

    2017-02-01

    This paper presents a 12.5 Gbps serial link transmitter application-specific integrated circuit (ASIC) designed in a 65-nm CMOS technology. The ASIC mainly includes an LC-VCO phase-locked-loop (PLL), a 16:1 serializer and a CML driver. Simulation results show that the PLL achieves a 7-to-14 GHz frequency tuning range and an RMS jitter of 0.4 pS. The serializer has a deterministic jitter of 9 pS and a programmable output swing from 200 mV to 1.0 V. The PLL and the serializer consumes 39.6 mW and 73 mW from a 1.2 V power supply, respectively.

  11. Multipurpose Test Structures and Process Characterization using 0.13 μm CMOS: The CHAMP ASIC

    Science.gov (United States)

    Cooney, Michael; Andrew, Matt; Nishimura, Kurtis; Ruckman, Larry; Varner, Gary; Grabas, Hervé; Oberla, Eric; Genat, Jean-Francois; Large Area Picosecond Photodetector Collaboration

    The University of Hawaii (UH) in collaboration with the University of Chicago (UC) submitted a test Application Specific Integrated Circuit (ASIC), the Chicago-Hawaii ASIC MultiPurpose (CHAMP), composed of a number of discrete test elements in a 0.13 μm CMOS process. This paper describes the structures submitted by UH and UC. Hawaii designs include high speed flip-flops, voltage controlled ring oscillators and delay lines, an Low Voltage Differential Signal (LVDS) receiver, a set of four 64-cell waveform samplers with shared input, an analog storage and comparator structure, as well as a 12-bit Digital to Analog Converter (DAC). The Chicago designs include voltage controlled delay lines, delay locked loops, voltage controlled ring oscillators, transmission lines, and resistors. Each of the structures will be described, with simulation and test results presented.

  12. A 32-channel, 025 mum CMOS ASIC for the readout of the silicon drift detectors of the ALICE experiment

    CERN Document Server

    Mazza, G; Anghinolfi, F; Martínez, M I; Rivetti, A; Rotondo, F

    2004-01-01

    In this paper we present a 32 channel ASIC prototype for the readout of the silicon drift detectors (SDDs) of the ALICE experiment. The ASIC integrates on the same substrate 32 transimpedance amplifiers, a 32 x 256 cell analogue memory and 16 successive approximation 10 bit A/D converters. The circuit amplifies and samples at 40 MS/s the input signal in a continuous way. When an external trigger signal validates the acquisition, the sampling is stopped and the data are digitized at lower speed (0.5 MS/s). The chip has been designed and fabricated in a commercial 0.25 mum CMOS technology. It has been extensively tested both on a bench and connected with a detector in several beam tests. In this paper both design issues and test results are presented. The radiation tolerance of the design has been increased by special layout techniques. Total dose irradiation tests are also presented.

  13. A Radiation Hard Multi-Channel Digitizer ASIC for Operation in the Harsh Jovian Environment

    Science.gov (United States)

    Aslam, Shahid; Aslam, S.; Akturk, A.; Quilligan, G.

    2011-01-01

    ultimately impact the surface of Europa after the mission is completed. The current JEO mission concept includes a range of instruments on the payload, to monitor dynamic phenomena (such as Io's volcanoes and Jupiters atmosphere), map the Jovian magnetosphere and its interactions with the Galilean satellites, and characterize water oceans beneath the ice shells of Europa and Ganymede. The payload includes a low mass (3.7 Kg) and low power (< 5 W) Thermal Instrument (TI) concept for measuring possible warm thermal anomalies on Europa s cold surface caused by recent (< 10,000 years) eruptive activity. Regions of anomalously high heat flow will be identified by thermal mapping using a nadir pointing, push-broom filter radiometer that provides far-IR imagery in two broad band spectral wavelength regions, 8-20 m and 20-100 m, for surface temperature measurements with better than a 2 K accuracy and a spatial resolution of 250 m/pixel obtained from a 100 Km orbit. The temperature accuracy permits a search for elevated temperatures when combined with albedo information. The spatial resolution is sufficient to resolve Europa's larger cracks and ridge axial valleys. In order to accomplish the thermal mapping, the TI uses sensitive thermopile arrays that are readout by a custom designed low-noise Multi-Channel Digitizer (MCD) ASIC that resides very close to the thermopile linear array outputs. Both the thermopile array and the MCD ASIC will need to show full functionality within the harsh Jovian radiation environment, operating at cryogenic temperatures, typically 150 K to 170 K. In the following, a radiation mitigation strategy together with a low risk Radiation-Hardened-By-Design (RHBD) methodology using commercial foundry processes is given for the design and manufacture of a MCD ASIC that will meet this challenge.

  14. Upgrade of the ATLAS Monitored Drift Tube Frontend Electronics for the HL-LHC

    CERN Document Server

    Zhu, Junjie; The ATLAS collaboration

    2017-01-01

    The ATLAS monitored drift tube (MDT) chambers are the main component of the precision tracking system in the ATLAS muon spectrometer. The MDT system is capable of measuring the sagitta of muon tracks to an accuracy of 60 μm, which corresponds to a momentum accuracy of about 10% at pT=1 TeV. To cope with large amount of data and high event rate expected from the High-Luminosity LHC (HL-LHC) upgrade, ATLAS plans to use the MDT detector at the first-trigger level to improve the muon transverse momentum resolution and reduce the trigger rate. The new MDT trigger and readout system will have an output event rate of 1 MHz and a latency of 6 us at the first-level trigger. The signals from MDT tubes are first processed by an Amplifier/Shaper/Discriminator (ASD) ASIC, and the binary differential signals output by the ASDs are then router to the Time-to-Digital Converter (TDC) ASIC, where the arrival times of leading and trailing edges are digitized in a time bin of 0.78 ns which leads to an RMS timing error of 0.25 n...

  15. Results of radiation test of the cathode front-end board for CMS endcap muon chambers

    Science.gov (United States)

    Breedon, R.; Bylsma, B.; Durkin, L. S.; Gilmore, J.; Gu, J.; Hauser, J.; Holbrook, B.; Kim, C. L.; Ling, T. Y.; von der Mey, M.; Murray, P.; Rush, C. J.; Santiard, J. C.; Tripathi, M.

    2001-10-01

    After a brief overview of the CMS EMU electronics system, results on radiation induced single event effects, total ionization dose and displacement effects will be reported. These results are obtained by irradiating the components on electronics boards with 63 MeV protons and 1 MeV neutrons. During the proton irradiation, the electronics board was fully under power, all components on the board were active and the data were read out in the same way as designed for CMS. No deterioration of analog performance for each of the three CMOS ASICs on the tested board was observed, up to a dose of 10 krad. Each of the tested FPGAs survived beyond the dose of 30 krad. No single event latch-up was detected for the CMOS ASICs up to a proton fluence of 2×10 12 cm-2. Single Event Upsets (SEU) in FPGAs were detected and their cross-sections measured. SEU mitigation with triple module redundancy and voting was implemented and tested.

  16. Results of radiation test of the cathode front-end board for CMS endcap muon chambers

    CERN Document Server

    Breedon, R; Durkin, L S; Gilmore, J; Gu, J; Hauser, J; Holbrook, B; Kim, C L; Ling, T; Mey, M; Murray, P; Rush, C J; Santiard, Jean-Claude; Tripathi, M

    2001-01-01

    After a brief overview of the CMS EMU electronics system, results on radiation induced single event effects, total ionization dose and displacement effects will be reported. These results are obtained by irradiating the components on electronics boards with 63 MeV protons and 1 MeV neutrons. During the proton irradiation, the electronics board was fully under power, all components on the board were active and the data were read out in the same way as designed for CMS. No deterioration of analog performance for each of the three CMOS ASICs on the tested board was observed, up to a dose of 10 krad. Each of the tested FPGAs survived beyond the dose of 30 krad. No single event latch-up was detected for the CMOS ASICs up to a proton fluence of 2x10 sup 1 sup 2 cm sup - sup 2. Single Event Upsets (SEU) in FPGAs were detected and their cross-sections measured. SEU mitigation with triple module redundancy and voting was implemented and tested.

  17. Test systems of the STS-XYTER2 ASIC: from wafer-level to in-system verification

    Science.gov (United States)

    Kasinski, Krzysztof; Zubrzycka, Weronika

    2016-09-01

    The STS/MUCH-XYTER2 ASIC is a full-size prototype chip for the Silicon Tracking System (STS) and Muon Chamber (MUCH) detectors in the new fixed-target experiment Compressed Baryonic Matter (CBM) at FAIR-center, Darmstadt, Germany. The STS assembly includes more than 14000 ASICs. The complicated, time-consuming, multi-step assembly process of the detector building blocks and tight quality assurance requirements impose several intermediate testing to be performed for verifying crucial assembly steps (e.g. custom microcable tab-bonding before wire-bonding to the PCB) and - if necessary - identifying channels or modules for rework. The chip supports the multi-level testing with different probing / contact methods (wafer probe-card, pogo-probes, in-system tests). A huge number of ASICs to be tested restricts the number and kind of tests possible to be performed within a reasonable time. The proposed architectures of test stand equipment and a brief summary of methodologies are presented in this paper.

  18. Inhibition of acid-induced apoptosis by targeting ASIC1a mRNA with short hairpin RNA

    Institute of Scientific and Technical Information of China (English)

    Xie-chuan WENG; Jian-quan ZHENG; Qing-e JIN; Xiao-yun MA

    2007-01-01

    Aim: To study the role of acid-sensing ion channel (ASIC) la in the cell death and apoptosis induced by extracellular acid in C6 glioma cells. Methods: The stable ASICla-silenced C6 cell line, built with RNA interference technology, were con-firmed by RT-PCR and Western blot analysis. The cell viability following acid exposure was analyzed with lactate dehydrogenase (LDH) and 3-(4,5-dimethylthiazol-2-yl)-2, 5-diphenyltetrazolium bromide (MTT) assay. The apoptotic cells dyed with Annexin-V and propidium iodide were measured with a flow cytometer, while the changes of cell cycle were also assayed. Results: The downregulation of ASIC 1 a proteins by stable transfection of short hairpin RNA decreased the cell death percentage and increased cell viability following acid exposure with LDH and the MTT assay. The rate of apoptosis was lower in the ASIC la-silenced cell line than that in the wild-type C6 cell line. The percentage of sub-G0 cells was lower in the ASICla-silenced C6 cells than that in the wild-type cells. Conclusion: Extracellular acid induced cell death and apoptosis viaASICla mechanisms in the C6 glioma cells.

  19. Cognitive Cellular Systems: A New Challenge on the RF Analog Frontend

    Science.gov (United States)

    Varga, Gabor; Schrey, Moritz; Subbiah, Iyappan; Ashok, Arun; Heinen, Stefan

    2016-07-01

    Cognitive Cellular Systems are seen today as one of the most promising ways of moving forward solving or at least easing the still worsening situation of congested spectrum caused by the growing number of users and the expectation of higher data transfer rates. As the intelligence of a Cognitive Radio system is located in the digital domain - the Cognitive Engine and associated layers - extensive research has been ongoing in that domain since Mitola published his idea in 1999. Since, a big progress has been made in the domain of architectures and algorithms making systems more efficient and highly flexible. The pace of this progress, however, is going to be impeded by hard requirements on the received and transmitted signal quality, introducing ultimate challenges on the performance of the RF analog frontend, such as in-band local oscillator harmonics, ultra low sensitivity and ultra high linearity. The RF frontend is thus likely to become the limiting technical factor in the true realization of a Cognitive Cellular System. Based on short recapitulations of the most crucial issues in RF analog design for Cognitive Systems, this article will point out why those mechanisms become responsible for the limitation of the overall performance particularly in a broadband Cognitive Cellular System. Furthermore, as part of a possible solution to ease the situation, system design of a high intermediate frequency (IF) to UHF frequency converter for cognitive radios is discussed and the performance of such a converter analyzed as a proof of concept. In addition to successfully tackling some of the challenges, such a high-IF converter enables white space operation for existing commercial devices by acting as frequency converter. From detailed measurements, the capabilities in both physical layer and application layer performance of a high-IF frontend developed out of off-the-shelf components is explained and is shown to provide negligible degradation to the commercial device

  20. Reading a GEM with a VLSI pixel ASIC used as a direct charge collecting anode

    CERN Document Server

    Bellazzini, R; Baldini, L; Bitti, F; Brez, A; Latronico, L; Massai, M M; Minuti, M; Omodei, N; Razzano, M; Sgro, C; Spandre, G; Costa, E; Soffitta, P

    2004-01-01

    In MicroPattern Gas Detectors (MPGD) when the pixel size is below 100 micron and the number of pixels is large (above 1000) it is virtually impossible to use the conventional PCB read-out approach to bring the signal charge from the individual pixel to the external electronics chain. For this reason a custom CMOS array of 2101 active pixels with 80 micron pitch, directly used as the charge collecting anode of a GEM amplifying structure, has been developed and built. Each charge collecting pad, hexagonally shaped, realized using the top metal layer of a deep submicron VLSI technology is individually connected to a full electronics chain (pre-amplifier, shaping-amplifier, sample and hold, multiplexer) which is built immediately below it by using the remaining five active layers. The GEM and the drift electrode window are assembled directly over the chip so the ASIC itself becomes the pixelized anode of a MicroPattern Gas Detector. With this approach, for the first time, gas detectors have reached the level of i...

  1. Automatic Testing of the Trigger Data Serializer ASIC for the Upgrade of the ATLAS Muon Spectrometer

    CERN Document Server

    Pinkham, Reid; Schwarz, Thomas

    The Trigger Data Serializer (TDS) is a custom designed Application Specific Integrated Circuit (ASIC) designed at the University of Michigan to be used on the ATLAS New Small Wheel (NSW) detector. The TDS is a central hub of the NSW trigger system. It prepares the trigger data for both pad and strip detectors, performs pad-strip matching, and serializes the matched strip data to other circuits on the rim of the NSW. In total, 6000 TDS chips will be produced. As part of the TDS’ initial production run, a test platform was developed to verify the functionality of each chip before being sent to users. The test platform consisted of multiple FPGA evaluation boards with custom designed mezzanine boards to hold the TDS chip during testing and control software running on a local computer. Of the initial run of 200 chips, 161 chips were tested with the automatic setup of which 158 passed. Detailed description of the TDS and automatic test fixture can be found in this thesis.

  2. An important step forward in continuous spectroscopic imaging of ionising radiations using ASICs

    Energy Technology Data Exchange (ETDEWEB)

    Fessler, P. [11 rue Rabelais, 92170 Vanves (France); Coffin, J. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Eberle, H. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Raad Iseli, C. de [Smart Silicon Systems SA, Ch. de la Graviere 6, CH-1007 Lausanne (Switzerland); Hilt, B. [Universite de Haute-Alsace, GRPHE, 61, rue Albert Camus, 68093 Mulhouse (France); Huss, D. [Universite de Haute-Alsace, GRPHE, 61, rue Albert Camus, 68093 Mulhouse (France); Krummenacher, F. [Smart Silicon Systems SA, Ch. de la Graviere 6, CH-1007 Lausanne (Switzerland); Lutz, J.R. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Prevot, G. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Renouprez, A. [Institut de Recherche sur la Catalyse, 2 Avenue Albert Einstein, 69626 Villeurbanne (France); Sigward, M.H. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Schwaller, B. [Universite de Haute-Alsace, GRPHE, 61, rue Albert Camus, 68093 Mulhouse (France); Voltolini, C. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France)

    1999-01-21

    Characterization results are given for an original ASIC allowing continuous acquisition of ionising radiation images in spectroscopic mode. Ionising radiation imaging in general and spectroscopic imaging in particular must primarily be guided by the attempt to decrease statistical noise, which requires detection systems designed to allow very high counting rates. Any source of dead time must therefore be avoided. Thus, the use of on-line corrections of the inevitable dispersion of characteristics between the large number of electronic channels of the detection system, shall be precluded. Without claiming to achieve ultimate noise levels, the work described is focused on how to prevent good individual acquisition channel noise performance from being totally destroyed by the dispersion between channels without introducing dead times. With this goal, we developed an automatic charge amplifier output voltage offset compensation system which operates regardless of the cause of the offset (detector or electronic). The main performances of the system are the following: the input equivalent noise charge is 190 e rms (input non connected, peaking time 500 ns), the highest gain is 255 mV/fC, the peaking time is adjustable between 200 ns and 2 {mu}s and the power consumption is 10 mW per channel. The agreement between experimental data and theoretical simulation results is excellent.

  3. CLARO-CMOS, a very low power ASIC for fast photon counting with pixellated photodetectors

    Science.gov (United States)

    Carniti, P.; De Matteis, M.; Giachero, A.; Gotti, C.; Maino, M.; Pessina, G.

    2012-11-01

    The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). The first prototype has four channels, each with a charge sensitive amplifier with settable gain and a discriminator with settable threshold, providing fast hit information for each channel independently. The design was realized in a long-established, stable and inexpensive 0.35 μm CMOS technology, and provides outstanding performance in terms of speed and power dissipation. The prototype consumes less than 1 mW per channel at low rate, and less than 2 mW at an event rate of 10 MHz per channel. The recovery time after each pulse is less than 25 ns for input signals within a factor of 10 above threshold. Input referred RMS noise is about 7.7 ke- (1.2 fC) with an input capacitance of 3.3 pF. With this value of input capacitance a timing resolution down to 10 ps RMS was measured for pulser signals of a few million electrons, corresponding to the single photon response for these detectors.

  4. CLARO-CMOS, a very low power ASIC for fast photon counting with pixellated photodetectors

    CERN Document Server

    Carniti, Paolo

    2012-01-01

    The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). The first prototype has four channels, each with a charge sensitive amplifier with settable gain and a discriminator with settable threshold, providing fast hit information for each channel independently. The design was realized in a long-established, stable and inexpensive 0.35 um CMOS technology, and provides outstanding performance in terms of speed and power dissipation. The prototype consumes less than 1 mW per channel at low rate, and less than 2 mW at an event rate of 10 MHz per channel. The recovery time after each pulse is less than 25 ns for input signals within a factor of 10 above threshold. Input referred RMS noise is about 7.7 ke^- (1.2 fC) with an input capacitance of 3.3 pF. Thanks to the low noise and high speed, a timing resolution down to 10 ps ...

  5. A pixel detector asic for dosimetry using time-over-threshold energy measurements

    CERN Document Server

    Wong, W S; Ballabriga, R; Bohnel, M; Campbell, M; Heijne, E; Llopart, X; Michel, T; Munster, I; Plackett, R; Sievers, P; Takoukam, P; Tlustos, L; Valerio, P

    2011-01-01

    In this work we present the design of a chip which provides the readout of a highly segmented diode array, in which signals induced by individual X-ray photons are processed discretely. There are several benefits to this approach, including the ability to achieve a high signal to noise ratio due to the inherently low sensor capacitance, and the suppression of background noise (e.g. dark current) using an analogue threshold. The segmentation also ensures a linear behaviour even at very high dose rates. A time over threshold (ToT) energy measurement technique provides an immediate digital value corresponding to the energy deposited onto the diode by each individual photon. Deadtime-free operation is achieved by reading out a subset of the detector segments at a time while the rest of the detector continues to process signals. This paper describes the application-specific integrated circuit (ASIC) chip which was designed to provide pre-processing of photo-induced signals in the detector and readout of the proces...

  6. Systematic study of new types of Hamamatsu MPPCs read out with the NINO ASIC

    CERN Document Server

    Doroud, K; Williams, M C S; Yamamoto, K; Zichichi, A; Zuyeuski, R

    2014-01-01

    Over the last decade there have been commercial TOF-PET scanners constructed using Photo-Multiplier Tubes (PMT) that have achieved View the MathML source~500ps FWHM Coincidence Time Resolution (CTR). A new device known as the Silicon PhotoMultiplier (SiPM) has the potential to overcome some of the limitations of the PMT. Therefore implementing a SiPM based TOF-PET scanner is of high interest. Recently Philips has introduced a TOF-PET scanner that uses digital Silicon PhotoMultipliers (d-SiPMs) which has a CTR of 350 ps. Here we will report on the timing performance of two Hamamatsu 3×3 mm2 analogue-SiPMs read out with the NINO ASIC: this is an ultra-fast amplifier/discriminator with a differential architecture. The differential architecture is very important since the single-ended readout uses the ground as the signal return; as the ground is also the reference level for the discriminators, the result is high crosstalk and degraded time resolution. However differential readout allows the scaling up from a si...

  7. Circuit design and simulation of a transmit beamforming ASIC for high-frequency ultrasonic imaging systems.

    Science.gov (United States)

    Athanasopoulos, Georgios I; Carey, Stephen J; Hatfield, John V

    2011-07-01

    This paper describes the design of a programmable transmit beamformer application-specific integrated circuit (ASIC) with 8 channels for ultrasound imaging systems. The system uses a 20-MHz reference clock. A digital delay-locked loop (DLL) was designed with 50 variable delay elements, each of which provides a clock with different phase from a single reference. Two phase detectors compare the phase difference of the reference clock with the feedback clock, adjusting the delay of the delay elements to bring the feedback clock signal in phase with the reference clock signal. Two independent control voltages for the delay elements ensure that the mark space ratio of the pulses remain at 50%. By combining a 10- bit asynchronous counter with the delays from the DLL, each channel can be programmed to give a maximum time delay of 51 μs with 1 ns resolution. It can also give bursts of up to 64 pulses. Finally, for a single pulse, it can adjust the pulse width between 9 ns and 100 ns by controlling the current flowing through a capacitor in a one-shot circuit, for use with 40-MHz and 5-MHz transducers, respectively.

  8. Development of high performance readout ASICs for silicon photomultipliers (SiPMs)

    Energy Technology Data Exchange (ETDEWEB)

    Shen, Wei

    2012-07-24

    Silicon Photomultipliers (SiPMs) are novel kind of solid state photon detectors with extremely high photon detection resolution. They are composed of hundreds or thousands of avalanche photon diode pixels connected in parallel. These avalanche photon diodes are operated in Geiger Mode. SiPMs have the same magnitude of multiplication gain compared to the conventional photomultipliers (PMTs). Moreover, they have a lot of advantages such as compactness, relatively low bias voltage and magnetic field immunity etc. Special readout electronics are required to preserve the high performance of the detector. KLauS and STiC are two CMOS ASIC chips designed in particular for SiPMs. KLauS is used for SiPM charge readout applications. Since SiPMs have a much larger detector capacitance compared to other solid state photon detectors such as PIN diodes and APDs, a few special techniques are used inside the chip to make sure a descent signal to noise ratio for pixel charge signal can be obtained. STiC is a chip dedicated to SiPM time-of-flight applications. High bandwidth and low jitter design schemes are mandatory for such applications where time jitter less than tens of picoseconds is required. Design schemes and error analysis as well as measurement results are presented in the thesis.

  9. Abstracts of the “GIORNATE DI CONIGLICOLTURA ASIC 2013”

    Directory of Open Access Journals (Sweden)

    GIORNATE DI CONIGLICOLTURA ASIC Forlì, Italy

    2013-06-01

    Full Text Available Onthe 10 and 11 of April, in Forlì (Italy it was held the 5th edition of the Italian Rabbit Days, product of the collaboration among ASIC (Italian Rabbit Scientific Association, ASPA (Animal Production Scientific Association and the Forlì Fair. The 1st day included a round table focused on “Which future for italian rabbit faming?”. During the 2nd day, there were presented 2 main lectures “Resources allocation in reproductive rabbit does: genetic strategies for a suitable performance”, by Pascual J.J., Savietto D., Cervera C., Baselga M. and “Controlling the rabbit digestive ecosystem to improve digestive health and efficacy”, by Combes S., Fortun-Lamothe L, Cauquil L., Gidenne T. which were previously presented at the last World Rabbit Congress. Moreover, 2 sessions of oral communications on Pathology and Zootechnics were held. Finally a Poster Session was through the 2 days. The meeting was attended by more than 80 participants, including researchers from France, Spain, and Hungary. A total of 2 main lectures, 10 oral communications and 6 posters were presented during the congress. Following are reported the abstracts of all contributions presented.

  10. Sensor-based whole-arm obstacle avoidance utilizing ASIC technology

    Science.gov (United States)

    Wintenberg, A. L.; Ericson, M. N.; Babcock, S. M.; Armstrong, G. A.; Britton, C. L., Jr.; Butler, P. L.; Hamel, W. R.; Newport, D. F.

    Operation of manipulator systems in poorly defined work environments often presents a significant hazard to both the robotic assembly and the environment. In applications relating to the Environmental Restoration and Waste Management (ER&WM) Program, many of the environments are considered hazardous, both, in the structure and composition of the environment. Use of a sensing system that provides information to the manipulator control unit regarding obstacles in close proximity will provide protection against collisions. A hierarchical design and implementation of a whole-arm obstacle avoidance system is presented. The system is based on capacitive sensors configured as bracelets for proximity sensing. Each bracelet contains a number of sensor nodes and a processor for sensor node control and readout, and communications with a higher level host, common to all bracelets. The host controls the entire sensing network and communicates proximity information to the manipulator controller. The overall architecture of this system is discussed with detail on the individual system modules. Details of an application specific integrated circuit (ASIC) designed to implement the sensor node electronics are presented. Justifications for the general measurement methods and associated implementation are discussed. Additionally, the current state of development including measured data is presented.

  11. A CMOS self-powered front-end architecture for subcutaneous event-detector devices

    CERN Document Server

    Colomer-Farrarons, Jordi

    2011-01-01

    A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices presents the conception and prototype realization of a Self-Powered architecture for subcutaneous detector devices. The architecture is designed to work as a true/false (event detector) or threshold level alarm of some substances, ions, etc. that are detected through a three-electrodes amperometric BioSensor approach. The device is conceived as a Low-Power subcutaneous implantable application powered by an inductive link, one emitter antenna at the external side of the skin and the receiver antenna under the ski

  12. THz semiconductor-based front-end receiver technology for space applications

    Science.gov (United States)

    Mehdi, Imran; Siegel, Peter

    2004-01-01

    Advances in the design and fabrication of very low capacitance planar Schottky diodes and millimeter-wave power amplifiers, more accurate device and circuit models for commercial 3-D electromagnetic simulators, and the availability of both MEMS and high precision metal machining, have enabled RF engineers to extend traditional waveguide-based sensor and source technologies well into the TI-Iz frequency regime. This short paper will highlight recent progress in realizing THz space-qualified receiver front-ends based on room temperature semiconductor devices.

  13. CMOS front-end for duobinary data over 50-m SI-POF links

    Science.gov (United States)

    Aguirre, J.; Guerrero, E.; Gimeno, C.; Sánchez-Azqueta, C.; Celma, S.

    2015-06-01

    This paper presents a front-end for short-reach high-speed optical communications that compensates the limited bandwidth of 1-mm 50-m step-index plastic optical fiber (SI-POF). For that purpose, it combines two techniques: continuous-time equalization and duobinary modulation. An addition of both enables the receiver to operate at 3.125 Gbps. The prototype contains a transimpedance amplifier, a continuous-time equalizer and a duobinary decoder. The prototype has been implemented in a cost-effective 0.18-μm CMOS process and is fed with 1.8 V.

  14. A wide dynamics neutron monitor with BF3 and logarithmic amplifier based front-end electronics

    OpenAIRE

    2010-01-01

    In this paper a wide dynamics neutron monitor based on BF3 neutron detector is described. The detector is used in current mode, and a front-end electronics based on a logarithmic amplifier is used in order to have a measurement capability ranging over many decades. The system has been calibrated at Polytechnic of Milan, CESNEF, with an AmBe neutron source, and has been tested in a pulsed field at the PUNITA facility at JRC, Ispra. The detector has achieved a dynamics ranging ov...

  15. Balancing research and organizational capacity building in front-end project design

    DEFF Research Database (Denmark)

    Hjortsø, Carsten Nico Portefée; Meilby, Henrik

    2013-01-01

    phase of RCB partnerships and examine how they influence the balance between performing collaborative research and developing general organizational capacity. Data collection was based on a survey (n = 25), and individual interviews and focus group discussions with 17 Danish project managers from...... is more complex. We identify 11 specific factors influencing front-end project management related to structure, process and relationship, and we theorize about how these factors influence the choice between research and more general capacity development activities. Copyright © 2013 John Wiley & Sons, Ltd...

  16. 65 nm CMOS analog front-end for pixel detectors at the HL-LHC

    Science.gov (United States)

    Gaioni, L.; De Canio, F.; Manghisoni, M.; Ratti, L.; Re, V.; Traversi, G.

    2016-02-01

    This work is concerned with the design and the experimental characterization of analog front-end electronics conceived for experiments with unprecedented particle rates and radiation levels at future high-energy physics colliders. A prototype chip integrating different test structures has been submitted in the framework of the CHIPIX65 project. These structures are standalone channels for the readout of hybrid pixels, featuring a charge sensitive preamplifier as the first stage of the readout chain, a high-speed comparator and a circuit for fine threshold tuning. The paper thoroughly discusses the results, mainly focused on the charge sensitive amplifier, coming from the characterization of the submitted test structures.

  17. Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting

    Directory of Open Access Journals (Sweden)

    Jianhong Xiao

    2007-01-01

    Full Text Available A low-cost low-power DTV tuner for current digital television application is described. In order to increase integration level and reduce power consumption for off-air DTV tuner application, an SAW-filterless tuner front-end architecture is adopted. As a part of the concept, key building blocks for this architecture are implemented on a main stream 0.35 μm CMOS technology. Experimental measurements for the prototype chip validate the system architecture; the prototype consumes 300 mw and achieves 45 dB of image rejection ratio within the entire 750 MHz frequency band.

  18. POLARIS: ESA's airborne ice sounding radar front-end design, performance assessment and first results

    DEFF Research Database (Denmark)

    Hernández, Carlos Cilla; Krozer, Viktor; Vidkjær, Jens;

    2009-01-01

    This paper addresses the design, implementation and experimental performance assessment of the RF front-end of an airborne P-band ice sounding radar. The ice sounder design comprises commercial-of-the-shelf modules and newly purpose-built components at a centre frequency of 435 MHz with 20......% relative bandwidth. The transmitter uses two amplifiers combined in parallel to generate more than >128 W peak power, with system >60% PAE and 47 dB in-band to out-of-band signal ratio. The four channel receiver features digitally controlled variable gain to achieve more than 100 dB dynamic range, 2.4 d...

  19. HTS filter and front-end subsystem for GSM1800 wireless base station

    Institute of Scientific and Technical Information of China (English)

    2002-01-01

    The first HTS front-end subsystem for wireless base station in China was developed. This demonstration system, which aims at the application in GSM1800 mobile communication base station, consists of a single RF path, i.e. one filter and one LNA, integrated with the pulse tube cooler. The subsystem works at a pass band of 1710-1785 MHz with a gain of 18 dB and at a temperature of 70 K. The accomplishment of such a demonstration subsystem can boost the development of HTS commercial subsystem.

  20. Investigation of characteristics and radiation hardness of the Beetle 1.0 front-end chip

    CERN Document Server

    Van Bakel, N; Jans, E; Klous, S; Verkooijen, H

    2001-01-01

    Noise characteristics of the Beetle 1.0 front-end chip have been investigated as a function of input capacitance. Values for the equivalent noise charge and ballastic deficit have been extracted. Amplification and pulse shape have been studied by varying the bias settings over a wide range. Results are compared with simulations that include realistic impedances at the input and output. The chip has been subjected to 10 Mrad of radiation. Subsequently, its behaviour is measured again and compared to that preceeding the irradiation. Observed radiation damage effects are discussed.