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Sample records for front-end electronics readout

  1. Front end readout electronics for the CMS hadron calorimeter

    CERN Document Server

    Shaw, Terri M

    2002-01-01

    The front-end electronics for the CMS Hadron Calorimeter provides digitized data at the beam interaction rate of 40 MHz. Analog signals provided by hybrid photodiodes (HPDs) or photomultiplier tubes (PMTs) are digitized and the data is sent off board through serialized fiber optic links running at 1600 Mbps. In order to maximize the input signal, the front-end electronics are housed on the detector in close proximity to the scintillating fibers or phototubes. To fit the electronics into available space, custom crates, backplanes and cooling methods have had to be developed. During the expected ten-year lifetime, the front-end readout electronics will exist in an environment where radiation levels approach 330 rads and the neutron fluence will be 1.3E11 n/cm sup 2. For this reason, the design approach relies heavily upon custom radiation tolerant ASICs. This paper will present the system architecture of the front-end readout crates and describe their results with early prototypes.

  2. Status on the development of front-end and readout electronics for ...

    Indian Academy of Sciences (India)

    Status on the development of front-end and readout electronics for large silicon trackers. J David M Dhellot J-F Genat F Kapusta H Lebbolo T-H Pham F Rossel A Savoy-Navarro E Deumens P Mallisse D Fougeron R Hermel Y Karyotakis S Vilalte. Tracking and Vertexing Volume 69 Issue 6 December 2007 pp 969-975 ...

  3. Front-end module readout and control electronics for the PHENIX Multiplicity Vertex Detector

    International Nuclear Information System (INIS)

    Ericson, M.N.; Allen, M.D.; Boissevain, J.

    1997-11-01

    Front-end module (FEM) readout and control are implemented as modular, high-density, reprogrammable functions in the PHENIX Multiplicity Vertex Detector. FEM control is performed by the heap manager, an FPGA-based circuit in the FEM unit. Each FEM has 256 channels of front-end electronics, readout, and control, all located on an MCM. Data readout, formatting, and control are performed by the heap manager along with 4 interface units that reside outside the MVD detector cylinder. This paper discusses the application of a generic heap manager and the addition of 4 interface module types to meet the specific control and data readout needs of the MVD. Unit functioning, interfaces, timing, data format, and communication rates will be discussed in detail. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling, and FPGA implementation and programming will be presented

  4. Front-end electronics and readout system for the ILD TPC

    CERN Document Server

    Hedberg, V; Lundberg, B; Mjörnmark, U; Oskarsson, A; Österman, L; De Lentdecker, G; Yang, Y; Zhang, F

    2015-01-01

    A high resolution TPC is the main option for a central tracking detector at the future International Linear Collider (ILC). It is planned that the MPGD (Micro Pattern Gas Detector) technology will be used for the readout. A Large Prototype TPC at DESY has been used to test the performance of MPGDs in an electron beam of energies up to 6 GeV. The first step in the technology development was to demonstrate that the MPGDs are able to achieve the necessary performance set by the goals of ILC. For this ’proof of principle’ phase, the ALTRO front-end electronics from the ALICE TPC was used, modified to adapt to MPGD readout. The proof of principle has been verified and at present further improvement of the MPGD technology is going on, using the same readout electronics. The next step is the ’feasibility phase’, which aims at producing front-end electronics comparable in size (few mm2) to the readout pads of the TPC. This development work is based on the succeeding SALTRO16 chip, which combines the analogue ...

  5. The front-end data conversion and readout electronics for the CMS ECAL upgrade

    CERN Document Server

    Mazza, Gianni

    2017-01-01

    The High Luminosity LHC (HL-LHC) will require a significant upgrade of the readout electronics for the CMS Electromagnetic Calorimeter (ECAL). The Very Front-End (VFE) output signal will be sampled at 160 MS/s (i.e. four times the current sampling rate) with 13 bit resolution. Therefore, a high-speed, high-resolution ADC is required. Moreover, each readout channel will produce 2.08 Gb/s, thus requiring fast data transmission circuitry. A new readout architecture, based on two 12 bit, 160 MS/s ADCs, lossless data compression algorithms and fast serial links have been developed for the ECAL upgrade. These functions will be integrated in a single ASIC which is currently under design in a commercial CMOS 65 nm technology using radiation damage mitigation techniques.

  6. Upgrade Design of TileCal Front-end Readout Electronics and Radiation Hardness Studies

    CERN Document Server

    Anderson, K; The ATLAS collaboration; Drake, G; Eriksson, D; Muschter, S; Oreglia, M; Pilcher, J; Price, L; Tang, F

    2011-01-01

    The ATLAS Tile Calorimeter (TileCal) is essential for measuring the energy and direction of hadrons and taus produced in LHC collisions. The TileCal consists of "tiles" of plastic scintillator dispersed in a fine-grained steel matrix . Optical fibers from the tiles are sent to ~10,000 photomultiplier tubes (PMT) and associated readout electronics. The TileCal front-end analog readout electronics process the signals from ~10,000 PMTs. Signals from each PMT are shaped with a 7-pole passive LC shaper and split it to two channels amplified by a pair of clamping amplifiers with a gain ratio of 32. Incorporated with two 40Msps 12-bit ADCs, the readout electronics provide a combined dynamic range of 17-bits. With this dynamic range, the readout system is capable of measuring the energy deposition in the calorimeter cells from ~220MeV to 1.3TeV with the least signal-to-noise ratio of greater than 20. The digitized data from each PMT are transmitted off-detector optically, where the data are further processed with ded...

  7. Optimizing read-out of the NECTAr front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Vorobiov, S., E-mail: vorobiov@lpta.in2p3.fr [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); DESY-Zeuthen, Platanenallee 6, 15738 Zeuthen (Germany); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Delagnes, E. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Falvard, A. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Gascon, D. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Glicenstein, J.-F. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Ribo, M.; Sanuy, A. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Tavernet, J.-P.; Toussenel, F.; Vincent, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France)

    2012-12-11

    We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

  8. A high performance Front End Electronics for drift chamber readout in MEG experiment upgrade

    International Nuclear Information System (INIS)

    Chiarello, G.; Chiri, C.; Corvaglia, A.; Grancagnolo, F.; Panareo, M.; Pepino, A.; Pinto, C.; Tassielli, G.

    2016-01-01

    Front End (FE) Electronics plays an essential role in Drift Chambers (DC) for time resolution and, therefore, spatial resolution. The use of cluster timing techniques, by measuring the timing of all the individual ionization clusters after the first one, may enable to reach resolutions even below 100 μm in the measurement of the impact parameter. To this purpose, a Front End Electronics with a wide bandwidth and low noise is mandatory in order to acquire and amplify the drift chamber signals.

  9. A high performance Front End Electronics for drift chamber readout in MEG experiment upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Chiarello, G. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Chiri, C.; Corvaglia, A.; Grancagnolo, F. [Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Panareo, M. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Pepino, A., E-mail: aurora.pepino@le.infn.it [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Pinto, C.; Tassielli, G. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy)

    2016-07-11

    Front End (FE) Electronics plays an essential role in Drift Chambers (DC) for time resolution and, therefore, spatial resolution. The use of cluster timing techniques, by measuring the timing of all the individual ionization clusters after the first one, may enable to reach resolutions even below 100 μm in the measurement of the impact parameter. To this purpose, a Front End Electronics with a wide bandwidth and low noise is mandatory in order to acquire and amplify the drift chamber signals.

  10. Development of front-end readout electronics for multi-channel silicon detector

    International Nuclear Information System (INIS)

    Zhang Fei; Fan Ruirui; Peng Wenxi; Dong Yifan; Gong Ke; Wang Huanyu

    2014-01-01

    A front-end readout circuit used in charge measurement for multi-channel silicon detector and its performance test results are introduced in this paper. A 64-channel charge sensitive ASIC chip (VA140) from IDEAS company is adopted in this method. With its features of low power consumption (< 0.29 mW/ch), low noise (RMSE < O.l fC), large dynamic range (-200 fC∼ +200 fC) and high integration (include 64 channels preamplifier-shaper), it can be used in future particle detecting experiments base on silicon detector. (authors)

  11. Cold front-end electronics and Ethernet-based DAQ systems for large LAr TPC readout

    CERN Document Server

    D.Autiero,; B.Carlus,; Y.Declais,; S.Gardien,; C.Girerd,; J.Marteau; H.Mathez

    2010-01-01

    Large LAr TPCs are among the most powerful detectors to address open problems in particle and astro-particle physics, such as CP violation in leptonic sector, neutrino properties and their astrophysical implications, proton decay search etc. The scale of such detectors implies severe constraints on their readout and DAQ system. We are carrying on a R&D in electronics on a complete readout chain including an ASIC located close to the collecting planes in the argon gas phase and a DAQ system based on smart Ethernet sensors implemented in a µTCA standard. The choice of the latter standard is motivated by the similarity in the constraints with those existing in Network Telecommunication Industry. We also developed a synchronization scheme developed from the IEEE1588 standard integrated by the use of the recovered clock from the Gigabit link

  12. FILTRES: a 128 channels VLSI mixed front-end readout electronic development for microstrip detectors

    International Nuclear Information System (INIS)

    Anstotz, F.; Hu, Y.; Michel, J.; Sohler, J.L.; Lachartre, D.

    1998-01-01

    We present a VLSI digital-analog readout electronic chain for silicon microstrip detectors. The characteristics of this circuit have been optimized for the high resolution tracker of the CERN CMS experiment. This chip consists of 128 channels at 50 μm pitch. Each channel is composed by a charge amplifier, a CR-RC shaper, an analog memory, an analog processor, an output FIFO read out serially by a multiplexer. This chip has been processed in the radiation hard technology DMILL. This paper describes the architecture of the circuit and presents test results of the 128 channel full chain chip. (orig.)

  13. Dedicated front-end and readout electronics developments for real time 3D directional detection of dark matter with MIMAC

    OpenAIRE

    Bourrion, O.; Bosson, G.; Grignon, C.; Richer, J. P.; Guillaudin, O.; Mayet, F.; Billard, J.; Santos, D.

    2011-01-01

    A complete dedicated electronics, from front-end to back-end, was developed to instrument a MIMAC prototype. A front end ASIC able to monitor 64 strips of pixels and to provide their individual "Time Over Threshold" information has been designed. An associated acquisition electronics and a real time track reconstruction software have been developed to monitor a 512 channel prototype. This auto-triggered electronic uses embedded processing to reduce the data transfer to its useful part only, i...

  14. Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    de La Taille, C

    2008-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  15. A circuit design for front-end read-out electronics of beam homogeneity measurement

    International Nuclear Information System (INIS)

    She Qianshun; Su Hong; Xu Zhiguo; Ma Xiaoli; Hu Zhengguo; Mao Ruishi; Xu Hushan

    2011-01-01

    It introduces a circuit design of beam homogeneity measurement for heavy ion beam in the monitoring needs, which convert multichannel weak current from 10 pA to 100 nA of the output of parallel plate avalanche counter (PPAC) for large area with sensitive two-dimensional position to voltage signal from -2 V to -20 mV by current-voltage-converter (IVC) circuit which composed of T-feedback resistor networks, combined with data acquisition and processing system realized the beam homogeneity measurement in heavy ion tumor therapy of the Institute of Modern Physics. Experiments have shown that the circuit with speed and high precision. This circuit can be used for read-out of the beam for the Multiwire Proportional Chamber, Faraday Cup and other weak current sources. (authors)

  16. SPD very front end electronics

    International Nuclear Information System (INIS)

    Luengo, S.; Gascon, D.; Comerma, A.; Garrido, L.; Riera, J.; Tortella, S.; Vilasis, X.

    2006-01-01

    The Scintillator Pad Detector (SPD) is part of the LHCb calorimetry system [D. Breton, The front-end electronics for LHCb calorimeters, Tenth International Conference on Calorimetry in Particle Physics, CALOR, Pasadena, 2002] that provides high-energy hadron, electron and photon candidates for the first level trigger. The SPD is designed to distinguish electrons from photons. It consists of a plastic scintillator layer, divided into about 6000 cells of different size to obtain better granularity near the beam [S. Amato, et al., LHCb technical design report, CERN/LHCC/2000-0036, 2000]. Charged particles will produce, and photons will not, ionization in the scintillator. This ionization generates a light pulse that is collected by a WaveLength Shifting (WLS) fiber that is coiled inside the scintillator cell. The light is transmitted through a clear fiber to the readout system that is placed at the periphery of the detector. Due to space constraints, and in order to reduce costs, these 6000 cells are divided in groups using a MAPMT [Z. Ajaltouni, et al., Nucl. Instr. and Meth. A 504 (2003) 9] of 64 channels that provides information to the VFE readout electronics. The SPD signal has rather large statistical fluctuations because of the low number (20-30) of photoelectrons per MIP. Therefore the signal is integrated over the whole bunch crossing length of 25 ns in order to have the maximum value. Since in average about 85% of the SPD signal is within 25 ns, 15% of a sample is subtracted from the following one using an operational amplifier. The SPD VFE readout system that will be presented consists of the following components. A specific ASIC [D. Gascon, et al., Discriminator ASIC for the VFE SPD of the LHCb Calorimeter, LHCB Technical Note, LHCB 2004-xx] integrates the signal, makes the signal-tail subtraction, and compares the level obtained to a programmable threshold (to distinguish electrons from photons). A FPGA programmes the ASIC threshold and the value for

  17. The LHCb Outer Tracker Front End Electronics

    CERN Document Server

    Berkien, A; Hommels, B; Knopf, J; Nedos, M; Pellegrino, A; Sluijk, T; Spelt, J; Stange, U; Trunk, U; Uwer, U; Wiedner, D; Zwart, A

    2008-01-01

    This note provides an overview of the front-end electronics used to readout the drift-times of the LHCb Outer Tracker straw tube chambers. The main functional components of the readout are the ASDBLR ASIC for amplification and signal digitization, the OTIS ASIC for the time measurement and for the L0 buffering, and the GOL ASIC to serialize the digital data for the optical data transmission. The L1 buffer board used to receive the data which is sent via the optical link is a common LHCb development and is not described here. This note supersedes an earlier document [1].

  18. SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    Bouchel, Michel; Dulucq, Frédéric; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

    2009-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  19. SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    Bouchel, Michel; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

    2007-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  20. The front-end electronics for LHCb calorimeters

    CERN Document Server

    Breton, D

    2002-01-01

    For the readout of the calorimeters of the LHCb experiment at CERN, specific front-end electronics have been designed. In particular, three different front-end analog chips were studied respectively for the ECAL/HCAL, preshower and scintillator pad detector. We will present the three front-end electronic chains, point out their specific requirements together with their common purpose, and describe the corresponding ASICs. (6 refs).

  1. The ALICE TPC front end electronics

    CERN Document Server

    Musa, L; Bialas, N; Bramm, R; Campagnolo, R; Engster, Claude; Formenti, F; Bonnes, U; Esteve-Bosch, R; Frankenfeld, Ulrich; Glässel, P; Gonzales, C; Gustafsson, Hans Åke; Jiménez, A; Junique, A; Lien, J; Lindenstruth, V; Mota, B; Braun-Munzinger, P; Oeschler, H; Österman, L; Renfordt, R E; Ruschmann, G; Röhrich, D; Schmidt, H R; Stachel, J; Soltveit, A K; Ullaland, K

    2004-01-01

    In this paper we present the front end electronics for the time projection chamber (TPC) of the ALICE experiment. The system, which consists of about 570000 channels, is based on two basic units: (a) an analogue ASIC (PASA) that incorporates the shaping-amplifier circuits for 16 channels; (b) a mixed-signal ASIC (ALTRO) that integrates 16 channels, each consisting of a 10-bit 25-MSPS ADC, the baseline subtraction, tail cancellation filter, zero suppression and multi-event buffer. The complete readout chain is contained in front end cards (FEC), with 128 channels each, connected to the detector by means of capton cables. A number of FECs (up to 25) are controlled by a readout control unit (RCU), which interfaces the FECs to the data acquisition (DAQ), the trigger, and the detector control system (DCS) . A function of the final electronics (1024 channels) has been characterized in a test that incorporates a prototype of the ALICE TPC as well as many other components of the final set-up. The tests show that the ...

  2. The CMS Tracker Readout Front End Driver

    CERN Document Server

    Foudas, C.; Ballard, D.; Church, I.; Corrin, E.; Coughlan, J.A.; Day, C.P.; Freeman, E.J.; Fulcher, J.; Gannon, W.J.F.; Hall, G.; Halsall, R.N.J.; Iles, G.; Jones, J.; Leaver, J.; Noy, M.; Pearson, M.; Raymond, M.; Reid, I.; Rogers, G.; Salisbury, J.; Taghavi, S.; Tomalin, I.R.; Zorba, O.

    2004-01-01

    The Front End Driver, FED, is a 9U 400mm VME64x card designed for reading out the Compact Muon Solenoid, CMS, silicon tracker signals transmitted by the APV25 analogue pipeline Application Specific Integrated Circuits. The FED receives the signals via 96 optical fibers at a total input rate of 3.4 GB/sec. The signals are digitized and processed by applying algorithms for pedestal and common mode noise subtraction. Algorithms that search for clusters of hits are used to further reduce the input rate. Only the cluster data along with trigger information of the event are transmitted to the CMS data acquisition system using the S-LINK64 protocol at a maximum rate of 400 MB/sec. All data processing algorithms on the FED are executed in large on-board Field Programmable Gate Arrays. Results on the design, performance, testing and quality control of the FED are presented and discussed.

  3. Front-end electronics development for the SSC

    International Nuclear Information System (INIS)

    Levi, M.

    1990-12-01

    This is a status report on electronics development undertaken by the Front-End Electronics Collaboration. The overall goal of the collaboration remains the development by 1992 of complete, architecturally compatible, front end electronic systems for calorimeter, wire drift chamber, and silicon strip readout. We report here a few highlights to give a brief overview of the work underway. Performance requirements and capabilities, selected architectures, circuit designs and test results are presented. 13 refs., 21 figs., 1 tab

  4. A digital Front-End and Readout MIcrosystem for calorimetry at LHC

    CERN Multimedia

    2002-01-01

    % RD-16 A Digital Front-End and Readout Microsystem for Calorimetry at LHC \\\\ \\\\Front-end signal processing for calorimetric detectors is essential in order to achieve adequate selectivity in the trigger function of an LHC experiment, with data identification and compaction before readout being required in the harsh, high rate environment of a high luminosity hadron machine. Other crucial considerations are the extremely wide dynamic range and bandwidth requirements, as well as the volume of data to be transferred to following stages of the trigger and readout system. These requirements are best met by an early digitalization of the detector information, followed by integrated digital signal processing and buffering functions covering the trigger latencies.\\\\ \\\\The FERMI (Front-End Readout MIcrosystem) is a digital implementation of the front-end and readout electronic chain for calorimeters. It is based on dynamic range compression, high speed A to D converters, a fully programmable pipeline/digital filter c...

  5. RPC performance vs. front-end electronics

    International Nuclear Information System (INIS)

    Cardarelli, R.; Aielli, G.; Camarri, P.; Di Ciaccio, A.; Di Stante, L.; Liberti, B.; Pastori, E.; Santonico, R.; Zerbini, A.

    2012-01-01

    Moving the amplification from the gas to the front-end electronics was a milestone in the development of Resistive Plate Chambers. Here we discuss the historical evolution of RPCs and we show the results obtained with newly developed front-end electronics with threshold in the fC range.

  6. Firmware Development and Integration for ALICE TPC and PHOS Front-end Electronics A Trigger Based Readout and Control System operating in a Radiation Environment

    CERN Document Server

    AUTHOR|(CDS)2068589; Rohrich, Dieter

    2008-01-01

    The readout electronics in PHOS and TPC - two of the major detectors of the ALICE experiment at the LHC - consist of a set of Front End Cards (FECs) that digitize, process and buffer the data from the detector sensors. The FECs are connected to a Readout Control Unit (RCU) via two sets of custom made PCB backplanes. For PHOS, 28 FECs are connected to one RCU, while for TPC the number is varying from 18 to 25 FECs depending on location. The RCU is in charge of the data readout, including reception and distribution of triggers and in moving the data from the FECs to the Data Acquisition System. In addition it does low level control tasks. The RCU consists of an RCU Motherboard that hosts a Detector Control System (DCS) board and a Source Interface Unit. The DCS board is an embedded computer running Linux that controls the readout electronics. All the mentioned devices are implemented in commercial grade SRAM based Field Programmable Gate Arrays (FPGAs). Even if these devices are not very radiation tolerant, the...

  7. Design of the new front-end electronics for the readout of the upgraded CMS electromagnetic calorimeter for the HL-LHC

    CERN Document Server

    Cometti, Simona

    2017-01-01

    The Compact Muon Solenoid detector was originally designed to operate for about ten years, for LHC instantaneous luminosities up to $1 \\cdot 10^{34}$ cm$^{-2}$ s$^{-1}$ and integrated luminosity of 500 fb$^{-1}$. The High Luminosity LHC will increase the instantaneous luminosity by about a factor of 5 from current levels and CMS will accumulate an integrated luminosity of 3000 fb$^{-1}$ by about 2035. With such high luminosity the electromagnetic calorimeter of CMS will have to cope with a challenging increase in the number of interactions per bunch crossing and in radiation levels. The front-end readout electronics will be completely redesigned, with the goals of providing precision timing, low noise and added flexibility in the trigger system. It will use a faster pre-amplifier, increase the sampling frequency from 40 MS/s to 160 MS/s and implement a trigger system that resides entirely off-detector.

  8. A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

    CERN Document Server

    Senkin, Sergey; The ATLAS collaboration

    2017-01-01

    We present a front-end readout system, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on 130 nm CMOS technology, FATALIC performs the full signal processing, including amplification, shaping and digitisation.

  9. The ATLAS tile calorimeter front end electronics

    CERN Document Server

    Martin, F

    2002-01-01

    After a short description of the ATLAS (1999) tile calorimeter front end electronics, the quality control procedure is presented. It is required both to ensure that the electronics match the ATLAS requirements and to face the complexity of any maintenance access in ATLAS. The test benches dedicated to tests of more than 10000 photomultipliers and all 256 entire electronics modules are described, and some results about the radiation hardness are given. (17 refs).

  10. Novel Front-end Electronics for Time Projection Chamber Detectors

    CERN Document Server

    García García, Eduardo José

    This work has been carried out in the European Organization for Nuclear Research (CERN) and it was supported by the European Union as part of the research and development towards the European detector the (EUDET) project, specifically for the International Linear Collider (ILC). In particle physics there are several different categories of particle detectors. The presented design is focused on a particular kind of tracking detector called Time Projection Chamber (TPC). The TPC provides a three dimensional image of electrically charged particles crossing a gaseous volume. The thesis includes a study of the requirements for future TPC detectors summarizing the parameters that the front-end readout electronics must fulfill. In addition, these requirements are compared with respect to the readouts used in existing TPC detectors. It is concluded that none of the existing front-end readout designs fulfill the stringent requirements. The main requirements for future TPC detectors are high integration, an increased n...

  11. A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

    CERN Document Server

    Senkin, Sergey; The ATLAS collaboration

    2017-01-01

    The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC) foreseen in 2024. We present here one of the front-end readout options, an ASIC called FATALIC, which is proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. Hereby we describe the full characterisation of FATALIC and also the signal reconstruction up to the observables of interest for physics: the energy and the arrival time of the particle. The Optimal Filtering signal reconstruction method is adapted to fully exploit the FATALIC three-range layout. Additionally, we present the performance in terms of resolution of the whole chain measured using the charge injection system designed for calibration. Finally, the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN are discussed.

  12. Performance of Front-End Readout System for PHENIX RICH

    International Nuclear Information System (INIS)

    Oyama, K.; Hamagaki, H.; Nishimura, S.; Shigaki, K.; Hayano, R.S.; Hibino, M.; Kametani, S.; Kikuchi, J.; Matsumoto, T.; Sakaguchi, T.; Ebisu, K.; Hara, H.; Tanaka, Y.; Ushiroda, T.; Moscone, C.G.; Wintenberg, A.L.; Young, G.R.

    1999-01-01

    A front-end electronics system has been developed for the Ring Imaging Cerenkov (RICH) detector of the PHENIX experiment at the Relativistic Heavy Ion Collider (RHIC), Brookhaven National Laboratory (BNL). A high speed custom back-plane with source synchronous bus architecture, a full custom analog ASIC, and board modules with FPGA's and CPLD's were developed for high performance real time data acquisition. The transfer rate of the back-lane has reached 640 MB/s with 128 bits data bus. Total transaction time is estimated to be less than 30 micros per event. The design specifications and test results of the system are presented in this paper

  13. Design of front end electronics and a full scale 4k pixel readout ASIC for the DSSC X-ray detector at the European XFEL

    International Nuclear Information System (INIS)

    Erdinger, Florian

    2016-01-01

    The goal of this thesis was to design a large scale readout ASIC for the 1-Mega pixel DEPFET Sensor with Signal Compression (DSSC) detector system which is being developed by an international collaboration for the European XFEL (EuXFEL). Requirements for the DSSC detector include single photon detection down to 0.5 keV combined with a large dynamic range of up to 10000 photons at frame rates of up to 4.5 MHz. The detector core concepts include full parallel readout, signal compression on the sensor or ASIC level, filtering, immediate digitization and local storage within the pixel. The DSSC is a hybrid pixel detector, each sensor pixel mates to a dedicated ASIC pixel, which includes the entire specified signal processing chain along with auxiliary circuits. One ASIC comprises 4096 pixels and a full periphery including biasing and digital control. This thesis presents the design of the ASIC, its components and integration are described in detail. Emphasis is put on the design of the analog front-end. The first full format ASIC (F1) has been fabricated within the scope of this thesis along with numerous test chips. Furthermore, the EuXFEL and the DSSC detector system are presented to create the context for the ASIC, which is the core topic of this thesis.

  14. Low noise monolithic CMOS front end electronics

    International Nuclear Information System (INIS)

    Lutz, G.; Bergmann, H.; Holl, P.; Manfredi, P.F.

    1987-01-01

    Design considerations for low noise charge measurement and their application in CMOS electronics are described. The amplifier driver combination whose noise performance has been measured in detail as well as the analog multiplexing silicon strip detector readout electronics are designed with low power consumption and can be operated in pulsed mode so as to reduce heat dissipation even further in many applications. (orig.)

  15. Installation and testing of the 112 boards for the front-end electronics.

    CERN Multimedia

    2006-01-01

    Installation and testing of the 112 boards for the front-end electronics. 28 boards are interconnected to a TPC type Readout Controller Unit trought the horizontal bus strips. The blue tubes are for the circulating cooling water.

  16. Front-end electronics and trigger systems - status and challenges

    International Nuclear Information System (INIS)

    Spieler, Helmuth G; Spieler, Helmuth G

    2007-01-01

    The past quarter century has brought about a revolution in front-end electronics for large-scale detector systems. Custom integrated circuits specifically tailored to the requirements of large detector systems have provided unprecedented performance and enabled systems that once were deemed impossible. The evolution of integrated circuit readouts in strip detectors is summarized, the present status described, and challenges posed by the sLHC and ILC are discussed. Performance requirements increase, but key considerations remain as in the past: power dissipation, material, and services. Smaller CMOS feature sizes will not provide the required electronic noise at lower power, but will improve digital power efficiency. Significant improvements appear to be practical in more efficient power distribution. Enhanced digital electronics have provided powerful trigger processors that greatly improve the trigger efficiency. In data readout systems they also improve data throughput, while reducing power requirements. Concurrently with new developments in high energy physics, detector systems for cosmology and astrophysics have made great strides. As an example, a large-scale readout for superconducting bolometer arrays is described

  17. Characterisation of the VMM3 Front-end read-out ASIC

    CERN Document Server

    Bartels, Lara Maria

    2018-01-01

    This research project was conducted in the RD51 collaboration at CERN, which is involved in the development of micropattern gaseous detector technologies and read-out systems. One example in the broad range of possible applications of such gaseous detectors is the NMX macromolecular diffractometer instrument planned for the European spallation source (ESS) which is currently under construction in Lund, Sweden. For the NMX instrument neutron detectors with high rate capabilities, high stability and excellent spatial resolution are required. A group working in the RD51 collaboration at CERN within the BrightnESS project aims to fulfil those requirements using gas electron multiplier (GEM) detectors with Gadolinium foils as neutron converters [PFE]. In order to match the high rate capability of the detectors, new front-end read-out systems need to be tested and implemented. This project aims to understand and test the capabilities of the VMM3 as the front-end read-out ASIC for GEM detectors.

  18. Noise Susceptibility Measurements of Front-End Electronics Systems

    CERN Document Server

    Allongue, B; Blanchot, G; Faccio, F; Fuentes, C; Michelis, S; Orlandi, S; Toro, A

    2008-01-01

    The conducted and radiated noise that is emitted by a power supply constrains the noise performance of the frontend electronics system that it powers. The characterization of the noise susceptibility of the front-end electronics allows setting proper requirements for the back-end power supply in order to achieve the expected system performance. A method to measure the common mode current susceptibility using current probes is presented. The compatibility between power supplies and various front-end systems is explored.

  19. A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

    Science.gov (United States)

    Senkin, Sergey

    2018-01-01

    The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC) foreseen in 2024. We present here one of the frontend readout options, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. We describe the full characterisation of FATALIC and also the Optimal Filtering signal reconstruction method adapted to fully exploit the FATALIC three-range layout. Additionally we present the resolution performance of the whole chain measured using the charge injection system designed for calibration. Finally we discuss the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN.

  20. A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

    Directory of Open Access Journals (Sweden)

    Senkin Sergey

    2018-01-01

    Full Text Available The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC foreseen in 2024. We present here one of the frontend readout options, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. We describe the full characterisation of FATALIC and also the Optimal Filtering signal reconstruction method adapted to fully exploit the FATALIC three-range layout. Additionally we present the resolution performance of the whole chain measured using the charge injection system designed for calibration. Finally we discuss the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN.

  1. Front-end electronics for the ALICE calorimeters

    Science.gov (United States)

    Wang, Yaping; Ma, Ke; Muller, Hans; Cai, Xu; Zhou, Daicui; Yin, Zhongbao; Awes, Terry C.; Wang, Dong

    2010-05-01

    The ALICE calorimeters PHOS and EMCal are based on Avalanche Photo-Diode (APD) photosensors with Charge Sensitive Preamplifiers (CSP) for readout of the scintillating elements. The amplified signals are read out via 32-channel shaper/digitizer front-end electronics (FEE) with 14-bit effective dynamic range. The electronics is based on second order shapers with dual gain for each channel, getting digitized by ALTRO chips. Each APD channel is equipped with an individual 10-bit APD gain adjustment and 2×2 channel clusters generate a 100 ns shaped analog sums output (Fast OR) for the associated Trigger Region Units (TRU). The Fast OR signals are generated by first order shapers with a dynamic range of 12-bit given by the ADC in the TRU cards. Board controller firmware in the FPGA provides local monitoring and configuration of all parameters via the ALICE DCS system. The signal to noise ratio for MIP at 215 MeV is ˜7 per channel with a noise level of 30 MeV at room temperature for a dynamic range of 80 GeV for PHOS, and the fast-OR RMS noise level is about 75 MeV for a dynamic range of 250 GeV for EMCal.

  2. Front-end Electronics for the ALICE Calorimeters

    Energy Technology Data Exchange (ETDEWEB)

    Aamodt, K. [University of Oslo, Norway; Awes, Terry C [ORNL; Enokizono, Akitomo [Oak Ridge National Laboratory (ORNL); Silvermyr, David O [ORNL; Zhang, Chun [University of Tennessee, Knoxville (UTK) & Oak Ridge National Laboratory (ORNL); Young, Glenn R [ORNL; The, ALICE [Collaboration affiliations

    2010-05-01

    The ALICE calorimeters PHOS and EMCal are based on Avalanche Photo-Diode (APD) photosensors with Charge Sensitive Preamplifiers (CSP) for readout of the scintillating elements. The amplified signals are read out via 32-channel shaper/digitizer front-end electronics (FEE) with 14-bit effective dynamic range. The electronics is based on second order shapers with dual gain for each channel, getting digitized by ALTRO chips. Each APD channel is equipped with an individual 10-bit APD gain adjustment and 2 x 2 channel clusters generate a 100 ns shaped analog sums output (Fast OR) for the associated Trigger Region Units (TRU). The Fast OR signals are generated by first order shapers with a dynamic range of 12-bit given by the ADC in the TRU cards. Board controller firmware in the FPGA provides local monitoring and configuration of all parameters via the ALICE DCS system. The signal to noise ratio for MIP at 215 MeV is {approx}7 per channel with a noise level of 30 MeV at room temperature for a dynamic range of 80 GeV for PHOS, and the fast-OR RMS noise level is about 75 MeV for a dynamic range of 250 GeV for EMCal.

  3. Front-end electronics for the ALICE calorimeters

    CERN Document Server

    Wang, Ya-Ping; Muller, Hans; Cai, Xu; Zhou, Daicui; Yin, Zhong-Bao; Awes, Terry C.; Wang, Dong

    2010-01-01

    The ALICE calorimeters PHOS and EMCal are based on Avalanche Photo-Diode (APD) photosensors with Charge Sensitive Preamplifiers (CSP) for readout of the scintillating elements. The amplified signals are read out via 32-channel shaper/digitizer front-end electronics (FEE) with 14-bit effective dynamic range. The electronics is based on second order shapers with dual gain for each channel, getting digitized by ALTRO chips. Each APD channel is equipped with an individual 10-bit APD gain adjustment and 2×2 channel clusters generate a 100 ns shaped analog sums output (Fast OR) for the associated Trigger Region Units (TRU). The Fast OR signals are generated by first order shapers with a dynamic range of 12-bit given by the ADC in the TRU cards. Board controller firmware in the FPGA provides local monitoring and configuration of all parameters via the ALICE DCS system. The signal to noise ratio for MIP at 215 MeV is not, vert, similar7 per channel with a noise level of 30 MeV at room temperature for a dynamic range...

  4. Front-end electronics for the ALICE calorimeters

    Energy Technology Data Exchange (ETDEWEB)

    Wang Yaping, E-mail: wangyaping@mail.ccnu.edu.c [Key Laboratory of Quark and Lepton Physics (Huazhong Normal University, CCNU), Ministry of Education, Wuhan 43079 (China); Institute of Particle Physics, Huazhong Normal University, Wuhan 430079 (China); Ma Ke [Institute of Particle Physics, Huazhong Normal University, Wuhan 430079 (China); Huazhong University of Science and Technology, Wuhan 430079 (China); Muller, Hans [CERN, PH-AID-DT, 1211 Geneva 23 (Switzerland); Cai Xu; Zhou Daicui; Yin Zhongbao [Key Laboratory of Quark and Lepton Physics (Huazhong Normal University, CCNU), Ministry of Education, Wuhan 43079 (China); Institute of Particle Physics, Huazhong Normal University, Wuhan 430079 (China); Awes, Terry C. [Oak Ridge National Laboratory, Oak Ridge, TN 37831 (United States); Wang Dong [Key Laboratory of Quark and Lepton Physics (Huazhong Normal University, CCNU), Ministry of Education, Wuhan 43079 (China); Institute of Particle Physics, Huazhong Normal University, Wuhan 430079 (China)

    2010-05-21

    The ALICE calorimeters PHOS and EMCal are based on Avalanche Photo-Diode (APD) photosensors with Charge Sensitive Preamplifiers (CSP) for readout of the scintillating elements. The amplified signals are read out via 32-channel shaper/digitizer front-end electronics (FEE) with 14-bit effective dynamic range. The electronics is based on second order shapers with dual gain for each channel, getting digitized by ALTRO chips. Each APD channel is equipped with an individual 10-bit APD gain adjustment and 2x2 channel clusters generate a 100 ns shaped analog sums output (Fast OR) for the associated Trigger Region Units (TRU). The Fast OR signals are generated by first order shapers with a dynamic range of 12-bit given by the ADC in the TRU cards. Board controller firmware in the FPGA provides local monitoring and configuration of all parameters via the ALICE DCS system. The signal to noise ratio for MIP at 215 MeV is {approx}7 per channel with a noise level of 30 MeV at room temperature for a dynamic range of 80 GeV for PHOS, and the fast-OR RMS noise level is about 75 MeV for a dynamic range of 250 GeV for EMCal.

  5. CMOS front-end electronics for radiation sensors

    CERN Document Server

    AUTHOR|(CDS)2071026

    2015-01-01

    This book offers a comprehensive treatment of front-end electronics for radiation detection. It discusses the fundamental principles of signal processing for radiation detectors and describes circuits at the level of functional building blocks, omitting transistor-level implementation. It also covers important system-level topics commonly found in the world of front-end electronics for radiation sensors. The book develops the topics in detail, with a constant focus on practical problems. It also provides real implementation examples that offer insights and stimuli for more experienced engineers already working in the field.

  6. A multichannel front end ASIC for PMT readout in LHAASO WCDA

    Science.gov (United States)

    Liang, Y.; Zhao, L.; Guo, Y.; Qin, J.; Yang, Y.; Cheng, B.; Liu, S.; An, Q.

    2018-01-01

    Time and charge measurements over a large dynamic range from 1 Photo Electron (P.E.) to 4000 P.E. are required for the Water Cherenkov Detector Array (WCDA), which is one of the key components in the Large High Altitude Air Shower Observatory (LHAASO). To simplify the circuit structure of the readout electronics, a front end ASIC was designed. Based on the charge-to-time conversion method, the output pulse width of the ASIC corresponds to the input signal charge information while time information of the input signal is picked off through a discriminator, and thus the time and charge information can be digitized simultaneously using this ASIC and a following Time-to-Digital Converter (TDC). To address the challenge of mismatch among the channels observed in the previous prototype version, this work presents approaches for analyzing the problem and optimizing the circuits. A new version of the ASIC was designed and fabricated in the GLOBALFOUNDRIES 0.35 μm CMOS technology, which integrates 6 channels (corresponding to the readout of the 3 PMTs) in each chip. The test results indicate that the mismatch between the channels is significantly reduced to less than 20% using the proposed approach. The time measurement resolution better than 300 ps is achieved, and the charge measurement resolution is better than 10% at 1 P.E., and 1% at 4000 P.E., which meets the application requirements.

  7. Overview of the front end electronics for the Atlas LAR calorimeter

    International Nuclear Information System (INIS)

    Rescia, S.

    1997-11-01

    Proposed experiments for the Large Hadron Collider (LHC) set new demands on calorimeter readout electronics. The very high energy and large luminosity of the collider call for a large number of high speed, large dynamic range readout channels which have to be carefully synchronized. The ATLAS liquid argon collaboration, after more than 5 years of R and D developments has now finalized the architecture of its front end and read-out electronics, which have been written down in its Technical Design Report (TDR). An overview is presented

  8. A front-end electronics module for the PHENIX pad chamber

    International Nuclear Information System (INIS)

    Smith, M.C.; Bryan, W.L.; Smith, D.

    1999-01-01

    The Pad Chamber (PC) is part of the Tracking System of the PHENIX detector at the RHIC accelerator of Brookhaven National Laboratory. A front-end electronics module (FEM) has been developed for the PHENIX Pad Chamber. The module's control functions are performed by the heap manager unit, an FPGE-based circuit on the FEM. Each FEM processes signals from 2,160 channels of front-end electronics (FEE). Data readout and formatting are performed by an additional FPGA-based circuit of the FEM. Three external systems provide initialization, timing, and data information via serial interfaces. This paper discusses the application of the heap manager, data formatter, and serial interfaces to meet the specific control and data readout needs of the Pad Chamber subsystem. Unit functions, interfaces, timing, data format, and communication rates will be discussed. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling and FPGA/Implementation and programming will be presented

  9. Development of ATLAS Liquid Argon Calorimeter Front-end Electronics for the HL-LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00219286; The ATLAS collaboration

    2016-01-01

    The high-luminosity phase of the Large Hadron Collider will provide 5-7 times greater luminosities than assumed in the original detector design. An improved trigger system requires an upgrade of the readout electronics of the ATLAS Liquid Argon Calorimeter. Concepts for the future readout of the 182,500 calorimeter channels at 40-80 MHz and 16-bit dynamic range and the developments of radiation-tolerant, low-noise, low-power, and high-bandwidth front-end electronic components, including preamplifiers and shapers, 14-bit ADCs, and 10-Gb/s laser diode array drivers, are presented.

  10. Dead-time free pixel readout architecture for ATLAS front-end IC

    CERN Document Server

    Einsweiler, Kevin F; Kleinfelder, S A; Luo, L; Marchesini, R; Milgrome, O; Pengg, F X

    1999-01-01

    A low power sparse scan readout architecture has been developed for the ATLAS pixel front-end IC. The architecture supports a dual discriminator and extracts the time over threshold (TOT) information along with a 2-D spatial address $9 of the hits associating them with a unique 7-bit beam crossing number. The IC implements level-1 trigger filtering along with event building (grouping together all hits in a beam crossing) in the end of column (EOC) buffer. The $9 events are transmitted over a 40 MHz serial data link with the protocol supporting buffer overflow handling by appending error flags to events. This mixed-mode full custom IC is implemented in 0.8 mu HP process to meet the $9 requirements for the pixel readout in the ATLAS inner detector. The circuits have been tested and the IC provides dead-time-less ambiguity free readout at 40 MHz data rate.

  11. Digital column readout architecture for the ATLAS pixel 025 mum front end IC

    CERN Document Server

    Mandelli, E; Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Marchesini, R; Meddeler, G; Peric, I

    2002-01-01

    A fast low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified to allow a safe transition to quarter micron technology. Each pixel cell, organized in a 160 multiplied by 18 matrix, can be independently enabled and configured in order to optimize the analog signal response and to prevent defective pixels from saturating the readout. The digital readout organizes hit data coming from each column, with respect to time, and output them on a low-level serial interface. A considerable effort was made to design state machines free of undefined states, where single-point defects and charge deposited by heavy ions in the silicon could have led to unpredicted forbidden states. 7 Refs.

  12. A fully integrated, low noise and low power BiCMOS front-end readout system for capacitive detectors

    CERN Document Server

    Guo, C C; Deptuch, G; Hu, Y Y

    2001-01-01

    Bipolar transistors are interesting for low noise front-end readout systems when high speed and low power consumption are required. This paper presents a fully integrated, low noise front-end design for the future Large Hadron Collider (LHC) experiments using the radiation hard SOI BiCMOS process. In the present prototype, the input-referred Equivalent Noise Charge (ENC) of 990 electrons (r.m.s.) for 12 pF detector capacitance with a shaping time of 25 ns and power consumption of 1.4 mW/channel has been measured. The gain of this front-end is 90 mV/MIP (Minimum Ionisation Particle: 1 MIP=3.84 fC) with non-linearity of less than 3% and linear input dynamic range is +or-5 MIP. These results are obtained at room temperature and before irradiation. The measurements after irradiations by high intensity pion beam with an integrated flux of 1.0*10/sup 14/ pions/cm/sup 2/ are also presented in this paper. (10 refs).

  13. Trigger/front end electronics and data collection

    International Nuclear Information System (INIS)

    Ikeda, Hirokazu

    1989-01-01

    The data collection system in the B factory at KEK is planned to have the features that the beam cross intervals will be small (15-30 necs), that the first-step trigger frequency will be 1 kHz, that the frequency of data transfer from the mass storage will be around 10 Hz, and that the data capacity will be 256 kilobyte/sec at most. A possible approach to meet these requirements is to use a trigger system of a pipeline mechanism, a multiple front end system, a high-speed data scanning module and a large-scale processor farm. The trigger system is intended to extract high-speed signals from the detector and to start and control the entire data collection system. The start signals and control signals should synchronize with the beam cross. The front end electronics comprises high-sensitivity analog electronics, including front amplifier, and an analog/digital converter. The data collection system has a tree structure. Its lowest layer comprises a multiple buffered memory. Required data are extracted by the high-speed data scanning module, stored in a memory incorporated in the scanning module, and then transferred to the processor farm. (N.K.)

  14. Front-end electronics for H.E.P

    International Nuclear Information System (INIS)

    Hrisoho, A.

    1990-07-01

    A simplified description of the front-end electronics used for High Energy Physics Detectors is given. A brief analysis of the speed limitation due to the time necessary for the detector charge transfer is given, which depends as well of the detector behaviour as of the preamplifier configuration. A description of the sample electronic circuits like differentiation, integration, pole zero circuit and preamplifier are given. Noise analysis is carried out to derive the relations for the equivalent noise signal for the measuring device with some description of practical noise measuring. The shaping of the signals to obtain an optimization for the noise is considered and some hints for shaping amplifier design, with a description of the noise weightling function for normal and time variant shaping are given

  15. Web-based DAQ systems: connecting the user and electronics front-ends

    International Nuclear Information System (INIS)

    Lenzi, Thomas

    2016-01-01

    Web technologies are quickly evolving and are gaining in computational power and flexibility, allowing for a paradigm shift in the field of Data Acquisition (DAQ) systems design. Modern web browsers offer the possibility to create intricate user interfaces and are able to process and render complex data. Furthermore, new web standards such as WebSockets allow for fast real-time communication between the server and the user with minimal overhead. Those improvements make it possible to move the control and monitoring operations from the back-end servers directly to the user and to the front-end electronics, thus reducing the complexity of the data acquisition chain. Moreover, web-based DAQ systems offer greater flexibility, accessibility, and maintainability on the user side than traditional applications which often lack portability and ease of use. As proof of concept, we implemented a simplified DAQ system on a mid-range Spartan6 Field Programmable Gate Array (FPGA) development board coupled to a digital front-end readout chip. The system is connected to the Internet and can be accessed from any web browser. It is composed of custom code to control the front-end readout and of a dual soft-core Microblaze processor to communicate with the client.

  16. Digital front-end electronics for COMPASS Muon-Wall 1 detector

    International Nuclear Information System (INIS)

    Alekseev, G.D.; Zhuravlev, N.I.; Maggiora, A.

    2005-01-01

    The digital front-end electronics for the COMPASS Muon-Wall 1 (CERN) detector is described. The digital card has been designed on the basis of the TDC chip F1. One card includes 6 F1 chips (192 channels), bus arbiter, DAC, power supply distribution, hot-link interface. The total number of the digital cards in the system is 44 housed in 5 euro-crates (6U), the total number of readout channels is 8448. The electronics has been designed by the Dzhelepov Laboratory of Nuclear Problems (JINR) and INFN (Torino, Italy) experts

  17. BGO front-end electronics and signal processing in the MXGS instrument for the ASIM mission

    DEFF Research Database (Denmark)

    Skogseide, Yngve; Cenkeramaddi, Linga Reddy; Genov, Georgi

    2012-01-01

    for the design and development of the detector layers and readout electronics for the MXGS instrument. The principal objective of the instrument is to detect Terrestrial Gamma ray Flashes (TGFs), which are related to thunderstorm activity. The digital pulse processing scheme used in the MXGS BGO detector gives......This paper presents the Bismuth Germanate Oxide (BGO) front-end electronics design and signal processing in Modular X- and Gamma ray sensor (MXGS) instrument onboard the Atmosphere Space Interaction Monitor (ASIM) mission, funded by the European Space Agency. University of Bergen is responsible...

  18. CMOS front end analog signal readout chip for Si-strip/PIN detectors

    International Nuclear Information System (INIS)

    Chandratre, V.B.; Sardesai, S.V.; Kataria, S.K.

    2001-01-01

    The paper presents the design of an 8-channel front-end chip for Si-strip detectors, ranging in capacitance from 1 to 30 pf. Each channel consists of a charge amplifier, a shaper amplifier (CR-RC 3 ) and a track-hold stage. The channel outputs are connected to an analog multiplexer which is controlled by an external clock for serial readout. The peaking time is adjustable over 250ns-2us in four fixed steps by external control. There is provision for changing gain low/high. A derivative of the chip is also developed for dosimeter application that uses small area diodes as detectors. The circuit has a power dissipation of 6 MW per channel and is designed to fabricate in 1.2um CMOS technology. The Opf noise is ∼400e. The design approach is presented and the results of simulation are shown. (author)

  19. Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

    CERN Document Server

    Albert, J; Alimonti, Gianluca; Allport, Phil; Altenheiner, Silke; Ancu, Lucian; Andreazza, Attilio; Arguin, Jean-Francois; Arutinov, David; Backhaus, Malte; Bagolini, Alvise; Ballansat, Jacques; Barbero, Marlon; Barbier, Gérard; Bates, Richard; Battistin, Michele; Baudin, Patrick; Beau, Tristan; Beccherle, Roberto; Beck, Hans Peter; Benoit, Mathieu; Bensinger, Jim; Bomben, Marco; Borri, Marcello; Boscardin, Maurizio; Botelho Direito, Jose Antonio; Bousson, Nicolas; Boyd, George Russell Jr; Breugnon, Patrick; Bruni, Graziano; Bruschi, Marco; Buchholz, Peter; Buttar, Craig; Cadoux, Franck; Calderini, Giovanni; Caminada, Leah; Capeans, Mar; Casse, Gianluigi; Catinaccio, Andrea; Cavalli-Sforza, Matteo; Chauveau, Jacques; Chu, Ming-Lee; Ciapetti, Marco; Cindro, Vladimir; Citterio, Mauro; Clark, Allan; Cobal, Marina; Coelli, Simone; Colijn, Auke-Pieter; Colin, Daly; Collot, Johann; Crespo-Lopez, Olivier; Dalla Betta, Gian-Franco; Darbo, Giovanni; DaVia, Cinzia; David, Pierre-Yves; Debieux, Stéphane; Delebecque, Pierre; Devetak, Erik; DeWilde, Burton; Di Girolamo, Beniamino; Dinu, Nicoleta; Dittus, Fridolin; Diyakov, Denis; Djama, Fares; Dobos, Daniel Adam; Doonan, Kate; Dopke, Jens; Dorholt, Ole; Dube, Sourabh; Dushkin, Andrey; Dzahini, Daniel; Egorov, Kirill; Ehrmann, Oswin; Elldge, David; Elles, Sabine; Elsing, Markus; Eraud, Ludovic; Ereditato, Antonio; Eyring, Andreas; Falchieri, Davide; Falou, Aboud; Fang, Xiaochao; Fausten, Camille; Favre, Yannick; Ferrere, Didier; Fleta, Celeste; Fleury, Julien; Flick, Tobias; Forshaw, Dean; Fougeron, Denis; Fritzsch, Thomas; Gabrielli, Alessandro; Gaglione, Renaud; Gallrapp, Christian; Gan, K; Garcia-Sciveres, Maurice; Gariano, Giuseppe; Gastaldi, Thibaut; Gemme, Claudia; Gensolen, Fabrice; George, Matthias; Ghislain, Patrick; Giacomini, Gabriele; Gibson, Stephen; Giordani, Mario Paolo; Giugni, Danilo; Gjersdal, Håvard; Glitza, Karl Walter; Gnani, Dario; Godlewski, Jan; Gonella, Laura; Gorelov, Igor; Gorišek, Andrej; Gössling, Claus; Grancagnolo, Sergio; Gray, Heather; Gregor, Ingrid-Maria; Grenier, Philippe; Grinstein, Sebastian; Gromov, Vladimir; Grondin, Denis; Grosse-Knetter, Jörn; Hansen, Thor-Erik; Hansson, Per; Harb, Ali; Hartman, Neal; Hasi, Jasmine; Hegner, Franziska; Heim, Timon; Heinemann, Beate; Hemperek, Tomasz; Hessey, Nigel; Hetmánek, Martin; Hoeferkamp, Martin; Hostachy, Jean-Yves; Hügging, Fabian; Husi, Coralie; Iacobucci, Giuseppe; Idarraga, John; Ikegami, Yoichi; Janoška, Zdenko; Jansen, Jens; Jansen, Luc; Jensen, Frank; Jentzsch, Jennifer; Joseph, John; Kagan, Harris; Karagounis, Michael; Kass, Richard; Kenney, Christopher J; Kersten, Susanne; Kind, Peter; Klingenberg, Reiner; Kluit, Ruud; Kocian, Martin; Koffeman, Els; Kok, Angela; Korchak, Oleksandr; Korolkov, Ilya; Kostyukhin, Vadim; Krieger, Nina; Krüger, Hans; Kruth, Andre; Kugel, Andreas; Kuykendall, William; La Rosa, Alessandro; Lai, Chung-Hang; Lantzsch, Kerstin; Laporte, Didier; Lapsien, Tobias; Lounis, abdenour; Lozano, Manuel; Lu, Yunpeng; Lubatti, Henry; Macchiolo, Anna; Mallik, Usha; Mandić, Igor; Marchand, Denis; Marchiori, Giovanni; Massol, Nicolas; Matthias, Wittgen; Mättig, Peter; Mekkaoui, Abderrazak; Menouni, Mohsine; Menu, Johann; Meroni, Chiara; Mesa, Javier; Micelli, Andrea; Michal, Sébastien; Miglioranzi, Silvia; Mikuž, Marko; Mitsui, Shingo; Monti, Mauro; Moore, J; Morettini, Paolo; Muenstermann, Daniel; Murray, Peyton; Nellist, Clara; Nelson, David J; Nessi, Marzio; Neumann, Manuel; Nisius, Richard; Nordberg, Markus; Nuiry, Francois-Xavier; Oppermann, Hermann; Oriunno, Marco; Padilla, Cristobal; Parker, Sherwood; Pellegrini, Giulio; Pelleriti, Gabriel; Pernegger, Heinz; Piacquadio, Nicola Giacinto; Picazio, Attilio; Pohl, David; Polini, Alessandro; Popule, Jiří; Portell Bueso, Xavier; Povoli, Marco; Puldon, David; Pylypchenko, Yuriy; Quadt, Arnulf; Quirion, David; Ragusa, Francesco; Rambure, Thibaut; Richards, Erik; Ristic, Branislav; Røhne, Ole; Rothermund, Mario; Rovani, Alessandro; Rozanov, Alexandre; Rubinskiy, Igor; Rudolph, Matthew Scott; Rummler, André; Ruscino, Ettore; Salek, David; Salzburger, Andreas; Sandaker, Heidi; Schipper, Jan-David; Schneider, Basil; Schorlemmer, Andre; Schroer, Nicolai; Schwemling, Philippe; Seidel, Sally; Seiden, Abraham; Šícho, Petr; Skubic, Patrick; Sloboda, Michal; Smith, D; Sood, Alex; Spencer, Edwin; Strang, Michael; Stugu, Bjarne; Stupak, John; Su, Dong; Takubo, Yosuke; Tassan, Jean; Teng, Ping-Kun; Terada, Susumu; Todorov, Theodore; Tomášek, Michal; Toms, Konstantin; Travaglini, Riccardo; Trischuk, William; Troncon, Clara; Troska, Georg; Tsiskaridze, Shota; Tsurin, Ilya; Tsybychev, Dmitri; Unno, Yoshinobu; Vacavant, Laurent; Verlaat, Bart; Vianello, Elisa; Vigeolas, Eric; von Kleist, Stephan; Vrba, Václav; Vuillermet, Raphaël; Wang, Rui; Watts, Stephen; Weber, Michele; Weber, Marteen; Weigell, Philipp; Weingarten, Jens; Welch, Steven David; Wenig, Siegfried; Wermes, Norbert; Wiese, Andreas; Wittig, Tobias; Yildizkaya, Tamer; Zeitnitz, Christian; Ziolkowski, Michal; Zivkovic, Vladimir; Zoccoli, Antonio; Zorzi, Nicola; Zwalinski, Lukasz

    2012-01-01

    The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

  20. Front-end electronics for accurate energy measurement of double beta decays

    International Nuclear Information System (INIS)

    Gil, A.; Díaz, J.; Gómez-Cadenas, J.J.; Herrero, V.; Rodriguez, J.; Serra, L.; Toledo, J.; Esteve, R.; Monzó, J.M.; Monrabal, F.; Yahlali, N.

    2012-01-01

    NEXT, a double beta decay experiment that will operate in Canfranc Underground Laboratory (Spain), aims at measuring the neutrinoless double-β decay of the 136Xe isotope using a TPC filled with enriched Xenon gas at high pressure operated in electroluminescence mode. One technological challenge of the experiment is to achieve resolution better than 1% in the energy measurement using a plane of UV sensitive photomultipliers readout with appropriate custom-made front-end electronics. The front-end is designed to be sensitive to the single photo-electron to detect the weak primary scintillation light produced in the chamber, and also to be able to cope with the electroluminescence signal (several hundred times higher and with a duration of microseconds). For efficient primary scintillation detection and precise energy measurement of the electroluminescent signals the front-end electronics features low noise and adequate amplification. The signal shaping provided allows the digitization of the signals at a frequency as low as 40 MHz.

  1. System-level considerations for the front-end readout ASIC in the CBM experiment from the power supply perspective

    Science.gov (United States)

    Kasinski, K.; Koczon, P.; Ayet, S.; Löchner, S.; Schmidt, C. J.

    2017-03-01

    New fixed target experiments using high intensity beams with energy up to 10 AGeV from the SIS100 synchrotron presently being constructed at FAIR/GSI are under preparation. Most of the readout electronics and power supplies are expected to be exposed to a very high flux of nuclear reaction products and have to be radiation tolerant up to 3 MRad (TID) and sustain up to 1014/cm2 of 1 MeV neutron equivalent in their life time. Moreover, the mostly minimum ionising particles under investigation leave very little signal in the sensors. Therefore very low noise level amplitude measurements are required by the front-end electronics for effective tracking. Sensor and interconnecting micro-cable capacitance and series resistance in conjunction with intrinsic noise of the charge sensitive amplifier are dominant noise sources in the system. However, the single-ended architecture of the amplifiers employed for the charge processing channels implies a potential problem with noise contributions from power supply sources. Strict system-level constraints leave very little freedom in selecting a power supply structure optimal with respect to: power efficiency, cooling capabilities and power density on modules, but also noise injection to the front-end via the power supply lines. Design of the power supply and distribution system of the Silicon Tracking System in the CBM experiment together with details on the front-end ASICs (STS -XYTER2) and measurement results of power supply and conditioning electronics (selected DC/DC converter and LDO regulators) are presented.

  2. Front-End electronics configuration system for CMS

    CERN Document Server

    Gras, P; Funk, W; Gross, L; Vintache, D

    2001-01-01

    The four LHC experiments at CERN have decided to use a commercial SCADA (Supervisory Control And Data Acquisition) product for the supervision of their DCS (Detector Control System). The selected SCADA, which is therefore used for the CMS DCS, is PVSS II from the company ETM. This SCADA has its own database, which is suitable for storing conventional controls data such as voltages, temperatures and pressures. In addition, calibration data and FE (Front-End) electronics configuration need to be stored. The amount of these data is too large to be stored in the SCADA database [1]. Therefore an external database will be used for managing such data. However, this database should be completely integrated into the SCADA framework, it should be accessible from the SCADA and the SCADA features, e.g. alarming, logging should be benefited from. For prototyping, Oracle 8i was selected as the external database manager. The development of the control system for calibration constants and FE electronics configuration has bee...

  3. A front end ASIC for the readout of the PMT in the KM3NeT detector

    International Nuclear Information System (INIS)

    Gajanana, D; Gromov, V; Timmer, P; Heine, E; Kluit, R

    2010-01-01

    In this work, we describe the front end ASIC to readout the Photo-Multiplier-Tube of the KM3NeT detector, in detail. Stringent power budgeting, area constraints and lowering cost motivate us to design a custom front-end ASIC for reading the PMT. The ASIC amplifies the PMT signal and discriminates it against a threshold level and delivers the information via low voltage differential signals (LVDS). These LVDS signals carry highly accurate timing information of the photons . The length of the LVDS signals or Time over Threshold (ToT) gives information on the number of detected photons. A one-time programmable read-only memory (PROM) block provides unique identification to the chip. The chip communicates with the data acquisition electronics via an I 2 C bus. The data is transmitted to shore via fiber optics, where processing is done. The ASIC was fabricated in 0.35u CMOS process from AustriaMicroSystems (AMS).

  4. A Front-End Readout Architecture for the CMS Barrel Muon Detector: A Feasibility Study

    International Nuclear Information System (INIS)

    Aguayo, P.; Alberdi, J.; Barcala, J.M.; Marin, J.; Molinero, A.; Navarrete, J.; Pablos, J.L. de; Romero, L.; Willmot, C.

    1995-01-01

    A feasibility study of a possible architecture for the CMS barrel muon detector readout electronics is presented. some aspects of system reliability are discussed. Values for the required FIFO's to store data during the first level trigger latency are given

  5. A front-end electronic system for large arrays of bolometers

    Science.gov (United States)

    Arnaboldi, C.; Carniti, P.; Cassina, L.; Gotti, C.; Liu, X.; Maino, M.; Pessina, G.; Rosenfeld, C.; Zhu, B. X.

    2018-02-01

    CUORE is an array of thermal calorimeters composed of 988 crystals held at about 10 mK, whose absorbed energy is read out with semiconductor thermistors. The composition of the crystal is TeO2, and the aim is the study of the double beta decay of 130Te on very long and stable runs. CUPID-0 is an array of 26 Zn82Se crystals with double thermistor readout to study the double beta decay of 82Se. In the present paper, we present an overview of the entire front-end electronic readout chain, from the preamplifier to the anti-aliasing filter. This overview includes motivations, design strategies, circuit implementation and performance results of the electronic system, including other auxiliary yet important elements like power supplies and the slow control communication system. The stringent requirements of stability on the very long experimental runs that are foreseen during CUORE and CUPID-0 operation, are achieved thanks to novel solutions of the front-end preamplifier and of the detector bias circuit setup.

  6. Front-end electronics for long straw tube systems

    International Nuclear Information System (INIS)

    Paulos, J.J.; Blake, S.L.

    1990-01-01

    This paper addresses several critical issues in the readout of long, small diameter plastic straw tubes for central tracking subsystems. Of particular concern are signal attentuation in long straw tubes and signal reflections which arise from improper termination at the ends of the tube. This work is part of a 12 institution collaboration to design and validate a hybrid central tracking chamber (HCTC) utilizing both straw tube and scintillating fiber components. The HCTC design calls for 4 mm diameter plastic straw tubes spanning the entire central tracking region (6-8 m) with readout electronics at both ends. An electrical isolator may be used at the center of each wire to separate each tube into two electrically isolated regions so as to reduce occupancy by a factor of two. With this scheme, no track is farther than 4 m from the associated readout electronics. The HCTC collaboration includes the participation of researchers at the University of Pennsylvania who have contributed a preamplifier and shaper ship which is used in the simulations presented here. A more complete discussion of the HCTC design can be found in the paper by Dr. Alfred Goshaw

  7. ATLAS LAr Phase upgrade of the Front End Electronics

    CERN Document Server

    Newcomer, Mitchel; The ATLAS collaboration

    2016-01-01

    The Phase II upgrade of the ATLAS Liquid Argon detector includes a 17 bit dynamic range front end amplifier with a two or three gain multi‐pole shaper employing CR‐(RC)n shaping. Each gain stage of the shaper will be followed by a 40Msps, 14b dynamic range, 12‐13b ENOB digitizer, serializer and fiber optic driver. A study is underway to see if a single technology (65nm or 130nm CMOS) will be suitable for all blocks up to the optical Link, enabling consideration of the development a Front End System On a Chip (FESOC).

  8. FERMI: a digital Front End and Readout MIcrosystem for high resolution calorimetry

    International Nuclear Information System (INIS)

    Alexanian, H.; Appelquist, G.; Bailly, P.

    1995-01-01

    We present a digital solution for the front-end electronics of high resolution calorimeters at future colliders. It is based on analogue signal compression, high speed A/D converters, a fully programmable pipeline and a digital signal processing (DSP) chain with local intelligence and system supervision. This digital solution is aimed at providing maximal front-end processing power by performing waveform analysis using DSP methods. For the system integration of the multichannel device a multi-chip, silicon-on-silicon multi-chip module (MCM) has been adopted. This solution allows a high level of integration of complex analogue and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of multichip integration provides a high degree of reliability and programmability at both the function and the system level, with the additional possibility of customising the microsystem to detector-specific requirements. For enhanced reliability in high radiation environments, fault tolerance strategies, i.e. redundancy, reconfigurability, majority voting and coding for error detection and correction, are integrated into the design. ((orig.))

  9. Front-End Electronics in calorimetry: from LHC to ILC

    International Nuclear Information System (INIS)

    De La Taille, Ch.

    2009-09-01

    This report summarizes the electronics developments for liquid argon calorimeter read-out at LHC and the development carried out in the framework of the CALICE collaboration for those of the future linear collider (ILC). It also includes chips designed for multi-anode photomultipliers (MaPMT) used in the OPERA experiment or on ATLAS luminometer, which also find applications in medical imaging. Started in the early 90's, the development for ATLAS calorimetry was extremely challenging in terms of readout speed, radiation tolerance and measurement accuracy. The high speed has required a new approach using current-sensitive preamplifiers instead of charge sensitive ones and the redefinition of noise performance in terms of ENI. The preamplifiers developed at Orsay and the monolithic shapers are described in Chapter 1, including considerations of digital filtering, which was a new technique in our field. Chapter 2 is dedicated to the calibration system, designed and built by Orsay, for which the high performance and accuracy necessitated in-depth studies. The 3. chapter closes the studies for ATLAS with a summary of the detector measurements which had to be carried out on the 200 000 channels in order to understand and model the detector and achieve everywhere the accuracy and uniformity at per-cent level. These developments for ATLAS ended in 2004, although parallel work was also carried out for the NA48 and DO calorimeters which are not detailed here. The next generation of collider will require a new generation of calorimeters, much more granular, referred to as 'imaging calorimetry' with embedded read-out electronics. The ASICs developed for this purpose in the framework of the CALICE collaboration are described in Chapter 4. They integrate all the functionalities of amplification, digitization and read-out making them complex 'System-On-Chip' circuits extremely efficient that find many other applications. A family of 3 chips reads out the Si-W electromagnetic

  10. Review of input stages used in front end electronics for particle detectors

    CERN Document Server

    Kaplon, J

    2015-01-01

    In this paper we present noise analysis of the input stages most commonly used in front end electronics for particle detectors. Analysis shows the calculation of the input referenced noise related to the active devices. It identifies the type, parallel or series, of the equivalent noise sources related to the input transistors, which is the important input for the further choice of the signal processing method. Moreover we calculate the input impedance of amplifiers employed in applications where the particle detector is connected to readout electronics by means of transmission line. We present schematics, small signal models,a complete set of equations, and results of the major steps of calculations for all discussed circuits.

  11. FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Plessl, Christian; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Zhang, Jinlong

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24~Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented, and hardware and ...

  12. Design and implementation of the ATLAS TRT front end electronics

    Science.gov (United States)

    Newcomer, Mitch; Atlas TRT Collaboration

    2006-07-01

    The ATLAS TRT subsystem is comprised of 380,000 4 mm straw tube sensors ranging in length from 30 to 80 cm. Polypropelene plastic layers between straws and a xenon-based gas mixture in the straws allow the straws to be used for both tracking and transition radiation detection. Detector-mounted electronics with data sparsification was chosen to minimize the cable plant inside the super-conducting solenoid of the ATLAS inner tracker. The "on detector" environment required a small footprint, low noise, low power and radiation-tolerant readout capable of triggering at rates up to 20 MHz with an analog signal dynamic range of >300 times the discriminator setting. For tracking, a position resolution better than 150 μm requires leading edge trigger timing with ˜1 ns precision and for transition radiation detection, a charge collection time long enough to integrate the direct and reflected signal from the unterminated straw tube is needed for position-independent energy measurement. These goals have been achieved employing two custom Application-specific integrated circuits (ASICS) and board design techniques that successfully separate analog and digital functionality while providing an integral part of the straw tube shielding.

  13. Design and implementation of the ATLAS TRT front end electronics

    International Nuclear Information System (INIS)

    Newcomer, Mitch

    2006-01-01

    The ATLAS TRT subsystem is comprised of 380,000 4 mm straw tube sensors ranging in length from 30 to 80 cm. Polypropelene plastic layers between straws and a xenon-based gas mixture in the straws allow the straws to be used for both tracking and transition radiation detection. Detector-mounted electronics with data sparsification was chosen to minimize the cable plant inside the super-conducting solenoid of the ATLAS inner tracker. The 'on detector' environment required a small footprint, low noise, low power and radiation-tolerant readout capable of triggering at rates up to 20 MHz with an analog signal dynamic range of >300 times the discriminator setting. For tracking, a position resolution better than 150 μm requires leading edge trigger timing with ∼1 ns precision and for transition radiation detection, a charge collection time long enough to integrate the direct and reflected signal from the unterminated straw tube is needed for position-independent energy measurement. These goals have been achieved employing two custom Application-specific integrated circuits (ASICS) and board design techniques that successfully separate analog and digital functionality while providing an integral part of the straw tube shielding

  14. FELIX: A high-throughput network approach for interfacing to front end electronics for ATLAS upgrades

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Christian Plessl; Roich, Alexander; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Zhang, Jinlong

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates probably up to 9.6 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. In particular the links used for readout are often detector-specific. Already in Run 3 this technology will be deployed in conjunction with new muon detectors, additional muon first-level triggering electronics and new on-detector and off-detector liquid argon calorimeter electronics to be used for first level triggering. A total of roughly 2000 GBT links or GBT-like links (for connecting to off-detector trigger electronics) will be needed. A new class of devices will need to be developed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper we prese...

  15. Computing challenges in the certification of ATLAS Tile Calorimeter front-end electronics during maintenance periods

    International Nuclear Information System (INIS)

    Solans, C; Carrió, F; Valero, A; Kim, H Y; Usai, G; Moreno, P; Reed, R; Sandrock, C; Ruan, X; Shalyugin, A; Schettino, V; Souza, J

    2014-01-01

    After two years of operation of the LHC, the ATLAS Tile calorimeter is undergoing a consolidation process of its front-end electronics. The certification is performed in the experimental area with a portable test-bench which is capable of controlling and reading out one front-end module through dedicated cables. This test-bench has been redesigned to improve the tests of the electronics functionality quality assessment of the data until the end of Phase I.

  16. Petiroc and Citiroc: front-end ASICs for SiPM read-out and ToF applications

    International Nuclear Information System (INIS)

    Fleury, J; Ahmad, S; Callier, S; Taille, C de La; Seguin, N; Thienpont, D; Dulucq, F; Martin, G

    2014-01-01

    Petiroc and Citiroc are the two latest ASIC from Weeroc dedicated to SiPM read-out. Petiroc is a 16-channel front-end ASIC designed to readout silicon photomultipliers (SiPMs) for particle time-of-flight measurement applications. It combines a very fast and low-jitter trigger with an accurate charge measurement. Citiroc is a 32-channel front-end ASIC designed to readout silicon photo-multipliers (SiPM). It allows triggering down to 1/3 pe and provides the charge measurement with a good noise rejection. Moreover, Citiroc outputs the 32-channel triggers with a high accuracy (100 ps). Each channel of both ASICs combines a trigger path with an accurate charge measurement path. An adjustment of the SiPM high voltage is possible using a channel-by-channel input DAC. That allows a fine SiPM gain and dark noise adjustment at the system level to correct for the non-uniformity of SiPMs. Timing measurement down to 16 ps RMS jitter for Petiroc and 100 ps RMS for Citiroc is possible along with 1% linearity energy measurement up to 2500 pe. The power consumption is around 3.5 mW/channel for Petiroc and 3 mW/channel for Citiroc, excluding ASICs outing buffer

  17. Front-end electronics and data acquisition system for imaging atmospheric Cherenkov telescopes

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Y.T., E-mail: chenytao@ynu.edu.cn [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Yunnan University, 650091 Kunming (China); La Taille, C. de [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Suomijärvi, T. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Cao, Z. [Institute of High Energy Physics, 100049 Beijing (China); Deligny, O. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Dulucq, F. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Ge, M.M. [Yunnan University, 650091 Kunming (China); Lhenry-Yvon, I. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Martin-Chassard, G. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Nguyen Trung, T.; Wanlin, E. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Xiao, G.; Yin, L.Q. [Institute of High Energy Physics, 100049 Beijing (China); Yun Ky, B. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Zhang, L. [Yunnan University, 650091 Kunming (China); Zhang, H.Y. [Tsinghua University, 100084 Beijing (China); Zhang, S.S.; Zhu, Z. [Institute of High Energy Physics, 100049 Beijing (China)

    2015-09-21

    In this paper, a front-end electronics based on an application-specific integrated circuit (ASIC) is presented for the future imaging atmospheric Cherenkov telescopes (IACTs). To achieve this purpose, a 16-channel ASIC chip, PARISROC 2 (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is used in the analog signal processing and digitization. The digitized results are sent to the server by a user-defined User Datagram Protocol/Internet Protocol (UDP/IP) hardcore engine through Ethernet that is managed by a FPGA. A prototype electronics fulfilling the requirements of the Wide Field of View Cherenkov Telescope Array (WFCTA) of the Large High Altitude Air Shower Observatory (LHAASO) project has been designed, fabricated and tested to prove the concept of the design. A detailed description of the development with the results of the test measurements are presented. By using a new input structure and a new configuration of the ASIC, the dynamic range of the circuit is extended. A highly precise-time calibrating algorithm is also proposed, verified and optimized for the mass production. The test results suggest that the proposed electronics design fulfills the general specification of the future IACTs.

  18. Controlling front-end electronics boards using commercial solutions

    CERN Document Server

    Beneyton, R; Jost, B; Schmeling, S

    2002-01-01

    LHCb is a dedicated B-physics experiment under construction at CERN's large hadron collider (LHC) accelerator. This paper will describe the novel approach LHCb is taking toward controlling and monitoring of electronics boards. Instead of using the bus in a crate to exercise control over the boards, we use credit-card sized personal computers (CCPCs) connected via Ethernet to cheap control PCs. The CCPCs will provide a simple parallel, I2C, and JTAG buses toward the electronics board. Each board will be equipped with a CCPC and, hence, will be completely independently controlled. The advantages of this scheme versus the traditional bus-based scheme will be described. Also, the integration of the controls of the electronics boards into a commercial supervisory control and data acquisition (SCADA) system will be shown. (5 refs).

  19. CMS Tracker Readout Prototype Front-End Driver PCI Mezzanine Card (Mk1) (connector side)

    CERN Multimedia

    J.Coughlan

    1998-01-01

    The tracking system of the CMS detector at the LHC employs Front End Driver (FED) cards to digitise, buffer and sparsify analogue data arriving via optical links from on detector pipeline chips. This paper describes a prototype version of the FED based upon the popular commercial PCI bus Mezzanine Card (PMC) form factor. The FED-PMC consists of an 8 channel, 9 bit ADC, card, providing a 1 MByte data buffer and operating at the LHC design frequency of 40 MHz. The core of the card is a re-programmable FPGA which allows the functionality of the card to be conveniently modified. The card is supplied with a comprehensive library of C routines.The PMC form factor allows the card to be plugged onto a wide variety of processor carrier boards and even directly into PCI based PCs. The flexibility of the FPGA based design permits the card to be used in a variety of ADC based applications.

  20. Front-End Electron Transfer Dissociation: A New Ionization Source

    Science.gov (United States)

    Earley, Lee; Anderson, Lissa C.; Bai, Dina L.; Mullen, Christopher; Syka, John E. P.; English, A. Michelle; Dunyach, Jean-Jacques; Stafford, George C.; Shabanowitz, Jeffrey; Hunt, Donald F.; Compton, Philip D.

    2013-01-01

    Electron transfer dissociation (ETD), a technique that provides efficient fragmentation while depositing little energy into vibrational modes, has been widely integrated into proteomics workflows. Current implementations of this technique, as well as other ion–ion reactions like proton transfer, involve sophisticated hardware, lack robustness, and place severe design limitations on the instruments to which they are attached. Described herein is a novel, electrical discharge-based reagent ion source that is located in the first differentially pumped region of the mass spectrometer. The reagent source was found to produce intense reagent ion signals over extended periods of time while having no measurable impact on precursor ion signal. Further, the source is simple to construct and enables implementation of ETD on any instrument without modification to footprint. Finally, in the context of hybrid mass spectrometers, relocation of the reagent ion source to the front of the mass spectrometer enables new approaches to gas phase interrogation of intact proteins. PMID:23909443

  1. Photodetectors and front-end electronics for the LHCb RICH upgrade

    Science.gov (United States)

    Cassina, L.; LHCb RICH

    2017-12-01

    The RICH detectors of the LHCb experiment provide identification of hadrons produced in high energy proton-proton collisions in the LHC at CERN over a wide momentum range (2-100 GeV/c). Cherenkov light is collected on photon detector planes sensitive to single photons. The RICH will be upgraded (in 2019) to read out every bunch crossing, at a rate of 40 MHz. The current hybrid photon detectors (HPD) will be replaced with multi-anode photomultiplier tubes (customisations of the Hamamatsu R11265 and the H12699 MaPMTs). These 8×8 pixel devices meet the experimental requirements thanks to their small pixel size, high gain, negligible dark count rate (∼50 Hz/cm2) and moderate cross-talk. The measured performance of several tubes is reported, together with their long-term stability. A new 8-channel front-end chip, named CLARO, has been designed in 0.35 μm CMOS AMS technology for the MaPMT readout. The CLARO chip operates in binary mode and combines low power consumption (∼1 mW/Ch), wide bandwidth (baseline restored in ⩽ 25 ns) and radiation hardness. A 12-bit digital register permits the optimisation of the dynamic range and the threshold level for each channel and provides tools for the on-site calibration. The design choices and the characterization of the electronics are presented.

  2. SENSROC4: An Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

    International Nuclear Information System (INIS)

    Gao, W.; Liu, H.; Gao, D.; Gan, B.; Wei, T.; Hu, Y.

    2013-06-01

    In this paper, we present the design of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for our small animal PET systems which objective is to achieve the following performances, the spatial resolution of 1 mm 3 , the detection efficiency of 15 % and the time resolution of 1 ns. A cascade amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuit is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. Based on the above techniques, an eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm x 2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 V/pC. The best test result of ENC is 86.5 e- at zero farad plus 9.3 e- per pico-farad. The nonlinearity is less than 3 %. The crosstalk is less than 2 %. The power dissipation is about 9 mW/channel (authors)

  3. Development of a dedicated front-end electronics for straw tube trackers in the bar PANDA experiment

    Science.gov (United States)

    Przyborowski, D.; Fiutowski, T.; Idzik, M.; Kajetanowicz, M.; Korcyl, G.; Salabura, P.; Smyrski, J.; Strzempek, P.; Swientek, K.; Terlecki, P.; Tokarz, J.

    2016-08-01

    The design and tests of front-end electronics for straw tube trackers in the bar PANDA experiment at FAIR are presented. The challenges for the front-end electronics, comprising operation at high counting rate up to 1 MHz per straw tube, are discussed and the proposed architecture comprising a switched gain charge sensitive preamplifier (CSP), a pole-zero cancellation circuit (PZC), a second order variable peaking time shaper, a trimming ion tail cancellation circuit, and a baseline holder (BLH), is described. The front-end provides an analogue output and a discriminator with LVDS differential driver for the Time-of-Arrival (ToA) and Time-over-Threshold (ToT) measurements. A prototype readout ASIC featuring four channels was fabricated in 0.35 μm CMOS technology consuming 15.5 mW (analog part) and 12 mW (LVDS) per channel. The results of measurements of peaking time (25-67 ns), gain, noise (ENC 800-2500 el. for various gains), time walk and jitter are presented as well as the first results obtained with prototype straw tubes connected.

  4. LHCb calorimeter front-end electronics radiation dose and single event effects

    CERN Document Server

    Beigbeder-Beau, C; Charlet, D; Lefrançois, J; Machefert, F P; Tocut, V; Truong, K D

    2002-01-01

    The LHCb calorimeter front-end electronics will be located above the ECAL / HCAL, i.e. in a region which is not protected from radiations. We present here an estimation of the radiation effect for the electronics and the solutions we investigate to reduce it. Two irradiation tests of the calorimeter front-end shaper have been performed, in June 2001 at the Centre de Proton Thérapie (Orsay) and in December 2001 at GANIL (Caen). The results of the tests clearly show the satisfying resistance of the shaper to SEL.

  5. A new approach to front-end electronics interfacing in the ATLAS experiment

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00015561; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Wu, Weihao; Zhang, Jinlong

    2016-01-01

    For new detector and trigger systems to be installed in the ATLAS experiment after LHC Run 2, a new approach will be followed for Front-End electronics interfacing. The FELIX (Front-End LInk eXchange) system will function as gateway connecting: on one side to detector and trigger electronics links, as well as providing timing and trigger (TTC) information; and on the other side a commodity switched network built using standard technology (either Ethernet or Infiniband). The new approach is described in this paper, and results achieved so far are presented.

  6. Upgrade to the front-end electronics of the BESIII muon identification system

    International Nuclear Information System (INIS)

    Xi Jianbo; Liang Hao; Xiang Shitao

    2014-01-01

    Resistive Plate Chambers (RPCs) built from a new type of Bakelite developed at Institute of High Energy Physics (IHEP), Chinese Academy of Sciences have been used in the BESIII Muon identification system for several years without linseed oil coating, but characteristic aging performances were observed. To adapt to the RPCs in the aging state, the front-end electronics have been upgraded by enhancing the front-end protection, improving the threshold setting circuit, and separating power supplies of the comparator and the field programmable gate array (FPGA). Improvements in system stability, front-end protection and threshold consistency have been achieved. In this paper, the system upgrade and the test results are described in detail. (authors)

  7. D-Zero muon readout electronics design

    International Nuclear Information System (INIS)

    Baldin, B.; Hansen, S.; Los, S.; Matveev, M.; Vaniev, V.

    1996-11-01

    The readout electronics designed for the D null Muon Upgrade are described. These electronics serve three detector subsystems and one trigger system. The front-ends and readout hardware are synchronized by means of timing signals broadcast from the D null Trigger Framework. The front-end electronics have continuously running digitizers and two levels of buffering resulting in nearly deadtimeless operation. The raw data is corrected and formatted by 16- bit fixed point DSP processors. These processors also perform control of the data buffering. The data transfer from the front-end electronics located on the detector platform is performed by serial links running at 160 Mbit/s. The design and test results of the subsystem readout electronics and system interface are discussed

  8. FELIX: a high-throughput network approach for interfacing to front end electronics for ATLAS upgrades

    NARCIS (Netherlands)

    Anderson, J.; Borga, A.; Boterenbrood, H.; Chen, H.; Chen, K.; Drake, G.; Francis, D.; Gorini, B.; Lanni, F.; Lehmann Miotto, G.; Levinson, L.; Narevicius, J.; Plessl, C.; Roich, A.; Ryu, S.; Schreuder, F.; Schumacher, J.; Vandelli, W.; Vermeulen, J.; Zhang, J.

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will

  9. Front-end Electronics for Unattended Measurement (FEUM). Prototype Test Plan

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C.; Morris, Scott J.; Smith, Leon E.; Keller, Daniel T.

    2015-09-16

    The IAEA has requested that PNNL perform an initial set of tests on front-end electronics for unattended measurement (FEUM) prototypes. The FEUM prototype test plan details the tests to be performed, the criteria for evaluation, and the procedures used to execute the tests.

  10. LHCb: Test Station for the LHCb Muon Front-End Electronic

    CERN Multimedia

    Polycarpo, E

    2005-01-01

    The LHCb Muon Group has developed the CMOS ASIC CARIOCA to readout its Multiwire Proportional Chambers (MWPC) and GEM detectors, using a rad-hard IBM 0.25um process. Each ASIC holds 8 identical current-mode ASDB channels with individual input thresholds. The Muon detector contains around 120000 physical channels, requiring production of 20000 front-end chips, roughly. CARIOCA has been developed to process MWPC cathode and anode signals and two different versions have been implemented to overcome the requirement of MWP and GEM chambers operation. The test station has been devised to accomplish bipolar tests and to measure characteristics of both CARIOCA versions.

  11. A 10 MHz micropower CMOS front end for direct readout of pixel detectors

    International Nuclear Information System (INIS)

    Campbell, M.; Heijne, E.H.M.; Jarron, P.; Krummenacher, F.; Enz, C.C.; Declercq, M.; Vittoz, E.; Viertel, G.

    1990-01-01

    In the framework of the CERN-LAA project for detector R and D, a micropower circuit of 200 μmx200 μm with a current amplifier, a latched comparator and a digital memory element has been tested electrically and operated in connection with linear silicon detector arrays. The experimental direct-readout (DRO) chip comprises a matrix of 9x12 circuit cells and has been manufactured in a 3 μm CMOS technology. Particles and X-ray photons below 22 keV were detected, and thresholds can be set between 2000 and 20000 e - . The noise is less than 4 keV FWHM or 500 e - rms and the power dissipation per pixel element is 30 μW. The chip can be coupled to a detector matrix using bump bonding. (orig.)

  12. Analog front-end electronics for the outer layers of the SuperB SVT: Design and expected performances

    Science.gov (United States)

    Bombelli, Luca; Fiorini, Carlo; Nasri, Bayan; Trigilio, Paolo; Citterio, Mauro; Neri, Nicola

    2013-08-01

    The Silicon Vertex Tracker (SVT) of the new SuperB collider will be composed of 6 different detector layers [1]. The innermost layer (L0) will be composed by striplets or pixels [2]; the other 5 detector layers will be double-sided long-strip detectors. The strip geometries and the foreseen hit-rates will change according to the different layers. As a consequence, different optimization of the analog read-out electronics is needed in order to provide high detection-efficiency and low noise level in the different layers. Two readout ASICs are currently developed, one for layers 0-3, another for layers 4 and 5; they differ mainly in the analog front-end. In this work, we present the design and the expected performances of the analog front-end for layers 4 and 5. For these layers, the strip detectors show a very high stray capacitance and high series resistance. In this condition, the noise optimization is our primary concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been found. We will present the design of preamplifier and shaper and the results of simulation of noise performance and efficiency (with the expected background rates). In addition, the design of the time-over-threshold and its use to correct the time-walk of the event trigger is discussed as well as the achievable timing accuracy of the circuit.

  13. Development of front-end electronics and TDC LSI for the ATLAS MDT

    CERN Document Server

    Arai, Y

    2000-01-01

    Architecture of the front-end electronics for the ATLAS muon precision chamber (MDT) is presented. Especially, test results of a prototype TDC chip are described in detail. The chip was fabricated in a 0.3 mu m CMOS gate-array technology. Measurements of critical elements of the chip such as the PLL, and data buffering circuits demonstrated adequate performance. The effect of gamma-ray irradiation, using a /sup 60/Co source, and neutron irradiation, were also examined. The test results revealed radiation tolerance adequate for the operation of the circuits in the environment of the ATLAS MDT. Mounting of the front-end electronics to the MDT is scheduled to start in the year 2001. (10 refs).

  14. An ASIC implementation of digital front-end electronics for a high resolution PET scanner

    International Nuclear Information System (INIS)

    Newport, D.F.; Young, J.W.

    1993-01-01

    AN Application Specific Integrated Circuit (ASIC) has been designed and fabricated which implements many of the current functions found in the digital front-end electronics for a high resolution Positron Emission Tomography (PET) scanner. The ASIC performs crystal selection, energy qualification, time correction, and event counting functions for block technology high resolution PET scanners. Digitized x and y position, event energy, and time information are used by the ASIC to determine block crystal number, qualify the event based on energy, and correct the event time. In addition, event counting and block dead time calculations are performed for system dead time corrections. A loadable sequencer for controlling the analog front-end electronics is also implemented. The ASIC is implemented in a 37,000 gate, 1.0 micron CMOS gate-array and is capable of handling 4 million events/second while reducing parts count, cost, and power consumption over current board-level designs

  15. The new Front End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00226662; The ATLAS collaboration

    2016-01-01

    We present the plans, design, and performance results to date for the new front end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front end electronics will be replaced to address the increased luminosity at the HL-LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low voltage power supply. There are different options for implementing these subcomponents, which will be describ...

  16. The New Front End Electronics For the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Gomes, Agostinho; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increased luminosity at the HL-LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be describ...

  17. The new front-end electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    Science.gov (United States)

    Gomes, A.

    2016-02-01

    We present the plans, design, and performance results to date for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increased luminosity at the HL-LHC around 2025, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector. The new on-detector electronics contains five main parts: the front-end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low voltage power supply. There are different options for implementing these subcomponents, which will be described. The new system contains new features that in the current version include power system redundancy, data collection redundancy, data transmission redundancy with 2 QSFP optical transceivers and Kintex-7 FPGAs with firmware enhanced scheme for single event upset mitigation. To date, we have built a Demonstrator—a fully functional prototype of the new system. Performance results and plans are presented.

  18. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date ofor the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcompone...

  19. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00029377; The ATLAS collaboration

    2015-01-01

    We present the design for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the Front End Boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be described. The new sys...

  20. The front-end analog and digital signal processing electronics for the drift chambers of the Stanford Large Detector

    International Nuclear Information System (INIS)

    Haller, G.M.; Freytag, D.R.; Fox, J.; Olsen, J.; Paffrath, L.; Yim, A.; Honma, A.

    1990-10-01

    The front-end signal processing electronics for the drift-chambers of the Stanford Large Detector (SLD) at the Stanford Linear Collider is described. The system is implemented with printed-circuit boards which are shaped for direct mounting on the detector. Typically, a motherboard comprises 64 channels of transimpedance amplification and analog waveform sampling, A/D conversion, and associated control and readout circuitry. The loaded motherboard thus forms a processor which records low-level wave forms from 64 detector channels and transforms the information into a 64 k-byte serial data stream. In addition, the package performs calibration functions, measures leakage currents on the wires, and generates wire hit patterns for triggering purposes. The construction and operation of the electronic circuits utilizing monolithic, hybridized, and programmable components are discussed

  1. Test system for the production of the Atlas Tile Calorimeter front-end electronics

    International Nuclear Information System (INIS)

    Calvet, David

    2004-01-01

    The Atlas hadronic Tile Calorimeter front-end electronics is fully included in the so-called 'super-drawers'. The 256 super-drawers needed for the entire calorimeter are assembled and extensively tested in Clermont-Ferrand before being sent to CERN to be inserted in the calorimeter modules. A mobile system has been developed to perform a complete test of the super-drawers during their insertion

  2. Automation of front-end loaders : electronic self leveling and payload estimation

    OpenAIRE

    Yung, I

    2017-01-01

    A growing population is driving automatization in agricultural industry to strive for more productive arable land. Being part of this process, this work is aimed to investigate the possibility to implement sensor-based automation in a particular system called Front End Loader, which is a lifting arms that is commonly mounted on the front of a tractor. Two main tasks are considered here, namely Electronic Self Leveling (ESL) and payload estimation. To propose commercially implementable solutio...

  3. Test system for the production of the ATLAS Tile Calorimeter front- end electronics

    CERN Document Server

    Calvet, D

    2004-01-01

    The Atlas hadronic Tile Calorimeter front-end electronics is fully included in the so-called "super-drawers". The 256 super-drawers needed for the entire calorimeter are assembled and extensively tested in Clermont-Ferrand before being sent to CERN to be inserted in the calorimeter modules. A mobile system has been developed to perform a complete test of the super-drawers during their insertion.

  4. Search for supersymmetric top-quark partners using support vector machines and upgrade of the hadron calorimeter front-end readout control system at CMS

    International Nuclear Information System (INIS)

    Sahin, Mehmet Oezguer

    2017-04-01

    the 8 TeV center-of-mass energy in the single lepton final states is extended to m t = 675 GeV and m χ 0 = 225 GeV. The results of the present analysis once again verified the necessity to reach higher center-of-mass energies and luminosities at the LHC. Such an upgrade will increase the radiation exposure of the readout electronics. A reliable operation of the detector electronics under these harsh conditions is absolutely crucial. Therefore, a new front-end readout control system has been integrated to the upgraded electronics infrastructure of the CMS HCAL, which simultaneously sets up and controls all front-end modules. Furthermore, it recovers diagnostic information and responses immediately in case of unexpected events. A firmware for the next-generation Front-End-Control module helping to accomplish these tasks has been developed. Consistency and reliability of the control system is successfully tested in the test-stands and irradiation beam tests.

  5. Search for supersymmetric top-quark partners using support vector machines and upgrade of the hadron calorimeter front-end readout control system at CMS

    Energy Technology Data Exchange (ETDEWEB)

    Sahin, Mehmet Oezguer

    2017-04-15

    previous searches with the 8 TeV center-of-mass energy in the single lepton final states is extended to m{sub t} = 675 GeV and m{sub χ{sup 0}} = 225 GeV. The results of the present analysis once again verified the necessity to reach higher center-of-mass energies and luminosities at the LHC. Such an upgrade will increase the radiation exposure of the readout electronics. A reliable operation of the detector electronics under these harsh conditions is absolutely crucial. Therefore, a new front-end readout control system has been integrated to the upgraded electronics infrastructure of the CMS HCAL, which simultaneously sets up and controls all front-end modules. Furthermore, it recovers diagnostic information and responses immediately in case of unexpected events. A firmware for the next-generation Front-End-Control module helping to accomplish these tasks has been developed. Consistency and reliability of the control system is successfully tested in the test-stands and irradiation beam tests.

  6. A Front-End Electronics Prototype Based on Gigabit Ethernet for the ATLAS Small-Strip Thin Gap Chamber

    Science.gov (United States)

    Hu, Kun; Lu, Houbing; Wang, Xu; Li, Feng; Wang, Xinxin; Geng, Tianru; Yang, Hang; Liu, Shengquan; Han, Liang; Jin, Ge

    2017-06-01

    A front-end electronics prototype for the ATLAS small-strip Thin Gap Chamber (sTGC) based on gigabit Ethernet has been developed. The prototype is designed to read out signals of pads, wires, and strips of the sTGC detector. The prototype includes two VMM2 chips developed to read out the signals of the sTGC, a Xilinx Kintex-7 field-programmable gate array (FPGA) used for the VMM2 configuration and the events storage, and a gigabit Ethernet transceiver PHY chip for interfacing with a computer. The VMM2 chip is designed for the readout of the Micromegas detector and sTGC detector, which is composed of 64 linear front-end channels. Each channel integrates a charge-sensitive amplifier, a shaper, several analog-to-digital converters, and other digital functions. For a bunch-crossing interval of 25 ns, events are continuously read out by the FPGA and forwarded to the computer. The interface between the computer and the prototype has been measured to reach an error-free rate of 900 Mb/s, therefore making a very effective use of the available bandwidth. Additionally, the computer can control several prototypes of this kind simultaneously via the Ethernet interface. At present, the prototype will be used for the sTGC performance test. The features of the prototype are described in detail.

  7. Characterization and performance of monolithic detector blocks with a dedicated ASIC front-end readout for PET imaging of the human brain

    International Nuclear Information System (INIS)

    Rato Mendes, Pedro; Sarasola Martin, Iciar; Canadas, Mario; Garcia de Acilu, Paz; Cuypers, Robin; Perez, Jose Manuel; Willmott, Carlos

    2011-01-01

    We are developing a human brain PET scanner prototype compatible with MRI based on monolithic scintillator crystals, APD matrices and a dedicated ASIC front-end readout. In this work we report on the performance of individual detector modules and on the operation of such modules in PET coincidence. Results will be presented on the individual characterization of detector blocks and its ASIC front-end readout, with measured energy resolutions of 13% full-width half-maximum (FWHM) at 511 keV and spatial resolutions of the order of 2 mm FWHM. First results on PET coincidence performance indicate spatial resolutions as good as 2.1 mm FWHM for SSRB/FBP reconstruction of tomographic data obtained using a simple PET demonstrator based on a pair of monolithic detector blocks with ASIC readout.

  8. The DIRC front-end electronics chain for BaBar

    CERN Document Server

    Bailly, P; Del Buono, L; Genat, J F; Lebbolo, H; Roos, L; Zhang, B; Beigbeder-Beau, C; Bernier, R; Breton, D; Cacéres, T; Chase, Robert L; Ducorps, A; Hrisoho, A; Imbert, P; Sen, S; Tocut, V; Truong, K; Wormser, G; Zomer, F; Bonneaud, G; Dohou, F; Gastaldi, F; Matricon, P; Renard, C; Thiebaux, C; Vasileiadis, G; Verderi, M; Oxoby, G; Vavra, J; Warner, D; Wilson, R J

    1999-01-01

    The detector of Internally Reflected Cherenkov light (DIRC) of the BaBar detector (SLAC Stanford, USA) measures better than 1 ns the arrival time of Cherenkov photoelectrons, detected in a 11 000 phototubes array and their amplitude spectra. It mainly comprises of 64-channel DIRC Front-End Boards (DFB) equipped with eight full-custom Analog chips performing zero-cross discrimination with 2 mV threshold and pulse shaping, four full-custom Digital TDC chips for timing measurements with 500 ps binning and a readout logic selecting hits in the trigger window, and DIRC Crate Controller cards (DCC) serializing the data collected from up to 16 DFBs onto a 1.2 Gb/s optical link. Extensive test of the pre-production chips have been performed as well as system tests.

  9. FE-I2 a front-end readout chip designed in a commercial 025- mu m process for the ATLAS pixel detector at LHC

    CERN Document Server

    Blanquart, L; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I

    2004-01-01

    A new front-end chip (FE-I2) has been developed for the ATLAS pixel detector at the future Large Hadron Collider (LHC) accelerator facility of the European Laboratory for Particle Physics (CERN). This chip has been submitted in a commercial 0.25- mu m CMOS process using special layout techniques for radiation tolerance. It comprises 2880 pixels arranged into 18 columns of 160 channels. Each pixel element of dimension 50 mu m * 400 mu m is composed of a charge- sensitive amplifier followed by a fast discriminator with a detection threshold adjustable within a range of 0-6000 electrons and slow control logic incorporating a wired-hit-Or, preamplifier-kill, readout mask, and automatic threshold tuning circuitry. There are two single-event- upset (SEU)-tolerant DACs for reducing threshold (7-b) and recovery- time (3-b) mismatches from pixel to pixel along with digital hit emulation and a differential readout circuit aimed at transporting time-stamped data from each pixel to buffers at the bottom of the chip. In c...

  10. The Front End Electronics of the Scintillator Pad Detector of LHCb Calorimeter

    CERN Document Server

    Gascon, David; Bota, S; Comerma, A; Diéguez, A; Garrido, L; Gaspar, A; Graciani, R; Graciani, E; Herms, A; Llorens, M; Luengo, S; Picatoste, E; Riera, J; Rosselló, M; Ruiz, H; Tortella, S; Vilasís, X

    2007-01-01

    In this paper the Front End electronics of the Scintillator Pad Detector (SPD) is outlined. The SPD is a sub-system of the Calorimeter of the LHCb experiment designed to discriminate between charged and neutral particles for the first level trigger. The system design is presented, describing its different functionalities implemented through three different cards and several ASICs. These functionalities are signal processing and digitization, data transmission, interface with control and timing systems of the experiment, low voltage power supply distribution and monitoring. Special emphasis is placed on installation and commissioning subjects such as cabling, grounding, shielding and power distribution.

  11. A GEM-TPC prototype with low-Noise highly integrated front-end electronics for linear collider studies

    CERN Document Server

    Kappler, Steffen; Kaminski, Jochen; Ledermann, Bernhard; Müller, Thomas; Ronan, Michael T; Ropelewski, Leszek; Sauli, Fabio; Settles, Ronald

    2004-01-01

    Connected to the linear collider project, studies on the readout of time projection chambers (TPCs) based on the gas electron multiplier (GEM) are ongoing. Higher granularity and intrinsically suppressed ion feedback are the major advantages of this technology. After a short discussion of these issues, we present the design of a small and very flexible TPC prototype, whose cylindrical drift volume can be equipped with endcaps of different gas detector types. An endcap with multi-GEM readout is currently set up and successfully operated with a low-noise highly integrated front-end electronics. We discuss results of measurements with this system in high intensity particle beams at CERN, where 99.3 plus or minus 0.2% single-pad-row efficiency could be achieved at an effective gain of 2.5 multiplied by 10**3 only, and spatial resolutions down to 63 plus or minus 3 mum could be demonstrated. Finally, these results are extrapolated to the high magnetic field in a linear collider TPC. 5 Refs.

  12. Performance of a radiation hard 128 channel analogue front-end chip for the readout of a silicon-based hybrid photon detector

    CERN Document Server

    Lacasta, C; Dulinski, W; Chesi, Enrico Guido; Joram, C; Kaplon, J; Lozano-Bahilo, J; Séguinot, Jacques; Szczygiel, R; Weilhammer, Peter; Ypsilantis, Thomas

    2003-01-01

    The performance is described of a front-end chip, the SCT128A-LC chip, originally developed for the readout of a silicon based Hybrid Photon Detector (HPD), which is part of an RICH detector to be run in an LHC experimental environment. The relatively low signal charge from single photoelectrons, impinging on the silicon pad sensor, put very stringent requirements on the noise performance of the front-end chip. An absolute noise calibration using X-ray sources and a **2**4**1Am gamma source was performed. It is demonstrated that sufficiently good signal over noise ratio can be obtained to use this chip for the read-out of an HPD in LHC experiments.

  13. Estimation of radiation effects in the front-end electronics of an ILC electromagnetic calorimeter

    International Nuclear Information System (INIS)

    Bartsch, V.; Postranecky, M.; Targett-Adams, C.; Warren, M.; Wing, M.

    2008-01-01

    The front-end electronics of the electromagnetic calorimeter of an International Linear Collider detector are situated in a radiation environment. This requires the effect of the radiation on the performance of the electronics, specifically FPGAs, to be examined. In this paper we study the flux, particle spectra and deposited doses at the front-end electronics of the electromagnetic calorimeter of a detector at the ILC. We also study the occupancy of the electromagnetic calorimeter. These estimates are compared with measurements, e.g. of the radiation damage of FPGAs, done elsewhere. The outcome of the study shows that the radiation doses and the annual flux is low enough to allow today's FPGAs to operate. The Single Event Upset rate, however, lies between 14 min and 12 h depending on the FPGA used and therefore needs to be considered in the design of the data acquisition system of the electromagnetic calorimeter. The occupancy is about 0.002 per bunch train not taking into account the effect of noise which depends on the choice of the detector

  14. A new portable test bench for the ATLAS Tile Calorimeter front-end electronics certification

    International Nuclear Information System (INIS)

    Alves, J.; Carrio, F.; Moreno, P.; Usai, G.; Valero, A.; Kim, H.Y.; Minashvili, I.; Shalyugin, A.; Reed, R.; Schettino, V.; Souza, J.; Solans, C.

    2013-06-01

    This paper describes the upgraded portable test bench for the Tile Calorimeter of the ATLAS experiment at CERN. The previous version of the portable test bench was extensively used for certification and qualification of the front-end electronics during the commissioning phase as well as during the short maintenance periods of 2010 and 2011. The new version described here is designed to be an easily upgradable version of the 10-year-old system, able to evaluate the new technologies planned for the ATLAS upgrade as well as provide new functionalities to the present system. It will be used in the consolidation of electronics campaign during the long shutdown of the LHC in 2013-14 and during future maintenance periods. The system, based on a global re-design with state-of-the-art devices, is based on a back-end electronics crate instrumented with commercial and custom modules and a front-end GUI that is executed on an external portable computer and communicates with the controller in the crate through an Ethernet connection. (authors)

  15. Front-end Electronics for Unattended Measurement (FEUM). Results of Prototype Evaluation

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Keller, Daniel T. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Morris, Scott J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Smith, Leon E. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

    2015-07-01

    The International Atomic Energy Agency (IAEA) deploys unattended monitoring systems to provide continuous monitoring of nuclear material within safeguarded facilities around the world. As the number of unattended monitoring instruments increases, the IAEA is challenged to become more efficient in the implementation of those systems. In 2010, the IAEA initiated the Front-End Electronics for Unattended Measurement (FEUM) project with the goals of greater flexibility in the interfaces to various sensors and data acquisition systems, and improved capabilities for remotely located sensors (e.g., where sensor and front-end electronics might be separated by tens of meters). In consultation with the IAEA, a technical evaluation of a candidate FEUM device produced by a commercial vendor has been performed. This evaluation assessed the device against the IAEA’s original technical specifications and a broad range of important parameters that include sensor types, cable lengths and types, industrial electromagnetic noise that can degrade signals from remotely located detectors, and high radiation fields. Testing data, interpretation, findings and recommendations are provided.

  16. Detector and Front-end electronics for ALICE and STAR silicon strip layers

    CERN Document Server

    Arnold, L; Coffin, J P; Guillaume, G; Higueret, S; Jundt, F; Kühn, C E; Lutz, Jean Robert; Suire, C; Tarchini, A; Berst, D; Blondé, J P; Clauss, G; Colledani, C; Deptuch, G; Dulinski, W; Hu, Y; Hébrard, L; Kucewicz, W; Boucham, A; Bouvier, S; Ravel, O; Retière, F

    1998-01-01

    Detector modules consisting of Silicon Strip Detector (SSD) and Front End Electronics (FEE) assembly have been designed in order to provide the two outer layers of the ALICE Inner Tracker System (ITS) [1] as well as the outer layer of the STAR Silicon Vertex Tracker (SVT) [2]. Several prototypes have beenproduced and tested in the SPS and PS beam at CERN to validate the final design. Double-sided, AC-coupled SSD detectors provided by two different manufacturers and also a pair of single-sided SSD have been asssociated to new low-power CMOS ALICE128C ASIC chips in a new detector module assembly. The same detectors have also been associated to current Viking electronics for reference purpose. These prototype detector modules are described and some first results are presented.

  17. Front end electronics and first results of the ALICE V0 detector

    Energy Technology Data Exchange (ETDEWEB)

    Zoccarato, Y., E-mail: y.zoccarato@ipnl.in2p3.f [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Tromeur, W. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Aguilar, S.; Alfaro, R.; Almaraz Avina, E.; Anzo, A.; Belmont, E. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico); Cheshkov, C.; Cheynis, B.; Combaret, C. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Contreras, G. [Centro de Investigacion y de Estudios Avanzados (CINVESTAV), Av. Instituto Politecnico Nacional 2508 Col. San Pedro Zacatenco, C.P. 07360, Mexico, D.F. (Mexico); Cuautle, E. [Instituto de Ciencias Nucleares, Universidad Nacional Autonoma de Mexico, Circuito Exterior s/n, Ciudad Universitaria. Delg. Coyoacan, C.P. 04510, Mexico, D.F. (Mexico); Ducroux, L. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Gonzalez Trueba, L.; Grabski, V. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico); Grossiord, J.-Y. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Herrera Corral, G. [Centro de Investigacion y de Estudios Avanzados (CINVESTAV), Av. Instituto Politecnico Nacional 2508 Col. San Pedro Zacatenco, C.P. 07360, Mexico, D.F. (Mexico); Martinez, A. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico)

    2011-01-21

    This paper gives a detailed description of the acquisition and trigger electronics especially designed for the V0 detector of ALICE at LHC. A short presentation of the detector itself is given before the description of the Front End Electronics (FEE) system, which is completely embedded within the LHC environment as far as acquisition (DAQ), trigger (CTP), and detector control (DCS) are concerned. It is able to detect on-line coincident events and to achieve charge (with a precision of 0.6 pC) and time measurements (with a precision of 100 ps). It deploys quite a simple architecture. It is however totally programmable and fully non-standard in discriminating events coming from Beam-Beam interaction and Beam-Gas background. Finally, raw data collected from the first LHC colliding beams illustrate the performance of the system.

  18. Design and Measurement of a Low-Noise 64-Channels Front-End Readout ASIC for CdZnTe Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Gan, Bo; Wei, Tingcun; Gao, Wu; Liu, Hui; Hu, Yann [School of Computer Science and Technology, Northwestern Polytechnical University, Xi' an (China)

    2015-07-01

    Cadmium zinc telluride (CdZnTe) detectors, as one of the principal detectors for the next-generation X-ray and γ-ray imagers, have high energy resolution and supporting electrode patterning in the radiation environment at room-temperature. In the present, a number of internationally renowned research institutions and universities are actively using these detector systems to carry out researches of energy spectrum analysis, medical imaging, materials characterization, high-energy physics, nuclear plant monitoring, and astrophysics. As the most important part of the readout system for the CdZnTe detector, the front-end readout application specific integrated circuit (ASIC) would have an important impact on the performances of the whole detector system. In order to ensure the small signal to noise ratio (SNR) and sufficient range of the output signal, it is necessary to design a front-end readout ASIC with very low noise and very high dynamic range. In addition, radiation hardness should be considered when the detectors are utilized in the space applications and high energy physics experiments. In this paper, we present measurements and performances of a novel multi-channel radiation-hardness low-noise front-end readout ASIC for CdZnTe detectors. The readout circuits in each channel consist of charge sensitive amplifier, leakage current compensation circuit (LCC), CR-RC shaper, S-K filter, inverse proportional amplifier, peak detect and hold circuit (PDH), discriminator and trigger logic, time sequence control circuit and driving buffer. All of 64 readout channels' outputs enter corresponding inputs of a 64 channel multiplexer. The output of the mux goes directly out of the chip via the output buffer. The 64-channel readout ASIC is implemented using the TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 2.7 mm x 8 mm. At room temperature, the equivalent noise level of a typical channel reaches 66 e{sup -} (rms) at zero farad for a

  19. Performance of the front-end electronics of the ANTARES neutrino telescope

    Science.gov (United States)

    Aguilar, J. A.; Al Samarai, I.; Albert, A.; Anghinolfi, M.; Anton, G.; Anvar, S.; Ardid, M.; Assis Jesus, A. C.; Astraatmadja, T.; Aubert, J.-J.; Auer, R.; Baret, B.; Basa, S.; Bazzotti, M.; Bertin, V.; Biagi, S.; Bigongiari, C.; Bou-Cabo, M.; Bouwhuis, M. C.; Brown, A.; Brunner, J.; Busto, J.; Camarena, F.; Capone, A.; Caponetto, L.; Cârloganu, C.; Carminati, G.; Carr, J.; Castorina, E.; Cavasinni, V.; Cecchini, S.; Chaleil, Th.; Charvis; Chiarusi, T.; Chon Sen, N.; Circella, M.; Costantini, H.; Cottini, N.; Coyle, P.; Curtil, C.; de Bonis, G.; de Botton, N.; Dekeyser, I.; Delagnes, E.; Deschamps, A.; Distefano, C.; Donzaud, C.; Dornic, D.; Drouhin, D.; Druillole, F.; Eberl, T.; Emanuele, U.; Ernenwein, J.-P.; Escoffier, S.; Falchini, E.; Fehr, F.; Feinstein, F.; Flaminio, V.; Fopma, J.; Fratini, K.; Fritsch, U.; Fuda, J.-L.; Gay, P.; Giacomelli, G.; Gómez-González, J. P.; Graf, K.; Guillard, G.; Halladjian, G.; Hallewell, G.; Hoffmann, C.; van Haren, H.; Heijboer, A. J.; Hello, Y.; Hernández-Rey, J. J.; Herold, B.; Hößl, J.; de Jong, M.; Kalantar-Nayestanaki, N.; Kalekin, O.; Kappes, A.; Katz, U.; Kooijman, P.; Kopper, C.; Kouchner, A.; Kretschmer, W.; Lachartre, D.; Lafoux, H.; Lahmann, R.; Lamare, P.; Lambard, G.; Larosa, G.; Laschinsky, H.; Le Provost, H.; Le van Suu, A.; Lefèvre, D.; Legou, T.; Lelaizant, G.; Lim, G.; Lo Presti, D.; Loehner, H.; Loucatos, S.; Lucarelli, F.; Mangano, S.; Marcelin, M.; Margiotta, A.; Martinez-Mora, J. A.; Mazure, A.; Monmarthe, E.; Montaruli, T.; Morganti, M.; Moscoso, L.; Motz, H.; Naumann, C.; Neff, M.; Olivetto, Ch.; Ostasch, R.; Palioselitis, D.; Păvăla, G. E.; Payre, P.; Petrovic, J.; Piattelli, P.; Picot-Clemente, N.; Picq, C.; Pineau, J.-P.; Poinsignon, J.; Popa, V.; Pradier, T.; Presani, E.; Racca, C.; Radu, A.; Reed, C.; Réthoré, F.; Riccobene, G.; Richardt, C.; Rujoiu, M.; Russo, G. V.; Salesa, F.; Sapienza, P.; Schöck, F.; Schuller, J. P.; Shanidze, R.; Simeone, F.; Spurio, M.; Steijger, J. J. M.; Stolarczyk, Th.; Tamburini, C.; Tasca, L.; Toscano, S.; Vallage, B.; van Elewyck, V.; Vannoni, G.; Vecchi, M.; Vernin, P.; Wijnker, G.; de Wolf, E.; Yepes, H.; Zaborov, D.; Zornoza, J. D.; Zúñiga, J.; ANTARES Collaboration

    2010-10-01

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube signals, measure their arrival time, amplitude and shape as well as perform monitoring and calibration tasks. The ARS chip processes the analogue signals from the optical modules and converts information into digital data. All the information is transmitted to shore through further multiplexing electronics and an optical link. This paper describes the performance of the ARS chip; results from the functionality and characterization tests in the laboratory are summarized and the long-term performance in the apparatus is illustrated.

  20. Front-End-Electronics Communication software for multiple detectors in the ALICE experiment

    CERN Document Server

    Bablok, Sebastian; Hartung, G; Keidel, R; Kofler, C; Krawutschke, T; Lindenstruth, V; Röhrich, D

    2006-01-01

    In the ALICE experiment at CERN, the Detector Control System (DCS) employs several interacting software components to accomplish its task of ensuring the correct operation and monitoring of the experiment. This paper describes the Front-End-Electronics Communication (FeeCommunication) software and its role within the DCS. The FeeCommunication software's central task is passing configuration and monitoring data between the top level DCS process control and the field devices of several detectors within ALICE. The lowest level of the FeeCommunication software runs on the DCS boards, specialized embedded systems which are in direct contact with the field devices and are physically located within the detector. The middle and upper layers run on standard PC hardware located in the counting room or other external locations. This paper focuses on the design and implementation of the FeeCommunication software and the steps that were taken to fulfill the imposed reliability and performance requirements, specifically th...

  1. The front end electronics of the NA62 Gigatracker: challenges, design and experimental measurements

    Science.gov (United States)

    Noy, M.; Aglieri Rinella, G.; Ceccucci, A.; Dellacasa, G.; Fiorini, M.; Garbolino, S.; Jarron, P.; Kaplon, J.; Kluge, A.; Marchetto, F.; Martin, E.; Mazza, G.; Martoiu, S.; Morel, M.; Perktold, L.; Rivetti, A.; Tiuraniemi, S.

    2011-06-01

    The beam spectrometer of the NA62 experiment consists of 3 Gigatracker (GTK) stations. Each station comprises a pixel detector of 16 cm active area made of an assembly of 10 readout ASICs bump bonded to a 200 μm thick pixel silicon sensor, comprising 18000 pixels of 300 μm×300 μm. The main challenge of the NA62 pixel GTK station is the combination of an extremely high kaon/pion beam rate, where the intensity in the center of the beam reaches up to 1.5 Mhit s mm together with an extreme time resolution of 100 ps. To date, it is the first silicon tracking system with this time resolution. To face this challenge, the pixel analogue front end has been designed with a peaking time of 4 ns, with a planar silicon sensor operating up to 300 V over depletion. Moreover, the radiation level is severe, 2×10 1 MeV n cm per year of operation. Easy replacement of the GTK stations is foreseen as a design requirement. The amount of material of a single station should also be less than 0.5% X to minimize the background, which imposes strong constraints on the mechanics and the cooling system. We report upon the design and architecture of the 2 prototype demonstrator chips both designed in 130 nm CMOS technology, one with a constant fraction discriminator and the time stamp digitisation in each pixel (In-Pixel), and the other with a time-over-threshold discriminator and the processing of the time stamp located in the End of Column (EoC) region at the chip periphery. Some preliminary results are presented.

  2. The front-end electronics system for the CMS electromagnetic calorimeter

    CERN Document Server

    Pastrone, Nadia

    2004-01-01

    The CMS electromagnetic calorimeter at the CERN Large Hadron Collider (LHC) has been designed to measure the energy of electrons and photons with high resolution over a wide dynamic range, using lead tungstate scintillating crystals. To minimize external noise most of the readout chain must be placed within the detector in a high radiation environment, inside the 4 T magnetic field. To cope with these demanding constraints innovative solutions have been adopted since most of the common technologies are excluded. The basic architecture and the first prototype tests of the on-detector readout chain are described. (12 refs).

  3. Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

    International Nuclear Information System (INIS)

    Zeng, Huiming; Wei, Tingcun; Wang, Jia

    2017-01-01

    A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal–oxide–semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 µm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e − +16.3e − /pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

  4. Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

    Energy Technology Data Exchange (ETDEWEB)

    Zeng, Huiming; Wei, Tingcun, E-mail: weitc@nwpu.edu.cn; Wang, Jia

    2017-03-01

    A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal–oxide–semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 µm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e{sup −}+16.3e{sup −}/pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

  5. Architecture and Implementation of the Front-End Electronics of the Time Projection Chambers in the T2K Experiment

    Science.gov (United States)

    Baron, P.; Besin, D.; Calvet, D.; Coquelet, C.; De La Broise, X.; Delagnes, E.; Druillole, F.; Le Coguie, A.; Monmarthe, E.; Zonca, E.

    2010-04-01

    The tracker of the near detector in the T2K neutrino oscillation experiment comprises three time projection chambers based on micro-pattern gaseous detectors. A new readout system is being developed to amplify, condition and acquire in real time the data produced by the 124.000 detector channels. The cornerstone of the system is a 72-channel application specific integrated circuit which is based on a switched capacitor array. Using analog memories combined with deferred digitization enables reducing the initial burstiness of traffic from 50 Tbps to 400 Gbps in a practical manner and with a very low power budget. Modern field programmable gate arrays coupled to commercial digital memories are the next elements in the chain. Multi-gigabit optical links provide 140 Gbps of aggregate bandwidth to carry data outside of the magnet surrounding the detector to concentrator cards that pack data and provide the interface to commercial PCs via a standard Gigabit Ethernet network. We describe the requirements and constraints for this application and justify our technical choices. We detail the design and the performance of several key elements and show the deployment of the front-end electronics on the first time projection chamber where the final tests before installation on-site are being conducted.

  6. Development of pixel front-end electronics using advanced deep submicron CMOS technologies

    International Nuclear Information System (INIS)

    Havranek, Miroslav

    2014-09-01

    The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

  7. Reliability Analysis of a Low Voltage Power Supply Design for the Front-End Electronics of the Atlas Tile Calorimeter

    CERN Document Server

    Drake, G; The ATLAS collaboration; Gopalakrishnan, A; Mahadik, S; Mellado, B; Proudfoot, J

    2012-01-01

    –We present a reliability study on a new low voltage power supply design for the front-end electronics of the ATLAS Tile Calorimeter. Using the reliability data from the manufacturers of the components, we derive an estimate of the expected number of failures per year during the normal operating lifetime of the power supply bricks. This may be useful for other power supply designs or front-end electronics designs where high reliability is required. We discuss the factors in the design that limit reliability, and present conclusions for improvements to the power distribution system for the LHC Phase 2 upgrade.

  8. Reliability Analysis of a Low Voltage Power Supply Design for the Front-End Electronics of the ATLAS Tile Calorimeter

    CERN Document Server

    Senthilkumaran, A; The ATLAS collaboration; Gopalakrishnan, A; Mahadik, S; Drake, G; Proudfoot, J

    2012-01-01

    We present a reliability study on a new low voltage power supply design for the front-end electronics of the ATLAS Tile Calorimeter. Using the reliability data from the manufacturers of the components, we derive an estimate of the expected number of failures per year during the normal operating lifetime of the power supply bricks. We will illustrate the technique, which may be useful for other power supply designs or front-end electronics designs where high reliability is required. We discuss the factors in the design that limit reliability, and present our preliminary design work for improvements in the power distribution system for the LHC Phase 2 upgrade.

  9. Front-end receiver electronics for a matrix transducer for 3-D transesophageal echocardiography.

    Science.gov (United States)

    Yu, Zili; Blaak, Sandra; Chang, Zu-yao; Yao, Jiajian; Bosch, Johan G; Prins, Christian; Lancée, Charles T; de Jong, Nico; Pertijs, Michiel A P; Meijer, Gerard C M

    2012-07-01

    There is a clear clinical need for creating 3-D images of the heart. One promising technique is the use of transesophageal echocardiography (TEE). To enable 3-D TEE, we are developing a miniature ultrasound probe containing a matrix piezoelectric transducer with more than 2000 elements. Because a gastroscopic tube cannot accommodate the cables needed to connect all transducer elements directly to an imaging system, a major challenge is to locally reduce the number of channels, while maintaining a sufficient signal-to-noise ratio. This can be achieved by using front-end receiver electronics bonded to the transducers to provide appropriate signal conditioning in the tip of the probe. This paper presents the design of such electronics, realizing time-gain compensation (TGC) and micro-beamforming using simple, low-power circuits. Prototypes of TGC amplifiers and micro-beamforming cells have been fabricated in 0.35-μm CMOS technology. These prototype chips have been combined on a printed circuit board (PCB) to form an ultrasound-receiver system capable of reading and combining the signals of three transducer elements. Experimental results show that this design is a suitable candidate for 3-D TEE.

  10. Fast front-end L0 trigger electronics for ALICE FMD-MCP tests and performance

    CERN Document Server

    Efimov, L G; Kasatkan, V; Klempt, W; Kuts, V; Lenti, V; Platanov, V; Rudge, A; Stolyarov, O I; Tsimbal, F A; Valiev, F F; Villalobos Baillie, O; Vinogradov, L I; Zhigunov, O

    1997-01-01

    We present design details and new measurements of the performance of fast electronics for the Forward Multiplicity Detector for ALICE. These detectors based on sector type Microchannel Plates (MCP) forming several disks gave the very first trigger decision in the experiment (L0). Fast passive summators integrated with the detectors are used for linear summation of up to eight isochronous signal channels from MCP pads belonging to one sector. Two types of microelectronics design thin film summators were produced. We present test results for these summators, working in the frequency range up to 1 Ghz. New low noise preamplifiers have been built to work with these summators. The new design shows a good performance with the usable frequency range extended up to 1 Ghz. An upgrade of the functional scheme for the L0 ALICE pre-trigger design is also presented.Abstract:List of figures Figure 1: ALICE L0 Trigger Front-End Electronics Functional Scheme. Figure 2: UHF design for a fast passive summator based on direct...

  11. Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

    Science.gov (United States)

    Zeng, Huiming; Wei, Tingcun; Wang, Jia

    2017-03-01

    A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal-oxide-semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 μm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e-+16.3e-/pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

  12. Integration of 2D CMUT arrays with front-end electronics for volumetric ultrasound imaging.

    Science.gov (United States)

    Wygant, Ira O; Zhuang, Xuefeng; Yeh, David T; Oralkan, Omer; Sanli Ergun, A; Karaman, Mustafa; Khuri-Yakub, Butrus T

    2008-02-01

    For three-dimensional (3D) ultrasound imaging, connecting elements of a two-dimensional (2D) transducer array to the imaging system's front-end electronics is a challenge because of the large number of array elements and the small element size. To compactly connect the transducer array with electronics, we flip-chip bond a 2D 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array to a custom-designed integrated circuit (IC). Through-wafer interconnects are used to connect the CMUT elements on the top side of the array with flip-chip bond pads on the back side. The IC provides a 25-V pulser and a transimpedance preamplifier to each element of the array. For each of three characterized devices, the element yield is excellent (99 to 100% of the elements are functional). Center frequencies range from 2.6 MHz to 5.1 MHz. For pulse echo operation, the average - 6-dB fractional bandwidth is as high as 125%. Transmit pressures normalized to the face of the transducer are as high as 339 kPa and input-referred receiver noise is typically 1.2 to 2.1 mPa/pHz. The flip-chip bonded devices were used to acquire 3D synthetic aperture images of a wire-target phantom. Combining the transducer array and IC, as shown in this paper, allows for better utilization of large arrays, improves receive sensitivity, and may lead to new imaging techniques that depend on transducer arrays that are closely coupled to IC electronics.

  13. Front-end electronics for high rate, position sensitive neutron detectors

    CERN Document Server

    Yu, B; Harder, J A; Hrisoho, A; Radeka, V; Smith, G C

    2002-01-01

    Advanced neutron detectors for experiments at new spallation sources will require greater counting rate capabilities than previously attainable. This necessitates careful design of both detector and readout electronics. As part of a new instrument for protein crystallography at LANSCE, we are constructing a detector whose concept was described previously (IEEE Trans. Nucl. Sci. NS-46 (1999) 1916). Here, we describe the signal processing circuit, which is well suited for sup 3 He detectors with a continuous interpolating readout. The circuit is based on standard charge preamplification, transmission of this signal over 20 meters or so, followed by sample and hold using a second order gated baseline restorer. This latter unit provides high rate capability without requiring pole-zero and tail cancellation circuits. There is also provision for gain-adjustment. The circuits are produced in surface mounted technology.

  14. The DIALOG Chip in the Front-End Electronics of the LHCb Muon Detector

    CERN Document Server

    Cadeddu, S; Lai, A

    2004-01-01

    We present a custom integrated circuit, named DIALOG, which is a fundamental building block in the front-end architecture of the LHCb Muon detector. DIALOG is realized in IBM 0.25 um technology, using radiation hardening layout techniques. DIALOG integrates important tools for detector time alignment procedures and time alignment monitoring on the front- end system. In particular, it integrates 16 programmable delays, which can be regulated in steps of 1 ns. Many other features, necessary for the Muon trigger operation and for a safe front-end monitoring are integrated: DIALOG generates the information used by the trigger as a combination of its 16 inputs from the Amplifier-Shaper-Discriminator (ASD) chips, it generates the thresholds of the ASD, it monitors the rate of all its input channels. We describe the circuit architecture, its internal blocks and its main modes of operation.

  15. Hybrid circuit prototypes for the CMS Tracker upgrade front-end electronics

    International Nuclear Information System (INIS)

    Blanchot, G; Honma, A; Kovacs, M; Braga, D; Raymond, M

    2013-01-01

    New high-density interconnect hybrid circuits are under development for the CMS tracker modules at the HL-LHC. These hybrids will provide module connectivity between flip-chip front-end ASICs, strip sensors and a service board for the data transmission and powering. Rigid organic-based substrate prototypes and also a flexible hybrid design have been built, containing up to eight front-end flip chip ASICs. A description of the function of the hybrid circuit in the tracker, the first prototype designs, results of some electrical and mechanical properties from the prototypes, and examples of the integration of the hybrids into detector modules are presented

  16. Testing and commissioning of the LHCb Outer Tracker front-end electronic and a study for a background estimation in the decay B{sup 0}{sub s} {yields} J/{psi} {phi}; Tests und Inbetriebnahme der LHCb Outer Tracker Front-end Elektronik und eine Studie zur Abschaetzung des Untergrundes im Zerfall B{sup 0}{sub s} {yields} J/{psi} {phi}

    Energy Technology Data Exchange (ETDEWEB)

    Knopf, Jan

    2009-07-08

    The readout electronic of the LHCb outer tracker measures the drift time of a straw tube. The front-end electronic consists of three radiation hard chips. The ASDBLR preamplifier amplifies and discriminates the charge puls produced by the drift chamber. The OTIS-TDC chip measures the drift time every 25 ns on 32 detector channels. The generated data is send via an optical link with 1.6 GBit/s, making use of the GOL chip. The main part of this thesis is dedicated to the testing and commissioning of the outer tracker front-end electronic. Altogether three test systems were developed and operated. The first test system was built to thoroughly check the features of the OTIS-TDC chips on the wafer. The quality of the OTIS board and GOL-Aux board production was checked with another test system. The front-end electronic was also combined and tested to the LHCB readout chain. One of the main goals of the LHCb experiment is the measurement of the CP-violating phase {phi}{sub s}. It can be measured by using the golden decay mode B{sup 0}{sub s} {yields} J/{psi} {phi}. It is vital to have a good knowledge about the background for this decay in order to extract the phase. In this thesis a study was performed to overcome the current limitations due to low Monte-Carlo statistics in this area. (orig.)

  17. The front-end electronics of the LHCb ring-imaging-Cherenkov system

    International Nuclear Information System (INIS)

    Wyllie, K.

    2006-01-01

    The LHCb experiment at the CERN Large Hadron Collider will use ring-imaging Cherenkov detectors for particle identification. By measuring rings of Cherenkov photons generated by elementary particles traversing a radiative medium, these particles can be identified across a wide range of momenta. The photons will be measured by a new type of detector, the pixel hybrid photon detector (HPD). In total, 484 HPDs will be used, providing ∼500,000 channels of data. Specific readout electronics have been developed for processing the data from the HPDs, and this paper describes the design and testing of these devices together with the final system to be used in the experiment. Emphasis is on the application-specific integrated circuits that are encapsulated within the HPDs, allowing high channel density and low noise. These are subject to the strict requirements of efficient photon detection and reliability within the harsh environment of the experiment. Special interconnect techniques developed for this application are described. Finally, the additional electronics infrastructure to readout the full system of 500,000 channels is outlined, including data transmission and power distribution

  18. Performance of a 128 channel analogue front-end chip for read-out of Si strip detector modules for LHC experiments

    CERN Document Server

    Chesi, Enrico Guido; Cindro, V; Dabrowski, W; Ferrère, D; Kramberger, G; Kaplon, J; Lacasta, C; Lozano-Bahilo, J; Mikuz, M; Morone, C; Roe, S; Szczygiel, R; Tadel, M; Weilhammer, Peter; Zsenei, A

    2000-01-01

    We present a 128-channel analogue front-end chip, SCT128A-HC, for readout of silicon strip detectors employed in the inner tracking detectors of the LHC experiment. The chip is produced in the radiation hard DMILL technology. The architecture of the chip and critical design issues are discussed. The performance of the chip has been evaluated in details in the test bench and is presented in the paper. The chip is used to read out prototype analogue modules compatible in size, functionality and performance with the ATLAS SCT base line modules. Several full size detector modules equipped with SCT128A-HC chips has been built and tested successfully in the lab with beta particles as well as in the test beam. The results concerning the signal-to-noise ratio, noise occupancy, efficiency and spatial resolution are presented. The radiation hardness issues are discussed. (5 refs).

  19. FELIX: The New Approach for Interfacing to Front-end Electronics for the ATLAS Experiment

    CERN Document Server

    AUTHOR|(SzGeCERN)754725; The ATLAS collaboration; Anderson, John Thomas; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Guest, Daniel; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Zhang, Jinlong

    2016-01-01

    From the ATLAS Phase-I upgrade and onward, new or upgraded detectors and trigger systems will be interfaced to the data acquisition, detector control and timing (TTC) systems by the Front-End Link eXchange (FELIX). FELIX is the core of the new ATLAS Trigger/DAQ architecture. Functioning as a router between custom serial links and a commodity network, FELIX is implemented by server PCs with commodity network interfaces and PCIe cards with large FPGAs and many high speed serial fiber transceivers. By separating data transport from data manipulation, the latter can be done by software in commodity servers attached to the network. Replacing traditional point-to-point links between Front-end components and the DAQ system by a switched network, FELIX provides scaling, flexibility uniformity and upgradability and reduces the diversity of custom hardware solutions in favour of software.

  20. A compact front-end electronics module for the SDC strawtube outer tracker

    International Nuclear Information System (INIS)

    Emery, M.S.; Alley, G.T.; Leitch, R.M.; Maples, R.A.; Holmes, W.

    1993-01-01

    The challenges of building a detector for the Superconducting Super Collider have been talked about for the last several years. Those challenges are proving to be real and in some cases tougher than expected as prototype subsystem and component development continues within the different collaborations. Not to be daunted, engineers and scientists are using ingenuity and novel designs to meet the challenges. One such area has been in the development of the outer tracker readout electronics for the Solenoidal Detector Collaboration (SDC) detector. The tracker has over 100,000 channels and is composed of strawtubes that are 4 mm in diameter and 4 meters long. The sheer number of channels and small-diameter tubes require a very high density packaging scheme with critical attendant concerns, including power consumption, cooling, and crosstalk. This paper describes the novel approach taken to solve some of these challenges

  1. Super-Altro 16: a Front-End System on Chip for DSP Based Readout of Gaseous Detectors

    CERN Document Server

    Aspell, P.; Franca, H.; Garcia Garcia, E.; Musa, L.

    2013-01-01

    This paper presents the architecture, design and test results of an ASIC specifically designed for the readout of gaseous detectors. The primary application is the readout of the Linear Collider Time Projection Chamber. The small area available (4mm2/channel) requires an innovative design, where sensitive analog components and massive digital functionalities are integrated on the same chip. Moreover, shut down (power pulsing) features are necessary in order to reduce the power consumption. The Super-Altro is a 16-channel demonstrator ASIC involving analog and digital signal processing. Each channel contains a low noise Pre-Amplifier and Shaping Amplifier (PASA), a pipeline ADC, and a Digital Signal Processor (DSP). The PASA is programmable in terms of gain and shaping time and can operate with both positive and negative polarities of input charge. The 10-bit ADC samples the output of the PASA at a frequency up to 40MHz before providing the digitized signal to the DSP which performs baseline subtraction, signa...

  2. Architecture of PAU survey camera readout electronics

    Science.gov (United States)

    Castilla, Javier; Cardiel-Sas, Laia; De Vicente, Juan; Illa, Joseph; Jimenez, Jorge; Maiorino, Marino; Martinez, Gustavo

    2012-07-01

    PAUCam is a new camera for studying the physics of the accelerating universe. The camera will consist of eighteen 2Kx4K HPK CCDs: sixteen for science and two for guiding. The camera will be installed at the prime focus of the WHT (William Herschel Telescope). In this contribution, the architecture of the readout electronics system is presented. Back- End and Front-End electronics are described. Back-End consists of clock, bias and video processing boards, mounted on Monsoon crates. The Front-End is based on patch panel boards. These boards are plugged outside the camera feed-through panel for signal distribution. Inside the camera, individual preamplifier boards plus kapton cable completes the path to connect to each CCD. The overall signal distribution and grounding scheme is shown in this paper.

  3. Development of an analogue optical link for the front-end read-out of the ATLAS electromagnetic calorimeter

    CERN Document Server

    Dinkespiler, B; Olivetto, C; Martin, O; Mirea, A; Monnier, E; Tisserant, S; Wielers, M; Andrieux, M L; Ballon, J; Collot, J; Patti, A; Eek, L O; Go, A; Lund-Jensen, B; Pearce, M; Söderqvist, J; Coulon, J P

    1999-01-01

    We have developed an analogue optical data transmission system intended to meet the read-out requirements of the ATLAS liquid argon electromagnetic calorimeter. Eight-way demonstrators have been built and tested. The link uses arrays of VCSEL diodes as the optical emitters, coupled to a 70 m long fibre ribbon to simulate the distance between the detector and the control room. The receiver is based around a custom-designed PIN photodiode array. We describe here the final results of laboratory tests on a demonstrator, laying stress on the VCSEL-to-fibre coupling issues, and the overall performance of the full link. A 9-bit dynamic range is achieved, with a 5on-linearity.

  4. Characterization of silicon microstrip sensors, front-end electronics, and prototype tracking detectors for the CBM experiment at FAIR

    International Nuclear Information System (INIS)

    Sorokin, Iurii

    2013-01-01

    The Compressed Baryonic Matter (CBM) experiment will explore the phase diagram of strongly interacting matter in the region of high net baryonic densities. The matter at the extreme conditions will be studied in collisions of a heavy ion beam with a fixed heavy element target. The present work is devoted to the development of the main component of the CBM experiment - the Silicon Tracking System (STS). The STS has to enable reconstruction of up to 1000 charged particle tracks per nucleus-nucleus interaction at the rate of up to 10 MHz, provide a momentum resolution Δp/p of 1 %, and withstand the radiation load of up to 10 14 n eq /cm 2 (n eq -neutron equivalent). The STS will be based on double-sided silicon microstrip sensors, that will be arranged in 8 planes in the aperture of the dipole magnet. Selftriggering readout electronics will be located on the periphery of the detecting planes, and connected to the sensors with low mass microcables. In the stage of R and D, as well as in the stages of pre-series and series production, characterization of the sensors, of the front-end electronics, and of the complete detector modules has to be performed. In the present work the required techniques were developed, and the performance of the latest detector prototypes was evaluated. A particular attention is paid to evaluation of the signal amplitude, as it is one of the most important detector characteristics. Techniques for measuring the passive electrical characteristics of the sensors were developed. These include: the coupling and the interstrip capacitances, the interstrip resistance, the bias resistance, the strip leakage current, the bulk capacitance, and the bulk leakage current. The techniques will be applied for the quality assurance of the sensors during the pre-series and the series production. Extensive characterization of the prototype readout chip, n-XYTER, was performed. The register settings were optimized, and the dependence of the amplitude response on

  5. Characterization of silicon microstrip sensors, front-end electronics, and prototype tracking detectors for the CBM experiment at FAIR

    Energy Technology Data Exchange (ETDEWEB)

    Sorokin, Iurii

    2013-07-01

    The Compressed Baryonic Matter (CBM) experiment will explore the phase diagram of strongly interacting matter in the region of high net baryonic densities. The matter at the extreme conditions will be studied in collisions of a heavy ion beam with a fixed heavy element target. The present work is devoted to the development of the main component of the CBM experiment - the Silicon Tracking System (STS). The STS has to enable reconstruction of up to 1000 charged particle tracks per nucleus-nucleus interaction at the rate of up to 10 MHz, provide a momentum resolution Δp/p of 1 %, and withstand the radiation load of up to 10{sup 14} n{sub eq}/cm{sup 2} (n{sub eq}-neutron equivalent). The STS will be based on double-sided silicon microstrip sensors, that will be arranged in 8 planes in the aperture of the dipole magnet. Selftriggering readout electronics will be located on the periphery of the detecting planes, and connected to the sensors with low mass microcables. In the stage of R and D, as well as in the stages of pre-series and series production, characterization of the sensors, of the front-end electronics, and of the complete detector modules has to be performed. In the present work the required techniques were developed, and the performance of the latest detector prototypes was evaluated. A particular attention is paid to evaluation of the signal amplitude, as it is one of the most important detector characteristics. Techniques for measuring the passive electrical characteristics of the sensors were developed. These include: the coupling and the interstrip capacitances, the interstrip resistance, the bias resistance, the strip leakage current, the bulk capacitance, and the bulk leakage current. The techniques will be applied for the quality assurance of the sensors during the pre-series and the series production. Extensive characterization of the prototype readout chip, n-XYTER, was performed. The register settings were optimized, and the dependence of the

  6. The TDCpix readout ASIC: A 75ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    CERN Document Server

    Kluge, A; Bonacini, S; Jarron, P; Kaplon, J; Morel, M; Noy, M; Perktold, L; Poltorak, K

    2013-01-01

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak fl ow of particles crossing the detector modules reaches 1.27 MHz/mm 2 for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection ef fi ciency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45 40 square pixels of 300 300 μ m 2 and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low...

  7. First test results from the Front-End Board with Cyclone V as a test high-resolution platform for the Auger-Beyond-2015 Front End Electronics

    International Nuclear Information System (INIS)

    Szadkowski, Zbigniew

    2015-01-01

    The paper presents the first results from the Front- End Board (FEB) with the biggest Cyclone R V E FPGA 5CEFA9F31I7N, supporting 8 channels sampled up to 250 MSps at 14-bit resolution. Considered sampling for the SD is 120 MSps, however, the FEB has been developed with external anti-aliasing filters to keep a maximal flexibility. Six channels are targeted to the SD, two the rest for other experiments like: Auger Engineering Radio Array and additional muon counters. More channels and higher sampling generate larger size of registered events. We used the standard radio channel for a radio transmission from the detectors to the Central Data Acquisition Station (CDAS) to avoid at present a significant modification of a software in both sides: the detector and the CDAS (planned in a future for a final design). Seven FEBs have been deployed in the test detectors on a dedicated Engineering Array in a hexagon. Several variants of the FPGA code were tested for 120, 160, 200 and even 240 MSps DAQ. Tests confirmed a stability and reliability of the FEB design in real pampas conditions with more than 40 deg. C daily temperature variation and a strong sun exposition with a limited power budget only from a single solar panel. (authors)

  8. Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

    CERN Document Server

    Garcia-Argos, Carlos; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment is currently preparing for an upgrade of the tracking system in the course of the High Luminosity LHC, scheduled for 2024. The existing Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) with a pixel detector surrounded by a strip detector. The ITk strip detector consists of a four layer barrel and a forward region composed of six discs on each side of the barrel. The basic unit of the detector is the silicon-strip module, consisting of a sensor and one or more hybrid circuits that hold the read-out electronics. The geometries of the barrel and end-cap modules take into account the regions that they have to cover. In the central region, the detectors are rectangular with straight strips, whereas on the forward region the modules require wedge shaped sensors with varying strip length and pitch. The current prototyping phase has resulted in the ITk Strip Detector Technical Design Report (TDR), which kicks-off the pre-production readiness phase at the involved institutes. ...

  9. Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

    CERN Document Server

    Garcia-Argos, Carlos; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment is currently preparing for an upgrade of the tracking system in the course of the High Luminosity LHC, scheduled for 2024. The existing Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) with a pixel detector surrounded by a strip detector. The ITk strip detector consists of a four layer barrel and a forward region composed of six discs on each side of the barrel. The basic unit of the detector is the silicon-strip module, consisting of a sensor and one or more hybrid circuits that hold the read-out electronics. The geometries of the barrel and end-cap modules take into account the regions that they have to cover. In the central region, the detectors are rectangular with straight strips, whereas in the forward region the modules require wedge shaped sensors with varying strip length and pitch. The current prototyping phase has resulted in the ITk Strip Detector Technical Design Report (TDR), which kicks-off the pre-production readiness phase at the involved institutes. ...

  10. The TDCpix Readout ASIC: A 75 ps Resolution Timing Front-End for the Gigatrackerof theNA62 Experiment

    Science.gov (United States)

    Rinella, G. Aglieri; Fiorini, M.; Jarron, P.; Kaplon, J.; Kluge, A.; Martin, E.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    NA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at measuring ultra rare kaon decays. The Gigatracker (GTK) detector shall combine on-beam tracking of individual particles with a time resolution of 150 ps rms. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm2 fora total rateof about 0.75 GHz.Ahybrid siliconpixel detectoris beingdevelopedto meet these requirements. The pixel chip for the Gigatracker (TDCpix) is under design. The TDCpix chip will feature 1800 square pixels of 300×300 μm2 arranged in a matrix of 45 rows × 40 columns. Bump-bonded to a silicon pixel sensor it shall perform time stamping of particle hits with a timing accuracybetter than 200 ps rms and a detection efficiencyabove 99%. The chosen architecture provides full separation of the sensitive analog amplifiers of the pixel matrix from the noisy digital circuits of the TDCs and of the readout blocks. Discriminated hit signals from each pixel are transmitted to the end of column region. An array ofTime to Digital Converters (TDC) is implemented at the bottom of the pixel array. The TDCs are based on time tagging the events with the fine time codes generated by Delay Locked Loops (DLL) and have a nominal time bin of ˜100 ps. Time stamps and time-over-threshold are recorded for each discriminated hit and the correction of the discriminator's time-walk is performed off-detector. Data are continuously transmitted on four 2.4 Gb/s serial output links. Adescription of the on-going design of the final TDCpix is given in this paper. Design choices and some technical implementation details are presented. Aprototype ASIC including thekeycomponents of this architecture has been manufactured. The achievement of specification figures such as a time resolution of the processing chain of 75 ps rms as well as charged particle time stampingwitha resolutionbetterthan200psrmswere demonstratedexperimentally.Asummaryoftheseresultsisalso presented in

  11. Search for Supersymmetric Top-Quark Partners Using Support Vector Machines and Upgrade of the Hadron Calorimeter Front-End Readout Control System at CMS

    CERN Document Server

    Sahin, Mehmet Ozgur; Schleper, Peter

    2017-01-01

    In this thesis a search for direct pair production of supersymmetric top-quark partners aswell as work on the upgrade of the front-end readout controller of the Hadron Calorimeter(HCAL) of the Compact Muon Solenoid (CMS) experiment are presented.The most appealing extension of the Standard Model (SM) is supersymmetry (SUSY), relating the integer spin (bosons) and half-integer spin elementary particles (fermions). Supersymmetric top-quark partners (t) around and below the TeV energy scale offer a solution to thehierarchy problem. Furthermore, R-parity conserving SUSY models propose a cold dark matter candidate in the form of stable lightest supersymmetric particles, e.g. lightest neutralinos(χ0 ).The analysis performed in this thesis is a search for top-squark pair production in a final state consisting of a single isolated lepton, jets, among which at least one is tagged asbottom-quark jet, and large missing transverse energy at the CMS experiment at the CERNLarge Hadron Collider (LHC) with 8 TeV center-of-...

  12. Design of a New Switching Power Supply for the ATLAS TileCAL Front-End Electronics

    CERN Document Server

    Drake, G; The ATLAS collaboration

    2012-01-01

    We present the design of an upgraded switching power supply for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and improved reliability, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the steps taken to improve the design. We present the results from extensive radiation testing to qualify the design, including SEU sensitivity. We also present our reliability analysis. Production of 2400 new bricks for the detector is currently in progress, and we present preliminary results from the production checkout.

  13. Design of a New Switching Power Supply for the ATLAS TileCal Front-End Electronics

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2012-01-01

    We present the design of an upgraded switching power supply for the front-end electronics of the ATLAS Hadron Tile Calorimeter. The new design features significant improvement in noise, improved fault detection, and improved reliability, while retaining the compact size, water-cooling, output control, and monitoring features. We discuss the steps taken to improve the design. We present the results from extensive radiation testing to qualify the design, including SEU sensitivity. We also present our reliability analysis. Production of 2400 new bricks for the detector is in progress, and we present preliminary results from the production checkout.

  14. Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

    International Nuclear Information System (INIS)

    Carrió, F; Valero, A; Kim, H Y; Usai, G; Moreno, P; Reed, R; Sandrock, C; Schettino, V; Souza, J; Shalyugin, A; Solans, C

    2014-01-01

    The portable test-bench for the certification of the ATLAS tile hadronic calorimeter front-end electronics has been redesigned for the present Long Shutdown (LS1) of LHC, improving its portability and expanding its functionalities. This paper presents a new test-bench based on a Xilinx Virtex-5 FPGA that implements an embedded system using a PowerPC 440 microprocessor hard core and custom IP cores. A light Linux version runs on the PowerPC microprocessor and handles the IP cores which implement the different functionalities needed to perform the desired tests such as TTCvi emulation, G-Link decoding, ADC control and data reception

  15. Production and performance of LHCb triple-GEM detectors equipped with the dedicated CARDIAC-GEM front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Alfonsi, M. [Laboratori Nazionali di Frascati - INFN (Italy)]. E-mail: matteo.alfonsi@lnf.infn.it; Bencivenni, G. [Laboratori Nazionali di Frascati - INFN (Italy); Bonivento, W. [Sezione INFN di Cagliari (Italy); Cardelli, E. [Sezione INFN di Cagliari (Italy); Cardini, A. [Sezione INFN di Cagliari (Italy); De Simone, P. [Laboratori Nazionali di Frascati - INFN (Italy); Domenici, D. [Laboratori Nazionali di Frascati - INFN (Italy); Murtas, F. [Laboratori Nazionali di Frascati - INFN (Italy); Pinci, D. [Sezione INFN di Roma 1 (Italy); Poli Lener, M. [Laboratori Nazionali di Frascati - INFN (Italy); Raspino, D. [Sezione INFN di Cagliari (Italy); Saitta, B. [Sezione INFN di Cagliari (Italy)

    2007-03-01

    The production of the triple-GEM detectors for the innermost region of the first muon station of the LHCb experiment has started in February 2006, and is foreseen to be completed by the end of July. The final design of the detector and the construction procedure and tools, as well as the quality controls are defined. The performances of each detector, composed by two triple-GEM chambers equipped with dedicated CARDIAC-GEM front-end electronics, are studied with a cosmic ray telescope. The cosmic ray telescope has been set up including all the final off-detector components.

  16. Silicon photomultipliers: On ground characterizations and modelling for use in front-end electronics aimed to space-borne experiments

    Energy Technology Data Exchange (ETDEWEB)

    Badoni, Davide [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy)]. E-mail: davide.badoni@roma2.infn.it; Altamura, Francesco [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Basili, Alessandro [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Bencardino, Raffaele [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Bidoli, Vittorio [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Casolino, Marco [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); De Carli, Anna [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Froysland, Tom [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Marchetti, Marcello [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Messi, Roberto [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Minori, Mauro [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Picozza, Piergiorgio [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Salina, Gaetano [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Galper, Arkady [Moscow Engineering and Physics Institute (Russian Federation); Korotkov, Mikhail [Moscow Engineering and Physics Institute (Russian Federation); Popov, Alexander [Moscow Engineering and Physics Institute (Russian Federation)

    2007-03-01

    Silicon Photomultipliers (Si-PM) consist of an array of semiconductor photodiodes joint on the common substrate and operating in limited geiger mode. A new generation of Si-PM is currently under test in INFN Rome Tor Vergata facilities: they consist of a 5625 element, 3*3mm{sup 2} array with an improved light response. These elements have been characterized. Furthermore, a functional model of the Si-PM has been developed to be used in a VLSI development of front-end electronics.

  17. Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

    CERN Document Server

    Carrio, F; The ATLAS collaboration; Moreno, P; Reed, R; Sandrock, C; Shalyugin, A; Schettino, V; Solans, C; Souza, J; Usai, G; Valero, A

    2013-01-01

    The portable test bench (VME based) used for the certification of the Tile calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (2013-2014) improving its portability. The new version is based on a Xilinx Virtex 5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. The PowerPC microprocessor runs a light Linux version and handles the IP cores written in VHDL that implement the different functionalities (TTC, G-Link, CAN-Bus) Description of the system and performance measurements of the different components will be shown.

  18. Testing and commissioning of the LHCb Outer Tracker front-end electronic and a study for a background estimation in the decay B0s → J/ψ Φ

    International Nuclear Information System (INIS)

    Knopf, Jan

    2009-01-01

    The readout electronic of the LHCb outer tracker measures the drift time of a straw tube. The front-end electronic consists of three radiation hard chips. The ASDBLR preamplifier amplifies and discriminates the charge puls produced by the drift chamber. The OTIS-TDC chip measures the drift time every 25 ns on 32 detector channels. The generated data is send via an optical link with 1.6 GBit/s, making use of the GOL chip. The main part of this thesis is dedicated to the testing and commissioning of the outer tracker front-end electronic. Altogether three test systems were developed and operated. The first test system was built to thoroughly check the features of the OTIS-TDC chips on the wafer. The quality of the OTIS board and GOL-Aux board production was checked with another test system. The front-end electronic was also combined and tested to the LHCB readout chain. One of the main goals of the LHCb experiment is the measurement of the CP-violating phase Φ s . It can be measured by using the golden decay mode B 0 s → J/ψ Φ. It is vital to have a good knowledge about the background for this decay in order to extract the phase. In this thesis a study was performed to overcome the current limitations due to low Monte-Carlo statistics in this area. (orig.)

  19. The CBM Experiment at FAIR-New challenges for Front-End Electronics, Data Acquisition and Trigger Systems

    International Nuclear Information System (INIS)

    Mueller, Walter F J

    2006-01-01

    The 'Compressed Baryonic Matter' (CBM) experiment at the new 'Facility for Antiproton and Ion Research' (FAIR) in Darmstadt is designed to study the properties of highly compressed baryonic matter produced in nucleus-nucleus collisions in the 10 to 45 A GeV energy range. One of the key observables is hidden (J/ψ) and open (D 0 , D ± ) charm production. To achieve an adequate sensitivity extremely high interaction rates of up to 10 7 events/second are required, resulting in major technological challenges for the detectors, front-end electronics and data processing. The front-end electronics will be self-triggered, autonomously detect particle hits, and output hit parameter together with a precise absolute time-stamp. Several layers of feature extraction and event selection will reduce the primary data flow of about 1 TByte/sec to a level of 1 GByte/sec. This new architecture avoids many limitations of conventional DAQ/Trigger systems and is for example essential for open charm detection, which requires the reconstruction of displaced vertices, in a high-rate heavy ion environment

  20. Development of the control system of the ALICE transition radiation detector and of a test environment for quality-assurance of its front-end electronics

    International Nuclear Information System (INIS)

    Mercado Perez, Jorge

    2008-01-01

    Within this thesis, the detector control system (DCS) for the Transition Radiation Detector (TRD) of the ALICE experiment at the Large Hadron Collider has been developed. The TRD DCS is fully implemented as a detector oriented hierarchy of objects behaving as finite state machines. It controls and monitors over 65 thousand front-end electronics (FEE) units, a few hundred low voltage and one thousand high voltage channels, and other sub-systems such as cooling and gas. Commissioning of the TRD DCS took place during several runs with ALICE using cosmic events. Another part of this thesis describes the development of a test environment for large-scale production quality-assurance of over 4 thousand FEE read-out boards containing in total about 1.2 million read-out channels. The hardware and software components are described in detail. Additionally, a series of performance studies were carried out earlier including radiation tolerance tests of the TRAP chip which is the core component of the TRD FEE. (orig.)

  1. Development of the control system of the ALICE Transition Radiation Detector and of a test environment for quality-assurance of its front-end electronics

    CERN Document Server

    Mercado Pérez, Jorge

    2008-01-01

    Within this thesis, the detector control system (DCS) for the Transition Radiation Detector (TRD) of the ALICE experiment at the Large Hadron Collider has been developed. The TRD DCS is fully implemented as a detector oriented hierarchy of objects behaving as finite state machines. It controls and monitors over 65 thousand front-end electronics (FEE) units, a few hundred low voltage and one thousand high voltage channels, and other sub-systems such as cooling and gas. Commissioning of the TRD DCS took place during several runs with ALICE using cosmic events. Another part of this thesis describes the development of a test environment for large-scale production quality-assurance of over 4 thousand FEE read-out boards containing in total about 1.2 million read-out channels. The hardware and software components are described in detail. Additionally, a series of performance studies were carried out earlier including radiation tolerance tests of the TRAP chip which is the core component of the TRD FEE.

  2. Development of the control system of the ALICE transition radiation detector and of a test environment for quality-assurance of its front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Mercado Perez, Jorge

    2008-11-10

    Within this thesis, the detector control system (DCS) for the Transition Radiation Detector (TRD) of the ALICE experiment at the Large Hadron Collider has been developed. The TRD DCS is fully implemented as a detector oriented hierarchy of objects behaving as finite state machines. It controls and monitors over 65 thousand front-end electronics (FEE) units, a few hundred low voltage and one thousand high voltage channels, and other sub-systems such as cooling and gas. Commissioning of the TRD DCS took place during several runs with ALICE using cosmic events. Another part of this thesis describes the development of a test environment for large-scale production quality-assurance of over 4 thousand FEE read-out boards containing in total about 1.2 million read-out channels. The hardware and software components are described in detail. Additionally, a series of performance studies were carried out earlier including radiation tolerance tests of the TRAP chip which is the core component of the TRD FEE. (orig.)

  3. Evaluation of the PANDA silicon pixel front-end electronics and investigation of the anti ΛΛ final state

    Energy Technology Data Exchange (ETDEWEB)

    Esch, Simone

    2014-04-28

    high precision particle beams for several experiments. The AntiProton Annihilation at Darmstadt (PANDA) experiment is one of the large detectors at FAIR. PANDAs main physics objectives center around the properties of particles and excited particles made from quarks of the first and second quark family. It is a fixed target experiment within the High Energy Storage Ring (HESR), which delivers an intense, phase-space cooled antiproton beam in the momentum range of 1.5 to 15 GeV/c. With the high precision of the HESR, PANDA will be able to perform precise spectroscopic studies of hadronic states in the charm quark mass range. The luminosity will be up to 2.10{sup 32} cm{sup -2}s{sup -1}, thus enabling very rare processes to be studied. This high luminosity leads to a high particle flux and a high radiation environment which the sub-detectors must withstand. The most highly affected sub-detector of this high radiation environment is the Micro Vertex Detector (MVD), the innermost detector of PANDA. The main task of the MVD is the detection of the interaction points of events (vertexing). This vertex finding is crucial for the analysis of short living particles like e.g. D-mesons, particles consisting of a c-quark and a light antiquark. An essential part of the MVD detector is the readout of the semiconductor sensors. The ToPix (Torino Pixel) Application Specific Integrated Circuit (ASIC) is the front-end electronics for the MVD sensor, developed at the Istituto Nazionale di Fisica Nucleare (INFN) in Turin, Italy. It measures the spatial coordinate, the time and the deposited charge of incident charged particles. The most recent prototype of this ASIC is the ToPix 3, a version of reduced size and functionality. The Juelich Digital Readout System (JDRS) was adopted and extended to be able to readout this prototype, thus enabling specific test measurements of the prototype. In addition, the performance of PANDA for detecting long lived. particles was studied, and the

  4. LHCb: The Front-End electronics for the LHCb scintillating fibres detector

    CERN Multimedia

    Chanal, H; Pillet, N

    2014-01-01

    The LHCb detector will be upgraded during the next LHC shutdown in 2018/19. The tracker system will have a major overhaul. Its components will be replaced with new technologies in order to cope with the increased hit occupancy and radiation environment. A detector made of scintillating fibres read out by silicon photomultipliers (SiPM) is studied for this upgrade. Even if this technology has proven to achieve high efficiency and spatial resolution, its integration within a LHC experiment bears new challenges. This detector will consist of 12 planes of 5 to 6 layers of 250 $\\mu$m fibres with an area of 5×6 m$^2$. Its lead to a total of 500k SiPM channels which need to will be read out at 40MHz. This talk gives an overview of the R&D status of the readout board and the PACIFIC chip. The readout board is connected to the SiPM on one side and to the experiment data-acquisition, experimental control system and services on the other side . The PACIFIC chip is a 128 channel ASIC which can be connected to one 12...

  5. The Front-End electronics for the LHCb scintillating fibres detector

    CERN Document Server

    Chanal, Hervé; Pillet, Nicolas

    2014-01-01

    The LHCb detector will be upgraded during the next LHC shutdown in 2018/19 [ 1 ]. The tracker system will have a major overhaul. Its components will be replaced with new technologies in order to cope with the increased hit occupancy and radiation environment. A detector made of scintillating fibres read out by silicon photomultipliers (SiPM) is studied for this upgrade. Even if this technology has proven to achieve high efficiency and spatial resolution, its integration within a LHC experiment bears new challenges. This detector will consist of 12 planes of 5 to 6 layers of 250 m m fibres with an area of 5 6 m 2 . It leads to a total of 500k SiPM channels which need to be read out at 40 MHz. This article gives an overview of the R&D; status of the readout board and the PACIFIC chip. The readout board is connected to the SiPM on one side and to the experiment data-acquisition, experimental control system and services on the other side. The PACIFIC chip is a 128-channels ASIC which can be connected to one 1...

  6. Design and construction of the front-end electronics data acquisition for the SLD CRID [Cherenkov Ring Imaging Detector

    International Nuclear Information System (INIS)

    Hoeflich, J.; McShurley, D.; Marshall, D.; Oxoby, G.; Shapiro, S.; Stiles, P.; Spencer, E.

    1990-10-01

    We describe the front-end electronics for the Cherenkov Ring Imaging Detector (CRID) of the SLD at the Stanford Linear Accelerator Center. The design philosophy and implementation are discussed with emphasis on the low-noise hybrid amplifiers, signal processing and data acquisition electronics. The system receives signals from a highly efficient single-photo electron detector. These signals are shaped and amplified before being stored in an analog memory and processed by a digitizing system. The data from several ADCs are multiplexed and transmitted via fiber optics to the SLD FASTBUS system. We highlight the technologies used, as well as the space, power dissipation, and environmental constraints imposed on the system. 16 refs., 10 figs

  7. Considerations on the design of front-end electronics for silicon calorimetry for the SSC [Superconducting Super Collider

    International Nuclear Information System (INIS)

    Wintenberg, A.L.; Bauer, M.L.; Britton, C.L. Jr.; Kennedy, E.J.; Todd, R.A.; Berridge, S.C.; Bugg, W.M.

    1990-01-01

    Some considerations are described for the design of a silicon-based sampling calorimetry detector for the Superconducting Super Collider (SSC). The use of silicon as the detection medium allows fast, accurate, and fine-grained energy measurements -- but for optimal performance, the front-end electronics must be matched to the detector characteristics and have the speed required by the high SSC interaction rates. The relation between the signal-to-noise ratio of the calorimeter electronics and the charge collection time, the preamplifier power dissipation, detector capacitance and leakage, charge gain, and signal shaping and sampling was studied. The electrostatic transformer connection was analyzed and found to be unusable for a tightly arranged calorimeter because of stray capacitance effects. The method of deconvolutional sampling was developed as a means for pileup correction following synchronous sampling and analog storage. 3 refs., 6 figs

  8. The digital ASIC for the digital front end electronics of the SPI astrophysics gamma-ray experiment

    International Nuclear Information System (INIS)

    Lafond, E.; Mur, M.; Schanne, S.

    1998-01-01

    The SPI spectrometer is one of the gamma-ray astronomy instruments that will be installed on the ESA INTEGRAL satellite, intended to be launched in 2001 by the European Space Agency. The Digital Front-End Electronics sub-system (DFEE) is in charge of the real time data processing of the various measurements produced by the Germanium (Ge) detectors and the Bismuth Germanate (BGO) anti-coincidence shield. The central processing unit of the DFEE is implemented in a digital ASIC circuit, which provides the real time association of the various time signals, acquires the associated energy measurements, and classifies the various types of physics events. The paper gives the system constraints of the DFEE, the architecture of the ASIC circuit, the technology requirements, and the strategy for test and integration. Emphasis is given to the high level language development and simulation, the automatic circuit synthesis approach, and the performance estimation

  9. A wide dynamic range BF{sub 3} neutron monitor with front-end electronics based on a logarithmic amplifier

    Energy Technology Data Exchange (ETDEWEB)

    Ferrarini, M., E-mail: michele.ferrarini@polimi.i [Politecnico di Milano, Dipartimento Energia, via G. Ponzio 34/3, I-20133 Milano (Italy); Fondazione CNAO, via Caminadella 16, 20123 Milano (Italy); Varoli, V. [Politecnico di Milano, Dipartimento Energia, via G. Ponzio 34/3, I-20133 Milano (Italy); Favalli, A. [European Commission, Joint Research Centre, Institute for the Protection and Security of Citizen, TP 800, Via E. Fermi, 21027 Ispra (Vatican City State, Holy See) (Italy); Caresana, M. [Politecnico di Milano, Dipartimento Energia, via G. Ponzio 34/3, I-20133 Milano (Italy); Pedersen, B. [European Commission, Joint Research Centre, Institute for the Protection and Security of Citizen, TP 800, Via E. Fermi, 21027 Ispra (Italy)

    2010-02-01

    This paper describes a wide dynamic range neutron monitor based on a BF{sub 3} neutron detector. The detector is used in current mode, and front-end electronics based on a logarithmic amplifier are used in order to have a measurement capability ranging over many orders of magnitude. The system has been calibrated at the Polytechnic of Milan, CESNEF, with an AmBe neutron source, and has been tested in a pulsed field at the PUNITA facility at JRC, Ispra. The detector has achieved a dynamic range of over 6 orders of magnitude, being able to measure single neutron pulses and showing saturation-free response for a reaction rate up to 10{sup 6} s{sup -1}. It has also proved effective in measuring the PUNITA facility pulse integral fluence.

  10. The OPERA RPCs front end electronics; a novel application of LVDS line receiver as low cost discriminator

    International Nuclear Information System (INIS)

    Balsamo, E; Bergnoli, A; Bertolin, A; Brugnera, R; Carrara, E; Ciesielski, R; Dal Corso, F; Dusini, S; Garfagnini, A; Kose, U; Longhin, A; Medinaceli, E; Stanco, L

    2012-01-01

    The OPERA spectrometer is built from two large dipoles instrumented with around 1000 Resistive Plate Chambers (RPCs), covering a surface of about 3350 m 2 , and digitally read out by means of almost 27000 strips. The huge number of channels, the inaccessibility of many parts of the detector and the wide uncertainty about the signal amplitude pushed to study a low cost, high sensitivity discriminator, and a very carefully designed layout for the read out system. Here we will present a novel application of LVDS line receiver as discriminator, showing that it exceeds the requirements of a large RPC based detector and offers the intrinsic advantages of a mature technology in terms of costs, reliability and integration scale. We will also present the layout of the read out system showing as the sensitivity and the noise immunity were preserved in a system where the front end electronics is far away from the detector.

  11. The OPERA RPCs front end electronics; a novel application of LVDS line receiver as low cost discriminator

    Science.gov (United States)

    Balsamo, E.; Bergnoli, A.; Bertolin, A.; Brugnera, R.; Carrara, E.; Ciesielski, R.; Dal Corso, F.; Dusini, S.; Garfagnini, A.; Kose, U.; Longhin, A.; Medinaceli, E.; Stanco, L.

    2012-11-01

    The OPERA spectrometer is built from two large dipoles instrumented with around 1000 Resistive Plate Chambers (RPCs), covering a surface of about 3350 m2, and digitally read out by means of almost 27000 strips. The huge number of channels, the inaccessibility of many parts of the detector and the wide uncertainty about the signal amplitude pushed to study a low cost, high sensitivity discriminator, and a very carefully designed layout for the read out system. Here we will present a novel application of LVDS line receiver as discriminator, showing that it exceeds the requirements of a large RPC based detector and offers the intrinsic advantages of a mature technology in terms of costs, reliability and integration scale. We will also present the layout of the read out system showing as the sensitivity and the noise immunity were preserved in a system where the front end electronics is far away from the detector.

  12. The Development of High-Performance Front-End Electronics Based Upon the QIE12 Custom ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2016-01-01

    We present the design of a new candidate front-end electronic readout system being developed for the ATLAS TileCal Phase 2 Upgrade. The system is based upon the QIE12 custom Application Specific Integrated Circuit. The chip features a least count sensitivity of 1.5 fC, more than 17 bits of dynamic range with logarithmic response, and an on-chip TDC with one nanosecond resolution. The design incorporates an on-board current integrator, and has several calibration systems. The new electronics will operate dead-timelessly at 40 MHz, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room using high-speed optical links. The system is one of three candidate systems for the Phase 2 Upgrade. We have built a “Demonstrator” – a fully functional prototype of the new system. Performance results from bench measurements and from a recent test beam campaign will be presented.

  13. Challenges of front-end and triggering electronics for High Granularity Calorimetry

    CERN Document Server

    Puljak, Ivica

    2017-01-01

    A high granularity calorimeter is presently being designed by the CMS Collaboration to replace the existing endcap detectors. It must be able to cope with the very high collision rates, imposing the development of novel filtering and triggering strategies, as well as with the harsh radiation environment of the high-luminosity LHC. In this paper we present an overview of the full electronics architecture and the performance of prototype components and algorithms.

  14. LHCb Scintillating Fiber detector front end electronics design and quality assurance

    Science.gov (United States)

    Vink, W. E. W.; Pellegrino, A.; Ietswaard, G. C. M.; Verkooijen, J. C.; Carneiro, U.; Massefferi, A.

    2017-03-01

    The on-detector electronics of the LHCb Scintillating Fiber Detector consists of multiple PCBs assembled in a unit called Read Out Box, capable of reading out 2048 channels with an output rate of 70 Gbps. There are three types of boards: PACIFIC, Clusterization and Master Board. The Pacific Boards host PACIFIC ASICs, with pre-amplifier and comparator stages producing two bits of data per channel. A cluster-finding algorithm is then run in an FPGA on the Clusterization Board. The Master Board distributes fast and slow control, and power. We describe the design, production and test of prototype PCBs.

  15. Triggering, front-end electronics, and data acquisition for high-rate beauty experiments

    International Nuclear Information System (INIS)

    Johnson, M.; Lankford, A.J.

    1988-04-01

    The working group explored the feasibility of building a trigger and an electronics data acquisition system for both collider and fixed target experiments. There appears to be no fundamental technical limitation arising from either the rate or the amount of data for a collider experiment. The fixed target experiments will likely require a much higher rate because of the smaller cross section. Rates up to one event per RF bucket (50 MHz) appear to be feasible. Higher rates depend on the details of the particular experiment and trigger. Several ideas were presented on multiplicity jump and impact parameter triggers for fixed target experiments. 14 refs., 3 figs

  16. Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

    Science.gov (United States)

    Gurun, Gokce; Hasler, Paul; Degertekin, F

    2011-08-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

  17. Acoustic backing in 3-D integration of CMUT with front-end electronics.

    Science.gov (United States)

    Berg, Sigrid; Rønnekleiv, Arne

    2012-07-01

    Capacitive micromachined ultrasonic transducers (CMUTs) have shown promising qualities for medical imaging. However, there are still some problems to be investigated, and some challenges to overcome. Acoustic backing is necessary to prevent SAWs excited in the surface of the silicon substrate from affecting the transmit pattern from the array. In addition, echoes resulting from bulk waves in the substrate must be removed. There is growing interest in integrating electronic circuits to do some of the beamforming directly below the transducer array. This may be easier to achieve for CMUTs than for traditional piezoelectric transducers. We will present simulations showing that the thickness of the silicon substrate and thicknesses and acoustic properties of the bonding material must be considered, especially when designing highfrequency transducers. Through simulations, we compare the acoustic properties of 3-D stacks bonded with three different bonding techniques; solid-liquid interdiffusion (SLID) bonding, direct fusion bonding, and anisotropic conductive adhesives (ACA). We look at a CMUT array with a center frequency of 30 MHz and three silicon wafers underneath, having a total silicon thickness of 100 μm. We find that fusion bonding is most beneficial if we want to prevent surface waves from damaging the array response, but SLID and ACA are also promising if bonding layer thicknesses can be reduced.

  18. Tissue Banking, Bioinformatics, and Electronic Medical Records: The Front-End Requirements for Personalized Medicine

    Science.gov (United States)

    Suh, K. Stephen; Sarojini, Sreeja; Youssif, Maher; Nalley, Kip; Milinovikj, Natasha; Elloumi, Fathi; Russell, Steven; Pecora, Andrew; Schecter, Elyssa; Goy, Andre

    2013-01-01

    Personalized medicine promises patient-tailored treatments that enhance patient care and decrease overall treatment costs by focusing on genetics and “-omics” data obtained from patient biospecimens and records to guide therapy choices that generate good clinical outcomes. The approach relies on diagnostic and prognostic use of novel biomarkers discovered through combinations of tissue banking, bioinformatics, and electronic medical records (EMRs). The analytical power of bioinformatic platforms combined with patient clinical data from EMRs can reveal potential biomarkers and clinical phenotypes that allow researchers to develop experimental strategies using selected patient biospecimens stored in tissue banks. For cancer, high-quality biospecimens collected at diagnosis, first relapse, and various treatment stages provide crucial resources for study designs. To enlarge biospecimen collections, patient education regarding the value of specimen donation is vital. One approach for increasing consent is to offer publically available illustrations and game-like engagements demonstrating how wider sample availability facilitates development of novel therapies. The critical value of tissue bank samples, bioinformatics, and EMR in the early stages of the biomarker discovery process for personalized medicine is often overlooked. The data obtained also require cross-disciplinary collaborations to translate experimental results into clinical practice and diagnostic and prognostic use in personalized medicine. PMID:23818899

  19. Readout electronic for multichannel detectors

    CERN Document Server

    Kulibaba, V I; Naumov, S V

    2001-01-01

    Readout electronics based on the 128-channel chip 'Viking' (IDE AS inc., Norway) is considered. The chip 'Viking' integrates 128 low noise charge-sensitive preamplifiers with tunable CR-(RC) sup 2 shapers,analog memory and multiplexed readout to one output. All modules of readout electronics were designed and produced in KIPT taking into account the published recommendations of IDE AS inc.

  20. Simulation study of n-XYTER front-end electronics in overflow situations for early prototyping of detectors in the CBM experiment

    Energy Technology Data Exchange (ETDEWEB)

    Balog, Tomas [GSI Darmstadt (Germany); Collaboration: CBM-Collaboration

    2011-07-01

    In high-rate experiments a situation can occur in which the data rate temporarily exceeds the available bandwidth. With self-triggered front end electronics such overload situations would lead, without further measures, to uncontrolled data losses and potentially large number of incomplete events. Mechanisms needed to control data losses and to ensure complete events can be understood using simulations performed by the hardware description language SystemC. Simulations of a simplified n-XYTER based front-end electronics are presented that give first insight in the behaviour of data flow and data losses in the DAQ system of the CBM experiment.

  1. The front-end electronics for the 1.8-kchannel SiPM tracking plane in the NEW detector

    International Nuclear Information System (INIS)

    Rodríguez, J.; Lorca, D.; Monrabal, F.; Toledo, J.; Esteve, R.

    2015-01-01

    NEW is the first phase of NEXT-100 experiment, an experiment aimed at searching for neutrinoless double-beta decay. NEXT technology combines an excellent energy resolution with tracking capabilities thanks to a combination of optical sensors, PMTs for the energy measurement and SiPMs for topology reconstruction. Those two tools result in one of the highest background rejection potentials in the field. This work describes the tracking plane that will be constructed for the NEW detector which consists of close to 1800 sensors with a 1-cm pitch arranged in twenty-eight 64-SiPM boards. Then it focuses in the development of the electronics needed to read the 1800 channels with a front-end board that includes per-channel differential transimpedance input amplifier, gated integrator, automatic offset voltage compensation and 12-bit ADC. Finally, a description of how the FPGA buffers data, carries out zero suppression and sends data to the DAQ interface using CERN RD-51 SRS's DTCC link specification complements the description of the electronics of the NEW detector tracking plane

  2. Front-end data processing the SLD data acquisition system

    International Nuclear Information System (INIS)

    Nielsen, B.S.

    1986-07-01

    The data acquisition system for the SLD detector will make extensive use of parallel at the front-end level. Fastbus acquisition modules are being built with powerful processing capabilities for calibration, data reduction and further pre-processing of the large amount of analog data handled by each module. This paper describes the read-out electronics chain and data pre-processing system adapted for most of the detector channels, exemplified by the central drift chamber waveform digitization and processing system

  3. The PHENIX Drift Chamber Front End Electroncs

    Science.gov (United States)

    Pancake, C.; Velkovska, J.; Pantuev, V.; Fong, D.; Hemmick, T.

    1998-04-01

    The PHENIX Drift Chamber (DC) is designed to operate in the high particle flux environment of the Relativistic Heavy Ion Collider and provide high resolution track measurements. It is segmented into 80 keystones with 160 readout channels each. The Front End Electronics (FEE) developed to meet the demanding operating conditions and the large number of readout channels of the DC will be discussed. It is based on two application specific integrated circuits: the ASD8 and the TMC-PHX1. The ASD8 chip contains 8 channels of bipolar amplifier-shaper-discriminator with 6 ns shaping time and ≈ 20 ns pulse width, which satisfies the two track resolution requirements. The TMC-PHX1 chip is a high-resolution multi-hit Time-to-Digital Converter. The outputs from the ASD8 are digitized in the Time Memory Cell (TMC) every (clock period)/32 or 0.78 ns (at 40 MHz), which gives the intrinsic time resolution of the system. A 256 words deep dual port memory keeps 6.4 μs time history of data at 40 MHz clock. Each DC keystone is supplied with 4 ASD8/TMC boards and one FEM board, which performs the readout of the TMC-PHX1's, buffers and formats the data to be transmitted over the Glink. The slow speed control communication between the FEM and the system is carried out over ARCNET. The full readout chain and the data aquisition system are being tested.

  4. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS upgrade framework

    CERN Document Server

    Schreuder, Frans Philip; The ATLAS collaboration

    2018-01-01

    Starting during the upcoming major LHC shutdown (2019-2021), the ATLAS experiment at CERN will move to the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX will function as a router between custom serial links and a commodity switch network, which will use industry standard technologies to communicate with data collection and processing components. This presentation will describe the FELIX system design as well as reporting on results of the ongoing development program.

  5. Status on the development of front-end and readout electronics for ...

    Indian Academy of Sciences (India)

    CMOS 0.13 µm is under investigations. Table 1. Overall noise contributions at 30 pF detector capacitance and 3 µs shaping time. Source. Value. Noise 0.18 µm CMOS. Input stage (measured) gm = 0.7 mA/V. 615 e− (measured) m Detector leak. 10 nA. 588 e− (from literature). Biasing resistor. 10 MΩ. 423 (thermal noise).

  6. Status on the development of front-end and readout electronics for ...

    Indian Academy of Sciences (India)

    These technologies allow also to implement efficient data extraction and signal processing techniques such as analog sampling and on-chip digitization. For detectors that covers of the order of 100 square meters and millions of channels, the multiplexing of several tasks such as analog-to-digital conversion and zero sup-.

  7. Super conductor Supercollider front end electronics development; ring imaging Cerenkov studies; and warm liquid calorimetry. Final report

    International Nuclear Information System (INIS)

    1998-01-01

    The University of Pennsylvania group that was involved in SDC was responsible, jointly with the KEK Laboratory in Japan, for the design and production of the readout electronics for the SDC straw tube tracker (a $12 million electronics effort). Their responsibilities included major contributions to the overall conceptual design, oversight of all the contributions from North America and direct responsibility for the HV/ASD assembly, the amplifier-shaper-discriminator chip, and HV distribution on the detector (the responsibility for the latter being shared with Colorado)

  8. A protocol for hit and control synchronous transfer for the front-end electronics at the CBM experiment

    International Nuclear Information System (INIS)

    Kasinski, K.; Szczygiel, R.; Zabolotny, W.; Lehnert, J.; Schmidt, C.J.; Müller, W.F.J.

    2016-01-01

    The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.

  9. A protocol for hit and control synchronous transfer for the front-end electronics at the CBM experiment

    Energy Technology Data Exchange (ETDEWEB)

    Kasinski, K., E-mail: kasinski@agh.edu.pl [AGH University of Science and Technology, Department of Measurement and Electronics, Av. Mickiewicza 30, 30-059 Cracow (Poland); Szczygiel, R. [AGH University of Science and Technology, Department of Measurement and Electronics, Av. Mickiewicza 30, 30-059 Cracow (Poland); Zabolotny, W. [Institute of Electronic Systems, Warsaw University of Technology, ul. Nowowiejska 15/19, 00-665 Warsaw (Poland); Lehnert, J.; Schmidt, C.J. [GSI Helmholtzzentrum für Schwerionenforschung GmbH, Planckstrasse 1, 64-291 Darmstadt (Germany); Müller, W.F.J. [FAIR Facility for Antiproton and Ion Research in Europe GmbH, Planckstrasse 1, 64-291 Darmstadt (Germany)

    2016-11-01

    The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.

  10. A custom readout electronics for the BESIII CGEM detector

    Science.gov (United States)

    Da Rocha Rolo, M.; Alexeev, M.; Amoroso, A.; Baldini Ferroli, R.; Bertani, M.; Bettoni, D.; Bianchi, F.; Bugalho, R.; Calcaterra, A.; Canale, N.; Capodiferro, M.; Carassiti, V.; Cerioni, S.; Chai, J. Y.; Chiozzi, S.; Cibinetto, G.; Cossio, F.; Cotta Ramusino, A.; De Mori, F.; Destefanis, M.; Di Francesco, A.; Dong, J.; Evangelisti, F.; Farinelli, R.; Fava, L.; Felici, G.; Fioravanti, E.; Garzia, I.; Gatta, M.; Greco, M.; Lavezzi, L.; Leng, C. Y.; Li, H.; Maggiora, M.; Malaguti, R.; Marcello, S.; Marciniewski, P.; Melchiorri, M.; Mezzadri, G.; Mignone, M.; Morello, G.; Pacetti, S.; Patteri, P.; Pellegrino, J.; Pelosi, A.; Rivetti, A.; Savrié, M.; Scodeggio, M.; Soldani, E.; Sosio, S.; Spataro, S.; Tskhadadze, E.; Varela, J.; Verma, S.; Wheadon, R.; Yan, L.

    2017-07-01

    For the upgrade of the inner tracker of the BESIII spectrometer, planned for 2018, a lightweight tracker based on an innovative Cylindrical Gas Electron Multiplier (CGEM) detector is now under development. The analogue readout of the CGEM enables the use of a charge centroid algorithm to improve the spatial resolution to better than 130 μm while loosening the pitch strip to 650 μm, which allows to reduce the total number of channels to about 10 000. The channels are readout by 160 dedicated integrated 64-channel front-end ASICs, providing a time and charge measurement and featuring a fully-digital output. The energy measurement is extracted either from the time-over-threshold (ToT) or the 10-bit digitisation of the peak amplitude of the signal. The time of the event is generated by quad-buffered low-power TDCs, allowing for rates in excess of 60 kHz per channel. The TDCs are based on analogue interpolation techniques and produce a time stamp (or two, if working in ToT mode) of the event with a time resolution better than 50 ps. The front-end noise, based on a CSA and a two-stage complex conjugated pole shapers, dominate the channel intrinsic time jitter, which is less than 5 ns r.m.s. The time information of the hit can be used to reconstruct the track path, operating the detector as a small TPC and hence improving the position resolution when the distribution of the cloud, due to large incident angle or magnetic field, is very broad. Event data is collected by an off-detector motherboard, where each GEM-ROC readout card handles 4 ASIC carrier FEBs (512 channels). Configuration upload and data readout between the off-detector electronics and the VME-based data collector cards are managed by bi-directional fibre optical links. This paper covers the design of a custom front-end electronics for the readout of the new inner tracker of the BESIII experiment, addressing the relevant design aspects of the detector electronics and the front-end ASIC for the CGEM readout

  11. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00015561; Bauer, Kevin Thomas; Borga, Andrea; Boterenbrood, Henk; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Guest, Daniel; Gorini, Benedetto; Joos, Markus; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Panduro Vazquez, William; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Whiteson, Daniel; Wu, Weihao; Zhang, Jinlong

    2016-01-01

    The ATLAS Phase-I upgrade (2018) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

  12. Upgrade of the ALICE-TPC read-out electronics

    CERN Document Server

    Junique, A; Musa , L; Rehman , A U

    2010-01-01

    The ALICE experiment at CERN LHC employs a large volume time projection chamber (TPC) as its main tracking device. Instigated by analyses indicating that the high level trigger is capable of sifting events with rare physics probes, it is endeavoured to read out the TPC an order of magnitude faster then was reckoned during the design of its read-out electronics. Based on an analysis of the read-out performance of the current system, an upgrade of the front-end read-out network is proposed. The performance of the foreseen architecture is simulated with raw data from real 7 TeV pp collisions. Events are superimposed in order to emulate the future ALICE running conditions: high multiplicity events generated either by PbPb collisions or by the superposition (pile-up) of a large number of pp collisions. The first prototype of the main building block has been produced and characterised, demonstrating the feasibility of the approach

  13. Upgrade of the ALICE-TPC read-out electronics

    Energy Technology Data Exchange (ETDEWEB)

    Junique, A; Mager, M; Musa, L; Rehman, A Ur, E-mail: Magnus.Mager@cern.ch [CERN, Geneva (Switzerland)

    2010-12-15

    The ALICE experiment at CERN LHC employs a large volume time projection chamber (TPC) as its main tracking device. Instigated by analyses indicating that the high level trigger is capable of sifting events with rare physics probes, it is endeavoured to read out the TPC an order of magnitude faster then was reckoned during the design of its read-out electronics. Based on an analysis of the read-out performance of the current system, an upgrade of the front-end read-out network is proposed. The performance of the foreseen architecture is simulated with raw data from real 7 TeV pp collisions. Events are superimposed in order to emulate the future ALICE running conditions: high multiplicity events generated either by PbPb collisions or by the superposition (pile-up) of a large number of pp collisions. The first prototype of the main building block has been produced and characterised, demonstrating the feasibility of the approach.

  14. The STAR Heavy Flavor Tracker PXL detector readout electronics

    International Nuclear Information System (INIS)

    Schambach, J.; Contin, G.; Greiner, L.; Stezelberger, T.; Vu, C.; Sun, X.; Szelezniak, M.

    2016-01-01

    The Heavy Flavor Tracker (HFT) is a recently installed micro-vertex detector upgrade to the STAR experiment at RHIC, consisting of three subsystems with various technologies of silicon sensors arranged in 4 concentric cylinders. The two innermost layers of the HFT close to the beam pipe, the Pixel ('PXL') subsystem, employ CMOS Monolithic Active Pixel Sensor (MAPS) technology that integrate the sensor, front-end electronics, and zero-suppression circuitry in one silicon die. This paper presents selected characteristics of the PXL detector part of the HFT and the hardware, firmware and software associated with the readout system for this detector

  15. Optimization of DC-DC Converters for Improved Electromagnetic Compatibility With High Energy Physics Front-End Electronics

    CERN Document Server

    Fuentes, C; Michelis, S; Blanchot, G; Allongue, B; Faccio, F; Orlandi, S; Kayal, M; Pontt, J

    2011-01-01

    The upgrade of the Large Hadron Collider (LHC) experiments at CERN sets new challenges for the powering of the detectors. One of the powering schemes under study is based on DC-DC buck converters mounted on the front-end modules. The hard environmental conditions impose strict restrictions to the converters in terms of low volume, radiation and magnetic field tolerance. Furthermore, the noise emission of the switching converters must not affect the performance of the powered systems. A study of the sources and paths of noise of a synchronous buck converter has been made for identifying the critical parameters to reduce their emissions. As proof of principle, a converter was designed following the PCB layout considerations proposed and then used for powering a silicon strip module prototype for the ATLAS upgrade, in order to evaluate their compatibility.

  16. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS upgrade framework

    CERN Document Server

    Chen, Kai; The ATLAS collaboration

    2016-01-01

    The ATLAS Phase-I upgrade requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The FELIX system provides this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, routing between custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, and a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favor of software on commercial servers. The FELIX system, results of demonstrator, design and testing of prototype are described.

  17. Front End Spectroscopy ASIC for Germanium Detectors

    Science.gov (United States)

    Wulf, Eric

    Large-area, tracking, semiconductor detectors with excellent spatial and spectral resolution enable exciting new access to soft (0.2-5 MeV) gamma-ray astrophysics. The improvements from semiconductor tracking detectors come with the burden of high density of strips and/or pixels that require high-density, low-power, spectroscopy quality readout electronics. CMOS ASIC technologies are a natural fit to this requirement and have led to high-quality readout systems for all current semiconducting tracking detectors except for germanium detectors. The Compton Spectrometer and Imager (COSI), formerly NCT, at University of California Berkeley and the Gamma-Ray Imager/Polarimeter for Solar flares (GRIPS) at Goddard Space Flight Center utilize germanium cross-strip detectors and are on the forefront of NASA's Compton telescope research with funded missions of long duration balloon flights. The development of a readout ASIC for germanium detectors would allow COSI to replace their discrete electronics readout and would enable the proposed Gamma-Ray Explorer (GRX) mission utilizing germanium strip-detectors. We propose a 3-year program to develop and test a germanium readout ASIC to TRL 5 and to integrate the ASIC readout onto a COSI detector allowing a TRL 6 demonstration for the following COSI balloon flight. Our group at NRL led a program, sponsored by another government agency, to produce and integrate a cross-strip silicon detector ASIC, designed and fabricated by Dr. De Geronimo at Brookhaven National Laboratory. The ASIC was designed to handle the large (>30 pF) capacitance of three 10 cm^2 detectors daisy-chained together. The front-end preamplifier, selectable inverter, shaping times, and gains make this ASIC compatible with a germanium cross-strip detector as well. We therefore have the opportunity and expertise to leverage the previous investment in the silicon ASIC for a new mission. A germanium strip detector ASIC will also require precise timing of the signals at

  18. Gossipo-3 A prototype of a Front-End Pixel Chip for Read-Out of Micro-Pattern Gas Detectors

    CERN Document Server

    Brezina, Christpoh; van der Graaf, Haryy; Gromov, Vladimir; Kluit, Ruud; Kruth, Andre; Zappon, Francesco

    2009-01-01

    In a joint effort of Nikhef (Amsterdam) and the University of Bonn, the Gossipo-3 integrated circuit (IC) has been developed. This circuit is a prototype of a chip dedicated for read-out of various types of position sensitive Micro-Pattern Gas detectors (MPGD). The Gossipo-3 is defined as a set of building blocks to be used in a future highly granulated (60 μm) chip. The pixel circuit can operate in two modes. In Time mode every readout pixel measures the hit arrival time and the charge deposit. For this purpose it has been equipped with a high resolution TDC (1.7 ns) covering dynamic range up to 102 μs. Charge collected by the pixel will be measured using Time-over- Threshold method in the range from 400 e- to 28000 e- with accuracy of 200 e- (standard deviation). In Counting mode every pixel operates as a 24-bit counter, counting the number of incoming hits. The circuit is also optimized to operate at low power consumption (100 mW/cm2) that is required to avoid the need for massive power transport and coo...

  19. The control system for the CMS tracker front-end

    CERN Document Server

    Drouhin, F; Ljuslin, C; Maazouzi, C; Marchiero, A; Marinelli, N; Paillard, C; Siegrist, P; Tsirou, A L; Verdini, P G; Walsham, P; Zghiche, A

    2002-01-01

    The CMS Tracker uses complex, programmable embedded electronics for the readout of the Silicon sensors, for the control of the working point of the optical transmitters, for the phase adjustment of the 40 MHz LHC clock and for the monitoring of the voltages, currents and temperatures. In order to establish reliable, noise-free communication with the outside world the control chain has been designed to operate over a ribbon of optical fibers. The optical links, the Front End Controller board that carries their support electronics, the Clocking and Control Unit module receiving the signals over the high-speed link and fanning them out to the front- ends have recently become available. A multi-layered software architecture to handle these devices, and the front-ends, in a way transparent to the end-user, interfaced to an Oracle database for the retrieval of the parameters to be downloaded with the intent of building and operating a small-scale prototype of the control system for the CMS Tracker. The paper descri...

  20. Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays

    OpenAIRE

    Çiçek, İhsan; Cicek, Ihsan; Bozkurt, Ayhan; Karaman, Mustafa

    2005-01-01

    Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMU...

  1. A new front-end 100 MHz time-to-digital electronics to study extensive air shower

    International Nuclear Information System (INIS)

    Bezboruah, T.; Boruah, K.; Boruah, P.K.

    2001-01-01

    A new 100 MHz time to digital electronics (time digitizer) is described. The time digitizer is characterized by a 10 nS time-resolution and low-power consumption. The simple design and low cost make it preferable for use in Extensive Air Showers (EAS) experiment. A description of the operation and tests of the time digitizer is presented. This electronics is used in an EAS experiment in Guwahati University to study UHE Cosmic Rays by Mini Array Method (Assam, India) (Bezboruah et al., Astro. part. phys. 11(3) (1999) 395). We present here the results of the time digitizer and the performances of it in this experiment

  2. A Modular Active Front-End Rectifier with Electronic Phase-Shifting for Harmonic Mitigation in Motor Drive Applications

    DEFF Research Database (Denmark)

    Zare, Firuz; Davari, Pooya; Blaabjerg, Frede

    2017-01-01

    In this paper, an electronic phase-shifting strategy has been optimized for a multi-parallel configuration of line-commutated rectifiers with a common dc-bus voltage used in motor drive application. This feature makes the performance of the system independent of the load profile and maximizes its...... harmonic reduction ability. In order to further reduce the generated low order harmonics, a dc-link current modulation scheme and its phase shift values of multi-drive systems have been optimized. Analysis, simulations and experiments have been carried out to verify the proposed method....

  3. UWB front-end for SAR-based imaging system

    NARCIS (Netherlands)

    Monni, S.; Grooters, R.; Neto, A.; Nennie, F.A.

    2010-01-01

    A planarly fed UWB leaky lens antenna is presented integrated with wide band transmit and receive front-end electronics, to be used in a SAR-based imaging system. The unique non-dispersive characteristics of this antenna over a very wide bandwidth, together with the dual band front-end electronics

  4. Performance of a resistive plate chamber equipped with a new prototype of amplified front-end electronics

    CERN Document Server

    Marchisone, Massimiliano

    2016-01-01

    ALICE is the LHC experiment dedicated to the study of heavy-ion collisions. At forward rapidity a muon spectrometer detects muons from low mass mesons, quarkonia, open heavy-flavor hadrons as well as weak bosons. A muon selection based on transverse momentum is made by a trigger system composed of 72 resistive plate chambers (RPCs). For the LHC Run 1 and the ongoing Run 2 the RPCs have been equipped with a non-amplified FEE called ADULT. However, in view of an increase in luminosity expected for Run 3 (2021-2023) the possibility to use an amplified FEE has been explored in order to improve the counting rate limitation and to prevent the aging of the detector, by reducing the charge per hit. A prototype of this new electronics (FEERIC) has been developed and tested first with cosmic rays before equipping one RPC in the ALICE cavern with it. In this talk the most important performance indicators - efficiency, dark current, dark rate, cluster size and total charge - of an RPC equipped with this new FEE will be r...

  5. Study of the violation of the T and CP symmetries in the reactions Λb0 → Λ0 + a vector meson. Validation of the Front-end electronics for the PreShower detector of the LHCb experiment

    International Nuclear Information System (INIS)

    Conte, E.

    2007-11-01

    This thesis probes the beauty baryon physics in the framework of the LHCb experiment. The present study deals with the Λ b 0 → Λ 0 V decays where V is a vector meson such as J/Ψ(μ + μ - ), φ(K + K - ), ω(π + π - π0) or the ρ 0 - ω 0 (π + π - ) mixing. These processes allow to test independently the CP symmetry, which violation has not been observed yet in the baryonic sector, and the T symmetry, which experimental proofs are limited. Among the possible perspectives, a precise measurement of the Λ b 0 lifetime could contribute to the resolution of the raising theoretical-experimental puzzle. A phenomenological model of the Λ b 0 → Λ 0 V decays has been performed, from which branching ratios and angular distributions have been estimated. An advanced study of the reconstruction and the selection of these reactions by the LHCb apparatus shows that the channel Λ b 0 → Λ 0 J/Ψ is the dominant channel on both statistics and purity aspects. The Λ b 0 lifetime measure is the most imminent result; the constrains on asymmetries due to CP and T violation require several data taking years. Besides, an instrumental work has been achieved on the read-out electronics, called Front-End, of the experiment pre-shower. This contribution takes into account the validation of the prototype boards and the development of tools required by the qualification of the 100 production boards. (author)

  6. A generic firmware core to drive the Front-End GBT-SCAs for the LHCb ugprade

    CERN Document Server

    Alessio, F; Gaspar, C; Jacobsson, R; Wyllie, K

    2014-01-01

    The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well.

  7. LHCb : A generic firmware core to drive the Front-End GBT-SCAs for the LHCb ugprade

    CERN Multimedia

    Alessio, Federico; Gaspar, Clara; Jacobsson, Richard; Wyllie, Ken

    2014-01-01

    The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well

  8. Performance of a resistive plate chamber equipped with a new prototype of amplified front-end electronics in the ALICE detector

    Science.gov (United States)

    Marchisone, Massimiliano

    2017-09-01

    ALICE is the LHC experiment dedicated to the study of heavy-ion collisions. At forward rapidity a muon spectrometer detects muons from low mass mesons, quarkonia (c\\bar{c} and b\\bar{b} mesons), open heavy-flavor hadrons (D and B mesons) as well as from weak bosons. A muon selection based on transverse momentum is made by a trigger system composed of 72 Resistive Plate Chambers (RPCs). For the LHC Run 1 and the ongoing Run 2 the RPCs have been equipped with a non-amplified Front-End Electronics (FEE) called ADULT. However, in view of an increase in luminosity expected for Run 3 (foreseen to start in 2021) the possibility to use an amplified FEE has been explored in order to improve the counting rate limitation and to prevent the aging of the detector by reducing the charge per hit. A prototype of this new electronics (FEERIC) has been developed and tested first with cosmic rays before equipping one RPC in the ALICE cavern with it. In this proceeding the most important performance indicators (such as efficiency, dark current, dark rate, cluster size, total charge and charge per hit) of the RPC equipped with this new FEE will be reviewed and compared to the others read out with ADULT.

  9. The hybrid front end PCBs production for the CMS preshower

    CERN Document Server

    Soukoulias, P

    2009-01-01

    The High Energy Physics Detector CMS (Compact Muon Solenoid),installed at the Large Hadron Collider(LHC) at CERN,Geneva,has been built by an International Collaboration;CMS will measure and identify the particles from proton-proton collisions.One of the CMS component is the Preshower sub-detector,comprising 5000 silicon strip sensors connected to Hybrid Front End Boards for the readout.This paper focuses on an in-kind contibution of Greece.This work was carried out by researches,engineers and managers from a medium size Company,Prisma Electronics,located in Alexandropolis and researchers from CERN in Geneva,Demokritos in Athens and the University of Ioannina.The number of pieces fitting the technical specifications was close to 100%.Because of that,in March 2009,Prisma received as recognition a CERN CMS gold award.

  10. Qualification method for a 1 MGy-tolerant front-end chip designed in 65 nm CMOS for the read-out of remotely operated sensors and actuators during maintenance in ITER

    Energy Technology Data Exchange (ETDEWEB)

    Verbeeck, Jens, E-mail: jens.verbeeck@esat.kuleuven.be [KU Leuven (KUL), Div. LRD-MAGyICS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); Cao, Ying [KU Leuven (KUL), Div. LRD-MAGyICS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); Van Uffelen, Marco; Casellas, Laura Mont; Damiani, Carlo; Morales, Emilio Ruiz; Santana, Roberto Ranz [Fusion for Energy (F4E), c/Josep, no. 2, Torres Diagonal Litoral, Ed. B3, 08019 Barcelona (Spain); Meek, Richard; Haist, Bernhard [Oxford Technologies Ltd. (OTL), 7 Nuffield Way, Abingdon OX14 1RL (United Kingdom); Hamilton, David [ITER Organisation (IO), Route de Vinon-sur-Verdon, CS 90 046, 13067 St. Paul les Durance Cedex (France); Steyaert, Michiel [KU Leuven, ESAT-MICAS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); Leroux, Paul [KU Leuven, ESAT-MICAS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); KU Leuven, ESAT, Advanced Integrated Sensing Lab (AdvISe), Kleinhoefstraat 4, 2440 Geel (Belgium)

    2015-10-15

    This paper describes the radiation qualification procedure for a 1 MGy-tolerant Application Specific Integrated Circuit (ASIC) developed in 65 nm CMOS technology. The chip is intended for the read-out of electrical signals of sensors and actuators during maintenance in ITER. First the general working principle of the ASIC is shown. The developed IC allows to read-out, condition and digitize multiple low bandwidth (<10 kHz) sensors. In addition the IC is able to multiplex the digitized sensor signals. To comply with ITER-relevant constraints an adapted radiation qualification procedure has been proposed. The radiation-qualification procedure describes the test criteria and test conditions of the developed ASICs, which are also compared with COTS alternatives, to meet the stringent qualification procedures for electronics exposed to radiation in ITER.

  11. The new version of the LHCb SOL40-SCA core to drive front-end GBT-SCAs for the LHCb upgrade

    CERN Document Server

    Viana Barbosa, Joao Vitor; Gaspar, Clara

    2018-01-01

    The LHCb experiment is currently engaged in an upgrade effort that will implement a triggerless 40 MHz readout system. The upgraded Front-End Electronics profit from the GBT chipset functionalities and bidirectional optical fibers for readout, control and synchronization. This paper describes the new version of the firmware core that transmits slow control information from the Control System to thousands of Front-End chips and discusses the implementation that expedites and makes the operation more versatile. The detailed architecture, original interaction with the software control system and integration within the LHCb upgraded architecture are described.

  12. AFEII Analog Front End Board Design Specifications

    Energy Technology Data Exchange (ETDEWEB)

    Rubinov, Paul; /Fermilab

    2005-04-01

    This document describes the design of the 2nd iteration of the Analog Front End Board (AFEII), which has the function of receiving charge signals from the Central Fiber Tracker (CFT) and providing digital hit pattern and charge amplitude information from those charge signals. This second iteration is intended to address limitations of the current AFE (referred to as AFEI in this document). These limitations become increasingly deleterious to the performance of the Central Fiber Tracker as instantaneous luminosity increases. The limitations are inherent in the design of the key front end chips on the AFEI board (the SVXIIe and the SIFT) and the architecture of the board itself. The key limitations of the AFEI are: (1) SVX saturation; (2) Discriminator to analog readout cross talk; (3) Tick to tick pedestal variation; and (4) Channel to channel pedestal variation. The new version of the AFE board, AFEII, addresses these limitations by use of a new chip, the TriP-t and by architectural changes, while retaining the well understood and desirable features of the AFEI board.

  13. Front-End Electron Transfer Dissociation Coupled to a 21 Tesla FT-ICR Mass Spectrometer for Intact Protein Sequence Analysis

    Science.gov (United States)

    Weisbrod, Chad R.; Kaiser, Nathan K.; Syka, John E. P.; Early, Lee; Mullen, Christopher; Dunyach, Jean-Jacques; English, A. Michelle; Anderson, Lissa C.; Blakney, Greg T.; Shabanowitz, Jeffrey; Hendrickson, Christopher L.; Marshall, Alan G.; Hunt, Donald F.

    2017-09-01

    High resolution mass spectrometry is a key technology for in-depth protein characterization. High-field Fourier transform ion cyclotron resonance mass spectrometry (FT-ICR MS) enables high-level interrogation of intact proteins in the most detail to date. However, an appropriate complement of fragmentation technologies must be paired with FTMS to provide comprehensive sequence coverage, as well as characterization of sequence variants, and post-translational modifications. Here we describe the integration of front-end electron transfer dissociation (FETD) with a custom-built 21 tesla FT-ICR mass spectrometer, which yields unprecedented sequence coverage for proteins ranging from 2.8 to 29 kDa, without the need for extensive spectral averaging (e.g., 60% sequence coverage for apo-myoglobin with four averaged acquisitions). The system is equipped with a multipole storage device separate from the ETD reaction device, which allows accumulation of multiple ETD fragment ion fills. Consequently, an optimally large product ion population is accumulated prior to transfer to the ICR cell for mass analysis, which improves mass spectral signal-to-noise ratio, dynamic range, and scan rate. We find a linear relationship between protein molecular weight and minimum number of ETD reaction fills to achieve optimum sequence coverage, thereby enabling more efficient use of instrument data acquisition time. Finally, real-time scaling of the number of ETD reactions fills during method-based acquisition is shown, and the implications for LC-MS/MS top-down analysis are discussed. [Figure not available: see fulltext.

  14. The front-end electronics and slow control of large area SiPM for the SST-1M camera developed for the CTA experiment

    Czech Academy of Sciences Publication Activity Database

    Aguilar, J.A.; Bilnik, W.; Borkowski, J.; Mandát, Dušan; Pech, Miroslav; Schovánek, Petr

    2016-01-01

    Roč. 830, Sep (2016), s. 219-232 ISSN 0168-9002 R&D Projects: GA MŠk LM2015046; GA MŠk LE13012; GA MŠk LG14019 Institutional support: RVO:68378271 Keywords : CTA * SiPM * G-APD * preamplifier * front-end * slow-control * compensation Subject RIV: BF - Elementary Particles and High Energy Physics Impact factor: 1.362, year: 2016

  15. The Phase-I Trigger Readout Electronics Upgrade for the ATLAS Liquid-Argon Calorimeters

    CERN Document Server

    Ochoa, Ines; The ATLAS collaboration

    2017-01-01

    Electronics developments are pursued for the trigger readout of the ATLAS Liquid-Argon Calorimeter towards the Phase-I upgrade scheduled in the LHC shut-down period of 2019-2020. The LAr Trigger Digitizer system will digitize 34000 channels at a 40 MHz sampling with 12 bit precision after the bipolar shaper at the front-end system, and transmit to the LAr Digital Processing system in the back-end to extract the transverse energies. Results of ASIC developments including QA and radiation hardness evaluations, and performances on prototypes will presented with the overall system design.

  16. Supporting radical front end innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth; Gertsen, Frank

    2011-01-01

    An organization benefits substantially by improving front end innovation (FEI) actively and may thereby enhance the chances of developing innovations, as emphasized by several authors e.g. Reinertsen (1999), Dahl & Moreau (2002), Boeddrich (2004), Williams et al. (2007) and Vernorn et al. (2008......). Pharmaceutical innovation is unique, as it opposed to most other industries’ product development is science-driven and not customer-driven. In addition, the pharmaceutical FEI, as represented by research, lasts up to 5 years and the entire R&D process constitutes a period of 10-12 years, which is highly...... regulated by external authorities, e.g. The American Food and Drug Administration (FDA). The research aim of this paper is: to contribute to the field of FEI by studying how FEI can be actively supported within the industry specific context of the pharmaceutical industry, and through a conceptual discussion...

  17. Handheld readout electronics to fully exploit the particle discrimination capabilities of elpasolite scintillators

    Energy Technology Data Exchange (ETDEWEB)

    Budden, B.S., E-mail: bbudden@lanl.gov [Intelligence and Space Research Division, Los Alamos National Laboratory, Los Alamos, NM 87545 (United States); Stonehill, L.C.; Warniment, A.; Michel, J.; Storms, S.; Dallmann, N.; Coupland, D.D.S.; Stein, P.; Weller, S.; Borges, L.; Proicou, M.; Duran, G. [Intelligence and Space Research Division, Los Alamos National Laboratory, Los Alamos, NM 87545 (United States); Kamto, J. [Intelligence and Space Research Division, Los Alamos National Laboratory, Los Alamos, NM 87545 (United States); Electrical & Computer Engineering Department, Praire View A& M University, Prairie View, TX 77446 (United States)

    2015-09-21

    A new class of elpasolite scintillators has garnered recent attention due to the ability to perform as simultaneous gamma spectrometers and thermal neutron detectors. Such a dual-mode capability is made possible by pulse-shape discrimination (PSD), whereby the emission waveform profiles of gamma and neutron events are fundamentally unique. To take full advantage of these materials, we have developed the Compact Advanced Readout Electronics for Elpasolites (CAREE). This handheld instrument employs a multi-channel PSD-capable ASIC, custom micro-processor board, front-end electronics, power supplies, and a 2 in. photomultiplier tube for readout of the scintillator. The unit is highly configurable to allow for performance optimization amongst a wide sample of elpasolites which provide PSD in fundamentally different ways. We herein provide an introduction to elpasolites, then describe the motivation for the work, mechanical and electronic design, and preliminary performance results.

  18. Handheld readout electronics to fully exploit the particle discrimination capabilities of elpasolite scintillators

    Science.gov (United States)

    Budden, B. S.; Stonehill, L. C.; Warniment, A.; Michel, J.; Storms, S.; Dallmann, N.; Coupland, D. D. S.; Stein, P.; Weller, S.; Borges, L.; Proicou, M.; Duran, G.; Kamto, J.

    2015-09-01

    A new class of elpasolite scintillators has garnered recent attention due to the ability to perform as simultaneous gamma spectrometers and thermal neutron detectors. Such a dual-mode capability is made possible by pulse-shape discrimination (PSD), whereby the emission waveform profiles of gamma and neutron events are fundamentally unique. To take full advantage of these materials, we have developed the Compact Advanced Readout Electronics for Elpasolites (CAREE). This handheld instrument employs a multi-channel PSD-capable ASIC, custom micro-processor board, front-end electronics, power supplies, and a 2 in. photomultiplier tube for readout of the scintillator. The unit is highly configurable to allow for performance optimization amongst a wide sample of elpasolites which provide PSD in fundamentally different ways. We herein provide an introduction to elpasolites, then describe the motivation for the work, mechanical and electronic design, and preliminary performance results.

  19. Handheld readout electronics to fully exploit the particle discrimination capabilities of elpasolite scintillators

    International Nuclear Information System (INIS)

    Budden, B.S.; Stonehill, L.C.; Warniment, A.; Michel, J.; Storms, S.; Dallmann, N.; Coupland, D.D.S.; Stein, P.; Weller, S.; Borges, L.; Proicou, M.; Duran, G.; Kamto, J.

    2015-01-01

    A new class of elpasolite scintillators has garnered recent attention due to the ability to perform as simultaneous gamma spectrometers and thermal neutron detectors. Such a dual-mode capability is made possible by pulse-shape discrimination (PSD), whereby the emission waveform profiles of gamma and neutron events are fundamentally unique. To take full advantage of these materials, we have developed the Compact Advanced Readout Electronics for Elpasolites (CAREE). This handheld instrument employs a multi-channel PSD-capable ASIC, custom micro-processor board, front-end electronics, power supplies, and a 2 in. photomultiplier tube for readout of the scintillator. The unit is highly configurable to allow for performance optimization amongst a wide sample of elpasolites which provide PSD in fundamentally different ways. We herein provide an introduction to elpasolites, then describe the motivation for the work, mechanical and electronic design, and preliminary performance results

  20. Development of ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00534610; The ATLAS collaboration

    2017-01-01

    The LHC high-luminosity upgrade in 2024-2026 requires the associated detectors to operate at luminosities about 5-7 times larger than assumed in their original design. The pile-up is expected to increase to up to 200 events per proton bunch-crossing. To be able to retain interesting physics events even at rather low transverse energy scales, increased trigger rates are foreseen for the ATLAS detector. At the hardware selection stage acceptance rates of 1 MHz are planned, combined with longer latencies up to 60 micro-seconds in order to read out the necessary data from all detector channels. Under these conditions, the current readout of the ATLAS Liquid Argon (LAr) Calorimeters does not provide sufficient buffering and bandwidth capabilities. Furthermore, the expected total radiation doses are beyond the qualification range of the current front-end electronics. For these reasons a replacement of the LAr front-end and back-end readout system is foreseen for all 182,500 readout channels, with the exception of t...

  1. Upgraded Trigger Readout Electronics for the ATLAS LAr Calorimeters for Future LHC Running

    CERN Document Server

    Ma, H; The ATLAS collaboration

    2015-01-01

    The ATLAS Liquid Argon (LAr) calorimeters produce almost 200K signals that are digitized and processed by the front-end and back-end electronics for every triggered event. Additionally, the front-end electronics sums analog signals to provide coarse-grained energy sums to the first- level (L1) trigger system. The current design was optimized for the nominal LHC luminosity of 10^34cm^−2s^−1. In order to retain the capability to trigger on low energy electrons and photons when the LHC is upgraded to higher luminosity, an improved LAr calorimeter trigger readout is proposed and being constructed. The new trigger readout system makes available the fine segmentation of the calorimeter at the L1 trigger with high precision in order to reduce the QCD jet background in electron, photon and tau triggers, and to improve jet and missing ET trigger performance. The new LAr Trigger Digitizer Board is designed to receive the higher granularity signals, digitize them on-detector and send them via fast optical links to a...

  2. MDT-ASD, CMOS front-end for ATLAS MDT

    CERN Document Server

    Posch, C; Oliver, J

    2007-01-01

    This document serves as the main reference and user`s manual for the read-out chip of the Monitored Drift Tubes in the ATLAS Muon Spectrometer. The eight-channel front-end ASIC is referred to as MDT-ASD. The document contains the requirements and complete specifications, a detailed description of the design with characteristics of all sub-circuits and building blocks, a comprehensive section on functionality and performance test results, and a complete bibliography.

  3. Electronic Readout of the Atlas Liquid Argon Calorimeter: Calibration and Performance

    CERN Document Server

    Majewski, S; The ATLAS collaboration

    2010-01-01

    The Liquid Argon (LAr) calorimeter is a key detector component in the ATLAS experiment at the Large Hadron Collider (LHC) at CERN. The LHC is a proton-proton collider with a center-of-mass energy of 14 TeV. The machine has been operated at energies of 900 GeV and 2.36 TeV in 2009 and is expected to reach the energy of 7 TeV in 2010. The LAr calorimeter is designed to provide precision measurements of electrons, photons, jets and missing transverse energy. It consists of a set of sampling calorimeters with liquid argon as active medium kept into three separate cryostats. The LAr calorimeters are read out via a system of custom electronics. The electronic readout of the ATLAS LAr calorimeters is divided into a Front End (FE) system of boards mounted in custom crates directly on the cryostat feedthroughs, and a Back End (BE) system of VME-based boards located in an off-detector underground counting room where there is no radiation. The FE system includes Front End boards (FEBs), which perform the readout and dig...

  4. Optimization of the design of DC-DC converters for improving the electromagnetic compatibility with the Front-End electronic for the super Large Hadron Collider Trackers

    CERN Document Server

    Fuentes Rojas, Cristian Alejandro; Blanchot, G

    2011-01-01

    The upgrade of the Large Hadron Collider (LHC) experiments at CERN sets new challenges for the powering of the detectors. One of the powering schemes under study is based on DC-DC buck converters mounted on the front-end modules. The hard environmental conditions impose strict restrictions to the converters in terms of low volume, radiation and magnetic field tolerance. Furthermore, the noise emission of the switching converters must not affect the performance of the powered systems. A study of the sources and paths of noise of a synchronous buck converter has been made for identifying the critical parameters to reduce their emissions. As proof of principle, a converter was designed following the PCB layout considerations proposed and then used for powering a silicon strip module prototype for the ATLAS upgrade, in order to evaluate their compatibility.

  5. Muon front end for the neutrino factory

    Directory of Open Access Journals (Sweden)

    C. T. Rogers

    2013-04-01

    Full Text Available In the neutrino factory, muons are produced by firing high-energy protons onto a target to produce pions. The pions decay to muons and pass through a capture channel known as the muon front end, before acceleration to 12.6 GeV. The muon front end comprises a variable frequency rf system for longitudinal capture and an ionization cooling channel. In this paper we detail recent improvements in the design of the muon front end.

  6. The CMS silicon strip tracker and its electronic readout

    International Nuclear Information System (INIS)

    Friedl, M.

    2001-05-01

    The Large Hadron Collider (LHC) at CERN (Geneva, CH) will be the world's biggest accelerator machine when operation starts in 2006. One of its four detector experiments is the Compact Muon Solenoid (CMS), consisting of a large-scale silicon tracker and electromagnetic and hadron calorimeters, all embedded in a solenoidal magnetic field of 4 T, and a muon system surrounding the magnet coil. The Silicon Strip Tracker has a sensitive area of 206m 2 with 10 million analog channels which are read out at the collider frequency of 40 MHz. The building blocks of the CMS Tracker are the silicon sensors, APV amplifier ASICs, supporting front-end ASICs, analog and digital optical links as well as data processors and control units in the back-end. Radiation tolerance, readout speed and the huge data volume are challenging requirements. The charge collection in silicon detectors was modeled, which is discussed as well as the concepts of readout amplifiers with respect to the LHC requirements, including the deconvolution method of fast pulse shaping, electronic noise constraints and radiation effects. Moreover, extensive measurements on prototype components of the CMS Tracker and different versions of the APV chip in particular were performed. There was a significant contribution to the construction of several detector modules, characterized them in particle beam tests and quantified radiation induced effects on the APV chip and on silicon detectors. In addition, a prototype of the analog optical link and the analog performance of the back-end digitization unit were evaluated. The results are very encouraging, demonstrating the feasibility of the CMS Silicon Strip Tracker system and motivating progress towards the construction phase. (author)

  7. Development of Trigger and Readout Electronics for the ATLAS New Small Wheel Detector Upgrade

    CERN Document Server

    Guan, Liang; The ATLAS collaboration

    2017-01-01

    The present small wheel muon detector at ATLAS will be replaced with a New Small Wheel (NSW) detector to handle the increase in data rates and harsh radiation environment expected at the LHC. Resistive Micromegas and small strip Thin Gap Chambers will be used to provide both trigger and tracking primitives. Muon segments found at NSW will be combined with the segments found at the Big Wheel to determine the muon transverse momentum at the first-level trigger. A new trigger and readout system is developed for the NSW detector. The new system has about 2.4 million trigger and readout channels and about 8,000 Front-End boards. The large number of input channels, short time available to prepare and transmit data, harsh radiation environment, and low power consumption all impose great challenges on the design. We will discuss the overall electronics design and studies with various ASICs and high-speed circuit board prototypes.

  8. Timing and Readout Contorl in the LHCb Upgraded Readout System

    CERN Document Server

    Alessio, Federico

    2016-01-01

    In 2019, the LHCb experiment at CERN will undergo a major upgrade where its detectors electronics and entire readout system will be changed to read-out events at the full LHC rate of 40 MHz. In this paper, the new timing, trigger and readout control system for such upgrade is reviewed. Particular attention is given to the distribution of the clock, timing and synchronization information across the entire readout system using generic FTTH technology like Passive Optical Networks. Moreover the system will be responsible to generically control the Front-End electronics by transmitting configuration data and receiving monitoring data, offloading the software control system from the heavy task of manipulating complex protocols of thousands of Front-End electronics devices. The way in which this was implemented is here reviewed with a description of results from first implementations of the system, including usages in test-benches, implementation of techniques for timing distribution and latency control."

  9. End-Users, Front Ends and Librarians.

    Science.gov (United States)

    Bourne, Donna E.

    1989-01-01

    The increase in end-user searching, the advantages and limitations of front ends, and the role of the librarian in end-user searching are discussed. It is argued that librarians need to recognize that front ends can be of benefit to themselves and patrons, and to assume the role of advisors and educators for end-users. (37 references) (CLB)

  10. The front end of the fuel cycle

    International Nuclear Information System (INIS)

    Cohen, K.P.

    1985-01-01

    The purpose of this paper is to examine the front end of the fuel cycle as it relates to nuclear power and proliferation, with the ultimate purpose of recommending policies that foster widespread use of nuclear power without contributing to the risk of proliferation of nuclear weapons. Reactor design and construction, the production of reactor materials such as D/sub 2/O and zirconium, uranium mining, and uranium enrichment--all are characteristic front end activities. To keep the scope manageable, the first and fourth topics are the focus. There is, of course, no clear distinction between the front end and the back end of the fuel cycle, since the back of one fuel cycle can well be the front end of another. Even when fuel is not recycled, the choice of the front end often depends on the products one desires from the back end

  11. The ALICE TPC Readout Electronics Design, performance optimization and verification of the DAQ circuit

    CERN Document Server

    Attiq, urRehman; Dieter, Røhrich

    2012-12-03

    ALICE (A Large Ion Collider Experiment) is a dedicated heavy-ion experiment at CERN’s LHC (Large Hadron Collider). It is designed to study the physics of strongly interacting matter and the quark-gluon plasma in heavy-ion collisions. It contains a large volume Time Projection Chamber (TPC) as its main tracking device. The ALICE TPC is the largest ever built gaseous TPC, both in terms of dimensions and number of read-out channels (557,578). A total number of 128 channels are packed in one TPC Front End Card (FEC) and 4,356 FECs are distributed over 216 independent readout partitions. Each readout partition steered by a single Readout Control Unit (RCU) functions as an independent unit in the data acquisition system of the TPC. The RCU functions as an interface between the FECs, Data AcQuisition system (DAQ), the Trigger and Timing Circuit (TTC) and the Detector Control System (DCS). The ALICE TPC readout electronics is in operation since the start of the LHC in November 2009. The primary objectives of the wo...

  12. Readout electronics for CBM-TOF super module quality evaluation based on 10 Gbps ethernet

    Science.gov (United States)

    Jiang, D.; Cao, P.; Huang, X.; Zheng, J.; Wang, Q.; Li, B.; Li, J.; Liu, S.; An, Q.

    2017-07-01

    The Compressed Baryonic Matter-Time of Flight (CBM-TOF) wall uses high performance of Multi-gap Resistive Plate Chambers (MRPC) assembled in super modules to identify charged particles with high channel density and high measurement precision at high event rate. Electronics meet the challenge for reading data out from a super module at high speed of about 6 Gbps in real time. In this paper, the readout electronics for CBM-TOF super module quality evaluation is proposed based on 10 Gigabit Ethernet. The digitized TOF data from one super module will be concentrated at the front-end electronics residing on the side of the super module and transmitted to an extreme speed readout module (XSRM) housed in the backend crate through the PCI Express (PCIe) protocol via optic channels. Eventually, the XSRM transmits data to the data acquisition (DAQ) system through four 10 Gbps Ethernet ports in real time. This readout structure has advantages of high performance and expansibility. Furthermore, it is easy to operate. Test results on the prototype show that the overall data readout performance for each XSRM can reach up to 28.8 Gbps, which means XSRM can meet the requirement of reading data out from 4 super modules with 1280 channels in real time.

  13. The ANTARES Detector: Electronics and Readout

    Science.gov (United States)

    Circella, M.

    The ANTARES collaboration is building an underwater neutrino telescope at 2500 m depth in the Mediterranean Sea. The experiment aims to detect high- energy cosmic neutrinos using a 3D array of 900 photomultipliers distributed along 12 lines. 5 such lines have been operational since January 2007. The PMTs collect the Cherenkov light induced by neutrino-produced charged particles in the water. In this contribution, we will illustrate the electronics and the data acquisition system of the apparatus and discuss their performance. The PMT signals are digitized and time-stamped offshore. The front-end electronics, based on the ASIC Analogue Ring Sampler, is located inside electronics modules which collect data from PMT triplets and control the various calibration/monitoring devices. Bidirectional data communication is maintained between the shore station and the apparatus over a network of optical fibres with a DWDM technique. This is a convenient solution to allow control of the detector from the shore and to guarantee a high-bandwidth for data transport to shore. Common clock signals, GPS-synchronized onshore, are delivered to the whole apparatus on dedicated optical fibres. An onshore computer farm performs the data filtering and, depending on selectable trigger conditions, writes data to disk. Results from the current 5-line apparatus will be shown.

  14. Construction of a test facility for the readout electronics of the ZEUS calorimeter

    International Nuclear Information System (INIS)

    Geitz, G.

    1991-05-01

    The Uranium-Scintillator Calorimeter for the ZEUS Detector at HERA is read out by pulse-shaping front-end electronics which take samples on the stretched photomultiplier pulses and store them as analog voltages. After each trigger decision, the data is then digitized. By equalizing the calorimeter response to hadrons and electrons of the same energy and by minimisation of systematic errors a hadronic resolution of σ E /E = 35%/√(E/GEV) + 2% is achieved. To ensure a calibration of the calorimeter to better than 2%, an electronics calibartion has to be done for each readout channel which corrects for inequalities and sets the energy scale. A test facility designed to carry out series measurements and special investigations on the analog electronics has been built. A description of this facility and of the first measurements made with it are given. (orig.) [de

  15. Upgrade for the ATLAS Tile Calorimeter Readout Electronics at the High Luminosity LHC

    International Nuclear Information System (INIS)

    Cerqueira, A S

    2012-01-01

    The Tile Calorimeter (TileCal) is the hadronic calorimeter covering the most central region of the ATLAS experiment at LHC. The TileCal readout consists of about 10000 channels. The main TileCal upgrade will occur when preparing for the high luminosity operation. This (Phase 2) upgrade is scheduled around 2022. The upgrade aims at replacing the majority of the on- and off-detector electronics so that all calorimeter signals are directly digitized and sent to the off-detector electronics in the counting room. An ambitious upgrade development program is pursued to study different electronics options. Three options are presently being investigated for the front-end electronic upgrade. The first option is an improved version of the present system built using discrete components, the second alternative is based on the development of a dedicated ASIC, and the third is the development of a new version of the “QIE” based on the one developed for Fermilab. For the off-detector electronics a new back-end architecture is being developed, the so-called “super” Read-Out Driver (sROD). A demonstrator prototype read-out for a slice of the calorimeter with most of the new electronics, but also compatible with the present system, is planned to be inserted in ATLAS already in mid 2014 (at the end of the phase 0 upgrade).

  16. A compact system for two-dimensional readout of Gas Electron Multiplier detectors

    International Nuclear Information System (INIS)

    Mindur, B; Dąbrowski, W; Fiutowski, T; Wiącek, P; Zielińska, A

    2013-01-01

    There is a growing interest in the use of Gas Electron Multiplier (GEM) and other micro-pattern gas detectors (MPGD) for two-dimensional (2-D) position sensitive measurements of photons or charged particles. A Gas Electron Multiplier Readout Chip (GEMROC) is an Application Specific Integrated Circuit (ASIC) dedicated for 2-D strip readout of GEM detectors. The ASICs deliver the amplitudes and time coordinates of the signals recorded on two sets of orthogonal strips. Timing information is used for finding coincidences of signals on two spatial coordinates while amplitude information is used to find the center of gravity for the cluster of signals belonging to the same detection event. In this paper we present a Field Programmable Gate Array (FPGA) based compact readout system dedicated for these ASICs. The readout system consists of two synchronized FPGA-ADC boards connected to four front-end boards, each one equipped with two GEMROCs. Both FPGAs are connected to a DAQ PC using separate Gigabit Ethernet links. The DAQ PC is equipped with a dedicated C++ based software, which is responsible for configuration of the FPGAs and ASICs settings, storing all the incoming data as well as for on-line/off-line data processing and visualization. The performance of the system is illustrated by test bench measurements.

  17. Chapter 9: Electronics

    International Nuclear Information System (INIS)

    Grupen, Claus; Shwartz, Boris A.

    2006-01-01

    Sophisticated front-end electronics are a key part of practically all modern radiation detector systems. This chapter introduces the basic principles and their implementation. Topics include signal acquisition, electronic noise, pulse shaping (analog and digital), and data readout techniques

  18. Readout Electronics for the ATLAS LAr Calorimeter at HL-LHC

    Science.gov (United States)

    Chen, Hucheng; ATLAS Liquid Argon Calorimeter Group

    The ATLAS Liquid Argon (LAr) calorimeters are high precision, high sensitivity and high granularity detectors designed to provide precision measurements of electrons, photons, jets and missing transverse energy. ATLAS and its LAr calorimeters have been operating and collecting proton-proton collisions at LHC since 2009. The current front-end electronics of the LAr calorimeters need to be upgraded to sustain the higher radiation levels and data rates expected at the upgraded high luminosity LHC machine (HL-LHC), which will have 5 times more luminosity than the LHC in its ultimate configuration. The complexity of the present electronics and the obsolescence of some of components of which it is made, will not allow a partial replacement of the system. A completely new readout architecture scheme is under study and many components are being developed in various R&D programs of the LAr Calorimeter Group.The new front-end readout electronics will send data continuously at each bunch crossing through high speed radiation resistant optical links. The data will be processed real-time with the possibility of implementing trigger algorithms for clusters and electron/photon identification at a higher granularity than that which is currently implemented. The new architecture will eliminate the intrinsic limitation presently existing on Level-1 trigger acceptance. This article is an overview of the R&D activities which covers architectural design aspects of the new electronics as well as some detailed progress on the development of several ASICs needed, and preliminary studies with FPGAs to cover the backend functions including part of the Level-1 trigger requirements. A recently proposed staged upgrade with hybrid Tower Builder Board (TBB) is also described.

  19. Upgrade for the ATLAS Tile Calorimeter Readout Electronics at the High Luminosity LHC

    International Nuclear Information System (INIS)

    Carrió, F.

    2013-01-01

    This work presents an overview of the on-detector and off-detector electronics for the Phase II Upgrade of the ATLAS Tile Calorimeter at the LHC scheduled around 2022. Three options are being studied for the implementation of the new front-end readout: an improved version of the 3-in-1 card, a new version of the QIE chip and a dedicated ASIC called FATALIC. Moreover, the MainBoard will manage incoming signals from the FEBs and the DaughterBoard will send the digitized data to the off-detector electronics where the sROD will perform processing tasks on them. This work summarizes the status of the project

  20. Upgrade for the ATLAS Tile Calorimeter Readout Electronics at the High Luminosity LHC

    CERN Document Server

    Carrió, F; The ATLAS collaboration

    2012-01-01

    This work presents an overview of the on-detector and off-detector electronics for the Phase II Upgrade of the ATLAS Tile Calorimeter at the LHC scheduled around 2022. Three options are being studied for the implementation of the new front end readout: an improved version of the 3-in-1 card, a new version of the QIE chip and a dedicated ASIC called FATALIC. Moreover, the MainBoard will manage incoming signals of the FEBs and the DaughterBoard will send the digitized data to the off-detector electronics where the sROD will perform processing tasks on them. This work summarizes the status of the project.

  1. Demonstrator System for the Phase-I Upgrade of the Trigger Readout Electronics of the ATLAS Liquid Argon Calorimeters

    CERN Document Server

    FRAGNAUD, J; The ATLAS collaboration

    2014-01-01

    The trigger readout electronics of the ATLAS LAr Calorimeters will be improved for the Phase-I luminosity upgrade of the LHC to enhance the trigger feature extraction. Signals with higher spatial granularity will be digitized and processed by newly developed front-end and back-end components. In order to evaluate technical and performance aspects, a demonstrator system is being set up which is planned to be installed on the ATLAS detector during the upcoming LHC run. Results from system tests of the analog signal treatment, the trigger digitizer, the optical signal transmission and the FPGA-based back-end are reported.

  2. A front-end read out chip for the OPERA scintillator tracker

    CERN Document Server

    Lucotte, A; Borer, K; Campagne, J E; Cazes, A; Hess, M; de La Taille, C; Martin-Chassard, G; Raux, L; Repellin, J P

    2004-01-01

    Multi-anode photomultipliers H7546 are used to readout signal from the OPERA Scintillator Tracker (CERN/SPSC 2000-028, SPSC/P318, LNGSP 25/2000; CERN/SPSC 2001-025, SPSC/M668, LNGS-EXP30/2001). A 32- channel front-end Read Out Chip prototype accommodating the H7546 has been designed at LAL. This device features a low-noise, variable gain preamplifier to correct for multi-anode non-uniformity, an auto- trigger capability 100% efficient at a 0.3 photo-electron, and a charge measurement extending over a large dynamic range left bracket 0-100 right bracket photo-electrons. In this article we describe the ASIC architecture that is being implemented for the Target Tracker in OPERA, with a special emphasis put on the designs and the measured performance.

  3. Development of Trigger and Readout Electronics for the ATLAS New Small Wheel Detector Upgrade

    CERN Document Server

    Zhu, Junjie; The ATLAS collaboration

    2017-01-01

    The planned Phase-I and Phase-II upgrades of the LHC accelerator drastically impacts the ATLAS trigger and trigger rates. A replacement of the ATLAS innermost endcap muon station with a new small wheel (NSW) detector is planned for the second long shutdown period of 2019 - 2020. This upgrade will allow us to maintain a low pT threshold for single muon and excellent tracking capability even after the High-Luminosity LHC upgrade. The NSW detector will feature two new detector technologies, Resistive Micromegas and small-strip Thin Gap Chambers. Both detector technologies will provide trigger and tracking primitives. The total number of trigger and readout channels is about 2.4 millions, and the overall power consumption is expected to be about 75 kW. The electronics design will be implemented in some 8000 front-end boards including the design of four custom front-end ASICs capable to drive trigger and tracking primitives with high speed sterilizers to drive trigger candidates to the backend trigger processor sy...

  4. THREE PERSPECTIVES ON MANAGING FRONT END INNOVATION

    DEFF Research Database (Denmark)

    Jensen, Anna Rose Vagn; Clausen, Christian; Gish, Liv

    2018-01-01

    This paper presents three complementary perspectives on the management of front end innovation: A process model perspective, a knowledge perspective and a translational perspective. While the first two perspectives are well established in literature, we offer the translation perspective...... as a complementary perspective. The paper combines a literature review with an empirical examination of the application of these multiple perspectives across three cases of front end of innovation (FEI) management in mature product developing companies. While the process models represent the dominant, albeit rather...... to represent an emergent approach in managing FEI where process models, knowledge strategies and objects become integrated elements in more advanced navigational strategies for key players....

  5. RF front-end world class designs

    CERN Document Server

    Love, Janine

    2009-01-01

    All the design and development inspiration and direction a harware engineer needs in one blockbuster book! Janine Love site editor for RF Design Line,columnist, and author has selected the very best RF design material from the Newnes portfolio and has compiled it into this volume. The result is a book covering the gamut of RF front end design from antenna and filter design fundamentals to optimized layout techniques with a strong pragmatic emphasis. In addition to specific design techniques and practices, this book also discusses various approaches to solving RF front end design problems and h

  6. Effects of high-energy particle showers on the embedded front-end electronics of an electromagnetic calorimeter for a future lepton collider

    Czech Academy of Sciences Publication Activity Database

    Adloff, C.; Francis, K.; Repond, J.; Marčišovský, Michal; Šícho, Petr; Vrba, Václav; Zálešák, Jaroslav

    2011-01-01

    Roč. 654, č. 1 (2011), s. 97-109 ISSN 0168-9002 R&D Projects: GA MŠk LA09042; GA MŠk LA08032 Grant - others:EC(XE) RII3-CT-2006-026126 Institutional research plan: CEZ:AV0Z10100502 Keywords : lepton collider * electromagnetic calorimeter * embedded electronics * fake hits Subject RIV: BF - Elementary Particles and High Energy Physics Impact factor: 1.207, year: 2011 http://arxiv.org/pdf/arXiv:1102.3454v2

  7. A Multi-Pulse Front-End Rectifier System with Electronic Phase-Shifting for Harmonic Mitigation in Motor Drive Applications

    DEFF Research Database (Denmark)

    Zare, Firuz; Davari, Pooya; Blaabjerg, Frede

    2016-01-01

    In this paper, an electronic phase-shifting strategy has been optimized for a multi-parallel configuration of line-commutated rectifiers with a common dc-bus voltage used in motor drive application. This feature makes the performance of the system independent of the load profile and maximizes its...... harmonic reduction ability. To further reduce the generated low order harmonics, a dc-link current modulation scheme and its phase shift values of multi-drive systems have been optimized. Analysis and simulations have been carried out to verify the proposed method....

  8. Development of ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00069444; The ATLAS collaboration

    2017-01-01

    The LHC high-luminosity upgrade in 2024-2026 requires the associated detectors to operate at luminosities about 5-7 times larger than assumed in their original design. The pile- up is expected to increase to up to 200 events per proton bunch-crossing. To be able to retain interesting physics events at electroweak energy scales, increased trigger rates are foreseen for the ATLAS detector. At the hardware selection stage acceptance rates of up to 1 MHz are planned, combined with longer latencies up to 40 micro-seconds in order to read out the necessary data from all detector channels. The current readout of the ATLAS Liquid Argon (LAr) Calorimeters does not provide sufficient buffering and bandwidth capabilities. For these reasons a replacement of the LAr front-end and off-detector readout systems is foreseen for all 182,500 readout channels, with the exception of the cold pre-amplifier and summing devices of the hadronic LAr Calorimeter. The new low-power electronics must be able to capture the triangular dete...

  9. Analog lightwave links for detector front-ends at the LHC

    International Nuclear Information System (INIS)

    Baird, A.; Dowell, J.; Duthie, P.

    1995-01-01

    Lightwave links are being developed for volume application in the transfer of analog signals from the tracking detector front-ends to the readout electronics. The links are based on electro-optic intensity modulators which are mounted on detectors and connected by optical fibers to remotely located transceivers (lasers and photoreceivers). The modulators are 3--5 semiconductor reflective devices based on multi-quantum well structures. The transceivers will be integrated devices of a novel design. Modulator prototypes have been fabricated and tested. Neutron and γ-ray irradiation studies have been performed on modulators and fibers. The main results achieved so far are reported and key system issues are reviewed. This work is part of the CERN DRDC project RD23 project RD23

  10. A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

    International Nuclear Information System (INIS)

    Gao, W.; Yin, J.; Li, C.; Zeng, H.; Gao, D.; Hu, Y.

    2015-01-01

    This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e - to 100000 e - , which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)

  11. Tests of CMS Hadron Forward Calorimeter Upgrade Readout Box Prototype

    CERN Document Server

    Chatrchyan, Sergey; Sirunyan, Albert; Tumasyan, Armen; Mossolov, Vladimir; Shumeiko, Nikolai; Cornelis, Tom; Ochesanu, Silvia; Roland, Benoit Florent; Staykova, Zlatka; Van Haevermaet, Hans; Van Mechelen, Pierre; Van Spilbeeck, Alex; Alves, Gilvan Augusto; Martins, Thiago Dos Reis; Pol, Maria Elena; Vaz Da Silva Filho, Mario; Alda Junior, Walter Luiz; Carvalho, Wagner De Paula; Chinellato, Jose Augusto; De Oliveira Martins, Carley Pedro; Figueiredo, Diego Matos; Tonelli Manganote, Edmilson Jose; Molina Insfran, Jorge Andres; Mundim, Luiz; Nogima, Helio; Prado Da Silva, Wanda Lucia; Santoro, Alberto; Rosa Lopes Zachi, Alessandro; Finger, Miroslav; Finger, Michael; Tsamalaidze, Zviad; Borras, Kerstin; Gunnellini, Paolo; Jung, Hannes; Knutsson, Albert Hans; Lutz, Benjamin; Ribeiro Cipriano, Pedro Miguel; Sen, Niladri; Baus, Colin; Katkov, Igor; Ulrich, Ralf Matthias; Wohrmann, H; Panagiotou, Apostolos; Bencze, Gyorgy; Horvath, D; Bala, Suman; Gupta, Ruchi; Jindal, M; Lal, Manjit Kaur; Nishu, Nishu; Saini, Lovedeep Kaur; Banerjee, Sunanda; Bhattacharya, S; Gomber, Bhawna; Jain, Shilpi; Khurana, Raman; Sharan, Manoj Kumar; Aziz, Tariq; Maity, Manas; Majumder, Gobinda; Mazumdar, Kajari; Mohanty, Gagan Bihari; Katta, Sudhakar; Banerjee, Sudeshna; Dugad, Shashikant Raichand; Etesami, Seyed Mohsen; Fahim, Ali; Jafari, Abideh; Paktinat Mehdiabadi, Saeid; Zeinali, Maryam; Penzo, Aldo; Afanasyev, A; Bunin, Pavel; Ershov, Yuri; Fedoseev, Oleg; Gavrilenko, Mikhail; Golutvin, Igor; Gorbunov, Ilya; Konoplynikov, V; Malakhov, Alexander; Moisenz, Petr; Smirnov, Vitaly; Volodko, Anton; Zarubin, Anatoly; Andreev, Yuri; Dermenev, Alexander; Krasnikov, Nikolay; Pashenkov, Anatoli; Tlisov, Danila; Toropin, A; Epshteyn, Vladimir; Erofeeva, Maria; Gavrilov, Vladimir; Kosov, Mikhail Vladimirovich; Kudinov, Ilya; Lychkovskaya, Natalia; Popov, V; Safronov, Grigory; Semenov, Sergey; Stolin, Viatcheslav; Vlassov, Evgueni; Zhokin, Alexander; Belyaev, A; Boos, Eduard; Dubinin, Mikhail; Dudko, Lev; Ershov, Alexander; Gribushin, Andrey; Klyukhin, Vyacheslav; Kodolova, Olga; Korotkikh, Vladimir; Lokhtin, Igor; Markina, Anastasia; Obraztsov, Stepan; Perfilov, Maxim; Petrushanko, Sergey; Popov, Andrey; Savrin, Victor; Snigirev, Alexander; Vardanyan, Irina; Andreev, V; Azarkin, Maksim; Dremin, Igor; Kirakosyan, Martin; Leonidov, Andrey; Mesyats, Gennady; Vinogradov, Alexey; Bayshev, Igor; Bityukov, Sergey; Grishin, Viatcheslav; Kryshkin, Victor; Petrov, V; Ryutin, Roman; Sobol, Andrey; Turchanovich, Leonid; Troshin, Sergey; Uzunyan, Andrey; Volkov, Alexey; Santanastasio, Francesco; Adiguzel, Aytul; Bakirci, Numan Mustafa; Cerci, Salim; Dozen, Candan; Dumanoglu, Isa; Eskut, Eda; Girgis, Semiray; G�kbulut, Gul; Gurpinar, Emine; Hos, Ilknur; Kangal, Evrim Ersin; Karapinar, Guler; Kayis Topaksu, Aysel; Onengut, Gulsen; Ozdemir, Kadri; Ozturk, Sertac; Polatoz, Ayse; Sogut, Kenan; Sunar Cerci, Deniz; Tali, Bayram; Topakli, Huseyin; Vergili, Latife Nukhet; Vergili, Mehmet; Aliyev, Takhmasib; Deniz, Muhammed; Guler, Ali Murat; Ozpineci, Altug; Serin, Meltem; Sever, Ramazan; Zeyrek, Mehmet; Deliomeroglu, Mehmet; Gulmez, Erhan; Isildak, Bora; Kaya, Mithat; Kaya, Ozlem; Ozkorucuklu, Suat; Sonmez, Nasuf; Cankocak, Kerem; Levchuk, Leonid; Hatakeyama, Kenichi; Liu, H; Scarborough, Tara Ann; Rumerio, Paolo; Heister, Arno; Hill, C; Lawson, Philip Daniel; Lazic, Dragoslav; Rohlf, James; St. John, Jason; Sulak, Lawrence; Gennadiy, G; Laird, Edward; Landsberg, Greg; Narain, Meenakshi; Sinthuprasith, Tutanon; Tsang, Ka Vang; Long, Owen Rosser; Nguyen, Harold; Paramesvaran, Sudarshan; Sturdy, Jared; Stuart, David; To, Wing; West, Christopher Alan; Apresyan, Artur; Chen, Y; Mott, Alexander Robert; Spiropulu, Maria; Winn, David; Abdoulline, Salavat; Anderson, J; Chlebana, Frank; Freeman, James; Green, Daniel; Hanlon, J; Hirschauer, James Francis; Joshi, Umeshwar; Kunori, Shuichi; Musienko, Yuri; Sharma, Seema; Spalding, William Jeffrey; Tkaczyk, Slawomir; Vidal, Richard; Whitmore, Juliana; Wu, W; Gaultney, Vanessa; Linn, Stephan; Markowitz, Pete Edward; Martinez, German Ruben; Gleyzer, Sergei; Hagopian, Sharon Lee; Hagopian, Vasken; Jenkins, Charles Merrill; Baarmand, Marc M; Dorney, Brian L; Vodopiyanov, Igor; Akgun, Ugur; Albayrak, Elif Asli; Bilki, Burak; Clarida, Warren James; Duru, Firdevs; Merlo, Jean-Pierre; Mermerkaya, Hamit; Mestvirishvili, Alexi; Moeller, Anthony Richard; Nachtman, Jane; Newsom, Charles Ray; Norbeck, John Edwin; Olson, Jonathan Edward; Onel, Yasar; Ozok, Ferhat; Sen, Sercan; Schmidt, Ianos; Tiras, Emrah; Yetkin, Taylan; Yi, Kai; Kenny, Raymond Patrick; Murray, Michael Joseph; Wood, Jeffrey Scott; Baden, Andrew; Calvert, Brian Michael; Eno, Sarah Catherine; Gomez, Jaime Arturo; Grassi, Tullio; Hadley, Nicholas John; Kellogg, Richard; Kolberg, Ted; Lu, Y; Marionneau, Matthieu; Mignerey, Alice Louise Cox; Peterman, Alison Marie; Skuja, Andris; Temple, Jeffrey; Tonjes, Marguerite Belt; Kao, Shih-Chuan; Klapoetke, Kevin Humphrey; Mans, Jeremiah Michael; Pastika, Nathaniel Joseph; Kroeger, Robert; Rahmat, Rahmat; Sanders, David; Cremaldi, Lucien Marcus; Jain, S; Anastassov, Anton; Velasco, Mayda Marie; Won, Steven; Heering, Adriaan; Karmgard, Daniel; Pearson, Tessa Jae; Ruchti, Randal; Berry, Edmund A; Halyo, Valerie; Hebda, Philip; Hunt, Adam Paul; Lujan, Paul Joseph; Marlow, Daniel; Medvedeva, Tatiana; Saka, Halil; Tully, Christopher; Zuranski, Andrzej Maciej; Barnes, Virgil Everett; Laasanen, Alvin; Bodek, Arie; Chung, Yeon Sei; de Barbaro, Pawel Jan; Eshaq, Yossof; Garcia-bellido, Aran Angel; Goldenzweig, Pablo David; Han, Ji Yeon; Harel, Amnon; Miner, Daniel Carl; Vishnevskiy, Dmitry; Zielinski, Marek; Bhatti, Anwar; Ciesielski, Robert Adam; Flanagan, Will Hogan; Kamon, Teruki; Montalvo, Roy Joaquin; Sakuma, Tai; Akchurin, Nural; Damgov, Jordan; Dudero, Phillip Russell; Kovitanggoon, Kittikul; Lee, Sung Won; Libeiro, Terence; Volobouev, Igor; Gurrola, Alfredo; Milstene, Caroline

    2012-01-01

    A readout box prototype for CMS Hadron Forward calorimeter upgrade is built and tested in CERN H2 beamline. The prototype is designed to enable simultaneous tests of different readout options for the four anode upgrade PMTs, new front-end electronics design and new cabling. The response of the PMTs with different readout options is uniform and the background response is minimal. Multi-channel readout options further enhance the background elimination. Passing all the electronics, mechanical and physics tests, the readout box proves to be capable of providing the forward hadron calorimeter operations requirements in the upgrade era.

  12. A radiation hard bipolar monolithic front-end readout

    CERN Document Server

    Baschirotto, A; Cappelluti, I; Castello, R; Cermesoni, M; Gola, A; Pessina, G; Pistolesi, E; Rancoita, P G; Seidman, A

    1999-01-01

    A fast bipolar monolithic charge sensitive preamplifier (CSP), implemented in the monolithic 2 mu m BiCMOS technology (called HF2CMOS) was designed and built in a quad monolithic chip. Studies of radiation effects in the CSP $9 performance, from non-irradiated and up to neutron irradiation of 5.3*10/sup 14/ n/cm/sup 2/, have confirmed that the use of bipolar npn transistors is suitable for the radiation level of the future LHC collider environment. The CSP $9 presents a new circuit solution for obtaining adequate slew rate performances which results in an integral linearity better than 0.8554330n 5 V at 20 ns of shaping time, regardless of the bias current selected for the CSP. This way $9 the bias current of the CSP can be set for optimizing the power dissipation with respect to series and parallel noise, especially useful when the CSP is put in a radiation environment. A prototype test with a novel monolithic 20 ns $9 time constant RC-CR shaper, capable to sum up four inputs has been also realized, featurin...

  13. Dispersion management of the SULF front end

    Science.gov (United States)

    Li, Shuai; Wang, Cheng; Liu, Yanqi; Xu, Yi; Liu, Zhengzheng; Lu, Jun; Li, Yanyan; Liu, Xingyan; Li, Zhaoyang; Leng, Yuxin; Li, Ruxin

    2017-04-01

    To manage dispersion of the front end in the Shanghai Superintense Ultrafast Laser Facility (SULF), which is a large-scale project aimed at delivering 10 PW laser pulses, a stretcher based on a combination of a grating and a prism (grism) pair is inserted between an Öffner-triplet-type stretcher and a regenerative amplifier to reduce high-order dispersion introduced by optical materials at the amplification stage. The alignment of the grism pair is implemented by controlling the far-field pattern of the output beam of the grism pair. The energy of the front end reaches up to 7 J at a 1-Hz repetition rate. Experimental results show that the pulse duration can be compressed to 22.4 fs and the spectral distortion over the spectrum is less than 2.25 rad.

  14. Front-end conceptual platform modeling

    DEFF Research Database (Denmark)

    Guðlaugsson, Tómas Vignir; Ravn, Poul Martin; Mortensen, Niels Henrik

    2014-01-01

    Platform thinking has been the subject of investigation and deployment in many projects in both academia and industry. Most contributions involve the restructuring of product programs, and only a few support front-end development of a new platform in parallel with technology development. This con......Platform thinking has been the subject of investigation and deployment in many projects in both academia and industry. Most contributions involve the restructuring of product programs, and only a few support front-end development of a new platform in parallel with technology development....... The conclusion is that the Conceptual Product Platform model supports stakeholders in achieving an overview of the development tasks and communicating these across multidisciplinary development teams, as well as making decisions on the contents of the platform and providing a link between technical solutions...

  15. Managing Controversies in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Christiansen, John K.; Gasparin, Marta

    2016-01-01

    This research investigates the controversies that emerge in the fuzzy front end (FFE) and how they are closed so the innovation process can move on. The fuzzy front has been characterized in the literature as a very critical phase, but controversies in the FFE have not been studied before....... The analysis investigates the microprocesses around the controversies that emerge during the fuzzy front end of four products. Five different types of controversies are identified: profit, production, design, brand and customers/market. Each controversy represents a threat, but also an opportunity to search...... demonstrates how the fuzzy front requires managers to deal with controversies that emerge from many different places and involve both human and non-human actors. Closing the controversies requires managers to take account of the situation, identify the problem that needs to be addressed, and initiate a search...

  16. Prototype ALICE front-end card

    CERN Multimedia

    Maximilien Brice

    2004-01-01

    This circuit board is a prototype 48-channel front end digitizer card for the ALICE time projection chamber (TPC), which takes electrical signals from the wire sensors in the TPC and shapes the data before converting the analogue signal to digital data. A total of 4356 cards will be required to process the data from the ALICE TPC, the largest of this type of detector in the world.

  17. Pixel readout electronics for LHC and biomedical applications

    CERN Document Server

    Blanquart, L; Comes, G; Delpierre, P A; Fischer, P; Hausmann, J C; Keil, M; Lindner, Manfred; Meuser, S; Wermes, N

    2000-01-01

    The demanding requirements for pixel readout electronics for high- energy physics experiments and biomedical applications are reviewed. Some examples of the measured analog performance of prototype chips are given. The readout architectures of the PIxel readout for the ATlas experiment (PIRATE) chip suited for LHC experiments and of the multi-picture element counter (MPEC) counting chip targeted for biomedical applications are presented. First results with complete chip-sensor assemblies are also shown. (12 refs).

  18. Redesigned front end for the upgrade at CHESS

    International Nuclear Information System (INIS)

    Headrick, R.L.; Smolenski, K.W.

    1996-01-01

    We will report on beamline front-end upgrades for the 24-pole wiggler beamlines at CHESS. A new design for primary x-ray beamstops based on a tapered, water-cooled copper block has been implemented and installed in the CHESS F beamline. The design uses a horizontally tapered open-quote open-quote V close-quote close-quote shape to reduce the power density on the internal surfaces and internal water channels in the block to provide efficient water cooling. Upstream of the beam stops, we have installed a new photoelectron style beam position monitor with separate monitoring of the wiggler and dipole vertical beam positions and with micron-level sensitivity. The monitor close-quote s internal surfaces are designed to absorb the full x-ray power in case of beam missteering, and the uncooled photoelectron collecting plates are not visible to the x-ray beam. A graphite prefilter has been installed to protect the beryllium windows that separate the front end from the x-ray optics downstream. The redesigned front end is required by the upgrade of the Cornell storage ring, now in progress, which will allow stored electron and positron currents of 300 mA by 1996, and 500 mA by 1998. At 500 mA, the wiggler power output will be over 32 kW. copyright 1996 American Institute of Physics

  19. Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays.

    Science.gov (United States)

    Ciçek, Ihsan; Bozkurt, Ayhan; Karaman, Mustafa

    2005-12-01

    Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMUT element, we developed an electrical CMUT model with parameters derived through finite element analysis, and performed both the pre- and postlayout verification. An experimental chip consisting of 4 X 4 array of the designed circuit cells, each cell occupying a 200 X 200 microm2 area, was formed for the initial test studies and scheduled for fabrication in 0.8 microm, 50 V CMOS technology. The designed circuit is suitable for integration with CMUT arrays through flip-chip bonding and the CMUT-on-CMOS process.

  20. An Updated Front-End Data Link Design for the Phase-2 Upgrade of the ATLAS Tile Calorimeter

    CERN Document Server

    Silverstein, Samuel; The ATLAS collaboration

    2017-01-01

    We present a new design for the advanced Link Daughter Board (DB) for the front-end electronics upgrade of the ATLAS hadronic Tile Calorimeter. The DB provides control, configuration and continuous ADC readout for the front-end, as well as bi-directional multi-GB/s optical links to the off-detector readout system. The DB will operate in high luminosity LHC conditions with limited detector access, so the design is fault tolerant with a high level of redundancy to avoid single-point failure modes. The DB is divided longitudinally, with an FPGA serving the ADC channels on its respective side. The new design is based on the new Xilinx Kintex Ultrascale+ FPGA family, which provides improved high-speed link timing performance as well as better signal compatibility with the CERN-developed GBTx link and timing distribution ASICs. Two GBTx ASICs each provide redundant phase-adjusted, LHC synchronous clocks, parallel control buses and remote JTAG configuration access to both FPGAs on the DB.

  1. Trigger and readout electronics for the Phase-I upgrade of the ATLAS forward muon spectrometer

    CERN Document Server

    Moschovakos, Paris; The ATLAS collaboration

    2017-01-01

    The upgrades of the LHC accelerator and the experiments in 2019/20 and 2023/24 will increase the instantaneous and integrated luminosity, but also will drastically increase the data and trigger rates. To cope with the huge data flow while maintaining high muon detection efficiency and reducing fake muons found at Level-1, the present ATLAS small wheel muon detector will be replaced with a New Small Wheel (NSW) detector for high luminosity LHC runs. The NSW will feature two new detector technologies: resistive micromegas and small strip Thin Gap Chambers conforming a system of ~2.4 million readout channels. Both detector technologies will provide trigger and tracking primitives. A common readout path and a separate trigger path are developed for each detector technology. The electronics design of such a system will be implemented in about 8000 front-end boards, including the design of a number of custom radiation tolerant Application Specific Integrated Circuits (ASICs), capable of driving trigger and tracking...

  2. Trigger and Readout Electronics for the Phase-I Upgrade of the ATLAS Forward Muon Spectrometer

    CERN Document Server

    Moschovakos, Paris; The ATLAS collaboration

    2017-01-01

    The upgrades of the LHC accelerator and the experiments in 2019/20 and 2023/24 will increase the instantaneous and integrated luminosity, but also will drastically increase the data and trigger rates. To cope with the huge data flow while maintaining high muon detection efficiency and reducing fake muons found at Level-1, the present ATLAS small wheel muon detector will be replaced with a New Small Wheel (NSW) detector for high luminosity LHC runs. The NSW will feature two new detector technologies: resistive micromegas (MM) and small strip Thin Gap Chambers (sTGC) conforming a system of ~2.4 million readout channels. Both detector technologies will provide trigger and tracking primitives. A common readout path and a separate trigger path are developed for each detector technology. The electronics design of such a system will be implemented in about 8000 front-end boards, including the design of a number of custom radiation tolerant Application Specific Integrated Circuits (ASICs), capable of driving trigger ...

  3. The CMS silicon strip tracker and its electronic readout

    CERN Document Server

    Friedl, M

    2001-01-01

    The Large Hadron Collider (LHC) at CERN (Geneva, CH) will be the world's biggest accelerator machine when operation starts in 2006. One of its four detector experiments is the Compact Muon Solenoid (CMS), consisting of a large-scale silicon tracker and electromagnetic and hadron calorimeters, all embedded in a solenoidal magnetic field of 4T, and a muon system surrounding the magnet coil. The Silicon Strip Tracker has a sensitive area of 206m sup 2 with 10 million analog channels which are read out at the collider frequency of 40 MHz. The building blocks of the CMS Tracker are the silicon sensors, APV amplifier ASICs, supporting front-end ASICs, analog and digital optical links as well as data processors and control units in the back-end. Radiation tolerance, readout speed and the huge data volume are challenging requirements. I have modeled the charge collection in silicon detectors which is discussed as well as the concepts of readout amplifiers with respect to the LHC requirements, including the deconvolut...

  4. ATLAS Tile Calorimeter Readout Electronics Upgrade Program for the High Luminosity LHC

    CERN Document Server

    Cerqueira, A S

    2013-01-01

    The Tile Calorimeter (TileCal) is the hadronic calorimeter covering the most central region of the ATLAS experiment at LHC. The TileCal readout consists of about 10000 channels. The ATLAS upgrade program is divided in three phases: The Phase~0 occurs during 2013-2014, Phase~1 during 2018-1019 and finally Phase~2, which is foreseen for 2022-2023, whereafter the peak luminosity will reach 5-7 x 10$^{34}$ cm$^2$s$^{-1}$ (HL-LHC). The main TileCal upgrade is focused on the Phase~2 period. The upgrade aims at replacing the majority of the on- and off-detector electronics so that all calorimeter signals are directly digitized and sent to the off-detector electronics in the counting room. All new electronics must be able to cope with the increased radiation levels. An ambitious upgrade development program is pursued to study different electronics options. Three options are presently being investigated for the front-end electronic upgrade. The first option is an improved version of the present system built using comm...

  5. A new wire chamber front-end system, based on the ASD-8 B chip

    Energy Technology Data Exchange (ETDEWEB)

    Kruesemann, B.A.M. E-mail: kruesemann@kvi.nl; Bassini, R.; Ellinghaus, F.; Frekers, D.; Hagemann, M.; Hannen, V.M.; Heynitz, H. von; Heyse, J.; Rakers, S.; Sohlbach, H.; Woertche, H.J

    1999-07-11

    The Focal-Plane Polarimeter (FPP) for the Big-Bite Spectrometer van den Berg (Nucl. Instr. and Meth. B 99 (1995) 637ff) at the KVI requires the read-out of four large-area MWPCs and two VDCs with 3872 wires in total. The EUROSUPERNOVA collaboration (SNOVA) developed a digital 16 channel preamplifier front-end board, housing two amplifier-shaper-discriminatorchips ASD-8 B. The main features of this board are a fast single-wire readout, a high integration density, a low power consumption and compatibility to common instrumentation standards. The board represents the first successfully running application of the ASD-8 for wire chamber readout. (author)

  6. A new wire chamber front-end system, based on the ASD-8 B chip

    CERN Document Server

    Kruesemann, B A M; Ellinghaus, F; Frekers, D; Hagemann, M; Hannen, V M; Heynitz, H V; Heyse, J; Rakers, S; Sohlbach, H; Wörtche, H J

    1999-01-01

    The Focal-Plane Polarimeter (FPP) for the Big-Bite Spectrometer van den Berg (Nucl. Instr. and Meth. B 99 (1995) 637ff) at the KVI requires the read-out of four large-area MWPCs and two VDCs with 3872 wires in total. The EUROSUPERNOVA collaboration (SNOVA) developed a digital 16 channel preamplifier front-end board, housing two amplifier-shaper-discriminatorchips ASD-8 B. The main features of this board are a fast single-wire readout, a high integration density, a low power consumption and compatibility to common instrumentation standards. The board represents the first successfully running application of the ASD-8 for wire chamber readout. (author)

  7. Readout Electronics for the ATLAS LAr Calorimeter at HL-LHC

    CERN Document Server

    Chen, H; The ATLAS collaboration

    2011-01-01

    The ATLAS experiment is one of the two general-purpose detectors designed to study proton-proton collisions (14 TeV in the center of mass) produced at the Large Hadron Collider (LHC) and to explore the full physics potential of the LHC machine at CERN. The ATLAS Liquid Argon (LAr) calorimeters are high precision, high sensitivity and high granularity detectors designed to provide precision measurements of electrons, photons, jets and missing transverse energy. ATLAS (and its LAr Calorimeters) has been operating and collecting p-p collisions at LHC since 2009. The on-detector electronics (front-end) part of the current readout electronics of the calorimeters measures the ionization current signals by means of preamplifiers, shapers and digitizers and then transfers the data to the off-detector electronics (back-end) for further elaboration, via optical links. Only the data selected by the level-1 calorimeter trigger system are transferred, achieving a bandwidth reduction to 1.6 Gbps. The analog trigger sum sig...

  8. System Electronics for the ATLAS Upgraded Strip Detector

    CERN Document Server

    Affolder, T; The ATLAS collaboration; Clark, A; Dabrowskic, W; Dewitt, J; Diez Cornell, S; Dressdant, N; Fadeyev, V; Farthouat, P; Ferrere, D; Greenall, A; Grillo, A; Kaplon, J; Key-Charriere, M; La Marra, D; Lipeles, E; Lynn, D; Newcomer, M; Pereirab, F; Phillips, P; Spencer, E; Swientekc, K; Warren, M; Weidberg, A

    2013-01-01

    The basic concept of the front-end system of the Silicon Strip Detector in the Atlas Detector upgraded for the HL-LHC is being elaborated and proposed. The readout electronics of this new detector is based on front-end chips (ABC130), Hybrid Controller chips (HCC) and End of Stave Controller chips (EOSC). This document defines the basic functionality of the front-end system and of the different ASICs.

  9. Demonstrator System for the Phase-I Upgrade of the Trigger Readout Electronics of the ATLAS Liquid-Argon Calorimeters

    CERN Document Server

    Chen, Kai; The ATLAS collaboration

    2014-01-01

    The trigger readout electronics of the ATLAS Liquid Argon (LAr) Calorimeters will be improved for the Phase- I luminosity upgrade of the LHC, to enhance the trigger feature extraction. Signals with higher spatial granularity will be digitized and processed by newly developed front-end and back- end electronics. In order to evaluate technical and performance aspects, a demonstrator system has been set up, many off-detector tests have been done. Analog signal parameters including the noise and cross-talk, as well as digital signal treatment, high speed data transmission have been measured and verified. After a series of tests, the demonstrator system has been installed on the ATLAS detector before the LHC run-2.

  10. PARISROC, an autonomous front-end ASIC for triggerless acquisition in next generation neutrino experiments

    International Nuclear Information System (INIS)

    Conforti Di Lorenzo, S.; Campagne, J.E.; Drouet, S.; Dulucq, F.; El Berni, M.; Genolini, B.; La Taille, C. de; Martin-Chassard, G.; Seguin Moreau, N.; Wanlin, E.; Xiangbo, Y.

    2012-01-01

    PARISROC (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is a complete readout chip in AustriaMicroSystems (AMS) SiGe 0.35 μm technology designed to read array of 16 Photomultipliers (PMTs). The ASIC is realized in the context of the PMm2 (square meter PhotoMultiplier) project that has proposed a new system of “smart photo-detectors” composed by sensor and read-out electronics dedicated to next generation neutrino experiments. The future water Cherenkov detectors will take place in megaton size water tanks then with a large surface of photo-detection. We propose to segment the large surface in arrays with a single front-end electronics and only the useful data send in surface to be stocked and analyzed. This paper describes the second version of the ASIC and illustrates the chip principle of operation and the main characteristics thank to a series of measurements. It is a 16-channel ASIC with channels that work independently, in triggerless mode and all managed by a common digital part. Then main innovation is that all the channels are handled independently by the digital part so that only channels that have triggered are digitized. Then the data are transferred to the internal memory and sent out in a data driven way. The ASIC allows charge and time measurement. We measured a charge measurement range starting from 160 fC (1 photoelectron-p.e., at PMT gain of 10 6 ) to 100 pC (around 600 p.e.) at 1% of linearity; time tagging at 1 ns thanks to a 24-bit counter at 10 MHz and a Time to Digital Converter (TDC) on a 100 ns ramp.

  11. PARISROC, an autonomous front-end ASIC for triggerless acquisition in next generation neutrino experiments

    Science.gov (United States)

    Conforti Di Lorenzo, S.; Campagne, J. E.; Drouet, S.; Dulucq, F.; El Berni, M.; Genolini, B.; de La Taille, C.; Martin-Chassard, G.; Seguin Moreau, N.; Wanlin, E.; Xiangbo, Y.

    2012-12-01

    PARISROC (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is a complete readout chip in AustriaMicroSystems (AMS) SiGe 0.35 μm technology designed to read array of 16 Photomultipliers (PMTs). The ASIC is realized in the context of the PMm2 (square meter PhotoMultiplier) project that has proposed a new system of “smart photo-detectors” composed by sensor and read-out electronics dedicated to next generation neutrino experiments. The future water Cherenkov detectors will take place in megaton size water tanks then with a large surface of photo-detection. We propose to segment the large surface in arrays with a single front-end electronics and only the useful data send in surface to be stocked and analyzed. This paper describes the second version of the ASIC and illustrates the chip principle of operation and the main characteristics thank to a series of measurements. It is a 16-channel ASIC with channels that work independently, in triggerless mode and all managed by a common digital part. Then main innovation is that all the channels are handled independently by the digital part so that only channels that have triggered are digitized. Then the data are transferred to the internal memory and sent out in a data driven way. The ASIC allows charge and time measurement. We measured a charge measurement range starting from 160 fC (1 photoelectron-p.e., at PMT gain of 106) to 100 pC (around 600 p.e.) at 1% of linearity; time tagging at 1 ns thanks to a 24-bit counter at 10 MHz and a Time to Digital Converter (TDC) on a 100 ns ramp.

  12. Front-end multiplexing—applied to SQUID multiplexing: Athena X-IFU and QUBIC experiments

    Science.gov (United States)

    Prele, D.

    2015-08-01

    As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device) will be described.

  13. Upgrade Analog Readout and Digitizing System for ATLAS TileCal Demonstrator

    CERN Document Server

    Tang, F; The ATLAS collaboration; Akerstedt, H; Biot, A; Bohm, C; Carrio, F; Drake, G; Hildebrand, K; Muschter, S; Oreglia, M; Paramonov, A

    2013-01-01

    A potential upgrade for the front-end electronics and signal digitization and data acquisition system of the ATLAS hadron calorimeter for the high luminosity Large Hadron Collider (HL-LHC) is described. A Demonstrator is being built to readout a slice of the TileCal detector. The on-detector electronics includes up to 48 Analog Front-end Boards for PMT analog signal processing, 4 Main Boards for data digitization and slow controls, 4 Daughter Boards with high speed optical links to interface the on-detector and off-detector electronics. Two super readout driver boards are used for off-detector data acquisition and fulfilling digital trigger.\

  14. FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

    2007-10-27

    We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

  15. An updated front-end data link design for the Phase-2 upgrade of the ATLAS Tile Calorimeter

    CERN Document Server

    Silverstein, Samuel; The ATLAS collaboration

    2017-01-01

    We present a new design of the advanced Link Daughter Board (DB) for the front-end electronics upgrade of the ATLAS Tile Calorimeter (TileCal) for Phase-II. The new TileCal front-end comprises 1024 “mini-drawers” (MD) installed in 256 calorimeter modules. Each MD serves up to 12 PMT channels, with ADCs and calibration provided by one “main board” (MB) per MD. The DB is connected to the MB through a dense, high-speed FMC connector, and provides bi-directional multi-Gb/s optlcal links to the off-detector electronics for timing, control, and continuous high-speed readout of the ADC channels on the MB. The DB is designed for redundancy and fault-tolerance, and previous versions have already been successfully tested at CERN and elsewhere. The new revision includes Kintex Ultrascale+ FPGAs for improved link timing and radiation tolerance, an expanded role for the rad-tolerant GBTx ASICs, and a simpler design requiring fewer components and optical links.

  16. Demonstrator System for the Phase-I Upgrade of the Trigger Readout Electronics of the ATLAS Liquid-Argon Calorimeters

    CERN Document Server

    Chen, Kai; The ATLAS collaboration

    2014-01-01

    The trigger readout electronics of the ATLAS Liquid Argon Calorimeters are foreseen to be improved for the Phase-I luminosity upgrade of the LHC, in 2019, in order to enhance the trigger feature extraction. Signals with higher spatial granularity will be digitized and processed by newly developed front-end and back-end components. In order to evaluate technical and performance aspects, a demonstrator system is being developed, with the intention of installing it on the ATLAS detector for operation during the data-taking period beginning in 2015. Results from system tests of the analog signal treatment, the trigger digitizer, the optical signal transmission and the FPGA-based back-end modules will be reported.

  17. Highly Integrated Mixed-Mode Electronics for the readout of Time Projection Chambers

    CERN Document Server

    França Santos, Hugo Miguel; Musa, Luciano

    Time Projection Chambers (TPCs) are one of the most prevalent particle trackers for high-energy physics experiments. Future planed TPCs for the International Linear Collider (ILC) and the Compact Linear Collider (CLIC) entail very high spatial resolution in large gas volumes, but impose low material budget for the end caps of the TPC cylinder. This constraint is not accomplished with the state-of-the-art front-end electronics because of its unsuited relatively large mass and of its associated water cooling system. To reach the required material budget, highly compact and power efficient dedicated TPC front-end electronics should be developed. This project aims at re-designing the different electronic elements with significant improvements in terms of performance, power efficiency and versatility, and developing an integrated circuit that merges all components of the front-end electronics. This chip ambitions a large volume production at low unitary cost and its employment in multiple detectors. The design of ...

  18. AFTER, the front end ASIC of the T2K Time Projection Chambers

    CERN Document Server

    Baron, P; Calvet, D; de la Broise, X; Delagnes, E; Delbart, A; Druillole, F; Le Coguie, A; Mazzucato, E; Monmarthe, E; Zito, M

    2009-01-01

    The T2K (Tokai-to-Kamioka) experiment is a long baseline neutrino oscillation experiment in Japan. A near detector, located at 280m of the production target, is used to characterize the beam. One of its key elements is a tracker, made of three Time Projection Chambers (TPC) read by Micromegas endplates. A new readout system has been developed to collect, amplify, condition and acquire the data produced by the 124,000 detector channels of these detectors. The front-end element of this system is a a new 72-channel application specific integrated circuit. Each channel includes a low noise charge preamplifier, a pole zero compensation stage, a second order Sallen-Key low pass filter and a 511-cell Switched Capacitor Array. This electronics offers a large flexibility in sampling frequency, shaping time, gain, while taking advantage of the low physics events rate of 0.3 Hz. We detail the design and the performance of this ASIC and report on the deployment of the frond-end electronics on-site.

  19. Performance evaluation of the analogue front-end and ADC prototypes for the Gotthard-II development

    Science.gov (United States)

    Zhang, J.; Andrä, M.; Barten, R.; Bergamaschi, A.; Brückner, M.; Dinapoli, R.; Fröjdh, E.; Greiffenberg, D.; Lopez-Cuenca, C.; Mezza, D.; Mozzanica, A.; Ramilli, M.; Redford, S.; Ruat, M.; Ruder, C.; Schmitt, B.; Shi, X.; Thattil, D.; Tinti, G.; Turcato, M.; Vetter, S.

    2017-12-01

    Gotthard-II is a silicon microstrip detector developed for the European X-ray Free-Electron Laser (XFEL.EU). Its potential scientific applications include X-ray absorption/emission spectroscopy, hard X-ray high resolution single-shot spectrometry (HiREX), energy dispersive experiments at 4.5 MHz frame rate, beam diagnostics, as well as veto signal generation for pixel detectors. Gotthard-II uses a silicon microstrip sensor with a pitch of 50 μm or 25 μm and with 1280 or 2560 channels wire-bonded to readout chips (ROCs). In the ROC, an adaptive gain switching pre-amplifier (PRE), a fully differential Correlated-Double-Sampling (CDS) stage, an Analog-to-Digital Converter (ADC) as well as a Static Random-Access Memory (SRAM) capable of storing all the 2700 images in an XFEL.EU bunch train will be implemented. Several prototypes with different designs of the analogue front-end (PRE and CDS) and ADC test structures have been fabricated in UMC-110 nm CMOS technology and their performance has been evaluated. In this paper, the performance of the analogue front-end and ADC will be summarized.

  20. MMIC front-ends for optical communication systems

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad

    1993-01-01

    Two different types of optical front-end MMIC amplifiers for a 2.5-Gb/s coherent heterodyne optical receiver are presented. A bandwidth of 6-12 GHz has been obtained for a tuned front-end and 3-13 GHz for a distributed front-end. An input noise current density of 5-15 pA/√Hz has been obtained for...

  1. Radiation Tolerant Electronics and Digital Processing for the Phase-1 Readout Upgrade of the ATLAS Liquid Argon Calorimeters

    CERN Document Server

    Milic, Adriana; The ATLAS collaboration

    2015-01-01

    The high luminosities of $L > 10^{34} cm^{-2} s^{-1}$ at the Large Hadron Collider (LHC) at CERN produce an intense radiation environment that the detectors and their electronics must withstand. The ATLAS detector is a multi-purpose apparatus constructed to explore the new particle physics regime opened by the LHC. Of the many decay particles observed by the ATLAS detector, the energy of the created electrons and photons is measured by a sampling calorimeter technique that uses Liquid Argon (LAr) as its active medium. The front end (FE) electronic readout of the ATLAS LAr calorimeter located on the detector itself consists of a combined analog and digital processing system. In order to exploit the higher luminosity while keeping the same trigger bandwidth of 100 kHz, higher transverse granularity, higher resolution and longitudinal shower shape information will be provided from the LAr calorimeter to the Level-1 trigger processors. New trigger readout electronics have been designed for this purpose, which wil...

  2. Bringing the Fuzzy Front End into Focus

    Energy Technology Data Exchange (ETDEWEB)

    Beck, D.F.; Boyack, K.W.; Bray, O.H.; Siemens, W.D.

    1999-03-03

    Technology planning is relatively straightforward for well-established research and development (R and D) areas--those areas in which an organization has a history, the competitors are well understood, and the organization clearly knows where it is going with that technology. What we are calling the fuzzy front-end in this paper is that condition in which these factors are not well understood--such as for new corporate thrusts or emerging areas where the applications are embryonic. While strategic business planning exercises are generally good at identifying technology areas that are key to future success, they often lack substance in answering questions like: (1) Where are we now with respect to these key technologies? ... with respect to our competitors? (2) Where do we want or need to be? ... by when? (3) What is the best way to get there? In response to its own needs in answering such questions, Sandia National Laboratories is developing and implementing several planning tools. These tools include knowledge mapping (or visualization), PROSPERITY GAMES and technology roadmapping--all three of which are the subject of this paper. Knowledge mapping utilizes computer-based tools to help answer Question 1 by graphically representing the knowledge landscape that we populate as compared with other corporate and government entities. The knowledge landscape explored in this way can be based on any one of a number of information sets such as citation or patent databases. PROSPERITY GAMES are high-level interactive simulations, similar to seminar war games, which help address Question 2 by allowing us to explore consequences of various optional goals and strategies with all of the relevant stakeholders in a risk-free environment. Technology roadmapping is a strategic planning process that helps answer Question 3 by collaboratively identifying product and process performance targets and obstacles, and the technology alternatives available to reach those targets.

  3. The "fuzzy front end" of product development: An exploratory study

    OpenAIRE

    Verworn, Birgit

    2002-01-01

    The aim of this paper is to describe front-end activities in practice and get first hints for effects of the front end on project outcome and the meaning of contextual factors. The results of an exploratory study of fourteen product development projects are contrary to the wide-spread opinion that the quality of execution of front-end activities in practice is low. Although, due to the small sample size, our findings are limited, there seems to be an indirect impact of the fuzzy front end ...

  4. Tests und Inbetriebnahme der LHCb Outer Tracker Front-end Elektronik und eine Studie zur Abschätzung des Untergrundes im Zerfall $B^{0}_{s} \\to J\\Psi \\Phi$

    CERN Document Server

    Knopf, Jan

    2009-01-01

    The readout electronic of the LHCb outer tracker measures the drift time of a straw tube. The front-end electronic consists of three radiation hard chips. The ASDBLR preamplifier amplifies and discriminates the charge puls produced by the drift chamber. The OTIS-TDC chip measures the drift time every 25 ns on 32 detector channels. The generated data is send via an optical link with 1,6 GBit/s, making use of the GOL chip. The main part of this thesis is dedicated to the testing and commissioning of the outer tracker front-end electronic. Altogether three test systems were developed and operated. The first test system was built to thoroughly check the features of the OTIS-TDC chips on the wafer. The quality of the OTIS board and GOL-Aux board production was checked with another test system. The front-end electronic was also combined and tested to the LHCB readout chain. One of the main goals of the LHCb experiment is the measurement of the CP-violating phase Phi_s. It can be measured by using the golden decay m...

  5. FELIX: the detector readout upgrade of the ATLAS experiment

    CERN Document Server

    Ryu, Soo; The ATLAS collaboration

    2015-01-01

    After the Phase-I upgrade and onward, the Front-End Link eXchange(FELIX) system will be the interface between the readout system and the detector front-end electronics and trigger electronics at the ATLAS experiment. FELIX will function as a gateway to a commodity switched network which will use standard technologies (Ethernet or Infiniband) to communicate with data collecting and processing components. In this talk the system architecture of FELIX will be described and the testing results of the FELIX demonstrator will be presented

  6. Design of analog front-ends for the RD53 demonstrator chip

    CERN Document Server

    Gaioni, L; Nodari, B; Manghisoni, M; Re, V; Traversi, G; Barbero, M B; Fougeron, D; Gensolen, F; Godiot, S; Menouni, M; Pangaud, P; Rozanov, A; Wang, A; Bomben, M; Calderini, G; Crescioli, F; Le Dortz, O; Marchiori, G; Dzahini, D; Rarbi, F E; Gaglione, R; Gonella, L; Hemperek, T; Huegging, F; Karagounis, M; Kishishita, T; Krueger, H; Rymaszewski, P; Wermes, N; Ciciriello, F; Corsi, F; Marzocca, C; De Robertis, G; Loddo, F; Licciulli, F; Andreazza, A; Liberali, V; Shojaii, S; Stabile, A; Bagatin, M; Bisello, D; Mattiazzo, S; Ding, L; Gerardin, S; Giubilato, P; Neviani, A; Paccagnella, A; Vogrig, D; Wyss, J; Bacchetta, N; Della Casa, G; Demaria, N; Mazza, G; Rivetti, A; Da Rocha Rolo, M D; Comotti, D; Ratti, L; Vacchi, C; Beccherle, R; Bellazzini, R; Magazzu, G; Minuti, M; Morsani, F; Palla, F; Poulios, S; Fanucci, L; Rizzi, A; Saponara, S; Androsov, K; Bilei, G M; Menichelli, M; Conti, E; Marconi, S; Passeri, D; Placidi, P; Monteil, E; Pacher, L; Paternò, A; Gajanana, D; Gromov, V; Hessey, N; Kluit, R; Zivkovic, V; Havranek, M; Janoska, Z; Marcisovsky, M; Neue, G; Tomasek, L; Kafka, V; Sicho, P; Vrba, V; Vila, I; Lopez-Morillo, E; Aguirre, M A; Palomo, F R; Muñoz, F; Abbaneo, D; Christiansen, J; Dannheim, D; Dobos, D; Linssen, L; Pernegger, H; Valerio, P; Alipour Tehrani, N; Bell, S; Prydderch, M L; Thomas, S; Christian, D C; Fahim, F; Hoff, J; Lipton, R; Liu, T; Zimmerman, T; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gorelov, I; Hoeferkamp, M; Seidel, S; Toms, K; De Witt, J N; Grillo, A

    2017-01-01

    The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

  7. A low-power high dynamic range front-end ASIC for imaging calorimeters

    CERN Document Server

    Bagliesi, M G; Marrocchesi, P S; Meucci, M; Millucci, V; Morsani, F; Paoletti, R; Pilo, F; Scribano, A; Turini, N; Valle, G D

    2002-01-01

    High granularity calorimeters with shower imaging capabilities require dedicated front-end electronics. The ICON 4CH and VA4 PMT chip-set is suitable for very high dynamic range systems with strict noise requirements. The ICON 4CH is a 4 channel input, 12 channel output ASIC designed for use in a multi-anode photomultiplier system with very large dynamic range and low-noise requirements. Each of the four input signals to the ASIC is split equally into three branches by a current conveyor. Each of the three branches is scaled differently: 1:1, 1:8 and 1:80. The signal is read out by a 12 channel low noise/low power high dynamic range charge sensitive preamplifier-shaper circuit (VA4-PMT chip), with simultaneous sample- and-hold, multiplexed analog read-out, calibration facilities. Tests performed in our lab with a PMT are reported in terms of linearity, dynamic range and cross-talk of the system. (5 refs).

  8. Fatalic, a very-front-end Asic for the ATLAS Tile Calorimeter

    CERN Document Server

    Manen, Samuel Pierre; The ATLAS collaboration

    2016-01-01

    Abstract—The ATLAS Collaboration has started a vast program of upgrades in the context of high-luminosity LHC (HLLHC) forseen in 2024. The current readout electronics of every subdetector, including the Tile Calorimeter (TileCal), must be upgraded to comply with the new specifications aiming for the future operating conditions. The ASIC described in this document, named Front-end ATlAs tiLe Integrated Circuit (FATALIC), has been developed to fulfil the requirements of the TileCal upgrade. FATALIC is based on a 130 nm CMOS technology and performs the complete processing of the signal, including amplification, shaping and digitization. The first stage is a current conveyor which splits the input signal into three ranges, allowing to deal with a large dynamic range (from 25 fC up to 1.2 nC). Each current conveyor output is followed by a shaper and a dedicated pipeline 12 bit ADC operating at 40 MHz. Measurements show a non-linearity at the percent level for a typical input charge of interest. The noise of the ...

  9. Radiation induced Single Event Effects in the ATLAS MDT-ASD front-end chip

    CERN Document Server

    Posch, C

    2002-01-01

    Single Event Effect (SEE) tests of the MDT-ASD, the ATLAS MDT front-end chip have been performed at the Harvard Cyclotron Lab. The MDT-ASD is an 8-channel drift tube read-out ASIC fabricated in a commercial 0.5um CMOS process (AMOS14TB). The chip contains a 53 bit register which holds the setup information and an associated shift register of the same length plus some additional control logic. 10 test devices were exposed to a 160 MeV proton beam with a fluence of 1.05E9 p.cm-2.s-1 up to >4.4E p.cm-2 per device. After a total fluence of 4.46E13 p.cm-2, 7 soft SEEs (non-permanent bit flips in the registers) and 0 hard/destructive SEE (e.g. latch-ups, SEL) had occurred. The simulated fluence for 10 years of LHC operation at nominal luminosity for worst case location MDT components is 2.67E11 h.cm-2. The rate of SEUs in the ASD setup register for all of ATLAS, derived from these numbers, is 2.4 per day. It is foreseen to update the active registers of the on-detector electronics at regular intervals. Depending on...

  10. Multi-chip module development for the ATLAS pixel detector. Analysis of the front-end chip electronics in radiation hard 0.25-μm technology as well as development and realization of a serial power concept

    International Nuclear Information System (INIS)

    Stockmanns, T.

    2004-08-01

    The innermost layer of the ATLAS tracking system is a silicon pixel detector. The use of radiation tolerant components is mandatory due to the harsh radiation environment. The smallest independent component of the pixel detector is a hybride pixel module consisting of a large oxygen enriched silicon sensor and 16 specifically developed ASICs. To achieve the necessary radiation tolerance the ASICs are produced in a 0.25 μm technology in combination with special design techniques. The measurements of the readout electronics during all stages of production of a full module are presented and the performance of the modules is compared with the strict requirements of the ATLAS pixel detector. Furthermore a new powering scheme for pixel detectors is presented, aiming at reducing the total power consumption, the material for the electrical services and the amount of power cables. The advantages and disadvantages of this concept are discussed on the example of the ATLAS pixel detector with pixel modules modified accounting to the new powering scheme. The performance of six of those modules operating at the same time in a small system test is compared to that of normal ATLAS pixel modules. (orig.)

  11. Cost of pedestrian and bicycle accidents involving car front ends.

    NARCIS (Netherlands)

    Kampen, L.T.B. van & Huijbers, J.J.W.

    1995-01-01

    A cost study has been carried out, based on Dutch insurance data of payments to victims (pedestrians and cyclists) of collisions against car front ends. The results of this study will be used for a cost-benefit analysis of a proposed amendment (a series of car front end crash tests) to the existing

  12. A New Readout Electronics for the LHCb Muon Detector Upgrade

    CERN Multimedia

    Cadeddu, Sandro

    2016-01-01

    The 2018/2019 upgrade of LHCb Muon System foresees a 40 MHz readout scheme and requires the development of a new Off Detector Electronics (nODE) board that will be based on the nSYNC, a radiation tolerant custom ASIC developed in UMC 130 nm technology. Each nODE board has 192 input channels processed by 4 nSYNCs. The nSYNC is equipped with fully digital TDCs and it implements all the required functionalities for the readout: bunch crossing alignment, data zero suppression, time measurements. Optical interfaces, based on GBT and Versatile link components, are used to communicate with DAQ, TFC and ECS systems.

  13. Idea management in support of pharmaceutical front end innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2012-01-01

    , which again put pressure on the efficiency of front end innovation (FEI). In the attempt to overcome these various challenges pharmaceutical companies are looking for new models to support FEI. This paper explores in what way idea management can be applied as a tool in facilitation of front end...... innovation in practice. First I show through a literature study, how idea management and front end innovation are related and may support each other. Hereafter I apply an exploratory case study of front end innovation in eight medium to large pharmaceutical companies in examination of how idea management...... is applied in facilitation of front end innovation in practice. In order for a pharmaceutical company to support FEI, I present propositions of effective facilitation of pharmaceutical FEI and idea management....

  14. Prototype readout electronics for the upgraded ALICE Inner Tracking System

    Czech Academy of Sciences Publication Activity Database

    Sielewicz, K. M.; Rinella, G. A.; Bonora, M.; Ferencei, Jozef; Giubilato, P.; Rossewij, M. J.; Schambach, J.; Vaňát, Tomáš

    2017-01-01

    Roč. 12, JAN (2017), č. článku C01008. ISSN 1748-0221. [Topical Workshop on Electronics for Particle Physics. Karlsruhe, 26.09.2016-30.09.2016] R&D Projects: GA MŠk LM2015056; GA MŠk(CZ) LG15052; GA MŠk LM2015058 Institutional support: RVO:61389005 Keywords : digital electronic circuits * electronic detector readout concepts * modlar electronics * radiation-hard electronics Subject RIV: BG - Nuclear, Atomic and Molecular Physics, Colliders OBOR OECD: Nuclear physics Impact factor: 1.220, year: 2016

  15. Development of SuperHERO readout electronics

    Data.gov (United States)

    National Aeronautics and Space Administration — Next-generation solar hard X-ray (HXR) imagers will make high-sensitivity, high-dynamic-range observations of the signatures of accelerated electrons in solar...

  16. Digital front-end module (DFEM) series; Digital front end module (DFEM) series

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2000-03-01

    The digital front-end module (DFEM) is a module in which the processes ranging from the reception of digitally modulated radiofrequencies to the output of digital IF (Intermediate Frequency) signals or data streams are integrated. Beginning with a module for the MCNS (Multimedia Cable Network System) cable modem which was the first module in this business field approved by the Cable Labs, U.S., Toshiba has developed a series of DFEMs for various digital media for satellites, ground waves, and CATV (Cable Television) systems. The series is characterized by (1) the serialization of DFEMs compatible with various digital modulation techniques such as 8 PSK (Phase Shift Keying), OFDM (Orthogonal Frequency Division Multiplexing), and 256 QAM (Quadrature Amplitude Modulation), (2) easy connection with digital circuits thanks to the high shielding effect, and (3) the achievement of smaller size, higher performance, and lower power consumption. (translated by NEDO)

  17. Design of a wideband CMOS impedance spectroscopy ASIC analog front-end for multichannel biosensor interfaces.

    Science.gov (United States)

    Valente, Virgilio; Dai Jiang; Demosthenous, Andreas

    2015-08-01

    This paper presents the preliminary design and simulation of a flexible and programmable analog front-end (AFE) circuit with current and voltage readout capabilities for electric impedance spectroscopy (EIS). The AFE is part of a fully integrated multifrequency EIS platform. The current readout comprises of a transimpedance stage and an automatic gain control (AGC) unit designed to accommodate impedance changes larger than 3 order of magnitude. The AGC is based on a dynamic peak detector that tracks changes in the input current over time and regulates the gain of a programmable gain amplifier in order to optimise the signal-to-noise ratio. The system works up to 1 MHz. The voltage readout consists of a 2 stages of fully differential current-feedback instrumentation amplifier which provide 100 dB of CMRR and a programmable gain up to 20 V/V per stage with a bandwidth in excess of 10MHz.

  18. Adaptive RF front-ends for hand-held applications

    CERN Document Server

    van Bezooijen, Andre; van Roermund, Arthur

    2010-01-01

    The RF front-end - antenna combination is a vital part of a mobile phone because its performance is very relevant to the link quality between hand-set and cellular network base-stations. The RF front-end performance suffers from changes in operating environment, like hand-effects, that are often unpredictable. ""Adaptive RF Front-Ends for Hand-Held Applications"" presents an analysis on the impact of fluctuating environmental parameters. In order to overcome undesired behavior two different adaptive control methods are treated that make RF frond-ends more resilient: adaptive impedance control,

  19. Muon capture for the front end of a muon collider

    Energy Technology Data Exchange (ETDEWEB)

    Neuffer, D.; /Fermilab; Yoshikawa, C.; /MUONS Inc., Batavia

    2011-03-01

    We discuss the design of the muon capture front end for a {mu}{sup +}-{mu}{sup -} Collider. In the front end, a proton bunch on a target creates secondary pions that drift into a capture transport channel, decaying into muons. A sequence of rf cavities forms the resulting muon beams into strings of bunches of differing energies, aligns the bunches to (nearly) equal central energies, and initiates ionization cooling. The muons are then cooled and accelerated to high energy into a storage ring for high-energy high luminosity collisions. Our initial design is based on the somewhat similar front end of the International Design Study (IDS) neutrino factory.

  20. A 3-Channel 14-Bit Optimum SNS Wideband Digital Antenna: Analysis of the Electro-Optic Sampling Front End

    National Research Council Canada - National Science Library

    Foster, Kevin

    1997-01-01

    .... This thesis describes the design, construction, testing and analysis of the optical electronics at the front end of a prototype optimum SNS digital antenna with a desired accuracy of 14 bits and a bandwidth of 2.5 MHz...

  1. Design of the Readout Electronics for the BGO Calorimeter of DAMPE Mission

    Science.gov (United States)

    Feng, Changqing; Zhang, Deliang; Zhang, Junbin; Gao, Shanshan; Yang, Di; Zhang, Yunlong; Zhang, Zhiyong; Liu, Shubin; An, Qi

    2015-12-01

    The DAMPE (DArk Matter Particle Explorer) is a scientific satellite being developed in China, aimed at cosmic ray study, gamma ray astronomy, and searching for the clue of dark matter particles in the near future. The BGO (Bismuth Germanate Oxide) Calorimeter, which consists of 616 PMTs (photomultiplier tubes) and 1848 dynode signals, is a crucial part of the DAMPE payload for measuring the energy of cosmic ray particles, distinguishing interesting particles from background, and providing trigger information. An electronics system, which consists of 16 FEE (Front End Electronics) modules with a total power consumption of about 26 W, has been developed. Its main functions are based on the low power, 32-channel VA160 and VATA160 ASICs (Application Specific Integrated Circuits) for precisely measuring the charge of PMT signals and providing“hit”signals as well. To assure the long-term reliability in harsh space environment, a series of critical issues such as the radiation hardness, thermal design, components and board level quality control, etc., are taken into consideration. Test result showed that the system level ENC (equivalent noise charge) for each channel is about 10 fC in RMS (root mean square), and the timing uncertainty of the hit signals is about 300 ns, both of which satisfy the physics requirements of the detector. Experiments with 60Co radioactive source proved that 20 krad(Si) TID (Total Ionizing Dose) level is achieved, while the heavy ion beam and laser beam tests indicated that its SEL (Single Event Latch-up) and SEU (Single Event Upset) performance in orbit will be acceptable by taking some hardness measures. All the readout modules successfully passed the board-level screening, the sub-system level and finally the satellite system level environmental tests, and behave well in the beam test at CERN (European Organisation for Nuclear Research).

  2. Evaluation of Cryogenic Readout Electronics for ASTRO-F

    Science.gov (United States)

    Watabe, Toyoki; Hirao, Takanori; Shibai, Hiroshi; Kawada, Mitsunobu; Nagata, Hiroshi; Hibi, Yasunori; Noda, Manabu

    Cryogenic readout electronics have been developed for the far-infrared detectors onboard ASTRO-F, the first Japanese infrared astronomical satellite. This cryogenic readout circuit should be mounted near the detector array at the liquid helium temperature in order to achieve high sensitivity. We succeeded in developing the cryogenic p-MOS transistor by a standard Bi-CMOS process with a slight modification. By using the new p-MOS transistor, we have made several types of cryogenic electronics, (OP-AMP and CTIA), and evaluated their performances in the liquid helium temperature. The results are: 1. Open loop gain of OP-AMP ~300 2. Input equivalence noise ~3μV/Hz1/2 3. Power consumption ~10μW/ch More details will be shown on the poster.

  3. Optical Module Front-End for a Neutrino Underwater Telescope PMT interface

    CERN Document Server

    Lo Presti, D; Caponetto, L

    2007-01-01

    A proposal for a new system to capture signals in the Optical Module (OM) of an Underwater Neutrino Telescope is described. It concentrates on the problem of power consumption in relation to precision. In particular, a solution for the interface between the photomultiplier (PMT) and the front-end electronics is presented.

  4. Indico front-end: From spaghetti to lasagna

    CERN Multimedia

    CERN. Geneva

    2017-01-01

    We will present how we transitioned from legacy spaghetti UI code to a more coherent, easier to understand and maintain ecosystem of front-end technologies and facilities with a strong emphasis in reusable components. In particular, we will share with you: 1) how we use Sass to maintain our home-baked CSS, 2) how we survive in 2017 without front-end Javascript frameworks, and 3) how we use template macros and WTForms for generating consistent HTML transparently.

  5. Radiation Tolerant Electronics and Digital Processing for the Phase-I Trigger Readout Upgrade of the ATLAS Liquid Argon Calorimeters

    CERN Document Server

    Milic, Adriana; The ATLAS collaboration

    2015-01-01

    The high luminosities of $\\mathcal{L} > 10^{34} \\mathrm{cm}^{-2} \\mathrm{s}^{-1}$at the Large Hadron Collider (LHC) at CERN produce an intense radiation environment that the detectors and their electronics must withstand. The ATLAS detector is a multi-purpose apparatus constructed to explore the new particle physics regime opened by the LHC. Of the many decay particles observed by the ATLAS detector, the energy of the created electrons and photons is measured by a sampling calorimeter technique that uses Liquid Argon (LAr) as its active medium. The Front End (FE) electronic readout of the ATLAS LAr calorimeter located on the detector itself consists of a combined analog and digital processing system. The FE electronics were qualified for radiation levels corresponding to 10 years of LHC operations. The high luminosity running of the LHC (HL-LHC), with instantaneous luminosities of $5 \\times 10^{34} \\mathrm{cm}^ {-2} \\mathrm{s}^{-1}$ and an integrated luminosity of $3000 \\ \\mathrm{fb}^{-1}$ will exceed these d...

  6. A modular electronic readout system for the OPAL electromagnetic presampler

    International Nuclear Information System (INIS)

    Hobbs, J.D.; Anderson, K.J.; Gensler, S.W.; Kroll, J.; Merritt, F.S.; Nguyen, H.H.; Oreglia, M.J.; Pilcher, J.E.; Roney, J.M.; Redmond, M.W.; Sanders, H.; Schappert, W.S.; Strom, D.

    1993-01-01

    The readout system used to sample and digitize the 21 504 channels of the OPAL electromagnetic barrel presampler is described. The system consists of semi-custom analog electronics mounted directly on the detector to provide integrate-and-hold capability and custom VME boards to implement the digitization functions. The data from one event is digitized completely in under 7 ms. This meets the OPAL requirement of a sustained 10 Hz trigger rate with less than 10% dead time. A minimum ionizing particle deposits 2.7 pC in a single layer of the presampler, and the largest signal commonly seen in 200 pC. The dynamic range of the readout system is 0.032 to 1000 pC. The noise on a single channel is typically 0.2 pC. A linear analog calibration is automatically applied on a channel-by-channel basis. Programmable logic is used extensively. (orig.)

  7. The front-end chip of the SuperB SVT detector

    Science.gov (United States)

    Giorgi, F.; Comotti, D.; Manghisoni, M.; Re, V.; Traversi, G.; Fabbri, L.; Gabrielli, A.; Pellegrini, G.; Sbarra, C.; Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A.; Berra, A.; Lietti, D.; Prest, M.; Bevan, A.; Wilson, F.; Beck, G.; Morris, J.; Ganaway, F.; Cenci, R.; Bombelli, L.; Citterio, M.; Coelli, S.; Fiorini, C.; Liberali, V.; Monti, M.; Nasri, B.; Neri, N.; Palombo, F.; Stabile, A.; Balestri, G.; Batignani, G.; Bernardelli, A.; Bettarini, S.; Bosi, F.; Casarosa, G.; Ceccanti, M.; Forti, F.; Giorgi, M. A.; Lusiani, A.; Mammini, P.; Morsani, F.; Oberhof, B.; Paoloni, E.; Perez, A.; Petragnani, G.; Profeti, A.; Rizzo, G.; Soldani, A.; Walsh, J.; Gaioni, L.; Manazza, A.; Quartieri, E.; Ratti, L.; Zucca, S.; Dalla Betta, G.-F.; Fontana, G.; Pancheri, L.; Povoli, M.; Verzellesi, G.; Bosisio, L.; Lanceri, L.; Rashevskaya, I.; Stella, C.; Vitale, L.

    2013-08-01

    The asymmetric e+e- collider SuperB is designed to deliver a high luminosity, greater than 1036cm-2s-1, with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2 MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2 MHz per strip, the efficiency of the digital readout remained above 99.8%.

  8. A new electronic read-out for the YAPPET scanner

    CERN Document Server

    Damiani, C; Malaguti, R; Guerra, A D; Domenico, G D; Zavattini, G

    2002-01-01

    A small animal PET-SPECT scanner (YAPPET) prototype was built at the Physics Department of the Ferrara University and is presently being used at the Nuclear Medicine Department for radiopharmaceutical studies on rats. The first YAPPET prototype shows very good performances, but needs some improvements before it can be fully used for intensive radiopharmaceutical research. The main problem of the actual prototype is its heavy electronics, based on NIM and CAMAC standard modules. For this reason a new, compact read-out electronics was developed and tested. The results of a first series of tests made on the first prototype will be presented in the paper.

  9. Multi-chip module development for the ATLAS pixel detector. Analysis of the front-end chip electronics in radiation hard 0.25-{mu}m technology as well as development and realization of a serial power concept; Multi-Chip-Modul-Entwicklung fuer den ATLAS-Pixeldetektor. Analyse der Front-End-Chip-Elektronik in strahlenharter0,25-{mu}m-Technologie sowie Entwicklung und Realisierung eines Serial-Powering-Konzeptes

    Energy Technology Data Exchange (ETDEWEB)

    Stockmanns, T.

    2004-08-01

    The innermost layer of the ATLAS tracking system is a silicon pixel detector. The use of radiation tolerant components is mandatory due to the harsh radiation environment. The smallest independent component of the pixel detector is a hybride pixel module consisting of a large oxygen enriched silicon sensor and 16 specifically developed ASICs. To achieve the necessary radiation tolerance the ASICs are produced in a 0.25 {mu}m technology in combination with special design techniques. The measurements of the readout electronics during all stages of production of a full module are presented and the performance of the modules is compared with the strict requirements of the ATLAS pixel detector. Furthermore a new powering scheme for pixel detectors is presented, aiming at reducing the total power consumption, the material for the electrical services and the amount of power cables. The advantages and disadvantages of this concept are discussed on the example of the ATLAS pixel detector with pixel modules modified accounting to the new powering scheme. The performance of six of those modules operating at the same time in a small system test is compared to that of normal ATLAS pixel modules. (orig.)

  10. Readout Electronics for BGO Calorimeter of DAMPE: Status during the First Half-year after Launching

    Science.gov (United States)

    Ma, Siyuan; Feng, Changqing; Zhang, Deliang; Wang, Qi

    2016-07-01

    The DAMPE (DArk Matter Particle Explorer) is a scientic satellite which was successfully launched into a 500 Km sun-synchronous orbit, on December 17th, 2015, from the Jiuquan Satellite Launch Center of China. The major scientific objective of DAMPE mission is indirect searching for dark matter by observing high energy primary cosmic rays, especially positrons/electrons and gamma rays with an energy range from 5 GeV to 10 TeV. The BGO (Bismuth Germanate Oxide) calorimeter, which is a critical sub-detector of DAMPE payload, was developed for measuring the energy of cosmic particles, distinguishing positrons/electrons and gamma rays from hadron background, and providing trigger information. It is composed of 308 BGO crystal logs, with the size of 2.5cm*2.5cm*60cm for each log to form a total absorption electromagnetic calorimeter. All the BGO logs are stacked in 14 layers, with each layer consisting of 22 BGO crystal logs and each log is viewed by two Hamamatsu R5610A PMTs (photomultiplier tubes), from both sides respectively. Each PMT incorporates a three dynode pick off to achieve a large dynamic range, which results in 616 PMTs and 1848 signal channels. The main function of readout electronics system, which consists of 16 FEE(Front End Electronics) modules, is to precisely measure the charge of PMT signals and providing "hit" signals. The hit signals are sent to the trigger module of PDPU (Payload Data Process Unit) to generate triggers for the payload. The calibration of the BGO calorimeter is composed of pedestal testing and electronic linear scale, which are executed frequently in the space after launching. The data of the testing is transmitted to ground station in the form of scientific data. The monitor status consists of temperature, current and status words of the FEE, which are measured and recorded every 16 seconds and packed in the engineering data, then transmitted to ground station. The status of the BGO calorimeter can be evaluated by the calibration

  11. Concepts for a Muon Accelerator Front-End

    Energy Technology Data Exchange (ETDEWEB)

    Stratakis, Diktys [Fermilab; Berg, Scott [Brookhaven; Neuffer, David [Fermilab

    2017-03-16

    We present a muon capture front-end scheme for muon based applications. In this Front-End design, a proton bunch strikes a target and creates secondary pions that drift into a capture channel, decaying into muons. A series of rf cavities forms the resulting muon beams into a series of bunches of differerent energies, aligns the bunches to equal central energies, and initiates ionization cooling. We also discuss the design of a chicane system for the removal of unwanted secondary particles from the muon capture region and thus reduce activation of the machine. With the aid of numerical simulations we evaluate the performance of this Front-End scheme as well as study its sensitivity against key parameters such as the type of target, the number of rf cavities and the gas pressure of the channel.

  12. Integrated input protection against discharges for Micro Pattern Gas Detectors readout ASICs

    International Nuclear Information System (INIS)

    Fiutowski, T.; Dąbrowski, W.; Koperny, S.; Wiącek, P.

    2017-01-01

    Immunity against possible random discharges inside active detector volume of MPGDs is one of the key aspects that should be addressed in the design of the front-end electronics. This issue becomes particularly critical for systems with high channel counts and high density readout employing the front-end electronics built as multichannel ASICs implemented in modern CMOS technologies, for which the breakdown voltages are in the range of a few Volts. The paper presents the design of various input protection structures integrated in the ASIC manufactured in a 350 nm CMOS process and test results using an electrical circuit to mimic discharges in the detectors.

  13. Self-calibrating quadrature mixing front-end for SDR

    CSIR Research Space (South Africa)

    De Witt, JJ

    2008-01-01

    Full Text Available ]. True SDR, however, implies a hardware radio front-end that is able to cope with different carrier frequencies and bandwidth requirements of various communication standards. The quadrature mixing front-end of zero-IF and digital low-IF transceivers... complex baseband message signal m(t) = mI(t) + jmQ(t), with frequency- domain representation M(f), are passed through these filters, the resulting signal, M ′(f), is given by M ′(f) = MI(f)HI,M (f) + jMQ(f)HQ,M (f). (1) After some algebraic...

  14. All-Dielectric Photonic-Assisted Radio Front-End Technology

    Science.gov (United States)

    Ayazi, Hossein Ali

    The threats to civil society posed by high-power electromagnetic weapons are viewed as a grim but real possibility in the world after 11 September 2001. These weapons produce a power surge capable of destroying or damaging sensitive circuitry in electronic systems. Unfortunately, the trend towards circuits with smaller sizes and voltages renders modern electronics highly susceptible to such damage. Radiofrequency communication systems are particularly vulnerable, because the antenna provides a direct port of entry for electromagnetic radiation. In this work, we present a novel type of radiofrequency receiver front end featuring a complete absence of electronic circuitry and metal interconnects, the traditional 'soft spots' of a conventional radiofrequency receiver. The device exploits a dielectric resonator antenna to capture and deliver the radiofrequency signal onto a whispering-gallery mode electro-optic field sensor. The dielectric approach has an added benefit in that it reduces the physical size of the front end, an important benefit in mobile applications.

  15. Low Background Signal Readout Electronics for the MAJORANA DEMONSTRATOR

    Energy Technology Data Exchange (ETDEWEB)

    Guinn, I. [University of Washington, Seattle; Abgrall, N. [Lawrence Berkeley National Laboratory (LBNL); Arnquist, I. J. [Pacific Northwest National Laboratory (PNNL); Avignone, III, F. T. [University of South Carolina/Oak Ridge National Laboratory (ORNL); Baldenegro-Barrera, C. X. [Oak Ridge National Laboratory (ORNL); Barabash, A.S. [Institute of Theoretical & Experimental Physics (ITEP), Moscow, Russia; Bertrand, F. E. [Oak Ridge National Laboratory (ORNL); Bradley, A. W. [Lawrence Berkeley National Laboratory (LBNL); Brudanin, V. [Joint Institute for Nuclear Research, Dubna, Russia; Busch, M. [Duke University/TUNL; Buuck, M. [University of Washington, Seattle; Byram, D. [University of South Dakota; Caldwell, A. S. [South Dakota School of Mines and Technology; Chan, Y-D [Lawrence Berkeley National Laboratory (LBNL); Christofferson, C. D. [South Dakota School of Mines and Technology; Cuesta, C [University of Washington, Seattle; Detwiler, J. A. [University of Washington, Seattle; Efremenko, M. [University of Tennessee, Knoxville (UTK); Ejiri, H. [Osaka University, Japan; Elliott, S. R. [Los Alamos National Laboratory (LANL); Galindo-Uribarri, A. [Oak Ridge National Laboratory (ORNL); Gilliss, T. [Univ. North Carolina-Chapel Hill/Triangle Univ. Nucl. Lab., Durham, NC; Giovanetti, G. K. [University of North Carolina / Triangle Universities Nuclear Lababoratory, Durham; Goett, J [Los Alamos National Laboratory (LANL); Green, M. P. [Oak Ridge National Laboratory (ORNL); Gruszko, J [University of Washington, Seattle; Guiseppe, V E [University of South Carolina, Columbia; Henning, R. [University of North Carolina / Triangle Universities Nuclear Lababoratory, Durham; Hoppe, E.W. [Pacific Northwest National Laboratory (PNNL); Howard, S. [South Dakota School of Mines and Technology; Howe, M. A. [University of North Carolina / Triangle Universities Nuclear Lababoratory, Durham; Jasinski, B R [University of South Dakota; Keeter, K.J. [Black Hills State University, Spearfish, South Dakota; Kidd, M. F. [Tennessee Technological University (TTU); Konovalov, S.I. [Institute of Theoretical & Experimental Physics (ITEP), Moscow, Russia; Kouzes, R. T. [Pacific Northwest National Laboratory (PNNL); LaFerriere, B. D. [Pacific Northwest National Laboratory (PNNL); Leon, J. [University of Washington, Seattle; MacMullin, J. [University of North Carolina / Triangle Universities Nuclear Lababoratory, Durham; Martin, R. D. [University of South Dakota; Meijer, S. J. [University of North Carolina / Triangle Universities Nuclear Lababoratory, Durham; Mertens, S. [Lawrence Berkeley National Laboratory (LBNL); Orrell, J. L. [Pacific Northwest National Laboratory (PNNL); O' Shaughnessy, C. [Univ. North Carolina-Chapel Hill/Triangle Univ. Nucl. Lab., Durham, NC; Poon, A.W.P. [Lawrence Berkeley National Laboratory (LBNL); Radford, D. C. [Oak Ridge National Laboratory (ORNL); Rager, J. [Univ. North Carolina-Chapel Hill/Triangle Univ. Nucl. Lab., Durham, NC; Rielage, K. [Los Alamos National Laboratory (LANL); Robertson, R.G.H. [University of Washington, Seattle; Romero-Romero, E. [University of Tennessee, Knoxville, (UTK)/Oak Ridge National Lab (ORNL); Shanks, B. [Univ. North Carolina-Chapel Hill/Triangle Univ. Nucl. Lab., Durham, NC; Shirchenko, M. [Joint Institute for Nuclear Research, Dubna, Russia; Snyder, N [University of South Dakota; Suriano, A. M. [South Dakota School of Mines and Technology; Tedeschi, D [University of South Carolina, Columbia; Trimble, J. [Univ. North Carolina-Chapel Hill/Triangle Univ. Nucl. Lab., Durham, NC; Varner, R. L. [Oak Ridge National Laboratory (ORNL); Vasilyev, S. [Joint Institute for Nuclear Research, Dubna, Russia; Vetter, K. [University of California/Lawrence Berkeley National Laboratory (LBNL); Vorren, K. [University of North Carolina / Triangle Universities Nuclear Lababoratory, Durham; et al.

    2015-01-01

    The MAJORANA Collaboration will seek neutrinoless double beta decay (0 nu beta beta) in Ge-76 using isotopically enriched p-type point contact (PPC) high purity Germanium (HPGe) detectors. A tonne-scale array of HPGe detectors would require background levels below 1 count/ROI-tonne-year in the 4 keV region of interest (ROI) around the 2039 keV Q-value of the decay. In order to demonstrate the feasibility of such an experiment, the MAJORANA DEMONSTRATOR, a 40 kg HPGe detector array, is being constructed with a background goal of <3 counts/ROI-tonne-year, which is expected to scale down to <1 count/ROI-tonne-year for a tonne-scale experiment. The signal readout electronics, which must be placed in close proximity to the detectors, present a challenge toward reaching this background goal. This talk will discuss the materials and design used to construct signal readout electronics with low enough backgrounds for the MAJORANA DEMONSTRATOR.

  16. Business modelling in the fuzzy front end of innovation

    NARCIS (Netherlands)

    Limonard, A.J.P.; Berkers, F.T.H.M.; Niamut, O.A.; Bachet, T.T.; Reuver, M. de

    2011-01-01

    In this paper we address the techno-economic dilemma in the fuzzy front end of R&D consortia: how to bridge the gap between the lack of knowledge on future demand for a technology and the need to make design decisions. The problem in these types of collaborations that the business interests to

  17. PACE3 - front-end chip for the CMS Preshower

    CERN Multimedia

    Aspel, Paul

    2003-01-01

    This is PACE3 which is the front-end chip for the CMS Preshower. In fact PACE3 is the combination of two ASICs called Delta3 and PACEAM3. Delta3 is on the left and PACEAM3 is on the right. The two ASICs are bonded together and then packaged within a single 196 pin fpBGA package.

  18. Calibration method for direct conversion receiver front-ends

    Directory of Open Access Journals (Sweden)

    R. Müller

    2008-05-01

    Full Text Available Technology induced process tolerances in analog circuits cause device characteristics different from specification. For direct conversion receiver front-ends a system level calibration method is presented. The malfunctions of the devices are compensated by tuning dominant circuit parameters. Thereto optimization techniques are applied which use measurement values and special evaluation functions.

  19. FACILITATING RADICAL FRONT-END INNOVATION THROUGH TARGETED HR PRACTICES

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2017-01-01

    study of the Danish pharmaceutical company, H. Lundbeck A/S, and explorative studies of seven European and American pharmaceutical and biotech companies. The study aims to show how companies can apply HR practices in ways that actively supports the development of radical front end innovation. The value...

  20. Managing Front-End Innovation through Idea Markets at Novozymes

    DEFF Research Database (Denmark)

    Lauto, Giancarlo; Valentin, Finn; Hatzack, Frank

    2013-01-01

    Online collaboration is a powerful tool for boosting idea generation in large corporations. However, management may experience an overload of proposals from employees. To improve front-end innovation, the Danish industrial biotech company Novozymes implemented an internal idea competition in whic...

  1. An open-loop front-end stage with signal compression capability and improved PSRR for mini-SDD pixel detectors

    Science.gov (United States)

    Grande, A.; Fiorini, C.; Erdinger, F.; Fischer, P.; Porro, M.

    2017-12-01

    In this work we present the design and the experimental characterization of a front-end stage for X-ray pixel sensors. Our study was carried out in the framework of the DSSC detector development for the European XFEL (X-ray Free Electron Laser). The DSSC detector is going to be used in photon science applications at the European XFEL GmbH in Hamburg, Germany, and must be able to cope with an image frame rate up to 4.5 MHz. Moreover, the single photon sensitivity and a dynamic range up to 104 photons/pixel/pulse, with a photon energy of 1 keV, is required at the same time. Therefore, to achieve these requirement the front-end must provide a non-linear amplification. The non-linear response is obtained with a simple circuit that pushes the input PMOSFET into triode region as the input signal increases. However, since the readout ASIC has more than 4000 channels operating in parallel, particular care was devoted to the robustness of the implemented solution, especially with respect to power supply rejection ratio and crosstalk among channels.

  2. Complementary bipolar application specific analog semicustom array, intended to implement front-end units

    CERN Document Server

    Atkin, E; Kondratenko, S; Maslennikov, V; Meshcheriakov, V; Mishin, Yu; Volkov, Yu

    2002-01-01

    The structure of an analog semicustom array, intended to implement front-end electronics ICs on its basis, is considered. The features of this array are: implementation with an inexpensive bipolar process despite containing an equal number of NPN and PNP structures with well matched characteristics, supply voltages from 1.5 V to 15 V, transistor current gains Bst~100 and unity gain frequencies Ft > 3 GHz at collector currents of (100...300) mu A, high- and low-ohmic resistors, MOS capacitors, minimum two variable plating levels available. Specific circuit diagrams and parameters of the front-end electronics ICs, created on the basis of the considered array, are presented. The results of their tests are given. (4 refs).

  3. Preliminary cleaning tests on candidate materials for APS beamline and front end UHV components

    International Nuclear Information System (INIS)

    Nielsen, R.; Kuzay, T.M.

    1992-01-01

    Comparative cleaning tests have been done on four candidate materials for use in APS beamline and front-end vacuum components. These materials are 304 SS, 304L SS, OFHC copper, and Glidcop* (Cu-Al 2 O 3 )- Samples of each material were prepared and cleaned using two different methods. After cleaning, the sample surfaces were analyzed using ESCA (Electron Spectography for Chemical Analysis). Uncleaned samples were used as a reference. The cleaning methods and surface analysis results are further discussed

  4. Design and characterization of integrated front-end transistors in a micro-strip detector technology

    International Nuclear Information System (INIS)

    Simi, G.; Angelini, C.; Batignani, G.; Bettarini, S.; Bondioli, M.; Boscardin, M.; Bosisio, L.; Dalla Betta, G.-F.; Dittongo, S.; Forti, F.; Giorgi, M.; Gregori, P.; Manghisoni, M.; Morganti, M.; U. Pignatel, G.; Ratti, L.; Re, V.; Rizzo, G.; Speziali, V.; Zorzi, N.

    2002-01-01

    We present the developments in a research program aimed at the realization of silicon micro-strip detectors with front-end electronics integrated in a high resistivity substrate to be used in high-energy physics, space and medical/industrial imaging applications. We report on the fabrication process developed at IRST (Trento, Italy), the characterization of the basic wafer parameters and measurements of the relevant working characteristics of the integrated transistors and related test structures

  5. Electron spin manipulation and readout through an optical fiber

    Science.gov (United States)

    Fedotov, I. V.; Doronina-Amitonova, L. V.; Voronin, A. A.; Levchenko, A. O.; Zibrov, S. A.; Sidorov-Biryukov, D. A.; Fedotov, A. B.; Velichansky, V. L.; Zheltikov, A. M.

    2014-07-01

    The electron spin of nitrogen--vacancy (NV) centers in diamond offers a solid-state quantum bit and enables high-precision magnetic-field sensing on the nanoscale. Implementation of these approaches in a fiber format would offer unique opportunities for a broad range of technologies ranging from quantum information to neuroscience and bioimaging. Here, we demonstrate an ultracompact fiber-optic probe where a diamond microcrystal with a well-defined orientation of spin quantization NV axes is attached to the fiber tip, allowing the electron spins of NV centers to be manipulated, polarized, and read out through a fiber-optic waveguide integrated with a two-wire microwave transmission line. The microwave field transmitted through this line is used to manipulate the orientation of electron spins in NV centers through the electron-spin resonance tuned by an external magnetic field. The electron spin is then optically initialized and read out, with the initializing laser radiation and the photoluminescence spin-readout return from NV centers delivered by the same optical fiber.

  6. 40 CFR 63.492 - Batch front-end process vents-reporting requirements.

    Science.gov (United States)

    2010-07-01

    ... recorded under § 63.491(e)(3) when the batch front-end process vent is diverted away from the control... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents-reporting... Batch front-end process vents—reporting requirements. (a) The owner or operator of a batch front-end...

  7. Trigger readout electronics upgrade for the ATLAS Liquid Argon Calorimeters

    Science.gov (United States)

    Dinkespiler, B.

    2017-09-01

    The upgrade of the Large Hadron Collider (LHC) scheduled for the 2019-2020 shut-down period, referred to as Phase-I upgrade, will increase the instantaneous luminosity to about three times the design value. Since the current ATLAS trigger system does not allow sufficient increase of the trigger rate, an improvement of the trigger system is required. The Liquid Argon (LAr) Calorimeter read-out will therefore be modified to deliver digital trigger signals with a higher spatial granularity in order to improve the identification efficiencies of electrons, photons, tau, jets and missing energy, at high background rejection rates at the Level-1 trigger. The new trigger signals will be arranged in 34000 so-called Super Cells which achieves 5-10 times better granularity than the trigger towers currently used and allows an improved background rejection. The readout of the trigger signals will process the signal of the Super Cells at every LHC bunch-crossing at 12-bit precision and a frequency of 40 MHz. The data will be transmitted to the Back End using a custom serializer and optical converter and 5.12 Gb/s optical links. In order to verify the full functionality of the future Liquid Argon trigger system, a demonstrator set-up has been installed on the ATLAS detector and is operated in parallel to the regular ATLAS data taking during the LHC Run-2 in 2015 and 2016. Noise level and linearity on the energy measurement have been verified to be within our requirements. In addition, we have collected data from 13 TeV proton collisions during the LHC 2015 and 2016 runs, and have observed real pulses from the detector through the demonstrator system. The talk will give an overview of the Phase-I Upgrade of the ATLAS Liquid Argon Calorimeter readout and present the custom developed hardware including their role in real-time data processing and fast data transfer. This contribution will also report on the performance of the newly developed ASICs including their radiation tolerance

  8. Infrared readout electronics; Proceedings of the Meeting, Orlando, FL, Apr. 21, 22, 1992

    Science.gov (United States)

    Fossum, Eric R.

    The present volume on IR readout electronics discusses cryogenic readout using silicon devices, cryogenic readout using III-V and LTS devices, multiplexers for higher temperatures, and focal-plane signal processing electronics. Attention is given to the optimization of cryogenic CMOS processes for sub-10-K applications, cryogenic measurements of aerojet GaAs n-JFETs, inP-based heterostructure device technology for ultracold readout applications, and a three-terminal semiconductor-superconductor transimpedance amplifier. Topics addressed include unfulfilled needs in IR astronomy focal-plane readout electronics, IR readout integrated circuit technology for tactical missile systems, and radiation-hardened 10-bit A/D for FPA signal processing. Also discussed are the implementation of a noise reduction circuit for spaceflight IR spectrometers, a real-time processor for staring receivers, and a fiber-optic link design for INMOS transputers.

  9. The VFAT3-Comm-Port: a complete communication port for front-end ASICs intended for use within the high luminosity radiation environments of the LHC

    International Nuclear Information System (INIS)

    Dabrowski, M.; Aspell, P.; Bonacini, S.; Ciaglia, D.; Kloukinas, K.; Lentdecker, G. De; Robertis, G. De; Kupiainen, M.; Talvitie, J.; Tuuva, T.; Leroux, P.; Tavernier, F.

    2015-01-01

    This paper presents the VFAT3 Comm-Port (V3CP), which offers a single port for all communication to and from a front-end ASIC within the HL-LHC environment. This includes synchronization to the LHC clock, slow control communication, the execution of fast control commands and the readout of data

  10. Alpha-particle detection based on the BJT detector and simple, IC-based readout electronics

    Energy Technology Data Exchange (ETDEWEB)

    Rovati, L; Bonaiuti, M [Dipartimento di Ingegneria dell' Informazione, Universita di Modena e Reggio Emilia, Modena (Italy); Bettarini, S [Dipartimento di Fisica, Universita di Pisa and INFN Pisa, Pisa (Italy); Bosisio, L [Dipartimento di Fisica, Universita di Trieste and INFN Trieste, Trieste (Italy); Dalla Betta, G-F; Tyzhnevyi, V [Dipartimento di Ingegneria e Scienza dell' Informazione, Universita di Trento e INFN Trento, Trento (Italy); Verzellesi, G [Dipartimento di Scienze e Metodi dell' Ingegneria, Universita di Modena e Reggio Emilia and INFN Trento, Reggio Emilia (Italy); Zorzi, N, E-mail: giovanni.verzellesi@unimore.i [Fondazione Bruno Kessler (FBK), Trento (Italy)

    2009-11-15

    In this paper we propose a portable instrument for alpha-particle detection based on a previously-developed BJT detector and a simple, IC-based readout electronics. Experimental tests of the BJT detector and readout electronics are reported. Numerical simulations are adopted to predict the performance enhancement achievable with optimized BJT detectors.

  11. Alpha-particle detection based on the BJT detector and simple, IC-based readout electronics

    International Nuclear Information System (INIS)

    Rovati, L; Bonaiuti, M; Bettarini, S; Bosisio, L; Dalla Betta, G-F; Tyzhnevyi, V; Verzellesi, G; Zorzi, N

    2009-01-01

    In this paper we propose a portable instrument for alpha-particle detection based on a previously-developed BJT detector and a simple, IC-based readout electronics. Experimental tests of the BJT detector and readout electronics are reported. Numerical simulations are adopted to predict the performance enhancement achievable with optimized BJT detectors.

  12. The Role of Devices in Staging Front End Innovation

    DEFF Research Database (Denmark)

    Clausen, Christian; Yoshinaka, Yutaka

    2009-01-01

    in the innovative process of product development. The sole reliance on formalised models of planning, and rigid Stage-Gate models for product-based innovations in industry is seen to be wanting in this pursuit. What remains unaddressed is the role of models and other devices such as representations of users...... or market and technological opportunities in the innovative process. In this respect, models are not neutral but offer certain framings, contribute translations and act as sensemaking devices.......This paper addresses Front End Innovation as an object for the management and staging of innovation processes. We examine the role which devices play in the managing of Front End Innovation, with inspiration from Science and Technology Studies (STS). The paper contributes to a new understanding...

  13. Flexible Frequency Discrimination Subsystems for Reconfigurable Radio Front Ends

    Directory of Open Access Journals (Sweden)

    Carey-Smith Bruce E

    2005-01-01

    Full Text Available The required flexibility of the software-defined radio front end may currently be met with better overall performance by employing tunable narrowband circuits rather than pursuing a truly wideband approach. A key component of narrowband transceivers is appropriate filtering to reduce spurious spectral content in the transmitter and limit out-of-band interference in the receiver. In this paper, recent advances in flexible, frequency-selective, circuit components applicable to reconfigurable SDR front ends are reviewed. The paper contains discussion regarding the filtering requirements in the SDR context and the use of intelligent, adaptive control to provide environment-aware frequency discrimination. Wide tuning-range frequency-selective circuit elements are surveyed including bandpass and bandstop filters and narrowband tunable antennas. The suitability of these elements to the mobile wireless SDR environment is discussed.

  14. Front-end IC design for intravascular ultrasound imaging

    OpenAIRE

    Yamaner, Yalçın Feysel; Yamaner, Yalcin Feysel; Cenkeramaddi, Linga Reddy; Bozkurt, Ayhan

    2008-01-01

    Capacitive micromachined ultrasonic transducers(cMUT) technology is a new trend for intravascular ultrasound (IVUS) imaging. Large bandwidth, high sensitivity and compatibility to CMOS processes makes the cMUT a better choice compared to the conventional piezoelectric transducer. To exploit the merits of cMUT technology, an accurately designed front end circuit is required. The circuit functions as an output pulse driver for the generation of the acoustic signal and buffers the return echo. F...

  15. Exploring the front-end of project management

    OpenAIRE

    Edkins, A. J.; Geraldi, J.; Morris, P.; Smith, A.

    2013-01-01

    This paper is a multi-case study exploratory investigation into the earliest stages of projects and their management. We refer to this throughout the paper as the ‘front-end’. We provide a definition of this phase of the project life cycle and conduct a literature review of the various topics that would suggest themselves to be apposite to the front-end. This includes governance and strategy; requirements and technology; estimating; risk and value; people and learning and development. Followi...

  16. Spike timing precision in the visual front-end

    OpenAIRE

    Borghuis, B.G. (Bart Gerard)

    2003-01-01

    This thesis describes a series of investigations into the reliability of neural responses in the primary visual pathway. The results described in subsequent chapters are primarily based on extracellular recordings from single neurons in anaesthetized cats and area MT of an awake monkey, and computational model analysis. Comparison of spike timing precision in recorded and Poisson-simulated spike trains shows that spike timing in the front-end visual system is considerably more precise than on...

  17. Frequency to Voltage Converter Analog Front-End Prototype

    Science.gov (United States)

    Mata, Carlos; Raines, Matthew

    2012-01-01

    The frequency to voltage converter analog front end evaluation prototype (F2V AFE) is an evaluation board designed for comparison of different methods of accurately extracting the frequency of a sinusoidal input signal. A configurable input stage is routed to one or several of five separate, configurable filtering circuits, and then to a configurable output stage. Amplifier selection and gain, filter corner frequencies, and comparator hysteresis and voltage reference are all easily configurable through the use of jumpers and potentiometers.

  18. Development and characterisation of a front-end ASIC for macro array of photo-detectors of large dimensions

    International Nuclear Information System (INIS)

    Conforti Di Lorenzo, S.

    2010-10-01

    The coverage of large areas of photo-detection is a crucial element of experiments studying high energy atmospheric cosmic showers and neutrinos from different sources. The objective of this project is to realize big detectors using thousands of photomultipliers (PMT). The project proposes to segment the large surface of photo-detection into macro pixels consisting of an array of 16 PMT of 12 inches (2*2 m 2 ), connected to an autonomous front-end electronics which works in without-trigger data acquisition mode placed near the array. This is possible thanks to the microelectronics progress that allows to integrate the readout and the signal processing, of all the multipliers, in the same circuit (ASIC) named PARISROC (Photomultiplier Array Integrated ins SiGe Read Out Chip). The ASIC must only send out the digital data by network to the surface central data storage. The PARISROC chip made in AM's Silicon Germanium (SiGe) 0.35 μm technology, integrates 16 independent channels for each PMT of the array, providing charge and time measurements. The first prototype of PARISROC chip has a total surface of 19 mm 2 . The ASIC measurements have led to the realization of a second prototype. Important measurements were performed in terms of noise, dynamic range, readout frequency (from 10 MHz to 40 MHz), time measurements (TDC improvements) and charge measurements (Slow shaper improvements). This new prototype of PARISROC-2 has been tested and the characterisation has shown a good overall behavior and the verification of the improvements. (author)

  19. Optimized capture section for a muon accelerator front end

    Directory of Open Access Journals (Sweden)

    Hisham Kamal Sayed

    2014-07-01

    Full Text Available In a muon accelerator complex, a target is bombarded by a multi-MW proton beam to produce pions, which decay into the muons which are thereafter bunched, cooled, and accelerated. The front end of the complex captures those pions, then manipulates their phase space, and that of the muons into which they decay, to maximize the number of muons within the acceptance of the downstream systems. The secondary pion beam produced at the target is captured by a high field target solenoid that tapers down to a constant field throughout the rest of the front end. In this study we enhance the useful muon flux by introducing a new design of the longitudinal profile of the solenoid field at, and downstream of, the target. We find that the useful muon flux exiting the front end is larger when the field at the target is higher, the distance over which the field tapers down is shorter, and the field at the end of the taper is higher. We describe how the solenoid field profile impacts the transverse and longitudinal phase space of the beam and thereby leads to these dependencies.

  20. Design of the Front-End Detector Control System of the ATLAS New Small Wheels

    CERN Document Server

    Koulouris, Aimilianos; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment will be upgraded during the next LHC Long Shutdown (LS2). The flagship upgrade is the New Small Wheel (NSW), which consists of 2 disks of Muon Gas detectors. The detector technologies used are Micromegas (MM) and sTGC, providing a total of 16 layers of tracking and trigger. The Slow Control Adapter (SCA) is part of the GigaBit Transceiver (GBT) - “Radiation Hard Optical Link Project” family of chips designed at CERN, EP-ESE department, which will be used at the NSW upgrade. The SCA offers several interfaces to read analog and digital inputs, and configure front-end Readout ASICs, FPGAs, or other chips. This poster gives an overview of the system, data flow, and software developed for communicating with the SCA.

  1. A new approach to front-­‐end electronics interfacing in the ATLAS experiment

    CERN Document Server

    Borga, Andrea; The ATLAS collaboration; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Vermeulen, Jos; Ryu, Soo; Zhang, Jinlong; Anderson, John Thomas; Boterenbrood, Hendrik; Chen, Kai; Chen, Hucheng; Drake, Gary; Donszelmann, Mark; Francis, David

    2015-01-01

    For new detector and trigger systems to be installed in the ATLAS experiment after LHC Run 2 a new approach will be followed for front-end electronics interfacing. The FELIX (Front-End Link eXchange) system will interface to links connecting to front-end detector and trigger electronics instead of the RODs (ReadOut Drivers) currently used. FELIX will function as a gateway to a commodity switched network built using standard technology (either Ethernet or Infiniband). In the paper the new approach will be described and results of the demonstrator program currently in progress will be presented.

  2. Reviewed approach to defining the Active Interlock Envelope for Front End ray tracing

    Energy Technology Data Exchange (ETDEWEB)

    Seletskiy, S. [Brookhaven National Lab. (BNL), Upton, NY (United States); Shaftan, T. [Brookhaven National Lab. (BNL), Upton, NY (United States)

    2015-09-24

    To protect the NSLS-II Storage Ring (SR) components from damage from synchrotron radiation produced by insertion devices (IDs) the Active Interlock (AI) keeps electron beam within some safe envelope (a.k.a Active Interlock Envelope or AIE) in the transverse phase space. The beamline Front Ends (FEs) are designed under assumption that above certain beam current (typically 2 mA) the ID synchrotron radiation (IDSR) fan is produced by the interlocked e-beam. These assumptions also define how the ray tracing for FE is done. To simplify the FE ray tracing for typical uncanted ID it was decided to provide the Mechanical Engineering group with a single set of numbers (x,x’,y,y’) for the AIE at the center of the long (or short) ID straight section. Such unified approach to the design of the beamline Front Ends will accelerate the design process and save valuable human resources. In this paper we describe our new approach to defining the AI envelope and provide the resulting numbers required for design of the typical Front End.

  3. The HADES-RICH upgrade using Hamamatsu H12700 MAPMTs with DiRICH FEE + Readout

    Science.gov (United States)

    Patel, V.; Traxler, M.

    2018-03-01

    The High Acceptance Di-Electron Spectrometer (HADES) is operational since the year 2000 and uses a hadron blind RICH detector for electron identification. The RICH photon detector is currently replaced by Hamamatsu H12700 MAPMTs with a readout system based on the DiRICH front-end module. The electronic readout chain is being developed as a joint effort of the HADES-, CBM- and PANDA collaborations and will also be used in the photon detectors for the upcoming Compressed Baryonic Matter (CBM) and PANDA experiments at FAIR . This article gives a brief overview on the photomultipliers and their quality assurance test measurements, as well as first measurements of the new DiRICH front-end module in final configurations.

  4. Cherenkov Ring Imaging Detector front-end electronics

    International Nuclear Information System (INIS)

    Antilogus, P.; Aston, D.; Bienz, T.; Bird, F.; Dasu, S.; Dunwoodie, W.; Hallewell, G.; Kawahara, H.; Kwon, Y.; Leith, D.; Marshall, D.; Muller, D.; Nagamine, T.; Oxoby, G.; Ratcliff, B.; Rensing, P.; Schultz, D.; Shapiro, S.; Simopoulos, C.; Solodov, E.; Suekane, F.; Toge, N.; Va'Vra, J.; Williams, S.; Wilson, R.J.; Whitaker, J.S.; Bean, A.; Caldwell, D.; Duboscq, J.; Huber, J.; Lu, A.; Mathys, L.; McHugh, S.; Morrison, R.; Witherell, M.; Yellin, S.; Coyle, P.; Coyne, D.; Spencer, E.; d'Oliveira, A.; Johnson, R.A.; Martinez, J.; Nussbaum, M.; Santha, A.K.S.; Shoup, A.; Stockdale, I.; Jacques, P.; Plano, R.; Stamer, P.; Abe, K.; Hasegawa, K.; Yuta, H.

    1990-10-01

    The SLD Cherenkov Ring Imaging Detector use a proportional wire detector for which a single channel hybrid has been developed. It consists of a preamplifier, gain selectable amplifier, load driver amplifier, power switching, and precision calibrator. For this hybrid, a bipolar, semicustom integrated circuit has been designed which includes video operational amplifiers for two of the gain stages. This approach allows maximization of the detector volume, allows DC coupling, and enables gain selection. System tests show good noise performance, calibration precision, system linearity, and signal shape uniformity over the full dynamic range. 10 refs., 8 figs

  5. Scintillating Fibre Tracker Front-End Electronics for LHCb upgrade

    CERN Multimedia

    Comerma, A

    2014-01-01

    The LHCb detector will be upgraded during the next LHC shutdown in 2018/19. The tracker system will undergo major changes. Its components will be replaced by new technologies in order to cope with the increased hit occupancy and the higher radiation dose. A detector made of scintillating fibres read out by silicon photomultipliers (SiPM) is envisaged for this upgrade. Even if this technology has proven to achieve high efficiency and spatial resolution, its integration within a LHC experiment bears new challenges. The detector will consist of 12 planes of 5 to 6 layers of 250μm fibres stacked covering a total area of 5x6m^2 . The desired spacial resolution on the reconstructed hit is 100μm. SiPMs have been adapted to the detector geometry reducing the dead area between channels. A total of 64 channels are arranged in a single die with common cathode connection and channel size of 0.23x1.32mm^2 . Two dies are packaged together with only 0.25mm of dead area between them. Radiation tolerance of such devices is ...

  6. Structuring front-end innovation activities throughout strategic product planning

    Directory of Open Access Journals (Sweden)

    Thaisa Rodrigues

    Full Text Available Abstract Strategic product planning (SPP for new product development (NPD in the front-end of innovation (FEI is a great challenge for managers and practitioners. This article analyzes the structuring process of FEI activities during SPP. A research was carried out with 78 industries from both food and furniture in Brazil. Our study revealed that FEI activities are structured in an intricate network with a high level of complexity and interdependence. The large amount of activities and the complexity in structuring them denote that companies are concerned to reduce uncertainties and risks intensifying the planning phase.

  7. Instrument Front-Ends at Fermilab During Run II

    Energy Technology Data Exchange (ETDEWEB)

    Meyer, Thomas; Slimmer, David; Voy, Duane; /Fermilab

    2011-07-13

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  8. CODA : Compact front-end analog ASIC for silicon detectors

    International Nuclear Information System (INIS)

    Chandratre, V.B.; Sardesai, S.V.; Kataria, S.K.

    2004-01-01

    The paper presents the design of a front-end signal processing ASIC to be used with Silicon detectors having full depletion capacitance up to 40 pf. The ASIC channel consists of a charge amplifier, a shaper amplifier (CR-RC 3 ) and a comparator. There is provision for changing gain and polarity. The circuit has an estimated power dissipation of 16 mw. The ASIC is fabricated in 1.2 um CMOS technology. The 0pf noise is ∼400e. The chip has an area of 3 by 4 mm is packaged in 48 pin CLCC and COB option (Chip on Board). (author)

  9. High-linearity CMOS RF front-end circuits

    CERN Document Server

    Ding, Yongwang

    2005-01-01

    This monograph presents techniques to improve the performance of linear integrated circuits (IC) in CMOS at high frequencies. Those circuits are primarily used in radio-frequency (RF) front-ends of wireless communication systems, such as low noise amplifiers (LNA) and mixers in a receiver and power amplifiers (PA) in a transmitter. A novel linearization technique is presented. With a small trade-off of gain and power consumption this technique can improve the linearity of the majority of circuits by tens of dB. Particularly, for modern CMOS processes, most of which has device matching better than 1%, the distortion can be compressed by up to 40 dB at the output. A prototype LNA has been fabricated in a 0.25um CMOS process, with a measured +18 dBm IIP3. This technique improves the dynamic range of a receiver RF front-end by 12 dB. A new class of power amplifier (parallel class A&B) is also presented to extend the linear operation range and save the DC power consumption. It has been shown by both simulation...

  10. Underwater fiber-wireless communication with a passive front end

    Science.gov (United States)

    Xu, Jing; Sun, Bin; Lyu, Weichao; Kong, Meiwei; Sarwar, Rohail; Han, Jun; Zhang, Wei; Deng, Ning

    2017-11-01

    We propose and experimentally demonstrate a novel concept on underwater fiber-wireless (Fi-Wi) communication system with a fully passive wireless front end. A low-cost step-index (SI) plastic optical fiber (POF) together with a passive collimating lens at the front end composes the underwater Fi-Wi architecture. We have achieved a 1.71-Gb/s transmission at a mean BER of 4.97 × 10-3 (1.30 × 10-3 when using power loading) over a 50-m SI-POF and 2-m underwater wireless channel using orthogonal frequency division multiplexing (OFDM). Although the wireless part is very short, it actually plays a crucial role in practical underwater implementation, especially in deep sea. Compared with the wired solution (e.g. using a 52-m POF cable without the UWOC part), the proposed underwater Fi-Wi scheme can save optical wet-mate connectors that are sophisticated, very expensive and difficult to install in deep ocean. By combining high-capacity robust POF with the mobility and ubiquity of underwater wireless optical communication (UWOC), the proposed underwater Fi-Wi technology will find wide application in ocean exploration.

  11. The Readout Control Unit of the ALICE TPC

    CERN Document Server

    Lien, J A; Musa, L

    2004-01-01

    The ALICE Time Projection Chamber (TPC) is the main tracking detector of the central barrel of the ALICE (A Large Ion Collider) Experiment at the Large Hadron Collider (LHC), being constructed at CERN, Geneva. It is a 88 m$^{3}$ cylinder filled with gas and divided into two drift regions by the central electrode located at its axial center. The readout chambers of the TPC are multi-wire proportional chambers with cathode pad readout. About 570 000 pads are read-out by an electronics chain of amplification, digitalization and pre-processing. One of the challenges in designing the TPC for ALICE is the design of Front End Electronics (FEE) to cope with the data rates and the channel occupancy. The Readout Control Unit (RCU), which is presented in this work, is designed to control and monitor the Front End Electronics, and to collect and ship data to the High Level Trigger and the Data Acquisition System, via the Detector Data Link (DDL - optical fibre). The RCU must be capable of reading out up to 200 Mbytes/s f...

  12. A Low Power Rad-Hard ADC for the KID Readout Electronics, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — The proposal aims to develop a radiation hardened analog-to-digital converter (ADC) required for the Kinetic Inductance Detector (KID) readout electronics. KIDs are...

  13. Online readout and control unit for high-speed / high resolution readout of silicon tracking detectors

    International Nuclear Information System (INIS)

    Buerger, J.; Hansen, K.; Lange, W.; Nowak, T.; Prell, S.; Zimmermann, W.

    1996-09-01

    We are describing a high speed VME readout and control module developed and presently working at the H1 experiment at DESY in Hamburg. It has the capability to read out 4 x 2048 analogue data channels at sampling rates up to 10 MHz with a dynamic input range of 1 V. The nominal resolution of the A/D converters can be adjusted between 8 and 12 bit. At the latter resolution we obtain signal-to-noise ratio better than 61.4 dB at a conversion rate of 5 MSps. At this data rate all 8192 detector channels can be read out to the internal raw data memory and VME interface within about 410 μs and 510 μs, respectively. The pedestal subtracted signals can be analyzed on-line. At a raw data hit occupation of 10%, the VME readout time is 50 μs per module. Each module provides four complementary CMOS signals to control the front-end electronics and four independent sets of power supplies for analogue and digital voltages (10 V, 100 mA) to drive the front-end electronics and for the bias voltage (100 V, 1.2 mA) to assure the full functionality of the detectors and the readout. (orig.)

  14. 40 CFR 63.487 - Batch front-end process vents-reference control technology.

    Science.gov (United States)

    2010-07-01

    ... § 63.487 Batch front-end process vents—reference control technology. (a) Batch front-end process vents... process vent, reduce organic HAP emissions for the batch cycle by 90 weight percent using a control device... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents-reference...

  15. 40 CFR 63.489 - Batch front-end process vents-monitoring equipment.

    Science.gov (United States)

    2010-07-01

    ... operator of a batch front-end process vent or aggregate batch vent stream that uses a control device to... meets the conditions of § 63.490(b)(3). (i) For batch front-end process vents using a control device to... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents...

  16. 40 CFR 63.486 - Batch front-end process vent provisions.

    Science.gov (United States)

    2010-07-01

    ... sources with batch front-end process vents classified as Group 1 shall comply with the reference control... Group 2 batch front-end process vents shall comply with the applicable reference control technology... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vent provisions...

  17. A new front-end ASIC for GEM detectors with time and charge measurement capabilities

    Science.gov (United States)

    Ciciriello, F.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Marzocca, C.; Matarrese, G.; Ranieri, A.

    2016-07-01

    A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e- for a detector capacitance of 10 pF.

  18. Testing of the Front-End Hybrid Circuits for the CMS Tracker Upgrade

    CERN Document Server

    Gadek, Tomasz; Honma, Alan; Kovacs, Mark Istvan; Raymond, David Mark; Rose, Pierre

    2017-01-01

    The upgrade of the CMS tracker for the HL-LHC requires the design of new double-sensor, silicon detector modules, which implement Level 1 trigger functionality in the increased luminosity environment. These new modules will contain two different, high density front-end hybrid circuits, equipped with flip-chip ASICs, auxiliary electronic components and mechanical structures. The hybrids require qualification tests before they are assembled into modules. Test methods are proposed together with the corresponding test hardware and software. They include functional tests and signal injection in a cold environment to find possible failure modes of the hybrids under real operating conditions.

  19. FATALIC: A Dedicated Front-End ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Royer, Laurent; The ATLAS collaboration

    2015-01-01

    A front-end ASIC (FATALIC) has been developed to fulfil the requirements of the Phase 2 upgrade of the ATLAS Tile Calorimeter. This electronics performs the complete processing of the signal delivered by each PM tube. The first stage is a current conveyor which splits the 17-bit dynamic range of the input signal into three ranges. Each channel is followed by a shaper and a dedicated pipeline 12-bit ADC operating at 40MHz. The chip is developed using a 130nm CMOS technology. Measurements show a linearity better than 0.5% for low energy particles, and an ENC limited to 10 fC.

  20. Upgraded readout and trigger electronics for the ATLAS liquid argon calorimeters for future LHC running

    CERN Document Server

    Ma, Hong; The ATLAS collaboration

    2014-01-01

    The ATLAS Liquid Argon (LAr) calorimeters produce almost 200K signals that must be digitized and processed by the front-end and back-end electronics for every triggered event. Additionally, the front-end electronics sums analog signals to provide coarse-grained energy sums to the first-level (L1) trigger system. The current design was optimized for the nominal LHC luminosity of 10^34/cm^2/s. However, in future higher-luminosity phases of LHC operation, the luminosity (and associated pile-up noise) will be 3-7 times higher. An improved spatial granularity of the trigger primitives is therefore proposed, in order to improve the trigger performance at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Boards are being designed to receive the higher granularity signals, digitize them on-detector and send them via fast optical links to a new digital processing system (DPS). This applies digital filtering and identifies significant energy depositions in each trigger chan...

  1. Upgrade readout and trigger electronics for the ATLAS liquid argon calorimeters for future LHC running

    CERN Document Server

    Yamanaka, T; The ATLAS collaboration

    2014-01-01

    The ATLAS Liquid Argon (LAr) calorimeters produce almost 200K signals that must be digitized and processed by the front-end and back-end electronics at every triggered event. Additionally, the front-end electronics sums analog signals to provide coarse-grained energy sums to the first-level (L1) trigger system. The current design was optimized for the nominal LHC luminosity of 10^34 cm^-2s^-1. However, in future higher-luminosity phases of LHC operation, the luminosity (and associated pile-up noise) will be 3-7 times higher. An improved spatial granularity of the trigger primitives is therefore proposed, in order to improve the trigger performance at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Boards are being designed to receive the higher granularity signals, digitize them on-detector and send them via fast optical links to a new digital processing system (DPS). This applies digital filtering and identifies significant energy depositions in each trigger ch...

  2. Upgraded readout and trigger electronics for the ATLAS liquid argon calorimeters for future LHC running

    CERN Document Server

    Yamanaka, T; The ATLAS collaboration

    2014-01-01

    The ATLAS Liquid Argon (LAr) calorimeters produce almost 200K signals that must be digitized and processed by the front-end and back-end electronics at every triggered event. Additionally, the front-end electronics sums analog signals to provide coarse-grained energy sums to the first-level (L1) trigger system. The current design was optimized for the nominal LHC luminosity of 10^34 cm^-2s^-1. However, in future higher-luminosity phases of LHC operation, the luminosity (and associated pile-up noise) will be 3-7 times higher. An improved spatial granularity of the trigger primitives is therefore proposed, in order to improve the trigger performance at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Boards are being designed to receive the higher granularity signals, digitize them on-detector and send them via fast optical links to a new digital processing system (DPS). This applies digital filtering and identifies significant energy depositions in each trigger ch...

  3. Shielding design for the front end of the CERN SPL.

    Science.gov (United States)

    Magistris, Matteo; Silari, Marco; Vincke, Helmut

    2005-01-01

    CERN is designing a 2.2-GeV Superconducting Proton Linac (SPL) with a beam power of 4 MW, to be used for the production of a neutrino superbeam. The SPL front end will initially accelerate 2 x 10(14) negative hydrogen ions per second up to an energy of 120 MeV. The FLUKA Monte Carlo code was employed for shielding design. The proposed shielding is a combined iron-concrete structure, which also takes into consideration the required RF wave-guide ducts and access labyrinths to the machine. Two beam-loss scenarios were investigated: (1) constant beam loss of 1 Wm(-1) over the whole accelerator length and (2) full beam loss occurring at various locations. A comparison with results based on simplified approaches is also presented.

  4. Evolutionary algorithm for the neutrino factory front end design

    Energy Technology Data Exchange (ETDEWEB)

    Poklonskiy, Alexey A.; /Michigan State U.; Neuffer, David; /Fermilab

    2009-01-01

    The Neutrino Factory is an important tool in the long-term neutrino physics program. Substantial effort is put internationally into designing this facility in order to achieve desired performance within the allotted budget. This accelerator is a secondary beam machine: neutrinos are produced by means of the decay of muons. Muons, in turn, are produced by the decay of pions, produced by hitting the target by a beam of accelerated protons suitable for acceleration. Due to the physics of this process, extra conditioning of the pion beam coming from the target is needed in order to effectively perform subsequent acceleration. The subsystem of the Neutrino Factory that performs this conditioning is called Front End, its main performance characteristic is the number of the produced muons.

  5. Test and improvement of readout system based on APV25 chip for GEM detector

    International Nuclear Information System (INIS)

    Hu Shouyang; Jian Siyu; Zhou Jing; Shan Chao; Li Xinglong; Li Xia; Li Xiaomei; Zhou Yi

    2014-01-01

    Gas electron multiplier (GEM) is the most promising position sensitive gas detector. The new generation of readout electronics system includes APV25 front-end card, multi-purpose digitizer (MPD), VME controller and Linux-based acquisition software DAQ. The construction and preliminary test of this readout system were finished, and the ideal data with the system working frequency of 40 MHz and 20 MHz were obtained. The long time running test shows that the system has a very good time-stable ability. Through optimizing the software configuration and improving hardware quality, the noise level was reduced, and the signal noise ratio was improved. (authors)

  6. READOUT ELECTRONICS FOR A HIGH-RATE CSC DETECTOR

    International Nuclear Information System (INIS)

    OCONNOR, P.; GRATCHEV, V.; KANDASAMY, A.; POLYCHRONAKOS, V.; TCHERNIATINE, V.; PARSONS, J.; SIPPACH, W.

    1999-01-01

    A readout system for a high-rate muon Cathode Strip Chamber (CSC) is described. The system, planned for use in the forward region of the ATLAS muon spectrometer, uses two custom CMOS integrated circuits to achieve good position resolution at a flux of up to 2,500 tracks/cm 2 /s

  7. A 2.5 mW/ch, 50 Mcps, 10-Analog Channel, Adaptively Biased Read-Out Front-End IC With Low Intrinsic Timing Resolution for Single-Photon Time-of-Flight PET Applications With Time-Dependent Noise Analysis in 90 nm CMOS.

    Science.gov (United States)

    Cruz, Hugo; Huang, Hong-Yi; Luo, Ching-Hsing; Lee, Shuenn-Yuh

    2017-04-01

    This paper presents a 10-channel time-of-flight application-specific integrated circuit (ASIC) for positron emission tomography in a 90 nm standard CMOS process. To overcome variations in channel-to-channel timing resolution caused by mismatch and process variations, adaptive biases and a digital-to-analog converter (DAC) are utilized. The main contributions of this work are as follows. First, multistage architectures reduce the total power consumption, and detection bandwidths of analog preamplifiers and comparators are increased to 1 and 1.5 GHz, respectively, relative to those in previous studies. Second, a total intrinsic electronic timing resolution of 9.71 ps root-mean-square (RMS) is achieved (13.88 ps peak and 11.8 ps average of the 10 channels in 5 ASICs). Third, the proposed architecture reduces variations in channel-to-channel timing resolution to 2.6 bits (equivalent to 4.17 ps RMS) by calibrating analog comparator threshold levels. A 181.5 ps full-width-at-half-maximum timing resolution is measured with an avalanche photo diode and a laser setup. The power consumption is 2.5 mW using 0.5 and 1.2 V power supplies. The proposed ASIC is implemented in a 90 nm TSMC CMOS process with a total area of 3.3 mm × 2.7 mm.

  8. General-purpose readout electronics for white neutron source at China Spallation Neutron Source.

    Science.gov (United States)

    Wang, Q; Cao, P; Qi, X; Yu, T; Ji, X; Xie, L; An, Q

    2018-01-01

    The under-construction White Neutron Source (WNS) at China Spallation Neutron Source is a facility for accurate measurements of neutron-induced cross section. Seven spectrometers are planned at WNS. As the physical objectives of each spectrometer are different, the requirements for readout electronics are not the same. In order to simplify the development of the readout electronics, this paper presents a general method for detector signal readout. This method has advantages of expansibility and flexibility, which makes it adaptable to most detectors at WNS. In the WNS general-purpose readout electronics, signals from any kinds of detectors are conditioned by a dedicated signal conditioning module corresponding to this detector, and then digitized by a common waveform digitizer with high speed and high precision (1 GSPS at 12-bit) to obtain the full waveform data. The waveform digitizer uses a field programmable gate array chip to process the data stream and trigger information in real time. PXI Express platform is used to support the functionalities of data readout, clock distribution, and trigger information exchange between digitizers and trigger modules. Test results show that the performance of the WNS general-purpose readout electronics can meet the requirements of the WNS spectrometers.

  9. General-purpose readout electronics for white neutron source at China Spallation Neutron Source

    Science.gov (United States)

    Wang, Q.; Cao, P.; Qi, X.; Yu, T.; Ji, X.; Xie, L.; An, Q.

    2018-01-01

    The under-construction White Neutron Source (WNS) at China Spallation Neutron Source is a facility for accurate measurements of neutron-induced cross section. Seven spectrometers are planned at WNS. As the physical objectives of each spectrometer are different, the requirements for readout electronics are not the same. In order to simplify the development of the readout electronics, this paper presents a general method for detector signal readout. This method has advantages of expansibility and flexibility, which makes it adaptable to most detectors at WNS. In the WNS general-purpose readout electronics, signals from any kinds of detectors are conditioned by a dedicated signal conditioning module corresponding to this detector, and then digitized by a common waveform digitizer with high speed and high precision (1 GSPS at 12-bit) to obtain the full waveform data. The waveform digitizer uses a field programmable gate array chip to process the data stream and trigger information in real time. PXI Express platform is used to support the functionalities of data readout, clock distribution, and trigger information exchange between digitizers and trigger modules. Test results show that the performance of the WNS general-purpose readout electronics can meet the requirements of the WNS spectrometers.

  10. Small-Scale Readout Systems Prototype for the STAR PIXEL Detector

    Energy Technology Data Exchange (ETDEWEB)

    Szelezniak, Michal A.; Besson, Auguste; Colledani, Claude; Dorokhov, Andrei; Dulinski, Wojciech; Greiner, Leo C.; Himmi, Abdelkader; Hu, Christine; Matis, Howard S.; Ritter, Hans Georg; Rose, Andrew; Shabetai, Alexandre; Stezelberger, Thorsten; Sun, Xiangming; Thomas, Jim H.; Valin, Isabelle; Vu, Chinh Q.; Wieman, Howard H.; Winter, Marc

    2008-10-01

    A prototype readout system for the STAR PIXEL detector in the Heavy Flavor Tracker (HFT) vertex detector upgrade is presented. The PIXEL detector is a Monolithic Active Pixel Sensor (MAPS) based silicon pixel vertex detector fabricated in a commercial CMOS process that integrates the detector and front-end electronics layers in one silicon die. Two generations ofMAPS prototypes designed specifically for the PIXEL are discussed. We have constructed a prototype telescope system consisting of three small MAPS sensors arranged in three parallel and coaxial planes with a readout system based on the readout architecture for PIXEL. This proposed readout architecture is simple and scales to the size required to readout the final detector. The real-time hit finding algorithm necessary for data rate reduction in the 400 million pixel detector is described, and aspects of the PIXEL system integration into the existing STAR framework are addressed. The complete system has been recently tested and shown to be fully functional.

  11. Development of TORCH readout electronics for customised MCPs

    Science.gov (United States)

    Gao, R.; Brook, N.; Castillo García, L.; Cussans, D.; Fohl, K.; Forty, R.; Frei, C.; Gys, T.; Harnew, N.; Piedigrossi, D.; Rademacker, J.; Ros García, A.; Van Dijk, M.

    2016-04-01

    The TORCH detector is being developed for low-momentum particle identification, combining time-of-flight and Cherenkov techniques to achieve charged particle pi/K/p separation up to 10 GeV/c over a flight distance of 10m. This requires a timing resolution of 70 ps for single photons. Based on an existing scalable design, production and testing of a TORCH readout system has been undertaken over the past year, and a novel customized Micro Channel Plate (MCP) photomultiplier device with 128-channels has been instrumented. This paper will report on the development of the readout system which is being used to measure time-of-flight in a test-beam, and its performance. We will also discuss the communication and data alignment between the TORCH system and the TimePix3 telescope in order to provide track reconstruction.

  12. Compact Receiver Front Ends for Submillimeter-Wave Applications

    Science.gov (United States)

    Mehdi, Imran; Chattopadhyay, Goutam; Schlecht, Erich T.; Lin, Robert H.; Sin, Seth; Peralta, Alejandro; Lee, Choonsup; Gill, John J.; Gulkis, Samuel; Thomas, Bertrand C.

    2012-01-01

    The current generation of submillimeter-wave instruments is relatively mass and power-hungry. The receiver front ends (RFEs) of a submillimeter instrument form the heart of the instrument, and any mass reduction achieved in this subsystem is propagated through the instrument. In the current implementation, the RFE consists of different blocks for the mixer and LO circuits. The motivation for this work is to reduce the mass of the RFE by integrating the mixer and LO circuits in one waveguide block. The mixer and its associated LO chips will all be packaged in a single waveguide package. This will reduce the mass of the RFE and also provide a number of other advantages. By bringing the mixer and LO circuits close together, losses in the waveguide will be reduced. Moreover, the compact nature of the block will allow for better thermal control of the block, which is important in order to reduce gain fluctuations. A single waveguide block with a 600- GHz RFE functionality (based on a subharmonically pumped Schottky diode pair) has been demonstrated. The block is about 3x3x3 cubic centimeters. The block combines the mixer and multiplier chip in a single package. 3D electromagnetic simulations were carried out to design the waveguide circuit around the mixer and multiplier chip. The circuit is optimized to provide maximum output power and maximum bandwidth. An integrated submillimeter front end featuring a 520-600-GHz sub-harmonic mixer and a 260-300-GHz frequency tripler in a single cavity was tested. Both devices used GaAs MMIC membrane planar Schottky diode technology. The sub-harmonic mixer/tripler circuit has been tested using conventional metal-machined blocks. Measurement results on the metal block give best DSB (double sideband) mixer noise temperature of 2,360 K and conversion losses of 7.7 dB at 520 GHz. The LO input power required to pump the integrated tripler/sub-harmonic mixer is between 30 and 50 mW.

  13. Multi-anode photon-multiplier readout electronics for the LHCb ring imaging Cherenkov detectors

    CERN Document Server

    Smale, N J

    2004-01-01

    A readout system for the Ring Imaging CHerenkov (RICH) detectors of the LHCb experiment has been developed. Two detector technologies for the measurement of Cherenkov photons are considered, the Multi-Anode Photo-Multiplier Tube (MAPMT) and the Hybrid Photon Detector (HPD), both of which meet the RICH requirements. The properties of the MAPMT are evaluated using a controlled single-photon source; a pixel-to-pixel gain variation of ~3 and a typical signal to noise of ~20 is measured. The relative tube efficiency is found to be reduced by ~26 % due to the detailed focusing structure of the MAPMT device. A radiation hard application-specific integrated circuit (ASIC) chip, the Beetle1.2MA0, has been developed to capture and store signals from a pair of MAPMTs. The Beetle1.2MA0 is built on the architecture of the Beetle family that was designed for silicon strip detectors, the difference being a modified front-end amplifier. The 128 input-channels of the Beetle1.2MA0 have a charge-sensitive pre-amplifier followed...

  14. Study of the violation of the T and CP symmetries in the reactions {lambda}{sub b}{sup 0} {yields} {lambda}{sup 0} + a vector meson. Validation of the Front-end electronics for the PreShower detector of the LHCb experiment; Recherche de la violation des symetries CP et T dans les reactions {lambda}{sub b}{sup 0} {yields} {lambda}{sup 0} + un meson vecteur. Validation de l'architecture de lecteur des canaux du detecteur de pied de gerbe de l'experience LHCb

    Energy Technology Data Exchange (ETDEWEB)

    Conte, E

    2007-11-15

    This thesis probes the beauty baryon physics in the framework of the LHCb experiment. The present study deals with the {lambda}{sub b}{sup 0} {yields} {lambda}{sup 0}V decays where V is a vector meson such as J/{psi}({mu}{sup +}{mu}{sup -}), {phi}(K{sup +}K{sup -}), {omega}({pi}{sup +}{pi}{sup -}{pi}0) or the {rho}{sup 0} - {omega}{sup 0}({pi}{sup +}{pi}{sup -}) mixing. These processes allow to test independently the CP symmetry, which violation has not been observed yet in the baryonic sector, and the T symmetry, which experimental proofs are limited. Among the possible perspectives, a precise measurement of the {lambda}{sub b}{sup 0} lifetime could contribute to the resolution of the raising theoretical-experimental puzzle. A phenomenological model of the {lambda}{sub b}{sup 0} {yields} {lambda}{sup 0}V decays has been performed, from which branching ratios and angular distributions have been estimated. An advanced study of the reconstruction and the selection of these reactions by the LHCb apparatus shows that the channel {lambda}{sub b}{sup 0} {yields} {lambda}{sup 0}J/{psi} is the dominant channel on both statistics and purity aspects. The {lambda}{sub b}{sup 0} lifetime measure is the most imminent result; the constrains on asymmetries due to CP and T violation require several data taking years. Besides, an instrumental work has been achieved on the read-out electronics, called Front-End, of the experiment pre-shower. This contribution takes into account the validation of the prototype boards and the development of tools required by the qualification of the 100 production boards. (author)

  15. BORA: a front end board, with local intelligence, for the RICH detector of the Compass Collaboration

    International Nuclear Information System (INIS)

    Baum, G.; Birsa, R.; Bradamante, F.; Bressan, A.; Colavita, A.; Crespo, M.; Costa, S.; Dalla Torre, S.; Fauland, P.; Finger, M.; Fratnik, F.; Giorgi, M.; Gobbo, B.; Grasso, A.; Lamanna, M.; Martin, A.; Menon, G.; Panzieri, D.; Schiavon, P.; Tessarotto, F.; Zanetti, A.M.

    1999-01-01

    In this paper we describe the design of the re-configurable front-end boards (BORA boards) for the 82944 channel RICH-1 (Ring Imaging CHerenkov) of the Compass Collaboration (NA58). The front-end electronics controls the sample-and-hold operation after the arrival of an event trigger, acquires the analog voltages from the pre-amp VLSI and converts them into 10 bits at a rate of 20 Ms/s per analog channel. The digitized analogue values are then written into FIFOs. A subsequent operation compares the readings of each and every channel with corresponding programmable thresholds, and transmits those values larger than the threshold, together with the channel number, through an optical fiber to subsequent processing stages of the acquisition system. The overall operation of the board is controlled and supervised by a fast DSP. The availability of local intelligence allows the board to present innovative features such as: to be part of a computer network that connects several similar boards of the detector with a PC. The presence of the DSP allows testing the operability and linearity of the analog channels; and creating engineering frames containing local temperatures and voltages and transmitting the results through the network. The operator can reconfigure the hardware and software of the board by downloading programs from the PC

  16. BORA: A front end board, with local intelligence, for the rich detector of the compass collaboration

    International Nuclear Information System (INIS)

    Baum, G.; Birsa, R.; Bradamante, F.

    1999-02-01

    In this paper we describe the design of the re-configurable front-end boards (BORA boards) for the 82944 channel RICH-1 (Ring Imaging CHerenkov) of the Compass Collaboration (NA58). The front-end electronics controls the sample-and-hold operation after the arrival of an event trigger, acquires the analogue voltages from the pre-amp VLSI and converts them into 10 bits at a rate of 20 Ms/s per analogue channel. After the analog values are digitized they are written into FIFOs. A subsequent operation compares the readings of each and every channel with corresponding programmable thresholds, and transmits those values larger than the threshold, together with the channel number, through an optical fiber to subsequent processing stages of the acquisition system. The overall operation of the board is controlled and supervised by a fast DSP. The availability of local intelligence allows the board to present innovative features such as: to be part of a computer network that connects several similar boards of the detector with a PC. The presence of the DSP allows testing the operability and linearity of the analogue channels; and creating engineering frames containing local temperatures and voltages and transmitting the results through the network. The operator can reconfigure the hardware and software of the board by downloading programs from the PC. (author)

  17. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    Energy Technology Data Exchange (ETDEWEB)

    Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

    2002-03-19

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented.

  18. Instrumentation of a Track Trigger with Double Buffer Front-End Architecture

    CERN Document Server

    Wardrope, DR; The ATLAS collaboration

    2012-01-01

    The planned high luminosity upgrade for the LHC (SLHC), will increase the collision rate in the ATLAS detector by approximately a factor 5 beyond the present LHC design goal, while also increasing the number of pile-up collisions in each event by a similar factor. This means that the level-1 trigger must achieve a higher rejection factor in a more difficult environment. We describe a possible design which splits the level-1 trigger into a two-level system, where the first level, using only calorimetry and muon chambers, defines regions of interest in the tracker from which to extract information for a second, refined trigger. The use of a two-buffer front-end architecture will allow a significantly longer decision time to move data off the detector keeping the data bandwidth and buffer sizes moderate. We will describe the implementation of the scheme in the ATLAS tracker front-end electronics and the simulated performance of the system. Results on thresholds, rejection, bandwidth and trigger latency will be s...

  19. Numerical study of a magnetically insulated front-end channel for a neutrino factory

    Directory of Open Access Journals (Sweden)

    Diktys Stratakis

    2011-01-01

    Full Text Available A neutrino factory, which can deliver an intense flux of ∼10^{21} neutrinos per year from a multi-GeV stored muon beam, is seemingly the ideal tool for studying neutrino oscillations and CP violations for leptons. The front end of this facility plays a critical role in determining the number of muons that can be accepted by the downstream accelerators. Delivering peak performance requires transporting the muon beams through long sections of a beam channel containing high-gradient rf cavities and strong focusing solenoids. Here, we propose a novel scheme to improve the performance of the cavities, thereby increasing the number of muons within the acceptance of the accelerator chain. The key element of our new scheme is to apply a tangential magnetic field to the rf surfaces, thus forcing any field-emitted electrons to return to the surface before gaining enough energy to damage the cavity. We incorporate this idea into a new lattice design for a neutrino factory, and detail its performance numerically. Although our proposed front-end channel requires more rf power than conventional pillbox designs, it provides enough beam cooling and muon production to be a feasible option for a neutrino factory.

  20. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    International Nuclear Information System (INIS)

    Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

    2002-01-01

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

  1. Front-End Intelligence for Large-Scale Application-Oriented Internet-of-Things

    KAUST Repository

    Bader, Ahmed

    2016-06-14

    The Internet-of-things (IoT) refers to the massive integration of electronic devices, vehicles, buildings, and other objects to collect and exchange data. It is the enabling technology for a plethora of applications touching various aspects of our lives such as healthcare, wearables, surveillance, home automation, smart manufacturing, and intelligent automotive systems. Existing IoT architectures are highly centralized and heavily rely on a back-end core network for all decision-making processes. This may lead to inefficiencies in terms of latency, network traffic management, computational processing, and power consumption. In this paper, we advocate the empowerment of front-end IoT devices to support the back-end network in fulfilling end-user applications requirements mainly by means of improved connectivity and efficient network management. A novel conceptual framework is presented for a new generation of IoT devices that will enable multiple new features for both the IoT administrators as well as end users. Exploiting the recent emergence of software-defined architecture, these smart IoT devices will allow fast, reliable, and intelligent management of diverse IoT-based applications. After highlighting relevant shortcomings of the existing IoT architectures, we outline some key design perspectives to enable front-end intelligence while shedding light on promising future research directions.

  2. Results of the SNS front end commissioning at Berkeley Lab

    International Nuclear Information System (INIS)

    Ratti, A.; Ayers, J.J.; Doolittle, L.; Greer, J.B.; Keller, R.; Lewis, S.; Lionberger, C.; Monroy, M.; Pruyn, J.; Staples, J.W.; Syversrude, D.; Thomae, R.; Virostek, S.; Aleksandrov, A.; Shea, T.; SNS Accelerator Physics Group; SNS Beam Diagnostics Collaboration

    2002-01-01

    The Front-End Systems (FES) for the Spallation Neutron Source (SNS) project comprise an rf-driven H - ion source, an electrostatic 2-lens LEBT, a 2.5 MeV RFQ, followed by a 14-quadrupole, 4-rebuncher MEBT including traveling-wave fast choppers. The nominal 2.5 MeV H - beam has a current of 38 mA at a repetition rate of 60 Hz and 1 ms pulse length, for a macro duty-factor of 6%, and is chopped at a rate of approximately 1 MHz with a mini duty-factor of 68%. The normalized rms beam emittance at the MEBT exit, matching the first tank of a 402.5 MHz Alvarez linac, is measured to be approximately 0.3 π mm mrad. Diagnostic elements include wire scanners, BPMs, fast current monitors, a slit-harp emittance device and RFQ field monitoring probes. The results of the beam commissioning and the operation of the RFQ and diagnostic instrumentation are reported. The entire FES was shut down at LBNL at the end of May 2002 and will be recommissioned at ORNL prior to installation of the drift-tube linac

  3. Neural networks in front-end processing and control

    International Nuclear Information System (INIS)

    Lister, J.B.; Schnurrenberger, H.; Staeheli, N.; Stockhammer, N.; Duperrex, P.A.; Moret, J.M.

    1991-07-01

    Research into neural networks has gained a large following in recent years. In spite of the long term timescale of this Artificial Intelligence research, the tools which the community is developing can already find useful applications to real practical problems in experimental research. One of the main advantages of the parallel algorithms being developed in AI is the structural simplicity of the required hardware implementation, and the simple nature of the calculations involved. This makes these techniques ideal for problems in which both speed and data volume reduction are important, the case for most front-end processing tasks. In this paper we illustrate the use of a particular neural network known as the Multi-Layer Perceptron as a method for solving several different tasks, all drawn from the field of Tokamak research. We also briefly discuss the use of the Multi-Layer Perceptron as a non-linear controller in a feedback loop. We outline the type of problem which can be usefully addressed by these techniques, even before the large-scale parallel processing hardware currently under development becomes cheaply available. We also present some of the difficulties encountered in applying these networks. (author) 13 figs., 9 refs

  4. Neural networks in front-end processing and control

    International Nuclear Information System (INIS)

    Lister, J.B.; Schnurrenberger, H.; Staeheli, N.; Stockhammer, N.; Duperrex, P.A.; Moret, J.M.

    1992-01-01

    Research into neural networks has gained a large following in recent years. In spite of the long term timescale of this Artificial Intelligence research, the tools which the community is developing can already find useful applications to real practical problems in experimental research. One of the main advantages of the parallel algorithms being developed in AI is the structural simplicity of the required hardware implementation, and the simple nature of the calculations involved. This makes these techniques ideal for problems in which both speed and data volume reduction are important, the case for most front-end processing tasks. In this paper the authors illustrate the use of a particular neural network known as the Multi-Layer Perceptron as a method for solving several different tasks, all drawn from the field of Tokamak research. The authors also briefly discuss the use of the Multi-Layer Perceptron as a non-linear controller in a feedback loop. The authors outline the type of problem which can be usefully addressed by these techniques, even before the large-scale parallel processing hardware currently under development becomes cheaply available. The authors also present some of the difficulties encountered in applying these networks

  5. AC-coupled front-end for biopotential measurements.

    Science.gov (United States)

    Spinelli, Enrique Mario; Pallàs-Areny, Ramon; Mayosky, Miguel Angel

    2003-03-01

    AC coupling is essential in biopotential measurements. Electrode offset potentials can be several orders of magnitude larger than the amplitudes of the biological signals of interest, thus limiting the admissible gain of a dc-coupled front end to prevent amplifier saturation. A high-gain input stage needs ac input coupling. This can be achieved by series capacitors, but in order to provide a bias path, grounded resistors are usually included, which degrade the common mode rejection ratio (CMRR). This paper proposes a novel balanced input ac-coupling network that provides a bias path without any connection to ground, thus resulting in a high CMRR. The circuit being passive, it does not limit the differential dc input voltage. Furthermore, differential signals are ac coupled, whereas common-mode voltages are dc coupled, thus allowing the closed-loop control of the dc common mode voltage by means of a driven-right-leg circuit. This makes the circuit compatible with common-mode dc shifting strategies intended for single-supply biopotential amplifiers. The proposed circuit allows the implementation of high-gain biopotential amplifiers with a reduced number of parts, thus resulting in low power consumption. An electrocardiogram amplifier built according to the proposed design achieves a CMRR of 123 dB at 50 Hz.

  6. Front end design of smartphone-based mobile health

    Science.gov (United States)

    Zhang, Changfan; He, Lingsong; Gao, Zhiqiang; Ling, Cong; Du, Jianhao

    2015-02-01

    Mobile health has been a new trend all over the world with the rapid development of intelligent terminals and mobile internet. It can help patients monitor health in-house and is convenient for doctors to diagnose remotely. Smart-phone-based mobile health has big advantages in cost and data sharing. Front end design of it mainly focuses on two points: one is implementation of medical sensors aimed at measuring kinds of medical signal; another is acquisition of medical signal from sensors to smart phone. In this paper, the above two aspects were both discussed. First, medical sensor implementation was proposed to refer to mature measurement solutions with ECG (electrocardiograph) sensor design taken for example. And integrated chip using can simplify design. Then second, typical data acquisition architecture of smart phones, namely Bluetooth and MIC (microphone)-based architecture, were compared. Bluetooth architecture should be equipped with an acquisition card; MIC design uses sound card of smart phone instead. Smartphone-based virtual instrument app design corresponding to above acquisition architecture was discussed. In experiments, Bluetooth and MIC architecture were used to acquire blood pressure and ECG data respectively. The results showed that Bluetooth design can guarantee high accuracy during the acquisition and transmission process, and MIC design is competitive because of low cost and convenience.

  7. Toward 5G software defined radio receiver front-ends

    CERN Document Server

    Spiridon, Silvian

    2016-01-01

    This book introduces a new intuitive design methodology for the optimal design path for next-generation software defined radio front-ends (SDRXs). The methodology described empowers designers to "attack" the multi-standard environment in a parallel way rather than serially, providing a critical tool for any design methodology targeting 5G circuits and systems. Throughout the book the SDRX design follows the key wireless standards of the moment (i.e., GSM, WCDMA, LTE, Bluetooth, WLAN), since a receiver compatible with these standards is the most likely candidate for the first design iteration in a 5G deployment. The author explains the fundamental choice the designer has to make regarding the optimal channel selection: how much of the blockers/interferers will be filtered in the analog domain and how much will remain to be filtered in the digital domain. The system-level analysis the author describes entails the direct sampling architecture is treated as a particular case of mixer-based direct conversion archi...

  8. Prototype ATLAS IBL modules using the FE-I4A front-end readout chip

    Czech Academy of Sciences Publication Activity Database

    Albert, J.; Alex, M.; Alimonti, G.; Hejtmánek, Martin; Janoška, Zdenko; Korchak, Oleksandr; Popule, Jiří; Šícho, Petr; Sloboda, Michal; Tomášek, Michal; Vrba, Václav

    2012-01-01

    Roč. 7, NOV (2012), 1-45 ISSN 1748-0221 R&D Projects: GA MŠk LA08032 Institutional research plan: CEZ:AV0Z10100502 Keywords : ATLAS * upgrade * tracker * silicon * FE-I4 * planar sensors * test beam Subject RIV: BF - Elementary Particles and High Energy Physics Impact factor: 1.869, year: 2011 http://arxiv.org/abs/arXiv:1209.1906

  9. SPACIROC2: a front-end readout ASIC for the JEM-EUSO observatory

    International Nuclear Information System (INIS)

    Ahmad, S; Barrillon, P; Blin-Bondil, S; Dagoret-Campagne, S; Taille, C de La; Dulucq, F; Martin-Chassard, G; Kawasaki, Y; Miyamoto, H; Ikeda, H; Iguchi, T; Kajino, F

    2013-01-01

    The SPACIROC ASIC is designed for the JEM-EUSO observatory onboard of the International Space Station (ISS). The main goal of JEM-EUSO is to observe Extensive Air Shower (EAS) produced in the atmosphere by the passage of the high energetic extraterrestrial particles above a few 10 19 eV. A low-power, rad-hard ASIC is proposed for reading out the 64-channel Multi-Anode Photomultipliers which are going to equip the detection surface of JEM-EUSO. The two main features of this ASIC are the photon counting mode for each input and the charge-to-time (Q-to-T) conversion for the multiplexed channels. In the photon counting mode, the 100% triggering efficiency is achieved for 50 fC input charges. For the Q-to-T converter, the ASIC requires a minimum input of 2 pC. In order to comply with the strict power budget available from the ISS, the ASIC is needed to dissipate less than 1 mW/channel. The design of SPACIROC and the test results are presented in this paper.

  10. Channel Control ASIC for the CMS hadron calorimeter front end readout module

    CERN Document Server

    Yarema, R J; Boubekeur, A; Elias, J E; Shaw, T

    2002-01-01

    The Channel Control ASIC (CCA) is used along with a custom Charge Integrator and Encoder (QIE) ASIC to digitize signals from the hybrid photo diodes (HPDs) and photomultiplier tubes (PMTs) in the CMS hadron calorimeter. The CCA sits between the QIE and the data acquisition system. All digital signals to and from the QIE pass through the CCA chip. One CCA chip interfaces with two QIE channels. The CCA provides individually delayed clocks to each of the QIE chips in addition to various control signals. The QIE sends digitized PMT or HPD signals and time slice information to the CCA, which sends the data to the data acquisition system through an optical link. (2 refs) .

  11. Performance of the Electronic Readout of the ATLAS Liquid Argon Calorimeters

    CERN Document Server

    Abreu, H; Aleksa, M; Aperio Bella, L; Archambault, JP; Arfaoui, S; Arnaez, O; Auge, E; Aurousseau, M; Bahinipati, S; Ban, J; Banfi, D; Barajas, A; Barillari, T; Bazan, A; Bellachia, F; Beloborodova, O; Benchekroun, D; Benslama, K; Berger, N; Berghaus, F; Bernat, P; Bernier, R; Besson, N; Binet, S; Blanchard, JB; Blondel, A; Bobrovnikov, V; Bohner, O; Boonekamp, M; Bordoni, S; Bouchel, M; Bourdarios, C; Bozzone, A; Braun, HM; Breton, D; Brettel, H; Brooijmans, G; Caputo, R; Carli, T; Carminati, L; Caughron, S; Cavalleri, P; Cavalli, D; Chareyre, E; Chase, RL; Chekulaev, SV; Chen, H; Cheplakov, A; Chiche, R; Citterio, M; Cojocaru, C; Colas, J; Collard, C; Collot, J; Consonni, M; Cooke, M; Copic, K; Costa, GC; Courneyea, L; Cuisy, D; Cwienk, WD; Damazio, D; Dannheim, D; De Cecco, S; De La Broise, X; De La Taille, C; de Vivie, JB; Debennerot, B; Delagnes, E; Delmastro, M; Derue, F; Dhaliwal, S; Di Ciaccio, L; Doan, O; Dudziak, F; Duflot, L; Dumont-Dayot, N; Dzahini, D; Elles, S; Ertel, E; Escalier, M; Etienvre, AI; Falleau, I; Fanti, M; Farooque, T; Favre, P; Fayard, Louis; Fent, J; Ferencei, J; Fischer, A; Fournier, D; Fournier, L; Fras, M; Froeschl, R; Gadfort, T; Gallin-Martel, ML; Gibson, A; Gillberg, D; Gingrich, DM; Göpfert, T; Goodson, J; Gouighri, M; Goy, C; Grassi, V; Gray, J; Guillemin, T; Guo, B; Habring, J; Handel, C; Heelan, L; Heintz, H; Helary, L; Henrot-Versille, S; Hervas, L; Hobbs, J; Hoffman, J; Hostachy, JY; Hoummada, A; Hrivnac, J; Hrynova, T; Hubaut, F; Huber, J; Iconomidou-Fayard, L; Iengo, P; Imbert, P; Ishmukhametov, R; Jantsch, A; Javadov, N; Jezequel, S; Jimenez Belenguer, M; Ju, XY; Kado, M; Kalinowski, A; Kar, D; Karev, A; Katsanos, I; Kazarinov, M; Kerschen, N; Kierstead, J; Kim, MS; Kiryunin, A; Kladiva, E; Knecht, N; Kobel, M; Koletsou, I; König, S; Krieger, P; Kukhtin, V; Kuna, M; Kurchaninov, L; Labbe, J; Lacour, D; Ladygin, E; Lafaye, R; Laforge, B; Lamarra, D; Lampl, W; Lanni, F; Laplace, S; Laskus, H; Le Coguie, A; Le Dortz, O; Le Maner, C; Lechowski, M; Lee, SC; Lefebvre, M; Leonhardt, K; Lethiec, L; Leveque, J; Liang, Z; Liu, C; Liu, T; Liu, Y; Loch, P; Lu, J; Ma, H; Mader, W; Majewski, S; Makovec, N; Makowiecki, D; Mandelli, L; Mangeard, PS; Mansoulie, B; Marchand, JF; Marchiori, G; Martin, D; Martin-Chassard, G; Martin dit Latour, B; Marzin, A; Maslennikov, A; Massol, N; Matricon, P; Maximov, D; Mazzanti, M; McCarthy, T; McPherson, R; Menke, S; Meyer, JP; Ming, Y; Monnier, E; Mooshofer, P; Neganov, A; Niedercorn, F; Nikolic-Audit, I; Nugent, IM; Oakham, G; Oberlack, H; Ocariz, J; Odier, J; Oram, CJ; Orlov, I; Orr, R; Parsons, JA; Peleganchuk, S; Penson, A; Perini, L; Perrodo, P; Perrot, G; Perus, A; Petit, E; Pisarev, I; Plamondon, M; Poffenberger, P; Poggioli, L; Pospelov, G; Pralavorio, P; Prast, J; Prudent, X; Przysiezniak, H; Puzo, P; Quentin, M; Radeka, V; Rajagopalan, S; Rauter, E; Reimann, O; Rescia, S; Resende, B; Richer, JP; Ridel, M; Rios, R; Roos, L; Rosenbaum, G; Rosenzweig, H; Rossetto, O; Roudil, W; Rousseau, D; Ruan, X; Rudert, A; Rusakovich, N; Rusquart, P; Rutherfoord, J; Sauvage, G; Savine, A; Schaarschmidt, J; Schacht, P; Schaffer, A; Schram, M; Schwemling, P; Seguin Moreau, N; Seifert, F; Serin, L; Seuster, R; Shalyugin, A; Shupe, M; Simion, S; Sinervo, P; Sippach, W; Skovpen, K; Sliwa, R; Soukharev, A; Spano, F; Stavina, P; Straessner, A; Strizenec, P; Stroynowski, R; Talyshev, A; Tapprogge, S; Tarrade, F; Tartarelli, GF; Teuscher, R; Tikhonov, Yu; Tocut, V; Tompkins, D; Thompson, P; Tisserant, S; Todorov, T; Tomasz, F; Trincaz-Duvoid, S; Trinh, Thi N; Trochet, S; Trocme, B; Tschann-Grimm, K; Tsionou, D; Ueno, R; Unal, G; Urbaniec, D; Usov, Y; Voss, K; Veillet, JJ; Vincter, M; Vogt, S; Weng, Z; Whalen, K; Wicek, F; Wilkens, H; Wingerter-Seez, I; Wulf, E; Yang, Z; Ye, J; Yuan, L; Yurkewicz, A; Zarzhitsky, P; Zerwas, D; Zhang, H; Zhang, L; Zhou, N; Zimmer, J; Zitoun, R; Zivkovic, L

    2010-01-01

    The ATLAS detector has been designed for operation at the Large Hadron Collider at CERN. ATLAS includes electromagnetic and hadronic liquid argon calorimeters, with almost 200,000 channels of data that must be sampled at the LHC bunch crossing frequency of 40 MHz. The calorimeter electronics calibration and readout are performed by custom electronics developed specifically for these purposes. This paper describes the system performance of the ATLAS liquid argon calibration and readout electronics, including noise, energy and time resolution, and long term stability, with data taken mainly from full-system calibration runs performed after installation of the system in the ATLAS detector hall at CERN.

  12. Simple Front-End Concept for the Complex Challenges of Multi-Band Communications

    DEFF Research Database (Denmark)

    Buskgaard, Emil Feldborg; Tatomirescu, Alexandru; Barrio, Samantha Caporal Del

    2015-01-01

    This paper proposes a new architecture for mobile phone front-ends that dramatically reduces the complexity of multi-band smart phones. Traditional smart phone front-ends consist of many parallel transmit (Tx) and receive (Rx) chains each dedicated to a single band. The proposed architecture simp...... bands realistic. Current 5G investigations show that the advantages of flexible front-ends will be even bigger as technology moves toward software defined radio. \\end{abstract}...

  13. Development of radiation hard readout electronics for LHCb

    CERN Document Server

    Sexauer, Edgar; Lindenstruth, Volker

    2001-01-01

    The experiment LHCb is under development at CERN and aims to measure CP-violation in the B-Meson system at very high precision. The experiment makes use of a vertex detector that is equipped with silicon microstrip detectors. A chip suitable for the readout of this detector has been developed in a working group at the ASIC-laboratory Heidelberg. This readout chip 'Beetle-1.0' contains 128 analog input stages of a charge sensitive preamplifier, a pulse shaper and a buffer. The analog signal is fed into a comparator, from which a fast trigger signal can be derived. The following pipeline, realized as an array of gate capacitances, can be used to either store the analog output of the input amplifiers or to store the digital comparator output. External trigger signals mark events that have to be read out and the according pipeline location is stored in a derandomizing buffer. Pending events are read out from the pipeline via a charge-sensitive, resetable amplifier and an analog multiplexer, which serializes the s...

  14. A 32-channel front-end ASIC for GEM detectors used in beam monitoring applications

    Science.gov (United States)

    Ciciriello, F.; Altieri, P. R.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Lorusso, L.; Marzocca, C.; Matarrese, G.; Ranieri, A.; Stamerra, A.

    2017-11-01

    A multichannel, mixed-signal, front-end ASIC for GEM detectors, intended for beam monitoring in hadron therapy applications, has been designed and prototyped in a standard 0.35 μm CMOS technology. The analog channels are based on the classic CSA + shaper processing chain, followed by a peak detector which can work as an analog memory, to simplifiy the analog-to-digital conversion of the peak voltage of the output pulse, proportional to the energy of the detected event. The available hardware resources include an 8-bit A/D converter and a standard-cell digital part, which manages the read-out procedure, in sparse or serial mode. The ASIC is self-triggered and transfers energy and address data to the external DAQ via a fast 100 MHz LVDS link. Preliminary characterization results show that the non-linearity error is limited to 5% for a maximum input charge of about 70 fC, the measured ENC is about 1400e- and the time jitter of the trigger signal generated in response to an injected charge of 60 fC is close to 200 ps.

  15. A Test Setup for Quality Assurance of Front End Hybrids

    CERN Document Server

    Axer, Markus; Camps, Clemens; Commichau, Volker; Flügge, Günter; Franke, Torsten; Hangarter, Klaus; Ilgin, Can; Mnich, Joachim; Niehusmann, Jan; Poettgens, Michael; Schorn, Peter; Schulte, Reiner; Struczinski, Wolfgang

    2001-01-01

    The APV Readout Control (ARC) Test Setup is a compact, cost efficient test and diagnostic tool which is suited for full operation and characterisation of FE hybrids and Si-Detector modules. This note gives an overview of the construction and the features of the test facility. Based on the ARC setup and the experience gained with one prototype FE hybrid, possible quality assurance scenarios for short and long term tests of FE hybrids are also presented.

  16. AREUS - a software framework for the ATLAS Readout Electronics Upgrade Simulation

    CERN Document Server

    Horn, Philipp; The ATLAS collaboration

    2018-01-01

    The design of readout electronics for the LAr calorimeters of the ATLAS detector to be operated at the future High-Luminosity LHC (HL-LHC) requires a detailed simulation of the full readout chain in order to find optimal solutions for the analog and digital processing of the detector signals. Due to the long duration of the LAr calorimeter pulses relative to the LHC bunch crossing time, out-of-time signal pile-up needs to be taken intoaccountandrealisticpulsesequencesmustbesimulatedtogetherwiththeresponseoftheelectronics. For this purpose, the ATLAS Readout Electronics Upgrade Simulation framework (AREUS) has been developed based on the Observer design pattern to provide a fast and flexible simulation tool. Energy deposits in the LAr calorimeters from fully simulated HL-LHC collision events are taken as input. Simulated and measured analog pulse shapes proportional to these energies are then combined in discrete time series with proper representation of electronics noise. Analog-to-digital conversion, gain se...

  17. Fiber laser front end for high energy petawatt laser systems

    International Nuclear Information System (INIS)

    Dawson, J W; Messerly, M J; Phan, H; Mitchell, S; Drobshoff, A; Beach, R J; Siders, C; Lucianetti, A; Crane, J K; Barty, C J

    2006-01-01

    We are developing a fiber laser front end suitable for high energy petawatt laser systems on large glass lasers such as NIF. The front end includes generation of the pulses in a fiber mode-locked oscillator, amplification and pulse cleaning, stretching of the pulses to >3ns, dispersion trimming, timing, fiber transport of the pulses to the main laser bay and amplification of the pulses to an injection energy of 150 (micro)J. We will discuss current status of our work including data from packaged components. Design detail such as how the system addresses pulse contrast, dispersion trimming and pulse width adjustment and impact of B-integral on the pulse amplification will be discussed. A schematic of the fiber laser system we are constructing is shown in figure 1 below. A 40MHz packaged mode-locked fiber oscillator produces ∼1nJ pulses which are phase locked to a 10MHz reference clock. These pulses are down selected to 100kHz and then amplified while still compressed. The amplified compressed pulses are sent through a non-linear polarization rotation based pulse cleaner to remove background amplified spontaneous emission (ASE). The pulses are then stretched by a chirped fiber Bragg grating (CFBG) and then sent through a splitter. The splitter splits the signal into two beams. (From this point we follow only one beam as the other follows an identical path.) The pulses are sent through a pulse tweaker that trims dispersion imbalances between the final large optics compressor and the CFBG. The pulse tweaker also permits the dispersion of the system to be adjusted for the purpose of controlling the final pulse width. Fine scale timing between the two beam lines can also be adjusted in the tweaker. A large mode area photonic crystal single polarization fiber is used to transport the pulses from the master oscillator room to the main laser bay. The pulses are then amplified a two stage fiber amplifier to 150mJ. These pulses are then launched into the main amplifier

  18. Fully Integrated Biopotential Acquisition Analog Front-End IC.

    Science.gov (United States)

    Song, Haryong; Park, Yunjong; Kim, Hyungseup; Ko, Hyoungho

    2015-09-30

    A biopotential acquisition analog front-end (AFE) integrated circuit (IC) is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA) to achieve low input referred noise (IRN) and to block unwanted DC potential signals. A DC servo loop (DSL) is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL) is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL) is designed to enhance the input impedance and common mode rejection ratio (CMRR) without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL) at each CCIA stage. The biopotential AFE is fabricated using a 0.18 μm one polysilicon and six metal layers (1P6M) complementary metal oxide semiconductor (CMOS) process. The core chip size of the AFE without input/output (I/O) pads is 10.5 mm². A fourth-order band-pass filter (BPF) with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 μVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.

  19. Fully Integrated Biopotential Acquisition Analog Front-End IC

    Directory of Open Access Journals (Sweden)

    Haryong Song

    2015-09-01

    Full Text Available A biopotential acquisition analog front-end (AFE integrated circuit (IC is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA to achieve low input referred noise (IRN and to block unwanted DC potential signals. A DC servo loop (DSL is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL is designed to enhance the input impedance and common mode rejection ratio (CMRR without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL at each CCIA stage. The biopotential AFE is fabricated using a 0.18 μm one polysilicon and six metal layers (1P6M complementary metal oxide semiconductor (CMOS process. The core chip size of the AFE without input/output (I/O pads is 10.5 mm2. A fourth-order band-pass filter (BPF with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 μVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.

  20. Realization of Miniaturized Multi-/Wideband Microwave Front-Ends

    Science.gov (United States)

    Al Shamaileh, Khair A.

    The ever-growing demand toward designing microwave front-end components with enhanced access to the radio spectrum (e.g., multi-/wideband functionality) and improved physical features (e.g., miniaturized circuitry, ease and cost of fabrication) is becoming more paramount than ever before. This dissertation proposes new design methodologies, simulations, and experimental validations of passive front-ends (i.e., antennas, couplers, dividers) at microwave frequencies. The presented design concepts optimize both electrical and physical characteristics without degrading the intended performance. The developed designs are essential to the upcoming wireless technologies. The first proposed component is a compact ultra-wideband (UWB) Wilkinson power divider (WPD). The design procedure is accomplished by replacing the uniform transmission lines in each arm of the conventional single-frequency divider with impedance-varying profiles governed by a truncated Fourier series. While such non-uniform transmission lines (NTLs) are obtained through the even-mode analysis, three isolation resistors are optimized in the odd-mode circuit to achieve proper isolation and output ports matching over the frequency range of interest. The proposed design methodology is systematic, and results in single-layered and compact structures. For verification purposes, an equal split WPD is designed, simulated, and measured. The obtained results show that the input and output ports matching as well as the isolation between the output ports are below --10 dB; whereas the transmission parameters vary between --3.2 dB and --5 dB across the 3.1--10.6 GHz band. The designed divider is expected to find applications in UWB antenna diversity, multiple-input-multiple-output (MIMO) schemes, and antenna arrays feeding networks. The second proposed component is a wideband multi-way Bagley power divider (BPD). Wideband functionality is achieved by replacing the single-frequency matching uniform microstrip lines in

  1. Design and performance of the ABCD3TA ASIC for readout of silicon strip detectors in the ATLAS semiconductor tracker

    Czech Academy of Sciences Publication Activity Database

    Campabadal, F.; Fleta, C.; Key, M.; Böhm, Jan; Mikeštíková, Marcela; Šťastný, Jan

    2005-01-01

    Roč. 552, - (2005), s. 292-328 ISSN 0168-9002 R&D Projects: GA MŠk 1P04LA212 Institutional research plan: CEZ:AV0Z10100502 Keywords : front-end electronics * binary readout * silicon strip detectors * application specific integrated circuits * quality assurance Subject RIV: BF - Elementary Particles and High Energy Physics Impact factor: 1.224, year: 2005

  2. ATLAS IBL: Integration of new HW/SW readout features for the additional layer of Pixel Detector

    CERN Document Server

    Bruni, G; D’Antone, I; Dopke, J; Falchieri, D; Flick, T; Gabrielli, A; Gross-Kettner, J; Joseph, J; Krieger, N; Kugel, A; Morettini, P; Polini, A; Rizzi, M; Schroer, N C; Travaglini, R; Zannoli, S; Zoccoli, A

    2011-01-01

    An additional inner layer for the existing ATLAS Pixel Detector, called Insertable B-Layer (IBL), is under design. The front-end electronics features a new readout ASIC, named FeI4, which requires new off-detector electronics, currently realized with two VME-based boards, which implement optical I/O functionality (BOC card) and data processing functionality (ROD card), plus a timing interface module (TIM). This paper presents a proposal for the IBL readout system, mainly focusing on the ROD board.

  3. AVME readout module for multichannel ASIC characterization

    International Nuclear Information System (INIS)

    Borkar, S.P.; Lalwani, S.K.; Ghodgaonkar, M.D.; Kataria, S.K.; Reynaud, Serge; )

    2004-01-01

    Electronics Division, BARC has been working on the development of multi-channel ASIC, called SPAIR (Silicon-strip Pulse Amplifier Integrated Readout). It contains 8 channels of preamplifier, shaper and track-and-hold circuitry. Electronics Division has also actively participated in development of test setup for the front-end ASIC, called PACE, for the preshower detector of the Compact Muon Solenoid (CMS) Experiment at CERN, Geneva. PACE is a 32 channel ASIC for silicon strip detector, containing preamplifier, shaper, calibration circuitry, switched capacitor array, readout amplifier per channel and an analog multiplexer. A VME Readout Module, (VRM) is developed which can be utilized in data acquisition from ASICs like PACE and SPAIR. The VRM can also be used as the Detector Dependent Unit for digitally processing the data received from the front-end electronics on the 16-bit LVDS port. The processed, data can be read by the VME system. Thus the VRM is very useful in building an ASIC characterization system and/or the automated ASIC production testing system. It can be used also to build the applications using such ASICs. To cater to various requirements arising in future, variety of VME modules are to be developed like ADCs, DACs and D 1/0. VME interface remains a common part to all these modules. The different functional blocks of these modules can be designed and fabricated on small piggyback boards (called Test Boards) and mounted on the VRM, which provides the common VME interface. The design details and uses of VRM are presented here. (author)

  4. Search for second generation leptoquarks in $\\sqrt{s}$ = 1.8-TeV $p^-$ pbar at CDF and silicon detector readout electronics development with ATLAS

    Energy Technology Data Exchange (ETDEWEB)

    Kambara, Hisanori [Geneva U.

    1998-02-01

    In this thesis, a search for second generation leptoquark is presented. It is based on the data collected at the Collider Detector at Fermilab with the Tevatron proton-antiproton collisions of $\\sqrt{s}$ = 1.8 TeV. A total integrated luminosity of 110 pb-1 collected during runs in 1992-1995 is used. The search was performed on the charged dimuon plus dijet channel. No evidence for existence of leptoquark was found, and a new production cross section limit is set as a result of this analysis. Using the most recent theoretical calculation of pair leptoquark production [1], a new lower mass limit for second generation scalar leptoquark is extracted. The new limit excludes M(LQ2)< 202 GeV/c2. The Large Hadron Collider (LHC), a proton-proton collider with a center of mass energy ($\\sqrt{s}$) of 14 TeV, is currently under the construction at CERN. It will be utilised to extend the searches for the leptoquarks to higher mass regions. As in CDF, tracking detectors are essential to identify charged leptons decaying from leptoquarks. A silicon strip tracking detector is being developed for the ATLAS experiment. A dense and fast readout system with a good signal to noise ratio and low power consumption are required with high luminosity and short event collision interval (25 ns) expected at the LHC. A description of a prototype front-end micro-electronic chip, the ADAM, for silicon strip detector readout application is presented. Results from a complete laboratory test as well as its performance on a test beam at CERN are reported.

  5. Development of ATLAS Liquid Argon Calorimeters Readout Electronics for HL-LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00388354; The ATLAS collaboration

    2016-01-01

    The high-luminosity phase of the Large Hadron Collider will provide 5-7 times greater instantaneous and total luminosities than assumed in the original design of the ATLAS Liquid Argon Calorimeters and their readout system. An improved trigger system with a higher acceptance rate of 1 MHz and a longer latency of up to 60 micro-seconds together with a better radiation tolerance require an upgrade of the readout electronics. Concepts for the future readout of the 182,500 calorimeter channels at 40/80 MHz and 16 bit dynamic range, and the development of low-noise, low-power and high-bandwidth electronic components will be presented. These include ASIC developments towards radiation-tolerant low-noise pre-amplifiers, analog-to-digital converters up to 14 bits and low-power optical links providing transfer rates of at least 10 Gb/s per fiber.

  6. Redesign and Reconstruction of the Equipment Protection Systems for the Upgrading Front Ends and Beamlines at BSRF

    International Nuclear Information System (INIS)

    Xiong Shenshou; Tan Yinglei; Wu Xuehui

    2007-01-01

    The BEPC(Beijing Electron-Positron Collider) is upgraded to be BEPCII, a two-ring Electron-Positron collider. Due to the construction of the BEPCII and upgrade of the existing front ends and beamlines, all the existing EPSs(Equipment Protection Systems) have to be redesigned and reconstructed at BSRF. All the redesigned EPSs for the upgrading front ends and beamlines are a PLC- and SCADA-based equipment protection and control and monitoring system. The EPSs are used to protect BEPCII two storage rings vacuum against vacuum failures in a beamline, as well as to protect the front-end and beamline components from being damaged by synchrotron radiation. For the high-power wiggler beam lines, a fast movable mask is used to protect the blade of a fast-closing valve from damage when the fast-closing valve is triggered to close, which does not need to dump the electron beam running in BEPCII outer ring. In addition, all redesigned PLC- based EPSs are used to communicate with the same centralized monitoring computer to monitor a variety of parameters from all PLC- based EPS systems. The monitoring computer runs the SCADA (Supervisory Control And Data Acquisition) software with its own web server. Graphical HMI interfaces are used to display a few overall views of all front-end equipment operation status and the further detailed information for each EPS in a different pop-up window. On the web services, the SCADA-based centralized monitoring system provides a web browse function, etc. The design of the reconstructed systems is described in this paper

  7. SEU rate estimates for the ATLAS/SCT front-end ASIC

    CERN Document Server

    Eklund, L; Grigson, C; Kramberger, G; Mandic, I; Mikuz, M; Phillips, P

    2003-01-01

    We present a method of estimating the sensitivity to radiation- induced Single Event Upset (SEU) in the front-end ASICs for the ATLAS Semiconductor Tracker. The method is using ASICs of the final design with limited read-back possibilities of internal registers. Hence the measurement is adapted to utilise the event-data flow in the digital part of the ASIC to detect bit-flips. Furthermore, we report on the application of this method to estimate the SEU sensitivity. The results presented are based on data from three irradiation periods using prototype electronics hybrids and detector modules. The measurements were done with 24 GeV/c protons and 200 MeV/c pions.

  8. Radiation Protection Aspects of the Linac Coherent Light Source Front End Enclosure

    Energy Technology Data Exchange (ETDEWEB)

    Vollaire, J.; Fasso, A.; Liu, J.C.; Mao, X.S.; Prinz, A.; Rokni, S.H.; Leitner, M.Santana; /SLAC

    2010-08-26

    The Front End Enclosure (FEE) of the Linac Coherent Light Source (LCLS) is a shielding housing located between the electron dump area and the first experimental hutch. The upstream part of the FEE hosts the commissioning diagnostics for the FEL beam. In the downstream part of the FEE, two sets of grazing incidence mirror and several collimators are used to direct the beam to one of the experimental stations and reduce the bremsstrahlung background and the hard component of the spontaneous radiation spectrum. This paper addresses the beam loss assumptions and radiation sources entering the FEE used for the design of the FEE shielding using the Monte-Carlo code FLUKA. The beam containment system prevents abnormal levels of radiations inside the FEE and ensures that the beam remains in its intended path is also described.

  9. 40 CFR 63.491 - Batch front-end process vents-recordkeeping requirements.

    Science.gov (United States)

    2010-07-01

    ... combustion device to control halogenated batch front-end process vents or halogenated aggregate batch vent... periods of process or control device operation when monitors are not operating. (f) Aggregate batch vent... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents...

  10. Sustainability in the front-end of innovation at design agencies

    NARCIS (Netherlands)

    Storaker, A.; Wever, R.; Dewulf, K.; Blankenburg, D.

    2013-01-01

    In the two last decades a considerable amount of research has been conducted on the Front End of Innovation. This is the stage of the product development process where the design brief is formulated. This phase is argued to be crucial to the success of the final product. While the Front End of

  11. Tuned Optical Front-End MMIC Amplifiers for a Coherent Optical Receiver

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad; Jagd, A M

    1992-01-01

    Two low noise tuned optical front-end GaAs MESFET MMIC amplifiers for a coherent optical CPFSK (Continuous Phase Frequency Shift Keying) receiver are presented. The receiver operates at 2.5 Gbit/s at an IF of approx. 9 GHz. The front-ends are based on full-custom designed MMICs and a commercially...

  12. Development of Digital Readout Electronics for the CMS Tracker

    CERN Document Server

    Corrin, E P

    2002-01-01

    The Compact Muon Solenoid (CMS) is a general-purpose detector, based at CERN in Switzerland, designed to look for new physics in high-energy protonproton collisions provided by the Large Hadron Collider. The CMS tracker has 10 million readout channels being sampled at a rate of 40 MHz, then read out at up to 100 kHz, generating huge volumes of data; it is essential that the system can handle these rates without any of the data being lost or corrupted. The CMS tracker FED processes the data, removing pedestal and common mode-noise, and then performing hit and cluster finding. Strips below threshold are discarded, resulting in a significant reduction in data size. These zero suppressed data are stored in a buffer before being sent to the DAQ. The processing on the FEDs is done using FPGAs. Programmable logic was chosen over custom ASICs because of the lower cost, faster design and verification process, and the ability to easily upgrade the firmware at a later date. This thesis is concerned with the digital read...

  13. Performance and calibration of the CHORUS scintillating fiber tracker and opto-electronics readout system

    International Nuclear Information System (INIS)

    Annis, P.; Aoki, S.; Brunner, J.; De Jong, M.; Fabre, J.P.; Ferreira, R.; Flegel, W.; Frekers, D.; Gregoire, G.; Herin, J.; Kobayashi, M.; Konijn, J.; Lemaitre, V.; Macina, D.; Meijer Drees, R.; Meinhard, H.; Michel, L.; Mommaert, C.; Nakamura, K.; Nakamura, M.; Nakano, T.; Niwa, K.; Niu, E.; Panman, J.; Riccardi, F.; Rondeshagen, D.; Sato, O.; Stefanini, G.; Vander Donckt, M.; Vilain, P.; Wilquet, G.; Winter, K.; Wong, H.T.

    1995-01-01

    An essential component of the CERN WA95/CHORUS experiment is a scintillating fiber tracker system for precise track reconstruction of particles. The tracker design, its opto-electronics readout and calibration system are discussed. Performances of the detector are presented. (orig.)

  14. The electronic readout system used on the Mk II R.A.L. positron camera

    International Nuclear Information System (INIS)

    Stephenson, R.

    1984-06-01

    The paper describes the operating principles of the electronic readout system as used on the Mk II R.A.L. positron camera. The individual modules are described in detail, and the specifications and the performance figures for the individual units, and of the complete system are given. Some early results obtained with the full system are presented. (author)

  15. Ultra-wideband wireless receiver front-end for high-speed indoor applications

    Directory of Open Access Journals (Sweden)

    Zhe-Yang Huang

    2014-12-01

    Full Text Available Low-noise, ultra-wideband (UWB wireless receiver front-end circuits were presented in this study. A two-stage common-source low-noise amplifier with wideband input impedance matching network, an active-balun and a double-balanced down-conversion mixer were adopted in the UWB wireless receiver front-end. The proposed wireless receiver front-end circuits were implemented in 0.18 μm radio-frequency-CMOS process. The maximum down-conversion power gain of the front-end is 25.8 dB; minimum single-sideband noise figure of the front-end is 4.9 dB over complete UWB band ranging from 3.1 to 10.6 GHz. Power consumption including buffers is 39.2 mW.

  16. Readout architecture for the Pixel-Strip module of the CMS Outer Tracker Phase-2 upgrade

    CERN Document Server

    Caratelli, Alessandro; Jan Kaplon; Kloukinas, Konstantinos; Simone Scarfi

    2016-01-01

    The Outer Tracker upgrade of the Compact Muon Solenoid (CMS) experiment at CERN introduces new challenges for the front-end readout electronics. In particular, the capability of identifying particles with high transverse momentum using modules with double sensor layers requires high speed real time interconnects between readout ASICs. The Pixel-Strip module combines a pixelated silicon layer with a silicon-strip layer. Consequently, it needs two different readout ASICs, namely the Short Strip ASIC (SSA) for the strip sensor and the Macro Pixel ASIC (MPA) for the pixelated sensor. The architecture proposed in this paper allows for a total data flow between readout ASICs of $\\sim$100\\,Gbps and reduces the output data flow from 1.3\\,Tbps to 30\\,Gbps per module while limiting the total power density to below 100\\,mW/cm$^2$. In addition a system-level simulation framework of all the front-end readout ASICs is developed in order to verify the data processing algorithm and the hardware implementation allowing mult...

  17. Dual stage beamforming in the absence of front-end receive focusing

    Science.gov (United States)

    Bera, Deep; Bosch, Johan G.; Verweij, Martin D.; de Jong, Nico; Vos, Hendrik J.

    2017-08-01

    Ultrasound front-end receive designs for miniature, wireless, and/or matrix transducers can be simplified considerably by direct-element summation in receive. In this paper we develop a dual-stage beamforming technique that is able to produce a high-quality image from scanlines that are produced with focused transmit, and simple summation in receive (no delays). We call this non-delayed sequential beamforming (NDSB). In the first stage, low-resolution RF scanlines are formed by simple summation of element signals from a running sub-aperture. In the second stage, delay-and-sum beamforming is performed in which the delays are calculated considering the transmit focal points as virtual sources emitting spherical waves, and the sub-apertures as large unfocused receive elements. The NDSB method is validated with simulations in Field II. For experimental validation, RF channel data were acquired with a commercial research scanner using a 5 MHz linear array, and were subsequently processed offline. For NDSB, good average lateral resolution (0.99 mm) and low grating lobe levels (spread function was on average 20% smaller than that of DRF except for at depths  <30 mm and 10% larger than SASB considering all the depths. NDSB showed only a minor degradation in contrast-to-noise ratio and contrast ratio compared to DRF and SASB when measured on an anechoic cyst embedded in a tissue-mimicking phantom. In conclusion, using simple receive electronics front-end, NDSB can attain an image quality better than DRF and slightly inferior to SASB.

  18. JACoW Design of the front-end detector control system of the ATLAS New Small Wheels

    CERN Document Server

    Moschovakos, Paris

    2018-01-01

    The ATLAS experiment will be upgraded during the next LHC Long Shutdown (LS2). The flagship upgrade is the New Small Wheel (NSW) [1], which consists of 2 disks of Muon Gas detectors. The detector technologies used are Micromegas (MM) and sTGC, providing a total of 16 layers of tracking and trigger. The Slow Control Adapter (SCA) is part of the Gigabit Transceiver (GBT) - “Radiation Hard Optical Link Project” family of chips designed at CERN, EP-ESE department [2,3], which will be used at the NSW upgrade. The SCA offers several interfaces to read analogue and digital inputs, and configure front-end Readout ASICs, FPGAs, or other chips. The design of the NSW Detector Control System (DCS) takes advantage of this functionality, as described in this paper.

  19. Radio frequency single electron transistors: readout for a solid state quantum computer

    International Nuclear Information System (INIS)

    Buehler, T.M.; Reilly, D.J.; Starrett, R.P.; Brenner, R.; Hamilton, A.R.; Clark, R.G.; Court, N.A.; Dzurak, A.S.

    2002-01-01

    Full text: Quantum computers promise unprecedented computational power if they can be scaled to a large number of qubits. Essential to the operation of such a machine is readout: the determination of the final quantum state of the system. In the case of the silicon based solid state architecture proposed by Kane, readout is achieved by determining the direction of a single electron spin via the detection of a spin dependent tunneling event. This requires a highly sensitive electrometer that can detect the motion of a single electron in a timescale less than the spin relaxation time. The Radio Frequency Single Electron Transistor (RF-SET) is a device that possesses both the charge sensitivity (oq ∼ 10 -6 / √Hz), approaching the quantum limit) and fast response required to perform readout in such a system. Here we describe the fabrication and operation of transmission mode RF-SETs and discuss the application of these novel electrometers in the readout of a solid state quantum computer

  20. Upgrade for the ATLAS Tile Calorimeter Readout Electronics at the High Luminosity LHC

    CERN Document Server

    Carrio, F; The ATLAS collaboration

    2012-01-01

    The Tile Calorimeter (TileCal) is the hadronic calorimeter covering the most central region of the ATLAS experiment at LHC. I consists of about 1000 channels. The main upgrade will occur for the High Luminosity LHC phase (phase 2) scheduled around 2022. The upgrade aims at replacing the majority of the on- and off-detector electronics so that all calorimeter signals are directly digitized and sent to the off-detector electronics in the counting room. This will be done with minimum latency and maximum robustness. It will provide maximum information to the first level of the calorimeter trigger to improve the trigger efficiency as required to cope with the increased luminosity. Three options are presently being investigated for the front-end electronic upgrade. The first option is an improved version of the present system built using discrete components. The second alternative is based on the development of a dedicated ASIC, which will provide most of the functionality including the digitization. The third alte...

  1. Programmer's guide to FFE: a fast front-end data-acquisition program

    International Nuclear Information System (INIS)

    Million, D.L.

    1983-05-01

    The Large Coil Test Facility project of the Fusion Energy Division has a data acquisition system which includes a large host computer and several small, peripheral front-end computers. The front-end processors handle details of data acquisition under the control of the host and pass data back to the host for storage. Some of the front ends are known as fast front ends and are required to collect a maximum of 64,000 samples each second. This speed and other hardware constraints resulted in a need for a stand-alone, assembly language task which could be downline loaded from the host system into the fast front ends. FFE (Fast Front End) was written to satisfy this need. It was written in the PDP-11 MACRO-11 assembly language for an LSI-11/23 processor. After the host loads the task into the front end, it controls the data acquisition process with a series of commands and parameters. This Programmer's Guide describes the structure and operation of FFE in detail from a programming point of view. A companion User's guide provides more information on the use of the program from the host system

  2. Alibava : A portable readout system for silicon microstrip sensors

    CERN Document Server

    Marco-Hernández, Ricardo; Casse, G; García, C; Greenall, A; Lacasta, C; Lozano, M; Martí i García, S; Martínez, R; Miñano, M; Pellegrini, G; Smith, N A; Ullán, M

    2007-01-01

    A portable readout system for silicon microstrip sensors is currently being developed. This system uses a front-end readout chip, which was developed for the LHC experiments. The system will be used to investigate the main properties of this type of sensors and their future applications. The system is divided in two parts: a daughter board and a mother board. The first one is a small board which contains two readout chips and has fan-ins and sensor support to interface the sensors. The last one is intended to process the analogue data that comes from the readout chips and from external trigger signals, to control the whole system and to communicate with a PC via USB. The core of this board is a FPGA that controls the readout chips, a 10 bit ADC, an integrated TDC and an USB controller. This board also contains the analogue electronics to process the data that comes from the readout chips. There is also provision for an external trigger input (e.g. scintillator trigger) and a 'synchronised' trigger output for ...

  3. Wide-band low-noise distributed front-end for multi-gigabit CPFSK receivers

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad; Ebskamp, F; Pedersen, Rune Johan Skullerud

    1994-01-01

    In this paper a distributed optical front-end amplifier for a coherent optical CPFSK receiver is presented. The measured average input noise current density is 20 pA/√(Hz) in a 3-13 GHz bandwidth. This is the lowest value reported for a distributed optical front-end in this frequency range....... The front-end is tested in a system set-up at a bit rate of 2.5 Gbit/s and a receiver sensitivity of -41.5 dBm is achieved at a 10-9 bit error rate...

  4. Test results of the front-end system for the Silicon Drift Detectors of ALICE

    CERN Document Server

    Mazza, G; Anelli, G; Martínez, M I; Rotondo, F; Tosello, F; Wheadon, R

    2001-01-01

    The front-end system of the Silicon Drift Detectors (SDDs) of the ALICE experiment is made of two ASICs. The first chip performs the preamplification, temporary analogue storage and analogue-to-digital conversion of the detector signals. The second chip is a digital buffer that allows for a significant reduction of the connection from the front-end module to the outside world. In this paper, the results achieved on the first complete prototype of the front-end system for the SDDs of ALICE are presented.

  5. Charge-sensitive amplifier front-end with an nJFET and a forward-biased reset diode

    Energy Technology Data Exchange (ETDEWEB)

    Fazzi, A. [Politecnico di Milano (Italy); Jalas, P. [Univ. of Helsinki, Espoo (Finland); Rehak, P. [Brookhaven National Lab., Upton, NY (United States); Holl, P. [Max Planck Inst., Garching (Germany)

    1996-12-01

    A new configuration of a resistorless charge sensitive preamplifier with an nJFET as an input device was tested. The dc level of the input of the amplifier was kept constant by a slightly forward-biased np junction connected between the input of the amplifier and ground. A noise level of 22 root mean square (r.m.s.) electrons is measured at 295 K and 15 r.m.s. electrons at 253 K. The dynamic behavior of the amplifier is investigated with different leakage current conditions. The technological benefits and the suitability of the front-end connection for room temperature detectors, particularly multianode drift chambers, are highlighted.

  6. Electronics for the CMS muon drift tube chambers the read-out minicrate

    CERN Document Server

    Fernandez Bedoya, Cristina; Oller, Juan Carlos; Willmott, Carlos

    2005-01-01

    On the Compact Muon Solenoid (CMS) experimentat the Large Hadron Collider (LHC) at the CERN laboratory, the drift tube chambers are responsible for muon detection and precise momentum measurement. In this paper the first level of the read out electronics for these drift tube chambers is described. These drift tube chambers will be located inside the muon barrel detector in the so-called minicrates (MCs), attached to the chambers. The read out boards (ROBs) are the main component of this first level data acquisition system, and they are responsible for the time digitalization related to Level 1 Accept (L1A) trigger of the incoming signals from the front-end electronics, followed by a consequent data merging to the next stages of the data acquisition system. ROBs' architecture and functionality have been exhaustively tested, as well as their capability of operation beyond the expected environmental conditions inside the CMS detector. Due to the satisfactory results obtained, final production of ROBs and their a...

  7. Detection of electron showers in dual-readout crystal calorimeters

    International Nuclear Information System (INIS)

    Akchurin, N.; Bedeschi, F.; Cardini, A.; Cascella, M.; Ciapetti, G.; D'Orazio, A.; Collica, L.; De Pedis, D.; Ferrari, R.; Franchino, S.; Fraternali, M.; Gaudio, G.; Genova, P.; Hauptman, J.; Lacava, F.; La Rotonda, L.; Lee, S.; Livan, M.; Meoni, E.; Negri, A.

    2012-01-01

    Some high-Z scintillating crystals offer the possibility to distinguish the contributions from the scintillation and Čherenkov mechanisms to the generated signals. Among these crystals are BGO and PbWO 4 . We have tested matrices of these crystals as electromagnetic calorimeters and studied the properties of the Čherenkov and scintillation components of the signals generated by high-energy electrons showering in these detectors.

  8. An X-Ray facility to perform irradiation tests and TID studies on electronics and detectors

    CERN Document Server

    Brundu, Davide; Cadeddu, Sandro; Wyllie, Ken; Ciambrone, Paolo

    2018-01-01

    The X-Ray irradiation system of the LHCb group, installed in Cagliari, is presented; with a particular focus on the setup configuration and dose rate calibration. The system can be used to perform Total Ionizing Dose (TID) studies for detectors, readout and front-end electronics. It was already used to test the nSYNC chip, an ASIC for the readout of the LHCb upgraded muon system.

  9. Readout of a single electron spin in a double quantum dot using a quantum point contact

    International Nuclear Information System (INIS)

    Zhang Jianping; Ouyang Shihua; You, J Q; Lam, C.-H.

    2008-01-01

    We study the dynamics of a single electron spin in a double quantum dot (DQD) and its readout via a quantum point contact (QPC). We model the system microscopically and derive rate equations for the reduced electron density matrix of the DQD. Two cases with one and two electrons in the DQD are studied. In the one-electron case, with different Zeeman splittings in the two dots, the electron spin states are distinctly characterized by a constant and an oscillatory current through the QPC. In the two-electron case, the readout of the spin state of the electron in one of the dots called the qubit dot is essentially similar after considering hyperfine interactions between the electrons and the nuclear spins of the host materials and a uniform magnetic field applied to the DQD. Moreover, to ensure that an electron is properly injected into the qubit dot, we propose to determine the success of the electron injection from the variations of the QPC current after applying an oscillating magnetic field to the qubit dot

  10. Development of hybrid photon detectors with integrated silicon pixel readout for the RICH counters of LHCb

    CERN Document Server

    Alemi, M; Formenti, F; Gys, Thierry; Piedigrossi, D; Puertolas, D; Rosso, E; Snoeys, W; Wyllie, Ken H

    1999-01-01

    We report on the ongoing work towards a hybrid photon detector with integrated silicon pixel readout for the ring imaging Cherenkov detectors of the LHCb experiment at the Large Hadron Collider at CERN. The photon detector is based $9 on a cross-focussed image intensifier tube geometry where the image is de-magnified by a factor of 4. The anode consists of a silicon pixel array, bump-bonded to a fast, binary readout chip with matching pixel electronics. The $9 performance of a half-scale prototype is presented, together with the developments and tests of a full-scale tube with large active area. Specific requirements for pixel front-end and readout electronics in LHCb are outlined, and $9 recent results obtained from pixel chips applicable to hybrid photon detector design are summarized.

  11. A THEORETICAL MODEL OF SUPPORTING OPEN SOURCE FRONT END INNOVATION THROUGH IDEA MANAGEMENT

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2013-01-01

    to overcome these various challenges companies are looking for new models to support FEI. This theoretical paper explores in what way idea management may be applied as a tool in facilitation of front end innovation and how this facilitation may be captured in a conceptual model. First, I show through...... a literature study, how idea management and front end innovation are related and how they may support each other. Secondly, I present a theoretical model of how idea management may be applied in support of the open source front end of new product innovations. Thirdly, I present different venues of further...... exploration of active facilitation of open source front end innovation through idea management....

  12. Front end designs for the 7-GeV advanced photon source

    International Nuclear Information System (INIS)

    Shu, D.; Barraza, J.; Sanchez, T.; Nielsen, R.W.; Collins, J.T.; Kuzay, T.M.

    1992-01-01

    The conceptual designs for the insertion device (ID) and bending magnet (BM) front ends have been completed for the 7-GeV Advanced Photon Source (APS) under construction at Argonne National Laboratory. These designs satisfy the generic front end functions. However, the high power and high heat fluxes imposed by the X-ray sources of the 7-GeV APS have presented various design engineering challenges for the front end. Consideration of such challenges and their solutions have led to novel and advanced features including modularized systems, enhanced heat transfer concepts in the fixed mask and the photon shutter designs, a radiation safety philosophy based on multiple photon shutters for a fail-safe operation, a sub-micron resolution beam position monitor for beam monitoring and ring feedback information, and minimal beam filtering concepts to deliver maximized beam power and spectra to the experimenters. The criteria and special features of the front end design are discussed in this paper

  13. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — In this SBIR project, AlphaSense, Inc. and the Carnegie Mellon University propose to develop a RF receiver front end based on CMOS-MEMS components for miniaturized...

  14. Desarrollo de un terminal punto de venta (TPV) : Arquitectura front-end con Angular2

    OpenAIRE

    López Jurado, Francisco Carlos

    2017-01-01

    Desarrollo de la arquitectura front-end para un terminal de punto de venta. Diseño y maquetación de las vistas de la aplicación. Implementación de todas las vistas, utilizando una arquitectura de componentes con Angular2. Definición de los endpoints del back-end que debe utilizar la capa front-end. Definición e implementación de los modelos de la capa front-end, que serán recibidos por la capa back-end como wrappers. Implantación de un plan de pruebas para la capa front-end, haciend...

  15. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — In this proposal, AlphaSense, Inc. (AI) and the Carnegie Mellon University (CMU) detail the development of RF front end based on MEMS components for miniaturized...

  16. Study on FPGA SEU Mitigation for the Readout Electronics of DAMPE BGO Calorimeter in Space

    Science.gov (United States)

    Shen, Zhongtao; Feng, Changqing; Gao, Shanshan; Zhang, Deliang; Jiang, Di; Liu, Shubin; An, Qi

    2015-06-01

    The BGO calorimeter, which provides a wide measurement range of the primary cosmic ray spectrum, is a key sub-detector of the Dark Matter Particle Explorer (DAMPE). The readout electronics of calorimeter consists of 16 pieces of Actel ProASIC Plus FLASH-based field-programmable gate array (FPGA), of which the design-level flip-flops and embedded block random access memories (RAM) are single event upset (SEU) sensitive in the harsh space environment. To comply with radiation hardness assurance (RHA), SEU mitigation methods, including partial triple modular redundancy (TMR), CRC checksum, and multi-domain reset are analyzed and tested by the heavy-ion beam test. Composed of multi-level redundancy, a FPGA design with the characteristics of SEU tolerance and low resource consumption is implemented for the readout electronics.

  17. Beam test results for the upgraded LHCb RICH opto-electronic readout system

    CERN Multimedia

    Carniti, Paolo

    2016-01-01

    The LHCb experiment is devoted to high-precision measurements of CP violation and search for New Physics by studying the decays of beauty and charmed hadrons produced at the Large Hadron Collider (LHC). Two RICH detectors are currently installed and operating successfully, providing a crucial role in the particle identification system of the LHCb experiment. Starting from 2019, the LHCb experiment will be upgraded to operate at higher luminosity, extending its potential for discovery and study of new phenomena. Both the RICH detectors will be upgraded and the entire opto-electronic system has been redesigned in order to cope with the new specifications, namely higher readout rates, and increased occupancies. The new photodetectors, readout electronics, mechanical assembly and cooling system have reached the final phase of development and their performance was thoroughly and successfully validated during several beam test sessions in 2014 and 2015 at the SPS facility at CERN. Details of the test setup and perf...

  18. A Contingency Approach on the Impact of Front-End Success on Project Portfolio Success

    OpenAIRE

    Kock, Alexander; Heising, Wilderich; Gemünden, Hans Georg

    2016-01-01

    This is the article as published by PMI The pre-project or ideation phase is often disregarded in project portfolio management. Senior managers put more emphasis on later project stages, and researchers predominantly investigate the front end from a single project perspective. This study investigates how and under which circumstances the performance of the front end affects project portfolio success. Using a sample of 175 firms, we confirm a strong positive re...

  19. Front end embedded microprocessors in the JET computer-based control system, past, present and future

    International Nuclear Information System (INIS)

    Steed, C.A.; VanderBeken, H.; Browne, M.L.; Fullard, K.; Reed, K.; Tilley, M.; Schmidt, V.

    1987-01-01

    A brief history of the use of Front End Microprocessors in the JET Control and Data Acquisition System (CODAS) is presented. The present expansion in their use from 2 or 3 in 1983 to 27 now, is covered along with the reasoning behind their present usage. Finally, their future planned use in the area of remote handling is discussed and the authors present views on the use of front end processing in future large distributed control systems are presented

  20. Measurement of Design Process Front-End – Radical Innovation Approach

    DEFF Research Database (Denmark)

    Berg, Pekka; Pihlajamaa, Jussi; Hansen, Poul H. Kyvsgård

    2014-01-01

    The overall structure and the main characteristics of the future product are all decided in the front-end phase, which then strongly affects subsequent new product development activities. Recent studies indicate that these early front-end activities represent the most troublesome phase of the inn...... is flexible and can also be applied extensively to other purposes than manufacturing companies, like service sector, as well....

  1. Single Electron Detection in Quadruple-GEM Detector with Pad Readout

    Energy Technology Data Exchange (ETDEWEB)

    Va' vra, Jaroslav

    2001-03-07

    Using a system of four GEMs operating in tandem and coupled to pad readout, we have demonstrated the detection of single electrons in ethane at 1 bar. The paper presents measurements of single electron pulse height distributions, total gas gain measurement and calculation, pad-to-pad cross-talk, quenching capability, high rate capability, charging effects, etc. We describe the overall operational experience, including addition of a gaseous photocathode, TMAE, and compare it to the SLD CRID single-electron detector [1], which has been operational during the past decade.

  2. Implementasi Analog Front End Pada Sensor Kapasitif Untuk Pengaturan Kelembaban Menggunakan Mikrokontroller STM32

    Directory of Open Access Journals (Sweden)

    Rendy Setiawan

    2017-01-01

    Full Text Available Sensor kapasitif merupakan jenis sensor yang mengubah stimulus fisik menjadi perubahan kapasitansi. Pada sensor kapasitif, adanya stray capacitance atau kapasitansi parasitik pada sensor dapat menyebabkan kesalahan dalam pengukuran. Dalam aplikasi pengaturan kelembaban, dibutuhkan sistem pengukuran kelembaban dengan kesalahan minimum untuk mendapatkan nilai setting point dengan galat minimum. Maka diperlukan implementasi analog front end yang dapat meminimalisir kesalahan akibat stray capacitance pada sensor kapasitif untuk pengukuran kelembaban relatif. Pada sistem pengukuran sensor kapasitif ini, sensor dieksitasi dengan sinyal AC yang dihasilkan oleh generator sinyal pada frekuensi 10 KHz, kemudian diimplementasikan analog front end untuk mengondisikan sinyal dari sensor. Keluaran dari analog front end dikonversi menjadi sinyal DC menggunakan demodulator sinkron dan filter low pass lalu dikonversi menjadi data digital menggunakan ADC di mikrokontroller STM32. Hasil pengukuran yang didapatkan dengan implementasi analog front end kemudian kemudian gunakan untuk mengatur kelembaban pada sebuah plant growth chamber. Berdasarkan hasil dari pengujian, rangkaian analog front end dapat mengompensasi stray capacitance dengan kesalahan pembacaan nilai kapasitansi maksimal sebesar 4.2% pada kondisi stray capacitance sebesar 236,6pF, 174,3pF dan 115,7pF. Implementasi analog front end pada pengaturan kelembaban menghasilkan galat pada setting point maksimal sebesar 8.8% untuk nilai RH 75% dan 33%.

  3. Control and Interlocking System for Bending Magnet Front-end at Indus-2

    Science.gov (United States)

    Kane, Sanjeev R.; Garg, Chander Kant; Nandedkar, R. V.

    2007-01-01

    We present control and interlock system developed for Indus-2 bending magnet front-end. The paper describes in detail the control of various signals associated with the front-end and the interlocking scheme implemented for the installed front-end. The number of signals associated with each front-end is ˜ 75. A control system is designed for monitoring temperature, pressure, airflow, water flow and control of vacuum gauges, fast shutter, water cooled shutter, safety shutter, pneumatic gate valves, sputter ion pump power supplies, beam position monitor etc. Two independent signals are generated for critical components that are used for software interlock and hard-wired interlock. The front-end control system is VME based and window 2000/XP workstation as an operator console. The CPU used is Motorola 68000-processor board of the VME bus having OS-9 real time operating system. One VME crate serves a cluster of 2-3 front ends. The communication between the VME and the workstation is linked over RS232 serial communication. The sputter ion power supplies are connected over isolated RS485 network. Critical protection features are implemented so that no single failure can render the system unsafe. This is implemented by providing two independent chains of protection (1) Hard wired in which relay logic is used and (2) Software. A Graphical User Interface (GUI) is developed using Lab view Version 7.0.

  4. The OPERA global readout and GPS distribution system

    Science.gov (United States)

    Marteau, J.; Opera Collaboration

    2010-05-01

    OPERA is an experiment dedicated to the observation of νμ into ντ oscillations in appearance mode using a pure νμ beam (CNGS) produced at CERN and detected at Gran Sasso. The experiment exploits a hybrid technology with emulsions and electronics detectors. The OPERA readout is performed through a triggerless, continuously running, distributed and highly available system. Its global architecture is based on Ethernet-capable smart sensors with microprocessing and network interface directly at the front-end stage. A unique interface board is used for the full detector reading out ADC-, TDC- or Controller-boards. All the readout channels are synchronized through a GPS-locked common bidirectional clock distribution system developed on purpose in a PCI format. It offers a second line to address all channels and the off-line synchronization with the CNGS to select the events.

  5. The OPERA global readout and GPS distribution system

    International Nuclear Information System (INIS)

    Marteau, J.

    2010-01-01

    OPERA is an experiment dedicated to the observation of ν μ into ν τ oscillations in appearance mode using a pure ν μ beam (CNGS) produced at CERN and detected at Gran Sasso. The experiment exploits a hybrid technology with emulsions and electronics detectors. The OPERA readout is performed through a triggerless, continuously running, distributed and highly available system. Its global architecture is based on Ethernet-capable smart sensors with microprocessing and network interface directly at the front-end stage. A unique interface board is used for the full detector reading out ADC-, TDC- or Controller-boards. All the readout channels are synchronized through a GPS-locked common bidirectional clock distribution system developed on purpose in a PCI format. It offers a second line to address all channels and the off-line synchronization with the CNGS to select the events.

  6. Upgrade Analog Readout and Digitizing System for ATLAS TileCal Demonstrator

    CERN Document Server

    Tang, F; The ATLAS collaboration; Akerstedt, H; Biot, A; Bohm, C; Carrio, F; Drake, G; Hildebrand, K; Muschter, S; Oreglia, M; Paramonov, A

    2013-01-01

    A potential upgrade for the front-end electronics and signal digitization and data acquisition system of the ATLAS hadron calorimeter for the high luminosity Large Hadron Collider (HL-LHC) is described. A Demonstrator is being built to readout a slice of the TileCal detector. The on-detector electronics includes up to 48 Analog Front-end Boards for PMT analog signal processing, 4 Main Boards for data digitization and slow controls, 4 Daughter Boards with high speed optical links to interface the on-detector and off-detector electronics. Two super readout driver boards are used for off-detector data acquisition and fulfilling digital trigger. The ATLAS Tile Calorimeter on-detector electronics is housed in the drawers at the back of each of the 256 detector wedges. Each drawer services up to 48 photomultiplier tubes. The new readout system is designed to replace the present system as it will reach component lifetime and radiation tolerance limits making it incompatible with continued use into the HL-LHC era. Wi...

  7. Upgraded Readout and Trigger Electronics for the ATLAS Liquid Argon Calorimeter at the LHC at the Horizons 2018-2022

    CERN Document Server

    Oliveira Damazio, Denis; The ATLAS collaboration

    2013-01-01

    The ATLAS Liquid Argon (LAr) calorimeters produce a total of 182,486 signals which are digitized and processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics is summing analog signals to provide coarsely grained energy sums, called trigger towers, to the first-level trigger system, which is optimized for nominal LHC luminosities. However, the pile-up noise expected during the High Luminosity phases of LHC will be increased by factors of 3 to 7. An improved spatial granularity of the trigger primitives is therefore proposed in order to improve the identification performance for trigger signatures, like electrons, photons, tau leptons, jets, total and missing energy, at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Board (LTDB) are being designed to receive higher granularity signals, digitize them on detector and send them via fast optical links to a new digital processing system (DPS). The DPS applies...

  8. Readout Driver Firmware Development for the ATLAS Insertable B-Layer

    CERN Document Server

    Chen, Shaw-Pin; Hsu, Shih-Chieh

    During the Large Hadron Collider shutdown from 2013 to 2014 a fourth silicon layer, called the Insertable-B Layer (IBL), was inserted inside the existing ATLAS Pixel Detector. The IBL uses the state-of-the-art FE-I4 front-end readout ASICs for enhanced detector readout efficiency during upcoming LHC runs at higher energy and luminosity. The control and data acquisition (DAQ) of the IBL requires the commissioning of new off-detector readout electronics, mainly consisting of Field-Programmable Gate Array (FPGA)-based Readout Driver (ROD) and Back-of-Crate (BOC) Cards. This thesis focuses on the architecture, implementation, simulation, and hardware test results of the new IBL ROD datapath firmware. Characterization of the IBL detector front-end and an overview of ATLAS Trigger DAQ (TDAQ) system are provided in the first chapters of the thesis. IBL ROD datapath firmware was designed and simulated in a ModelSim testbench with a realistic HDL FE-I4 model as source of data. The hardware tests using both real and em...

  9. The next generation FrontEnd Controller for the Phase 1 Upgrade of the CMS Hadron Calorimeters

    OpenAIRE

    Costanza, Francesco

    2016-01-01

    The ngFEC (next generation FrontEnd Controller) is the system responsible for slow and fast control within the Phase 1 Upgrade of the CMS Hadron Calorimeters. It is based on the FC7, a μ TCA compatible Advanced Mezzanine Card developed at CERN and built around the Xilinx Kintex®-7 FPGA. The ngFEC decodes the 40.0788 MHz LHC clock and the synchronization signals received from the backplane and distributes them to the frontend electronics using a GBT link. The latency of the fast control signal...

  10. An Upgraded Front-End Switching Power Supply Design For the ATLAS TileCAL Detector of the LHC

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2011-01-01

    We present the design of an upgraded switching power supply brick for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and generally a more robust design, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the improvements to the design, and the radiation testing that we have done to qualify the design. We also present our plans for the production of 2400 new bricks for installation on the detector in 2013.

  11. An Upgraded Front-End Switching Power Supply Design for the ATLAS TileCAL Detector of the LHC

    CERN Document Server

    Drake, G; The ATLAS collaboration; De Lurgio, P; Henriques, A; Minashvili, I; Nemecek, S; Price, L; Proudfoot, J; Stanek, R

    2011-01-01

    We present the design of an upgraded switching power supply brick for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and generally a more robust design, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the improvements to the design, and the radiation testing that we have done to qualify the design. We also present our plans for the production of 2400 new bricks for installation on the detector in 2013.

  12. Electronics development for the ATLAS liquid argon calorimeter trigger and readout for future LHC running

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00009068; The ATLAS collaboration

    2016-01-01

    The upgrade of the LHC will provide 7 times greater instantaneous and total luminosities than assumed in the original design of the ATLAS Liquid Argon (LAr) Calorimeters. Radiation tolerance criteria and an improved trigger system with higher acceptance rate and longer latency require an upgrade of the LAr readout electronics. In the first upgrade phase in 2019-2020, a trigger readout with up to 10 times higher granularity will be implemented. This allows an improved reconstruction of electromagnetic and hadronic showers and will reduce the background for electron, photon and energy-flow signals at the first trigger level. The analog and digital signal processing components are currently in their final design stages and a fully functional demonstrator system is operated and tested on the LAr Calorimeters. In a second upgrade stage in 2024-2026, the readout of all 183,000 LAr Calorimeter cells will be performed without trigger selection at 40 MHz sampling rate and 16 bit dynamic range. Calibrated energies of a...

  13. Electronics Development for the ATLAS Liquid ArgonCalorimeter Trigger and Readout for Future LHC Running

    CERN Document Server

    Hopkins, Walter; The ATLAS collaboration

    2016-01-01

    The upgrade of the LHC will provide 7 times greater instantaneous and total luminosities than assumed in the original design of the ATLAS Liquid Argon (LAr) Calorimeters. Radiation tolerance criteria and an improved trigger system with higher acceptance rate and longer latency require an upgrade of the LAr readout electronics. In the first upgrade phase in 2019-2020, a trigger readout with up to 10 times higher granularity will be implemented. This allows an improved reconstruction of electromagnetic and hadronic showers and will reduce the background for electron, photon and energy-flow signals at the first trigger level. The analog and digital signal processing components are currently in their final design stages and a fully functional demonstrator system is operated and tested on the LAr Calorimeters. In a second upgrade stage in 2024-2026, the readout of all 183,000 LAr Calorimeter cells will be performed without trigger selection at 40 MHz sampling rate and 16 bit dynamic range. Calibrated energies of a...

  14. Electronics Development for the ATLAS Liquid Argon Calorimeter - Trigger and Readout for Future LHC Running -

    CERN Document Server

    Starz, Steffen; The ATLAS collaboration

    2016-01-01

    The upgrade of the LHC will provide up to 7.5 times greater instantaneous and total luminosities than assumed in the original design of the ATLAS Liquid Argon (LAr) Calorimeters. Radiation tolerance criteria and an improved trigger system with higher acceptance rate and longer latency require an upgrade of the LAr readout electronics. In the first upgrade phase in 2019-2020, a trigger-readout with up to 10 times higher granularity will be implemented. This allows an improved reconstruction of electromagnetic and hadronic showers and will reduce the background for electron, photon and energy-flow signals at the first trigger level. The analog and digital signal processing components are currently in their final design stages and a fully functional demonstrator system is operated and tested on the LAr Calorimeters. In a second upgrade stage in 2024-2026, the readout of all 183,000 LAr Calorimeter cells will be performed without trigger selection at 40 MHz sampling rate and 16 bit dynamic range. Calibrated energ...

  15. Electronics Development for the ATLAS Liquid Argon Calorimeter Trigger and Readout for Future LHC Running

    CERN Document Server

    Pacheco Rodriguez, Laura; The ATLAS collaboration

    2016-01-01

    The upgrade of the LHC will provide up to 7.5 times greater instantaneous and total luminosities than assumed in the original design of the ATLAS Liquid Argon (LAr) Calorimeters. The radiation tolerance criteria and the improved trigger system with higher acceptance rate and longer latency require an upgrade of the LAr readout electronics. In the first upgrade phase in 2019-2020, a trigger-readout with up to 10 times higher granularity will be implemented. This allows an improved reconstruction of electromagnetic and hadronic showers and will reduce the background for electron, photon and energy-flow signals at the first trigger level. The analog and digital signal processing components are currently in their final design stages and a fully functional demonstrator system is operated and tested on the LAr Calorimeters. In a second upgrade stage in 2024-2026, the readout of all 183,000 LAr Calorimeter cells will be performed without trigger selection at 40 MHz sampling rate and 16 bit dynamic range. Calibrated ...

  16. Electronics and readout of a large area silicon detector for LHC

    International Nuclear Information System (INIS)

    Borer, K.; Munday, D.J.; Parker, M.A.; Anghinolfi, F.; Aspell, P.; Campbell, M.; Chilingarov, A.; Jarron, P.; Heijne, E.H.M.; Santiard, J.C.; Scampoli, P.; Verweij, H.; Goessling, C.; Lisowski, B.; Reichold, A.; Spiwoks, R.; Tsesmelis, E.; Benslama, K.; Bonino, R.; Clark, A.G.; Couyoumtzelis, C.; Kambara, H.; Wu, X.; Fretwurst, E.; Lindstroem, G.; Schultz, T.; Bardos, R.A.; Gorfine, G.W.; Moorhead, G.F.; Taylor, G.N.; Tovey, S.N.; Bibby, J.H.; Hawkings, R.J.; Kundu, N.; Weidberg, A.; Campbell, D.; Murray, P.; Seller, P.; Teiger, J.

    1994-01-01

    The purpose of the RD2 project is to evaluate the feasibility of a silicon tracker and/or preshower detector for LHC. Irradiation studies with doses equivalent to those expected at LHC have been performed to determine the behavior of operational parameters such as leakage current, depletion voltage and charge collection during the life of the detector. The development of fast, dense, low power and low cost signal processing electronics is one of the major activities of the collaboration. We describe the first fully functional integrated analog memory chip with asynchronous read and write operations and level 1 trigger capture capabilities. A complete test beam system using this analog memory chip at 66 MHz has been successfully operated with RD2 prototype silicon detectors during various test runs. The flexibility of the electronics and readout have allowed us to easily interface our set-up to other data acquisition systems. Mechanical studies are in progress to design a silicon tracking detector with several million channels that may be operated at low (0-10 C) temperature, while maintaining the required geometrical precision. Prototype readout boards for such a detector are being developed and simulation studies are being performed to optimize the readout architecture. (orig.)

  17. Development of Trigger and Readout Electronics for the ATLAS New Small Wheel Detector Upgrade

    CERN Document Server

    Antrim, Daniel Joseph; The ATLAS collaboration

    2017-01-01

    The present small wheel muon detector at ATLAS will be replaced with a New Small Wheel (NSW) detector to handle the increase in data rates and harsh radiation environment expected at the LHC. Resistive Micromegas and small-strip Thin Gap Chambers will be used to provide both trigger and tracking primitives. Muon segments found at NSW will be combined with the segments found at the Big Wheel to determine the muon transverse momentum at the first-level trigger. A new trigger and readout system is developed for the NSW detector. The new system has about 2.4 million trigger and readout channels and about 8,000 frontend boards. The large number of input channels, short time available to prepare and transmit data, harsh radiation environment, and low power consumption all impose great challenges on the design. We will discuss the overall electronics design and studies with various ASIC and board prototypes.

  18. Analog front end circuit design of CSNS beam loss monitor system

    International Nuclear Information System (INIS)

    Xiao Shuai; Guo Xian; Tian Jianmin; Zeng Lei; Xu Taoguang; Fu Shinian

    2013-01-01

    The China Spallation Neutron Source (CSNS) beam loss monitor system uses gas ionization chamber to detect beam losses. The output signals from ionization chamber need to be processed in the analog front end circuit, which has been designed and developed independently. The way of transimpedance amplifier was used to achieve current-voltage (I-V) conversion measurement of signal with low repetition rate, low duty cycle and low amplitude. The analog front end circuit also realized rapid response to the larger beam loss in order to protect the safe operation of the accelerator equipment. The testing results show that the analog front end circuit meets the requirements of beam loss monitor system. (authors)

  19. Report on the value engineering workshop on APS beamline front ends

    International Nuclear Information System (INIS)

    Kuzay, T.

    1993-01-01

    A formal value engineering evaluation process was developed to address the front end components of the beamlines for the Advanced Photon Source (APS). This process (described in Section 2) involved an information phase, a creative phase, a judgment phase, a development phase, and a recommendation phase. Technical experts from other national laboratories and industry were invited to a two-day Value Engineering Workshop on November 5-6, 1992. The results of this Workshop are described in Section 4. Following the Workshop, various actions by the APS staff led to the redesign of the front end components, which are presented in Sections 5 and 6. The cost benefit analysis is presented in Section 7. It is important of realize that an added benefit of the Workshop was to obtain numerous design evaluations and enhancements of the front end components by experts in the field. As the design work proceeds to Title II completion, the APS staff is including many of these suggestions

  20. Measures of the Environmental Footprint of the Front End of the Nuclear Fuel Cycle

    Energy Technology Data Exchange (ETDEWEB)

    Brett Carlsen; Emily Tavrides; Erich Schneider

    2010-08-01

    Previous estimates of environmental impacts associated with the front end of the nuclear fuel cycle have focused primarily on energy consumption and CO2 emissions. Results have varied widely. Section 2 of this report provides a summary of historical estimates. This study revises existing empirical correlations and their underlying assumptions to fit to a more complete set of existing data. This study also addresses land transformation, water withdrawals, and occupational and public health impacts associated with the processes of the front end of the once-through nuclear fuel cycle. These processes include uranium mining, milling, refining, conversion, enrichment, and fuel fabrication. Metrics are developed to allow environmental impacts to be summed across the full set of front end processes, including transportation and disposition of the resulting depleted uranium.

  1. Design and Characteristics of a Multichannel Front-End ASIC Using Current-Mode CSA for Small-Animal PET Imaging.

    Science.gov (United States)

    Ollivier-Henry, N; Wu Gao; Xiaochao Fang; Mbow, N A; Brasse, D; Humbert, B; Hu-Guo, C; Colledani, C; Yann Hu

    2011-02-01

    This paper presents the design and characteristics of a front-end readout application-specific integrated circuit (ASIC) dedicated to a multichannel-plate photodetector coupled to LYSO scintillating crystals. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. Both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. A current-mode charge-sensitive amplifier is proposed for this application. This paper presents performance characteristics of a 10-channel prototype chip designed and fabricated in a 0.35-μm complementary metal-oxide semiconductor process. The main results of simulations and measurements are presented and discussed. The gain of the chip is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The signal-to-noise ratio is 39 dB and the rms noise is 300 μV/√(Hz). The nonlinearity is less than 3% and the crosstalk is about 0.2%. The power dissipation is less than 15 mW/channel. This prototype will be extended to a 64-channel circuit with integrated time-to-digital converter and analog-to-digital converter together for a high-sensitive small-animal positron emission tomography imaging system.

  2. C2D8: An eight channel CCD readout electronics dedicated to low energy neutron detection

    Science.gov (United States)

    Bourrion, O.; Clement, B.; Tourres, D.; Pignol, G.; Xi, Y.; Rebreyend, D.; Nesvizhevsky, V. V.

    2018-02-01

    Position-sensitive detectors for cold and ultra-cold neutrons (UCN) are in use in fundamental research. In particular, measuring the properties of the quantum states of bouncing neutrons requires micro-metric spatial resolution. To this end, a Charge Coupled Device (CCD) coated with a thin conversion layer that allows a real time detection of neutron hits is under development at LPSC. In this paper, we present the design and performance of a dedicated electronic board designed to read-out eight CCDs simultaneously and operating under vacuum.

  3. An aging study of a gas electron multiplier with micro-strip gas chamber readout

    CERN Document Server

    Miyamoto, J

    1999-01-01

    We have performed an aging study of a Gas Electron Multiplier (GEM) readout with a Micro-Strip Gas Chamber (MSGC). The GEM is constructed from Kapton and copper, and the MSGC is constructed from semiconductive glass and gold. When the detector (GEM+MSGC) is operated in an argon-dimethyl ether (DME) gas mixture and irradiated with a 5.4 keV photon beam, about 220 mC/cm of charge can be accumulated without degradation of the detector performance. This corresponds to about 20 years of operation at the LHC.

  4. Alternative Muon Front-end for the International Design Study (IDS)

    CERN Document Server

    Alekou, A; Martini, M; Prior, G; Rogers, C; Stratakis, D; Yoshikawa, C; Zisman, M

    2010-01-01

    We discuss alternative designs of the muon capture front end of the Neutrino Factory International Design Study (IDS). In the front end, a proton bunch on a target creates secondary pions that drift into a capture channel, decaying into muons. A sequence of RF cavities forms the resulting muon beams into strings of bunches of differing energies, aligns the bunches to (nearly) equal central energies, and initiates ionization cooling. This design is affected by limitations on accelerating gradients within magnetic fields. The effects of gradient limitations are explored, and mitigation strategies are presented

  5. EBR-II Cover Gas Cleanup System upgrade distributed control and front end computer systems

    International Nuclear Information System (INIS)

    Carlson, R.B.

    1992-01-01

    The Experimental Breeder Reactor II (EBR-II) Cover Gas Cleanup System (CGCS) control system was upgraded in 1991 to improve control and provide a graphical operator interface. The upgrade consisted of a main control computer, a distributed control computer, a front end input/output computer, a main graphics interface terminal, and a remote graphics interface terminal. This paper briefly describes the Cover Gas Cleanup System and the overall control system; gives reasons behind the computer system structure; and then gives a detailed description of the distributed control computer, the front end computer, and how these computers interact with the main control computer. The descriptions cover both hardware and software

  6. Control of SiC Based Front-End Rectifier under Unbalanced Supply Voltage

    DEFF Research Database (Denmark)

    Maheshwari, Ramkrishan; Trintis, Ionut; Gohil, Ghanshyamsinh Vijaysinh

    2015-01-01

    A voltage source converter is used as a front end converter typically. In this paper, a converter which is realized using SiC MOSFET is considered. Due to SiC MOSFET, a switching frequency more than 50 kHz can be achieved. This can help increasing the current control loop bandwidth, which is not ...... together with a positive-sequence current controller for the front-end rectifier. A gain in the feedforward term can be changed to control the negative-sequence current. Simulation results are presented to verify the theory....

  7. SiPM arrays and miniaturized readout electronics for compact gamma camera

    Energy Technology Data Exchange (ETDEWEB)

    Dinu, N., E-mail: dinu@lal.in2p3.fr [Laboratory of Linear Accelerator, IN2P3, CNRS, Orsay (France); Imando, T. Ait; Nagai, A. [Laboratory of Linear Accelerator, IN2P3, CNRS, Orsay (France); Pinot, L. [Laboratory of Imaging and Modelisation in Neurobiology and Cancerology, IN2P3, CNRS, Orsay (France); Puill, V. [Laboratory of Linear Accelerator, IN2P3, CNRS, Orsay (France); Callier, S. [Omega Microelectronics Group, CNRS, Palaiseau (France); Janvier, B.; Esnault, C.; Verdier, M.-A. [Laboratory of Imaging and Modelisation in Neurobiology and Cancerology, IN2P3, CNRS, Orsay (France); Raux, L. [Omega Microelectronics Group, CNRS, Palaiseau (France); Vandenbussche, V.; Charon, Y.; Menard, L. [Laboratory of Imaging and Modelisation in Neurobiology and Cancerology, IN2P3, CNRS, Orsay (France)

    2015-07-01

    This article reports on the design and features of a very compact and light gamma camera based on SiPM arrays and miniaturized readout electronics dedicated to tumor localization during radio-guided cancer surgery. This gamma camera, called MAGICS, is composed of four (2×2) photo-detection elementary modules coupled to an inorganic scintillator. The 256 channels photo-detection system covers a sensitive area of 54×53 m{sup 2}. Each elementary module is based on four (2×2) SiPM monolithic arrays, each array consisting of 16 SiPM photo-sensors (4×4) with 3×3 mm{sup 2} sensitive area, coupled to a miniaturized readout electronics and a dedicated ASIC. The overall dimensions of the electronics fit the size of the detector, enabling to assemble side-by-side several elementary modules in a close-packed arrangement. The preliminary performances of the system are very encouraging, showing an energy resolution of 9.8% and a spatial resolution of less than 1 mm at 122 keV.

  8. The prototype readout electronics system for the External Target Experiment in CSR of HIRFL

    Science.gov (United States)

    Zhao, L.; Kang, L.; Li, M.; Liu, S.; Zhou, J.; An, Q.

    2014-07-01

    A prototype readout electronics system was designed for the External Target Experiment in the Cooling Storage Ring (CSR) of the Heavy Ion Research Facility in Lanzhou (HIRFL). The kernel parts include the 128-channel 100 ps high-resolution time digitization module, the 16-channel 25 ps high-resolution time and charge measurement module, and the trigger electronics, as well as the clock generation circuits, which are all integrated within the PXI-6U crate. The laboratory test results indicate that a good resolution is achieved, better than the requirement. We also have conducted initial commissioning tests with the detectors to confirm the functions of the system. Through the research of this prototype electronics, preparation for the future extended system is made.

  9. Auto-triggerable HPD sensors fully readout on Ethernet, applications for high energy physics and medical imaging

    International Nuclear Information System (INIS)

    Katsanevas, S.; Largeron, G.; Marteau, J.; Moret, G.

    2002-01-01

    The OPERA project is dedicated to neutrino oscillation search in the CNGS neutrino beam from CERN to Gran Sasso. The experiment is designed to characterize the interaction of ν τ resulted from the ν μ → ν τ oscillation. The main element of the detector is a brick consisting of the emulsion sheets interleaved with lead plates. These bricks are assembled in walls of about 7 m side. A total of 72 walls is foreseen for OPERA experiment with a total of fiducial mass of 2 k tons. When a neutrino interaction occurs the tracks of the charged particles are recorded in the emulsions with a high accuracy and the topology of the event is fully reconstructed with an automatic scanning of the emulsions. The role of the target tracker in OPERA is to locate the brick where the primary neutrino interaction occurs to provide triggers and to make a coarser reconstruction of the events. It consists of 2 planes of scintillator strips located after a brick wall.. The scintillation photons are collected by WLS fibers and read by a multi-pixel photodetector. The results obtained with 61 pixels HPDs readout by auto-triggerable front-end electronics of the VA-TA series. A new kind of acquisition system based on Ethernet abler to read the front-end electronics and deliver the data directly to the Ethernet network is described. The Ethernet DAQ system is based on a ORCA (Opera Readout Card) module which includes all the features to control the front-end and the time stamping of the trigger of the events. The front-end electronics and the HPD characteristics are described in Sections 2 and 3 while the PMT which validates the acquisition chain is presented in Section 4. Medical applications and the results obtained with the acquisition system used as micro pet and for characterized photodetectors in High Energy experiment are also presented

  10. Proton and Neutron Irradiation Tests of Readout Electronics of the ATLAS Hadronic Endcap Calorimeter

    CERN Document Server

    INSPIRE-00106910

    2012-01-01

    The readout electronics of the ATLAS Hadronic Endcap Calorimeter will have to withstand the about ten times larger radiation environment of the future high-luminosity LHC (HL-LHC) compared to their design values. The GaAs ASIC which comprises the heart of the readout electronics has been exposed to neutron and proton radiation with fluences up to ten times the total expected fluences for ten years of running of the HL-LHC. Neutron tests were performed at the NPI in Rez, Czech Republic, where a 36 MeV proton beam is directed on a thick heavy water target to produce neutrons. The proton irradiation was done with 200 MeV protons at the PROSCAN area of the Proton Irradiation Facility at the PSI in Villigen, Switzerland. In-situ measurements of S-parameters in both tests allow the evaluation of frequency dependent performance parameters - like gain and input impedance - as a function of the fluence. The linearity of the ASIC response has been measured directly in the neutron tests with a triangular input pulse of ...

  11. Proton and Neutron Irradiation Tests of Readout Electronics of the ATLAS Hadronic Endcap Calorimeter

    CERN Document Server

    Menke, Sven; The ATLAS collaboration

    2012-01-01

    The readout electronics of the ATLAS Hadronic Endcap Calorimeter will have to withstand the about ten times larger radiation environment of the future high-luminosity LHC (HL-LHC) compared to their design values. The GaAs ASIC which comprises the heart of the readout electronics has been exposed to neutron and proton radiation with fluences up to ten times the total expected fluences for ten years of running of the HL-LHC. Neutron tests where performed at the NPI in Rez, Czech Republic, where a 36 MeV proton beam is directed on a thick heavy water target to produce neutrons. The proton irradiation was done with 200 MeV protons at the PROSCAN area of the Proton Irradiation Facility at the PSI in Villigen, Switzerland. In-situ measurements of S-parameters in both tests allow the evaluation of frequency dependent performance parameters - like gain and input impedance - as a function of the fluence. The linearity of the ASIC response has been measured directly in the neutron tests with a triangular input pulse of...

  12. Wireless front-end with power management for an implantable cardiac microstimulator.

    Science.gov (United States)

    Lee, Shuenn-Yuh; Hsieh, Cheng-Han; Yang, Chung-Min

    2012-02-01

    Inductive coupling is presented with the help of a high-efficiency Class-E power amplifier for an implantable cardiac microstimulator. The external coil inductively transmits power and data with a carrier frequency of 256 kHz into the internal coil of electronic devices inside the body. The detected cardiac signal is fed back to the external device with the same pair of coils to save on space in the telemetry device. To maintain the power reliability of the microstimulator for long-term use, two small rechargeable batteries are employed to supply voltage to the internal circuits. The power management unit, which includes radio frequency front-end circuits with battery charging and detection functions, is used for the supply control. For cardiac stimulation, a high-efficiency charge pump is also proposed in the present paper to generate a stimulated voltage of 3.2 V under a 1 V supply voltage. A phase-locked-loop (PLL)-based phase shift keying demodulator is implemented to efficiently extract the data and clock from an inductive AC signal. The circuits, with an area of 0.45 mm², are implemented in a TSMC 0.35 μm 2P4M standard CMOS process. Measurement results reveal that power can be extracted from the inductive coupling and stored in rechargeable batteries, which are controlled by the power management unit, when one of the batteries is drained. Moreover, the data and clock can be precisely recovered from the coil coupling, and a stimulated voltage of 3.2 V can be readily generated by the proposed charge-pump circuits to stimulate cardiac tissues.

  13. System-Level Design of an Integrated Receiver Front End for a Wireless Ultrasound Probe

    DEFF Research Database (Denmark)

    di Ianni, Tommaso; Hemmsen, Martin Christian; Llimos Muntal, Pere

    2016-01-01

    In this paper, a system-level design is presented for an integrated receive circuit for a wireless ultrasound probe, which includes analog front ends and beamformation modules. This paper focuses on the investigation of the effects of architectural design choices on the image quality. The point s...

  14. POLARIS: ESA's airborne ice sounding radar front-end design, performance assessment and first results

    DEFF Research Database (Denmark)

    Hernández, Carlos Cilla; Krozer, Viktor; Vidkjær, Jens

    2009-01-01

    B noise figure, 160 ns receiver recovery time and -46 dBc 3rd order IMD products. The system comprises also, a digital front-end, a digital signal generator, a microstrip antenna array and a control unit. All the subsystems were integrated, certified and functionally tested, and in May 2008 a successful...

  15. Magnet Misalignment Studies for the Front-end of the Neutrino Factory

    CERN Document Server

    Prior, G; Stratakis, D; Neuffer, D; Snopok, P; Rogers, C

    2013-01-01

    In the Neutrino Factory front-end the muon beam coming from the interaction of a high-power (4 MW) proton beam on a mercury jet target is transformed through a buncher, a phase rotator and an ionization cooling channel before entering the downstream acceleration system. The muon front-end channel is densely packed with solenoid magnets, normal conducting radio-frequency cavities and absorber windows for the cooling section. The tolerance to the misalignment of the different components has to be determined in order on one hand to set the limits beyond which the performance of the front-end channel would be degraded; on the other hand to optimize the design and assembly of the front-end cells such that the component alignment can be checked and corrected for where crucial for the performance of the channel. In this paper we show the results of some of the simulations of the frontend channel performance where the magnetic field direction has been altered compared to the baseline.

  16. Systematic Approach to Formulate PSS Development Project Proposals in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Barquet, Ana Paula B.; Pigosso, Daniela Cristina Antelmi; Rozenfeld, Henrique

    2013-01-01

    be considered by companies during this definition. The systematization of PSS attributes may help increase the knowledge about different PSS projects that can emerge in the front end, thus leading to the discovery of opportunities that are not apparent in the existing business models and give rise to new ideas...... that can be translated into successful projects....

  17. Front-End Types. Automotive Mechanics. Steering & Suspension. Instructor's Guide [and] Student Guide.

    Science.gov (United States)

    Spignesi, B.

    This instructional package, one in a series of individualized instructional units on automotive steering and suspension, consists of a student guide and an instructor guide dealing with automobile front-end types. Covered in the module are three common types of passenger car front suspension systems and their major components as well as two types…

  18. Commissioning and Operation of the FNAL Front end Injection Line and Ion Sources.

    Energy Technology Data Exchange (ETDEWEB)

    Karns, Patrick R. [Indiana Univ., Bloomington, IN (United States)

    2015-09-01

    This thesis documents the efforts made in commissioning and operating the RFQ Injection Line (RIL) as a replacement for the Cockcroft Walton front end. The Low Energy Beam Transport (LEBT) was assembled and tested with multiwire position and emittance monitor measurements. The Radio Frequency Quadrupole (RFQ) commissioning was completed with the same measurements as well as output beam energy measurements that showed it initially accelerated beam only to 700 keV, which was 50 keV lower than the design energy. Working with the manufacturer solutions were found and instituted to continue testing. The Medium Energy Beam Transport (MEBT) was then connected as the RIL was installed as the new front end of Linac. Testing gave way to operation when the new front end was used as the source of all High Energy Physics (HEP) beam for Fermi National Accelerator Laboratory (FNAL). The magnetron ion source that provides the H- beam for the front end required several changes and eventual upgrades to operate well; such as new source operating points for vacuum pressure and cesium admixture, and new materials for critical source components. Further research was conducted on the cathode geometry and nitrogen doping of the hydrogen gas as well as using solid state switches for the extractor system high voltage.

  19. The ICARUS Front-end Preamplifier Working at Liquid Argon Temperature

    CERN Document Server

    Baibussinov, B; Casagrande, F; Cennini, P; Centro, S; Curioni, A; Meng, G; Picchi, P; Pietropaolo, F; Rubbia, C; Sergiampietri, F; Ventura, S

    2011-01-01

    We describe characteristics and performance of the low-noise front-end preamplifier used in the ICARUS 50-litre liquid Argon Time Projection Chamber installed in the CERN West Area Neutrino Facility during the 1997-98 neutrino runs. The preamplifiers were designed to work immersed in ultra-pure liquid Argon at a temperature of 87K.

  20. Social Networks in the Front End: The Organizational Life of an Idea

    NARCIS (Netherlands)

    R.C. Kijkuit (Bob)

    2007-01-01

    textabstractAn effective front end (FE) of the new product development (NPD) process is important for innovative performance in companies. To date the NPD literature has mainly focused on the selection process of ideas and very little on the processes that take place before selection. This study

  1. Compact Front-end Prototype for Next Generation RFI-rejecting Polarimetric L-band Radiometer

    DEFF Research Database (Denmark)

    Jensen, Brian Sveistrup; Søbjærg, Sten Schmidl; Skou, Niels

    2009-01-01

    Realizing the need for lower noise figure and smaller physical size in todays higly sensitive radiometers, this paper presents a new compact analog front-end (AFE) for use with the existing L-band (1400-1427 MHz) radiometer designed and operated by the Technical University of Denmark. Using subha...

  2. Structure and thermal analysis of the water cooling mask at NSRL front end

    International Nuclear Information System (INIS)

    Zhao Feiyun; Xu Chaoyin; Wang Qiuping; Wang Naxiu

    2003-01-01

    A water cooling mask is an important part of the front end, usually used for absorbing high power density synchrotron radiation to protect the apparatus from being destroyed by heat load. This paper presents the structure of the water cooling mask and the thermal analysis results of the mask block at NSRL using Program ANSYS5.5

  3. Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell

    DEFF Research Database (Denmark)

    Liscidini, Antonio; Mazzanti, Andrea; Tonietto, Riccardo

    2006-01-01

    This paper presents the first quadrature RF receiver front-end where, in a single stage, low-noise amplifier (LNA), mixer and voltage-controlled oscillator (VCO) share the same bias current. The new structure exploits the intrinsic mixing functionality of a classical LC-tank oscillator providing ...

  4. Active Feedback Technique for RF Channel Selection in Front-End Receivers

    NARCIS (Netherlands)

    Youssef, S.S.T.; van der Zee, Ronan A.R.; Nauta, Bram

    2012-01-01

    Co-existence problems in a mobile terminal environment pose strict requirements on the linearity of a front-end receiver. In this paper, active feedback is explored as a means to relax such requirements by providing channel selectivity as early as possible in the receiver chain. The proposed

  5. Practices of a "green" front end of innovation; A gateway to environmental innovation

    NARCIS (Netherlands)

    Hassi, L.; Wever, R.

    2010-01-01

    Activities in the fuzzy front end of the innovation process (FFE) are the root of success for any company hoping to compete on the basis of innovations. Considering the importance of the FFE, it would seem logical to bring the environmental considerations already to the activities of the early

  6. Predictive Duty Cycle Control of Three-Phase Active-Front-End Rectifiers

    DEFF Research Database (Denmark)

    Song, Zhanfeng; Tian, Yanjun; Chen, Wei

    2016-01-01

    This paper proposed an on-line optimizing duty cycle control approach for three-phase active-front-end rectifiers, aiming to obtain the optimal control actions under different operating conditions. Similar to finite control set model predictive control strategy, a cost function previously...

  7. The fuzziness of the fuzzy front end : the influence of non-technical factors

    NARCIS (Netherlands)

    Kiewiet, Derk Jan; van Engelen, Jo; Achterkamp, Marjolein; Chen, J; Xu, QR; Wu, XB

    2007-01-01

    The Fuzzy Front End (FFE) can be considered the most challenging part of the innovation process where large opportunities are to be found for an organization. Because of the inherently creative and non-routine characteristics of the FFE, only a small number of formal techniques are available to

  8. Systematic Approach to Formulate PSS Development Project Proposals in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Barquet, Ana Paula B.; Pigosso, Daniela Cristina Antelmi; Rozenfeld, Henrique

    2013-01-01

    patterns adopted for product development. Currently, there is not a systematic approach that can be followed for the formulation of PSS proposals in the fuzzy front end. Therefore, the aim of this research is to develop a method for defining PSS project proposals based on attributes that should...

  9. InP DHBT MMICs for millimeter-wave front-ends

    DEFF Research Database (Denmark)

    Johansen, Tom Keinicke; Hadziabdic, Dzenan; Krozer, Viktor

    2009-01-01

    In this paper, we show advanced MMIC's using InP DHBT technology. In particular, we demonstrate front-end circuits covering a broad frequency range from Q-band to E-band. Realizations of power amplifiers, quadrature VCOs, and sub-harmonic mixers, are presented and experimental results are discussed....

  10. Test of New Readout Electronics for the BONuS12 Experiment

    Energy Technology Data Exchange (ETDEWEB)

    Ehrhart, Mathieu [Inst. de Physique Nucleaire (IPN), Orsay (France)

    2017-07-01

    For decades, electron-proton scattering experiments have been providing a large amount of data on the proton structure function. However, because of the instability of free neutrons, fewer experiments have been able to study the neutron structure function. The BONuS collaboration at Jefferson Laboratory addresses this challenge by scattering electrons off a deuterium target, using a RTPC capable of detecting the low-momentum spectator protons near the target. Events of electrons scattering on almost free neutrons are selected by constraining the spectator protons to very low momenta and very backward scattering angles. In 2005, BONuS successfully measured the neutron structure with scattering electrons of up to 5.3 GeV energy. An extension of this measurement has been approved using the newly upgraded 12 GeV electron beam and CLAS12 (CEBAF Large Acceptance Spectrometer). For this new set of measurements, a new RTPC detector using GEM trackers is being developed to allow measurements of spectator protons with momenta as low as 70 MeV/c. The new RTPC will use a new readout electronic system, which is also used by other trackers in CLAS12. This thesis will present the first tests of this electronics using a previously built RTPC of similar design.

  11. Microwave Photonic Architecture for Direction Finding of LPI Emitters: Front End Analog Circuit Design and Component Characterization

    Science.gov (United States)

    2016-09-01

    PHOTONIC ARCHITECTURE FOR DIRECTION FINDING OF LPI EMITTERS: FRONT-END ANALOG CIRCUIT DESIGN AND COMPONENT CHARACTERIZATION by Chew K. Tan... PHOTONIC ARCHITECTURE FOR DIRECTION FINDING OF LPI EMITTERS: FRONT-END ANALOG CIRCUIT DESIGN AND COMPONENT CHARACTERIZATION 5. FUNDING NUMBERS 6. AUTHOR...miniature microwave- photonic phase-sampling DF technique is investigated in this thesis. This front-end design uses a combination of integrated optical

  12. Soft X-ray imaging with axisymmetry microscope and electronic readout

    International Nuclear Information System (INIS)

    Sauneuf, A.; Cavailler, C.; Henry, Ph.; Launspach, J.; Mascureau, J. de; Rostaing, M.

    1984-11-01

    An axisymmetric microscope with 10 X magnification has been constructed; its resolution has been measured using severals grids, backlighted by an X-ray source and found to be near 25 μm. So it could be used to make images of laser driven plasmas in the soft X-ray region. In order to see rapidly those images we have associated it with a new detector. It is a small image converter tube with a soft X-ray photocathode and a P20 phosphor deposited on an optic fiber plate. The electronic image appearing on the screen is read by a CCD working in the spectral range. An electronic image readout chain, which is identical to those we use with streak cameras, then processes automatically and immediatly the images given by the microscope

  13. Test Beam Studies for the ATLAS Tile Calorimeter Upgrade Readout Electronics

    CERN Document Server

    Schaefer, Douglas; The ATLAS collaboration

    2018-01-01

    The High Luminosity Large Hadron Collider is expected to deliver 3-4/ab of p-p collisions with around 200 collisions per proton bunch crossing starting in 2026, and the readout electronics of the ATLAS Tile Calorimeter need to be upgraded to deal with the high rate of data taking as well as the large pileup conditions. The proposed digitizer/shaper cards were tested in 2016-7 in the North Area at CERN using the beam from the SPS to produce high energy pions, electrons, muons, and kaons. This presentation summarizes the setup for particle identification and study of the ATLAS Tile Calorimeter data taking in preparation for the production of main boards and digitizer/shaper boards for the photo-multiplier tubes. The fully assembled and tested mini-drawers will start to be installed after the LHC long shutdown in December 2023. The pulse shape, uniformity, and timing precision of the upgrade system are demonstrated.

  14. Parameters-adjustable front-end controller in digital nuclear measurement system

    International Nuclear Information System (INIS)

    Hao Dejian; Zhang Ruanyu; Yan Yangyang; Wang Peng; Tang Changjian

    2013-01-01

    Background: One digitizer is used to implement a digital nuclear measurement for the acquisition of nuclear information. Purpose: A principle and method of a parameter-adjustable front-end controller is presented for the sake of reducing the quantitative errors while getting the maximum ENOB (effective number of bits) of ADC (analog-to-digital converter) during waveform digitizing, as well as reducing the losing counts. Methods: First of all, the quantitative relationship among the radiation count rate (n), the amplitude of input signal (V in ), the conversion scale of ADC (±V) and the amplification factor (A) was derived. Secondly, the hardware and software of the front-end controller were designed to fulfill matching the output of different detectors, adjusting the amplification linearly through the control of channel switching, and setting of digital potentiometer by CPLD (Complex Programmable Logic Device). Results: (1) Through the measurement of γ-ray of Am-241 under our digital nuclear measurement set-up with CZT detector, it was validated that the amplitude of output signal of detectors of RC feedback type could be amplified linearly with adjustable amplification by the front-end controller. (2) Through the measurement of X-ray spectrum of Fe-5.5 under our digital nuclear measurement set-up with Si-PIN detector, it was validated that the front-end controller was suitable for the switch resetting type detectors, by which high precision measurement under various count rates could be fulfilled. Conclusion: The principle and method of the parameter-adjustable front-end controller presented in this paper is correct and feasible. (authors)

  15. Measurement of the front-end dead-time of the LHCb muon detector and evaluation of its contribution to the muon detection inefficiency

    CERN Document Server

    INSPIRE-00357120; Archilli, F.; Auriemma, G.; Baldini, W.; Bencivenni, G.; Bizzeti, A.; Bocci, V.; Bondar, N.; Bonivento, W.; Bochin, B.; Bozzi, C.; Brundu, D.; Cadeddu, S.; Campana, P.; Carboni, G.; Cardini, A.; Carletti, M.; Casu, L.; Chubykin, A.; Ciambrone, P.; Dané, E.; De Simone, P.; Falabella, A.; Felici, G.; Fiore, M.; Fontana, M.; Fresch, P.; Furfaro, E.; Graziani, G.; Kashchuk, A.; Kotriakhova, S.; Lai, A.; Lanfranchi, G.; Loi, A.; Maev, O.; Manca, G.; Martellotti, G.; Neustroev, P.; Oldeman, R.G.C.; Palutan, M.; Passaleva, G.; Penso, G.; Pinci, D.; Polycarpo, E.; Saitta, B.; Santacesaria, R.; Santimaria, M.; Santovetti, E.; Saputi, A.; Sarti, A.; Satriano, C.; Satta, A.; Schmidt, B.; Schneider, T.; Sciascia, B.; Sciubba, A.; Siddi, B.G.; Tellarini, G.; Vacca, C.; Vazquez-Gomez, R.; Vecchi, S.; Veltri, M.; Vorobyev, A.

    2016-04-06

    A method is described which allows to deduce the dead-time of the front-end electronics of the LHCb muon detector from a series of measurements performed at different luminosities at a bunch-crossing rate of 20 MHz. The measured values of the dead-time range from 70 ns to 100 ns. These results allow to estimate the performance of the muon detector at the future bunch-crossing rate of 40 MHz and at higher luminosity.

  16. Common Bias Readout for TES Array on Scanning Transmission Electron Microscope

    Science.gov (United States)

    Yamamoto, R.; Sakai, K.; Maehisa, K.; Nagayoshi, K.; Hayashi, T.; Muramatsu, H.; Nakashima, Y.; Mitsuda, K.; Yamasaki, N. Y.; Takei, Y.; Hidaka, M.; Nagasawa, S.; Maehata, K.; Hara, T.

    2016-07-01

    A transition edge sensor (TES) microcalorimeter array as an X-ray sensor for a scanning transmission electron microscope system is being developed. The technical challenge of this system is a high count rate of ˜ 5000 counts/second/array. We adopted a 64 pixel array with a parallel readout. Common SQUID bias, and common TES bias are planned to reduce the number of wires and the resources of a room temperature circuit. The reduction rate of wires is 44 % when a 64 pixel array is read out by a common bias of 8 channels. The possible degradation of the energy resolution has been investigated by simulations and experiments. The bias fluctuation effects of a series connection are less than those of a parallel connection. Simple calculations expect that the fluctuations of the common SQUID bias and common TES bias in a series connection are 10^{-7} and 10^{-3}, respectively. We constructed 8 SQUIDs which are connected to 8 TES outputs and a room temperature circuit for common bias readout and evaluated experimentally. Our simulation of crosstalk indicates that at an X-ray event rate of 500 cps/pixel, crosstalk will broaden a monochromatic line by about 0.01 %, or about 1.5 eV at 15 keV. Thus, our design goal of 10 eV energy resolution across the 0.5-15 keV band should be achievable.

  17. Readout of non-irradiated and irradiated strip detectors with fast analogue electronics

    CERN Document Server

    Cindro, V; Mikuz, M; Zontar, D; Kaplon, J; Riedler, P; Roe, S; Weilhammer, Peter; Dabrowski, W

    2000-01-01

    Silicon microstrip detectors with 50 mu m readout pitch were connected to fast LHC-type analogue readout electronics (DMILL SCT32A) and their performance evaluated before and after irradiation. The p-type strips with a length of 4 cm were fabricated on high- resistivity n-bulk wafers by CSEM. Fast neutrons from the TRIGA research reactor in Ljubljana were used to irradiate detectors to two different fluences: 4.5*10/sup 13/ and 1.5*10/sup 14//cm/sup 2/ 1 MeV neutron equivalent non-ionizing energy loss. A /sup 90/Sr beta source setup was used for detector performance measurements. Most of the observed signal/noise degradation after irradiation could be attributed to the signal loss. Around 82Xharge collection efficiency was measured at higher fluence 100 V above full depletion voltage as determined with C-V measurements. Measurements were performed during annealing and reverse annealing of effective dopant concentration. (9 refs).

  18. Phase - I Trigger Readout Electronics upgrade for the ATLAS Liquid Argon Calorimeters

    CERN Document Server

    Dinkespiler, Bernard; The ATLAS collaboration

    2017-01-01

    The upgrade of the Large Hadron Collider (LHC) scheduled for shut-down period of 2018-2019, referred to as Phase-I upgrade, will increase the instantaneous luminosity to about three times the design value. Since the current ATLAS trigger system does not allow sufficient increase of the trigger rate, an improvement of the trigger system is required. The Liquid Argon (LAr) Calorimeter read-out will therefore be modified to use digital trigger signals with a higher spatial granularity in order to improve the identification efficiencies of electrons, photons, tau, jets and missing energy, at high background rejection rates at the Level-1 trigger. The new trigger signals will be arranged in 34000 so-called Super Cells which achieves 5-10 times better granularity than the trigger towers currently used and allows an improved background rejection. The readout of the trigger signals will process the signal of the Super Cells at every LHC bunch-crossing at 12-bit precision and a frequency of 40 MHz. The data will be tr...

  19. Development of Cryogenic Readout Electronics for Sensitive Far-Infrared Detectors

    Science.gov (United States)

    Watabe, Toyoki; Shibai, Hiroshi; Hirao, Takanori; Nagata, Hirohisa; Hibi, Yasunori; Kawada, Mitsunobu; Nakagawa, Takao; Noda, Manabu

    We have successfully developed low-noise, low-power cryogenic readout electronics (CRE) for sensitive far-infrared detectors operated at low temperatures. The CRE must be mounted besides of the detector, and thus, it must be operated at cryogenic temperatures. The reasons of that are to avoid electrical interferences to the high-impedance portion between the detector itself and the CRE, and to minimize the stray capacitance that may decrease the read-out gain. The goals of the CRE performance are the operation temperature can be down to 2K, the noise level is 2µV/√Hz at 1Hz, the power consumption is 10µW/channel, and the open-loop gain of differential amplifier is over 1000. We have so far manufactured the CRE four times, and evaluated the performances at 4.2K. The present performance achieved is nearly acceptable for the far-infrared sensor of the next Japanese infrared astronomical satellite, ASTRO-F.

  20. Phase-I Trigger Readout Electronics Upgrade for the ATLAS Liquid-Argon Calorimeters

    CERN Document Server

    Camplani, Alessandra; The ATLAS collaboration

    2017-01-01

    The upgrade of the Large Hadron Collider (LHC) scheduled for shut-down period of 2018-2019, referred to as Phase-I upgrade, will increase the instantaneous luminosity to about three times the design value. Since the current ATLAS trigger system does not allow sufficient increase of the trigger rate, an improvement of the trigger system is required. The Liquid Argon (LAr) Calorimeter read-out will therefore be modified to use digital trigger signals with a higher spatial granularity in order to improve the identification efficiencies of electrons, photons, tau, jets and missing energy, at high background rejection rates at the Level-1 trigger. The new trigger signals will be arranged in 34000 so-called Super Cells which achieves 5-10 times better granularity than the trigger towers currently used and allows an improved background rejection. The readout of the trigger signals will process the signal of the Super Cells at every LHC bunch-crossing at 12-bit precision and a frequency of 40 MHz. The data will be tr...