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Sample records for fpga block structures

  1. Technologies for faults diagnosis of FPGA logic blocks

    Directory of Open Access Journals (Sweden)

    C. U. Ngene

    2012-08-01

    Full Text Available The critical issues of testing field programmable gate arrays (FPGA with a view to diagnosing faults are an important step that ensures the reliability of FPGA designs. Correct diagnosis of faulty logic blocks of FPGAs guarantees restoration of functionality through replacement of faulty block with replacement units. This process can be done autonomously or without the intervention of an engineer depending on application area. This paper considers two methods for analysing test results of FPGA logic blocks with the purpose of localising and distinguishing faults. The algebraic logic and vector-logical methods are proposed for diagnosing faulty logic blocks in FPGA fabric. It is found that the algebraic logic method is more useful for processing of sparse faults tables when the number of coordinates with 1s values with respect to zero values ​​is not more than 20%, whereas the vector-logical method facilitates the analysis of faults table with predominance of 1s values.

  2. Design for an IO block array in a tile-based FPGA

    International Nuclear Information System (INIS)

    Ding Guangxin; Chen Lingdou; Liu Zhongli

    2009-01-01

    A design for an IO block array in a tile-based FPGA is presented. Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers. Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area. The local routing pool increases the flexibility of routing and the routability of the whole FPGA. An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards. The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool. This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series. The bond-out schemes of the same FPGA chip in different packages are also considered. The layout is based on SMIC 0.13 μm logic 1P8M salicide 1.2/2.5 V CMOS technology. Our performance is comparable with commercial SRAM-based FPGAs which use a similar process. (semiconductor integrated circuits)

  3. FPGA Implementation of Block Parallel DF-MPIC Detectors for DS-CDMA Systems in Frequency-Nonselective Channels

    Directory of Open Access Journals (Sweden)

    Adel Omar Dahmane

    2008-01-01

    Full Text Available Multistage parallel interference cancellation- (MPIC- based detectors allow to mitigate multiple-access interference in direct-sequence code-division multiple-access (DS-CDMA systems. They are considered serious candidates for practical implementation showing a good tradeoff between performance and complexity. Better performance is obtained when decision feedback (DF is employed. Although MPIC and DF-MPIC have the same arithmetic complexity, DF-MPIC needs much more FPGA resources when compared to MPIC without decision feedback. In this letter, FPGA implementation of block parallel DF-MPIC (BP-DF-MPIC is proposed allowing better tradeoff between performance and FPGA area occupancy. To reach an uncoded bit-error rate of 10−3, BP-DF-MPIC shows a 1.5 dB improvement over the MPIC without decision feedback with only 8% increase in FPGA resources compared to 69% for DF-MPIC.

  4. Area, speed and power measurements of FPGA-based complex orthogonal space-time block code channel encoders

    Science.gov (United States)

    Passas, Georgios; Freear, Steven; Fawcett, Darren

    2010-01-01

    Space-time coding (STC) is an important milestone in modern wireless communications. In this technique, more copies of the same signal are transmitted through different antennas (space) and different symbol periods (time), to improve the robustness of a wireless system by increasing its diversity gain. STCs are channel coding algorithms that can be readily implemented on a field programmable gate array (FPGA) device. This work provides some figures for the amount of required FPGA hardware resources, the speed that the algorithms can operate and the power consumption requirements of a space-time block code (STBC) encoder. Seven encoder very high-speed integrated circuit hardware description language (VHDL) designs have been coded, synthesised and tested. Each design realises a complex orthogonal space-time block code with a different transmission matrix. All VHDL designs are parameterisable in terms of sample precision. Precisions ranging from 4 bits to 32 bits have been synthesised. Alamouti's STBC encoder design [Alamouti, S.M. (1998), 'A Simple Transmit Diversity Technique for Wireless Communications', IEEE Journal on Selected Areas in Communications, 16:55-108.] proved to be the best trade-off, since it is on average 3.2 times smaller, 1.5 times faster and requires slightly less power than the next best trade-off in the comparison, which is a 3/4-rate full-diversity 3Tx-antenna STBC.

  5. Hamming Weight Counters and Comparators based on Embedded DSP Blocks for Implementation in FPGA

    Directory of Open Access Journals (Sweden)

    SKLYAROV, V.

    2014-05-01

    Full Text Available This paper is dedicated to the design, implementation and evaluation of fast FPGA-based circuits that compute Hamming weights for binary vectors and compare the results with fixed thresholds and variable bounds. It is shown that digital signal processing (DSP slices that are widely available in contemporary FPGAs may be used efficiently and they frequently provide the fastest and least resource consuming solutions. A thorough analysis and comparison of these with the best known alternatives both in hardware and in software is presented. The results are supported by numerous experiments in recent prototyping boards. A fully synthesizable hardware description language (VHDL specification for one of the proposed core components is given that is ready to be synthesized, implemented, tested and compared in any FPGA that contains embedded DSP48E1 slices (or alternatively DSP48A1 slices from previous generations. Finally, the results of comparisons are provided that include discussions of designs in an ARM processor combined with reconfigurable logic for very long vectors.

  6. Fine-grained parallelism accelerating for RNA secondary structure prediction with pseudoknots based on FPGA.

    Science.gov (United States)

    Xia, Fei; Jin, Guoqing

    2014-06-01

    PKNOTS is a most famous benchmark program and has been widely used to predict RNA secondary structure including pseudoknots. It adopts the standard four-dimensional (4D) dynamic programming (DP) method and is the basis of many variants and improved algorithms. Unfortunately, the O(N(6)) computing requirements and complicated data dependency greatly limits the usefulness of PKNOTS package with the explosion in gene database size. In this paper, we present a fine-grained parallel PKNOTS package and prototype system for accelerating RNA folding application based on FPGA chip. We adopted a series of storage optimization strategies to resolve the "Memory Wall" problem. We aggressively exploit parallel computing strategies to improve computational efficiency. We also propose several methods that collectively reduce the storage requirements for FPGA on-chip memory. To the best of our knowledge, our design is the first FPGA implementation for accelerating 4D DP problem for RNA folding application including pseudoknots. The experimental results show a factor of more than 50x average speedup over the PKNOTS-1.08 software running on a PC platform with Intel Core2 Q9400 Quad CPU for input RNA sequences. However, the power consumption of our FPGA accelerator is only about 50% of the general-purpose micro-processors.

  7. The effect of structural design parameters on FPGA-based feed-forward space-time trellis coding-orthogonal frequency division multiplexing channel encoders

    Science.gov (United States)

    Passas, Georgios; Freear, Steven; Fawcett, Darren

    2010-08-01

    Orthogonal frequency division multiplexing (OFDM)-based feed-forward space-time trellis code (FFSTTC) encoders can be synthesised as very high speed integrated circuit hardware description language (VHDL) designs. Evaluation of their FPGA implementation can lead to conclusions that help a designer to decide the optimum implementation, given the encoder structural parameters. VLSI architectures based on 1-bit multipliers and look-up tables (LUTs) are compared in terms of FPGA slices and block RAMs (area), as well as in terms of minimum clock period (speed). Area and speed graphs versus encoder memory order are provided for quadrature phase shift keying (QPSK) and 8 phase shift keying (8-PSK) modulation and two transmit antennas, revealing best implementation under these conditions. The effect of number of modulation bits and transmit antennas on the encoder implementation complexity is also investigated.

  8. Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures

    Directory of Open Access Journals (Sweden)

    James Coole

    2010-01-01

    Full Text Available Field-programmable gate arrays (FPGAs and other reconfigurable computing (RC devices have been widely shown to have numerous advantages including order of magnitude performance and power improvements compared to microprocessors for some applications. Unfortunately, FPGA usage has largely been limited to applications exhibiting sequential memory access patterns, thereby prohibiting acceleration of important applications with irregular patterns (e.g., pointer-based data structures. In this paper, we present a design pattern for RC application development that serializes irregular data structure traversals online into a traversal cache, which allows the corresponding data to be efficiently streamed to the FPGA. The paper presents a generalized framework that benefits applications with repeated traversals, which we show can achieve between 7x and 29x speedup over pointer-based software. For applications without strictly repeated traversals, we present application-specialized extensions that benefit applications with highly similar traversals by exploiting similarity to improve memory bandwidth and execute multiple traversals in parallel. We show that these extensions can achieve a speedup between 11x and 70x on a Virtex4 LX100 for Barnes-Hut n-body simulation.

  9. Naming Block Structures: A Multimodal Approach

    Science.gov (United States)

    Cohen, Lynn; Uhry, Joanna

    2011-01-01

    This study describes symbolic representation in block play in a culturally diverse suburban preschool classroom. Block play is "multimodal" and can allow children to experiment with materials to represent the world in many forms of literacy. Combined qualitative and quantitative data from seventy-seven block structures were collected and analyzed.…

  10. FPGA design

    CERN Document Server

    Simpson, Philip

    2010-01-01

    This book describes best practices for successful FPGA design. It is the result of the author's meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book's content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design t

  11. High speed true random number generator with a new structure of coarse-tuning PDL in FPGA

    Science.gov (United States)

    Fang, Hongzhen; Wang, Pengjun; Cheng, Xu; Zhou, Keji

    2018-03-01

    A metastability-based TRNG (true random number generator) is presented in this paper, and implemented in FPGA. The metastable state of a D flip-flop is tunable through a two-stage PDL (programmable delay line). With the proposed coarse-tuning PDL structure, the TRNG core does not require extra placement and routing to ensure its entropy. Furthermore, the core needs fewer stages of coarse-tuning PDL at higher operating frequency, and thus saves more resources in FPGA. The designed TRNG achieves 25 Mbps @ 100 MHz throughput after proper post-processing, which is several times higher than other previous TRNGs based on FPGA. Moreover, the robustness of the system is enhanced with the adoption of a feedback system. The quality of the designed TRNG is verified by NIST (National Institute of Standards and Technology) and also accepted by class P1 of the AIS-20/31 test suite. Project supported by the S&T Plan of Zhejiang Provincial Science and Technology Department (No. 2016C31078), the National Natural Science Foundation of China (Nos. 61574041, 61474068, 61234002), and the K.C. Wong Magna Fund in Ningbo University, China.

  12. Autonomous Lawnmower using FPGA implementation.

    Science.gov (United States)

    Ahmad, Nabihah; Lokman, Nabill bin; Helmy Abd Wahab, Mohd

    2016-11-01

    Nowadays, there are various types of robot have been invented for multiple purposes. The robots have the special characteristic that surpass the human ability and could operate in extreme environment which human cannot endure. In this paper, an autonomous robot is built to imitate the characteristic of a human cutting grass. A Field Programmable Gate Array (FPGA) is used to control the movements where all data and information would be processed. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is used to describe the hardware using Quartus II software. This robot has the ability of avoiding obstacle using ultrasonic sensor. This robot used two DC motors for its movement. It could include moving forward, backward, and turning left and right. The movement or the path of the automatic lawn mower is based on a path planning technique. Four Global Positioning System (GPS) plot are set to create a boundary. This to ensure that the lawn mower operates within the area given by user. Every action of the lawn mower is controlled by the FPGA DE' Board Cyclone II with the help of the sensor. Furthermore, Sketch Up software was used to design the structure of the lawn mower. The autonomous lawn mower was able to operate efficiently and smoothly return to coordinated paths after passing the obstacle. It uses 25% of total pins available on the board and 31% of total Digital Signal Processing (DSP) blocks.

  13. Design and FPGA Implementation of Variable Cutoff Frequency Filter based on Continuously Variable Fractional Delay Structure and Interpolation Technique

    Directory of Open Access Journals (Sweden)

    Sumedh Dhabu

    2015-09-01

    Full Text Available This paper presents the design and FPGA implementation of interpolated continuously variable fractional delay structure based filter (ICVFD filter with fine control over the cutoff frequency. In the ICVFD filter, each unit delay of the prototype lowpass filter is replaced by a continuously variable fractional delay (CVFD element proposed in this paper. The CVFD element requires the same number of multiplications as that of the second-order fractional delay structure used in the existing fractional delay structure based variable filter (FDS based filter, however it provides fractional delays corresponding to the higher-order fractional delay structures. Hence, the proposed ICVFD filter provides wider cutoff frequency range compared to the FDS based filter. The ICVFD filter is also capable of providing variable bandpass and highpass responses. We use two-stage approach for the FPGA implementation of the ICVFD filter. First, we use pipelining stages to shorten the critical path and improve the operating frequency. Then, we make use of specific hardware resource, i.e. RAM-based Shift Register (SRL to further improve the operating frequency and resource usage.

  14. From OO to FPGA :

    Energy Technology Data Exchange (ETDEWEB)

    Kou, Stephen; Palsberg, Jens; Brooks, Jeffrey

    2012-09-01

    Consumer electronics today such as cell phones often have one or more low-power FPGAs to assist with energy-intensive operations in order to reduce overall energy consumption and increase battery life. However, current techniques for programming FPGAs require people to be specially trained to do so. Ideally, software engineers can more readily take advantage of the benefits FPGAs offer by being able to program them using their existing skills, a common one being object-oriented programming. However, traditional techniques for compiling object-oriented languages are at odds with todays FPGA tools, which support neither pointers nor complex data structures. Open until now is the problem of compiling an object-oriented language to an FPGA in a way that harnesses this potential for huge energy savings. In this paper, we present a new compilation technique that feeds into an existing FPGA tool chain and produces FPGAs with up to almost an order of magnitude in energy savings compared to a low-power microprocessor while still retaining comparable performance and area usage.

  15. Determining the Mechanical Properties of Lattice Block Structures

    Science.gov (United States)

    Wilmoth, Nathan

    2013-01-01

    Lattice block structures and shape memory alloys possess several traits ideal for solving intriguing new engineering problems in industries such as aerospace, military, and transportation. Recent testing at the NASA Glenn Research Center has investigated the material properties of lattice block structures cast from a conventional aerospace titanium alloy as well as lattice block structures cast from nickel-titanium shape memory alloy. The lattice block structures for both materials were sectioned into smaller subelements for tension and compression testing. The results from the cast conventional titanium material showed that the expected mechanical properties were maintained. The shape memory alloy material was found to be extremely brittle from the casting process and only compression testing was completed. Future shape memory alloy lattice block structures will utilize an adjusted material composition that will provide a better quality casting. The testing effort resulted in baseline mechanical property data from the conventional titanium material for comparison to shape memory alloy materials once suitable castings are available.

  16. Block Tridiagonal Matrices in Electronic Structure Calculations

    DEFF Research Database (Denmark)

    Petersen, Dan Erik

    in the Landauer–Büttiker ballistic transport regime. These calculations concentrate on determining the so– called Green’s function matrix, or portions thereof, which is the inverse of a block tridiagonal general complex matrix. To this end, a sequential algorithm based on Gaussian elimination named Sweeps...

  17. Elementary structural building blocks encountered in silicon surface reconstructions

    International Nuclear Information System (INIS)

    Battaglia, Corsin; Monney, Claude; Didiot, Clement; Schwier, Eike Fabian; Garnier, Michael Gunnar; Aebi, Philipp; Gaal-Nagy, Katalin; Onida, Giovanni

    2009-01-01

    Driven by the reduction of dangling bonds and the minimization of surface stress, reconstruction of silicon surfaces leads to a striking diversity of outcomes. Despite this variety even very elaborate structures are generally comprised of a small number of structural building blocks. We here identify important elementary building blocks and discuss their integration into the structural models as well as their impact on the electronic structure of the surface. (topical review)

  18. Structuring oil by protein building blocks

    NARCIS (Netherlands)

    Vries, de Auke

    2017-01-01

    Over the recent years, structuring of oil into ‘organogels’ or ‘oleogels’ has gained much attention amongst colloid-, material,- and food scientists. Potentially, these oleogels could be used as an alternative for saturated- and trans fats in food products. To develop oleogels as a

  19. An Optimized Structure on FPGA of Key Point Detection in SIFT Algorithm

    Directory of Open Access Journals (Sweden)

    Xu Chenyu

    2016-01-01

    Full Text Available SIFT algorithm is the most efficient and powerful algorithm to describe the features of images and it has been applied in many fields. In this paper, we propose an optimized method to realize the hardware implementation of the SIFT algorithm. We mainly discuss the structure of Data Generation here. A pipeline architecture is introduced to accelerate this optimized system. Parameters’ setting and approximation’s controlling in different image qualities and hardware resources are the focus of this paper. The results of experiments fully prove that this structure is real-time and effective, and provide consultative opinion to meet the different situations.

  20. Phonons as building blocks in nuclear structure

    International Nuclear Information System (INIS)

    Silvestre-Brac, B.

    1980-01-01

    The structure of a nuclear system in terms of eigenmodes (phonons) of subsystems is investigated in three different approaches. In the frame of nuclear field theory the three identical particle system is analysed and the elimination of spurious states due to the violation of the Pauli principle is emphasized. In terms of weak coupling, a new approach of the shell model is proposed which is shown to be rapidly convergent with the number of basis vectors. Applications of three particle systems in the lead region are made. Lastly, a microscopic multiphonon theorie of collective K=0 states in deformed nuclei based on a Tamm Dancoff phonon is developed. The role of the Pauli principle as well as comparisons with boson expansion methods are deeply analysed [fr

  1. Initial Mechanical Testing of Superalloy Lattice Block Structures Conducted

    Science.gov (United States)

    Krause, David L.; Whittenberger, J. Daniel

    2002-01-01

    The first mechanical tests of superalloy lattice block structures produced promising results for this exciting new lightweight material system. The testing was performed in-house at NASA Glenn Research Center's Structural Benchmark Test Facility, where small subelement-sized compression and beam specimens were loaded to observe elastic and plastic behavior, component strength levels, and fatigue resistance for hundreds of thousands of load cycles. Current lattice block construction produces a flat panel composed of thin ligaments arranged in a three-dimensional triangulated trusslike structure. Investment casting of lattice block panels has been developed and greatly expands opportunities for using this unique architecture in today's high-performance structures. In addition, advances made in NASA's Ultra-Efficient Engine Technology Program have extended the lattice block concept to superalloy materials. After a series of casting iterations, the nickel-based superalloy Inconel 718 (IN 718, Inco Alloys International, Inc., Huntington, WV) was successfully cast into lattice block panels; this combination offers light weight combined with high strength, high stiffness, and elevated-temperature durability. For tests to evaluate casting quality and configuration merit, small structural compression and bend test specimens were machined from the 5- by 12- by 0.5-in. panels. Linear elastic finite element analyses were completed for several specimen layouts to predict material stresses and deflections under proposed test conditions. The structural specimens were then subjected to room-temperature static and cyclic loads in Glenn's Life Prediction Branch's material test machine. Surprisingly, the test results exceeded analytical predictions: plastic strains greater than 5 percent were obtained, and fatigue lives did not depreciate relative to the base material. These assets were due to the formation of plastic hinges and the redundancies inherent in lattice block construction

  2. Structural analysis of ceramic blocks sealing or structural incorporated with the industrial laundry sludge

    International Nuclear Information System (INIS)

    Almeida, P.H.S.; Grippe, V.Y.Q.; Goulart, J.V.

    2016-01-01

    Industrial and commercial development of recent decades has led to an increase in waste generation. Thus, it is necessary to develop alternative and effective methods of treatment, replacing the simple disposal of these wastes in landfills. The objective of this work is to study the incorporation of textile industrial laundries sludge in ceramic blocks sealing or structural. Samples of ceramic blocks were produced using formulation with 20% sludge, the mass of ceramic clay. Structural analysis of the block was observed the tendency of most empty emergence (pores) during the firing of the blocks, as textile sludge was added in the ceramic paste composition. The mechanical testing of blocks compressive strength was above the minimum 3.0 MPa specified by the standard limit. The physical test water absorption of the blocks was within the range 8 to 22% specified by the standard. (author)

  3. FPGA Design Methodologies Applicable to Nuclear Power Plants

    International Nuclear Information System (INIS)

    Kwong, Yongil; Jeong, Choongheui

    2013-01-01

    In order to solve the above problem, NPPs in some countries such as the US, Canada and Japan have already applied FPGA-based equipment which has advantages as follows: It is easier to verify the performance because it needs only HDL code to configure logic circuits without other software, compared to microprocessor-based equipment, It is much cheaper than ASIC in a small quantity, Its logic circuits are re configurable, It has enough resources like logic blocks and memory blocks to implement I and C functions, Multiple functions can be implemented in a FPGA chip, It is stronger with respect to carboy security than microprocessor-based equipment because its configuration cannot be changed by external access, It is simple to replace it with new one when it is obsolete, Its power consumption is lower. However, FPGA-based equipment does not have only the merits. There are some issues on its application to NPPs. First of all, the experiences in applying it to NPPs are much less than to other industries, and international standards or guidelines are also very few. And there is the small number of FPGA platforms for I and C systems. Finally, the specific guidelines on FPGA design are required because the design has both hardware and software characteristics. In order to handle the above issues, KINS(Korea Institute of Nuclear Safety) built a test platform last year and have developed regulatory guidelines for FPGA-application in NPPs. I and C systems of NPPs have been increasingly using FPGA-based equipment as an alternative of microprocessor-based equipment which is not simple to be evaluated for safety due to its complexity. This paper explained the FPGA design flow and design guidelines. Those methodologies can be used as the guidelines on FPGA verification for safety of I and C systems

  4. Efficient Eulerian gyrokinetic simulations with block-structured grids

    International Nuclear Information System (INIS)

    Jarema, Denis

    2017-01-01

    Gaining a deep understanding of plasma microturbulence is of paramount importance for the development of future nuclear fusion reactors, because it causes a strong outward transport of heat and particles. Gyrokinetics has proven itself as a valid mathematical model to simulate such plasma microturbulence effects. In spite of the advantages of this model, nonlinear radially extended (or global) gyrokinetic simulations are still extremely computationally expensive, involving a very large number of computational grid points. Hence, methods that reduce the number of grid points without a significant loss of accuracy are a prerequisite to be able to run high-fidelity simulations. At the level of the mathematical model, the gyrokinetic approach achieves a reduction from six to five coordinates in comparison to the fully kinetic models. This reduction leads to an important decrease in the total number of computational grid points. However, the velocity space mixed with the radial direction still requires a very fine resolution in grid based codes, due to the disparities in the thermal speed, which are caused by a strong temperature variation along the radial direction. An attempt to address this problem by modifying the underlying gyrokinetic set of equations leads to additional nonlinear terms, which are the most expensive parts to simulate. Furthermore, because of these modifications, well-established and computationally efficient implementations developed for the original set of equations can no longer be used. To tackle such issues, in this thesis we introduce an alternative approach of blockstructured grids. This approach reduces the number of grid points significantly, but without changing the underlying mathematical model. Furthermore, our technique is minimally invasive and allows the reuse of a large amount of already existing code using rectilinear grids, modifications being necessary only on the block boundaries. Moreover, the block-structured grid can be

  5. Efficient Eulerian gyrokinetic simulations with block-structured grids

    Energy Technology Data Exchange (ETDEWEB)

    Jarema, Denis

    2017-01-20

    Gaining a deep understanding of plasma microturbulence is of paramount importance for the development of future nuclear fusion reactors, because it causes a strong outward transport of heat and particles. Gyrokinetics has proven itself as a valid mathematical model to simulate such plasma microturbulence effects. In spite of the advantages of this model, nonlinear radially extended (or global) gyrokinetic simulations are still extremely computationally expensive, involving a very large number of computational grid points. Hence, methods that reduce the number of grid points without a significant loss of accuracy are a prerequisite to be able to run high-fidelity simulations. At the level of the mathematical model, the gyrokinetic approach achieves a reduction from six to five coordinates in comparison to the fully kinetic models. This reduction leads to an important decrease in the total number of computational grid points. However, the velocity space mixed with the radial direction still requires a very fine resolution in grid based codes, due to the disparities in the thermal speed, which are caused by a strong temperature variation along the radial direction. An attempt to address this problem by modifying the underlying gyrokinetic set of equations leads to additional nonlinear terms, which are the most expensive parts to simulate. Furthermore, because of these modifications, well-established and computationally efficient implementations developed for the original set of equations can no longer be used. To tackle such issues, in this thesis we introduce an alternative approach of blockstructured grids. This approach reduces the number of grid points significantly, but without changing the underlying mathematical model. Furthermore, our technique is minimally invasive and allows the reuse of a large amount of already existing code using rectilinear grids, modifications being necessary only on the block boundaries. Moreover, the block-structured grid can be

  6. Computer vision camera with embedded FPGA processing

    Science.gov (United States)

    Lecerf, Antoine; Ouellet, Denis; Arias-Estrada, Miguel

    2000-03-01

    Traditional computer vision is based on a camera-computer system in which the image understanding algorithms are embedded in the computer. To circumvent the computational load of vision algorithms, low-level processing and imaging hardware can be integrated in a single compact module where a dedicated architecture is implemented. This paper presents a Computer Vision Camera based on an open architecture implemented in an FPGA. The system is targeted to real-time computer vision tasks where low level processing and feature extraction tasks can be implemented in the FPGA device. The camera integrates a CMOS image sensor, an FPGA device, two memory banks, and an embedded PC for communication and control tasks. The FPGA device is a medium size one equivalent to 25,000 logic gates. The device is connected to two high speed memory banks, an IS interface, and an imager interface. The camera can be accessed for architecture programming, data transfer, and control through an Ethernet link from a remote computer. A hardware architecture can be defined in a Hardware Description Language (like VHDL), simulated and synthesized into digital structures that can be programmed into the FPGA and tested on the camera. The architecture of a classical multi-scale edge detection algorithm based on a Laplacian of Gaussian convolution has been developed to show the capabilities of the system.

  7. Completely random measures for modelling block-structured sparse networks

    DEFF Research Database (Denmark)

    Herlau, Tue; Schmidt, Mikkel Nørgaard; Mørup, Morten

    2016-01-01

    Many statistical methods for network data parameterize the edge-probability by attributing latent traits to the vertices such as block structure and assume exchangeability in the sense of the Aldous-Hoover representation theorem. Empirical studies of networks indicate that many real-world networks...... have a power-law distribution of the vertices which in turn implies the number of edges scale slower than quadratically in the number of vertices. These assumptions are fundamentally irreconcilable as the Aldous-Hoover theorem implies quadratic scaling of the number of edges. Recently Caron and Fox...

  8. Structure, rheology and shear alignment of Pluronic block copolymer mixtures.

    Science.gov (United States)

    Newby, Gemma E; Hamley, Ian W; King, Stephen M; Martin, Christopher M; Terrill, Nicholas J

    2009-01-01

    The structure and flow behaviour of binary mixtures of Pluronic block copolymers P85 and P123 is investigated by small-angle scattering, rheometry and mobility tests. Micelle dimensions are probed by dynamic light scattering. The micelle hydrodynamic radius for the 50/50 mixture is larger than that for either P85 or P123 alone, due to the formation of mixed micelles with a higher association number. The phase diagram for 50/50 mixtures contains regions of cubic and hexagonal phases similar to those for the parent homopolymers, however the region of stability of the cubic phase is enhanced at low temperature and concentrations above 40 wt%. This is ascribed to favourable packing of the mixed micelles containing core blocks with two different chain lengths, but similar corona chain lengths. The shear flow alignment of face-centred cubic and hexagonal phases is probed by in situ small-angle X-ray or neutron scattering with simultaneous rheology. The hexagonal phase can be aligned using steady shear in a Couette geometry, however the high modulus cubic phase cannot be aligned well in this way. This requires the application of oscillatory shear or compression.

  9. FPGA Vision Data Architecture

    Science.gov (United States)

    Morfopoulos, Arin C.; Pham, Thang D.

    2013-01-01

    JPL has produced a series of FPGA (field programmable gate array) vision algorithms that were written with custom interfaces to get data in and out of each vision module. Each module has unique requirements on the data interface, and further vision modules are continually being developed, each with their own custom interfaces. Each memory module had also been designed for direct access to memory or to another memory module.

  10. Commercial FPGA based multipurpose controller: implementation perspective

    International Nuclear Information System (INIS)

    Arredondo, I.; Campo, M. del; Echevarria, P.; Belver, D.; Muguira, L.; Garmendia, N.; Hassanzadegan, H.; Eguiraun, M.; Jugo, J.; Etxebarria, V.

    2012-01-01

    This work presents a fast acquisition multipurpose controller, focussing on its EPICS integration and on its XML based configuration. This controller is based on a Lyrtech VHS-ADC board which encloses an FPGA, connected to a Host PC. This Host acts as local controller and implements an IOC integrating the device in an EPICS network. These tasks have been performed using Java as the main tool to program the PC to make the device fit the desired application. All the process includes the use of different technologies: JNA to handle C functions i.e. FPGA API, JavaIOC to integrate EPICS and XML w3c DOM classes to easily configure the particular application. In order to manage the functions, Java specific tools have been developed: Methods to manage the FPGA (read/write registers, acquire data,...), methods to create and use the EPICS server (put, get, monitor,...), mathematical methods to process the data (numeric format conversions,...) and methods to create/ initialize the application structure by means of an XML file (parse elements, build the DOM and the specific application structure). This XML file has some common nodes and tags for all the applications: FPGA registers specifications definition and EPICS variables. This means that the user only has to include a node for the specific application and use the mentioned tools. A main class is in charge of managing the FPGA and EPICS server according to this XML file. This multipurpose controller has been successfully used to implement a BPM and an LLRF application for the ESS-Bilbao (European Spallation Source) facility. (authors)

  11. FPGA programming using FX3

    CERN Document Server

    Calleja, Stefano

    2014-01-01

    An FPGA is required to be programmed via USB3 cable. Connectivity to the host PC is achieved by using an FX3 chip. By changing the firmware of the FX3, one can alter the function of the FX3. To program the FPGA via USB3, the FX3 must act as a connector from the host to the FPGA. This type of connection is known as an FPGA link. This method of connection is required to avoid programming the FPGA and FX3 dedicated memories and thus not having to use different programming methods and cables to program the board. It is considered that the FX3 is suitable to be used as an FPGA link since its previous version, the FX2, was also used as an FPGA link in a similar project. Firmware was downloaded on the FX3 using libusb and fx3load files from a Linux terminal. Some testing firmware was verified to perform as intended. However, the connection firmware intended to make the FPGA link truly functional has not been successful so far. Yet, through the FX3 documentation, it can be noted that an FPGA link is possible. UrJTAG ...

  12. Realise of PWM-generating based on FPGA

    International Nuclear Information System (INIS)

    Su Rongfeng; Xu Ruinian; Huang Maomao

    2012-01-01

    The power supply digital controllers of Shanghai Synchrotron Radiation Facility(SSRF) make use of the PWM (pulse width modulation) wave as the feedback to the power-electrical devices, so as to obtain constant current of high accuracy and stability. The design of PWM wave generation structure in FPGA is good for a compact controller,and the reduction of the usage of Integrated Circuits (ICs) decreases the interference from the noise among the ICs, hence better performance of the controller. In addition, FPGA can be programmed circularly at any time,so as to optimize the structure design and make a maximum use of the advantage of FPGA. As a part of transplanting the complete function of the DSP (digital signal processor/processing), realizing the generation of PWM wave in FPGA is feasible. In this paper, we report progress in this regard at SSRF. (authors)

  13. A PMSM current controller system on FPGA platform | Ahmadian ...

    African Journals Online (AJOL)

    Journal of Fundamental and Applied Sciences ... Proposed system architecture and computational blocks are described and system level and RTL simulation results are presented. Simulation results show that the total computation cycle time of implemented system on Altera Cyclone II FPGA is 456ns. Keywords: PMSM ...

  14. FPGA Implementation of Heart Rate Monitoring System.

    Science.gov (United States)

    Panigrahy, D; Rakshit, M; Sahu, P K

    2016-03-01

    This paper describes a field programmable gate array (FPGA) implementation of a system that calculates the heart rate from Electrocardiogram (ECG) signal. After heart rate calculation, tachycardia, bradycardia or normal heart rate can easily be detected. ECG is a diagnosis tool routinely used to access the electrical activities and muscular function of the heart. Heart rate is calculated by detecting the R peaks from the ECG signal. To provide a portable and the continuous heart rate monitoring system for patients using ECG, needs a dedicated hardware. FPGA provides easy testability, allows faster implementation and verification option for implementing a new design. We have proposed a five-stage based methodology by using basic VHDL blocks like addition, multiplication and data conversion (real to the fixed point and vice-versa). Our proposed heart rate calculation (R-peak detection) method has been validated, using 48 first channel ECG records of the MIT-BIH arrhythmia database. It shows an accuracy of 99.84%, the sensitivity of 99.94% and the positive predictive value of 99.89%. Our proposed method outperforms other well-known methods in case of pathological ECG signals and successfully implemented in FPGA.

  15. Parallel Block Structured Adaptive Mesh Refinement on Graphics Processing Units

    Energy Technology Data Exchange (ETDEWEB)

    Beckingsale, D. A. [Atomic Weapons Establishment (AWE), Aldermaston (United Kingdom); Gaudin, W. P. [Atomic Weapons Establishment (AWE), Aldermaston (United Kingdom); Hornung, R. D. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Gunney, B. T. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Gamblin, T. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Herdman, J. A. [Atomic Weapons Establishment (AWE), Aldermaston (United Kingdom); Jarvis, S. A. [Atomic Weapons Establishment (AWE), Aldermaston (United Kingdom)

    2014-11-17

    Block-structured adaptive mesh refinement is a technique that can be used when solving partial differential equations to reduce the number of zones necessary to achieve the required accuracy in areas of interest. These areas (shock fronts, material interfaces, etc.) are recursively covered with finer mesh patches that are grouped into a hierarchy of refinement levels. Despite the potential for large savings in computational requirements and memory usage without a corresponding reduction in accuracy, AMR adds overhead in managing the mesh hierarchy, adding complex communication and data movement requirements to a simulation. In this paper, we describe the design and implementation of a native GPU-based AMR library, including: the classes used to manage data on a mesh patch, the routines used for transferring data between GPUs on different nodes, and the data-parallel operators developed to coarsen and refine mesh data. We validate the performance and accuracy of our implementation using three test problems and two architectures: an eight-node cluster, and over four thousand nodes of Oak Ridge National Laboratory’s Titan supercomputer. Our GPU-based AMR hydrodynamics code performs up to 4.87× faster than the CPU-based implementation, and has been scaled to over four thousand GPUs using a combination of MPI and CUDA.

  16. A novel partitioning method for block-structured adaptive meshes

    Science.gov (United States)

    Fu, Lin; Litvinov, Sergej; Hu, Xiangyu Y.; Adams, Nikolaus A.

    2017-07-01

    We propose a novel partitioning method for block-structured adaptive meshes utilizing the meshless Lagrangian particle concept. With the observation that an optimum partitioning has high analogy to the relaxation of a multi-phase fluid to steady state, physically motivated model equations are developed to characterize the background mesh topology and are solved by multi-phase smoothed-particle hydrodynamics. In contrast to well established partitioning approaches, all optimization objectives are implicitly incorporated and achieved during the particle relaxation to stationary state. Distinct partitioning sub-domains are represented by colored particles and separated by a sharp interface with a surface tension model. In order to obtain the particle relaxation, special viscous and skin friction models, coupled with a tailored time integration algorithm are proposed. Numerical experiments show that the present method has several important properties: generation of approximately equal-sized partitions without dependence on the mesh-element type, optimized interface communication between distinct partitioning sub-domains, continuous domain decomposition which is physically localized and implicitly incremental. Therefore it is particularly suitable for load-balancing of high-performance CFD simulations.

  17. A novel partitioning method for block-structured adaptive meshes

    Energy Technology Data Exchange (ETDEWEB)

    Fu, Lin, E-mail: lin.fu@tum.de; Litvinov, Sergej, E-mail: sergej.litvinov@aer.mw.tum.de; Hu, Xiangyu Y., E-mail: xiangyu.hu@tum.de; Adams, Nikolaus A., E-mail: nikolaus.adams@tum.de

    2017-07-15

    We propose a novel partitioning method for block-structured adaptive meshes utilizing the meshless Lagrangian particle concept. With the observation that an optimum partitioning has high analogy to the relaxation of a multi-phase fluid to steady state, physically motivated model equations are developed to characterize the background mesh topology and are solved by multi-phase smoothed-particle hydrodynamics. In contrast to well established partitioning approaches, all optimization objectives are implicitly incorporated and achieved during the particle relaxation to stationary state. Distinct partitioning sub-domains are represented by colored particles and separated by a sharp interface with a surface tension model. In order to obtain the particle relaxation, special viscous and skin friction models, coupled with a tailored time integration algorithm are proposed. Numerical experiments show that the present method has several important properties: generation of approximately equal-sized partitions without dependence on the mesh-element type, optimized interface communication between distinct partitioning sub-domains, continuous domain decomposition which is physically localized and implicitly incremental. Therefore it is particularly suitable for load-balancing of high-performance CFD simulations.

  18. Printable and Rewritable Full Block Copolymer Structural Color.

    Science.gov (United States)

    Kang, Han Sol; Lee, Jinseong; Cho, Suk Man; Park, Tae Hyun; Kim, Min Ju; Park, Chanho; Lee, Seung Won; Kim, Kang Lib; Ryu, Du Yeol; Huh, June; Thomas, Edwin L; Park, Cheolmin

    2017-08-01

    Structural colors (SCs) of photonic crystals (PCs) arise from selective constructive interference of incident light. Here, an ink-jet printable and rewritable block copolymer (BCP) SC display is demonstrated, which can be quickly written and erased over 50 times with resolution nearly equivalent to that obtained with a commercial office ink-jet printer. Moreover, the writing process employs an easily modified printer for position- and concentration-controlled deposition of a single, colorless, water-based ink containing a reversible crosslinking agent, ammonium persulfate. Deposition of the ink onto a self-assembled BCP PC film comprising a 1D stack of alternating layers enables differential swelling of the written BCP film and produces a full-colored SC display of characters and images. Furthermore, the information can be readily erased and the system can be reset by application of hydrogen bromide. Subsequently, new information can be rewritten, resulting in a chemically rewritable BCP SC display. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  19. Adaptive Hardware Cryptography Engine Based on FPGA

    International Nuclear Information System (INIS)

    Afify, M.A.A.

    2011-01-01

    In the last two decades, with spread of the real time applications over public networks or communications the need for information security become more important but with very high speed for data processing, to keep up with the real time applications requirements, that is the reason for using FPGA as an implementation platform for the proposed cryptography engine. Hence in this thesis a new S-Box design has been demonstrated and implemented, there is a comparison for the simulation results for proposed S-Box simulation results with respect to different designs for S-Box in DES, Two fish and Rijndael algorithms and another comparison among proposed S-Box with different sizes. The proposed S-Box implemented with 32-bits Input data lines and compared with different designs in the encryption algorithms with the same input lines, the proposed S-Box gives implementation results for the maximum frequency 120 MHz but the DES S-Box gives 34 MHz and Rijndael gives 71 MHz, on the other hand the proposed design gives the best implementation area, hence it gives 50 Configurable logic Block CLB but DES gives 88 CLB. The proposed S-Box implemented in different sizes 64-bits, 128-bits, and 256-bits for input data lines. The implementation carried out by using UniDAq PCI card with FPGA Chip XCV 800, synthesizing carried out for all designs by using Leonardo spectrum and simulation carried out by using model sim simulator program form the FPGA advantage package. Finally the results evaluation and verifications carried out using the UniDAq FPGA PCI card with chip XCV 800. Different cases study have been implemented, data encryption, images encryption, voice encryption, and video encryption. A prototype for Remote Monitoring Control System has been implemented. Finally the proposed design for S-Box has a significant achievement in maximum frequency, implementation area, and encryption strength.

  20. Logic synthesis for FPGA-based finite state machines

    CERN Document Server

    Barkalov, Alexander; Kolopienczyk, Malgorzata; Mielcarek, Kamil; Bazydlo, Grzegorz

    2016-01-01

    This book discusses control units represented by the model of a finite state machine (FSM). It contains various original methods and takes into account the peculiarities of field-programmable gate arrays (FPGA) chips and a FSM model. It shows that one of the peculiarities of FPGA chips is the existence of embedded memory blocks (EMB). The book is devoted to the solution of problems of logic synthesis and reduction of hardware amount in control units. The book will be interesting and useful for researchers and PhD students in the area of Electrical Engineering and Computer Science, as well as for designers of modern digital systems.

  1. An FPGA-based reconfigurable DDC algorithm

    Science.gov (United States)

    Juszczyk, B.; Kasprowicz, G.

    2016-09-01

    This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fulfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.

  2. The FPGA Pixel Array Detector

    International Nuclear Information System (INIS)

    Hromalik, Marianne S.; Green, Katherine S.; Philipp, Hugh T.; Tate, Mark W.; Gruner, Sol M.

    2013-01-01

    A proposed design for a reconfigurable x-ray Pixel Array Detector (PAD) is described. It operates by integrating a high-end commercial field programmable gate array (FPGA) into a 3-layer device along with a high-resistivity diode detection layer and a custom, application-specific integrated circuit (ASIC) layer. The ASIC layer contains an energy-discriminating photon-counting front end with photon hits streamed directly to the FPGA via a massively parallel, high-speed data connection. FPGA resources can be allocated to perform user defined tasks on the pixel data streams, including the implementation of a direct time autocorrelation function (ACF) with time resolution down to 100 ns. Using the FPGA at the front end to calculate the ACF reduces the required data transfer rate by several orders of magnitude when compared to a fast framing detector. The FPGA-ASIC high-speed interface, as well as the in-FPGA implementation of a real-time ACF for x-ray photon correlation spectroscopy experiments has been designed and simulated. A 16×16 pixel prototype of the ASIC has been fabricated and is being tested. -- Highlights: ► We describe the novelty and need for the FPGA Pixel Array Detector. ► We describe the specifications and design of the Diode, ASIC and FPGA layers. ► We highlight the Autocorrelation Function (ACF) for speckle as an example application. ► Simulated FPGA output calculates the ACF for different input bitstreams to 100 ns. ► Reduced data transfer rate by 640× and sped up real-time ACF by 100× other methods.

  3. Flexible experimental FPGA based platform

    DEFF Research Database (Denmark)

    Andersen, Karsten Holm; Nymand, Morten

    2016-01-01

    This paper presents an experimental flexible Field Programmable Gate Array (FPGA) based platform for testing and verifying digital controlled dc-dc converters. The platform supports different types of control strategies, dc-dc converter topologies and switching frequencies. The controller platform...... interface supporting configuration and reading of setup parameters, controller status and the acquisition memory in a simple way. The FPGA based platform, provides an easy way within education or research to use different digital control strategies and different converter topologies controlled by an FPGA...

  4. Assessment of Structural Strength of Commercial Sandcrete Blocks ...

    African Journals Online (AJOL)

    makorede

    cement to 6 or 8 parts of sand (1:6 or 1:8) with a water/cement ratio of between 50 and .... FACTORS AFFECTING QUALITY OF SANDCRETE. BLOCKS. Compressive ... that it is a cohesionless aggregate of rounded angular or sub angular ...

  5. FPGA-Based Sonar Processing

    National Research Council Canada - National Science Library

    Graham, Paul; Nelson, Brent

    1998-01-01

    This paper presents the application of time-delay sonar beamforming and discusses a multi-board FPGA system for performing several variations of this beamforming method in real-time for realistic sonar arrays...

  6. Exploration of Heterogeneous FPGA Architectures

    Directory of Open Access Journals (Sweden)

    Umer Farooq

    2011-01-01

    mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.

  7. Architecture exploration of FPGA based accelerators for bioinformatics applications

    CERN Document Server

    Varma, B Sharat Chandra; Balakrishnan, M

    2016-01-01

    This book presents an evaluation methodology to design future FPGA fabrics incorporating hard embedded blocks (HEBs) to accelerate applications. This methodology will be useful for selection of blocks to be embedded into the fabric and for evaluating the performance gain that can be achieved by such an embedding. The authors illustrate the use of their methodology by studying the impact of HEBs on two important bioinformatics applications: protein docking and genome assembly. The book also explains how the respective HEBs are designed and how hardware implementation of the application is done using these HEBs. It shows that significant speedups can be achieved over pure software implementations by using such FPGA-based accelerators. The methodology presented in this book may also be used for designing HEBs for accelerating software implementations in other domains besides bioinformatics. This book will prove useful to students, researchers, and practicing engineers alike.

  8. Verification of BGA type FPGA logic applied to a control equipment with Safety Class using the special socket

    International Nuclear Information System (INIS)

    Chung, YounHu; Yoo, Kwanwoo; Lee, Myeongkyun; Yun, Donghwa

    2015-01-01

    This article aims to provide the verification method for BGA-type FPGA of Programmable Logic Controller (PLC) developed as Safety Class. The logic of FPGA in the control device with Safety Class is the circuit to control overall logic of PLC. This device converts to the different module from the input signals for both digital and analogue of the equipment in the field and outputs their data. In addition, it should perform the logical controls such as backplane communication control and data communication. We suggest acquiring method of the data signal with efficient logic using the socket in this article. Proposed test socket is made by simpler process than former one, and the process is done in batches by which cost can be reduces, and the test socket can be quickly produced in response to any request. Also, it is possible to reduce the wear by reducing the contact force of the ball phenomenon. The structure on the basis of silicon can be reduced the modification, and it has excellent linearity. At the logic verification, the operation that state data block is designed in the FPGA could be easily confirmed by using a socket

  9. FPGA based, modular, configurable controller with fast synchronous optical network

    Energy Technology Data Exchange (ETDEWEB)

    Graczyk, R.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland). Inst. of Electronic Systems

    2006-07-01

    The paper describes a configurable controller equipped with programmable VLSI FPGA circuit, universal expansion modules PMC, synchronous, optical, multi-gigabit links, commonly used industrial and computer communication interfaces, Ethernet 100TB, system of automatic initialization ACE etc. There are characterized the basic functional characteristics of the device. The possibilities of its usage in various work modes were presented. Realization of particular blocks of the device were discussed. Resulting, during the realization of this project, new hardware layer solutions were also characterized. (orig.)

  10. FPGA based, modular, configurable controller with fast synchronous optical network

    International Nuclear Information System (INIS)

    Graczyk, R.; Pozniak, K.T.; Romaniuk, R.S.

    2006-01-01

    The paper describes a configurable controller equipped with programmable VLSI FPGA circuit, universal expansion modules PMC, synchronous, optical, multi-gigabit links, commonly used industrial and computer communication interfaces, Ethernet 100TB, system of automatic initialization ACE etc. There are characterized the basic functional characteristics of the device. The possibilities of its usage in various work modes were presented. Realization of particular blocks of the device were discussed. Resulting, during the realization of this project, new hardware layer solutions were also characterized. (orig.)

  11. FPGA design best practices for team-based reuse

    CERN Document Server

    Simpson, Philip Andrew

    2015-01-01

    This book describes best practices for successful FPGA design. It is the result of the author’s meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book’s content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design teams by establishing a common methodology across design teams; enabling the exchange of design blocks across teams. Coverage includes the complete FPGA design flow, from the basics to advanced techniques.  This new edition has been enhanced to include new sections on System modeling, embedded design and high level design. The original sections on Design Environment, RTL design and timing closure have all been expand...

  12. Two-dimensional phase separated structures of block copolymers on solids

    Science.gov (United States)

    Sen, Mani; Jiang, Naisheng; Endoh, Maya; Koga, Tadanori; Ribbe, Alexander

    The fundamental, yet unsolved question in block copolymer (BCP) thin films is the self-organization process of BCPs at the solid-polymer melt interface. We here focus on the self-organization processes of cylinder-forming polystyrene-block-poly (4-vinylpyridine) diblock copolymer and lamellar-forming poly (styrene-block-butadiene-block-styrene) triblock copolymer on Si substrates as model systems. In order to reveal the buried interfacial structures, the following experimental protocols were utilized: the BCP monolayer films were annealed under vacuum at T>Tg of the blocks (to equilibrate the melts); vitrification of the annealed BCP films via rapid quench to room temperature; subsequent intensive solvent leaching (to remove unadsorbed chains) with chloroform, a non-selective good solvent for the blocks. The strongly bound BCP layers were then characterized by using atomic force microscopy, scanning electron microscopy, grazing incidence small angle X-ray scattering, and X-ray reflectivity. The results showed that both blocks lie flat on the substrate, forming the two-dimensional, randomly phase-separated structure irrespective of their microdomain structures and interfacial energetics. Acknowledgement of financial support from NSF Grant (CMMI -1332499).

  13. FPGA fabric specific optimization for RLT design

    International Nuclear Information System (INIS)

    Perwaiz, A.; Khan, S.A.

    2010-01-01

    This paper proposes a technique custom to the optimization requirements suited for a particular family of Field Programmable Gate Arrays (FPGAs). As FPGAs have introduced re configurable black boxes there is a need to perform optimization across FPGAs slice fabric in order to achieve optimum performance. Though the Register Transfer Level (RTL) Hardware Descriptive Language (HDL) code should be technology independent but in many design instances it is imperative to understand the target technology especially once the target device embeds dedicated arithmetic blocks. No matter what the degree of optimization of the algorithm is, the configuration of target device plays an important role as far as the device utilization and path delays are concerned Index Terms: Field Programmable Gate Arrays (FPGA), Compression Tree, Bit Width Reduction, Look Ahead Pipelining. (author)

  14. FPGA Design and Implementation of a Rangefinder

    Directory of Open Access Journals (Sweden)

    ALBU Răzvan-Daniel

    2017-10-01

    Full Text Available In this paper we will present the design and implementation of an ultrasonic non-contact rangefinder with FPGA. This rangefinder can be used in numerous applications, ranging from hardly accessible spaces to electromagnetically polluted environments. The experimental implementations proved to be accurate, portable, and easy to operate. Attributable to their programmable nature, FPGAs are an ideal fit for many dissimilar markets. Even though FPGAs used to be designated for lower speed and complexity designs in the past, today’s FPGAs effortlessly push the 500 MHz performance barricade. Since they bring features, such as embedded processors, DSP blocks, clocking, and high-speed serial at lower prices, FPGAs are a convincing alternative for almost any type of design.

  15. The integration of FPGA TDC inside White Rabbit node

    International Nuclear Information System (INIS)

    Li, H.; Xue, T.; Gong, G.; Li, J.

    2017-01-01

    White Rabbit technology is capable of delivering sub-nanosecond accuracy and picosecond precision of synchronization and normal data packets over the fiber network. Carry chain structure in FPGA is a popular way to build TDC and tens of picosecond RMS resolution has been achieved. The integration of WR technology with FPGA TDC can enhance and simplify the TDC in many aspects that includes providing a low jitter clock for TDC, a synchronized absolute UTC/TAI timestamp for coarse counter, a fancy way to calibrate the carry chain DNL and an easy to use Ethernet link for data and control information transmit. This paper presents a FPGA TDC implemented inside a normal White Rabbit node with sub-nanosecond measurement precision. The measured standard deviation reaches 50ps between two distributed TDCs. Possible applications of this distributed TDC are also discussed.

  16. The integration of FPGA TDC inside White Rabbit node

    Science.gov (United States)

    Li, H.; Xue, T.; Gong, G.; Li, J.

    2017-04-01

    White Rabbit technology is capable of delivering sub-nanosecond accuracy and picosecond precision of synchronization and normal data packets over the fiber network. Carry chain structure in FPGA is a popular way to build TDC and tens of picosecond RMS resolution has been achieved. The integration of WR technology with FPGA TDC can enhance and simplify the TDC in many aspects that includes providing a low jitter clock for TDC, a synchronized absolute UTC/TAI timestamp for coarse counter, a fancy way to calibrate the carry chain DNL and an easy to use Ethernet link for data and control information transmit. This paper presents a FPGA TDC implemented inside a normal White Rabbit node with sub-nanosecond measurement precision. The measured standard deviation reaches 50ps between two distributed TDCs. Possible applications of this distributed TDC are also discussed.

  17. An FPGA-based heterogeneous image fusion system design method

    Science.gov (United States)

    Song, Le; Lin, Yu-chi; Chen, Yan-hua; Zhao, Mei-rong

    2011-08-01

    Taking the advantages of FPGA's low cost and compact structure, an FPGA-based heterogeneous image fusion platform is established in this study. Altera's Cyclone IV series FPGA is adopted as the core processor of the platform, and the visible light CCD camera and infrared thermal imager are used as the image-capturing device in order to obtain dualchannel heterogeneous video images. Tailor-made image fusion algorithms such as gray-scale weighted averaging, maximum selection and minimum selection methods are analyzed and compared. VHDL language and the synchronous design method are utilized to perform a reliable RTL-level description. Altera's Quartus II 9.0 software is applied to simulate and implement the algorithm modules. The contrast experiments of various fusion algorithms show that, preferably image quality of the heterogeneous image fusion can be obtained on top of the proposed system. The applied range of the different fusion algorithms is also discussed.

  18. A block structure Laplacian for hyperspectral image data clustering

    CSIR Research Space (South Africa)

    Lunga, D

    2013-12-01

    Full Text Available and points to new directions that boost unsupervised pattern classification. In particular, the paper offers design insights on the generation of a well structured graph Laplacian based on an affinity function that induces context-dependence to create compact...

  19. Development of an FPGA-based controller for safety critical application

    International Nuclear Information System (INIS)

    Xing, A.; De Grosbois, J.; Sklyar, V.; Archer, P.; Awwal, A.

    2011-01-01

    In implementing safety functions, Field Programmable Gate Arrays (FPGA) technology offers a distinct combination of benefits and advantages over microprocessor-based systems. FPGAs can be designed such that the final product is purely hardware, without any overhead runtime software, bringing the design closer to a conventional hardware-based solution. On the other hand, FPGAs can implement more complex safety logic that would generally require microprocessor-based safety systems. There are now qualified FPGA-based platforms available on the market with a credible use history in safety applications in nuclear power plants. Atomic Energy of Canada (AECL), in collaboration with RPC Radiy, has initiated a development program to define a vigorous FPGA engineering process suitable for implementing safety critical functions at the application development level. This paper provides an update on the FPGA development program along with the proposed design model using function block diagrams for the development of safety controllers in CANDU applications. (author)

  20. Block-structured Adaptive Mesh Refinement - Theory, Implementation and Application

    Directory of Open Access Journals (Sweden)

    Deiterding Ralf

    2011-12-01

    Full Text Available Structured adaptive mesh refinement (SAMR techniques can enable cutting-edge simulations of problems governed by conservation laws. Focusing on the strictly hyperbolic case, these notes explain all algorithmic and mathematical details of a technically relevant implementation tailored for distributed memory computers. An overview of the background of commonly used finite volume discretizations for gas dynamics is included and typical benchmarks to quantify accuracy and performance of the dynamically adaptive code are discussed. Large-scale simulations of shock-induced realistic combustion in non-Cartesian geometry and shock-driven fluid-structure interaction with fully coupled dynamic boundary motion demonstrate the applicability of the discussed techniques for complex scenarios.

  1. Studies on microphase-separated structures of block copolymers by neutron reflectivity measurement

    International Nuclear Information System (INIS)

    Torikai, Naoya; Noda, Ichiro; Matsushita, Yushu; Karim, A.; Satija, S.K.; Han, C.C.; Ebisawa, Toru.

    1996-01-01

    Segmental distributions of block copolymer chains in lamellar microphase-separated structure and those of homopolymers in block copolymer/homopolymer blends also with lamellar structures were studied by neutron reflectivity measurements. It was revealed that polystyrene and poly(2-vinylpyridine) lamellae were alternately stacked within the thin films of pure block copolymers spin-coated on silicon wafers, and they were preferentially oriented along the direction parallel to film surface. Polystyrene lamella appeared at air surfaces of the films, while poly(2-vinylpyridine) lamella did on silicon surfaces. Segment distribution at lamellar interface was well described by an error function, and the width of the lamellar interface, defined by a full-width half-maximum value of interfacial profile, was estimated to be about 4.5 nm. Segments of block chains adjacent to the chemical junction points connecting different block chains were strongly localized near the lamellar interfaces, while those on the free ends of block chains were distributed all over the lamellar microdomains with their distribution maxima at the centers of lamellae. On the other hand, it was clarified that homopolymers dissolved in the corresponding lamellar microdomains of block copolymers were also distributed throughout the microdomains with their concentration maxima at the centers of the lamellae. (author)

  2. The Organization of Nanoporous Structure Using Controlled Micelle Size from MPEG-b-PDLLA Block Copolymers

    International Nuclear Information System (INIS)

    Chang, Jeong Ho; Kim, Kyung Ja; Shin, Young Kook

    2004-01-01

    Selected MPEG-b-PDLLA block copolymers have been synthesized by ring-opening polymerization with systematic variation of the chain lengths of the resident hydrophilic and hydrophobic blocks. The size and shape of the micelles that spontaneously form in solution are then controlled by the characteristics of the block copolymer template. All the materials prepared in this study showed the tunable pore size of 20-80 A with the increase of hydrophobic chain lengths and up to 660 m 2 /g of specific surface area. The formation mechanism of these nanoporous structures obtained by controlling the micelle size has been confirmed using both liquid and solid state 13 C and 29 Si NMR techniques. This work verifies the formation mechanism of nanoporous structures in which the pore size and wall thickness are closely dependent on the size of hydrophobic cores and hydrophilic shells of the block copolymer templates

  3. Association and Structure of Thermo Sensitive Comblike Block Copolymers in Aqueous Solutions

    International Nuclear Information System (INIS)

    Cheng, Gang

    2008-01-01

    The structures and association properties of thermo sensitive poly(methoxyoligo(ethylene glycol) norbornenyl esters) block copolymers in D2O were investigated by Small Angle Neutron Scattering (SANS). Each block is a comb-like polymer with a polynorbornene (PNB) backbone and oligo ethylene glycol (OEG) side chains (one side chain per NB monomer). The chemical formula of the block copolymer is (OEG3NB)79-(OEG6.6NB)67, where subscripts represent the degree of polymerization (DP) of OEG and NB in each block The polymer concentration was fixed at 2.0 wt % and the structural changes were investigated over a temperature range between 25 C and 68 C. It was found that at room temperature polymers associate to form micelles with a spherical core formed by the block (OEG3NB)79 and corona formed by the block (OEG6.6NB)67 and that the shape of the polymer in the corona could be described by the form factor of rigid cylinders. At elevated temperatures, the aggregation number increases and the micelles become more compact. At temperatures round the cloud point temperature (CPT) T = 60 C a correlation peak started to appear and became pronounced at 68 C due to the formation of a partially ordered structure with a correlation length ∼ 349

  4. QuaBingo: A Prediction System for Protein Quaternary Structure Attributes Using Block Composition

    Directory of Open Access Journals (Sweden)

    Chi-Hua Tung

    2016-01-01

    Full Text Available Background. Quaternary structures of proteins are closely relevant to gene regulation, signal transduction, and many other biological functions of proteins. In the current study, a new method based on protein-conserved motif composition in block format for feature extraction is proposed, which is termed block composition. Results. The protein quaternary assembly states prediction system which combines blocks with functional domain composition, called QuaBingo, is constructed by three layers of classifiers that can categorize quaternary structural attributes of monomer, homooligomer, and heterooligomer. The building of the first layer classifier uses support vector machines (SVM based on blocks and functional domains of proteins, and the second layer SVM was utilized to process the outputs of the first layer. Finally, the result is determined by the Random Forest of the third layer. We compared the effectiveness of the combination of block composition, functional domain composition, and pseudoamino acid composition of the model. In the 11 kinds of functional protein families, QuaBingo is 23% of Matthews Correlation Coefficient (MCC higher than the existing prediction system. The results also revealed the biological characterization of the top five block compositions. Conclusions. QuaBingo provides better predictive ability for predicting the quaternary structural attributes of proteins.

  5. Contributions to Estimation and Testing Block Covariance Structures in Multivariate Normal Models

    OpenAIRE

    Liang, Yuli

    2015-01-01

    This thesis concerns inference problems in balanced random effects models with a so-called block circular Toeplitz covariance structure. This class of covariance structures describes the dependency of some specific multivariate two-level data when both compound symmetry and circular symmetry appear simultaneously. We derive two covariance structures under two different invariance restrictions. The obtained covariance structures reflect both circularity and exchangeability present in the data....

  6. FPGA based fast synchronous serial multi-wire links synchronization

    Science.gov (United States)

    Pozniak, Krzysztof T.

    2013-10-01

    The paper debates synchronization method of multi-wire, serial link of constant latency, by means of pseudo-random numbers generators. The solution was designed for various families of FPGA circuits. There were debated synchronization algorithm and functional structure of parameterized transmitter and receiver modules. The modules were realized in VHDL language in a behavioral form.

  7. FPGA-based implementation of sorting networks in MMC applications

    DEFF Research Database (Denmark)

    Ricco, Mattia; Máthé, Lászlo; Teodorescu, Remus

    2016-01-01

    , and they are usually implemented in microcontrollers or DSPs. However, they are not convenient for hardware implementation due to their inherent sequential operation. Instead, the proposed SNs, are suitable for FPGA devices thanks to their fixed parallel structure that allows improving the timing performance...

  8. Asymmetric block copolymer membranes with ultrahigh porosity and hierarchical pore structure by plain solvent evaporation

    KAUST Repository

    Yu, H.

    2016-09-14

    Membranes with a hierarchical porous structure could be manufactured from a block copolymer blend by pure solvent evaporation. Uniform pores in a 30 nm thin skin layer supported by a macroporous structure were formed. This new process is attractive for membrane production because of its simplicity and the lack of liquid waste.

  9. Asymmetric block copolymer membranes with ultrahigh porosity and hierarchical pore structure by plain solvent evaporation

    KAUST Repository

    Yu, H.; Qiu, Xiaoyan; Behzad, Ali Reza; Musteata, Valentina-Elena; Smilgies, D.-M.; Nunes, Suzana Pereira; Peinemann, Klaus-Viktor

    2016-01-01

    Membranes with a hierarchical porous structure could be manufactured from a block copolymer blend by pure solvent evaporation. Uniform pores in a 30 nm thin skin layer supported by a macroporous structure were formed. This new process is attractive for membrane production because of its simplicity and the lack of liquid waste.

  10. SEU mitigation exploratory tests in a ITER related FPGA

    International Nuclear Information System (INIS)

    Batista, Antonio J.N.; Leong, Carlos; Santos, Bruno; Fernandes, Ana; Ramos, Ana Rita; Santos, Joana P.; Marques, José G.; Teixeira, Isabel C.; Teixeira, João P.; Sousa, Jorge; Gonçalves, Bruno

    2017-01-01

    Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-errors caused by neutrons radiation in ITER related FPGAs. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of Instrumentation & Control (I & C) products – Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), the functional data is stored in dedicated Block RAM (BRAM) and the functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons cause soft errors, unintended changes (bit-flips) of the logic values stored in the state elements of the FPGA. Real-time SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA Configuration Memory (CM). BRAM based SEU sensors with Error Correction Code (ECC) detect and repair the respective BRAM contents. Real-time mitigation of SEU can increase reliability and availability of data acquisition hardware for nuclear applications. The results of the tests performed using the SEM controller and the SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor, operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU soft-errors in the FPGA memory.

  11. SEU mitigation exploratory tests in a ITER related FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Batista, Antonio J.N., E-mail: toquim@ipfn.tecnico.ulisboa.pt [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Leong, Carlos [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Santos, Bruno; Fernandes, Ana [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Ramos, Ana Rita; Santos, Joana P.; Marques, José G. [Centro de Ciências e Tecnologias Nucleares (C2TN), Instituto Superior Técnico (IST), Universidade de Lisboa - UL, 2695-066 Bobadela (Portugal); Teixeira, Isabel C.; Teixeira, João P. [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Sousa, Jorge; Gonçalves, Bruno [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal)

    2017-05-15

    Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-errors caused by neutrons radiation in ITER related FPGAs. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of Instrumentation & Control (I & C) products – Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), the functional data is stored in dedicated Block RAM (BRAM) and the functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons cause soft errors, unintended changes (bit-flips) of the logic values stored in the state elements of the FPGA. Real-time SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA Configuration Memory (CM). BRAM based SEU sensors with Error Correction Code (ECC) detect and repair the respective BRAM contents. Real-time mitigation of SEU can increase reliability and availability of data acquisition hardware for nuclear applications. The results of the tests performed using the SEM controller and the SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor, operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU soft-errors in the FPGA memory.

  12. Structure and ionic conductivity of block copolymer electrolytes over a wide salt concentration range

    Science.gov (United States)

    Chintapalli, Mahati; Le, Thao; Venkatesan, Naveen; Thelen, Jacob; Rojas, Adriana; Balsara, Nitash

    Block copolymer electrolytes are promising materials for safe, long-lasting lithium batteries because of their favorable mechanical and ion transport properties. The morphology, phase behavior, and ionic conductivity of a block copolymer electrolyte, SEO mixed with LiTFSI was studied over a wide, previously unexplored salt concentration range using small angle X-ray scattering, differential scanning calorimetry and ac impedance spectroscopy, respectively. SEO exhibits a maximum in ionic conductivity at twice the salt concentration that PEO, the homopolymer analog of the ion-containing block, does. This finding is contrary to prior studies that examined a more limited range of salt concentrations. In SEO, the phase behavior of the PEO block and LiTFSI closely resembles the phase behavior of homopolymer PEO and LiTFSI. The grain size of the block copolymer morphology was found to decrease with increasing salt concentration, and the ionic conductivity of SEO correlates with decreasing grain size. Structural effects impact the ionic conductivity-salt concentration relationship in block copolymer electrolytes. SEO: polystyrene-block-poly(ethylene oxide); also PS-PEO LiTFSI: lithium bis(trifluoromethanesulfonyl imide

  13. FPGA-Based Embedded Motion Estimation Sensor

    Directory of Open Access Journals (Sweden)

    Zhaoyi Wei

    2008-01-01

    Full Text Available Accurate real-time motion estimation is very critical to many computer vision tasks. However, because of its computational power and processing speed requirements, it is rarely used for real-time applications, especially for micro unmanned vehicles. In our previous work, a FPGA system was built to process optical flow vectors of 64 frames of 640×480 image per second. Compared to software-based algorithms, this system achieved much higher frame rate but marginal accuracy. In this paper, a more accurate optical flow algorithm is proposed. Temporal smoothing is incorporated in the hardware structure which significantly improves the algorithm accuracy. To accommodate temporal smoothing, the hardware structure is composed of two parts: the derivative (DER module produces intermediate results and the optical flow computation (OFC module calculates the final optical flow vectors. Software running on a built-in processor on the FPGA chip is used in the design to direct the data flow and manage hardware components. This new design has been implemented on a compact, low power, high performance hardware platform for micro UV applications. It is able to process 15 frames of 640×480 image per second and with much improved accuracy. Higher frame rate can be achieved with further optimization and additional memory space.

  14. Thermal-structural analysis for ITER in-wall shielding block

    International Nuclear Information System (INIS)

    Hao Junchuan; Song Yuntao; Wu Weiyue; Du Shuangsong; Wang, X.; Ioki, K.

    2012-01-01

    Highlights: ► IWS blocks shall withstand various types of mechanical loads including EM loads, inertial loads and thermal loads. ► Due to the complicated geometry, the finite element method is the suitable tool to solve the problem. ► Contact element has been selected to simulate the friction between the different components. ► At baking phase, secondary stresses due to preloading and temperature difference predominate in the total stress. ► At plasma operation phase, secondary stresses due to preloading and thermal loads were deducted from the total stresses. - Abstract: In order to verify the design strength of the in-wall shielding (IWS) blocks of the ITER, thermal-structural analyses of one IWS block under vacuum vessel (VV) baking and plasma operation conditions have been respectively performed with finite element (FE) method. Among the complicated operation scenarios of the ITER, two critical types of combined loads required by the load specification of IWS were applied on the shielding block. The stress of the block is judged by American Society of Mechanical Engineers (ASME) criterion. Results show that the structure of this block has enough safety margin, and it also supplies detailed information of the stress distribution in concerned region under certain loads.

  15. Usage of digital image correlation in assessment of behavior of block element pavement structure

    Science.gov (United States)

    Grygierek, M.; Grzesik, B.; Rokitowski, P.; Rusin, T.

    2018-05-01

    In diagnostics of existing road pavement structures deflection measurements have fundamental meaning, because of ability to assess present stiffness (bearing capacity) of whole layered construction. During test loading the reaction of pavement structure to applied load is measured in central point or in a few points located along a straight on a 1.5 ÷ 1.8 m distance (i.e. Falling Weight Deflectometer) in similar spacing equal to 20 ÷ 30 cm. Typical measuring techniques are productive and precise enough for most common pavement structures such as flexible, semi-rigid and rigid. It should be noted that in experimental research as well as in pavements in complex stress state, measurement techniques allowing observation of pavement deformation in 3D would have been very helpful. A great example of that type of pavements is a block element pavement structure consisting of i.e. paving blocks or stone slabs. Due to high stiffness and confined ability of cooperation of surrounding block elements, in that type of pavements fatigue life is strongly connected with displacement distribution. Unfortunately, typical deflection measurement methods forefend displacement observations and rotation of single block elements like paving blocks or slabs. Another difficult problem is to carry out unmistakable analysis of cooperation between neighboring elements. For more precise observations of displacements state of block element pavements under a wheel load a Digital Image Correlation (DIC) was used. Application of this method for assessment of behavior of stone slabs pavement under a traffic load enabled the monitoring of deformations distribution and encouraged to formulate conclusions about the initiation mechanism and development of damages in this type of pavement structures. Results shown in this article were obtained in field tests executed on an exploited pavement structure with a surface course made of granite slabs with dimensions 0.5x1.0x0.14 m.

  16. FPGA Implementation of a SAR Two-dimensional Autofocus Approach

    Directory of Open Access Journals (Sweden)

    Guo Jiangzhe

    2016-08-01

    Full Text Available For real-time autofocus of defocused images produced by Synthetic Aperture Radar (SAR, the twodimensional autofocus approach proposed in this study is used to correct the residual range cell migration and compensate for the phase error. Next, a block-wise Phase Gradient Autofocus (PGA is used to correct the space-variant phase error. The Field-Programmable Gate Array (FPGA design procedures, resource utilization, processing speed, accuracy, and autofocus are discussed in detail. The system is able to autofocus an 8K × 8K complex image with single precision within 5.7 s when the FPGA works at 200 MHz. The processing of the measured data verifies the effectiveness and real-time capability of the proposed method.

  17. Relationship between Structural and Stress Relaxation in a Block-Copolymer Melt

    International Nuclear Information System (INIS)

    Patel, Amish J.; Narayanan, Suresh; Sandy, Alec; Mochrie, Simon G. J.; Garetz, Bruce A.; Watanabe, Hiroshi; Balsara, Nitash P.

    2006-01-01

    The relationship between structural relaxation on molecular length scales and macroscopic stress relaxation was explored in a disordered block-copolymer melt. Experiments show that the structural relaxation time, measured by x-ray photon correlation spectroscopy is larger than the terminal stress relaxation time, measured by rheology, by factors as large as 100. We demonstrate that the structural relaxation data are dominated by the diffusion of intact micelles while the stress relaxation data are dominated by contributions due to disordered concentration fluctuations

  18. Superalloy Lattice Block Developed for Use in Lightweight, High-Temperature Structures

    Science.gov (United States)

    Hebsur, Mohan G.; Whittenberger, J. Daniel; Krause, David L.

    2003-01-01

    Successful development of advanced gas turbine engines for aircraft will require lightweight, high-temperature components. Currently titanium-aluminum- (TiAl) based alloys are envisioned for such applications because of their lower density (4 g/cm3) in comparison to superalloys (8.5 g/cm3), which have been utilized for hot turbine engine parts for over 50 years. However, a recently developed concept (lattice block) by JAMCORP, Inc., of Willmington, Massachusetts, would allow lightweight, high-temperature structures to be directly fabricated from superalloys and, thus, take advantage of their well-known, characterized properties. In its simplest state, lattice block is composed of thin ligaments arranged in a three dimensional triangulated trusslike configuration that forms a structurally rigid panel. Because lattice block can be fabricated by casting, correctly sized hardware is produced with little or no machining; thus very low cost manufacturing is possible. Together, the NASA Glenn Research Center and JAMCORP have extended their lattice block methodology for lower melting materials, such as Al alloys, to demonstrate that investment casting of superalloy lattice block is possible. This effort required advances in lattice block pattern design and assembly, higher temperature mold materials and mold fabrication technology, and foundry practice suitable for superalloys (ref. 1). Lattice block panels have been cast from two different Ni-base superalloys: IN 718, which is the most commonly utilized superalloy and retains its strength up to 650 C; and MAR M247, which possesses excellent mechanical properties to at least 1100 C. In addition to the open-cell lattice block geometry, same-sized lattice block panels containing a thin (1-mm-thick) solid face on one side have also been cast from both superalloys. The elevated-temperature mechanical properties of the open cell and face-sheeted superalloy lattice block panels are currently being examined, and the

  19. An efficient HW and SW design of H.264 video compression, storage and playback on FPGA devices for handheld thermal imaging systems

    Science.gov (United States)

    Gunay, Omer; Ozsarac, Ismail; Kamisli, Fatih

    2017-05-01

    Video recording is an essential property of new generation military imaging systems. Playback of the stored video on the same device is also desirable as it provides several operational benefits to end users. Two very important constraints for many military imaging systems, especially for hand-held devices and thermal weapon sights, are power consumption and size. To meet these constraints, it is essential to perform most of the processing applied to the video signal, such as preprocessing, compression, storing, decoding, playback and other system functions on a single programmable chip, such as FPGA, DSP, GPU or ASIC. In this work, H.264/AVC (Advanced Video Coding) compatible video compression, storage, decoding and playback blocks are efficiently designed and implemented on FPGA platforms using FPGA fabric and Altera NIOS II soft processor. Many subblocks that are used in video encoding are also used during video decoding in order to save FPGA resources and power. Computationally complex blocks are designed using FPGA fabric, while blocks such as SD card write/read, H.264 syntax decoding and CAVLC decoding are done using NIOS processor to benefit from software flexibility. In addition, to keep power consumption low, the system was designed to require limited external memory access. The design was tested using 640x480 25 fps thermal camera on CYCLONE V FPGA, which is the ALTERA's lowest power FPGA family, and consumes lower than 40% of CYCLONE V 5CEFA7 FPGA resources on average.

  20. Small Microprocessor for ASIC or FPGA Implementation

    Science.gov (United States)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  1. High performance parallel backprojection on FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Pfanner, Florian; Knaup, Michael; Kachelriess, Marc [Erlangen-Nuernberg Univ., Erlangen (Germany). Inst. of Medical Physics (IMP)

    2011-07-01

    Reconstruction of tomographic images, i.e., images from a Computed Tomography scanner, is a very time consuming issue. The most calculation power is needed for the backprojection step. A closer inspection shows that the algorithm for backprojection is easy to parallelize. FPGAs are able to execute many operations in the same time, so a highly parallel algorithm is a requirement for a powerful acceleration. For data flow rate maximization, we realized the backprojection in a pipelined structure with data throughput of one clock cycle. Due the hardware limitations of the FPGA, it is not possible to reconstruct the image as a whole. So it is necessary to split up the image and reconstruct these parts separately. Despite that, a reconstruction of 512 projections into a 5122 image is calculated within 13 ms on a Virtex 5 FPGA. To save hardware resources we use fixed point arithmetic with an accuracy of 23 bit for calculation. A comparison of the result image and an image, calculated with floating point arithmetic on CPU, shows that there are no differences between these images. (orig.)

  2. Thermally induced structural evolution and performance of mesoporous block copolymer-directed alumina perovskite solar cells.

    KAUST Repository

    Tan, Kwan Wee

    2014-04-11

    Structure control in solution-processed hybrid perovskites is crucial to design and fabricate highly efficient solar cells. Here, we utilize in situ grazing incidence wide-angle X-ray scattering and scanning electron microscopy to investigate the structural evolution and film morphologies of methylammonium lead tri-iodide/chloride (CH3NH3PbI(3-x)Cl(x)) in mesoporous block copolymer derived alumina superstructures during thermal annealing. We show the CH3NH3PbI(3-x)Cl(x) material evolution to be characterized by three distinct structures: a crystalline precursor structure not described previously, a 3D perovskite structure, and a mixture of compounds resulting from degradation. Finally, we demonstrate how understanding the processing parameters provides the foundation needed for optimal perovskite film morphology and coverage, leading to enhanced block copolymer-directed perovskite solar cell performance.

  3. Thermally induced structural evolution and performance of mesoporous block copolymer-directed alumina perovskite solar cells.

    KAUST Repository

    Tan, Kwan Wee; Moore, David T; Saliba, Michael; Sai, Hiroaki; Estroff, Lara A; Hanrath, Tobias; Snaith, Henry J; Wiesner, Ulrich

    2014-01-01

    Structure control in solution-processed hybrid perovskites is crucial to design and fabricate highly efficient solar cells. Here, we utilize in situ grazing incidence wide-angle X-ray scattering and scanning electron microscopy to investigate the structural evolution and film morphologies of methylammonium lead tri-iodide/chloride (CH3NH3PbI(3-x)Cl(x)) in mesoporous block copolymer derived alumina superstructures during thermal annealing. We show the CH3NH3PbI(3-x)Cl(x) material evolution to be characterized by three distinct structures: a crystalline precursor structure not described previously, a 3D perovskite structure, and a mixture of compounds resulting from degradation. Finally, we demonstrate how understanding the processing parameters provides the foundation needed for optimal perovskite film morphology and coverage, leading to enhanced block copolymer-directed perovskite solar cell performance.

  4. Thermally Induced Structural Evolution and Performance of Mesoporous Block Copolymer-Directed Alumina Perovskite Solar Cells

    Science.gov (United States)

    2015-01-01

    Structure control in solution-processed hybrid perovskites is crucial to design and fabricate highly efficient solar cells. Here, we utilize in situ grazing incidence wide-angle X-ray scattering and scanning electron microscopy to investigate the structural evolution and film morphologies of methylammonium lead tri-iodide/chloride (CH3NH3PbI3–xClx) in mesoporous block copolymer derived alumina superstructures during thermal annealing. We show the CH3NH3PbI3–xClx material evolution to be characterized by three distinct structures: a crystalline precursor structure not described previously, a 3D perovskite structure, and a mixture of compounds resulting from degradation. Finally, we demonstrate how understanding the processing parameters provides the foundation needed for optimal perovskite film morphology and coverage, leading to enhanced block copolymer-directed perovskite solar cell performance. PMID:24684494

  5. Structural Color for Additive Manufacturing: 3D-Printed Photonic Crystals from Block Copolymers.

    Science.gov (United States)

    Boyle, Bret M; French, Tracy A; Pearson, Ryan M; McCarthy, Blaine G; Miyake, Garret M

    2017-03-28

    The incorporation of structural color into 3D printed parts is reported, presenting an alternative to the need for pigments or dyes for colored parts produced through additive manufacturing. Thermoplastic build materials composed of dendritic block copolymers were designed, synthesized, and used to additively manufacture plastic parts exhibiting structural color. The reflection properties of the photonic crystals arise from the periodic nanostructure formed through block copolymer self-assembly during polymer processing. The wavelength of reflected light could be tuned across the visible spectrum by synthetically controlling the block copolymer molecular weight and manufacture parts that reflected violet, green, or orange light with the capacity to serve as selective optical filters and light guides.

  6. Thermal Analysis, Structural Studies and Morphology of Spider Silk-like Block Copolymers

    Science.gov (United States)

    Huang, Wenwen

    Spider silk is a remarkable natural block copolymer, which offers a unique combination of low density, excellent mechanical properties, and thermal stability over a wide range of temperature, along with biocompatibility and biodegrability. The dragline silk of Nephila clavipes, is one of the most well understood and the best characterized spider silk, in which alanine-rich hydrophobic blocks and glycine-rich hydrophilic blocks are linked together generating a functional block copolymer with potential uses in biomedical applications such as guided tissue repair and drug delivery. To provide further insight into the relationships among peptide amino acid sequence, block length, and physical properties, in this thesis, we studied synthetic proteins inspired by the genetic sequences found in spider dragline silks, and used these bioengineered spider silk block copolymers to study thermal, structural and morphological features. To obtain a fuller understanding of the thermal dynamic properties of these novel materials, we use a model to calculate the heat capacity of spider silk block copolymer in the solid or liquid state, below or above the glass transition temperature, respectively. We characterize the thermal phase transitions by temperature modulated differential scanning calorimetry (TMDSC) and thermogravimetric analysis (TGA). We also determined the crystallinity by TMDSC and compared the result with Fourier transform infrared spectroscopy (FTIR) and wide angle X-ray diffraction (WAXD). To understand the protein-water interactions with respect to the protein amino acid sequence, we also modeled the specific reversing heat capacity of the protein-water system, Cp(T), based on the vibrational, rotational and translational motions of protein amino acid residues and water molecules. Advanced thermal analysis methods using TMDSC and TGA show two glass transitions were observed in all samples during heating. The low temperature glass transition, Tg(1), is related to

  7. Development of FPGA-Based Control Board

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Yoon Hee; Jeong, See Chae; Choi, Woong Seock; Lee, Chang Jae; Jeong, Jin Kwon; Ha, Jae Hong [Korea Power Engineering Company Inc., Daejeon (Korea, Republic of)

    2009-10-15

    It is well known that existing nuclear power plant (NPP) control systems contain many components which are becoming obsolete at an increasing rate. Various studies have been conducted to address control system hardware obsolescence. Obsolete analog and digital control systems in non-nuclear power plants are commonly replaced with modern digital control systems, programmable logic controllers (PLC) and distributed control systems (DCS). Field Programmable Gate Arrays (FPGAs) are highlighted as an alternative means for obsolete control systems. FPGAs are advanced digital integrated circuits (ICs) that contain configurable (programmable) blocks of logic along with configurable interconnects between these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of Programmable Logic Device (PLD). Nowadays they can contain millions of logic gates by nanotechnology and so be used to implement extremely large and complex functions that previously could be realized only using Application-Specific Integrated Circuits (ASICs). This paper is to present the development of a FPGAbased control board performing user-defined control functions. An Actel ProASIC{sup plus} FPGA platform is implemented as the comparator of Plant Protection System (PPS). Functional simulation is implemented for the comparator.

  8. Thinned crustal structure and tectonic boundary of the Nansha Block, southern South China Sea

    Science.gov (United States)

    Dong, Miao; Wu, Shi-Guo; Zhang, Jian

    2016-12-01

    The southern South China Sea margin consists of the thinned crustal Nansha Block and a compressional collision zone. The Nansha Block's deep structure and tectonic evolution contains critical information about the South China Sea's rifting. Multiple geophysical data sets, including regional magnetic, gravity and reflection seismic data, reveal the deep structure and rifting processes. Curie point depth (CPD), estimated from magnetic anomalies using a windowed wavenumber-domain algorithm, enables us to image thermal structures. To derive a 3D Moho topography and crustal thickness model, we apply Oldenburg algorithm to the gravity anomaly, which was extracted from the observed free air gravity anomaly data after removing the gravity effect of density variations of sediments, and temperature and pressure variations of the lithospheric mantle. We found that the Moho depth (20 km) is shallower than the CPD (24 km) in the Northwest Borneo Trough, possibly caused by thinned crust, low heat flow and a low vertical geothermal gradient. The Nansha Block's northern boundary is a narrow continent-ocean transition zone constrained by magnetic anomalies, reflection seismic data, gravity anomalies and an interpretation of Moho depth (about 13 km). The block extends southward beneath a gravity-driven deformed sediment wedge caused by uplift on land after a collision, with a contribution from deep crustal flow. Its southwestern boundary is close to the Lupar Line defined by a significant negative reduction to the pole (RTP) of magnetic anomaly and short-length-scale variation in crustal thickness, increasing from 18 to 26 km.

  9. Rapid-X - An FPGA Development Toolset Using a Custom Simulink Library for MTCA.4 Modules

    Science.gov (United States)

    Prędki, Paweł; Heuer, Michael; Butkowski, Łukasz; Przygoda, Konrad; Schlarb, Holger; Napieralski, Andrzej

    2015-06-01

    The recent introduction of advanced hardware architectures such as the Micro Telecommunications Computing Architecture (MTCA) caused a change in the approach to implementation of control schemes in many fields. The development has been moving away from traditional programming languages ( C/C++), to hardware description languages (VHDL, Verilog), which are used in FPGA development. With MATLAB/Simulink it is possible to describe complex systems with block diagrams and simulate their behavior. Those diagrams are then used by the HDL experts to implement exactly the required functionality in hardware. Both the porting of existing applications and adaptation of new ones require a lot of development time from them. To solve this, Xilinx System Generator, a toolbox for MATLAB/Simulink, allows rapid prototyping of those block diagrams using hardware modelling. It is still up to the firmware developer to merge this structure with the hardware-dependent HDL project. This prevents the application engineer from quickly verifying the proposed schemes in real hardware. The framework described in this article overcomes these challenges, offering a hardware-independent library of components that can be used in Simulink/System Generator models. The components are subsequently translated into VHDL entities and integrated with a pre-prepared VHDL project template. Furthermore, the entire implementation process is run in the background, giving the user an almost one-click path from control scheme modelling and simulation to bit-file generation. This approach allows the application engineers to quickly develop new schemes and test them in real hardware environment. The applications may range from simple data logging or signal generation ones to very advanced controllers. Taking advantage of the Simulink simulation capabilities and user-friendly hardware implementation routines, the framework significantly decreases the development time of FPGA-based applications.

  10. Assessment of Structural Strength of Commercial Sandcrete Blocks in Kano State

    Directory of Open Access Journals (Sweden)

    M. Mohammed

    2014-12-01

    Full Text Available This research was aimed at studying the strength properties of the commercial sandcrete blocks produced in Kano State. A total number of 250 block samples were randomly collected from five local government areas, fifty (50 from each of the local governments and cured for 3, 7, 14, 21 and 28 days. The blocks were subjected to various tests at wet and dry conditions as follow: wet compressive test, drying shrinkage, moisture movement and density all in accordance with established standards in the structural laboratory of Department of Civil Engineering, Ahmadu Bello University, Zaria, and the aggregates were subjected to sieve analysis and moisture content determination in the Geotechnical Laboratory of the department. The compressive strength was found to be between 0.25 N/mm2 and 0.92 N/mm2 which are far below the specified values (2.5 N/mm2 to 3.45N/mm2 respectively in the Nigerian Industrial Standard (NIS 87, 2000. It is concluded that the commercially produced sandcrete blocks in Kano State are of lower standard than expected. It is recommended that workshop should be organised periodically to enlighten the producers of sandcrete blocks. The importance of adhering to standard specifications should be emphasised and strict penalties be meted out to erring producers by the Nigerian Industrial Standard Organisation.

  11. Reflection of block neotectonics in geological structure of paleogene strata of Chornobyl exclusion zone

    International Nuclear Information System (INIS)

    Skvortsov, V.V.; Oleksandrova, N.V.; Khodorovs'kij, A.Ya.

    2014-01-01

    Neotectonic block differentiation of Chernobyl Exclusion zone area was fixed by the results of the geological and structure analysis of paleogene strata in complex with the space survey data interpretation. Structural plan of the latest tectonic movements had a block character; it was shown by the fracture systems, which represent the components of known regional tectonic zones of various trends and are found in the features of phanerozoic rock mass structure. The territory under study is divided into two parts - the northern one, where in the neotectonic movements are generally more intensive with manifestation practically all over the fracture zones, and the southern part, where in the newest breaks belong mainly to submeridional also to south-western regional fracture zones. The southern part of the Exclusion zone, as a whole, holds the greatest promise by comparison with the northern one in the view of neotectonic criteria regarding the geological repository siting for radioactive waste disposal

  12. Heuristic algorithms for feature selection under Bayesian models with block-diagonal covariance structure.

    Science.gov (United States)

    Foroughi Pour, Ali; Dalton, Lori A

    2018-03-21

    Many bioinformatics studies aim to identify markers, or features, that can be used to discriminate between distinct groups. In problems where strong individual markers are not available, or where interactions between gene products are of primary interest, it may be necessary to consider combinations of features as a marker family. To this end, recent work proposes a hierarchical Bayesian framework for feature selection that places a prior on the set of features we wish to select and on the label-conditioned feature distribution. While an analytical posterior under Gaussian models with block covariance structures is available, the optimal feature selection algorithm for this model remains intractable since it requires evaluating the posterior over the space of all possible covariance block structures and feature-block assignments. To address this computational barrier, in prior work we proposed a simple suboptimal algorithm, 2MNC-Robust, with robust performance across the space of block structures. Here, we present three new heuristic feature selection algorithms. The proposed algorithms outperform 2MNC-Robust and many other popular feature selection algorithms on synthetic data. In addition, enrichment analysis on real breast cancer, colon cancer, and Leukemia data indicates they also output many of the genes and pathways linked to the cancers under study. Bayesian feature selection is a promising framework for small-sample high-dimensional data, in particular biomarker discovery applications. When applied to cancer data these algorithms outputted many genes already shown to be involved in cancer as well as potentially new biomarkers. Furthermore, one of the proposed algorithms, SPM, outputs blocks of heavily correlated genes, particularly useful for studying gene interactions and gene networks.

  13. Controlling sub-microdomain structure in microphase-ordered block copolymers and their nanocomposites

    Science.gov (United States)

    Bowman, Michelle Kathleen

    Block copolymers exhibit a wealth of morphologies that continue to find ubiquitous use in a diverse variety of mature and emergent (nano)technologies, such as photonic crystals, integrated circuits, pharmaceutical encapsulents, fuel cells and separation membranes. While numerous studies have explored the effects of molecular confinement on such copolymers, relatively few have examined the sub-microdomain structure that develops upon modification of copolymer molecular architecture or physical incorporation of nanoscale objects. This work will address two relevant topics in this vein: (i) bidisperse brushes formed by single block copolymer molecules and (ii) copolymer nanocomposites formed by addition of molecular or nanoscale additives. In the first case, an isomorphic series of asymmetric poly(styrene-b -isoprene-b-styrene) (S1IS2) triblock copolymers of systematically varied chain length has been synthesized from a parent SI diblock copolymer. Small-angle x-ray scattering, coupled with dynamic rheology and self-consistent field theory (SCFT), reveals that the progressively grown S2 block initially resides in the I-rich matrix and effectively reduces the copolymer incompatibility until a critical length is reached. At this length, the S2 block co-locates with the S1 block so that the two blocks generate a bidisperse brush (insofar as the S1 and S2 lengths differ). This single-molecule analog to binary block copolymer blends affords unique opportunities for materials design at sub-microdomain length scales and provides insight into the transition from diblock to triblock copolymer (and thermoplastic elastomeric nature). In the second case, I explore the distribution of molecular and nanoscale additives in microphase-ordered block copolymers and demonstrate via SCFT that an interfacial excess, which depends strongly on additive concentration, selectivity and relative size, develops. These predictions are in agreement with experimental findings. Moreover, using a

  14. The MCD circuit based on FPGA

    International Nuclear Information System (INIS)

    Vu Quoc Trong

    2003-01-01

    Two MCD circuits based on different FPGA are presented as results of the study of the MAX+PLUS II software and FPGA devices. An external memory like 62256 and programmed EPM7064S will be able to form a MCD with 8 kilo channels. (NHA)

  15. Nano-structured micropatterns by combination of block copolymer self-assembly and UV photolithography

    International Nuclear Information System (INIS)

    Gorzolnik, B; Mela, P; Moeller, M

    2006-01-01

    A procedure for the fabrication of nano-structured micropatterns by direct UV photo-patterning of a monolayer of a self-assembled block copolymer/transition metal hybrid structure is described. The method exploits the selective photochemical modification of a self-assembled monolayer of hexagonally ordered block copolymer micelles loaded with a metal precursor salt. Solvent development of the monolayer after irradiation results in the desired pattern of micelles on the surface. Subsequent plasma treatment of the pattern leaves ordered metal nanodots. The presented technique is a simple and low-cost combination of 'top-down' and 'bottom-up' approaches that allows decoration of large areas with periodic and aperiodic patterns of nano-objects, with good control over two different length scales: nano- and micrometres

  16. An efficient, block-by-block algorithm for inverting a block tridiagonal, nearly block Toeplitz matrix

    International Nuclear Information System (INIS)

    Reuter, Matthew G; Hill, Judith C

    2012-01-01

    We present an algorithm for computing any block of the inverse of a block tridiagonal, nearly block Toeplitz matrix (defined as a block tridiagonal matrix with a small number of deviations from the purely block Toeplitz structure). By exploiting both the block tridiagonal and the nearly block Toeplitz structures, this method scales independently of the total number of blocks in the matrix and linearly with the number of deviations. Numerical studies demonstrate this scaling and the advantages of our method over alternatives.

  17. An efficient and cost effective FPGA based implementation of the Viola-Jones face detection algorithm

    Directory of Open Access Journals (Sweden)

    Peter Irgens

    2017-04-01

    Full Text Available We present an field programmable gate arrays (FPGA based implementation of the popular Viola-Jones face detection algorithm, which is an essential building block in many applications such as video surveillance and tracking. Our implementation is a complete system level hardware design described in a hardware description language and validated on the affordable DE2-115 evaluation board. Our primary objective is to study the achievable performance with a low-end FPGA chip based implementation. In addition, we release to the public domain the entire project. We hope that this will enable other researchers to easily replicate and compare their results to ours and that it will encourage and facilitate further research and educational ideas in the areas of image processing, computer vision, and advanced digital design and FPGA prototyping.

  18. New block matrix spectral problem and Hamiltonian structure of the discrete integrable coupling system

    International Nuclear Information System (INIS)

    Yu Fajun

    2008-01-01

    In [W.X. Ma, J. Phys. A: Math. Theor. 40 (2007) 15055], Prof. Ma gave a beautiful result (a discrete variational identity). In this Letter, based on a discrete block matrix spectral problem, a new hierarchy of Lax integrable lattice equations with four potentials is derived. By using of the discrete variational identity, we obtain Hamiltonian structure of the discrete soliton equation hierarchy. Finally, an integrable coupling system of the soliton equation hierarchy and its Hamiltonian structure are obtained through the discrete variational identity

  19. New block matrix spectral problem and Hamiltonian structure of the discrete integrable coupling system

    Energy Technology Data Exchange (ETDEWEB)

    Yu Fajun [College of Maths and Systematic Science, Shenyang Normal University, Shenyang 110034 (China)], E-mail: yufajun888@163.com

    2008-06-09

    In [W.X. Ma, J. Phys. A: Math. Theor. 40 (2007) 15055], Prof. Ma gave a beautiful result (a discrete variational identity). In this Letter, based on a discrete block matrix spectral problem, a new hierarchy of Lax integrable lattice equations with four potentials is derived. By using of the discrete variational identity, we obtain Hamiltonian structure of the discrete soliton equation hierarchy. Finally, an integrable coupling system of the soliton equation hierarchy and its Hamiltonian structure are obtained through the discrete variational identity.

  20. Computational strategies for the automated design of RNA nanoscale structures from building blocks using NanoTiler.

    Science.gov (United States)

    Bindewald, Eckart; Grunewald, Calvin; Boyle, Brett; O'Connor, Mary; Shapiro, Bruce A

    2008-10-01

    One approach to designing RNA nanoscale structures is to use known RNA structural motifs such as junctions, kissing loops or bulges and to construct a molecular model by connecting these building blocks with helical struts. We previously developed an algorithm for detecting internal loops, junctions and kissing loops in RNA structures. Here we present algorithms for automating or assisting many of the steps that are involved in creating RNA structures from building blocks: (1) assembling building blocks into nanostructures using either a combinatorial search or constraint satisfaction; (2) optimizing RNA 3D ring structures to improve ring closure; (3) sequence optimisation; (4) creating a unique non-degenerate RNA topology descriptor. This effectively creates a computational pipeline for generating molecular models of RNA nanostructures and more specifically RNA ring structures with optimized sequences from RNA building blocks. We show several examples of how the algorithms can be utilized to generate RNA tecto-shapes.

  1. Computational strategies for the automated design of RNA nanoscale structures from building blocks using NanoTiler☆

    Science.gov (United States)

    Bindewald, Eckart; Grunewald, Calvin; Boyle, Brett; O’Connor, Mary; Shapiro, Bruce A.

    2013-01-01

    One approach to designing RNA nanoscale structures is to use known RNA structural motifs such as junctions, kissing loops or bulges and to construct a molecular model by connecting these building blocks with helical struts. We previously developed an algorithm for detecting internal loops, junctions and kissing loops in RNA structures. Here we present algorithms for automating or assisting many of the steps that are involved in creating RNA structures from building blocks: (1) assembling building blocks into nanostructures using either a combinatorial search or constraint satisfaction; (2) optimizing RNA 3D ring structures to improve ring closure; (3) sequence optimisation; (4) creating a unique non-degenerate RNA topology descriptor. This effectively creates a computational pipeline for generating molecular models of RNA nanostructures and more specifically RNA ring structures with optimized sequences from RNA building blocks. We show several examples of how the algorithms can be utilized to generate RNA tecto-shapes. PMID:18838281

  2. An FPGA-based silicon neuronal network with selectable excitability silicon neurons

    Directory of Open Access Journals (Sweden)

    Jing eLi

    2012-12-01

    Full Text Available This paper presents a digital silicon neuronal network which simulates the nerve system in creatures and has the ability to execute intelligent tasks, such as associative memory. Two essential elements, the mathematical-structure-based digital spiking silicon neuron (DSSN and the transmitter release based silicon synapse, allow the network to show rich dynamic behaviors and are computationally efficient for hardware implementation. We adopt mixed pipeline and parallel structure and shift operations to design a sufficient large and complex network without excessive hardware resource cost. The network with $256$ full-connected neurons is built on a Digilent Atlys board equipped with a Xilinx Spartan-6 LX45 FPGA. Besides, a memory control block and USB control block are designed to accomplish the task of data communication between the network and the host PC. This paper also describes the mechanism of associative memory performed in the silicon neuronal network. The network is capable of retrieving stored patterns if the inputs contain enough information of them. The retrieving probability increases with the similarity between the input and the stored pattern increasing. Synchronization of neurons is observed when the successful stored pattern retrieval occurs.

  3. Using a best-practice perioperative governance structure to implement better block scheduling.

    Science.gov (United States)

    Heiser, Randy

    2013-01-01

    Achieving, developing, and maintaining a well-functioning OR scheduling system requires a well-designed perioperative governance structure. Traditional OR/surgery committees, consisting mainly of surgeons, have tried to provide this function but often have not succeeded. An OR governance model should be led by an OR executive committee that functions as a board of directors for the surgery program and works closely with the surgery department medical director and an OR advisory committee. Ideally, the OR executive committee should develop a block schedule that includes a mix of block, open, and urgent or emergent OR access, because this combination is most effective for improving OR use and adapting to changes in surgical procedure volume. Copyright © 2013 AORN, Inc. Published by Elsevier Inc. All rights reserved.

  4. Quantifying private benefits of control from a structural model of block trades

    NARCIS (Netherlands)

    Albuquerque, R.; Schroth, E.

    2009-01-01

    We study the determinants of private benefits of control in negotiated block transactions. We estimate the block pricing model in Burkart, Gromb, and Panunzi (2000) explicitly accounting for both block premia and block discounts in the data. The evidence suggests that the occurrence of a block

  5. Design Verification Enhancement of FPGA-based Plant Protection System Trip Logics for Nuclear Power Plant

    International Nuclear Information System (INIS)

    Ahmed, Ibrahim; Jung, Jae Cheon; Heo, Gyun Young

    2016-01-01

    As part of strengthening the application of FPGA technology and find solution to its challenges in NPPs, international atomic energy agency (IAEA) has indicated interest by joining sponsorship of Topical Group on FPGA Applications in NPPs (TG-FAN) that hold meetings up to 7th times until now, in form of workshop (International workshop on the application of FPGAs in NPPs) annually since 2008. The workshops attracted a significant interest and had a broad representation of stakeholders such as regulators, utilities, research organizations, system designers, and vendors, from various countries that converge to discuss the current issues regarding instrumentation and control (I and C) systems as well as FPGA applications. Two out of many technical issues identified by the group are lifecycle of FPGA-based platforms, systems, and applications; and methods and tools for V and V. Therefore, in this work, several design steps that involved the use of model-based systems engineering process as well as MATLAB/SIMULINK model which lead to the enhancement of design verification are employed. The verified and validated design output works correctly and effectively. Conclusively, the model-based systems engineering approach and the structural step-by-step design modeling techniques including SIMULINK model utilized in this work have shown how FPGA PPS trip logics design verification can be enhanced. If these design approaches are employ in the design of FPGA-based I and C systems, the design can be easily verified and validated

  6. Embedded Active Vision System Based on an FPGA Architecture

    Directory of Open Access Journals (Sweden)

    Chalimbaud Pierre

    2007-01-01

    Full Text Available In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks, inspired by biological vision systems. For this reason, we propose an original approach based on a system on programmable chip implemented in an FPGA connected to a CMOS imager and an inertial set. With such a structure based on reprogrammable devices, this system admits a high degree of versatility and allows the implementation of parallel image processing algorithms.

  7. Embedded Active Vision System Based on an FPGA Architecture

    Directory of Open Access Journals (Sweden)

    Pierre Chalimbaud

    2006-12-01

    Full Text Available In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks, inspired by biological vision systems. For this reason, we propose an original approach based on a system on programmable chip implemented in an FPGA connected to a CMOS imager and an inertial set. With such a structure based on reprogrammable devices, this system admits a high degree of versatility and allows the implementation of parallel image processing algorithms.

  8. Mesoscopic multiphase structures and the interfaces of block and graft copolymers in bulk

    International Nuclear Information System (INIS)

    Matsushita, Yushu

    1996-01-01

    Microphase-separated structures of copolymers with various architectures and their polymer/polymer interfaces were studied. They are SP diblock, PSP triblock, and SPP graft copolymers, where S and P denote polystyrene and poly(2-vinylpyridine), respectively. Morphological observations were carried out by means of transmission electron microscopy and small-angle X-ray scattering. Chain dimensions of component polymers were measured by small-angle neutron scattering and microphase-separated interfaces were observed by neutron reflectivity measurements using deuterium-labeled samples. It was clarified that morphological phase transitions among thermodynamically equilibrium structures for SP diblock and PSP triblock copolymers occur at almost the same compositions; however, those of SPP graft copolymers tend to occur at higher volume fraction of polystyrene, φ s , than those for block copolymers. As for alternating lamellar structures it turned out to be clear that lamellar domain spacings, D's, were scaled as the 2/3 power of the molecular weight of polymers irrespective of their architectures. S block chains of SP diblock and PSP triblock copolymers in lamellar structures were both confirmed to be deformed toward the direction perpendicular to the lamellar interfaces, but it revealed that their volumes were preserved. Further, S/P interfacial thicknesses of SP and PSP were essentially the same to each other and the values defined as the FWHM of the error functions which express the segment density distributions of the interfaces were determined to be about 4 nm. (author)

  9. On the interaction of the morphological structure and the LC behaviour of LC side chain block copolymers

    NARCIS (Netherlands)

    Fischer, H.R.; Poser, S.; Arnold, M.

    1995-01-01

    The interaction between morphological structure and phase behaviour of a LC side group block copolymer has been investigated using DSC, TEM and small angle X-ray diffraction. All samples of Polystyrene-block-2-(3-cholesteryloxycarbonyloxy)ethyl methacrylate (PS-b-PChEMA) show a phase separation

  10. On the interaction of the morphological structure and the LC behaviour of LC side chain block copolymers

    NARCIS (Netherlands)

    Fischer, H.R.; Arnold, M.

    1995-01-01

    The interaction between morphological structure and phase behaviour of a group of LC side group block copolymers have been investigated using DSC, TEM and small angle X-ray diffraction. Generally, phase separation between the two blocks was observed. It was found that in the case of those samples,

  11. Self-assembled structures of amphiphilic ionic block copolymers: Theory, self-consistent field modeling and experiment

    NARCIS (Netherlands)

    Borisov, O.V.; Zhulina, E.B.; Leermakers, F.A.M.; Muller, A.H.E.

    2011-01-01

    We present an overview of statistical thermodynamic theories that describe the self-assembly of amphiphilic ionic/hydrophobic diblock copolymers in dilute solution. Block copolymers with both strongly and weakly dissociating (pH-sensitive) ionic blocks are considered. We focus mostly on structural

  12. Multichannel analyzer embedded in FPGA; Analizador multicanal embebido en FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Garcia D, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98060 Zacatecas, Zac. (Mexico); Ordaz G, O. O. [Universidad de Cordoba, Departamento de Arquitectura de Computadores, Electronica y Tecnologia Electronica, Campus de Rabanales, Ctra. N-IVa Km 396, 14071 Cordoba (Spain); Bravo M, I., E-mail: angelogarciad@hotmail.com [Universidad de Alcala de Henares, Departamento de Electronica, Campus Universitario, Carretera Madrid-Barcelona Km 33.600, 28801 Alcala de Henares, Madrid (Spain)

    2017-10-15

    Ionizing radiation has different applications, so it is a very significant and useful tool, which in turn can be dangerous for living beings if they are exposed to uncontrolled doses. However, due to its characteristics, it cannot be perceived by any of the senses of the human being, so that in order to know the presence of it, radiation detectors and additional devices are required to quantify and classify it. A multichannel analyzer is responsible for separating the different pulse heights that are generated in the detectors, in a certain number of channels; according to the number of bits of the analog to digital converter. The objective of the work was to design and implement a multichannel analyzer and its associated virtual instrument, for nuclear spectrometry. The components of the multichannel analyzer were created in VHDL hardware description language and packaged in the Xilinx Vivado design suite, making use of resources such as the ARM processing core that the System on Chip Zynq contains and the virtual instrument was developed on the LabView programming graphics platform. The first phase was to design the hardware architecture to be embedded in the FPGA and for the internal control of the multichannel analyzer the application was generated for the ARM processor in C language. For the second phase, the virtual instrument was developed for the management, control and visualization of the results. The data obtained as a result of the development of the system were observed graphically in a histogram showing the spectrum measured. The design of the multichannel analyzer embedded in FPGA was tested with two different radiation detection systems (hyper-pure germanium and scintillation) which allowed determining that the spectra obtained are similar in comparison with the commercial multichannel analyzers. (Author)

  13. Electrically and chemically tunable soft-solid block copolymer structural color (Conference Presentation)

    Science.gov (United States)

    Park, Cheolmin

    2016-09-01

    1D photonic crystals based on the periodic stacking of two different dielectric layers have been widely studied due to their potential use in low-power reflective mode displays, e-books and sensors, but the fabrication of mechanically flexible polymer structural color (SC) films, with electro-active color switching, remains challenging. Here, we demonstrate free-standing electric field tunable ionic liquid swollen block copolymer films. Placement of a polymer/ionic liquid (IL) film-reservoir adjacent to a self-assembled poly(styrene-block-quaternized 2vinyl pyridine) (PS-b-QP2VP) copolymer SC film allowed the development of R, G and B full-color SC block copolymer films by swelling of the QP2VP domains by the ionic liquid associated with water molecules. The IL-polymer/BCP SC film is mechanically flexible with excellent color stability over several days at ambient conditions. The selective swelling of the QP2VP domains could be controlled by both the ratio of the IL to a polymer in the gel-like IL reservoir layer and by an applied voltage in the range of -3V to +6V using a metal/IL reservoir/SC film/IL reservoir/metal capacitor type device.

  14. Implementation of FPGA-Based Diverse Protection System

    International Nuclear Information System (INIS)

    Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min

    2015-01-01

    Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails

  15. Implementation of FPGA-Based Diverse Protection System

    Energy Technology Data Exchange (ETDEWEB)

    Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min [KEPCO Engineering and Construction Company Inc., Daejeon (Korea, Republic of)

    2015-10-15

    Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails.

  16. SVM-PB-Pred: SVM based protein block prediction method using sequence profiles and secondary structures.

    Science.gov (United States)

    Suresh, V; Parthasarathy, S

    2014-01-01

    We developed a support vector machine based web server called SVM-PB-Pred, to predict the Protein Block for any given amino acid sequence. The input features of SVM-PB-Pred include i) sequence profiles (PSSM) and ii) actual secondary structures (SS) from DSSP method or predicted secondary structures from NPS@ and GOR4 methods. There were three combined input features PSSM+SS(DSSP), PSSM+SS(NPS@) and PSSM+SS(GOR4) used to test and train the SVM models. Similarly, four datasets RS90, DB433, LI1264 and SP1577 were used to develop the SVM models. These four SVM models developed were tested using three different benchmarking tests namely; (i) self consistency, (ii) seven fold cross validation test and (iii) independent case test. The maximum possible prediction accuracy of ~70% was observed in self consistency test for the SVM models of both LI1264 and SP1577 datasets, where PSSM+SS(DSSP) input features was used to test. The prediction accuracies were reduced to ~53% for PSSM+SS(NPS@) and ~43% for PSSM+SS(GOR4) in independent case test, for the SVM models of above two same datasets. Using our method, it is possible to predict the protein block letters for any query protein sequence with ~53% accuracy, when the SP1577 dataset and predicted secondary structure from NPS@ server were used. The SVM-PB-Pred server can be freely accessed through http://bioinfo.bdu.ac.in/~svmpbpred.

  17. Small angle neutron scattering study of the micelle structure of amphiphilic block copolymers

    International Nuclear Information System (INIS)

    Yamaoka, H.; Matsuoka, H.; Sumaru, K.; Hanada, S.

    1994-01-01

    The amphiphilic block copolymers of vinyl ether were prepared by living cationic polymerization. The partially deuterated copolymers for SANS experiments were especially synthesized by introducing deuterated phenyl units in the hydrophobic chain. SANS measurements were performed for aqueous solutions of these copolymers by changing H 2 O/D 2 O ratios. The SANS profiles indicate that the micelles in the present system exhibit a core-shell structure and that the size and shape of micelles are largely dependent on the length of hydrophobic chain. The micelle of shorter hydrophobic chain was found to be nearly spherical, whereas the micelle of longer hydrophobic chain was confirmed to have an ellipsoidal shape

  18. Crustal block structure by GPS data using neural network in the Northern Tien Shan

    Science.gov (United States)

    Kostuk, A.; Carmenate, D.

    2010-05-01

    For over ten years regular GPS measurements have been carried out by Research Station RAS in the Central Asia. The results of these measurements have not only proved the conclusion that the Earth's crust meridional compression equals in total about 17 mm/year from the Tarim massif to the Kazakh shield, but have also allowed estimating deformation behavior in the region. As is known, deformation behavior of continental crust is an actively discussed issue. On the one hand, the Earth's crust is presented as a set of microplates (blocks) and deformation here is a result of shifting along the blocks boundaries, on the other hand, lithospheric deformation is distributed by volume and meets the rheological model of nonlinear viscous fluid. This work represents an attempt to detect the block structure of the surface of the Northern Tien Shan using GPS velocity fields. As a significant difference from analogous works, appears the vector field clustering with the help of neural network used as a classifier by many criteria that allows dividing input space into areas and using of all three components of GPS velocity. In this case, we use such a feature of neural networks as self-organization. Among the mechanisms of self-organization there are two main classes: self-organization based on the Hebb associative rule and the mechanism of neuronal competition based on the generalized Kohonen rule. In this case, we use an approach of self-organizing networks in which we take neuronal competition as an algorithm for their training. As a rule, these are single-layer networks where each neuron is connected to all components of m-dimensional input vector. GPS vectors of the Central Asian velocity field located within the territory of the Northern Tien Shan were used as input patterns. Measurements at GPS sites were fulfilled in 36 hour-long sessions by double-frequency receivers Trimble and Topcon. In so doing, measurement discreteness equaled 30 seconds; the data were processed by

  19. New poly(dimethylsiloxane)/poly(perfluorooctylethyl acrylate) block copolymers: structure and order across multiple length scales in thin films

    KAUST Repository

    Martinelli, Elisa; Galli, Giancarlo; Krishnan, Sitaraman; Paik, Marvin Y.; Ober, Christopher K.; Fischer, Daniel A.

    2011-01-01

    Three sets of a new class of low surface tension block copolymers were synthesized consisting of a poly(dimethylsiloxane) (PDMS) block and a poly(perfluorooctylethyl acrylate) (AF8) block. The polymers were prepared using a bromo-terminated PDMS macroinitiator, to which was attached an AF8 block grown using atom transfer radical polymerization (ATRP) in such a designed way that the molecular weight and composition of the two polymer blocks were regularly varied. The interplay of both the phase separated microstructure and the mesomorphic character of the fluorinated domains with their effect on surface structure was evaluated using a suite of analytical tools. Surfaces of spin-coated and thermally annealed films were assessed using a combination of X-ray photoelectron spectroscopy (XPS) and near-edge X-ray absorption fine structure (NEXAFS) studies. Both atomic force microscopy (AFM) measurements and grazing incidence small angle X-ray scattering (GISAXS) studies were carried out to evaluate the microstructure of the thin films. Even in block copolymers in which the PDMS block was the majority component, a significant presence of the lower surface energy AF8 block was detected at the film surface. Moreover, the perfluorooctyl helices of the AF8 repeat units were highly oriented at the surface in an ordered, tilted smectic structure, which was compared with those of the bulk powder samples using wide-angle X-ray powder diffraction (WAXD) studies. © 2011 The Royal Society of Chemistry.

  20. Multichannel analyzer embedded in FPGA

    International Nuclear Information System (INIS)

    Garcia D, A.; Hernandez D, V. M.; Vega C, H. R.; Ordaz G, O. O.; Bravo M, I.

    2017-10-01

    Ionizing radiation has different applications, so it is a very significant and useful tool, which in turn can be dangerous for living beings if they are exposed to uncontrolled doses. However, due to its characteristics, it cannot be perceived by any of the senses of the human being, so that in order to know the presence of it, radiation detectors and additional devices are required to quantify and classify it. A multichannel analyzer is responsible for separating the different pulse heights that are generated in the detectors, in a certain number of channels; according to the number of bits of the analog to digital converter. The objective of the work was to design and implement a multichannel analyzer and its associated virtual instrument, for nuclear spectrometry. The components of the multichannel analyzer were created in VHDL hardware description language and packaged in the Xilinx Vivado design suite, making use of resources such as the ARM processing core that the System on Chip Zynq contains and the virtual instrument was developed on the LabView programming graphics platform. The first phase was to design the hardware architecture to be embedded in the FPGA and for the internal control of the multichannel analyzer the application was generated for the ARM processor in C language. For the second phase, the virtual instrument was developed for the management, control and visualization of the results. The data obtained as a result of the development of the system were observed graphically in a histogram showing the spectrum measured. The design of the multichannel analyzer embedded in FPGA was tested with two different radiation detection systems (hyper-pure germanium and scintillation) which allowed determining that the spectra obtained are similar in comparison with the commercial multichannel analyzers. (Author)

  1. Effect of autonomic blocking agents and structurally related substances on the “salt arousal of drinking”

    NARCIS (Netherlands)

    Wied, D. de

    The effect of autonomic blocking agents and structurally related substances was studied in rats in which thirst was produced by the administration of a hypertonic sodium chloride solution. Scopolamine, methamphetamine, amphetamine, chlorpromazine, atropine, mecamylamine, hexamethonium, nethalide,

  2. Irradiation test of FPGA for BES III

    International Nuclear Information System (INIS)

    Chen Yixin; Liang Hao; Xue Jundong; Liu Baoying; Liu Qiang; Yu Xiaoqi; Zhou Yongzhao; Hou Long

    2005-01-01

    The irradiation effect of FPGA, applied in Front-end Electronics for experiments of High-Energy Physics, is a serious problem. The performance of FPGA, used in the front-end card of Muon Counters of BES III project, needs to be evaluated under irradiation. SEUs on Altera ACEX 1K FPGA, observed in the experiment under the irradiation of γ ray, 14 and 2.5 MeV neutrons, was investigated. The authors calculated involved cross-section and provided reasonable analysis and evaluation for the result of the experiment. The conclusion about feasibility of applying ACEX 1K FPGA in the front-end card of the readout system of Muon Counters for BES III was given. (authors)

  3. Analysis of the aggregation structure from amphiphilic block copolymers in solutions by small-angle x-ray scattering

    CERN Document Server

    Rong Li Xia; Wang Jun; Wei Liu He; Li Fu Mian; Li Zi Chen

    2002-01-01

    The aggregation structure of polystyrene-p vinyl benzoic amphiphilic block copolymers which were prepared in different conditions was investigated by synchrotron radiation small-angle x-ray scattering (SAXS). The micelle was self-assembled in selective solvents of the block copolymers. Authors' results demonstrate that the structure of the micelle depends on the factors, such as the composition of the copolymers, the nature of the solvent and the concentration of the solution

  4. Algorithmic strategies for FPGA-based vision

    OpenAIRE

    Lim, Yoong Kang

    2016-01-01

    As demands for real-time computer vision applications increase, implementations on alternative architectures have been explored. These architectures include Field-Programmable Gate Arrays (FPGAs), which offer a high degree of flexibility and parallelism. A problem with this is that many computer vision algorithms have been optimized for serial processing, and this often does not map well to FPGA implementation. This thesis introduces the concept of FPGA-tailored computer vision algorithms...

  5. Block-induced Complex Structures Building the Flare-productive Solar Active Region 12673

    Energy Technology Data Exchange (ETDEWEB)

    Yang, Shuhong; Zhang, Jun [CAS Key Laboratory of Solar Activity, National Astronomical Observatories, Chinese Academy of Sciences, Beijing 100012 (China); Zhu, Xiaoshuai [Max-Planck Institute for Solar System Research, D-37077 Göttingen (Germany); Song, Qiao, E-mail: shuhongyang@nao.cas.cn [Key Laboratory of Space Weather, National Center for Space Weather, China Meteorological Administration, Beijing 100081 (China)

    2017-11-10

    Solar active region (AR) 12673 produced 4 X-class, 27 M-class, and numerous lower-class flares during its passage across the visible solar disk in 2017 September. Our study is to answer the questions why this AR was so flare-productive and how the X9.3 flare, the largest one of the past decade, took place. We find that there was a sunspot in the initial several days, and then two bipolar regions emerged nearby it successively. Due to the standing of the pre-existing sunspot, the movement of the bipoles was blocked, while the pre-existing sunspot maintained its quasi-circular shaped umbra only with the disappearance of a part of penumbra. Thus, the bipolar patches were significantly distorted, and the opposite polarities formed two semi-circular shaped structures. After that, two sequences of new bipolar regions emerged within the narrow semi-circular zone, and the bipolar patches separated along the curved channel. The new bipoles sheared and interacted with the previous ones, forming a complex topological system, during which numerous flares occurred. At the highly sheared region, a great deal of free energy was accumulated. On September 6, one negative patch near the polarity inversion line began to rapidly rotate and shear with the surrounding positive fields, and consequently the X9.3 flare erupted. Our results reveal that the block-induced complex structures built the flare-productive AR and the X9.3 flare was triggered by an erupting filament due to the kink instability. To better illustrate this process, a block-induced eruption model is proposed for the first time.

  6. Protection and Control with FPGA technology

    Energy Technology Data Exchange (ETDEWEB)

    Sohn, K. Y.; Yi, W. J. [Korea Reliability Technology and System, Daejeon (Korea, Republic of); Koo, I. S. [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2012-03-15

    To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper.

  7. Protection and Control with FPGA technology

    International Nuclear Information System (INIS)

    Sohn, K. Y.; Yi, W. J.; Koo, I. S.

    2012-01-01

    To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper

  8. Tethered Forth system for FPGA applications

    Science.gov (United States)

    Goździkowski, Paweł; Zabołotny, Wojciech M.

    2013-10-01

    This paper presents the tethered Forth system dedicated for testing and debugging of FPGA based electronic systems. Use of the Forth language allows to interactively develop and run complex testing or debugging routines. The solution is based on a small, 16-bit soft core CPU, used to implement the Forth Virtual Machine. Thanks to the use of the tethered Forth model it is possible to minimize usage of the internal RAM memory in the FPGA. The function of the intelligent terminal, which is an essential part of the tethered Forth system, may be fulfilled by the standard PC computer or by the smartphone. System is implemented in Python (the software for intelligent terminal), and in VHDL (the IP core for FPGA), so it can be easily ported to different hardware platforms. The connection between the terminal and FPGA may be established and disconnected many times without disturbing the state of the FPGA based system. The presented system has been verified in the hardware, and may be used as a tool for debugging, testing and even implementing of control algorithms for FPGA based systems.

  9. The effect of heat treatment on the internal structure of nanostructured block copolymer films

    Energy Technology Data Exchange (ETDEWEB)

    Sepe, A; Hoppe, E T; Jaksch, S; Magerl, D; Zhong, Q; Papadakis, C M [Technische Universitaet Muenchen, Physikdepartment, Fachgebiet Physik weicher Materie/Lehrstuhl fuer funktionelle Materialien, James-Franck-Strasse 1, 85747 Garching (Germany); Perlich, J [HASYLAB at DESY, Notkestrasse 85, 22603 Hamburg (Germany); Posselt, D [IMFUFA, Department of Science, Systems and Models, Roskilde University, PO Box 260, 4000 Roskilde (Denmark); Smilgies, D-M, E-mail: papadakis@tum.de [Cornell High Energy Synchrotron Source (CHESS), Wilson Laboratory, Cornell University, Ithaca, NY 14853 (United States)

    2011-06-29

    We report on the temperature dependence of the nanostructure of thin block copolymer films, as studied using in situ grazing-incidence small-angle x-ray scattering (GISAXS). We focus on spin-coated poly(styrene-b-butadiene) diblock copolymer thin films featuring lamellae perpendicular to the substrate. In situ GISAXS measurements elucidate the structural changes during heat treatment at temperatures between 60 and 130 {sup 0}C. Thermal treatment below 100 {sup 0}C does not destroy the perpendicular lamellar order. In contrast, treatment between 105 and 120 {sup 0}C leads to a broad distribution of lamellar orientations which only partially recovers upon subsequent cooling. Treatment at 130 {sup 0}C leads to severe changes of the film structure. We attribute the change of behavior at 100 {sup 0}C to the onset of the glass transition of the polystyrene block and the related increase of long-range mobility. Our results indicate that the perpendicular lamellar orientation for high molar mass samples is not stable under all conditions.

  10. Structural analysis of cellular blocks for a prestressed cast iron reactor pressure vessel

    International Nuclear Information System (INIS)

    Thomas, R.G.; Head, J.L.

    1979-01-01

    The cast segments from which the prestressed cast iron nuclear reactor pressure vessel may be constructed are not readily amenable to detailed three-dimensional finite element analysis because their complex internal web structure requires a very large number of elements if reasonable aspect ratios are to be retained. A technique has been developed of modelling these blocks using plate bending elements from the ASKA code. By this means it has been possible to study in detail several designs of casting and to identify favourable features. The results of these studies, and others in which assessments are made of the sensitivity of the structure to prestressing load changes and machining errors, are reported. (orig.)

  11. Reliability study of Piezoelectric Structures Dedicated to Energy Harvesting by the Way of Blocking Force Investigation

    International Nuclear Information System (INIS)

    Maaroufi, S; Parrain, F; Lefeuvre, E; Boutaud, B; Molin, R Dal

    2015-01-01

    In this paper we propose an approach to study the reliability of piezoelectric structures and more precisely energy harvesting micro-devices dedicated to autonomous active medical implants (new generation pacemakers). The structure under test is designed as a bimorph piezoelectric cantilever with a seismic mass at its tip. Good understanding of material aging and mechanical failure is critical for this kind of system. To study the reliability and durability of the piezoelectric part we propose to establish a new accelerated methodology and an associated test bench where the environment and stimuli can be precisely controlled over a wide period of time. This will allow the identification of potential failure modes and the study of their impacts by the way of direct mechanical investigation based on stiffness and blocking force measurements performed periodically. (paper)

  12. Reliability study of Piezoelectric Structures Dedicated to Energy Harvesting by the Way of Blocking Force Investigation

    Science.gov (United States)

    Maaroufi, S.; Parrain, F.; Lefeuvre, E.; Boutaud, B.; Dal Molin, R.

    2015-12-01

    In this paper we propose an approach to study the reliability of piezoelectric structures and more precisely energy harvesting micro-devices dedicated to autonomous active medical implants (new generation pacemakers). The structure under test is designed as a bimorph piezoelectric cantilever with a seismic mass at its tip. Good understanding of material aging and mechanical failure is critical for this kind of system. To study the reliability and durability of the piezoelectric part we propose to establish a new accelerated methodology and an associated test bench where the environment and stimuli can be precisely controlled over a wide period of time. This will allow the identification of potential failure modes and the study of their impacts by the way of direct mechanical investigation based on stiffness and blocking force measurements performed periodically.

  13. Development of a multitechnology FPGA: a reconfigurable architecture for photonic information processing

    Science.gov (United States)

    Mal, Prosenjit; Toshniwal, Kavita; Hawk, Chris; Bhadri, Prashant R.; Beyette, Fred R., Jr.

    2004-06-01

    Over the years, Field Programmable Gate Arrays (FPGAs) have made a profound impact on the electronics industry with rapidly improving semiconductor-manufacturing technology ranging from sub-micron to deep sub-micron processes and equally innovative CAD tools. Though FPGA has revolutionized programmable/reconfigurable digital logic technology, one limitation of current FPGA"s is that the user is limited to strictly electronic designs. Thus, they are not suitable for applications that are not purely electronic, such as optical communications, photonic information processing systems and other multi-technology applications (ex. analog devices, MEMS devices and microwave components). Over recent years, the growing trend has been towards the incorporation of non-traditional device technologies into traditional CMOS VLSI systems. The integration of these technologies requires a new kind of FPGA that can merge conventional FPGA technology with photonic and other multi-technology devices. The proposed new class of field programmable device will extend the flexibility, rapid prototyping and reusability benefits associated with conventional electronic into photonic and multi-technology domain and give rise to the development of a wider class of programmable and embedded integrated systems. This new technology will create a tremendous opportunity for applying the conventional programmable/reconfigurable hardware concepts in other disciplines like photonic information processing. To substantiate this novel architectural concept, we have fabricated proof-of-the-concept CMOS VLSI Multi-technology FPGA (MT-FPGA) chips that include both digital field programmable logic blocks and threshold programmable photoreceivers which are suitable for sensing optical signals. Results from these chips strongly support the feasibility of this new optoelectronic device concept.

  14. Semiexperimental equilibrium structures for building blocks of organic and biological molecules: the B2PLYP route.

    Science.gov (United States)

    Penocchio, Emanuele; Piccardo, Matteo; Barone, Vincenzo

    2015-10-13

    The B2PLYP double hybrid functional, coupled with the correlation-consistent triple-ζ cc-pVTZ (VTZ) basis set, has been validated in the framework of the semiexperimental (SE) approach for deriving accurate equilibrium structures of molecules containing up to 15 atoms. A systematic comparison between new B2PLYP/VTZ results and several equilibrium SE structures previously determined at other levels, in particular B3LYP/SNSD and CCSD(T) with various basis sets, has put in evidence the accuracy and the remarkable stability of such model chemistry for both equilibrium structures and vibrational corrections. New SE equilibrium structures for phenylacetylene, pyruvic acid, peroxyformic acid, and phenyl radical are discussed and compared with literature data. Particular attention has been devoted to the discussion of systems for which lack of sufficient experimental data prevents a complete SE determination. In order to obtain an accurate equilibrium SE structure for these situations, the so-called templating molecule approach is discussed and generalized with respect to our previous work. Important applications are those involving biological building blocks, like uracil and thiouracil. In addition, for more general situations the linear regression approach has been proposed and validated.

  15. Structural implications of hERG K+ channel block by a high-affinity minimally structured blocker

    Science.gov (United States)

    Helliwell, Matthew V.; Zhang, Yihong; El Harchi, Aziza; Du, Chunyun; Hancox, Jules C.; Dempsey, Christopher E.

    2018-01-01

    Cardiac potassium channels encoded by human ether-à-go-go–related gene (hERG) are major targets for structurally diverse drugs associated with acquired long QT syndrome. This study characterized hERG channel inhibition by a minimally structured high-affinity hERG inhibitor, Cavalli-2, composed of three phenyl groups linked by polymethylene spacers around a central amino group, chosen to probe the spatial arrangement of side chain groups in the high-affinity drug-binding site of the hERG pore. hERG current (IhERG) recorded at physiological temperature from HEK293 cells was inhibited with an IC50 of 35.6 nm with time and voltage dependence characteristic of blockade contingent upon channel gating. Potency of Cavalli-2 action was markedly reduced for attenuated inactivation mutants located near (S620T; 54-fold) and remote from (N588K; 15-fold) the channel pore. The S6 Y652A and F656A mutations decreased inhibitory potency 17- and 75-fold, respectively, whereas T623A and S624A at the base of the selectivity filter also decreased potency (16- and 7-fold, respectively). The S5 helix F557L mutation decreased potency 10-fold, and both F557L and Y652A mutations eliminated voltage dependence of inhibition. Computational docking using the recent cryo-EM structure of an open channel hERG construct could only partially recapitulate experimental data, and the high dependence of Cavalli-2 block on Phe-656 is not readily explainable in that structure. A small clockwise rotation of the inner (S6) helix of the hERG pore from its configuration in the cryo-EM structure may be required to optimize Phe-656 side chain orientations compatible with high-affinity block. PMID:29545312

  16. Structured nanoporous surfaces from hybrid block copolymer micelle films with metal ions

    International Nuclear Information System (INIS)

    Kim, Minsoo P; Yi, Gi-Ra; Kim, Hyeong Jun; Kim, Bumjoon J

    2015-01-01

    We present a novel method for producing structured nanoporous thin films using block copolymer (BCP) micelles loaded with metallic ions. The BCP micellar thin films containing gold (Au) ions were prepared by spin-coating poly(styrene-block-4-vinylpyridine) (PS-b-P4VP) micelle solutions in which Au precursors (AuCl 4 − ) were selectively loaded onto the P4VP core. When the micellar films were exposed to cetyltrimethylammonium bromide (CTAB) solutions, the Au precursors were selectively extracted from the P4VP domains due to their strong electrostatic interaction with CTAB, leading to the formation of pores in the micelles. Consequently, regularly patterned nanoporous surfaces were formed. By controlling the molecular weight (M n ) of PS-b-P4VP and the amount of Au precursors (λ) that were loaded in the P4VP domains, the pore size and depth could be tuned precisely. In particular, when a sufficient amount of Au precursors was loaded (λ  ≥ 0.3), the porous surface nanostructure was well developed. In addition, the pore size and depth of the nanostructure increased as the λ value increased. For instance, when the λ value increased from 0.3 to 1.0, the pore size increased from 22.8 nm to 28.8 nm, and the pore depth increased from 2.1 nm to 3.2 nm. Interestingly, the transition from the nonporous structures to the porous structures in the micellar film could be reversibly controlled by adding and removing the Au precursors in the film. Moreover, our method for the preparation of nanoporous films can be extended to micellar film by incorporating other metal ions such as silver (Ag) and iron (Fe). (paper)

  17. Intramolecular structures in a single copolymer chain consisting of flexible and semiflexible blocks: Monte Carlo simulation of a lattice model

    International Nuclear Information System (INIS)

    Martemyanova, Julia A; Ivanov, Victor A; Paul, Wolfgang

    2014-01-01

    We study conformational properties of a single multiblock copolymer chain consisting of flexible and semiflexible blocks. Monomer units of different blocks are equivalent in the sense of the volume interaction potential, but the intramolecular bending potential between successive bonds along the chain is different. We consider a single flexible-semiflexible regular multiblock copolymer chain with equal content of flexible and semiflexible units and vary the length of the blocks and the stiffness parameter. We perform flat histogram type Monte Carlo simulations based on the Wang-Landau approach and employ the bond fluctuation lattice model. We present here our data on different non-trivial globular morphologies which we have obtained in our model for different values of the block length and the stiffness parameter. We demonstrate that the collapse can occur in one or in two stages depending on the values of both these parameters and discuss the role of the inhomogeneity of intraglobular distributions of monomer units of both flexible and semiflexible blocks. For short block length and/or large stiffness the collapse occurs in two stages, because it goes through intermediate (meta-)stable structures, like a dumbbell shaped conformation. In such conformations the semiflexible blocks form a cylinder-like core, and the flexible blocks form two domains at both ends of such a cylinder. For long block length and/or small stiffness the collapse occurs in one stage, and in typical conformations the flexible blocks form a spherical core of a globule while the semiflexible blocks are located on the surface and wrap around this core.

  18. The effect of film thickness and molecular structure on order and disorder in thin films of compositionally asymmetric block copolymers

    Science.gov (United States)

    Mishra, Vindhya

    Directed self-assembly of thin film block copolymers offer a high throughput-low cost route to produce next generation lithographic devices, if one can bring the defect densities in the self assembled patterns below tolerance limits. However, the ability to control the nanoscale structure or morphology in thin film block copolymers presents challenges due to confinement effects on equilibrium behavior. Using structure characterization techniques such as grazing incidence small angle X-ray scattering (GISAXS), transmission electron and atomic force microscopy as well as self-consistent field theory, we have investigated how film thickness, annealing temperature and block copolymer structure affects the equilibrium behavior of asymmetric block copolymer films. Our studies have revealed the complicated dependence of order-disorder transitions, order-order transitions and symmetry transitions on film thickness. We found that the thickness dependent transition in the packing symmetry of spherical morphology diblock copolymers can be suppressed by blending with a small amount of majority block homopolymer, which allowed us to resolve the driving force behind this transition. Defect densities in, and the order-disorder transition temperature of, thin films of graphoepitaxially aligned diblock copolymer cylinders showed surprising sensitivity to the microdomain spacing. Methods to mitigate defect formation in thin films have been identified. The challenge of quantification of structural order in these systems was overcome using GISAXS, which allowed us to study the phenomena of disordering in two and three dimensions. Through studies on block copolymers which exhibit an order-order transition in bulk, we found that that subtle differences in the packing frustration of the spherical and cylindrical phases as well as the higher configurational entropy of free chain ends at the surface can drive the equilibrium configuration in thin films away from the stable bulk structure

  19. Efficient FPGA Implementation of a STBC-OFDM Combiner for an IEEE 802.16 Software Radio Receiver

    DEFF Research Database (Denmark)

    Cattoni, Andrea Fabio; Le Moullec, Yannick; Sacchi, Claudio

    2014-01-01

    In this paper, an efficient FPGA implementation of a 4x4 Space-Time Block Coding (STBC) combiner for MIMO-OFDM software radio receivers is considered. The proposed combiner is based on a low-complexity algorithm which reduces the interference due to the Quasi-Orthogonality of the STBC decoding...

  20. Fpga-based control of piezoelectric actuators

    Directory of Open Access Journals (Sweden)

    Juhász László

    2011-01-01

    Full Text Available In many industrial applications like semiconductor production and optical inspection systems, the availability of positioning systems capable to follow trajectory paths in the range of several centimetres, featuring at the same time a nanometre-range precision, is demanding. Pure piezoelectric stages and standard positioning systems with motor and spindle are not able to meet such requirements, because of the small operation range and inadequacies like backlash and friction. One concept for overcoming these problems consists of a hybrid positioning system built through the integration of a DC-drive in series with a piezoelectric actuator. The wide range of potential applications enables a considerable market potential for such an actuator, but due to the high variety of possible positioned objects and dynamic requirements, the required control complexity may be significant. In this paper, a real-time capable state-space control concept for the piezoelectric actuators, embedded in such a hybrid micropositioning system, is presented. The implementation of the controller together with a real-time capable hysteresis compensation measure is performed using a low-budget FPGA-board, whereas the superimposed integrated controller is realized with a dSPACE RCP-system. The advantages of the designed control over a traditional proportional-integral control structure are proven through experimental results using a commercially available hybrid micropositioning system. Positioning results by different dynamic requirements featuring positioning velocities from 1 μm/s up to 5 cm/s are given.

  1. Fault tolerance based on serial communication of FPGA

    International Nuclear Information System (INIS)

    Peng Jing; Fang Zongliang; Xu Quanzhou; Hu Jiewei; Ma Guizhen

    2012-01-01

    There maybe appear mistake in serial communication. This paper was described the intellectual detector of γ dose ratemeter communication with FPGA. The software of FPGA designed the code about fault tolerance, prevented mistake effectively. (authors)

  2. Using block pulse functions for seismic vibration semi-active control of structures with MR dampers

    Science.gov (United States)

    Rahimi Gendeshmin, Saeed; Davarnia, Daniel

    2018-03-01

    This article applied the idea of block pulse functions in the semi-active control of structures. The BP functions give effective tools to approximate complex problems. The applied control algorithm has a major effect on the performance of the controlled system and the requirements of the control devices. In control problems, it is important to devise an accurate analytical technique with less computational cost. It is proved that the BP functions are fundamental tools in approximation problems which have been applied in disparate areas in last decades. This study focuses on the employment of BP functions in control algorithm concerning reduction the computational cost. Magneto-rheological (MR) dampers are one of the well-known semi-active tools that can be used to control the response of civil Structures during earthquake. For validation purposes, numerical simulations of a 5-story shear building frame with MR dampers are presented. The results of suggested method were compared with results obtained by controlling the frame by the optimal control method based on linear quadratic regulator theory. It can be seen from simulation results that the suggested method can be helpful in reducing seismic structural responses. Besides, this method has acceptable accuracy and is in agreement with optimal control method with less computational costs.

  3. Cutting method for structural component into block like shape, and device used for cutting

    International Nuclear Information System (INIS)

    Nakazawa, Koichi; Ito, Akira; Tateiwa, Masaaki.

    1995-01-01

    Two grooves each of a predetermined depth are formed along a surface of a structural component, and a portion between the two grooves is cut in the direction of the depth from the surface of the structural component by using a cutting wire of a wire saw device. Then, the cutting wire is moved in the extending direction of the grooves while optionally changing the position in the direction of the depth to conduct cutting for the back face. Further, the cutting wire is moved in the direction of the depth of the groove toward the surface, to cut a portion between the two grooves. The wire saw device comprises a wire saw main body movable along the surface of the structural component, a pair of wire guide portions extending in the direction of the depth, guide pooleys capable of guiding the cutting wire guides revolvably and rotatably disposed at the top end, and an endless annular cutting wire extending between the wire guide portions. Thus, it is possible to continuously cut out blocks set to optional size and thickness. In addition, remote cutting is possible with no requirement for an operator to access to the vicinity of radioactivated portions. (N.H.)

  4. Synthesis of blind source separation algorithms on reconfigurable FPGA platforms

    Science.gov (United States)

    Du, Hongtao; Qi, Hairong; Szu, Harold H.

    2005-03-01

    Recent advances in intelligence technology have boosted the development of micro- Unmanned Air Vehicles (UAVs) including Sliver Fox, Shadow, and Scan Eagle for various surveillance and reconnaissance applications. These affordable and reusable devices have to fit a series of size, weight, and power constraints. Cameras used on such micro-UAVs are therefore mounted directly at a fixed angle without any motion-compensated gimbals. This mounting scheme has resulted in the so-called jitter effect in which jitter is defined as sub-pixel or small amplitude vibrations. The jitter blur caused by the jitter effect needs to be corrected before any other processing algorithms can be practically applied. Jitter restoration has been solved by various optimization techniques, including Wiener approximation, maximum a-posteriori probability (MAP), etc. However, these algorithms normally assume a spatial-invariant blur model that is not the case with jitter blur. Szu et al. developed a smart real-time algorithm based on auto-regression (AR) with its natural generalization of unsupervised artificial neural network (ANN) learning to achieve restoration accuracy at the sub-pixel level. This algorithm resembles the capability of the human visual system, in which an agreement between the pair of eyes indicates "signal", otherwise, the jitter noise. Using this non-statistical method, for each single pixel, a deterministic blind sources separation (BSS) process can then be carried out independently based on a deterministic minimum of the Helmholtz free energy with a generalization of Shannon's information theory applied to open dynamic systems. From a hardware implementation point of view, the process of jitter restoration of an image using Szu's algorithm can be optimized by pixel-based parallelization. In our previous work, a parallelly structured independent component analysis (ICA) algorithm has been implemented on both Field Programmable Gate Array (FPGA) and Application

  5. Rapid and highly integrated FPGA-based Shack-Hartmann wavefront sensor for adaptive optics system

    Science.gov (United States)

    Chen, Yi-Pin; Chang, Chia-Yuan; Chen, Shean-Jen

    2018-02-01

    In this study, a field programmable gate array (FPGA)-based Shack-Hartmann wavefront sensor (SHWS) programmed on LabVIEW can be highly integrated into customized applications such as adaptive optics system (AOS) for performing real-time wavefront measurement. Further, a Camera Link frame grabber embedded with FPGA is adopted to enhance the sensor speed reacting to variation considering its advantage of the highest data transmission bandwidth. Instead of waiting for a frame image to be captured by the FPGA, the Shack-Hartmann algorithm are implemented in parallel processing blocks design and let the image data transmission synchronize with the wavefront reconstruction. On the other hand, we design a mechanism to control the deformable mirror in the same FPGA and verify the Shack-Hartmann sensor speed by controlling the frequency of the deformable mirror dynamic surface deformation. Currently, this FPGAbead SHWS design can achieve a 266 Hz cyclic speed limited by the camera frame rate as well as leaves 40% logic slices for additionally flexible design.

  6. FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging.

    Science.gov (United States)

    Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

    2012-07-01

    In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models.

  7. Chain conformations of the component polymers and the microphase separation structures of homopolymer/block coplymer blends

    International Nuclear Information System (INIS)

    Torikai, Naoya; Mogi, Yasuhiro; Matsushita, Yushu; Noda, Ichiro; Han, C.C.

    1993-01-01

    Microdomain spacings of lamellar structures formed by styrene homopolymer/styrene-2-vinylpyridine diblock copolymer/2-vinylpyridine homopolymer blends were measured by small-angle X-ray scattering (SAXS) and single chain conformations of block copolymers in the same blend system were measured by small-angle neutron scattering (SANS). The molecular weight of diblock copolymers is 78K-72K, and three kinds of styrene homopolymer (S H ) and 2-vinylpyridine homopolymer (P H ) pairs were blended, their molecular weight ratios to that of host block chains were 0.17, 0.38, and 0.78, respectively. Two blend ratios of homopolymer (H)/block copolymer (B), i.e. 1/2 and 1/1 were examined. It was found that the domain spacings of all blends are larger than that of pure block copolymer and that they are increasing with increasing the molecular weight of homopolymers and/or with increasing the volume fraction of homopolymers. Further, block chains in the blends were confirmed to have almost the same chain dimension as that of block chain in pure block copolymer system in the direction parallel to the domain interface irrespective of molecular weight and volume fraction of homopolymers. (author)

  8. A Scalable Unsegmented Multiport Memory for FPGA-Based Systems

    Directory of Open Access Journals (Sweden)

    Kevin R. Townsend

    2015-01-01

    Full Text Available On-chip multiport memory cores are crucial primitives for many modern high-performance reconfigurable architectures and multicore systems. Previous approaches for scaling memory cores come at the cost of operating frequency, communication overhead, and logic resources without increasing the storage capacity of the memory. In this paper, we present two approaches for designing multiport memory cores that are suitable for reconfigurable accelerators with substantial on-chip memory or complex communication. Our design approaches tackle these challenges by banking RAM blocks and utilizing interconnect networks which allows scaling without sacrificing logic resources. With banking, memory congestion is unavoidable and we evaluate our multiport memory cores under different memory access patterns to gain insights about different design trade-offs. We demonstrate our implementation with up to 256 memory ports using a Xilinx Virtex-7 FPGA. Our experimental results report high throughput memories with resource usage that scales with the number of ports.

  9. Development of Integral Environment in Matlab/Simulink for FPGA

    Directory of Open Access Journals (Sweden)

    Dejan Jokic

    2014-01-01

    Full Text Available In this paper is presented realization of integral environment which consists of software and hardware components for the purpose of programming Altera DE boards. Software component is Toolbox FPGA Real Time which enables simple use of Matlab/Simulink with DSP Builder for the purpose of realization of control structures. Hardware component are Interface cards that make connection of DE board with object of control possible. Simulation and experimental results of DC motor control indicate the usefulness of the proposed concept.

  10. Structure-directing star-shaped block copolymers: supramolecular vesicles for the delivery of anticancer drugs.

    Science.gov (United States)

    Yang, Chuan; Liu, Shao Qiong; Venkataraman, Shrinivas; Gao, Shu Jun; Ke, Xiyu; Chia, Xin Tian; Hedrick, James L; Yang, Yi Yan

    2015-06-28

    Amphiphilic polycarbonate/PEG copolymer with a star-like architecture was designed to facilitate a unique supramolecular transformation of micelles to vesicles in aqueous solution for the efficient delivery of anticancer drugs. The star-shaped amphipilic block copolymer was synthesized by initiating the ring-opening polymerization of trimethylene carbonate (TMC) from methyl cholate through a combination of metal-free organo-catalytic living ring-opening polymerization and post-polymerization chain-end derivatization strategies. Subsequently, the self-assembly of the star-like polymer in aqueous solution into nanosized vesicles for anti-cancer drug delivery was studied. DOX was physically encapsulated into vesicles by dialysis and drug loading level was significant (22.5% in weight) for DOX. Importantly, DOX-loaded nanoparticles self-assembled from the star-like copolymer exhibited greater kinetic stability and higher DOX loading capacity than micelles prepared from cholesterol-initiated diblock analogue. The advantageous disparity is believed to be due to the transformation of micelles (diblock copolymer) to vesicles (star-like block copolymer) that possess greater core space for drug loading as well as the ability of such supramolecular structures to encapsulate DOX. DOX-loaded vesicles effectively inhibited the proliferation of 4T1, MDA-MB-231 and BT-474 cells, with IC50 values of 10, 1.5 and 1.0mg/L, respectively. DOX-loaded vesicles injected into 4T1 tumor-bearing mice exhibited enhanced accumulation in tumor tissue due to the enhanced permeation and retention (EPR) effect. Importantly, DOX-loaded vesicles demonstrated greater tumor growth inhibition than free DOX without causing significant body weight loss or cardiotoxicity. The unique ability of the star-like copolymer emanating from the methyl cholate core provided the requisite modification in the block copolymer interfacial curvature to generate vesicles of high loading capacity for DOX with significant

  11. FPGA based Smart Wireless MIMO Control System

    International Nuclear Information System (INIS)

    Ali, Syed M Usman; Hussain, Sajid; Siddiqui, Ali Akber; Arshad, Jawad Ali; Darakhshan, Anjum

    2013-01-01

    In our present work, we have successfully designed, and developed an FPGA based smart wireless MIMO (Multiple Input and Multiple Output) system capable of controlling multiple industrial process parameters such as temperature, pressure, stress and vibration etc. To achieve this task we have used Xilin x Spartan 3E FPGA (Field Programmable Gate Array) instead of conventional microcontrollers. By employing FPGA kit to PC via RF transceivers which has a working range of about 100 meters. The developed smart system is capable of performing the control task assigned to it successfully. We have also provided a provision to our proposed system that can be accessed for monitoring and control through the web and GSM as well. Our proposed system can be equally applied to all the hazardous and rugged industrial environments where a conventional system cannot work effectively

  12. FPGA controlled artificial vascular system

    Directory of Open Access Journals (Sweden)

    Laqua D.

    2015-09-01

    Full Text Available Monitoring the oxygen saturation of an unborn child is an invasive procedure, so far. Transabdominal fetal pulse oximetry is a promising method under research, used to estimate the oxygen saturation of a fetus noninvasively. Due to the nature of the method, the fetal information needs to be extracted from a mixed signal. To properly evaluate signal processing algorithms, a phantom modeling fetal and maternal blood circuits and tissue layers is necessary. This paper presents an improved hardware concept for an artificial vascular system, utilizing an FPGA based CompactRIO System from National Instruments. The experimental model to simulate the maternal and fetal blood pressure curve consists of two identical hydraulic circuits. Each of these circuits consists of a pre-pressure system and an artificial vascular system. Pulse curves are generated by proportional valves, separating these two systems. The dilation of the fetal and maternal artificial vessels in tissue substitutes is measured by transmissive and reflective photoplethysmography. The measurement results from the pressure sensors and the transmissive optical sensors are visualized to show the functionality of the pulse generating systems. The trigger frequency for the maternal valve was set to 1 per second, the fetal valve was actuated at 0.7 per second for validation. The reflective curve, capturing pulsations of the fetal and maternal circuit, was obtained with a high power LED (905 nm as light source. The results show that the system generates pulse curves, similar to its physiological equivalent. Further, the acquired reflective optical signal is modulated by the alternating diameter of the tubes of both circuits, allowing for tests of signal processing algorithms.

  13. Design of optical axis jitter control system for multi beam lasers based on FPGA

    Science.gov (United States)

    Ou, Long; Li, Guohui; Xie, Chuanlin; Zhou, Zhiqiang

    2018-02-01

    A design of optical axis closed-loop control system for multi beam lasers coherent combining based on FPGA was introduced. The system uses piezoelectric ceramics Fast Steering Mirrors (FSM) as actuator, the Fairfield spot detection of multi beam lasers by the high speed CMOS camera for optical detecting, a control system based on FPGA for real-time optical axis jitter suppression. The algorithm for optical axis centroid detecting and PID of anti-Integral saturation were realized by FPGA. Optimize the structure of logic circuit by reuse resource and pipeline, as a result of reducing logic resource but reduced the delay time, and the closed-loop bandwidth increases to 100Hz. The jitter of laser less than 40Hz was reduced 40dB. The cost of the system is low but it works stably.

  14. FPGA Implementation of the stepwise shutdown system

    Energy Technology Data Exchange (ETDEWEB)

    Lotjonen, L.

    2012-07-01

    This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and stanfards can be used to some extent but the hardware aspects bring new challenges that cannot be tacled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation processfrom the reguirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)

  15. FPGA Implementation of the stepwise shutdown system

    International Nuclear Information System (INIS)

    Lotjonen, L.

    2012-01-01

    This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and standards can be used to some extent but the hardware aspects bring new challenges that cannot be tackled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation process from the requirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)

  16. An FPGA-Based Massively Parallel Neuromorphic Cortex Simulator.

    Science.gov (United States)

    Wang, Runchun M; Thakur, Chetan S; van Schaik, André

    2018-01-01

    This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as complex models of various areas of the cortex. The main novelty of this work is the abstraction of a neuromorphic architecture into clusters represented by minicolumns and hypercolumns, analogously to the fundamental structural units observed in neurobiology. Without this approach, simulating large-scale fully connected networks needs prohibitively large memory to store look-up tables for point-to-point connections. Instead, we use a novel architecture, based on the structural connectivity in the neocortex, such that all the required parameters and connections can be stored in on-chip memory. The cortex simulator can be easily reconfigured for simulating different neural networks without any change in hardware structure by programming the memory. A hierarchical communication scheme allows one neuron to have a fan-out of up to 200 k neurons. As a proof-of-concept, an implementation on one Altera Stratix V FPGA was able to simulate 20 million to 2.6 billion leaky-integrate-and-fire (LIF) neurons in real time. We verified the system by emulating a simplified auditory cortex (with 100 million neurons). This cortex simulator achieved a low power dissipation of 1.62 μW per neuron. With the advent of commercially available FPGA boards, our system offers an accessible and scalable tool for the design, real-time simulation, and analysis of large-scale spiking neural networks.

  17. AFM study of excimer laser patterning of block-copolymer: Creation of ordered hierarchical, hybrid, or recessed structures

    International Nuclear Information System (INIS)

    Švanda, Jan; Siegel, Jakub; Švorčík, Vaclav; Lyutakov, Oleksiy

    2016-01-01

    Highlights: • Combination of bottom-up (BCP separation) and top-down (laser patterning) technologies allows obtaining hierarchical structures. • Surface morphologies were determined by the order of patterning steps (laser modification, annealing, surface reconstruction). • Tuning the order of steps enables the reorientation of BCP domain at large scale, fabrication of hierarchical, hybrid or recessed structures. • The obtained structures can find potential applications in nanotechnology, plasmonics, information storage, sensors and smart surfaces. - Abstract: We report fabrication of the varied range of hierarchical structures by combining bottom-up self-assembly of block copolymer poly(styrene-block-vinylpyridine) (PS-b-P4VP) with top-down excimer laser patterning method. Different procedures were tested, where laser treatment was applied before phase separation and after phase separation or phase separation and surface reconstruction. Laser treatment was performed using either polarized laser light with the aim to create periodical pattern on polymer surface or non-polarized light for preferential removing of polystyrene (PS) part from PS-b-P4VP. Additionally, dye was introduced into one part of block copolymer (P4VP) with the aim to modify its response to laser light. Resulting structures were analyzed by XPS, UV–vis and AFM techniques. Application of polarized laser light leads to creation of structures with hierarchical, recessed or hybrid geometries. Non-polarized laser beam allows pronouncing the block copolymer phase separated structure. Tuning the order of steps or individual step conditions enables the efficient reorientation of block-copolymer domain at large scale, fabrication of hierarchical, hybrid or recessed structures. The obtained structures can find potential applications in nanotechnology, photonics, plasmonics, information storage, optical devices, sensors and smart surfaces.

  18. Structure of malaria invasion protein RH5 with erythrocyte basigin and blocking antibodies.

    Science.gov (United States)

    Wright, Katherine E; Hjerrild, Kathryn A; Bartlett, Jonathan; Douglas, Alexander D; Jin, Jing; Brown, Rebecca E; Illingworth, Joseph J; Ashfield, Rebecca; Clemmensen, Stine B; de Jongh, Willem A; Draper, Simon J; Higgins, Matthew K

    2014-11-20

    Invasion of host erythrocytes is essential to the life cycle of Plasmodium parasites and development of the pathology of malaria. The stages of erythrocyte invasion, including initial contact, apical reorientation, junction formation, and active invagination, are directed by coordinated release of specialized apical organelles and their parasite protein contents. Among these proteins, and central to invasion by all species, are two parasite protein families, the reticulocyte-binding protein homologue (RH) and erythrocyte-binding like proteins, which mediate host-parasite interactions. RH5 from Plasmodium falciparum (PfRH5) is the only member of either family demonstrated to be necessary for erythrocyte invasion in all tested strains, through its interaction with the erythrocyte surface protein basigin (also known as CD147 and EMMPRIN). Antibodies targeting PfRH5 or basigin efficiently block parasite invasion in vitro, making PfRH5 an excellent vaccine candidate. Here we present crystal structures of PfRH5 in complex with basigin and two distinct inhibitory antibodies. PfRH5 adopts a novel fold in which two three-helical bundles come together in a kite-like architecture, presenting binding sites for basigin and inhibitory antibodies at one tip. This provides the first structural insight into erythrocyte binding by the Plasmodium RH protein family and identifies novel inhibitory epitopes to guide design of a new generation of vaccines against the blood-stage parasite.

  19. Double-beam cantilever structure with embedded intelligent damping block: Dynamics and control

    Science.gov (United States)

    Szmidt, Tomasz; Pisarski, Dominik; Bajer, Czesław; Dyniewicz, Bartłomiej

    2017-08-01

    In this paper a semi-active method to control the vibrations of twin beams connected at their tips by a smart damping element is investigated. The damping element can be made of a magnetorheological elastomer or a smart material of another type, for instance vacuum packed particles. What is crucial is the ability to modify the storage and loss moduli of the damping block by means of devices attached directly to the vibrating structure. First, a simple dynamical model of the system is proposed. The continuous model is discretized using the Galerkin procedure. Then, a practical state-feedback control law is developed. The control strategy aims at achieving the best instantaneous energy dissipation of the system. Numerical simulations confirm its effectiveness in reducing free vibrations. The proposed control strategy appears to be robust in the sense that its application does not require any knowledge of the initial conditions imposed on the structure, and its performance is better than passive solutions, especially for the system induced in the first mode.

  20. Data acquisition system for charge-division mechanism based on FPGA

    International Nuclear Information System (INIS)

    Yang Litao; Li Dongcang; Yang Lei; Wu Huaiyi; Qi Zhong

    2010-01-01

    Design a system of Peak value acquisition, data processing and data output for 4 channels nuclear signal at the same time by FPGA that base on the basic principle of position information readout for particle through Charger-division Mechanism. In view of the randomness of nuclear signal, so insert asynchronous FIFO in the system, which greatly improve the sampling rate of system. In the article has produced the conjunctive relation and inner circuit structure and give out simulation. From here, you can see the great power of FPGA which used in nuclear data acquisition and processing system. (authors)

  1. Elfin: An algorithm for the computational design of custom three-dimensional structures from modular repeat protein building blocks.

    Science.gov (United States)

    Yeh, Chun-Ting; Brunette, T J; Baker, David; McIntosh-Smith, Simon; Parmeggiani, Fabio

    2018-02-01

    Computational protein design methods have enabled the design of novel protein structures, but they are often still limited to small proteins and symmetric systems. To expand the size of designable proteins while controlling the overall structure, we developed Elfin, a genetic algorithm for the design of novel proteins with custom shapes using structural building blocks derived from experimentally verified repeat proteins. By combining building blocks with compatible interfaces, it is possible to rapidly build non-symmetric large structures (>1000 amino acids) that match three-dimensional geometric descriptions provided by the user. A run time of about 20min on a laptop computer for a 3000 amino acid structure makes Elfin accessible to users with limited computational resources. Protein structures with controlled geometry will allow the systematic study of the effect of spatial arrangement of enzymes and signaling molecules, and provide new scaffolds for functional nanomaterials. Copyright © 2017 Elsevier Inc. All rights reserved.

  2. Burst-Mode Asynchronous Controllers on FPGA

    Directory of Open Access Journals (Sweden)

    Duarte L. Oliveira

    2008-01-01

    Full Text Available FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.

  3. Mechanical behavior analysis of small-scale modeling of ceramic block masonry structures: geometries effect

    Directory of Open Access Journals (Sweden)

    E. Rizzatti

    Full Text Available This paper presents the experimental results of a research program with ceramic block masonry under compression. Four different block geometries were investigated. Two of them had circular hollows with different net area. The third one had two rectangular hollow and the last block was with rectangular hollows and a double central webs. The prisms and walls were built with two mortar type 1:1:6 (I and 1:0,5:4 (II (proportions by volume of cement: lime: sand. One:three small scale blocks were used to test block, prisms and walls on compression. It was possible to conclude that the block with double central webs gave better results of compressive strength showing to be more efficient. The mortar didn't influenced the compressive strength of prisms and walls.

  4. Nanoporous materials from stable and metastable structures of 1,2-PB-b-PDMS block copolymers

    DEFF Research Database (Denmark)

    Schulte, Lars; Grydgaard, Anne; Jakobsen, Mathilde R.

    2011-01-01

    matrix component) and secondly degrading PDMS (the expendable component). Depending on the temperature of the cross-linking reaction different morphologies can be ‘frozen’ from the same block copolymer. Starting with a block copolymer precursor of lamellar morphology at room temperature, the gyroid...... structure or a metastable structure showing hexagonal symmetry (probably HPL) were permanently captured by cross-linking the precursor at 140 °C or at 85 °C, respectively. PDMS was degraded by reaction with tetrabutylamonium fluoride; considerations on the mechanism of cleaving reaction are presented...

  5. Numerical modeling of block structure dynamics: Application to the Vrancea region and study of earthquakes sequences in the synthetic catalogs

    International Nuclear Information System (INIS)

    Soloviev, A.A.; Vorobieva, I.A.

    1995-08-01

    A seismically active region is represented as a system of absolutely rigid blocks divided by infinitely thin plane faults. The interaction of the blocks along the fault planes and with the underlying medium is viscous-elastic. The system of blocks moves as a consequence of prescribed motion of boundary blocks and the underlying medium. When for some part of a fault plane the stress surpasses a certain strength level a stress-drop (''a failure'') occurs. It can cause a failure for other parts of fault planes. The failures are considered as earthquakes. As a result of the numerical simulation a synthetic earthquake catalogue is produced. This procedure is applied for numerical modeling of dynamics of the block structure approximating the tectonic structure of the Vrancea region. By numerical experiments the values of the model parameters were obtained which supplied the synthetic earthquake catalog with the space distribution of epicenters close to the real distribution of the earthquake epicenters in the Vrancea region. The frequency-magnitude relations (Gutenberg-Richter curves) obtained for the synthetic and real catalogs have some common features. The sequences of earthquakes arising in the model are studied for some artificial structures. It is found that ''foreshocks'', ''main shocks'', and ''aftershocks'' could be detected among earthquakes forming the sequences. The features of aftershocks, foreshocks, and catalogs of main shocks are analysed. (author). 5 refs, 12 figs, 16 tabs

  6. FPGA Design and Verification Procedure for Nuclear Power Plant MMIS

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Dongil; Yoo, Kawnwoo; Ryoo, Kwangki [Hanbat National Univ., Daejeon (Korea, Republic of)

    2013-05-15

    In this paper, it is shown that it is possible to ensure reliability by performing the steps of the verification based on the FPGA development methodology, to ensure the safety of application to the NPP MMIS of the FPGA run along the step. Currently, the PLC (Programmable Logic Controller) which is being developed is composed of the FPGA (Field Programmable Gate Array) and CPU (Central Processing Unit). As the importance of the FPGA in the NPP (Nuclear Power Plant) MMIS (Man-Machine Interface System) has been increasing than before, the research on the verification of the FPGA has being more and more concentrated recently.

  7. OrFPGA: An Empirical Performance Tuning Tool for FPGA Designs, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — In this Phase II STTR project, RNET and its subcontractors are proposing to fully develop an empirical performance optimization tool called OrFPGA that efficiently...

  8. FPGA-based multichannel optical concentrator SIMCON 4.0 for TESLA cavities LLRF control system

    Science.gov (United States)

    Perkuszewski, Karol; Pozniak, Krzysztof T.; Jalmuzna, Wojciech; Koprek, Waldemar; Szewinski, Jaroslaw; Romaniuk, Ryszard S.; Simrock, Stefan

    2006-10-01

    The paper presents an idea, design and realization of a gigabit, optoelectronic synchronous massive data concentrator for the LLRF control system for FLASH and XFEL superconducting accelerators and lasers. The design bases on a central, large, programmable FPGA VirtexIIPro circuit by Xilinx and on eight commercial optoelectronic transceivers. There were implemented peripheral devices for embedded PowerPC block like: memory and Ethernet. The SIMCON 4.0 module was realized as a single, standard EURO-6HE board with VXI/VME-bus. Hardware implementation was described for the most important functional blocks. Construction solutions were presented.

  9. FPGA based multichannel optical concentrator SIMCON 4.0 for TESLA cavities LLRF control system

    International Nuclear Information System (INIS)

    Perkuszewski, K.; Pozniak, K.T.; Jalmuzna, W.; Koprek, W.; Szewinski, J.; Romaniuk, R.S.

    2006-01-01

    The paper presents an idea, design and realization of a gigabit, optoelectronic synchronous massive data concentrator for the LLRF control system for FLASH and XFEL superconducting accelerators and lasers. The design bases on a central, large, programmable FPGA VirtexIIPro circuit by Xilinx and on eight commercial optoelectronic transceivers. There were implemented peripheral devices for embedded PowerPC block like: memory and Ethernet. The SIMCON 4.0 module was realized as a single, standard EURO-6HE board with VXI/VME-bus. Hardware implementation was described for the most important functional blocks. Construction solutions were presented. (orig.)

  10. FPGA based multichannel optical concentrator SIMCON 4.0 for TESLA cavities LLRF control system

    Energy Technology Data Exchange (ETDEWEB)

    Perkuszewski, K.; Pozniak, K.T.; Jalmuzna, W.; Koprek, W.; Szewinski, J.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland). Inst. of Electronic Systems; Simrock, S. [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany)

    2006-07-01

    The paper presents an idea, design and realization of a gigabit, optoelectronic synchronous massive data concentrator for the LLRF control system for FLASH and XFEL superconducting accelerators and lasers. The design bases on a central, large, programmable FPGA VirtexIIPro circuit by Xilinx and on eight commercial optoelectronic transceivers. There were implemented peripheral devices for embedded PowerPC block like: memory and Ethernet. The SIMCON 4.0 module was realized as a single, standard EURO-6HE board with VXI/VME-bus. Hardware implementation was described for the most important functional blocks. Construction solutions were presented. (orig.)

  11. Qualification of FPGA-Based Safety-Related PRM System

    International Nuclear Information System (INIS)

    Miyazaki, Tadashi; Oda, Naotaka; Goto, Yasushi; Hayashi, Toshifumi

    2011-01-01

    Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of basic logic circuits, and FPGA performs defined processing which is configured by connecting the basic logic circuit inside the FPGA. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Neutron Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development process to the other safety-related systems such as RPS from now on. Toshiba developed a special design process for NRW-FPGA-based safety-related I and C systems. The design process resolves issues for many years regarding testability of the digital system for nuclear safety application. Thus, Toshiba NRW-FPGA-based safety-related I and C systems has much advantage to be a would standard of the digital systems for nuclear safety application. (author)

  12. Test results of an ITER relevant FPGA when irradiated with neutrons

    Energy Technology Data Exchange (ETDEWEB)

    Batista, Antonio J. N.; Santos, Bruno; Fernandes, Ana; Goncalves, Bruno [Instituto de Plasmas e Fusao Nuclear, Instituto Superior Tecnico, Universidade de Lisboa, 1049-001 Lisboa, (Portugal); Leong, Carlos; Teixeira, Joao P. [Instituto de Engenharia de Sistemas e Computadores - Investigacao e Desenvolvimento, 1000-029 Lisboa, (Portugal); Ramos, Ana Rita; Santos, Joana P.; Marques, Jose G. [Centro de Ciencias e Tecnologias Nucleares, Instituto Superior Tecnico, Universidade de Lisboa, 2695-066 Bobadela, (Portugal)

    2015-07-01

    The data acquisition and control instrumentation cubicles room of the ITER tokamak will be irradiated with neutrons during the fusion reactor operation. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of I and C products - Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), functional data stored in dedicated Block RAM (BRAM) and functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons causes soft errors, unintended changes (bit-flips) to the values stored in state elements of the FPGA. The SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA configuration memory. Novel SEU sensors with Error Correction Code (ECC) detect and repair the BRAM memories. Proper management of SEU can increase reliability and availability of control instrumentation hardware for nuclear applications. The results of the tests performed using the SEM controller and the BRAM SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU errors in the configuration and BRAM memories. (authors)

  13. The analytic structure of conformal blocks and the generalized Wilson-Fisher fixed points

    Energy Technology Data Exchange (ETDEWEB)

    Gliozzi, Ferdinando [Dipartimento di Fisica, Università di Torino andIstituto Nazionale di Fisica Nucleare - sezione di Torino,Via P. Giuria 1, I-10125 Torino (Italy); Guerrieri, Andrea L. [Department of Physics, Faculty of Science, Chulalongkorn University,Thanon Phayathai, Pathumwan, Bangkok 10330 (Thailand); I.N.F.N. Sezione di Roma Tor Vergata,Via della Ricerca Scientifica, I-00133 Roma (Italy); Petkou, Anastasios C. [Institute of Theoretical Physics, Aristotle University of Thessaloniki,54124 Thessaloniki (Greece); Wen, Congkao [Walter Burke Institute for Theoretical Physics, California Institute of Technology,Pasadena, CA 91125 (United States); Mani L. Bhaumik Institute for Theoretical Physics,Department of Physics and Astronomy, UCLA,Los Angeles, CA 90095 (United States)

    2017-04-11

    We describe in detail the method used in our previous work https://arxiv.org/abs/1611.10344 to study the Wilson-Fisher critical points nearby generalized free CFTs, exploiting the analytic structure of conformal blocks as functions of the conformal dimension of the exchanged operator. Our method is equivalent to the mechanism of conformal multiplet recombination set up by null states. We compute, to the first non-trivial order in the ϵ-expansion, the anomalous dimensions and the OPE coefficients of infinite classes of scalar local operators using just CFT data. We study single-scalar and O(N)-invariant theories, as well as theories with multiple deformations. When available we agree with older results, but we also produce a wealth of new ones. Unitarity and crossing symmetry are not used in our approach and we are able to apply our method to non-unitary theories as well. Some implications of our results for the study of the non-unitary theories containing partially conserved higher-spin currents are briefly mentioned.

  14. Finite Macro-Element Mesh Deformation in a Structured Multi-Block Navier-Stokes Code

    Science.gov (United States)

    Bartels, Robert E.

    2005-01-01

    A mesh deformation scheme is developed for a structured multi-block Navier-Stokes code consisting of two steps. The first step is a finite element solution of either user defined or automatically generated macro-elements. Macro-elements are hexagonal finite elements created from a subset of points from the full mesh. When assembled, the finite element system spans the complete flow domain. Macro-element moduli vary according to the distance to the nearest surface, resulting in extremely stiff elements near a moving surface and very pliable elements away from boundaries. Solution of the finite element system for the imposed boundary deflections generally produces smoothly varying nodal deflections. The manner in which distance to the nearest surface has been found to critically influence the quality of the element deformation. The second step is a transfinite interpolation which distributes the macro-element nodal deflections to the remaining fluid mesh points. The scheme is demonstrated for several two-dimensional applications.

  15. Multilayer Stochastic Block Models Reveal the Multilayer Structure of Complex Networks

    Directory of Open Access Journals (Sweden)

    Toni Vallès-Català

    2016-03-01

    Full Text Available In complex systems, the network of interactions we observe between systems components is the aggregate of the interactions that occur through different mechanisms or layers. Recent studies reveal that the existence of multiple interaction layers can have a dramatic impact in the dynamical processes occurring on these systems. However, these studies assume that the interactions between systems components in each one of the layers are known, while typically for real-world systems we do not have that information. Here, we address the issue of uncovering the different interaction layers from aggregate data by introducing multilayer stochastic block models (SBMs, a generalization of single-layer SBMs that considers different mechanisms of layer aggregation. First, we find the complete probabilistic solution to the problem of finding the optimal multilayer SBM for a given aggregate-observed network. Because this solution is computationally intractable, we propose an approximation that enables us to verify that multilayer SBMs are more predictive of network structure in real-world complex systems.

  16. Using high-order methods on adaptively refined block-structured meshes - discretizations, interpolations, and filters.

    Energy Technology Data Exchange (ETDEWEB)

    Ray, Jaideep; Lefantzi, Sophia; Najm, Habib N.; Kennedy, Christopher A.

    2006-01-01

    Block-structured adaptively refined meshes (SAMR) strive for efficient resolution of partial differential equations (PDEs) solved on large computational domains by clustering mesh points only where required by large gradients. Previous work has indicated that fourth-order convergence can be achieved on such meshes by using a suitable combination of high-order discretizations, interpolations, and filters and can deliver significant computational savings over conventional second-order methods at engineering error tolerances. In this paper, we explore the interactions between the errors introduced by discretizations, interpolations and filters. We develop general expressions for high-order discretizations, interpolations, and filters, in multiple dimensions, using a Fourier approach, facilitating the high-order SAMR implementation. We derive a formulation for the necessary interpolation order for given discretization and derivative orders. We also illustrate this order relationship empirically using one and two-dimensional model problems on refined meshes. We study the observed increase in accuracy with increasing interpolation order. We also examine the empirically observed order of convergence, as the effective resolution of the mesh is increased by successively adding levels of refinement, with different orders of discretization, interpolation, or filtering.

  17. FPGA Realization of Memory 10 Viterbi Decoder

    DEFF Research Database (Denmark)

    Paaske, Erik; Bach, Thomas Bo; Andersen, Jakob Dahl

    1997-01-01

    sequence mode when feedback from the Reed-Solomon decoder is available. The Viterbi decoder is realized using two Altera FLEX 10K50 FPGA's. The overall operating speed is 30 kbit/s, and since up to three iterations are performed for each frame and only one decoder is used, the operating speed...

  18. Prototyping Advanced Control Systems on FPGA

    Directory of Open Access Journals (Sweden)

    Simard Stéphane

    2009-01-01

    Full Text Available In advanced digital control and mechatronics, FPGA-based systems on a chip (SoCs promise to supplant older technologies, such as microcontrollers and DSPs. However, the tackling of FPGA technology by control specialists is complicated by the need for skilled hardware/software partitioning and design in order to match the performance requirements of more and more complex algorithms while minimizing cost. Currently, without adequate software support to provide a straightforward design flow, the amount of time and efforts required is prohibitive. In this paper, we discuss our choice, adaptation, and use of a rapid prototyping platform and design flow suitable for the design of on-chip motion controllers and other SoCs with a need for analog interfacing. The platform consists of a customized FPGA design for the Amirix AP1000 PCI FPGA board coupled with a multichannel analog I/O daughter card. The design flow uses Xilinx System Generator in Matlab/Simulink for system design and test, and Xilinx Platform Studio for SoC integration. This approach has been applied to the analysis, design, and hardware implementation of a vector controller for 3-phase AC induction motors. It also has contributed to the development of CMC's MEMS prototyping platform, now used by several Canadian laboratories.

  19. Multidimensional-DSP Beamformers Using the ROACH-2 FPGA Platform

    Directory of Open Access Journals (Sweden)

    Vishwa Seneviratne

    2017-07-01

    Full Text Available Antenna array-based multi-dimensional infinite-impulse response (IIR digital beamformers are employed in a multitude of radio frequency (RF applications ranging from electronically-scanned radar, radio telescopes, long-range detection and target tracking. A method to design 3D IIR beam filters using 2D IIR beam filters is described. A cascaded 2D IIR beam filter architecture is proposed based on systolic array architecture as an alternative for an existing radar application. Differential-form transfer function and polyphase structures are employed in the design to gain an increase in the speed of operation to gigahertz range. The feasibility of practical implementation of a 4-phase polyphase 2D IIR beam filter is explored. A digital hardware prototype is designed, implemented and tested using a ROACH-2 Field Programmable Gate Array (FPGA platform fitted with a Xilinx Virtex-6 SX475T FPGA chip and multi-input analog-to-digital converters (ADC boards set to a maximum sampling rate of 960 MHz. The article describes a method to build a 3D IIR beamformer using polyphase structures. A comparison of technical specifications of an existing radar application based on phased-array and the proposed 3D IIR beamformer is also explained to illustrate the proposed method to be a better alternative for such applications.

  20. Natrium: Use of FPGA embedded processors for real-time data compression

    Energy Technology Data Exchange (ETDEWEB)

    Ammendola, R; Salamon, A; Salina, G [INFN Sezione di Roma Tor Vergata, Rome (Italy); Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P [INFN Sezione di Roma, Rome (Italy)

    2011-12-15

    We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

  1. Natrium: Use of FPGA embedded processors for real-time data compression

    International Nuclear Information System (INIS)

    Ammendola, R; Salamon, A; Salina, G; Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P

    2011-01-01

    We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

  2. Implementation of T-box/T/sup -1/-box based AES design on latest xilinx fpga

    International Nuclear Information System (INIS)

    Kundi, D.E.; Aziz, A.

    2015-01-01

    This work presents an efficient implementation of the AES (Advance Encryption Standard) based on Tbox/T-1-box design for both the encryption and decryption on FPGA (Field Programmable Gate Array). The proposed architecture not only make efficient use of full capacity of dedicated 32 Kb BRAM (Block RAM) of latest Xilinx FPGAs (Virtex-5, Virtex-6 and 7 Series) but also saves considerable amount of BRAM and logical resources by using multiple accesses from single BRAM in one cycle of system clock as compared to conventional LUT (Look-Up-Table) techniques. The proposed T-box/T-1-box based AES design for both the encryption and decryption fits into just 4 BRAMs on FPGA and results in good efficiency TPS (Throughput per Slice) with less power consumption. (author)

  3. Study on FPGA SEU Mitigation for the Readout Electronics of DAMPE BGO Calorimeter in Space

    Science.gov (United States)

    Shen, Zhongtao; Feng, Changqing; Gao, Shanshan; Zhang, Deliang; Jiang, Di; Liu, Shubin; An, Qi

    2015-06-01

    The BGO calorimeter, which provides a wide measurement range of the primary cosmic ray spectrum, is a key sub-detector of the Dark Matter Particle Explorer (DAMPE). The readout electronics of calorimeter consists of 16 pieces of Actel ProASIC Plus FLASH-based field-programmable gate array (FPGA), of which the design-level flip-flops and embedded block random access memories (RAM) are single event upset (SEU) sensitive in the harsh space environment. To comply with radiation hardness assurance (RHA), SEU mitigation methods, including partial triple modular redundancy (TMR), CRC checksum, and multi-domain reset are analyzed and tested by the heavy-ion beam test. Composed of multi-level redundancy, a FPGA design with the characteristics of SEU tolerance and low resource consumption is implemented for the readout electronics.

  4. Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA

    Directory of Open Access Journals (Sweden)

    P. Fiala

    2015-09-01

    Full Text Available This paper is devoted to the proposal of a highly efficient symbol synchronization subsystem for Software Defined Radio. The proposed feedback phase-locked loop timing synchronizer is suitable for parallel implementation on an FPGA. The polyphase FIR filter simultaneously performs matched-filtering and arbitrary interpolation between acquired samples. Determination of the proper sampling instant is achieved by selecting a suitable polyphase filterbank using a derived index. This index is determined based on the output either the Zero-Crossing or Gardner Timing Error Detector. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. This model is composed of a fully parallel polyphase filterbank based on distributed arithmetic, timing error detector and interpolation control block. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented and resource utilization in comparison with a conventional model is analyzed.

  5. Studies on atom transfer radical polymerization of acrylates and styrenes with controlled polymeric block structures

    OpenAIRE

    Ibrahim, Khalid

    2006-01-01

    Atom transfer radical polymerization (ATRP) was applied to homo and block copolymerization of vinyl monomers methacrylates, acrylates, and styrene with iron (FeCl2.4H2O) as the transition metal in most cases. As complexing ligand either a commercially available ligand (triphenyl phosphine) (PPh3) or synthetic aliphatic amines were used. As initiators, methyl 2-bromopropionate, ethyl 2-bromoisobutyrate, α,α-dichloroacetophenone, and poly(ethylene oxide) macroinitiator were employed. Block ...

  6. Use of shock block transmitters in the structural rehabilitation of historical buildings in Calabria and Sicily

    International Nuclear Information System (INIS)

    Bianco, Alessia; Candela, Michele; Fonti, Roberta

    2008-01-01

    Many old and historical masonry buildings, located in the Calabrian and Sicilian areas near the strait of Messina, are affected by typical pattern of cracks, which are not produced by previous earthquakes. These cracks in the masonry walls are characterized by a quasi-vertical trend with constant width. The careful examination of the crack distribution allows to clearly identify the diagnosis: the damage is caused by the sinking due to a horizontal movement of translation of the ground, which is an evident effect of creep phenomena in the soil, so-called 'solifluxion'. This paper, after showing this geological pathology, proposes an innovative strategy of intervention, which consists of the use of 'oleo-dynamic' devices, so-called shock block transmitters, providing different degrees of restraint, according to the loading conditions. In addition, in case of earthquake, an important part of the in-put seismic energy can be dissipated. The strategy of application of this system to the building consists of the subdivision of each masonry wall in two different parts, which are physically separated by the cracks. Each wall portion must be consolidated separately and the different parts of walls behave as statically independent each other, so that they can move independently during the serviceability conditions. The connection among the walls composing the whole structural organism is given by metal tie-rods equipped with 'oleo dynamic' devices, which allows, in a given range, the horizontal sliding in case of slow movement due to the phenomenon of 'solifluxion'. Contrary, in case of dynamic and fast movements, such as the ones produced by an earthquake, each 'oleo dynamic' device provides a fully restraint effect and, as a consequence, the tie-rods behave in the classical way

  7. Nerve Blocks

    Science.gov (United States)

    ... News Physician Resources Professions Site Index A-Z Nerve Blocks A nerve block is an injection to ... the limitations of Nerve Block? What is a Nerve Block? A nerve block is an anesthetic and/ ...

  8. Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation

    Directory of Open Access Journals (Sweden)

    Srilata Raman

    1996-01-01

    Full Text Available In this paper we present a simple but efficient timing-driven placement algorithm for FPGAs. The algorithm computes forces acting on a logic block in the FPGA to determine its relative location with respect to other blocks. The forces depend on the criticality of nets shared between the two blocks. Unlike other net-based approaches, timing constraints are incorporated directly into the force equations to guide the placement. Slot assignment is then used to move the blocks into valid slot locations on the FPGA chip. The assignment algorithm also makes use of the delay information of nets so that the final placement is able to meet the timing criteria specified for the circuit. The novelty of the approach lies in the formulation of the force equations and the manner in which weights of the nets are dynamically altered to influence the placement. Experiments conducted on industrial test circuits and MCNC circuits give very promising results and indicate that the algorithm succeeds in significantly reducing the maximum delay in the circuit. In addition, routability is not adversely affected and running time is low.

  9. An FPGA-based torus communication network

    Energy Technology Data Exchange (ETDEWEB)

    Pivanti, Marcello; Schifano, Sebastiano Fabio [INFN, Ferrara (Italy); Ferrara Univ. (Italy); Simma, Hubert [DESY, Zeuthen (Germany). John von Neumann-Institut fuer Computing NIC

    2011-02-15

    We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results. (orig.)

  10. Moessbauer spectrometric data acquisition based on FPGA

    International Nuclear Information System (INIS)

    Zhang Yuan; Li Shimin; Chen Nan; Zhu Jingbo; Xia Yuanfu

    2008-01-01

    FPGA(Field Programmable Gate Array) is a programmable device with strong logical function and timing control ability. It is extremely potent in acquiring and processing timing signals. By replacing the traditional used SCM (Single-Chip Microcomputer) with FPGA, counting speed of Moessbauer spectrometric data acquisition can be improved markedly with significantly decreased size of the spectrometer. The counter, RAM and RS-232 communication of the module are developed on Altera Cyclone series chip EP1C6T144C8 with Quartus II. EP1C6T144C8 has 5980 logical units accompanied by 92160 bits of memory space. It is so powerful that all needs in data acquisition of the Moessbauer spectrometer can be perfectly satisfied while allowing modifications in functions and parameters. (authors)

  11. An Improved Rotary Interpolation Based on FPGA

    Directory of Open Access Journals (Sweden)

    Mingyu Gao

    2014-08-01

    Full Text Available This paper presents an improved rotary interpolation algorithm, which consists of a standard curve interpolation module and a rotary process module. Compared to the conventional rotary interpolation algorithms, the proposed rotary interpolation algorithm is simpler and more efficient. The proposed algorithm was realized on a FPGA with Verilog HDL language, and simulated by the ModelSim software, and finally verified on a two-axis CNC lathe, which uses rotary ellipse and rotary parabolic as an example. According to the theoretical analysis and practical process validation, the algorithm has the following advantages: firstly, less arithmetic items is conducive for interpolation operation; and secondly the computing time is only two clock cycles of the FPGA. Simulations and actual tests have proved that the high accuracy and efficiency of the algorithm, which shows that it is highly suited for real-time applications.

  12. An FPGA-based torus communication network

    International Nuclear Information System (INIS)

    Pivanti, Marcello; Schifano, Sebastiano Fabio; Simma, Hubert

    2011-02-01

    We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results. (orig.)

  13. An FPGA-Based Electronic Cochlea

    Directory of Open Access Journals (Sweden)

    M. P. Leong

    2003-06-01

    Full Text Available A module generator which can produce an FPGA-based implementation of an electronic cochlea filter with arbitrary precision is presented. Although hardware implementations of electronic cochlea models have traditionally used analog VLSI as the implementation medium due to their small area, high speed, and low power consumption, FPGA-based implementations offer shorter design times, improved dynamic range, higher accuracy, and a simpler computer interface. The tool presented takes filter coefficients as input and produces a synthesizable VHDL description of an application-optimized design as output. Furthermore, the tool can use simulation test vectors in order to determine the appropriate scaling of the fixed point precision parameters for each filter. The resulting model can be used as an accelerator for research in audition or as the front-end for embedded auditory signal processing systems. The application of this module generator to a real-time cochleagram display is also presented.

  14. Guide to FPGA Implementation of Arithmetic Functions

    CERN Document Server

    Deschamps, Jean-Pierre; Cantó, Enrique

    2012-01-01

    This book is designed both for FPGA users interested in developing new, specific components - generally for reducing execution times –and IP core designers interested in extending their catalog of specific components.  The main focus is circuit synthesis and the discussion shows, for example, how a given algorithm executing some complex function can be translated to a synthesizable circuit description, as well as which are the best choices the designer can make to reduce the circuit cost, latency, or power consumption.  This is not a book on algorithms.  It is a book that shows how to translate efficiently an algorithm to a circuit, using techniques such as parallelism, pipeline, loop unrolling, and others.  Numerous examples of FPGA implementation are described throughout this book and the circuits are modeled in VHDL. Complete and synthesizable source files are available for download.

  15. FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION

    Directory of Open Access Journals (Sweden)

    B. Lakshmi

    2010-09-01

    Full Text Available In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be entered at right time and hence, vulnerability of encryption through brute force attack is eliminated. Presently available encryption systems, suffer from Brute force attack and in such a case, the time taken for breaking a code depends on the system used for cryptanalysis. The proposed scheme provides an effective method in which the time is taken as the second dimension of the key so that the same system can defend against brute force attack more vigorously. In the proposed scheme, the key is rotated continuously and four bits are drawn from the key with their concatenated value representing the delay the system has to wait. This forms the time based key concept. Also the key based function selection from a pool of functions enhances the confusion and diffusion to defend against linear and differential attacks while the time factor inclusion makes the brute force attack nearly impossible. In the proposed scheme, the key scheduler is implemented on FPGA that generates the right key at right time intervals which is then connected to a NIOS – II processor (a virtual microcontroller which is brought out from Altera FPGA that communicates with the keys to the personal computer through JTAG (Joint Test Action Group communication and the computer is used to perform encryption (or decryption. In this case the FPGA serves as hardware key (dongle for data encryption (or decryption.

  16. FPGA Flash Memory High Speed Data Acquisition

    Science.gov (United States)

    Gonzalez, April

    2013-01-01

    The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

  17. Signal compression in radar using FPGA

    OpenAIRE

    Escamilla Hemández, Enrique; Kravchenko, Víctor; Ponomaryov, Volodymyr; Duchen Sánchez, Gonzalo; Hernández Sánchez, David

    2010-01-01

    We present the hardware implementation of radar real time processing procedures using a simple, fast technique based on FPGA (Field Programmable Gate Array) architecture. This processing includes different window procedures during pulse compression in synthetic aperture radar (SAR). The radar signal compression processing is realized using matched filter, and classical and novel window functions, where we focus on better solution for minimum values of sidelobes. The proposed architecture expl...

  18. FPGA Implementation of Computer Vision Algorithm

    OpenAIRE

    Zhou, Zhonghua

    2014-01-01

    Computer vision algorithms, which play an significant role in vision processing, is widely applied in many aspects such as geology survey, traffic management and medical care, etc.. Most of the situations require the process to be real-timed, in other words, as fast as possible. Field Programmable Gate Arrays (FPGAs) have a advantage of parallelism fabric in programming, comparing to the serial communications of CPUs, which makes FPGA a perfect platform for implementing vision algorithms. The...

  19. Remote monitoring and fault recovery for FPGA-based field controllers of telescope and instruments

    Science.gov (United States)

    Zhu, Yuhua; Zhu, Dan; Wang, Jianing

    2012-09-01

    As the increasing size and more and more functions, modern telescopes have widely used the control architecture, i.e. central control unit plus field controller. FPGA-based field controller has the advantages of field programmable, which provide a great convenience for modifying software and hardware of control system. It also gives a good platform for implementation of the new control scheme. Because of multi-controlled nodes and poor working environment in scattered locations, reliability and stability of the field controller should be fully concerned. This paper mainly describes how we use the FPGA-based field controller and Ethernet remote to construct monitoring system with multi-nodes. When failure appearing, the new FPGA chip does self-recovery first in accordance with prerecovery strategies. In case of accident, remote reconstruction for the field controller can be done through network intervention if the chip is not being restored. This paper also introduces the network remote reconstruction solutions of controller, the system structure and transport protocol as well as the implementation methods. The idea of hardware and software design is given based on the FPGA. After actual operation on the large telescopes, desired results have been achieved. The improvement increases system reliability and reduces workload of maintenance, showing good application and popularization.

  20. An FPGA-Based Multiple-Axis Velocity Controller and Stepping Motors Drives Design

    Directory of Open Access Journals (Sweden)

    Lai Chiu-Keng

    2016-01-01

    Full Text Available A Field Programmable Gate Array based system is a great hardware platform to support the implementation of hardware controllers such as PID controller and fuzzy controller. It is also programmed as hardware accelerator to speed up the mathematic calculation and greatly enhance the performance as applied to motor drive and motion control. Furthermore, the open structure of FPGA-based system is suitable for those designs with the ability of parallel processing or soft code processor embedded. In this paper, we apply the FPGA to a multi-axis velocity controller design. The developed system integrated three functions inside the FPGA chip, which are respectively the stepping motor drive, the multi-axis motion controller and the motion planning. Furthermore, an embedded controller with a soft code processor compatible to 8051 micro-control unit (MCU is built to handle the data transfer between the FPGA board and host PC. The MCU is also used to initialize the motion control and run the interpolator. The designed system is practically applied to a XYZ motion platform which is driven by stepping motors to verify its performance.

  1. FPGA remote update for nuclear environments

    Energy Technology Data Exchange (ETDEWEB)

    Fernandes, Ana; Pereira, Rita C.; Sousa, Jorge; Carvalho, Paulo F.; Correia, Miguel; Rodrigues, Antonio P.; Carvalho, Bernardo B.; Goncalves, Bruno [Instituto de Plasmasbe Fusao Nuclear, Instituto Superior Tecnico, Universidade de Lisboa, 1049-001 Lisboa, (Portugal); Correia, Carlos M.B.A. [Centro de Instrumentacao, Dept. de Fisica, Universidade de Coimbra, 3004-516 Coimbra, (Portugal)

    2015-07-01

    The Instituto de Plasmas e Fusao Nuclear (IPFN) has developed dedicated re-configurable modules based on field programmable gate array (FPGA) devices for several nuclear fusion machines worldwide. Moreover, new Advanced Telecommunication Computing Architecture (ATCA) based modules developed by IPFN are already included in the ITER catalogue. One of the requirements for re-configurable modules operating in future nuclear environments including ITER is the remote update capability. Accordingly, this work presents an alternative method for FPGA remote programing to be implemented in new ATCA based re-configurable modules. FPGAs are volatile devices and their programming code is usually stored in dedicated flash memories for properly configuration during module power-on. The presented method is capable to store new FPGA codes in Serial Peripheral Interface (SPI) flash memories using the PCIexpress (PCIe) network established on the ATCA back-plane, linking data acquisition endpoints and the data switch blades. The method is based on the Xilinx Quick Boot application note, adapted to PCIe protocol and ATCA based modules. (authors)

  2. FPGA communications based on Gigabit Ethernet

    International Nuclear Information System (INIS)

    Doolittle, L.R.; Serrano, C.

    2012-01-01

    The use of Field Programmable Gate Arrays (FPGAs) in accelerators is widespread due to their flexibility, performance, and reasonable costs. Whether they are used for fast feedback systems, data acquisition, fast communications using custom protocols, or any other application, there is a need for the end-user and the global control software to access FPGA features using a commodity computer. The choice of communication standards that can be used to interface to a FPGA board is wide, however there is one that stands out for its maturity, basis in standards, performance, and hardware support: Gigabit Ethernet. In the context of accelerators it is desirable to have highly reliable, portable, and flexible solutions. We have therefore developed a chip and board-independent FPGA design which implements the Gigabit Ethernet (GbE) standard. Our design has been configured for use with multiple projects, supports full line-rate traffic, and communicates with any other device implementing the same well-established protocol, easily supported by any modern workstation or controls computer. (authors)

  3. Comparative evaluation of structural integrity for ITER blanket shield block based on SDC-IC and ASME code

    Energy Technology Data Exchange (ETDEWEB)

    Shim, Hee-Jin [ITER Korea, National Fusion Research Institute, 169-148 Gwahak-Ro, Yuseong-Gu, Daejeon (Korea, Republic of); Ha, Min-Su, E-mail: msha12@nfri.re.kr [ITER Korea, National Fusion Research Institute, 169-148 Gwahak-Ro, Yuseong-Gu, Daejeon (Korea, Republic of); Kim, Sa-Woong; Jung, Hun-Chea [ITER Korea, National Fusion Research Institute, 169-148 Gwahak-Ro, Yuseong-Gu, Daejeon (Korea, Republic of); Kim, Duck-Hoi [ITER Organization, Route de Vinon sur Verdon - CS 90046, 13067 Sant Paul Lez Durance (France)

    2016-11-01

    Highlights: • The procedure of structural integrity and fatigue assessment was described. • Case studies were performed according to both SDC-IC and ASME Sec. • III codes The conservatism of the ASME code was demonstrated. • The study only covers the specifically comparable case about fatigue usage factor. - Abstract: The ITER blanket Shield Block is a bulk structure to absorb radiation and to provide thermal shielding to vacuum vessel and external vessel components, therefore the most significant load for Shield Block is the thermal load. In the previous study, the thermo-mechanical analysis has been performed under the inductive operation as representative loading condition. And the fatigue evaluations were conducted to assure structural integrity for Shield Block according to Structural Design Criteria for In-vessel Components (SDC-IC) which provided by ITER Organization (IO) based on the code of RCC-MR. Generally, ASME code (especially, B&PV Sec. III) is widely applied for design of nuclear components, and is usually well known as more conservative than other specific codes. For the view point of the fatigue assessment, ASME code is very conservative compared with SDC-IC in terms of the reflected K{sub e} factor, design fatigue curve and other factors. Therefore, an accurate fatigue assessment comparison is needed to measure of conservatism. The purpose of this study is to provide the fatigue usage comparison resulting from the specified operating conditions shall be evaluated for Shield Block based on both SDC-IC and ASME code, and to discuss the conservatism of the results.

  4. Comparative evaluation of structural integrity for ITER blanket shield block based on SDC-IC and ASME code

    International Nuclear Information System (INIS)

    Shim, Hee-Jin; Ha, Min-Su; Kim, Sa-Woong; Jung, Hun-Chea; Kim, Duck-Hoi

    2016-01-01

    Highlights: • The procedure of structural integrity and fatigue assessment was described. • Case studies were performed according to both SDC-IC and ASME Sec. • III codes The conservatism of the ASME code was demonstrated. • The study only covers the specifically comparable case about fatigue usage factor. - Abstract: The ITER blanket Shield Block is a bulk structure to absorb radiation and to provide thermal shielding to vacuum vessel and external vessel components, therefore the most significant load for Shield Block is the thermal load. In the previous study, the thermo-mechanical analysis has been performed under the inductive operation as representative loading condition. And the fatigue evaluations were conducted to assure structural integrity for Shield Block according to Structural Design Criteria for In-vessel Components (SDC-IC) which provided by ITER Organization (IO) based on the code of RCC-MR. Generally, ASME code (especially, B&PV Sec. III) is widely applied for design of nuclear components, and is usually well known as more conservative than other specific codes. For the view point of the fatigue assessment, ASME code is very conservative compared with SDC-IC in terms of the reflected K_e factor, design fatigue curve and other factors. Therefore, an accurate fatigue assessment comparison is needed to measure of conservatism. The purpose of this study is to provide the fatigue usage comparison resulting from the specified operating conditions shall be evaluated for Shield Block based on both SDC-IC and ASME code, and to discuss the conservatism of the results.

  5. Self-assembly of POSS-containing block copolymers: fixing the hierarchical structure in networks

    Czech Academy of Sciences Publication Activity Database

    Matějka, Libor; Janata, Miroslav; Pleštil, Josef; Zhigunov, Alexander; Šlouf, Miroslav

    2014-01-01

    Roč. 55, č. 1 (2014), s. 126-136 ISSN 0032-3861 R&D Projects: GA ČR GAP108/12/1459 Grant - others:AV ČR(CZ) M200500903 Institutional support: RVO:61389013 Keywords : block copolymers * self-assembly * POSS Subject RIV: CD - Macromolecular Chemistry Impact factor: 3.562, year: 2014

  6. Functional porous structures based on the pyrolysis of cured templates of block copolymer and phenolic resin

    NARCIS (Netherlands)

    Kosonen, H; Valkama, S; Nykanen, A; Toivanen, M; ten Brinke, G; Ruokolainen, J; Ikkala, O; Nykänen, Antti

    2006-01-01

    Porous materials with controlled pore size and large surface area (see Figure) have been prepared by crosslinking phenolic resin in the presence of a self-assembled block-copolymer template, followed by pyrolysis. Many phenolic hydroxyl groups remain at the matrix and pore walls, which can be used

  7. Structural analysis of superposed fault systems of the Bornholm horst block, Tornquist Zone, Denmark

    DEFF Research Database (Denmark)

    Graversen, Ole

    2009-01-01

    The Bornholm horst block is composed of Precambrian crystalline basement overlain by Palaeozoicand Mesozoic cover rocks. The cover intervals are separated by an angular unconformity and a hiatus spanning the Devonian through Middle Triassic interval. Late Palaeozoic faulting of the Early Palaeozo...

  8. The structure of P85 pluronic block copolymer micelles determined by small-angle neutron scattering

    DEFF Research Database (Denmark)

    Pedersen, J.S.; Gerstenberg, M.C.

    2003-01-01

    a spherical core of poly(propylene oxide) (PPO) with some water surrounded by a corona of the poly(ethylene oxide) (PEO) block. The latter are non-interacting and obey Gaussian statistics, but are expelled from the core region. The analysis shows that the micelles are fairly concentration and temperature...

  9. Block Copolymer Modified Epoxy Amine System for Reactive Rotational Molding: Structures, Properties and Processability

    Science.gov (United States)

    Lecocq, Eva; Nony, Fabien; Tcharkhtchi, Abbas; Gérard, Jean-François

    2011-05-01

    Poly(styrene-butadiene-methylmethacrylate) (SBM) and poly(methylmethacrylate-butyle-acrylate-methylmethacrylate) (MAM) triblock copolymers have been dissolved in liquid DGEBA epoxy resin which is subsequently polymerized by meta-xylene diamine (MXDA) or Jeffamine EDR-148. A chemorheology study of these formulations by plate-plate rheology and by thermal analysis has allowed to conclude that the addition of these copolymer blocks improve the reactive rotational moulding processability without affecting the processing time. Indeed, it prevents the pooling of the formulation at the bottom of the mould and a too rapid build up of resin viscosity of these thermosetting systems. The morphology of the cured blends examined by scanning electron microscopy (SEM) shows an increase of fracture surface area and thereby a potential increase of the toughness with the modification of epoxy system. Dynamic mechanical spectroscopy (DMA) and opalescence of final material show that the block PMMA, initially miscible, is likely to induce phase separation from the epoxy-amine matrix. Thereby, the poor compatibilisation between the toughener and the matrix has a detrimental effect on the tensile mechanical properties. The compatibilisation has to be increased to improve in synergy the processability and the final properties of these block copolymer modified formulations. First attempts could be by adapting the length and ratio of each block.

  10. An FPGA-Based Massively Parallel Neuromorphic Cortex Simulator

    Directory of Open Access Journals (Sweden)

    Runchun M. Wang

    2018-04-01

    Full Text Available This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as complex models of various areas of the cortex. The main novelty of this work is the abstraction of a neuromorphic architecture into clusters represented by minicolumns and hypercolumns, analogously to the fundamental structural units observed in neurobiology. Without this approach, simulating large-scale fully connected networks needs prohibitively large memory to store look-up tables for point-to-point connections. Instead, we use a novel architecture, based on the structural connectivity in the neocortex, such that all the required parameters and connections can be stored in on-chip memory. The cortex simulator can be easily reconfigured for simulating different neural networks without any change in hardware structure by programming the memory. A hierarchical communication scheme allows one neuron to have a fan-out of up to 200 k neurons. As a proof-of-concept, an implementation on one Altera Stratix V FPGA was able to simulate 20 million to 2.6 billion leaky-integrate-and-fire (LIF neurons in real time. We verified the system by emulating a simplified auditory cortex (with 100 million neurons. This cortex simulator achieved a low power dissipation of 1.62 μW per neuron. With the advent of commercially available FPGA boards, our system offers an accessible and scalable tool for the design, real-time simulation, and analysis of large-scale spiking neural networks.

  11. Studies and mechanical properties of a new type of 'hybrid' ceramic block for buildings in structural masonry

    International Nuclear Information System (INIS)

    Camara, Cassio Freire; Gomes, Uilame Umbelino

    2012-01-01

    This paper presents the development of a hybrid ceramic block to the use of resides in the buildings executed with structural masonry. This work seeking new materials and / or products with the purpose of increasing the compressive strength of the ceramic blocks, without neglecting other properties (water absorption and linear shrinkage). After the obtained material (clay powder and crushed), the packaging (in percentages ranging from 0%, 5%, 10% and 15% substitution of crushed clay powder), the identification and measuring (weights and lengths) of the bodies of the test piece, was performed on the approach characterized by fluorescence, mineralogy and SEM of these materials as well as the characterization (SEM) of ceramic blocks after the sintering (temperature of the 900 deg C, 1000 deg C, and 1100 deg C rate with heating tax of 5 o C/minute and soak for 1 hour). Then the samples were subjected to the tests (compressive strength and water absorption) and the respective calculated linear shrinkage. After conducting the analysis of the results of these tests (according to the criteria and parameters required by the ABNT NBR 15270) was found that the 'hybrid' block with the addition of 10% crushed powder obtained the best results, increasing the compressive strength at 16 % without compromising the other parameters required by the Standard. (author)

  12. Structural and Mechanical Hysteresis at the Order-Order Transition of Block Copolymer Micellar Crystals

    Directory of Open Access Journals (Sweden)

    Theresa A. LaFollette

    2011-01-01

    Full Text Available Concentrated solutions of a water-soluble block copolymer (PEO20-(PPO70-(PEO20 show a thermoreversible transition from a liquid to a gel. Over a range of concentration there also exists an order-order transition (OOT between cubically-packed spherical micelles and hexagonally-packed cylindrical micelles. This OOT displays a hysteresis between the heating and cooling transitions that is observed at both the macroscale through rheology and nanoscale through small angle neutron scattering (SANS. The hysteresis is caused by the persistence of the cubically-packed spherical micelle phase into the hexagonally-packed cylindrical micelle phase likely due to the hindered realignment of the spherical micelles into cylindrical micelles and then packing of the cylindrical micelles into a hexagonally-packed cylindrical micelle phase. This type of hysteresis must be fully characterized, and possibly avoided, for these block copolymer systems to be used as templates in nanocomposites.

  13. Stabilized and Block Approximate Inverse Preconditioners for Problems in Solid and Structural Mechanics

    Czech Academy of Sciences Publication Activity Database

    Benzi, M.; Kouhia, R.; Tůma, Miroslav

    2001-01-01

    Roč. 190, - (2001), s. 6533-6554 ISSN 0045-7825 R&D Projects: GA AV ČR IAA2030801; GA ČR GA201/00/0080 Institutional research plan: AV0Z1030915 Keywords : preconditioning * conjugate gradient * factorized sparse approximate inverse * block algorithms * finite elements * shells Subject RIV: BA - General Mathematics Impact factor: 0.913, year: 2001

  14. Embedded algorithms within an FPGA-based system to process nonlinear time series data

    Science.gov (United States)

    Jones, Jonathan D.; Pei, Jin-Song; Tull, Monte P.

    2008-03-01

    This paper presents some preliminary results of an ongoing project. A pattern classification algorithm is being developed and embedded into a Field-Programmable Gate Array (FPGA) and microprocessor-based data processing core in this project. The goal is to enable and optimize the functionality of onboard data processing of nonlinear, nonstationary data for smart wireless sensing in structural health monitoring. Compared with traditional microprocessor-based systems, fast growing FPGA technology offers a more powerful, efficient, and flexible hardware platform including on-site (field-programmable) reconfiguration capability of hardware. An existing nonlinear identification algorithm is used as the baseline in this study. The implementation within a hardware-based system is presented in this paper, detailing the design requirements, validation, tradeoffs, optimization, and challenges in embedding this algorithm. An off-the-shelf high-level abstraction tool along with the Matlab/Simulink environment is utilized to program the FPGA, rather than coding the hardware description language (HDL) manually. The implementation is validated by comparing the simulation results with those from Matlab. In particular, the Hilbert Transform is embedded into the FPGA hardware and applied to the baseline algorithm as the centerpiece in processing nonlinear time histories and extracting instantaneous features of nonstationary dynamic data. The selection of proper numerical methods for the hardware execution of the selected identification algorithm and consideration of the fixed-point representation are elaborated. Other challenges include the issues of the timing in the hardware execution cycle of the design, resource consumption, approximation accuracy, and user flexibility of input data types limited by the simplicity of this preliminary design. Future work includes making an FPGA and microprocessor operate together to embed a further developed algorithm that yields better

  15. Combining a popularity-productivity stochastic block model with a discriminative-content model for general structure detection.

    Science.gov (United States)

    Chai, Bian-fang; Yu, Jian; Jia, Cai-Yan; Yang, Tian-bao; Jiang, Ya-wen

    2013-07-01

    Latent community discovery that combines links and contents of a text-associated network has drawn more attention with the advance of social media. Most of the previous studies aim at detecting densely connected communities and are not able to identify general structures, e.g., bipartite structure. Several variants based on the stochastic block model are more flexible for exploring general structures by introducing link probabilities between communities. However, these variants cannot identify the degree distributions of real networks due to a lack of modeling of the differences among nodes, and they are not suitable for discovering communities in text-associated networks because they ignore the contents of nodes. In this paper, we propose a popularity-productivity stochastic block (PPSB) model by introducing two random variables, popularity and productivity, to model the differences among nodes in receiving links and producing links, respectively. This model has the flexibility of existing stochastic block models in discovering general community structures and inherits the richness of previous models that also exploit popularity and productivity in modeling the real scale-free networks with power law degree distributions. To incorporate the contents in text-associated networks, we propose a combined model which combines the PPSB model with a discriminative model that models the community memberships of nodes by their contents. We then develop expectation-maximization (EM) algorithms to infer the parameters in the two models. Experiments on synthetic and real networks have demonstrated that the proposed models can yield better performances than previous models, especially on networks with general structures.

  16. Fast FPGA Implementation of an Original Impedance Analyser

    Directory of Open Access Journals (Sweden)

    Abdulrahman HAMED

    2011-02-01

    Full Text Available This article describes in detail the design and rapid prototyping of an embedded impedance analyzer. The measurement principle is based on the feedback control of the excitation voltage VD during a fast frequency sweeping. This function is carried out by a high precision synthesizer whose output resistance RG is digitally adjustable. Real and imaginary parts of the dipole impedance are determined from RG and the phase of VD. The digital architecture design uses the hardware-in-the-loop simulation in which the dipole is modeled using an RLC parallel circuit and a Butterworth Van Dyke structure. All digital functions are implemented on a Stratix II FPGA board with a 100 MHz frequency clock. The parameters taken into account are the frequency range (0 to 5 MHz, speed and resolution of the analysis and the quality factor of the resonant dipole. To reduce the analysis duration, the frequency sweeping rate is adjusted in real time.

  17. Validation of a Real-time AVS Encoder on FPGA

    Directory of Open Access Journals (Sweden)

    Qun Fang Yuan

    2014-01-01

    Full Text Available A whole I frame AVS real-time video encoder is designed and implemented on FPGA platform in this paper. The system uses the structure of the flow calculation, coupled with a dual-port RAM memory between/among the various functional modules. Reusable design and pipeline design are used to optimize various encoding module and to ensure the efficient operation of the pipeline. Through the simulation of ISE software and the verification of Xilinx Vritex-4 pro platform, it can be seen that the highest working frequency can be up to 110 MHz, meeting the requirements of the whole I frame real- time encoding of AVS in CIF resolution.

  18. Implementation of a pulse coupled neural network in FPGA.

    Science.gov (United States)

    Waldemark, J; Millberg, M; Lindblad, T; Waldemark, K; Becanovic, V

    2000-06-01

    The Pulse Coupled neural network, PCNN, is a biologically inspired neural net and it can be used in various image analysis applications, e.g. time-critical applications in the field of image pre-processing like segmentation, filtering, etc. a VHDL implementation of the PCNN targeting FPGA was undertaken and the results presented here. The implementation contains many interesting features. By pipelining the PCNN structure a very high throughput of 55 million neuron iterations per second could be achieved. By making the coefficients re-configurable during operation, a complete recognition system could be implemented on one, or maybe two, chip(s). Reconsidering the ranges and resolutions of the constants may save a lot of hardware, since the higher resolution requires larger multipliers, adders, memories etc.

  19. Method to implement the CCD timing generator based on FPGA

    Science.gov (United States)

    Li, Binhua; Song, Qian; He, Chun; Jin, Jianhui; He, Lin

    2010-07-01

    With the advance of the PFPA technology, the design methodology of digital systems is changing. In recent years we develop a method to implement the CCD timing generator based on FPGA and VHDL. This paper presents the principles and implementation skills of the method. Taking a developed camera as an example, we introduce the structure, input and output clocks/signals of a timing generator implemented in the camera. The generator is composed of a top module and a bottom module. The bottom one is made up of 4 sub-modules which correspond to 4 different operation modes. The modules are implemented by 5 VHDL programs. Frame charts of the architecture of these programs are shown in the paper. We also describe implementation steps of the timing generator in Quartus II, and the interconnections between the generator and a Nios soft core processor which is the controller of this generator. Some test results are presented in the end.

  20. Heat flow, heat generation and crustal thermal structure of the northern block of the South Indian Craton

    Science.gov (United States)

    Gupta, Mohan L.; Sharma, S. R.; Sundar, A.

    Heat flow values and heat generation data calculated from the concentration of heat producing radioactive elements, U, Th and K in surface rocks were analyzed. The South Indian Craton according to Drury et al., can be divided into various blocks, separated by late Proterozoic shear belts. The northern block comprises Eastern and Western Dharwar Cratons of Rogers (1986), Naqvi and Rogers (1987) and a part of the South Indian granulite terrain up to a shear system occupying the Palghat-Cauvery low lands. The geothermal data analysis clearly demonstrates that the present thermal characteristics of the above two Archaean terrains of the Indian and Australian Shields are quite similar. Their crustal thermal structures are likely to be similar also.

  1. Heat flow, heat generation and crustal thermal structure of the northern block of the South Indian Craton

    Science.gov (United States)

    Gupta, Mohan L.; Sharma, S. R.; Sundar, A.

    1988-01-01

    Heat flow values and heat generation data calculated from the concentration of heat producing radioactive elements, U, Th and K in surface rocks were analyzed. The South Indian Craton according to Drury et al., can be divided into various blocks, separated by late Proterozoic shear belts. The northern block comprises Eastern and Western Dharwar Cratons of Rogers (1986), Naqvi and Rogers (1987) and a part of the South Indian granulite terrain up to a shear system occupying the Palghat-Cauvery low lands. The geothermal data analysis clearly demonstrates that the present thermal characteristics of the above two Archaean terrains of the Indian and Australian Shields are quite similar. Their crustal thermal structures are likely to be similar also.

  2. FPGA based Control of a Production Cell System

    NARCIS (Netherlands)

    Groothuis, M.A.; van Zuijlen, Jasper J.P.; Broenink, Johannes F.

    Most motion control systems for mechatronic systems are implemented on digital computers. In this paper we present an FPGA based solution implemented on a low cost Xilinx Spartan III FPGA. A Production Cell setup with multiple parallel operating units is chosen as a test case. The embedded control

  3. Automatic generation of application specific FPGA multicore accelerators

    DEFF Research Database (Denmark)

    Hindborg, Andreas Erik; Schleuniger, Pascal; Jensen, Nicklas Bo

    2014-01-01

    High performance computing systems make increasing use of hardware accelerators to improve performance and power properties. For large high-performance FPGAs to be successfully integrated in such computing systems, methods to raise the abstraction level of FPGA programming are required...... to identify optimal performance energy trade-offs points for a multicore based FPGA accelerator....

  4. FPGA Acceleration by Dynamically-Loaded Hardware Libraries

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Nannarelli, Alberto; Re, Marco

    -the-y the speciffic processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. Results show that significant speed-up and energy efficiency can be obtained by HLL acceleration on system-on-chips where reconfigurable fabric is placed next to the CPUs....

  5. Elucidation of the Structure Formation of Polymer-Conjugated Proteins in Solution and Block Copolymer Templates

    Science.gov (United States)

    Ferebee, Rachel L.

    The broader technical objective of this work is to contribute to the development of enzyme-functionalized nanoporous membranes that can function as autonomous and target selective dynamic separators. The scientific objective of the research performed within this thesis is to elucidate the parameters that control the mixing of proteins in organic host materials and in block copolymers templates in particular. A "biomimetic" membrane system that uses enzymes to selectively neutralize targets and trigger a change in permeability of nanopores lined with a pH-responsive polymer has been fabricated and characterized. Mechanical and functional stability, as well as scalability, have been demonstrated for this system. Additional research has focused on the role of polymeric ligands on the solubility characteristics of the model protein, Bovine Serum Albumin (BSA). For this purpose BSA was conjugated with poly(ethylene glycol) (PEG) ligands of varied degree of polymerization and grafting density. Combined static and dynamic light scattering was used (in conjunction with MALDI-TOF) to determine the second virial coefficient in PBS solutions. At a given mass fraction PEG or average number of grafts, the solubility of BSA-PEG conjugates is found to increase with the degree of polymerization of conjugated PEG. This result informs the synthesis of protein-conjugate systems that are optimized for the fabrication of block copolymer blend materials with maximum protein loading. Blends of BSA-PEG conjugates and block copolymer (BCP) matrices were fabricated to evaluate the dispersion morphology and solubility limits in a model system. Electron microscopy was used to evaluate the changes in lamellar spacing with increased filling fraction of BSA-PEG conjugates.

  6. Self-Assembled Structures of PMAA-PMMA Block Copolymers : Synthesis, Characterization, and Self-Consistent Field Computations

    NARCIS (Netherlands)

    Li, Feng; Schellekens, Mike; de Bont, Jens; Peters, Ron; Overbeek, Ad; Leermakers, Frans A. M.; Tuinier, Remco

    2015-01-01

    Block copolymers composed of methacrylic acid (MAA) and methyl methacrylate (MMA) blocks are interesting candidates for replacing surfactants in emulsion polymerization methods. Here the synthesis and experimental characterization of well-defined PMAA-PMMA block copolymers made via RAFT

  7. Self-assembled structures of PMAA-PMMA block copolymers: Synthesis, characterization, and self-consistent field computations

    NARCIS (Netherlands)

    Li, F.; Schellekens, J.; Bont, de J.A.M.; Peters, R.; Overbeek, A.; Leermakers, F.A.M.; Tuinier, R.

    2015-01-01

    Block copolymers composed of methacrylic acid (MAA) and methyl methacrylate (MMA) blocks are interesting candidates for replacing surfactants in emulsion polymerization methods. Here the synthesis and experimental characterization of well-defined PMAA–PMMA block copolymers made via RAFT

  8. Hyperchaotic Chameleon: Fractional Order FPGA Implementation

    Directory of Open Access Journals (Sweden)

    Karthikeyan Rajagopal

    2017-01-01

    Full Text Available There are many recent investigations on chaotic hidden attractors although hyperchaotic hidden attractor systems and their relationships have been less investigated. In this paper, we introduce a hyperchaotic system which can change between hidden attractor and self-excited attractor depending on the values of parameters. Dynamic properties of these systems are investigated. Fractional order models of these systems are derived and their bifurcation with fractional orders is discussed. Field programmable gate array (FPGA implementations of the systems with their power and resource utilization are presented.

  9. Superconducting cavity driving with FPGA controller

    International Nuclear Information System (INIS)

    Czarski, Tomasz; Koprek, Waldemar; Pozniak, Krzysztof T.; Romaniuk, Ryszard S.; Simrock, Stefan; Brandt, Alexander; Chase, Brian; Carcagno, Ruben; Cancelo, Gustavo; Koeth, Timothy W.

    2006-01-01

    A digital control of superconducting cavities for a linear accelerator is presented. FPGA-based controller, supported by Matlab system, was applied. Electrical model of a resonator was used for design of a control system. Calibration of the signal path is considered. Identification of cavity parameters has been carried out for adaptive control algorithm. Feed-forward and feedback modes were applied in operating the cavities. Required performance has been achieved; i.e. driving on resonance during filling and field stabilization during flattop time, while keeping reasonable level of the power consumption. Representative results of the experiments are presented for different levels of the cavity field gradient

  10. Spacewire Routers Implemented with FPGA Technology

    Science.gov (United States)

    Habinc, Sandi; Isomaki, Marko

    2011-08-01

    Routers are an integral part of SpaceWire networks. Aeroflex Gaisler has developed a highly configurable SpaceWire router VHDL IP core to meet the needs for technology independent router designs. The main design goals have been configurability, technology independence, support of the standard and expandability. The IP core being technologically independent allows it to be used in both ASIC and FPGA technology. The latter is now being used to produce versatile standard products that can reach the market faster than for example an ASIC based product.

  11. Signal compression in radar using FPGA

    OpenAIRE

    Enrique Escamilla Hemández; Víctor Kravchenko; Volodymyr Ponomaryov; Gonzalo Duchen Sánchez; David Hernández Sánchez

    2010-01-01

    El presente artículo muestra la puesta en práctica de hardware para realizar el procesamiento en tiempo real de la señal de radar usando una técnica simple, rápida basada en arquitectura de FPGA (Field Programmable Gate Array). El proceso incluye diversos procedimientos de enventanado durante la compresión del pulso del radar de apertura sintética (SAR). El proceso de compresión de la señal de radar se hace con un filtro acoplado. que aplica funciones clásicas y nuevas de enventanado, donde n...

  12. Surprising transformation of a block copolymer into a high performance polystyrene ultrafiltration membrane with a hierarchically organized pore structure

    KAUST Repository

    Shevate, Rahul

    2018-02-08

    We describe the preparation of hierarchical polystyrene nanoporous membranes with a very narrow pore size distribution and an extremely high porosity. The nanoporous structure is formed as a result of unusual degradation of the poly(4-vinyl pyridine) block from self-assembled poly(styrene)-b-poly(4-vinyl pyridine) (PS-b-P4VP) membranes through the formation of an unstable pyridinium intermediate in an alkaline medium. During this process, the confined swelling and controlled degradation produced a tunable pore size. We unequivocally confirmed the successful elimination of the P4VP block from a PS-b-P4VPVP membrane using 1D/2D NMR spectroscopy and other characterization techniques. Surprisingly, the long range ordered surface porosity was preserved even after degradation of the P4VP block from the main chain of the diblock copolymer, as revealed by SEM. Aside from a drastically improved water flux (∼67% increase) compared to the PS-b-P4VP membrane, the hydraulic permeability measurements validated pH independent behaviour of the isoporous PS membrane over a wide pH range from 3 to 10. The effect of the pore size on protein transport rate and selectivity (a) was investigated for lysozyme (Lys), bovine serum albumin (BSA) and globulin-γ (IgG). A high selectivity of 42 (Lys/IgG) and 30 (BSA/IgG) was attained, making the membranes attractive for size selective separation of biomolecules from their synthetic model mixture solutions.

  13. Effect of cyclic block loading on character of deformation and strength of structural materials in plane stressed state

    International Nuclear Information System (INIS)

    Kul'chitskij, N.M.; Troshchenko, A.V.; Koval'chuk, B.I.; Khamaza, L.A.; Nikolaev, I.A.

    1982-01-01

    The paper is concerned with choice of conditions for preliminary cyclic block loading, determination of fatigue failure resistance characteristics for various structural materials under regular and selected block loading, investigation of the preliminary cyclic loading effect on regularities of elastoplastic deformation of materials concerned in the biaxial stressed state. Under selected conditions of cyclic block loading the character of damage accumulation is close to the linear law for the materials of high-srength doped steel, and VT6 alloys of concern. These materials in the initial state and after preliminary cyclic loading are anisotropic. Axial direction is characterized by a higher plastic strain resistance for steel and tangential direction - for VT6 alloy. The generalized strain curves for the materials in question are not invariant as to the stressed state type. It is stated that the effect of preliminary unsteady cyclic loading on resistance and general regularities of material deformation in the complex stressed state is insignificant. It is observed that stress-strain properties of the materials tend to vary in the following way: plastic strain resistance of the steel lowers and that of VT6 rises, anisotropy of the materials somehow decreases. The variation in the material anisotropy may be attributed to a decrease in residual stresses resulting from preliminary cyclic loading

  14. FPGA implementation of image dehazing algorithm for real time applications

    Science.gov (United States)

    Kumar, Rahul; Kaushik, Brajesh Kumar; Balasubramanian, R.

    2017-09-01

    Weather degradation such as haze, fog, mist, etc. severely reduces the effective range of visual surveillance. This degradation is a spatially varying phenomena, which makes this problem non trivial. Dehazing is an essential preprocessing stage in applications such as long range imaging, border security, intelligent transportation system, etc. However, these applications require low latency of the preprocessing block. In this work, single image dark channel prior algorithm is modified and implemented for fast processing with comparable visual quality of the restored image/video. Although conventional single image dark channel prior algorithm is computationally expensive, it yields impressive results. Moreover, a two stage image dehazing architecture is introduced, wherein, dark channel and airlight are estimated in the first stage. Whereas, transmission map and intensity restoration are computed in the next stages. The algorithm is implemented using Xilinx Vivado software and validated by using Xilinx zc702 development board, which contains an Artix7 equivalent Field Programmable Gate Array (FPGA) and ARM Cortex A9 dual core processor. Additionally, high definition multimedia interface (HDMI) has been incorporated for video feed and display purposes. The results show that the dehazing algorithm attains 29 frames per second for the image resolution of 1920x1080 which is suitable of real time applications. The design utilizes 9 18K_BRAM, 97 DSP_48, 6508 FFs and 8159 LUTs.

  15. FPGA Hardware Acceleration of a Phylogenetic Tree Reconstruction with Maximum Parsimony Algorithm

    OpenAIRE

    BLOCK, Henry; MARUYAMA, Tsutomu

    2017-01-01

    In this paper, we present an FPGA hardware implementation for a phylogenetic tree reconstruction with a maximum parsimony algorithm. We base our approach on a particular stochastic local search algorithm that uses the Progressive Neighborhood and the Indirect Calculation of Tree Lengths method. This method is widely used for the acceleration of the phylogenetic tree reconstruction algorithm in software. In our implementation, we define a tree structure and accelerate the search by parallel an...

  16. Effects of structural characteristics on the productivity of shale gas wells: A case study on the Jiaoshiba Block in the Fuling shale gasfield, Sichuan Basin

    Directory of Open Access Journals (Sweden)

    Ming Hu

    2018-03-01

    Full Text Available For the sake of figuring out the influential mechanisms of structural characteristics on the productivity of shale gas wells, the structural characteristics of the Jiaoshiba Block in the Fuling shale gasfield, Sichuan Basin, were analyzed. Then, based on well test data of more than 190 horizontal wells, the effects of structures on shale gas well productivity were discussed systematically, and the main structural factors of different structural units in the Jiaoshiba Block that influence the productivity of shale gas wells were clarified. The following results were obtained. First, the structural units in the Jiaoshiba Block were obviously different in structural characteristics and their deformation strength is different. Second, the influence of structural characteristics on shale gas well productivity is directly manifested in gas-bearing property and fracturing effect. The stronger the structural deformation and the more developed the large faults and natural fractures, the more easily shale gas escapes and the poorer the gas bearing property will be, and vice versa. Third, The stronger the structural deformation, the more developed the fractures, the greater the burial depth and the higher the compressive stress of negative structures, the worse the fracturing effect will be, and vice versa. And fourth, Tectonics is the key factor controlling the difference of shale gas productivity between different structural units in the Jiaoshiba Block, but the main structural factors influencing the productivity are different in different structural units. Keywords: Sichuan Basin, Fuling shale gasfield, Jiaoshiba, Shale gas, Structural characteristics, Gas bearing property, Fracturing, Productivity

  17. Structural insight into RNA recognition motifs: versatile molecular Lego building blocks for biological systems.

    Science.gov (United States)

    Muto, Yutaka; Yokoyama, Shigeyuki

    2012-01-01

    'RNA recognition motifs (RRMs)' are common domain-folds composed of 80-90 amino-acid residues in eukaryotes, and have been identified in many cellular proteins. At first they were known as RNA binding domains. Through discoveries over the past 20 years, however, the RRMs have been shown to exhibit versatile molecular recognition activities and to behave as molecular Lego building blocks to construct biological systems. Novel RNA/protein recognition modes by RRMs are being identified, and more information about the molecular recognition by RRMs is becoming available. These RNA/protein recognition modes are strongly correlated with their biological significance. In this review, we would like to survey the recent progress on these versatile molecular recognition modules. Copyright © 2012 John Wiley & Sons, Ltd.

  18. Superconducting cavity driving with FPGA controller

    Energy Technology Data Exchange (ETDEWEB)

    Czarski, T.; Koprek, W.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland); Simrock, S.; Brand, A. [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany); Chase, B.; Carcagno, R.; Cancelo, G. [Fermi National Accelerator Lab., Batavia, IL (United States); Koeth, T.W. [Rutgers - the State Univ. of New Jersey, NJ (United States)

    2006-07-01

    The digital control of several superconducting cavities for a linear accelerator is presented. The laboratory setup of the CHECHIA cavity and ACC1 module of the VU-FEL TTF in DESY-Hamburg have both been driven by a Field Programmable Gate Array (FPGA) based system. Additionally, a single 9-cell TESLA Superconducting cavity of the FNPL Photo Injector at FERMILAB has been remotely controlled from WUT-ISE laboratory with the support of the DESY team using the same FPGA control system. These experiments focused attention on the general recognition of the cavity features and projected control methods. An electrical model of the resonator was taken as a starting point. Calibration of the signal path is considered key in preparation for the efficient driving of a cavity. Identification of the resonator parameters has been proven to be a successful approach in achieving required performance; i.e. driving on resonance during filling and field stabilization during flattop time while requiring reasonable levels of power consumption. Feed-forward and feedback modes were successfully applied in operating the cavities. Representative results of the experiments are presented for different levels of the cavity field gradient. (orig.)

  19. Control de acceso usando FPGA y RFID

    Directory of Open Access Journals (Sweden)

    Dora Luz Almanza Ojeda

    2012-10-01

    Full Text Available Este trabajo presenta el diseño e implementación de un sistema de control de acceso mediante Identificación por Radiofrecuencia (RFID, Radio Frequency Identification controlado por una Matriz de compuertas programables (FPGA, Field Programmable Gate Array. El sistema está constituido por un par de dispositivos de adquisición de radiofrecuencia, una FPGA, un juego de etiquetas y tarjetas pasivas de identificación. Mediante una interfaz gráfica de usuario es posible controlar todo movimiento dentro de una zona determinada, desde los accesos hasta la disponibilidad de equipo; utilizando los dispositivos de adquisición de radiofrecuencia se puede acceder a la información de los usuarios autorizados, así como al control del equipo. Con este sistema es posible monitorear, administrar y reportar todo acceso de personal, movimiento de equipo o plagio de manera eficiente y evitando un gran número de errores humanos.  

  20. An FPGA-Based People Detection System

    Directory of Open Access Journals (Sweden)

    James J. Clark

    2005-05-01

    Full Text Available This paper presents an FPGA-based system for detecting people from video. The system is designed to use JPEG-compressed frames from a network camera. Unlike previous approaches that use techniques such as background subtraction and motion detection, we use a machine-learning-based approach to train an accurate detector. We address the hardware design challenges involved in implementing such a detector, along with JPEG decompression, on an FPGA. We also present an algorithm that efficiently combines JPEG decompression with the detection process. This algorithm carries out the inverse DCT step of JPEG decompression only partially. Therefore, it is computationally more efficient and simpler to implement, and it takes up less space on the chip than the full inverse DCT algorithm. The system is demonstrated on an automated video surveillance application and the performance of both hardware and software implementations is analyzed. The results show that the system can detect people accurately at a rate of about 2.5 frames per second on a Virtex-II 2V1000 using a MicroBlaze processor running at 75 MHz, communicating with dedicated hardware over FSL links.

  1. Signal compression in radar using FPGA

    Directory of Open Access Journals (Sweden)

    Enrique Escamilla Hemández

    2010-01-01

    Full Text Available El presente artículo muestra la puesta en práctica de hardware para realizar el procesamiento en tiempo real de la señal de radar usando una técnica simple, rápida basada en arquitectura de FPGA (Field Programmable Gate Array. El proceso incluye diversos procedimientos de enventanado durante la compresión del pulso del radar de apertura sintética (SAR. El proceso de compresión de la señal de radar se hace con un filtro acoplado. que aplica funciones clásicas y nuevas de enventanado, donde nos centramos en obtener una mejor atenuación para los valores de lóbulos laterales. La arquitectura propuesta explota los recursos de computación paralela de los dispositivos FPGA para alcanzar una mejor velocidad de cómputo. Las investigaciones experimentales han demostrado que los mejores resultados para el funcionamiento de la compresión del pulso se han obtenido usando las funciones atómicas, mejorando el funcionamiento del sistema del radar en presencia de ruido, y consiguiendo una pequeña degradación en la resolución de rango. La puesta en práctica del tratamiento de señales en el sistema de radar en tiempo real se discute y se justifica la eficiencia de la arquitectura de hardware propuesta.

  2. Superconducting cavity driving with FPGA controller

    International Nuclear Information System (INIS)

    Czarski, T.; Koprek, W.; Pozniak, K.T.; Romaniuk, R.S.; Simrock, S.; Brand, A.; Chase, B.; Carcagno, R.; Cancelo, G.; Koeth, T.W.

    2006-01-01

    The digital control of several superconducting cavities for a linear accelerator is presented. The laboratory setup of the CHECHIA cavity and ACC1 module of the VU-FEL TTF in DESY-Hamburg have both been driven by a Field Programmable Gate Array (FPGA) based system. Additionally, a single 9-cell TESLA Superconducting cavity of the FNPL Photo Injector at FERMILAB has been remotely controlled from WUT-ISE laboratory with the support of the DESY team using the same FPGA control system. These experiments focused attention on the general recognition of the cavity features and projected control methods. An electrical model of the resonator was taken as a starting point. Calibration of the signal path is considered key in preparation for the efficient driving of a cavity. Identification of the resonator parameters has been proven to be a successful approach in achieving required performance; i.e. driving on resonance during filling and field stabilization during flattop time while requiring reasonable levels of power consumption. Feed-forward and feedback modes were successfully applied in operating the cavities. Representative results of the experiments are presented for different levels of the cavity field gradient. (orig.)

  3. Automated Metabolic P System Placement in FPGA

    Directory of Open Access Journals (Sweden)

    Kulakovskis Darius

    2016-07-01

    Full Text Available An original Very High Speed Integrated Circuit Hardware Description Language (VHDL code generation tool that can be used to automate Metabolic P (MP system implementation in hardware such as Field Programmable Gate Arrays (FPGA is described. Unlike P systems, MP systems use a single membrane in their computations. Nevertheless, there are many biological processes that have been successfully modeled by MP systems in software. This is the first attempt to analyze MP system hardware implementations. Two different MP systems are investigated with the purpose of verifying the developed software: the model of glucose–insulin interactions in the Intravenous Glucose Tolerance Test (IVGTT, and the Non-Photochemical Quenching process. The implemented systems’ calculation accuracy and hardware resource usage are examined. It is found that code generation tool works adequately; however, a final decision has to be done by the developer because sometimes several implementation architecture alternatives have to be considered. As an archetypical example serves the IVGTT MP systems’ 21–23 bits FPGA implementation manifesting this in the Digital Signal Processor (DSP, slice, and 4-input LUT usage.

  4. An improved real time superresolution FPGA system

    Science.gov (United States)

    Lakshmi Narasimha, Pramod; Mudigoudar, Basavaraj; Yue, Zhanfeng; Topiwala, Pankaj

    2009-05-01

    In numerous computer vision applications, enhancing the quality and resolution of captured video can be critical. Acquired video is often grainy and low quality due to motion, transmission bottlenecks, etc. Postprocessing can enhance it. Superresolution greatly decreases camera jitter to deliver a smooth, stabilized, high quality video. In this paper, we extend previous work on a real-time superresolution application implemented in ASIC/FPGA hardware. A gradient based technique is used to register the frames at the sub-pixel level. Once we get the high resolution grid, we use an improved regularization technique in which the image is iteratively modified by applying back-projection to get a sharp and undistorted image. The algorithm was first tested in software and migrated to hardware, to achieve 320x240 -> 1280x960, about 30 fps, a stunning superresolution by 16X in total pixels. Various input parameters, such as size of input image, enlarging factor and the number of nearest neighbors, can be tuned conveniently by the user. We use a maximum word size of 32 bits to implement the algorithm in Matlab Simulink as well as in FPGA hardware, which gives us a fine balance between the number of bits and performance. The proposed system is robust and highly efficient. We have shown the performance improvement of the hardware superresolution over the software version (C code).

  5. Gravity evidence for shaping of the crustal structure of the Ameca graben (Jalisco block northern limit). Western Mexico

    Science.gov (United States)

    Alatorre-Zamora, Miguel Angel; Campos-Enríquez, José Oscar; Fregoso-Becerra, Emilia; Quintanar-Robles, Luis; Toscano-Fletes, Roberto; Rosas-Elguera, José

    2018-03-01

    The Ameca tectonic depression (ATD) is located at the NE of the Jalisco Block along the southwestern fringe of the NW-SE trending Tepic-Zacoalco Rift, in the west-central part of the Trans-Mexican Volcanic Belt, western Mexico. To characterize its shallow crustal structure, we conducted a gravity survey based on nine N-S gravity profiles across the western half of the Ameca Valley. The Bouguer residual anomalies are featured by a central low between two zones of positive gravity values with marked gravity gradients. These anomalies have a general NW-SE trend similar to the Tepic-Zacoalco Rift general trend. Basement topography along these profiles was obtained by means of: 1) a Tsuboi's type inverse modeling, and 2) forward modeling. Approximately northward dipping 10° slopes are modeled in the southern half, with south tilted down faulted blocks of the Cretaceous granitic basement and its volcano-sedimentary cover along sub-vertical and intermediate normal faults, whereas southward dipping slopes of almost 15° are observed at the northern half. According to features of the obtained models, this depression corresponds to a slight asymmetric graben. The Ameca Fault is part of the master fault system along its northern limit. The quantitative interpretation shows an approximately 500 to 1100 m thick volcano-sedimentary infill capped by alluvial products. This study has several implications concerning the limit between the Jalisco Block and the Tepic-Zacoalco Rift. The established shallow crustal structure points to the existence of a major listric fault with its detachment surface beneath the Tepic-Zacoalco Rift. The Ameca Fault is interpreted as a secondary listric fault. The models indicate the presence of granitic bodies of the Jalisco Block beneath the TMVB volcanic products of the Tepic-Zacoalco rift. This implies that the limit between these two regional structures is not simple but involves a complex transition zone. A generic model suggests that the

  6. Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA)

    International Nuclear Information System (INIS)

    Jinyuan Wu; Zonghan Shi; Irena Y Wang

    2003-01-01

    A Time-to-Digital Converter (TDC) implemented in general purpose field-programmable gate array (FPGA) for the Fermilab CKM experiment will be presented. The TDC uses a delay chain and register array structure to produce lower bits in addition to higher bits from a clock counter. Lacking the direct controls custom chips, the FPGA implementation of the delay chain and register array structure had to address two major problems: (1) the logic elements used for the delay chain and register array structure must be placed and routed by the FPGA compiler in a predictable manner, to assure uniformity of the TDC binning and short-term stability. (2) The delay variation due to temperature and power supply voltage must be compensated for to assure long-term stability. They used the chain structures in the existing FPGAs that the venders designed for general purpose such as carry algorithm or logic expansion to solve the first problem. To compensate for delay variations, they studied several digital compensation strategies that can be implemented in the same FPGA device. Some bench-top test results will also be presented in this document

  7. Research on acceleration method of reactor physics based on FPGA platforms

    International Nuclear Information System (INIS)

    Li, C.; Yu, G.; Wang, K.

    2013-01-01

    The physical designs of the new concept reactors which have complex structure, various materials and neutronic energy spectrum, have greatly improved the requirements to the calculation methods and the corresponding computing hardware. Along with the widely used parallel algorithm, heterogeneous platforms architecture has been introduced into numerical computations in reactor physics. Because of the natural parallel characteristics, the CPU-FPGA architecture is often used to accelerate numerical computation. This paper studies the application and features of this kind of heterogeneous platforms used in numerical calculation of reactor physics through practical examples. After the designed neutron diffusion module based on CPU-FPGA architecture achieves a 11.2 speed up factor, it is proved to be feasible to apply this kind of heterogeneous platform into reactor physics. (authors)

  8. FPGA and optical-network-based LLRF distributed control system for TESLA-XFEL linear accelerator

    Science.gov (United States)

    Pozniak, Krzysztof T.; Romaniuk, Ryszard S.; Czarski, Tomasz; Giergusiewicz, Wojciech; Jalmuzna, Wojciech; Olowski, Krysztof; Perkuszewski, Karol; Zielinski, Jerzy; Simrock, Stefan

    2005-02-01

    The work presents a structural and functional model of a distributed low level radio frequency (LLRF) control system for the TESLA-XFEL accelerator. The design of a system basing on the FPGA chips and multi-gigabit optical network was debated. The system design approach was fully parametric. The major emphasis is put on the methods of the functional and hardware concentration to use fully both: a very big transmission capacity of the optical fiber telemetric channels and very big processing power of the latest series of the, DSP enhanced and optical I/O equipped, FPGA chips. The subject of the work is the design of a universal, laboratory module of the LLRF sub-system. Initial parameters of the system model under the design are presented.

  9. Evaluation of radiation tolerance of TMR designs in SRAM-based FPGA.

    CERN Document Server

    Shibin, Konstantin

    2016-01-01

    During the Summer Student program in CERN I was working in the CMS Muon Drift Tube group, building a setup for evaluating the radiation tolerance of the drift tube signal encoding hardware (Time-to-Digital Converter, TDC) implemented in SRAM-based FPGA using Triple Modular Redundancy (TMR). While commercially available SRAM-based FPGAs have more computational power, are more advanced in general than flash-based FPGAs and are the most suitable technology for implementing the TDC logic (also taking into account the performance requirements), in the context of operation inside an environment with high levels of ionizing radiation (such as inside CMS DT detector) they are more susceptible to configuration memory bit flips – Single Event Upsets (SEUs) - due to lower required energy for a memory bit being flipped. The effect of a SEU inside the configuration memory might change the functionality of the underlying building blocks of FPGA and if the respective blocks were involved in implementing the desired custom...

  10. Fast electromagnetic characterization of integrated circuit passive isolation structures based on interference blocking

    NARCIS (Netherlands)

    Grau Novellas, M.; Serra, R.; Rose, Matthias

    2017-01-01

    An early characterization of integrated circuit passive isolation structures is crucial to predict their performance and effectiveness in minimizing substrate coupling. In this paper, an electromagnetic (EM) modeling methodology is proposed, which can be applied to different types of isolation

  11. A fast improved fat tree encoder for wave union TDC in an FPGA

    International Nuclear Information System (INIS)

    Shen Qi; Zhao Lei; Liu Shubin; Qi Binxiang; Hu Xueye; An Qi; Liao Shengkai; Peng Chengzhi

    2013-01-01

    Up to now, the wave union method can achieve the best timing performance in FPGA-based TDC designs. However, it should be guaranteed in such a structure that the non-thermometer code to binary code (NTH2B) encoding process should be finished within just one system clock cycle. So the implementation of the NTH2B encoder is quite challenging considering the high speed requirement. Besides, the high resolution wave union TDC also demands that the encoder convert an ultra-wide input code to a binary code. We present a fast improved fat tree encoder (IFTE) to fulfill such requirements, in which bubble error suppression is also integrated. With this encoder scheme, a wave union TDC with 7.7 ps RMS and 3.8 ps effective bin size was implemented in an FPGA from Xilinx Virtex 5 family. An encoding time of 8.33 ns was achieved for a 276-bit non-thermometer code to a 9-bit binary code conversion. We conducted a series of tests on the oscillating period of the wave union launcher, as well as the overall performance of the TDC; test results indicate that the IFTE works well. In fact, in the implementation of this encoder, no manual routing or special constraints were required; therefore, this IFTE structure could also be further applied in other delay-chain-based FPGA TDCs. (authors)

  12. Embedded FPGA Design for Optimal Pixel Adjustment Process of Image Steganography

    Directory of Open Access Journals (Sweden)

    Chiung-Wei Huang

    2018-01-01

    Full Text Available We propose a prototype of field programmable gate array (FPGA implementation for optimal pixel adjustment process (OPAP algorithm of image steganography. In the proposed scheme, the cover image and the secret message are transmitted from a personal computer (PC to an FPGA board using RS232 interface for hardware processing. We firstly embed k-bit secret message into each pixel of the cover image by the last-significant-bit (LSB substitution method, followed by executing associated OPAP calculations to construct a stego pixel. After all pixels of the cover image have been embedded, a stego image is created and transmitted from FPGA back to the PC and stored in the PC. Moreover, we have extended the basic pixel-wise structure to a parallel structure which can fully use the hardware devices to speed up the embedding process and embed several bits of secret message at the same time. Through parallel mechanism of the hardware based design, the data hiding process can be completed in few clock cycles to produce steganography outcome. Experimental results show the effectiveness and correctness of the proposed scheme.

  13. Fpga As A Part Of Ms Windows Control Environment

    Directory of Open Access Journals (Sweden)

    Krzysztof Kołek

    2007-01-01

    Full Text Available The attention is focused on the Windows operating system (OS used as a control and measurementenvironment. Windows OS due to extensions becomes a real-time OS (RTOS.Benefits and drawbacks of typical software extensions are compared. As far as hardwaresolutions are concerned the field programmable gate arrays FPGA technology is proposed toensure fast time-critical operations. FPGA-based parallel execution and hardware implementationof the data processing algorithms significantly outperform the classical microprocessoroperating modes. Suitability of the RTOS for a particular application and FPGA hardwaremaintenance is studied.

  14. Long-distance configuration of FPGA based on serial communication

    International Nuclear Information System (INIS)

    Liu Xiang; Song Kezhu; Zhang Sifeng

    2010-01-01

    To solve FPGA configuration in some nuclear electronics, which works in radioactivity environment, the article introduces a way of long-distance configuration with PC and CPLD, based on serial communication. Taking CYCLONE series FPGA and EPCS configuration chip from ALTERA for example, and using the AS configuration mode, we described our design from the aspects of basic theory, hardware connection, software function and communication protocol. With this design, we could configure several FPGAs in the distance of 100 meters, or we could configure on FPGA in the distance of 150 meters. (authors)

  15. Lithosphere Structure of the Rivera Plate - Jalisco Block Contact Zone: Septentrional Region of the Islas Marías (Mexico)

    Science.gov (United States)

    Madrigal-Ávalos, L. A.; Nunez, D.; Escalona-Alcazar, F. D. J.; Nuñez-Cornu, F. J.; Barba, D. C., Sr.; Danobeitia, J.

    2017-12-01

    The western margin of Mexico is a tectonic complex region where large earthquakes occurred with very destructive consequences, including the generation of big tsunamis. This fact is mainly the result of the Rivera plate subduction beneath the North American plate and the Jalisco Block implying a high potential seismic risk. In the north, between the Tamayo Fracture Zone and the Mesoamerican Trench, the Islas Marías region is a complex tectonic limit within the interaction of the Rivera plate oceanic crust and the Jalisco Block continental crust. In order to know the shallow and deep structure of the Rivera plate - Jalisco Block contact zone and to be able to determine these potential seismic sources, the TSUJAL geophysical experiment was carried out from 2012 to 2016. As part of this project, we present the results of the processed and analyzed MCS and WAS data along the TS09 and RTSIM01 seismic transects, respectively, across the septentrional region of Islas Marías. These marine seismic lines are coincident with 110 km length for MCS and 240 km for WAS, and perpendicular to the coastline with SW-NE orientation. The seismic sources used in this work aboard RRS James Cook consisted of 12 guns with a total capacity for WAS data of 5800 in3 every 120 s and 3540 in3 every 50 m for MCS data. The MCS data were acquired with a 5.85 km length streamer with a 468 active channels, while the WAS data were recorded by a network of 4 OBS and 27 land seismic stations. After data processing and joint interpretation, it was possible to determine that shallow structure is mainly constituted by normal faults associated to graben structures forming sedimentary basins with non-deformed sediments in the basement. While the deep structure is characterized by depths from 9 to 12 km in the oceanic crust and 18 to 21 km in the continental crust. The deepest layers of the upper mantle were determined up to 35 km depth. In this study, it was possible to calculate a dip angle between 6

  16. Soft error rate estimations of the Kintex-7 FPGA within the ATLAS Liquid Argon (LAr) Calorimeter

    International Nuclear Information System (INIS)

    Wirthlin, M J; Harding, A; Takai, H

    2014-01-01

    This paper summarizes the radiation testing performed on the Xilinx Kintex-7 FPGA in an effort to determine if the Kintex-7 can be used within the ATLAS Liquid Argon (LAr) Calorimeter. The Kintex-7 device was tested with wide-spectrum neutrons, protons, heavy-ions, and mixed high-energy hadron environments. The results of these tests were used to estimate the configuration ram and block ram upset rate within the ATLAS LAr. These estimations suggest that the configuration memory will upset at a rate of 1.1 × 10 −10 upsets/bit/s and the bram memory will upset at a rate of 9.06 × 10 −11 upsets/bit/s. For the Kintex 7K325 device, this translates to 6.85 × 10 −3 upsets/device/s for configuration memory and 1.49 × 10 −3 for block memory

  17. Structural analysis of ceramic blocks sealing or structural incorporated with the industrial laundry sludge; Anllise estrutural de blocos ceramicos de vedacao ou estruturais incorporados com lodo de lavanderia industrial

    Energy Technology Data Exchange (ETDEWEB)

    Almeida, P.H.S.; Grippe, V.Y.Q.; Goulart, J.V., E-mail: phsoal@yahoo.com.br [Universidade Federal de Mato Grosso (UFMT), MT (Brazil)

    2016-07-01

    Industrial and commercial development of recent decades has led to an increase in waste generation. Thus, it is necessary to develop alternative and effective methods of treatment, replacing the simple disposal of these wastes in landfills. The objective of this work is to study the incorporation of textile industrial laundries sludge in ceramic blocks sealing or structural. Samples of ceramic blocks were produced using formulation with 20% sludge, the mass of ceramic clay. Structural analysis of the block was observed the tendency of most empty emergence (pores) during the firing of the blocks, as textile sludge was added in the ceramic paste composition. The mechanical testing of blocks compressive strength was above the minimum 3.0 MPa specified by the standard limit. The physical test water absorption of the blocks was within the range 8 to 22% specified by the standard. (author)

  18. Automated global structure extraction for effective local building block processing in XCS.

    Science.gov (United States)

    Butz, Martin V; Pelikan, Martin; Llorà, Xavier; Goldberg, David E

    2006-01-01

    Learning Classifier Systems (LCSs), such as the accuracy-based XCS, evolve distributed problem solutions represented by a population of rules. During evolution, features are specialized, propagated, and recombined to provide increasingly accurate subsolutions. Recently, it was shown that, as in conventional genetic algorithms (GAs), some problems require efficient processing of subsets of features to find problem solutions efficiently. In such problems, standard variation operators of genetic and evolutionary algorithms used in LCSs suffer from potential disruption of groups of interacting features, resulting in poor performance. This paper introduces efficient crossover operators to XCS by incorporating techniques derived from competent GAs: the extended compact GA (ECGA) and the Bayesian optimization algorithm (BOA). Instead of simple crossover operators such as uniform crossover or one-point crossover, ECGA or BOA-derived mechanisms are used to build a probabilistic model of the global population and to generate offspring classifiers locally using the model. Several offspring generation variations are introduced and evaluated. The results show that it is possible to achieve performance similar to runs with an informed crossover operator that is specifically designed to yield ideal problem-dependent exploration, exploiting provided problem structure information. Thus, we create the first competent LCSs, XCS/ECGA and XCS/BOA, that detect dependency structures online and propagate corresponding lower-level dependency structures effectively without any information about these structures given in advance.

  19. Wire Position Monitoring with FPGA based Electronics

    International Nuclear Information System (INIS)

    Eddy, N.; Lysenko, O.

    2009-01-01

    This fall the first Tesla-style cryomodule cooldown test is being performed at Fermilab. Instrumentation department is preparing the electronics to handle the data from a set of wire position monitors (WPMs). For simulation purposes a prototype pipe with a WMP has been developed and built. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The wire is stretched along the pipe with a tensioning load of 9.07 kg. The WPM consists of four 50 (Omega) striplines spaced 90 o apart. FPGA based digitizer scans the WPM and transmits the data to a PC via VME interface. The data acquisition is based on the PC running LabView. In order to increase the accuracy and convenience of the measurements some modifications were required. The first is implementation of an average and decimation filter algorithm in the integrator operation in the FPGA. The second is the development of alternative tool for WPM measurements in the PC. The paper describes how these modifications were performed and test results of a new design. The last cryomodule generation has a single chain of seven WPMs (placed in critical positions: at each end, at the three posts and between the posts) to monitor a cold mass displacement during cooldown. The system was developed in Italy in collaboration with DESY. Similar developments have taken place at Fermilab in the frame of cryomodules construction for SCRF research. This fall preliminary cryomodule cooldown test is being performed. In order to prepare an appropriate electronic system for the test a prototype pipe with a WMP has been developed and built, figure 1. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The 0.5 mm diameter Cu wire is stretched along the pipe with a tensioning load of 9.07 kg and has a length of 1.1 m. The WPM consists of four 50 (Omega) striplines spaced 90 o apart. An FPGA based digitizer

  20. An Electronic Structure Approach to Charge Transfer and Transport in Molecular Building Blocks for Organic Optoelectronics

    Science.gov (United States)

    Hendrickson, Heidi Phillips

    A fundamental understanding of charge separation in organic materials is necessary for the rational design of optoelectronic devices suited for renewable energy applications and requires a combination of theoretical, computational, and experimental methods. Density functional theory (DFT) and time-dependent (TD)DFT are cost effective ab-initio approaches for calculating fundamental properties of large molecular systems, however conventional DFT methods have been known to fail in accurately characterizing frontier orbital gaps and charge transfer states in molecular systems. In this dissertation, these shortcomings are addressed by implementing an optimally-tuned range-separated hybrid (OT-RSH) functional approach within DFT and TDDFT. The first part of this thesis presents the way in which RSH-DFT addresses the shortcomings in conventional DFT. Environmentally-corrected RSH-DFT frontier orbital energies are shown to correspond to thin film measurements for a set of organic semiconducting molecules. Likewise, the improved RSH-TDDFT description of charge transfer excitations is benchmarked using a model ethene dimer and silsesquioxane molecules. In the second part of this thesis, RSH-DFT is applied to chromophore-functionalized silsesquioxanes, which are currently investigated as candidates for building blocks in optoelectronic applications. RSH-DFT provides insight into the nature of absorptive and emissive states in silsesquioxanes. While absorption primarily involves transitions localized on one chromophore, charge transfer between chromophores and between chromophore and silsesquioxane cage have been identified. The RSH-DFT approach, including a protocol accounting for complex environmental effects on charge transfer energies, was tested and validated against experimental measurements. The third part of this thesis addresses quantum transport through nano-scale junctions. The ability to quantify a molecular junction via spectroscopic methods is crucial to their

  1. Application-specific mesh-based heterogeneous FPGA architectures

    CERN Document Server

    Parvez, Husain

    2011-01-01

    This volume presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. Readers will find a description of state-of-the-art techniques for reducing area requirements, which both increase performance and enable power reduction.

  2. Reconfigurable Computing for Embedded Systems, FPGA Devices and Software Components

    National Research Council Canada - National Science Library

    Bardouleau, Graham; Kulp, James

    2005-01-01

    In recent years the size and capabilities of field-programmable gate array (FPGA) devices have increased to a point where they can be deployed as adjunct processing elements within a multicomputer environment...

  3. High-Performance Linear Algebra Processor using FPGA

    National Research Council Canada - National Science Library

    Johnson, J

    2004-01-01

    With recent advances in FPGA (Field Programmable Gate Array) technology it is now feasible to use these devices to build special purpose processors for floating point intensive applications that arise in scientific computing...

  4. A Hardware Framework for on-Chip FPGA Acceleration

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

    2016-01-01

    In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accele......In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA......-based accelerator. Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism....

  5. A software radio platform based on ARM and FPGA

    Directory of Open Access Journals (Sweden)

    Yang Xin.

    2016-01-01

    Full Text Available The rapid rise in computational performance offered by computer systems has greatly increased the number of practical software radio applications. A scheme presented in this paper is a software radio platform based on ARM and FPGA. FPGA works as the coprocessor together with the ARM, which serves as the core processor. ARM is used for digital signal processing and real-time data transmission, and FPGA is used for synchronous timing control and serial-parallel conversion. A SPI driver for real-time data transmission between ARM and FPGA under ARM-Linux system is provided. By adopting modular design, the software radio platform is capable of implementing wireless communication functions and satisfies the requirements of real-time signal processing platform for high security and broad applicability.

  6. fpga controller design and simulation of a portable dough mixing

    African Journals Online (AJOL)

    modelled and simulated with Matlab/Simulink. Synthesizable VHDL ... Keywords: FPGA, VHDL, PID controller, Pulse Width Modulation, Full H-Bridge DC motor driver. 1. ... and (b) to simulate the control process in a virtual environment, using.

  7. Real-time FPGA architectures for computer vision

    Science.gov (United States)

    Arias-Estrada, Miguel; Torres-Huitzil, Cesar

    2000-03-01

    This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low level image processing. The FPGA-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on a dedicated VLSI to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real time performance are discussed. Some results are presented and discussed.

  8. Chain end distribution of block copolymer in two-dimensional microphase-separated structure studied by scanning near-field optical microscopy.

    Science.gov (United States)

    Sekine, Ryojun; Aoki, Hiroyuki; Ito, Shinzaburo

    2009-10-01

    The chain end distribution of a block copolymer in a two-dimensional microphase-separated structure was studied by scanning near-field optical microscopy (SNOM). In the monolayer of poly(octadecyl methacrylate)-block-poly(isobutyl methacrylate) (PODMA-b-PiBMA), the free end of the PiBMA subchain was directly observed by SNOM, and the spatial distributions of the whole block and the chain end are examined and compared with the convolution of the point spread function of the microscope and distribution function of the model structures. It was found that the chain end distribution of the block copolymer confined in two dimensions has a peak near the domain center, being concentrated in the narrower region, as compared with three-dimensional systems.

  9. Simultaneous Perturbation Particle Swarm Optimization and Its FPGA Implementation

    OpenAIRE

    Maeda, Yutaka; Matsushita, Naoto

    2009-01-01

    In this paper, we presented hardware implementation of the particle swarm optimization algorithm which is combination of the ordinary particle swarm optimization and the simultaneous perturbation method. FPGA is used to realize the system. This algorithm utilizes local information of objective function effectively without lack of advantage of the original particle swarm optimization. Moreover, the FPGA implementation gives higher operation speed effectively using parallelism of the particle s...

  10. Building Block Approach' for Structural Analysis of Thermoplastic Composite Components for Automotive Applications

    Science.gov (United States)

    Carello, M.; Amirth, N.; Airale, A. G.; Monti, M.; Romeo, A.

    2017-12-01

    Advanced thermoplastic prepreg composite materials stand out with regard to their ability to allow complex designs with high specific strength and stiffness. This makes them an excellent choice for lightweight automotive components to reduce mass and increase fuel efficiency, while maintaining the functionality of traditional thermosetting prepreg (and mechanical characteristics) and with a production cycle time and recyclability suited to mass production manufacturing. Currently, the aerospace and automotive sectors struggle to carry out accurate Finite Elements (FE) component analyses and in some cases are unable to validate the obtained results. In this study, structural Finite Elements Analysis (FEA) has been done on a thermoplastic fiber reinforced component designed and manufactured through an integrated injection molding process, which consists in thermoforming the prepreg laminate and overmolding the other parts. This process is usually referred to as hybrid molding, and has the provision to reinforce the zones subjected to additional stresses with thermoformed themoplastic prepreg as required and overmolded with a shortfiber thermoplastic resin in single process. This paper aims to establish an accurate predictive model on a rational basis and an innovative methodology for the structural analysis of thermoplastic composite components by comparison with the experimental tests results.

  11. The structure and function of glutamate receptors: Mg2+ block to X-ray diffraction.

    Science.gov (United States)

    Mayer, Mark L

    2017-01-01

    Experiments on the action of glutamate on mammalian and amphibian nervous systems started back in the 1950s but decades passed before it became widely accepted that glutamate was the major excitatory neurotransmitter in the CNS. The pace of research greatly accelerated in the 1980s when selective ligands that identified glutamate receptor subtypes became widely available, and voltage clamp techniques, coupled with rapid perfusion, began to resolve the unique functional properties of what cloning subsequently revealed to be a large family of receptors with numerous subtypes. More recently the power of X-ray crystallography and cryo-EM has been applied to the study of glutamate receptors, revealing their atomic structures, and the conformational changes that underlie their gating. In this review I summarize the history of this field, viewed through the lens of a career in which I spent 3 decades working on the structure and function of glutamate receptor ion channels. This article is part of the Special Issue entitled 'Ionotropic glutamate receptors'. Published by Elsevier Ltd.

  12. A Novel Coordination Polymer Based on Trinuclear Cobalt Building Blocks Cluster: Synthesis, Crystal Structure, and Properties

    Science.gov (United States)

    Lu, J. F.; Tang, Z. H.; Shi, J.; Ge, H. G.; Jiang, M.; Song, J.; Jin, L. X.

    2017-12-01

    The title compound {[Co3(μ3-OH)(μ2-H2O)2(H2O)5(BTC)2] · 6H2O} n (H3BTC is a 1,3,5-benzenetricarboxylic acid) was prepared and characterized by single crystal and powder X-ray diffraction, Fourier transform infrared spectroscopy, thermogravimetric and elemental analyses. The single crystal X-ray diffraction reveals that the title compound consists of 1D infinite zigzag chains which were constructed by trinuclear cobalt cluster and BTC3- ligand. Neighbouring above-mentioned 1D infinite zigzag chains are further linked by intermolecular hydrogen bonding to form a 3D supermolecular structure. In addition, the luminescent properties of the title compound were investigated.

  13. An FPGA based control unit for synchronization of laser Thomson scattering measurements to plasma events on MAST

    International Nuclear Information System (INIS)

    Naylor, G.A.

    2010-01-01

    The power and flexibility of modern Field Programmable Gate Arrays (FPGAs) is now being recognised in many areas of instrumentation and control . The high performance of modern ADCs and the high throughput of FPGAs allow the emulation of many specialised analogue instruments. The functions of heterodyne detection, phase measurements, spectrum analyzers, phase sensitive detectors, counters, etc. can be achieved in relatively simple hardware using an FPGA. The complex filtering functions can be efficiently performed digitally in the FPGA, without recourse to a separate DSP chip. This paper describes the use of a custom off the shelf FPGA board with a collection of custom interface boards to produce a powerful custom trigger system. This has been developed for agile triggering of YAG lasers on MAST. This unit allows various analogue inputs including magnetics data to be processed in real-time and allow Thomson scattering data to be collected at accurate times with respect to randomly occurring MHD phenomena such as neoclassical tearing modes (NTMs). The FPGA allows a 'System On a Chip' architecture in order to perform fast filtering in logic coupled to a dedicated soft processor for real-time fixed latency operations and a second soft processor to handle external communications with the control system for system configuration and reporting of status/archived data. The use of such a generic structure in order to provide a common approach, with reduced software development times, for diverse diagnostic situations will be discussed.

  14. Epidural block

    Science.gov (United States)

    ... page: //medlineplus.gov/ency/patientinstructions/000484.htm Epidural block - pregnancy To use the sharing features on this page, please enable JavaScript. An epidural block is a numbing medicine given by injection (shot) ...

  15. Experiments on graphite block gaps connected with leak flow in bottom-core structure of experimental very high-temperature gas-cooled reactor

    International Nuclear Information System (INIS)

    Kikuchi, Kenji; Futakawa, Masatoshi; Takizuka, Takakazu; Kaburaki, Hideo; Sanokawa, Konomo

    1984-01-01

    In order to minimize the leak flow rate of an experimental VHTR (a multi-purpose very high-temperature gas-cooled reactor), the graphite blocks are tightened to reduce the gap distance between blocks by core restrainers surrounded outside of the fixed reflectors of the bottom-core structure and seal elements are placed in the gaps. By using a 1/2.75-scale model of the bottom-core structure, the experiments on the following items have been carried out: a relationship between core restraint force and block gap, a relationship between core restraint force and inclined angle of the model, leak flow characteristics of seal elements etc. The conclusions derived from the experiments are as follows: (1) Core restraint force is significantly effective for decreasing the gap distance between hot plenum blocks, but ineffective for the gap between hot plenum block and fixed reflector. (2) Graphite seal element reduces the leak flow rate from the top surface of hot plenum block into plenum region to one-third. (author)

  16. Fast semivariogram computation using FPGA architectures

    Science.gov (United States)

    Lagadapati, Yamuna; Shirvaikar, Mukul; Dong, Xuanliang

    2015-02-01

    The semivariogram is a statistical measure of the spatial distribution of data and is based on Markov Random Fields (MRFs). Semivariogram analysis is a computationally intensive algorithm that has typically seen applications in the geosciences and remote sensing areas. Recently, applications in the area of medical imaging have been investigated, resulting in the need for efficient real time implementation of the algorithm. The semivariogram is a plot of semivariances for different lag distances between pixels. A semi-variance, γ(h), is defined as the half of the expected squared differences of pixel values between any two data locations with a lag distance of h. Due to the need to examine each pair of pixels in the image or sub-image being processed, the base algorithm complexity for an image window with n pixels is O(n2). Field Programmable Gate Arrays (FPGAs) are an attractive solution for such demanding applications due to their parallel processing capability. FPGAs also tend to operate at relatively modest clock rates measured in a few hundreds of megahertz, but they can perform tens of thousands of calculations per clock cycle while operating in the low range of power. This paper presents a technique for the fast computation of the semivariogram using two custom FPGA architectures. The design consists of several modules dedicated to the constituent computational tasks. A modular architecture approach is chosen to allow for replication of processing units. This allows for high throughput due to concurrent processing of pixel pairs. The current implementation is focused on isotropic semivariogram computations only. Anisotropic semivariogram implementation is anticipated to be an extension of the current architecture, ostensibly based on refinements to the current modules. The algorithm is benchmarked using VHDL on a Xilinx XUPV5-LX110T development Kit, which utilizes the Virtex5 FPGA. Medical image data from MRI scans are utilized for the experiments

  17. Population Blocks.

    Science.gov (United States)

    Smith, Martin H.

    1992-01-01

    Describes an educational game called "Population Blocks" that is designed to illustrate the concept of exponential growth of the human population and some potential effects of overpopulation. The game material consists of wooden blocks; 18 blocks are painted green (representing land), 7 are painted blue (representing water); and the remaining…

  18. Energy efficiency analysis and implementation of AES on an FPGA

    Science.gov (United States)

    Kenney, David

    The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher

  19. Evaluation of CHO Benchmarks on the Arria 10 FPGA using Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-05-23

    The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. Benchmarking of OpenCL-based framework is an effective way for analyzing the performance of system by studying the execution of the benchmark applications. CHO is a suite of benchmark applications that provides support for OpenCL [1]. The authors presented CHO as an OpenCL port of the CHStone benchmark. Using Altera OpenCL (AOCL) compiler to synthesize the benchmark applications, they listed the resource usage and performance of each kernel that can be successfully synthesized by the compiler. In this report, we evaluate the resource usage and performance of the CHO benchmark applications using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board that features an Arria 10 FPGA device. The focus of the report is to have a better understanding of the resource usage and performance of the kernel implementations using Arria-10 FPGA devices compared to Stratix-5 FPGA devices. In addition, we also gain knowledge about the limitations of the current compiler when it fails to synthesize a benchmark

  20. FPGA implementation of a ZigBee wireless network control interface to transmit biomedical signals

    Science.gov (United States)

    Gómez López, M. A.; Goy, C. B.; Bolognini, P. C.; Herrera, M. C.

    2011-12-01

    In recent years, cardiac hemodynamic monitors have incorporated new technologies based on wireless sensor networks which can implement different types of communication protocols. More precisely, a digital conductance catheter system recently developed adds a wireless ZigBee module (IEEE 802.15.4 standards) to transmit cardiac signals (ECG, intraventricular pressure and volume) which would allow the physicians to evaluate the patient's cardiac status in a noninvasively way. The aim of this paper is to describe a control interface, implemented in a FPGA device, to manage a ZigBee wireless network. ZigBee technology is used due to its excellent performance including simplicity, low-power consumption, short-range transmission and low cost. FPGA internal memory stores 8-bit signals with which the control interface prepares the information packets. These data were send to the ZigBee END DEVICE module that receives and transmits wirelessly to the external COORDINATOR module. Using an USB port, the COORDINATOR sends the signals to a personal computer for displaying. Each functional block of control interface was assessed by means of temporal diagrams. Three biological signals, organized in packets and converted to RS232 serial protocol, were sucessfully transmitted and displayed in a PC screen. For this purpose, a custom-made graphical software was designed using LabView.

  1. FPGA implementation of a ZigBee wireless network control interface to transmit biomedical signals

    International Nuclear Information System (INIS)

    López, M A Gómez; Goy, C B; Bolognini, P C; Herrera, M C

    2011-01-01

    In recent years, cardiac hemodynamic monitors have incorporated new technologies based on wireless sensor networks which can implement different types of communication protocols. More precisely, a digital conductance catheter system recently developed adds a wireless ZigBee module (IEEE 802.15.4 standards) to transmit cardiac signals (ECG, intraventricular pressure and volume) which would allow the physicians to evaluate the patient's cardiac status in a noninvasively way. The aim of this paper is to describe a control interface, implemented in a FPGA device, to manage a ZigBee wireless network. ZigBee technology is used due to its excellent performance including simplicity, low-power consumption, short-range transmission and low cost. FPGA internal memory stores 8-bit signals with which the control interface prepares the information packets. These data were send to the ZigBee END DEVICE module that receives and transmits wirelessly to the external COORDINATOR module. Using an USB port, the COORDINATOR sends the signals to a personal computer for displaying. Each functional block of control interface was assessed by means of temporal diagrams. Three biological signals, organized in packets and converted to RS232 serial protocol, were successfully transmitted and displayed in a PC screen. For this purpose, a custom-made graphical software was designed using LabView.

  2. FPGA based computation of average neutron flux and e-folding period for start-up range of reactors

    International Nuclear Information System (INIS)

    Ram, Rajit; Borkar, S.P.; Dixit, M.Y.; Das, Debashis

    2013-01-01

    Pulse processing instrumentation channels used for reactor applications, play a vital role to ensure nuclear safety in startup range of reactor operation and also during fuel loading and first approach to criticality. These channels are intended for continuous run time computation of equivalent reactor core neutron flux and e-folding period. This paper focuses only the computational part of these instrumentation channels which is implemented in single FPGA using 32-bit floating point arithmetic engine. The computations of average count rate, log of average count rate, log rate and reactor period are done in VHDL using digital circuit realization approach. The computation of average count rate is done using fully adaptive window size moving average method, while Taylor series expansion for logarithms is implemented in FPGA to compute log of count rate, log rate and reactor e-folding period. This paper describes the block diagrams of digital logic realization in FPGA and advantage of fully adaptive window size moving average technique over conventional fixed size moving average technique for pulse processing of reactor instrumentations. (author)

  3. Optical network and FPGA/DSP based control system for free electron laser

    International Nuclear Information System (INIS)

    Romaniuk, R.S.; Pozniak, K.T.; Czarski, T.; Czuba, K.; Giergusiewicz, W.; Kasprowicz, G.; Koprek, W.

    2005-01-01

    The work presents a structural and functional model of a distributed low level radio frequency (LLRF) control, diagnostic and telemetric system for a large industrial object. An example of system implementation is the European TESLA-XFEL accelerator. The free electron laser is expected to work in the VUV region now and in the range of X-rays in the future. The design of a system based on the FPGA circuits and multi-gigabit optical network is discussed. The system design approach is fully parametric. The major emphasis is put on the methods of the functional and hardware concentration to use fully both: a very big transmission capacity of the optical fiber telemetric channels and very big processing power of the latest series of DSP/PC enhanced and optical I/O equipped, FPGA chips. The subject of the work is the design of a universal, laboratory module of the LLRF sub-system. The current parameters of the system model, under the design, are presented. The considerations are shown on the background of the system application in the hostile industrial environment. The work is a digest of a few development threads of the hybrid, optoelectronic, telemetric networks (HOTN). In particular, the outline of construction theory of HOTN node was presented as well as the technology of complex, modular, multilayer HOTN system PCBs. The PCBs contain critical sub-systems of the node and the network. The presented exemplary sub-systems are: fast optical data transmission of 2.5 Gbit/s, 3.125 Gbit/s and 10 Gbit/s; fast A/C and C/A multichannel data conversion managed by FPGA chip (40 MHz, 65 MHz, 105 MHz), data and functionality concentration, integration of floating point calculations in the DSP units of FPGA circuit, using now discrete and next integrated PC chip with embedded OS; optical distributed timing system of phase reference; and 1GbEth video interface (over UTP or FX) for CCD telemetry and monitoring. The data and functions concentration in the HOTN node is necessary to

  4. FPGA fault tolerance in particle physics experiments

    Energy Technology Data Exchange (ETDEWEB)

    Gebelein, Jano; Engel, Heiko; Kebschull, Udo [Kirchhoff-Institute for Physics, Heidelberg University (Germany)

    2010-07-01

    The behavior of matter in physically extreme conditions is in focus of many high-energy-physics experiments. For this purpose, high energy charged particles (ions) are collided with each other and energy- or baryon densities are created similar to those at the beginning of the universe or to those which can be found in the center of neutron stars. In both cases a plasma of quarks and gluons (QGP) is present, which immediately decomposes to hadrons within a short period of time. At this process, particles are formed, which allow statements about the beginning of the universe when captured by large detectors, but which also lead to the massive occurance of hardware failures within the detector's electronic devices. This contribution is about methods to mitigate radiation susceptibility for Field Programmable Gate Arrays (FPGA), enabling them to be used within particle detector systems to directly gain valid data in the readout chain or to be used as detector-control-system.

  5. IMPLEMENTATION OF NEURAL - CRYPTOGRAPHIC SYSTEM USING FPGA

    Directory of Open Access Journals (Sweden)

    KARAM M. Z. OTHMAN

    2011-08-01

    Full Text Available Modern cryptography techniques are virtually unbreakable. As the Internet and other forms of electronic communication become more prevalent, electronic security is becoming increasingly important. Cryptography is used to protect e-mail messages, credit card information, and corporate data. The design of the cryptography system is a conventional cryptography that uses one key for encryption and decryption process. The chosen cryptography algorithm is stream cipher algorithm that encrypt one bit at a time. The central problem in the stream-cipher cryptography is the difficulty of generating a long unpredictable sequence of binary signals from short and random key. Pseudo random number generators (PRNG have been widely used to construct this key sequence. The pseudo random number generator was designed using the Artificial Neural Networks (ANN. The Artificial Neural Networks (ANN providing the required nonlinearity properties that increases the randomness statistical properties of the pseudo random generator. The learning algorithm of this neural network is backpropagation learning algorithm. The learning process was done by software program in Matlab (software implementation to get the efficient weights. Then, the learned neural network was implemented using field programmable gate array (FPGA.

  6. Video Watermarking Implementation Based on FPGA

    International Nuclear Information System (INIS)

    EL-ARABY, W.S.M.S.

    2012-01-01

    The sudden increase in watermarking interest is most likely due to the increase in concern over copyright protection of content. With the rapid growth of the Internet and the multimedia systems in distributed environments, digital data owners are now easier to transfer multimedia documents across the Internet. However, current technology does not protect their copyrights properly. This leads to wide interest of multimedia security and multimedia copyright protection and it has become a great concern to the public in recent years. In the early days, encryption and control access techniques were used to protect the ownership of media. Recently, the watermarking techniques are utilized to keep safely the copyrights. In this thesis, a fast and secure invisible video watermark technique has been introduced. The technique based mainly on DCT and Low Frequency using pseudo random number (PN) sequence generator for embedding algorithm. The system has been realized using VHDL and the results have been verified using MATLAB. The implementation of the introduced watermark system done using Xilinx chip (XCV800). The implementation results show that the total area of watermark technique is 45% of total FPGA area with maximum delay equals 16.393ns. The experimental results show that the two techniques have mean square error (MSE) equal to 0.0133 and peak signal to noise ratio (PSNR) equal to 66.8984db. The results have been demonstrated and compared with conventional watermark technique using DCT.

  7. FPGA Congestion-Driven Placement Refinement

    Energy Technology Data Exchange (ETDEWEB)

    Vicente de, J.

    2005-07-01

    The routing congestion usually limits the complete proficiency of the FPGA logic resources. A key question can be formulated regarding the benefits of estimating the congestion at placement stage. In the last years, it is gaining acceptance the idea of a detailed placement taking into account congestion. In this paper, we resort to the Thermodynamic Simulated Annealing (TSA) algorithm to perform a congestion-driven placement refinement on the top of the common Bounding-Box pre optimized solution. The adaptive properties of TSA allow the search to preserve the solution quality of the pre optimized solution while improving other fine-grain objectives. Regarding the cost function two approaches have been considered. In the first one Expected Occupation (EO), a detailed probabilistic model to account for channel congestion is evaluated. We show that in spite of the minute detail of EO, the inherent uncertainty of this probabilistic model impedes to relieve congestion beyond the sole application of the Bounding-Box cost function. In the second approach we resort to the fast Rectilinear Steiner Regions algorithm to perform not an estimation but a measurement of the global routing congestion. This second strategy allows us to successfully reduce the requested channel width for a set of benchmark circuits with respect to the widespread Versatile Place and Route (VPR) tool. (Author) 31 refs.

  8. Multi-Softcore Architecture on FPGA

    Directory of Open Access Journals (Sweden)

    Mouna Baklouti

    2014-01-01

    Full Text Available To meet the high performance demands of embedded multimedia applications, embedded systems are integrating multiple processing units. However, they are mostly based on custom-logic design methodology. Designing parallel multicore systems using available standards intellectual properties yet maintaining high performance is also a challenging issue. Softcore processors and field programmable gate arrays (FPGAs are a cheap and fast option to develop and test such systems. This paper describes a FPGA-based design methodology to implement a rapid prototype of parametric multicore systems. A study of the viability of making the SoC using the NIOS II soft-processor core from Altera is also presented. The NIOS II features a general-purpose RISC CPU architecture designed to address a wide range of applications. The performance of the implemented architecture is discussed, and also some parallel applications are used for testing speedup and efficiency of the system. Experimental results demonstrate the performance of the proposed multicore system, which achieves better speedup than the GPU (29.5% faster for the FIR filter and 23.6% faster for the matrix-matrix multiplication.

  9. Substantiation of the Fault-Block Structure for Effective Additional Exploration and Development of the West-Kommunarsky Field

    Directory of Open Access Journals (Sweden)

    M.A. Lobusev

    2017-08-01

    Full Text Available While the seismic exploration and methodological geological interpretation of geological data for drilling various wells and other types of research are improved for a significant part of the fields being developed in the Samara Region, the reliability of the structure of geological and recoverable oil and gas reserves increases. The complication of the structure and multiple recalculations of reserves at a number of fields are due to the introduction into the development of undiscovered to the required conditions of complex geological fields and licensed areas. The example of the West-Kommunarsky field shows how its geological structure becomes more complex as its study becomes more extensive. Thus, the oil reservoir in the Lower Paschian sediments, according to the created integrated model, has horizontal positions, but with different levels of water-oil contact in adjacent blocks separated by downthrows. The justification of disjunctive dislocations, which have been planned but not tracked due to their uncertainty in seismic data and determination of their main characteristics, was performed by stratigraphic correlation of well sections using the rules of projective geometry and confirmed by other traditional methodical methods. With each new tectonic movement along the strike-slip, a near-faul fracture of rocks is formed parallel to it, as a reflection of geodynamic stresses and energy-intensive processes in the downthrows and strike-slips of rocks along the fault plane. Near-fault regular changes in the fracturing of rocks and the dependence of well productivity on their location relative to the disjunctive make it possible to predict the latitudinal reservoirs zonation in near-fault area: fractured, porous-fractured, fractured-porous and porous types. Such a dialectical process of movement towards a real model of the field ensures the reliability of revised reserves and updated technological documents for the development of fields.

  10. The influence of polarity of additive molecules on micelle structures of polystyrene-block-poly(4-vinylpyridine) in the fabrication of nano-porous templates.

    Science.gov (United States)

    Chua, Kee Sze; Koh, Ai Peng; Lam, Yeng Ming

    2010-11-01

    Block copolymers are useful for in situ synthesis of nanoparticles as well as producing nanoporous templates. As such, the effects of precursors on the block copolymer micelle structure is important. In this study, we investigate the effects of polarity of molecules introduced into block copolymer micelle cores on the micelle structure. The molecular dipole moment of the additive molecules has been evaluated and their effects on the block copolymer micelles investigated using light scattering spectroscopy, small-angle X-ray scattering, transmission electron microscopy and atomic force microscopy. The molecule with the largest dipole moment resulted in spherical structures with a polydispersity of less than 0.06 in a fully translational diffusion system. Surprisingly, the less polar additive molecules produced elongated micelles and the aspect ratio increases with decreasing polarity. The change in structure from spherical to elongated structure was attributed to P4VP chain extension, where compounds with polarity most similar to P4VP induce the most chain extension. The second virial coefficients of the solutions with elongated micelles are lower than that for spherical micelle systems by up to one order in magnitude, indicating a strong tendency for micelles to coalesce. On rinsing the spin-cast films, pores were obtained from spherical micelles and ridges from elongated micelles, suggesting a viable alternative for morphology modification using mild conditions where external annealing treatments to the film are not preferred. The knowledge of polarity effects of additive molecules on micelle structure has wider implications for supramolecular block copolymer systems where, depending on the application requirements, changes to the shape of the micelle structure can be induced or avoided. Copyright 2010 Elsevier Inc. All rights reserved.

  11. Structures of PEP–PEO Block Copolymer Micelles: Effects of Changing Solvent and PEO Length and Comparison to a Thermodynamic Model

    DEFF Research Database (Denmark)

    Jensen, Grethe Vestergaard; Shi, Qing; Deen, G. Roshan

    2012-01-01

    Structures of poly(ethylene propylene)–poly(ethylene oxide) (PEP–PEO) block copolymer micelles were determined from small-angle X-ray scattering and static light scattering and compared to predictions from a thermodynamic model. Both the corona block length and the solvent water–ethanol ratio were...... changed, leading to a thorough test of this model. With increasing ethanol fraction, the PEP core–solvent interfacial tension decreases, and the solvent quality for PEO changes. The weight-average block masses were 5.0 kDa for PEP and 2.8–49 kDa for PEO. For the lowest PEO molar mass and samples in pure...... water (except for the highest PEO molar mass), the micelles were cylindrical; for other conditions they were spherical. The structural parameters can be reasonably well described by the thermodynamic model by Zhulina et al. [Macromolecules2005, 38 (12), 5330–5351]; however, they have a stronger...

  12. Embedded system in FPGA-based LLRF controller for FLASH

    Science.gov (United States)

    Szewinski, Jaroslaw; Pucyk, Piotr; Jalmuzna, Wojciech; Fafara, Przemyslaw; Pieciukiewicz, Marcin; Romaniuk, Ryszard; Pozniak, Krzysztof T.

    2006-10-01

    FPGA devices are often used in High Energy Physics and accelerator technology experiments, where the highest technologies are needed. To make FPGA based systems more flexible, common technique is to provide SoC (System on a Chip) solution in the FPGA, which is in most cases a CPU unit. Such a combination gives possibility to balance between hardware and software implementation of particular task. SoC solution on FPGA can be very flexible, because in simplest cases no additional hardware is needed to run programs on CPU, and when system has such devices like UART, SDRAM memory, mass storage and network interface, it can handle full featured operating system such as Linux or VxWorks. Embedded process can be set up in different configurations, depending on the available resources on board, so every user can adjust system to his own needs. Embedded systems can be also used to perform partial self-reconfiguration of FPGA logic of the chip, on which the system is running. This paper will also present some results on SoC implementations in a Low Level RF system under design for the VUV Free Electron Laser, FLASH, DESY, Hamburg.

  13. FAS: Using FPGA to Accelerate and Secure SDN Software Switches

    Directory of Open Access Journals (Sweden)

    Wenwen Fu

    2018-01-01

    Full Text Available Software-Defined Networking (SDN promises the vision of more flexible and manageable networks but requires certain level of programmability in the data plane to accommodate different forwarding abstractions. SDN software switches running on commodity multicore platforms are programmable and are with low deployment cost. However, the performance of SDN software switches is not satisfactory due to the complex forwarding operations on packets. Moreover, this may hinder the performance of real-time security on software switch. In this paper, we analyze the forwarding procedure and identify the performance bottleneck of SDN software switches. An FPGA-based mechanism for accelerating and securing SDN switches, named FAS (FPGA-Accelerated SDN software switch, is proposed to take advantage of the reconfigurability and high-performance advantages of FPGA. FAS improves the performance as well as the capacity against malicious traffic attacks of SDN software switches by offloading some functional modules. We validate FAS on an FPGA-based network processing platform. Experiment results demonstrate that the forwarding rate of FAS can be 44% higher than the original SDN software switch. In addition, FAS provides new opportunity to enhance the security of SDN software switches by allowing the deployment of bump-in-the-wire security modules (such as packet detectors and filters in FPGA.

  14. Perpendicular Structure Formation of Block Copolymer Thin Films during Thermal Solvent Vapor Annealing: Solvent and Thickness Effects

    Directory of Open Access Journals (Sweden)

    Qiuyan Yang

    2017-10-01

    Full Text Available Solvent vapor annealing of block copolymer (BCP thin films can produce a range of interesting morphologies, especially when the perpendicular orientation of micro-domains with respect to the substrate plays a role. This, for instance, allows BCP thin films to serve as useful templates for nanolithography and hybrid materials preparation. However, precise control of the arising morphologies is essential, but in most cases difficult to achieve. In this work, we investigated the solvent and thickness effects on the morphology of poly(styrene-b-2 vinyl pyridine (PS-b-P2VP thin films with a film thickness range from 0.4 L0 up to 0.8 L0. Ordered perpendicular structures were achieved. One of the main merits of our work is that the phase behavior of the ultra-high molecular weight BCP thin films, which hold a 100-nm sized domain distance, can be easily monitored via current available techniques, such as scanning electron microscope (SEM, atomic force microscope (AFM, and transmission electron microscope (TEM. Systematic monitoring of the self-assembly behavior during solvent vapor annealing can thus provide an experimental guideline for the optimization of processing conditions of related BCP films systems.

  15. Development of an FPGA-based multipoint laser pyroshock measurement system for explosive bolts

    International Nuclear Information System (INIS)

    Abbas, Syed Haider; Lee, Jung-Ryul; Jang, Jae-Kyeong; Kim, Zaeill

    2016-01-01

    Pyroshock can cause failure to the objective of an aerospace structure by damaging its sensitive electronic equipment, which is responsible for performing decisive operations. A pyroshock is the high intensity shock wave that is generated when a pyrotechnic device is explosively triggered to separate, release, or activate structural subsystems of an aerospace architecture. Pyroshock measurement plays an important role in experimental simulations to understand the characteristics of pyroshock on the host structure. This paper presents a technology to measure a pyroshock wave at multiple points using laser Doppler vibrometers (LDVs). These LDVs detect the pyroshock wave generated due to an explosive-based pyrotechnical event. Field programmable gate array (FPGA) based data acquisition is used in the study to acquire pyroshock signals simultaneously from multiple channels. This paper describes the complete system design for multipoint pyroshock measurement. The firmware architecture for the implementation of multichannel data acquisition on an FPGA-based development board is also discussed. An experiment using explosive bolts was configured to test the reliability of the system. Pyroshock was generated using explosive excitation on a 22-mm-thick steel plate. Three LDVs were deployed to capture the pyroshock wave at different points. The pyroshocks captured were displayed as acceleration plots. The results showed that our system effectively captured the pyroshock wave with a peak-to-peak magnitude of 303 741 g. The contribution of this paper is a specialized architecture of firmware design programmed in FPGA for data acquisition of large amount of multichannel pyroshock data. The advantages of the developed system are the near-field, multipoint, non-contact, and remote measurement of a pyroshock wave, which is dangerous and expensive to produce in aerospace pyrotechnic tests.

  16. Development of an FPGA-based multipoint laser pyroshock measurement system for explosive bolts

    Energy Technology Data Exchange (ETDEWEB)

    Abbas, Syed Haider; Lee, Jung-Ryul [Department of Aerospace Engineering, Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of); Jang, Jae-Kyeong [The Engineering Institute-Korea, Chonbuk National University, Jeonju (Korea, Republic of); Kim, Zaeill [The 4th R& D Institute-1st directorate, Agency for Defense Development, Daejeon (Korea, Republic of)

    2016-07-15

    Pyroshock can cause failure to the objective of an aerospace structure by damaging its sensitive electronic equipment, which is responsible for performing decisive operations. A pyroshock is the high intensity shock wave that is generated when a pyrotechnic device is explosively triggered to separate, release, or activate structural subsystems of an aerospace architecture. Pyroshock measurement plays an important role in experimental simulations to understand the characteristics of pyroshock on the host structure. This paper presents a technology to measure a pyroshock wave at multiple points using laser Doppler vibrometers (LDVs). These LDVs detect the pyroshock wave generated due to an explosive-based pyrotechnical event. Field programmable gate array (FPGA) based data acquisition is used in the study to acquire pyroshock signals simultaneously from multiple channels. This paper describes the complete system design for multipoint pyroshock measurement. The firmware architecture for the implementation of multichannel data acquisition on an FPGA-based development board is also discussed. An experiment using explosive bolts was configured to test the reliability of the system. Pyroshock was generated using explosive excitation on a 22-mm-thick steel plate. Three LDVs were deployed to capture the pyroshock wave at different points. The pyroshocks captured were displayed as acceleration plots. The results showed that our system effectively captured the pyroshock wave with a peak-to-peak magnitude of 303 741 g. The contribution of this paper is a specialized architecture of firmware design programmed in FPGA for data acquisition of large amount of multichannel pyroshock data. The advantages of the developed system are the near-field, multipoint, non-contact, and remote measurement of a pyroshock wave, which is dangerous and expensive to produce in aerospace pyrotechnic tests.

  17. Study of matrix micro-cracking in nano clay and acrylic tri-block-copolymer modified epoxy/basalt fiber-reinforced pressure-retaining structures

    Directory of Open Access Journals (Sweden)

    2011-10-01

    Full Text Available In fiber-reinforced polymer pressure-retaining structures, such as pipes and vessels, micro-level failure commonly causes fluid permeation due to matrix cracking. This study explores the effect of nano-reinforcements on matrix cracking in filament-wound basalt fiber/epoxy composite structures. The microstructure and mechanical properties of bulk epoxy nanocomposites and hybrid fiber-reinforced composite pipes modified with acrylic tri-block-copolymer and organophilic layered silicate clay were investigated. In cured epoxy, the tri-block-copolymer phase separated into disordered spherical micelle inclusions; an exfoliated and intercalated structure was observed for the nano-clay. Block-copolymer addition significantly enhanced epoxy fracture toughness by a mechanism of particle cavitation and matrix shear yielding, whereas toughness remained unchanged in nano-clay filled nanocomposites due to the occurrence of lower energy resistance phenomena such as crack deflection and branching.Tensile stiffness increased with nano-clay content, while it decreased slightly for block-copolymer modified epoxy. Composite pipes modified with either the organic and inorganic nanoparticles exhibited moderate improvements in leakage failure strain (i.e. matrix cracking strain; however, reductions in functional and structural failure strength were observed.

  18. High performance integer arithmetic circuit design on FPGA architecture, implementation and design automation

    CERN Document Server

    Palchaudhuri, Ayan

    2016-01-01

    This book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs). It explores regular, modular, cascadable, and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary “User Constraints File”. The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from us...

  19. High-frequency, three-phase current controller implementation in an FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Hartmann, M.; Round, S. D.; Kolar, J. W.

    2008-07-01

    Three phase rectifiers with switching frequencies of 500 kHz or more require high speed current controllers. At such high switching frequencies analog controllers as well as high speed digital signal processing (DSP) systems have limited performance. In this paper, two high speed current controller implementations using two different field-programmable gate arrays (FPGA) - one for switching frequencies up to 1 MHz and one for switching frequencies beyond 1 MHz - are presented to overcome this performance limitation. Starting with the digital system design all the blocks of the signal chain, containing analog-to-digital (A/D) interface, digital controller implementation using HW-multipliers and implementation of a novel high speed, high resolution pulse width modulation (PWM) are discussed and compared. Final measurements verify the performance of the controllers. (author)

  20. A low-power wave union TDC implemented in FPGA

    International Nuclear Information System (INIS)

    Wu, Jinyuan; Shi, Yanchen; Zhu, Douglas

    2011-01-01

    A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

  1. FPGA-Based Implementation of Lithuanian Isolated Word Recognition Algorithm

    Directory of Open Access Journals (Sweden)

    Tomyslav Sledevič

    2013-05-01

    Full Text Available The paper describes the FPGA-based implementation of Lithuanian isolated word recognition algorithm. FPGA is selected for parallel process implementation using VHDL to ensure fast signal processing at low rate clock signal. Cepstrum analysis was applied to features extraction in voice. The dynamic time warping algorithm was used to compare the vectors of cepstrum coefficients. A library of 100 words features was created and stored in the internal FPGA BRAM memory. Experimental testing with speaker dependent records demonstrated the recognition rate of 94%. The recognition rate of 58% was achieved for speaker-independent records. Calculation of cepstrum coefficients lasted for 8.52 ms at 50 MHz clock, while 100 DTWs took 66.56 ms at 25 MHz clock.Article in Lithuanian

  2. Flexible, fpga-based electronics for modular robots

    DEFF Research Database (Denmark)

    Brandt, David; Larsen, Jørgen Christian; Christensen, David Johan

    2008-01-01

    In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays (FPGAs). The immediate advantage of using FPGAs is that some of the module’s electronics can be moved into the FPGA, thereby the number of components can be reduced. In the case...... the FPGA and therefore integrate task-specific electronics without physically changing the electronics or we can reconfigure the electronics for specific tasks. The disadvantages of an FPGA-based design include the cost of FPGAs, the extra layer of complexity in programming, and a limited increase in power...... consumption compared to micro-controllers. However, overall FPGAs make the electronics of modular robots more flexible and therefore may make them more suitable for real applications. AB - In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays...

  3. FPGA development board for applications in cosmic rays physics

    International Nuclear Information System (INIS)

    Angelov, Ivo; Damov, Krasimir; Dimitrova, Svetla

    2013-01-01

    The modern experiments in cosmic rays and particle physics are usually performed with large number of detectors and signal processing have to be done by complex electronics. The analog signals from the detectors are converted to digital (by discriminators or fast ADC) and connected to different type of logic implemented in FPGA (Field Programmable Gate Arrays). A FPGA development board based on Xilinx XC3S50AN was designed, assembled and tested. The board will be used for developing a modern registering controller (to replace the existing now) for the muon telescope in the University and can be used for other experiments in cosmic rays physics when fast digital pulses have to be processed. Keywords: FPGA, Spartan3A, muon telescope, cosmic rays variations

  4. Porting VIRTEX4 data acquisition design to SPARTAN6 FPGA

    International Nuclear Information System (INIS)

    Suetoe, J.; Hegyesi, G.

    2012-01-01

    Complete text of publication follows. The Atomki's Virtex 4 based 4 channel data acquisition card (LIR) card was used in many applications (miniPET-II, miniPET-III, data acquisition system for the multichannel plate installed at the ECR lab). The goal of the work was to improve the LIR using a higher performance FPGA (Spartan6 Trenz module). The Trenz module based system also supports ADC channels up to 16 channels. This work also implied the porting of the Virtex4 based VHDL code to Spartan 6. Further advantage of the proposed system, besides the improvement in the number of ADC channels, that the Spartan6 FPGA is able to run more complex digital signal processing algorithms than the Virtex 4 FPGA. Easy access to the control parameters (via serial interface or Ethernet), flexibility and high performance were considered during the development. SPARTAN6 FPGA based data acquisition provides more facilities than the VIRTEX4 based. SPARTAN6 is a newer generation of XILINX’s FPGAs, which excellent into the high-speed data acquisition. We ported the HDL code, which runs on LIR module (VIRTEX4 based), to the Trenz module (SPARTAN6 based). The main parts of the whole program code are the command line interpreter, GMII interface, DHCP process, ARP process and the data read out. Those parts were implemented by picoblaze embedded system. Figure 1 shows the command line interpreter process in the Hyper Terminal. The command line interpreter communicates with the PC via serial port. In addition, the AdamIOSetting software also use the serial communication, which was created to the VIRTEX FPGA based data collector. In the Wireshark network analyzer software we examined the DHCP and ARP process and using the AdamIOSettings software we tested the data read out from the flash memory of FPGA board. Figure 2 shows the AdamIOSettings program. Acknowledgements. This work was supported by the ENIAC CSI Project (No.120209).

  5. Design improvement of FPGA and CPU based digital circuit cards to solve timing issues

    International Nuclear Information System (INIS)

    Lee, Dongil; Lee, Jaeki; Lee, Kwang-Hyun

    2016-01-01

    The digital circuit cards installed at NPPs (Nuclear Power Plant) are mostly composed of a CPU (Central Processing Unit) and a PLD (Programmable Logic Device; these include a FPGA (Field Programmable Gate Array) and a CPLD (Complex Programmable Logic Device)). This type of structure is typical and is maintained using digital circuit cards. There are no big problems with this device as a structure. In particular, signal delay causes a lot of problems when various IC (Integrated Circuit) and several circuit cards are connected to the BUS of the backplane in the BUS design. This paper suggests a structure to improve the BUS signal timing problems in a circuit card consisting of CPU and FPGA. Nowadays, as the structure of circuit cards has become complex and mass data at high speed is communicated through the BUS, data integrity is the most important issue. The conventional design does not consider delay and the synchronicity of signal and this causes many problems in data processing. In order to solve these problems, it is important to isolate the BUS controller from the CPU and maintain constancy of the signal delay by using a PLD

  6. Design improvement of FPGA and CPU based digital circuit cards to solve timing issues

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Dongil; Lee, Jaeki; Lee, Kwang-Hyun [KHNP CRI, Daejeon (Korea, Republic of)

    2016-10-15

    The digital circuit cards installed at NPPs (Nuclear Power Plant) are mostly composed of a CPU (Central Processing Unit) and a PLD (Programmable Logic Device; these include a FPGA (Field Programmable Gate Array) and a CPLD (Complex Programmable Logic Device)). This type of structure is typical and is maintained using digital circuit cards. There are no big problems with this device as a structure. In particular, signal delay causes a lot of problems when various IC (Integrated Circuit) and several circuit cards are connected to the BUS of the backplane in the BUS design. This paper suggests a structure to improve the BUS signal timing problems in a circuit card consisting of CPU and FPGA. Nowadays, as the structure of circuit cards has become complex and mass data at high speed is communicated through the BUS, data integrity is the most important issue. The conventional design does not consider delay and the synchronicity of signal and this causes many problems in data processing. In order to solve these problems, it is important to isolate the BUS controller from the CPU and maintain constancy of the signal delay by using a PLD.

  7. Multifunctional data acquisition system based on USB and FPGA

    International Nuclear Information System (INIS)

    Huang Tuchen; Gong Hui; Shao Beibei

    2013-01-01

    A multifunctional data acquisition system based on USB and FPGA was developed. The system has four analog inputs digitalized by fast ADC. Based on flexibility of FPGA, different functions can be implemented such as waveform sampling, pulse counting, multi-channel pulse height analysis, and charge division readout process. The hardware communicates with host PC via USB interface. The Labview based user soft ware initializes the hardware, configures the running parameters, reads and processes the data as well as displays the result online. (authors)

  8. VIRTEX-5 Fpga Implementation of Advanced Encryption Standard Algorithm

    Science.gov (United States)

    Rais, Muhammad H.; Qasim, Syed M.

    2010-06-01

    In this paper, we present an implementation of Advanced Encryption Standard (AES) cryptographic algorithm using state-of-the-art Virtex-5 Field Programmable Gate Array (FPGA). The design is coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL). Timing simulation is performed to verify the functionality of the designed circuit. Performance evaluation is also done in terms of throughput and area. The design implemented on Virtex-5 (XC5VLX50FFG676-3) FPGA achieves a maximum throughput of 4.34 Gbps utilizing a total of 399 slices.

  9. Design and FPGA Implementation of a new hyperchaotic system

    International Nuclear Information System (INIS)

    Wang Guangyi; Bao Xulei; Wang Zhonglin

    2008-01-01

    In this paper, a new four-dimensional autonomous hyperchaotic system is designed for generating complex chaotic signals. In the design, its parameters are selected according to the requirements for chaos and hyperchaos. The hyperchaotic Nature is verified theoretically by using the bifurcation analysis and demonstrated experimentally by the implementation of an analogue electronic circuit. Moreover, the Field Programmable Gate Array (FPGA) technology is applied to implementing a continuous system in a digital form by using a chip of Altera Cyclone II EP2C35F484C8. The digital sequence generated from the FPGA device is observed in our experimental setup. (general)

  10. B-DCGAN:Evaluation of Binarized DCGAN for FPGA

    OpenAIRE

    Terada, Hideo; Shouno, Hayaru

    2018-01-01

    We are trying to implement deep neural networks in the edge computing environment for real-world applications such as the IoT(Internet of Things), the FinTech etc., for the purpose of utilizing the significant achievement of Deep Learning in recent years. Especially, we now focus algorithm implementation on FPGA, because FPGA is one of the promising devices for low-cost and low-power implementation of the edge computer. In this work, we introduce Binary-DCGAN(B-DCGAN) - Deep Convolutional GAN...

  11. Using FPGA coprocessor for ATLAS level 2 trigger application

    International Nuclear Information System (INIS)

    Khomich, Andrei; Hinkelbein, Christian; Kugel, Andreas; Maenner, Reinhard; Mueller, Matthias

    2006-01-01

    Tracking has a central role in the event selection for the High-Level Triggers of ATLAS. It is particularly important to have fast tracking algorithms in the trigger system. This paper investigates the feasibility of using FPGA coprocessor for speeding up of the TRT LUT algorithm-one of the tracking algorithms for second level trigger for ATLAS experiment (CERN). Two realisations of the same algorithm have been compared: one in C++ and a hybrid C++/VHDL implementation. Using a FPGA coprocessor gives an increase of speed by a factor of two compared to a CPU-only implementation

  12. FPGA Implementation of a Frame Synchronization Algorithm for Powerline Communications

    Directory of Open Access Journals (Sweden)

    S. Tsakiris

    2009-09-01

    Full Text Available This paper presents an FPGA implementation of a pilot–based time synchronization scheme employing orthogonal frequency division multiplexing for powerline communication channels. The functionality of the algorithm is analyzed and tested over a real powerline residential network. For this purpose, an appropriate transmitter circuit, implemented by an FPGA, and suitable coupling circuits are constructed. The system has been developed using VHDL language on Nallatech XtremeDSP development kits. The communication system operates in the baseband up to 30 MHz. Measurements of the algorithm's good performance in terms of the number of detected frames and timing offset error are taken and compared to simulations of existing algorithms.

  13. Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems

    Directory of Open Access Journals (Sweden)

    Bhattacharyya Shuvra S

    2003-01-01

    Full Text Available We introduce the Logic Foundry, a system for the rapid creation and integration of FPGA-based digital signal processing systems. Recognizing that some of the greatest challenges in creating FPGA-based systems occur in the integration of the various components, we have proposed a system that targets the following four areas of integration: design flow integration, component integration, platform integration, and software integration. Using the Logic Foundry, a system can be easily specified, and then automatically constructed and integrated with system level software.

  14. FPGA prototyping by Verilog examples Xilinx Spartan-3 version

    CERN Document Server

    Chu, Pong P

    2008-01-01

    FPGA Prototyping Using Verilog Examples will provide you with a hands-on introduction to Verilog synthesis and FPGA programming through a "learn by doing" approach. By following the clear, easy-to-understand templates for code development and the numerous practical examples, you can quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify the operation of its physical implementation. This introductory text that will provide you with a solid foundation, instill confidence with rigorous examples for complex systems and prepare you for future development tasks.

  15. Study on the relationship of the fault-block structure feature and sandstone uranium formation in Chaoshui basin north belt

    International Nuclear Information System (INIS)

    Liu Lin

    2006-12-01

    The mineralization conditions for three types of acclivity belt (Baojia Jing A' Lashan Youqi-Tangjia Gou and Taojia Jing CHAOSHUI BASIN NORTH BELT) are analyzed, according to the fault-block acclivity belt, the prospecting goal layer, the interlayer oxidized zone and uranium metallization characteristic and so on. It is considered that the positive fault-block acclivity belt favors containing oxygen and uranium water coming from eclipse source area to go into prospecting goal layer, and advanced the formation of interlayer oxidized zone and sandstone uranium metallization. The antithetic fault-block and the buried fault-block acclivity don't favors containing oxygen and uranium water into prospecting goal layer, and format difficultly interlayer oxidized belt and sandstone uranium metallization. Therefore A'Lashan Youqi-Tangjia Gou part is a uranium mineralization prospect sector. (authors)

  16. Principles of building and assembly technology of containment from steel structural blocks for WWER 1000 nuclear power plant

    International Nuclear Information System (INIS)

    Eichstedt, J.; Friedrich, F.

    1983-01-01

    This technology is being developed in cooperation between the USSR and the GDR. The cylindrical part of the containment consists of prefabricated double-sided steel blocks with inner reinforcement. The steel plates in a thickness of 20 mm provide casing and secure tightness. Blocks with one steel wall are used for the construction of the cupola. The outer slabs are assembled subsequently. The methods of assembly, concreting and quality assurance are described. (Ha)

  17. Structure of PEP-PEO block copolymer micelles: Exploiting the complementarity of small-angle X-ray scattering and static light scattering

    DEFF Research Database (Denmark)

    Jensen, Grethe Vestergaard; Shi, Qing; Hernansanz, María J.

    2011-01-01

    )-b-poly(ethylene oxide) (PEP-PEO) in a 70% ethanol solution are investigated. The polymers have identical PEP blocks of 5.0 kDa and varying PEO blocks of 2.8-49 kDa. The SLS contrasts of PEP and PEO are similar, providing a homogeneous contrast, making SLS ideal for determining the overall micelle morphology. The SAXS...... contrasts of the two components are very different, allowing for resolution of the internal micelle structure. A core-shell model with a PEP core and PEO corona is fitted simultaneously to the SAXS and SLS data using the different contrasts of the two blocks for each technique. With increasing PEO molecular...

  18. Fabrication of honeycomb-structured poly(ethylene glycol)-block-poly(lactic acid) porous films and biomedical applications for cell growth

    Energy Technology Data Exchange (ETDEWEB)

    Yao, Bingjian [Key Laboratory of Special Functional Aggregated Materials, Ministry of Education, School of Chemistry and Chemical Engineering, Shandong University, Jinan 250199 (China); College of chemistry, Chemical Engineering and Materials Science, Collaborative Innovation Center of Functionalized Probes for Chemical Imaging, Key Laboratory of Molecular and Nano Probes, Ministry of Education, Shandong Normal University, Jinan 250014 (China); Zhu, Qingzeng, E-mail: qzzhu@sdu.edu.cn [Key Laboratory of Special Functional Aggregated Materials, Ministry of Education, School of Chemistry and Chemical Engineering, Shandong University, Jinan 250199 (China); Yao, Linli [Key Laboratory of the Ministry of Education for Experimental Teratology, Department of Histology and Embryology, Shandong University School of Medicine, 250012 Jinan (China); Hao, Jingcheng [Key Laboratory of Special Functional Aggregated Materials, Ministry of Education, School of Chemistry and Chemical Engineering, Shandong University, Jinan 250199 (China)

    2015-03-30

    Graphical abstract: - Highlights: • Honeycomb-structured PEG-PLA porous films were fabricated. • The organization of pores depends on molecular weight ratio of PEG-to-PLA block. • The pores in the film were internally decorated with a layer of PEG. • The honeycomb-structured PEG-PLA film was suitable as a substrate for cell growth. - Abstract: A series of poly(ethylene glycol)-block-poly(lactic acid) (PEG-PLA) copolymers with a hydrophobic PLA block of different molecular weights and a fixed length hydrophilic PEG were synthesized successfully and characterized. These amphiphilic block copolymers were used to fabricate honeycomb-structured porous films using the breath figure (BF) templating technique. The surface topology and composition of the highly ordered pattern film were further characterized by scanning electron microscopy (SEM), atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS) and fluorescence microscopy. The results indicated that the PEG-to-PLA block molecular weight ratio influenced the BF film surface topology. The film with the best ordered pores was obtained with a PEG-to-PLA ratio of 2.0 × 10{sup 3}:3.0 × 10{sup 4}. The self-organization of the hydrophilic PEG chains within the pores was confirmed by XPS and fluorescence labeled PEG. A model is proposed to elucidate the stabilization process of the amphiphilic PEG-PLA aggregated architecture on the water droplet-based templates. In addition, GFP-U87 cell viability has been investigated by MTS test and the cell morphology on the honeycomb-structured PEG-PLA porous film has been evaluated using phase-contrast microscope. This porous film is shown to be suitable as a matrix for cell growth.

  19. Fabrication of honeycomb-structured poly(ethylene glycol)-block-poly(lactic acid) porous films and biomedical applications for cell growth

    International Nuclear Information System (INIS)

    Yao, Bingjian; Zhu, Qingzeng; Yao, Linli; Hao, Jingcheng

    2015-01-01

    Graphical abstract: - Highlights: • Honeycomb-structured PEG-PLA porous films were fabricated. • The organization of pores depends on molecular weight ratio of PEG-to-PLA block. • The pores in the film were internally decorated with a layer of PEG. • The honeycomb-structured PEG-PLA film was suitable as a substrate for cell growth. - Abstract: A series of poly(ethylene glycol)-block-poly(lactic acid) (PEG-PLA) copolymers with a hydrophobic PLA block of different molecular weights and a fixed length hydrophilic PEG were synthesized successfully and characterized. These amphiphilic block copolymers were used to fabricate honeycomb-structured porous films using the breath figure (BF) templating technique. The surface topology and composition of the highly ordered pattern film were further characterized by scanning electron microscopy (SEM), atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS) and fluorescence microscopy. The results indicated that the PEG-to-PLA block molecular weight ratio influenced the BF film surface topology. The film with the best ordered pores was obtained with a PEG-to-PLA ratio of 2.0 × 10 3 :3.0 × 10 4 . The self-organization of the hydrophilic PEG chains within the pores was confirmed by XPS and fluorescence labeled PEG. A model is proposed to elucidate the stabilization process of the amphiphilic PEG-PLA aggregated architecture on the water droplet-based templates. In addition, GFP-U87 cell viability has been investigated by MTS test and the cell morphology on the honeycomb-structured PEG-PLA porous film has been evaluated using phase-contrast microscope. This porous film is shown to be suitable as a matrix for cell growth

  20. CAN and FPGA communication engineering implementation of a CAN bus based measurement system on an FPGA development kit

    CERN Document Server

    Zhu, Yu

    2010-01-01

    Hauptbeschreibung The Controller Area Network (CAN), invented by Bosch in 1983, is a serial field bus protocol which was originally used in road vehicles and now is widely applied in other industrial fields. Since its birth automotive electronic engineers have been use Microcontrollers (MCU) to control the CAN bus. Today, as the Field-programmable Gate Array (FPGA) has become very advance, this book introduces a new method which uses an FPGA and a MCU jointly instead of a single MCU is to design a CAN bus measurement system. Furthermore the designed system should be able to work at the fastest

  1. Random number generators for large-scale parallel Monte Carlo simulations on FPGA

    Science.gov (United States)

    Lin, Y.; Wang, F.; Liu, B.

    2018-05-01

    Through parallelization, field programmable gate array (FPGA) can achieve unprecedented speeds in large-scale parallel Monte Carlo (LPMC) simulations. FPGA presents both new constraints and new opportunities for the implementations of random number generators (RNGs), which are key elements of any Monte Carlo (MC) simulation system. Using empirical and application based tests, this study evaluates all of the four RNGs used in previous FPGA based MC studies and newly proposed FPGA implementations for two well-known high-quality RNGs that are suitable for LPMC studies on FPGA. One of the newly proposed FPGA implementations: a parallel version of additive lagged Fibonacci generator (Parallel ALFG) is found to be the best among the evaluated RNGs in fulfilling the needs of LPMC simulations on FPGA.

  2. A new delay line loops shrinking time-to-digital converter in low-cost FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, Jie, E-mail: zhangjie071063@163.com [State Key Laboratory of Geodesy and Earth’s Dynamics, Institute of Geodesy and Geophysics, CAS, Wuhan, China, 430077 (China); University of Chinese Academy of Sciences, Beijing, China, 100049 (China); Zhou, Dongming [State Key Laboratory of Geodesy and Earth’s Dynamics, Institute of Geodesy and Geophysics, CAS, Wuhan, China, 430077 (China)

    2015-01-21

    The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3 ps and the measurement standard deviation is about 61.7 ps within the measurement range of 5 ns. - Highlights: • We provide a new FPGA-integrated time-to-digital converter based on delay line loops method which used two delay line loops to directly shrink time intervals with only rising edges. • The two delay line loops consist of the same delay cells with the same number and symmetrical structure. • The resolution is dependent on the difference between the entire delays of the two delay line loops. • We use delay-locked loop to stabilize the resolution against temperature and supply voltage.

  3. A new delay line loops shrinking time-to-digital converter in low-cost FPGA

    International Nuclear Information System (INIS)

    Zhang, Jie; Zhou, Dongming

    2015-01-01

    The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3 ps and the measurement standard deviation is about 61.7 ps within the measurement range of 5 ns. - Highlights: • We provide a new FPGA-integrated time-to-digital converter based on delay line loops method which used two delay line loops to directly shrink time intervals with only rising edges. • The two delay line loops consist of the same delay cells with the same number and symmetrical structure. • The resolution is dependent on the difference between the entire delays of the two delay line loops. • We use delay-locked loop to stabilize the resolution against temperature and supply voltage

  4. Implementation of 4-way Superscalar Hash MIPS Processor Using FPGA

    Science.gov (United States)

    Sahib Omran, Safaa; Fouad Jumma, Laith

    2018-05-01

    Due to the quick advancements in the personal communications systems and wireless communications, giving data security has turned into a more essential subject. This security idea turns into a more confounded subject when next-generation system requirements and constant calculation speed are considered in real-time. Hash functions are among the most essential cryptographic primitives and utilized as a part of the many fields of signature authentication and communication integrity. These functions are utilized to acquire a settled size unique fingerprint or hash value of an arbitrary length of message. In this paper, Secure Hash Algorithms (SHA) of types SHA-1, SHA-2 (SHA-224, SHA-256) and SHA-3 (BLAKE) are implemented on Field-Programmable Gate Array (FPGA) in a processor structure. The design is described and implemented using a hardware description language, namely VHSIC “Very High Speed Integrated Circuit” Hardware Description Language (VHDL). Since the logical operation of the hash types of (SHA-1, SHA-224, SHA-256 and SHA-3) are 32-bits, so a Superscalar Hash Microprocessor without Interlocked Pipelines (MIPS) processor are designed with only few instructions that were required in invoking the desired Hash algorithms, when the four types of hash algorithms executed sequentially using the designed processor, the total time required equal to approximately 342 us, with a throughput of 4.8 Mbps while the required to execute the same four hash algorithms using the designed four-way superscalar is reduced to 237 us with improved the throughput to 5.1 Mbps.

  5. VHDL, FPGA and the master trigger controller of BES

    International Nuclear Information System (INIS)

    Guo Yanan; Wang Jufang; Zhao Dixin

    1996-01-01

    A Master Trigger Controller was made using fast FPGA (Field-Programmable Gate Array) instead of ECLIC (Emitter-Coupled Logic Integrated Circuit). VHDL (Verilog Hardware Description Language) was used in its design. The same performance was obtained with increased flexibility

  6. FPGA based VME boards for Indus-2 timing control system

    International Nuclear Information System (INIS)

    Lulani, Nitin; Barpande, K.; Fatnani, P.; Sheth, Y.

    2009-01-01

    FPGA based two VME boards are developed and deployed recently for Indus-2 timing control system at RRCAT Indore. New FPGA based 5-channel programmable (Coarse-Fine) delay generator board has replaced three 2-channel coarse and one 4-channel fine existing delay generator boards. Introduction of this board has improved the fine delay resolution (to 0.5ns) as well as channel to channel jitter (to 0.8ns) of the system. It has also improved the coarse delay resolution from previous 33ns to 8ns with the possibility to work at divided Indus-2 RF clock. These improved parameters have resulted in better injection rate of beam. Old coincidence generator board is also replaced with FPGA based newly developed Coincidence clock generator VME board, which has resulted in successful controlled filling of beam (single, multi and 3-symmetrical bucket filling) in Indus-2. Three more existing boards will be replaced by single FPGA based delay generator card in near future. This paper presents the design, test results and features of new boards. (author)

  7. FPGA Mezzanine Cards for CERN’s Accelerator Control System

    CERN Document Server

    Alvarez, P R; Lewis, J; Serrano, J; Wlostowski, T

    2009-01-01

    Field Programmable Gate Arrays (FPGAs) have become a key player in modern real time control systems. They offer determinism, simple design, high performance and versatility. A typical hardware architecture consists of an FPGA interfaced with a control bus and a variable number of digital IOs, ADCs and DACs depending on the application. Until recently the low-cost hardware paradigm has been using mezzanines containing a front end interface plus custom logic (typically an FPGA) and a local bus that interfaces the mezzanine to a carrier. As FPGAs grow in size and shrink in price, hardware reuse, testability and bus access speed could be improved if the user logic is moved to the carrier. The new FPGA Mezzanine Card (FMC) Vita 57 standard is a good example of this new paradigm. In this paper we present a standard kit of FPGA carriers and IO mezzanines for accelerator control. Carriers form factors will be VME, PCI and PCIe. The carriers will feature White Rabbit support for accurate synchronization of distributed...

  8. N queens on an fpga: mathematics,programming, or both?

    NARCIS (Netherlands)

    Kuper, Jan; Wester, Rinse

    2014-01-01

    This paper presents a design methodology for deriving an FPGA implementation directly from a mathematical specification, thus avoiding the switch in semantic perspective as is present in widely applied methods which include an imperative implementation as an intermediate step. The first step in the

  9. Junction Temperature Aware Energy Efficient Router Design on FPGA

    DEFF Research Database (Denmark)

    Thind, Vandana; Sharma, Shivani; Minwer, M H

    2015-01-01

    Energy, Power and efficiency are very much related to each other. To make any system efficient, Power consumed by it must be minimized or we can say that power dissipation should be less. In our research we tried to make a energy efficient router design on FPGA by varying junction temperature...

  10. Effective and efficient FPGA synthesis through general functional decomposition

    NARCIS (Netherlands)

    Jozwiak, L.; Slusarczyk, A.S.; Chojnacki, A.

    2003-01-01

    In this paper, a new information-driven circuit synthesis method is discussed that targets LUT-based FPGAs and FPGA-based reconfigurable system-on-a-chip platforms. The method is based on the bottom–up general functional decomposition and theory of information relationship measures that we

  11. Programovatelná hradlová pole - FPGA

    Czech Academy of Sciences Publication Activity Database

    Daněk, Martin

    2006-01-01

    Roč. 12, č. 2 (2006), s. 9-13 ISSN 1210-9592 R&D Projects: GA ČR GA102/04/2137 Institutional research plan: CEZ:AV0Z10750506 Keywords : FPGA architecture * physical design * design flow Subject RIV: JC - Computer Hardware ; Software

  12. Test of Gb Ethernet with FPGA for HADES upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Gilardi, C. [II. Physikalisches Inst., Giessen Univ. (Germany)

    2007-07-01

    Within the HADES experiment, we are investigating a trigger upgrade in order to run heavier systems (Au + Au). We investigate Gigabit Ethernet transfers with Xilinx Virtex II FPGA on the commercial board Celoxica RC300E. We implement the transfer protocols (UDP, ICMP, ARP) with Handel-C. First results of bandwidth and latency will be presented. (orig.)

  13. Uranus: a rapid prototyping tool for FPGA embedded computer vision

    Science.gov (United States)

    Rosales-Hernández, Victor; Castillo-Jimenez, Liz; Viveros-Velez, Gilberto; Zuñiga-Grajeda, Virgilio; Treviño Torres, Abel; Arias-Estrada, M.

    2007-01-01

    The starting point for all successful system development is the simulation. Performing high level simulation of a system can help to identify, insolate and fix design problems. This work presents Uranus, a software tool for simulation and evaluation of image processing algorithms with support to migrate them to an FPGA environment for algorithm acceleration and embedded processes purposes. The tool includes an integrated library of previous coded operators in software and provides the necessary support to read and display image sequences as well as video files. The user can use the previous compiled soft-operators in a high level process chain, and code his own operators. Additional to the prototyping tool, Uranus offers FPGA-based hardware architecture with the same organization as the software prototyping part. The hardware architecture contains a library of FPGA IP cores for image processing that are connected with a PowerPC based system. The Uranus environment is intended for rapid prototyping of machine vision and the migration to FPGA accelerator platform, and it is distributed for academic purposes.

  14. Single Event Effects in FPGA Devices 2015-2016

    Science.gov (United States)

    Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

    2016-01-01

    This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing, mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

  15. Commissioning of FPGA-based Transverse and Longitudinal Bunch-by-Bunch Feedback System for the TLS

    International Nuclear Information System (INIS)

    Hu, K. H.; Kuo, C. H.; Lau, W. K.; Yeh, M. S.; Hsu, S. Y.; Chou, P. J.; Wang, M. H.; Lee, Demi; Chen, Jenny; Wang, C. J.; Hsu, K. T.; Kobayashi, K.; Nakamura, T.; Dehler, M.

    2006-01-01

    Multi-bunch instabilities deteriorate beam quality, increasing beam emittance, or even causing beam loss in the synchrotron light source. The feedback system is essential to suppress multi-bunch instabilities caused by the impedances of beam ducts, and trapped ions. A new FPGA based transverse and longitudinal bunch-by-bunch feedback system have been commissioned at the Taiwan Light Source recently, A single feedback loop is used to simultaneously suppress the horizontal and the vertical multi-bunch instabilities. Longitudinal instabilities caused by cavity-like structures are suppressed by the longitudinal feedback loop. The same FPGA processor is employed in the transverse feedback and the longitudinal feedback system respectively. Diagnostic memory is included in the system to capture the bunch oscillation signal, which supports various studies

  16. Photoelectric radar servo control system based on ARM+FPGA

    Science.gov (United States)

    Wu, Kaixuan; Zhang, Yue; Li, Yeqiu; Dai, Qin; Yao, Jun

    2016-01-01

    In order to get smaller, faster, and more responsive requirements of the photoelectric radar servo control system. We propose a set of core ARM + FPGA architecture servo controller. Parallel processing capability of FPGA to be used for the encoder feedback data, PWM carrier modulation, A, B code decoding processing and so on; Utilizing the advantage of imaging design in ARM Embedded systems achieves high-speed implementation of the PID algorithm. After the actual experiment, the closed-loop speed of response of the system cycles up to 2000 times/s, in the case of excellent precision turntable shaft, using a PID algorithm to achieve the servo position control with the accuracy of + -1 encoder input code. Firstly, This article carry on in-depth study of the embedded servo control system hardware to determine the ARM and FPGA chip as the main chip with systems based on a pre-measured target required to achieve performance requirements, this article based on ARM chip used Samsung S3C2440 chip of ARM7 architecture , the FPGA chip is chosen xilinx's XC3S400 . ARM and FPGA communicate by using SPI bus, the advantage of using SPI bus is saving a lot of pins for easy system upgrades required thereafter. The system gets the speed datas through the photoelectric-encoder that transports the datas to the FPGA, Then the system transmits the datas through the FPGA to ARM, transforms speed datas into the corresponding position and velocity data in a timely manner, prepares the corresponding PWM wave to control motor rotation by making comparison between the position data and the velocity data setted in advance . According to the system requirements to draw the schematics of the photoelectric radar servo control system and PCB board to produce specially. Secondly, using PID algorithm to control the servo system, the datas of speed obtained from photoelectric-encoder is calculated position data and speed data via high-speed digital PID algorithm and coordinate models. Finally, a

  17. Influence of 1,2-PB matrix cross-linking on structure and properties of selectively etched 1,2-PB-b-PDMS block copolymers

    DEFF Research Database (Denmark)

    Guo, Fengxiao; Andreasen, Jens Wenzel; Vigild, Martin Etchells

    2007-01-01

    of the cross-linked samples in toluene was converted into a degree of cross-linking following the Flory scheme; a simple relation between the Flory cross-linking degree and the fraction of consumed double bonds during the cross-linking reaction followed. The structure of the block copolymer at different stages...... of preparation was characterized by small-angle X-ray scattering (SAXS). In addition, scanning electron microscopy (SEM) gave direct images of the nanoporous polymer structure. Nanocavities are accessible to methanol, and observations of methanol uptake were combined with structural information from SAXS...

  18. LDPC Codes with Minimum Distance Proportional to Block Size

    Science.gov (United States)

    Divsalar, Dariush; Jones, Christopher; Dolinar, Samuel; Thorpe, Jeremy

    2009-01-01

    error floors as well as low decoding thresholds. As an example, the illustration shows the protograph (which represents the blueprint for overall construction) of one proposed code family for code rates greater than or equal to 1.2. Any size LDPC code can be obtained by copying the protograph structure N times, then permuting the edges. The illustration also provides Field Programmable Gate Array (FPGA) hardware performance simulations for this code family. In addition, the illustration provides minimum signal-to-noise ratios (Eb/No) in decibels (decoding thresholds) to achieve zero error rates as the code block size goes to infinity for various code rates. In comparison with the codes mentioned in the preceding article, these codes have slightly higher decoding thresholds.

  19. Overview and future developments of the FPGA-based DAQ of COMPASS

    Energy Technology Data Exchange (ETDEWEB)

    Bai, Yunpeng; Huber, Stefan; Konorov, Igor; Levit, Dmytro [Physik-Department E18, Technische Universitaet Muenchen (Germany); Bodlak, Martin [Department of Low-Temperature Physics, Charles University Prague (Czech Republic); Frolov, Vladimir [European Organization for Nuclear Research - CERN (Switzerland); Jary, Vladimir; Virius, Miroslav [Faculty of Nuclear Sciences and Physical Engineering, Czech Technical University (Czech Republic); Novy, Josef [European Organization for Nuclear Research - CERN (Switzerland); Faculty of Nuclear Sciences and Physical Engineering, Czech Technical University (Czech Republic); Steffen, Dominik [Physik-Department E18, Technische Universitaet Muenchen (Germany); European Organization for Nuclear Research - CERN (Switzerland)

    2016-07-01

    COMPASS is a fixed-target experiment at the SPS accelerator at CERN dedicated to the study of hadron structure and spectroscopy. In 2014, an FPGA-based data acquisition system (FDAQ) was deployed. Its hardware event builder consisting of nine custom designed FPGA-cards replaced 30 distributed online computers and around 100 PCI cards. As a result, the new DAQ provides higher bandwidth and better reliability. By buffering the data, the system exploits the spill structure of the SPS averaging the maximum on-spill data rate of 1.5 GB/s over the whole SPS duty cycle. A modern run control software allows user-friendly monitoring and configuration of the hardware nodes of the event builder. From 2016, it is planned to wire all point-to-point high-speed links via a fully programmable crosspoint switch. The crosspoint switch will provide a fully customizable DAQ network topology between front-end electronics, the event building hardware, and the readout computers. It will therefore simplify compensation for hardware failure and improve load balancing.

  20. Detection block

    International Nuclear Information System (INIS)

    Bezak, A.

    1987-01-01

    A diagram is given of a detection block used for monitoring burnup of nuclear reactor fuel. A shielding block is an important part of the detection block. It stabilizes the fuel assembly in the fixing hole in front of a collimator where a suitable gamma beam is defined for gamma spectrometry determination of fuel burnup. The detector case and a neutron source case are placed on opposite sides of the fixing hole. For neutron measurement for which the water in the tank is used as a moderator, the neutron detector-fuel assembly configuration is selected such that neutrons from spontaneous fission and neutrons induced with the neutron source can both be measured. The patented design of the detection block permits longitudinal travel and rotation of the fuel assembly to any position, and thus more reliable determination of nuclear fuel burnup. (E.S.). 1 fig

  1. Multi-DSP and FPGA based Multi-channel Direct IF/RF Digital receiver for atmospheric radar

    Science.gov (United States)

    Yasodha, Polisetti; Jayaraman, Achuthan; Kamaraj, Pandian; Durga rao, Meka; Thriveni, A.

    2016-07-01

    Modern phased array radars depend highly on digital signal processing (DSP) to extract the echo signal information and to accomplish reliability along with programmability and flexibility. The advent of ASIC technology has made various digital signal processing steps to be realized in one DSP chip, which can be programmed as per the application and can handle high data rates, to be used in the radar receiver to process the received signal. Further, recent days field programmable gate array (FPGA) chips, which can be re-programmed, also present an opportunity to utilize them to process the radar signal. A multi-channel direct IF/RF digital receiver (MCDRx) is developed at NARL, taking the advantage of high speed ADCs and high performance DSP chips/FPGAs, to be used for atmospheric radars working in HF/VHF bands. Multiple channels facilitate the radar t be operated in multi-receiver modes and also to obtain the wind vector with improved time resolution, without switching the antenna beam. MCDRx has six channels, implemented on a custom built digital board, which is realized using six numbers of ADCs for simultaneous processing of the six input signals, Xilinx vertex5 FPGA and Spartan6 FPGA, and two ADSPTS201 DSP chips, each of which performs one phase of processing. MCDRx unit interfaces with the data storage/display computer via two gigabit ethernet (GbE) links. One of the six channels is used for Doppler beam swinging (DBS) mode and the other five channels are used for multi-receiver mode operations, dedicatedly. Each channel has (i) ADC block, to digitize RF/IF signal, (ii) DDC block for digital down conversion of the digitized signal, (iii) decoding block to decode the phase coded signal, and (iv) coherent integration block for integrating the data preserving phase intact. ADC block consists of Analog devices make AD9467 16-bit ADCs, to digitize the input signal at 80 MSPS. The output of ADC is centered around (80 MHz - input frequency). The digitized data is fed

  2. 15 CFR 50.40 - Fee structure for statistics for city blocks in the 1980 Census of Population and Housing.

    Science.gov (United States)

    2010-01-01

    ... blocks in the 1980 Census of Population and Housing. 50.40 Section 50.40 Commerce and Foreign Trade... the 1980 Census of Population and Housing. (a) As part of the regular program of the 1980 census, the Census Bureau will publish printed reports containing certain summary population and housing statistics...

  3. Perpendicular Structure Formation of Block Copolymer Thin Films during Thermal Solvent Vapor Annealing : Solvent and Thickness Effects

    NARCIS (Netherlands)

    Yang, Qiuyan; Loos, Katja

    2017-01-01

    Solvent vapor annealing of block copolymer (BCP) thin films can produce a range of interesting morphologies, especially when the perpendicular orientation of micro-domains with respect to the substrate plays a role. This, for instance, allows BCP thin films to serve as useful templates for

  4. Production of Polyclonal Antiobies to a Recombinant Potato Mop-top Virus Non-structural Triple Gene Block Protein l

    Czech Academy of Sciences Publication Activity Database

    Čeřovská, Noemi; Filigarová, Marie; Pečenková, Tamara

    2006-01-01

    Roč. 154, - (2006), s. 422-427 ISSN 0931-1785 R&D Projects: GA ČR GA522/04/1329 Institutional research plan: CEZ:AV0Z50380511 Keywords : Potato mop-top virus * recombinant protein * triple gene block * polyclonal antibodies Subject RIV: EB - Genetics ; Molecular Biology Impact factor: 0.817, year: 2006

  5. Surprising transformation of a block copolymer into a high performance polystyrene ultrafiltration membrane with a hierarchically organized pore structure

    KAUST Repository

    Shevate, Rahul; Kumar, Mahendra; Karunakaran, Madhavan; Canlas, Christian; Peinemann, Klaus-Viktor

    2018-01-01

    ) block from self-assembled poly(styrene)-b-poly(4-vinyl pyridine) (PS-b-P4VP) membranes through the formation of an unstable pyridinium intermediate in an alkaline medium. During this process, the confined swelling and controlled degradation produced a

  6. STRUCTURAL SOLUTIONS AND SPECIAL FEATURES OF THE THERMAL PROTECTION ANALYSIS OF EXTERIOR WALLS OF BUILDINGS MADE OF AUTOCLAVED GAS-CONCRETE BLOCKS

    Directory of Open Access Journals (Sweden)

    Bedov Anatolij Ivanovich

    2012-10-01

    Full Text Available Relevant structural solutions, physical and mechanical characteristics, coefficients of thermal conductivity for exterior masonry walls made of autoclaved gas-concrete blocks are provided in the article. If a single-layer wall is under consideration, an autoclaved gas-concrete block is capable of performing the two principal functions of a shell structure, including the function of thermal protection and the bearing function. The functions are performed simultaneously. Therefore, the application of the above masonry material means the design development and erection of exterior walls of residential buildings noteworthy for their thermal efficiency. In the event of frameless structures, the height of the residential building in question may be up to 5 stories, while the use of a monolithic or a ready-made frame makes it possible to build high-rise buildings, and the number of stories is not limited in this case. If the average block density is equal to 400…500 kilograms per cubic meter, the designed wall thickness is to be equal to 400 mm. Its thermal resistance may be lower than the one set in the event of the per-element design of the thermal protection (Rreq = 3.41 м2 C/Watt, in Ufa, although it will meet the requirements of the applicable regulations if per-unit power consumption rate is considered.

  7. FPGA-based architecture for motion recovering in real-time

    Science.gov (United States)

    Arias-Estrada, Miguel; Maya-Rueda, Selene E.; Torres-Huitzil, Cesar

    2002-03-01

    A key problem in the computer vision field is the measurement of object motion in a scene. The main goal is to compute an approximation of the 3D motion from the analysis of an image sequence. Once computed, this information can be used as a basis to reach higher level goals in different applications. Motion estimation algorithms pose a significant computational load for the sequential processors limiting its use in practical applications. In this work we propose a hardware architecture for motion estimation in real time based on FPGA technology. The technique used for motion estimation is Optical Flow due to its accuracy, and the density of velocity estimation, however other techniques are being explored. The architecture is composed of parallel modules working in a pipeline scheme to reach high throughput rates near gigaflops. The modules are organized in a regular structure to provide a high degree of flexibility to cover different applications. Some results will be presented and the real-time performance will be discussed and analyzed. The architecture is prototyped in an FPGA board with a Virtex device interfaced to a digital imager.

  8. Development of An Embedded FPGA-Based Data Acquisition System Dedicated to Zero Power Reactor Noise Experiments

    Directory of Open Access Journals (Sweden)

    Arkani Mohammad

    2014-08-01

    Full Text Available An embedded time interval data acquisition system (DAS is developed for zero power reactor (ZPR noise experiments. The system is capable of measuring the correlation or probability distribution of a random process. The design is totally implemented on a single Field Programmable Gate Array (FPGA. The architecture is tested on different FPGA platforms with different speed grades and hardware resources. Generic experimental values for time resolution and inter-event dead time of the system are 2.22 ns and 6.67 ns respectively. The DAS can record around 48-bit x 790 kS/s utilizing its built-in fast memory. The system can measure very long time intervals due to its 48-bit timing structure design. As the architecture can work on a typical FPGA, this is a low cost experimental tool and needs little time to be established. In addition, revisions are easily possible through its reprogramming capability. The performance of the system is checked and verified experimentally.

  9. Structure and Properties of Nanocomposites based on PTT-block-PTMO Copolymer and Graphene Oxide prepared by in Situ Polymerization

    OpenAIRE

    Paszkiewicz, Sandra; Szymczyk, Anna; Špitalský, Zdenko; Mosnáček, Jaroslav; Kwiatkowski, Konrad; Rosłaniec, Zbigniew

    2014-01-01

    Poly(trimethylene terephthalate-block-tetramethylene oxide) (PTT-PTMO) copolymer/graphene oxide nanocomposites were prepared by in situ polymerization. From the SEM and TEM images of PTT-PTMO/GO nanocomposite, it can be seen that GO sheets are clearly well-dispersed in the PTT-PTMO matrix. TEM images also showed that graphene was well exfoliated into individual sheets, suggesting that in situ polymerization is a highly efficient method for preparing nanocomposites. The influence of GO on the ...

  10. A block structured method for the simulation of the flow around complex configurations; Ein blockstrukturiertes Verfahren zur Simulation der Umstroemung komplexer Konfigurationen

    Energy Technology Data Exchange (ETDEWEB)

    Schwarz, T.O.

    2005-07-01

    A block structured method for the simulation of the viscous flow around complex configurations is presented. The computational domain is discretized with overlapping meshes. The meshes are composed of individually created grids for the components of a configuration and an automatically generated Cartesian background grid. The background grid is a multi-block mesh with hanging grid nodes, which is adapted to the cell size of the component grids. The cells of the background grid can be cubes or cuboids. The overlapping grid approach simplifies the generation of block structured grids significantly. The flow computations are performed with a Navier-Stokes solver. The Chimera capabilities of the solver are extended by methods for the computation of interpolation coefficients and global forces in case of grid overlap on body surfaces. Additionally, a flux conservative boundary condition for the hanging grid nodes is implemented. The consistency and accuracy of the methods is proved by grid refinement studies. Validation test cases include a three element airfoil, a helicopter fuselage and an airplane in landing configuration. Numerical results obtained for Chimera meshes as well as conventional grids agree very well. The agreement with wind tunnel experiments is good. The computational costs for Chimera computations are slightly higher than for conventional grids. (orig.)

  11. Conformation of single block copolymer chain in two-dimensional microphase-separated structure studied by scanning near-field optical microscopy.

    Science.gov (United States)

    Sekine, Ryojun; Aoki, Hiroyuki; Ito, Shinzaburo

    2009-05-21

    The localization and orientation of the symmetric diblock copolymer chain in a quasi-two-dimensional microphase-separated structure were studied by scanning near-field optical microscopy (SNOM). In the monolayer of poly(isobutyl methacrylate)-block-poly(octadecyl methacrylate) (PiBMA-b-PODMA), the individual PiBMA subchains were directly observed by SNOM, and the center of mass (CM) and orientational angle relative to the phase interface were examined at the single chain level. It was found that the position of the CM and the orientation of the PiBMA subchain in the lamellar structure were dependent on the curvature of the PiBMA/PODMA interface. As the interface was bent toward the objective chain, the block chain preferred the CM position closer to the domain center, and the conformation was strongly oriented perpendicularly to the domain interface. With increase of the curvature, the steric hindrance among the block chain increases, resulting in the stretched conformation.

  12. Stratigraphy of amethyst geode-bearing lavas and fault-block structures of the Entre Rios mining district, Paraná volcanic province, southern Brazil

    Directory of Open Access Journals (Sweden)

    LÉO A. HARTMANN

    2014-03-01

    Full Text Available The Entre Rios mining district produces a large volume of amethyst geodes in underground mines and is part of the world class deposits in the Paraná volcanic province of South America. Two producing basalt flows are numbered 4 and 5 in the lava stratigraphy. A total of seven basalt flows and one rhyodacite flow are present in the district. At the base of the stratigraphy, beginning at the Chapecó river bed, two basalt flows are Esmeralda, low-Ti type. The third flow in the sequence is a rhyodacite, Chapecó type, Guarapuava subtype. Above the rhyodacite flow, four basalt flows are Pitanga, high-Ti type including the two mineralized flows; only the topmost basalt in the stratigraphy is a Paranapanema, intermediate-Ti type. Each individual flow is uniquely identified from its geochemical and gamma-spectrometric properties. The study of several sections in the district allowed for the identification of a fault-block structure. Blocks are elongated NW and the block on the west side of the fault was downthrown. This important structural characterization of the mining district will have significant consequences in the search for new amethyst geode deposits and in the understanding of the evolution of the Paraná volcanic province.

  13. 垫块结构对PELE横向效应的影响%Influence of Block Structure on Lateral Effect of PELE

    Institute of Scientific and Technical Information of China (English)

    徐立志; 杜忠华; 王德胜; 温瑞青; 胡云超

    2016-01-01

    To study the influence of block structure on PELE penetrating reinforced concrete targets,the stress in the process of penetration was analyzed,and the theoretical model was established. By utilizing the methods of numerical simulation and test, PELE added with block of different pressure-angles penetrating reinforced concrete targets was analyzed,which was compared with the PELE without block. The pressure-angle obtained by theoretical model agrees well with test results. The results show that the different pressure-angles of the block significantly influence the lateral effect of PELE penetrating reinforced concrete targets,and there exists the optimum pressure angle. The lateral effect of PELE can be enhanced by adding a block and changing the pressure angle. The mechanism of penetrating reinforced concrete targets of PELE with block at 45° angle is very different from that of PELE without block.%为了研究垫块结构对PELE侵彻钢筋混凝土靶开孔尺寸的影响,在分析侵彻过程受力情况的基础上建立了工程模型,利用数值仿真和试验研究的方法分析了具有不同压力角垫块结构的PELE侵彻钢筋混凝土靶,与未添加垫块结构PELE侵彻钢筋混凝土靶进行了对比分析,工程模型对垫块压力角的计算结果与试验结果吻合较好。结果表明:垫块的压力角大小对PELE侵彻钢筋混凝土靶的横向效应影响显著,且存在最优压力角;添加垫块并且改变压力角大小可以增强PELE的横向效应;具有45°压力角的垫块结构和未添加垫块的PELE侵彻钢筋混凝土的作用机理相差较大。

  14. FPGA Online Tracking Algorithm for the PANDA Straw Tube Tracker

    Science.gov (United States)

    Liang, Yutie; Ye, Hua; Galuska, Martin J.; Gessler, Thomas; Kuhn, Wolfgang; Lange, Jens Soren; Wagner, Milan N.; Liu, Zhen'an; Zhao, Jingzhou

    2017-06-01

    A novel FPGA based online tracking algorithm for helix track reconstruction in a solenoidal field, developed for the PANDA spectrometer, is described. Employing the Straw Tube Tracker detector with 4636 straw tubes, the algorithm includes a complex track finder, and a track fitter. Implemented in VHDL, the algorithm is tested on a Xilinx Virtex-4 FX60 FPGA chip with different types of events, at different event rates. A processing time of 7 $\\mu$s per event for an average of 6 charged tracks is obtained. The momentum resolution is about 3\\% (4\\%) for $p_t$ ($p_z$) at 1 GeV/c. Comparing to the algorithm running on a CPU chip (single core Intel Xeon E5520 at 2.26 GHz), an improvement of 3 orders of magnitude in processing time is obtained. The algorithm can handle severe overlapping of events which are typical for interaction rates above 10 MHz.

  15. Design of CMOS imaging system based on FPGA

    Science.gov (United States)

    Hu, Bo; Chen, Xiaolai

    2017-10-01

    In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

  16. Intermediate Frequency Digital Receiver Based on Multi-FPGA System

    Directory of Open Access Journals (Sweden)

    Chengchang Zhang

    2016-01-01

    Full Text Available Aiming at high-cost, large-size, and inflexibility problems of traditional analog intermediate frequency receiver in the aerospace telemetry, tracking, and command (TTC system, we have proposed a new intermediate frequency (IF digital receiver based on Multi-FPGA system in this paper. Digital beam forming (DBF is realized by coordinated rotation digital computer (CORDIC algorithm. An experimental prototype has been developed on a compact Multi-FPGA system with three FPGAs to receive 16 channels of IF digital signals. Our experimental results show that our proposed scheme is able to provide a great convenience for the design of IF digital receiver, which offers a valuable reference for real-time, low power, high density, and small size receiver design.

  17. A new FPGA architecture suitable for DSP applications

    International Nuclear Information System (INIS)

    Wang Liyun; Lai Jinmei; Tong Jiarong; Tang Pushan; Chen Xing; Duan Xueyan; Chen Liguang; Wang Jian; Wang Yuan

    2011-01-01

    A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 μm CMOS technology successfully. The die size is 6.3 x 4.5 mm 2 with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs. (semiconductor integrated circuits)

  18. FPGA-based network data transmission scheme for CSNS

    International Nuclear Information System (INIS)

    Wang Xiuku; Zhang Hongyu; Gu Minhao; Xiao Liang

    2012-01-01

    This paper presents the FPGA-based network data transmission solutions for the Data Acquisition System of China Spallation Neutron Source (CSNS). The board with FPGA as the core is used as the hardware platform to realize the transmission of network data. A SOPC system is built and an embedded Linux is transplanted on PowerPC Core. An application program based on Linux has been finished to realize the data transmission via embedded Gigabit Ethernet. The relationship between network transfer performance and packet size was obtained by a test program. In addition, the paper also tried to realize some other ways to transfer data: transplanting PetaLinux on Microblaze, transplanting Lwip protocol stack on PowerPC Core and Microblaze. Their advantages and disadvantages are analyzed and compared in this paper, so that different options and recommendations can be given to meet the actual needs of different projects in the future. (authors)

  19. FPGA-based digital convolution for wireless applications

    CERN Document Server

    Guan, Lei

    2017-01-01

    This book presents essential perspectives on digital convolutions in wireless communications systems and illustrates their corresponding efficient real-time field-programmable gate array (FPGA) implementations. Covering these digital convolutions from basic concept to vivid simulation/illustration, the book is also supplemented with MS PowerPoint presentations to aid in comprehension. FPGAs or generic all programmable devices will soon become widespread, serving as the “brains” of all types of real-time smart signal processing systems, like smart networks, smart homes and smart cities. The book examines digital convolution by bringing together the following main elements: the fundamental theory behind the mathematical formulae together with corresponding physical phenomena; virtualized algorithm simulation together with benchmark real-time FPGA implementations; and detailed, state-of-the-art case studies on wireless applications, including popular linear convolution in digital front ends (DFEs); nonlinear...

  20. HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

    DEFF Research Database (Denmark)

    Madhok, Shivani; Pandey, Bishwajeet; Kaur, Amanpreet

    2015-01-01

    standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power...... consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA....

  1. Teaching Computer Organization and Architecture Using Simulation and FPGA Applications

    OpenAIRE

    D. K.M. Al-Aubidy

    2007-01-01

    This paper presents the design concepts and realization of incorporating micro-operation simulation and FPGA implementation into a teaching tool for computer organization and architecture. This teaching tool helps computer engineering and computer science students to be familiarized practically with computer organization and architecture through the development of their own instruction set, computer programming and interfacing experiments. A two-pass assembler has been designed and implemente...

  2. FPGA applications for single dish activity at Medicina radio telescopes

    Science.gov (United States)

    Bartolini, M.; Naldi, G.; Mattana, A.; Maccaferri, A.; De Biaggi, M.

    FPGA technologies are gaining major attention in the recent years in the field of radio astronomy. At Medicina radio telescopes, FPGAs have been used in the last ten years for a number of purposes and in this article we will take into exam the applications developed and installed for the Medicina Single Dish 32m Antenna: these range from high performance digital signal processing to instrument control developed on top of smaller FPGAs.

  3. Design of a synthesizer for magnetic resonance equipment using FPGA

    International Nuclear Information System (INIS)

    Sonora A

    2006-01-01

    This paper exposes the design of a direct digital synthesizer in FPGA. This desing can generate a sine wave output up to 4MHZ with 3,33 mHz of precision. The frequency is set by 32bit word of phase increment in 350ns. The desing was made for Magnetic Resonance scanners and uses a 97% of logic resources of device. Functions for the synthesizer control are implemented in the same chip

  4. FPGA based mixed-signal circuit novel testing techniques

    International Nuclear Information System (INIS)

    Pouros, Sotirios; Vassios, Vassilios; Papakostas, Dimitrios; Hristov, Valentin

    2013-01-01

    Electronic circuits fault detection techniques, especially on modern mixed-signal circuits, are evolved and customized around the world to meet the industry needs. The paper presents techniques used on fault detection in mixed signal circuits. Moreover, the paper involves standardized methods, along with current innovations for external testing like Design for Testability (DfT) and Built In Self Test (BIST) systems. Finally, the research team introduces a circuit implementation scheme using FPGA

  5. Implementation of Serial and Parallel Bubble Sort on Fpga

    OpenAIRE

    Purnomo, Dwi Marhaendro Jati; Arinaldi, Ahmad; Priyantini, Dwi Teguh; Wibisono, Ari; Febrian, Andreas

    2016-01-01

    Sorting is common process in computational world. Its utilization are on many fields from research to industry. There are many sorting algorithm in nowadays. One of the simplest yet powerful is bubble sort. In this study, bubble sort is implemented on FPGA. The implementation was taken on serial and parallel approach. Serial and parallel bubble sort then compared by means of its memory, execution time, and utility which comprises slices and LUTs. The experiments show that serial bubble sort r...

  6. Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

    OpenAIRE

    Zulfikar, Z

    2012-01-01

    A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared....

  7. VHDL resolved function based inner communication bus for FPGA

    Science.gov (United States)

    Pozniak, Krzysztof T.

    2017-08-01

    This article discusses a method of building an internal, universal and parametric bus. The solution was designed for a variety of FPGA families and popular VHDL compilers. The algorithm of automatic configuration of address space and methods of receiving and sending addressed data are discussed. The basic solution realized in VHDL language in a behavioral form and chosen examples of practical use of the internal bus are presented in detail.

  8. Accelerating String Set Matching in FPGA Hardware for Bioinformatics Research

    Directory of Open Access Journals (Sweden)

    Burgess Shane C

    2008-04-01

    Full Text Available Abstract Background This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomics. The process of matching peptide sequences against a genome translated in six reading frames is part of a proteogenomic mapping pipeline that is used as a case-study. The Aho-Corasick algorithm is adapted for execution in field programmable gate array (FPGA devices in a manner that optimizes space and performance. In this approach, the traditional Aho-Corasick finite state machine (FSM is split into smaller FSMs, operating in parallel, each of which matches up to 20 peptides in the input translated genome. Each of the smaller FSMs is further divided into five simpler FSMs such that each simple FSM operates on a single bit position in the input (five bits are sufficient for representing all amino acids and special symbols in protein sequences. Results This bit-split organization of the Aho-Corasick implementation enables efficient utilization of the limited random access memory (RAM resources available in typical FPGAs. The use of on-chip RAM as opposed to FPGA logic resources for FSM implementation also enables rapid reconfiguration of the FPGA without the place and routing delays associated with complex digital designs. Conclusion Experimental results show storage efficiencies of over 80% for several data sets. Furthermore, the FPGA implementation executing at 100 MHz is nearly 20 times faster than an implementation of the traditional Aho-Corasick algorithm executing on a 2.67 GHz workstation.

  9. DNA Assembly with De Bruijn Graphs Using an FPGA Platform.

    Science.gov (United States)

    Poirier, Carl; Gosselin, Benoit; Fortier, Paul

    2018-01-01

    This paper presents an FPGA implementation of a DNA assembly algorithm, called Ray, initially developed to run on parallel CPUs. The OpenCL language is used and the focus is placed on modifying and optimizing the original algorithm to better suit the new parallelization tool and the radically different hardware architecture. The results show that the execution time is roughly one fourth that of the CPU and factoring energy consumption yields a tenfold savings.

  10. Embedded active vision system based on an FPGA architecture

    OpenAIRE

    Chalimbaud , Pierre; Berry , François

    2006-01-01

    International audience; In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision) is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks,...

  11. The current state of FPGA technology in the nuclear domain

    Energy Technology Data Exchange (ETDEWEB)

    Ranta, J.

    2012-07-01

    Field programmable gate arrays are a form of programmable electronic device used in various applications including automation systems. In recent years, there has been a growing interest in the use of FPGA-based systems also for safety automation of nuclear power plants. The interest is driven by the need for reliable new alternatives to replace, on one hand, the aging technology currently in use and, on the other hand, microprocessor and software-based systems, which are seen as overly complex from the safety evaluation point of view. This report presents an overview of FPGA technology, including hardware aspects, the application development process, risks and advantages of the technology, and introduces some of the current systems. FPGAs contain an interesting combination of features from software-based and fully hardware-based systems. Application development has a great deal in common with software development, but the final product is a hardware component without the operating system and other platform functions on which software would execute. Currently the number of FPGA-based applications used for safety functions of nuclear power plants is rather limited, but it is growing. So far there is little experience or common solid understanding between different parties on how FPGAs should be evaluated and handled in the licensing process. (orig.)

  12. The current state of FPGA technology in the nuclear domain

    International Nuclear Information System (INIS)

    Ranta, J.

    2012-01-01

    Field programmable gate arrays are a form of programmable electronic device used in various applications including automation systems. In recent years, there has been a growing interest in the use of FPGA-based systems also for safety automation of nuclear power plants. The interest is driven by the need for reliable new alternatives to replace, on one hand, the aging technology currently in use and, on the other hand, microprocessor and software-based systems, which are seen as overly complex from the safety evaluation point of view. This report presents an overview of FPGA technology, including hardware aspects, the application development process, risks and advantages of the technology, and introduces some of the current systems. FPGAs contain an interesting combination of features from software-based and fully hardware-based systems. Application development has a great deal in common with software development, but the final product is a hardware component without the operating system and other platform functions on which software would execute. Currently the number of FPGA-based applications used for safety functions of nuclear power plants is rather limited, but it is growing. So far there is little experience or common solid understanding between different parties on how FPGAs should be evaluated and handled in the licensing process. (orig.)

  13. Desain Protokol Suara Sebagai Pengendali Dalam Smart Home Menggunakan FPGA

    Directory of Open Access Journals (Sweden)

    Barlian Henryranu Prasetio

    2017-05-01

    Smart home is a system that uses computers and information technology to control home-like equipment such as windows and lights. The system can be a simple control system to a complex system. Computer / microcontroller based on internet/ethernet network equipped with intelligent system and automation system so as to make home to work automatically. Many computer devices / microcontrollers that can be implemented as a controller in the smart home. Smart home control system in this study using Xilinx xpartan-3e that controls the equipment in the house through LAN (Local Area Networking. This control system communicates using broadcast voice on the local network. The Controller System is designed to be able to transmit a voice signal packet from the microphone input and then send it using the ethernet protocol in the home local network using the FPGA. The FPGA is programmed to transmit and encode data packets, converting digital data into analog data to be able to control the equipment in the home. From the simulation test results using ISIM, it is seen that the system works in realtime. Keywords: smart home, voice, fpga, control

  14. Estimation of channel impulse response and FPGA simulation

    Directory of Open Access Journals (Sweden)

    YU Longjie

    2015-02-01

    Full Text Available Wideband code division multiple access (WCDMA is a 3G wireless communication network.The common pilot channel in downlink of WCDMA provides an effective method to estimate the channel impulse response.In this paper,universal software radio peripheral (USRP is utilized to sample and process WCDMA signal which is emitted by China Unicom base station.Firstly,the received signal is pre-processed with filtering and down-sampling.Secondly,fast algorithm of WCDMA cell search is fulfilled.Thirdly,frequency shift caused by USRP′s crystal oscillator is checked and compensated.Eventually,channel impulse response is estimated.In this paper,MATLAB is used to describe the above algorithm and field programmable gate array (FPGA is used to simulate algorithm.In the process of simulation,pipeline and IP core multiplexing are introduced.In the case of 32 MHz clock frequency,FPGA simulation time is 80.861 ms.Simulation results show that FPGA is able to estimate the channel impulse response quickly and accurately with less hardware resources.

  15. Hardware and Software Integration in Project Development of Automated Controller System Using LABVIEW FPGA

    International Nuclear Information System (INIS)

    Mohd Khairulezwan Abd Manan; Mohd Sabri Minhat; Izhar Abu Hussin

    2014-01-01

    The Field-Programmable Gate Array (FPGA) is a semiconductor device that can be programmed after manufacturing. Instead of being restricted to any predetermined hardware function, an FPGA allows user to program product features and functions, adapt to new standards, and reconfigure hardware for specific applications even after the product has been installed in the field, hence the name field-programmable. This project developed a control system using LabVIEW FPGA. LabVIEW FPGA is easier where it is programmed by using drag and drop icon. Then it will be integrated with the hardware input and output. (author)

  16. New Developments in FPGA: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

    Science.gov (United States)

    Berg, Melanie D.; Label, Kenneth A.; Pellish, Jonathan

    2016-01-01

    It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

  17. New Developments in FPGA Devices: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

    Science.gov (United States)

    Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

    2016-01-01

    It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

  18. New slow-control FPGA IP for GBT based system and status update of the GBT-FPGA project

    CERN Document Server

    Mendez, Julian Maxime; Caratelli, Alessandro; Leitao, Pedro Vicente

    2018-01-01

    The GBT-FPGA, part of the GBT (GigaBit Transceiver) project framework, is a VHDL-based core designed to offer a back-end counterpart to the GBTx ASIC, a radiation tolerant 4.8 Gb/s optical transceiver. The GBT-SCA (Slow Control Adapter) radiation tolerant ASIC is also part of the GBT chipset and is used for the slow control in the High Energy Physics experiments. In this context, a new VHDL core named GBT-SC has been designed and released to handle the slow control fields hosted in the serial GBT frame for the GBTx and GBT-SCA. This paper presents the architecture and performance of this new GBT-SC module as well as an outline of recent GBT-FPGA core releases and future plans.

  19. Economical Implementation of a Filter Engine in an FPGA

    Science.gov (United States)

    Kowalski, James E.

    2009-01-01

    A logic design has been conceived for a field-programmable gate array (FPGA) that would implement a complex system of multiple digital state-space filters. The main innovative aspect of this design lies in providing for reuse of parts of the FPGA hardware to perform different parts of the filter computations at different times, in such a manner as to enable the timely performance of all required computations in the face of limitations on available FPGA hardware resources. The implementation of the digital state-space filter involves matrix vector multiplications, which, in the absence of the present innovation, would ordinarily necessitate some multiplexing of vector elements and/or routing of data flows along multiple paths. The design concept calls for implementing vector registers as shift registers to simplify operand access to multipliers and accumulators, obviating both multiplexing and routing of data along multiple paths. Each vector register would be reused for different parts of a calculation. Outputs would always be drawn from the same register, and inputs would always be loaded into the same register. A simple state machine would control each filter. The output of a given filter would be passed to the next filter, accompanied by a "valid" signal, which would start the state machine of the next filter. Multiple filter modules would share a multiplication/accumulation arithmetic unit. The filter computations would be timed by use of a clock having a frequency high enough, relative to the input and output data rate, to provide enough cycles for matrix and vector arithmetic operations. This design concept could prove beneficial in numerous applications in which digital filters are used and/or vectors are multiplied by coefficient matrices. Examples of such applications include general signal processing, filtering of signals in control systems, processing of geophysical measurements, and medical imaging. For these and other applications, it could be

  20. Design and implementation of universal mathematical library supporting algorithm development for FPGA based systems in high energy physics experiments

    International Nuclear Information System (INIS)

    Jalmuzna, W.

    2006-02-01

    The X-ray free-electron laser XFEL that is being planned at the DESY research center in cooperation with European partners will produce high-intensity ultra-short Xray flashes with the properties of laser light. This new light source, which can only be described in terms of superlatives, will open up a whole range of new perspectives for the natural sciences. It could also offer very promising opportunities for industrial users. SIMCON (SIMulator and CONtroller) is the project of the fast, low latency digital controller dedicated for LLRF system in VUV FEL experiment based on modern FPGA chips It is being developed by ELHEP group in Institute of Electronic Systems at Warsaw University of Technology. The main purpose of the project is to create a controller for stabilizing the vector sum of fields in cavities of one cryomodule in the experiment. The device can be also used as the simulator of the cavity and testbench for other devices. Flexibility and computation power of this device allow implementation of fast mathematical algorithms. This paper describes the concept, implementation and tests of universal mathematical library for FPGA algorithm implementation. It consists of many useful components such as IQ demodulator, division block, library for complex and floating point operations, etc. It is able to speed up implementation time of many complicated algorithms. Library have already been tested using real accelerator signals and the performance achieved is satisfactory. (Orig.)

  1. Design and implementation of universal mathematical library supporting algorithm development for FPGA based systems in high energy physics experiments

    Energy Technology Data Exchange (ETDEWEB)

    Jalmuzna, W.

    2006-02-15

    The X-ray free-electron laser XFEL that is being planned at the DESY research center in cooperation with European partners will produce high-intensity ultra-short Xray flashes with the properties of laser light. This new light source, which can only be described in terms of superlatives, will open up a whole range of new perspectives for the natural sciences. It could also offer very promising opportunities for industrial users. SIMCON (SIMulator and CONtroller) is the project of the fast, low latency digital controller dedicated for LLRF system in VUV FEL experiment based on modern FPGA chips It is being developed by ELHEP group in Institute of Electronic Systems at Warsaw University of Technology. The main purpose of the project is to create a controller for stabilizing the vector sum of fields in cavities of one cryomodule in the experiment. The device can be also used as the simulator of the cavity and testbench for other devices. Flexibility and computation power of this device allow implementation of fast mathematical algorithms. This paper describes the concept, implementation and tests of universal mathematical library for FPGA algorithm implementation. It consists of many useful components such as IQ demodulator, division block, library for complex and floating point operations, etc. It is able to speed up implementation time of many complicated algorithms. Library have already been tested using real accelerator signals and the performance achieved is satisfactory. (Orig.)

  2. An Efficient, FPGA-Based, Cluster Detection Algorithm Implementation for a Strip Detector Readout System in a Time Projection Chamber Polarimeter

    Science.gov (United States)

    Gregory, Kyle J.; Hill, Joanne E. (Editor); Black, J. Kevin; Baumgartner, Wayne H.; Jahoda, Keith

    2016-01-01

    A fundamental challenge in a spaceborne application of a gas-based Time Projection Chamber (TPC) for observation of X-ray polarization is handling the large amount of data collected. The TPC polarimeter described uses the APV-25 Application Specific Integrated Circuit (ASIC) to readout a strip detector. Two dimensional photoelectron track images are created with a time projection technique and used to determine the polarization of the incident X-rays. The detector produces a 128x30 pixel image per photon interaction with each pixel registering 12 bits of collected charge. This creates challenging requirements for data storage and downlink bandwidth with only a modest incidence of photons and can have a significant impact on the overall mission cost. An approach is described for locating and isolating the photoelectron track within the detector image, yielding a much smaller data product, typically between 8x8 pixels and 20x20 pixels. This approach is implemented using a Microsemi RT-ProASIC3-3000 Field-Programmable Gate Array (FPGA), clocked at 20 MHz and utilizing 10.7k logic gates (14% of FPGA), 20 Block RAMs (17% of FPGA), and no external RAM. Results will be presented, demonstrating successful photoelectron track cluster detection with minimal impact to detector dead-time.

  3. Design and FPGA-implementation of multilayer neural networks with on-chip learning

    International Nuclear Information System (INIS)

    Haggag, S.S.M.Y

    2008-01-01

    Artificial Neural Networks (ANN) is used in many applications in the industry because of their parallel structure, high speed, and their ability to give easy solution to complicated problems. For example identifying the orange and apple in the sorting machine with neural network is easier than using image processing techniques to do the same thing. There are different software for designing, training, and testing the ANN, but in order to use the ANN in the industry, it should be implemented on hardware outside the computer. Neural networks are artificial systems inspired on the brain's cognitive behavior, which can learn tasks with some degree of complexity, such as signal processing, diagnosis, robotics, image processing, and pattern recognition. Many applications demand a high computing power and the traditional software implementation are not sufficient.This thesis presents design and FPGA implementation of Multilayer Neural Networks with On-chip learning in re-configurable hardware. Hardware implementation of neural network algorithm is very interesting due their high performance and they can easily be made parallel. The architecture proposed herein takes advantage of distinct data paths for the forward and backward propagation stages and a pipelined adaptation of the on- line backpropagation algorithm to significantly improve the performance of the learning phase. The architecture is easily scalable and able to cope with arbitrary network sizes with the same hardware. The implementation is targeted diagnosis of the Research Reactor accidents to avoid the risk of occurrence of a nuclear accident. The proposed designed circuits are implemented using Xilinx FPGA Chip XC40150xv and occupied 73% of Chip CLBs. It achieved 10.8 μs to take decision in the forward propagation compared with current software implemented of RPS which take 24 ms. The results show that the proposed architecture leads to significant speed up comparing to high end software solutions. On

  4. Mesomorphic structure of poly(styrene)-block-poly(4-vinylpyridine) with oligo(ethylene oxide)sulfonic acid side chains as a model for molecularly reinforced polymer electrolyte

    NARCIS (Netherlands)

    Kosonen, H; Valkama, S; Hartikainen, J; Eerikainen, H; Torkkeli, M; Jokela, K; Serimaa, R; Sundholm, F; ten Brinke, G; Ikkala, O; Eerikäinen, Hannele

    2002-01-01

    We report self-organized polymer electrolytes based on poly(styrene)-block-poly(4-vinylpyridine) (PS-block-P4VP). Liquidlike ethylene oxide (EO) oligomers with sulfonic acid end groups are bonded to the P4VP block, leading to comb-shaped supramolecules with the PS-block-P4VP backbone. Lithium

  5. A real-time MTFC algorithm of space remote-sensing camera based on FPGA

    Science.gov (United States)

    Zhao, Liting; Huang, Gang; Lin, Zhe

    2018-01-01

    A real-time MTFC algorithm of space remote-sensing camera based on FPGA was designed. The algorithm can provide real-time image processing to enhance image clarity when the remote-sensing camera running on-orbit. The image restoration algorithm adopted modular design. The MTF measurement calculation module on-orbit had the function of calculating the edge extension function, line extension function, ESF difference operation, normalization MTF and MTFC parameters. The MTFC image filtering and noise suppression had the function of filtering algorithm and effectively suppressing the noise. The algorithm used System Generator to design the image processing algorithms to simplify the design structure of system and the process redesign. The image gray gradient dot sharpness edge contrast and median-high frequency were enhanced. The image SNR after recovery reduced less than 1 dB compared to the original image. The image restoration system can be widely used in various fields.

  6. A Study of BUS Architecture Design for Controller of Nuclear Power Plant Using FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Dongil; Yun, Donghwa; Hwang, Sungjae; Kim, Myeongyun; Lee, Dongyun [PONUTech Co. Ltd., Seoul (Korea, Republic of)

    2014-05-15

    CPU (Central Processing Unit) operating speed and communication rate have been more technically improved than before. However, whole system is been a degradation of performance by electronic and structural limitation of parallel bus. Transmission quantity and speed have a limit and need arbiter in order to do arbitration because several boards shared parallel bus. Arbiter is a high complexity in implementing so it increases component per chip. If a parallel bus uses, it will occurs some problems what are reflection noise, power/ground noise (or ground bounce) as SSN (Simultaneous Switching Noise) and crosstalk noise like magnetic coupling. In this paper, in order to solve a problem of parallel bus in controller of NPP (Nuclear Power Plant), proposes the bus architecture design using FPGA (Field Programmable Gate Array) based on LVDS (Low Voltage Differential Signaling)

  7. A Study of BUS Architecture Design for Controller of Nuclear Power Plant Using FPGA

    International Nuclear Information System (INIS)

    Lee, Dongil; Yun, Donghwa; Hwang, Sungjae; Kim, Myeongyun; Lee, Dongyun

    2014-01-01

    CPU (Central Processing Unit) operating speed and communication rate have been more technically improved than before. However, whole system is been a degradation of performance by electronic and structural limitation of parallel bus. Transmission quantity and speed have a limit and need arbiter in order to do arbitration because several boards shared parallel bus. Arbiter is a high complexity in implementing so it increases component per chip. If a parallel bus uses, it will occurs some problems what are reflection noise, power/ground noise (or ground bounce) as SSN (Simultaneous Switching Noise) and crosstalk noise like magnetic coupling. In this paper, in order to solve a problem of parallel bus in controller of NPP (Nuclear Power Plant), proposes the bus architecture design using FPGA (Field Programmable Gate Array) based on LVDS (Low Voltage Differential Signaling)

  8. Design and demonstration of a multitechnology FPGA for photonic information processing

    Science.gov (United States)

    Mal, Prosenjit; Hawk, Chris; Toshniwal, Kavita; Beyette, Fred R., Jr.

    2003-11-01

    We present here a novel architecture for a multi-technology field programmabler gate array (MT-FPGA). Implemented with a conventional CMOS VLSI technology the architecture is suitable for prototyping photonic information processing systems. We report here that this new FPGA architecture will enable the design of reconfigurable systems that incorporate technologies outside the traditional electronic domain.

  9. Implementation of a feed-forward artificial neural network in VHDL on FPGA

    NARCIS (Netherlands)

    Dondon, P.; Carvalho, J.; Gardere, R.; Lahalle, P.; Tsenov, G.; Mladenov, V.M.; Reljin, B.; Stankovic, S.

    2014-01-01

    Describing an Artificial Neural Network (ANN) using VHDL allows a further implementation of such a system on FPGA. Indeed, the principal point of using FPGA for ANNs is flexibility that gives it an advantage toward other systems like ASICS which are entirely dedicated to one unique architecture and

  10. Development of a multi-purpose logic module with the FPGA

    International Nuclear Information System (INIS)

    Nanbu, K.; Ishikawa, T.; Shimizu, H.

    2008-01-01

    We have developed a multi-purpose logic module (MPLM) with an FPGA. The internal circuit of this module can be modified easily with the FPGA. This kind of module enables trigger pulse processing for nuclear science. As a first step, the MPLM is used as an event tag generator in experiments with the FOREST detector system. (author)

  11. An FPGA bridge preserving traffing quality of service for on-chip network-based systems

    NARCIS (Netherlands)

    Nejad, A.B.; Escudero Martinez, M.; Goossens, K.G.W.

    2011-01-01

    FPGA prototyping of recent large Systems on Chip (SoCs) is very challenging due to the resource limitation of a single FPGA. Moreover, having external access to SoCs for verification and debug purposes is essential. In this paper, we suggest to partition a network-on-chip (NoC) based system into

  12. Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration

    NARCIS (Netherlands)

    Becher, Andreas; Bauer, Florian; Ziener, Daniel; Teich, Jürgen

    2014-01-01

    In this paper, we propose an approach for energy-aware FPGA-based query acceleration for databases on embedded devices. After the analysis of an incoming query, a query-specific hardware accelerator is generated on-the-fly and loaded on the FPGA for subsequent query execution using partial dynamic

  13. Exploration of government policy structure which support and block energy transition process in indonesia using system dynamics model

    Science.gov (United States)

    Destyanto, A. R.; Silalahi, T. D.; Hidayatno, A.

    2017-11-01

    System dynamic modeling is widely used to predict and simulate the energy system in several countries. One of the applications of system dynamics is to evaluate national energy policy alternatives, and energy efficiency analysis. Using system dynamic modeling, this research aims to evaluate the energy transition policy that has been implemented in Indonesia on the past conversion program of kerosene to LPG for household cook fuel consumption, which considered as successful energy transition program implemented since 2007. This research is important since Indonesia considered not yet succeeded to execute another energy transition program on conversion program of oil fuel to gas fuel for transportation that has started since 1989. The aim of this research is to explore which policy intervention that has significant contribution to support or even block the conversion program. Findings in this simulation show that policy intervention to withdraw the kerosene supply and government push to increase production capacity of the support equipment industries (gas stove, regulator, and LPG Cylinder) is the main influence on the success of the program conversion program.

  14. Multirate Digital Filters Based on FPGA and Its Applications

    International Nuclear Information System (INIS)

    Sharaf El-Din, R.M.A.

    2013-01-01

    Digital Signal Processing (DSP) is one of the fastest growing techniques in the electronics industry. It is used in a wide range of application fields such as, telecommunications, data communications, image enhancement and processing, video signals, digital TV broadcasting, and voice synthesis and recognition. Field Programmable Gate Array (FPGA) offers good solution for addressing the needs of high performance DSP systems. The focus of this thesis is on one of the basic DSP functions, namely filtering signals to remove unwanted frequency bands. Multi rate Digital Filters (MDFs) are the main theme here. Theory and implementation of MDF, as a special class of digital filters, will be discussed. Multi rate digital filters represent a class of digital filters having a number of attractive features like, low requirements for the coefficient word lengths, significant saving in computation and storage requirements results in a significant reduction in its dynamic power consumption. This thesis introduces an efficient FPGA realization of a multi rate decimation filter with narrow pass-band and narrow transition band to reduce the frequency sample rate by factor of 64 for noise thermometer applications. The proposed multi rate decimation filter is composed of three stages; the first stage is a Cascaded Integrator Comb (CIC) decimation filter, the second stage is a two-coefficient Half-Band (HB) filter and the last stage is a sharper transition HB filter. The frequency responses of individual stages as well as the overall filter response have been demonstrated with full simulation using MATLAB. The design and implementation of the proposed MDF on FPGA (XILINX Virtex XCV800 BG432-4), using VHSIC Hardware Description Language (VHDL), has been introduced. The implementation areas of the proposed filter stages are compared. Using CIC-HB technique saves 18% of the design area, compared to using six stages HB decimation filters.

  15. Delay model and performance testing for FPGA carry chain TDC

    International Nuclear Information System (INIS)

    Kang Xiaowen; Liu Yaqiang; Cui Junjian Yang Zhangcan; Jin Yongjie

    2011-01-01

    Time-of-flight (TOF) information would improve the performance of PET (position emission tomography). TDC design is a key technique. It proposed Carry Chain TDC Delay model. Through changing the significant delay parameter of model, paper compared the difference of TDC performance, and finally realized Time-to-Digital Convertor (TDC) based on Carry Chain Method using FPGA EP2C20Q240C8N with 69 ps LSB, max error below 2 LSB. Such result could meet the TOF demand. It also proposed a Coaxial Cable Measuring method for TDC testing, without High-precision test equipment. (authors)

  16. IMPLEMENTATION OF SERIAL AND PARALLEL BUBBLE SORT ON FPGA

    Directory of Open Access Journals (Sweden)

    Dwi Marhaendro Jati Purnomo

    2016-06-01

    Full Text Available Sorting is common process in computational world. Its utilization are on many fields from research to industry. There are many sorting algorithm in nowadays. One of the simplest yet powerful is bubble sort. In this study, bubble sort is implemented on FPGA. The implementation was taken on serial and parallel approach. Serial and parallel bubble sort then compared by means of its memory, execution time, and utility which comprises slices and LUTs. The experiments show that serial bubble sort required smaller memory as well as utility compared to parallel bubble sort. Meanwhile, parallel bubble sort performed faster than serial bubble sort

  17. Enhanced Temperature Control Method Using ANFIS with FPGA

    Directory of Open Access Journals (Sweden)

    Chiung-Wei Huang

    2014-01-01

    Full Text Available Temperature control in etching process is important for semiconductor manufacturing technology. However, pressure variations in vacuum chamber results in a change in temperature, worsening the accuracy of the temperature of the wafer and the speed and quality of the etching process. This work develops an adaptive network-based fuzzy inference system (ANFIS using a field-programmable gate array (FPGA to improve the effectiveness. The proposed method adjusts every membership function to keep the temperature in the chamber stable. The improvement of the proposed algorithm is confirmed using a medium vacuum (MV inductively-coupled plasma- (ICP- type etcher.

  18. Energy Efficient FPGA based Hardware Accelerators for Financial Applications

    DEFF Research Database (Denmark)

    Kenn Toft, Jakob; Nannarelli, Alberto

    2014-01-01

    Field Programmable Gate Arrays (FPGAs) based accelerators are very suitable to implement application-specific processors using uncommon operations or number systems. In this work, we design FPGA-based accelerators for two financial computations with different characteristics and we compare...... the accelerator performance and energy consumption to a software execution of the application. The experimental results show that significant speed-up and energy savings, can be obtained for large data sets by using the accelerator at expenses of a longer development time....

  19. FPGA curved track fitter with very low resource usage

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Jin-Yuan; Wang, M.; Gottschalk, E.; Shi, Z.; /Fermilab

    2006-11-01

    Standard least-squares curved track fitting process is tailored for FPGA implementation. The coefficients in the fitting matrices are carefully chosen so that only shift and accumulation operations are used in the process. The divisions and full multiplications are eliminated. Comparison in an application example shows that the fitting errors of the low resource usage implementation are less than 4% bigger than the fitting errors of the exact least-squares algorithm. The implementation is suitable for low-cost, low-power applications such as high energy physics detector trigger systems.

  20. Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

    Directory of Open Access Journals (Sweden)

    . Zulfikar

    2012-10-01

    Full Text Available A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits.

  1. Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

    Directory of Open Access Journals (Sweden)

    Zulfikar .

    2015-05-01

    Full Text Available A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits.

  2. FPGA implementation of adaptive beamforming in hearing aids.

    Science.gov (United States)

    Samtani, Kartik; Thomas, Jobin; Varma, G Abhinav; Sumam, David S; Deepu, S P

    2017-07-01

    Beamforming is a spatial filtering technique used in hearing aids to improve target sound reception by reducing interference from other directions. In this paper we propose improvements in an existing architecture present for two omnidirectional microphone array based adaptive beamforming for hearing aid applications and implement the same on Xilinx Artix 7 FPGA using VHDL coding and Xilinx Vivado ® 2015.2. The nulls are introduced in particular directions by combination of two fixed polar patterns. This combination can be adaptively controlled to steer the null in the direction of noise. The beamform patterns and improvements in SNR values obtained from experiments in a conference room environment are analyzed.

  3. FPGA Based Low Power ROM Design Using Capacitance Scaling

    DEFF Research Database (Denmark)

    Bansal, Meenakshi; Bansal, Neha; Saini, Rishita

    2015-01-01

    An ideal capacitor will not dissipate any power, but a real capacitor wil l have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM w...... in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog....

  4. FPGA Implementation of Video Transmission System Based on LTE

    Directory of Open Access Journals (Sweden)

    Lu Yan

    2015-01-01

    Full Text Available In order to support high-definition video transmission, an implementation of video transmission system based on Long Term Evolution is designed. This system is developed on Xilinx Virtex-6 FPGA ML605 Evaluation Board. The paper elaborates the features of baseband link designed in Xilinx ISE and protocol stack designed in Xilinx SDK, and introduces the process of setting up hardware and software platform in Xilinx XPS. According to test, this system consumes less hardware resource and is able to transmit bidirectional video clearly and stably.

  5. LAPACKrc: Fast linear algebra kernels/solvers for FPGA accelerators

    International Nuclear Information System (INIS)

    Gonzalez, Juan; Nunez, Rafael C

    2009-01-01

    We present LAPACKrc, a family of FPGA-based linear algebra solvers able to achieve more than 100x speedup per commodity processor on certain problems. LAPACKrc subsumes some of the LAPACK and ScaLAPACK functionalities, and it also incorporates sparse direct and iterative matrix solvers. Current LAPACKrc prototypes demonstrate between 40x-150x speedup compared against top-of-the-line hardware/software systems. A technology roadmap is in place to validate current performance of LAPACKrc in HPC applications, and to increase the computational throughput by factors of hundreds within the next few years.

  6. SRF cavity testing using a FPGA Self Excited Loop

    Energy Technology Data Exchange (ETDEWEB)

    Ben-Zvi, I. [Brookhaven National Lab. (BNL), Upton, NY (United States)

    2017-08-30

    Various authors have previously studied the theory and practice of cavity testing, notably an extensive treatment by Powers [1] and Padamsee [2]. The advent of the digital Low Level RF (LLRF) electronics based on Field Programmable Logic Arrays (FPGA) provides various improvements over the rather complex systems used in the past as well as enabling new measurement techniques.In this document we reintroduce a technique that seems to have fallen out of practice in recent times, that is obtaining the coupling constant β through measurements from just one port, the reflected power port, of the directional coupler placed in front of the cavity.

  7. SRF cavity testing using a FPGA Self Excited Loop

    CERN Document Server

    Ben-Zvi, Ilan

    2018-01-01

    This document provides a detailed description of procedures for very-high precision calibration and testing of superconducting RF cavities using digital Low-Level RF (LLRF) electronics based on Field Programmable Gate Arrays (FPGA). The use of a Self-Excited Loop with an innovative procedure for fast turn-on allows the measurement of the forward, reflected and transmitted power from a single port of the directional coupler in front of the cavity, thus eliminating certain measurement errors. Various procedures for measuring the quality factor as a function of cavity fields are described, including a single RF pulse technique. Errors are estimated for the measurements.

  8. Compact FPGA hardware architecture for public key encryption in embedded devices.

    Science.gov (United States)

    Rodríguez-Flores, Luis; Morales-Sandoval, Miguel; Cumplido, René; Feregrino-Uribe, Claudia; Algredo-Badillo, Ignacio

    2018-01-01

    Security is a crucial requirement in the envisioned applications of the Internet of Things (IoT), where most of the underlying computing platforms are embedded systems with reduced computing capabilities and energy constraints. In this paper we present the design and evaluation of a scalable low-area FPGA hardware architecture that serves as a building block to accelerate the costly operations of exponentiation and multiplication in [Formula: see text], commonly required in security protocols relying on public key encryption, such as in key agreement, authentication and digital signature. The proposed design can process operands of different size using the same datapath, which exhibits a significant reduction in area without loss of efficiency if compared to representative state of the art designs. For example, our design uses 96% less standard logic than a similar design optimized for performance, and 46% less resources than other design optimized for area. Even using fewer area resources, our design still performs better than its embedded software counterparts (190x and 697x).

  9. An FPGA-Based Omnidirectional Vision Sensor for Motion Detection on Mobile Robots

    Directory of Open Access Journals (Sweden)

    Jones Y. Mori

    2012-01-01

    Full Text Available This work presents the development of an integrated hardware/software sensor system for moving object detection and distance calculation, based on background subtraction algorithm. The sensor comprises a catadioptric system composed by a camera and a convex mirror that reflects the environment to the camera from all directions, obtaining a panoramic view. The sensor is used as an omnidirectional vision system, allowing for localization and navigation tasks of mobile robots. Several image processing operations such as filtering, segmentation and morphology have been included in the processing architecture. For achieving distance measurement, an algorithm to determine the center of mass of a detected object was implemented. The overall architecture has been mapped onto a commercial low-cost FPGA device, using a hardware/software co-design approach, which comprises a Nios II embedded microprocessor and specific image processing blocks, which have been implemented in hardware. The background subtraction algorithm was also used to calibrate the system, allowing for accurate results. Synthesis results show that the system can achieve a throughput of 26.6 processed frames per second and the performance analysis pointed out that the overall architecture achieves a speedup factor of 13.78 in comparison with a PC-based solution running on the real-time operating system xPC Target.

  10. Structural studies of three-arm star block copolymers exposed to extreme stretch suggests persistent polymer tube

    DEFF Research Database (Denmark)

    Garvey, Christopher J.; Almdal, Kristoffer; Dorokhin, Andriy

    2018-01-01

    We present structural SANS-studies of a three-armed polystyrene star polymer with short deuterated segments at the end of each arm. We show that the form factor of the three-armed star molecules in the relaxed state agrees with that of the random phase approximation of Gaussian chains. Upon...

  11. Emplacement of small and large buffer blocks

    International Nuclear Information System (INIS)

    Saari, H.; Nikula, M.; Suikki, M.

    2010-05-01

    The report describes emplacement of a buffer structure encircling a spent fuel canister to be deposited in a vertical hole. The report deals with installability of various size blocks and with an emplacement gear, as well as evaluates the achieved quality of emplacement and the time needed for installing the buffer. Two block assembly of unequal size were chosen for examination. A first option involved small blocks, the use of which resulted in a buffer structure consisting of small sector blocks 200 mm in height. A second option involved large blocks, resulting in a buffer structure which consists of eight blocks. In these tests, the material chosen for both block options was concrete instead of bentonite. The emplacement test was a three-phase process. A first phase included stacking a two meter high buffer structure with small blocks for ensuring the operation of test equipment and blocks. A second phase included installing buffer structures with both block options to a height matching that of a canister-encircling cylindrical component. A third phase included testing also the installability of blocks to be placed above the canister by using small blocks. In emplacement tests, special attention was paid to the installability of blocks as well as to the time required for emplacement. Lifters for both blocks worked well. Due to the mass to be lifted, the lifter for large blocks had a more heavy-duty frame structure (and other lifting gear). The employed lifters were suspended in the tests on a single steel wire rope. Stacking was managed with both block sizes at adequate precision and stacked-up towers were steady. The stacking of large blocks was considerably faster. Therefore it is probably that the overall handling of the large blocks will be more convenient at a final disposal site. From the standpoint of reliability in lifting, the small blocks were safer to install above the canister. In large blocks, there are strict shape-related requirements which are

  12. Structural Studies of Three-Arm Star Block Copolymers Exposed to Extreme Stretch Suggests a Persistent Polymer Tube

    Science.gov (United States)

    Mortensen, Kell; Borger, Anine L.; Kirkensgaard, Jacob J. K.; Garvey, Christopher J.; Almdal, Kristoffer; Dorokhin, Andriy; Huang, Qian; Hassager, Ole

    2018-05-01

    We present structural small-angle neutron scattering studies of a three-armed polystyrene star polymer with short deuterated segments at the end of each arm. We show that the form factor of the three-armed star molecules in the relaxed state agrees with that of the random phase approximation of Gaussian chains. Upon exposure to large extensional flow conditions, the star polymers change conformation resulting in a highly stretched structure that mimics a fully extended three-armed tube model. All three arms are parallel to the flow, one arm being either in positive or negative stretching direction, while the two other arms are oriented parallel, right next to each other in the direction opposite to the first arm.

  13. Effect of the Cationic Block Structure on the Characteristics of Sludge Flocs Formed by Charge Neutralization and Patching

    Directory of Open Access Journals (Sweden)

    Huaili Zheng

    2017-05-01

    Full Text Available In this study, a template copolymer (TPAA of (3-Acrylamidopropyl trimethylammonium chloride (AATPAC and acrylamide (AM was successfully synthesized though ultrasonic-initiated template copolymerization (UTP, using sodium polyacrylate (PAAS as a template. TPAA was characterized by an evident cationic microblock structure which was observed through the analyses of the reactivity ratio, Fourier transform infrared spectroscopy (FTIR, 1H (13C nuclear magnetic resonance spectroscopy (1H (13C NMR, and thermogravimetry/differential scanning calorimetry (TG/DSC. The introduction of the template could improve the monomer (AATPAC reactivity ratio and increase the length and amount of AATPAC segments. This novel cationic microblock structure extremely enhanced the ability of charge neutralization, patching, and bridging, thus improving the activated sludge flocculation performance. The experiments of floc formation, breakage, and regrowth revealed that the cationic microblock structure in the copolymer resulted in large and compact flocs, and these flocs had a rapid regrowth when broken. Finally, the larger and more compact flocs contributed to the formation of more channels and voids, and therefore the specific resistance to filtration (SRF reached a minimum.

  14. A new FPGA architecture suitable for DSP applications

    Energy Technology Data Exchange (ETDEWEB)

    Wang Liyun; Lai Jinmei; Tong Jiarong; Tang Pushan; Chen Xing; Duan Xueyan; Chen Liguang; Wang Jian; Wang Yuan, E-mail: 071021037@fudan.edu.cn [ASIC and System State Key Laboratory, Fudan University, Shanghai 201203 (China)

    2011-05-15

    A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 {mu}m CMOS technology successfully. The die size is 6.3 x 4.5 mm{sup 2} with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs. (semiconductor integrated circuits)

  15. An FPGA Implementation of Secured Steganography Communication System

    Directory of Open Access Journals (Sweden)

    Ahlam Fadhil Mahmood

    2013-04-01

    Full Text Available     Steganography is the idea of hiding secret message in multimedia cover which will be transmitted through the Internet. The cover carriers can be image, video, sound or text data. This paper presents an implementation of color image steganographic system on Field Programmable Gate Array and the information hiding/extracting techniques in various images. The proposed algorithm is based on merge between the idea from the random pixel manipulation methods and the Least Significant Bit (LSB matching of Steganography embedding and extracting method.        In a proposed steganography hardware approach, Linear Feedback Shift Register (LFSR method has been used in stego architecture to hide the information in the image. The LFSRs are utilized in this approach as address generators. Different LFSR arrangements using different connection unit have been implemented at the hardware level for hiding/extracting the secret data. Multilayer embedding is implemented in parallel manner with a three-stage pipeline on FPGA.      This work showed attractive results especially in the high throughputs, better stego-image quality, requires little calculation and less utilization of FPGA area. The imperceptibility of the technique combined with high payload, robustness of embedded data and accurate data retrieval renders the proposed Steganography system is suitable for covert communication and secures data transmission applications

  16. An FPGA Implementation of Secured Steganography Communication System

    Directory of Open Access Journals (Sweden)

    Ahlam Mahmood

    2014-04-01

    Full Text Available Steganography is the idea of hiding secret message in multimedia cover which will be transmitted through the Internet. The cover carriers can be image, video, sound or text data. This paper presents an implementation of color image steganographic system on Field Programmable Gate Array and the information hiding/extracting techniques in various images. The proposed algorithm is based on merge between the idea from the random pixel manipulation methods and the Least Significant Bit (LSB matching of Steganography embedding and extracting method.  In a proposed steganography hardware approach, Linear Feedback Shift Register (LFSR method has been used in stego architecture to hide the information in the image. The LFSRs are utilized in this approach as address generators. Different LFSR arrangements using different connection unit have been implemented at the hardware level for hiding/extracting the secret data. Multilayer embedding is implemented in parallel manner with a three-stage pipeline on FPGA.  This work showed attractive results especially in the high throughputs, better stego-image quality, requires little calculation and less utilization of FPGA area. The imperceptibility of the technique combined with high payload, robustness of embedded data and accurate data retrieval renders the proposed Steganography system is suitable for covert communication and secure data transmission applications

  17. FPGA platform for MEMS Disc Resonance Gyroscope (DRG) control

    Science.gov (United States)

    Keymeulen, Didier; Peay, Chris; Foor, David; Trung, Tran; Bakhshi, Alireza; Withington, Phil; Yee, Karl; Terrile, Rich

    2008-04-01

    Inertial navigation systems based upon optical gyroscopes tend to be expensive, large, power consumptive, and are not long lived. Micro-Electromechanical Systems (MEMS) based gyros do not have these shortcomings; however, until recently, the performance of MEMS based gyros had been below navigation grade. Boeing and JPL have been cooperating since 1997 to develop high performance MEMS gyroscopes for miniature, low power space Inertial Reference Unit applications. The efforts resulted in demonstration of a Post Resonator Gyroscope (PRG). This experience led to the more compact Disc Resonator Gyroscope (DRG) for further reduced size and power with potentially increased performance. Currently, the mass, volume and power of the DRG are dominated by the size of the electronics. This paper will detail the FPGA based digital electronics architecture and its implementation for the DRG which will allow reduction of size and power and will increase performance through a reduction in electronics noise. Using the digital control based on FPGA, we can program and modify in real-time the control loop to adapt to the specificity of each particular gyro and the change of the mechanical characteristic of the gyro during its life time.

  18. Optimizing latency in Xilinx FPGA implementations of the GBT

    International Nuclear Information System (INIS)

    Muschter, S; Bohm, C; Baron, S; Soos, C; Cachemiche, J-P

    2010-01-01

    The GigaBit Transceiver (GBT) system has been developed to replace the Timing, Trigger and Control (TTC) system, currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation. This code was optimized for resource utilization, as the GBT protocol is very demanding. It was not, however, optimized for latency - which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The latency optimization results were compared with measurement results from a Virtex 6 ML605 development board equipped with a XC6VLX240T with speedgrade-1 and the package FF1156. Bit error rate tests were also performed to ensure an error free operation. The two final optimizations were analyzed for utilization and compared with the original code, distributed in the Starter Kit.

  19. FPGA based algorithms for data reduction at Belle II

    Energy Technology Data Exchange (ETDEWEB)

    Muenchow, David; Gessler, Thomas; Kuehn, Wolfgang; Lange, Jens Soeren; Liu, Ming; Spruck, Bjoern [II. Physikalisches Institut, Universitaet Giessen (Germany)

    2011-07-01

    Belle II, the upgrade of the existing Belle experiment at Super-KEKB in Tsukuba, Japan, is an asymmetric e{sup +}e{sup -} collider with a design luminosity of 8.10{sup 35}cm{sup -2}s{sup -1}. At Belle II the estimated event rate is {<=}30 kHz. The resulting data rate at the Pixel Detector (PXD) will be {<=}7.2 GB/s. This data rate needs to be reduced to be able to process and store the data. A region of interest (ROI) selection is based upon two mechanisms. a.) a tracklet finder using the silicon strip detector and b.) the HLT using all other Belle II subdetectors. These ROIs and the pixel data are forwarded to an FPGA based Compute Node for processing. Here a VHDL based algorithm on FPGA with the benefit of pipelining and parallelisation will be implemented. For a fast data handling we developed a dedicated memory management system for buffering and storing the data. The status of the implementation and performance tests of the memory manager and data reduction algorithm is presented.

  20. FPGA Implementation of a Simple 3D Graphics Pipeline

    Directory of Open Access Journals (Sweden)

    Vladimir Kasik

    2015-01-01

    Full Text Available Conventional methods for computing 3D projects are nowadays usually implemented on standard or graphics processors. The performance of these devices is limited especially by the used architecture, which to some extent works in a sequential manner. In this article we describe a project which utilizes parallel computation for simple projection of a wireframe 3D model. The algorithm is optimized for a FPGA-based implementation. The design of the numerical logic is described in VHDL with the use of several basic IP cores used especially for computing trigonometric functions. The implemented algorithms allow smooth rotation of the model in two axes (azimuth and elevation and a change of the viewing angle. Tests carried out on a FPGA Xilinx Spartan-6 development board have resulted in real-time rendering at over 5000fps. In the conclusion of the article, we discuss additional possibilities for increasing the computational output in graphics applications via the use of HPC (High Performance Computing.

  1. Optimizing latency in Xilinx FPGA implementations of the GBT

    CERN Document Server

    Muschter, S; Bohm, C; Cachemiche, J-P; Baron, S

    2010-01-01

    The GigaBit Transceiver (GBT) {[}1] system has been developed to replace the Timing, Trigger and Control (TTC) system {[}2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation {[}3]. This code was optimized for resource utilization {[}4], as the GBT protocol is very demanding. It was not, however, optimized for latency - which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The la...

  2. Optimizing latency in Xilinx FPGA implementations of the GBT

    Science.gov (United States)

    Muschter, S.; Baron, S.; Bohm, C.; Cachemiche, J.-P.; Soos, C.

    2010-12-01

    The GigaBit Transceiver (GBT) [1] system has been developed to replace the Timing, Trigger and Control (TTC) system [2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation [3]. This code was optimized for resource utilization [4], as the GBT protocol is very demanding. It was not, however, optimized for latency — which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The latency optimization results were compared with measurement results from a Virtex 6 ML605 development board [5] equipped with a XC6VLX240T with speedgrade-1 and the package FF1156. Bit error rate tests were also performed to ensure an error free operation. The two final optimizations were analyzed for utilization and compared with the original code, distributed in the Starter Kit.

  3. A Sea-of-Gates Style FPGA Placement Algorithm

    Directory of Open Access Journals (Sweden)

    Kalapi Roy

    1996-01-01

    Full Text Available Field Programmable Gate Arrays (FPGAs have a pre-defined chip boundary with fixed cell locations and routing resources. Placement objectives for flexible architectures (e.g., the standard cell design style such as minimization of chip area do not reflect the primary placement goals for FPGAs. For FPGAs, the layout tools must seek 100% routability within the architectural constraints. Routability and congestion estimates must be made directly based on the demand and availability of routing resources for detailed routing of the particular FPGA. We. present a hierarchical placement approach consisting of two phases: a global placement phase followed by a detailed placement phase. The global placement phase minimizes congestion estimates of the global routing regions and satisfies all constraints at a coarser level. The detailed placer seeks to maximize the routability of the FPGA by considering factors which cause congestion at the detailed routing level and to precisely satisfy all of the constraints. Despite having limited knowledge about the gate level architectural details, we have achieved a 90%reduction in the number of unrouted nets in comparison to an industrial tool (the only other tool developed specifically for this architecture.

  4. FPGA Dynamic Power Minimization through Placement and Routing Constraints

    Directory of Open Access Journals (Sweden)

    Deepak Agarwal

    2006-08-01

    Full Text Available Field-programmable gate arrays (FPGAs are pervasive in embedded systems requiring low-power utilization. A novel power optimization methodology for reducing the dynamic power consumed by the routing of FPGA circuits by modifying the constraints applied to existing commercial tool sets is presented. The power optimization techniques influence commercial FPGA Place and Route (PAR tools by translating power goals into standard throughput and placement-based constraints. The Low-Power Intelligent Tool Environment (LITE is presented, which was developed to support the experimentation of power models and power optimization algorithms. The generated constraints seek to implement one of four power optimization approaches: slack minimization, clock tree paring, N-terminal net colocation, and area minimization. In an experimental study, we optimize dynamic power of circuits mapped into 0.12 μm Xilinx Virtex-II FPGAs. Results show that several optimization algorithms can be combined on a single design, and power is reduced by up to 19.4%, with an average power savings of 10.2%.

  5. Anti Theft Mechanism Through Face recognition Using FPGA

    Science.gov (United States)

    Sundari, Y. B. T.; Laxminarayana, G.; Laxmi, G. Vijaya

    2012-11-01

    The use of vehicle is must for everyone. At the same time, protection from theft is also very important. Prevention of vehicle theft can be done remotely by an authorized person. The location of the car can be found by using GPS and GSM controlled by FPGA. In this paper, face recognition is used to identify the persons and comparison is done with the preloaded faces for authorization. The vehicle will start only when the authorized personís face is identified. In the event of theft attempt or unauthorized personís trial to drive the vehicle, an MMS/SMS will be sent to the owner along with the location. Then the authorized person can alert the security personnel for tracking and catching the vehicle. For face recognition, a Principal Component Analysis (PCA) algorithm is developed using MATLAB. The control technique for GPS and GSM is developed using VHDL over SPTRAN 3E FPGA. The MMS sending method is written in VB6.0. The proposed application can be implemented with some modifications in the systems wherever the face recognition or detection is needed like, airports, international borders, banking applications etc.

  6. A shared synapse architecture for efficient FPGA implementation of autoencoders.

    Science.gov (United States)

    Suzuki, Akihiro; Morie, Takashi; Tamukoh, Hakaru

    2018-01-01

    This paper proposes a shared synapse architecture for autoencoders (AEs), and implements an AE with the proposed architecture as a digital circuit on a field-programmable gate array (FPGA). In the proposed architecture, the values of the synapse weights are shared between the synapses of an input and a hidden layer, and between the synapses of a hidden and an output layer. This architecture utilizes less of the limited resources of an FPGA than an architecture which does not share the synapse weights, and reduces the amount of synapse modules used by half. For the proposed circuit to be implemented into various types of AEs, it utilizes three kinds of parameters; one to change the number of layers' units, one to change the bit width of an internal value, and a learning rate. By altering a network configuration using these parameters, the proposed architecture can be used to construct a stacked AE. The proposed circuits are logically synthesized, and the number of their resources is determined. Our experimental results show that single and stacked AE circuits utilizing the proposed shared synapse architecture operate as regular AEs and as regular stacked AEs. The scalability of the proposed circuit and the relationship between the bit widths and the learning results are also determined. The clock cycles of the proposed circuits are formulated, and this formula is used to estimate the theoretical performance of the circuit when the circuit is used to construct arbitrary networks.

  7. A Correctness Verification Technique for Commercial FPGA Synthesis Tools

    International Nuclear Information System (INIS)

    Kim, Eui Sub; Yoo, Jun Beom; Choi, Jong Gyun; Kim, Jang Yeol; Lee, Jang Soo

    2014-01-01

    Once the FPGA (Filed-Programmable Gate Array) designers designs Verilog programs, the commercial synthesis tools automatically translate the Verilog programs into EDIF programs so that the designers can have largely focused on HDL designs for correctness of functionality. Nuclear regulation authorities, however, require more considerate demonstration of the correctness and safety of mechanical synthesis processes of FPGA synthesis tools, even if the FPGA industry have acknowledged them empirically as correct and safe processes and tools. In order to assure of the safety, the industry standards for the safety of electronic/electrical devices, such as IEC 61508 and IEC 60880, recommend using the formal verification technique. There are several formal verification tools (i.e., 'FormalPro' 'Conformal' 'Formality' and so on) to verify the correctness of translation from Verilog into EDIF programs, but it is too expensive to use and hard to apply them to the works of 3rd-party developers. This paper proposes a formal verification technique which can contribute to the correctness demonstration in part. It formally checks the behavioral equivalence between Verilog and subsequently synthesized Net list with the VIS verification system. A Net list is an intermediate output of FPGA synthesis process, and EDIF is used as a standard format of Net lists. If the formal verification succeeds, then we can assure that the synthesis process from Verilog into Net list worked correctly at least for the Verilog used. In order to support the formal verification, we developed the mechanical translator 'EDIFtoBLIFMV,' which translates EDIF into BLIF-MV as an input front-end of VIS system, while preserving their behavior equivalence.. We performed the case study with an example of a preliminary version of RPS in a Korean nuclear power plant in order to provide the efficiency of the proposed formal verification technique and implemented translator. It

  8. A Correctness Verification Technique for Commercial FPGA Synthesis Tools

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Eui Sub; Yoo, Jun Beom [Konkuk University, Seoul (Korea, Republic of); Choi, Jong Gyun; Kim, Jang Yeol; Lee, Jang Soo [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2014-10-15

    Once the FPGA (Filed-Programmable Gate Array) designers designs Verilog programs, the commercial synthesis tools automatically translate the Verilog programs into EDIF programs so that the designers can have largely focused on HDL designs for correctness of functionality. Nuclear regulation authorities, however, require more considerate demonstration of the correctness and safety of mechanical synthesis processes of FPGA synthesis tools, even if the FPGA industry have acknowledged them empirically as correct and safe processes and tools. In order to assure of the safety, the industry standards for the safety of electronic/electrical devices, such as IEC 61508 and IEC 60880, recommend using the formal verification technique. There are several formal verification tools (i.e., 'FormalPro' 'Conformal' 'Formality' and so on) to verify the correctness of translation from Verilog into EDIF programs, but it is too expensive to use and hard to apply them to the works of 3rd-party developers. This paper proposes a formal verification technique which can contribute to the correctness demonstration in part. It formally checks the behavioral equivalence between Verilog and subsequently synthesized Net list with the VIS verification system. A Net list is an intermediate output of FPGA synthesis process, and EDIF is used as a standard format of Net lists. If the formal verification succeeds, then we can assure that the synthesis process from Verilog into Net list worked correctly at least for the Verilog used. In order to support the formal verification, we developed the mechanical translator 'EDIFtoBLIFMV,' which translates EDIF into BLIF-MV as an input front-end of VIS system, while preserving their behavior equivalence.. We performed the case study with an example of a preliminary version of RPS in a Korean nuclear power plant in order to provide the efficiency of the proposed formal verification technique and implemented translator. It

  9. Proposed and existing passive and inherent safety-related structures, systems, and components (building blocks) for advanced light-water reactors

    International Nuclear Information System (INIS)

    Forsberg, C.W.; Moses, D.L.; Lewis, E.B.; Gibson, R.; Pearson, R.; Reich, W.J.; Murphy, G.A.; Staunton, R.H.; Kohn, W.E.

    1989-10-01

    A nuclear power plant is composed of many structures, systems, and components (SSCs). Examples include emergency core cooling systems, feedwater systems, and electrical systems. The design of a reactor consists of combining various SSCs (building blocks) into an integrated plant design. A new reactor design is the result of combining old SSCs in new ways or use of new SSCs. This report identifies, describes, and characterizes SSCs with passive and inherent features that can be used to assure safety in light-water reactors. Existing, proposed, and speculative technologies are described. The following approaches were used to identify the technologies: world technical literature searches, world patent searches, and discussions with universities, national laboratories and industrial vendors. 214 refs., 105 figs., 26 tabs

  10. Proposed and existing passive and inherent safety-related structures, systems, and components (building blocks) for advanced light-water reactors

    Energy Technology Data Exchange (ETDEWEB)

    Forsberg, C.W.; Moses, D.L.; Lewis, E.B.; Gibson, R.; Pearson, R.; Reich, W.J.; Murphy, G.A.; Staunton, R.H.; Kohn, W.E.

    1989-10-01

    A nuclear power plant is composed of many structures, systems, and components (SSCs). Examples include emergency core cooling systems, feedwater systems, and electrical systems. The design of a reactor consists of combining various SSCs (building blocks) into an integrated plant design. A new reactor design is the result of combining old SSCs in new ways or use of new SSCs. This report identifies, describes, and characterizes SSCs with passive and inherent features that can be used to assure safety in light-water reactors. Existing, proposed, and speculative technologies are described. The following approaches were used to identify the technologies: world technical literature searches, world patent searches, and discussions with universities, national laboratories and industrial vendors. 214 refs., 105 figs., 26 tabs.

  11. Analysis the evaluation of reinforces concrete structure Block 62 by Non Destructive Method, Destructive Method and Esteem Computer Program

    International Nuclear Information System (INIS)

    Mohd Jamil Hashim; Norhazwani Mohd Azahari

    2012-01-01

    The evaluation of old and unrecorded building is a difficult task to work on. This is because no detail record of building component such as reinforce concrete strength test record, type of reinforcement used, construction methods and soil investigation (SI) which make it impossible to analyse. Through NDT building reinforced concrete component is easily evaluated and mean while DT method give assurance through actual sample testing. From these early result detail drawing plans can be rebuild and building forensic work can be done. These data will be fed into the computer program to produce a structure evaluation result whether it is safe or not in accordance to design standard BS8110. (author)

  12. Chiral 1,2- and 1,3-diol-functionalized chromophores as Lego building blocks for coupled structures.

    Science.gov (United States)

    Spange, Stefan; Hofmann, Katja; Walfort, Bernhard; Rüffer, Tobias; Lang, Heinrich

    2005-10-14

    Chiral nitroanilines containing 1,2- or 1,3-diol functionalities have been synthesized by nucleophilic aromatic substitution of fluoronitroanilines with 1-aminopropane-2,3-diols and 2-aminopropane-1,3-diol in the melt. X-ray structure analyses confirm retention of the configuration of the chiral center. The novel chromophores are suitable to link reversibly to various substituted arylboronic acids which allows the construction of new solvatochromic sensor molecules suitable to response to solvent and anion coordination by fluoride. The solvatochromism of the new compounds has been studied using the Kamlet-Taft LSE relationship.

  13. Analysis of Block OMP using Block RIP

    OpenAIRE

    Wang, Jun; Li, Gang; Zhang, Hao; Wang, Xiqin

    2011-01-01

    Orthogonal matching pursuit (OMP) is a canonical greedy algorithm for sparse signal reconstruction. When the signal of interest is block sparse, i.e., it has nonzero coefficients occurring in clusters, the block version of OMP algorithm (i.e., Block OMP) outperforms the conventional OMP. In this paper, we demonstrate that a new notion of block restricted isometry property (Block RIP), which is less stringent than standard restricted isometry property (RIP), can be used for a very straightforw...

  14. Crystal structures of functional building blocks derived from bis(benzo[b]thiophen-2-yl)methane.

    Science.gov (United States)

    Katzsch, Felix; Gruber, Tobias; Weber, Edwin

    2016-09-01

    The syntheses of three bis(benzo[b]thiophen-2-yl)methane derivatives, namely bis(benzo[b]thiophen-2-yl)methanone, C17H10OS2, (I), 1,1-bis(benzo[b]thiophen-2-yl)-3-(trimethylsilyl)prop-2-yn-1-ol, C22H20OS2Si, (II), and 1,1-bis(benzo[b]thiophen-2-yl)prop-2-yn-1-ol, C19H12OS2, (III), are described and their crystal structures discussed comparatively. The conformation of ketone (I) and the respective analogues are rather similar for most of the compounds compared. This is true for the interplanar angles, the Caryl-Cbridge-Caryl angles and the dihedral angles. The best resemblance is found for a bioisotere of (I), viz. 2,2'-dinaphthyl ketone, (VII). By way of interest, the crystal packings also reveal similarities between (I) and (VII). In (I), the edge-to-face interactions seen between two napthyl residues in (VII) are substituted by S...π contacts between the benzo[b]thiophen-2-yl units in (I). In the structures of the bis(benzo[b]thiophen-2-yl)methanols, i.e. (II) and (III), the interplanar angles are also quite similar compared with analogues and related active pharmaceutical ingredients (APIs) containing the dithiophen-2-ylmethane scaffold, though the dihedral angles show a larger variability and produce unsymmetrical molecules.

  15. Development of FPGA-based safety-related I and C systems

    Energy Technology Data Exchange (ETDEWEB)

    Goto, Y.; Oda, N.; Miyazaki, T.; Hayashi, T.; Sato, T.; Igawa, S. [08, Shinsugita-cho, Isogo-ku, Yokohama 235-8523 (Japan); 1, Toshiba-cho, Fuchu, Tokyo 183-8511 (Japan)

    2006-07-01

    Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system [1]. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

  16. Development of FPGA-based safety-related instrumentation and control systems

    Energy Technology Data Exchange (ETDEWEB)

    Oda, N.; Tanaka, A.; Izumi, M.; Tarumi, T.; Sato, T. [Toshiba Corporation, Isogo Nuclear Engineering Center, Yokohama (Japan)

    2004-07-01

    Toshiba has developed systems which perform signal processing by field programmable gate arrays (FPGA) for safety-related instrumentation and control systems. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing units (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. Considering application to safety-related systems, nonvolatile and non rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. The systems which Toshiba developed this time are Power range Monitor (PRM) and Trip Module (TM). These systems are compatible with the conventional analog-based systems and the CPU-based systems. Therefore, requested cost for upgrading will be minimized. Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

  17. Verification of FPGA-based NPP I and C systems. General approach and techniques

    International Nuclear Information System (INIS)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; Reva, Lubov; Siora, Alexander

    2011-01-01

    This paper presents a general approach and techniques for design and verification of Field Programmable Gates Arrays (FPGA)-based Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP). Appropriate regulatory documents used for I and C systems design, development, verification and validation (V and V) are discussed considering the latest international standards and guidelines. Typical development and V and V processes of FPGA electronic design for FPGA-based NPP I and C systems are presented. Some safety-related features of implementation process are discussed. Corresponding development artifacts, related to design and implementation activities are outlined. An approach to test-based verification of FPGA electronic design algorithms, used in FPGA-based reactor trip systems is proposed. The results of application of test-based techniques for assessment of FPGA electronic design algorithms for reactor trip system (RTS) produced by Research and Production Corporation (RPC) 'Radiy' are presented. Some principles of invariant-oriented verification for FPGA-based safety-critical systems are outlined. (author)

  18. An evaluation and acceptance of COTS software for FPGA-based controllers in NPPS

    International Nuclear Information System (INIS)

    Jung, Sejin; Kim, Eui-Sub; Yoo, Junbeom; Kim, Jang-Yeol; Choi, Jong Gyun

    2016-01-01

    Highlights: • All direct/indirect COTS SW should be dedicated. • FPGA synthesis tools are important for the safety of new digital I&Cs. • No standards/reports are yet available to deal with the indirect SW – FPGA synthesis tools. • This paper proposes a new evaluation/acceptance process and criteria for indirect SW. - Abstract: FPGA (Field-Programmable Gate Array) has received much attention from nuclear industry as an alternative platform of PLC (Programmable Logic Controller)-based digital I&C (Instrumentation & Control). Software aspect of FPGA development encompasses several commercial tools such as logic synthesis and P&R (Place & Route), which should be first dedicated in accordance with domestic standards based on EPRI NP-5652. Even if a state-of-the-art supplementary EPRI TR-1025243 makes an effort, the dedication of indirect COTS (Commercial Off-The-Shelf) SW such as FPGA logic synthesis tools has still caused a dispute. This paper proposes an acceptance process and evaluation criteria, specific to COTS SW, not commercial-grade direct items. It specifically incorporates indirect COTS SW and also provides categorized evaluation criteria for acceptance. It provides an explicit linkage between acceptance methods (Verification and Validation techniques) and evaluation criteria, too. We tried to perform the evaluation and acceptance process upon a commercial FPGA logic synthesis tool being used to develop a new FPGA-based digital I&C in Korea, and could confirm its applicability.

  19. Logic qualification of FPGA-based safety-related I and C systems

    International Nuclear Information System (INIS)

    Hayashi, Toshifumi; Oda, Naotaka; Ito, Toshiaki; Miyazaki, Tadashi; Haren, Yasuhiko

    2009-01-01

    We established a logic qualification method for FPGA-Based I and C safety-related use in Nuclear Power Plants Systems. The FPGA is a programmable logic device and has advantages that the programming is rigorous, simple verifiable, and the technology is stable. However, logic qualification of FPGA had been an issue to be solved when it is used in the safety-related systems, because FPGA is relatively new technology for the nuclear power industry. We employed a software-life cycle approach, because its development process is similar to that of conventional computer-based systems. There are some differences between the FPGA-Based systems and the computer-based systems in the implementation and integration of logic. We examined the FPGA logic implementation and integration process to identify any FPGA-Based system specific hazards. The identified hazards are (1) small logic errors, (2) timing errors, (3) logic synthesis errors, (4) place and route errors, and (5) logic embedding errors. We took the appropriate countermeasures to mitigate these hazards, and employed this logic qualification method in the qualification of the Power Range Monitor System for BWR Power Plants. (author)

  20. Electron microscopy of human peripheral nerves of clinical relevance to the practice of nerve blocks. A structural and ultrastructural review based on original experimental and laboratory data.

    Science.gov (United States)

    Reina, M A; Arriazu, R; Collier, C B; Sala-Blanch, X; Izquierdo, L; de Andrés, J

    2013-12-01

    The goal is to describe the ultrastructure of normal human peripheral nerves, and to highlight key aspects that are relevant to the practice of peripheral nerve block anaesthesia. Using samples of sciatic nerve obtained from patients, and dural sac, nerve root cuff and brachial plexus dissected from fresh human cadavers, an analysis of the structure of peripheral nerve axons and distribution of fascicles and topographic composition of the layers that cover the nerve is presented. Myelinated and unmyelinated axons, fascicles, epineurium, perineurium and endoneurium obtained from patients and fresh cadavers were studied by light microscopy using immunohistochemical techniques, and transmission and scanning electron microscopy. Structure of perineurium and intrafascicular capillaries, and its implications in blood-nerve barrier were revised. Each of the anatomical elements is analyzed individually with regard to its relevance to clinical practice to regional anaesthesia. Routine practice of regional anaesthetic techniques and ultrasound identification of nerve structures has led to conceptions, which repercussions may be relevant in future applications of these techniques. In this regard, the ultrastructural and histological perspective accomplished through findings of this study aims at enlightening arising questions within the field of regional anaesthesia. Copyright © 2013 Sociedad Española de Anestesiología, Reanimación y Terapéutica del Dolor. Published by Elsevier España. All rights reserved.

  1. Medicinal chemistry of small molecule CCR5 antagonists for blocking HIV-1 entry: a review of structural evolution.

    Science.gov (United States)

    Tian, Ye; Zhang, Dujuan; Zhan, Peng; Liu, Xinyong

    2014-01-01

    CCR5, a member of G protein-coupled receptors superfamily, plays an important role in the HIV-1 entry process. Antagonism of this receptor finally leads to the inhibition of R5 strains of HIV entry into the human cells. The identification of CCR5 antagonists as antiviral agents will provide more option for HAART. Now, more than a decade after the first small molecule CCR5 inhibitor was discovered, great achievements have been made. In this article, we will give a brief introduction of several series of small molecule CCR5 antagonists, focused on their appealing structure evolution, essential SAR information and thereof the enlightenment of strategies on CCR5 inhibitors design.

  2. Carry-chain propagation delay impacts on resolution of FPGA-based TDC

    International Nuclear Information System (INIS)

    Dong Lei; Yang Junfeng; Song Kezhu

    2014-01-01

    The architecture of carry chains in Field-Programmable Gate Array (FPGA) is introduced in this paper. The propagation delay time of the rising and falling edges in the carry chains are calculated according to the architecture and they are predicted not equal in most cases. Tests show that the measuring results of the propagation delay time in EP3C120F484C8N series FPGA of Altera are in line with the inference. The difference of propagation delay time results in different accuracies of Time-to-Digital Converter (TDC). This phenomenon shall be considered in the design of TDC implemented in FPGA. It can ensure better accuracy. (authors)

  3. Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

    International Nuclear Information System (INIS)

    Pappas, I; Kalenteridis, V; Vassiliadis, N; Pournara, H; Siozios, K; Koutroumpezis, G; Tatas, K; Nikolaidis, S; Siskos, S; Soudris, D J; Thanailakis, A

    2005-01-01

    A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. A novel energy-efficient FPGA architecture is presented (CLB, interconnect network, configuration hardware) and simulated in STM 0.18 μm CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools

  4. Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

    Energy Technology Data Exchange (ETDEWEB)

    Pappas, I [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Kalenteridis, V [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Vassiliadis, N [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Pournara, H [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Siozios, K [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Koutroumpezis, G [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Tatas, K [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Nikolaidis, S [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Siskos, S [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Soudris, D J [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Thanailakis, A [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece)

    2005-01-01

    A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. A novel energy-efficient FPGA architecture is presented (CLB, interconnect network, configuration hardware) and simulated in STM 0.18 {mu}m CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools.

  5. Development of γ dose rate monitor based on FPGA and single-chip microcomputer

    International Nuclear Information System (INIS)

    He Zhiguo; Ling Qiu; Guo Lanying; Yang Binhua

    2009-01-01

    A novelγdose rate monitor with multiple channels signal collection in which takes the FPGA as the core process chip and single-chip microcomputer as the data processor had been developed. This paper introduced the communication interface design between FPGA and MCU, and gave the data acquisition module and the function simulation chart designed by FPGA. In addition, the software and hardware design diagrams of MCU had been given in this paper. The maximum digitallization was carried on in the designing process. The experiments showed that the scheme for the system matched to the requests completely. (authors)

  6. High Performance and Energy Efficient Traffic Light Controller Design Using FPGA

    DEFF Research Database (Denmark)

    Pandey, Sujeet; Shrivastav, Vivek Kumar; Sharma, Rashmi

    2017-01-01

    and then we have analyzed power consumption for traffic light controller on different FPGA. Leakage power is in range of 97.5-99% of total power consumption by traffic light controller on Virtex-7 FPGA. Signal power, clock power and IOs power are almost negligible. Power dissipation is measured on XPOWER......In this work, Verilog is used as hardware description language for implementation of traffic light controller. It shows Red, Green and Yellow color at a predefined interval. Technology scaling is used as energy efficient technique. We have used 90nm, 65nm, 40nm and 28nm technology based FPGA...

  7. Note: Design of FPGA based system identification module with application to atomic force microscopy

    Science.gov (United States)

    Ghosal, Sayan; Pradhan, Sourav; Salapaka, Murti

    2018-05-01

    The science of system identification is widely utilized in modeling input-output relationships of diverse systems. In this article, we report field programmable gate array (FPGA) based implementation of a real-time system identification algorithm which employs forgetting factors and bias compensation techniques. The FPGA module is employed to estimate the mechanical properties of surfaces of materials at the nano-scale with an atomic force microscope (AFM). The FPGA module is user friendly which can be interfaced with commercially available AFMs. Extensive simulation and experimental results validate the design.

  8. Development of an FPGA-Based Motion Control IC for Caving Machine

    Directory of Open Access Journals (Sweden)

    Chiu-Keng Lai

    2014-03-01

    Full Text Available Since the Field Programmable Gate Arrays (FPGAs with high density are available nowadays, systems with complex functions can thus be realized by FPGA in a single chip while they are traditionally implemented by several individual chips. In this research, the control of stepping motor drives as well as motion controller is integrated and implemented on Altera Cyclone III FPGA; the resulting system is evaluated by applying it to a 3-axis caving machine which is driven by stepping motors. Finally, the experimental results of current regulation and motion control integrated in FPGA IC are shown to prove the validness.

  9. Controlador empotrado en FPGA para Sistema Inteligente de Transporte

    Directory of Open Access Journals (Sweden)

    Alejandro José Cabrera Sarmiento

    2011-11-01

    Full Text Available 1024x768 Normal 0 21 false false false ES X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Tabla normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi;} En el presente trabajo se expone la concepción, desarrollo e implementación de un controlador empotrado en un FPGA de Xilinx para ser utilizado en un Sistema Inteligente de Transporte (SIT. La estructura hardware del controlador está basada en la utilización de diversos módulos de propiedad intelectual del sistema de procesamiento MicroBlaze y el soporte de software está basado en la utilización del sistema operativo Petalinux. El controlador empotrado dispone de interfaces Ethernet, USB, UART, SPI e I2C para la comunicación con los diferentes niveles jerárquicos del SIT. Ha sido implementado sobre una placa de desarrollo basada en un FPGA Spartan3E de 1.200 k compuertas, ocupando un 59% de sus recursos configurables. El resto de los recursos disponibles en el FPGA permite, además de la posible actualización del controlador, la implementación hardware de algoritmos que requieren una alta velocidad de procesamiento.

  10. Extending the BEAGLE library to a multi-FPGA platform.

    Science.gov (United States)

    Jin, Zheming; Bakos, Jason D

    2013-01-19

    Maximum Likelihood (ML)-based phylogenetic inference using Felsenstein's pruning algorithm is a standard method for estimating the evolutionary relationships amongst a set of species based on DNA sequence data, and is used in popular applications such as RAxML, PHYLIP, GARLI, BEAST, and MrBayes. The Phylogenetic Likelihood Function (PLF) and its associated scaling and normalization steps comprise the computational kernel for these tools. These computations are data intensive but contain fine grain parallelism that can be exploited by coprocessor architectures such as FPGAs and GPUs. A general purpose API called BEAGLE has recently been developed that includes optimized implementations of Felsenstein's pruning algorithm for various data parallel architectures. In this paper, we extend the BEAGLE API to a multiple Field Programmable Gate Array (FPGA)-based platform called the Convey HC-1. The core calculation of our implementation, which includes both the phylogenetic likelihood function (PLF) and the tree likelihood calculation, has an arithmetic intensity of 130 floating-point operations per 64 bytes of I/O, or 2.03 ops/byte. Its performance can thus be calculated as a function of the host platform's peak memory bandwidth and the implementation's memory efficiency, as 2.03 × peak bandwidth × memory efficiency. Our FPGA-based platform has a peak bandwidth of 76.8 GB/s and our implementation achieves a memory efficiency of approximately 50%, which gives an average throughput of 78 Gflops. This represents a ~40X speedup when compared with BEAGLE's CPU implementation on a dual Xeon 5520 and 3X speedup versus BEAGLE's GPU implementation on a Tesla T10 GPU for very large data sizes. The power consumption is 92 W, yielding a power efficiency of 1.7 Gflops per Watt. The use of data parallel architectures to achieve high performance for likelihood-based phylogenetic inference requires high memory bandwidth and a design methodology that emphasizes high memory

  11. Crustal structure across the NE Tibetan Plateau and Ordos Block from the joint inversion of receiver functions and Rayleigh-wave dispersions

    Science.gov (United States)

    Li, Yonghua; Wang, Xingchen; Zhang, Ruiqing; Wu, Qingju; Ding, Zhifeng

    2017-05-01

    We investigated the crustal structure at 34 stations using the H-κ stacking method and jointly inverting receiver functions with Rayleigh-wave phase and group velocities. These seismic stations are distributed along a profile extending across the Songpan-Ganzi Terrane, Qinling-Qilian terranes and southwestern Ordos Basin. Our results reveal the variation in crustal thickness across this profile. We found thick crust beneath the Songpan-Ganzi Terrane (47-59 km) that decreases to 45-47 km in the west Qinling and Qilian terranes, and reaches its local minimum beneath the southwestern Ordos Block (43-51 km) at an average crustal thickness of 46.7 ± 2.5 km. A low-velocity zone in the upper crust was found beneath most of the stations in NE Tibet, which may be indicative of partial melt or a weak detachment layer. Our observations of low to moderate Vp/Vs (1.67-1.79) represent a felsic to intermediate crustal composition. The shear velocity models estimated from joint inversions also reveal substantial lateral variations in velocity beneath the profile, which is mainly reflected in the lower crustal velocities. For the Ordos Block, the average shear wave velocities below 20 km are 3.8 km/s, indicating an intermediate-to-felsic lower crust. The thick NE Tibet crust is characterized by slow shear wave velocities (3.3-3.6 km/s) below 20 km and lacks high-velocity material (Vs ≥ 4.0 km/s) in the lower crust, which may be attributed to mafic lower crustal delamination or/and the thickening of the upper and middle crust.

  12. Novel metal-organic and supramolecular 3D frameworks constructed from flexible biphenyl-2,5,3‧-tricarboxylate blocks: Synthesis, structural features and properties

    Science.gov (United States)

    You, Ao; Li, Yu; Zhang, Ze-Min; Zou, Xun-Zhong; Gu, Jin-Zhong; Kirillov, Alexander M.; Chen, Jin-Wei; Chen, Yun-Bo

    2017-10-01

    Biphenyl-2,5,3‧-tricarboxylic acid (H3L) was selected as an unexplored tricarboxylate building block and applied for the hydrothermal synthesis of three novel coordination compounds, namely a 0D tetramer [Co4(HL)2(μ3-HL)2(phen)6(H2O)2]·3H2O (1) and two 3D metal-organic frameworks (MOFs) [Cd3(μ5-L)(μ6-L)(py)(μ-H2O)2(H2O)]n·H2O (2) and [Zn3(μ4-L)2(2,2‧-bpy)(μ-4,4‧-bpy)]n·2H2O (3). These products were easily generated in aqueous medium from the corresponding metal(II) chlorides, H3L, and various N-donor ancillary ligands, selected from 1,10-phenanthroline (phen), pyridine (py), 2,2‧-bipyridine (2,2‧-bpy), and 4,4‧-bipyridine (4,4‧-bpy). Compounds 1-3 were isolated as stable crystalline solids and were fully characterized by IR and UV-vis spectroscopy, elemental, thermogravimetric (TGA), powder (PXRD) and single-crystal X-ray diffraction analyses. Compound 1 possesses a discrete tetracobalt(II) structure, which is extended into a 3D H-bonded network with the pcu topology. In contrast, MOF 2 discloses a very complex trinodal 4,5,12-connected net with an undocumented topology, while MOF 3 features the nce/I topological framework. The magnetic (for 1) and luminescence (for 2 and 3) properties were also studied and discussed. The present study thus widens a still very limited family of metal-organic and supramolecular frameworks driven by flexible biphenyl-2,5,3‧-tricarboxylate building blocks.

  13. Rod-like plasmonic nanoparticles as optical building blocks: how differences in particle shape and structural geometry influence optical signal

    Energy Technology Data Exchange (ETDEWEB)

    Stender, Anthony [Iowa State Univ., Ames, IA (United States)

    2013-01-01

    interlock with one another quite easily. The dimers that form as a result display optical behavior that differs from what has been previously reported about nanorod dimers. Simulated surface charge density patterns reveal that hybridization of LSPR modes occurs readily along the lobes of individual dumbbells in some situations. A pentamer of dumbbells also displays hybridization of modes, and “hot spots” are observed at junctions between pairings of dumbbells. In the final set of experiments, the assembly behavior of nanoparticles in solution was observed in real time. In general, large assemblies of nanoparticles display backbone-like rigidity, but an interesting variety of movements is permitted within the larger structures.

  14. Encoders for block-circulant LDPC codes

    Science.gov (United States)

    Divsalar, Dariush (Inventor); Abbasfar, Aliazam (Inventor); Jones, Christopher R. (Inventor); Dolinar, Samuel J. (Inventor); Thorpe, Jeremy C. (Inventor); Andrews, Kenneth S. (Inventor); Yao, Kung (Inventor)

    2009-01-01

    Methods and apparatus to encode message input symbols in accordance with an accumulate-repeat-accumulate code with repetition three or four are disclosed. Block circulant matrices are used. A first method and apparatus make use of the block-circulant structure of the parity check matrix. A second method and apparatus use block-circulant generator matrices.

  15. Bonding and magnetic response properties of several toroid structures. Insights of the role of Ni2S2 as a building block from relativistic density functional theory calculations.

    Science.gov (United States)

    Muñoz-Castro, Alvaro

    2011-10-06

    Relativistic density functional calculations were carried out on several nickel toroid mercaptides of the general formula [Ni(μ-SR)(2)](n), with the aim to characterize and analyze their stability and magnetic response properties, in order to gain more insights into their stabilization and size-dependent behavior. The Ni-ligand interaction has been studied by means projected density of states and energy decomposition analysis, which denotes its stabilizing character. The graphical representation of the response to an external magnetic field is applied for the very first time taking into account the spin-orbit term. This map allows one to clearly characterize the magnetic behavior inside and in the closeness of the toroid structure showing the prescence of paratropic ring currents inside the Ni(n) ring, and by contrast, diatropic currents confined in each Ni(2)S(2) motif denoting an aromatic behavior (in terms of magnetic criteria). The calculated data suggests that the Ni(2)S(2) moiety can be regarded as a stable constructing block, which can afford several toroid structures of different nuclearities in agreement with that reported in the experimental literature. In addition, the effects of the relativistic treatment over the magnetic response properties on these lighter compounds are denoted by comparing nonrelativistic, scalar relativistic, and scalar plus spin-orbit relativistic treatments, showing their acting, although nonpronunced, role.

  16. Determination of the structure of the organized phase of the block copolymer PEO-PPO-PEO in aqueous solutions under flow by small-angle neutron scattering

    International Nuclear Information System (INIS)

    Perreur, Christelle; Habas, Jean-Pierre; Francois, Jeanne; Peyrelasse, Jean; Lapp, Alain

    2002-01-01

    The organization of Tetronic 908 registered (T908), a star copolymer of poly(ethylene oxide) (PEO) and poly(propylene oxide) (PPO) blocks, has been examined. Above critical conditions of temperature and concentration, the micelles formed by the aggregation of PPO units self-organize into particular structures. While small-angle neutron scattering (SANS) characterizations performed with static conditions demonstrate the organization of the medium, the experimental results do not allow us to make a distinction between simple cubic and body-centered-cubic structures. However, SANS measurements realized under shear produce characteristic diffraction diagrams. In this paper, an accurate methodology is proposed to identify, without ambiguity, the exact nature of the organized phase. Applied to our system, indexing of the diffraction pattern spots reveals that the organization of T908 is of bcc type oriented with the [111] direction parallel to the direction of flow, but the crystals can present any orientation about this direction. The lattice size has been estimated and compared to previous published results

  17. Time-delayed chameleon: Analysis, synchronization and FPGA implementation

    Science.gov (United States)

    Rajagopal, Karthikeyan; Jafari, Sajad; Laarem, Guessas

    2017-12-01

    In this paper we report a time-delayed chameleon-like chaotic system which can belong to different families of chaotic attractors depending on the choices of parameters. Such a characteristic of self-excited and hidden chaotic flows in a simple 3D system with time delay has not been reported earlier. Dynamic analysis of the proposed time-delayed systems are analysed in time-delay space and parameter space. A novel adaptive modified functional projective lag synchronization algorithm is derived for synchronizing identical time-delayed chameleon systems with uncertain parameters. The proposed time-delayed systems and the synchronization algorithm with controllers and parameter estimates are then implemented in FPGA using hardware-software co-simulation and the results are presented.

  18. improvement of digital image watermarking techniques based on FPGA implementation

    International Nuclear Information System (INIS)

    EL-Hadedy, M.E

    2006-01-01

    digital watermarking provides the ownership of a piece of digital data by marking the considered data invisibly or visibly. this can be used to protect several types of multimedia objects such as audio, text, image and video. this thesis demonstrates the different types of watermarking techniques such as (discrete cosine transform (DCT) and discrete wavelet transform (DWT) and their characteristics. then, it classifies these techniques declaring their advantages and disadvantages. an improved technique with distinguished features, such as peak signal to noise ratio ( PSNR) and similarity ratio (SR) has been introduced. the modified technique has been compared with the other techniques by measuring heir robustness against differ attacks. finally, field programmable gate arrays (FPGA) based implementation and comparison, for the proposed watermarking technique have been presented and discussed

  19. Real-time particle image velocimetry based on FPGA technology

    International Nuclear Information System (INIS)

    Iriarte Munoz, Jose Miguel

    2008-01-01

    Particle image velocimetry (PIV), based on laser sheet, is a method for image processing and calculation of distributed velocity fields.It is well established as a fluid dynamics measurement tool, being applied to liquid, gases and multiphase flows.Images of particles are processed by means of computationally demanding algorithms, what makes its real-time implementation difficult.The most probable displacements are found applying two dimensional cross-correlation function. In this work, we detail how it is possible to achieve real-time visualization of PIV method by designing an adaptive embedded architecture based on FPGA technology.We show first results of a physical field of velocity calculated by this platform system in a real-time approach. [es

  20. An FPGA-based rapid prototyping platform for wavelet coprocessors

    Science.gov (United States)

    Vera, Alonzo; Meyer-Baese, Uwe; Pattichis, Marios

    2007-04-01

    MatLab/Simulink-based design flows are being used by DSP designers to improve time-to-market of FPGA implementations. 1 Commonly, digital signal processing cores are integrated in an embedded system as coprocessors. Existing CAD tools do not fully address the integration of a DSP coprocessor into an embedded system design. This integration might prove to be time consuming and error prone. It also requires that the DSP designer has an excellent knowledge of embedded systems and computer architecture details. We present a prototyping platform and design flow that allows rapid integration of embedded systems with a wavelet coprocessor. The platform comprises of software and hardware modules that allow a DSP designer a painless integration of a coprocessor with a PowerPC-based embedded system. The platform has a wide range of applications, from industrial to educational environments.

  1. FPGA implementation of predictive degradation model for engine oil lifetime

    Science.gov (United States)

    Idros, M. F. M.; Razak, A. H. A.; Junid, S. A. M. Al; Suliman, S. I.; Halim, A. K.

    2018-03-01

    This paper presents the implementation of linear regression model for degradation prediction on Register Transfer Logic (RTL) using QuartusII. A stationary model had been identified in the degradation trend for the engine oil in a vehicle in time series method. As for RTL implementation, the degradation model is written in Verilog HDL and the data input are taken at a certain time. Clock divider had been designed to support the timing sequence of input data. At every five data, a regression analysis is adapted for slope variation determination and prediction calculation. Here, only the negative value are taken as the consideration for the prediction purposes for less number of logic gate. Least Square Method is adapted to get the best linear model based on the mean values of time series data. The coded algorithm has been implemented on FPGA for validation purposes. The result shows the prediction time to change the engine oil.

  2. FPGA implementation of advanced FEC schemes for intelligent aggregation networks

    Science.gov (United States)

    Zou, Ding; Djordjevic, Ivan B.

    2016-02-01

    In state-of-the-art fiber-optics communication systems the fixed forward error correction (FEC) and constellation size are employed. While it is important to closely approach the Shannon limit by using turbo product codes (TPC) and low-density parity-check (LDPC) codes with soft-decision decoding (SDD) algorithm; rate-adaptive techniques, which enable increased information rates over short links and reliable transmission over long links, are likely to become more important with ever-increasing network traffic demands. In this invited paper, we describe a rate adaptive non-binary LDPC coding technique, and demonstrate its flexibility and good performance exhibiting no error floor at BER down to 10-15 in entire code rate range, by FPGA-based emulation, making it a viable solution in the next-generation high-speed intelligent aggregation networks.

  3. A minimal SATA III Host Controller based on FPGA

    Science.gov (United States)

    Liu, Hailiang

    2018-03-01

    SATA (Serial Advanced Technology Attachment) is an advanced serial bus which has a outstanding performance in transmitting high speed real-time data applied in Personal Computers, Financial Industry, astronautics and aeronautics, etc. In this express, a minimal SATA III Host Controller based on Xilinx Kintex 7 serial FPGA is designed and implemented. Compared to the state-of-art, registers utilization are reduced 25.3% and LUTs utilization are reduced 65.9%. According to the experimental results, the controller works precisely and steady with the reading bandwidth of up to 536 MB per second and the writing bandwidth of up to 512 MB per second, both of which are close to the maximum bandwidth of the SSD(Solid State Disk) device. The host controller is very suitable for high speed data transmission and mass data storage.

  4. Implementace OFDM demodulátoru v obvodu FPGA

    OpenAIRE

    Solar, Pavel

    2010-01-01

    Diplomová práce stručně rozebírá princip OFDM modulace, možnosti synchronizace a odhadu frekvenční charakteristiky kanálu v OFDM. Je vytvořen jednoduchý model OFDM systému v programu MATLAB. Kombinací schématického popisu a popisu v jazyce VHDL je vytvořen ve vývojovém prostředí ISE behaviorální popis OFDM demodulátoru pro implementaci do FPGA. The master's thesis briefly analyses the principle of OFDM modulation, possibilities of the synchronization and channel estimation in OFDM. The sim...

  5. FPGA Implementation of Real-Time Ethernet for Motion Control

    Directory of Open Access Journals (Sweden)

    Chen Youdong

    2013-01-01

    Full Text Available This paper provides an applicable implementation of real-time Ethernet named CASNET, which modifies the Ethernet medium access control (MAC to achieve the real-time requirement for motion control. CASNET is the communication protocol used for motion control system. Verilog hardware description language (VHDL has been used in the MAC logic design. The designed MAC serves as one of the intellectual properties (IPs and is applicable to various industrial controllers. The interface of the physical layer is RJ45. The other layers have been implemented by using C programs. The real-time Ethernet has been implemented by using field programmable gate array (FPGA technology and the proposed solution has been tested through the cycle time, synchronization accuracy, and Wireshark testing.

  6. FPGA based compute nodes for high level triggering in PANDA

    International Nuclear Information System (INIS)

    Kuehn, W; Gilardi, C; Kirschner, D; Lang, J; Lange, S; Liu, M; Perez, T; Yang, S; Schmitt, L; Jin, D; Li, L; Liu, Z; Lu, Y; Wang, Q; Wei, S; Xu, H; Zhao, D; Korcyl, K; Otwinowski, J T; Salabura, P

    2008-01-01

    PANDA is a new universal detector for antiproton physics at the HESR facility at FAIR/GSI. The PANDA data acquisition system has to handle interaction rates of the order of 10 7 /s and data rates of several 100 Gb/s. FPGA based compute nodes with multi-Gb/s bandwidth capability using the ATCA architecture are designed to handle tasks such as event building, feature extraction and high level trigger processing. Data connectivity is provided via optical links as well as multiple Gb Ethernet ports. The boards will support trigger algorithms such us pattern recognition for RICH detectors, EM shower analysis, fast tracking algorithms and global event characterization. Besides VHDL, high level C-like hardware description languages will be considered to implement the firmware

  7. A FPGA Implementation of the CAR-FAC Cochlear Model

    Directory of Open Access Journals (Sweden)

    Ying Xu

    2018-04-01

    Full Text Available This paper presents a digital implementation of the Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC cochlear model. The CAR part simulates the basilar membrane's (BM response to sound. The FAC part models the outer hair cell (OHC, the inner hair cell (IHC, and the medial olivocochlear efferent system functions. The FAC feeds back to the CAR by moving the poles and zeros of the CAR resonators automatically. We have implemented a 70-section, 44.1 kHz sampling rate CAR-FAC system on an Altera Cyclone V Field Programmable Gate Array (FPGA with 18% ALM utilization by using time-multiplexing and pipeline parallelizing techniques and present measurement results here. The fully digital reconfigurable CAR-FAC system is stable, scalable, easy to use, and provides an excellent input stage to more complex machine hearing tasks such as sound localization, sound segregation, speech recognition, and so on.

  8. A FPGA Implementation of the CAR-FAC Cochlear Model.

    Science.gov (United States)

    Xu, Ying; Thakur, Chetan S; Singh, Ram K; Hamilton, Tara Julia; Wang, Runchun M; van Schaik, André

    2018-01-01

    This paper presents a digital implementation of the Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC) cochlear model. The CAR part simulates the basilar membrane's (BM) response to sound. The FAC part models the outer hair cell (OHC), the inner hair cell (IHC), and the medial olivocochlear efferent system functions. The FAC feeds back to the CAR by moving the poles and zeros of the CAR resonators automatically. We have implemented a 70-section, 44.1 kHz sampling rate CAR-FAC system on an Altera Cyclone V Field Programmable Gate Array (FPGA) with 18% ALM utilization by using time-multiplexing and pipeline parallelizing techniques and present measurement results here. The fully digital reconfigurable CAR-FAC system is stable, scalable, easy to use, and provides an excellent input stage to more complex machine hearing tasks such as sound localization, sound segregation, speech recognition, and so on.

  9. Hardware Implementation Of Line Clipping A lgorithm By Using FPGA

    Directory of Open Access Journals (Sweden)

    Amar Dawod

    2013-04-01

    Full Text Available The computer graphics system performance is increasing faster than any other computing application. Algorithms for line clipping against convex polygons and lines have been studied for a long time and many research papers have been published so far. In spite of the latest graphical hardware development and significant increase of performance the clipping is still a bottleneck of any graphical system. So its implementation in hardware is essential for real time applications. In this paper clipping operation is discussed and a hardware implementation of the line clipping algorithm is presented and finally formulated and tested using Field Programmable Gate Arrays (FPGA. The designed hardware unit consists of two parts : the first is positional code generator unit and the second is the clipping unit. Finally it is worth mentioning that the  designed unit is capable of clipping (232524 line segments per second.       

  10. Exploring Manycore Multinode Systems for Irregular Applications with FPGA Prototyping

    Energy Technology Data Exchange (ETDEWEB)

    Ceriani, Marco; Palermo, Gianluca; Secchi, Simone; Tumeo, Antonino; Villa, Oreste

    2013-04-29

    We present a prototype of a multi-core architecture implemented on FPGA, designed to enable efficient execution of irregular applications on distributed shared memory machines, while maintaining high performance on regular workloads. The architecture is composed of off-the-shelf soft-core cores, local interconnection and memory interface, integrated with custom components that optimize it for irregular applications. It relies on three key elements: a global address space, multithreading, and fine-grained synchronization. Global addresses are scrambled to reduce the formation of network hot-spots, while the latency of the transactions is covered by integrating an hardware scheduler within the custom load/store buffers to take advantage from the availability of multiple executions threads, increasing the efficiency in a transparent way to the application. We evaluated a dual node system irregular kernels showing scalability in the number of cores and threads.

  11. FPGA-based prototype of portable environmental radiation monitor

    Energy Technology Data Exchange (ETDEWEB)

    Benahmed, A.; Elkarch, H. [CNESTEN -Centre National de l' Energie des Sciences et Techniques Nucleaires (Morocco)

    2015-07-01

    This new portable radiological environmental monitor consists of 2 main components, Gamma ionization chamber and a FPGA-based electronic enclosure linked to convivial software for treatment and analyzing. The HPIC ion chamber is the heart of this radiation measurement system and is running in range from 0 to 100 mR/h, so that the sensitivity at the output is 20 mV/μR/h, with a nearly flat energy response from 0,07 to 10 MEV. This paper presents a contribution for developing a new nuclear measurement data acquisition system based on Cyclone III FPGA Starter Kit ALTERA, and a user-friendly software to run real-time control and data processing. It was developed to substitute the older radiation monitor RSS-112 PIC installed in CNESTEN's Laboratory in order to improve some of its functionalities related to acquisition time and data memory capacity. As for the associated acquisition software, it was conceived under the virtual LabView platform from National Instrument, and offers a variety of system setup for radiation environmental monitoring. It gives choice to display both the statistical data and the dose rate. Statistical data shows a summary of current data, current time/date and dose integrator values, and the dose rate displays the current dose rate in large numbers for viewing from a distance as well as the date and time. The prototype version of this new instrument and its data processing software has been successfully tested and validated for viewing and monitoring the environmental radiation of Moroccan nuclear center. (authors)

  12. FPGA-based RF spectrum merging and adaptive hopset selection

    Science.gov (United States)

    McLean, R. K.; Flatley, B. N.; Silvius, M. D.; Hopkinson, K. M.

    The radio frequency (RF) spectrum is a limited resource. Spectrum allotment disputes stem from this scarcity as many radio devices are confined to a fixed frequency or frequency sequence. One alternative is to incorporate cognition within a reconfigurable radio platform, therefore enabling the radio to adapt to dynamic RF spectrum environments. In this way, the radio is able to actively sense the RF spectrum, decide, and act accordingly, thereby sharing the spectrum and operating in more flexible manner. In this paper, we present a novel solution for merging many distributed RF spectrum maps into one map and for subsequently creating an adaptive hopset. We also provide an example of our system in operation, the result of which is a pseudorandom adaptive hopset. The paper then presents a novel hardware design for the frequency merger and adaptive hopset selector, both of which are written in VHDL and implemented as a custom IP core on an FPGA-based embedded system using the Xilinx Embedded Development Kit (EDK) software tool. The design of the custom IP core is optimized for area, and it can process a high-volume digital input via a low-latency circuit architecture. The complete embedded system includes the Xilinx PowerPC microprocessor, UART serial connection, and compact flash memory card IP cores, and our custom map merging/hopset selection IP core, all of which are targeted to the Virtex IV FPGA. This system is then incorporated into a cognitive radio prototype on a Rice University Wireless Open Access Research Platform (WARP) reconfigurable radio.

  13. Innovative approach to implementation of FPGA-based NPP instrumentation and control systems

    International Nuclear Information System (INIS)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; Siora, Alexander

    2011-01-01

    Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper. (author)

  14. Innovative Approach to Implementation of FPGA-based NPP Instrumentation and Control Systems

    International Nuclear Information System (INIS)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; SIORA Alexander

    2011-01-01

    Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper

  15. Innovative Approach to Implementation of FPGA-based NPP Instrumentation and Control Systems

    Energy Technology Data Exchange (ETDEWEB)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir [Centre for Safety Infrastructure-Oriented Research and Analysis, Kharkov (Ukraine); SIORA Alexander [Research and Production Corporation Radiy, Kirovograd (Ukraine)

    2011-08-15

    Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper.

  16. A natural-color mapping for single-band night-time image based on FPGA

    Science.gov (United States)

    Wang, Yilun; Qian, Yunsheng

    2018-01-01

    A natural-color mapping for single-band night-time image method based on FPGA can transmit the color of the reference image to single-band night-time image, which is consistent with human visual habits and can help observers identify the target. This paper introduces the processing of the natural-color mapping algorithm based on FPGA. Firstly, the image can be transformed based on histogram equalization, and the intensity features and standard deviation features of reference image are stored in SRAM. Then, the real-time digital images' intensity features and standard deviation features are calculated by FPGA. At last, FPGA completes the color mapping through matching pixels between images using the features in luminance channel.

  17. Implementing EW Receivers Based on Large Point Reconfigured FFT on FPGA Platforms

    Directory of Open Access Journals (Sweden)

    He Chen

    2011-12-01

    Full Text Available This paper presents design and implementation of digital receiver based on large point fast Fourier transform (FFT suitable for electronic warfare (EW applications. When implementing the FFT algorithm on field-programmable gate array (FPGA platforms, the primary goal is to maximize throughput and minimize area. This algorithm adopts two-dimension, parallel and pipeline stream mode and implements the reconfiguration of FFT's points. Moreover, a double-sequence-separation FFT algorithm has been implemented in order to achieve faster real time processing in broadband digital receivers. The performance of the hardware implementation on the FPGA platforms of broadband digital receivers has been analyzed in depth. It reaches the requirement of high-speed digital signal processing, and reveals the designing this kind of digital signal processing systems on FPGA platforms. Keywords: digital receivers, field programmable gate array (FPGA, fast Fourier transform (FFT, large point reconfigured, signal processing system.

  18. A FPGA Approach in a Motorised Linear Stage Remote Controlled Experiment

    Directory of Open Access Journals (Sweden)

    Stamen Gadzhanov

    2013-04-01

    Full Text Available In recent years, an advanced motion control software for rapid development has been introduced by National Instruments, accompanied by innovative and improved FPGA-based hardware platforms. Compared to the well-known standard NI DAQ PCI/USB board solutions, this new approach offers robust stability in a deterministic real-time environment combined with the highest possible performance and re-configurability of the FPGA core. The NI Compact RIO (cRIO Real Time Controller utilises two distinctive interface modes of functionality: Scan and FPGA modes. This paper presents an application of a motion control flexible workbench based on the FPGA module, and analyses the advantages and disadvantages in comparison to another approach - the LabVIEW NI SoftMotion module run in scan interface mode. The workbench replicates real industrial applications and is very useful for experimentation with Brushless DC/ Permanent Magnet Synchronous motors and drives, and feedback devices.

  19. Timing measurements of some tracking algorithms and suitability of FPGA's to improve the execution speed

    CERN Document Server

    Khomich, A; Kugel, A; Männer, R; Müller, M; Baines, J T M

    2003-01-01

    Some of track reconstruction algorithms which are common to all B-physics channels and standard RoI processing have been tested for execution time and assessed for suitability for speed-up by using FPGA coprocessor. The studies presented in this note were performed in the C/C++ framework, CTrig, which was the fullest set of algorithms available at the time of study For investigation of possible speed-up of algorithms most time consuming parts of TRT-LUT was implemented in VHDL for running in FPGA coprocessor board MPRACE. MPRACE (Reconfigurable Accelerator / Computing Engine) is an FPGA-Coprocessor based on Xilinx Virtex-2 FPGA and made as 64Bit/66MHz PCI card developed at the University of Mannheim. Timing measurements results for a TRT Full Scan algorithm executed on the MPRACE are presented here as well. The measurement results show a speed-up factor of ~2 for this algorithm.

  20. Dynamic Reconfiguration Of FPGA Nodes In A Distributed Computing System: A Preliminary Investigation

    National Research Council Canada - National Science Library

    Nixon, Patrick

    2002-01-01

    This report results from a contract tasking Trinity College, Dublin to investigate a specialized portion of a heterogeneous information system, specifically, Field Programmable Gate Array (FPGA)-based nodes...

  1. Advanced Image Processing Package for FPGA-Based Re-Programmable Miniature Electronics

    National Research Council Canada - National Science Library

    Ovod, Vladimir I; Baxter, Christopher R; Massie, Mark A; McCarley, Paul L

    2005-01-01

    .... An advanced image-processing package has been designed at Nova Sensors to re-configure the FPGA-based co-processor board for numerous applications including motion detection, optical background...

  2. Rad-Hard and ULP FPGA with "Full" Functionality, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — RNET has demonstrated the feasibility of developing an innovative radiation hardened (RH) and ultra low power (ULP) field programmable gate array (FPGA), called the...

  3. A FPGA-based architecture for real-time image matching

    Science.gov (United States)

    Wang, Jianhui; Zhong, Sheng; Xu, Wenhui; Zhang, Weijun; Cao, Zhiguo

    2013-10-01

    Image matching is a fundamental task in computer vision. It is used to establish correspondence between two images taken at different viewpoint or different time from the same scene. However, its large computational complexity has been a challenge to most embedded systems. This paper proposes a single FPGA-based image matching system, which consists of SIFT feature detection, BRIEF descriptor extraction and BRIEF matching. It optimizes the FPGA architecture for the SIFT feature detection to reduce the FPGA resources utilization. Moreover, we implement BRIEF description and matching on FPGA also. The proposed system can implement image matching at 30fps (frame per second) for 1280x720 images. Its processing speed can meet the demand of most real-life computer vision applications.

  4. FPGA-based High-Performance Collision Detection: An Enabling Technique for Image-Guided Robotic Surgery

    Directory of Open Access Journals (Sweden)

    Zhaorui Zhang

    2016-08-01

    Full Text Available Collision detection, which refers to the computational problem of finding the relative placement or con-figuration of two or more objects, is an essential component of many applications in computer graphics and robotics. In image-guided robotic surgery, real-time collision detection is critical for preserving healthy anatomical structures during the surgical procedure. However, the computational complexity of the problem usually results in algorithms that operate at low speed. In this paper, we present a fast and accurate algorithm for collision detection between Oriented-Bounding-Boxes (OBBs that is suitable for real-time implementation. Our proposed Sweep and Prune algorithm can perform a preliminary filtering to reduce the number of objects that need to be tested by the classical Separating Axis Test algorithm, while the OBB pairs of interest are preserved. These OBB pairs are re-checked by the Separating Axis Test algorithm to obtain accurate overlapping status between them. To accelerate the execution, our Sweep and Prune algorithm is tailor-made for the proposed method. Meanwhile, a high performance scalable hardware architecture is proposed by analyzing the intrinsic parallelism of our algorithm, and is implemented on FPGA platform. Results show that our hardware design on the FPGA platform can achieve around 8X higher running speed than the software design on a CPU platform. As a result, the proposed algorithm can achieve a collision frame rate of 1 KHz, and fulfill the requirement for the medical surgery scenario of Robot Assisted Laparoscopy.

  5. Development of 8K-MCA Add-on based on FPGA technique with a control of VB6 software application under windows environment

    International Nuclear Information System (INIS)

    Dang Lanh; Nguyen Nhi Dien; Nguyen Xuan Hai; Nguyen Bach Viet; Pham Ngoc Son; Huynh Minh; Vuong Huu Tan; Pham Dinh Khang; Phan Nam Anh

    2003-01-01

    The multichannel analyzer is the heart of most experimental measurements. Today, it becomes popular and convenient. It can play a role of getting, processing data and easily interfacing to PC. Some standard-alone multichannel analysis systems can be replaced by Add-on MCA card. Especially, MCA card is necessary for application in nuclear physics research. The main aim of this sub-project is to focus on a design and construction of an 8K-MCA Add-on served for studying nuclear structure, for development of Gamma spectroscopy system, and for a production of low-cost electronics instruments as well. Some experimental results were obtained through the aforementioned card combining with other needed functional analog units. A multichannel data processing (MCD) circuit for nuclear spectroscopy application was developed using a field programmable gate arrays (FPGA) as the central processing element. In addition to the first role, A 13-bit analog-to-digital converter (8k ADC) circuit for nuclear spectroscopy application was also developed using a successive approximation ADC with a control of FPGA technology. The FPGA operates a program that builds the distributed functions of data collected by the ADC and then corrects the ADC differential non-linearity (DNL) via the sliding scale method. The acquisition routine runs in 3.7μ s. the conversion time is approximated 2.2μ s, and the integral non-linearity ≤ 0.14%. (author)

  6. Fuzzy Controller Design Using FPGA for Photovoltaic Maximum Power Point Tracking

    OpenAIRE

    Basil M Hamed; Mohammed S. El-Moghany

    2012-01-01

    The cell has optimum operating point to be able to get maximum power. To obtain Maximum Power from photovoltaic array, photovoltaic power system usually requires Maximum Power Point Tracking (MPPT) controller. This paper provides a small power photovoltaic control system based on fuzzy control with FPGA technology design and implementation for MPPT. The system composed of photovoltaic module, buck converter and the fuzzy logic controller implemented on FPGA for controlling on/off time of MOSF...

  7. Direct Measurement of Power Dissipated by Monte Carlo Simulations on CPU and FPGA Platforms

    OpenAIRE

    Albicocco, Pietro; Papini, Davide; Nannarelli, Alberto

    2012-01-01

    In this technical report, we describe how power dissipation measurements on different computing platforms (a desktop computer and an FPGA board) are performed by using a Hall effectbased current sensor. The chosen application is a Monte Carlo simulation for European option pricing which is a popular algorithm used in financial computations. The Hall effect probe measurements complement the measurements performed on the core of the FPGA by a built-in Xilinxpower monitoring system.

  8. Scaling of Supply Voltage in Design of Energy Saver FIR Filter on 28nm FPGA

    DEFF Research Database (Denmark)

    Pandey, Bishwajeet; Jain, Vishal; Sharma, Rashmi

    2017-01-01

    In this work, we are going to analyze the effect of main supply voltage, auxiliary supply voltage, local voltage of different power bank, and supply voltage in GTX transceiver and BRAM on power dissipation of our FIR design using Verilog during implementation on 28nm FPGA. We have also taken three.......33%, 86%, 90.67%, 65.33%, 52%, and 48.67% reduction in IO power dissipation of FIR Filter design on CSG324 package of Artix-7 FPGA family....

  9. Time and Power Optimizations in FPGA-Based Architectures for Polyphase Channelizers

    DEFF Research Database (Denmark)

    Awan, Mehmood-Ur-Rehman; Harris, Fred; Koch, Peter

    2012-01-01

    This paper presents the time and power optimization considerations for Field Programmable Gate Array (FPGA) based architectures for a polyphase filter bank channelizer with an embedded square root shaping filter in its polyphase engine. This configuration performs two different re-sampling tasks......% slice register resources of a Xilinx Virtex-5 FPGA, operating at 400 and 480 MHz, and consuming 1.9 and 2.6 Watts of dynamic power, respectively....

  10. Investigation of Electromagnetic Signatures of a FPGA Using an APREL EM-ISIGHT System

    Science.gov (United States)

    2015-12-01

    shelf (COTS) field- programmable gate array (FPGA) at the optimized factor levels established from the DOE and varying the programmed signal. This...signature using APREL’s EM-ISight automated system is hypothesized to be a novel way to accomplish this task. Research Questions The research...a field programmable gate array (FPGA) is the circuit board utilized for testing the inherent electromagnetic signature. Every device produces an

  11. A Design Methodology for Efficient Implementation of Deconvolutional Neural Networks on an FPGA

    OpenAIRE

    Zhang, Xinyu; Das, Srinjoy; Neopane, Ojash; Kreutz-Delgado, Ken

    2017-01-01

    In recent years deep learning algorithms have shown extremely high performance on machine learning tasks such as image classification and speech recognition. In support of such applications, various FPGA accelerator architectures have been proposed for convolutional neural networks (CNNs) that enable high performance for classification tasks at lower power than CPU and GPU processors. However, to date, there has been little research on the use of FPGA implementations of deconvolutional neural...

  12. FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

    Directory of Open Access Journals (Sweden)

    Swapnil Mhaske

    2017-01-01

    Full Text Available We propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding schedule without utilizing additional hardware resources. High-level synthesis compilation is used to design and develop the architecture on the FPGA hardware platform. To validate this architecture, an IEEE 802.11n compliant 608 Mb/s decoder is implemented on the Xilinx Kintex-7 FPGA using the LabVIEW FPGA Compiler in the LabVIEW Communication System Design Suite. Architecture scalability was leveraged to accomplish a 2.48 Gb/s decoder on a single Xilinx Kintex-7 FPGA. Further, we present rapidly prototyped experimentation of an IEEE 802.16 compliant hybrid automatic repeat request system based on the efficient decoder architecture developed. In spite of the mixed nature of data processing—digital signal processing and finite-state machines—LabVIEW FPGA Compiler significantly reduced time to explore the system parameter space and to optimize in terms of error performance and resource utilization. A 4x improvement in the system throughput, relative to a CPU-based implementation, was achieved to measure the error-rate performance of the system over large, realistic data sets using accelerated, in-hardware simulation.

  13. FPGA hardware acceleration for high performance neutron transport computation based on agent methodology - 318

    International Nuclear Information System (INIS)

    Shanjie, Xiao; Tatjana, Jevremovic

    2010-01-01

    The accurate, detailed and 3D neutron transport analysis for Gen-IV reactors is still time-consuming regardless of advanced computational hardware available in developed countries. This paper introduces a new concept in addressing the computational time while persevering the detailed and accurate modeling; a specifically designed FPGA co-processor accelerates robust AGENT methodology for complex reactor geometries. For the first time this approach is applied to accelerate the neutronics analysis. The AGENT methodology solves neutron transport equation using the method of characteristics. The AGENT methodology performance was carefully analyzed before the hardware design based on the FPGA co-processor was adopted. The most time-consuming kernel part is then transplanted into the FPGA co-processor. The FPGA co-processor is designed with data flow-driven non von-Neumann architecture and has much higher efficiency than the conventional computer architecture. Details of the FPGA co-processor design are introduced and the design is benchmarked using two different examples. The advanced chip architecture helps the FPGA co-processor obtaining more than 20 times speed up with its working frequency much lower than the CPU frequency. (authors)

  14. A digital frequency stabilization system of external cavity diode laser based on LabVIEW FPGA

    Science.gov (United States)

    Liu, Zhuohuan; Hu, Zhaohui; Qi, Lu; Wang, Tao

    2015-10-01

    Frequency stabilization for external cavity diode laser has played an important role in physics research. Many laser frequency locking solutions have been proposed by researchers. Traditionally, the locking process was accomplished by analog system, which has fast feedback control response speed. However, analog system is susceptible to the effects of environment. In order to improve the automation level and reliability of the frequency stabilization system, we take a grating-feedback external cavity diode laser as the laser source and set up a digital frequency stabilization system based on National Instrument's FPGA (NI FPGA). The system consists of a saturated absorption frequency stabilization of beam path, a differential photoelectric detector, a NI FPGA board and a host computer. Many functions, such as piezoelectric transducer (PZT) sweeping, atomic saturation absorption signal acquisition, signal peak identification, error signal obtaining and laser PZT voltage feedback controlling, are totally completed by LabVIEW FPGA program. Compared with the analog system, the system built by the logic gate circuits, performs stable and reliable. User interface programmed by LabVIEW is friendly. Besides, benefited from the characteristics of reconfiguration, the LabVIEW program is good at transplanting in other NI FPGA boards. Most of all, the system periodically checks the error signal. Once the abnormal error signal is detected, FPGA will restart frequency stabilization process without manual control. Through detecting the fluctuation of error signal of the atomic saturation absorption spectrum line in the frequency locking state, we can infer that the laser frequency stability can reach 1MHz.

  15. Ultrasound guided supraclavicular block.

    LENUS (Irish Health Repository)

    Hanumanthaiah, Deepak

    2013-09-01

    Ultrasound guided regional anaesthesia is becoming increasingly popular. The supraclavicular block has been transformed by ultrasound guidance into a potentially safe superficial block. We reviewed the techniques of performing supraclavicular block with special focus on ultrasound guidance.

  16. Relativistic and Non-Relativistic Electronic Molecular-Structure Calculations for Dimers of 4p-, 5p-, and 6p-Block Elements

    DEFF Research Database (Denmark)

    Hofener, S.; Ahlrichs, R.; Knecht, S.

    2012-01-01

    We report results of non-relativistic and two-component relativistic single-reference coupled-cluster with single and double and perturbative triple excitations [CCSD(T)] treatments for the 4p-block dimers Ga2 to Br2, the 5p-block dimers In2 to I2, and their atoms. Extended basis sets up...

  17. Mechanical properties and electronic structure of anti-ReO3 structured cubic nitrides, M3N, of d block transition metals M: An ab initio study

    International Nuclear Information System (INIS)

    Zhou, Xiuquan; Gall, Daniel; Khare, Sanjay V.

    2014-01-01

    Highlights: • We use DFT to model the anti-ReO 3 structured transition metal nitrides M 3 N. • We predict their lattice constants, electronic structures and mechanical properties. • We correlate the metal d and nitrogen 2p orbitals with stability and hardness. • We established a high-throughput database for materials design. - Abstract: We report a systematic study of the anti-ReO 3 structured transition metal nitrides, M 3 N, using ab initio density functional theory computations in the local density approximation. Here M denotes all the 3d, 4d and 5d transition metals. Our calculations indicate that all M 3 N compounds except V 3 N of group 5 and Zn 3 N and Hg 3 N of group 12 are mechanically stable. For the stable M 3 N compounds, we report a database of predictions for their lattice constants, electronic properties and mechanical properties including bulk modulus, Young’s modulus, shear modulus, ductility, hardness and Debye temperature. It is found that most M 3 N compounds exhibit ductility with Vickers hardness between 0.4 GPa and 11.2 GPa. Our computed lattice constant for Cu 3 N, the only M 3 N compound where experiments exist, agrees well with the experimentally reported values. We report ratios of the melting points of all M 3 N compounds to that of Cu 3 N. The local density of states for all M 3 N compounds are obtained, and electronic band gaps are observed only for M of group 11 (Cu, Ag and Au) while the remaining M 3 N compounds are metallic without band gaps. Valence electron density along with the hybridization of the metal d and nitrogen 2p orbitals play an important role in determining the stability and hardness of different compounds. Our high-throughput databases for the cubic anti-ReO 3 structured transition metal nitrides should motivate future experimental work and shorten the time to their discovery

  18. Minimum description length block finder, a method to identify haplotype blocks and to compare the strength of block boundaries.

    Science.gov (United States)

    Mannila, H; Koivisto, M; Perola, M; Varilo, T; Hennah, W; Ekelund, J; Lukk, M; Peltonen, L; Ukkonen, E

    2003-07-01

    We describe a new probabilistic method for finding haplotype blocks that is based on the use of the minimum description length (MDL) principle. We give a rigorous definition of the quality of a segmentation of a genomic region into blocks and describe a dynamic programming algorithm for finding the optimal segmentation with respect to this measure. We also describe a method for finding the probability of a block boundary for each pair of adjacent markers: this gives a tool for evaluating the significance of each block boundary. We have applied the method to the published data of Daly and colleagues. The results expose some problems that exist in the current methods for the evaluation of the significance of predicted block boundaries. Our method, MDL block finder, can be used to compare block borders in different sample sets, and we demonstrate this by applying the MDL-based method to define the block structure in chromosomes from population isolates.

  19. Empirical Mode Decomposition and Neural Networks on FPGA for Fault Diagnosis in Induction Motors

    Directory of Open Access Journals (Sweden)

    David Camarena-Martinez

    2014-01-01

    Full Text Available Nowadays, many industrial applications require online systems that combine several processing techniques in order to offer solutions to complex problems as the case of detection and classification of multiple faults in induction motors. In this work, a novel digital structure to implement the empirical mode decomposition (EMD for processing nonstationary and nonlinear signals using the full spline-cubic function is presented; besides, it is combined with an adaptive linear network (ADALINE-based frequency estimator and a feed forward neural network (FFNN-based classifier to provide an intelligent methodology for the automatic diagnosis during the startup transient of motor faults such as: one and two broken rotor bars, bearing defects, and unbalance. Moreover, the overall methodology implementation into a field-programmable gate array (FPGA allows an online and real-time operation, thanks to its parallelism and high-performance capabilities as a system-on-a-chip (SoC solution. The detection and classification results show the effectiveness of the proposed fused techniques; besides, the high precision and minimum resource usage of the developed digital structures make them a suitable and low-cost solution for this and many other industrial applications.

  20. Empirical Mode Decomposition and Neural Networks on FPGA for Fault Diagnosis in Induction Motors

    Science.gov (United States)

    Garcia-Perez, Arturo; Osornio-Rios, Roque Alfredo; Romero-Troncoso, Rene de Jesus

    2014-01-01

    Nowadays, many industrial applications require online systems that combine several processing techniques in order to offer solutions to complex problems as the case of detection and classification of multiple faults in induction motors. In this work, a novel digital structure to implement the empirical mode decomposition (EMD) for processing nonstationary and nonlinear signals using the full spline-cubic function is presented; besides, it is combined with an adaptive linear network (ADALINE)-based frequency estimator and a feed forward neural network (FFNN)-based classifier to provide an intelligent methodology for the automatic diagnosis during the startup transient of motor faults such as: one and two broken rotor bars, bearing defects, and unbalance. Moreover, the overall methodology implementation into a field-programmable gate array (FPGA) allows an online and real-time operation, thanks to its parallelism and high-performance capabilities as a system-on-a-chip (SoC) solution. The detection and classification results show the effectiveness of the proposed fused techniques; besides, the high precision and minimum resource usage of the developed digital structures make them a suitable and low-cost solution for this and many other industrial applications. PMID:24678281